2 * ACPI support for Intel Lynxpoint LPSS.
4 * Copyright (C) 2013, Intel Corporation
5 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/acpi.h>
14 #include <linux/clkdev.h>
15 #include <linux/clk-provider.h>
16 #include <linux/err.h>
18 #include <linux/mutex.h>
19 #include <linux/platform_device.h>
20 #include <linux/platform_data/clk-lpss.h>
21 #include <linux/platform_data/x86/pmc_atom.h>
22 #include <linux/pm_domain.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pwm.h>
25 #include <linux/delay.h>
29 ACPI_MODULE_NAME("acpi_lpss");
31 #ifdef CONFIG_X86_INTEL_LPSS
33 #include <asm/cpu_device_id.h>
34 #include <asm/intel-family.h>
35 #include <asm/iosf_mbi.h>
37 #define LPSS_ADDR(desc) ((unsigned long)&desc)
39 #define LPSS_CLK_SIZE 0x04
40 #define LPSS_LTR_SIZE 0x18
42 /* Offsets relative to LPSS_PRIVATE_OFFSET */
43 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
44 #define LPSS_RESETS 0x04
45 #define LPSS_RESETS_RESET_FUNC BIT(0)
46 #define LPSS_RESETS_RESET_APB BIT(1)
47 #define LPSS_GENERAL 0x08
48 #define LPSS_GENERAL_LTR_MODE_SW BIT(2)
49 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
50 #define LPSS_SW_LTR 0x10
51 #define LPSS_AUTO_LTR 0x14
52 #define LPSS_LTR_SNOOP_REQ BIT(15)
53 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF
54 #define LPSS_LTR_SNOOP_LAT_1US 0x800
55 #define LPSS_LTR_SNOOP_LAT_32US 0xC00
56 #define LPSS_LTR_SNOOP_LAT_SHIFT 5
57 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
58 #define LPSS_LTR_MAX_VAL 0x3FF
59 #define LPSS_TX_INT 0x20
60 #define LPSS_TX_INT_MASK BIT(1)
62 #define LPSS_PRV_REG_COUNT 9
65 #define LPSS_CLK BIT(0)
66 #define LPSS_CLK_GATE BIT(1)
67 #define LPSS_CLK_DIVIDER BIT(2)
68 #define LPSS_LTR BIT(3)
69 #define LPSS_SAVE_CTX BIT(4)
70 #define LPSS_NO_D3_DELAY BIT(5)
72 /* Crystal Cove PMIC shares same ACPI ID between different platforms */
76 struct lpss_private_data;
78 struct lpss_device_desc {
80 const char *clk_con_id;
81 unsigned int prv_offset;
82 size_t prv_size_override;
83 struct property_entry *properties;
84 void (*setup)(struct lpss_private_data *pdata);
87 static const struct lpss_device_desc lpss_dma_desc = {
91 struct lpss_private_data {
92 struct acpi_device *adev;
93 void __iomem *mmio_base;
94 resource_size_t mmio_size;
95 unsigned int fixed_clk_rate;
97 const struct lpss_device_desc *dev_desc;
98 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
101 /* LPSS run time quirks */
102 static unsigned int lpss_quirks;
105 * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
107 * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
108 * it can be powered off automatically whenever the last LPSS device goes down.
109 * In case of no power any access to the DMA controller will hang the system.
110 * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
111 * well as on ASuS T100TA transformer.
113 * This quirk overrides power state of entire LPSS island to keep DMA powered
114 * on whenever we have at least one other device in use.
116 #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0)
118 /* UART Component Parameter Register */
119 #define LPSS_UART_CPR 0xF4
120 #define LPSS_UART_CPR_AFCE BIT(4)
122 static void lpss_uart_setup(struct lpss_private_data *pdata)
127 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
128 val = readl(pdata->mmio_base + offset);
129 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
131 val = readl(pdata->mmio_base + LPSS_UART_CPR);
132 if (!(val & LPSS_UART_CPR_AFCE)) {
133 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
134 val = readl(pdata->mmio_base + offset);
135 val |= LPSS_GENERAL_UART_RTS_OVRD;
136 writel(val, pdata->mmio_base + offset);
140 static void lpss_deassert_reset(struct lpss_private_data *pdata)
145 offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
146 val = readl(pdata->mmio_base + offset);
147 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
148 writel(val, pdata->mmio_base + offset);
152 * BYT PWM used for backlight control by the i915 driver on systems without
153 * the Crystal Cove PMIC.
155 static struct pwm_lookup byt_pwm_lookup[] = {
156 PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
157 "pwm_backlight", 0, PWM_POLARITY_NORMAL,
158 "pwm-lpss-platform"),
161 static void byt_pwm_setup(struct lpss_private_data *pdata)
163 struct acpi_device *adev = pdata->adev;
165 /* Only call pwm_add_table for the first PWM controller */
166 if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
169 if (!acpi_dev_present("INT33FD", NULL, BYT_CRC_HRV))
170 pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
173 #define LPSS_I2C_ENABLE 0x6c
175 static void byt_i2c_setup(struct lpss_private_data *pdata)
177 lpss_deassert_reset(pdata);
179 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
180 pdata->fixed_clk_rate = 133000000;
182 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
185 /* BSW PWM used for backlight control by the i915 driver */
186 static struct pwm_lookup bsw_pwm_lookup[] = {
187 PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
188 "pwm_backlight", 0, PWM_POLARITY_NORMAL,
189 "pwm-lpss-platform"),
192 static void bsw_pwm_setup(struct lpss_private_data *pdata)
194 struct acpi_device *adev = pdata->adev;
196 /* Only call pwm_add_table for the first PWM controller */
197 if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
200 pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));
203 static const struct lpss_device_desc lpt_dev_desc = {
204 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
208 static const struct lpss_device_desc lpt_i2c_dev_desc = {
209 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR,
213 static struct property_entry uart_properties[] = {
214 PROPERTY_ENTRY_U32("reg-io-width", 4),
215 PROPERTY_ENTRY_U32("reg-shift", 2),
216 PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
220 static const struct lpss_device_desc lpt_uart_dev_desc = {
221 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
222 .clk_con_id = "baudclk",
224 .setup = lpss_uart_setup,
225 .properties = uart_properties,
228 static const struct lpss_device_desc lpt_sdio_dev_desc = {
230 .prv_offset = 0x1000,
231 .prv_size_override = 0x1018,
234 static const struct lpss_device_desc byt_pwm_dev_desc = {
235 .flags = LPSS_SAVE_CTX,
236 .setup = byt_pwm_setup,
239 static const struct lpss_device_desc bsw_pwm_dev_desc = {
240 .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
241 .setup = bsw_pwm_setup,
244 static const struct lpss_device_desc byt_uart_dev_desc = {
245 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
246 .clk_con_id = "baudclk",
248 .setup = lpss_uart_setup,
249 .properties = uart_properties,
252 static const struct lpss_device_desc bsw_uart_dev_desc = {
253 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
255 .clk_con_id = "baudclk",
257 .setup = lpss_uart_setup,
258 .properties = uart_properties,
261 static const struct lpss_device_desc byt_spi_dev_desc = {
262 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
266 static const struct lpss_device_desc byt_sdio_dev_desc = {
270 static const struct lpss_device_desc byt_i2c_dev_desc = {
271 .flags = LPSS_CLK | LPSS_SAVE_CTX,
273 .setup = byt_i2c_setup,
276 static const struct lpss_device_desc bsw_i2c_dev_desc = {
277 .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
279 .setup = byt_i2c_setup,
282 static const struct lpss_device_desc bsw_spi_dev_desc = {
283 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
286 .setup = lpss_deassert_reset,
289 #define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
291 static const struct x86_cpu_id lpss_cpu_ids[] = {
292 ICPU(INTEL_FAM6_ATOM_SILVERMONT1), /* Valleyview, Bay Trail */
293 ICPU(INTEL_FAM6_ATOM_AIRMONT), /* Braswell, Cherry Trail */
299 #define LPSS_ADDR(desc) (0UL)
301 #endif /* CONFIG_X86_INTEL_LPSS */
303 static const struct acpi_device_id acpi_lpss_device_ids[] = {
304 /* Generic LPSS devices */
305 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
307 /* Lynxpoint LPSS devices */
308 { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
309 { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
310 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
311 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
312 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
313 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
314 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
317 /* BayTrail LPSS devices */
318 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
319 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
320 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
321 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
322 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
326 /* Braswell LPSS devices */
327 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
328 { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
329 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
330 { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
332 /* Broadwell LPSS devices */
333 { "INT3430", LPSS_ADDR(lpt_dev_desc) },
334 { "INT3431", LPSS_ADDR(lpt_dev_desc) },
335 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
336 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
337 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
338 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
339 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
342 /* Wildcat Point LPSS devices */
343 { "INT3438", LPSS_ADDR(lpt_dev_desc) },
348 #ifdef CONFIG_X86_INTEL_LPSS
350 static int is_memory(struct acpi_resource *res, void *not_used)
353 return !acpi_dev_resource_memory(res, &r);
356 /* LPSS main clock device. */
357 static struct platform_device *lpss_clk_dev;
359 static inline void lpt_register_clock_device(void)
361 lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
364 static int register_device_clock(struct acpi_device *adev,
365 struct lpss_private_data *pdata)
367 const struct lpss_device_desc *dev_desc = pdata->dev_desc;
368 const char *devname = dev_name(&adev->dev);
370 struct lpss_clk_data *clk_data;
371 const char *parent, *clk_name;
372 void __iomem *prv_base;
375 lpt_register_clock_device();
377 clk_data = platform_get_drvdata(lpss_clk_dev);
382 if (!pdata->mmio_base
383 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
386 parent = clk_data->name;
387 prv_base = pdata->mmio_base + dev_desc->prv_offset;
389 if (pdata->fixed_clk_rate) {
390 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
391 pdata->fixed_clk_rate);
395 if (dev_desc->flags & LPSS_CLK_GATE) {
396 clk = clk_register_gate(NULL, devname, parent, 0,
397 prv_base, 0, 0, NULL);
401 if (dev_desc->flags & LPSS_CLK_DIVIDER) {
402 /* Prevent division by zero */
403 if (!readl(prv_base))
404 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
406 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
409 clk = clk_register_fractional_divider(NULL, clk_name, parent,
411 1, 15, 16, 15, 0, NULL);
414 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
419 clk = clk_register_gate(NULL, clk_name, parent,
420 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
421 prv_base, 31, 0, NULL);
430 clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
434 struct lpss_device_links {
435 const char *supplier_hid;
436 const char *supplier_uid;
437 const char *consumer_hid;
438 const char *consumer_uid;
443 * The _DEP method is used to identify dependencies but instead of creating
444 * device links for every handle in _DEP, only links in the following list are
445 * created. That is necessary because, in the general case, _DEP can refer to
446 * devices that might not have drivers, or that are on different buses, or where
447 * the supplier is not enumerated until after the consumer is probed.
449 static const struct lpss_device_links lpss_device_links[] = {
450 {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME},
453 static bool hid_uid_match(const char *hid1, const char *uid1,
454 const char *hid2, const char *uid2)
456 return !strcmp(hid1, hid2) && uid1 && uid2 && !strcmp(uid1, uid2);
459 static bool acpi_lpss_is_supplier(struct acpi_device *adev,
460 const struct lpss_device_links *link)
462 return hid_uid_match(acpi_device_hid(adev), acpi_device_uid(adev),
463 link->supplier_hid, link->supplier_uid);
466 static bool acpi_lpss_is_consumer(struct acpi_device *adev,
467 const struct lpss_device_links *link)
469 return hid_uid_match(acpi_device_hid(adev), acpi_device_uid(adev),
470 link->consumer_hid, link->consumer_uid);
478 static int match_hid_uid(struct device *dev, void *data)
480 struct acpi_device *adev = ACPI_COMPANION(dev);
481 struct hid_uid *id = data;
486 return hid_uid_match(acpi_device_hid(adev), acpi_device_uid(adev),
490 static struct device *acpi_lpss_find_device(const char *hid, const char *uid)
492 struct hid_uid data = {
497 return bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid);
500 static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle)
502 struct acpi_handle_list dep_devices;
506 if (!acpi_has_method(adev->handle, "_DEP"))
509 status = acpi_evaluate_reference(adev->handle, "_DEP", NULL,
511 if (ACPI_FAILURE(status)) {
512 dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n");
516 for (i = 0; i < dep_devices.count; i++) {
517 if (dep_devices.handles[i] == handle)
524 static void acpi_lpss_link_consumer(struct device *dev1,
525 const struct lpss_device_links *link)
529 dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid);
533 if (acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1)))
534 device_link_add(dev2, dev1, link->flags);
539 static void acpi_lpss_link_supplier(struct device *dev1,
540 const struct lpss_device_links *link)
544 dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid);
548 if (acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2)))
549 device_link_add(dev1, dev2, link->flags);
554 static void acpi_lpss_create_device_links(struct acpi_device *adev,
555 struct platform_device *pdev)
559 for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) {
560 const struct lpss_device_links *link = &lpss_device_links[i];
562 if (acpi_lpss_is_supplier(adev, link))
563 acpi_lpss_link_consumer(&pdev->dev, link);
565 if (acpi_lpss_is_consumer(adev, link))
566 acpi_lpss_link_supplier(&pdev->dev, link);
570 static int acpi_lpss_create_device(struct acpi_device *adev,
571 const struct acpi_device_id *id)
573 const struct lpss_device_desc *dev_desc;
574 struct lpss_private_data *pdata;
575 struct resource_entry *rentry;
576 struct list_head resource_list;
577 struct platform_device *pdev;
580 dev_desc = (const struct lpss_device_desc *)id->driver_data;
582 pdev = acpi_create_platform_device(adev, NULL);
583 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
585 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
589 INIT_LIST_HEAD(&resource_list);
590 ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
594 list_for_each_entry(rentry, &resource_list, node)
595 if (resource_type(rentry->res) == IORESOURCE_MEM) {
596 if (dev_desc->prv_size_override)
597 pdata->mmio_size = dev_desc->prv_size_override;
599 pdata->mmio_size = resource_size(rentry->res);
600 pdata->mmio_base = ioremap(rentry->res->start,
605 acpi_dev_free_resource_list(&resource_list);
607 if (!pdata->mmio_base) {
608 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */
609 adev->pnp.type.platform_id = 0;
610 /* Skip the device, but continue the namespace scan. */
616 pdata->dev_desc = dev_desc;
619 dev_desc->setup(pdata);
621 if (dev_desc->flags & LPSS_CLK) {
622 ret = register_device_clock(adev, pdata);
624 /* Skip the device, but continue the namespace scan. */
631 * This works around a known issue in ACPI tables where LPSS devices
632 * have _PS0 and _PS3 without _PSC (and no power resources), so
633 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
635 ret = acpi_device_fix_up_power(adev);
637 /* Skip the device, but continue the namespace scan. */
642 adev->driver_data = pdata;
643 pdev = acpi_create_platform_device(adev, dev_desc->properties);
644 if (!IS_ERR_OR_NULL(pdev)) {
645 acpi_lpss_create_device_links(adev, pdev);
650 adev->driver_data = NULL;
657 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
659 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
662 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
665 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
668 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
670 struct acpi_device *adev;
671 struct lpss_private_data *pdata;
675 ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
679 spin_lock_irqsave(&dev->power.lock, flags);
680 if (pm_runtime_suspended(dev)) {
684 pdata = acpi_driver_data(adev);
685 if (WARN_ON(!pdata || !pdata->mmio_base)) {
689 *val = __lpss_reg_read(pdata, reg);
692 spin_unlock_irqrestore(&dev->power.lock, flags);
696 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
703 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
704 ret = lpss_reg_read(dev, reg, <r_value);
708 return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
711 static ssize_t lpss_ltr_mode_show(struct device *dev,
712 struct device_attribute *attr, char *buf)
718 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode);
722 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
723 return sprintf(buf, "%s\n", outstr);
726 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
727 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
728 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
730 static struct attribute *lpss_attrs[] = {
731 &dev_attr_auto_ltr.attr,
732 &dev_attr_sw_ltr.attr,
733 &dev_attr_ltr_mode.attr,
737 static const struct attribute_group lpss_attr_group = {
742 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
744 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
745 u32 ltr_mode, ltr_val;
747 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
749 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
750 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
751 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
755 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
756 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
757 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
758 val = LPSS_LTR_MAX_VAL;
759 } else if (val > LPSS_LTR_MAX_VAL) {
760 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
761 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
763 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
766 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
767 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
768 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
769 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
775 * acpi_lpss_save_ctx() - Save the private registers of LPSS device
777 * @pdata: pointer to the private data of the LPSS device
779 * Most LPSS devices have private registers which may loose their context when
780 * the device is powered down. acpi_lpss_save_ctx() saves those registers into
783 static void acpi_lpss_save_ctx(struct device *dev,
784 struct lpss_private_data *pdata)
788 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
789 unsigned long offset = i * sizeof(u32);
791 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
792 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
793 pdata->prv_reg_ctx[i], offset);
798 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
800 * @pdata: pointer to the private data of the LPSS device
802 * Restores the registers that were previously stored with acpi_lpss_save_ctx().
804 static void acpi_lpss_restore_ctx(struct device *dev,
805 struct lpss_private_data *pdata)
809 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
810 unsigned long offset = i * sizeof(u32);
812 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
813 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
814 pdata->prv_reg_ctx[i], offset);
818 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
821 * The following delay is needed or the subsequent write operations may
822 * fail. The LPSS devices are actually PCI devices and the PCI spec
823 * expects 10ms delay before the device can be accessed after D3 to D0
824 * transition. However some platforms like BSW does not need this delay.
826 unsigned int delay = 10; /* default 10ms delay */
828 if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
834 static int acpi_lpss_activate(struct device *dev)
836 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
839 ret = acpi_dev_resume(dev);
843 acpi_lpss_d3_to_d0_delay(pdata);
846 * This is called only on ->probe() stage where a device is either in
847 * known state defined by BIOS or most likely powered off. Due to this
848 * we have to deassert reset line to be sure that ->probe() will
849 * recognize the device.
851 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
852 lpss_deassert_reset(pdata);
857 static void acpi_lpss_dismiss(struct device *dev)
859 acpi_dev_suspend(dev, false);
862 /* IOSF SB for LPSS island */
863 #define LPSS_IOSF_UNIT_LPIOEP 0xA0
864 #define LPSS_IOSF_UNIT_LPIO1 0xAB
865 #define LPSS_IOSF_UNIT_LPIO2 0xAC
867 #define LPSS_IOSF_PMCSR 0x84
868 #define LPSS_PMCSR_D0 0
869 #define LPSS_PMCSR_D3hot 3
870 #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0)
872 #define LPSS_IOSF_GPIODEF0 0x154
873 #define LPSS_GPIODEF0_DMA1_D3 BIT(2)
874 #define LPSS_GPIODEF0_DMA2_D3 BIT(3)
875 #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2)
876 #define LPSS_GPIODEF0_DMA_LLP BIT(13)
878 static DEFINE_MUTEX(lpss_iosf_mutex);
880 static void lpss_iosf_enter_d3_state(void)
883 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
884 u32 value2 = LPSS_PMCSR_D3hot;
885 u32 mask2 = LPSS_PMCSR_Dx_MASK;
887 * PMC provides an information about actual status of the LPSS devices.
888 * Here we read the values related to LPSS power island, i.e. LPSS
889 * devices, excluding both LPSS DMA controllers, along with SCC domain.
891 u32 func_dis, d3_sts_0, pmc_status, pmc_mask = 0xfe000ffe;
894 ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
898 mutex_lock(&lpss_iosf_mutex);
900 ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
905 * Get the status of entire LPSS power island per device basis.
906 * Shutdown both LPSS DMA controllers if and only if all other devices
907 * are already in D3hot.
909 pmc_status = (~(d3_sts_0 | func_dis)) & pmc_mask;
913 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
914 LPSS_IOSF_PMCSR, value2, mask2);
916 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
917 LPSS_IOSF_PMCSR, value2, mask2);
919 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
920 LPSS_IOSF_GPIODEF0, value1, mask1);
922 mutex_unlock(&lpss_iosf_mutex);
925 static void lpss_iosf_exit_d3_state(void)
927 u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |
928 LPSS_GPIODEF0_DMA_LLP;
929 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
930 u32 value2 = LPSS_PMCSR_D0;
931 u32 mask2 = LPSS_PMCSR_Dx_MASK;
933 mutex_lock(&lpss_iosf_mutex);
935 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
936 LPSS_IOSF_GPIODEF0, value1, mask1);
938 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
939 LPSS_IOSF_PMCSR, value2, mask2);
941 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
942 LPSS_IOSF_PMCSR, value2, mask2);
944 mutex_unlock(&lpss_iosf_mutex);
947 static int acpi_lpss_suspend(struct device *dev, bool wakeup)
949 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
952 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
953 acpi_lpss_save_ctx(dev, pdata);
955 ret = acpi_dev_suspend(dev, wakeup);
958 * This call must be last in the sequence, otherwise PMC will return
959 * wrong status for devices being about to be powered off. See
960 * lpss_iosf_enter_d3_state() for further information.
962 if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
963 lpss_iosf_enter_d3_state();
968 static int acpi_lpss_resume(struct device *dev)
970 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
974 * This call is kept first to be in symmetry with
975 * acpi_lpss_runtime_suspend() one.
977 if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
978 lpss_iosf_exit_d3_state();
980 ret = acpi_dev_resume(dev);
984 acpi_lpss_d3_to_d0_delay(pdata);
986 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
987 acpi_lpss_restore_ctx(dev, pdata);
992 #ifdef CONFIG_PM_SLEEP
993 static int acpi_lpss_suspend_late(struct device *dev)
997 if (dev_pm_smart_suspend_and_suspended(dev))
1000 ret = pm_generic_suspend_late(dev);
1001 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
1004 static int acpi_lpss_resume_early(struct device *dev)
1006 int ret = acpi_lpss_resume(dev);
1008 return ret ? ret : pm_generic_resume_early(dev);
1010 #endif /* CONFIG_PM_SLEEP */
1012 static int acpi_lpss_runtime_suspend(struct device *dev)
1014 int ret = pm_generic_runtime_suspend(dev);
1016 return ret ? ret : acpi_lpss_suspend(dev, true);
1019 static int acpi_lpss_runtime_resume(struct device *dev)
1021 int ret = acpi_lpss_resume(dev);
1023 return ret ? ret : pm_generic_runtime_resume(dev);
1025 #endif /* CONFIG_PM */
1027 static struct dev_pm_domain acpi_lpss_pm_domain = {
1029 .activate = acpi_lpss_activate,
1030 .dismiss = acpi_lpss_dismiss,
1034 #ifdef CONFIG_PM_SLEEP
1035 .prepare = acpi_subsys_prepare,
1036 .complete = acpi_subsys_complete,
1037 .suspend = acpi_subsys_suspend,
1038 .suspend_late = acpi_lpss_suspend_late,
1039 .suspend_noirq = acpi_subsys_suspend_noirq,
1040 .resume_noirq = acpi_subsys_resume_noirq,
1041 .resume_early = acpi_lpss_resume_early,
1042 .freeze = acpi_subsys_freeze,
1043 .freeze_late = acpi_subsys_freeze_late,
1044 .freeze_noirq = acpi_subsys_freeze_noirq,
1045 .thaw_noirq = acpi_subsys_thaw_noirq,
1046 .poweroff = acpi_subsys_suspend,
1047 .poweroff_late = acpi_lpss_suspend_late,
1048 .poweroff_noirq = acpi_subsys_suspend_noirq,
1049 .restore_noirq = acpi_subsys_resume_noirq,
1050 .restore_early = acpi_lpss_resume_early,
1052 .runtime_suspend = acpi_lpss_runtime_suspend,
1053 .runtime_resume = acpi_lpss_runtime_resume,
1058 static int acpi_lpss_platform_notify(struct notifier_block *nb,
1059 unsigned long action, void *data)
1061 struct platform_device *pdev = to_platform_device(data);
1062 struct lpss_private_data *pdata;
1063 struct acpi_device *adev;
1064 const struct acpi_device_id *id;
1066 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
1067 if (!id || !id->driver_data)
1070 if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
1073 pdata = acpi_driver_data(adev);
1077 if (pdata->mmio_base &&
1078 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
1079 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
1084 case BUS_NOTIFY_BIND_DRIVER:
1085 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
1087 case BUS_NOTIFY_DRIVER_NOT_BOUND:
1088 case BUS_NOTIFY_UNBOUND_DRIVER:
1089 dev_pm_domain_set(&pdev->dev, NULL);
1091 case BUS_NOTIFY_ADD_DEVICE:
1092 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
1093 if (pdata->dev_desc->flags & LPSS_LTR)
1094 return sysfs_create_group(&pdev->dev.kobj,
1097 case BUS_NOTIFY_DEL_DEVICE:
1098 if (pdata->dev_desc->flags & LPSS_LTR)
1099 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
1100 dev_pm_domain_set(&pdev->dev, NULL);
1109 static struct notifier_block acpi_lpss_nb = {
1110 .notifier_call = acpi_lpss_platform_notify,
1113 static void acpi_lpss_bind(struct device *dev)
1115 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1117 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
1120 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
1121 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
1123 dev_err(dev, "MMIO size insufficient to access LTR\n");
1126 static void acpi_lpss_unbind(struct device *dev)
1128 dev->power.set_latency_tolerance = NULL;
1131 static struct acpi_scan_handler lpss_handler = {
1132 .ids = acpi_lpss_device_ids,
1133 .attach = acpi_lpss_create_device,
1134 .bind = acpi_lpss_bind,
1135 .unbind = acpi_lpss_unbind,
1138 void __init acpi_lpss_init(void)
1140 const struct x86_cpu_id *id;
1143 ret = lpt_clk_init();
1147 id = x86_match_cpu(lpss_cpu_ids);
1149 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
1151 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
1152 acpi_scan_add_handler(&lpss_handler);
1157 static struct acpi_scan_handler lpss_handler = {
1158 .ids = acpi_lpss_device_ids,
1161 void __init acpi_lpss_init(void)
1163 acpi_scan_add_handler(&lpss_handler);
1166 #endif /* CONFIG_X86_INTEL_LPSS */