1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2020-2023 Intel Corporation
9 #include <drm/drm_device.h>
10 #include <drm/drm_drv.h>
11 #include <drm/drm_managed.h>
12 #include <drm/drm_mm.h>
13 #include <drm/drm_print.h>
15 #include <linux/pci.h>
16 #include <linux/xarray.h>
17 #include <uapi/drm/ivpu_accel.h>
19 #include "ivpu_mmu_context.h"
21 #define DRIVER_NAME "intel_vpu"
22 #define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)"
23 #define DRIVER_DATE "20230117"
25 #define PCI_DEVICE_ID_MTL 0x7d1d
26 #define PCI_DEVICE_ID_ARL 0xad1d
27 #define PCI_DEVICE_ID_LNL 0x643e
29 #define IVPU_HW_37XX 37
30 #define IVPU_HW_40XX 40
32 #define IVPU_GLOBAL_CONTEXT_MMU_SSID 0
33 /* SSID 1 is used by the VPU to represent reserved context */
34 #define IVPU_RESERVED_CONTEXT_MMU_SSID 1
35 #define IVPU_USER_CONTEXT_MIN_SSID 2
36 #define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 63)
38 #define IVPU_NUM_ENGINES 2
40 #define IVPU_PLATFORM_SILICON 0
41 #define IVPU_PLATFORM_SIMICS 2
42 #define IVPU_PLATFORM_FPGA 3
43 #define IVPU_PLATFORM_INVALID 8
45 #define IVPU_DBG_REG BIT(0)
46 #define IVPU_DBG_IRQ BIT(1)
47 #define IVPU_DBG_MMU BIT(2)
48 #define IVPU_DBG_FILE BIT(3)
49 #define IVPU_DBG_MISC BIT(4)
50 #define IVPU_DBG_FW_BOOT BIT(5)
51 #define IVPU_DBG_PM BIT(6)
52 #define IVPU_DBG_IPC BIT(7)
53 #define IVPU_DBG_BO BIT(8)
54 #define IVPU_DBG_JOB BIT(9)
55 #define IVPU_DBG_JSM BIT(10)
56 #define IVPU_DBG_KREF BIT(11)
57 #define IVPU_DBG_RPM BIT(12)
59 #define ivpu_err(vdev, fmt, ...) \
60 drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
62 #define ivpu_err_ratelimited(vdev, fmt, ...) \
63 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
65 #define ivpu_warn(vdev, fmt, ...) \
66 drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
68 #define ivpu_warn_ratelimited(vdev, fmt, ...) \
69 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
71 #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
73 #define ivpu_dbg(vdev, type, fmt, args...) do { \
74 if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \
75 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \
78 #define IVPU_WA(wa_name) (vdev->wa.wa_name)
80 #define IVPU_PRINT_WA(wa_name) do { \
81 if (IVPU_WA(wa_name)) \
82 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \
85 struct ivpu_wa_table {
87 bool clear_runtime_mem;
88 bool d3hot_after_power_off;
89 bool interrupt_clear_with_0;
90 bool disable_clock_relinquish;
91 bool disable_d0i3_msg;
101 struct drm_device drm;
107 struct ivpu_wa_table wa;
108 struct ivpu_hw_info *hw;
109 struct ivpu_mmu_info *mmu;
110 struct ivpu_fw_info *fw;
111 struct ivpu_ipc_info *ipc;
112 struct ivpu_pm_info *pm;
114 struct ivpu_mmu_context gctx;
115 struct ivpu_mmu_context rctx;
116 struct xarray context_xa;
117 struct xa_limit context_xa_limit;
119 struct mutex bo_list_lock; /* Protects bo_list */
120 struct list_head bo_list;
122 struct xarray submitted_jobs_xa;
123 struct task_struct *job_done_thread;
125 atomic64_t unique_id_counter;
131 int reschedule_suspend;
138 * file_priv has its own refcount (ref) that allows user space to close the fd
139 * without blocking even if VPU is still processing some jobs.
141 struct ivpu_file_priv {
143 struct ivpu_device *vdev;
144 struct mutex lock; /* Protects cmdq */
145 struct ivpu_cmdq *cmdq[IVPU_NUM_ENGINES];
146 struct ivpu_mmu_context ctx;
151 extern int ivpu_dbg_mask;
152 extern u8 ivpu_pll_min_ratio;
153 extern u8 ivpu_pll_max_ratio;
154 extern bool ivpu_disable_mmu_cont_pages;
156 #define IVPU_TEST_MODE_FW_TEST BIT(0)
157 #define IVPU_TEST_MODE_NULL_HW BIT(1)
158 #define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2)
159 #define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4)
160 #define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5)
161 extern int ivpu_test_mode;
163 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
164 struct ivpu_file_priv *ivpu_file_priv_get_by_ctx_id(struct ivpu_device *vdev, unsigned long id);
165 void ivpu_file_priv_put(struct ivpu_file_priv **link);
167 int ivpu_boot(struct ivpu_device *vdev);
168 int ivpu_shutdown(struct ivpu_device *vdev);
169 void ivpu_prepare_for_reset(struct ivpu_device *vdev);
171 static inline u8 ivpu_revision(struct ivpu_device *vdev)
173 return to_pci_dev(vdev->drm.dev)->revision;
176 static inline u16 ivpu_device_id(struct ivpu_device *vdev)
178 return to_pci_dev(vdev->drm.dev)->device;
181 static inline int ivpu_hw_gen(struct ivpu_device *vdev)
183 switch (ivpu_device_id(vdev)) {
184 case PCI_DEVICE_ID_MTL:
185 case PCI_DEVICE_ID_ARL:
187 case PCI_DEVICE_ID_LNL:
190 ivpu_err(vdev, "Unknown VPU device\n");
195 static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
197 return container_of(dev, struct ivpu_device, drm);
200 static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
202 struct xa_limit ctx_limit = vdev->context_xa_limit;
204 return (ctx_limit.max - ctx_limit.min + 1);
207 static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
209 WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
210 return vdev->platform;
213 static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
215 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
218 static inline bool ivpu_is_simics(struct ivpu_device *vdev)
220 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
223 static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
225 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA;
228 #endif /* __IVPU_DRV_H__ */