1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2020-2023 Intel Corporation
9 #include <drm/drm_device.h>
10 #include <drm/drm_managed.h>
11 #include <drm/drm_mm.h>
12 #include <drm/drm_print.h>
14 #include <linux/pci.h>
15 #include <linux/xarray.h>
16 #include <uapi/drm/ivpu_accel.h>
18 #include "ivpu_mmu_context.h"
20 #define DRIVER_NAME "intel_vpu"
21 #define DRIVER_DESC "Driver for Intel Versatile Processing Unit (VPU)"
22 #define DRIVER_DATE "20230117"
24 #define PCI_DEVICE_ID_MTL 0x7d1d
26 #define IVPU_GLOBAL_CONTEXT_MMU_SSID 0
27 #define IVPU_CONTEXT_LIMIT 64
28 #define IVPU_NUM_ENGINES 2
30 #define IVPU_PLATFORM_SILICON 0
31 #define IVPU_PLATFORM_SIMICS 2
32 #define IVPU_PLATFORM_FPGA 3
33 #define IVPU_PLATFORM_INVALID 8
35 #define IVPU_DBG_REG BIT(0)
36 #define IVPU_DBG_IRQ BIT(1)
37 #define IVPU_DBG_MMU BIT(2)
38 #define IVPU_DBG_FILE BIT(3)
39 #define IVPU_DBG_MISC BIT(4)
40 #define IVPU_DBG_FW_BOOT BIT(5)
41 #define IVPU_DBG_PM BIT(6)
42 #define IVPU_DBG_IPC BIT(7)
43 #define IVPU_DBG_BO BIT(8)
44 #define IVPU_DBG_JOB BIT(9)
45 #define IVPU_DBG_JSM BIT(10)
46 #define IVPU_DBG_KREF BIT(11)
47 #define IVPU_DBG_RPM BIT(12)
49 #define ivpu_err(vdev, fmt, ...) \
50 drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
52 #define ivpu_err_ratelimited(vdev, fmt, ...) \
53 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
55 #define ivpu_warn(vdev, fmt, ...) \
56 drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
58 #define ivpu_warn_ratelimited(vdev, fmt, ...) \
59 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
61 #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
63 #define ivpu_dbg(vdev, type, fmt, args...) do { \
64 if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \
65 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \
68 #define IVPU_WA(wa_name) (vdev->wa.wa_name)
70 struct ivpu_wa_table {
72 bool clear_runtime_mem;
79 struct drm_device drm;
85 struct ivpu_wa_table wa;
86 struct ivpu_hw_info *hw;
87 struct ivpu_mmu_info *mmu;
89 struct ivpu_mmu_context gctx;
90 struct xarray context_xa;
91 struct xa_limit context_xa_limit;
97 int reschedule_suspend;
102 * file_priv has its own refcount (ref) that allows user space to close the fd
103 * without blocking even if VPU is still processing some jobs.
105 struct ivpu_file_priv {
107 struct ivpu_device *vdev;
108 struct ivpu_mmu_context ctx;
113 extern int ivpu_dbg_mask;
114 extern u8 ivpu_pll_min_ratio;
115 extern u8 ivpu_pll_max_ratio;
117 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
118 struct ivpu_file_priv *ivpu_file_priv_get_by_ctx_id(struct ivpu_device *vdev, unsigned long id);
119 void ivpu_file_priv_put(struct ivpu_file_priv **link);
120 int ivpu_shutdown(struct ivpu_device *vdev);
122 static inline bool ivpu_is_mtl(struct ivpu_device *vdev)
124 return to_pci_dev(vdev->drm.dev)->device == PCI_DEVICE_ID_MTL;
127 static inline u8 ivpu_revision(struct ivpu_device *vdev)
129 return to_pci_dev(vdev->drm.dev)->revision;
132 static inline u16 ivpu_device_id(struct ivpu_device *vdev)
134 return to_pci_dev(vdev->drm.dev)->device;
137 static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
139 return container_of(dev, struct ivpu_device, drm);
142 static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
144 struct xa_limit ctx_limit = vdev->context_xa_limit;
146 return (ctx_limit.max - ctx_limit.min + 1);
149 static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
151 WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
152 return vdev->platform;
155 static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
157 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
160 static inline bool ivpu_is_simics(struct ivpu_device *vdev)
162 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
165 static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
167 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA;
170 #endif /* __IVPU_DRV_H__ */