drivers/accel/habanalabs/goya/goya.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 /*
   4  * Copyright 2016-2022 HabanaLabs, Ltd.
   5  * All Rights Reserved.
   6  */
   7
   8 #include "goyaP.h"
   9 #include "../include/hw_ip/mmu/mmu_general.h"
  10 #include "../include/hw_ip/mmu/mmu_v1_0.h"
  11 #include "../include/goya/asic_reg/goya_masks.h"
  12 #include "../include/goya/goya_reg_map.h"
  13
  14 #include <linux/pci.h>
  15 #include <linux/hwmon.h>
  16 #include <linux/iommu.h>
  17 #include <linux/seq_file.h>
  18
  19 /*
  20  * GOYA security scheme:
  21  *
  22  * 1. Host is protected by:
  23  *        - Range registers (When MMU is enabled, DMA RR does NOT protect host)
  24  *        - MMU
  25  *
  26  * 2. DRAM is protected by:
  27  *        - Range registers (protect the first 512MB)
  28  *        - MMU (isolation between users)
  29  *
  30  * 3. Configuration is protected by:
  31  *        - Range registers
  32  *        - Protection bits
  33  *
  34  * When MMU is disabled:
  35  *
  36  * QMAN DMA: PQ, CQ, CP, DMA are secured.
  37  * PQ, CB and the data are on the host.
  38  *
  39  * QMAN TPC/MME:
  40  * PQ, CQ and CP are not secured.
  41  * PQ, CB and the data are on the SRAM/DRAM.
  42  *
  43  * Since QMAN DMA is secured, the driver is parsing the DMA CB:
  44  *     - checks DMA pointer
  45  *     - WREG, MSG_PROT are not allowed.
  46  *     - MSG_LONG/SHORT are allowed.
  47  *
  48  * A read/write transaction by the QMAN to a protected area will succeed if
  49  * and only if the QMAN's CP is secured and MSG_PROT is used
  50  *
  51  *
  52  * When MMU is enabled:
  53  *
  54  * QMAN DMA: PQ, CQ and CP are secured.
  55  * MMU is set to bypass on the Secure props register of the QMAN.
  56  * The reasons we don't enable MMU for PQ, CQ and CP are:
  57  *     - PQ entry is in kernel address space and the driver doesn't map it.
  58  *     - CP writes to MSIX register and to kernel address space (completion
  59  *       queue).
  60  *
  61  * DMA is not secured but because CP is secured, the driver still needs to parse
  62  * the CB, but doesn't need to check the DMA addresses.
  63  *
  64  * For QMAN DMA 0, DMA is also secured because only the driver uses this DMA and
  65  * the driver doesn't map memory in MMU.
  66  *
  67  * QMAN TPC/MME: PQ, CQ and CP aren't secured (no change from MMU disabled mode)
  68  *
  69  * DMA RR does NOT protect host because DMA is not secured
  70  *
  71  */
  72
  73 #define GOYA_BOOT_FIT_FILE      "habanalabs/goya/goya-boot-fit.itb"
  74 #define GOYA_LINUX_FW_FILE      "habanalabs/goya/goya-fit.itb"
  75
  76 #define GOYA_MMU_REGS_NUM               63
  77
  78 #define GOYA_DMA_POOL_BLK_SIZE          0x100           /* 256 bytes */
  79
  80 #define GOYA_RESET_TIMEOUT_MSEC         500             /* 500ms */
  81 #define GOYA_PLDM_RESET_TIMEOUT_MSEC    20000           /* 20s */
  82 #define GOYA_RESET_WAIT_MSEC            1               /* 1ms */
  83 #define GOYA_CPU_RESET_WAIT_MSEC        100             /* 100ms */
  84 #define GOYA_PLDM_RESET_WAIT_MSEC       1000            /* 1s */
  85 #define GOYA_TEST_QUEUE_WAIT_USEC       100000          /* 100ms */
  86 #define GOYA_PLDM_MMU_TIMEOUT_USEC      (MMU_CONFIG_TIMEOUT_USEC * 100)
  87 #define GOYA_PLDM_QMAN0_TIMEOUT_USEC    (HL_DEVICE_TIMEOUT_USEC * 30)
  88 #define GOYA_BOOT_FIT_REQ_TIMEOUT_USEC  1000000         /* 1s */
  89 #define GOYA_MSG_TO_CPU_TIMEOUT_USEC    4000000         /* 4s */
  90 #define GOYA_WAIT_FOR_BL_TIMEOUT_USEC   15000000        /* 15s */
  91
  92 #define GOYA_QMAN0_FENCE_VAL            0xD169B243
  93
  94 #define GOYA_MAX_STRING_LEN             20
  95
  96 #define GOYA_CB_POOL_CB_CNT             512
  97 #define GOYA_CB_POOL_CB_SIZE            0x20000         /* 128KB */
  98
  99 #define IS_QM_IDLE(engine, qm_glbl_sts0) \
 100         (((qm_glbl_sts0) & engine##_QM_IDLE_MASK) == engine##_QM_IDLE_MASK)
 101 #define IS_DMA_QM_IDLE(qm_glbl_sts0)    IS_QM_IDLE(DMA, qm_glbl_sts0)
 102 #define IS_TPC_QM_IDLE(qm_glbl_sts0)    IS_QM_IDLE(TPC, qm_glbl_sts0)
 103 #define IS_MME_QM_IDLE(qm_glbl_sts0)    IS_QM_IDLE(MME, qm_glbl_sts0)
 104
 105 #define IS_CMDQ_IDLE(engine, cmdq_glbl_sts0) \
 106         (((cmdq_glbl_sts0) & engine##_CMDQ_IDLE_MASK) == \
 107                         engine##_CMDQ_IDLE_MASK)
 108 #define IS_TPC_CMDQ_IDLE(cmdq_glbl_sts0) \
 109         IS_CMDQ_IDLE(TPC, cmdq_glbl_sts0)
 110 #define IS_MME_CMDQ_IDLE(cmdq_glbl_sts0) \
 111         IS_CMDQ_IDLE(MME, cmdq_glbl_sts0)
 112
 113 #define IS_DMA_IDLE(dma_core_sts0) \
 114         !((dma_core_sts0) & DMA_CH_0_STS0_DMA_BUSY_MASK)
 115
 116 #define IS_TPC_IDLE(tpc_cfg_sts) \
 117         (((tpc_cfg_sts) & TPC_CFG_IDLE_MASK) == TPC_CFG_IDLE_MASK)
 118
 119 #define IS_MME_IDLE(mme_arch_sts) \
 120         (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)
 121
 122 static const char goya_irq_name[GOYA_MSIX_ENTRIES][GOYA_MAX_STRING_LEN] = {
 123                 "goya cq 0", "goya cq 1", "goya cq 2", "goya cq 3",
 124                 "goya cq 4", "goya cpu eq"
 125 };
 126
 127 static u16 goya_packet_sizes[MAX_PACKET_ID] = {
 128         [PACKET_WREG_32]        = sizeof(struct packet_wreg32),
 129         [PACKET_WREG_BULK]      = sizeof(struct packet_wreg_bulk),
 130         [PACKET_MSG_LONG]       = sizeof(struct packet_msg_long),
 131         [PACKET_MSG_SHORT]      = sizeof(struct packet_msg_short),
 132         [PACKET_CP_DMA]         = sizeof(struct packet_cp_dma),
 133         [PACKET_MSG_PROT]       = sizeof(struct packet_msg_prot),
 134         [PACKET_FENCE]          = sizeof(struct packet_fence),
 135         [PACKET_LIN_DMA]        = sizeof(struct packet_lin_dma),
 136         [PACKET_NOP]            = sizeof(struct packet_nop),
 137         [PACKET_STOP]           = sizeof(struct packet_stop)
 138 };
 139
 140 static inline bool validate_packet_id(enum packet_id id)
 141 {
 142         switch (id) {
 143         case PACKET_WREG_32:
 144         case PACKET_WREG_BULK:
 145         case PACKET_MSG_LONG:
 146         case PACKET_MSG_SHORT:
 147         case PACKET_CP_DMA:
 148         case PACKET_MSG_PROT:
 149         case PACKET_FENCE:
 150         case PACKET_LIN_DMA:
 151         case PACKET_NOP:
 152         case PACKET_STOP:
 153                 return true;
 154         default:
 155                 return false;
 156         }
 157 }
 158
 159 static u64 goya_mmu_regs[GOYA_MMU_REGS_NUM] = {
 160         mmDMA_QM_0_GLBL_NON_SECURE_PROPS,
 161         mmDMA_QM_1_GLBL_NON_SECURE_PROPS,
 162         mmDMA_QM_2_GLBL_NON_SECURE_PROPS,
 163         mmDMA_QM_3_GLBL_NON_SECURE_PROPS,
 164         mmDMA_QM_4_GLBL_NON_SECURE_PROPS,
 165         mmTPC0_QM_GLBL_SECURE_PROPS,
 166         mmTPC0_QM_GLBL_NON_SECURE_PROPS,
 167         mmTPC0_CMDQ_GLBL_SECURE_PROPS,
 168         mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS,
 169         mmTPC0_CFG_ARUSER,
 170         mmTPC0_CFG_AWUSER,
 171         mmTPC1_QM_GLBL_SECURE_PROPS,
 172         mmTPC1_QM_GLBL_NON_SECURE_PROPS,
 173         mmTPC1_CMDQ_GLBL_SECURE_PROPS,
 174         mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS,
 175         mmTPC1_CFG_ARUSER,
 176         mmTPC1_CFG_AWUSER,
 177         mmTPC2_QM_GLBL_SECURE_PROPS,
 178         mmTPC2_QM_GLBL_NON_SECURE_PROPS,
 179         mmTPC2_CMDQ_GLBL_SECURE_PROPS,
 180         mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS,
 181         mmTPC2_CFG_ARUSER,
 182         mmTPC2_CFG_AWUSER,
 183         mmTPC3_QM_GLBL_SECURE_PROPS,
 184         mmTPC3_QM_GLBL_NON_SECURE_PROPS,
 185         mmTPC3_CMDQ_GLBL_SECURE_PROPS,
 186         mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS,
 187         mmTPC3_CFG_ARUSER,
 188         mmTPC3_CFG_AWUSER,
 189         mmTPC4_QM_GLBL_SECURE_PROPS,
 190         mmTPC4_QM_GLBL_NON_SECURE_PROPS,
 191         mmTPC4_CMDQ_GLBL_SECURE_PROPS,
 192         mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS,
 193         mmTPC4_CFG_ARUSER,
 194         mmTPC4_CFG_AWUSER,
 195         mmTPC5_QM_GLBL_SECURE_PROPS,
 196         mmTPC5_QM_GLBL_NON_SECURE_PROPS,
 197         mmTPC5_CMDQ_GLBL_SECURE_PROPS,
 198         mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS,
 199         mmTPC5_CFG_ARUSER,
 200         mmTPC5_CFG_AWUSER,
 201         mmTPC6_QM_GLBL_SECURE_PROPS,
 202         mmTPC6_QM_GLBL_NON_SECURE_PROPS,
 203         mmTPC6_CMDQ_GLBL_SECURE_PROPS,
 204         mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS,
 205         mmTPC6_CFG_ARUSER,
 206         mmTPC6_CFG_AWUSER,
 207         mmTPC7_QM_GLBL_SECURE_PROPS,
 208         mmTPC7_QM_GLBL_NON_SECURE_PROPS,
 209         mmTPC7_CMDQ_GLBL_SECURE_PROPS,
 210         mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS,
 211         mmTPC7_CFG_ARUSER,
 212         mmTPC7_CFG_AWUSER,
 213         mmMME_QM_GLBL_SECURE_PROPS,
 214         mmMME_QM_GLBL_NON_SECURE_PROPS,
 215         mmMME_CMDQ_GLBL_SECURE_PROPS,
 216         mmMME_CMDQ_GLBL_NON_SECURE_PROPS,
 217         mmMME_SBA_CONTROL_DATA,
 218         mmMME_SBB_CONTROL_DATA,
 219         mmMME_SBC_CONTROL_DATA,
 220         mmMME_WBC_CONTROL_DATA,
 221         mmPCIE_WRAP_PSOC_ARUSER,
 222         mmPCIE_WRAP_PSOC_AWUSER
 223 };
 224
 225 static u32 goya_all_events[] = {
 226         GOYA_ASYNC_EVENT_ID_PCIE_IF,
 227         GOYA_ASYNC_EVENT_ID_TPC0_ECC,
 228         GOYA_ASYNC_EVENT_ID_TPC1_ECC,
 229         GOYA_ASYNC_EVENT_ID_TPC2_ECC,
 230         GOYA_ASYNC_EVENT_ID_TPC3_ECC,
 231         GOYA_ASYNC_EVENT_ID_TPC4_ECC,
 232         GOYA_ASYNC_EVENT_ID_TPC5_ECC,
 233         GOYA_ASYNC_EVENT_ID_TPC6_ECC,
 234         GOYA_ASYNC_EVENT_ID_TPC7_ECC,
 235         GOYA_ASYNC_EVENT_ID_MME_ECC,
 236         GOYA_ASYNC_EVENT_ID_MME_ECC_EXT,
 237         GOYA_ASYNC_EVENT_ID_MMU_ECC,
 238         GOYA_ASYNC_EVENT_ID_DMA_MACRO,
 239         GOYA_ASYNC_EVENT_ID_DMA_ECC,
 240         GOYA_ASYNC_EVENT_ID_CPU_IF_ECC,
 241         GOYA_ASYNC_EVENT_ID_PSOC_MEM,
 242         GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT,
 243         GOYA_ASYNC_EVENT_ID_SRAM0,
 244         GOYA_ASYNC_EVENT_ID_SRAM1,
 245         GOYA_ASYNC_EVENT_ID_SRAM2,
 246         GOYA_ASYNC_EVENT_ID_SRAM3,
 247         GOYA_ASYNC_EVENT_ID_SRAM4,
 248         GOYA_ASYNC_EVENT_ID_SRAM5,
 249         GOYA_ASYNC_EVENT_ID_SRAM6,
 250         GOYA_ASYNC_EVENT_ID_SRAM7,
 251         GOYA_ASYNC_EVENT_ID_SRAM8,
 252         GOYA_ASYNC_EVENT_ID_SRAM9,
 253         GOYA_ASYNC_EVENT_ID_SRAM10,
 254         GOYA_ASYNC_EVENT_ID_SRAM11,
 255         GOYA_ASYNC_EVENT_ID_SRAM12,
 256         GOYA_ASYNC_EVENT_ID_SRAM13,
 257         GOYA_ASYNC_EVENT_ID_SRAM14,
 258         GOYA_ASYNC_EVENT_ID_SRAM15,
 259         GOYA_ASYNC_EVENT_ID_SRAM16,
 260         GOYA_ASYNC_EVENT_ID_SRAM17,
 261         GOYA_ASYNC_EVENT_ID_SRAM18,
 262         GOYA_ASYNC_EVENT_ID_SRAM19,
 263         GOYA_ASYNC_EVENT_ID_SRAM20,
 264         GOYA_ASYNC_EVENT_ID_SRAM21,
 265         GOYA_ASYNC_EVENT_ID_SRAM22,
 266         GOYA_ASYNC_EVENT_ID_SRAM23,
 267         GOYA_ASYNC_EVENT_ID_SRAM24,
 268         GOYA_ASYNC_EVENT_ID_SRAM25,
 269         GOYA_ASYNC_EVENT_ID_SRAM26,
 270         GOYA_ASYNC_EVENT_ID_SRAM27,
 271         GOYA_ASYNC_EVENT_ID_SRAM28,
 272         GOYA_ASYNC_EVENT_ID_SRAM29,
 273         GOYA_ASYNC_EVENT_ID_GIC500,
 274         GOYA_ASYNC_EVENT_ID_PLL0,
 275         GOYA_ASYNC_EVENT_ID_PLL1,
 276         GOYA_ASYNC_EVENT_ID_PLL3,
 277         GOYA_ASYNC_EVENT_ID_PLL4,
 278         GOYA_ASYNC_EVENT_ID_PLL5,
 279         GOYA_ASYNC_EVENT_ID_PLL6,
 280         GOYA_ASYNC_EVENT_ID_AXI_ECC,
 281         GOYA_ASYNC_EVENT_ID_L2_RAM_ECC,
 282         GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET,
 283         GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT,
 284         GOYA_ASYNC_EVENT_ID_PCIE_DEC,
 285         GOYA_ASYNC_EVENT_ID_TPC0_DEC,
 286         GOYA_ASYNC_EVENT_ID_TPC1_DEC,
 287         GOYA_ASYNC_EVENT_ID_TPC2_DEC,
 288         GOYA_ASYNC_EVENT_ID_TPC3_DEC,
 289         GOYA_ASYNC_EVENT_ID_TPC4_DEC,
 290         GOYA_ASYNC_EVENT_ID_TPC5_DEC,
 291         GOYA_ASYNC_EVENT_ID_TPC6_DEC,
 292         GOYA_ASYNC_EVENT_ID_TPC7_DEC,
 293         GOYA_ASYNC_EVENT_ID_MME_WACS,
 294         GOYA_ASYNC_EVENT_ID_MME_WACSD,
 295         GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER,
 296         GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC,
 297         GOYA_ASYNC_EVENT_ID_PSOC,
 298         GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR,
 299         GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR,
 300         GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR,
 301         GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR,
 302         GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR,
 303         GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR,
 304         GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR,
 305         GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR,
 306         GOYA_ASYNC_EVENT_ID_TPC0_CMDQ,
 307         GOYA_ASYNC_EVENT_ID_TPC1_CMDQ,
 308         GOYA_ASYNC_EVENT_ID_TPC2_CMDQ,
 309         GOYA_ASYNC_EVENT_ID_TPC3_CMDQ,
 310         GOYA_ASYNC_EVENT_ID_TPC4_CMDQ,
 311         GOYA_ASYNC_EVENT_ID_TPC5_CMDQ,
 312         GOYA_ASYNC_EVENT_ID_TPC6_CMDQ,
 313         GOYA_ASYNC_EVENT_ID_TPC7_CMDQ,
 314         GOYA_ASYNC_EVENT_ID_TPC0_QM,
 315         GOYA_ASYNC_EVENT_ID_TPC1_QM,
 316         GOYA_ASYNC_EVENT_ID_TPC2_QM,
 317         GOYA_ASYNC_EVENT_ID_TPC3_QM,
 318         GOYA_ASYNC_EVENT_ID_TPC4_QM,
 319         GOYA_ASYNC_EVENT_ID_TPC5_QM,
 320         GOYA_ASYNC_EVENT_ID_TPC6_QM,
 321         GOYA_ASYNC_EVENT_ID_TPC7_QM,
 322         GOYA_ASYNC_EVENT_ID_MME_QM,
 323         GOYA_ASYNC_EVENT_ID_MME_CMDQ,
 324         GOYA_ASYNC_EVENT_ID_DMA0_QM,
 325         GOYA_ASYNC_EVENT_ID_DMA1_QM,
 326         GOYA_ASYNC_EVENT_ID_DMA2_QM,
 327         GOYA_ASYNC_EVENT_ID_DMA3_QM,
 328         GOYA_ASYNC_EVENT_ID_DMA4_QM,
 329         GOYA_ASYNC_EVENT_ID_DMA0_CH,
 330         GOYA_ASYNC_EVENT_ID_DMA1_CH,
 331         GOYA_ASYNC_EVENT_ID_DMA2_CH,
 332         GOYA_ASYNC_EVENT_ID_DMA3_CH,
 333         GOYA_ASYNC_EVENT_ID_DMA4_CH,
 334         GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU,
 335         GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU,
 336         GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU,
 337         GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU,
 338         GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU,
 339         GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU,
 340         GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU,
 341         GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU,
 342         GOYA_ASYNC_EVENT_ID_DMA_BM_CH0,
 343         GOYA_ASYNC_EVENT_ID_DMA_BM_CH1,
 344         GOYA_ASYNC_EVENT_ID_DMA_BM_CH2,
 345         GOYA_ASYNC_EVENT_ID_DMA_BM_CH3,
 346         GOYA_ASYNC_EVENT_ID_DMA_BM_CH4,
 347         GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S,
 348         GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E,
 349         GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S,
 350         GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E
 351 };
 352
 353 static s64 goya_state_dump_specs_props[SP_MAX] = {0};
 354
 355 static int goya_mmu_clear_pgt_range(struct hl_device *hdev);
 356 static int goya_mmu_set_dram_default_page(struct hl_device *hdev);
 357 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev);
 358 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid);
 359
 360 int goya_set_fixed_properties(struct hl_device *hdev)
 361 {
 362         struct asic_fixed_properties *prop = &hdev->asic_prop;
 363         int i;
 364
 365         prop->max_queues = GOYA_QUEUE_ID_SIZE;
 366         prop->hw_queues_props = kcalloc(prop->max_queues,
 367                         sizeof(struct hw_queue_properties),
 368                         GFP_KERNEL);
 369
 370         if (!prop->hw_queues_props)
 371                 return -ENOMEM;
 372
 373         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
 374                 prop->hw_queues_props[i].type = QUEUE_TYPE_EXT;
 375                 prop->hw_queues_props[i].driver_only = 0;
 376                 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL;
 377         }
 378
 379         for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES ; i++) {
 380                 prop->hw_queues_props[i].type = QUEUE_TYPE_CPU;
 381                 prop->hw_queues_props[i].driver_only = 1;
 382                 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL;
 383         }
 384
 385         for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES +
 386                         NUMBER_OF_INT_HW_QUEUES; i++) {
 387                 prop->hw_queues_props[i].type = QUEUE_TYPE_INT;
 388                 prop->hw_queues_props[i].driver_only = 0;
 389                 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_USER;
 390         }
 391
 392         prop->cfg_base_address = CFG_BASE;
 393         prop->device_dma_offset_for_host_access = HOST_PHYS_BASE;
 394         prop->host_base_address = HOST_PHYS_BASE;
 395         prop->host_end_address = prop->host_base_address + HOST_PHYS_SIZE;
 396         prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES;
 397         prop->completion_mode = HL_COMPLETION_MODE_JOB;
 398         prop->dram_base_address = DRAM_PHYS_BASE;
 399         prop->dram_size = DRAM_PHYS_DEFAULT_SIZE;
 400         prop->dram_end_address = prop->dram_base_address + prop->dram_size;
 401         prop->dram_user_base_address = DRAM_BASE_ADDR_USER;
 402
 403         prop->sram_base_address = SRAM_BASE_ADDR;
 404         prop->sram_size = SRAM_SIZE;
 405         prop->sram_end_address = prop->sram_base_address + prop->sram_size;
 406         prop->sram_user_base_address = prop->sram_base_address +
 407                                                 SRAM_USER_BASE_OFFSET;
 408
 409         prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR;
 410         prop->mmu_dram_default_page_addr = MMU_DRAM_DEFAULT_PAGE_ADDR;
 411         if (hdev->pldm)
 412                 prop->mmu_pgt_size = 0x800000; /* 8MB */
 413         else
 414                 prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE;
 415         prop->mmu_pte_size = HL_PTE_SIZE;
 416         prop->dram_page_size = PAGE_SIZE_2MB;
 417         prop->device_mem_alloc_default_page_size = prop->dram_page_size;
 418         prop->dram_supports_virtual_memory = true;
 419
 420         prop->dmmu.hop_shifts[MMU_HOP0] = MMU_V1_0_HOP0_SHIFT;
 421         prop->dmmu.hop_shifts[MMU_HOP1] = MMU_V1_0_HOP1_SHIFT;
 422         prop->dmmu.hop_shifts[MMU_HOP2] = MMU_V1_0_HOP2_SHIFT;
 423         prop->dmmu.hop_shifts[MMU_HOP3] = MMU_V1_0_HOP3_SHIFT;
 424         prop->dmmu.hop_shifts[MMU_HOP4] = MMU_V1_0_HOP4_SHIFT;
 425         prop->dmmu.hop_masks[MMU_HOP0] = MMU_V1_0_HOP0_MASK;
 426         prop->dmmu.hop_masks[MMU_HOP1] = MMU_V1_0_HOP1_MASK;
 427         prop->dmmu.hop_masks[MMU_HOP2] = MMU_V1_0_HOP2_MASK;
 428         prop->dmmu.hop_masks[MMU_HOP3] = MMU_V1_0_HOP3_MASK;
 429         prop->dmmu.hop_masks[MMU_HOP4] = MMU_V1_0_HOP4_MASK;
 430         prop->dmmu.start_addr = VA_DDR_SPACE_START;
 431         prop->dmmu.end_addr = VA_DDR_SPACE_END;
 432         prop->dmmu.page_size = PAGE_SIZE_2MB;
 433         prop->dmmu.num_hops = MMU_ARCH_5_HOPS;
 434         prop->dmmu.last_mask = LAST_MASK;
 435         /* TODO: will be duplicated until implementing per-MMU props */
 436         prop->dmmu.hop_table_size = HOP_TABLE_SIZE_512_PTE;
 437         prop->dmmu.hop0_tables_total_size = HOP0_512_PTE_TABLES_TOTAL_SIZE;
 438
 439         /* shifts and masks are the same in PMMU and DMMU */
 440         memcpy(&prop->pmmu, &prop->dmmu, sizeof(prop->dmmu));
 441         prop->pmmu.start_addr = VA_HOST_SPACE_START;
 442         prop->pmmu.end_addr = VA_HOST_SPACE_END;
 443         prop->pmmu.page_size = PAGE_SIZE_4KB;
 444         prop->pmmu.num_hops = MMU_ARCH_5_HOPS;
 445         prop->pmmu.last_mask = LAST_MASK;
 446         /* TODO: will be duplicated until implementing per-MMU props */
 447         prop->pmmu.hop_table_size = HOP_TABLE_SIZE_512_PTE;
 448         prop->pmmu.hop0_tables_total_size = HOP0_512_PTE_TABLES_TOTAL_SIZE;
 449
 450         /* PMMU and HPMMU are the same except of page size */
 451         memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu));
 452         prop->pmmu_huge.page_size = PAGE_SIZE_2MB;
 453
 454         prop->dram_size_for_default_page_mapping = VA_DDR_SPACE_END;
 455         prop->cfg_size = CFG_SIZE;
 456         prop->max_asid = MAX_ASID;
 457         prop->num_of_events = GOYA_ASYNC_EVENT_ID_SIZE;
 458         prop->high_pll = PLL_HIGH_DEFAULT;
 459         prop->cb_pool_cb_cnt = GOYA_CB_POOL_CB_CNT;
 460         prop->cb_pool_cb_size = GOYA_CB_POOL_CB_SIZE;
 461         prop->max_power_default = MAX_POWER_DEFAULT;
 462         prop->dc_power_default = DC_POWER_DEFAULT;
 463         prop->tpc_enabled_mask = TPC_ENABLED_MASK;
 464         prop->pcie_dbi_base_address = mmPCIE_DBI_BASE;
 465         prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI;
 466
 467         strscpy_pad(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME,
 468                 CARD_NAME_MAX_LEN);
 469
 470         prop->max_pending_cs = GOYA_MAX_PENDING_CS;
 471
 472         prop->first_available_user_interrupt = USHRT_MAX;
 473         prop->tpc_interrupt_id = USHRT_MAX;
 474         prop->eq_interrupt_id = GOYA_EVENT_QUEUE_MSIX_IDX;
 475
 476         for (i = 0 ; i < HL_MAX_DCORES ; i++)
 477                 prop->first_available_cq[i] = USHRT_MAX;
 478
 479         prop->fw_cpu_boot_dev_sts0_valid = false;
 480         prop->fw_cpu_boot_dev_sts1_valid = false;
 481         prop->hard_reset_done_by_fw = false;
 482         prop->gic_interrupts_enable = true;
 483
 484         prop->server_type = HL_SERVER_TYPE_UNKNOWN;
 485
 486         prop->clk_pll_index = HL_GOYA_MME_PLL;
 487
 488         prop->use_get_power_for_reset_history = true;
 489
 490         prop->configurable_stop_on_err = true;
 491
 492         prop->set_max_power_on_device_init = true;
 493
 494         prop->dma_mask = 48;
 495
 496         return 0;
 497 }
 498
 499 /*
 500  * goya_pci_bars_map - Map PCI BARS of Goya device
 501  *
 502  * @hdev: pointer to hl_device structure
 503  *
 504  * Request PCI regions and map them to kernel virtual addresses.
 505  * Returns 0 on success
 506  *
 507  */
 508 static int goya_pci_bars_map(struct hl_device *hdev)
 509 {
 510         static const char * const name[] = {"SRAM_CFG", "MSIX", "DDR"};
 511         bool is_wc[3] = {false, false, true};
 512         int rc;
 513
 514         rc = hl_pci_bars_map(hdev, name, is_wc);
 515         if (rc)
 516                 return rc;
 517
 518         hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] +
 519                         (CFG_BASE - SRAM_BASE_ADDR);
 520
 521         return 0;
 522 }
 523
 524 static u64 goya_set_ddr_bar_base(struct hl_device *hdev, u64 addr)
 525 {
 526         struct goya_device *goya = hdev->asic_specific;
 527         struct hl_inbound_pci_region pci_region;
 528         u64 old_addr = addr;
 529         int rc;
 530
 531         if ((goya) && (goya->ddr_bar_cur_addr == addr))
 532                 return old_addr;
 533
 534         /* Inbound Region 1 - Bar 4 - Point to DDR */
 535         pci_region.mode = PCI_BAR_MATCH_MODE;
 536         pci_region.bar = DDR_BAR_ID;
 537         pci_region.addr = addr;
 538         rc = hl_pci_set_inbound_region(hdev, 1, &pci_region);
 539         if (rc)
 540                 return U64_MAX;
 541
 542         if (goya) {
 543                 old_addr = goya->ddr_bar_cur_addr;
 544                 goya->ddr_bar_cur_addr = addr;
 545         }
 546
 547         return old_addr;
 548 }
 549
 550 /*
 551  * goya_init_iatu - Initialize the iATU unit inside the PCI controller
 552  *
 553  * @hdev: pointer to hl_device structure
 554  *
 555  * This is needed in case the firmware doesn't initialize the iATU
 556  *
 557  */
 558 static int goya_init_iatu(struct hl_device *hdev)
 559 {
 560         struct hl_inbound_pci_region inbound_region;
 561         struct hl_outbound_pci_region outbound_region;
 562         int rc;
 563
 564         if (hdev->asic_prop.iatu_done_by_fw)
 565                 return 0;
 566
 567         /* Inbound Region 0 - Bar 0 - Point to SRAM and CFG */
 568         inbound_region.mode = PCI_BAR_MATCH_MODE;
 569         inbound_region.bar = SRAM_CFG_BAR_ID;
 570         inbound_region.addr = SRAM_BASE_ADDR;
 571         rc = hl_pci_set_inbound_region(hdev, 0, &inbound_region);
 572         if (rc)
 573                 goto done;
 574
 575         /* Inbound Region 1 - Bar 4 - Point to DDR */
 576         inbound_region.mode = PCI_BAR_MATCH_MODE;
 577         inbound_region.bar = DDR_BAR_ID;
 578         inbound_region.addr = DRAM_PHYS_BASE;
 579         rc = hl_pci_set_inbound_region(hdev, 1, &inbound_region);
 580         if (rc)
 581                 goto done;
 582
 583         /* Outbound Region 0 - Point to Host  */
 584         outbound_region.addr = HOST_PHYS_BASE;
 585         outbound_region.size = HOST_PHYS_SIZE;
 586         rc = hl_pci_set_outbound_region(hdev, &outbound_region);
 587
 588 done:
 589         return rc;
 590 }
 591
 592 static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev)
 593 {
 594         return RREG32(mmHW_STATE);
 595 }
 596
 597 /*
 598  * goya_early_init - GOYA early initialization code
 599  *
 600  * @hdev: pointer to hl_device structure
 601  *
 602  * Verify PCI bars
 603  * Set DMA masks
 604  * PCI controller initialization
 605  * Map PCI bars
 606  *
 607  */
 608 static int goya_early_init(struct hl_device *hdev)
 609 {
 610         struct asic_fixed_properties *prop = &hdev->asic_prop;
 611         struct pci_dev *pdev = hdev->pdev;
 612         resource_size_t pci_bar_size;
 613         u32 fw_boot_status, val;
 614         int rc;
 615
 616         rc = goya_set_fixed_properties(hdev);
 617         if (rc) {
 618                 dev_err(hdev->dev, "Failed to get fixed properties\n");
 619                 return rc;
 620         }
 621
 622         /* Check BAR sizes */
 623         pci_bar_size = pci_resource_len(pdev, SRAM_CFG_BAR_ID);
 624
 625         if (pci_bar_size != CFG_BAR_SIZE) {
 626                 dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n",
 627                         SRAM_CFG_BAR_ID, &pci_bar_size, CFG_BAR_SIZE);
 628                 rc = -ENODEV;
 629                 goto free_queue_props;
 630         }
 631
 632         pci_bar_size = pci_resource_len(pdev, MSIX_BAR_ID);
 633
 634         if (pci_bar_size != MSIX_BAR_SIZE) {
 635                 dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n",
 636                         MSIX_BAR_ID, &pci_bar_size, MSIX_BAR_SIZE);
 637                 rc = -ENODEV;
 638                 goto free_queue_props;
 639         }
 640
 641         prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID);
 642         hdev->dram_pci_bar_start = pci_resource_start(pdev, DDR_BAR_ID);
 643
 644         /* If FW security is enabled at this point it means no access to ELBI */
 645         if (hdev->asic_prop.fw_security_enabled) {
 646                 hdev->asic_prop.iatu_done_by_fw = true;
 647                 goto pci_init;
 648         }
 649
 650         rc = hl_pci_elbi_read(hdev, CFG_BASE + mmCPU_BOOT_DEV_STS0,
 651                                 &fw_boot_status);
 652         if (rc)
 653                 goto free_queue_props;
 654
 655         /* Check whether FW is configuring iATU */
 656         if ((fw_boot_status & CPU_BOOT_DEV_STS0_ENABLED) &&
 657                         (fw_boot_status & CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN))
 658                 hdev->asic_prop.iatu_done_by_fw = true;
 659
 660 pci_init:
 661         rc = hl_pci_init(hdev);
 662         if (rc)
 663                 goto free_queue_props;
 664
 665         /* Before continuing in the initialization, we need to read the preboot
 666          * version to determine whether we run with a security-enabled firmware
 667          */
 668         rc = hl_fw_read_preboot_status(hdev);
 669         if (rc) {
 670                 if (hdev->reset_on_preboot_fail)
 671                         /* we are already on failure flow, so don't check if hw_fini fails. */
 672                         hdev->asic_funcs->hw_fini(hdev, true, false);
 673                 goto pci_fini;
 674         }
 675
 676         if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
 677                 dev_dbg(hdev->dev, "H/W state is dirty, must reset before initializing\n");
 678                 rc = hdev->asic_funcs->hw_fini(hdev, true, false);
 679                 if (rc) {
 680                         dev_err(hdev->dev, "failed to reset HW in dirty state (%d)\n", rc);
 681                         goto pci_fini;
 682                 }
 683         }
 684
 685         if (!hdev->pldm) {
 686                 val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS);
 687                 if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK)
 688                         dev_warn(hdev->dev,
 689                                 "PCI strap is not configured correctly, PCI bus errors may occur\n");
 690         }
 691
 692         return 0;
 693
 694 pci_fini:
 695         hl_pci_fini(hdev);
 696 free_queue_props:
 697         kfree(hdev->asic_prop.hw_queues_props);
 698         return rc;
 699 }
 700
 701 /*
 702  * goya_early_fini - GOYA early finalization code
 703  *
 704  * @hdev: pointer to hl_device structure
 705  *
 706  * Unmap PCI bars
 707  *
 708  */
 709 static int goya_early_fini(struct hl_device *hdev)
 710 {
 711         kfree(hdev->asic_prop.hw_queues_props);
 712         hl_pci_fini(hdev);
 713
 714         return 0;
 715 }
 716
 717 static void goya_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid)
 718 {
 719         /* mask to zero the MMBP and ASID bits */
 720         WREG32_AND(reg, ~0x7FF);
 721         WREG32_OR(reg, asid);
 722 }
 723
 724 static void goya_qman0_set_security(struct hl_device *hdev, bool secure)
 725 {
 726         struct goya_device *goya = hdev->asic_specific;
 727
 728         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
 729                 return;
 730
 731         if (secure)
 732                 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED);
 733         else
 734                 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED);
 735
 736         RREG32(mmDMA_QM_0_GLBL_PROT);
 737 }
 738
 739 /*
 740  * goya_fetch_psoc_frequency - Fetch PSOC frequency values
 741  *
 742  * @hdev: pointer to hl_device structure
 743  *
 744  */
 745 static void goya_fetch_psoc_frequency(struct hl_device *hdev)
 746 {
 747         struct asic_fixed_properties *prop = &hdev->asic_prop;
 748         u32 nr = 0, nf = 0, od = 0, div_fctr = 0, pll_clk, div_sel;
 749         u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS], freq;
 750         int rc;
 751
 752         if (hdev->asic_prop.fw_security_enabled) {
 753                 struct goya_device *goya = hdev->asic_specific;
 754
 755                 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
 756                         return;
 757
 758                 rc = hl_fw_cpucp_pll_info_get(hdev, HL_GOYA_PCI_PLL,
 759                                 pll_freq_arr);
 760
 761                 if (rc)
 762                         return;
 763
 764                 freq = pll_freq_arr[1];
 765         } else {
 766                 div_fctr = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);
 767                 div_sel = RREG32(mmPSOC_PCI_PLL_DIV_SEL_1);
 768                 nr = RREG32(mmPSOC_PCI_PLL_NR);
 769                 nf = RREG32(mmPSOC_PCI_PLL_NF);
 770                 od = RREG32(mmPSOC_PCI_PLL_OD);
 771
 772                 if (div_sel == DIV_SEL_REF_CLK ||
 773                                 div_sel == DIV_SEL_DIVIDED_REF) {
 774                         if (div_sel == DIV_SEL_REF_CLK)
 775                                 freq = PLL_REF_CLK;
 776                         else
 777                                 freq = PLL_REF_CLK / (div_fctr + 1);
 778                 } else if (div_sel == DIV_SEL_PLL_CLK ||
 779                                 div_sel == DIV_SEL_DIVIDED_PLL) {
 780                         pll_clk = PLL_REF_CLK * (nf + 1) /
 781                                         ((nr + 1) * (od + 1));
 782                         if (div_sel == DIV_SEL_PLL_CLK)
 783                                 freq = pll_clk;
 784                         else
 785                                 freq = pll_clk / (div_fctr + 1);
 786                 } else {
 787                         dev_warn(hdev->dev,
 788                                 "Received invalid div select value: %d",
 789                                 div_sel);
 790                         freq = 0;
 791                 }
 792         }
 793
 794         prop->psoc_timestamp_frequency = freq;
 795         prop->psoc_pci_pll_nr = nr;
 796         prop->psoc_pci_pll_nf = nf;
 797         prop->psoc_pci_pll_od = od;
 798         prop->psoc_pci_pll_div_factor = div_fctr;
 799 }
 800
 801 /*
 802  * goya_set_frequency - set the frequency of the device
 803  *
 804  * @hdev: pointer to habanalabs device structure
 805  * @freq: the new frequency value
 806  *
 807  * Change the frequency if needed. This function has no protection against
 808  * concurrency, therefore it is assumed that the calling function has protected
 809  * itself against the case of calling this function from multiple threads with
 810  * different values
 811  *
 812  * Returns 0 if no change was done, otherwise returns 1
 813  */
 814 int goya_set_frequency(struct hl_device *hdev, enum hl_pll_frequency freq)
 815 {
 816         struct goya_device *goya = hdev->asic_specific;
 817
 818         if ((goya->pm_mng_profile == PM_MANUAL) ||
 819                         (goya->curr_pll_profile == freq))
 820                 return 0;
 821
 822         dev_dbg(hdev->dev, "Changing device frequency to %s\n",
 823                 freq == PLL_HIGH ? "high" : "low");
 824
 825         goya_set_pll_profile(hdev, freq);
 826
 827         goya->curr_pll_profile = freq;
 828
 829         return 1;
 830 }
 831
 832 static void goya_set_freq_to_low_job(struct work_struct *work)
 833 {
 834         struct goya_work_freq *goya_work = container_of(work,
 835                                                 struct goya_work_freq,
 836                                                 work_freq.work);
 837         struct hl_device *hdev = goya_work->hdev;
 838
 839         mutex_lock(&hdev->fpriv_list_lock);
 840
 841         if (!hdev->is_compute_ctx_active)
 842                 goya_set_frequency(hdev, PLL_LOW);
 843
 844         mutex_unlock(&hdev->fpriv_list_lock);
 845
 846         schedule_delayed_work(&goya_work->work_freq,
 847                         usecs_to_jiffies(HL_PLL_LOW_JOB_FREQ_USEC));
 848 }
 849
 850 int goya_late_init(struct hl_device *hdev)
 851 {
 852         struct asic_fixed_properties *prop = &hdev->asic_prop;
 853         struct goya_device *goya = hdev->asic_specific;
 854         int rc;
 855
 856         goya_fetch_psoc_frequency(hdev);
 857
 858         rc = goya_mmu_clear_pgt_range(hdev);
 859         if (rc) {
 860                 dev_err(hdev->dev,
 861                         "Failed to clear MMU page tables range %d\n", rc);
 862                 return rc;
 863         }
 864
 865         rc = goya_mmu_set_dram_default_page(hdev);
 866         if (rc) {
 867                 dev_err(hdev->dev, "Failed to set DRAM default page %d\n", rc);
 868                 return rc;
 869         }
 870
 871         rc = goya_mmu_add_mappings_for_device_cpu(hdev);
 872         if (rc)
 873                 return rc;
 874
 875         rc = goya_init_cpu_queues(hdev);
 876         if (rc)
 877                 return rc;
 878
 879         rc = goya_test_cpu_queue(hdev);
 880         if (rc)
 881                 return rc;
 882
 883         rc = goya_cpucp_info_get(hdev);
 884         if (rc) {
 885                 dev_err(hdev->dev, "Failed to get cpucp info %d\n", rc);
 886                 return rc;
 887         }
 888
 889         /* Now that we have the DRAM size in ASIC prop, we need to check
 890          * its size and configure the DMA_IF DDR wrap protection (which is in
 891          * the MMU block) accordingly. The value is the log2 of the DRAM size
 892          */
 893         WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size));
 894
 895         rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS, 0x0);
 896         if (rc) {
 897                 dev_err(hdev->dev,
 898                         "Failed to enable PCI access from CPU %d\n", rc);
 899                 return rc;
 900         }
 901
 902         /* force setting to low frequency */
 903         goya->curr_pll_profile = PLL_LOW;
 904
 905         goya->pm_mng_profile = PM_AUTO;
 906
 907         goya_set_pll_profile(hdev, PLL_LOW);
 908
 909         schedule_delayed_work(&goya->goya_work->work_freq,
 910                 usecs_to_jiffies(HL_PLL_LOW_JOB_FREQ_USEC));
 911
 912         return 0;
 913 }
 914
 915 /*
 916  * goya_late_fini - GOYA late tear-down code
 917  *
 918  * @hdev: pointer to hl_device structure
 919  *
 920  * Free sensors allocated structures
 921  */
 922 void goya_late_fini(struct hl_device *hdev)
 923 {
 924         struct goya_device *goya = hdev->asic_specific;
 925
 926         cancel_delayed_work_sync(&goya->goya_work->work_freq);
 927
 928         hl_hwmon_release_resources(hdev);
 929 }
 930
 931 static void goya_set_pci_memory_regions(struct hl_device *hdev)
 932 {
 933         struct asic_fixed_properties *prop = &hdev->asic_prop;
 934         struct pci_mem_region *region;
 935
 936         /* CFG */
 937         region = &hdev->pci_mem_region[PCI_REGION_CFG];
 938         region->region_base = CFG_BASE;
 939         region->region_size = CFG_SIZE;
 940         region->offset_in_bar = CFG_BASE - SRAM_BASE_ADDR;
 941         region->bar_size = CFG_BAR_SIZE;
 942         region->bar_id = SRAM_CFG_BAR_ID;
 943         region->used = 1;
 944
 945         /* SRAM */
 946         region = &hdev->pci_mem_region[PCI_REGION_SRAM];
 947         region->region_base = SRAM_BASE_ADDR;
 948         region->region_size = SRAM_SIZE;
 949         region->offset_in_bar = 0;
 950         region->bar_size = CFG_BAR_SIZE;
 951         region->bar_id = SRAM_CFG_BAR_ID;
 952         region->used = 1;
 953
 954         /* DRAM */
 955         region = &hdev->pci_mem_region[PCI_REGION_DRAM];
 956         region->region_base = DRAM_PHYS_BASE;
 957         region->region_size = hdev->asic_prop.dram_size;
 958         region->offset_in_bar = 0;
 959         region->bar_size = prop->dram_pci_bar_size;
 960         region->bar_id = DDR_BAR_ID;
 961         region->used = 1;
 962 }
 963
 964 /*
 965  * goya_sw_init - Goya software initialization code
 966  *
 967  * @hdev: pointer to hl_device structure
 968  *
 969  */
 970 static int goya_sw_init(struct hl_device *hdev)
 971 {
 972         struct goya_device *goya;
 973         int rc;
 974
 975         /* Allocate device structure */
 976         goya = kzalloc(sizeof(*goya), GFP_KERNEL);
 977         if (!goya)
 978                 return -ENOMEM;
 979
 980         /* according to goya_init_iatu */
 981         goya->ddr_bar_cur_addr = DRAM_PHYS_BASE;
 982
 983         goya->mme_clk = GOYA_PLL_FREQ_LOW;
 984         goya->tpc_clk = GOYA_PLL_FREQ_LOW;
 985         goya->ic_clk = GOYA_PLL_FREQ_LOW;
 986
 987         hdev->asic_specific = goya;
 988
 989         /* Create DMA pool for small allocations */
 990         hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),
 991                         &hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0);
 992         if (!hdev->dma_pool) {
 993                 dev_err(hdev->dev, "failed to create DMA pool\n");
 994                 rc = -ENOMEM;
 995                 goto free_goya_device;
 996         }
 997
 998         hdev->cpu_accessible_dma_mem = hl_asic_dma_alloc_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE,
 999                                                         &hdev->cpu_accessible_dma_address,
1000                                                         GFP_KERNEL | __GFP_ZERO);
1001
1002         if (!hdev->cpu_accessible_dma_mem) {
1003                 rc = -ENOMEM;
1004                 goto free_dma_pool;
1005         }
1006
1007         dev_dbg(hdev->dev, "cpu accessible memory at bus address %pad\n",
1008                 &hdev->cpu_accessible_dma_address);
1009
1010         hdev->cpu_accessible_dma_pool = gen_pool_create(ilog2(32), -1);
1011         if (!hdev->cpu_accessible_dma_pool) {
1012                 dev_err(hdev->dev,
1013                         "Failed to create CPU accessible DMA pool\n");
1014                 rc = -ENOMEM;
1015                 goto free_cpu_dma_mem;
1016         }
1017
1018         rc = gen_pool_add(hdev->cpu_accessible_dma_pool,
1019                                 (uintptr_t) hdev->cpu_accessible_dma_mem,
1020                                 HL_CPU_ACCESSIBLE_MEM_SIZE, -1);
1021         if (rc) {
1022                 dev_err(hdev->dev,
1023                         "Failed to add memory to CPU accessible DMA pool\n");
1024                 rc = -EFAULT;
1025                 goto free_cpu_accessible_dma_pool;
1026         }
1027
1028         spin_lock_init(&goya->hw_queues_lock);
1029         hdev->supports_coresight = true;
1030         hdev->asic_prop.supports_compute_reset = true;
1031         hdev->asic_prop.allow_inference_soft_reset = true;
1032         hdev->supports_wait_for_multi_cs = false;
1033         hdev->supports_ctx_switch = true;
1034
1035         hdev->asic_funcs->set_pci_memory_regions(hdev);
1036
1037         goya->goya_work = kmalloc(sizeof(struct goya_work_freq), GFP_KERNEL);
1038         if (!goya->goya_work) {
1039                 rc = -ENOMEM;
1040                 goto free_cpu_accessible_dma_pool;
1041         }
1042
1043         goya->goya_work->hdev = hdev;
1044         INIT_DELAYED_WORK(&goya->goya_work->work_freq, goya_set_freq_to_low_job);
1045
1046         return 0;
1047
1048 free_cpu_accessible_dma_pool:
1049         gen_pool_destroy(hdev->cpu_accessible_dma_pool);
1050 free_cpu_dma_mem:
1051         hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem,
1052                                         hdev->cpu_accessible_dma_address);
1053 free_dma_pool:
1054         dma_pool_destroy(hdev->dma_pool);
1055 free_goya_device:
1056         kfree(goya);
1057
1058         return rc;
1059 }
1060
1061 /*
1062  * goya_sw_fini - Goya software tear-down code
1063  *
1064  * @hdev: pointer to hl_device structure
1065  *
1066  */
1067 static int goya_sw_fini(struct hl_device *hdev)
1068 {
1069         struct goya_device *goya = hdev->asic_specific;
1070
1071         gen_pool_destroy(hdev->cpu_accessible_dma_pool);
1072
1073         hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem,
1074                                         hdev->cpu_accessible_dma_address);
1075
1076         dma_pool_destroy(hdev->dma_pool);
1077
1078         kfree(goya->goya_work);
1079         kfree(goya);
1080
1081         return 0;
1082 }
1083
1084 static void goya_init_dma_qman(struct hl_device *hdev, int dma_id,
1085                 dma_addr_t bus_address)
1086 {
1087         struct goya_device *goya = hdev->asic_specific;
1088         u32 mtr_base_lo, mtr_base_hi;
1089         u32 so_base_lo, so_base_hi;
1090         u32 gic_base_lo, gic_base_hi;
1091         u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI);
1092         u32 dma_err_cfg = QMAN_DMA_ERR_MSG_EN;
1093
1094         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1095         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1096         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1097         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1098
1099         gic_base_lo =
1100                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1101         gic_base_hi =
1102                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1103
1104         WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address));
1105         WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address));
1106
1107         WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH));
1108         WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0);
1109         WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0);
1110
1111         WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1112         WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1113         WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1114         WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1115         WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1116         WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1117         WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off,
1118                         GOYA_ASYNC_EVENT_ID_DMA0_QM + dma_id);
1119
1120         /* PQ has buffer of 2 cache lines, while CQ has 8 lines */
1121         WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002);
1122         WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008);
1123
1124         if (goya->hw_cap_initialized & HW_CAP_MMU)
1125                 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED);
1126         else
1127                 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED);
1128
1129         if (hdev->stop_on_err)
1130                 dma_err_cfg |= 1 << DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT;
1131
1132         WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, dma_err_cfg);
1133         WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE);
1134 }
1135
1136 static void goya_init_dma_ch(struct hl_device *hdev, int dma_id)
1137 {
1138         u32 gic_base_lo, gic_base_hi;
1139         u64 sob_addr;
1140         u32 reg_off = dma_id * (mmDMA_CH_1_CFG1 - mmDMA_CH_0_CFG1);
1141
1142         gic_base_lo =
1143                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1144         gic_base_hi =
1145                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1146
1147         WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo);
1148         WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi);
1149         WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off,
1150                         GOYA_ASYNC_EVENT_ID_DMA0_CH + dma_id);
1151
1152         if (dma_id)
1153                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
1154                                 (dma_id - 1) * 4;
1155         else
1156                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
1157
1158         WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr));
1159         WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001);
1160 }
1161
1162 /*
1163  * goya_init_dma_qmans - Initialize QMAN DMA registers
1164  *
1165  * @hdev: pointer to hl_device structure
1166  *
1167  * Initialize the H/W registers of the QMAN DMA channels
1168  *
1169  */
1170 void goya_init_dma_qmans(struct hl_device *hdev)
1171 {
1172         struct goya_device *goya = hdev->asic_specific;
1173         struct hl_hw_queue *q;
1174         int i;
1175
1176         if (goya->hw_cap_initialized & HW_CAP_DMA)
1177                 return;
1178
1179         q = &hdev->kernel_queues[0];
1180
1181         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++, q++) {
1182                 q->cq_id = q->msi_vec = i;
1183                 goya_init_dma_qman(hdev, i, q->bus_address);
1184                 goya_init_dma_ch(hdev, i);
1185         }
1186
1187         goya->hw_cap_initialized |= HW_CAP_DMA;
1188 }
1189
1190 /*
1191  * goya_disable_external_queues - Disable external queues
1192  *
1193  * @hdev: pointer to hl_device structure
1194  *
1195  */
1196 static void goya_disable_external_queues(struct hl_device *hdev)
1197 {
1198         struct goya_device *goya = hdev->asic_specific;
1199
1200         if (!(goya->hw_cap_initialized & HW_CAP_DMA))
1201                 return;
1202
1203         WREG32(mmDMA_QM_0_GLBL_CFG0, 0);
1204         WREG32(mmDMA_QM_1_GLBL_CFG0, 0);
1205         WREG32(mmDMA_QM_2_GLBL_CFG0, 0);
1206         WREG32(mmDMA_QM_3_GLBL_CFG0, 0);
1207         WREG32(mmDMA_QM_4_GLBL_CFG0, 0);
1208 }
1209
1210 static int goya_stop_queue(struct hl_device *hdev, u32 cfg_reg,
1211                                 u32 cp_sts_reg, u32 glbl_sts0_reg)
1212 {
1213         int rc;
1214         u32 status;
1215
1216         /* use the values of TPC0 as they are all the same*/
1217
1218         WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
1219
1220         status = RREG32(cp_sts_reg);
1221         if (status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK) {
1222                 rc = hl_poll_timeout(
1223                         hdev,
1224                         cp_sts_reg,
1225                         status,
1226                         !(status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK),
1227                         1000,
1228                         QMAN_FENCE_TIMEOUT_USEC);
1229
1230                 /* if QMAN is stuck in fence no need to check for stop */
1231                 if (rc)
1232                         return 0;
1233         }
1234
1235         rc = hl_poll_timeout(
1236                 hdev,
1237                 glbl_sts0_reg,
1238                 status,
1239                 (status & TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK),
1240                 1000,
1241                 QMAN_STOP_TIMEOUT_USEC);
1242
1243         if (rc) {
1244                 dev_err(hdev->dev,
1245                         "Timeout while waiting for QMAN to stop\n");
1246                 return -EINVAL;
1247         }
1248
1249         return 0;
1250 }
1251
1252 /*
1253  * goya_stop_external_queues - Stop external queues
1254  *
1255  * @hdev: pointer to hl_device structure
1256  *
1257  * Returns 0 on success
1258  *
1259  */
1260 static int goya_stop_external_queues(struct hl_device *hdev)
1261 {
1262         int rc, retval = 0;
1263
1264         struct goya_device *goya = hdev->asic_specific;
1265
1266         if (!(goya->hw_cap_initialized & HW_CAP_DMA))
1267                 return retval;
1268
1269         rc = goya_stop_queue(hdev,
1270                         mmDMA_QM_0_GLBL_CFG1,
1271                         mmDMA_QM_0_CP_STS,
1272                         mmDMA_QM_0_GLBL_STS0);
1273
1274         if (rc) {
1275                 dev_err(hdev->dev, "failed to stop DMA QMAN 0\n");
1276                 retval = -EIO;
1277         }
1278
1279         rc = goya_stop_queue(hdev,
1280                         mmDMA_QM_1_GLBL_CFG1,
1281                         mmDMA_QM_1_CP_STS,
1282                         mmDMA_QM_1_GLBL_STS0);
1283
1284         if (rc) {
1285                 dev_err(hdev->dev, "failed to stop DMA QMAN 1\n");
1286                 retval = -EIO;
1287         }
1288
1289         rc = goya_stop_queue(hdev,
1290                         mmDMA_QM_2_GLBL_CFG1,
1291                         mmDMA_QM_2_CP_STS,
1292                         mmDMA_QM_2_GLBL_STS0);
1293
1294         if (rc) {
1295                 dev_err(hdev->dev, "failed to stop DMA QMAN 2\n");
1296                 retval = -EIO;
1297         }
1298
1299         rc = goya_stop_queue(hdev,
1300                         mmDMA_QM_3_GLBL_CFG1,
1301                         mmDMA_QM_3_CP_STS,
1302                         mmDMA_QM_3_GLBL_STS0);
1303
1304         if (rc) {
1305                 dev_err(hdev->dev, "failed to stop DMA QMAN 3\n");
1306                 retval = -EIO;
1307         }
1308
1309         rc = goya_stop_queue(hdev,
1310                         mmDMA_QM_4_GLBL_CFG1,
1311                         mmDMA_QM_4_CP_STS,
1312                         mmDMA_QM_4_GLBL_STS0);
1313
1314         if (rc) {
1315                 dev_err(hdev->dev, "failed to stop DMA QMAN 4\n");
1316                 retval = -EIO;
1317         }
1318
1319         return retval;
1320 }
1321
1322 /*
1323  * goya_init_cpu_queues - Initialize PQ/CQ/EQ of CPU
1324  *
1325  * @hdev: pointer to hl_device structure
1326  *
1327  * Returns 0 on success
1328  *
1329  */
1330 int goya_init_cpu_queues(struct hl_device *hdev)
1331 {
1332         struct goya_device *goya = hdev->asic_specific;
1333         struct asic_fixed_properties *prop = &hdev->asic_prop;
1334         struct hl_eq *eq;
1335         u32 status;
1336         struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
1337         int err;
1338
1339         if (!hdev->cpu_queues_enable)
1340                 return 0;
1341
1342         if (goya->hw_cap_initialized & HW_CAP_CPU_Q)
1343                 return 0;
1344
1345         eq = &hdev->event_queue;
1346
1347         WREG32(mmCPU_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address));
1348         WREG32(mmCPU_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address));
1349
1350         WREG32(mmCPU_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address));
1351         WREG32(mmCPU_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address));
1352
1353         WREG32(mmCPU_CQ_BASE_ADDR_LOW,
1354                         lower_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR));
1355         WREG32(mmCPU_CQ_BASE_ADDR_HIGH,
1356                         upper_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR));
1357
1358         WREG32(mmCPU_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES);
1359         WREG32(mmCPU_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES);
1360         WREG32(mmCPU_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE);
1361
1362         /* Used for EQ CI */
1363         WREG32(mmCPU_EQ_CI, 0);
1364
1365         WREG32(mmCPU_IF_PF_PQ_PI, 0);
1366
1367         WREG32(mmCPU_PQ_INIT_STATUS, PQ_INIT_STATUS_READY_FOR_CP);
1368
1369         WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
1370                         GOYA_ASYNC_EVENT_ID_PI_UPDATE);
1371
1372         err = hl_poll_timeout(
1373                 hdev,
1374                 mmCPU_PQ_INIT_STATUS,
1375                 status,
1376                 (status == PQ_INIT_STATUS_READY_FOR_HOST),
1377                 1000,
1378                 GOYA_CPU_TIMEOUT_USEC);
1379
1380         if (err) {
1381                 dev_err(hdev->dev,
1382                         "Failed to setup communication with device CPU\n");
1383                 return -EIO;
1384         }
1385
1386         /* update FW application security bits */
1387         if (prop->fw_cpu_boot_dev_sts0_valid)
1388                 prop->fw_app_cpu_boot_dev_sts0 = RREG32(mmCPU_BOOT_DEV_STS0);
1389
1390         if (prop->fw_cpu_boot_dev_sts1_valid)
1391                 prop->fw_app_cpu_boot_dev_sts1 = RREG32(mmCPU_BOOT_DEV_STS1);
1392
1393         goya->hw_cap_initialized |= HW_CAP_CPU_Q;
1394         return 0;
1395 }
1396
1397 static void goya_set_pll_refclk(struct hl_device *hdev)
1398 {
1399         WREG32(mmCPU_PLL_DIV_SEL_0, 0x0);
1400         WREG32(mmCPU_PLL_DIV_SEL_1, 0x0);
1401         WREG32(mmCPU_PLL_DIV_SEL_2, 0x0);
1402         WREG32(mmCPU_PLL_DIV_SEL_3, 0x0);
1403
1404         WREG32(mmIC_PLL_DIV_SEL_0, 0x0);
1405         WREG32(mmIC_PLL_DIV_SEL_1, 0x0);
1406         WREG32(mmIC_PLL_DIV_SEL_2, 0x0);
1407         WREG32(mmIC_PLL_DIV_SEL_3, 0x0);
1408
1409         WREG32(mmMC_PLL_DIV_SEL_0, 0x0);
1410         WREG32(mmMC_PLL_DIV_SEL_1, 0x0);
1411         WREG32(mmMC_PLL_DIV_SEL_2, 0x0);
1412         WREG32(mmMC_PLL_DIV_SEL_3, 0x0);
1413
1414         WREG32(mmPSOC_MME_PLL_DIV_SEL_0, 0x0);
1415         WREG32(mmPSOC_MME_PLL_DIV_SEL_1, 0x0);
1416         WREG32(mmPSOC_MME_PLL_DIV_SEL_2, 0x0);
1417         WREG32(mmPSOC_MME_PLL_DIV_SEL_3, 0x0);
1418
1419         WREG32(mmPSOC_PCI_PLL_DIV_SEL_0, 0x0);
1420         WREG32(mmPSOC_PCI_PLL_DIV_SEL_1, 0x0);
1421         WREG32(mmPSOC_PCI_PLL_DIV_SEL_2, 0x0);
1422         WREG32(mmPSOC_PCI_PLL_DIV_SEL_3, 0x0);
1423
1424         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_0, 0x0);
1425         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_1, 0x0);
1426         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_2, 0x0);
1427         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_3, 0x0);
1428
1429         WREG32(mmTPC_PLL_DIV_SEL_0, 0x0);
1430         WREG32(mmTPC_PLL_DIV_SEL_1, 0x0);
1431         WREG32(mmTPC_PLL_DIV_SEL_2, 0x0);
1432         WREG32(mmTPC_PLL_DIV_SEL_3, 0x0);
1433 }
1434
1435 static void goya_disable_clk_rlx(struct hl_device *hdev)
1436 {
1437         WREG32(mmPSOC_MME_PLL_CLK_RLX_0, 0x100010);
1438         WREG32(mmIC_PLL_CLK_RLX_0, 0x100010);
1439 }
1440
1441 static void _goya_tpc_mbist_workaround(struct hl_device *hdev, u8 tpc_id)
1442 {
1443         u64 tpc_eml_address;
1444         u32 val, tpc_offset, tpc_eml_offset, tpc_slm_offset;
1445         int err, slm_index;
1446
1447         tpc_offset = tpc_id * 0x40000;
1448         tpc_eml_offset = tpc_id * 0x200000;
1449         tpc_eml_address = (mmTPC0_EML_CFG_BASE + tpc_eml_offset - CFG_BASE);
1450         tpc_slm_offset = tpc_eml_address + 0x100000;
1451
1452         /*
1453          * Workaround for Bug H2 #2443 :
1454          * "TPC SB is not initialized on chip reset"
1455          */
1456
1457         val = RREG32(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset);
1458         if (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK)
1459                 dev_warn(hdev->dev, "TPC%d MBIST ACTIVE is not cleared\n",
1460                         tpc_id);
1461
1462         WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000);
1463
1464         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_0 + tpc_offset, 0x37FF);
1465         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_1 + tpc_offset, 0x303F);
1466         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_2 + tpc_offset, 0x71FF);
1467         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_3 + tpc_offset, 0x71FF);
1468         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_4 + tpc_offset, 0x70FF);
1469         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_5 + tpc_offset, 0x70FF);
1470         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_6 + tpc_offset, 0x70FF);
1471         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_7 + tpc_offset, 0x70FF);
1472         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_8 + tpc_offset, 0x70FF);
1473         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_9 + tpc_offset, 0x70FF);
1474
1475         WREG32_OR(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1476                 1 << TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT);
1477
1478         err = hl_poll_timeout(
1479                 hdev,
1480                 mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1481                 val,
1482                 (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK),
1483                 1000,
1484                 HL_DEVICE_TIMEOUT_USEC);
1485
1486         if (err)
1487                 dev_err(hdev->dev,
1488                         "Timeout while waiting for TPC%d MBIST DONE\n", tpc_id);
1489
1490         WREG32_OR(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1491                 1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT);
1492
1493         msleep(GOYA_RESET_WAIT_MSEC);
1494
1495         WREG32_AND(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1496                 ~(1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT));
1497
1498         msleep(GOYA_RESET_WAIT_MSEC);
1499
1500         for (slm_index = 0 ; slm_index < 256 ; slm_index++)
1501                 WREG32(tpc_slm_offset + (slm_index << 2), 0);
1502
1503         val = RREG32(tpc_slm_offset);
1504 }
1505
1506 static void goya_tpc_mbist_workaround(struct hl_device *hdev)
1507 {
1508         struct goya_device *goya = hdev->asic_specific;
1509         int i;
1510
1511         if (hdev->pldm)
1512                 return;
1513
1514         if (goya->hw_cap_initialized & HW_CAP_TPC_MBIST)
1515                 return;
1516
1517         /* Workaround for H2 #2443 */
1518
1519         for (i = 0 ; i < TPC_MAX_NUM ; i++)
1520                 _goya_tpc_mbist_workaround(hdev, i);
1521
1522         goya->hw_cap_initialized |= HW_CAP_TPC_MBIST;
1523 }
1524
1525 /*
1526  * goya_init_golden_registers - Initialize golden registers
1527  *
1528  * @hdev: pointer to hl_device structure
1529  *
1530  * Initialize the H/W registers of the device
1531  *
1532  */
1533 static void goya_init_golden_registers(struct hl_device *hdev)
1534 {
1535         struct goya_device *goya = hdev->asic_specific;
1536         u32 polynom[10], tpc_intr_mask, offset;
1537         int i;
1538
1539         if (goya->hw_cap_initialized & HW_CAP_GOLDEN)
1540                 return;
1541
1542         polynom[0] = 0x00020080;
1543         polynom[1] = 0x00401000;
1544         polynom[2] = 0x00200800;
1545         polynom[3] = 0x00002000;
1546         polynom[4] = 0x00080200;
1547         polynom[5] = 0x00040100;
1548         polynom[6] = 0x00100400;
1549         polynom[7] = 0x00004000;
1550         polynom[8] = 0x00010000;
1551         polynom[9] = 0x00008000;
1552
1553         /* Mask all arithmetic interrupts from TPC */
1554         tpc_intr_mask = 0x7FFF;
1555
1556         for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x20000) {
1557                 WREG32(mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1558                 WREG32(mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1559                 WREG32(mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1560                 WREG32(mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1561                 WREG32(mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1562
1563                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB + offset, 0x204);
1564                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB + offset, 0x204);
1565                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB + offset, 0x204);
1566                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB + offset, 0x204);
1567                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB + offset, 0x204);
1568
1569
1570                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB + offset, 0x206);
1571                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB + offset, 0x206);
1572                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB + offset, 0x206);
1573                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB + offset, 0x207);
1574                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB + offset, 0x207);
1575
1576                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB + offset, 0x207);
1577                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB + offset, 0x207);
1578                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB + offset, 0x206);
1579                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB + offset, 0x206);
1580                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB + offset, 0x206);
1581
1582                 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB + offset, 0x101);
1583                 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB + offset, 0x102);
1584                 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB + offset, 0x103);
1585                 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB + offset, 0x104);
1586                 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB + offset, 0x105);
1587
1588                 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB + offset, 0x105);
1589                 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB + offset, 0x104);
1590                 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB + offset, 0x103);
1591                 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB + offset, 0x102);
1592                 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB + offset, 0x101);
1593         }
1594
1595         WREG32(mmMME_STORE_MAX_CREDIT, 0x21);
1596         WREG32(mmMME_AGU, 0x0f0f0f10);
1597         WREG32(mmMME_SEI_MASK, ~0x0);
1598
1599         WREG32(mmMME6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1600         WREG32(mmMME5_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1601         WREG32(mmMME4_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1602         WREG32(mmMME3_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1603         WREG32(mmMME2_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1604         WREG32(mmMME1_RTR_HBW_RD_RQ_N_ARB, 0x07010701);
1605         WREG32(mmMME6_RTR_HBW_RD_RQ_S_ARB, 0x04010401);
1606         WREG32(mmMME5_RTR_HBW_RD_RQ_S_ARB, 0x04050401);
1607         WREG32(mmMME4_RTR_HBW_RD_RQ_S_ARB, 0x03070301);
1608         WREG32(mmMME3_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1609         WREG32(mmMME2_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1610         WREG32(mmMME1_RTR_HBW_RD_RQ_S_ARB, 0x01050105);
1611         WREG32(mmMME6_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1612         WREG32(mmMME5_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1613         WREG32(mmMME4_RTR_HBW_RD_RQ_W_ARB, 0x01040301);
1614         WREG32(mmMME3_RTR_HBW_RD_RQ_W_ARB, 0x01030401);
1615         WREG32(mmMME2_RTR_HBW_RD_RQ_W_ARB, 0x01040101);
1616         WREG32(mmMME1_RTR_HBW_RD_RQ_W_ARB, 0x01050101);
1617         WREG32(mmMME6_RTR_HBW_WR_RQ_N_ARB, 0x02020202);
1618         WREG32(mmMME5_RTR_HBW_WR_RQ_N_ARB, 0x01070101);
1619         WREG32(mmMME4_RTR_HBW_WR_RQ_N_ARB, 0x02020201);
1620         WREG32(mmMME3_RTR_HBW_WR_RQ_N_ARB, 0x07020701);
1621         WREG32(mmMME2_RTR_HBW_WR_RQ_N_ARB, 0x01020101);
1622         WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1623         WREG32(mmMME6_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1624         WREG32(mmMME5_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1625         WREG32(mmMME4_RTR_HBW_WR_RQ_S_ARB, 0x07020701);
1626         WREG32(mmMME3_RTR_HBW_WR_RQ_S_ARB, 0x02020201);
1627         WREG32(mmMME2_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1628         WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01020102);
1629         WREG32(mmMME6_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1630         WREG32(mmMME5_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1631         WREG32(mmMME4_RTR_HBW_WR_RQ_W_ARB, 0x07020707);
1632         WREG32(mmMME3_RTR_HBW_WR_RQ_W_ARB, 0x01020201);
1633         WREG32(mmMME2_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1634         WREG32(mmMME1_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1635         WREG32(mmMME6_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1636         WREG32(mmMME5_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1637         WREG32(mmMME4_RTR_HBW_RD_RS_N_ARB, 0x01060102);
1638         WREG32(mmMME3_RTR_HBW_RD_RS_N_ARB, 0x01040102);
1639         WREG32(mmMME2_RTR_HBW_RD_RS_N_ARB, 0x01020102);
1640         WREG32(mmMME1_RTR_HBW_RD_RS_N_ARB, 0x01020107);
1641         WREG32(mmMME6_RTR_HBW_RD_RS_S_ARB, 0x01020106);
1642         WREG32(mmMME5_RTR_HBW_RD_RS_S_ARB, 0x01020102);
1643         WREG32(mmMME4_RTR_HBW_RD_RS_S_ARB, 0x01040102);
1644         WREG32(mmMME3_RTR_HBW_RD_RS_S_ARB, 0x01060102);
1645         WREG32(mmMME2_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1646         WREG32(mmMME1_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1647         WREG32(mmMME6_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1648         WREG32(mmMME5_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1649         WREG32(mmMME4_RTR_HBW_RD_RS_E_ARB, 0x01040602);
1650         WREG32(mmMME3_RTR_HBW_RD_RS_E_ARB, 0x01060402);
1651         WREG32(mmMME2_RTR_HBW_RD_RS_E_ARB, 0x01070202);
1652         WREG32(mmMME1_RTR_HBW_RD_RS_E_ARB, 0x01070102);
1653         WREG32(mmMME6_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1654         WREG32(mmMME5_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1655         WREG32(mmMME4_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1656         WREG32(mmMME3_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1657         WREG32(mmMME2_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1658         WREG32(mmMME1_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1659         WREG32(mmMME6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1660         WREG32(mmMME5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1661         WREG32(mmMME4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1662         WREG32(mmMME3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1663         WREG32(mmMME2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1664         WREG32(mmMME1_RTR_HBW_WR_RS_N_ARB, 0x01010107);
1665         WREG32(mmMME6_RTR_HBW_WR_RS_S_ARB, 0x01010107);
1666         WREG32(mmMME5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1667         WREG32(mmMME4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1668         WREG32(mmMME3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1669         WREG32(mmMME2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1670         WREG32(mmMME1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1671         WREG32(mmMME6_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1672         WREG32(mmMME5_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1673         WREG32(mmMME4_RTR_HBW_WR_RS_E_ARB, 0x01040301);
1674         WREG32(mmMME3_RTR_HBW_WR_RS_E_ARB, 0x01030401);
1675         WREG32(mmMME2_RTR_HBW_WR_RS_E_ARB, 0x01040101);
1676         WREG32(mmMME1_RTR_HBW_WR_RS_E_ARB, 0x01050101);
1677         WREG32(mmMME6_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1678         WREG32(mmMME5_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1679         WREG32(mmMME4_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1680         WREG32(mmMME3_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1681         WREG32(mmMME2_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1682         WREG32(mmMME1_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1683
1684         WREG32(mmTPC1_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1685         WREG32(mmTPC1_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1686         WREG32(mmTPC1_RTR_HBW_RD_RQ_E_ARB, 0x01060101);
1687         WREG32(mmTPC1_RTR_HBW_WR_RQ_N_ARB, 0x02020102);
1688         WREG32(mmTPC1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1689         WREG32(mmTPC1_RTR_HBW_WR_RQ_E_ARB, 0x02070202);
1690         WREG32(mmTPC1_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1691         WREG32(mmTPC1_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1692         WREG32(mmTPC1_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1693         WREG32(mmTPC1_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1694         WREG32(mmTPC1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1695         WREG32(mmTPC1_RTR_HBW_WR_RS_W_ARB, 0x01050101);
1696
1697         WREG32(mmTPC2_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1698         WREG32(mmTPC2_RTR_HBW_RD_RQ_S_ARB, 0x01050101);
1699         WREG32(mmTPC2_RTR_HBW_RD_RQ_E_ARB, 0x01010201);
1700         WREG32(mmTPC2_RTR_HBW_WR_RQ_N_ARB, 0x02040102);
1701         WREG32(mmTPC2_RTR_HBW_WR_RQ_S_ARB, 0x01050101);
1702         WREG32(mmTPC2_RTR_HBW_WR_RQ_E_ARB, 0x02060202);
1703         WREG32(mmTPC2_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1704         WREG32(mmTPC2_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1705         WREG32(mmTPC2_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1706         WREG32(mmTPC2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1707         WREG32(mmTPC2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1708         WREG32(mmTPC2_RTR_HBW_WR_RS_W_ARB, 0x01040101);
1709
1710         WREG32(mmTPC3_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1711         WREG32(mmTPC3_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1712         WREG32(mmTPC3_RTR_HBW_RD_RQ_E_ARB, 0x01040301);
1713         WREG32(mmTPC3_RTR_HBW_WR_RQ_N_ARB, 0x02060102);
1714         WREG32(mmTPC3_RTR_HBW_WR_RQ_S_ARB, 0x01040101);
1715         WREG32(mmTPC3_RTR_HBW_WR_RQ_E_ARB, 0x01040301);
1716         WREG32(mmTPC3_RTR_HBW_RD_RS_N_ARB, 0x01040201);
1717         WREG32(mmTPC3_RTR_HBW_RD_RS_S_ARB, 0x01060201);
1718         WREG32(mmTPC3_RTR_HBW_RD_RS_W_ARB, 0x01060402);
1719         WREG32(mmTPC3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1720         WREG32(mmTPC3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1721         WREG32(mmTPC3_RTR_HBW_WR_RS_W_ARB, 0x01030401);
1722
1723         WREG32(mmTPC4_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1724         WREG32(mmTPC4_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1725         WREG32(mmTPC4_RTR_HBW_RD_RQ_E_ARB, 0x01030401);
1726         WREG32(mmTPC4_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1727         WREG32(mmTPC4_RTR_HBW_WR_RQ_S_ARB, 0x01030101);
1728         WREG32(mmTPC4_RTR_HBW_WR_RQ_E_ARB, 0x02060702);
1729         WREG32(mmTPC4_RTR_HBW_RD_RS_N_ARB, 0x01060201);
1730         WREG32(mmTPC4_RTR_HBW_RD_RS_S_ARB, 0x01040201);
1731         WREG32(mmTPC4_RTR_HBW_RD_RS_W_ARB, 0x01040602);
1732         WREG32(mmTPC4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1733         WREG32(mmTPC4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1734         WREG32(mmTPC4_RTR_HBW_WR_RS_W_ARB, 0x01040301);
1735
1736         WREG32(mmTPC5_RTR_HBW_RD_RQ_N_ARB, 0x01050101);
1737         WREG32(mmTPC5_RTR_HBW_RD_RQ_S_ARB, 0x01020101);
1738         WREG32(mmTPC5_RTR_HBW_RD_RQ_E_ARB, 0x01200501);
1739         WREG32(mmTPC5_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1740         WREG32(mmTPC5_RTR_HBW_WR_RQ_S_ARB, 0x01020101);
1741         WREG32(mmTPC5_RTR_HBW_WR_RQ_E_ARB, 0x02020602);
1742         WREG32(mmTPC5_RTR_HBW_RD_RS_N_ARB, 0x01070201);
1743         WREG32(mmTPC5_RTR_HBW_RD_RS_S_ARB, 0x01020201);
1744         WREG32(mmTPC5_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1745         WREG32(mmTPC5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1746         WREG32(mmTPC5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1747         WREG32(mmTPC5_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1748
1749         WREG32(mmTPC6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1750         WREG32(mmTPC6_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1751         WREG32(mmTPC6_RTR_HBW_RD_RQ_E_ARB, 0x01010601);
1752         WREG32(mmTPC6_RTR_HBW_WR_RQ_N_ARB, 0x01010101);
1753         WREG32(mmTPC6_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1754         WREG32(mmTPC6_RTR_HBW_WR_RQ_E_ARB, 0x02020702);
1755         WREG32(mmTPC6_RTR_HBW_RD_RS_N_ARB, 0x01010101);
1756         WREG32(mmTPC6_RTR_HBW_RD_RS_S_ARB, 0x01010101);
1757         WREG32(mmTPC6_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1758         WREG32(mmTPC6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1759         WREG32(mmTPC6_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1760         WREG32(mmTPC6_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1761
1762         for (i = 0, offset = 0 ; i < 10 ; i++, offset += 4) {
1763                 WREG32(mmMME1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1764                 WREG32(mmMME2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1765                 WREG32(mmMME3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1766                 WREG32(mmMME4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1767                 WREG32(mmMME5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1768                 WREG32(mmMME6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1769
1770                 WREG32(mmTPC0_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1771                 WREG32(mmTPC1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1772                 WREG32(mmTPC2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1773                 WREG32(mmTPC3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1774                 WREG32(mmTPC4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1775                 WREG32(mmTPC5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1776                 WREG32(mmTPC6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1777                 WREG32(mmTPC7_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1778
1779                 WREG32(mmPCI_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1780                 WREG32(mmDMA_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1781         }
1782
1783         for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x40000) {
1784                 WREG32(mmMME1_RTR_SCRAMB_EN + offset,
1785                                 1 << MME1_RTR_SCRAMB_EN_VAL_SHIFT);
1786                 WREG32(mmMME1_RTR_NON_LIN_SCRAMB + offset,
1787                                 1 << MME1_RTR_NON_LIN_SCRAMB_EN_SHIFT);
1788         }
1789
1790         for (i = 0, offset = 0 ; i < 8 ; i++, offset += 0x40000) {
1791                 /*
1792                  * Workaround for Bug H2 #2441 :
1793                  * "ST.NOP set trace event illegal opcode"
1794                  */
1795                 WREG32(mmTPC0_CFG_TPC_INTR_MASK + offset, tpc_intr_mask);
1796
1797                 WREG32(mmTPC0_NRTR_SCRAMB_EN + offset,
1798                                 1 << TPC0_NRTR_SCRAMB_EN_VAL_SHIFT);
1799                 WREG32(mmTPC0_NRTR_NON_LIN_SCRAMB + offset,
1800                                 1 << TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1801
1802                 WREG32_FIELD(TPC0_CFG_MSS_CONFIG, offset,
1803                                 ICACHE_FETCH_LINE_NUM, 2);
1804         }
1805
1806         WREG32(mmDMA_NRTR_SCRAMB_EN, 1 << DMA_NRTR_SCRAMB_EN_VAL_SHIFT);
1807         WREG32(mmDMA_NRTR_NON_LIN_SCRAMB,
1808                         1 << DMA_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1809
1810         WREG32(mmPCI_NRTR_SCRAMB_EN, 1 << PCI_NRTR_SCRAMB_EN_VAL_SHIFT);
1811         WREG32(mmPCI_NRTR_NON_LIN_SCRAMB,
1812                         1 << PCI_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1813
1814         /*
1815          * Workaround for H2 #HW-23 bug
1816          * Set DMA max outstanding read requests to 240 on DMA CH 1.
1817          * This limitation is still large enough to not affect Gen4 bandwidth.
1818          * We need to only limit that DMA channel because the user can only read
1819          * from Host using DMA CH 1
1820          */
1821         WREG32(mmDMA_CH_1_CFG0, 0x0fff00F0);
1822
1823         WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
1824
1825         goya->hw_cap_initialized |= HW_CAP_GOLDEN;
1826 }
1827
1828 static void goya_init_mme_qman(struct hl_device *hdev)
1829 {
1830         u32 mtr_base_lo, mtr_base_hi;
1831         u32 so_base_lo, so_base_hi;
1832         u32 gic_base_lo, gic_base_hi;
1833         u64 qman_base_addr;
1834
1835         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1836         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1837         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1838         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1839
1840         gic_base_lo =
1841                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1842         gic_base_hi =
1843                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1844
1845         qman_base_addr = hdev->asic_prop.sram_base_address +
1846                                 MME_QMAN_BASE_OFFSET;
1847
1848         WREG32(mmMME_QM_PQ_BASE_LO, lower_32_bits(qman_base_addr));
1849         WREG32(mmMME_QM_PQ_BASE_HI, upper_32_bits(qman_base_addr));
1850         WREG32(mmMME_QM_PQ_SIZE, ilog2(MME_QMAN_LENGTH));
1851         WREG32(mmMME_QM_PQ_PI, 0);
1852         WREG32(mmMME_QM_PQ_CI, 0);
1853         WREG32(mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET, 0x10C0);
1854         WREG32(mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET, 0x10C4);
1855         WREG32(mmMME_QM_CP_LDMA_TSIZE_OFFSET, 0x10C8);
1856         WREG32(mmMME_QM_CP_LDMA_COMMIT_OFFSET, 0x10CC);
1857
1858         WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1859         WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1860         WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1861         WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1862
1863         /* QMAN CQ has 8 cache lines */
1864         WREG32(mmMME_QM_CQ_CFG1, 0x00080008);
1865
1866         WREG32(mmMME_QM_GLBL_ERR_ADDR_LO, gic_base_lo);
1867         WREG32(mmMME_QM_GLBL_ERR_ADDR_HI, gic_base_hi);
1868
1869         WREG32(mmMME_QM_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_QM);
1870
1871         WREG32(mmMME_QM_GLBL_ERR_CFG, QMAN_MME_ERR_MSG_EN);
1872
1873         WREG32(mmMME_QM_GLBL_PROT, QMAN_MME_ERR_PROT);
1874
1875         WREG32(mmMME_QM_GLBL_CFG0, QMAN_MME_ENABLE);
1876 }
1877
1878 static void goya_init_mme_cmdq(struct hl_device *hdev)
1879 {
1880         u32 mtr_base_lo, mtr_base_hi;
1881         u32 so_base_lo, so_base_hi;
1882         u32 gic_base_lo, gic_base_hi;
1883
1884         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1885         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1886         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1887         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1888
1889         gic_base_lo =
1890                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1891         gic_base_hi =
1892                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1893
1894         WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1895         WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1896         WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1897         WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1898
1899         /* CMDQ CQ has 20 cache lines */
1900         WREG32(mmMME_CMDQ_CQ_CFG1, 0x00140014);
1901
1902         WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_LO, gic_base_lo);
1903         WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_HI, gic_base_hi);
1904
1905         WREG32(mmMME_CMDQ_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_CMDQ);
1906
1907         WREG32(mmMME_CMDQ_GLBL_ERR_CFG, CMDQ_MME_ERR_MSG_EN);
1908
1909         WREG32(mmMME_CMDQ_GLBL_PROT, CMDQ_MME_ERR_PROT);
1910
1911         WREG32(mmMME_CMDQ_GLBL_CFG0, CMDQ_MME_ENABLE);
1912 }
1913
1914 void goya_init_mme_qmans(struct hl_device *hdev)
1915 {
1916         struct goya_device *goya = hdev->asic_specific;
1917         u32 so_base_lo, so_base_hi;
1918
1919         if (goya->hw_cap_initialized & HW_CAP_MME)
1920                 return;
1921
1922         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1923         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1924
1925         WREG32(mmMME_SM_BASE_ADDRESS_LOW, so_base_lo);
1926         WREG32(mmMME_SM_BASE_ADDRESS_HIGH, so_base_hi);
1927
1928         goya_init_mme_qman(hdev);
1929         goya_init_mme_cmdq(hdev);
1930
1931         goya->hw_cap_initialized |= HW_CAP_MME;
1932 }
1933
1934 static void goya_init_tpc_qman(struct hl_device *hdev, u32 base_off, int tpc_id)
1935 {
1936         u32 mtr_base_lo, mtr_base_hi;
1937         u32 so_base_lo, so_base_hi;
1938         u32 gic_base_lo, gic_base_hi;
1939         u64 qman_base_addr;
1940         u32 reg_off = tpc_id * (mmTPC1_QM_PQ_PI - mmTPC0_QM_PQ_PI);
1941
1942         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1943         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1944         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1945         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1946
1947         gic_base_lo =
1948                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1949         gic_base_hi =
1950                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1951
1952         qman_base_addr = hdev->asic_prop.sram_base_address + base_off;
1953
1954         WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr));
1955         WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr));
1956         WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH));
1957         WREG32(mmTPC0_QM_PQ_PI + reg_off, 0);
1958         WREG32(mmTPC0_QM_PQ_CI + reg_off, 0);
1959         WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0);
1960         WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4);
1961         WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8);
1962         WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC);
1963
1964         WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1965         WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1966         WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1967         WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1968
1969         WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008);
1970
1971         WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1972         WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1973
1974         WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off,
1975                         GOYA_ASYNC_EVENT_ID_TPC0_QM + tpc_id);
1976
1977         WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN);
1978
1979         WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT);
1980
1981         WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE);
1982 }
1983
1984 static void goya_init_tpc_cmdq(struct hl_device *hdev, int tpc_id)
1985 {
1986         u32 mtr_base_lo, mtr_base_hi;
1987         u32 so_base_lo, so_base_hi;
1988         u32 gic_base_lo, gic_base_hi;
1989         u32 reg_off = tpc_id * (mmTPC1_CMDQ_CQ_CFG1 - mmTPC0_CMDQ_CQ_CFG1);
1990
1991         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1992         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1993         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1994         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1995
1996         gic_base_lo =
1997                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1998         gic_base_hi =
1999                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
2000
2001         WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
2002         WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
2003         WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
2004         WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
2005
2006         WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014);
2007
2008         WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
2009         WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
2010
2011         WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off,
2012                         GOYA_ASYNC_EVENT_ID_TPC0_CMDQ + tpc_id);
2013
2014         WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN);
2015
2016         WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT);
2017
2018         WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE);
2019 }
2020
2021 void goya_init_tpc_qmans(struct hl_device *hdev)
2022 {
2023         struct goya_device *goya = hdev->asic_specific;
2024         u32 so_base_lo, so_base_hi;
2025         u32 cfg_off = mmTPC1_CFG_SM_BASE_ADDRESS_LOW -
2026                         mmTPC0_CFG_SM_BASE_ADDRESS_LOW;
2027         int i;
2028
2029         if (goya->hw_cap_initialized & HW_CAP_TPC)
2030                 return;
2031
2032         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
2033         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
2034
2035         for (i = 0 ; i < TPC_MAX_NUM ; i++) {
2036                 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_LOW + i * cfg_off,
2037                                 so_base_lo);
2038                 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + i * cfg_off,
2039                                 so_base_hi);
2040         }
2041
2042         goya_init_tpc_qman(hdev, TPC0_QMAN_BASE_OFFSET, 0);
2043         goya_init_tpc_qman(hdev, TPC1_QMAN_BASE_OFFSET, 1);
2044         goya_init_tpc_qman(hdev, TPC2_QMAN_BASE_OFFSET, 2);
2045         goya_init_tpc_qman(hdev, TPC3_QMAN_BASE_OFFSET, 3);
2046         goya_init_tpc_qman(hdev, TPC4_QMAN_BASE_OFFSET, 4);
2047         goya_init_tpc_qman(hdev, TPC5_QMAN_BASE_OFFSET, 5);
2048         goya_init_tpc_qman(hdev, TPC6_QMAN_BASE_OFFSET, 6);
2049         goya_init_tpc_qman(hdev, TPC7_QMAN_BASE_OFFSET, 7);
2050
2051         for (i = 0 ; i < TPC_MAX_NUM ; i++)
2052                 goya_init_tpc_cmdq(hdev, i);
2053
2054         goya->hw_cap_initialized |= HW_CAP_TPC;
2055 }
2056
2057 /*
2058  * goya_disable_internal_queues - Disable internal queues
2059  *
2060  * @hdev: pointer to hl_device structure
2061  *
2062  */
2063 static void goya_disable_internal_queues(struct hl_device *hdev)
2064 {
2065         struct goya_device *goya = hdev->asic_specific;
2066
2067         if (!(goya->hw_cap_initialized & HW_CAP_MME))
2068                 goto disable_tpc;
2069
2070         WREG32(mmMME_QM_GLBL_CFG0, 0);
2071         WREG32(mmMME_CMDQ_GLBL_CFG0, 0);
2072
2073 disable_tpc:
2074         if (!(goya->hw_cap_initialized & HW_CAP_TPC))
2075                 return;
2076
2077         WREG32(mmTPC0_QM_GLBL_CFG0, 0);
2078         WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0);
2079
2080         WREG32(mmTPC1_QM_GLBL_CFG0, 0);
2081         WREG32(mmTPC1_CMDQ_GLBL_CFG0, 0);
2082
2083         WREG32(mmTPC2_QM_GLBL_CFG0, 0);
2084         WREG32(mmTPC2_CMDQ_GLBL_CFG0, 0);
2085
2086         WREG32(mmTPC3_QM_GLBL_CFG0, 0);
2087         WREG32(mmTPC3_CMDQ_GLBL_CFG0, 0);
2088
2089         WREG32(mmTPC4_QM_GLBL_CFG0, 0);
2090         WREG32(mmTPC4_CMDQ_GLBL_CFG0, 0);
2091
2092         WREG32(mmTPC5_QM_GLBL_CFG0, 0);
2093         WREG32(mmTPC5_CMDQ_GLBL_CFG0, 0);
2094
2095         WREG32(mmTPC6_QM_GLBL_CFG0, 0);
2096         WREG32(mmTPC6_CMDQ_GLBL_CFG0, 0);
2097
2098         WREG32(mmTPC7_QM_GLBL_CFG0, 0);
2099         WREG32(mmTPC7_CMDQ_GLBL_CFG0, 0);
2100 }
2101
2102 /*
2103  * goya_stop_internal_queues - Stop internal queues
2104  *
2105  * @hdev: pointer to hl_device structure
2106  *
2107  * Returns 0 on success
2108  *
2109  */
2110 static int goya_stop_internal_queues(struct hl_device *hdev)
2111 {
2112         struct goya_device *goya = hdev->asic_specific;
2113         int rc, retval = 0;
2114
2115         if (!(goya->hw_cap_initialized & HW_CAP_MME))
2116                 goto stop_tpc;
2117
2118         /*
2119          * Each queue (QMAN) is a separate H/W logic. That means that each
2120          * QMAN can be stopped independently and failure to stop one does NOT
2121          * mandate we should not try to stop other QMANs
2122          */
2123
2124         rc = goya_stop_queue(hdev,
2125                         mmMME_QM_GLBL_CFG1,
2126                         mmMME_QM_CP_STS,
2127                         mmMME_QM_GLBL_STS0);
2128
2129         if (rc) {
2130                 dev_err(hdev->dev, "failed to stop MME QMAN\n");
2131                 retval = -EIO;
2132         }
2133
2134         rc = goya_stop_queue(hdev,
2135                         mmMME_CMDQ_GLBL_CFG1,
2136                         mmMME_CMDQ_CP_STS,
2137                         mmMME_CMDQ_GLBL_STS0);
2138
2139         if (rc) {
2140                 dev_err(hdev->dev, "failed to stop MME CMDQ\n");
2141                 retval = -EIO;
2142         }
2143
2144 stop_tpc:
2145         if (!(goya->hw_cap_initialized & HW_CAP_TPC))
2146                 return retval;
2147
2148         rc = goya_stop_queue(hdev,
2149                         mmTPC0_QM_GLBL_CFG1,
2150                         mmTPC0_QM_CP_STS,
2151                         mmTPC0_QM_GLBL_STS0);
2152
2153         if (rc) {
2154                 dev_err(hdev->dev, "failed to stop TPC 0 QMAN\n");
2155                 retval = -EIO;
2156         }
2157
2158         rc = goya_stop_queue(hdev,
2159                         mmTPC0_CMDQ_GLBL_CFG1,
2160                         mmTPC0_CMDQ_CP_STS,
2161                         mmTPC0_CMDQ_GLBL_STS0);
2162
2163         if (rc) {
2164                 dev_err(hdev->dev, "failed to stop TPC 0 CMDQ\n");
2165                 retval = -EIO;
2166         }
2167
2168         rc = goya_stop_queue(hdev,
2169                         mmTPC1_QM_GLBL_CFG1,
2170                         mmTPC1_QM_CP_STS,
2171                         mmTPC1_QM_GLBL_STS0);
2172
2173         if (rc) {
2174                 dev_err(hdev->dev, "failed to stop TPC 1 QMAN\n");
2175                 retval = -EIO;
2176         }
2177
2178         rc = goya_stop_queue(hdev,
2179                         mmTPC1_CMDQ_GLBL_CFG1,
2180                         mmTPC1_CMDQ_CP_STS,
2181                         mmTPC1_CMDQ_GLBL_STS0);
2182
2183         if (rc) {
2184                 dev_err(hdev->dev, "failed to stop TPC 1 CMDQ\n");
2185                 retval = -EIO;
2186         }
2187
2188         rc = goya_stop_queue(hdev,
2189                         mmTPC2_QM_GLBL_CFG1,
2190                         mmTPC2_QM_CP_STS,
2191                         mmTPC2_QM_GLBL_STS0);
2192
2193         if (rc) {
2194                 dev_err(hdev->dev, "failed to stop TPC 2 QMAN\n");
2195                 retval = -EIO;
2196         }
2197
2198         rc = goya_stop_queue(hdev,
2199                         mmTPC2_CMDQ_GLBL_CFG1,
2200                         mmTPC2_CMDQ_CP_STS,
2201                         mmTPC2_CMDQ_GLBL_STS0);
2202
2203         if (rc) {
2204                 dev_err(hdev->dev, "failed to stop TPC 2 CMDQ\n");
2205                 retval = -EIO;
2206         }
2207
2208         rc = goya_stop_queue(hdev,
2209                         mmTPC3_QM_GLBL_CFG1,
2210                         mmTPC3_QM_CP_STS,
2211                         mmTPC3_QM_GLBL_STS0);
2212
2213         if (rc) {
2214                 dev_err(hdev->dev, "failed to stop TPC 3 QMAN\n");
2215                 retval = -EIO;
2216         }
2217
2218         rc = goya_stop_queue(hdev,
2219                         mmTPC3_CMDQ_GLBL_CFG1,
2220                         mmTPC3_CMDQ_CP_STS,
2221                         mmTPC3_CMDQ_GLBL_STS0);
2222
2223         if (rc) {
2224                 dev_err(hdev->dev, "failed to stop TPC 3 CMDQ\n");
2225                 retval = -EIO;
2226         }
2227
2228         rc = goya_stop_queue(hdev,
2229                         mmTPC4_QM_GLBL_CFG1,
2230                         mmTPC4_QM_CP_STS,
2231                         mmTPC4_QM_GLBL_STS0);
2232
2233         if (rc) {
2234                 dev_err(hdev->dev, "failed to stop TPC 4 QMAN\n");
2235                 retval = -EIO;
2236         }
2237
2238         rc = goya_stop_queue(hdev,
2239                         mmTPC4_CMDQ_GLBL_CFG1,
2240                         mmTPC4_CMDQ_CP_STS,
2241                         mmTPC4_CMDQ_GLBL_STS0);
2242
2243         if (rc) {
2244                 dev_err(hdev->dev, "failed to stop TPC 4 CMDQ\n");
2245                 retval = -EIO;
2246         }
2247
2248         rc = goya_stop_queue(hdev,
2249                         mmTPC5_QM_GLBL_CFG1,
2250                         mmTPC5_QM_CP_STS,
2251                         mmTPC5_QM_GLBL_STS0);
2252
2253         if (rc) {
2254                 dev_err(hdev->dev, "failed to stop TPC 5 QMAN\n");
2255                 retval = -EIO;
2256         }
2257
2258         rc = goya_stop_queue(hdev,
2259                         mmTPC5_CMDQ_GLBL_CFG1,
2260                         mmTPC5_CMDQ_CP_STS,
2261                         mmTPC5_CMDQ_GLBL_STS0);
2262
2263         if (rc) {
2264                 dev_err(hdev->dev, "failed to stop TPC 5 CMDQ\n");
2265                 retval = -EIO;
2266         }
2267
2268         rc = goya_stop_queue(hdev,
2269                         mmTPC6_QM_GLBL_CFG1,
2270                         mmTPC6_QM_CP_STS,
2271                         mmTPC6_QM_GLBL_STS0);
2272
2273         if (rc) {
2274                 dev_err(hdev->dev, "failed to stop TPC 6 QMAN\n");
2275                 retval = -EIO;
2276         }
2277
2278         rc = goya_stop_queue(hdev,
2279                         mmTPC6_CMDQ_GLBL_CFG1,
2280                         mmTPC6_CMDQ_CP_STS,
2281                         mmTPC6_CMDQ_GLBL_STS0);
2282
2283         if (rc) {
2284                 dev_err(hdev->dev, "failed to stop TPC 6 CMDQ\n");
2285                 retval = -EIO;
2286         }
2287
2288         rc = goya_stop_queue(hdev,
2289                         mmTPC7_QM_GLBL_CFG1,
2290                         mmTPC7_QM_CP_STS,
2291                         mmTPC7_QM_GLBL_STS0);
2292
2293         if (rc) {
2294                 dev_err(hdev->dev, "failed to stop TPC 7 QMAN\n");
2295                 retval = -EIO;
2296         }
2297
2298         rc = goya_stop_queue(hdev,
2299                         mmTPC7_CMDQ_GLBL_CFG1,
2300                         mmTPC7_CMDQ_CP_STS,
2301                         mmTPC7_CMDQ_GLBL_STS0);
2302
2303         if (rc) {
2304                 dev_err(hdev->dev, "failed to stop TPC 7 CMDQ\n");
2305                 retval = -EIO;
2306         }
2307
2308         return retval;
2309 }
2310
2311 static void goya_dma_stall(struct hl_device *hdev)
2312 {
2313         struct goya_device *goya = hdev->asic_specific;
2314
2315         if (!(goya->hw_cap_initialized & HW_CAP_DMA))
2316                 return;
2317
2318         WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT);
2319         WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT);
2320         WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT);
2321         WREG32(mmDMA_QM_3_GLBL_CFG1, 1 << DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT);
2322         WREG32(mmDMA_QM_4_GLBL_CFG1, 1 << DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT);
2323 }
2324
2325 static void goya_tpc_stall(struct hl_device *hdev)
2326 {
2327         struct goya_device *goya = hdev->asic_specific;
2328
2329         if (!(goya->hw_cap_initialized & HW_CAP_TPC))
2330                 return;
2331
2332         WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2333         WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT);
2334         WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT);
2335         WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC3_CFG_TPC_STALL_V_SHIFT);
2336         WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC4_CFG_TPC_STALL_V_SHIFT);
2337         WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC5_CFG_TPC_STALL_V_SHIFT);
2338         WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC6_CFG_TPC_STALL_V_SHIFT);
2339         WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC7_CFG_TPC_STALL_V_SHIFT);
2340 }
2341
2342 static void goya_mme_stall(struct hl_device *hdev)
2343 {
2344         struct goya_device *goya = hdev->asic_specific;
2345
2346         if (!(goya->hw_cap_initialized & HW_CAP_MME))
2347                 return;
2348
2349         WREG32(mmMME_STALL, 0xFFFFFFFF);
2350 }
2351
2352 static int goya_enable_msix(struct hl_device *hdev)
2353 {
2354         struct goya_device *goya = hdev->asic_specific;
2355         int cq_cnt = hdev->asic_prop.completion_queues_count;
2356         int rc, i, irq_cnt_init, irq;
2357
2358         if (goya->hw_cap_initialized & HW_CAP_MSIX)
2359                 return 0;
2360
2361         rc = pci_alloc_irq_vectors(hdev->pdev, GOYA_MSIX_ENTRIES,
2362                                 GOYA_MSIX_ENTRIES, PCI_IRQ_MSIX);
2363         if (rc < 0) {
2364                 dev_err(hdev->dev,
2365                         "MSI-X: Failed to enable support -- %d/%d\n",
2366                         GOYA_MSIX_ENTRIES, rc);
2367                 return rc;
2368         }
2369
2370         for (i = 0, irq_cnt_init = 0 ; i < cq_cnt ; i++, irq_cnt_init++) {
2371                 irq = pci_irq_vector(hdev->pdev, i);
2372                 rc = request_irq(irq, hl_irq_handler_cq, 0, goya_irq_name[i],
2373                                 &hdev->completion_queue[i]);
2374                 if (rc) {
2375                         dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2376                         goto free_irqs;
2377                 }
2378         }
2379
2380         irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2381
2382         rc = request_irq(irq, hl_irq_handler_eq, 0,
2383                         goya_irq_name[GOYA_EVENT_QUEUE_MSIX_IDX],
2384                         &hdev->event_queue);
2385         if (rc) {
2386                 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2387                 goto free_irqs;
2388         }
2389
2390         goya->hw_cap_initialized |= HW_CAP_MSIX;
2391         return 0;
2392
2393 free_irqs:
2394         for (i = 0 ; i < irq_cnt_init ; i++)
2395                 free_irq(pci_irq_vector(hdev->pdev, i),
2396                         &hdev->completion_queue[i]);
2397
2398         pci_free_irq_vectors(hdev->pdev);
2399         return rc;
2400 }
2401
2402 static void goya_sync_irqs(struct hl_device *hdev)
2403 {
2404         struct goya_device *goya = hdev->asic_specific;
2405         int i;
2406
2407         if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2408                 return;
2409
2410         /* Wait for all pending IRQs to be finished */
2411         for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
2412                 synchronize_irq(pci_irq_vector(hdev->pdev, i));
2413
2414         synchronize_irq(pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX));
2415 }
2416
2417 static void goya_disable_msix(struct hl_device *hdev)
2418 {
2419         struct goya_device *goya = hdev->asic_specific;
2420         int i, irq;
2421
2422         if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2423                 return;
2424
2425         goya_sync_irqs(hdev);
2426
2427         irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2428         free_irq(irq, &hdev->event_queue);
2429
2430         for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) {
2431                 irq = pci_irq_vector(hdev->pdev, i);
2432                 free_irq(irq, &hdev->completion_queue[i]);
2433         }
2434
2435         pci_free_irq_vectors(hdev->pdev);
2436
2437         goya->hw_cap_initialized &= ~HW_CAP_MSIX;
2438 }
2439
2440 static void goya_enable_timestamp(struct hl_device *hdev)
2441 {
2442         /* Disable the timestamp counter */
2443         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2444
2445         /* Zero the lower/upper parts of the 64-bit counter */
2446         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0);
2447         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0);
2448
2449         /* Enable the counter */
2450         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1);
2451 }
2452
2453 static void goya_disable_timestamp(struct hl_device *hdev)
2454 {
2455         /* Disable the timestamp counter */
2456         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2457 }
2458
2459 static void goya_halt_engines(struct hl_device *hdev, bool hard_reset, bool fw_reset)
2460 {
2461         u32 wait_timeout_ms;
2462
2463         if (hdev->pldm)
2464                 wait_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2465         else
2466                 wait_timeout_ms = GOYA_RESET_WAIT_MSEC;
2467
2468         goya_stop_external_queues(hdev);
2469         goya_stop_internal_queues(hdev);
2470
2471         msleep(wait_timeout_ms);
2472
2473         goya_dma_stall(hdev);
2474         goya_tpc_stall(hdev);
2475         goya_mme_stall(hdev);
2476
2477         msleep(wait_timeout_ms);
2478
2479         goya_disable_external_queues(hdev);
2480         goya_disable_internal_queues(hdev);
2481
2482         goya_disable_timestamp(hdev);
2483
2484         if (hard_reset) {
2485                 goya_disable_msix(hdev);
2486                 goya_mmu_remove_device_cpu_mappings(hdev);
2487         } else {
2488                 goya_sync_irqs(hdev);
2489         }
2490 }
2491
2492 /*
2493  * goya_load_firmware_to_device() - Load LINUX FW code to device.
2494  * @hdev: Pointer to hl_device structure.
2495  *
2496  * Copy LINUX fw code from firmware file to HBM BAR.
2497  *
2498  * Return: 0 on success, non-zero for failure.
2499  */
2500 static int goya_load_firmware_to_device(struct hl_device *hdev)
2501 {
2502         void __iomem *dst;
2503
2504         dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET;
2505
2506         return hl_fw_load_fw_to_device(hdev, GOYA_LINUX_FW_FILE, dst, 0, 0);
2507 }
2508
2509 /*
2510  * goya_load_boot_fit_to_device() - Load boot fit to device.
2511  * @hdev: Pointer to hl_device structure.
2512  *
2513  * Copy boot fit file to SRAM BAR.
2514  *
2515  * Return: 0 on success, non-zero for failure.
2516  */
2517 static int goya_load_boot_fit_to_device(struct hl_device *hdev)
2518 {
2519         void __iomem *dst;
2520
2521         dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + BOOT_FIT_SRAM_OFFSET;
2522
2523         return hl_fw_load_fw_to_device(hdev, GOYA_BOOT_FIT_FILE, dst, 0, 0);
2524 }
2525
2526 static void goya_init_dynamic_firmware_loader(struct hl_device *hdev)
2527 {
2528         struct dynamic_fw_load_mgr *dynamic_loader;
2529         struct cpu_dyn_regs *dyn_regs;
2530
2531         dynamic_loader = &hdev->fw_loader.dynamic_loader;
2532
2533         /*
2534          * here we update initial values for few specific dynamic regs (as
2535          * before reading the first descriptor from FW those value has to be
2536          * hard-coded) in later stages of the protocol those values will be
2537          * updated automatically by reading the FW descriptor so data there
2538          * will always be up-to-date
2539          */
2540         dyn_regs = &dynamic_loader->comm_desc.cpu_dyn_regs;
2541         dyn_regs->kmd_msg_to_cpu =
2542                                 cpu_to_le32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU);
2543         dyn_regs->cpu_cmd_status_to_host =
2544                                 cpu_to_le32(mmCPU_CMD_STATUS_TO_HOST);
2545
2546         dynamic_loader->wait_for_bl_timeout = GOYA_WAIT_FOR_BL_TIMEOUT_USEC;
2547 }
2548
2549 static void goya_init_static_firmware_loader(struct hl_device *hdev)
2550 {
2551         struct static_fw_load_mgr *static_loader;
2552
2553         static_loader = &hdev->fw_loader.static_loader;
2554
2555         static_loader->preboot_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
2556         static_loader->boot_fit_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
2557         static_loader->kmd_msg_to_cpu_reg = mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU;
2558         static_loader->cpu_cmd_status_to_host_reg = mmCPU_CMD_STATUS_TO_HOST;
2559         static_loader->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS;
2560         static_loader->cpu_boot_dev_status0_reg = mmCPU_BOOT_DEV_STS0;
2561         static_loader->cpu_boot_dev_status1_reg = mmCPU_BOOT_DEV_STS1;
2562         static_loader->boot_err0_reg = mmCPU_BOOT_ERR0;
2563         static_loader->boot_err1_reg = mmCPU_BOOT_ERR1;
2564         static_loader->preboot_version_offset_reg = mmPREBOOT_VER_OFFSET;
2565         static_loader->boot_fit_version_offset_reg = mmUBOOT_VER_OFFSET;
2566         static_loader->sram_offset_mask = ~(lower_32_bits(SRAM_BASE_ADDR));
2567 }
2568
2569 static void goya_init_firmware_preload_params(struct hl_device *hdev)
2570 {
2571         struct pre_fw_load_props *pre_fw_load = &hdev->fw_loader.pre_fw_load;
2572
2573         pre_fw_load->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS;
2574         pre_fw_load->sts_boot_dev_sts0_reg = mmCPU_BOOT_DEV_STS0;
2575         pre_fw_load->sts_boot_dev_sts1_reg = mmCPU_BOOT_DEV_STS1;
2576         pre_fw_load->boot_err0_reg = mmCPU_BOOT_ERR0;
2577         pre_fw_load->boot_err1_reg = mmCPU_BOOT_ERR1;
2578         pre_fw_load->wait_for_preboot_timeout = GOYA_BOOT_FIT_REQ_TIMEOUT_USEC;
2579 }
2580
2581 static void goya_init_firmware_loader(struct hl_device *hdev)
2582 {
2583         struct asic_fixed_properties *prop = &hdev->asic_prop;
2584         struct fw_load_mgr *fw_loader = &hdev->fw_loader;
2585
2586         /* fill common fields */
2587         fw_loader->fw_comp_loaded = FW_TYPE_NONE;
2588         fw_loader->boot_fit_img.image_name = GOYA_BOOT_FIT_FILE;
2589         fw_loader->linux_img.image_name = GOYA_LINUX_FW_FILE;
2590         fw_loader->cpu_timeout = GOYA_CPU_TIMEOUT_USEC;
2591         fw_loader->boot_fit_timeout = GOYA_BOOT_FIT_REQ_TIMEOUT_USEC;
2592         fw_loader->skip_bmc = false;
2593         fw_loader->sram_bar_id = SRAM_CFG_BAR_ID;
2594         fw_loader->dram_bar_id = DDR_BAR_ID;
2595
2596         if (prop->dynamic_fw_load)
2597                 goya_init_dynamic_firmware_loader(hdev);
2598         else
2599                 goya_init_static_firmware_loader(hdev);
2600 }
2601
2602 static int goya_init_cpu(struct hl_device *hdev)
2603 {
2604         struct goya_device *goya = hdev->asic_specific;
2605         int rc;
2606
2607         if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU))
2608                 return 0;
2609
2610         if (goya->hw_cap_initialized & HW_CAP_CPU)
2611                 return 0;
2612
2613         /*
2614          * Before pushing u-boot/linux to device, need to set the ddr bar to
2615          * base address of dram
2616          */
2617         if (goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) {
2618                 dev_err(hdev->dev,
2619                         "failed to map DDR bar to DRAM base address\n");
2620                 return -EIO;
2621         }
2622
2623         rc = hl_fw_init_cpu(hdev);
2624
2625         if (rc)
2626                 return rc;
2627
2628         goya->hw_cap_initialized |= HW_CAP_CPU;
2629
2630         return 0;
2631 }
2632
2633 static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
2634                                                 u64 phys_addr)
2635 {
2636         u32 status, timeout_usec;
2637         int rc;
2638
2639         if (hdev->pldm)
2640                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
2641         else
2642                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
2643
2644         WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
2645         WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
2646         WREG32(MMU_ASID_BUSY, 0x80000000 | asid);
2647
2648         rc = hl_poll_timeout(
2649                 hdev,
2650                 MMU_ASID_BUSY,
2651                 status,
2652                 !(status & 0x80000000),
2653                 1000,
2654                 timeout_usec);
2655
2656         if (rc) {
2657                 dev_err(hdev->dev,
2658                         "Timeout during MMU hop0 config of asid %d\n", asid);
2659                 return rc;
2660         }
2661
2662         return 0;
2663 }
2664
2665 int goya_mmu_init(struct hl_device *hdev)
2666 {
2667         struct asic_fixed_properties *prop = &hdev->asic_prop;
2668         struct goya_device *goya = hdev->asic_specific;
2669         u64 hop0_addr;
2670         int rc, i;
2671
2672         if (goya->hw_cap_initialized & HW_CAP_MMU)
2673                 return 0;
2674
2675         hdev->dram_default_page_mapping = true;
2676
2677         for (i = 0 ; i < prop->max_asid ; i++) {
2678                 hop0_addr = prop->mmu_pgt_addr +
2679                                 (i * prop->dmmu.hop_table_size);
2680
2681                 rc = goya_mmu_update_asid_hop0_addr(hdev, i, hop0_addr);
2682                 if (rc) {
2683                         dev_err(hdev->dev,
2684                                 "failed to set hop0 addr for asid %d\n", i);
2685                         goto err;
2686                 }
2687         }
2688
2689         goya->hw_cap_initialized |= HW_CAP_MMU;
2690
2691         /* init MMU cache manage page */
2692         WREG32(mmSTLB_CACHE_INV_BASE_39_8,
2693                                 lower_32_bits(MMU_CACHE_MNG_ADDR >> 8));
2694         WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40);
2695
2696         /* Remove follower feature due to performance bug */
2697         WREG32_AND(mmSTLB_STLB_FEATURE_EN,
2698                         (~STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK));
2699
2700         hl_mmu_invalidate_cache(hdev, true, MMU_OP_USERPTR | MMU_OP_PHYS_PACK);
2701
2702         WREG32(mmMMU_MMU_ENABLE, 1);
2703         WREG32(mmMMU_SPI_MASK, 0xF);
2704
2705         return 0;
2706
2707 err:
2708         return rc;
2709 }
2710
2711 /*
2712  * goya_hw_init - Goya hardware initialization code
2713  *
2714  * @hdev: pointer to hl_device structure
2715  *
2716  * Returns 0 on success
2717  *
2718  */
2719 static int goya_hw_init(struct hl_device *hdev)
2720 {
2721         struct asic_fixed_properties *prop = &hdev->asic_prop;
2722         int rc;
2723
2724         /* Perform read from the device to make sure device is up */
2725         RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2726
2727         /*
2728          * Let's mark in the H/W that we have reached this point. We check
2729          * this value in the reset_before_init function to understand whether
2730          * we need to reset the chip before doing H/W init. This register is
2731          * cleared by the H/W upon H/W reset
2732          */
2733         WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY);
2734
2735         rc = goya_init_cpu(hdev);
2736         if (rc) {
2737                 dev_err(hdev->dev, "failed to initialize CPU\n");
2738                 return rc;
2739         }
2740
2741         goya_tpc_mbist_workaround(hdev);
2742
2743         goya_init_golden_registers(hdev);
2744
2745         /*
2746          * After CPU initialization is finished, change DDR bar mapping inside
2747          * iATU to point to the start address of the MMU page tables
2748          */
2749         if (goya_set_ddr_bar_base(hdev, (MMU_PAGE_TABLES_ADDR &
2750                         ~(prop->dram_pci_bar_size - 0x1ull))) == U64_MAX) {
2751                 dev_err(hdev->dev,
2752                         "failed to map DDR bar to MMU page tables\n");
2753                 return -EIO;
2754         }
2755
2756         rc = goya_mmu_init(hdev);
2757         if (rc)
2758                 return rc;
2759
2760         goya_init_security(hdev);
2761
2762         goya_init_dma_qmans(hdev);
2763
2764         goya_init_mme_qmans(hdev);
2765
2766         goya_init_tpc_qmans(hdev);
2767
2768         goya_enable_timestamp(hdev);
2769
2770         /* MSI-X must be enabled before CPU queues are initialized */
2771         rc = goya_enable_msix(hdev);
2772         if (rc)
2773                 goto disable_queues;
2774
2775         /* Perform read from the device to flush all MSI-X configuration */
2776         RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2777
2778         return 0;
2779
2780 disable_queues:
2781         goya_disable_internal_queues(hdev);
2782         goya_disable_external_queues(hdev);
2783
2784         return rc;
2785 }
2786
2787 static int goya_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset)
2788 {
2789         struct goya_device *goya = hdev->asic_specific;
2790         u32 reset_timeout_ms, cpu_timeout_ms, status;
2791
2792         if (hdev->pldm) {
2793                 reset_timeout_ms = GOYA_PLDM_RESET_TIMEOUT_MSEC;
2794                 cpu_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2795         } else {
2796                 reset_timeout_ms = GOYA_RESET_TIMEOUT_MSEC;
2797                 cpu_timeout_ms = GOYA_CPU_RESET_WAIT_MSEC;
2798         }
2799
2800         if (hard_reset) {
2801                 /* I don't know what is the state of the CPU so make sure it is
2802                  * stopped in any means necessary
2803                  */
2804                 WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE);
2805                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2806                         GOYA_ASYNC_EVENT_ID_HALT_MACHINE);
2807
2808                 msleep(cpu_timeout_ms);
2809
2810                 goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
2811                 goya_disable_clk_rlx(hdev);
2812                 goya_set_pll_refclk(hdev);
2813
2814                 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, RESET_ALL);
2815                 dev_dbg(hdev->dev,
2816                         "Issued HARD reset command, going to wait %dms\n",
2817                         reset_timeout_ms);
2818         } else {
2819                 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, DMA_MME_TPC_RESET);
2820                 dev_dbg(hdev->dev,
2821                         "Issued SOFT reset command, going to wait %dms\n",
2822                         reset_timeout_ms);
2823         }
2824
2825         /*
2826          * After hard reset, we can't poll the BTM_FSM register because the PSOC
2827          * itself is in reset. In either reset we need to wait until the reset
2828          * is deasserted
2829          */
2830         msleep(reset_timeout_ms);
2831
2832         status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM);
2833         if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK) {
2834                 dev_err(hdev->dev, "Timeout while waiting for device to reset 0x%x\n", status);
2835                 return -ETIMEDOUT;
2836         }
2837
2838         if (!hard_reset && goya) {
2839                 goya->hw_cap_initialized &= ~(HW_CAP_DMA | HW_CAP_MME |
2840                                                 HW_CAP_GOLDEN | HW_CAP_TPC);
2841                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2842                                 GOYA_ASYNC_EVENT_ID_SOFT_RESET);
2843                 return 0;
2844         }
2845
2846         /* Chicken bit to re-initiate boot sequencer flow */
2847         WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START,
2848                 1 << PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT);
2849         /* Move boot manager FSM to pre boot sequencer init state */
2850         WREG32(mmPSOC_GLOBAL_CONF_SW_BTM_FSM,
2851                         0xA << PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT);
2852
2853         if (goya) {
2854                 goya->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q |
2855                                 HW_CAP_DDR_0 | HW_CAP_DDR_1 |
2856                                 HW_CAP_DMA | HW_CAP_MME |
2857                                 HW_CAP_MMU | HW_CAP_TPC_MBIST |
2858                                 HW_CAP_GOLDEN | HW_CAP_TPC);
2859
2860                 memset(goya->events_stat, 0, sizeof(goya->events_stat));
2861         }
2862         return 0;
2863 }
2864
2865 int goya_suspend(struct hl_device *hdev)
2866 {
2867         int rc;
2868
2869         rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0);
2870         if (rc)
2871                 dev_err(hdev->dev, "Failed to disable PCI access from CPU\n");
2872
2873         return rc;
2874 }
2875
2876 int goya_resume(struct hl_device *hdev)
2877 {
2878         return goya_init_iatu(hdev);
2879 }
2880
2881 static int goya_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
2882                         void *cpu_addr, dma_addr_t dma_addr, size_t size)
2883 {
2884         int rc;
2885
2886         vm_flags_set(vma, VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
2887                         VM_DONTCOPY | VM_NORESERVE);
2888
2889         rc = dma_mmap_coherent(hdev->dev, vma, cpu_addr,
2890                                 (dma_addr - HOST_PHYS_BASE), size);
2891         if (rc)
2892                 dev_err(hdev->dev, "dma_mmap_coherent error %d", rc);
2893
2894         return rc;
2895 }
2896
2897 void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi)
2898 {
2899         u32 db_reg_offset, db_value;
2900
2901         switch (hw_queue_id) {
2902         case GOYA_QUEUE_ID_DMA_0:
2903                 db_reg_offset = mmDMA_QM_0_PQ_PI;
2904                 break;
2905
2906         case GOYA_QUEUE_ID_DMA_1:
2907                 db_reg_offset = mmDMA_QM_1_PQ_PI;
2908                 break;
2909
2910         case GOYA_QUEUE_ID_DMA_2:
2911                 db_reg_offset = mmDMA_QM_2_PQ_PI;
2912                 break;
2913
2914         case GOYA_QUEUE_ID_DMA_3:
2915                 db_reg_offset = mmDMA_QM_3_PQ_PI;
2916                 break;
2917
2918         case GOYA_QUEUE_ID_DMA_4:
2919                 db_reg_offset = mmDMA_QM_4_PQ_PI;
2920                 break;
2921
2922         case GOYA_QUEUE_ID_CPU_PQ:
2923                 db_reg_offset = mmCPU_IF_PF_PQ_PI;
2924                 break;
2925
2926         case GOYA_QUEUE_ID_MME:
2927                 db_reg_offset = mmMME_QM_PQ_PI;
2928                 break;
2929
2930         case GOYA_QUEUE_ID_TPC0:
2931                 db_reg_offset = mmTPC0_QM_PQ_PI;
2932                 break;
2933
2934         case GOYA_QUEUE_ID_TPC1:
2935                 db_reg_offset = mmTPC1_QM_PQ_PI;
2936                 break;
2937
2938         case GOYA_QUEUE_ID_TPC2:
2939                 db_reg_offset = mmTPC2_QM_PQ_PI;
2940                 break;
2941
2942         case GOYA_QUEUE_ID_TPC3:
2943                 db_reg_offset = mmTPC3_QM_PQ_PI;
2944                 break;
2945
2946         case GOYA_QUEUE_ID_TPC4:
2947                 db_reg_offset = mmTPC4_QM_PQ_PI;
2948                 break;
2949
2950         case GOYA_QUEUE_ID_TPC5:
2951                 db_reg_offset = mmTPC5_QM_PQ_PI;
2952                 break;
2953
2954         case GOYA_QUEUE_ID_TPC6:
2955                 db_reg_offset = mmTPC6_QM_PQ_PI;
2956                 break;
2957
2958         case GOYA_QUEUE_ID_TPC7:
2959                 db_reg_offset = mmTPC7_QM_PQ_PI;
2960                 break;
2961
2962         default:
2963                 /* Should never get here */
2964                 dev_err(hdev->dev, "H/W queue %d is invalid. Can't set pi\n",
2965                         hw_queue_id);
2966                 return;
2967         }
2968
2969         db_value = pi;
2970
2971         /* ring the doorbell */
2972         WREG32(db_reg_offset, db_value);
2973
2974         if (hw_queue_id == GOYA_QUEUE_ID_CPU_PQ) {
2975                 /* make sure device CPU will read latest data from host */
2976                 mb();
2977                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2978                                 GOYA_ASYNC_EVENT_ID_PI_UPDATE);
2979         }
2980 }
2981
2982 void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd)
2983 {
2984         /* The QMANs are on the SRAM so need to copy to IO space */
2985         memcpy_toio((void __iomem *) pqe, bd, sizeof(struct hl_bd));
2986 }
2987
2988 static void *goya_dma_alloc_coherent(struct hl_device *hdev, size_t size,
2989                                         dma_addr_t *dma_handle, gfp_t flags)
2990 {
2991         void *kernel_addr = dma_alloc_coherent(&hdev->pdev->dev, size,
2992                                                 dma_handle, flags);
2993
2994         /* Shift to the device's base physical address of host memory */
2995         if (kernel_addr)
2996                 *dma_handle += HOST_PHYS_BASE;
2997
2998         return kernel_addr;
2999 }
3000
3001 static void goya_dma_free_coherent(struct hl_device *hdev, size_t size,
3002                                         void *cpu_addr, dma_addr_t dma_handle)
3003 {
3004         /* Cancel the device's base physical address of host memory */
3005         dma_addr_t fixed_dma_handle = dma_handle - HOST_PHYS_BASE;
3006
3007         dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle);
3008 }
3009
3010 int goya_scrub_device_mem(struct hl_device *hdev)
3011 {
3012         return 0;
3013 }
3014
3015 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
3016                                 dma_addr_t *dma_handle, u16 *queue_len)
3017 {
3018         void *base;
3019         u32 offset;
3020
3021         *dma_handle = hdev->asic_prop.sram_base_address;
3022
3023         base = (__force void *) hdev->pcie_bar[SRAM_CFG_BAR_ID];
3024
3025         switch (queue_id) {
3026         case GOYA_QUEUE_ID_MME:
3027                 offset = MME_QMAN_BASE_OFFSET;
3028                 *queue_len = MME_QMAN_LENGTH;
3029                 break;
3030         case GOYA_QUEUE_ID_TPC0:
3031                 offset = TPC0_QMAN_BASE_OFFSET;
3032                 *queue_len = TPC_QMAN_LENGTH;
3033                 break;
3034         case GOYA_QUEUE_ID_TPC1:
3035                 offset = TPC1_QMAN_BASE_OFFSET;
3036                 *queue_len = TPC_QMAN_LENGTH;
3037                 break;
3038         case GOYA_QUEUE_ID_TPC2:
3039                 offset = TPC2_QMAN_BASE_OFFSET;
3040                 *queue_len = TPC_QMAN_LENGTH;
3041                 break;
3042         case GOYA_QUEUE_ID_TPC3:
3043                 offset = TPC3_QMAN_BASE_OFFSET;
3044                 *queue_len = TPC_QMAN_LENGTH;
3045                 break;
3046         case GOYA_QUEUE_ID_TPC4:
3047                 offset = TPC4_QMAN_BASE_OFFSET;
3048                 *queue_len = TPC_QMAN_LENGTH;
3049                 break;
3050         case GOYA_QUEUE_ID_TPC5:
3051                 offset = TPC5_QMAN_BASE_OFFSET;
3052                 *queue_len = TPC_QMAN_LENGTH;
3053                 break;
3054         case GOYA_QUEUE_ID_TPC6:
3055                 offset = TPC6_QMAN_BASE_OFFSET;
3056                 *queue_len = TPC_QMAN_LENGTH;
3057                 break;
3058         case GOYA_QUEUE_ID_TPC7:
3059                 offset = TPC7_QMAN_BASE_OFFSET;
3060                 *queue_len = TPC_QMAN_LENGTH;
3061                 break;
3062         default:
3063                 dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id);
3064                 return NULL;
3065         }
3066
3067         base += offset;
3068         *dma_handle += offset;
3069
3070         return base;
3071 }
3072
3073 static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
3074 {
3075         struct packet_msg_prot *fence_pkt;
3076         u32 *fence_ptr;
3077         dma_addr_t fence_dma_addr;
3078         struct hl_cb *cb;
3079         u32 tmp, timeout;
3080         int rc;
3081
3082         if (hdev->pldm)
3083                 timeout = GOYA_PLDM_QMAN0_TIMEOUT_USEC;
3084         else
3085                 timeout = HL_DEVICE_TIMEOUT_USEC;
3086
3087         if (!hdev->asic_funcs->is_device_idle(hdev, NULL, 0, NULL)) {
3088                 dev_err_ratelimited(hdev->dev,
3089                         "Can't send driver job on QMAN0 because the device is not idle\n");
3090                 return -EBUSY;
3091         }
3092
3093         fence_ptr = hl_asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, &fence_dma_addr);
3094         if (!fence_ptr) {
3095                 dev_err(hdev->dev,
3096                         "Failed to allocate fence memory for QMAN0\n");
3097                 return -ENOMEM;
3098         }
3099
3100         goya_qman0_set_security(hdev, true);
3101
3102         cb = job->patched_cb;
3103
3104         fence_pkt = cb->kernel_address +
3105                         job->job_cb_size - sizeof(struct packet_msg_prot);
3106
3107         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3108                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
3109                         (1 << GOYA_PKT_CTL_MB_SHIFT);
3110         fence_pkt->ctl = cpu_to_le32(tmp);
3111         fence_pkt->value = cpu_to_le32(GOYA_QMAN0_FENCE_VAL);
3112         fence_pkt->addr = cpu_to_le64(fence_dma_addr);
3113
3114         rc = hl_hw_queue_send_cb_no_cmpl(hdev, GOYA_QUEUE_ID_DMA_0,
3115                                         job->job_cb_size, cb->bus_address);
3116         if (rc) {
3117                 dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc);
3118                 goto free_fence_ptr;
3119         }
3120
3121         rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp,
3122                                 (tmp == GOYA_QMAN0_FENCE_VAL), 1000,
3123                                 timeout, true);
3124
3125         hl_hw_queue_inc_ci_kernel(hdev, GOYA_QUEUE_ID_DMA_0);
3126
3127         if (rc == -ETIMEDOUT) {
3128                 dev_err(hdev->dev, "QMAN0 Job timeout (0x%x)\n", tmp);
3129                 goto free_fence_ptr;
3130         }
3131
3132 free_fence_ptr:
3133         hl_asic_dma_pool_free(hdev, (void *) fence_ptr, fence_dma_addr);
3134
3135         goya_qman0_set_security(hdev, false);
3136
3137         return rc;
3138 }
3139
3140 int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
3141                                 u32 timeout, u64 *result)
3142 {
3143         struct goya_device *goya = hdev->asic_specific;
3144
3145         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) {
3146                 if (result)
3147                         *result = 0;
3148                 return 0;
3149         }
3150
3151         if (!timeout)
3152                 timeout = GOYA_MSG_TO_CPU_TIMEOUT_USEC;
3153
3154         return hl_fw_send_cpu_message(hdev, GOYA_QUEUE_ID_CPU_PQ, msg, len,
3155                                         timeout, result);
3156 }
3157
3158 int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
3159 {
3160         struct packet_msg_prot *fence_pkt;
3161         dma_addr_t pkt_dma_addr;
3162         u32 fence_val, tmp;
3163         dma_addr_t fence_dma_addr;
3164         u32 *fence_ptr;
3165         int rc;
3166
3167         fence_val = GOYA_QMAN0_FENCE_VAL;
3168
3169         fence_ptr = hl_asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, &fence_dma_addr);
3170         if (!fence_ptr) {
3171                 dev_err(hdev->dev,
3172                         "Failed to allocate memory for H/W queue %d testing\n",
3173                         hw_queue_id);
3174                 return -ENOMEM;
3175         }
3176
3177         *fence_ptr = 0;
3178
3179         fence_pkt = hl_asic_dma_pool_zalloc(hdev, sizeof(struct packet_msg_prot), GFP_KERNEL,
3180                                                 &pkt_dma_addr);
3181         if (!fence_pkt) {
3182                 dev_err(hdev->dev,
3183                         "Failed to allocate packet for H/W queue %d testing\n",
3184                         hw_queue_id);
3185                 rc = -ENOMEM;
3186                 goto free_fence_ptr;
3187         }
3188
3189         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3190                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
3191                         (1 << GOYA_PKT_CTL_MB_SHIFT);
3192         fence_pkt->ctl = cpu_to_le32(tmp);
3193         fence_pkt->value = cpu_to_le32(fence_val);
3194         fence_pkt->addr = cpu_to_le64(fence_dma_addr);
3195
3196         rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id,
3197                                         sizeof(struct packet_msg_prot),
3198                                         pkt_dma_addr);
3199         if (rc) {
3200                 dev_err(hdev->dev,
3201                         "Failed to send fence packet to H/W queue %d\n",
3202                         hw_queue_id);
3203                 goto free_pkt;
3204         }
3205
3206         rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp, (tmp == fence_val),
3207                                         1000, GOYA_TEST_QUEUE_WAIT_USEC, true);
3208
3209         hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id);
3210
3211         if (rc == -ETIMEDOUT) {
3212                 dev_err(hdev->dev,
3213                         "H/W queue %d test failed (scratch(0x%08llX) == 0x%08X)\n",
3214                         hw_queue_id, (unsigned long long) fence_dma_addr, tmp);
3215                 rc = -EIO;
3216         }
3217
3218 free_pkt:
3219         hl_asic_dma_pool_free(hdev, (void *) fence_pkt, pkt_dma_addr);
3220 free_fence_ptr:
3221         hl_asic_dma_pool_free(hdev, (void *) fence_ptr, fence_dma_addr);
3222         return rc;
3223 }
3224
3225 int goya_test_cpu_queue(struct hl_device *hdev)
3226 {
3227         struct goya_device *goya = hdev->asic_specific;
3228
3229         /*
3230          * check capability here as send_cpu_message() won't update the result
3231          * value if no capability
3232          */
3233         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
3234                 return 0;
3235
3236         return hl_fw_test_cpu_queue(hdev);
3237 }
3238
3239 int goya_test_queues(struct hl_device *hdev)
3240 {
3241         int i, rc, ret_val = 0;
3242
3243         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
3244                 rc = goya_test_queue(hdev, i);
3245                 if (rc)
3246                         ret_val = -EINVAL;
3247         }
3248
3249         return ret_val;
3250 }
3251
3252 static void *goya_dma_pool_zalloc(struct hl_device *hdev, size_t size,
3253                                         gfp_t mem_flags, dma_addr_t *dma_handle)
3254 {
3255         void *kernel_addr;
3256
3257         if (size > GOYA_DMA_POOL_BLK_SIZE)
3258                 return NULL;
3259
3260         kernel_addr =  dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle);
3261
3262         /* Shift to the device's base physical address of host memory */
3263         if (kernel_addr)
3264                 *dma_handle += HOST_PHYS_BASE;
3265
3266         return kernel_addr;
3267 }
3268
3269 static void goya_dma_pool_free(struct hl_device *hdev, void *vaddr,
3270                                 dma_addr_t dma_addr)
3271 {
3272         /* Cancel the device's base physical address of host memory */
3273         dma_addr_t fixed_dma_addr = dma_addr - HOST_PHYS_BASE;
3274
3275         dma_pool_free(hdev->dma_pool, vaddr, fixed_dma_addr);
3276 }
3277
3278 void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
3279                                         dma_addr_t *dma_handle)
3280 {
3281         void *vaddr;
3282
3283         vaddr = hl_fw_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle);
3284         *dma_handle = (*dma_handle) - hdev->cpu_accessible_dma_address +
3285                         VA_CPU_ACCESSIBLE_MEM_ADDR;
3286
3287         return vaddr;
3288 }
3289
3290 void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
3291                                         void *vaddr)
3292 {
3293         hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr);
3294 }
3295
3296 u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt)
3297 {
3298         struct scatterlist *sg, *sg_next_iter;
3299         u32 count, dma_desc_cnt;
3300         u64 len, len_next;
3301         dma_addr_t addr, addr_next;
3302
3303         dma_desc_cnt = 0;
3304
3305         for_each_sgtable_dma_sg(sgt, sg, count) {
3306                 len = sg_dma_len(sg);
3307                 addr = sg_dma_address(sg);
3308
3309                 if (len == 0)
3310                         break;
3311
3312                 while ((count + 1) < sgt->nents) {
3313                         sg_next_iter = sg_next(sg);
3314                         len_next = sg_dma_len(sg_next_iter);
3315                         addr_next = sg_dma_address(sg_next_iter);
3316
3317                         if (len_next == 0)
3318                                 break;
3319
3320                         if ((addr + len == addr_next) &&
3321                                 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3322                                 len += len_next;
3323                                 count++;
3324                                 sg = sg_next_iter;
3325                         } else {
3326                                 break;
3327                         }
3328                 }
3329
3330                 dma_desc_cnt++;
3331         }
3332
3333         return dma_desc_cnt * sizeof(struct packet_lin_dma);
3334 }
3335
3336 static int goya_pin_memory_before_cs(struct hl_device *hdev,
3337                                 struct hl_cs_parser *parser,
3338                                 struct packet_lin_dma *user_dma_pkt,
3339                                 u64 addr, enum dma_data_direction dir)
3340 {
3341         struct hl_userptr *userptr;
3342         int rc;
3343
3344         if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3345                         parser->job_userptr_list, &userptr))
3346                 goto already_pinned;
3347
3348         userptr = kzalloc(sizeof(*userptr), GFP_KERNEL);
3349         if (!userptr)
3350                 return -ENOMEM;
3351
3352         rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3353                                 userptr);
3354         if (rc)
3355                 goto free_userptr;
3356
3357         list_add_tail(&userptr->job_node, parser->job_userptr_list);
3358
3359         rc = hl_dma_map_sgtable(hdev, userptr->sgt, dir);
3360         if (rc) {
3361                 dev_err(hdev->dev, "failed to map sgt with DMA region\n");
3362                 goto unpin_memory;
3363         }
3364
3365         userptr->dma_mapped = true;
3366         userptr->dir = dir;
3367
3368 already_pinned:
3369         parser->patched_cb_size +=
3370                         goya_get_dma_desc_list_size(hdev, userptr->sgt);
3371
3372         return 0;
3373
3374 unpin_memory:
3375         list_del(&userptr->job_node);
3376         hl_unpin_host_memory(hdev, userptr);
3377 free_userptr:
3378         kfree(userptr);
3379         return rc;
3380 }
3381
3382 static int goya_validate_dma_pkt_host(struct hl_device *hdev,
3383                                 struct hl_cs_parser *parser,
3384                                 struct packet_lin_dma *user_dma_pkt)
3385 {
3386         u64 device_memory_addr, addr;
3387         enum dma_data_direction dir;
3388         enum hl_goya_dma_direction user_dir;
3389         bool sram_addr = true;
3390         bool skip_host_mem_pin = false;
3391         bool user_memset;
3392         u32 ctl;
3393         int rc = 0;
3394
3395         ctl = le32_to_cpu(user_dma_pkt->ctl);
3396
3397         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3398                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3399
3400         user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3401                         GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3402
3403         switch (user_dir) {
3404         case HL_DMA_HOST_TO_DRAM:
3405                 dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n");
3406                 dir = DMA_TO_DEVICE;
3407                 sram_addr = false;
3408                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3409                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3410                 if (user_memset)
3411                         skip_host_mem_pin = true;
3412                 break;
3413
3414         case HL_DMA_DRAM_TO_HOST:
3415                 dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n");
3416                 dir = DMA_FROM_DEVICE;
3417                 sram_addr = false;
3418                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3419                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3420                 break;
3421
3422         case HL_DMA_HOST_TO_SRAM:
3423                 dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n");
3424                 dir = DMA_TO_DEVICE;
3425                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3426                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3427                 if (user_memset)
3428                         skip_host_mem_pin = true;
3429                 break;
3430
3431         case HL_DMA_SRAM_TO_HOST:
3432                 dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n");
3433                 dir = DMA_FROM_DEVICE;
3434                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3435                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3436                 break;
3437         default:
3438                 dev_err(hdev->dev, "DMA direction %d is unsupported/undefined\n", user_dir);
3439                 return -EFAULT;
3440         }
3441
3442         if (sram_addr) {
3443                 if (!hl_mem_area_inside_range(device_memory_addr,
3444                                 le32_to_cpu(user_dma_pkt->tsize),
3445                                 hdev->asic_prop.sram_user_base_address,
3446                                 hdev->asic_prop.sram_end_address)) {
3447
3448                         dev_err(hdev->dev,
3449                                 "SRAM address 0x%llx + 0x%x is invalid\n",
3450                                 device_memory_addr,
3451                                 user_dma_pkt->tsize);
3452                         return -EFAULT;
3453                 }
3454         } else {
3455                 if (!hl_mem_area_inside_range(device_memory_addr,
3456                                 le32_to_cpu(user_dma_pkt->tsize),
3457                                 hdev->asic_prop.dram_user_base_address,
3458                                 hdev->asic_prop.dram_end_address)) {
3459
3460                         dev_err(hdev->dev,
3461                                 "DRAM address 0x%llx + 0x%x is invalid\n",
3462                                 device_memory_addr,
3463                                 user_dma_pkt->tsize);
3464                         return -EFAULT;
3465                 }
3466         }
3467
3468         if (skip_host_mem_pin)
3469                 parser->patched_cb_size += sizeof(*user_dma_pkt);
3470         else {
3471                 if ((dir == DMA_TO_DEVICE) &&
3472                                 (parser->hw_queue_id > GOYA_QUEUE_ID_DMA_1)) {
3473                         dev_err(hdev->dev,
3474                                 "Can't DMA from host on queue other then 1\n");
3475                         return -EFAULT;
3476                 }
3477
3478                 rc = goya_pin_memory_before_cs(hdev, parser, user_dma_pkt,
3479                                                 addr, dir);
3480         }
3481
3482         return rc;
3483 }
3484
3485 static int goya_validate_dma_pkt_no_host(struct hl_device *hdev,
3486                                 struct hl_cs_parser *parser,
3487                                 struct packet_lin_dma *user_dma_pkt)
3488 {
3489         u64 sram_memory_addr, dram_memory_addr;
3490         enum hl_goya_dma_direction user_dir;
3491         u32 ctl;
3492
3493         ctl = le32_to_cpu(user_dma_pkt->ctl);
3494         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3495                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3496
3497         if (user_dir == HL_DMA_DRAM_TO_SRAM) {
3498                 dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n");
3499                 dram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3500                 sram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3501         } else {
3502                 dev_dbg(hdev->dev, "DMA direction is SRAM --> DRAM\n");
3503                 sram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3504                 dram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3505         }
3506
3507         if (!hl_mem_area_inside_range(sram_memory_addr,
3508                                 le32_to_cpu(user_dma_pkt->tsize),
3509                                 hdev->asic_prop.sram_user_base_address,
3510                                 hdev->asic_prop.sram_end_address)) {
3511                 dev_err(hdev->dev, "SRAM address 0x%llx + 0x%x is invalid\n",
3512                         sram_memory_addr, user_dma_pkt->tsize);
3513                 return -EFAULT;
3514         }
3515
3516         if (!hl_mem_area_inside_range(dram_memory_addr,
3517                                 le32_to_cpu(user_dma_pkt->tsize),
3518                                 hdev->asic_prop.dram_user_base_address,
3519                                 hdev->asic_prop.dram_end_address)) {
3520                 dev_err(hdev->dev, "DRAM address 0x%llx + 0x%x is invalid\n",
3521                         dram_memory_addr, user_dma_pkt->tsize);
3522                 return -EFAULT;
3523         }
3524
3525         parser->patched_cb_size += sizeof(*user_dma_pkt);
3526
3527         return 0;
3528 }
3529
3530 static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev,
3531                                 struct hl_cs_parser *parser,
3532                                 struct packet_lin_dma *user_dma_pkt)
3533 {
3534         enum hl_goya_dma_direction user_dir;
3535         u32 ctl;
3536         int rc;
3537
3538         dev_dbg(hdev->dev, "DMA packet details:\n");
3539         dev_dbg(hdev->dev, "source == 0x%llx\n",
3540                 le64_to_cpu(user_dma_pkt->src_addr));
3541         dev_dbg(hdev->dev, "destination == 0x%llx\n",
3542                 le64_to_cpu(user_dma_pkt->dst_addr));
3543         dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3544
3545         ctl = le32_to_cpu(user_dma_pkt->ctl);
3546         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3547                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3548
3549         /*
3550          * Special handling for DMA with size 0. The H/W has a bug where
3551          * this can cause the QMAN DMA to get stuck, so block it here.
3552          */
3553         if (user_dma_pkt->tsize == 0) {
3554                 dev_err(hdev->dev,
3555                         "Got DMA with size 0, might reset the device\n");
3556                 return -EINVAL;
3557         }
3558
3559         if ((user_dir == HL_DMA_DRAM_TO_SRAM) || (user_dir == HL_DMA_SRAM_TO_DRAM))
3560                 rc = goya_validate_dma_pkt_no_host(hdev, parser, user_dma_pkt);
3561         else
3562                 rc = goya_validate_dma_pkt_host(hdev, parser, user_dma_pkt);
3563
3564         return rc;
3565 }
3566
3567 static int goya_validate_dma_pkt_mmu(struct hl_device *hdev,
3568                                 struct hl_cs_parser *parser,
3569                                 struct packet_lin_dma *user_dma_pkt)
3570 {
3571         dev_dbg(hdev->dev, "DMA packet details:\n");
3572         dev_dbg(hdev->dev, "source == 0x%llx\n",
3573                 le64_to_cpu(user_dma_pkt->src_addr));
3574         dev_dbg(hdev->dev, "destination == 0x%llx\n",
3575                 le64_to_cpu(user_dma_pkt->dst_addr));
3576         dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3577
3578         /*
3579          * WA for HW-23.
3580          * We can't allow user to read from Host using QMANs other than 1.
3581          * PMMU and HPMMU addresses are equal, check only one of them.
3582          */
3583         if (parser->hw_queue_id != GOYA_QUEUE_ID_DMA_1 &&
3584                 hl_mem_area_inside_range(le64_to_cpu(user_dma_pkt->src_addr),
3585                                 le32_to_cpu(user_dma_pkt->tsize),
3586                                 hdev->asic_prop.pmmu.start_addr,
3587                                 hdev->asic_prop.pmmu.end_addr)) {
3588                 dev_err(hdev->dev,
3589                         "Can't DMA from host on queue other then 1\n");
3590                 return -EFAULT;
3591         }
3592
3593         if (user_dma_pkt->tsize == 0) {
3594                 dev_err(hdev->dev,
3595                         "Got DMA with size 0, might reset the device\n");
3596                 return -EINVAL;
3597         }
3598
3599         parser->patched_cb_size += sizeof(*user_dma_pkt);
3600
3601         return 0;
3602 }
3603
3604 static int goya_validate_wreg32(struct hl_device *hdev,
3605                                 struct hl_cs_parser *parser,
3606                                 struct packet_wreg32 *wreg_pkt)
3607 {
3608         struct goya_device *goya = hdev->asic_specific;
3609         u32 sob_start_addr, sob_end_addr;
3610         u16 reg_offset;
3611
3612         reg_offset = le32_to_cpu(wreg_pkt->ctl) &
3613                         GOYA_PKT_WREG32_CTL_REG_OFFSET_MASK;
3614
3615         dev_dbg(hdev->dev, "WREG32 packet details:\n");
3616         dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset);
3617         dev_dbg(hdev->dev, "value      == 0x%x\n",
3618                 le32_to_cpu(wreg_pkt->value));
3619
3620         if (reg_offset != (mmDMA_CH_0_WR_COMP_ADDR_LO & 0x1FFF)) {
3621                 dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n",
3622                         reg_offset);
3623                 return -EPERM;
3624         }
3625
3626         /*
3627          * With MMU, DMA channels are not secured, so it doesn't matter where
3628          * the WR COMP will be written to because it will go out with
3629          * non-secured property
3630          */
3631         if (goya->hw_cap_initialized & HW_CAP_MMU)
3632                 return 0;
3633
3634         sob_start_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
3635         sob_end_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1023);
3636
3637         if ((le32_to_cpu(wreg_pkt->value) < sob_start_addr) ||
3638                         (le32_to_cpu(wreg_pkt->value) > sob_end_addr)) {
3639
3640                 dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n",
3641                         wreg_pkt->value);
3642                 return -EPERM;
3643         }
3644
3645         return 0;
3646 }
3647
3648 static int goya_validate_cb(struct hl_device *hdev,
3649                         struct hl_cs_parser *parser, bool is_mmu)
3650 {
3651         u32 cb_parsed_length = 0;
3652         int rc = 0;
3653
3654         parser->patched_cb_size = 0;
3655
3656         /* cb_user_size is more than 0 so loop will always be executed */
3657         while (cb_parsed_length < parser->user_cb_size) {
3658                 enum packet_id pkt_id;
3659                 u16 pkt_size;
3660                 struct goya_packet *user_pkt;
3661
3662                 user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
3663
3664                 pkt_id = (enum packet_id) (
3665                                 (le64_to_cpu(user_pkt->header) &
3666                                 PACKET_HEADER_PACKET_ID_MASK) >>
3667                                         PACKET_HEADER_PACKET_ID_SHIFT);
3668
3669                 if (!validate_packet_id(pkt_id)) {
3670                         dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
3671                         rc = -EINVAL;
3672                         break;
3673                 }
3674
3675                 pkt_size = goya_packet_sizes[pkt_id];
3676                 cb_parsed_length += pkt_size;
3677                 if (cb_parsed_length > parser->user_cb_size) {
3678                         dev_err(hdev->dev,
3679                                 "packet 0x%x is out of CB boundary\n", pkt_id);
3680                         rc = -EINVAL;
3681                         break;
3682                 }
3683
3684                 switch (pkt_id) {
3685                 case PACKET_WREG_32:
3686                         /*
3687                          * Although it is validated after copy in patch_cb(),
3688                          * need to validate here as well because patch_cb() is
3689                          * not called in MMU path while this function is called
3690                          */
3691                         rc = goya_validate_wreg32(hdev,
3692                                 parser, (struct packet_wreg32 *) user_pkt);
3693                         parser->patched_cb_size += pkt_size;
3694                         break;
3695
3696                 case PACKET_WREG_BULK:
3697                         dev_err(hdev->dev,
3698                                 "User not allowed to use WREG_BULK\n");
3699                         rc = -EPERM;
3700                         break;
3701
3702                 case PACKET_MSG_PROT:
3703                         dev_err(hdev->dev,
3704                                 "User not allowed to use MSG_PROT\n");
3705                         rc = -EPERM;
3706                         break;
3707
3708                 case PACKET_CP_DMA:
3709                         dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3710                         rc = -EPERM;
3711                         break;
3712
3713                 case PACKET_STOP:
3714                         dev_err(hdev->dev, "User not allowed to use STOP\n");
3715                         rc = -EPERM;
3716                         break;
3717
3718                 case PACKET_LIN_DMA:
3719                         if (is_mmu)
3720                                 rc = goya_validate_dma_pkt_mmu(hdev, parser,
3721                                         (struct packet_lin_dma *) user_pkt);
3722                         else
3723                                 rc = goya_validate_dma_pkt_no_mmu(hdev, parser,
3724                                         (struct packet_lin_dma *) user_pkt);
3725                         break;
3726
3727                 case PACKET_MSG_LONG:
3728                 case PACKET_MSG_SHORT:
3729                 case PACKET_FENCE:
3730                 case PACKET_NOP:
3731                         parser->patched_cb_size += pkt_size;
3732                         break;
3733
3734                 default:
3735                         dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3736                                 pkt_id);
3737                         rc = -EINVAL;
3738                         break;
3739                 }
3740
3741                 if (rc)
3742                         break;
3743         }
3744
3745         /*
3746          * The new CB should have space at the end for two MSG_PROT packets:
3747          * 1. A packet that will act as a completion packet
3748          * 2. A packet that will generate MSI-X interrupt
3749          */
3750         parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2;
3751
3752         return rc;
3753 }
3754
3755 static int goya_patch_dma_packet(struct hl_device *hdev,
3756                                 struct hl_cs_parser *parser,
3757                                 struct packet_lin_dma *user_dma_pkt,
3758                                 struct packet_lin_dma *new_dma_pkt,
3759                                 u32 *new_dma_pkt_size)
3760 {
3761         struct hl_userptr *userptr;
3762         struct scatterlist *sg, *sg_next_iter;
3763         u32 count, dma_desc_cnt;
3764         u64 len, len_next;
3765         dma_addr_t dma_addr, dma_addr_next;
3766         enum hl_goya_dma_direction user_dir;
3767         u64 device_memory_addr, addr;
3768         enum dma_data_direction dir;
3769         struct sg_table *sgt;
3770         bool skip_host_mem_pin = false;
3771         bool user_memset;
3772         u32 user_rdcomp_mask, user_wrcomp_mask, ctl;
3773
3774         ctl = le32_to_cpu(user_dma_pkt->ctl);
3775
3776         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3777                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3778
3779         user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3780                         GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3781
3782         if ((user_dir == HL_DMA_DRAM_TO_SRAM) || (user_dir == HL_DMA_SRAM_TO_DRAM) ||
3783                         (user_dma_pkt->tsize == 0)) {
3784                 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*new_dma_pkt));
3785                 *new_dma_pkt_size = sizeof(*new_dma_pkt);
3786                 return 0;
3787         }
3788
3789         if ((user_dir == HL_DMA_HOST_TO_DRAM) || (user_dir == HL_DMA_HOST_TO_SRAM)) {
3790                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3791                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3792                 dir = DMA_TO_DEVICE;
3793                 if (user_memset)
3794                         skip_host_mem_pin = true;
3795         } else {
3796                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3797                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3798                 dir = DMA_FROM_DEVICE;
3799         }
3800
3801         if ((!skip_host_mem_pin) &&
3802                 (hl_userptr_is_pinned(hdev, addr,
3803                         le32_to_cpu(user_dma_pkt->tsize),
3804                         parser->job_userptr_list, &userptr) == false)) {
3805                 dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n",
3806                                 addr, user_dma_pkt->tsize);
3807                 return -EFAULT;
3808         }
3809
3810         if ((user_memset) && (dir == DMA_TO_DEVICE)) {
3811                 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*user_dma_pkt));
3812                 *new_dma_pkt_size = sizeof(*user_dma_pkt);
3813                 return 0;
3814         }
3815
3816         user_rdcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK;
3817
3818         user_wrcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK;
3819
3820         sgt = userptr->sgt;
3821         dma_desc_cnt = 0;
3822
3823         for_each_sgtable_dma_sg(sgt, sg, count) {
3824                 len = sg_dma_len(sg);
3825                 dma_addr = sg_dma_address(sg);
3826
3827                 if (len == 0)
3828                         break;
3829
3830                 while ((count + 1) < sgt->nents) {
3831                         sg_next_iter = sg_next(sg);
3832                         len_next = sg_dma_len(sg_next_iter);
3833                         dma_addr_next = sg_dma_address(sg_next_iter);
3834
3835                         if (len_next == 0)
3836                                 break;
3837
3838                         if ((dma_addr + len == dma_addr_next) &&
3839                                 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3840                                 len += len_next;
3841                                 count++;
3842                                 sg = sg_next_iter;
3843                         } else {
3844                                 break;
3845                         }
3846                 }
3847
3848                 ctl = le32_to_cpu(user_dma_pkt->ctl);
3849                 if (likely(dma_desc_cnt))
3850                         ctl &= ~GOYA_PKT_CTL_EB_MASK;
3851                 ctl &= ~(GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK |
3852                                 GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK);
3853                 new_dma_pkt->ctl = cpu_to_le32(ctl);
3854                 new_dma_pkt->tsize = cpu_to_le32((u32) len);
3855
3856                 if (dir == DMA_TO_DEVICE) {
3857                         new_dma_pkt->src_addr = cpu_to_le64(dma_addr);
3858                         new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr);
3859                 } else {
3860                         new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr);
3861                         new_dma_pkt->dst_addr = cpu_to_le64(dma_addr);
3862                 }
3863
3864                 if (!user_memset)
3865                         device_memory_addr += len;
3866                 dma_desc_cnt++;
3867                 new_dma_pkt++;
3868         }
3869
3870         if (!dma_desc_cnt) {
3871                 dev_err(hdev->dev,
3872                         "Error of 0 SG entries when patching DMA packet\n");
3873                 return -EFAULT;
3874         }
3875
3876         /* Fix the last dma packet - rdcomp/wrcomp must be as user set them */
3877         new_dma_pkt--;
3878         new_dma_pkt->ctl |= cpu_to_le32(user_rdcomp_mask | user_wrcomp_mask);
3879
3880         *new_dma_pkt_size = dma_desc_cnt * sizeof(struct packet_lin_dma);
3881
3882         return 0;
3883 }
3884
3885 static int goya_patch_cb(struct hl_device *hdev,
3886                                 struct hl_cs_parser *parser)
3887 {
3888         u32 cb_parsed_length = 0;
3889         u32 cb_patched_cur_length = 0;
3890         int rc = 0;
3891
3892         /* cb_user_size is more than 0 so loop will always be executed */
3893         while (cb_parsed_length < parser->user_cb_size) {
3894                 enum packet_id pkt_id;
3895                 u16 pkt_size;
3896                 u32 new_pkt_size = 0;
3897                 struct goya_packet *user_pkt, *kernel_pkt;
3898
3899                 user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
3900                 kernel_pkt = parser->patched_cb->kernel_address +
3901                                         cb_patched_cur_length;
3902
3903                 pkt_id = (enum packet_id) (
3904                                 (le64_to_cpu(user_pkt->header) &
3905                                 PACKET_HEADER_PACKET_ID_MASK) >>
3906                                         PACKET_HEADER_PACKET_ID_SHIFT);
3907
3908                 if (!validate_packet_id(pkt_id)) {
3909                         dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
3910                         rc = -EINVAL;
3911                         break;
3912                 }
3913
3914                 pkt_size = goya_packet_sizes[pkt_id];
3915                 cb_parsed_length += pkt_size;
3916                 if (cb_parsed_length > parser->user_cb_size) {
3917                         dev_err(hdev->dev,
3918                                 "packet 0x%x is out of CB boundary\n", pkt_id);
3919                         rc = -EINVAL;
3920                         break;
3921                 }
3922
3923                 switch (pkt_id) {
3924                 case PACKET_LIN_DMA:
3925                         rc = goya_patch_dma_packet(hdev, parser,
3926                                         (struct packet_lin_dma *) user_pkt,
3927                                         (struct packet_lin_dma *) kernel_pkt,
3928                                         &new_pkt_size);
3929                         cb_patched_cur_length += new_pkt_size;
3930                         break;
3931
3932                 case PACKET_WREG_32:
3933                         memcpy(kernel_pkt, user_pkt, pkt_size);
3934                         cb_patched_cur_length += pkt_size;
3935                         rc = goya_validate_wreg32(hdev, parser,
3936                                         (struct packet_wreg32 *) kernel_pkt);
3937                         break;
3938
3939                 case PACKET_WREG_BULK:
3940                         dev_err(hdev->dev,
3941                                 "User not allowed to use WREG_BULK\n");
3942                         rc = -EPERM;
3943                         break;
3944
3945                 case PACKET_MSG_PROT:
3946                         dev_err(hdev->dev,
3947                                 "User not allowed to use MSG_PROT\n");
3948                         rc = -EPERM;
3949                         break;
3950
3951                 case PACKET_CP_DMA:
3952                         dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3953                         rc = -EPERM;
3954                         break;
3955
3956                 case PACKET_STOP:
3957                         dev_err(hdev->dev, "User not allowed to use STOP\n");
3958                         rc = -EPERM;
3959                         break;
3960
3961                 case PACKET_MSG_LONG:
3962                 case PACKET_MSG_SHORT:
3963                 case PACKET_FENCE:
3964                 case PACKET_NOP:
3965                         memcpy(kernel_pkt, user_pkt, pkt_size);
3966                         cb_patched_cur_length += pkt_size;
3967                         break;
3968
3969                 default:
3970                         dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3971                                 pkt_id);
3972                         rc = -EINVAL;
3973                         break;
3974                 }
3975
3976                 if (rc)
3977                         break;
3978         }
3979
3980         return rc;
3981 }
3982
3983 static int goya_parse_cb_mmu(struct hl_device *hdev,
3984                 struct hl_cs_parser *parser)
3985 {
3986         u64 handle;
3987         u32 patched_cb_size;
3988         struct hl_cb *user_cb;
3989         int rc;
3990
3991         /*
3992          * The new CB should have space at the end for two MSG_PROT pkt:
3993          * 1. A packet that will act as a completion packet
3994          * 2. A packet that will generate MSI-X interrupt
3995          */
3996         parser->patched_cb_size = parser->user_cb_size +
3997                         sizeof(struct packet_msg_prot) * 2;
3998
3999         rc = hl_cb_create(hdev, &hdev->kernel_mem_mgr, hdev->kernel_ctx,
4000                                 parser->patched_cb_size, false, false,
4001                                 &handle);
4002
4003         if (rc) {
4004                 dev_err(hdev->dev,
4005                         "Failed to allocate patched CB for DMA CS %d\n",
4006                         rc);
4007                 return rc;
4008         }
4009
4010         parser->patched_cb = hl_cb_get(&hdev->kernel_mem_mgr, handle);
4011         /* hl_cb_get should never fail here */
4012         if (!parser->patched_cb) {
4013                 dev_crit(hdev->dev, "DMA CB handle invalid 0x%llx\n", handle);
4014                 rc = -EFAULT;
4015                 goto out;
4016         }
4017
4018         /*
4019          * The check that parser->user_cb_size <= parser->user_cb->size was done
4020          * in validate_queue_index().
4021          */
4022         memcpy(parser->patched_cb->kernel_address,
4023                 parser->user_cb->kernel_address,
4024                 parser->user_cb_size);
4025
4026         patched_cb_size = parser->patched_cb_size;
4027
4028         /* validate patched CB instead of user CB */
4029         user_cb = parser->user_cb;
4030         parser->user_cb = parser->patched_cb;
4031         rc = goya_validate_cb(hdev, parser, true);
4032         parser->user_cb = user_cb;
4033
4034         if (rc) {
4035                 hl_cb_put(parser->patched_cb);
4036                 goto out;
4037         }
4038
4039         if (patched_cb_size != parser->patched_cb_size) {
4040                 dev_err(hdev->dev, "user CB size mismatch\n");
4041                 hl_cb_put(parser->patched_cb);
4042                 rc = -EINVAL;
4043                 goto out;
4044         }
4045
4046 out:
4047         /*
4048          * Always call cb destroy here because we still have 1 reference
4049          * to it by calling cb_get earlier. After the job will be completed,
4050          * cb_put will release it, but here we want to remove it from the
4051          * idr
4052          */
4053         hl_cb_destroy(&hdev->kernel_mem_mgr, handle);
4054
4055         return rc;
4056 }
4057
4058 static int goya_parse_cb_no_mmu(struct hl_device *hdev,
4059                                 struct hl_cs_parser *parser)
4060 {
4061         u64 handle;
4062         int rc;
4063
4064         rc = goya_validate_cb(hdev, parser, false);
4065
4066         if (rc)
4067                 goto free_userptr;
4068
4069         rc = hl_cb_create(hdev, &hdev->kernel_mem_mgr, hdev->kernel_ctx,
4070                                 parser->patched_cb_size, false, false,
4071                                 &handle);
4072         if (rc) {
4073                 dev_err(hdev->dev,
4074                         "Failed to allocate patched CB for DMA CS %d\n", rc);
4075                 goto free_userptr;
4076         }
4077
4078         parser->patched_cb = hl_cb_get(&hdev->kernel_mem_mgr, handle);
4079         /* hl_cb_get should never fail here */
4080         if (!parser->patched_cb) {
4081                 dev_crit(hdev->dev, "DMA CB handle invalid 0x%llx\n", handle);
4082                 rc = -EFAULT;
4083                 goto out;
4084         }
4085
4086         rc = goya_patch_cb(hdev, parser);
4087
4088         if (rc)
4089                 hl_cb_put(parser->patched_cb);
4090
4091 out:
4092         /*
4093          * Always call cb destroy here because we still have 1 reference
4094          * to it by calling cb_get earlier. After the job will be completed,
4095          * cb_put will release it, but here we want to remove it from the
4096          * idr
4097          */
4098         hl_cb_destroy(&hdev->kernel_mem_mgr, handle);
4099
4100 free_userptr:
4101         if (rc)
4102                 hl_userptr_delete_list(hdev, parser->job_userptr_list);
4103         return rc;
4104 }
4105
4106 static int goya_parse_cb_no_ext_queue(struct hl_device *hdev,
4107                                         struct hl_cs_parser *parser)
4108 {
4109         struct asic_fixed_properties *asic_prop = &hdev->asic_prop;
4110         struct goya_device *goya = hdev->asic_specific;
4111
4112         if (goya->hw_cap_initialized & HW_CAP_MMU)
4113                 return 0;
4114
4115         /* For internal queue jobs, just check if CB address is valid */
4116         if (hl_mem_area_inside_range(
4117                         (u64) (uintptr_t) parser->user_cb,
4118                         parser->user_cb_size,
4119                         asic_prop->sram_user_base_address,
4120                         asic_prop->sram_end_address))
4121                 return 0;
4122
4123         if (hl_mem_area_inside_range(
4124                         (u64) (uintptr_t) parser->user_cb,
4125                         parser->user_cb_size,
4126                         asic_prop->dram_user_base_address,
4127                         asic_prop->dram_end_address))
4128                 return 0;
4129
4130         dev_err(hdev->dev,
4131                 "Internal CB address 0x%px + 0x%x is not in SRAM nor in DRAM\n",
4132                 parser->user_cb, parser->user_cb_size);
4133
4134         return -EFAULT;
4135 }
4136
4137 int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser)
4138 {
4139         struct goya_device *goya = hdev->asic_specific;
4140
4141         if (parser->queue_type == QUEUE_TYPE_INT)
4142                 return goya_parse_cb_no_ext_queue(hdev, parser);
4143
4144         if (goya->hw_cap_initialized & HW_CAP_MMU)
4145                 return goya_parse_cb_mmu(hdev, parser);
4146         else
4147                 return goya_parse_cb_no_mmu(hdev, parser);
4148 }
4149
4150 void goya_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address,
4151                                 u32 len, u32 original_len, u64 cq_addr, u32 cq_val,
4152                                 u32 msix_vec, bool eb)
4153 {
4154         struct packet_msg_prot *cq_pkt;
4155         u32 tmp;
4156
4157         cq_pkt = kernel_address + len - (sizeof(struct packet_msg_prot) * 2);
4158
4159         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
4160                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
4161                         (1 << GOYA_PKT_CTL_MB_SHIFT);
4162         cq_pkt->ctl = cpu_to_le32(tmp);
4163         cq_pkt->value = cpu_to_le32(cq_val);
4164         cq_pkt->addr = cpu_to_le64(cq_addr);
4165
4166         cq_pkt++;
4167
4168         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
4169                         (1 << GOYA_PKT_CTL_MB_SHIFT);
4170         cq_pkt->ctl = cpu_to_le32(tmp);
4171         cq_pkt->value = cpu_to_le32(msix_vec & 0x7FF);
4172         cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_DBI_MSIX_DOORBELL_OFF);
4173 }
4174
4175 void goya_update_eq_ci(struct hl_device *hdev, u32 val)
4176 {
4177         WREG32(mmCPU_EQ_CI, val);
4178 }
4179
4180 void goya_restore_phase_topology(struct hl_device *hdev)
4181 {
4182
4183 }
4184
4185 static void goya_clear_sm_regs(struct hl_device *hdev)
4186 {
4187         int i, num_of_sob_in_longs, num_of_mon_in_longs;
4188
4189         num_of_sob_in_longs =
4190                 ((mmSYNC_MNGR_SOB_OBJ_1023 - mmSYNC_MNGR_SOB_OBJ_0) + 4);
4191
4192         num_of_mon_in_longs =
4193                 ((mmSYNC_MNGR_MON_STATUS_255 - mmSYNC_MNGR_MON_STATUS_0) + 4);
4194
4195         for (i = 0 ; i < num_of_sob_in_longs ; i += 4)
4196                 WREG32(mmSYNC_MNGR_SOB_OBJ_0 + i, 0);
4197
4198         for (i = 0 ; i < num_of_mon_in_longs ; i += 4)
4199                 WREG32(mmSYNC_MNGR_MON_STATUS_0 + i, 0);
4200
4201         /* Flush all WREG to prevent race */
4202         i = RREG32(mmSYNC_MNGR_SOB_OBJ_0);
4203 }
4204
4205 static int goya_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size, void *blob_addr)
4206 {
4207         dev_err(hdev->dev, "Reading via DMA is unimplemented yet\n");
4208         return -EPERM;
4209 }
4210
4211 static u64 goya_read_pte(struct hl_device *hdev, u64 addr)
4212 {
4213         struct goya_device *goya = hdev->asic_specific;
4214
4215         if (hdev->reset_info.hard_reset_pending)
4216                 return U64_MAX;
4217
4218         return readq(hdev->pcie_bar[DDR_BAR_ID] +
4219                         (addr - goya->ddr_bar_cur_addr));
4220 }
4221
4222 static void goya_write_pte(struct hl_device *hdev, u64 addr, u64 val)
4223 {
4224         struct goya_device *goya = hdev->asic_specific;
4225
4226         if (hdev->reset_info.hard_reset_pending)
4227                 return;
4228
4229         writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
4230                         (addr - goya->ddr_bar_cur_addr));
4231 }
4232
4233 static const char *_goya_get_event_desc(u16 event_type)
4234 {
4235         switch (event_type) {
4236         case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4237                 return "PCIe_if";
4238         case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4239         case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4240         case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4241         case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4242         case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4243         case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4244         case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4245         case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4246                 return "TPC%d_ecc";
4247         case GOYA_ASYNC_EVENT_ID_MME_ECC:
4248                 return "MME_ecc";
4249         case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4250                 return "MME_ecc_ext";
4251         case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4252                 return "MMU_ecc";
4253         case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4254                 return "DMA_macro";
4255         case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4256                 return "DMA_ecc";
4257         case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4258                 return "CPU_if_ecc";
4259         case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4260                 return "PSOC_mem";
4261         case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4262                 return "PSOC_coresight";
4263         case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4264                 return "SRAM%d";
4265         case GOYA_ASYNC_EVENT_ID_GIC500:
4266                 return "GIC500";
4267         case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4268                 return "PLL%d";
4269         case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4270                 return "AXI_ecc";
4271         case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4272                 return "L2_ram_ecc";
4273         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4274                 return "PSOC_gpio_05_sw_reset";
4275         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4276                 return "PSOC_gpio_10_vrhot_icrit";
4277         case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4278                 return "PCIe_dec";
4279         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4280         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4281         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4282         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4283         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4284         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4285         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4286         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4287                 return "TPC%d_dec";
4288         case GOYA_ASYNC_EVENT_ID_MME_WACS:
4289                 return "MME_wacs";
4290         case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4291                 return "MME_wacsd";
4292         case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4293                 return "CPU_axi_splitter";
4294         case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4295                 return "PSOC_axi_dec";
4296         case GOYA_ASYNC_EVENT_ID_PSOC:
4297                 return "PSOC";
4298         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4299         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4300         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4301         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4302         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4303         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4304         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4305         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4306                 return "TPC%d_krn_err";
4307         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4308                 return "TPC%d_cq";
4309         case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4310                 return "TPC%d_qm";
4311         case GOYA_ASYNC_EVENT_ID_MME_QM:
4312                 return "MME_qm";
4313         case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4314                 return "MME_cq";
4315         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4316                 return "DMA%d_qm";
4317         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4318                 return "DMA%d_ch";
4319         case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4320         case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4321         case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4322         case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4323         case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4324         case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4325         case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4326         case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4327                 return "TPC%d_bmon_spmu";
4328         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4329                 return "DMA_bm_ch%d";
4330         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4331                 return "POWER_ENV_S";
4332         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4333                 return "POWER_ENV_E";
4334         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4335                 return "THERMAL_ENV_S";
4336         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4337                 return "THERMAL_ENV_E";
4338         case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
4339                 return "QUEUE_OUT_OF_SYNC";
4340         default:
4341                 return "N/A";
4342         }
4343 }
4344
4345 static void goya_get_event_desc(u16 event_type, char *desc, size_t size)
4346 {
4347         u8 index;
4348
4349         switch (event_type) {
4350         case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4351         case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4352         case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4353         case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4354         case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4355         case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4356         case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4357         case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4358                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_ECC) / 3;
4359                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4360                 break;
4361         case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4362                 index = event_type - GOYA_ASYNC_EVENT_ID_SRAM0;
4363                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4364                 break;
4365         case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4366                 index = event_type - GOYA_ASYNC_EVENT_ID_PLL0;
4367                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4368                 break;
4369         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4370         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4371         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4372         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4373         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4374         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4375         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4376         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4377                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_DEC) / 3;
4378                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4379                 break;
4380         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4381         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4382         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4383         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4384         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4385         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4386         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4387         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4388                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR) / 10;
4389                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4390                 break;
4391         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4392                 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_CMDQ;
4393                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4394                 break;
4395         case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4396                 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_QM;
4397                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4398                 break;
4399         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4400                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_QM;
4401                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4402                 break;
4403         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4404                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_CH;
4405                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4406                 break;
4407         case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4408         case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4409         case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4410         case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4411         case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4412         case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4413         case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4414         case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4415                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU) / 10;
4416                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4417                 break;
4418         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4419                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA_BM_CH0;
4420                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4421                 break;
4422         case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
4423                 snprintf(desc, size, _goya_get_event_desc(event_type));
4424                 break;
4425         default:
4426                 snprintf(desc, size, _goya_get_event_desc(event_type));
4427                 break;
4428         }
4429 }
4430
4431 static void goya_print_razwi_info(struct hl_device *hdev)
4432 {
4433         if (RREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD)) {
4434                 dev_err_ratelimited(hdev->dev, "Illegal write to LBW\n");
4435                 WREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD, 0);
4436         }
4437
4438         if (RREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD)) {
4439                 dev_err_ratelimited(hdev->dev, "Illegal read from LBW\n");
4440                 WREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD, 0);
4441         }
4442
4443         if (RREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD)) {
4444                 dev_err_ratelimited(hdev->dev, "Illegal write to HBW\n");
4445                 WREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD, 0);
4446         }
4447
4448         if (RREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD)) {
4449                 dev_err_ratelimited(hdev->dev, "Illegal read from HBW\n");
4450                 WREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD, 0);
4451         }
4452 }
4453
4454 static void goya_print_mmu_error_info(struct hl_device *hdev)
4455 {
4456         struct goya_device *goya = hdev->asic_specific;
4457         u64 addr;
4458         u32 val;
4459
4460         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4461                 return;
4462
4463         val = RREG32(mmMMU_PAGE_ERROR_CAPTURE);
4464         if (val & MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) {
4465                 addr = val & MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK;
4466                 addr <<= 32;
4467                 addr |= RREG32(mmMMU_PAGE_ERROR_CAPTURE_VA);
4468
4469                 dev_err_ratelimited(hdev->dev, "MMU page fault on va 0x%llx\n",
4470                                         addr);
4471
4472                 WREG32(mmMMU_PAGE_ERROR_CAPTURE, 0);
4473         }
4474 }
4475
4476 static void goya_print_out_of_sync_info(struct hl_device *hdev,
4477                                         struct cpucp_pkt_sync_err *sync_err)
4478 {
4479         struct hl_hw_queue *q = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
4480
4481         dev_err(hdev->dev, "Out of sync with FW, FW: pi=%u, ci=%u, LKD: pi=%u, ci=%d\n",
4482                 le32_to_cpu(sync_err->pi), le32_to_cpu(sync_err->ci), q->pi, atomic_read(&q->ci));
4483 }
4484
4485 static void goya_print_irq_info(struct hl_device *hdev, u16 event_type,
4486                                 bool razwi)
4487 {
4488         char desc[20] = "";
4489
4490         goya_get_event_desc(event_type, desc, sizeof(desc));
4491         dev_err_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n",
4492                 event_type, desc);
4493
4494         if (razwi) {
4495                 goya_print_razwi_info(hdev);
4496                 goya_print_mmu_error_info(hdev);
4497         }
4498 }
4499
4500 static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr,
4501                 size_t irq_arr_size)
4502 {
4503         struct cpucp_unmask_irq_arr_packet *pkt;
4504         size_t total_pkt_size;
4505         u64 result;
4506         int rc;
4507         int irq_num_entries, irq_arr_index;
4508         __le32 *goya_irq_arr;
4509
4510         total_pkt_size = sizeof(struct cpucp_unmask_irq_arr_packet) +
4511                         irq_arr_size;
4512
4513         /* data should be aligned to 8 bytes in order to CPU-CP to copy it */
4514         total_pkt_size = (total_pkt_size + 0x7) & ~0x7;
4515
4516         /* total_pkt_size is casted to u16 later on */
4517         if (total_pkt_size > USHRT_MAX) {
4518                 dev_err(hdev->dev, "too many elements in IRQ array\n");
4519                 return -EINVAL;
4520         }
4521
4522         pkt = kzalloc(total_pkt_size, GFP_KERNEL);
4523         if (!pkt)
4524                 return -ENOMEM;
4525
4526         irq_num_entries = irq_arr_size / sizeof(irq_arr[0]);
4527         pkt->length = cpu_to_le32(irq_num_entries);
4528
4529         /* We must perform any necessary endianness conversation on the irq
4530          * array being passed to the goya hardware
4531          */
4532         for (irq_arr_index = 0, goya_irq_arr = (__le32 *) &pkt->irqs;
4533                         irq_arr_index < irq_num_entries ; irq_arr_index++)
4534                 goya_irq_arr[irq_arr_index] =
4535                                 cpu_to_le32(irq_arr[irq_arr_index]);
4536
4537         pkt->cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY <<
4538                                                 CPUCP_PKT_CTL_OPCODE_SHIFT);
4539
4540         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt,
4541                                                 total_pkt_size, 0, &result);
4542
4543         if (rc)
4544                 dev_err(hdev->dev, "failed to unmask IRQ array\n");
4545
4546         kfree(pkt);
4547
4548         return rc;
4549 }
4550
4551 static int goya_compute_reset_late_init(struct hl_device *hdev)
4552 {
4553         /*
4554          * Unmask all IRQs since some could have been received
4555          * during the soft reset
4556          */
4557         return goya_unmask_irq_arr(hdev, goya_all_events,
4558                                         sizeof(goya_all_events));
4559 }
4560
4561 static int goya_unmask_irq(struct hl_device *hdev, u16 event_type)
4562 {
4563         struct cpucp_packet pkt;
4564         u64 result;
4565         int rc;
4566
4567         memset(&pkt, 0, sizeof(pkt));
4568
4569         pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ <<
4570                                 CPUCP_PKT_CTL_OPCODE_SHIFT);
4571         pkt.value = cpu_to_le64(event_type);
4572
4573         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
4574                                                 0, &result);
4575
4576         if (rc)
4577                 dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type);
4578
4579         return rc;
4580 }
4581
4582 static void goya_print_clk_change_info(struct hl_device *hdev, u16 event_type)
4583 {
4584         ktime_t zero_time = ktime_set(0, 0);
4585
4586         mutex_lock(&hdev->clk_throttling.lock);
4587
4588         switch (event_type) {
4589         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4590                 hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_POWER;
4591                 hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_POWER;
4592                 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].start = ktime_get();
4593                 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = zero_time;
4594                 dev_info_ratelimited(hdev->dev,
4595                         "Clock throttling due to power consumption\n");
4596                 break;
4597
4598         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4599                 hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_POWER;
4600                 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = ktime_get();
4601                 dev_info_ratelimited(hdev->dev,
4602                         "Power envelop is safe, back to optimal clock\n");
4603                 break;
4604
4605         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4606                 hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_THERMAL;
4607                 hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_THERMAL;
4608                 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].start = ktime_get();
4609                 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = zero_time;
4610                 dev_info_ratelimited(hdev->dev,
4611                         "Clock throttling due to overheating\n");
4612                 break;
4613
4614         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4615                 hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_THERMAL;
4616                 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = ktime_get();
4617                 dev_info_ratelimited(hdev->dev,
4618                         "Thermal envelop is safe, back to optimal clock\n");
4619                 break;
4620
4621         default:
4622                 dev_err(hdev->dev, "Received invalid clock change event %d\n",
4623                         event_type);
4624                 break;
4625         }
4626
4627         mutex_unlock(&hdev->clk_throttling.lock);
4628 }
4629
4630 void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry)
4631 {
4632         u32 ctl = le32_to_cpu(eq_entry->hdr.ctl);
4633         u16 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK)
4634                                 >> EQ_CTL_EVENT_TYPE_SHIFT);
4635         struct goya_device *goya = hdev->asic_specific;
4636
4637         if (event_type >= GOYA_ASYNC_EVENT_ID_SIZE) {
4638                 dev_err(hdev->dev, "Event type %u exceeds maximum of %u",
4639                                 event_type, GOYA_ASYNC_EVENT_ID_SIZE - 1);
4640                 return;
4641         }
4642
4643         goya->events_stat[event_type]++;
4644         goya->events_stat_aggregate[event_type]++;
4645
4646         switch (event_type) {
4647         case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4648         case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4649         case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4650         case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4651         case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4652         case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4653         case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4654         case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4655         case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4656         case GOYA_ASYNC_EVENT_ID_MME_ECC:
4657         case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4658         case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4659         case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4660         case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4661         case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4662         case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4663         case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4664         case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4665         case GOYA_ASYNC_EVENT_ID_GIC500:
4666         case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4667         case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4668         case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4669                 goya_print_irq_info(hdev, event_type, false);
4670                 if (hdev->hard_reset_on_fw_events)
4671                         hl_device_reset(hdev, (HL_DRV_RESET_HARD |
4672                                                 HL_DRV_RESET_FW_FATAL_ERR));
4673                 break;
4674
4675         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4676                 goya_print_irq_info(hdev, event_type, false);
4677                 if (hdev->hard_reset_on_fw_events)
4678                         hl_device_reset(hdev, HL_DRV_RESET_HARD);
4679                 break;
4680
4681         case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4682         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4683         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4684         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4685         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4686         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4687         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4688         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4689         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4690         case GOYA_ASYNC_EVENT_ID_MME_WACS:
4691         case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4692         case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4693         case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4694         case GOYA_ASYNC_EVENT_ID_PSOC:
4695         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4696         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4697         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4698         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4699         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4700         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4701         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4702         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4703         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4704         case GOYA_ASYNC_EVENT_ID_MME_QM:
4705         case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4706         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4707         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4708                 goya_print_irq_info(hdev, event_type, true);
4709                 goya_unmask_irq(hdev, event_type);
4710                 break;
4711
4712         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4713         case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4714         case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4715         case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4716         case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4717         case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4718         case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4719         case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4720         case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4721         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4722                 goya_print_irq_info(hdev, event_type, false);
4723                 goya_unmask_irq(hdev, event_type);
4724                 break;
4725
4726         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4727         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4728         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4729         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4730                 goya_print_clk_change_info(hdev, event_type);
4731                 goya_unmask_irq(hdev, event_type);
4732                 break;
4733
4734         case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
4735                 goya_print_irq_info(hdev, event_type, false);
4736                 goya_print_out_of_sync_info(hdev, &eq_entry->pkt_sync_err);
4737                 if (hdev->hard_reset_on_fw_events)
4738                         hl_device_reset(hdev, HL_DRV_RESET_HARD);
4739                 else
4740                         hl_fw_unmask_irq(hdev, event_type);
4741                 break;
4742
4743         default:
4744                 dev_err(hdev->dev, "Received invalid H/W interrupt %d\n",
4745                                 event_type);
4746                 break;
4747         }
4748 }
4749
4750 void *goya_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size)
4751 {
4752         struct goya_device *goya = hdev->asic_specific;
4753
4754         if (aggregate) {
4755                 *size = (u32) sizeof(goya->events_stat_aggregate);
4756                 return goya->events_stat_aggregate;
4757         }
4758
4759         *size = (u32) sizeof(goya->events_stat);
4760         return goya->events_stat;
4761 }
4762
4763 static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size,
4764                                 u64 val, bool is_dram)
4765 {
4766         struct packet_lin_dma *lin_dma_pkt;
4767         struct hl_cs_job *job;
4768         u32 cb_size, ctl;
4769         struct hl_cb *cb;
4770         int rc, lin_dma_pkts_cnt;
4771
4772         lin_dma_pkts_cnt = DIV_ROUND_UP_ULL(size, SZ_2G);
4773         cb_size = lin_dma_pkts_cnt * sizeof(struct packet_lin_dma) +
4774                                                 sizeof(struct packet_msg_prot);
4775         cb = hl_cb_kernel_create(hdev, cb_size, false);
4776         if (!cb)
4777                 return -ENOMEM;
4778
4779         lin_dma_pkt = cb->kernel_address;
4780
4781         do {
4782                 memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt));
4783
4784                 ctl = ((PACKET_LIN_DMA << GOYA_PKT_CTL_OPCODE_SHIFT) |
4785                                 (1 << GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT) |
4786                                 (1 << GOYA_PKT_LIN_DMA_CTL_WO_SHIFT) |
4787                                 (1 << GOYA_PKT_CTL_RB_SHIFT) |
4788                                 (1 << GOYA_PKT_CTL_MB_SHIFT));
4789                 ctl |= (is_dram ? HL_DMA_HOST_TO_DRAM : HL_DMA_HOST_TO_SRAM) <<
4790                                 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
4791                 lin_dma_pkt->ctl = cpu_to_le32(ctl);
4792
4793                 lin_dma_pkt->src_addr = cpu_to_le64(val);
4794                 lin_dma_pkt->dst_addr = cpu_to_le64(addr);
4795                 if (lin_dma_pkts_cnt > 1)
4796                         lin_dma_pkt->tsize = cpu_to_le32(SZ_2G);
4797                 else
4798                         lin_dma_pkt->tsize = cpu_to_le32(size);
4799
4800                 size -= SZ_2G;
4801                 addr += SZ_2G;
4802                 lin_dma_pkt++;
4803         } while (--lin_dma_pkts_cnt);
4804
4805         job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true);
4806         if (!job) {
4807                 dev_err(hdev->dev, "Failed to allocate a new job\n");
4808                 rc = -ENOMEM;
4809                 goto release_cb;
4810         }
4811
4812         job->id = 0;
4813         job->user_cb = cb;
4814         atomic_inc(&job->user_cb->cs_cnt);
4815         job->user_cb_size = cb_size;
4816         job->hw_queue_id = GOYA_QUEUE_ID_DMA_0;
4817         job->patched_cb = job->user_cb;
4818         job->job_cb_size = job->user_cb_size;
4819
4820         hl_debugfs_add_job(hdev, job);
4821
4822         rc = goya_send_job_on_qman0(hdev, job);
4823
4824         hl_debugfs_remove_job(hdev, job);
4825         kfree(job);
4826         atomic_dec(&cb->cs_cnt);
4827
4828 release_cb:
4829         hl_cb_put(cb);
4830         hl_cb_destroy(&hdev->kernel_mem_mgr, cb->buf->handle);
4831
4832         return rc;
4833 }
4834
4835 int goya_context_switch(struct hl_device *hdev, u32 asid)
4836 {
4837         struct asic_fixed_properties *prop = &hdev->asic_prop;
4838         u64 addr = prop->sram_base_address, sob_addr;
4839         u32 size = hdev->pldm ? 0x10000 : prop->sram_size;
4840         u64 val = 0x7777777777777777ull;
4841         int rc, dma_id;
4842         u32 channel_off = mmDMA_CH_1_WR_COMP_ADDR_LO -
4843                                         mmDMA_CH_0_WR_COMP_ADDR_LO;
4844
4845         rc = goya_memset_device_memory(hdev, addr, size, val, false);
4846         if (rc) {
4847                 dev_err(hdev->dev, "Failed to clear SRAM in context switch\n");
4848                 return rc;
4849         }
4850
4851         /* we need to reset registers that the user is allowed to change */
4852         sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
4853         WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO, lower_32_bits(sob_addr));
4854
4855         for (dma_id = 1 ; dma_id < NUMBER_OF_EXT_HW_QUEUES ; dma_id++) {
4856                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
4857                                                         (dma_id - 1) * 4;
4858                 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO + channel_off * dma_id,
4859                                                 lower_32_bits(sob_addr));
4860         }
4861
4862         WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
4863
4864         goya_clear_sm_regs(hdev);
4865
4866         return 0;
4867 }
4868
4869 static int goya_mmu_clear_pgt_range(struct hl_device *hdev)
4870 {
4871         struct asic_fixed_properties *prop = &hdev->asic_prop;
4872         struct goya_device *goya = hdev->asic_specific;
4873         u64 addr = prop->mmu_pgt_addr;
4874         u32 size = prop->mmu_pgt_size + MMU_DRAM_DEFAULT_PAGE_SIZE +
4875                         MMU_CACHE_MNG_SIZE;
4876
4877         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4878                 return 0;
4879
4880         return goya_memset_device_memory(hdev, addr, size, 0, true);
4881 }
4882
4883 static int goya_mmu_set_dram_default_page(struct hl_device *hdev)
4884 {
4885         struct goya_device *goya = hdev->asic_specific;
4886         u64 addr = hdev->asic_prop.mmu_dram_default_page_addr;
4887         u32 size = MMU_DRAM_DEFAULT_PAGE_SIZE;
4888         u64 val = 0x9999999999999999ull;
4889
4890         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4891                 return 0;
4892
4893         return goya_memset_device_memory(hdev, addr, size, val, true);
4894 }
4895
4896 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev)
4897 {
4898         struct asic_fixed_properties *prop = &hdev->asic_prop;
4899         struct goya_device *goya = hdev->asic_specific;
4900         s64 off, cpu_off;
4901         int rc;
4902
4903         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4904                 return 0;
4905
4906         for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB) {
4907                 rc = hl_mmu_map_page(hdev->kernel_ctx,
4908                         prop->dram_base_address + off,
4909                         prop->dram_base_address + off, PAGE_SIZE_2MB,
4910                         (off + PAGE_SIZE_2MB) == CPU_FW_IMAGE_SIZE);
4911                 if (rc) {
4912                         dev_err(hdev->dev, "Map failed for address 0x%llx\n",
4913                                 prop->dram_base_address + off);
4914                         goto unmap;
4915                 }
4916         }
4917
4918         if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
4919                 rc = hl_mmu_map_page(hdev->kernel_ctx,
4920                         VA_CPU_ACCESSIBLE_MEM_ADDR,
4921                         hdev->cpu_accessible_dma_address,
4922                         PAGE_SIZE_2MB, true);
4923
4924                 if (rc) {
4925                         dev_err(hdev->dev,
4926                                 "Map failed for CPU accessible memory\n");
4927                         off -= PAGE_SIZE_2MB;
4928                         goto unmap;
4929                 }
4930         } else {
4931                 for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB) {
4932                         rc = hl_mmu_map_page(hdev->kernel_ctx,
4933                                 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
4934                                 hdev->cpu_accessible_dma_address + cpu_off,
4935                                 PAGE_SIZE_4KB, true);
4936                         if (rc) {
4937                                 dev_err(hdev->dev,
4938                                         "Map failed for CPU accessible memory\n");
4939                                 cpu_off -= PAGE_SIZE_4KB;
4940                                 goto unmap_cpu;
4941                         }
4942                 }
4943         }
4944
4945         goya_mmu_prepare_reg(hdev, mmCPU_IF_ARUSER_OVR, HL_KERNEL_ASID_ID);
4946         goya_mmu_prepare_reg(hdev, mmCPU_IF_AWUSER_OVR, HL_KERNEL_ASID_ID);
4947         WREG32(mmCPU_IF_ARUSER_OVR_EN, 0x7FF);
4948         WREG32(mmCPU_IF_AWUSER_OVR_EN, 0x7FF);
4949
4950         /* Make sure configuration is flushed to device */
4951         RREG32(mmCPU_IF_AWUSER_OVR_EN);
4952
4953         goya->device_cpu_mmu_mappings_done = true;
4954
4955         return 0;
4956
4957 unmap_cpu:
4958         for (; cpu_off >= 0 ; cpu_off -= PAGE_SIZE_4KB)
4959                 if (hl_mmu_unmap_page(hdev->kernel_ctx,
4960                                 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
4961                                 PAGE_SIZE_4KB, true))
4962                         dev_warn_ratelimited(hdev->dev,
4963                                 "failed to unmap address 0x%llx\n",
4964                                 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off);
4965 unmap:
4966         for (; off >= 0 ; off -= PAGE_SIZE_2MB)
4967                 if (hl_mmu_unmap_page(hdev->kernel_ctx,
4968                                 prop->dram_base_address + off, PAGE_SIZE_2MB,
4969                                 true))
4970                         dev_warn_ratelimited(hdev->dev,
4971                                 "failed to unmap address 0x%llx\n",
4972                                 prop->dram_base_address + off);
4973
4974         return rc;
4975 }
4976
4977 void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev)
4978 {
4979         struct asic_fixed_properties *prop = &hdev->asic_prop;
4980         struct goya_device *goya = hdev->asic_specific;
4981         u32 off, cpu_off;
4982
4983         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4984                 return;
4985
4986         if (!goya->device_cpu_mmu_mappings_done)
4987                 return;
4988
4989         WREG32(mmCPU_IF_ARUSER_OVR_EN, 0);
4990         WREG32(mmCPU_IF_AWUSER_OVR_EN, 0);
4991
4992         if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
4993                 if (hl_mmu_unmap_page(hdev->kernel_ctx,
4994                                 VA_CPU_ACCESSIBLE_MEM_ADDR,
4995                                 PAGE_SIZE_2MB, true))
4996                         dev_warn(hdev->dev,
4997                                 "Failed to unmap CPU accessible memory\n");
4998         } else {
4999                 for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB)
5000                         if (hl_mmu_unmap_page(hdev->kernel_ctx,
5001                                         VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
5002                                         PAGE_SIZE_4KB,
5003                                         (cpu_off + PAGE_SIZE_4KB) >= SZ_2M))
5004                                 dev_warn_ratelimited(hdev->dev,
5005                                         "failed to unmap address 0x%llx\n",
5006                                         VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off);
5007         }
5008
5009         for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB)
5010                 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5011                                 prop->dram_base_address + off, PAGE_SIZE_2MB,
5012                                 (off + PAGE_SIZE_2MB) >= CPU_FW_IMAGE_SIZE))
5013                         dev_warn_ratelimited(hdev->dev,
5014                                         "Failed to unmap address 0x%llx\n",
5015                                         prop->dram_base_address + off);
5016
5017         goya->device_cpu_mmu_mappings_done = false;
5018 }
5019
5020 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid)
5021 {
5022         struct goya_device *goya = hdev->asic_specific;
5023         int i;
5024
5025         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5026                 return;
5027
5028         if (asid & ~MME_QM_GLBL_SECURE_PROPS_ASID_MASK) {
5029                 dev_crit(hdev->dev, "asid %u is too big\n", asid);
5030                 return;
5031         }
5032
5033         /* zero the MMBP and ASID bits and then set the ASID */
5034         for (i = 0 ; i < GOYA_MMU_REGS_NUM ; i++)
5035                 goya_mmu_prepare_reg(hdev, goya_mmu_regs[i], asid);
5036 }
5037
5038 static int goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard,
5039                                         u32 flags)
5040 {
5041         struct goya_device *goya = hdev->asic_specific;
5042         u32 status, timeout_usec;
5043         int rc;
5044
5045         if (!(goya->hw_cap_initialized & HW_CAP_MMU) ||
5046                 hdev->reset_info.hard_reset_pending)
5047                 return 0;
5048
5049         /* no need in L1 only invalidation in Goya */
5050         if (!is_hard)
5051                 return 0;
5052
5053         if (hdev->pldm)
5054                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
5055         else
5056                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
5057
5058         /* L0 & L1 invalidation */
5059         WREG32(mmSTLB_INV_ALL_START, 1);
5060
5061         rc = hl_poll_timeout(
5062                 hdev,
5063                 mmSTLB_INV_ALL_START,
5064                 status,
5065                 !status,
5066                 1000,
5067                 timeout_usec);
5068
5069         return rc;
5070 }
5071
5072 static int goya_mmu_invalidate_cache_range(struct hl_device *hdev,
5073                                                 bool is_hard, u32 flags,
5074                                                 u32 asid, u64 va, u64 size)
5075 {
5076         /* Treat as invalidate all because there is no range invalidation
5077          * in Goya
5078          */
5079         return hl_mmu_invalidate_cache(hdev, is_hard, flags);
5080 }
5081
5082 int goya_send_heartbeat(struct hl_device *hdev)
5083 {
5084         struct goya_device *goya = hdev->asic_specific;
5085
5086         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5087                 return 0;
5088
5089         return hl_fw_send_heartbeat(hdev);
5090 }
5091
5092 int goya_cpucp_info_get(struct hl_device *hdev)
5093 {
5094         struct goya_device *goya = hdev->asic_specific;
5095         struct asic_fixed_properties *prop = &hdev->asic_prop;
5096         u64 dram_size;
5097         int rc;
5098
5099         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5100                 return 0;
5101
5102         rc = hl_fw_cpucp_handshake(hdev, mmCPU_BOOT_DEV_STS0,
5103                                         mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0,
5104                                         mmCPU_BOOT_ERR1);
5105         if (rc)
5106                 return rc;
5107
5108         dram_size = le64_to_cpu(prop->cpucp_info.dram_size);
5109         if (dram_size) {
5110                 if ((!is_power_of_2(dram_size)) ||
5111                                 (dram_size < DRAM_PHYS_DEFAULT_SIZE)) {
5112                         dev_err(hdev->dev,
5113                                 "F/W reported invalid DRAM size %llu. Trying to use default size\n",
5114                                 dram_size);
5115                         dram_size = DRAM_PHYS_DEFAULT_SIZE;
5116                 }
5117
5118                 prop->dram_size = dram_size;
5119                 prop->dram_end_address = prop->dram_base_address + dram_size;
5120         }
5121
5122         if (!strlen(prop->cpucp_info.card_name))
5123                 strscpy_pad(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME,
5124                                 CARD_NAME_MAX_LEN);
5125
5126         return 0;
5127 }
5128
5129 static bool goya_is_device_idle(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
5130                                 struct engines_data *e)
5131 {
5132         const char *fmt = "%-5d%-9s%#-14x%#-16x%#x\n";
5133         const char *dma_fmt = "%-5d%-9s%#-14x%#x\n";
5134         unsigned long *mask = (unsigned long *)mask_arr;
5135         u32 qm_glbl_sts0, cmdq_glbl_sts0, dma_core_sts0, tpc_cfg_sts,
5136                 mme_arch_sts;
5137         bool is_idle = true, is_eng_idle;
5138         u64 offset;
5139         int i;
5140
5141         if (e)
5142                 hl_engine_data_sprintf(e, "\nDMA  is_idle  QM_GLBL_STS0  DMA_CORE_STS0\n"
5143                                         "---  -------  ------------  -------------\n");
5144
5145         offset = mmDMA_QM_1_GLBL_STS0 - mmDMA_QM_0_GLBL_STS0;
5146
5147         for (i = 0 ; i < DMA_MAX_NUM ; i++) {
5148                 qm_glbl_sts0 = RREG32(mmDMA_QM_0_GLBL_STS0 + i * offset);
5149                 dma_core_sts0 = RREG32(mmDMA_CH_0_STS0 + i * offset);
5150                 is_eng_idle = IS_DMA_QM_IDLE(qm_glbl_sts0) &&
5151                                 IS_DMA_IDLE(dma_core_sts0);
5152                 is_idle &= is_eng_idle;
5153
5154                 if (mask && !is_eng_idle)
5155                         set_bit(GOYA_ENGINE_ID_DMA_0 + i, mask);
5156                 if (e)
5157                         hl_engine_data_sprintf(e, dma_fmt, i, is_eng_idle ? "Y" : "N",
5158                                         qm_glbl_sts0, dma_core_sts0);
5159         }
5160
5161         if (e)
5162                 hl_engine_data_sprintf(e,
5163                         "\nTPC  is_idle  QM_GLBL_STS0  CMDQ_GLBL_STS0  CFG_STATUS\n"
5164                         "---  -------  ------------  --------------  ----------\n");
5165
5166         offset = mmTPC1_QM_GLBL_STS0 - mmTPC0_QM_GLBL_STS0;
5167
5168         for (i = 0 ; i < TPC_MAX_NUM ; i++) {
5169                 qm_glbl_sts0 = RREG32(mmTPC0_QM_GLBL_STS0 + i * offset);
5170                 cmdq_glbl_sts0 = RREG32(mmTPC0_CMDQ_GLBL_STS0 + i * offset);
5171                 tpc_cfg_sts = RREG32(mmTPC0_CFG_STATUS + i * offset);
5172                 is_eng_idle = IS_TPC_QM_IDLE(qm_glbl_sts0) &&
5173                                 IS_TPC_CMDQ_IDLE(cmdq_glbl_sts0) &&
5174                                 IS_TPC_IDLE(tpc_cfg_sts);
5175                 is_idle &= is_eng_idle;
5176
5177                 if (mask && !is_eng_idle)
5178                         set_bit(GOYA_ENGINE_ID_TPC_0 + i, mask);
5179                 if (e)
5180                         hl_engine_data_sprintf(e, fmt, i, is_eng_idle ? "Y" : "N",
5181                                 qm_glbl_sts0, cmdq_glbl_sts0, tpc_cfg_sts);
5182         }
5183
5184         if (e)
5185                 hl_engine_data_sprintf(e,
5186                         "\nMME  is_idle  QM_GLBL_STS0  CMDQ_GLBL_STS0  ARCH_STATUS\n"
5187                         "---  -------  ------------  --------------  -----------\n");
5188
5189         qm_glbl_sts0 = RREG32(mmMME_QM_GLBL_STS0);
5190         cmdq_glbl_sts0 = RREG32(mmMME_CMDQ_GLBL_STS0);
5191         mme_arch_sts = RREG32(mmMME_ARCH_STATUS);
5192         is_eng_idle = IS_MME_QM_IDLE(qm_glbl_sts0) &&
5193                         IS_MME_CMDQ_IDLE(cmdq_glbl_sts0) &&
5194                         IS_MME_IDLE(mme_arch_sts);
5195         is_idle &= is_eng_idle;
5196
5197         if (mask && !is_eng_idle)
5198                 set_bit(GOYA_ENGINE_ID_MME_0, mask);
5199         if (e) {
5200                 hl_engine_data_sprintf(e, fmt, 0, is_eng_idle ? "Y" : "N", qm_glbl_sts0,
5201                                 cmdq_glbl_sts0, mme_arch_sts);
5202                 hl_engine_data_sprintf(e, "\n");
5203         }
5204
5205         return is_idle;
5206 }
5207
5208 static void goya_hw_queues_lock(struct hl_device *hdev)
5209         __acquires(&goya->hw_queues_lock)
5210 {
5211         struct goya_device *goya = hdev->asic_specific;
5212
5213         spin_lock(&goya->hw_queues_lock);
5214 }
5215
5216 static void goya_hw_queues_unlock(struct hl_device *hdev)
5217         __releases(&goya->hw_queues_lock)
5218 {
5219         struct goya_device *goya = hdev->asic_specific;
5220
5221         spin_unlock(&goya->hw_queues_lock);
5222 }
5223
5224 static u32 goya_get_pci_id(struct hl_device *hdev)
5225 {
5226         return hdev->pdev->device;
5227 }
5228
5229 static int goya_get_eeprom_data(struct hl_device *hdev, void *data,
5230                                 size_t max_size)
5231 {
5232         struct goya_device *goya = hdev->asic_specific;
5233
5234         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5235                 return 0;
5236
5237         return hl_fw_get_eeprom_data(hdev, data, max_size);
5238 }
5239
5240 static void goya_cpu_init_scrambler_dram(struct hl_device *hdev)
5241 {
5242
5243 }
5244
5245 static int goya_ctx_init(struct hl_ctx *ctx)
5246 {
5247         if (ctx->asid != HL_KERNEL_ASID_ID)
5248                 goya_mmu_prepare(ctx->hdev, ctx->asid);
5249
5250         return 0;
5251 }
5252
5253 static int goya_pre_schedule_cs(struct hl_cs *cs)
5254 {
5255         return 0;
5256 }
5257
5258 u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx)
5259 {
5260         return cq_idx;
5261 }
5262
5263 static u32 goya_get_signal_cb_size(struct hl_device *hdev)
5264 {
5265         return 0;
5266 }
5267
5268 static u32 goya_get_wait_cb_size(struct hl_device *hdev)
5269 {
5270         return 0;
5271 }
5272
5273 static u32 goya_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id,
5274                                 u32 size, bool eb)
5275 {
5276         return 0;
5277 }
5278
5279 static u32 goya_gen_wait_cb(struct hl_device *hdev,
5280                 struct hl_gen_wait_properties *prop)
5281 {
5282         return 0;
5283 }
5284
5285 static void goya_reset_sob(struct hl_device *hdev, void *data)
5286 {
5287
5288 }
5289
5290 static void goya_reset_sob_group(struct hl_device *hdev, u16 sob_group)
5291 {
5292
5293 }
5294
5295 u64 goya_get_device_time(struct hl_device *hdev)
5296 {
5297         u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32;
5298
5299         return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL);
5300 }
5301
5302 static int goya_collective_wait_init_cs(struct hl_cs *cs)
5303 {
5304         return 0;
5305 }
5306
5307 static int goya_collective_wait_create_jobs(struct hl_device *hdev,
5308                 struct hl_ctx *ctx, struct hl_cs *cs, u32 wait_queue_id,
5309                 u32 collective_engine_id, u32 encaps_signal_offset)
5310 {
5311         return -EINVAL;
5312 }
5313
5314 static void goya_ctx_fini(struct hl_ctx *ctx)
5315 {
5316
5317 }
5318
5319 static int goya_get_hw_block_id(struct hl_device *hdev, u64 block_addr,
5320                         u32 *block_size, u32 *block_id)
5321 {
5322         return -EPERM;
5323 }
5324
5325 static int goya_block_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
5326                                 u32 block_id, u32 block_size)
5327 {
5328         return -EPERM;
5329 }
5330
5331 static void goya_enable_events_from_fw(struct hl_device *hdev)
5332 {
5333         WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
5334                         GOYA_ASYNC_EVENT_ID_INTS_REGISTER);
5335 }
5336
5337 static int goya_ack_mmu_page_fault_or_access_error(struct hl_device *hdev, u64 mmu_cap_mask)
5338 {
5339         return -EINVAL;
5340 }
5341
5342 static int goya_map_pll_idx_to_fw_idx(u32 pll_idx)
5343 {
5344         switch (pll_idx) {
5345         case HL_GOYA_CPU_PLL: return CPU_PLL;
5346         case HL_GOYA_PCI_PLL: return PCI_PLL;
5347         case HL_GOYA_MME_PLL: return MME_PLL;
5348         case HL_GOYA_TPC_PLL: return TPC_PLL;
5349         case HL_GOYA_IC_PLL: return IC_PLL;
5350         case HL_GOYA_MC_PLL: return MC_PLL;
5351         case HL_GOYA_EMMC_PLL: return EMMC_PLL;
5352         default: return -EINVAL;
5353         }
5354 }
5355
5356 static int goya_gen_sync_to_engine_map(struct hl_device *hdev,
5357                                 struct hl_sync_to_engine_map *map)
5358 {
5359         /* Not implemented */
5360         return 0;
5361 }
5362
5363 static int goya_monitor_valid(struct hl_mon_state_dump *mon)
5364 {
5365         /* Not implemented */
5366         return 0;
5367 }
5368
5369 static int goya_print_single_monitor(char **buf, size_t *size, size_t *offset,
5370                                 struct hl_device *hdev,
5371                                 struct hl_mon_state_dump *mon)
5372 {
5373         /* Not implemented */
5374         return 0;
5375 }
5376
5377
5378 static int goya_print_fences_single_engine(
5379         struct hl_device *hdev, u64 base_offset, u64 status_base_offset,
5380         enum hl_sync_engine_type engine_type, u32 engine_id, char **buf,
5381         size_t *size, size_t *offset)
5382 {
5383         /* Not implemented */
5384         return 0;
5385 }
5386
5387
5388 static struct hl_state_dump_specs_funcs goya_state_dump_funcs = {
5389         .monitor_valid = goya_monitor_valid,
5390         .print_single_monitor = goya_print_single_monitor,
5391         .gen_sync_to_engine_map = goya_gen_sync_to_engine_map,
5392         .print_fences_single_engine = goya_print_fences_single_engine,
5393 };
5394
5395 static void goya_state_dump_init(struct hl_device *hdev)
5396 {
5397         /* Not implemented */
5398         hdev->state_dump_specs.props = goya_state_dump_specs_props;
5399         hdev->state_dump_specs.funcs = goya_state_dump_funcs;
5400 }
5401
5402 static u32 goya_get_sob_addr(struct hl_device *hdev, u32 sob_id)
5403 {
5404         return 0;
5405 }
5406
5407 static u32 *goya_get_stream_master_qid_arr(void)
5408 {
5409         return NULL;
5410 }
5411
5412 static int goya_get_monitor_dump(struct hl_device *hdev, void *data)
5413 {
5414         return -EOPNOTSUPP;
5415 }
5416
5417 static void goya_check_if_razwi_happened(struct hl_device *hdev)
5418 {
5419 }
5420
5421 static int goya_scrub_device_dram(struct hl_device *hdev, u64 val)
5422 {
5423         return -EOPNOTSUPP;
5424 }
5425
5426 static int goya_set_dram_properties(struct hl_device *hdev)
5427 {
5428         return 0;
5429 }
5430
5431 static int goya_set_binning_masks(struct hl_device *hdev)
5432 {
5433         return 0;
5434 }
5435
5436 static int goya_send_device_activity(struct hl_device *hdev, bool open)
5437 {
5438         return 0;
5439 }
5440
5441 static const struct hl_asic_funcs goya_funcs = {
5442         .early_init = goya_early_init,
5443         .early_fini = goya_early_fini,
5444         .late_init = goya_late_init,
5445         .late_fini = goya_late_fini,
5446         .sw_init = goya_sw_init,
5447         .sw_fini = goya_sw_fini,
5448         .hw_init = goya_hw_init,
5449         .hw_fini = goya_hw_fini,
5450         .halt_engines = goya_halt_engines,
5451         .suspend = goya_suspend,
5452         .resume = goya_resume,
5453         .mmap = goya_mmap,
5454         .ring_doorbell = goya_ring_doorbell,
5455         .pqe_write = goya_pqe_write,
5456         .asic_dma_alloc_coherent = goya_dma_alloc_coherent,
5457         .asic_dma_free_coherent = goya_dma_free_coherent,
5458         .scrub_device_mem = goya_scrub_device_mem,
5459         .scrub_device_dram = goya_scrub_device_dram,
5460         .get_int_queue_base = goya_get_int_queue_base,
5461         .test_queues = goya_test_queues,
5462         .asic_dma_pool_zalloc = goya_dma_pool_zalloc,
5463         .asic_dma_pool_free = goya_dma_pool_free,
5464         .cpu_accessible_dma_pool_alloc = goya_cpu_accessible_dma_pool_alloc,
5465         .cpu_accessible_dma_pool_free = goya_cpu_accessible_dma_pool_free,
5466         .dma_unmap_sgtable = hl_asic_dma_unmap_sgtable,
5467         .cs_parser = goya_cs_parser,
5468         .dma_map_sgtable = hl_asic_dma_map_sgtable,
5469         .add_end_of_cb_packets = goya_add_end_of_cb_packets,
5470         .update_eq_ci = goya_update_eq_ci,
5471         .context_switch = goya_context_switch,
5472         .restore_phase_topology = goya_restore_phase_topology,
5473         .debugfs_read_dma = goya_debugfs_read_dma,
5474         .add_device_attr = goya_add_device_attr,
5475         .handle_eqe = goya_handle_eqe,
5476         .get_events_stat = goya_get_events_stat,
5477         .read_pte = goya_read_pte,
5478         .write_pte = goya_write_pte,
5479         .mmu_invalidate_cache = goya_mmu_invalidate_cache,
5480         .mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range,
5481         .mmu_prefetch_cache_range = NULL,
5482         .send_heartbeat = goya_send_heartbeat,
5483         .debug_coresight = goya_debug_coresight,
5484         .is_device_idle = goya_is_device_idle,
5485         .compute_reset_late_init = goya_compute_reset_late_init,
5486         .hw_queues_lock = goya_hw_queues_lock,
5487         .hw_queues_unlock = goya_hw_queues_unlock,
5488         .get_pci_id = goya_get_pci_id,
5489         .get_eeprom_data = goya_get_eeprom_data,
5490         .get_monitor_dump = goya_get_monitor_dump,
5491         .send_cpu_message = goya_send_cpu_message,
5492         .pci_bars_map = goya_pci_bars_map,
5493         .init_iatu = goya_init_iatu,
5494         .rreg = hl_rreg,
5495         .wreg = hl_wreg,
5496         .halt_coresight = goya_halt_coresight,
5497         .ctx_init = goya_ctx_init,
5498         .ctx_fini = goya_ctx_fini,
5499         .pre_schedule_cs = goya_pre_schedule_cs,
5500         .get_queue_id_for_cq = goya_get_queue_id_for_cq,
5501         .load_firmware_to_device = goya_load_firmware_to_device,
5502         .load_boot_fit_to_device = goya_load_boot_fit_to_device,
5503         .get_signal_cb_size = goya_get_signal_cb_size,
5504         .get_wait_cb_size = goya_get_wait_cb_size,
5505         .gen_signal_cb = goya_gen_signal_cb,
5506         .gen_wait_cb = goya_gen_wait_cb,
5507         .reset_sob = goya_reset_sob,
5508         .reset_sob_group = goya_reset_sob_group,
5509         .get_device_time = goya_get_device_time,
5510         .pb_print_security_errors = NULL,
5511         .collective_wait_init_cs = goya_collective_wait_init_cs,
5512         .collective_wait_create_jobs = goya_collective_wait_create_jobs,
5513         .get_dec_base_addr = NULL,
5514         .scramble_addr = hl_mmu_scramble_addr,
5515         .descramble_addr = hl_mmu_descramble_addr,
5516         .ack_protection_bits_errors = goya_ack_protection_bits_errors,
5517         .get_hw_block_id = goya_get_hw_block_id,
5518         .hw_block_mmap = goya_block_mmap,
5519         .enable_events_from_fw = goya_enable_events_from_fw,
5520         .ack_mmu_errors = goya_ack_mmu_page_fault_or_access_error,
5521         .map_pll_idx_to_fw_idx = goya_map_pll_idx_to_fw_idx,
5522         .init_firmware_preload_params = goya_init_firmware_preload_params,
5523         .init_firmware_loader = goya_init_firmware_loader,
5524         .init_cpu_scrambler_dram = goya_cpu_init_scrambler_dram,
5525         .state_dump_init = goya_state_dump_init,
5526         .get_sob_addr = &goya_get_sob_addr,
5527         .set_pci_memory_regions = goya_set_pci_memory_regions,
5528         .get_stream_master_qid_arr = goya_get_stream_master_qid_arr,
5529         .check_if_razwi_happened = goya_check_if_razwi_happened,
5530         .mmu_get_real_page_size = hl_mmu_get_real_page_size,
5531         .access_dev_mem = hl_access_dev_mem,
5532         .set_dram_bar_base = goya_set_ddr_bar_base,
5533         .send_device_activity = goya_send_device_activity,
5534         .set_dram_properties = goya_set_dram_properties,
5535         .set_binning_masks = goya_set_binning_masks,
5536 };
5537
5538 /*
5539  * goya_set_asic_funcs - set Goya function pointers
5540  *
5541  * @*hdev: pointer to hl_device structure
5542  *
5543  */
5544 void goya_set_asic_funcs(struct hl_device *hdev)
5545 {
5546         hdev->asic_funcs = &goya_funcs;
5547 }