1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Express I/O Virtualization (IOV) support
4 * Address Translation Service 1.0
5 * Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
6 * PASID support added by Joerg Roedel <joerg.roedel@amd.com>
8 * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
9 * Copyright (C) 2011 Advanced Micro Devices,
12 #include <linux/export.h>
13 #include <linux/pci-ats.h>
14 #include <linux/pci.h>
15 #include <linux/slab.h>
19 void pci_ats_init(struct pci_dev *dev)
23 if (pci_ats_disabled())
26 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
34 * pci_ats_supported - check if the device can use ATS
35 * @dev: the PCI device
37 * Returns true if the device supports ATS and is allowed to use it, false
40 bool pci_ats_supported(struct pci_dev *dev)
45 return (dev->untrusted == 0);
47 EXPORT_SYMBOL_GPL(pci_ats_supported);
50 * pci_enable_ats - enable the ATS capability
51 * @dev: the PCI device
52 * @ps: the IOMMU page shift
54 * Returns 0 on success, or negative on failure.
56 int pci_enable_ats(struct pci_dev *dev, int ps)
61 if (!pci_ats_supported(dev))
64 if (WARN_ON(dev->ats_enabled))
67 if (ps < PCI_ATS_MIN_STU)
71 * Note that enabling ATS on a VF fails unless it's already enabled
72 * with the same STU on the PF.
74 ctrl = PCI_ATS_CTRL_ENABLE;
76 pdev = pci_physfn(dev);
77 if (pdev->ats_stu != ps)
81 ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
83 pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
88 EXPORT_SYMBOL_GPL(pci_enable_ats);
91 * pci_disable_ats - disable the ATS capability
92 * @dev: the PCI device
94 void pci_disable_ats(struct pci_dev *dev)
98 if (WARN_ON(!dev->ats_enabled))
101 pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl);
102 ctrl &= ~PCI_ATS_CTRL_ENABLE;
103 pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
105 dev->ats_enabled = 0;
107 EXPORT_SYMBOL_GPL(pci_disable_ats);
109 void pci_restore_ats_state(struct pci_dev *dev)
113 if (!dev->ats_enabled)
116 ctrl = PCI_ATS_CTRL_ENABLE;
118 ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
119 pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
123 * pci_ats_queue_depth - query the ATS Invalidate Queue Depth
124 * @dev: the PCI device
126 * Returns the queue depth on success, or negative on failure.
128 * The ATS spec uses 0 in the Invalidate Queue Depth field to
129 * indicate that the function can accept 32 Invalidate Request.
130 * But here we use the `real' values (i.e. 1~32) for the Queue
131 * Depth; and 0 indicates the function shares the Queue with
132 * other functions (doesn't exclusively own a Queue).
134 int pci_ats_queue_depth(struct pci_dev *dev)
144 pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap);
145 return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP;
149 * pci_ats_page_aligned - Return Page Aligned Request bit status.
150 * @pdev: the PCI device
152 * Returns 1, if the Untranslated Addresses generated by the device
153 * are always aligned or 0 otherwise.
155 * Per PCIe spec r4.0, sec 10.5.1.2, if the Page Aligned Request bit
156 * is set, it indicates the Untranslated Addresses generated by the
157 * device are always aligned to a 4096 byte boundary.
159 int pci_ats_page_aligned(struct pci_dev *pdev)
166 pci_read_config_word(pdev, pdev->ats_cap + PCI_ATS_CAP, &cap);
168 if (cap & PCI_ATS_CAP_PAGE_ALIGNED)
174 #ifdef CONFIG_PCI_PRI
175 void pci_pri_init(struct pci_dev *pdev)
179 pdev->pri_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
184 pci_read_config_word(pdev, pdev->pri_cap + PCI_PRI_STATUS, &status);
185 if (status & PCI_PRI_STATUS_PASID)
186 pdev->pasid_required = 1;
190 * pci_enable_pri - Enable PRI capability
191 * @ pdev: PCI device structure
193 * Returns 0 on success, negative value on error
195 int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
199 int pri = pdev->pri_cap;
202 * VFs must not implement the PRI Capability. If their PF
203 * implements PRI, it is shared by the VFs, so if the PF PRI is
204 * enabled, it is also enabled for the VF.
206 if (pdev->is_virtfn) {
207 if (pci_physfn(pdev)->pri_enabled)
212 if (WARN_ON(pdev->pri_enabled))
218 pci_read_config_word(pdev, pri + PCI_PRI_STATUS, &status);
219 if (!(status & PCI_PRI_STATUS_STOPPED))
222 pci_read_config_dword(pdev, pri + PCI_PRI_MAX_REQ, &max_requests);
223 reqs = min(max_requests, reqs);
224 pdev->pri_reqs_alloc = reqs;
225 pci_write_config_dword(pdev, pri + PCI_PRI_ALLOC_REQ, reqs);
227 control = PCI_PRI_CTRL_ENABLE;
228 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
230 pdev->pri_enabled = 1;
236 * pci_disable_pri - Disable PRI capability
237 * @pdev: PCI device structure
239 * Only clears the enabled-bit, regardless of its former value
241 void pci_disable_pri(struct pci_dev *pdev)
244 int pri = pdev->pri_cap;
246 /* VFs share the PF PRI */
250 if (WARN_ON(!pdev->pri_enabled))
256 pci_read_config_word(pdev, pri + PCI_PRI_CTRL, &control);
257 control &= ~PCI_PRI_CTRL_ENABLE;
258 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
260 pdev->pri_enabled = 0;
262 EXPORT_SYMBOL_GPL(pci_disable_pri);
265 * pci_restore_pri_state - Restore PRI
266 * @pdev: PCI device structure
268 void pci_restore_pri_state(struct pci_dev *pdev)
270 u16 control = PCI_PRI_CTRL_ENABLE;
271 u32 reqs = pdev->pri_reqs_alloc;
272 int pri = pdev->pri_cap;
277 if (!pdev->pri_enabled)
283 pci_write_config_dword(pdev, pri + PCI_PRI_ALLOC_REQ, reqs);
284 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
288 * pci_reset_pri - Resets device's PRI state
289 * @pdev: PCI device structure
291 * The PRI capability must be disabled before this function is called.
292 * Returns 0 on success, negative value on error.
294 int pci_reset_pri(struct pci_dev *pdev)
297 int pri = pdev->pri_cap;
302 if (WARN_ON(pdev->pri_enabled))
308 control = PCI_PRI_CTRL_RESET;
309 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
315 * pci_prg_resp_pasid_required - Return PRG Response PASID Required bit
317 * @pdev: PCI device structure
319 * Returns 1 if PASID is required in PRG Response Message, 0 otherwise.
321 int pci_prg_resp_pasid_required(struct pci_dev *pdev)
324 pdev = pci_physfn(pdev);
326 return pdev->pasid_required;
328 #endif /* CONFIG_PCI_PRI */
330 #ifdef CONFIG_PCI_PASID
331 void pci_pasid_init(struct pci_dev *pdev)
333 pdev->pasid_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
337 * pci_enable_pasid - Enable the PASID capability
338 * @pdev: PCI device structure
339 * @features: Features to enable
341 * Returns 0 on success, negative value on error. This function checks
342 * whether the features are actually supported by the device and returns
345 int pci_enable_pasid(struct pci_dev *pdev, int features)
347 u16 control, supported;
348 int pasid = pdev->pasid_cap;
351 * VFs must not implement the PASID Capability, but if a PF
352 * supports PASID, its VFs share the PF PASID configuration.
354 if (pdev->is_virtfn) {
355 if (pci_physfn(pdev)->pasid_enabled)
360 if (WARN_ON(pdev->pasid_enabled))
363 if (!pdev->eetlp_prefix_path)
369 pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported);
370 supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
372 /* User wants to enable anything unsupported? */
373 if ((supported & features) != features)
376 control = PCI_PASID_CTRL_ENABLE | features;
377 pdev->pasid_features = features;
379 pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control);
381 pdev->pasid_enabled = 1;
385 EXPORT_SYMBOL_GPL(pci_enable_pasid);
388 * pci_disable_pasid - Disable the PASID capability
389 * @pdev: PCI device structure
391 void pci_disable_pasid(struct pci_dev *pdev)
394 int pasid = pdev->pasid_cap;
396 /* VFs share the PF PASID configuration */
400 if (WARN_ON(!pdev->pasid_enabled))
406 pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control);
408 pdev->pasid_enabled = 0;
410 EXPORT_SYMBOL_GPL(pci_disable_pasid);
413 * pci_restore_pasid_state - Restore PASID capabilities
414 * @pdev: PCI device structure
416 void pci_restore_pasid_state(struct pci_dev *pdev)
419 int pasid = pdev->pasid_cap;
424 if (!pdev->pasid_enabled)
430 control = PCI_PASID_CTRL_ENABLE | pdev->pasid_features;
431 pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control);
435 * pci_pasid_features - Check which PASID features are supported
436 * @pdev: PCI device structure
438 * Returns a negative value when no PASI capability is present.
439 * Otherwise is returns a bitmask with supported features. Current
440 * features reported are:
441 * PCI_PASID_CAP_EXEC - Execute permission supported
442 * PCI_PASID_CAP_PRIV - Privileged mode supported
444 int pci_pasid_features(struct pci_dev *pdev)
450 pdev = pci_physfn(pdev);
452 pasid = pdev->pasid_cap;
456 pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported);
458 supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
462 EXPORT_SYMBOL_GPL(pci_pasid_features);
464 #define PASID_NUMBER_SHIFT 8
465 #define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT)
467 * pci_max_pasid - Get maximum number of PASIDs supported by device
468 * @pdev: PCI device structure
470 * Returns negative value when PASID capability is not present.
471 * Otherwise it returns the number of supported PASIDs.
473 int pci_max_pasids(struct pci_dev *pdev)
479 pdev = pci_physfn(pdev);
481 pasid = pdev->pasid_cap;
485 pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported);
487 supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;
489 return (1 << supported);
491 EXPORT_SYMBOL_GPL(pci_max_pasids);
492 #endif /* CONFIG_PCI_PASID */