4 * Extracted from init.c
6 #include <linux/percpu.h>
7 #include <linux/init.h>
8 #include <linux/string.h>
9 #include <linux/slab.h>
10 #include <linux/cache.h>
13 #include <asm/tlbflush.h>
14 #include <asm/mmu_context.h>
16 #include <asm/initialize_mmu.h>
19 void __init paging_init(void)
21 memset(swapper_pg_dir, 0, PAGE_SIZE);
25 * Flush the mmu and reset associated register to default values.
29 #if !(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
31 * Writing zeros to the instruction and data TLBCFG special
32 * registers ensure that valid values exist in the register.
34 * For existing PGSZID<w> fields, zero selects the first element
35 * of the page-size array. For nonexistent PGSZID<w> fields,
36 * zero is the best value to write. Also, when changing PGSZID<w>
37 * fields, the corresponding TLB must be flushed.
39 set_itlbcfg_register(0);
40 set_dtlbcfg_register(0);
42 #if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && defined(CONFIG_OF)
44 * Update the IO area mapping in case xtensa_kio_paddr has changed
46 write_dtlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
47 XCHAL_KIO_CACHED_VADDR + 6);
48 write_itlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
49 XCHAL_KIO_CACHED_VADDR + 6);
50 write_dtlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
51 XCHAL_KIO_BYPASS_VADDR + 6);
52 write_itlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
53 XCHAL_KIO_BYPASS_VADDR + 6);
56 local_flush_tlb_all();
58 /* Set rasid register to a known value. */
60 set_rasid_register(ASID_INSERT(ASID_USER_FIRST));
62 /* Set PTEVADDR special register to the start of the page
63 * table, which is in kernel mappable space (ie. not
64 * statically mapped). This register's value is undefined on
67 set_ptevaddr_register(PGTABLE_START);