2 * arch/xtensa/mm/cache.c
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2001-2006 Tensilica Inc.
10 * Chris Zankel <chris@zankel.net>
16 #include <linux/init.h>
17 #include <linux/signal.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/string.h>
22 #include <linux/types.h>
23 #include <linux/ptrace.h>
24 #include <linux/memblock.h>
25 #include <linux/swap.h>
26 #include <linux/pagemap.h>
27 #include <linux/pgtable.h>
29 #include <asm/bootparam.h>
30 #include <asm/mmu_context.h>
32 #include <asm/tlbflush.h>
37 * The kernel provides one architecture bit PG_arch_1 in the page flags that
38 * can be used for cache coherency.
42 * The Xtensa architecture doesn't keep the instruction cache coherent with
43 * the data cache. We use the architecture bit to indicate if the caches
44 * are coherent. The kernel clears this bit whenever a page is added to the
45 * page cache. At that time, the caches might not be in sync. We, therefore,
46 * define this flag as 'clean' if set.
50 * With cache aliasing, we have to always flush the cache when pages are
51 * unmapped (see tlb_start_vma(). So, we use this flag to indicate a dirty
58 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
59 static inline void kmap_invalidate_coherent(struct page *page,
62 if (!DCACHE_ALIAS_EQ(page_to_phys(page), vaddr)) {
65 if (!PageHighMem(page)) {
66 kvaddr = (unsigned long)page_to_virt(page);
68 __invalidate_dcache_page(kvaddr);
70 kvaddr = TLBTEMP_BASE_1 +
71 (page_to_phys(page) & DCACHE_ALIAS_MASK);
74 __invalidate_dcache_page_alias(kvaddr,
81 static inline void *coherent_kvaddr(struct page *page, unsigned long base,
82 unsigned long vaddr, unsigned long *paddr)
84 if (PageHighMem(page) || !DCACHE_ALIAS_EQ(page_to_phys(page), vaddr)) {
85 *paddr = page_to_phys(page);
86 return (void *)(base + (vaddr & DCACHE_ALIAS_MASK));
89 return page_to_virt(page);
93 void clear_user_highpage(struct page *page, unsigned long vaddr)
96 void *kvaddr = coherent_kvaddr(page, TLBTEMP_BASE_1, vaddr, &paddr);
99 kmap_invalidate_coherent(page, vaddr);
100 set_bit(PG_arch_1, &page->flags);
101 clear_page_alias(kvaddr, paddr);
104 EXPORT_SYMBOL(clear_user_highpage);
106 void copy_user_highpage(struct page *dst, struct page *src,
107 unsigned long vaddr, struct vm_area_struct *vma)
109 unsigned long dst_paddr, src_paddr;
110 void *dst_vaddr = coherent_kvaddr(dst, TLBTEMP_BASE_1, vaddr,
112 void *src_vaddr = coherent_kvaddr(src, TLBTEMP_BASE_2, vaddr,
116 kmap_invalidate_coherent(dst, vaddr);
117 set_bit(PG_arch_1, &dst->flags);
118 copy_page_alias(dst_vaddr, src_vaddr, dst_paddr, src_paddr);
121 EXPORT_SYMBOL(copy_user_highpage);
124 * Any time the kernel writes to a user page cache page, or it is about to
125 * read from a page cache page this routine is called.
129 void flush_dcache_page(struct page *page)
131 struct address_space *mapping = page_mapping_file(page);
134 * If we have a mapping but the page is not mapped to user-space
135 * yet, we simply mark this page dirty and defer flushing the
136 * caches until update_mmu().
139 if (mapping && !mapping_mapped(mapping)) {
140 if (!test_bit(PG_arch_1, &page->flags))
141 set_bit(PG_arch_1, &page->flags);
146 unsigned long phys = page_to_phys(page);
147 unsigned long temp = page->index << PAGE_SHIFT;
148 unsigned long alias = !(DCACHE_ALIAS_EQ(temp, phys));
152 * Flush the page in kernel space and user space.
153 * Note that we can omit that step if aliasing is not
154 * an issue, but we do have to synchronize I$ and D$
155 * if we have a mapping.
158 if (!alias && !mapping)
162 virt = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK);
163 __flush_invalidate_dcache_page_alias(virt, phys);
165 virt = TLBTEMP_BASE_1 + (temp & DCACHE_ALIAS_MASK);
168 __flush_invalidate_dcache_page_alias(virt, phys);
171 __invalidate_icache_page_alias(virt, phys);
175 /* There shouldn't be an entry in the cache for this page anymore. */
177 EXPORT_SYMBOL(flush_dcache_page);
180 * For now, flush the whole cache. FIXME??
183 void local_flush_cache_range(struct vm_area_struct *vma,
184 unsigned long start, unsigned long end)
186 __flush_invalidate_dcache_all();
187 __invalidate_icache_all();
189 EXPORT_SYMBOL(local_flush_cache_range);
192 * Remove any entry in the cache for this page.
194 * Note that this function is only called for user pages, so use the
195 * alias versions of the cache flush functions.
198 void local_flush_cache_page(struct vm_area_struct *vma, unsigned long address,
201 /* Note that we have to use the 'alias' address to avoid multi-hit */
203 unsigned long phys = page_to_phys(pfn_to_page(pfn));
204 unsigned long virt = TLBTEMP_BASE_1 + (address & DCACHE_ALIAS_MASK);
207 __flush_invalidate_dcache_page_alias(virt, phys);
208 __invalidate_icache_page_alias(virt, phys);
211 EXPORT_SYMBOL(local_flush_cache_page);
213 #endif /* DCACHE_WAY_SIZE > PAGE_SIZE */
216 update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep)
218 unsigned long pfn = pte_pfn(*ptep);
224 page = pfn_to_page(pfn);
226 /* Invalidate old entry in TLBs */
228 flush_tlb_page(vma, addr);
230 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
232 if (!PageReserved(page) && test_bit(PG_arch_1, &page->flags)) {
233 unsigned long phys = page_to_phys(page);
237 tmp = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK);
238 __flush_invalidate_dcache_page_alias(tmp, phys);
239 tmp = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK);
240 __flush_invalidate_dcache_page_alias(tmp, phys);
241 __invalidate_icache_page_alias(tmp, phys);
244 clear_bit(PG_arch_1, &page->flags);
247 if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags)
248 && (vma->vm_flags & VM_EXEC) != 0) {
249 unsigned long paddr = (unsigned long)kmap_atomic(page);
250 __flush_dcache_page(paddr);
251 __invalidate_icache_page(paddr);
252 set_bit(PG_arch_1, &page->flags);
253 kunmap_atomic((void *)paddr);
259 * access_process_vm() has called get_user_pages(), which has done a
260 * flush_dcache_page() on the page.
263 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
265 void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
266 unsigned long vaddr, void *dst, const void *src,
269 unsigned long phys = page_to_phys(page);
270 unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys));
272 /* Flush and invalidate user page if aliased. */
275 unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
277 __flush_invalidate_dcache_page_alias(t, phys);
283 memcpy(dst, src, len);
286 * Flush and invalidate kernel page if aliased and synchronize
287 * data and instruction caches for executable pages.
291 unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
294 __flush_invalidate_dcache_range((unsigned long) dst, len);
295 if ((vma->vm_flags & VM_EXEC) != 0)
296 __invalidate_icache_page_alias(t, phys);
299 } else if ((vma->vm_flags & VM_EXEC) != 0) {
300 __flush_dcache_range((unsigned long)dst,len);
301 __invalidate_icache_range((unsigned long) dst, len);
305 extern void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
306 unsigned long vaddr, void *dst, const void *src,
309 unsigned long phys = page_to_phys(page);
310 unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys));
313 * Flush user page if aliased.
314 * (Note: a simply flush would be sufficient)
318 unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
320 __flush_invalidate_dcache_page_alias(t, phys);
324 memcpy(dst, src, len);