2 * Low-level exception handling
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2004 - 2008 by Tensilica Inc.
9 * Copyright (C) 2015 Cadence Design Systems Inc.
11 * Chris Zankel <chris@zankel.net>
15 #include <linux/linkage.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/asmmacro.h>
18 #include <asm/processor.h>
19 #include <asm/coprocessor.h>
20 #include <asm/thread_info.h>
21 #include <asm/asm-uaccess.h>
22 #include <asm/unistd.h>
23 #include <asm/ptrace.h>
24 #include <asm/current.h>
25 #include <asm/pgtable.h>
27 #include <asm/signal.h>
28 #include <asm/tlbflush.h>
29 #include <variant/tie-asm.h>
31 /* Unimplemented features. */
33 #undef KERNEL_STACK_OVERFLOW_CHECK
41 * Macro to find first bit set in WINDOWBASE from the left + 1
48 .macro ffs_ws bit mask
51 nsau \bit, \mask # 32-WSBITS ... 31 (32 iff 0)
52 addi \bit, \bit, WSBITS - 32 + 1 # uppest bit set -> return 1
56 _bltui \mask, 0x10000, 99f
58 extui \mask, \mask, 16, 16
61 99: _bltui \mask, 0x100, 99f
65 99: _bltui \mask, 0x10, 99f
68 99: _bltui \mask, 0x4, 99f
71 99: _bltui \mask, 0x2, 99f
79 .macro irq_save flags tmp
81 #if defined(CONFIG_DEBUG_KERNEL) && (LOCKLEVEL | TOPLEVEL) >= XCHAL_DEBUGLEVEL
83 extui \tmp, \flags, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
84 bgei \tmp, LOCKLEVEL, 99f
90 or \flags, \flags, \tmp
95 rsil \flags, LOCKLEVEL
99 /* ----------------- DEFAULT FIRST LEVEL EXCEPTION HANDLERS ----------------- */
102 * First-level exception handler for user exceptions.
103 * Save some special registers, extra states and all registers in the AR
104 * register file that were in use in the user task, and jump to the common
106 * We save SAR (used to calculate WMASK), and WB and WS (we don't have to
107 * save them for kernel exceptions).
109 * Entry condition for user_exception:
111 * a0: trashed, original value saved on stack (PT_AREG0)
113 * a2: new stack pointer, original value in depc
115 * depc: a2, original value saved on stack (PT_DEPC)
116 * excsave1: dispatch table
118 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
119 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
121 * Entry condition for _user_exception:
123 * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC
124 * excsave has been restored, and
125 * stack pointer (a1) has been set.
127 * Note: _user_exception might be at an odd address. Don't use call0..call12
131 ENTRY(user_exception)
133 /* Save a1, a2, a3, and set SP. */
136 s32i a1, a2, PT_AREG1
137 s32i a0, a2, PT_AREG2
138 s32i a3, a2, PT_AREG3
141 .globl _user_exception
144 /* Save SAR and turn off single stepping */
147 wsr a2, depc # terminate user stack trace with 0
151 s32i a2, a1, PT_ICOUNTLEVEL
153 #if XCHAL_HAVE_THREADPTR
155 s32i a2, a1, PT_THREADPTR
158 /* Rotate ws so that the current windowbase is at bit0. */
159 /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
164 s32i a2, a1, PT_WINDOWBASE
165 s32i a3, a1, PT_WINDOWSTART
166 slli a2, a3, 32-WSBITS
168 srli a2, a2, 32-WSBITS
169 s32i a2, a1, PT_WMASK # needed for restoring registers
171 /* Save only live registers. */
174 s32i a4, a1, PT_AREG4
175 s32i a5, a1, PT_AREG5
176 s32i a6, a1, PT_AREG6
177 s32i a7, a1, PT_AREG7
179 s32i a8, a1, PT_AREG8
180 s32i a9, a1, PT_AREG9
181 s32i a10, a1, PT_AREG10
182 s32i a11, a1, PT_AREG11
184 s32i a12, a1, PT_AREG12
185 s32i a13, a1, PT_AREG13
186 s32i a14, a1, PT_AREG14
187 s32i a15, a1, PT_AREG15
188 _bnei a2, 1, 1f # only one valid frame?
190 /* Only one valid frame, skip saving regs. */
194 /* Save the remaining registers.
195 * We have to save all registers up to the first '1' from
196 * the right, except the current frame (bit 0).
197 * Assume a2 is: 001001000110001
198 * All register frames starting from the top field to the marked '1'
202 1: addi a3, a2, -1 # eliminate '1' in bit 0: yyyyxxww0
203 neg a3, a3 # yyyyxxww0 -> YYYYXXWW1+1
204 and a3, a3, a2 # max. only one bit is set
206 /* Find number of frames to save */
208 ffs_ws a0, a3 # number of frames to the '1' from left
210 /* Store information into WMASK:
211 * bits 0..3: xxx1 masked lower 4 bits of the rotated windowstart,
212 * bits 4...: number of valid 4-register frames
215 slli a3, a0, 4 # number of frames to save in bits 8..4
216 extui a2, a2, 0, 4 # mask for the first 16 registers
218 s32i a2, a1, PT_WMASK # needed when we restore the reg-file
220 /* Save 4 registers at a time */
223 s32i a0, a5, PT_AREG_END - 16
224 s32i a1, a5, PT_AREG_END - 12
225 s32i a2, a5, PT_AREG_END - 8
226 s32i a3, a5, PT_AREG_END - 4
231 /* WINDOWBASE still in SAR! */
233 rsr a2, sar # original WINDOWBASE
237 wsr a3, windowstart # set corresponding WINDOWSTART bit
238 wsr a2, windowbase # and WINDOWSTART
241 /* We are back to the original stack pointer (a1) */
243 2: /* Now, jump to the common exception handler. */
247 ENDPROC(user_exception)
250 * First-level exit handler for kernel exceptions
251 * Save special registers and the live window frame.
252 * Note: Even though we changes the stack pointer, we don't have to do a
253 * MOVSP here, as we do that when we return from the exception.
254 * (See comment in the kernel exception exit code)
256 * Entry condition for kernel_exception:
258 * a0: trashed, original value saved on stack (PT_AREG0)
260 * a2: new stack pointer, original in DEPC
262 * depc: a2, original value saved on stack (PT_DEPC)
263 * excsave_1: dispatch table
265 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
266 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
268 * Entry condition for _kernel_exception:
270 * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC
271 * excsave has been restored, and
272 * stack pointer (a1) has been set.
274 * Note: _kernel_exception might be at an odd address. Don't use call0..call12
277 ENTRY(kernel_exception)
279 /* Save a1, a2, a3, and set SP. */
281 rsr a0, depc # get a2
282 s32i a1, a2, PT_AREG1
283 s32i a0, a2, PT_AREG2
284 s32i a3, a2, PT_AREG3
287 .globl _kernel_exception
290 /* Save SAR and turn off single stepping */
296 s32i a2, a1, PT_ICOUNTLEVEL
298 /* Rotate ws so that the current windowbase is at bit0. */
299 /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
301 rsr a2, windowbase # don't need to save these, we only
302 rsr a3, windowstart # need shifted windowstart: windowmask
304 slli a2, a3, 32-WSBITS
306 srli a2, a2, 32-WSBITS
307 s32i a2, a1, PT_WMASK # needed for kernel_exception_exit
309 /* Save only the live window-frame */
312 s32i a4, a1, PT_AREG4
313 s32i a5, a1, PT_AREG5
314 s32i a6, a1, PT_AREG6
315 s32i a7, a1, PT_AREG7
317 s32i a8, a1, PT_AREG8
318 s32i a9, a1, PT_AREG9
319 s32i a10, a1, PT_AREG10
320 s32i a11, a1, PT_AREG11
322 s32i a12, a1, PT_AREG12
323 s32i a13, a1, PT_AREG13
324 s32i a14, a1, PT_AREG14
325 s32i a15, a1, PT_AREG15
329 /* Copy spill slots of a0 and a1 to imitate movsp
330 * in order to keep exception stack continuous
333 l32i a0, a1, PT_SIZE + 4
337 l32i a0, a1, PT_AREG0 # restore saved a0
340 #ifdef KERNEL_STACK_OVERFLOW_CHECK
342 /* Stack overflow check, for debugging */
343 extui a2, a1, TASK_SIZE_BITS,XX
345 _bge a2, a3, out_of_stack_panic
350 * This is the common exception handler.
351 * We get here from the user exception handler or simply by falling through
352 * from the kernel exception handler.
353 * Save the remaining special registers, switch to kernel mode, and jump
354 * to the second-level exception handler.
360 /* Save some registers, disable loops and clear the syscall flag. */
364 s32i a2, a1, PT_DEBUGCAUSE
369 s32i a2, a1, PT_SYSCALL
371 s32i a3, a1, PT_EXCVADDR
374 s32i a2, a1, PT_LCOUNT
377 /* It is now save to restore the EXC_TABLE_FIXUP variable. */
382 s32i a2, a1, PT_EXCCAUSE
383 s32i a3, a0, EXC_TABLE_FIXUP
385 /* All unrecoverable states are saved on stack, now, and a1 is valid.
386 * Now we can allow exceptions again. In case we've got an interrupt
387 * PS.INTLEVEL is set to LOCKLEVEL disabling furhter interrupts,
388 * otherwise it's left unchanged.
390 * Set PS(EXCM = 0, UM = 0, RING = 0, OWB = 0, WOE = 1, INTLEVEL = X)
394 s32i a3, a1, PT_PS # save ps
397 /* Correct PS needs to be saved in the PT_PS:
398 * - in case of exception or level-1 interrupt it's in the PS,
399 * and is already saved.
400 * - in case of medium level interrupt it's in the excsave2.
402 movi a0, EXCCAUSE_MAPPED_NMI
403 extui a3, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
404 beq a2, a0, .Lmedium_level_irq
405 bnei a2, EXCCAUSE_LEVEL1_INTERRUPT, .Lexception
406 beqz a3, .Llevel1_irq # level-1 IRQ sets ps.intlevel to 0
410 s32i a0, a1, PT_PS # save medium-level interrupt ps
411 bgei a3, LOCKLEVEL, .Lexception
417 movi a0, 1 << PS_WOE_BIT
420 addi a2, a2, -EXCCAUSE_LEVEL1_INTERRUPT
422 extui a3, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
424 moveqz a3, a0, a2 # a3 = LOCKLEVEL iff interrupt
425 movi a2, 1 << PS_WOE_BIT
430 /* restore return address (or 0 if return to userspace) */
433 rsync # PS.WOE => rsync => overflow
435 /* Save lbeg, lend */
445 #if XCHAL_HAVE_S32C1I
447 s32i a3, a1, PT_SCOMPARE1
450 /* Save optional registers. */
452 save_xtregs_opt a1 a3 a4 a5 a6 a7 PT_XTREGS_OPT
454 /* Go to second-level dispatcher. Set up parameters to pass to the
455 * exception handler and call the exception handler.
459 mov a6, a1 # pass stack frame
460 mov a7, a2 # pass EXCCAUSE
462 l32i a4, a4, EXC_TABLE_DEFAULT # load handler
464 /* Call the second-level handler */
468 /* Jump here for exception exit */
469 .global common_exception_return
470 common_exception_return:
473 l32i a2, a1, PT_EXCCAUSE
474 movi a3, EXCCAUSE_MAPPED_NMI
475 beq a2, a3, .LNMIexit
479 #ifdef CONFIG_TRACE_IRQFLAGS
480 call4 trace_hardirqs_off
483 /* Jump if we are returning from kernel exceptions. */
486 GET_THREAD_INFO(a2, a1)
487 l32i a4, a2, TI_FLAGS
488 _bbci.l a3, PS_UM_BIT, 6f
490 /* Specific to a user exception exit:
491 * We need to check some flags for signal handling and rescheduling,
492 * and have to restore WB and WS, extra states, and all registers
493 * in the register file that were in use in the user task.
494 * Note that we don't disable interrupts here.
497 _bbsi.l a4, TIF_NEED_RESCHED, 3f
498 _bbsi.l a4, TIF_NOTIFY_RESUME, 2f
499 _bbci.l a4, TIF_SIGPENDING, 5f
501 2: l32i a4, a1, PT_DEPC
502 bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 4f
504 /* Call do_signal() */
506 #ifdef CONFIG_TRACE_IRQFLAGS
507 call4 trace_hardirqs_on
511 call4 do_notify_resume # int do_notify_resume(struct pt_regs*)
516 #ifdef CONFIG_TRACE_IRQFLAGS
517 call4 trace_hardirqs_on
520 call4 schedule # void schedule (void)
523 #ifdef CONFIG_PREEMPT
525 _bbci.l a4, TIF_NEED_RESCHED, 4f
527 /* Check current_thread_info->preempt_count */
529 l32i a4, a2, TI_PRE_COUNT
531 call4 preempt_schedule_irq
538 _bbci.l a3, PS_UM_BIT, 4f
542 #ifdef CONFIG_HAVE_HW_BREAKPOINT
543 _bbci.l a4, TIF_DB_DISABLED, 7f
547 #ifdef CONFIG_DEBUG_TLB_SANITY
549 bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 4f
550 call4 check_tlb_sanity
554 #ifdef CONFIG_TRACE_IRQFLAGS
555 extui a4, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
556 bgei a4, LOCKLEVEL, 1f
557 call4 trace_hardirqs_on
560 /* Restore optional registers. */
562 load_xtregs_opt a1 a2 a4 a5 a6 a7 PT_XTREGS_OPT
564 /* Restore SCOMPARE1 */
566 #if XCHAL_HAVE_S32C1I
567 l32i a2, a1, PT_SCOMPARE1
570 wsr a3, ps /* disable interrupts */
572 _bbci.l a3, PS_UM_BIT, kernel_exception_exit
576 /* Restore the state of the task and return from the exception. */
578 /* Switch to the user thread WINDOWBASE. Save SP temporarily in DEPC */
580 l32i a2, a1, PT_WINDOWBASE
581 l32i a3, a1, PT_WINDOWSTART
582 wsr a1, depc # use DEPC as temp storage
583 wsr a3, windowstart # restore WINDOWSTART
584 ssr a2 # preserve user's WB in the SAR
585 wsr a2, windowbase # switch to user's saved WB
587 rsr a1, depc # restore stack pointer
588 l32i a2, a1, PT_WMASK # register frames saved (in bits 4...9)
589 rotw -1 # we restore a4..a7
590 _bltui a6, 16, 1f # only have to restore current window?
592 /* The working registers are a0 and a3. We are restoring to
593 * a4..a7. Be careful not to destroy what we have just restored.
594 * Note: wmask has the format YYYYM:
595 * Y: number of registers saved in groups of 4
596 * M: 4 bit mask of first 16 registers
602 2: rotw -1 # a0..a3 become a4..a7
603 addi a3, a7, -4*4 # next iteration
604 addi a2, a6, -16 # decrementing Y in WMASK
605 l32i a4, a3, PT_AREG_END + 0
606 l32i a5, a3, PT_AREG_END + 4
607 l32i a6, a3, PT_AREG_END + 8
608 l32i a7, a3, PT_AREG_END + 12
611 /* Clear unrestored registers (don't leak anything to user-land */
613 1: rsr a0, windowbase
617 extui a3, a3, 0, WBBITS
627 /* We are back were we were when we started.
628 * Note: a2 still contains WMASK (if we've returned to the original
629 * frame where we had loaded a2), or at least the lower 4 bits
630 * (if we have restored WSBITS-1 frames).
634 #if XCHAL_HAVE_THREADPTR
635 l32i a3, a1, PT_THREADPTR
639 j common_exception_exit
641 /* This is the kernel exception exit.
642 * We avoided to do a MOVSP when we entered the exception, but we
643 * have to do it here.
646 kernel_exception_exit:
648 /* Check if we have to do a movsp.
650 * We only have to do a movsp if the previous window-frame has
651 * been spilled to the *temporary* exception stack instead of the
652 * task's stack. This is the case if the corresponding bit in
653 * WINDOWSTART for the previous window-frame was set before
654 * (not spilled) but is zero now (spilled).
655 * If this bit is zero, all other bits except the one for the
656 * current window frame are also zero. So, we can use a simple test:
657 * 'and' WINDOWSTART and WINDOWSTART-1:
659 * (XXXXXX1[0]* - 1) AND XXXXXX1[0]* = XXXXXX0[0]*
661 * The result is zero only if one bit was set.
663 * (Note: We might have gone through several task switches before
664 * we come back to the current task, so WINDOWBASE might be
665 * different from the time the exception occurred.)
668 /* Test WINDOWSTART before and after the exception.
669 * We actually have WMASK, so we only have to test if it is 1 or not.
672 l32i a2, a1, PT_WMASK
673 _beqi a2, 1, common_exception_exit # Spilled before exception,jump
675 /* Test WINDOWSTART now. If spilled, do the movsp */
680 _bnez a3, common_exception_exit
682 /* Do a movsp (we returned from a call4, so we have at least a0..a7) */
687 s32i a3, a1, PT_SIZE+0
688 s32i a4, a1, PT_SIZE+4
691 s32i a3, a1, PT_SIZE+8
692 s32i a4, a1, PT_SIZE+12
694 /* Common exception exit.
695 * We restore the special register and the current window frame, and
696 * return from the exception.
698 * Note: We expect a2 to hold PT_WMASK
701 common_exception_exit:
703 /* Restore address registers. */
706 l32i a4, a1, PT_AREG4
707 l32i a5, a1, PT_AREG5
708 l32i a6, a1, PT_AREG6
709 l32i a7, a1, PT_AREG7
711 l32i a8, a1, PT_AREG8
712 l32i a9, a1, PT_AREG9
713 l32i a10, a1, PT_AREG10
714 l32i a11, a1, PT_AREG11
716 l32i a12, a1, PT_AREG12
717 l32i a13, a1, PT_AREG13
718 l32i a14, a1, PT_AREG14
719 l32i a15, a1, PT_AREG15
721 /* Restore PC, SAR */
723 1: l32i a2, a1, PT_PC
728 /* Restore LBEG, LEND, LCOUNT */
733 l32i a2, a1, PT_LCOUNT
738 /* We control single stepping through the ICOUNTLEVEL register. */
740 l32i a2, a1, PT_ICOUNTLEVEL
745 /* Check if it was double exception. */
748 l32i a3, a1, PT_AREG3
749 l32i a2, a1, PT_AREG2
750 _bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
752 /* Restore a0...a3 and return */
754 l32i a0, a1, PT_AREG0
755 l32i a1, a1, PT_AREG1
759 l32i a0, a1, PT_AREG0
760 l32i a1, a1, PT_AREG1
763 ENDPROC(kernel_exception)
766 * Debug exception handler.
768 * Currently, we don't support KGDB, so only user application can be debugged.
770 * When we get here, a0 is trashed and saved to excsave[debuglevel]
775 ENTRY(debug_exception)
777 rsr a0, SREG_EPS + XCHAL_DEBUGLEVEL
778 bbsi.l a0, PS_EXCM_BIT, 1f # exception mode
780 /* Set EPC1 and EXCCAUSE */
782 wsr a2, depc # save a2 temporarily
783 rsr a2, SREG_EPC + XCHAL_DEBUGLEVEL
786 movi a2, EXCCAUSE_MAPPED_DEBUG
789 /* Restore PS to the value before the debug exc but with PS.EXCM set.*/
791 movi a2, 1 << PS_EXCM_BIT
795 /* Switch to kernel/user stack, restore jump vector, and save a0 */
797 bbsi.l a2, PS_UM_BIT, 2f # jump if user mode
799 addi a2, a1, -16-PT_SIZE # assume kernel stack
801 l32i a0, a3, DT_DEBUG_SAVE
802 s32i a1, a2, PT_AREG1
803 s32i a0, a2, PT_AREG0
805 s32i a0, a2, PT_DEPC # mark it as a regular exception
806 xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
808 s32i a3, a2, PT_AREG3
809 s32i a0, a2, PT_AREG2
812 /* Debug exception is handled as an exception, so interrupts will
813 * likely be enabled in the common exception handler. Disable
814 * preemption if we have HW breakpoints to preserve DEBUGCAUSE.DBNUM
817 #if defined(CONFIG_PREEMPT_COUNT) && defined(CONFIG_HAVE_HW_BREAKPOINT)
818 GET_THREAD_INFO(a2, a1)
819 l32i a3, a2, TI_PRE_COUNT
821 s32i a3, a2, TI_PRE_COUNT
825 bbsi.l a2, PS_UM_BIT, _user_exception
829 l32i a2, a2, EXC_TABLE_KSTK # load kernel stack pointer
832 #ifdef CONFIG_HAVE_HW_BREAKPOINT
833 /* Debug exception while in exception mode. This may happen when
834 * window overflow/underflow handler or fast exception handler hits
835 * data breakpoint, in which case save and disable all data
836 * breakpoints, single-step faulting instruction and restore data
840 bbci.l a0, PS_UM_BIT, 1b # jump if kernel mode
843 bbsi.l a0, DEBUGCAUSE_DBREAK_BIT, .Ldebug_save_dbreak
846 .rept XCHAL_NUM_DBREAK
847 l32i a0, a3, DT_DBREAKC_SAVE + _index * 4
848 wsr a0, SREG_DBREAKC + _index
849 .set _index, _index + 1
852 l32i a0, a3, DT_ICOUNT_LEVEL_SAVE
855 l32i a0, a3, DT_ICOUNT_SAVE
858 l32i a0, a3, DT_DEBUG_SAVE
859 xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
864 .rept XCHAL_NUM_DBREAK
866 xsr a0, SREG_DBREAKC + _index
867 s32i a0, a3, DT_DBREAKC_SAVE + _index * 4
868 .set _index, _index + 1
871 movi a0, XCHAL_EXCM_LEVEL + 1
873 s32i a0, a3, DT_ICOUNT_LEVEL_SAVE
877 s32i a0, a3, DT_ICOUNT_SAVE
879 l32i a0, a3, DT_DEBUG_SAVE
880 xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
883 /* Debug exception while in exception mode. Should not happen. */
887 ENDPROC(debug_exception)
890 * We get here in case of an unrecoverable exception.
891 * The only thing we can do is to be nice and print a panic message.
892 * We only produce a single stack frame for panic, so ???
897 * - a0 contains the caller address; original value saved in excsave1.
898 * - the original a0 contains a valid return address (backtrace) or 0.
899 * - a2 contains a valid stackpointer
903 * - If the stack pointer could be invalid, the caller has to setup a
904 * dummy stack pointer (e.g. the stack of the init_task)
906 * - If the return address could be invalid, the caller has to set it
907 * to 0, so the backtrace would stop.
912 .ascii "Unrecoverable error in exception handler\0"
916 ENTRY(unrecoverable_exception)
925 movi a1, (1 << PS_WOE_BIT) | LOCKLEVEL
931 addi a1, a1, PT_REGS_OFFSET
933 movi a6, unrecoverable_text
938 ENDPROC(unrecoverable_exception)
940 /* -------------------------- FAST EXCEPTION HANDLERS ----------------------- */
943 * Fast-handler for alloca exceptions
945 * The ALLOCA handler is entered when user code executes the MOVSP
946 * instruction and the caller's frame is not in the register file.
948 * This algorithm was taken from the Ross Morley's RTOS Porting Layer:
950 * /home/ross/rtos/porting/XtensaRTOS-PortingLayer-20090507/xtensa_vectors.S
952 * It leverages the existing window spill/fill routines and their support for
953 * double exceptions. The 'movsp' instruction will only cause an exception if
954 * the next window needs to be loaded. In fact this ALLOCA exception may be
955 * replaced at some point by changing the hardware to do a underflow exception
956 * of the proper size instead.
958 * This algorithm simply backs out the register changes started by the user
959 * excpetion handler, makes it appear that we have started a window underflow
960 * by rotating the window back and then setting the old window base (OWB) in
961 * the 'ps' register with the rolled back window base. The 'movsp' instruction
962 * will be re-executed and this time since the next window frames is in the
963 * active AR registers it won't cause an exception.
965 * If the WindowUnderflow code gets a TLB miss the page will get mapped
966 * the the partial windeowUnderflow will be handeled in the double exception
971 * a0: trashed, original value saved on stack (PT_AREG0)
973 * a2: new stack pointer, original in DEPC
975 * depc: a2, original value saved on stack (PT_DEPC)
976 * excsave_1: dispatch table
978 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
979 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
986 extui a3, a2, PS_OWB_SHIFT, PS_OWB_WIDTH
988 l32i a4, a6, PT_AREG0
992 slli a3, a3, PS_OWB_SHIFT
1001 j _WindowUnderflow12
1002 8: j _WindowUnderflow8
1003 4: j _WindowUnderflow4
1004 ENDPROC(fast_alloca)
1007 * fast system calls.
1009 * WARNING: The kernel doesn't save the entire user context before
1010 * handling a fast system call. These functions are small and short,
1011 * usually offering some functionality not available to user tasks.
1013 * BE CAREFUL TO PRESERVE THE USER'S CONTEXT.
1017 * a0: trashed, original value saved on stack (PT_AREG0)
1019 * a2: new stack pointer, original in DEPC
1021 * depc: a2, original value saved on stack (PT_DEPC)
1022 * excsave_1: dispatch table
1025 ENTRY(fast_syscall_user)
1033 l32i a0, a2, PT_DEPC
1034 bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_syscall_unrecoverable
1036 rsr a0, depc # get syscall-nr
1037 _beqz a0, fast_syscall_spill_registers
1038 _beqi a0, __NR_xtensa, fast_syscall_xtensa
1042 ENDPROC(fast_syscall_user)
1044 ENTRY(fast_syscall_unrecoverable)
1046 /* Restore all states. */
1048 l32i a0, a2, PT_AREG0 # restore a0
1049 xsr a2, depc # restore a2, depc
1052 call0 unrecoverable_exception
1054 ENDPROC(fast_syscall_unrecoverable)
1057 * sysxtensa syscall handler
1059 * int sysxtensa (SYS_XTENSA_ATOMIC_SET, ptr, val, unused);
1060 * int sysxtensa (SYS_XTENSA_ATOMIC_ADD, ptr, val, unused);
1061 * int sysxtensa (SYS_XTENSA_ATOMIC_EXG_ADD, ptr, val, unused);
1062 * int sysxtensa (SYS_XTENSA_ATOMIC_CMP_SWP, ptr, oldval, newval);
1067 * a0: a2 (syscall-nr), original value saved on stack (PT_AREG0)
1069 * a2: new stack pointer, original in a0 and DEPC
1071 * a4..a15: unchanged
1072 * depc: a2, original value saved on stack (PT_DEPC)
1073 * excsave_1: dispatch table
1075 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
1076 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
1078 * Note: we don't have to save a2; a2 holds the return value
1083 #ifdef CONFIG_FAST_SYSCALL_XTENSA
1085 ENTRY(fast_syscall_xtensa)
1087 s32i a7, a2, PT_AREG7 # we need an additional register
1088 movi a7, 4 # sizeof(unsigned int)
1089 access_ok a3, a7, a0, a2, .Leac # a0: scratch reg, a2: sp
1091 _bgeui a6, SYS_XTENSA_COUNT, .Lill
1092 _bnei a6, SYS_XTENSA_ATOMIC_CMP_SWP, .Lnswp
1094 /* Fall through for ATOMIC_CMP_SWP. */
1096 .Lswp: /* Atomic compare and swap */
1098 EX(.Leac) l32i a0, a3, 0 # read old value
1099 bne a0, a4, 1f # same as old value? jump
1100 EX(.Leac) s32i a5, a3, 0 # different, modify value
1101 l32i a7, a2, PT_AREG7 # restore a7
1102 l32i a0, a2, PT_AREG0 # restore a0
1103 movi a2, 1 # and return 1
1106 1: l32i a7, a2, PT_AREG7 # restore a7
1107 l32i a0, a2, PT_AREG0 # restore a0
1108 movi a2, 0 # return 0 (note that we cannot set
1111 .Lnswp: /* Atomic set, add, and exg_add. */
1113 EX(.Leac) l32i a7, a3, 0 # orig
1114 addi a6, a6, -SYS_XTENSA_ATOMIC_SET
1115 add a0, a4, a7 # + arg
1116 moveqz a0, a4, a6 # set
1117 addi a6, a6, SYS_XTENSA_ATOMIC_SET
1118 EX(.Leac) s32i a0, a3, 0 # write new value
1122 l32i a7, a0, PT_AREG7 # restore a7
1123 l32i a0, a0, PT_AREG0 # restore a0
1126 .Leac: l32i a7, a2, PT_AREG7 # restore a7
1127 l32i a0, a2, PT_AREG0 # restore a0
1131 .Lill: l32i a7, a2, PT_AREG7 # restore a7
1132 l32i a0, a2, PT_AREG0 # restore a0
1136 ENDPROC(fast_syscall_xtensa)
1138 #else /* CONFIG_FAST_SYSCALL_XTENSA */
1140 ENTRY(fast_syscall_xtensa)
1142 l32i a0, a2, PT_AREG0 # restore a0
1146 ENDPROC(fast_syscall_xtensa)
1148 #endif /* CONFIG_FAST_SYSCALL_XTENSA */
1151 /* fast_syscall_spill_registers.
1155 * a0: trashed, original value saved on stack (PT_AREG0)
1157 * a2: new stack pointer, original in DEPC
1159 * depc: a2, original value saved on stack (PT_DEPC)
1160 * excsave_1: dispatch table
1162 * Note: We assume the stack pointer is EXC_TABLE_KSTK in the fixup handler.
1165 #ifdef CONFIG_FAST_SYSCALL_SPILL_REGISTERS
1167 ENTRY(fast_syscall_spill_registers)
1169 /* Register a FIXUP handler (pass current wb as a parameter) */
1172 movi a0, fast_syscall_spill_registers_fixup
1173 s32i a0, a3, EXC_TABLE_FIXUP
1175 s32i a0, a3, EXC_TABLE_PARAM
1176 xsr a3, excsave1 # restore a3 and excsave_1
1178 /* Save a3, a4 and SAR on stack. */
1181 s32i a3, a2, PT_AREG3
1184 /* The spill routine might clobber a4, a7, a8, a11, a12, and a15. */
1186 s32i a4, a2, PT_AREG4
1187 s32i a7, a2, PT_AREG7
1188 s32i a8, a2, PT_AREG8
1189 s32i a11, a2, PT_AREG11
1190 s32i a12, a2, PT_AREG12
1191 s32i a15, a2, PT_AREG15
1194 * Rotate ws so that the current windowbase is at bit 0.
1195 * Assume ws = xxxwww1yy (www1 current window frame).
1196 * Rotate ws right so that a4 = yyxxxwww1.
1200 rsr a3, windowstart # a3 = xxxwww1yy
1203 or a3, a3, a0 # a3 = xxxwww1yyxxxwww1yy
1204 srl a3, a3 # a3 = 00xxxwww1yyxxxwww1
1206 /* We are done if there are no more than the current register frame. */
1208 extui a3, a3, 1, WSBITS-1 # a3 = 0yyxxxwww
1209 movi a0, (1 << (WSBITS-1))
1210 _beqz a3, .Lnospill # only one active frame? jump
1212 /* We want 1 at the top, so that we return to the current windowbase */
1214 or a3, a3, a0 # 1yyxxxwww
1216 /* Skip empty frames - get 'oldest' WINDOWSTART-bit. */
1218 wsr a3, windowstart # save shifted windowstart
1220 and a3, a0, a3 # first bit set from right: 000010000
1222 ffs_ws a0, a3 # a0: shifts to skip empty frames
1224 sub a0, a3, a0 # WSBITS-a0:number of 0-bits from right
1225 ssr a0 # save in SAR for later.
1233 srl a3, a3 # shift windowstart
1235 /* WB is now just one frame below the oldest frame in the register
1236 window. WS is shifted so the oldest frame is in bit 0, thus, WB
1237 and WS differ by one 4-register frame. */
1239 /* Save frames. Depending what call was used (call4, call8, call12),
1240 * we have to save 4,8. or 12 registers.
1244 .Lloop: _bbsi.l a3, 1, .Lc4
1245 _bbci.l a3, 2, .Lc12
1247 .Lc8: s32e a4, a13, -16
1256 srli a11, a3, 2 # shift windowbase by 2
1261 .Lc4: s32e a4, a9, -16
1271 .Lc12: _bbci.l a3, 3, .Linvalid_mask # bit 2 shouldn't be zero!
1273 /* 12-register frame (call12) */
1288 /* The stack pointer for a4..a7 is out of reach, so we rotate the
1289 * window, grab the stackpointer, and rotate back.
1290 * Alternatively, we could also use the following approach, but that
1291 * makes the fixup routine much more complicated:
1314 /* Done. Do the final rotation and set WS */
1324 /* Advance PC, restore registers and SAR, and return from exception. */
1327 l32i a0, a2, PT_AREG0
1329 l32i a3, a2, PT_AREG3
1331 /* Restore clobbered registers. */
1333 l32i a4, a2, PT_AREG4
1334 l32i a7, a2, PT_AREG7
1335 l32i a8, a2, PT_AREG8
1336 l32i a11, a2, PT_AREG11
1337 l32i a12, a2, PT_AREG12
1338 l32i a15, a2, PT_AREG15
1345 /* We get here because of an unrecoverable error in the window
1346 * registers, so set up a dummy frame and kill the user application.
1347 * Note: We assume EXC_TABLE_KSTK contains a valid stack pointer.
1360 l32i a1, a3, EXC_TABLE_KSTK
1362 movi a4, (1 << PS_WOE_BIT) | LOCKLEVEL
1369 /* shouldn't return, so panic */
1372 call0 unrecoverable_exception # should not return
1376 ENDPROC(fast_syscall_spill_registers)
1380 * We get here if the spill routine causes an exception, e.g. tlb miss.
1381 * We basically restore WINDOWBASE and WINDOWSTART to the condition when
1382 * we entered the spill routine and jump to the user exception handler.
1384 * Note that we only need to restore the bits in windowstart that have not
1385 * been spilled yet by the _spill_register routine. Luckily, a3 contains a
1386 * rotated windowstart with only those bits set for frames that haven't been
1387 * spilled yet. Because a3 is rotated such that bit 0 represents the register
1388 * frame for the current windowbase - 1, we need to rotate a3 left by the
1389 * value of the current windowbase + 1 and move it to windowstart.
1391 * a0: value of depc, original value in depc
1392 * a2: trashed, original value in EXC_TABLE_DOUBLE_SAVE
1393 * a3: exctable, original value in excsave1
1396 ENTRY(fast_syscall_spill_registers_fixup)
1398 rsr a2, windowbase # get current windowbase (a2 is saved)
1399 xsr a0, depc # restore depc and a0
1400 ssl a2 # set shift (32 - WB)
1402 /* We need to make sure the current registers (a0-a3) are preserved.
1403 * To do this, we simply set the bit for the current window frame
1404 * in WS, so that the exception handlers save them to the task stack.
1406 * Note: we use a3 to set the windowbase, so we take a special care
1407 * of it, saving it in the original _spill_registers frame across
1408 * the exception handler call.
1411 xsr a3, excsave1 # get spill-mask
1412 slli a3, a3, 1 # shift left by one
1413 addi a3, a3, 1 # set the bit for the current window frame
1415 slli a2, a3, 32-WSBITS
1416 src a2, a3, a2 # a2 = xxwww1yyxxxwww1yy......
1417 wsr a2, windowstart # set corrected windowstart
1421 l32i a2, a2, EXC_TABLE_DOUBLE_SAVE # restore a2
1423 s32i a3, a2, EXC_TABLE_DOUBLE_SAVE # save a3
1424 l32i a3, a2, EXC_TABLE_PARAM # original WB (in user task)
1427 /* Return to the original (user task) WINDOWBASE.
1428 * We leave the following frame behind:
1430 * a3: trashed (saved in EXC_TABLE_DOUBLE_SAVE)
1431 * depc: depc (we have to return to that address)
1432 * excsave_1: exctable
1438 /* We are now in the original frame when we entered _spill_registers:
1439 * a0: return address
1440 * a1: used, stack pointer
1441 * a2: kernel stack pointer
1443 * depc: exception address
1445 * Note: This frame might be the same as above.
1448 /* Setup stack pointer. */
1450 addi a2, a2, -PT_USER_SIZE
1451 s32i a0, a2, PT_AREG0
1453 /* Make sure we return to this fixup handler. */
1455 movi a3, fast_syscall_spill_registers_fixup_return
1456 s32i a3, a2, PT_DEPC # setup depc
1458 /* Jump to the exception handler. */
1462 addx4 a0, a0, a3 # find entry in table
1463 l32i a0, a0, EXC_TABLE_FAST_USER # load handler
1464 l32i a3, a3, EXC_TABLE_DOUBLE_SAVE
1467 ENDPROC(fast_syscall_spill_registers_fixup)
1469 ENTRY(fast_syscall_spill_registers_fixup_return)
1471 /* When we return here, all registers have been restored (a2: DEPC) */
1473 wsr a2, depc # exception address
1475 /* Restore fixup handler. */
1478 s32i a3, a2, EXC_TABLE_DOUBLE_SAVE
1479 movi a3, fast_syscall_spill_registers_fixup
1480 s32i a3, a2, EXC_TABLE_FIXUP
1482 s32i a3, a2, EXC_TABLE_PARAM
1483 l32i a2, a2, EXC_TABLE_KSTK
1485 /* Load WB at the time the exception occurred. */
1487 rsr a3, sar # WB is still in SAR
1493 l32i a3, a3, EXC_TABLE_DOUBLE_SAVE
1497 ENDPROC(fast_syscall_spill_registers_fixup_return)
1499 #else /* CONFIG_FAST_SYSCALL_SPILL_REGISTERS */
1501 ENTRY(fast_syscall_spill_registers)
1503 l32i a0, a2, PT_AREG0 # restore a0
1507 ENDPROC(fast_syscall_spill_registers)
1509 #endif /* CONFIG_FAST_SYSCALL_SPILL_REGISTERS */
1513 * We should never get here. Bail out!
1516 ENTRY(fast_second_level_miss_double_kernel)
1519 call0 unrecoverable_exception # should not return
1522 ENDPROC(fast_second_level_miss_double_kernel)
1524 /* First-level entry handler for user, kernel, and double 2nd-level
1525 * TLB miss exceptions. Note that for now, user and kernel miss
1526 * exceptions share the same entry point and are handled identically.
1528 * An old, less-efficient C version of this function used to exist.
1529 * We include it below, interleaved as comments, for reference.
1533 * a0: trashed, original value saved on stack (PT_AREG0)
1535 * a2: new stack pointer, original in DEPC
1537 * depc: a2, original value saved on stack (PT_DEPC)
1538 * excsave_1: dispatch table
1540 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
1541 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
1544 ENTRY(fast_second_level_miss)
1546 /* Save a1 and a3. Note: we don't expect a double exception. */
1548 s32i a1, a2, PT_AREG1
1549 s32i a3, a2, PT_AREG3
1551 /* We need to map the page of PTEs for the user task. Find
1552 * the pointer to that page. Also, it's possible for tsk->mm
1553 * to be NULL while tsk->active_mm is nonzero if we faulted on
1554 * a vmalloc address. In that rare case, we must use
1555 * active_mm instead to avoid a fault in this handler. See
1557 * http://mail.nl.linux.org/linux-mm/2002-08/msg00258.html
1558 * (or search Internet on "mm vs. active_mm")
1561 * mm = tsk->active_mm;
1562 * pgd = pgd_offset (mm, regs->excvaddr);
1563 * pmd = pmd_offset (pgd, regs->excvaddr);
1568 l32i a0, a1, TASK_MM # tsk->mm
1571 8: rsr a3, excvaddr # fault address
1572 _PGD_OFFSET(a0, a3, a1)
1573 l32i a0, a0, 0 # read pmdval
1576 /* Read ptevaddr and convert to top of page-table page.
1578 * vpnval = read_ptevaddr_register() & PAGE_MASK;
1579 * vpnval += DTLB_WAY_PGTABLE;
1580 * pteval = mk_pte (virt_to_page(pmd_val(pmdval)), PAGE_KERNEL);
1581 * write_dtlb_entry (pteval, vpnval);
1583 * The messy computation for 'pteval' above really simplifies
1584 * into the following:
1586 * pteval = ((pmdval - PAGE_OFFSET + PHYS_OFFSET) & PAGE_MASK)
1590 movi a1, (PHYS_OFFSET - PAGE_OFFSET) & 0xffffffff
1591 add a0, a0, a1 # pmdval - PAGE_OFFSET
1592 extui a1, a0, 0, PAGE_SHIFT # ... & PAGE_MASK
1595 movi a1, _PAGE_DIRECTORY
1596 or a0, a0, a1 # ... | PAGE_DIRECTORY
1599 * We utilize all three wired-ways (7-9) to hold pmd translations.
1600 * Memory regions are mapped to the DTLBs according to bits 28 and 29.
1601 * This allows to map the three most common regions to three different
1603 * 0,1 -> way 7 program (0040.0000) and virtual (c000.0000)
1604 * 2 -> way 8 shared libaries (2000.0000)
1605 * 3 -> way 0 stack (3000.0000)
1608 extui a3, a3, 28, 2 # addr. bit 28 and 29 0,1,2,3
1610 addx2 a3, a3, a3 # -> 0,3,6,9
1611 srli a1, a1, PAGE_SHIFT
1612 extui a3, a3, 2, 2 # -> 0,0,1,2
1613 slli a1, a1, PAGE_SHIFT # ptevaddr & PAGE_MASK
1614 addi a3, a3, DTLB_WAY_PGD
1615 add a1, a1, a3 # ... + way_number
1620 /* Exit critical section. */
1624 s32i a0, a3, EXC_TABLE_FIXUP
1626 /* Restore the working registers, and return. */
1628 l32i a0, a2, PT_AREG0
1629 l32i a1, a2, PT_AREG1
1630 l32i a3, a2, PT_AREG3
1631 l32i a2, a2, PT_DEPC
1633 bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
1635 /* Restore excsave1 and return. */
1640 /* Return from double exception. */
1646 9: l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0
1649 /* Even more unlikely case active_mm == 0.
1650 * We can get here with NMI in the middle of context_switch that
1651 * touches vmalloc area.
1656 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
1658 2: /* Special case for cache aliasing.
1659 * We (should) only get here if a clear_user_page, copy_user_page
1660 * or the aliased cache flush functions got preemptively interrupted
1661 * by another task. Re-establish temporary mapping to the
1662 * TLBTEMP_BASE areas.
1665 /* We shouldn't be in a double exception */
1667 l32i a0, a2, PT_DEPC
1668 bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 2f
1670 /* Make sure the exception originated in the special functions */
1672 movi a0, __tlbtemp_mapping_start
1675 movi a0, __tlbtemp_mapping_end
1678 /* Check if excvaddr was in one of the TLBTEMP_BASE areas. */
1680 movi a3, TLBTEMP_BASE_1
1684 addi a1, a0, -TLBTEMP_SIZE
1687 /* Check if we have to restore an ITLB mapping. */
1689 movi a1, __tlbtemp_mapping_itlb
1698 /* Jump for ITLB entry */
1702 /* We can use up to two TLBTEMP areas, one for src and one for dst. */
1704 extui a3, a0, PAGE_SHIFT + DCACHE_ALIAS_ORDER, 1
1707 /* PPN is in a6 for the first TLBTEMP area and in a7 for the second. */
1713 /* ITLB entry. We only use dst in a6. */
1720 #endif // DCACHE_WAY_SIZE > PAGE_SIZE
1723 2: /* Invalid PGD, default exception handling */
1726 s32i a1, a2, PT_AREG2
1730 bbsi.l a2, PS_UM_BIT, 1f
1732 1: j _user_exception
1734 ENDPROC(fast_second_level_miss)
1737 * StoreProhibitedException
1739 * Update the pte and invalidate the itlb mapping for this pte.
1743 * a0: trashed, original value saved on stack (PT_AREG0)
1745 * a2: new stack pointer, original in DEPC
1747 * depc: a2, original value saved on stack (PT_DEPC)
1748 * excsave_1: dispatch table
1750 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
1751 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
1754 ENTRY(fast_store_prohibited)
1756 /* Save a1 and a3. */
1758 s32i a1, a2, PT_AREG1
1759 s32i a3, a2, PT_AREG3
1762 l32i a0, a1, TASK_MM # tsk->mm
1765 8: rsr a1, excvaddr # fault address
1766 _PGD_OFFSET(a0, a1, a3)
1771 * Note that we test _PAGE_WRITABLE_BIT only if PTE is present
1772 * and is not PAGE_NONE. See pgtable.h for possible PTE layouts.
1775 _PTE_OFFSET(a0, a1, a3)
1776 l32i a3, a0, 0 # read pteval
1777 movi a1, _PAGE_CA_INVALID
1779 bbci.l a3, _PAGE_WRITABLE_BIT, 2f
1781 movi a1, _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_HW_WRITE
1786 /* We need to flush the cache if we have page coloring. */
1787 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
1793 /* Exit critical section. */
1797 s32i a0, a3, EXC_TABLE_FIXUP
1799 /* Restore the working registers, and return. */
1801 l32i a3, a2, PT_AREG3
1802 l32i a1, a2, PT_AREG1
1803 l32i a0, a2, PT_AREG0
1804 l32i a2, a2, PT_DEPC
1806 bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
1811 /* Double exception. Restore FIXUP handler and return. */
1817 9: l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0
1820 2: /* If there was a problem, handle fault in C */
1822 rsr a3, depc # still holds a2
1823 s32i a3, a2, PT_AREG2
1827 bbsi.l a2, PS_UM_BIT, 1f
1829 1: j _user_exception
1831 ENDPROC(fast_store_prohibited)
1833 #endif /* CONFIG_MMU */
1838 * void system_call (struct pt_regs* regs, int exccause)
1847 /* regs->syscall = regs->areg[2] */
1849 l32i a7, a2, PT_AREG2
1850 s32i a7, a2, PT_SYSCALL
1852 GET_THREAD_INFO(a4, a1)
1853 l32i a3, a4, TI_FLAGS
1854 movi a4, _TIF_WORK_MASK
1859 call4 do_syscall_trace_enter
1860 l32i a7, a2, PT_SYSCALL
1865 /* syscall = sys_call_table[syscall_nr] */
1867 movi a4, sys_call_table
1868 movi a5, __NR_syscalls
1874 movi a5, sys_ni_syscall;
1877 /* Load args: arg0 - arg5 are passed via regs. */
1879 l32i a6, a2, PT_AREG6
1880 l32i a7, a2, PT_AREG3
1881 l32i a8, a2, PT_AREG4
1882 l32i a9, a2, PT_AREG5
1883 l32i a10, a2, PT_AREG8
1884 l32i a11, a2, PT_AREG9
1886 /* Pass one additional argument to the syscall: pt_regs (on stack) */
1891 1: /* regs->areg[2] = return_value */
1893 s32i a6, a2, PT_AREG2
1899 l32i a3, a2, PT_SYSCALL
1900 s32i a4, a2, PT_SYSCALL
1902 call4 do_syscall_trace_leave
1903 s32i a3, a2, PT_SYSCALL
1906 ENDPROC(system_call)
1909 * Spill live registers on the kernel stack macro.
1911 * Entry condition: ps.woe is set, ps.excm is cleared
1912 * Exit condition: windowstart has single bit set
1913 * May clobber: a12, a13
1915 .macro spill_registers_kernel
1917 #if XCHAL_NUM_AREGS > 16
1925 #if XCHAL_NUM_AREGS > 32
1926 .rept (XCHAL_NUM_AREGS - 32) / 12
1932 #if XCHAL_NUM_AREGS % 12 == 0
1934 #elif XCHAL_NUM_AREGS % 12 == 4
1936 #elif XCHAL_NUM_AREGS % 12 == 8
1949 * struct task* _switch_to (struct task* prev, struct task* next)
1957 mov a11, a3 # and 'next' (a3)
1959 l32i a4, a2, TASK_THREAD_INFO
1960 l32i a5, a3, TASK_THREAD_INFO
1962 save_xtregs_user a4 a6 a8 a9 a12 a13 THREAD_XTREGS_USER
1964 #if THREAD_RA > 1020 || THREAD_SP > 1020
1965 addi a10, a2, TASK_THREAD
1966 s32i a0, a10, THREAD_RA - TASK_THREAD # save return address
1967 s32i a1, a10, THREAD_SP - TASK_THREAD # save stack pointer
1969 s32i a0, a2, THREAD_RA # save return address
1970 s32i a1, a2, THREAD_SP # save stack pointer
1973 #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP)
1974 movi a6, __stack_chk_guard
1975 l32i a8, a3, TASK_STACK_CANARY
1979 /* Disable ints while we manipulate the stack pointer. */
1984 /* Switch CPENABLE */
1986 #if (XTENSA_HAVE_COPROCESSORS || XTENSA_HAVE_IO_PORTS)
1987 l32i a3, a5, THREAD_CPENABLE
1989 s32i a3, a4, THREAD_CPENABLE
1992 /* Flush register file. */
1994 spill_registers_kernel
1996 /* Set kernel stack (and leave critical section)
1997 * Note: It's save to set it here. The stack will not be overwritten
1998 * because the kernel stack will only be loaded again after
1999 * we return from kernel space.
2002 rsr a3, excsave1 # exc_table
2003 addi a7, a5, PT_REGS_OFFSET
2004 s32i a7, a3, EXC_TABLE_KSTK
2006 /* restore context of the task 'next' */
2008 l32i a0, a11, THREAD_RA # restore return address
2009 l32i a1, a11, THREAD_SP # restore stack pointer
2011 load_xtregs_user a5 a6 a8 a9 a12 a13 THREAD_XTREGS_USER
2020 ENTRY(ret_from_fork)
2022 /* void schedule_tail (struct task_struct *prev)
2023 * Note: prev is still in a6 (return value from fake call4 frame)
2028 call4 do_syscall_trace_leave
2030 j common_exception_return
2032 ENDPROC(ret_from_fork)
2035 * Kernel thread creation helper
2036 * On entry, set up by copy_thread: a2 = thread_fn, a3 = thread_fn arg
2037 * left from _switch_to: a6 = prev
2039 ENTRY(ret_from_kernel_thread)
2044 j common_exception_return
2046 ENDPROC(ret_from_kernel_thread)