1 # SPDX-License-Identifier: GPL-2.0
4 select ARCH_32BIT_OFF_T
5 select ARCH_HAS_BINFMT_FLAT if !MMU
6 select ARCH_HAS_CURRENT_STACK_POINTER
7 select ARCH_HAS_DMA_PREP_COHERENT if MMU
8 select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU
9 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU
10 select ARCH_HAS_DMA_SET_UNCACHED if MMU
11 select ARCH_HAS_STRNCPY_FROM_USER if !KASAN
12 select ARCH_HAS_STRNLEN_USER
13 select ARCH_USE_MEMTEST
14 select ARCH_USE_QUEUED_RWLOCKS
15 select ARCH_USE_QUEUED_SPINLOCKS
16 select ARCH_WANT_FRAME_POINTERS
17 select ARCH_WANT_IPC_PARSE_VERSION
18 select BUILDTIME_TABLE_SORT
19 select CLONE_BACKWARDS
21 select DMA_REMAP if MMU
22 select GENERIC_ATOMIC64
23 select GENERIC_IRQ_SHOW
24 select GENERIC_LIB_CMPDI2
25 select GENERIC_LIB_MULDI3
26 select GENERIC_LIB_UCMPDI2
27 select GENERIC_PCI_IOMAP
28 select GENERIC_SCHED_CLOCK
29 select HAVE_ARCH_AUDITSYSCALL
30 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
31 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
32 select HAVE_ARCH_SECCOMP_FILTER
33 select HAVE_ARCH_TRACEHOOK
34 select HAVE_DEBUG_KMEMLEAK
35 select HAVE_DMA_CONTIGUOUS
36 select HAVE_EXIT_THREAD
37 select HAVE_FUNCTION_TRACER
38 select HAVE_GCC_PLUGINS if GCC_VERSION >= 120000
39 select HAVE_HW_BREAKPOINT if PERF_EVENTS
40 select HAVE_IRQ_TIME_ACCOUNTING
42 select HAVE_PERF_EVENTS
43 select HAVE_STACKPROTECTOR
44 select HAVE_SYSCALL_TRACEPOINTS
46 select MODULES_USE_ELF_RELA
47 select PERF_USE_VMALLOC
48 select TRACE_IRQFLAGS_SUPPORT
51 Xtensa processors are 32-bit RISC machines designed by Tensilica
52 primarily for embedded systems. These processors are both
53 configurable and extensible. The Linux port to the Xtensa
54 architecture supports all processor configurations and extensions,
55 with reasonable minimum requirements. The Xtensa Linux project has
56 a home page at <http://www.linux-xtensa.org/>.
58 config GENERIC_HWEIGHT
61 config ARCH_HAS_ILOG2_U32
64 config ARCH_HAS_ILOG2_U64
74 config LOCKDEP_SUPPORT
77 config STACKTRACE_SUPPORT
83 config HAVE_XTENSA_GPIO32
86 config KASAN_SHADOW_OFFSET
91 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1)
93 config CPU_LITTLE_ENDIAN
94 def_bool !CPU_BIG_ENDIAN
96 config CC_HAVE_CALL0_ABI
97 def_bool $(success,test "$(shell,echo __XTENSA_CALL0_ABI__ | $(CC) -mabi=call0 -E -P - 2>/dev/null)" = 1)
99 menu "Processor type and features"
102 prompt "Xtensa Processor Configuration"
103 default XTENSA_VARIANT_FSF
105 config XTENSA_VARIANT_FSF
106 bool "fsf - default (not generic) configuration"
109 config XTENSA_VARIANT_DC232B
110 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
112 select HAVE_XTENSA_GPIO32
114 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE).
116 config XTENSA_VARIANT_DC233C
117 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
119 select HAVE_XTENSA_GPIO32
121 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE).
123 config XTENSA_VARIANT_CUSTOM
124 bool "Custom Xtensa processor configuration"
125 select HAVE_XTENSA_GPIO32
127 Select this variant to use a custom Xtensa processor configuration.
128 You will be prompted for a processor variant CORENAME.
131 config XTENSA_VARIANT_CUSTOM_NAME
132 string "Xtensa Processor Custom Core Variant Name"
133 depends on XTENSA_VARIANT_CUSTOM
135 Provide the name of a custom Xtensa processor variant.
136 This CORENAME selects arch/xtensa/variant/CORENAME.
137 Don't forget you have to select MMU if you have one.
139 config XTENSA_VARIANT_NAME
141 default "dc232b" if XTENSA_VARIANT_DC232B
142 default "dc233c" if XTENSA_VARIANT_DC233C
143 default "fsf" if XTENSA_VARIANT_FSF
144 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM
146 config XTENSA_VARIANT_MMU
147 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)"
148 depends on XTENSA_VARIANT_CUSTOM
152 Build a Conventional Kernel with full MMU support,
153 ie: it supports a TLB with auto-loading, page protection.
155 config XTENSA_VARIANT_HAVE_PERF_EVENTS
156 bool "Core variant has Performance Monitor Module"
157 depends on XTENSA_VARIANT_CUSTOM
160 Enable if core variant has Performance Monitor Module with
161 External Registers Interface.
165 config XTENSA_FAKE_NMI
166 bool "Treat PMM IRQ as NMI"
167 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS
170 If PMM IRQ is the only IRQ at EXCM level it is safe to
171 treat it as NMI, which improves accuracy of profiling.
173 If there are other interrupts at or above PMM IRQ priority level
174 but not above the EXCM level, PMM IRQ still may be treated as NMI,
175 but only if these IRQs are not used. There will be a build warning
176 saying that this is not safe, and a bugcheck if one of these IRQs
181 config XTENSA_UNALIGNED_USER
182 bool "Unaligned memory access in user space"
184 The Xtensa architecture currently does not handle unaligned
185 memory accesses in hardware but through an exception handler.
186 Per default, unaligned memory accesses are disabled in user space.
188 Say Y here to enable unaligned memory access in user space.
191 bool "System Supports SMP (MX)"
192 depends on XTENSA_VARIANT_CUSTOM
195 This option is used to indicate that the system-on-a-chip (SOC)
196 supports Multiprocessing. Multiprocessor support implemented above
197 the CPU core definition and currently needs to be selected manually.
199 Multiprocessor support is implemented with external cache and
200 interrupt controllers.
202 The MX interrupt distributer adds Interprocessor Interrupts
203 and causes the IRQ numbers to be increased by 4 for devices
204 like the open cores ethernet driver and the serial interface.
206 You still have to select "Enable SMP" to enable SMP on this SOC.
209 bool "Enable Symmetric multi-processing support"
211 select GENERIC_SMP_IDLE_THREAD
213 Enabled SMP Software; allows more than one CPU/CORE
214 to be activated during startup.
218 int "Maximum number of CPUs (2-32)"
223 bool "Enable CPU hotplug support"
226 Say Y here to allow turning CPUs off and on. CPUs can be
227 controlled through /sys/devices/system/cpu.
229 Say N if you want to disable CPU hotplug.
231 config SECONDARY_RESET_VECTOR
232 bool "Secondary cores use alternative reset vector"
236 Secondary cores may be configured to use alternative reset vector,
237 or all cores may use primary reset vector.
238 Say Y here to supply handler for the alternative reset location.
240 config FAST_SYSCALL_XTENSA
241 bool "Enable fast atomic syscalls"
244 fast_syscall_xtensa is a syscall that can make atomic operations
245 on UP kernel when processor has no s32c1i support.
247 This syscall is deprecated. It may have issues when called with
248 invalid arguments. It is provided only for backwards compatibility.
249 Only enable it if your userspace software requires it.
253 config FAST_SYSCALL_SPILL_REGISTERS
254 bool "Enable spill registers syscall"
257 fast_syscall_spill_registers is a syscall that spills all active
258 register windows of a calling userspace task onto its stack.
260 This syscall is deprecated. It may have issues when called with
261 invalid arguments. It is provided only for backwards compatibility.
262 Only enable it if your userspace software requires it.
268 default KERNEL_ABI_DEFAULT
270 Select ABI for the kernel code. This ABI is independent of the
271 supported userspace ABI and any combination of the
272 kernel/userspace ABI is possible and should work.
274 In case both kernel and userspace support only call0 ABI
275 all register windows support code will be omitted from the
278 If unsure, choose the default ABI.
280 config KERNEL_ABI_DEFAULT
283 Select this option to compile kernel code with the default ABI
284 selected for the toolchain.
285 Normally cores with windowed registers option use windowed ABI and
286 cores without it use call0 ABI.
288 config KERNEL_ABI_CALL0
289 bool "Call0 ABI" if CC_HAVE_CALL0_ABI
291 Select this option to compile kernel code with call0 ABI even with
292 toolchain that defaults to windowed ABI.
293 When this option is not selected the default toolchain ABI will
294 be used for the kernel code.
298 config USER_ABI_CALL0
302 prompt "Userspace ABI"
303 default USER_ABI_DEFAULT
305 Select supported userspace ABI.
307 If unsure, choose the default ABI.
309 config USER_ABI_DEFAULT
310 bool "Default ABI only"
312 Assume default userspace ABI. For XEA2 cores it is windowed ABI.
313 call0 ABI binaries may be run on such kernel, but signal delivery
314 will not work correctly for them.
316 config USER_ABI_CALL0_ONLY
317 bool "Call0 ABI only"
318 select USER_ABI_CALL0
320 Select this option to support only call0 ABI in userspace.
321 Windowed ABI binaries will crash with a segfault caused by
322 an illegal instruction exception on the first 'entry' opcode.
324 Choose this option if you're planning to run only user code
325 built with call0 ABI.
327 config USER_ABI_CALL0_PROBE
328 bool "Support both windowed and call0 ABI by probing"
329 select USER_ABI_CALL0
331 Select this option to support both windowed and call0 userspace
332 ABIs. When enabled all processes are started with PS.WOE disabled
333 and a fast user exception handler for an illegal instruction is
334 used to turn on PS.WOE bit on the first 'entry' opcode executed by
337 This option should be enabled for the kernel that must support
338 both call0 and windowed ABIs in userspace at the same time.
340 Note that Xtensa ISA does not guarantee that entry opcode will
341 raise an illegal instruction exception on cores with XEA2 when
342 PS.WOE is disabled, check whether the target core supports it.
348 config XTENSA_CALIBRATE_CCOUNT
351 On some platforms (XT2000, for example), the CPU clock rate can
352 vary. The frequency can be determined, however, by measuring
353 against a well known, fixed frequency, such as an UART oscillator.
355 config SERIAL_CONSOLE
358 config PLATFORM_HAVE_XIP
361 menu "Platform options"
364 prompt "Xtensa System Type"
365 default XTENSA_PLATFORM_ISS
367 config XTENSA_PLATFORM_ISS
369 select XTENSA_CALIBRATE_CCOUNT
370 select SERIAL_CONSOLE
372 ISS is an acronym for Tensilica's Instruction Set Simulator.
374 config XTENSA_PLATFORM_XT2000
377 XT2000 is the name of Tensilica's feature-rich emulation platform.
378 This hardware is capable of running a full Linux distribution.
380 config XTENSA_PLATFORM_XTFPGA
382 select ETHOC if ETHERNET
383 select PLATFORM_WANT_DEFAULT_MEM if !MMU
384 select SERIAL_CONSOLE
385 select XTENSA_CALIBRATE_CCOUNT
386 select PLATFORM_HAVE_XIP
388 XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605).
389 This hardware is capable of running a full Linux distribution.
393 config PLATFORM_NR_IRQS
395 default 3 if XTENSA_PLATFORM_XT2000
398 config XTENSA_CPU_CLOCK
399 int "CPU clock rate [MHz]"
400 depends on !XTENSA_CALIBRATE_CCOUNT
403 config GENERIC_CALIBRATE_DELAY
404 bool "Auto calibration of the BogoMIPS value"
406 The BogoMIPS value can easily be derived from the CPU frequency.
409 bool "Default bootloader kernel arguments"
412 string "Initial kernel command string"
413 depends on CMDLINE_BOOL
414 default "console=ttyS0,38400 root=/dev/ram"
416 On some architectures (EBSA110 and CATS), there is currently no way
417 for the boot loader to pass arguments to the kernel. For these
418 architectures, you should supply some command-line options at build
419 time by entering them here. As a minimum, you should specify the
420 memory size and the root device (e.g., mem=64M root=/dev/nfs).
423 bool "Flattened Device Tree support"
425 select OF_EARLY_FLATTREE
427 Include support for flattened device tree machine descriptions.
429 config BUILTIN_DTB_SOURCE
430 string "DTB to build into the kernel image"
433 config PARSE_BOOTPARAM
434 bool "Parse bootparam block"
437 Parse parameters passed to the kernel from the bootloader. It may
438 be disabled if the kernel is known to run without the bootloader.
443 prompt "Semihosting interface"
444 default XTENSA_SIMCALL_ISS
445 depends on XTENSA_PLATFORM_ISS
447 Choose semihosting interface that will be used for serial port,
448 block device and networking.
450 config XTENSA_SIMCALL_ISS
453 Use simcall instruction. simcall is only available on simulators,
454 it does nothing on hardware.
456 config XTENSA_SIMCALL_GDBIO
459 Use break instruction. It is available on real hardware when GDB
460 is attached to it via JTAG.
464 config BLK_DEV_SIMDISK
465 tristate "Host file-based simulated block device support"
467 depends on XTENSA_PLATFORM_ISS && BLOCK
469 Create block devices that map to files in the host file system.
470 Device binding to host file may be changed at runtime via proc
471 interface provided the device is not in use.
473 config BLK_DEV_SIMDISK_COUNT
474 int "Number of host file-based simulated block devices"
476 depends on BLK_DEV_SIMDISK
479 This is the default minimal number of created block devices.
480 Kernel/module parameter 'simdisk_count' may be used to change this
481 value at runtime. More file names (but no more than 10) may be
482 specified as parameters, simdisk_count grows accordingly.
484 config SIMDISK0_FILENAME
485 string "Host filename for the first simulated device"
486 depends on BLK_DEV_SIMDISK = y
489 Attach a first simdisk to a host file. Conventionally, this file
490 contains a root file system.
492 config SIMDISK1_FILENAME
493 string "Host filename for the second simulated device"
494 depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1
497 Another simulated disk in a host file for a buildroot-independent
501 bool "Enable XTFPGA LCD driver"
502 depends on XTENSA_PLATFORM_XTFPGA
505 There's a 2x16 LCD on most of XTFPGA boards, kernel may output
506 progress messages there during bootup/shutdown. It may be useful
507 during board bringup.
511 config XTFPGA_LCD_BASE_ADDR
512 hex "XTFPGA LCD base address"
513 depends on XTFPGA_LCD
516 Base address of the LCD controller inside KIO region.
517 Different boards from XTFPGA family have LCD controller at different
518 addresses. Please consult prototyping user guide for your board for
519 the correct address. Wrong address here may lead to hardware lockup.
521 config XTFPGA_LCD_8BIT_ACCESS
522 bool "Use 8-bit access to XTFPGA LCD"
523 depends on XTFPGA_LCD
526 LCD may be connected with 4- or 8-bit interface, 8-bit access may
527 only be used with 8-bit interface. Please consult prototyping user
528 guide for your board for the correct interface width.
530 comment "Kernel memory layout"
532 config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
533 bool "Initialize Xtensa MMU inside the Linux kernel code"
534 depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B
535 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM
537 Earlier version initialized the MMU in the exception vector
538 before jumping to _startup in head.S and had an advantage that
539 it was possible to place a software breakpoint at 'reset' and
540 then enter your normal kernel breakpoints once the MMU was mapped
541 to the kernel mappings (0XC0000000).
543 This unfortunately won't work for U-Boot and likely also won't
544 work for using KEXEC to have a hot kernel ready for doing a
547 So now the MMU is initialized in head.S but it's necessary to
548 use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup.
549 xt-gdb can't place a Software Breakpoint in the 0XD region prior
550 to mapping the MMU and after mapping even if the area of low memory
551 was mapped gdb wouldn't remove the breakpoint on hitting it as the
552 PC wouldn't match. Since Hardware Breakpoints are recommended for
553 Linux configurations it seems reasonable to just assume they exist
554 and leave this older mechanism for unfortunate souls that choose
555 not to follow Tensilica's recommendation.
557 Selecting this will cause U-Boot to set the KERNEL Load and Entry
558 address at 0x00003000 instead of the mapped std of 0xD0003000.
563 bool "Kernel Execute-In-Place from ROM"
564 depends on PLATFORM_HAVE_XIP
566 Execute-In-Place allows the kernel to run from non-volatile storage
567 directly addressable by the CPU, such as NOR flash. This saves RAM
568 space since the text section of the kernel is not loaded from flash
569 to RAM. Read-write sections, such as the data section and stack,
570 are still copied to RAM. The XIP kernel is not compressed since
571 it has to run directly from flash, so it will take more space to
572 store it. The flash address used to link the kernel object files,
573 and for storing it, is configuration dependent. Therefore, if you
574 say Y here, you must know the proper physical address where to
575 store the kernel image depending on your own flash memory usage.
577 Also note that the make target becomes "make xipImage" rather than
578 "make Image" or "make uImage". The final kernel binary to put in
579 ROM memory will be arch/xtensa/boot/xipImage.
583 config MEMMAP_CACHEATTR
584 hex "Cache attributes for the memory address space"
588 These cache attributes are set up for noMMU systems. Each hex digit
589 specifies cache attributes for the corresponding 512MB memory
590 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
591 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
593 Cache attribute values are specific for the MMU type.
594 For region protection MMUs:
606 3: special (c and e are illegal, f is reserved).
610 2: WB, no-write-allocate cache,
615 hex "Physical address of the KSEG mapping"
616 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU
619 This is the physical address where KSEG is mapped. Please refer to
620 the chosen KSEG layout help for the required address alignment.
621 Unpacked kernel image (including vectors) must be located completely
623 Physical memory below this address is not available to linux.
625 If unsure, leave the default value here.
627 config KERNEL_VIRTUAL_ADDRESS
628 hex "Kernel virtual address"
629 depends on MMU && XIP_KERNEL
632 This is the virtual address where the XIP kernel is mapped.
633 XIP kernel may be mapped into KSEG or KIO region, virtual address
634 provided here must match kernel load address provided in
637 config KERNEL_LOAD_ADDRESS
638 hex "Kernel load address"
639 default 0x60003000 if !MMU
640 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
641 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
643 This is the address where the kernel is loaded.
644 It is virtual address for MMUv2 configurations and physical address
645 for all other configurations.
647 If unsure, leave the default value here.
650 prompt "Relocatable vectors location"
651 default XTENSA_VECTORS_IN_TEXT
653 Choose whether relocatable vectors are merged into the kernel .text
654 or placed separately at runtime. This option does not affect
655 configurations without VECBASE register where vectors are always
656 placed at their hardware-defined locations.
658 config XTENSA_VECTORS_IN_TEXT
659 bool "Merge relocatable vectors into kernel text"
662 This option puts relocatable vectors into the kernel .text section
663 with proper alignment.
664 This is a safe choice for most configurations.
666 config XTENSA_VECTORS_SEPARATE
667 bool "Put relocatable vectors at fixed address"
669 This option puts relocatable vectors at specific virtual address.
670 Vectors are merged with the .init data in the kernel image and
671 are copied into their designated location during kernel startup.
672 Use it to put vectors into IRAM or out of FLASH on kernels with
673 XIP-aware MTD support.
678 hex "Kernel vectors virtual address"
680 depends on XTENSA_VECTORS_SEPARATE
682 This is the virtual address of the (relocatable) vectors base.
683 It must be within KSEG if MMU is used.
686 hex "XIP kernel data virtual address"
687 depends on XIP_KERNEL
690 This is the virtual address where XIP kernel data is copied.
691 It must be within KSEG if MMU is used.
693 config PLATFORM_WANT_DEFAULT_MEM
696 config DEFAULT_MEM_START
698 prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM
699 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM
702 This is the base address used for both PAGE_OFFSET and PHYS_OFFSET
703 in noMMU configurations.
705 If unsure, leave the default value here.
710 default XTENSA_KSEG_MMU_V2
712 config XTENSA_KSEG_MMU_V2
713 bool "MMUv2: 128MB cached + 128MB uncached"
715 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting
716 at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000
718 KSEG_PADDR must be aligned to 128MB.
720 config XTENSA_KSEG_256M
721 bool "256MB cached + 256MB uncached"
722 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
724 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000
725 with cache and to 0xc0000000 without cache.
726 KSEG_PADDR must be aligned to 256MB.
728 config XTENSA_KSEG_512M
729 bool "512MB cached + 512MB uncached"
730 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
732 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000
733 with cache and to 0xc0000000 without cache.
734 KSEG_PADDR must be aligned to 256MB.
739 bool "High Memory Support"
743 Linux can use the full amount of RAM in the system by
744 default. However, the default MMUv2 setup only maps the
745 lowermost 128 MB of memory linearly to the areas starting
746 at 0xd0000000 (cached) and 0xd8000000 (uncached).
747 When there are more than 128 MB memory in the system not
748 all of it can be "permanently mapped" by the kernel.
749 The physical memory that's not permanently mapped is called
752 If you are compiling a kernel which will never run on a
753 machine with more than 128 MB total physical RAM, answer
758 config FORCE_MAX_ZONEORDER
759 int "Maximum zone order"
762 The kernel memory allocator divides physically contiguous memory
763 blocks into "zones", where each zone is a power of two number of
764 pages. This option selects the largest power of two that the kernel
765 keeps in the memory allocator. If you need to allocate very large
766 blocks of physically contiguous memory, then you may need to
769 This config option is actually maximum order plus one. For example,
770 a value of 11 means that the largest free memory block is 2^10 pages.
774 menu "Power management options"
776 source "kernel/power/Kconfig"