1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Trampoline.S Derived from Setup.S by Linus Torvalds
6 * 4 Jan 1997 Michael Chastain: changed to gnu as.
7 * 15 Sept 2005 Eric Biederman: 64bit PIC support
9 * Entry: CS:IP point to the start of our code, we are
10 * in real mode with no stack, but the rest of the
11 * trampoline page to make our stack and everything else
14 * On entry to trampoline_start, the processor is in real mode
15 * with 16-bit addressing and 16-bit data. CS has some value
16 * and IP is zero. Thus, data addresses need to be absolute
17 * (no relocation) and are taken with regard to r_base.
19 * With the addition of trampoline_level4_pgt this code can
20 * now enter a 64bit kernel that lives at arbitrary 64bit
23 * If you work on this file, check the object module with objdump
24 * --full-contents --reloc to make sure there are no relocation
28 #include <linux/linkage.h>
29 #include <asm/pgtable_types.h>
30 #include <asm/page_types.h>
32 #include <asm/segment.h>
33 #include <asm/processor-flags.h>
34 #include <asm/realmode.h>
41 SYM_CODE_START(trampoline_start)
42 cli # We should be safe anyway
47 mov %cs, %ax # Code and data in the same place
53 movl $rm_stack_end, %esp
55 call verify_cpu # Verify the cpu supports long mode
56 testl %eax, %eax # Check for return code
59 .Lswitch_to_protected:
61 * GDT tables in non default location kernel can be beyond 16MB and
62 * lgdt will not be able to load the address as in real mode default
63 * operand size is 16bit. Use lgdtl instead to force operand size
67 lidtl tr_idt # load idt with 0, 0
68 lgdtl tr_gdt # load gdt with whatever is appropriate
70 movw $__KERNEL_DS, %dx # Data segment descriptor
72 # Enable protected mode
73 movl $(CR0_STATE & ~X86_CR0_PG), %eax
74 movl %eax, %cr0 # into protected mode
76 # flush prefetch and jump to startup_32
77 ljmpl $__KERNEL32_CS, $pa_startup_32
82 SYM_CODE_END(trampoline_start)
84 #ifdef CONFIG_AMD_MEM_ENCRYPT
85 /* SEV-ES supports non-zero IP for entry points - no alignment needed */
86 SYM_CODE_START(sev_es_trampoline_start)
87 cli # We should be safe anyway
91 mov %cs, %ax # Code and data in the same place
97 movl $rm_stack_end, %esp
99 jmp .Lswitch_to_protected
100 SYM_CODE_END(sev_es_trampoline_start)
101 #endif /* CONFIG_AMD_MEM_ENCRYPT */
103 #include "../kernel/verify_cpu.S"
105 .section ".text32","ax"
108 SYM_CODE_START(startup_32)
110 addl $pa_real_mode_base, %esp
117 * Check for memory encryption support. This is a safety net in
118 * case BIOS hasn't done the necessary step of setting the bit in
119 * the MSR for this AP. If SME is active and we've gotten this far
120 * then it is safe for us to set the MSR bit and continue. If we
121 * don't we'll eventually crash trying to execute encrypted
124 btl $TH_FLAGS_SME_ACTIVE_BIT, pa_tr_flags
126 movl $MSR_AMD64_SYSCFG, %ecx
128 bts $MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT, %eax
132 * Memory encryption is enabled but the SME enable bit for this
133 * CPU has has not been set. It is safe to set it, so do so.
139 movl %eax, %cr4 # Enable PAE mode
141 # Setup trampoline 4 level pagetables
142 movl $pa_trampoline_pgd, %eax
149 * Skip writing to EFER if the register already has desired
150 * value (to avoid #VE for the TDX guest).
154 cmp pa_tr_efer + 4, %edx
157 movl pa_tr_efer, %eax
158 movl pa_tr_efer + 4, %edx
162 # Enable paging and in turn activate Long Mode.
163 movl $CR0_STATE, %eax
167 * At this point we're in long mode but in 32bit compatibility mode
168 * with EFER.LME = 1, CS.L = 0, CS.D = 1 (and in turn
169 * EFER.LMA = 1). Now we want to jump in 64bit mode, to do that we use
170 * the new gdt/idt that has __KERNEL_CS with CS.L = 1.
172 ljmpl $__KERNEL_CS, $pa_startup_64
173 SYM_CODE_END(startup_32)
175 SYM_CODE_START(pa_trampoline_compat)
177 * In compatibility mode. Prep ESP and DX for startup_32, then disable
178 * paging and complete the switch to legacy 32-bit mode.
180 movl $rm_stack_end, %esp
181 movw $__KERNEL_DS, %dx
183 movl $(CR0_STATE & ~X86_CR0_PG), %eax
185 ljmpl $__KERNEL32_CS, $pa_startup_32
186 SYM_CODE_END(pa_trampoline_compat)
188 .section ".text64","ax"
191 SYM_CODE_START(startup_64)
192 # Now jump into the kernel using virtual addresses
194 SYM_CODE_END(startup_64)
196 SYM_CODE_START(trampoline_start64)
198 * APs start here on a direct transfer from 64-bit BIOS with identity
199 * mapped page tables. Load the kernel's GDT in order to gear down to
200 * 32-bit mode (to handle 4-level vs. 5-level paging), and to (re)load
201 * segment registers. Load the zero IDT so any fault triggers a
202 * shutdown instead of jumping back into BIOS.
207 ljmpl *tr_compat(%rip)
208 SYM_CODE_END(trampoline_start64)
210 .section ".rodata","a"
211 # Duplicate the global descriptor table
212 # so the kernel can live anywhere
214 SYM_DATA_START(tr_gdt)
215 .short tr_gdt_end - tr_gdt - 1 # gdt limit
218 .quad 0x00cf9b000000ffff # __KERNEL32_CS
219 .quad 0x00af9b000000ffff # __KERNEL_CS
220 .quad 0x00cf93000000ffff # __KERNEL_DS
221 SYM_DATA_END_LABEL(tr_gdt, SYM_L_LOCAL, tr_gdt_end)
223 SYM_DATA_START(tr_gdt64)
224 .short tr_gdt_end - tr_gdt - 1 # gdt limit
227 SYM_DATA_END(tr_gdt64)
229 SYM_DATA_START(tr_compat)
230 .long pa_trampoline_compat
232 SYM_DATA_END(tr_compat)
236 SYM_DATA(trampoline_pgd, .space PAGE_SIZE)
239 SYM_DATA_START(trampoline_header)
240 SYM_DATA_LOCAL(tr_start, .space 8)
241 SYM_DATA(tr_efer, .space 8)
242 SYM_DATA(tr_cr4, .space 4)
243 SYM_DATA(tr_flags, .space 4)
244 SYM_DATA_END(trampoline_header)
246 #include "trampoline_common.S"