1 // SPDX-License-Identifier: GPL-2.0-only
3 * Suspend support specific for i386/x86-64.
5 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
6 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
7 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
10 #include <linux/suspend.h>
11 #include <linux/export.h>
12 #include <linux/smp.h>
13 #include <linux/perf_event.h>
14 #include <linux/tboot.h>
15 #include <linux/dmi.h>
17 #include <asm/pgtable.h>
18 #include <asm/proto.h>
22 #include <asm/suspend.h>
23 #include <asm/fpu/internal.h>
24 #include <asm/debugreg.h>
26 #include <asm/mmu_context.h>
27 #include <asm/cpu_device_id.h>
30 __visible unsigned long saved_context_ebx;
31 __visible unsigned long saved_context_esp, saved_context_ebp;
32 __visible unsigned long saved_context_esi, saved_context_edi;
33 __visible unsigned long saved_context_eflags;
35 struct saved_context saved_context;
37 static void msr_save_context(struct saved_context *ctxt)
39 struct saved_msr *msr = ctxt->saved_msrs.array;
40 struct saved_msr *end = msr + ctxt->saved_msrs.num;
43 msr->valid = !rdmsrl_safe(msr->info.msr_no, &msr->info.reg.q);
48 static void msr_restore_context(struct saved_context *ctxt)
50 struct saved_msr *msr = ctxt->saved_msrs.array;
51 struct saved_msr *end = msr + ctxt->saved_msrs.num;
55 wrmsrl(msr->info.msr_no, msr->info.reg.q);
61 * __save_processor_state - save CPU registers before creating a
62 * hibernation image and before restoring the memory state from it
63 * @ctxt - structure to store the registers contents in
65 * NOTE: If there is a CPU register the modification of which by the
66 * boot kernel (ie. the kernel used for loading the hibernation image)
67 * might affect the operations of the restored target kernel (ie. the one
68 * saved in the hibernation image), then its contents must be saved by this
69 * function. In other words, if kernel A is hibernated and different
70 * kernel B is used for loading the hibernation image into memory, the
71 * kernel A's __save_processor_state() function must save all registers
72 * needed by kernel A, so that it can operate correctly after the resume
73 * regardless of what kernel B does in the meantime.
75 static void __save_processor_state(struct saved_context *ctxt)
78 mtrr_save_fixed_ranges(NULL);
85 store_idt(&ctxt->idt);
88 * We save it here, but restore it only in the hibernate case.
89 * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
90 * mode in "secondary_startup_64". In 32-bit mode it is done via
91 * 'pmode_gdt' in wakeup_start.
93 ctxt->gdt_desc.size = GDT_SIZE - 1;
94 ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_rw(smp_processor_id());
98 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
102 #ifdef CONFIG_X86_32_LAZY_GS
103 savesegment(gs, ctxt->gs);
106 savesegment(gs, ctxt->gs);
107 savesegment(fs, ctxt->fs);
108 savesegment(ds, ctxt->ds);
109 savesegment(es, ctxt->es);
111 rdmsrl(MSR_FS_BASE, ctxt->fs_base);
112 rdmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);
113 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
114 mtrr_save_fixed_ranges(NULL);
116 rdmsrl(MSR_EFER, ctxt->efer);
122 ctxt->cr0 = read_cr0();
123 ctxt->cr2 = read_cr2();
124 ctxt->cr3 = __read_cr3();
125 ctxt->cr4 = __read_cr4();
127 ctxt->cr8 = read_cr8();
129 ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
131 msr_save_context(ctxt);
134 /* Needed by apm.c */
135 void save_processor_state(void)
137 __save_processor_state(&saved_context);
138 x86_platform.save_sched_clock_state();
141 EXPORT_SYMBOL(save_processor_state);
144 static void do_fpu_end(void)
147 * Restore FPU regs if necessary.
152 static void fix_processor_context(void)
154 int cpu = smp_processor_id();
156 struct desc_struct *desc = get_cpu_gdt_rw(cpu);
161 * We need to reload TR, which requires that we change the
162 * GDT entry to indicate "available" first.
164 * XXX: This could probably all be replaced by a call to
167 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
170 memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
171 tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
172 write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
174 syscall_init(); /* This sets MSR_*STAR and related */
176 if (boot_cpu_has(X86_FEATURE_SEP))
179 load_TR_desc(); /* This does ltr */
180 load_mm_ldt(current->active_mm); /* This does lldt */
181 initialize_tlbstate_and_flush();
185 /* The processor is back on the direct GDT, load back the fixmap */
186 load_fixmap_gdt(cpu);
190 * __restore_processor_state - restore the contents of CPU registers saved
191 * by __save_processor_state()
192 * @ctxt - structure to load the registers contents from
194 * The asm code that gets us here will have restored a usable GDT, although
195 * it will be pointing to the wrong alias.
197 static void notrace __restore_processor_state(struct saved_context *ctxt)
199 if (ctxt->misc_enable_saved)
200 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
204 /* cr4 was introduced in the Pentium CPU */
207 __write_cr4(ctxt->cr4);
210 wrmsrl(MSR_EFER, ctxt->efer);
211 write_cr8(ctxt->cr8);
212 __write_cr4(ctxt->cr4);
214 write_cr3(ctxt->cr3);
215 write_cr2(ctxt->cr2);
216 write_cr0(ctxt->cr0);
218 /* Restore the IDT. */
219 load_idt(&ctxt->idt);
222 * Just in case the asm code got us here with the SS, DS, or ES
223 * out of sync with the GDT, update them.
225 loadsegment(ss, __KERNEL_DS);
226 loadsegment(ds, __USER_DS);
227 loadsegment(es, __USER_DS);
230 * Restore percpu access. Percpu access can happen in exception
231 * handlers or in complicated helpers like load_gs_index().
234 wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);
236 loadsegment(fs, __KERNEL_PERCPU);
237 loadsegment(gs, __KERNEL_STACK_CANARY);
240 /* Restore the TSS, RO GDT, LDT, and usermode-relevant MSRs. */
241 fix_processor_context();
244 * Now that we have descriptor tables fully restored and working
245 * exception handling, restore the usermode segments.
248 loadsegment(ds, ctxt->es);
249 loadsegment(es, ctxt->es);
250 loadsegment(fs, ctxt->fs);
251 load_gs_index(ctxt->gs);
254 * Restore FSBASE and GSBASE after restoring the selectors, since
255 * restoring the selectors clobbers the bases. Keep in mind
256 * that MSR_KERNEL_GS_BASE is horribly misnamed.
258 wrmsrl(MSR_FS_BASE, ctxt->fs_base);
259 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
260 #elif defined(CONFIG_X86_32_LAZY_GS)
261 loadsegment(gs, ctxt->gs);
265 tsc_verify_tsc_adjust(true);
266 x86_platform.restore_sched_clock_state();
268 perf_restore_debug_store();
269 msr_restore_context(ctxt);
272 /* Needed by apm.c */
273 void notrace restore_processor_state(void)
275 __restore_processor_state(&saved_context);
278 EXPORT_SYMBOL(restore_processor_state);
281 #if defined(CONFIG_HIBERNATION) && defined(CONFIG_HOTPLUG_CPU)
282 static void resume_play_dead(void)
285 tboot_shutdown(TB_SHUTDOWN_WFS);
289 int hibernate_resume_nonboot_cpu_disable(void)
291 void (*play_dead)(void) = smp_ops.play_dead;
295 * Ensure that MONITOR/MWAIT will not be used in the "play dead" loop
296 * during hibernate image restoration, because it is likely that the
297 * monitored address will be actually written to at that time and then
298 * the "dead" CPU will attempt to execute instructions again, but the
299 * address in its instruction pointer may not be possible to resolve
300 * any more at that point (the page tables used by it previously may
301 * have been overwritten by hibernate image data).
303 * First, make sure that we wake up all the potentially disabled SMT
304 * threads which have been initially brought up and then put into
305 * mwait/cpuidle sleep.
306 * Those will be put to proper (not interfering with hibernation
307 * resume) sleep afterwards, and the resumed kernel will decide itself
308 * what to do with them.
310 ret = cpuhp_smt_enable();
313 smp_ops.play_dead = resume_play_dead;
314 ret = disable_nonboot_cpus();
315 smp_ops.play_dead = play_dead;
321 * When bsp_check() is called in hibernate and suspend, cpu hotplug
322 * is disabled already. So it's unnessary to handle race condition between
323 * cpumask query and cpu hotplug.
325 static int bsp_check(void)
327 if (cpumask_first(cpu_online_mask) != 0) {
328 pr_warn("CPU0 is offline.\n");
335 static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
341 case PM_SUSPEND_PREPARE:
342 case PM_HIBERNATION_PREPARE:
345 #ifdef CONFIG_DEBUG_HOTPLUG_CPU0
346 case PM_RESTORE_PREPARE:
348 * When system resumes from hibernation, online CPU0 because
349 * 1. it's required for resume and
350 * 2. the CPU was online before hibernation
353 _debug_hotplug_cpu(0, 1);
355 case PM_POST_RESTORE:
357 * When a resume really happens, this code won't be called.
359 * This code is called only when user space hibernation software
360 * prepares for snapshot device during boot time. So we just
361 * call _debug_hotplug_cpu() to restore to CPU0's state prior to
362 * preparing the snapshot device.
364 * This works for normal boot case in our CPU0 hotplug debug
365 * mode, i.e. CPU0 is offline and user mode hibernation
366 * software initializes during boot time.
368 * If CPU0 is online and user application accesses snapshot
369 * device after boot time, this will offline CPU0 and user may
370 * see different CPU0 state before and after accessing
371 * the snapshot device. But hopefully this is not a case when
372 * user debugging CPU0 hotplug. Even if users hit this case,
373 * they can easily online CPU0 back.
375 * To simplify this debug code, we only consider normal boot
376 * case. Otherwise we need to remember CPU0's state and restore
377 * to that state and resolve racy conditions etc.
379 _debug_hotplug_cpu(0, 0);
385 return notifier_from_errno(ret);
388 static int __init bsp_pm_check_init(void)
391 * Set this bsp_pm_callback as lower priority than
392 * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
393 * earlier to disable cpu hotplug before bsp online check.
395 pm_notifier(bsp_pm_callback, -INT_MAX);
399 core_initcall(bsp_pm_check_init);
401 static int msr_build_context(const u32 *msr_id, const int num)
403 struct saved_msrs *saved_msrs = &saved_context.saved_msrs;
404 struct saved_msr *msr_array;
408 total_num = saved_msrs->num + num;
410 msr_array = kmalloc_array(total_num, sizeof(struct saved_msr), GFP_KERNEL);
412 pr_err("x86/pm: Can not allocate memory to save/restore MSRs during suspend.\n");
416 if (saved_msrs->array) {
418 * Multiple callbacks can invoke this function, so copy any
419 * MSR save requests from previous invocations.
421 memcpy(msr_array, saved_msrs->array,
422 sizeof(struct saved_msr) * saved_msrs->num);
424 kfree(saved_msrs->array);
427 for (i = saved_msrs->num, j = 0; i < total_num; i++, j++) {
428 msr_array[i].info.msr_no = msr_id[j];
429 msr_array[i].valid = false;
430 msr_array[i].info.reg.q = 0;
432 saved_msrs->num = total_num;
433 saved_msrs->array = msr_array;
439 * The following sections are a quirk framework for problematic BIOSen:
440 * Sometimes MSRs are modified by the BIOSen after suspended to
441 * RAM, this might cause unexpected behavior after wakeup.
442 * Thus we save/restore these specified MSRs across suspend/resume
443 * in order to work around it.
445 * For any further problematic BIOSen/platforms,
446 * please add your own function similar to msr_initialize_bdw.
448 static int msr_initialize_bdw(const struct dmi_system_id *d)
450 /* Add any extra MSR ids into this array. */
451 u32 bdw_msr_id[] = { MSR_IA32_THERM_CONTROL };
453 pr_info("x86/pm: %s detected, MSR saving is needed during suspending.\n", d->ident);
454 return msr_build_context(bdw_msr_id, ARRAY_SIZE(bdw_msr_id));
457 static const struct dmi_system_id msr_save_dmi_table[] = {
459 .callback = msr_initialize_bdw,
460 .ident = "BROADWELL BDX_EP",
462 DMI_MATCH(DMI_PRODUCT_NAME, "GRANTLEY"),
463 DMI_MATCH(DMI_PRODUCT_VERSION, "E63448-400"),
469 static int msr_save_cpuid_features(const struct x86_cpu_id *c)
471 u32 cpuid_msr_id[] = {
472 MSR_AMD64_CPUID_FN_1,
475 pr_info("x86/pm: family %#hx cpu detected, MSR saving is needed during suspending.\n",
478 return msr_build_context(cpuid_msr_id, ARRAY_SIZE(cpuid_msr_id));
481 static const struct x86_cpu_id msr_save_cpu_table[] = {
483 .vendor = X86_VENDOR_AMD,
485 .model = X86_MODEL_ANY,
486 .feature = X86_FEATURE_ANY,
487 .driver_data = (kernel_ulong_t)msr_save_cpuid_features,
490 .vendor = X86_VENDOR_AMD,
492 .model = X86_MODEL_ANY,
493 .feature = X86_FEATURE_ANY,
494 .driver_data = (kernel_ulong_t)msr_save_cpuid_features,
499 typedef int (*pm_cpu_match_t)(const struct x86_cpu_id *);
500 static int pm_cpu_check(const struct x86_cpu_id *c)
502 const struct x86_cpu_id *m;
505 m = x86_match_cpu(msr_save_cpu_table);
509 fn = (pm_cpu_match_t)m->driver_data;
516 static int pm_check_save_msr(void)
518 dmi_check_system(msr_save_dmi_table);
519 pm_cpu_check(msr_save_cpu_table);
524 device_initcall(pm_check_save_msr);