1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * x86 instruction analysis
5 * Copyright (C) IBM Corporation, 2002, 2004, 2009
8 #include <linux/kernel.h>
10 #include <linux/string.h>
14 #include <asm/inat.h> /*__ignore_sync_check__ */
15 #include <asm/insn.h> /* __ignore_sync_check__ */
16 #include <asm/unaligned.h> /* __ignore_sync_check__ */
18 #include <linux/errno.h>
19 #include <linux/kconfig.h>
21 #include <asm/emulate_prefix.h> /* __ignore_sync_check__ */
23 #define leXX_to_cpu(t, r) \
26 switch (sizeof(t)) { \
27 case 4: v = le32_to_cpu(r); break; \
28 case 2: v = le16_to_cpu(r); break; \
29 case 1: v = r; break; \
36 /* Verify next sizeof(t) bytes can be on the same instruction */
37 #define validate_next(t, insn, n) \
38 ((insn)->next_byte + sizeof(t) + n <= (insn)->end_kaddr)
40 #define __get_next(t, insn) \
41 ({ t r = get_unaligned((t *)(insn)->next_byte); (insn)->next_byte += sizeof(t); leXX_to_cpu(t, r); })
43 #define __peek_nbyte_next(t, insn, n) \
44 ({ t r = get_unaligned((t *)(insn)->next_byte + n); leXX_to_cpu(t, r); })
46 #define get_next(t, insn) \
47 ({ if (unlikely(!validate_next(t, insn, 0))) goto err_out; __get_next(t, insn); })
49 #define peek_nbyte_next(t, insn, n) \
50 ({ if (unlikely(!validate_next(t, insn, n))) goto err_out; __peek_nbyte_next(t, insn, n); })
52 #define peek_next(t, insn) peek_nbyte_next(t, insn, 0)
55 * insn_init() - initialize struct insn
56 * @insn: &struct insn to be initialized
57 * @kaddr: address (in kernel memory) of instruction (or copy thereof)
58 * @buf_len: length of the insn buffer at @kaddr
59 * @x86_64: !0 for 64-bit kernel or 64-bit app
61 void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64)
64 * Instructions longer than MAX_INSN_SIZE (15 bytes) are invalid
65 * even if the input buffer is long enough to hold them.
67 if (buf_len > MAX_INSN_SIZE)
68 buf_len = MAX_INSN_SIZE;
70 memset(insn, 0, sizeof(*insn));
72 insn->end_kaddr = kaddr + buf_len;
73 insn->next_byte = kaddr;
74 insn->x86_64 = x86_64;
82 static const insn_byte_t xen_prefix[] = { __XEN_EMULATE_PREFIX };
83 static const insn_byte_t kvm_prefix[] = { __KVM_EMULATE_PREFIX };
85 static int __insn_get_emulate_prefix(struct insn *insn,
86 const insn_byte_t *prefix, size_t len)
90 for (i = 0; i < len; i++) {
91 if (peek_nbyte_next(insn_byte_t, insn, i) != prefix[i])
95 insn->emulate_prefix_size = len;
96 insn->next_byte += len;
104 static void insn_get_emulate_prefix(struct insn *insn)
106 if (__insn_get_emulate_prefix(insn, xen_prefix, sizeof(xen_prefix)))
109 __insn_get_emulate_prefix(insn, kvm_prefix, sizeof(kvm_prefix));
113 * insn_get_prefixes - scan x86 instruction prefix bytes
114 * @insn: &struct insn containing instruction
116 * Populates the @insn->prefixes bitmap, and updates @insn->next_byte
117 * to point to the (first) opcode. No effect if @insn->prefixes.got
124 int insn_get_prefixes(struct insn *insn)
126 struct insn_field *prefixes = &insn->prefixes;
134 insn_get_emulate_prefix(insn);
138 b = peek_next(insn_byte_t, insn);
139 attr = inat_get_opcode_attribute(b);
140 while (inat_is_legacy_prefix(attr)) {
141 /* Skip if same prefix */
142 for (i = 0; i < nb; i++)
143 if (prefixes->bytes[i] == b)
146 /* Invalid instruction */
148 prefixes->bytes[nb++] = b;
149 if (inat_is_address_size_prefix(attr)) {
150 /* address size switches 2/4 or 4/8 */
152 insn->addr_bytes ^= 12;
154 insn->addr_bytes ^= 6;
155 } else if (inat_is_operand_size_prefix(attr)) {
156 /* oprand size switches 2/4 */
157 insn->opnd_bytes ^= 6;
163 b = peek_next(insn_byte_t, insn);
164 attr = inat_get_opcode_attribute(b);
166 /* Set the last prefix */
167 if (lb && lb != insn->prefixes.bytes[3]) {
168 if (unlikely(insn->prefixes.bytes[3])) {
169 /* Swap the last prefix */
170 b = insn->prefixes.bytes[3];
171 for (i = 0; i < nb; i++)
172 if (prefixes->bytes[i] == lb)
173 insn_set_byte(prefixes, i, b);
175 insn_set_byte(&insn->prefixes, 3, lb);
178 /* Decode REX prefix */
180 b = peek_next(insn_byte_t, insn);
181 attr = inat_get_opcode_attribute(b);
182 if (inat_is_rex_prefix(attr)) {
183 insn_field_set(&insn->rex_prefix, b, 1);
186 /* REX.W overrides opnd_size */
187 insn->opnd_bytes = 8;
190 insn->rex_prefix.got = 1;
192 /* Decode VEX prefix */
193 b = peek_next(insn_byte_t, insn);
194 attr = inat_get_opcode_attribute(b);
195 if (inat_is_vex_prefix(attr)) {
196 insn_byte_t b2 = peek_nbyte_next(insn_byte_t, insn, 1);
199 * In 32-bits mode, if the [7:6] bits (mod bits of
200 * ModRM) on the second byte are not 11b, it is
201 * LDS or LES or BOUND.
203 if (X86_MODRM_MOD(b2) != 3)
206 insn_set_byte(&insn->vex_prefix, 0, b);
207 insn_set_byte(&insn->vex_prefix, 1, b2);
208 if (inat_is_evex_prefix(attr)) {
209 b2 = peek_nbyte_next(insn_byte_t, insn, 2);
210 insn_set_byte(&insn->vex_prefix, 2, b2);
211 b2 = peek_nbyte_next(insn_byte_t, insn, 3);
212 insn_set_byte(&insn->vex_prefix, 3, b2);
213 insn->vex_prefix.nbytes = 4;
214 insn->next_byte += 4;
215 if (insn->x86_64 && X86_VEX_W(b2))
216 /* VEX.W overrides opnd_size */
217 insn->opnd_bytes = 8;
218 } else if (inat_is_vex3_prefix(attr)) {
219 b2 = peek_nbyte_next(insn_byte_t, insn, 2);
220 insn_set_byte(&insn->vex_prefix, 2, b2);
221 insn->vex_prefix.nbytes = 3;
222 insn->next_byte += 3;
223 if (insn->x86_64 && X86_VEX_W(b2))
224 /* VEX.W overrides opnd_size */
225 insn->opnd_bytes = 8;
228 * For VEX2, fake VEX3-like byte#2.
229 * Makes it easier to decode vex.W, vex.vvvv,
230 * vex.L and vex.pp. Masking with 0x7f sets vex.W == 0.
232 insn_set_byte(&insn->vex_prefix, 2, b2 & 0x7f);
233 insn->vex_prefix.nbytes = 2;
234 insn->next_byte += 2;
238 insn->vex_prefix.got = 1;
249 * insn_get_opcode - collect opcode(s)
250 * @insn: &struct insn containing instruction
252 * Populates @insn->opcode, updates @insn->next_byte to point past the
253 * opcode byte(s), and set @insn->attr (except for groups).
254 * If necessary, first collects any preceding (prefix) bytes.
255 * Sets @insn->opcode.value = opcode1. No effect if @insn->opcode.got
262 int insn_get_opcode(struct insn *insn)
264 struct insn_field *opcode = &insn->opcode;
271 ret = insn_get_prefixes(insn);
275 /* Get first opcode */
276 op = get_next(insn_byte_t, insn);
277 insn_set_byte(opcode, 0, op);
280 /* Check if there is VEX prefix or not */
281 if (insn_is_avx(insn)) {
283 m = insn_vex_m_bits(insn);
284 p = insn_vex_p_bits(insn);
285 insn->attr = inat_get_avx_attribute(op, m, p);
286 if ((inat_must_evex(insn->attr) && !insn_is_evex(insn)) ||
287 (!inat_accept_vex(insn->attr) &&
288 !inat_is_group(insn->attr))) {
289 /* This instruction is bad */
293 /* VEX has only 1 byte for opcode */
297 insn->attr = inat_get_opcode_attribute(op);
298 while (inat_is_escape(insn->attr)) {
299 /* Get escaped opcode */
300 op = get_next(insn_byte_t, insn);
301 opcode->bytes[opcode->nbytes++] = op;
302 pfx_id = insn_last_prefix_id(insn);
303 insn->attr = inat_get_escape_attribute(op, pfx_id, insn->attr);
306 if (inat_must_vex(insn->attr)) {
307 /* This instruction is bad */
320 * insn_get_modrm - collect ModRM byte, if any
321 * @insn: &struct insn containing instruction
323 * Populates @insn->modrm and updates @insn->next_byte to point past the
324 * ModRM byte, if any. If necessary, first collects the preceding bytes
325 * (prefixes and opcode(s)). No effect if @insn->modrm.got is already 1.
331 int insn_get_modrm(struct insn *insn)
333 struct insn_field *modrm = &insn->modrm;
334 insn_byte_t pfx_id, mod;
340 ret = insn_get_opcode(insn);
344 if (inat_has_modrm(insn->attr)) {
345 mod = get_next(insn_byte_t, insn);
346 insn_field_set(modrm, mod, 1);
347 if (inat_is_group(insn->attr)) {
348 pfx_id = insn_last_prefix_id(insn);
349 insn->attr = inat_get_group_attribute(mod, pfx_id,
351 if (insn_is_avx(insn) && !inat_accept_vex(insn->attr)) {
359 if (insn->x86_64 && inat_is_force64(insn->attr))
360 insn->opnd_bytes = 8;
371 * insn_rip_relative() - Does instruction use RIP-relative addressing mode?
372 * @insn: &struct insn containing instruction
374 * If necessary, first collects the instruction up to and including the
375 * ModRM byte. No effect if @insn->x86_64 is 0.
377 int insn_rip_relative(struct insn *insn)
379 struct insn_field *modrm = &insn->modrm;
385 ret = insn_get_modrm(insn);
389 * For rip-relative instructions, the mod field (top 2 bits)
390 * is zero and the r/m field (bottom 3 bits) is 0x5.
392 return (modrm->nbytes && (modrm->bytes[0] & 0xc7) == 0x5);
396 * insn_get_sib() - Get the SIB byte of instruction
397 * @insn: &struct insn containing instruction
399 * If necessary, first collects the instruction up to and including the
403 * 0: if decoding succeeded
406 int insn_get_sib(struct insn *insn)
414 ret = insn_get_modrm(insn);
418 if (insn->modrm.nbytes) {
419 modrm = insn->modrm.bytes[0];
420 if (insn->addr_bytes != 2 &&
421 X86_MODRM_MOD(modrm) != 3 && X86_MODRM_RM(modrm) == 4) {
422 insn_field_set(&insn->sib,
423 get_next(insn_byte_t, insn), 1);
436 * insn_get_displacement() - Get the displacement of instruction
437 * @insn: &struct insn containing instruction
439 * If necessary, first collects the instruction up to and including the
441 * Displacement value is sign-expanded.
444 * 0: if decoding succeeded
447 int insn_get_displacement(struct insn *insn)
449 insn_byte_t mod, rm, base;
452 if (insn->displacement.got)
455 ret = insn_get_sib(insn);
459 if (insn->modrm.nbytes) {
461 * Interpreting the modrm byte:
462 * mod = 00 - no displacement fields (exceptions below)
463 * mod = 01 - 1-byte displacement field
464 * mod = 10 - displacement field is 4 bytes, or 2 bytes if
465 * address size = 2 (0x67 prefix in 32-bit mode)
466 * mod = 11 - no memory operand
468 * If address size = 2...
469 * mod = 00, r/m = 110 - displacement field is 2 bytes
471 * If address size != 2...
472 * mod != 11, r/m = 100 - SIB byte exists
473 * mod = 00, SIB base = 101 - displacement field is 4 bytes
474 * mod = 00, r/m = 101 - rip-relative addressing, displacement
477 mod = X86_MODRM_MOD(insn->modrm.value);
478 rm = X86_MODRM_RM(insn->modrm.value);
479 base = X86_SIB_BASE(insn->sib.value);
483 insn_field_set(&insn->displacement,
484 get_next(signed char, insn), 1);
485 } else if (insn->addr_bytes == 2) {
486 if ((mod == 0 && rm == 6) || mod == 2) {
487 insn_field_set(&insn->displacement,
488 get_next(short, insn), 2);
491 if ((mod == 0 && rm == 5) || mod == 2 ||
492 (mod == 0 && base == 5)) {
493 insn_field_set(&insn->displacement,
494 get_next(int, insn), 4);
499 insn->displacement.got = 1;
506 /* Decode moffset16/32/64. Return 0 if failed */
507 static int __get_moffset(struct insn *insn)
509 switch (insn->addr_bytes) {
511 insn_field_set(&insn->moffset1, get_next(short, insn), 2);
514 insn_field_set(&insn->moffset1, get_next(int, insn), 4);
517 insn_field_set(&insn->moffset1, get_next(int, insn), 4);
518 insn_field_set(&insn->moffset2, get_next(int, insn), 4);
520 default: /* opnd_bytes must be modified manually */
523 insn->moffset1.got = insn->moffset2.got = 1;
531 /* Decode imm v32(Iz). Return 0 if failed */
532 static int __get_immv32(struct insn *insn)
534 switch (insn->opnd_bytes) {
536 insn_field_set(&insn->immediate, get_next(short, insn), 2);
540 insn_field_set(&insn->immediate, get_next(int, insn), 4);
542 default: /* opnd_bytes must be modified manually */
552 /* Decode imm v64(Iv/Ov), Return 0 if failed */
553 static int __get_immv(struct insn *insn)
555 switch (insn->opnd_bytes) {
557 insn_field_set(&insn->immediate1, get_next(short, insn), 2);
560 insn_field_set(&insn->immediate1, get_next(int, insn), 4);
561 insn->immediate1.nbytes = 4;
564 insn_field_set(&insn->immediate1, get_next(int, insn), 4);
565 insn_field_set(&insn->immediate2, get_next(int, insn), 4);
567 default: /* opnd_bytes must be modified manually */
570 insn->immediate1.got = insn->immediate2.got = 1;
577 /* Decode ptr16:16/32(Ap) */
578 static int __get_immptr(struct insn *insn)
580 switch (insn->opnd_bytes) {
582 insn_field_set(&insn->immediate1, get_next(short, insn), 2);
585 insn_field_set(&insn->immediate1, get_next(int, insn), 4);
588 /* ptr16:64 is not exist (no segment) */
590 default: /* opnd_bytes must be modified manually */
593 insn_field_set(&insn->immediate2, get_next(unsigned short, insn), 2);
594 insn->immediate1.got = insn->immediate2.got = 1;
602 * insn_get_immediate() - Get the immediate in an instruction
603 * @insn: &struct insn containing instruction
605 * If necessary, first collects the instruction up to and including the
606 * displacement bytes.
607 * Basically, most of immediates are sign-expanded. Unsigned-value can be
608 * computed by bit masking with ((1 << (nbytes * 8)) - 1)
614 int insn_get_immediate(struct insn *insn)
618 if (insn->immediate.got)
621 ret = insn_get_displacement(insn);
625 if (inat_has_moffset(insn->attr)) {
626 if (!__get_moffset(insn))
631 if (!inat_has_immediate(insn->attr))
635 switch (inat_immediate_size(insn->attr)) {
637 insn_field_set(&insn->immediate, get_next(signed char, insn), 1);
640 insn_field_set(&insn->immediate, get_next(short, insn), 2);
643 insn_field_set(&insn->immediate, get_next(int, insn), 4);
646 insn_field_set(&insn->immediate1, get_next(int, insn), 4);
647 insn_field_set(&insn->immediate2, get_next(int, insn), 4);
650 if (!__get_immptr(insn))
653 case INAT_IMM_VWORD32:
654 if (!__get_immv32(insn))
658 if (!__get_immv(insn))
662 /* Here, insn must have an immediate, but failed */
665 if (inat_has_second_immediate(insn->attr)) {
666 insn_field_set(&insn->immediate2, get_next(signed char, insn), 1);
669 insn->immediate.got = 1;
677 * insn_get_length() - Get the length of instruction
678 * @insn: &struct insn containing instruction
680 * If necessary, first collects the instruction up to and including the
687 int insn_get_length(struct insn *insn)
694 ret = insn_get_immediate(insn);
698 insn->length = (unsigned char)((unsigned long)insn->next_byte
699 - (unsigned long)insn->kaddr);
704 /* Ensure this instruction is decoded completely */
705 static inline int insn_complete(struct insn *insn)
707 return insn->opcode.got && insn->modrm.got && insn->sib.got &&
708 insn->displacement.got && insn->immediate.got;
712 * insn_decode() - Decode an x86 instruction
713 * @insn: &struct insn to be initialized
714 * @kaddr: address (in kernel memory) of instruction (or copy thereof)
715 * @buf_len: length of the insn buffer at @kaddr
716 * @m: insn mode, see enum insn_mode
719 * 0: if decoding succeeded
722 int insn_decode(struct insn *insn, const void *kaddr, int buf_len, enum insn_mode m)
726 /* #define INSN_MODE_KERN -1 __ignore_sync_check__ mode is only valid in the kernel */
728 if (m == INSN_MODE_KERN)
729 insn_init(insn, kaddr, buf_len, IS_ENABLED(CONFIG_X86_64));
731 insn_init(insn, kaddr, buf_len, m == INSN_MODE_64);
733 ret = insn_get_length(insn);
737 if (insn_complete(insn))