1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef ARCH_X86_KVM_X86_H
3 #define ARCH_X86_KVM_X86_H
5 #include <linux/kvm_host.h>
7 #include <asm/pvclock.h>
8 #include "kvm_cache_regs.h"
9 #include "kvm_emulate.h"
11 void kvm_spurious_fault(void);
13 #define KVM_NESTED_VMENTER_CONSISTENCY_CHECK(consistency_check) \
15 bool failed = (consistency_check); \
17 trace_kvm_nested_vmenter_failed(#consistency_check, 0); \
21 #define KVM_DEFAULT_PLE_GAP 128
22 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
23 #define KVM_DEFAULT_PLE_WINDOW_GROW 2
24 #define KVM_DEFAULT_PLE_WINDOW_SHRINK 0
25 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX
26 #define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX
27 #define KVM_SVM_DEFAULT_PLE_WINDOW 3000
29 static inline unsigned int __grow_ple_window(unsigned int val,
30 unsigned int base, unsigned int modifier, unsigned int max)
42 return min(ret, (u64)max);
45 static inline unsigned int __shrink_ple_window(unsigned int val,
46 unsigned int base, unsigned int modifier, unsigned int min)
59 #define MSR_IA32_CR_PAT_DEFAULT 0x0007040600070406ULL
61 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu);
62 int kvm_check_nested_events(struct kvm_vcpu *vcpu);
64 static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu)
66 vcpu->arch.exception.pending = false;
67 vcpu->arch.exception.injected = false;
70 static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector,
73 vcpu->arch.interrupt.injected = true;
74 vcpu->arch.interrupt.soft = soft;
75 vcpu->arch.interrupt.nr = vector;
78 static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu)
80 vcpu->arch.interrupt.injected = false;
83 static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu)
85 return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected ||
86 vcpu->arch.nmi_injected;
89 static inline bool kvm_exception_is_soft(unsigned int nr)
91 return (nr == BP_VECTOR) || (nr == OF_VECTOR);
94 static inline bool is_protmode(struct kvm_vcpu *vcpu)
96 return kvm_read_cr0_bits(vcpu, X86_CR0_PE);
99 static inline int is_long_mode(struct kvm_vcpu *vcpu)
102 return vcpu->arch.efer & EFER_LMA;
108 static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu)
112 WARN_ON_ONCE(vcpu->arch.guest_state_protected);
114 if (!is_long_mode(vcpu))
116 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
120 static inline bool is_64_bit_hypercall(struct kvm_vcpu *vcpu)
123 * If running with protected guest state, the CS register is not
124 * accessible. The hypercall register values will have had to been
125 * provided in 64-bit mode, so assume the guest is in 64-bit.
127 return vcpu->arch.guest_state_protected || is_64_bit_mode(vcpu);
130 static inline bool x86_exception_has_error_code(unsigned int vector)
132 static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) |
133 BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) |
134 BIT(PF_VECTOR) | BIT(AC_VECTOR);
136 return (1U << vector) & exception_has_error_code;
139 static inline bool mmu_is_nested(struct kvm_vcpu *vcpu)
141 return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;
144 static inline int is_pae(struct kvm_vcpu *vcpu)
146 return kvm_read_cr4_bits(vcpu, X86_CR4_PAE);
149 static inline int is_pse(struct kvm_vcpu *vcpu)
151 return kvm_read_cr4_bits(vcpu, X86_CR4_PSE);
154 static inline int is_paging(struct kvm_vcpu *vcpu)
156 return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG));
159 static inline bool is_pae_paging(struct kvm_vcpu *vcpu)
161 return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu);
164 static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
166 return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48;
169 static inline u64 get_canonical(u64 la, u8 vaddr_bits)
171 return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits);
174 static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu)
176 return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la;
179 static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
180 gva_t gva, gfn_t gfn, unsigned access)
182 u64 gen = kvm_memslots(vcpu->kvm)->generation;
184 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
188 * If this is a shadow nested page table, the "GVA" is
191 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK;
192 vcpu->arch.mmio_access = access;
193 vcpu->arch.mmio_gfn = gfn;
194 vcpu->arch.mmio_gen = gen;
197 static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu)
199 return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation;
203 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we
204 * clear all mmio cache info.
206 #define MMIO_GVA_ANY (~(gva_t)0)
208 static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
210 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
213 vcpu->arch.mmio_gva = 0;
216 static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
218 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva &&
219 vcpu->arch.mmio_gva == (gva & PAGE_MASK))
225 static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
227 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn &&
228 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
234 static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu, int reg)
236 unsigned long val = kvm_register_read_raw(vcpu, reg);
238 return is_64_bit_mode(vcpu) ? val : (u32)val;
241 static inline void kvm_register_write(struct kvm_vcpu *vcpu,
242 int reg, unsigned long val)
244 if (!is_64_bit_mode(vcpu))
246 return kvm_register_write_raw(vcpu, reg, val);
249 static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
251 return !(kvm->arch.disabled_quirks & quirk);
254 static inline bool kvm_vcpu_latch_init(struct kvm_vcpu *vcpu)
256 return is_smm(vcpu) || static_call(kvm_x86_apic_init_signal_blocked)(vcpu);
259 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
261 u64 get_kvmclock_ns(struct kvm *kvm);
263 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
264 gva_t addr, void *val, unsigned int bytes,
265 struct x86_exception *exception);
267 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu,
268 gva_t addr, void *val, unsigned int bytes,
269 struct x86_exception *exception);
271 int handle_ud(struct kvm_vcpu *vcpu);
273 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu);
275 void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu);
276 u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
277 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data);
278 int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
279 int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
280 bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn,
282 bool kvm_vector_hashing_enabled(void);
283 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code);
284 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
285 void *insn, int insn_len);
286 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
287 int emulation_type, void *insn, int insn_len);
288 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu);
290 extern u64 host_xcr0;
291 extern u64 supported_xcr0;
293 extern u64 supported_xss;
294 extern bool enable_pmu;
296 static inline bool kvm_mpx_supported(void)
298 return (supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR))
299 == (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
302 extern unsigned int min_timer_period_us;
304 extern bool enable_vmware_backdoor;
306 extern int pi_inject_timer;
308 extern bool report_ignored_msrs;
310 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
312 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
313 vcpu->arch.virtual_tsc_shift);
316 /* Same "calling convention" as do_div:
317 * - divide (n << 32) by base
321 #define do_shl32_div32(n, base) \
324 asm("divl %2" : "=a" (__quot), "=d" (__rem) \
325 : "rm" (base), "0" (0), "1" ((u32) n)); \
330 static inline bool kvm_mwait_in_guest(struct kvm *kvm)
332 return kvm->arch.mwait_in_guest;
335 static inline bool kvm_hlt_in_guest(struct kvm *kvm)
337 return kvm->arch.hlt_in_guest;
340 static inline bool kvm_pause_in_guest(struct kvm *kvm)
342 return kvm->arch.pause_in_guest;
345 static inline bool kvm_cstate_in_guest(struct kvm *kvm)
347 return kvm->arch.cstate_in_guest;
351 /* Values are arbitrary, but must be non-zero. */
352 KVM_HANDLING_IRQ = 1,
356 static inline void kvm_before_interrupt(struct kvm_vcpu *vcpu,
357 enum kvm_intr_type intr)
359 WRITE_ONCE(vcpu->arch.handling_intr_from_guest, (u8)intr);
362 static inline void kvm_after_interrupt(struct kvm_vcpu *vcpu)
364 WRITE_ONCE(vcpu->arch.handling_intr_from_guest, 0);
367 static inline bool kvm_handling_nmi_from_guest(struct kvm_vcpu *vcpu)
369 return vcpu->arch.handling_intr_from_guest == KVM_HANDLING_NMI;
372 static inline bool kvm_pat_valid(u64 data)
374 if (data & 0xF8F8F8F8F8F8F8F8ull)
376 /* 0, 1, 4, 5, 6, 7 are valid values. */
377 return (data | ((data & 0x0202020202020202ull) << 1)) == data;
380 static inline bool kvm_dr7_valid(u64 data)
382 /* Bits [63:32] are reserved */
383 return !(data >> 32);
385 static inline bool kvm_dr6_valid(u64 data)
387 /* Bits [63:32] are reserved */
388 return !(data >> 32);
392 * Trigger machine check on the host. We assume all the MSRs are already set up
393 * by the CPU and that we still run on the same CPU as the MCE occurred on.
394 * We pass a fake environment to the machine check handler because we want
395 * the guest to be always treated like user space, no matter what context
396 * it used internally.
398 static inline void kvm_machine_check(void)
400 #if defined(CONFIG_X86_MCE)
401 struct pt_regs regs = {
402 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
403 .flags = X86_EFLAGS_IF,
406 do_machine_check(®s);
410 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu);
411 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu);
412 int kvm_spec_ctrl_test_value(u64 value);
413 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
414 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
415 struct x86_exception *e);
416 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva);
417 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type);
420 * Internal error codes that are used to indicate that MSR emulation encountered
421 * an error that should result in #GP in the guest, unless userspace
424 #define KVM_MSR_RET_INVALID 2 /* in-kernel MSR emulation #GP condition */
425 #define KVM_MSR_RET_FILTERED 3 /* #GP due to userspace MSR filter */
427 #define __cr4_reserved_bits(__cpu_has, __c) \
429 u64 __reserved_bits = CR4_RESERVED_BITS; \
431 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
432 __reserved_bits |= X86_CR4_OSXSAVE; \
433 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \
434 __reserved_bits |= X86_CR4_SMEP; \
435 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \
436 __reserved_bits |= X86_CR4_SMAP; \
437 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \
438 __reserved_bits |= X86_CR4_FSGSBASE; \
439 if (!__cpu_has(__c, X86_FEATURE_PKU)) \
440 __reserved_bits |= X86_CR4_PKE; \
441 if (!__cpu_has(__c, X86_FEATURE_LA57)) \
442 __reserved_bits |= X86_CR4_LA57; \
443 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \
444 __reserved_bits |= X86_CR4_UMIP; \
445 if (!__cpu_has(__c, X86_FEATURE_VMX)) \
446 __reserved_bits |= X86_CR4_VMXE; \
447 if (!__cpu_has(__c, X86_FEATURE_PCID)) \
448 __reserved_bits |= X86_CR4_PCIDE; \
452 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
454 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
456 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
457 unsigned int port, void *data, unsigned int count,