1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef ARCH_X86_KVM_X86_H
3 #define ARCH_X86_KVM_X86_H
5 #include <linux/kvm_host.h>
7 #include <asm/pvclock.h>
8 #include "kvm_cache_regs.h"
9 #include "kvm_emulate.h"
11 static __always_inline void kvm_guest_enter_irqoff(void)
14 * VMENTER enables interrupts (host state), but the kernel state is
15 * interrupts disabled when this is invoked. Also tell RCU about
16 * it. This is the same logic as for exit_to_user_mode().
18 * This ensures that e.g. latency analysis on the host observes
19 * guest mode as interrupt enabled.
21 * guest_enter_irqoff() informs context tracking about the
22 * transition to guest mode and if enabled adjusts RCU state
25 instrumentation_begin();
26 trace_hardirqs_on_prepare();
27 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
28 instrumentation_end();
31 lockdep_hardirqs_on(CALLER_ADDR0);
34 static __always_inline void kvm_guest_exit_irqoff(void)
37 * VMEXIT disables interrupts (host state), but tracing and lockdep
38 * have them in state 'on' as recorded before entering guest mode.
39 * Same as enter_from_user_mode().
41 * context_tracking_guest_exit() restores host context and reinstates
42 * RCU if enabled and required.
44 * This needs to be done immediately after VM-Exit, before any code
45 * that might contain tracepoints or call out to the greater world,
46 * e.g. before x86_spec_ctrl_restore_host().
48 lockdep_hardirqs_off(CALLER_ADDR0);
49 context_tracking_guest_exit();
51 instrumentation_begin();
52 trace_hardirqs_off_finish();
53 instrumentation_end();
56 #define KVM_NESTED_VMENTER_CONSISTENCY_CHECK(consistency_check) \
58 bool failed = (consistency_check); \
60 trace_kvm_nested_vmenter_failed(#consistency_check, 0); \
64 #define KVM_DEFAULT_PLE_GAP 128
65 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
66 #define KVM_DEFAULT_PLE_WINDOW_GROW 2
67 #define KVM_DEFAULT_PLE_WINDOW_SHRINK 0
68 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX
69 #define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX
70 #define KVM_SVM_DEFAULT_PLE_WINDOW 3000
72 static inline unsigned int __grow_ple_window(unsigned int val,
73 unsigned int base, unsigned int modifier, unsigned int max)
85 return min(ret, (u64)max);
88 static inline unsigned int __shrink_ple_window(unsigned int val,
89 unsigned int base, unsigned int modifier, unsigned int min)
102 #define MSR_IA32_CR_PAT_DEFAULT 0x0007040600070406ULL
104 int kvm_check_nested_events(struct kvm_vcpu *vcpu);
106 static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu)
108 vcpu->arch.exception.pending = false;
109 vcpu->arch.exception.injected = false;
112 static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector,
115 vcpu->arch.interrupt.injected = true;
116 vcpu->arch.interrupt.soft = soft;
117 vcpu->arch.interrupt.nr = vector;
120 static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu)
122 vcpu->arch.interrupt.injected = false;
125 static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu)
127 return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected ||
128 vcpu->arch.nmi_injected;
131 static inline bool kvm_exception_is_soft(unsigned int nr)
133 return (nr == BP_VECTOR) || (nr == OF_VECTOR);
136 static inline bool is_protmode(struct kvm_vcpu *vcpu)
138 return kvm_read_cr0_bits(vcpu, X86_CR0_PE);
141 static inline int is_long_mode(struct kvm_vcpu *vcpu)
144 return vcpu->arch.efer & EFER_LMA;
150 static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu)
154 if (!is_long_mode(vcpu))
156 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
160 static inline bool is_la57_mode(struct kvm_vcpu *vcpu)
163 return (vcpu->arch.efer & EFER_LMA) &&
164 kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
170 static inline bool x86_exception_has_error_code(unsigned int vector)
172 static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) |
173 BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) |
174 BIT(PF_VECTOR) | BIT(AC_VECTOR);
176 return (1U << vector) & exception_has_error_code;
179 static inline bool mmu_is_nested(struct kvm_vcpu *vcpu)
181 return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;
184 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
186 ++vcpu->stat.tlb_flush;
187 static_call(kvm_x86_tlb_flush_current)(vcpu);
190 static inline int is_pae(struct kvm_vcpu *vcpu)
192 return kvm_read_cr4_bits(vcpu, X86_CR4_PAE);
195 static inline int is_pse(struct kvm_vcpu *vcpu)
197 return kvm_read_cr4_bits(vcpu, X86_CR4_PSE);
200 static inline int is_paging(struct kvm_vcpu *vcpu)
202 return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG));
205 static inline bool is_pae_paging(struct kvm_vcpu *vcpu)
207 return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu);
210 static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
212 return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48;
215 static inline u64 get_canonical(u64 la, u8 vaddr_bits)
217 return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits);
220 static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu)
222 return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la;
225 static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
226 gva_t gva, gfn_t gfn, unsigned access)
228 u64 gen = kvm_memslots(vcpu->kvm)->generation;
230 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
234 * If this is a shadow nested page table, the "GVA" is
237 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK;
238 vcpu->arch.mmio_access = access;
239 vcpu->arch.mmio_gfn = gfn;
240 vcpu->arch.mmio_gen = gen;
243 static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu)
245 return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation;
249 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we
250 * clear all mmio cache info.
252 #define MMIO_GVA_ANY (~(gva_t)0)
254 static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
256 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
259 vcpu->arch.mmio_gva = 0;
262 static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
264 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva &&
265 vcpu->arch.mmio_gva == (gva & PAGE_MASK))
271 static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
273 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn &&
274 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
280 static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu, int reg)
282 unsigned long val = kvm_register_read_raw(vcpu, reg);
284 return is_64_bit_mode(vcpu) ? val : (u32)val;
287 static inline void kvm_register_write(struct kvm_vcpu *vcpu,
288 int reg, unsigned long val)
290 if (!is_64_bit_mode(vcpu))
292 return kvm_register_write_raw(vcpu, reg, val);
295 static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
297 return !(kvm->arch.disabled_quirks & quirk);
300 static inline bool kvm_vcpu_latch_init(struct kvm_vcpu *vcpu)
302 return is_smm(vcpu) || static_call(kvm_x86_apic_init_signal_blocked)(vcpu);
305 void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs);
306 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
308 u64 get_kvmclock_ns(struct kvm *kvm);
310 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
311 gva_t addr, void *val, unsigned int bytes,
312 struct x86_exception *exception);
314 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu,
315 gva_t addr, void *val, unsigned int bytes,
316 struct x86_exception *exception);
318 int handle_ud(struct kvm_vcpu *vcpu);
320 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu);
322 void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu);
323 u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
324 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data);
325 int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
326 int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
327 bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn,
329 bool kvm_vector_hashing_enabled(void);
330 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code);
331 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
332 void *insn, int insn_len);
333 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
334 int emulation_type, void *insn, int insn_len);
335 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu);
337 extern u64 host_xcr0;
338 extern u64 supported_xcr0;
340 extern u64 supported_xss;
342 static inline bool kvm_mpx_supported(void)
344 return (supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR))
345 == (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
348 extern unsigned int min_timer_period_us;
350 extern bool enable_vmware_backdoor;
352 extern int pi_inject_timer;
354 extern struct static_key kvm_no_apic_vcpu;
356 extern bool report_ignored_msrs;
358 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
360 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
361 vcpu->arch.virtual_tsc_shift);
364 /* Same "calling convention" as do_div:
365 * - divide (n << 32) by base
369 #define do_shl32_div32(n, base) \
372 asm("divl %2" : "=a" (__quot), "=d" (__rem) \
373 : "rm" (base), "0" (0), "1" ((u32) n)); \
378 static inline bool kvm_mwait_in_guest(struct kvm *kvm)
380 return kvm->arch.mwait_in_guest;
383 static inline bool kvm_hlt_in_guest(struct kvm *kvm)
385 return kvm->arch.hlt_in_guest;
388 static inline bool kvm_pause_in_guest(struct kvm *kvm)
390 return kvm->arch.pause_in_guest;
393 static inline bool kvm_cstate_in_guest(struct kvm *kvm)
395 return kvm->arch.cstate_in_guest;
398 DECLARE_PER_CPU(struct kvm_vcpu *, current_vcpu);
400 static inline void kvm_before_interrupt(struct kvm_vcpu *vcpu)
402 __this_cpu_write(current_vcpu, vcpu);
405 static inline void kvm_after_interrupt(struct kvm_vcpu *vcpu)
407 __this_cpu_write(current_vcpu, NULL);
411 static inline bool kvm_pat_valid(u64 data)
413 if (data & 0xF8F8F8F8F8F8F8F8ull)
415 /* 0, 1, 4, 5, 6, 7 are valid values. */
416 return (data | ((data & 0x0202020202020202ull) << 1)) == data;
419 static inline bool kvm_dr7_valid(u64 data)
421 /* Bits [63:32] are reserved */
422 return !(data >> 32);
424 static inline bool kvm_dr6_valid(u64 data)
426 /* Bits [63:32] are reserved */
427 return !(data >> 32);
431 * Trigger machine check on the host. We assume all the MSRs are already set up
432 * by the CPU and that we still run on the same CPU as the MCE occurred on.
433 * We pass a fake environment to the machine check handler because we want
434 * the guest to be always treated like user space, no matter what context
435 * it used internally.
437 static inline void kvm_machine_check(void)
439 #if defined(CONFIG_X86_MCE)
440 struct pt_regs regs = {
441 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
442 .flags = X86_EFLAGS_IF,
445 do_machine_check(®s);
449 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu);
450 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu);
451 int kvm_spec_ctrl_test_value(u64 value);
452 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
453 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
454 struct x86_exception *e);
455 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva);
456 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type);
459 * Internal error codes that are used to indicate that MSR emulation encountered
460 * an error that should result in #GP in the guest, unless userspace
463 #define KVM_MSR_RET_INVALID 2 /* in-kernel MSR emulation #GP condition */
464 #define KVM_MSR_RET_FILTERED 3 /* #GP due to userspace MSR filter */
466 #define __cr4_reserved_bits(__cpu_has, __c) \
468 u64 __reserved_bits = CR4_RESERVED_BITS; \
470 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
471 __reserved_bits |= X86_CR4_OSXSAVE; \
472 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \
473 __reserved_bits |= X86_CR4_SMEP; \
474 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \
475 __reserved_bits |= X86_CR4_SMAP; \
476 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \
477 __reserved_bits |= X86_CR4_FSGSBASE; \
478 if (!__cpu_has(__c, X86_FEATURE_PKU)) \
479 __reserved_bits |= X86_CR4_PKE; \
480 if (!__cpu_has(__c, X86_FEATURE_LA57)) \
481 __reserved_bits |= X86_CR4_LA57; \
482 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \
483 __reserved_bits |= X86_CR4_UMIP; \
484 if (!__cpu_has(__c, X86_FEATURE_VMX)) \
485 __reserved_bits |= X86_CR4_VMXE; \
486 if (!__cpu_has(__c, X86_FEATURE_PCID)) \
487 __reserved_bits |= X86_CR4_PCIDE; \
491 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
493 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
495 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
496 unsigned int port, void *data, unsigned int count,