1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/sched/isolation.h>
58 #include <linux/mem_encrypt.h>
59 #include <linux/entry-kvm.h>
61 #include <trace/events/kvm.h>
63 #include <asm/debugreg.h>
67 #include <linux/kernel_stat.h>
68 #include <asm/fpu/internal.h> /* Ugh! */
69 #include <asm/pvclock.h>
70 #include <asm/div64.h>
71 #include <asm/irq_remapping.h>
72 #include <asm/mshyperv.h>
73 #include <asm/hypervisor.h>
74 #include <asm/intel_pt.h>
75 #include <asm/emulate_prefix.h>
76 #include <clocksource/hyperv_timer.h>
78 #define CREATE_TRACE_POINTS
81 #define MAX_IO_MSRS 256
82 #define KVM_MAX_MCE_BANKS 32
83 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
84 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
86 #define emul_to_vcpu(ctxt) \
87 ((struct kvm_vcpu *)(ctxt)->vcpu)
90 * - enable syscall per default because its emulated by KVM
91 * - enable LME and LMA per default on 64 bit KVM
95 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
97 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
100 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
102 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
103 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
105 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
106 static void process_nmi(struct kvm_vcpu *vcpu);
107 static void enter_smm(struct kvm_vcpu *vcpu);
108 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
109 static void store_regs(struct kvm_vcpu *vcpu);
110 static int sync_regs(struct kvm_vcpu *vcpu);
112 struct kvm_x86_ops kvm_x86_ops __read_mostly;
113 EXPORT_SYMBOL_GPL(kvm_x86_ops);
115 static bool __read_mostly ignore_msrs = 0;
116 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
118 static bool __read_mostly report_ignored_msrs = true;
119 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
121 unsigned int min_timer_period_us = 200;
122 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
124 static bool __read_mostly kvmclock_periodic_sync = true;
125 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
127 bool __read_mostly kvm_has_tsc_control;
128 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
129 u32 __read_mostly kvm_max_guest_tsc_khz;
130 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
131 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
132 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
133 u64 __read_mostly kvm_max_tsc_scaling_ratio;
134 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
135 u64 __read_mostly kvm_default_tsc_scaling_ratio;
136 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
138 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
139 static u32 __read_mostly tsc_tolerance_ppm = 250;
140 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
143 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
144 * adaptive tuning starting from default advancment of 1000ns. '0' disables
145 * advancement entirely. Any other value is used as-is and disables adaptive
146 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
148 static int __read_mostly lapic_timer_advance_ns = -1;
149 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
151 static bool __read_mostly vector_hashing = true;
152 module_param(vector_hashing, bool, S_IRUGO);
154 bool __read_mostly enable_vmware_backdoor = false;
155 module_param(enable_vmware_backdoor, bool, S_IRUGO);
156 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
158 static bool __read_mostly force_emulation_prefix = false;
159 module_param(force_emulation_prefix, bool, S_IRUGO);
161 int __read_mostly pi_inject_timer = -1;
162 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
164 #define KVM_NR_SHARED_MSRS 16
166 struct kvm_shared_msrs_global {
168 u32 msrs[KVM_NR_SHARED_MSRS];
171 struct kvm_shared_msrs {
172 struct user_return_notifier urn;
174 struct kvm_shared_msr_values {
177 } values[KVM_NR_SHARED_MSRS];
180 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
181 static struct kvm_shared_msrs __percpu *shared_msrs;
183 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
184 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
185 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
186 | XFEATURE_MASK_PKRU)
188 u64 __read_mostly host_efer;
189 EXPORT_SYMBOL_GPL(host_efer);
191 bool __read_mostly allow_smaller_maxphyaddr;
192 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
194 static u64 __read_mostly host_xss;
195 u64 __read_mostly supported_xss;
196 EXPORT_SYMBOL_GPL(supported_xss);
198 struct kvm_stats_debugfs_item debugfs_entries[] = {
199 VCPU_STAT("pf_fixed", pf_fixed),
200 VCPU_STAT("pf_guest", pf_guest),
201 VCPU_STAT("tlb_flush", tlb_flush),
202 VCPU_STAT("invlpg", invlpg),
203 VCPU_STAT("exits", exits),
204 VCPU_STAT("io_exits", io_exits),
205 VCPU_STAT("mmio_exits", mmio_exits),
206 VCPU_STAT("signal_exits", signal_exits),
207 VCPU_STAT("irq_window", irq_window_exits),
208 VCPU_STAT("nmi_window", nmi_window_exits),
209 VCPU_STAT("halt_exits", halt_exits),
210 VCPU_STAT("halt_successful_poll", halt_successful_poll),
211 VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
212 VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
213 VCPU_STAT("halt_wakeup", halt_wakeup),
214 VCPU_STAT("hypercalls", hypercalls),
215 VCPU_STAT("request_irq", request_irq_exits),
216 VCPU_STAT("irq_exits", irq_exits),
217 VCPU_STAT("host_state_reload", host_state_reload),
218 VCPU_STAT("fpu_reload", fpu_reload),
219 VCPU_STAT("insn_emulation", insn_emulation),
220 VCPU_STAT("insn_emulation_fail", insn_emulation_fail),
221 VCPU_STAT("irq_injections", irq_injections),
222 VCPU_STAT("nmi_injections", nmi_injections),
223 VCPU_STAT("req_event", req_event),
224 VCPU_STAT("l1d_flush", l1d_flush),
225 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
226 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
227 VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped),
228 VM_STAT("mmu_pte_write", mmu_pte_write),
229 VM_STAT("mmu_pte_updated", mmu_pte_updated),
230 VM_STAT("mmu_pde_zapped", mmu_pde_zapped),
231 VM_STAT("mmu_flooded", mmu_flooded),
232 VM_STAT("mmu_recycled", mmu_recycled),
233 VM_STAT("mmu_cache_miss", mmu_cache_miss),
234 VM_STAT("mmu_unsync", mmu_unsync),
235 VM_STAT("remote_tlb_flush", remote_tlb_flush),
236 VM_STAT("largepages", lpages, .mode = 0444),
237 VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444),
238 VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions),
242 u64 __read_mostly host_xcr0;
243 u64 __read_mostly supported_xcr0;
244 EXPORT_SYMBOL_GPL(supported_xcr0);
246 static struct kmem_cache *x86_fpu_cache;
248 static struct kmem_cache *x86_emulator_cache;
251 * When called, it means the previous get/set msr reached an invalid msr.
252 * Return 0 if we want to ignore/silent this failed msr access, or 1 if we want
253 * to fail the caller.
255 static int kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr,
256 u64 data, bool write)
258 const char *op = write ? "wrmsr" : "rdmsr";
261 if (report_ignored_msrs)
262 vcpu_unimpl(vcpu, "ignored %s: 0x%x data 0x%llx\n",
267 vcpu_debug_ratelimited(vcpu, "unhandled %s: 0x%x data 0x%llx\n",
273 static struct kmem_cache *kvm_alloc_emulator_cache(void)
275 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
276 unsigned int size = sizeof(struct x86_emulate_ctxt);
278 return kmem_cache_create_usercopy("x86_emulator", size,
279 __alignof__(struct x86_emulate_ctxt),
280 SLAB_ACCOUNT, useroffset,
281 size - useroffset, NULL);
284 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
286 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
289 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
290 vcpu->arch.apf.gfns[i] = ~0;
293 static void kvm_on_user_return(struct user_return_notifier *urn)
296 struct kvm_shared_msrs *locals
297 = container_of(urn, struct kvm_shared_msrs, urn);
298 struct kvm_shared_msr_values *values;
302 * Disabling irqs at this point since the following code could be
303 * interrupted and executed through kvm_arch_hardware_disable()
305 local_irq_save(flags);
306 if (locals->registered) {
307 locals->registered = false;
308 user_return_notifier_unregister(urn);
310 local_irq_restore(flags);
311 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
312 values = &locals->values[slot];
313 if (values->host != values->curr) {
314 wrmsrl(shared_msrs_global.msrs[slot], values->host);
315 values->curr = values->host;
320 void kvm_define_shared_msr(unsigned slot, u32 msr)
322 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
323 shared_msrs_global.msrs[slot] = msr;
324 if (slot >= shared_msrs_global.nr)
325 shared_msrs_global.nr = slot + 1;
327 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
329 static void kvm_shared_msr_cpu_online(void)
331 unsigned int cpu = smp_processor_id();
332 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
336 for (i = 0; i < shared_msrs_global.nr; ++i) {
337 rdmsrl_safe(shared_msrs_global.msrs[i], &value);
338 smsr->values[i].host = value;
339 smsr->values[i].curr = value;
343 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
345 unsigned int cpu = smp_processor_id();
346 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
349 value = (value & mask) | (smsr->values[slot].host & ~mask);
350 if (value == smsr->values[slot].curr)
352 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
356 smsr->values[slot].curr = value;
357 if (!smsr->registered) {
358 smsr->urn.on_user_return = kvm_on_user_return;
359 user_return_notifier_register(&smsr->urn);
360 smsr->registered = true;
364 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
366 static void drop_user_return_notifiers(void)
368 unsigned int cpu = smp_processor_id();
369 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
371 if (smsr->registered)
372 kvm_on_user_return(&smsr->urn);
375 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
377 return vcpu->arch.apic_base;
379 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
381 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
383 return kvm_apic_mode(kvm_get_apic_base(vcpu));
385 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
387 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
389 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
390 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
391 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
392 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
394 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
396 if (!msr_info->host_initiated) {
397 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
399 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
403 kvm_lapic_set_base(vcpu, msr_info->data);
404 kvm_recalculate_apic_map(vcpu->kvm);
407 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
409 asmlinkage __visible noinstr void kvm_spurious_fault(void)
411 /* Fault while not rebooting. We want the trace. */
412 BUG_ON(!kvm_rebooting);
414 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
416 #define EXCPT_BENIGN 0
417 #define EXCPT_CONTRIBUTORY 1
420 static int exception_class(int vector)
430 return EXCPT_CONTRIBUTORY;
437 #define EXCPT_FAULT 0
439 #define EXCPT_ABORT 2
440 #define EXCPT_INTERRUPT 3
442 static int exception_type(int vector)
446 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
447 return EXCPT_INTERRUPT;
451 /* #DB is trap, as instruction watchpoints are handled elsewhere */
452 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
455 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
458 /* Reserved exceptions will result in fault */
462 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
464 unsigned nr = vcpu->arch.exception.nr;
465 bool has_payload = vcpu->arch.exception.has_payload;
466 unsigned long payload = vcpu->arch.exception.payload;
474 * "Certain debug exceptions may clear bit 0-3. The
475 * remaining contents of the DR6 register are never
476 * cleared by the processor".
478 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
480 * DR6.RTM is set by all #DB exceptions that don't clear it.
482 vcpu->arch.dr6 |= DR6_RTM;
483 vcpu->arch.dr6 |= payload;
485 * Bit 16 should be set in the payload whenever the #DB
486 * exception should clear DR6.RTM. This makes the payload
487 * compatible with the pending debug exceptions under VMX.
488 * Though not currently documented in the SDM, this also
489 * makes the payload compatible with the exit qualification
490 * for #DB exceptions under VMX.
492 vcpu->arch.dr6 ^= payload & DR6_RTM;
495 * The #DB payload is defined as compatible with the 'pending
496 * debug exceptions' field under VMX, not DR6. While bit 12 is
497 * defined in the 'pending debug exceptions' field (enabled
498 * breakpoint), it is reserved and must be zero in DR6.
500 vcpu->arch.dr6 &= ~BIT(12);
503 vcpu->arch.cr2 = payload;
507 vcpu->arch.exception.has_payload = false;
508 vcpu->arch.exception.payload = 0;
510 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
512 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
513 unsigned nr, bool has_error, u32 error_code,
514 bool has_payload, unsigned long payload, bool reinject)
519 kvm_make_request(KVM_REQ_EVENT, vcpu);
521 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
523 if (has_error && !is_protmode(vcpu))
527 * On vmentry, vcpu->arch.exception.pending is only
528 * true if an event injection was blocked by
529 * nested_run_pending. In that case, however,
530 * vcpu_enter_guest requests an immediate exit,
531 * and the guest shouldn't proceed far enough to
534 WARN_ON_ONCE(vcpu->arch.exception.pending);
535 vcpu->arch.exception.injected = true;
536 if (WARN_ON_ONCE(has_payload)) {
538 * A reinjected event has already
539 * delivered its payload.
545 vcpu->arch.exception.pending = true;
546 vcpu->arch.exception.injected = false;
548 vcpu->arch.exception.has_error_code = has_error;
549 vcpu->arch.exception.nr = nr;
550 vcpu->arch.exception.error_code = error_code;
551 vcpu->arch.exception.has_payload = has_payload;
552 vcpu->arch.exception.payload = payload;
553 if (!is_guest_mode(vcpu))
554 kvm_deliver_exception_payload(vcpu);
558 /* to check exception */
559 prev_nr = vcpu->arch.exception.nr;
560 if (prev_nr == DF_VECTOR) {
561 /* triple fault -> shutdown */
562 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
565 class1 = exception_class(prev_nr);
566 class2 = exception_class(nr);
567 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
568 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
570 * Generate double fault per SDM Table 5-5. Set
571 * exception.pending = true so that the double fault
572 * can trigger a nested vmexit.
574 vcpu->arch.exception.pending = true;
575 vcpu->arch.exception.injected = false;
576 vcpu->arch.exception.has_error_code = true;
577 vcpu->arch.exception.nr = DF_VECTOR;
578 vcpu->arch.exception.error_code = 0;
579 vcpu->arch.exception.has_payload = false;
580 vcpu->arch.exception.payload = 0;
582 /* replace previous exception with a new one in a hope
583 that instruction re-execution will regenerate lost
588 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
590 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
592 EXPORT_SYMBOL_GPL(kvm_queue_exception);
594 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
596 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
598 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
600 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
601 unsigned long payload)
603 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
605 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
607 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
608 u32 error_code, unsigned long payload)
610 kvm_multiple_exception(vcpu, nr, true, error_code,
611 true, payload, false);
614 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
617 kvm_inject_gp(vcpu, 0);
619 return kvm_skip_emulated_instruction(vcpu);
623 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
625 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
627 ++vcpu->stat.pf_guest;
628 vcpu->arch.exception.nested_apf =
629 is_guest_mode(vcpu) && fault->async_page_fault;
630 if (vcpu->arch.exception.nested_apf) {
631 vcpu->arch.apf.nested_apf_token = fault->address;
632 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
634 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
638 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
640 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
641 struct x86_exception *fault)
643 struct kvm_mmu *fault_mmu;
644 WARN_ON_ONCE(fault->vector != PF_VECTOR);
646 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
650 * Invalidate the TLB entry for the faulting address, if it exists,
651 * else the access will fault indefinitely (and to emulate hardware).
653 if ((fault->error_code & PFERR_PRESENT_MASK) &&
654 !(fault->error_code & PFERR_RSVD_MASK))
655 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
656 fault_mmu->root_hpa);
658 fault_mmu->inject_page_fault(vcpu, fault);
659 return fault->nested_page_fault;
661 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
663 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
665 atomic_inc(&vcpu->arch.nmi_queued);
666 kvm_make_request(KVM_REQ_NMI, vcpu);
668 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
670 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
672 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
674 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
676 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
678 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
680 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
683 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
684 * a #GP and return false.
686 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
688 if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl)
690 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
693 EXPORT_SYMBOL_GPL(kvm_require_cpl);
695 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
697 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
700 kvm_queue_exception(vcpu, UD_VECTOR);
703 EXPORT_SYMBOL_GPL(kvm_require_dr);
706 * This function will be used to read from the physical memory of the currently
707 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
708 * can read from guest physical or from the guest's guest physical memory.
710 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
711 gfn_t ngfn, void *data, int offset, int len,
714 struct x86_exception exception;
718 ngpa = gfn_to_gpa(ngfn);
719 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
720 if (real_gfn == UNMAPPED_GVA)
723 real_gfn = gpa_to_gfn(real_gfn);
725 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
727 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
729 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
730 void *data, int offset, int len, u32 access)
732 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
733 data, offset, len, access);
736 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
738 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
743 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
745 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
747 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
748 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
751 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
753 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
754 offset * sizeof(u64), sizeof(pdpte),
755 PFERR_USER_MASK|PFERR_WRITE_MASK);
760 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
761 if ((pdpte[i] & PT_PRESENT_MASK) &&
762 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
769 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
770 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
776 EXPORT_SYMBOL_GPL(load_pdptrs);
778 bool pdptrs_changed(struct kvm_vcpu *vcpu)
780 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
785 if (!is_pae_paging(vcpu))
788 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
791 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
792 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
793 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
794 PFERR_USER_MASK | PFERR_WRITE_MASK);
798 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
800 EXPORT_SYMBOL_GPL(pdptrs_changed);
802 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
804 unsigned long old_cr0 = kvm_read_cr0(vcpu);
805 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG;
806 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
811 if (cr0 & 0xffffffff00000000UL)
815 cr0 &= ~CR0_RESERVED_BITS;
817 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
820 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
824 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
825 (cr0 & X86_CR0_PG)) {
830 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
835 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
836 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) &&
837 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)))
840 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
843 kvm_x86_ops.set_cr0(vcpu, cr0);
845 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
846 kvm_clear_async_pf_completion_queue(vcpu);
847 kvm_async_pf_hash_reset(vcpu);
850 if ((cr0 ^ old_cr0) & update_bits)
851 kvm_mmu_reset_context(vcpu);
853 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
854 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
855 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
856 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
860 EXPORT_SYMBOL_GPL(kvm_set_cr0);
862 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
864 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
866 EXPORT_SYMBOL_GPL(kvm_lmsw);
868 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
870 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
872 if (vcpu->arch.xcr0 != host_xcr0)
873 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
875 if (vcpu->arch.xsaves_enabled &&
876 vcpu->arch.ia32_xss != host_xss)
877 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
880 if (static_cpu_has(X86_FEATURE_PKU) &&
881 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
882 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
883 vcpu->arch.pkru != vcpu->arch.host_pkru)
884 __write_pkru(vcpu->arch.pkru);
886 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
888 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
890 if (static_cpu_has(X86_FEATURE_PKU) &&
891 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
892 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
893 vcpu->arch.pkru = rdpkru();
894 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
895 __write_pkru(vcpu->arch.host_pkru);
898 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
900 if (vcpu->arch.xcr0 != host_xcr0)
901 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
903 if (vcpu->arch.xsaves_enabled &&
904 vcpu->arch.ia32_xss != host_xss)
905 wrmsrl(MSR_IA32_XSS, host_xss);
909 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
911 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
914 u64 old_xcr0 = vcpu->arch.xcr0;
917 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
918 if (index != XCR_XFEATURE_ENABLED_MASK)
920 if (!(xcr0 & XFEATURE_MASK_FP))
922 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
926 * Do not allow the guest to set bits that we do not support
927 * saving. However, xcr0 bit 0 is always set, even if the
928 * emulated CPU does not support XSAVE (see fx_init).
930 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
931 if (xcr0 & ~valid_bits)
934 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
935 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
938 if (xcr0 & XFEATURE_MASK_AVX512) {
939 if (!(xcr0 & XFEATURE_MASK_YMM))
941 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
944 vcpu->arch.xcr0 = xcr0;
946 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
947 kvm_update_cpuid_runtime(vcpu);
951 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
953 if (kvm_x86_ops.get_cpl(vcpu) != 0 ||
954 __kvm_set_xcr(vcpu, index, xcr)) {
955 kvm_inject_gp(vcpu, 0);
960 EXPORT_SYMBOL_GPL(kvm_set_xcr);
962 int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
964 if (cr4 & cr4_reserved_bits)
967 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
972 EXPORT_SYMBOL_GPL(kvm_valid_cr4);
974 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
976 unsigned long old_cr4 = kvm_read_cr4(vcpu);
977 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
980 if (kvm_valid_cr4(vcpu, cr4))
983 if (is_long_mode(vcpu)) {
984 if (!(cr4 & X86_CR4_PAE))
986 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
988 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
989 && ((cr4 ^ old_cr4) & pdptr_bits)
990 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
994 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
995 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
998 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
999 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1003 if (kvm_x86_ops.set_cr4(vcpu, cr4))
1006 if (((cr4 ^ old_cr4) & pdptr_bits) ||
1007 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1008 kvm_mmu_reset_context(vcpu);
1010 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1011 kvm_update_cpuid_runtime(vcpu);
1015 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1017 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1019 bool skip_tlb_flush = false;
1020 #ifdef CONFIG_X86_64
1021 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1024 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1025 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1029 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1030 if (!skip_tlb_flush) {
1031 kvm_mmu_sync_roots(vcpu);
1032 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1037 if (is_long_mode(vcpu) &&
1038 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
1040 else if (is_pae_paging(vcpu) &&
1041 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1044 kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush);
1045 vcpu->arch.cr3 = cr3;
1046 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1050 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1052 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1054 if (cr8 & CR8_RESERVED_BITS)
1056 if (lapic_in_kernel(vcpu))
1057 kvm_lapic_set_tpr(vcpu, cr8);
1059 vcpu->arch.cr8 = cr8;
1062 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1064 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1066 if (lapic_in_kernel(vcpu))
1067 return kvm_lapic_get_cr8(vcpu);
1069 return vcpu->arch.cr8;
1071 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1073 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1077 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1078 for (i = 0; i < KVM_NR_DB_REGS; i++)
1079 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1080 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1084 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1088 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1089 dr7 = vcpu->arch.guest_debug_dr7;
1091 dr7 = vcpu->arch.dr7;
1092 kvm_x86_ops.set_dr7(vcpu, dr7);
1093 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1094 if (dr7 & DR7_BP_EN_MASK)
1095 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1097 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1099 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1101 u64 fixed = DR6_FIXED_1;
1103 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1108 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1110 size_t size = ARRAY_SIZE(vcpu->arch.db);
1114 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1115 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1116 vcpu->arch.eff_db[dr] = val;
1120 if (!kvm_dr6_valid(val))
1121 return -1; /* #GP */
1122 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1126 if (!kvm_dr7_valid(val))
1127 return -1; /* #GP */
1128 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1129 kvm_update_dr7(vcpu);
1136 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1138 if (__kvm_set_dr(vcpu, dr, val)) {
1139 kvm_inject_gp(vcpu, 0);
1144 EXPORT_SYMBOL_GPL(kvm_set_dr);
1146 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1148 size_t size = ARRAY_SIZE(vcpu->arch.db);
1152 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1156 *val = vcpu->arch.dr6;
1160 *val = vcpu->arch.dr7;
1165 EXPORT_SYMBOL_GPL(kvm_get_dr);
1167 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1169 u32 ecx = kvm_rcx_read(vcpu);
1173 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1176 kvm_rax_write(vcpu, (u32)data);
1177 kvm_rdx_write(vcpu, data >> 32);
1180 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1183 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1184 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1186 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1187 * extract the supported MSRs from the related const lists.
1188 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1189 * capabilities of the host cpu. This capabilities test skips MSRs that are
1190 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1191 * may depend on host virtualization features rather than host cpu features.
1194 static const u32 msrs_to_save_all[] = {
1195 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1197 #ifdef CONFIG_X86_64
1198 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1200 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1201 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1203 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1204 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1205 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1206 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1207 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1208 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1209 MSR_IA32_UMWAIT_CONTROL,
1211 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1212 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1213 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1214 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1215 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1216 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1217 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1218 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1219 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1220 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1221 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1222 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1223 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1224 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1225 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1226 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1227 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1228 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1229 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1230 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1231 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1232 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1235 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1236 static unsigned num_msrs_to_save;
1238 static const u32 emulated_msrs_all[] = {
1239 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1240 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1241 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1242 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1243 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1244 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1245 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1247 HV_X64_MSR_VP_INDEX,
1248 HV_X64_MSR_VP_RUNTIME,
1249 HV_X64_MSR_SCONTROL,
1250 HV_X64_MSR_STIMER0_CONFIG,
1251 HV_X64_MSR_VP_ASSIST_PAGE,
1252 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1253 HV_X64_MSR_TSC_EMULATION_STATUS,
1254 HV_X64_MSR_SYNDBG_OPTIONS,
1255 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1256 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1257 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1259 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1260 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1262 MSR_IA32_TSC_ADJUST,
1263 MSR_IA32_TSCDEADLINE,
1264 MSR_IA32_ARCH_CAPABILITIES,
1265 MSR_IA32_PERF_CAPABILITIES,
1266 MSR_IA32_MISC_ENABLE,
1267 MSR_IA32_MCG_STATUS,
1269 MSR_IA32_MCG_EXT_CTL,
1273 MSR_MISC_FEATURES_ENABLES,
1274 MSR_AMD64_VIRT_SPEC_CTRL,
1279 * The following list leaves out MSRs whose values are determined
1280 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1281 * We always support the "true" VMX control MSRs, even if the host
1282 * processor does not, so I am putting these registers here rather
1283 * than in msrs_to_save_all.
1286 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1287 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1288 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1289 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1291 MSR_IA32_VMX_CR0_FIXED0,
1292 MSR_IA32_VMX_CR4_FIXED0,
1293 MSR_IA32_VMX_VMCS_ENUM,
1294 MSR_IA32_VMX_PROCBASED_CTLS2,
1295 MSR_IA32_VMX_EPT_VPID_CAP,
1296 MSR_IA32_VMX_VMFUNC,
1299 MSR_KVM_POLL_CONTROL,
1302 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1303 static unsigned num_emulated_msrs;
1306 * List of msr numbers which are used to expose MSR-based features that
1307 * can be used by a hypervisor to validate requested CPU features.
1309 static const u32 msr_based_features_all[] = {
1311 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1312 MSR_IA32_VMX_PINBASED_CTLS,
1313 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1314 MSR_IA32_VMX_PROCBASED_CTLS,
1315 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1316 MSR_IA32_VMX_EXIT_CTLS,
1317 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1318 MSR_IA32_VMX_ENTRY_CTLS,
1320 MSR_IA32_VMX_CR0_FIXED0,
1321 MSR_IA32_VMX_CR0_FIXED1,
1322 MSR_IA32_VMX_CR4_FIXED0,
1323 MSR_IA32_VMX_CR4_FIXED1,
1324 MSR_IA32_VMX_VMCS_ENUM,
1325 MSR_IA32_VMX_PROCBASED_CTLS2,
1326 MSR_IA32_VMX_EPT_VPID_CAP,
1327 MSR_IA32_VMX_VMFUNC,
1331 MSR_IA32_ARCH_CAPABILITIES,
1332 MSR_IA32_PERF_CAPABILITIES,
1335 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1336 static unsigned int num_msr_based_features;
1338 static u64 kvm_get_arch_capabilities(void)
1342 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1343 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1346 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1347 * the nested hypervisor runs with NX huge pages. If it is not,
1348 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1349 * L1 guests, so it need not worry about its own (L2) guests.
1351 data |= ARCH_CAP_PSCHANGE_MC_NO;
1354 * If we're doing cache flushes (either "always" or "cond")
1355 * we will do one whenever the guest does a vmlaunch/vmresume.
1356 * If an outer hypervisor is doing the cache flush for us
1357 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1358 * capability to the guest too, and if EPT is disabled we're not
1359 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1360 * require a nested hypervisor to do a flush of its own.
1362 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1363 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1365 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1366 data |= ARCH_CAP_RDCL_NO;
1367 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1368 data |= ARCH_CAP_SSB_NO;
1369 if (!boot_cpu_has_bug(X86_BUG_MDS))
1370 data |= ARCH_CAP_MDS_NO;
1373 * On TAA affected systems:
1374 * - nothing to do if TSX is disabled on the host.
1375 * - we emulate TSX_CTRL if present on the host.
1376 * This lets the guest use VERW to clear CPU buffers.
1378 if (!boot_cpu_has(X86_FEATURE_RTM))
1379 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1380 else if (!boot_cpu_has_bug(X86_BUG_TAA))
1381 data |= ARCH_CAP_TAA_NO;
1386 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1388 switch (msr->index) {
1389 case MSR_IA32_ARCH_CAPABILITIES:
1390 msr->data = kvm_get_arch_capabilities();
1392 case MSR_IA32_UCODE_REV:
1393 rdmsrl_safe(msr->index, &msr->data);
1396 return kvm_x86_ops.get_msr_feature(msr);
1401 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1403 struct kvm_msr_entry msr;
1407 r = kvm_get_msr_feature(&msr);
1409 if (r == KVM_MSR_RET_INVALID) {
1410 /* Unconditionally clear the output for simplicity */
1412 r = kvm_msr_ignored_check(vcpu, index, 0, false);
1423 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1425 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1428 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1431 if (efer & (EFER_LME | EFER_LMA) &&
1432 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1435 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1441 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1443 if (efer & efer_reserved_bits)
1446 return __kvm_valid_efer(vcpu, efer);
1448 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1450 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1452 u64 old_efer = vcpu->arch.efer;
1453 u64 efer = msr_info->data;
1455 if (efer & efer_reserved_bits)
1458 if (!msr_info->host_initiated) {
1459 if (!__kvm_valid_efer(vcpu, efer))
1462 if (is_paging(vcpu) &&
1463 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1468 efer |= vcpu->arch.efer & EFER_LMA;
1470 kvm_x86_ops.set_efer(vcpu, efer);
1472 /* Update reserved bits */
1473 if ((efer ^ old_efer) & EFER_NX)
1474 kvm_mmu_reset_context(vcpu);
1479 void kvm_enable_efer_bits(u64 mask)
1481 efer_reserved_bits &= ~mask;
1483 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1486 * Write @data into the MSR specified by @index. Select MSR specific fault
1487 * checks are bypassed if @host_initiated is %true.
1488 * Returns 0 on success, non-0 otherwise.
1489 * Assumes vcpu_load() was already called.
1491 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1492 bool host_initiated)
1494 struct msr_data msr;
1499 case MSR_KERNEL_GS_BASE:
1502 if (is_noncanonical_address(data, vcpu))
1505 case MSR_IA32_SYSENTER_EIP:
1506 case MSR_IA32_SYSENTER_ESP:
1508 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1509 * non-canonical address is written on Intel but not on
1510 * AMD (which ignores the top 32-bits, because it does
1511 * not implement 64-bit SYSENTER).
1513 * 64-bit code should hence be able to write a non-canonical
1514 * value on AMD. Making the address canonical ensures that
1515 * vmentry does not fail on Intel after writing a non-canonical
1516 * value, and that something deterministic happens if the guest
1517 * invokes 64-bit SYSENTER.
1519 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1524 msr.host_initiated = host_initiated;
1526 return kvm_x86_ops.set_msr(vcpu, &msr);
1529 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1530 u32 index, u64 data, bool host_initiated)
1532 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1534 if (ret == KVM_MSR_RET_INVALID)
1535 ret = kvm_msr_ignored_check(vcpu, index, data, true);
1541 * Read the MSR specified by @index into @data. Select MSR specific fault
1542 * checks are bypassed if @host_initiated is %true.
1543 * Returns 0 on success, non-0 otherwise.
1544 * Assumes vcpu_load() was already called.
1546 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1547 bool host_initiated)
1549 struct msr_data msr;
1553 msr.host_initiated = host_initiated;
1555 ret = kvm_x86_ops.get_msr(vcpu, &msr);
1561 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1562 u32 index, u64 *data, bool host_initiated)
1564 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1566 if (ret == KVM_MSR_RET_INVALID) {
1567 /* Unconditionally clear *data for simplicity */
1569 ret = kvm_msr_ignored_check(vcpu, index, 0, false);
1575 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1577 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1579 EXPORT_SYMBOL_GPL(kvm_get_msr);
1581 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1583 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1585 EXPORT_SYMBOL_GPL(kvm_set_msr);
1587 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1589 u32 ecx = kvm_rcx_read(vcpu);
1592 if (kvm_get_msr(vcpu, ecx, &data)) {
1593 trace_kvm_msr_read_ex(ecx);
1594 kvm_inject_gp(vcpu, 0);
1598 trace_kvm_msr_read(ecx, data);
1600 kvm_rax_write(vcpu, data & -1u);
1601 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1602 return kvm_skip_emulated_instruction(vcpu);
1604 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1606 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1608 u32 ecx = kvm_rcx_read(vcpu);
1609 u64 data = kvm_read_edx_eax(vcpu);
1611 if (kvm_set_msr(vcpu, ecx, data)) {
1612 trace_kvm_msr_write_ex(ecx, data);
1613 kvm_inject_gp(vcpu, 0);
1617 trace_kvm_msr_write(ecx, data);
1618 return kvm_skip_emulated_instruction(vcpu);
1620 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1622 bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
1624 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
1625 xfer_to_guest_mode_work_pending();
1627 EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request);
1630 * The fast path for frequent and performance sensitive wrmsr emulation,
1631 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1632 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1633 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1634 * other cases which must be called after interrupts are enabled on the host.
1636 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1638 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1641 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1642 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1643 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1644 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1647 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1648 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1649 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1650 trace_kvm_apic_write(APIC_ICR, (u32)data);
1657 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
1659 if (!kvm_can_use_hv_timer(vcpu))
1662 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1666 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1668 u32 msr = kvm_rcx_read(vcpu);
1670 fastpath_t ret = EXIT_FASTPATH_NONE;
1673 case APIC_BASE_MSR + (APIC_ICR >> 4):
1674 data = kvm_read_edx_eax(vcpu);
1675 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
1676 kvm_skip_emulated_instruction(vcpu);
1677 ret = EXIT_FASTPATH_EXIT_HANDLED;
1680 case MSR_IA32_TSCDEADLINE:
1681 data = kvm_read_edx_eax(vcpu);
1682 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
1683 kvm_skip_emulated_instruction(vcpu);
1684 ret = EXIT_FASTPATH_REENTER_GUEST;
1691 if (ret != EXIT_FASTPATH_NONE)
1692 trace_kvm_msr_write(msr, data);
1696 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1699 * Adapt set_msr() to msr_io()'s calling convention
1701 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1703 return kvm_get_msr_ignored_check(vcpu, index, data, true);
1706 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1708 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
1711 #ifdef CONFIG_X86_64
1712 struct pvclock_clock {
1722 struct pvclock_gtod_data {
1725 struct pvclock_clock clock; /* extract of a clocksource struct */
1726 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1732 static struct pvclock_gtod_data pvclock_gtod_data;
1734 static void update_pvclock_gtod(struct timekeeper *tk)
1736 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1738 write_seqcount_begin(&vdata->seq);
1740 /* copy pvclock gtod data */
1741 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
1742 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1743 vdata->clock.mask = tk->tkr_mono.mask;
1744 vdata->clock.mult = tk->tkr_mono.mult;
1745 vdata->clock.shift = tk->tkr_mono.shift;
1746 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
1747 vdata->clock.offset = tk->tkr_mono.base;
1749 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
1750 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1751 vdata->raw_clock.mask = tk->tkr_raw.mask;
1752 vdata->raw_clock.mult = tk->tkr_raw.mult;
1753 vdata->raw_clock.shift = tk->tkr_raw.shift;
1754 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
1755 vdata->raw_clock.offset = tk->tkr_raw.base;
1757 vdata->wall_time_sec = tk->xtime_sec;
1759 vdata->offs_boot = tk->offs_boot;
1761 write_seqcount_end(&vdata->seq);
1764 static s64 get_kvmclock_base_ns(void)
1766 /* Count up from boot time, but with the frequency of the raw clock. */
1767 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1770 static s64 get_kvmclock_base_ns(void)
1772 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
1773 return ktime_get_boottime_ns();
1777 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1779 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1780 kvm_vcpu_kick(vcpu);
1783 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1787 struct pvclock_wall_clock wc;
1793 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1798 ++version; /* first time write, random junk */
1802 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1806 * The guest calculates current wall clock time by adding
1807 * system time (updated by kvm_guest_time_update below) to the
1808 * wall clock specified here. We do the reverse here.
1810 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1812 wc.nsec = do_div(wall_nsec, 1000000000);
1813 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1814 wc.version = version;
1816 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1819 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1822 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1824 do_shl32_div32(dividend, divisor);
1828 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1829 s8 *pshift, u32 *pmultiplier)
1837 scaled64 = scaled_hz;
1838 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1843 tps32 = (uint32_t)tps64;
1844 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1845 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1853 *pmultiplier = div_frac(scaled64, tps32);
1856 #ifdef CONFIG_X86_64
1857 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1860 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1861 static unsigned long max_tsc_khz;
1863 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1865 u64 v = (u64)khz * (1000000 + ppm);
1870 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1874 /* Guest TSC same frequency as host TSC? */
1876 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1880 /* TSC scaling supported? */
1881 if (!kvm_has_tsc_control) {
1882 if (user_tsc_khz > tsc_khz) {
1883 vcpu->arch.tsc_catchup = 1;
1884 vcpu->arch.tsc_always_catchup = 1;
1887 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1892 /* TSC scaling required - calculate ratio */
1893 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1894 user_tsc_khz, tsc_khz);
1896 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1897 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1902 vcpu->arch.tsc_scaling_ratio = ratio;
1906 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1908 u32 thresh_lo, thresh_hi;
1909 int use_scaling = 0;
1911 /* tsc_khz can be zero if TSC calibration fails */
1912 if (user_tsc_khz == 0) {
1913 /* set tsc_scaling_ratio to a safe value */
1914 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1918 /* Compute a scale to convert nanoseconds in TSC cycles */
1919 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1920 &vcpu->arch.virtual_tsc_shift,
1921 &vcpu->arch.virtual_tsc_mult);
1922 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1925 * Compute the variation in TSC rate which is acceptable
1926 * within the range of tolerance and decide if the
1927 * rate being applied is within that bounds of the hardware
1928 * rate. If so, no scaling or compensation need be done.
1930 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1931 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1932 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1933 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1936 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1939 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1941 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1942 vcpu->arch.virtual_tsc_mult,
1943 vcpu->arch.virtual_tsc_shift);
1944 tsc += vcpu->arch.this_tsc_write;
1948 static inline int gtod_is_based_on_tsc(int mode)
1950 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
1953 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1955 #ifdef CONFIG_X86_64
1957 struct kvm_arch *ka = &vcpu->kvm->arch;
1958 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1960 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1961 atomic_read(&vcpu->kvm->online_vcpus));
1964 * Once the masterclock is enabled, always perform request in
1965 * order to update it.
1967 * In order to enable masterclock, the host clocksource must be TSC
1968 * and the vcpus need to have matched TSCs. When that happens,
1969 * perform request to enable masterclock.
1971 if (ka->use_master_clock ||
1972 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1973 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1975 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1976 atomic_read(&vcpu->kvm->online_vcpus),
1977 ka->use_master_clock, gtod->clock.vclock_mode);
1981 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1983 u64 curr_offset = vcpu->arch.l1_tsc_offset;
1984 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1988 * Multiply tsc by a fixed point number represented by ratio.
1990 * The most significant 64-N bits (mult) of ratio represent the
1991 * integral part of the fixed point number; the remaining N bits
1992 * (frac) represent the fractional part, ie. ratio represents a fixed
1993 * point number (mult + frac * 2^(-N)).
1995 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1997 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1999 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
2002 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
2005 u64 ratio = vcpu->arch.tsc_scaling_ratio;
2007 if (ratio != kvm_default_tsc_scaling_ratio)
2008 _tsc = __scale_tsc(ratio, tsc);
2012 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2014 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2018 tsc = kvm_scale_tsc(vcpu, rdtsc());
2020 return target_tsc - tsc;
2023 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2025 return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
2027 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2029 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2031 vcpu->arch.l1_tsc_offset = offset;
2032 vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset);
2035 static inline bool kvm_check_tsc_unstable(void)
2037 #ifdef CONFIG_X86_64
2039 * TSC is marked unstable when we're running on Hyper-V,
2040 * 'TSC page' clocksource is good.
2042 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2045 return check_tsc_unstable();
2048 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
2050 struct kvm *kvm = vcpu->kvm;
2051 u64 offset, ns, elapsed;
2052 unsigned long flags;
2054 bool already_matched;
2055 u64 data = msr->data;
2056 bool synchronizing = false;
2058 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2059 offset = kvm_compute_tsc_offset(vcpu, data);
2060 ns = get_kvmclock_base_ns();
2061 elapsed = ns - kvm->arch.last_tsc_nsec;
2063 if (vcpu->arch.virtual_tsc_khz) {
2064 if (data == 0 && msr->host_initiated) {
2066 * detection of vcpu initialization -- need to sync
2067 * with other vCPUs. This particularly helps to keep
2068 * kvm_clock stable after CPU hotplug
2070 synchronizing = true;
2072 u64 tsc_exp = kvm->arch.last_tsc_write +
2073 nsec_to_cycles(vcpu, elapsed);
2074 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2076 * Special case: TSC write with a small delta (1 second)
2077 * of virtual cycle time against real time is
2078 * interpreted as an attempt to synchronize the CPU.
2080 synchronizing = data < tsc_exp + tsc_hz &&
2081 data + tsc_hz > tsc_exp;
2086 * For a reliable TSC, we can match TSC offsets, and for an unstable
2087 * TSC, we add elapsed time in this computation. We could let the
2088 * compensation code attempt to catch up if we fall behind, but
2089 * it's better to try to match offsets from the beginning.
2091 if (synchronizing &&
2092 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2093 if (!kvm_check_tsc_unstable()) {
2094 offset = kvm->arch.cur_tsc_offset;
2096 u64 delta = nsec_to_cycles(vcpu, elapsed);
2098 offset = kvm_compute_tsc_offset(vcpu, data);
2101 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2104 * We split periods of matched TSC writes into generations.
2105 * For each generation, we track the original measured
2106 * nanosecond time, offset, and write, so if TSCs are in
2107 * sync, we can match exact offset, and if not, we can match
2108 * exact software computation in compute_guest_tsc()
2110 * These values are tracked in kvm->arch.cur_xxx variables.
2112 kvm->arch.cur_tsc_generation++;
2113 kvm->arch.cur_tsc_nsec = ns;
2114 kvm->arch.cur_tsc_write = data;
2115 kvm->arch.cur_tsc_offset = offset;
2120 * We also track th most recent recorded KHZ, write and time to
2121 * allow the matching interval to be extended at each write.
2123 kvm->arch.last_tsc_nsec = ns;
2124 kvm->arch.last_tsc_write = data;
2125 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2127 vcpu->arch.last_guest_tsc = data;
2129 /* Keep track of which generation this VCPU has synchronized to */
2130 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2131 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2132 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2134 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
2135 update_ia32_tsc_adjust_msr(vcpu, offset);
2137 kvm_vcpu_write_tsc_offset(vcpu, offset);
2138 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2140 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2142 kvm->arch.nr_vcpus_matched_tsc = 0;
2143 } else if (!already_matched) {
2144 kvm->arch.nr_vcpus_matched_tsc++;
2147 kvm_track_tsc_matching(vcpu);
2148 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2151 EXPORT_SYMBOL_GPL(kvm_write_tsc);
2153 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2156 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2157 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2160 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2162 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2163 WARN_ON(adjustment < 0);
2164 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2165 adjust_tsc_offset_guest(vcpu, adjustment);
2168 #ifdef CONFIG_X86_64
2170 static u64 read_tsc(void)
2172 u64 ret = (u64)rdtsc_ordered();
2173 u64 last = pvclock_gtod_data.clock.cycle_last;
2175 if (likely(ret >= last))
2179 * GCC likes to generate cmov here, but this branch is extremely
2180 * predictable (it's just a function of time and the likely is
2181 * very likely) and there's a data dependence, so force GCC
2182 * to generate a branch instead. I don't barrier() because
2183 * we don't actually need a barrier, and if this function
2184 * ever gets inlined it will generate worse code.
2190 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2196 switch (clock->vclock_mode) {
2197 case VDSO_CLOCKMODE_HVCLOCK:
2198 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2200 if (tsc_pg_val != U64_MAX) {
2201 /* TSC page valid */
2202 *mode = VDSO_CLOCKMODE_HVCLOCK;
2203 v = (tsc_pg_val - clock->cycle_last) &
2206 /* TSC page invalid */
2207 *mode = VDSO_CLOCKMODE_NONE;
2210 case VDSO_CLOCKMODE_TSC:
2211 *mode = VDSO_CLOCKMODE_TSC;
2212 *tsc_timestamp = read_tsc();
2213 v = (*tsc_timestamp - clock->cycle_last) &
2217 *mode = VDSO_CLOCKMODE_NONE;
2220 if (*mode == VDSO_CLOCKMODE_NONE)
2221 *tsc_timestamp = v = 0;
2223 return v * clock->mult;
2226 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2228 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2234 seq = read_seqcount_begin(>od->seq);
2235 ns = gtod->raw_clock.base_cycles;
2236 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2237 ns >>= gtod->raw_clock.shift;
2238 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2239 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2245 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2247 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2253 seq = read_seqcount_begin(>od->seq);
2254 ts->tv_sec = gtod->wall_time_sec;
2255 ns = gtod->clock.base_cycles;
2256 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2257 ns >>= gtod->clock.shift;
2258 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2260 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2266 /* returns true if host is using TSC based clocksource */
2267 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2269 /* checked again under seqlock below */
2270 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2273 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2277 /* returns true if host is using TSC based clocksource */
2278 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2281 /* checked again under seqlock below */
2282 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2285 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2291 * Assuming a stable TSC across physical CPUS, and a stable TSC
2292 * across virtual CPUs, the following condition is possible.
2293 * Each numbered line represents an event visible to both
2294 * CPUs at the next numbered event.
2296 * "timespecX" represents host monotonic time. "tscX" represents
2299 * VCPU0 on CPU0 | VCPU1 on CPU1
2301 * 1. read timespec0,tsc0
2302 * 2. | timespec1 = timespec0 + N
2304 * 3. transition to guest | transition to guest
2305 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2306 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2307 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2309 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2312 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2314 * - 0 < N - M => M < N
2316 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2317 * always the case (the difference between two distinct xtime instances
2318 * might be smaller then the difference between corresponding TSC reads,
2319 * when updating guest vcpus pvclock areas).
2321 * To avoid that problem, do not allow visibility of distinct
2322 * system_timestamp/tsc_timestamp values simultaneously: use a master
2323 * copy of host monotonic time values. Update that master copy
2326 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2330 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2332 #ifdef CONFIG_X86_64
2333 struct kvm_arch *ka = &kvm->arch;
2335 bool host_tsc_clocksource, vcpus_matched;
2337 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2338 atomic_read(&kvm->online_vcpus));
2341 * If the host uses TSC clock, then passthrough TSC as stable
2344 host_tsc_clocksource = kvm_get_time_and_clockread(
2345 &ka->master_kernel_ns,
2346 &ka->master_cycle_now);
2348 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2349 && !ka->backwards_tsc_observed
2350 && !ka->boot_vcpu_runs_old_kvmclock;
2352 if (ka->use_master_clock)
2353 atomic_set(&kvm_guest_has_master_clock, 1);
2355 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2356 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2361 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2363 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2366 static void kvm_gen_update_masterclock(struct kvm *kvm)
2368 #ifdef CONFIG_X86_64
2370 struct kvm_vcpu *vcpu;
2371 struct kvm_arch *ka = &kvm->arch;
2373 spin_lock(&ka->pvclock_gtod_sync_lock);
2374 kvm_make_mclock_inprogress_request(kvm);
2375 /* no guest entries from this point */
2376 pvclock_update_vm_gtod_copy(kvm);
2378 kvm_for_each_vcpu(i, vcpu, kvm)
2379 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2381 /* guest entries allowed */
2382 kvm_for_each_vcpu(i, vcpu, kvm)
2383 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2385 spin_unlock(&ka->pvclock_gtod_sync_lock);
2389 u64 get_kvmclock_ns(struct kvm *kvm)
2391 struct kvm_arch *ka = &kvm->arch;
2392 struct pvclock_vcpu_time_info hv_clock;
2395 spin_lock(&ka->pvclock_gtod_sync_lock);
2396 if (!ka->use_master_clock) {
2397 spin_unlock(&ka->pvclock_gtod_sync_lock);
2398 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2401 hv_clock.tsc_timestamp = ka->master_cycle_now;
2402 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2403 spin_unlock(&ka->pvclock_gtod_sync_lock);
2405 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2408 if (__this_cpu_read(cpu_tsc_khz)) {
2409 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2410 &hv_clock.tsc_shift,
2411 &hv_clock.tsc_to_system_mul);
2412 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2414 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2421 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2423 struct kvm_vcpu_arch *vcpu = &v->arch;
2424 struct pvclock_vcpu_time_info guest_hv_clock;
2426 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2427 &guest_hv_clock, sizeof(guest_hv_clock))))
2430 /* This VCPU is paused, but it's legal for a guest to read another
2431 * VCPU's kvmclock, so we really have to follow the specification where
2432 * it says that version is odd if data is being modified, and even after
2435 * Version field updates must be kept separate. This is because
2436 * kvm_write_guest_cached might use a "rep movs" instruction, and
2437 * writes within a string instruction are weakly ordered. So there
2438 * are three writes overall.
2440 * As a small optimization, only write the version field in the first
2441 * and third write. The vcpu->pv_time cache is still valid, because the
2442 * version field is the first in the struct.
2444 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2446 if (guest_hv_clock.version & 1)
2447 ++guest_hv_clock.version; /* first time write, random junk */
2449 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2450 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2452 sizeof(vcpu->hv_clock.version));
2456 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2457 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2459 if (vcpu->pvclock_set_guest_stopped_request) {
2460 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2461 vcpu->pvclock_set_guest_stopped_request = false;
2464 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2466 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2468 sizeof(vcpu->hv_clock));
2472 vcpu->hv_clock.version++;
2473 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2475 sizeof(vcpu->hv_clock.version));
2478 static int kvm_guest_time_update(struct kvm_vcpu *v)
2480 unsigned long flags, tgt_tsc_khz;
2481 struct kvm_vcpu_arch *vcpu = &v->arch;
2482 struct kvm_arch *ka = &v->kvm->arch;
2484 u64 tsc_timestamp, host_tsc;
2486 bool use_master_clock;
2492 * If the host uses TSC clock, then passthrough TSC as stable
2495 spin_lock(&ka->pvclock_gtod_sync_lock);
2496 use_master_clock = ka->use_master_clock;
2497 if (use_master_clock) {
2498 host_tsc = ka->master_cycle_now;
2499 kernel_ns = ka->master_kernel_ns;
2501 spin_unlock(&ka->pvclock_gtod_sync_lock);
2503 /* Keep irq disabled to prevent changes to the clock */
2504 local_irq_save(flags);
2505 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2506 if (unlikely(tgt_tsc_khz == 0)) {
2507 local_irq_restore(flags);
2508 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2511 if (!use_master_clock) {
2513 kernel_ns = get_kvmclock_base_ns();
2516 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2519 * We may have to catch up the TSC to match elapsed wall clock
2520 * time for two reasons, even if kvmclock is used.
2521 * 1) CPU could have been running below the maximum TSC rate
2522 * 2) Broken TSC compensation resets the base at each VCPU
2523 * entry to avoid unknown leaps of TSC even when running
2524 * again on the same CPU. This may cause apparent elapsed
2525 * time to disappear, and the guest to stand still or run
2528 if (vcpu->tsc_catchup) {
2529 u64 tsc = compute_guest_tsc(v, kernel_ns);
2530 if (tsc > tsc_timestamp) {
2531 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2532 tsc_timestamp = tsc;
2536 local_irq_restore(flags);
2538 /* With all the info we got, fill in the values */
2540 if (kvm_has_tsc_control)
2541 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2543 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2544 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2545 &vcpu->hv_clock.tsc_shift,
2546 &vcpu->hv_clock.tsc_to_system_mul);
2547 vcpu->hw_tsc_khz = tgt_tsc_khz;
2550 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2551 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2552 vcpu->last_guest_tsc = tsc_timestamp;
2554 /* If the host uses TSC clocksource, then it is stable */
2556 if (use_master_clock)
2557 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2559 vcpu->hv_clock.flags = pvclock_flags;
2561 if (vcpu->pv_time_enabled)
2562 kvm_setup_pvclock_page(v);
2563 if (v == kvm_get_vcpu(v->kvm, 0))
2564 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2569 * kvmclock updates which are isolated to a given vcpu, such as
2570 * vcpu->cpu migration, should not allow system_timestamp from
2571 * the rest of the vcpus to remain static. Otherwise ntp frequency
2572 * correction applies to one vcpu's system_timestamp but not
2575 * So in those cases, request a kvmclock update for all vcpus.
2576 * We need to rate-limit these requests though, as they can
2577 * considerably slow guests that have a large number of vcpus.
2578 * The time for a remote vcpu to update its kvmclock is bound
2579 * by the delay we use to rate-limit the updates.
2582 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2584 static void kvmclock_update_fn(struct work_struct *work)
2587 struct delayed_work *dwork = to_delayed_work(work);
2588 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2589 kvmclock_update_work);
2590 struct kvm *kvm = container_of(ka, struct kvm, arch);
2591 struct kvm_vcpu *vcpu;
2593 kvm_for_each_vcpu(i, vcpu, kvm) {
2594 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2595 kvm_vcpu_kick(vcpu);
2599 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2601 struct kvm *kvm = v->kvm;
2603 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2604 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2605 KVMCLOCK_UPDATE_DELAY);
2608 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2610 static void kvmclock_sync_fn(struct work_struct *work)
2612 struct delayed_work *dwork = to_delayed_work(work);
2613 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2614 kvmclock_sync_work);
2615 struct kvm *kvm = container_of(ka, struct kvm, arch);
2617 if (!kvmclock_periodic_sync)
2620 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2621 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2622 KVMCLOCK_SYNC_PERIOD);
2626 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2628 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2630 /* McStatusWrEn enabled? */
2631 if (guest_cpuid_is_amd_or_hygon(vcpu))
2632 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2637 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2639 u64 mcg_cap = vcpu->arch.mcg_cap;
2640 unsigned bank_num = mcg_cap & 0xff;
2641 u32 msr = msr_info->index;
2642 u64 data = msr_info->data;
2645 case MSR_IA32_MCG_STATUS:
2646 vcpu->arch.mcg_status = data;
2648 case MSR_IA32_MCG_CTL:
2649 if (!(mcg_cap & MCG_CTL_P) &&
2650 (data || !msr_info->host_initiated))
2652 if (data != 0 && data != ~(u64)0)
2654 vcpu->arch.mcg_ctl = data;
2657 if (msr >= MSR_IA32_MC0_CTL &&
2658 msr < MSR_IA32_MCx_CTL(bank_num)) {
2659 u32 offset = array_index_nospec(
2660 msr - MSR_IA32_MC0_CTL,
2661 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2663 /* only 0 or all 1s can be written to IA32_MCi_CTL
2664 * some Linux kernels though clear bit 10 in bank 4 to
2665 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2666 * this to avoid an uncatched #GP in the guest
2668 if ((offset & 0x3) == 0 &&
2669 data != 0 && (data | (1 << 10)) != ~(u64)0)
2673 if (!msr_info->host_initiated &&
2674 (offset & 0x3) == 1 && data != 0) {
2675 if (!can_set_mci_status(vcpu))
2679 vcpu->arch.mce_banks[offset] = data;
2687 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2689 struct kvm *kvm = vcpu->kvm;
2690 int lm = is_long_mode(vcpu);
2691 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2692 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2693 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2694 : kvm->arch.xen_hvm_config.blob_size_32;
2695 u32 page_num = data & ~PAGE_MASK;
2696 u64 page_addr = data & PAGE_MASK;
2701 if (page_num >= blob_size)
2704 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2709 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2718 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
2720 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
2722 return (vcpu->arch.apf.msr_en_val & mask) == mask;
2725 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2727 gpa_t gpa = data & ~0x3f;
2729 /* Bits 4:5 are reserved, Should be zero */
2733 if (!lapic_in_kernel(vcpu))
2736 vcpu->arch.apf.msr_en_val = data;
2738 if (!kvm_pv_async_pf_enabled(vcpu)) {
2739 kvm_clear_async_pf_completion_queue(vcpu);
2740 kvm_async_pf_hash_reset(vcpu);
2744 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2748 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2749 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2751 kvm_async_pf_wakeup_all(vcpu);
2756 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
2758 /* Bits 8-63 are reserved */
2762 if (!lapic_in_kernel(vcpu))
2765 vcpu->arch.apf.msr_int_val = data;
2767 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
2772 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2774 vcpu->arch.pv_time_enabled = false;
2775 vcpu->arch.time = 0;
2778 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
2780 ++vcpu->stat.tlb_flush;
2781 kvm_x86_ops.tlb_flush_all(vcpu);
2784 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
2786 ++vcpu->stat.tlb_flush;
2787 kvm_x86_ops.tlb_flush_guest(vcpu);
2790 static void record_steal_time(struct kvm_vcpu *vcpu)
2792 struct kvm_host_map map;
2793 struct kvm_steal_time *st;
2795 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2798 /* -EAGAIN is returned in atomic context so we can just return. */
2799 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2800 &map, &vcpu->arch.st.cache, false))
2804 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2807 * Doing a TLB flush here, on the guest's behalf, can avoid
2810 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2811 st->preempted & KVM_VCPU_FLUSH_TLB);
2812 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2813 kvm_vcpu_flush_tlb_guest(vcpu);
2815 vcpu->arch.st.preempted = 0;
2817 if (st->version & 1)
2818 st->version += 1; /* first time write, random junk */
2824 st->steal += current->sched_info.run_delay -
2825 vcpu->arch.st.last_steal;
2826 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2832 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2835 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2838 u32 msr = msr_info->index;
2839 u64 data = msr_info->data;
2842 case MSR_AMD64_NB_CFG:
2843 case MSR_IA32_UCODE_WRITE:
2844 case MSR_VM_HSAVE_PA:
2845 case MSR_AMD64_PATCH_LOADER:
2846 case MSR_AMD64_BU_CFG2:
2847 case MSR_AMD64_DC_CFG:
2848 case MSR_F15H_EX_CFG:
2851 case MSR_IA32_UCODE_REV:
2852 if (msr_info->host_initiated)
2853 vcpu->arch.microcode_version = data;
2855 case MSR_IA32_ARCH_CAPABILITIES:
2856 if (!msr_info->host_initiated)
2858 vcpu->arch.arch_capabilities = data;
2860 case MSR_IA32_PERF_CAPABILITIES: {
2861 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
2863 if (!msr_info->host_initiated)
2865 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent))
2867 if (data & ~msr_ent.data)
2870 vcpu->arch.perf_capabilities = data;
2875 return set_efer(vcpu, msr_info);
2877 data &= ~(u64)0x40; /* ignore flush filter disable */
2878 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2879 data &= ~(u64)0x8; /* ignore TLB cache disable */
2881 /* Handle McStatusWrEn */
2882 if (data == BIT_ULL(18)) {
2883 vcpu->arch.msr_hwcr = data;
2884 } else if (data != 0) {
2885 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2890 case MSR_FAM10H_MMIO_CONF_BASE:
2892 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2897 case MSR_IA32_DEBUGCTLMSR:
2899 /* We support the non-activated case already */
2901 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2902 /* Values other than LBR and BTF are vendor-specific,
2903 thus reserved and should throw a #GP */
2906 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2909 case 0x200 ... 0x2ff:
2910 return kvm_mtrr_set_msr(vcpu, msr, data);
2911 case MSR_IA32_APICBASE:
2912 return kvm_set_apic_base(vcpu, msr_info);
2913 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
2914 return kvm_x2apic_msr_write(vcpu, msr, data);
2915 case MSR_IA32_TSCDEADLINE:
2916 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2918 case MSR_IA32_TSC_ADJUST:
2919 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2920 if (!msr_info->host_initiated) {
2921 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2922 adjust_tsc_offset_guest(vcpu, adj);
2924 vcpu->arch.ia32_tsc_adjust_msr = data;
2927 case MSR_IA32_MISC_ENABLE:
2928 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2929 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2930 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2932 vcpu->arch.ia32_misc_enable_msr = data;
2933 kvm_update_cpuid_runtime(vcpu);
2935 vcpu->arch.ia32_misc_enable_msr = data;
2938 case MSR_IA32_SMBASE:
2939 if (!msr_info->host_initiated)
2941 vcpu->arch.smbase = data;
2943 case MSR_IA32_POWER_CTL:
2944 vcpu->arch.msr_ia32_power_ctl = data;
2947 kvm_write_tsc(vcpu, msr_info);
2950 if (!msr_info->host_initiated &&
2951 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
2954 * KVM supports exposing PT to the guest, but does not support
2955 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
2956 * XSAVES/XRSTORS to save/restore PT MSRs.
2958 if (data & ~supported_xss)
2960 vcpu->arch.ia32_xss = data;
2963 if (!msr_info->host_initiated)
2965 vcpu->arch.smi_count = data;
2967 case MSR_KVM_WALL_CLOCK_NEW:
2968 case MSR_KVM_WALL_CLOCK:
2969 vcpu->kvm->arch.wall_clock = data;
2970 kvm_write_wall_clock(vcpu->kvm, data);
2972 case MSR_KVM_SYSTEM_TIME_NEW:
2973 case MSR_KVM_SYSTEM_TIME: {
2974 struct kvm_arch *ka = &vcpu->kvm->arch;
2976 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2977 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2979 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2980 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2982 ka->boot_vcpu_runs_old_kvmclock = tmp;
2985 vcpu->arch.time = data;
2986 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2988 /* we verify if the enable bit is set... */
2989 vcpu->arch.pv_time_enabled = false;
2993 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2994 &vcpu->arch.pv_time, data & ~1ULL,
2995 sizeof(struct pvclock_vcpu_time_info)))
2996 vcpu->arch.pv_time_enabled = true;
3000 case MSR_KVM_ASYNC_PF_EN:
3001 if (kvm_pv_enable_async_pf(vcpu, data))
3004 case MSR_KVM_ASYNC_PF_INT:
3005 if (kvm_pv_enable_async_pf_int(vcpu, data))
3008 case MSR_KVM_ASYNC_PF_ACK:
3010 vcpu->arch.apf.pageready_pending = false;
3011 kvm_check_async_pf_completion(vcpu);
3014 case MSR_KVM_STEAL_TIME:
3016 if (unlikely(!sched_info_on()))
3019 if (data & KVM_STEAL_RESERVED_MASK)
3022 vcpu->arch.st.msr_val = data;
3024 if (!(data & KVM_MSR_ENABLED))
3027 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3030 case MSR_KVM_PV_EOI_EN:
3031 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
3035 case MSR_KVM_POLL_CONTROL:
3036 /* only enable bit supported */
3037 if (data & (-1ULL << 1))
3040 vcpu->arch.msr_kvm_poll_control = data;
3043 case MSR_IA32_MCG_CTL:
3044 case MSR_IA32_MCG_STATUS:
3045 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3046 return set_msr_mce(vcpu, msr_info);
3048 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3049 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3052 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3053 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3054 if (kvm_pmu_is_valid_msr(vcpu, msr))
3055 return kvm_pmu_set_msr(vcpu, msr_info);
3057 if (pr || data != 0)
3058 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3059 "0x%x data 0x%llx\n", msr, data);
3061 case MSR_K7_CLK_CTL:
3063 * Ignore all writes to this no longer documented MSR.
3064 * Writes are only relevant for old K7 processors,
3065 * all pre-dating SVM, but a recommended workaround from
3066 * AMD for these chips. It is possible to specify the
3067 * affected processor models on the command line, hence
3068 * the need to ignore the workaround.
3071 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3072 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3073 case HV_X64_MSR_SYNDBG_OPTIONS:
3074 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3075 case HV_X64_MSR_CRASH_CTL:
3076 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3077 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3078 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3079 case HV_X64_MSR_TSC_EMULATION_STATUS:
3080 return kvm_hv_set_msr_common(vcpu, msr, data,
3081 msr_info->host_initiated);
3082 case MSR_IA32_BBL_CR_CTL3:
3083 /* Drop writes to this legacy MSR -- see rdmsr
3084 * counterpart for further detail.
3086 if (report_ignored_msrs)
3087 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3090 case MSR_AMD64_OSVW_ID_LENGTH:
3091 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3093 vcpu->arch.osvw.length = data;
3095 case MSR_AMD64_OSVW_STATUS:
3096 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3098 vcpu->arch.osvw.status = data;
3100 case MSR_PLATFORM_INFO:
3101 if (!msr_info->host_initiated ||
3102 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3103 cpuid_fault_enabled(vcpu)))
3105 vcpu->arch.msr_platform_info = data;
3107 case MSR_MISC_FEATURES_ENABLES:
3108 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3109 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3110 !supports_cpuid_fault(vcpu)))
3112 vcpu->arch.msr_misc_features_enables = data;
3115 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
3116 return xen_hvm_config(vcpu, data);
3117 if (kvm_pmu_is_valid_msr(vcpu, msr))
3118 return kvm_pmu_set_msr(vcpu, msr_info);
3119 return KVM_MSR_RET_INVALID;
3123 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3125 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3128 u64 mcg_cap = vcpu->arch.mcg_cap;
3129 unsigned bank_num = mcg_cap & 0xff;
3132 case MSR_IA32_P5_MC_ADDR:
3133 case MSR_IA32_P5_MC_TYPE:
3136 case MSR_IA32_MCG_CAP:
3137 data = vcpu->arch.mcg_cap;
3139 case MSR_IA32_MCG_CTL:
3140 if (!(mcg_cap & MCG_CTL_P) && !host)
3142 data = vcpu->arch.mcg_ctl;
3144 case MSR_IA32_MCG_STATUS:
3145 data = vcpu->arch.mcg_status;
3148 if (msr >= MSR_IA32_MC0_CTL &&
3149 msr < MSR_IA32_MCx_CTL(bank_num)) {
3150 u32 offset = array_index_nospec(
3151 msr - MSR_IA32_MC0_CTL,
3152 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3154 data = vcpu->arch.mce_banks[offset];
3163 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3165 switch (msr_info->index) {
3166 case MSR_IA32_PLATFORM_ID:
3167 case MSR_IA32_EBL_CR_POWERON:
3168 case MSR_IA32_DEBUGCTLMSR:
3169 case MSR_IA32_LASTBRANCHFROMIP:
3170 case MSR_IA32_LASTBRANCHTOIP:
3171 case MSR_IA32_LASTINTFROMIP:
3172 case MSR_IA32_LASTINTTOIP:
3174 case MSR_K8_TSEG_ADDR:
3175 case MSR_K8_TSEG_MASK:
3176 case MSR_VM_HSAVE_PA:
3177 case MSR_K8_INT_PENDING_MSG:
3178 case MSR_AMD64_NB_CFG:
3179 case MSR_FAM10H_MMIO_CONF_BASE:
3180 case MSR_AMD64_BU_CFG2:
3181 case MSR_IA32_PERF_CTL:
3182 case MSR_AMD64_DC_CFG:
3183 case MSR_F15H_EX_CFG:
3185 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3186 * limit) MSRs. Just return 0, as we do not want to expose the host
3187 * data here. Do not conditionalize this on CPUID, as KVM does not do
3188 * so for existing CPU-specific MSRs.
3190 case MSR_RAPL_POWER_UNIT:
3191 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3192 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3193 case MSR_PKG_ENERGY_STATUS: /* Total package */
3194 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3197 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3198 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3199 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3200 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3201 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3202 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3203 return kvm_pmu_get_msr(vcpu, msr_info);
3206 case MSR_IA32_UCODE_REV:
3207 msr_info->data = vcpu->arch.microcode_version;
3209 case MSR_IA32_ARCH_CAPABILITIES:
3210 if (!msr_info->host_initiated &&
3211 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3213 msr_info->data = vcpu->arch.arch_capabilities;
3215 case MSR_IA32_PERF_CAPABILITIES:
3216 if (!msr_info->host_initiated &&
3217 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3219 msr_info->data = vcpu->arch.perf_capabilities;
3221 case MSR_IA32_POWER_CTL:
3222 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3225 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
3228 case 0x200 ... 0x2ff:
3229 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3230 case 0xcd: /* fsb frequency */
3234 * MSR_EBC_FREQUENCY_ID
3235 * Conservative value valid for even the basic CPU models.
3236 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3237 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3238 * and 266MHz for model 3, or 4. Set Core Clock
3239 * Frequency to System Bus Frequency Ratio to 1 (bits
3240 * 31:24) even though these are only valid for CPU
3241 * models > 2, however guests may end up dividing or
3242 * multiplying by zero otherwise.
3244 case MSR_EBC_FREQUENCY_ID:
3245 msr_info->data = 1 << 24;
3247 case MSR_IA32_APICBASE:
3248 msr_info->data = kvm_get_apic_base(vcpu);
3250 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3251 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3252 case MSR_IA32_TSCDEADLINE:
3253 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3255 case MSR_IA32_TSC_ADJUST:
3256 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3258 case MSR_IA32_MISC_ENABLE:
3259 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3261 case MSR_IA32_SMBASE:
3262 if (!msr_info->host_initiated)
3264 msr_info->data = vcpu->arch.smbase;
3267 msr_info->data = vcpu->arch.smi_count;
3269 case MSR_IA32_PERF_STATUS:
3270 /* TSC increment by tick */
3271 msr_info->data = 1000ULL;
3272 /* CPU multiplier */
3273 msr_info->data |= (((uint64_t)4ULL) << 40);
3276 msr_info->data = vcpu->arch.efer;
3278 case MSR_KVM_WALL_CLOCK:
3279 case MSR_KVM_WALL_CLOCK_NEW:
3280 msr_info->data = vcpu->kvm->arch.wall_clock;
3282 case MSR_KVM_SYSTEM_TIME:
3283 case MSR_KVM_SYSTEM_TIME_NEW:
3284 msr_info->data = vcpu->arch.time;
3286 case MSR_KVM_ASYNC_PF_EN:
3287 msr_info->data = vcpu->arch.apf.msr_en_val;
3289 case MSR_KVM_ASYNC_PF_INT:
3290 msr_info->data = vcpu->arch.apf.msr_int_val;
3292 case MSR_KVM_ASYNC_PF_ACK:
3295 case MSR_KVM_STEAL_TIME:
3296 msr_info->data = vcpu->arch.st.msr_val;
3298 case MSR_KVM_PV_EOI_EN:
3299 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3301 case MSR_KVM_POLL_CONTROL:
3302 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3304 case MSR_IA32_P5_MC_ADDR:
3305 case MSR_IA32_P5_MC_TYPE:
3306 case MSR_IA32_MCG_CAP:
3307 case MSR_IA32_MCG_CTL:
3308 case MSR_IA32_MCG_STATUS:
3309 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3310 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3311 msr_info->host_initiated);
3313 if (!msr_info->host_initiated &&
3314 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3316 msr_info->data = vcpu->arch.ia32_xss;
3318 case MSR_K7_CLK_CTL:
3320 * Provide expected ramp-up count for K7. All other
3321 * are set to zero, indicating minimum divisors for
3324 * This prevents guest kernels on AMD host with CPU
3325 * type 6, model 8 and higher from exploding due to
3326 * the rdmsr failing.
3328 msr_info->data = 0x20000000;
3330 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3331 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3332 case HV_X64_MSR_SYNDBG_OPTIONS:
3333 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3334 case HV_X64_MSR_CRASH_CTL:
3335 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3336 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3337 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3338 case HV_X64_MSR_TSC_EMULATION_STATUS:
3339 return kvm_hv_get_msr_common(vcpu,
3340 msr_info->index, &msr_info->data,
3341 msr_info->host_initiated);
3342 case MSR_IA32_BBL_CR_CTL3:
3343 /* This legacy MSR exists but isn't fully documented in current
3344 * silicon. It is however accessed by winxp in very narrow
3345 * scenarios where it sets bit #19, itself documented as
3346 * a "reserved" bit. Best effort attempt to source coherent
3347 * read data here should the balance of the register be
3348 * interpreted by the guest:
3350 * L2 cache control register 3: 64GB range, 256KB size,
3351 * enabled, latency 0x1, configured
3353 msr_info->data = 0xbe702111;
3355 case MSR_AMD64_OSVW_ID_LENGTH:
3356 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3358 msr_info->data = vcpu->arch.osvw.length;
3360 case MSR_AMD64_OSVW_STATUS:
3361 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3363 msr_info->data = vcpu->arch.osvw.status;
3365 case MSR_PLATFORM_INFO:
3366 if (!msr_info->host_initiated &&
3367 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3369 msr_info->data = vcpu->arch.msr_platform_info;
3371 case MSR_MISC_FEATURES_ENABLES:
3372 msr_info->data = vcpu->arch.msr_misc_features_enables;
3375 msr_info->data = vcpu->arch.msr_hwcr;
3378 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3379 return kvm_pmu_get_msr(vcpu, msr_info);
3380 return KVM_MSR_RET_INVALID;
3384 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3387 * Read or write a bunch of msrs. All parameters are kernel addresses.
3389 * @return number of msrs set successfully.
3391 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3392 struct kvm_msr_entry *entries,
3393 int (*do_msr)(struct kvm_vcpu *vcpu,
3394 unsigned index, u64 *data))
3398 for (i = 0; i < msrs->nmsrs; ++i)
3399 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3406 * Read or write a bunch of msrs. Parameters are user addresses.
3408 * @return number of msrs set successfully.
3410 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3411 int (*do_msr)(struct kvm_vcpu *vcpu,
3412 unsigned index, u64 *data),
3415 struct kvm_msrs msrs;
3416 struct kvm_msr_entry *entries;
3421 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3425 if (msrs.nmsrs >= MAX_IO_MSRS)
3428 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3429 entries = memdup_user(user_msrs->entries, size);
3430 if (IS_ERR(entries)) {
3431 r = PTR_ERR(entries);
3435 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3440 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3451 static inline bool kvm_can_mwait_in_guest(void)
3453 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3454 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3455 boot_cpu_has(X86_FEATURE_ARAT);
3458 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3463 case KVM_CAP_IRQCHIP:
3465 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3466 case KVM_CAP_SET_TSS_ADDR:
3467 case KVM_CAP_EXT_CPUID:
3468 case KVM_CAP_EXT_EMUL_CPUID:
3469 case KVM_CAP_CLOCKSOURCE:
3471 case KVM_CAP_NOP_IO_DELAY:
3472 case KVM_CAP_MP_STATE:
3473 case KVM_CAP_SYNC_MMU:
3474 case KVM_CAP_USER_NMI:
3475 case KVM_CAP_REINJECT_CONTROL:
3476 case KVM_CAP_IRQ_INJECT_STATUS:
3477 case KVM_CAP_IOEVENTFD:
3478 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3480 case KVM_CAP_PIT_STATE2:
3481 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3482 case KVM_CAP_XEN_HVM:
3483 case KVM_CAP_VCPU_EVENTS:
3484 case KVM_CAP_HYPERV:
3485 case KVM_CAP_HYPERV_VAPIC:
3486 case KVM_CAP_HYPERV_SPIN:
3487 case KVM_CAP_HYPERV_SYNIC:
3488 case KVM_CAP_HYPERV_SYNIC2:
3489 case KVM_CAP_HYPERV_VP_INDEX:
3490 case KVM_CAP_HYPERV_EVENTFD:
3491 case KVM_CAP_HYPERV_TLBFLUSH:
3492 case KVM_CAP_HYPERV_SEND_IPI:
3493 case KVM_CAP_HYPERV_CPUID:
3494 case KVM_CAP_PCI_SEGMENT:
3495 case KVM_CAP_DEBUGREGS:
3496 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3498 case KVM_CAP_ASYNC_PF:
3499 case KVM_CAP_ASYNC_PF_INT:
3500 case KVM_CAP_GET_TSC_KHZ:
3501 case KVM_CAP_KVMCLOCK_CTRL:
3502 case KVM_CAP_READONLY_MEM:
3503 case KVM_CAP_HYPERV_TIME:
3504 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3505 case KVM_CAP_TSC_DEADLINE_TIMER:
3506 case KVM_CAP_DISABLE_QUIRKS:
3507 case KVM_CAP_SET_BOOT_CPU_ID:
3508 case KVM_CAP_SPLIT_IRQCHIP:
3509 case KVM_CAP_IMMEDIATE_EXIT:
3510 case KVM_CAP_PMU_EVENT_FILTER:
3511 case KVM_CAP_GET_MSR_FEATURES:
3512 case KVM_CAP_MSR_PLATFORM_INFO:
3513 case KVM_CAP_EXCEPTION_PAYLOAD:
3514 case KVM_CAP_SET_GUEST_DEBUG:
3515 case KVM_CAP_LAST_CPU:
3518 case KVM_CAP_SYNC_REGS:
3519 r = KVM_SYNC_X86_VALID_FIELDS;
3521 case KVM_CAP_ADJUST_CLOCK:
3522 r = KVM_CLOCK_TSC_STABLE;
3524 case KVM_CAP_X86_DISABLE_EXITS:
3525 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3526 KVM_X86_DISABLE_EXITS_CSTATE;
3527 if(kvm_can_mwait_in_guest())
3528 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3530 case KVM_CAP_X86_SMM:
3531 /* SMBASE is usually relocated above 1M on modern chipsets,
3532 * and SMM handlers might indeed rely on 4G segment limits,
3533 * so do not report SMM to be available if real mode is
3534 * emulated via vm86 mode. Still, do not go to great lengths
3535 * to avoid userspace's usage of the feature, because it is a
3536 * fringe case that is not enabled except via specific settings
3537 * of the module parameters.
3539 r = kvm_x86_ops.has_emulated_msr(MSR_IA32_SMBASE);
3542 r = !kvm_x86_ops.cpu_has_accelerated_tpr();
3544 case KVM_CAP_NR_VCPUS:
3545 r = KVM_SOFT_MAX_VCPUS;
3547 case KVM_CAP_MAX_VCPUS:
3550 case KVM_CAP_MAX_VCPU_ID:
3551 r = KVM_MAX_VCPU_ID;
3553 case KVM_CAP_PV_MMU: /* obsolete */
3557 r = KVM_MAX_MCE_BANKS;
3560 r = boot_cpu_has(X86_FEATURE_XSAVE);
3562 case KVM_CAP_TSC_CONTROL:
3563 r = kvm_has_tsc_control;
3565 case KVM_CAP_X2APIC_API:
3566 r = KVM_X2APIC_API_VALID_FLAGS;
3568 case KVM_CAP_NESTED_STATE:
3569 r = kvm_x86_ops.nested_ops->get_state ?
3570 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
3572 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3573 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3575 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3576 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
3578 case KVM_CAP_SMALLER_MAXPHYADDR:
3579 r = (int) allow_smaller_maxphyaddr;
3588 long kvm_arch_dev_ioctl(struct file *filp,
3589 unsigned int ioctl, unsigned long arg)
3591 void __user *argp = (void __user *)arg;
3595 case KVM_GET_MSR_INDEX_LIST: {
3596 struct kvm_msr_list __user *user_msr_list = argp;
3597 struct kvm_msr_list msr_list;
3601 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3604 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3605 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3608 if (n < msr_list.nmsrs)
3611 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3612 num_msrs_to_save * sizeof(u32)))
3614 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3616 num_emulated_msrs * sizeof(u32)))
3621 case KVM_GET_SUPPORTED_CPUID:
3622 case KVM_GET_EMULATED_CPUID: {
3623 struct kvm_cpuid2 __user *cpuid_arg = argp;
3624 struct kvm_cpuid2 cpuid;
3627 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3630 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3636 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3641 case KVM_X86_GET_MCE_CAP_SUPPORTED:
3643 if (copy_to_user(argp, &kvm_mce_cap_supported,
3644 sizeof(kvm_mce_cap_supported)))
3648 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3649 struct kvm_msr_list __user *user_msr_list = argp;
3650 struct kvm_msr_list msr_list;
3654 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3657 msr_list.nmsrs = num_msr_based_features;
3658 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3661 if (n < msr_list.nmsrs)
3664 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3665 num_msr_based_features * sizeof(u32)))
3671 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3681 static void wbinvd_ipi(void *garbage)
3686 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3688 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3691 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3693 /* Address WBINVD may be executed by guest */
3694 if (need_emulate_wbinvd(vcpu)) {
3695 if (kvm_x86_ops.has_wbinvd_exit())
3696 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3697 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3698 smp_call_function_single(vcpu->cpu,
3699 wbinvd_ipi, NULL, 1);
3702 kvm_x86_ops.vcpu_load(vcpu, cpu);
3704 /* Save host pkru register if supported */
3705 vcpu->arch.host_pkru = read_pkru();
3707 /* Apply any externally detected TSC adjustments (due to suspend) */
3708 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3709 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3710 vcpu->arch.tsc_offset_adjustment = 0;
3711 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3714 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3715 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3716 rdtsc() - vcpu->arch.last_host_tsc;
3718 mark_tsc_unstable("KVM discovered backwards TSC");
3720 if (kvm_check_tsc_unstable()) {
3721 u64 offset = kvm_compute_tsc_offset(vcpu,
3722 vcpu->arch.last_guest_tsc);
3723 kvm_vcpu_write_tsc_offset(vcpu, offset);
3724 vcpu->arch.tsc_catchup = 1;
3727 if (kvm_lapic_hv_timer_in_use(vcpu))
3728 kvm_lapic_restart_hv_timer(vcpu);
3731 * On a host with synchronized TSC, there is no need to update
3732 * kvmclock on vcpu->cpu migration
3734 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3735 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3736 if (vcpu->cpu != cpu)
3737 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3741 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3744 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3746 struct kvm_host_map map;
3747 struct kvm_steal_time *st;
3749 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3752 if (vcpu->arch.st.preempted)
3755 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3756 &vcpu->arch.st.cache, true))
3760 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
3762 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
3764 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
3767 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3771 if (vcpu->preempted)
3772 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu);
3775 * Disable page faults because we're in atomic context here.
3776 * kvm_write_guest_offset_cached() would call might_fault()
3777 * that relies on pagefault_disable() to tell if there's a
3778 * bug. NOTE: the write to guest memory may not go through if
3779 * during postcopy live migration or if there's heavy guest
3782 pagefault_disable();
3784 * kvm_memslots() will be called by
3785 * kvm_write_guest_offset_cached() so take the srcu lock.
3787 idx = srcu_read_lock(&vcpu->kvm->srcu);
3788 kvm_steal_time_set_preempted(vcpu);
3789 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3791 kvm_x86_ops.vcpu_put(vcpu);
3792 vcpu->arch.last_host_tsc = rdtsc();
3794 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3795 * on every vmexit, but if not, we might have a stale dr6 from the
3796 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3801 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3802 struct kvm_lapic_state *s)
3804 if (vcpu->arch.apicv_active)
3805 kvm_x86_ops.sync_pir_to_irr(vcpu);
3807 return kvm_apic_get_state(vcpu, s);
3810 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3811 struct kvm_lapic_state *s)
3815 r = kvm_apic_set_state(vcpu, s);
3818 update_cr8_intercept(vcpu);
3823 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3825 return (!lapic_in_kernel(vcpu) ||
3826 kvm_apic_accept_pic_intr(vcpu));
3830 * if userspace requested an interrupt window, check that the
3831 * interrupt window is open.
3833 * No need to exit to userspace if we already have an interrupt queued.
3835 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3837 return kvm_arch_interrupt_allowed(vcpu) &&
3838 !kvm_cpu_has_interrupt(vcpu) &&
3839 !kvm_event_needs_reinjection(vcpu) &&
3840 kvm_cpu_accept_dm_intr(vcpu);
3843 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3844 struct kvm_interrupt *irq)
3846 if (irq->irq >= KVM_NR_INTERRUPTS)
3849 if (!irqchip_in_kernel(vcpu->kvm)) {
3850 kvm_queue_interrupt(vcpu, irq->irq, false);
3851 kvm_make_request(KVM_REQ_EVENT, vcpu);
3856 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3857 * fail for in-kernel 8259.
3859 if (pic_in_kernel(vcpu->kvm))
3862 if (vcpu->arch.pending_external_vector != -1)
3865 vcpu->arch.pending_external_vector = irq->irq;
3866 kvm_make_request(KVM_REQ_EVENT, vcpu);
3870 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3872 kvm_inject_nmi(vcpu);
3877 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3879 kvm_make_request(KVM_REQ_SMI, vcpu);
3884 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3885 struct kvm_tpr_access_ctl *tac)
3889 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3893 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3897 unsigned bank_num = mcg_cap & 0xff, bank;
3900 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
3902 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3905 vcpu->arch.mcg_cap = mcg_cap;
3906 /* Init IA32_MCG_CTL to all 1s */
3907 if (mcg_cap & MCG_CTL_P)
3908 vcpu->arch.mcg_ctl = ~(u64)0;
3909 /* Init IA32_MCi_CTL to all 1s */
3910 for (bank = 0; bank < bank_num; bank++)
3911 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3913 kvm_x86_ops.setup_mce(vcpu);
3918 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3919 struct kvm_x86_mce *mce)
3921 u64 mcg_cap = vcpu->arch.mcg_cap;
3922 unsigned bank_num = mcg_cap & 0xff;
3923 u64 *banks = vcpu->arch.mce_banks;
3925 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3928 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3929 * reporting is disabled
3931 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3932 vcpu->arch.mcg_ctl != ~(u64)0)
3934 banks += 4 * mce->bank;
3936 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3937 * reporting is disabled for the bank
3939 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3941 if (mce->status & MCI_STATUS_UC) {
3942 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3943 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3944 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3947 if (banks[1] & MCI_STATUS_VAL)
3948 mce->status |= MCI_STATUS_OVER;
3949 banks[2] = mce->addr;
3950 banks[3] = mce->misc;
3951 vcpu->arch.mcg_status = mce->mcg_status;
3952 banks[1] = mce->status;
3953 kvm_queue_exception(vcpu, MC_VECTOR);
3954 } else if (!(banks[1] & MCI_STATUS_VAL)
3955 || !(banks[1] & MCI_STATUS_UC)) {
3956 if (banks[1] & MCI_STATUS_VAL)
3957 mce->status |= MCI_STATUS_OVER;
3958 banks[2] = mce->addr;
3959 banks[3] = mce->misc;
3960 banks[1] = mce->status;
3962 banks[1] |= MCI_STATUS_OVER;
3966 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3967 struct kvm_vcpu_events *events)
3972 * In guest mode, payload delivery should be deferred,
3973 * so that the L1 hypervisor can intercept #PF before
3974 * CR2 is modified (or intercept #DB before DR6 is
3975 * modified under nVMX). Unless the per-VM capability,
3976 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
3977 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
3978 * opportunistically defer the exception payload, deliver it if the
3979 * capability hasn't been requested before processing a
3980 * KVM_GET_VCPU_EVENTS.
3982 if (!vcpu->kvm->arch.exception_payload_enabled &&
3983 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
3984 kvm_deliver_exception_payload(vcpu);
3987 * The API doesn't provide the instruction length for software
3988 * exceptions, so don't report them. As long as the guest RIP
3989 * isn't advanced, we should expect to encounter the exception
3992 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3993 events->exception.injected = 0;
3994 events->exception.pending = 0;
3996 events->exception.injected = vcpu->arch.exception.injected;
3997 events->exception.pending = vcpu->arch.exception.pending;
3999 * For ABI compatibility, deliberately conflate
4000 * pending and injected exceptions when
4001 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
4003 if (!vcpu->kvm->arch.exception_payload_enabled)
4004 events->exception.injected |=
4005 vcpu->arch.exception.pending;
4007 events->exception.nr = vcpu->arch.exception.nr;
4008 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
4009 events->exception.error_code = vcpu->arch.exception.error_code;
4010 events->exception_has_payload = vcpu->arch.exception.has_payload;
4011 events->exception_payload = vcpu->arch.exception.payload;
4013 events->interrupt.injected =
4014 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
4015 events->interrupt.nr = vcpu->arch.interrupt.nr;
4016 events->interrupt.soft = 0;
4017 events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
4019 events->nmi.injected = vcpu->arch.nmi_injected;
4020 events->nmi.pending = vcpu->arch.nmi_pending != 0;
4021 events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu);
4022 events->nmi.pad = 0;
4024 events->sipi_vector = 0; /* never valid when reporting to user space */
4026 events->smi.smm = is_smm(vcpu);
4027 events->smi.pending = vcpu->arch.smi_pending;
4028 events->smi.smm_inside_nmi =
4029 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
4030 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
4032 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
4033 | KVM_VCPUEVENT_VALID_SHADOW
4034 | KVM_VCPUEVENT_VALID_SMM);
4035 if (vcpu->kvm->arch.exception_payload_enabled)
4036 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4038 memset(&events->reserved, 0, sizeof(events->reserved));
4041 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
4043 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4044 struct kvm_vcpu_events *events)
4046 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4047 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4048 | KVM_VCPUEVENT_VALID_SHADOW
4049 | KVM_VCPUEVENT_VALID_SMM
4050 | KVM_VCPUEVENT_VALID_PAYLOAD))
4053 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4054 if (!vcpu->kvm->arch.exception_payload_enabled)
4056 if (events->exception.pending)
4057 events->exception.injected = 0;
4059 events->exception_has_payload = 0;
4061 events->exception.pending = 0;
4062 events->exception_has_payload = 0;
4065 if ((events->exception.injected || events->exception.pending) &&
4066 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4069 /* INITs are latched while in SMM */
4070 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4071 (events->smi.smm || events->smi.pending) &&
4072 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4076 vcpu->arch.exception.injected = events->exception.injected;
4077 vcpu->arch.exception.pending = events->exception.pending;
4078 vcpu->arch.exception.nr = events->exception.nr;
4079 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4080 vcpu->arch.exception.error_code = events->exception.error_code;
4081 vcpu->arch.exception.has_payload = events->exception_has_payload;
4082 vcpu->arch.exception.payload = events->exception_payload;
4084 vcpu->arch.interrupt.injected = events->interrupt.injected;
4085 vcpu->arch.interrupt.nr = events->interrupt.nr;
4086 vcpu->arch.interrupt.soft = events->interrupt.soft;
4087 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4088 kvm_x86_ops.set_interrupt_shadow(vcpu,
4089 events->interrupt.shadow);
4091 vcpu->arch.nmi_injected = events->nmi.injected;
4092 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4093 vcpu->arch.nmi_pending = events->nmi.pending;
4094 kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked);
4096 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4097 lapic_in_kernel(vcpu))
4098 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4100 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4101 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4102 if (events->smi.smm)
4103 vcpu->arch.hflags |= HF_SMM_MASK;
4105 vcpu->arch.hflags &= ~HF_SMM_MASK;
4106 kvm_smm_changed(vcpu);
4109 vcpu->arch.smi_pending = events->smi.pending;
4111 if (events->smi.smm) {
4112 if (events->smi.smm_inside_nmi)
4113 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4115 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4118 if (lapic_in_kernel(vcpu)) {
4119 if (events->smi.latched_init)
4120 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4122 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4126 kvm_make_request(KVM_REQ_EVENT, vcpu);
4131 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4132 struct kvm_debugregs *dbgregs)
4136 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4137 kvm_get_dr(vcpu, 6, &val);
4139 dbgregs->dr7 = vcpu->arch.dr7;
4141 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4144 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4145 struct kvm_debugregs *dbgregs)
4150 if (dbgregs->dr6 & ~0xffffffffull)
4152 if (dbgregs->dr7 & ~0xffffffffull)
4155 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4156 kvm_update_dr0123(vcpu);
4157 vcpu->arch.dr6 = dbgregs->dr6;
4158 vcpu->arch.dr7 = dbgregs->dr7;
4159 kvm_update_dr7(vcpu);
4164 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4166 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4168 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4169 u64 xstate_bv = xsave->header.xfeatures;
4173 * Copy legacy XSAVE area, to avoid complications with CPUID
4174 * leaves 0 and 1 in the loop below.
4176 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4179 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4180 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4183 * Copy each region from the possibly compacted offset to the
4184 * non-compacted offset.
4186 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4188 u64 xfeature_mask = valid & -valid;
4189 int xfeature_nr = fls64(xfeature_mask) - 1;
4190 void *src = get_xsave_addr(xsave, xfeature_nr);
4193 u32 size, offset, ecx, edx;
4194 cpuid_count(XSTATE_CPUID, xfeature_nr,
4195 &size, &offset, &ecx, &edx);
4196 if (xfeature_nr == XFEATURE_PKRU)
4197 memcpy(dest + offset, &vcpu->arch.pkru,
4198 sizeof(vcpu->arch.pkru));
4200 memcpy(dest + offset, src, size);
4204 valid -= xfeature_mask;
4208 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4210 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4211 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4215 * Copy legacy XSAVE area, to avoid complications with CPUID
4216 * leaves 0 and 1 in the loop below.
4218 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4220 /* Set XSTATE_BV and possibly XCOMP_BV. */
4221 xsave->header.xfeatures = xstate_bv;
4222 if (boot_cpu_has(X86_FEATURE_XSAVES))
4223 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4226 * Copy each region from the non-compacted offset to the
4227 * possibly compacted offset.
4229 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4231 u64 xfeature_mask = valid & -valid;
4232 int xfeature_nr = fls64(xfeature_mask) - 1;
4233 void *dest = get_xsave_addr(xsave, xfeature_nr);
4236 u32 size, offset, ecx, edx;
4237 cpuid_count(XSTATE_CPUID, xfeature_nr,
4238 &size, &offset, &ecx, &edx);
4239 if (xfeature_nr == XFEATURE_PKRU)
4240 memcpy(&vcpu->arch.pkru, src + offset,
4241 sizeof(vcpu->arch.pkru));
4243 memcpy(dest, src + offset, size);
4246 valid -= xfeature_mask;
4250 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4251 struct kvm_xsave *guest_xsave)
4253 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4254 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4255 fill_xsave((u8 *) guest_xsave->region, vcpu);
4257 memcpy(guest_xsave->region,
4258 &vcpu->arch.guest_fpu->state.fxsave,
4259 sizeof(struct fxregs_state));
4260 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4261 XFEATURE_MASK_FPSSE;
4265 #define XSAVE_MXCSR_OFFSET 24
4267 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4268 struct kvm_xsave *guest_xsave)
4271 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4272 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4274 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4276 * Here we allow setting states that are not present in
4277 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4278 * with old userspace.
4280 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4282 load_xsave(vcpu, (u8 *)guest_xsave->region);
4284 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4285 mxcsr & ~mxcsr_feature_mask)
4287 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4288 guest_xsave->region, sizeof(struct fxregs_state));
4293 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4294 struct kvm_xcrs *guest_xcrs)
4296 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4297 guest_xcrs->nr_xcrs = 0;
4301 guest_xcrs->nr_xcrs = 1;
4302 guest_xcrs->flags = 0;
4303 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4304 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4307 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4308 struct kvm_xcrs *guest_xcrs)
4312 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4315 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4318 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4319 /* Only support XCR0 currently */
4320 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4321 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4322 guest_xcrs->xcrs[i].value);
4331 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4332 * stopped by the hypervisor. This function will be called from the host only.
4333 * EINVAL is returned when the host attempts to set the flag for a guest that
4334 * does not support pv clocks.
4336 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4338 if (!vcpu->arch.pv_time_enabled)
4340 vcpu->arch.pvclock_set_guest_stopped_request = true;
4341 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4345 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4346 struct kvm_enable_cap *cap)
4349 uint16_t vmcs_version;
4350 void __user *user_ptr;
4356 case KVM_CAP_HYPERV_SYNIC2:
4361 case KVM_CAP_HYPERV_SYNIC:
4362 if (!irqchip_in_kernel(vcpu->kvm))
4364 return kvm_hv_activate_synic(vcpu, cap->cap ==
4365 KVM_CAP_HYPERV_SYNIC2);
4366 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4367 if (!kvm_x86_ops.nested_ops->enable_evmcs)
4369 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
4371 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4372 if (copy_to_user(user_ptr, &vmcs_version,
4373 sizeof(vmcs_version)))
4377 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4378 if (!kvm_x86_ops.enable_direct_tlbflush)
4381 return kvm_x86_ops.enable_direct_tlbflush(vcpu);
4388 long kvm_arch_vcpu_ioctl(struct file *filp,
4389 unsigned int ioctl, unsigned long arg)
4391 struct kvm_vcpu *vcpu = filp->private_data;
4392 void __user *argp = (void __user *)arg;
4395 struct kvm_lapic_state *lapic;
4396 struct kvm_xsave *xsave;
4397 struct kvm_xcrs *xcrs;
4405 case KVM_GET_LAPIC: {
4407 if (!lapic_in_kernel(vcpu))
4409 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4410 GFP_KERNEL_ACCOUNT);
4415 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4419 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4424 case KVM_SET_LAPIC: {
4426 if (!lapic_in_kernel(vcpu))
4428 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4429 if (IS_ERR(u.lapic)) {
4430 r = PTR_ERR(u.lapic);
4434 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4437 case KVM_INTERRUPT: {
4438 struct kvm_interrupt irq;
4441 if (copy_from_user(&irq, argp, sizeof(irq)))
4443 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4447 r = kvm_vcpu_ioctl_nmi(vcpu);
4451 r = kvm_vcpu_ioctl_smi(vcpu);
4454 case KVM_SET_CPUID: {
4455 struct kvm_cpuid __user *cpuid_arg = argp;
4456 struct kvm_cpuid cpuid;
4459 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4461 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4464 case KVM_SET_CPUID2: {
4465 struct kvm_cpuid2 __user *cpuid_arg = argp;
4466 struct kvm_cpuid2 cpuid;
4469 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4471 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4472 cpuid_arg->entries);
4475 case KVM_GET_CPUID2: {
4476 struct kvm_cpuid2 __user *cpuid_arg = argp;
4477 struct kvm_cpuid2 cpuid;
4480 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4482 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4483 cpuid_arg->entries);
4487 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4492 case KVM_GET_MSRS: {
4493 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4494 r = msr_io(vcpu, argp, do_get_msr, 1);
4495 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4498 case KVM_SET_MSRS: {
4499 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4500 r = msr_io(vcpu, argp, do_set_msr, 0);
4501 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4504 case KVM_TPR_ACCESS_REPORTING: {
4505 struct kvm_tpr_access_ctl tac;
4508 if (copy_from_user(&tac, argp, sizeof(tac)))
4510 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4514 if (copy_to_user(argp, &tac, sizeof(tac)))
4519 case KVM_SET_VAPIC_ADDR: {
4520 struct kvm_vapic_addr va;
4524 if (!lapic_in_kernel(vcpu))
4527 if (copy_from_user(&va, argp, sizeof(va)))
4529 idx = srcu_read_lock(&vcpu->kvm->srcu);
4530 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4531 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4534 case KVM_X86_SETUP_MCE: {
4538 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4540 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4543 case KVM_X86_SET_MCE: {
4544 struct kvm_x86_mce mce;
4547 if (copy_from_user(&mce, argp, sizeof(mce)))
4549 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4552 case KVM_GET_VCPU_EVENTS: {
4553 struct kvm_vcpu_events events;
4555 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4558 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4563 case KVM_SET_VCPU_EVENTS: {
4564 struct kvm_vcpu_events events;
4567 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4570 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4573 case KVM_GET_DEBUGREGS: {
4574 struct kvm_debugregs dbgregs;
4576 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4579 if (copy_to_user(argp, &dbgregs,
4580 sizeof(struct kvm_debugregs)))
4585 case KVM_SET_DEBUGREGS: {
4586 struct kvm_debugregs dbgregs;
4589 if (copy_from_user(&dbgregs, argp,
4590 sizeof(struct kvm_debugregs)))
4593 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4596 case KVM_GET_XSAVE: {
4597 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4602 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4605 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4610 case KVM_SET_XSAVE: {
4611 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4612 if (IS_ERR(u.xsave)) {
4613 r = PTR_ERR(u.xsave);
4617 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4620 case KVM_GET_XCRS: {
4621 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4626 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4629 if (copy_to_user(argp, u.xcrs,
4630 sizeof(struct kvm_xcrs)))
4635 case KVM_SET_XCRS: {
4636 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4637 if (IS_ERR(u.xcrs)) {
4638 r = PTR_ERR(u.xcrs);
4642 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4645 case KVM_SET_TSC_KHZ: {
4649 user_tsc_khz = (u32)arg;
4651 if (kvm_has_tsc_control &&
4652 user_tsc_khz >= kvm_max_guest_tsc_khz)
4655 if (user_tsc_khz == 0)
4656 user_tsc_khz = tsc_khz;
4658 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4663 case KVM_GET_TSC_KHZ: {
4664 r = vcpu->arch.virtual_tsc_khz;
4667 case KVM_KVMCLOCK_CTRL: {
4668 r = kvm_set_guest_paused(vcpu);
4671 case KVM_ENABLE_CAP: {
4672 struct kvm_enable_cap cap;
4675 if (copy_from_user(&cap, argp, sizeof(cap)))
4677 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4680 case KVM_GET_NESTED_STATE: {
4681 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4685 if (!kvm_x86_ops.nested_ops->get_state)
4688 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4690 if (get_user(user_data_size, &user_kvm_nested_state->size))
4693 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
4698 if (r > user_data_size) {
4699 if (put_user(r, &user_kvm_nested_state->size))
4709 case KVM_SET_NESTED_STATE: {
4710 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4711 struct kvm_nested_state kvm_state;
4715 if (!kvm_x86_ops.nested_ops->set_state)
4719 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4723 if (kvm_state.size < sizeof(kvm_state))
4726 if (kvm_state.flags &
4727 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4728 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
4729 | KVM_STATE_NESTED_GIF_SET))
4732 /* nested_run_pending implies guest_mode. */
4733 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4734 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4737 idx = srcu_read_lock(&vcpu->kvm->srcu);
4738 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
4739 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4742 case KVM_GET_SUPPORTED_HV_CPUID: {
4743 struct kvm_cpuid2 __user *cpuid_arg = argp;
4744 struct kvm_cpuid2 cpuid;
4747 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4750 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4751 cpuid_arg->entries);
4756 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4771 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4773 return VM_FAULT_SIGBUS;
4776 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4780 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4782 ret = kvm_x86_ops.set_tss_addr(kvm, addr);
4786 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4789 return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr);
4792 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4793 unsigned long kvm_nr_mmu_pages)
4795 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4798 mutex_lock(&kvm->slots_lock);
4800 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4801 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4803 mutex_unlock(&kvm->slots_lock);
4807 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4809 return kvm->arch.n_max_mmu_pages;
4812 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4814 struct kvm_pic *pic = kvm->arch.vpic;
4818 switch (chip->chip_id) {
4819 case KVM_IRQCHIP_PIC_MASTER:
4820 memcpy(&chip->chip.pic, &pic->pics[0],
4821 sizeof(struct kvm_pic_state));
4823 case KVM_IRQCHIP_PIC_SLAVE:
4824 memcpy(&chip->chip.pic, &pic->pics[1],
4825 sizeof(struct kvm_pic_state));
4827 case KVM_IRQCHIP_IOAPIC:
4828 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4837 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4839 struct kvm_pic *pic = kvm->arch.vpic;
4843 switch (chip->chip_id) {
4844 case KVM_IRQCHIP_PIC_MASTER:
4845 spin_lock(&pic->lock);
4846 memcpy(&pic->pics[0], &chip->chip.pic,
4847 sizeof(struct kvm_pic_state));
4848 spin_unlock(&pic->lock);
4850 case KVM_IRQCHIP_PIC_SLAVE:
4851 spin_lock(&pic->lock);
4852 memcpy(&pic->pics[1], &chip->chip.pic,
4853 sizeof(struct kvm_pic_state));
4854 spin_unlock(&pic->lock);
4856 case KVM_IRQCHIP_IOAPIC:
4857 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4863 kvm_pic_update_irq(pic);
4867 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4869 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4871 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4873 mutex_lock(&kps->lock);
4874 memcpy(ps, &kps->channels, sizeof(*ps));
4875 mutex_unlock(&kps->lock);
4879 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4882 struct kvm_pit *pit = kvm->arch.vpit;
4884 mutex_lock(&pit->pit_state.lock);
4885 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4886 for (i = 0; i < 3; i++)
4887 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4888 mutex_unlock(&pit->pit_state.lock);
4892 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4894 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4895 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4896 sizeof(ps->channels));
4897 ps->flags = kvm->arch.vpit->pit_state.flags;
4898 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4899 memset(&ps->reserved, 0, sizeof(ps->reserved));
4903 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4907 u32 prev_legacy, cur_legacy;
4908 struct kvm_pit *pit = kvm->arch.vpit;
4910 mutex_lock(&pit->pit_state.lock);
4911 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4912 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4913 if (!prev_legacy && cur_legacy)
4915 memcpy(&pit->pit_state.channels, &ps->channels,
4916 sizeof(pit->pit_state.channels));
4917 pit->pit_state.flags = ps->flags;
4918 for (i = 0; i < 3; i++)
4919 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4921 mutex_unlock(&pit->pit_state.lock);
4925 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4926 struct kvm_reinject_control *control)
4928 struct kvm_pit *pit = kvm->arch.vpit;
4930 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4931 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4932 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4934 mutex_lock(&pit->pit_state.lock);
4935 kvm_pit_set_reinject(pit, control->pit_reinject);
4936 mutex_unlock(&pit->pit_state.lock);
4941 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
4944 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4946 if (kvm_x86_ops.flush_log_dirty)
4947 kvm_x86_ops.flush_log_dirty(kvm);
4950 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4953 if (!irqchip_in_kernel(kvm))
4956 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4957 irq_event->irq, irq_event->level,
4962 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4963 struct kvm_enable_cap *cap)
4971 case KVM_CAP_DISABLE_QUIRKS:
4972 kvm->arch.disabled_quirks = cap->args[0];
4975 case KVM_CAP_SPLIT_IRQCHIP: {
4976 mutex_lock(&kvm->lock);
4978 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4979 goto split_irqchip_unlock;
4981 if (irqchip_in_kernel(kvm))
4982 goto split_irqchip_unlock;
4983 if (kvm->created_vcpus)
4984 goto split_irqchip_unlock;
4985 r = kvm_setup_empty_irq_routing(kvm);
4987 goto split_irqchip_unlock;
4988 /* Pairs with irqchip_in_kernel. */
4990 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4991 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4993 split_irqchip_unlock:
4994 mutex_unlock(&kvm->lock);
4997 case KVM_CAP_X2APIC_API:
4999 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
5002 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
5003 kvm->arch.x2apic_format = true;
5004 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
5005 kvm->arch.x2apic_broadcast_quirk_disabled = true;
5009 case KVM_CAP_X86_DISABLE_EXITS:
5011 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
5014 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
5015 kvm_can_mwait_in_guest())
5016 kvm->arch.mwait_in_guest = true;
5017 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
5018 kvm->arch.hlt_in_guest = true;
5019 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
5020 kvm->arch.pause_in_guest = true;
5021 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
5022 kvm->arch.cstate_in_guest = true;
5025 case KVM_CAP_MSR_PLATFORM_INFO:
5026 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
5029 case KVM_CAP_EXCEPTION_PAYLOAD:
5030 kvm->arch.exception_payload_enabled = cap->args[0];
5040 long kvm_arch_vm_ioctl(struct file *filp,
5041 unsigned int ioctl, unsigned long arg)
5043 struct kvm *kvm = filp->private_data;
5044 void __user *argp = (void __user *)arg;
5047 * This union makes it completely explicit to gcc-3.x
5048 * that these two variables' stack usage should be
5049 * combined, not added together.
5052 struct kvm_pit_state ps;
5053 struct kvm_pit_state2 ps2;
5054 struct kvm_pit_config pit_config;
5058 case KVM_SET_TSS_ADDR:
5059 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
5061 case KVM_SET_IDENTITY_MAP_ADDR: {
5064 mutex_lock(&kvm->lock);
5066 if (kvm->created_vcpus)
5067 goto set_identity_unlock;
5069 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
5070 goto set_identity_unlock;
5071 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
5072 set_identity_unlock:
5073 mutex_unlock(&kvm->lock);
5076 case KVM_SET_NR_MMU_PAGES:
5077 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
5079 case KVM_GET_NR_MMU_PAGES:
5080 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
5082 case KVM_CREATE_IRQCHIP: {
5083 mutex_lock(&kvm->lock);
5086 if (irqchip_in_kernel(kvm))
5087 goto create_irqchip_unlock;
5090 if (kvm->created_vcpus)
5091 goto create_irqchip_unlock;
5093 r = kvm_pic_init(kvm);
5095 goto create_irqchip_unlock;
5097 r = kvm_ioapic_init(kvm);
5099 kvm_pic_destroy(kvm);
5100 goto create_irqchip_unlock;
5103 r = kvm_setup_default_irq_routing(kvm);
5105 kvm_ioapic_destroy(kvm);
5106 kvm_pic_destroy(kvm);
5107 goto create_irqchip_unlock;
5109 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
5111 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
5112 create_irqchip_unlock:
5113 mutex_unlock(&kvm->lock);
5116 case KVM_CREATE_PIT:
5117 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
5119 case KVM_CREATE_PIT2:
5121 if (copy_from_user(&u.pit_config, argp,
5122 sizeof(struct kvm_pit_config)))
5125 mutex_lock(&kvm->lock);
5128 goto create_pit_unlock;
5130 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5134 mutex_unlock(&kvm->lock);
5136 case KVM_GET_IRQCHIP: {
5137 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5138 struct kvm_irqchip *chip;
5140 chip = memdup_user(argp, sizeof(*chip));
5147 if (!irqchip_kernel(kvm))
5148 goto get_irqchip_out;
5149 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5151 goto get_irqchip_out;
5153 if (copy_to_user(argp, chip, sizeof(*chip)))
5154 goto get_irqchip_out;
5160 case KVM_SET_IRQCHIP: {
5161 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5162 struct kvm_irqchip *chip;
5164 chip = memdup_user(argp, sizeof(*chip));
5171 if (!irqchip_kernel(kvm))
5172 goto set_irqchip_out;
5173 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5180 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5183 if (!kvm->arch.vpit)
5185 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5189 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5196 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5198 mutex_lock(&kvm->lock);
5200 if (!kvm->arch.vpit)
5202 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5204 mutex_unlock(&kvm->lock);
5207 case KVM_GET_PIT2: {
5209 if (!kvm->arch.vpit)
5211 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5215 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5220 case KVM_SET_PIT2: {
5222 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5224 mutex_lock(&kvm->lock);
5226 if (!kvm->arch.vpit)
5228 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5230 mutex_unlock(&kvm->lock);
5233 case KVM_REINJECT_CONTROL: {
5234 struct kvm_reinject_control control;
5236 if (copy_from_user(&control, argp, sizeof(control)))
5239 if (!kvm->arch.vpit)
5241 r = kvm_vm_ioctl_reinject(kvm, &control);
5244 case KVM_SET_BOOT_CPU_ID:
5246 mutex_lock(&kvm->lock);
5247 if (kvm->created_vcpus)
5250 kvm->arch.bsp_vcpu_id = arg;
5251 mutex_unlock(&kvm->lock);
5253 case KVM_XEN_HVM_CONFIG: {
5254 struct kvm_xen_hvm_config xhc;
5256 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5261 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5265 case KVM_SET_CLOCK: {
5266 struct kvm_clock_data user_ns;
5270 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5279 * TODO: userspace has to take care of races with VCPU_RUN, so
5280 * kvm_gen_update_masterclock() can be cut down to locked
5281 * pvclock_update_vm_gtod_copy().
5283 kvm_gen_update_masterclock(kvm);
5284 now_ns = get_kvmclock_ns(kvm);
5285 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5286 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5289 case KVM_GET_CLOCK: {
5290 struct kvm_clock_data user_ns;
5293 now_ns = get_kvmclock_ns(kvm);
5294 user_ns.clock = now_ns;
5295 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5296 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5299 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5304 case KVM_MEMORY_ENCRYPT_OP: {
5306 if (kvm_x86_ops.mem_enc_op)
5307 r = kvm_x86_ops.mem_enc_op(kvm, argp);
5310 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5311 struct kvm_enc_region region;
5314 if (copy_from_user(®ion, argp, sizeof(region)))
5318 if (kvm_x86_ops.mem_enc_reg_region)
5319 r = kvm_x86_ops.mem_enc_reg_region(kvm, ®ion);
5322 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5323 struct kvm_enc_region region;
5326 if (copy_from_user(®ion, argp, sizeof(region)))
5330 if (kvm_x86_ops.mem_enc_unreg_region)
5331 r = kvm_x86_ops.mem_enc_unreg_region(kvm, ®ion);
5334 case KVM_HYPERV_EVENTFD: {
5335 struct kvm_hyperv_eventfd hvevfd;
5338 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5340 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5343 case KVM_SET_PMU_EVENT_FILTER:
5344 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5353 static void kvm_init_msr_list(void)
5355 struct x86_pmu_capability x86_pmu;
5359 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5360 "Please update the fixed PMCs in msrs_to_saved_all[]");
5362 perf_get_x86_pmu_capability(&x86_pmu);
5364 num_msrs_to_save = 0;
5365 num_emulated_msrs = 0;
5366 num_msr_based_features = 0;
5368 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5369 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5373 * Even MSRs that are valid in the host may not be exposed
5374 * to the guests in some cases.
5376 switch (msrs_to_save_all[i]) {
5377 case MSR_IA32_BNDCFGS:
5378 if (!kvm_mpx_supported())
5382 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5385 case MSR_IA32_UMWAIT_CONTROL:
5386 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
5389 case MSR_IA32_RTIT_CTL:
5390 case MSR_IA32_RTIT_STATUS:
5391 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5394 case MSR_IA32_RTIT_CR3_MATCH:
5395 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5396 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5399 case MSR_IA32_RTIT_OUTPUT_BASE:
5400 case MSR_IA32_RTIT_OUTPUT_MASK:
5401 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5402 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5403 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5406 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
5407 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5408 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5409 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5412 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5413 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5414 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5417 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5418 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5419 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5426 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5429 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5430 if (!kvm_x86_ops.has_emulated_msr(emulated_msrs_all[i]))
5433 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5436 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5437 struct kvm_msr_entry msr;
5439 msr.index = msr_based_features_all[i];
5440 if (kvm_get_msr_feature(&msr))
5443 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5447 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5455 if (!(lapic_in_kernel(vcpu) &&
5456 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5457 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5468 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5475 if (!(lapic_in_kernel(vcpu) &&
5476 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5478 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5480 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5490 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5491 struct kvm_segment *var, int seg)
5493 kvm_x86_ops.set_segment(vcpu, var, seg);
5496 void kvm_get_segment(struct kvm_vcpu *vcpu,
5497 struct kvm_segment *var, int seg)
5499 kvm_x86_ops.get_segment(vcpu, var, seg);
5502 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5503 struct x86_exception *exception)
5507 BUG_ON(!mmu_is_nested(vcpu));
5509 /* NPT walks are always user-walks */
5510 access |= PFERR_USER_MASK;
5511 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5516 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5517 struct x86_exception *exception)
5519 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5520 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5523 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5524 struct x86_exception *exception)
5526 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5527 access |= PFERR_FETCH_MASK;
5528 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5531 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5532 struct x86_exception *exception)
5534 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5535 access |= PFERR_WRITE_MASK;
5536 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5539 /* uses this to access any guest's mapped memory without checking CPL */
5540 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5541 struct x86_exception *exception)
5543 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5546 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5547 struct kvm_vcpu *vcpu, u32 access,
5548 struct x86_exception *exception)
5551 int r = X86EMUL_CONTINUE;
5554 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5556 unsigned offset = addr & (PAGE_SIZE-1);
5557 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5560 if (gpa == UNMAPPED_GVA)
5561 return X86EMUL_PROPAGATE_FAULT;
5562 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5565 r = X86EMUL_IO_NEEDED;
5577 /* used for instruction fetching */
5578 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5579 gva_t addr, void *val, unsigned int bytes,
5580 struct x86_exception *exception)
5582 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5583 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5587 /* Inline kvm_read_guest_virt_helper for speed. */
5588 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5590 if (unlikely(gpa == UNMAPPED_GVA))
5591 return X86EMUL_PROPAGATE_FAULT;
5593 offset = addr & (PAGE_SIZE-1);
5594 if (WARN_ON(offset + bytes > PAGE_SIZE))
5595 bytes = (unsigned)PAGE_SIZE - offset;
5596 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5598 if (unlikely(ret < 0))
5599 return X86EMUL_IO_NEEDED;
5601 return X86EMUL_CONTINUE;
5604 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5605 gva_t addr, void *val, unsigned int bytes,
5606 struct x86_exception *exception)
5608 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5611 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5612 * is returned, but our callers are not ready for that and they blindly
5613 * call kvm_inject_page_fault. Ensure that they at least do not leak
5614 * uninitialized kernel stack memory into cr2 and error code.
5616 memset(exception, 0, sizeof(*exception));
5617 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5620 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5622 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5623 gva_t addr, void *val, unsigned int bytes,
5624 struct x86_exception *exception, bool system)
5626 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5629 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5630 access |= PFERR_USER_MASK;
5632 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5635 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5636 unsigned long addr, void *val, unsigned int bytes)
5638 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5639 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5641 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5644 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5645 struct kvm_vcpu *vcpu, u32 access,
5646 struct x86_exception *exception)
5649 int r = X86EMUL_CONTINUE;
5652 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5655 unsigned offset = addr & (PAGE_SIZE-1);
5656 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5659 if (gpa == UNMAPPED_GVA)
5660 return X86EMUL_PROPAGATE_FAULT;
5661 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5663 r = X86EMUL_IO_NEEDED;
5675 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5676 unsigned int bytes, struct x86_exception *exception,
5679 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5680 u32 access = PFERR_WRITE_MASK;
5682 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5683 access |= PFERR_USER_MASK;
5685 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5689 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5690 unsigned int bytes, struct x86_exception *exception)
5692 /* kvm_write_guest_virt_system can pull in tons of pages. */
5693 vcpu->arch.l1tf_flush_l1d = true;
5695 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5696 PFERR_WRITE_MASK, exception);
5698 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5700 int handle_ud(struct kvm_vcpu *vcpu)
5702 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
5703 int emul_type = EMULTYPE_TRAP_UD;
5704 char sig[5]; /* ud2; .ascii "kvm" */
5705 struct x86_exception e;
5707 if (force_emulation_prefix &&
5708 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5709 sig, sizeof(sig), &e) == 0 &&
5710 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
5711 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5712 emul_type = EMULTYPE_TRAP_UD_FORCED;
5715 return kvm_emulate_instruction(vcpu, emul_type);
5717 EXPORT_SYMBOL_GPL(handle_ud);
5719 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5720 gpa_t gpa, bool write)
5722 /* For APIC access vmexit */
5723 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5726 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5727 trace_vcpu_match_mmio(gva, gpa, write, true);
5734 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5735 gpa_t *gpa, struct x86_exception *exception,
5738 u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5739 | (write ? PFERR_WRITE_MASK : 0);
5742 * currently PKRU is only applied to ept enabled guest so
5743 * there is no pkey in EPT page table for L1 guest or EPT
5744 * shadow page table for L2 guest.
5746 if (vcpu_match_mmio_gva(vcpu, gva)
5747 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5748 vcpu->arch.mmio_access, 0, access)) {
5749 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5750 (gva & (PAGE_SIZE - 1));
5751 trace_vcpu_match_mmio(gva, *gpa, write, false);
5755 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5757 if (*gpa == UNMAPPED_GVA)
5760 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5763 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5764 const void *val, int bytes)
5768 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5771 kvm_page_track_write(vcpu, gpa, val, bytes);
5775 struct read_write_emulator_ops {
5776 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5778 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5779 void *val, int bytes);
5780 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5781 int bytes, void *val);
5782 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5783 void *val, int bytes);
5787 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5789 if (vcpu->mmio_read_completed) {
5790 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5791 vcpu->mmio_fragments[0].gpa, val);
5792 vcpu->mmio_read_completed = 0;
5799 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5800 void *val, int bytes)
5802 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5805 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5806 void *val, int bytes)
5808 return emulator_write_phys(vcpu, gpa, val, bytes);
5811 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5813 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5814 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5817 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5818 void *val, int bytes)
5820 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5821 return X86EMUL_IO_NEEDED;
5824 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5825 void *val, int bytes)
5827 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5829 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5830 return X86EMUL_CONTINUE;
5833 static const struct read_write_emulator_ops read_emultor = {
5834 .read_write_prepare = read_prepare,
5835 .read_write_emulate = read_emulate,
5836 .read_write_mmio = vcpu_mmio_read,
5837 .read_write_exit_mmio = read_exit_mmio,
5840 static const struct read_write_emulator_ops write_emultor = {
5841 .read_write_emulate = write_emulate,
5842 .read_write_mmio = write_mmio,
5843 .read_write_exit_mmio = write_exit_mmio,
5847 static int emulator_read_write_onepage(unsigned long addr, void *val,
5849 struct x86_exception *exception,
5850 struct kvm_vcpu *vcpu,
5851 const struct read_write_emulator_ops *ops)
5855 bool write = ops->write;
5856 struct kvm_mmio_fragment *frag;
5857 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
5860 * If the exit was due to a NPF we may already have a GPA.
5861 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5862 * Note, this cannot be used on string operations since string
5863 * operation using rep will only have the initial GPA from the NPF
5866 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
5867 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
5868 gpa = ctxt->gpa_val;
5869 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5871 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5873 return X86EMUL_PROPAGATE_FAULT;
5876 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5877 return X86EMUL_CONTINUE;
5880 * Is this MMIO handled locally?
5882 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5883 if (handled == bytes)
5884 return X86EMUL_CONTINUE;
5890 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5891 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5895 return X86EMUL_CONTINUE;
5898 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5900 void *val, unsigned int bytes,
5901 struct x86_exception *exception,
5902 const struct read_write_emulator_ops *ops)
5904 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5908 if (ops->read_write_prepare &&
5909 ops->read_write_prepare(vcpu, val, bytes))
5910 return X86EMUL_CONTINUE;
5912 vcpu->mmio_nr_fragments = 0;
5914 /* Crossing a page boundary? */
5915 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5918 now = -addr & ~PAGE_MASK;
5919 rc = emulator_read_write_onepage(addr, val, now, exception,
5922 if (rc != X86EMUL_CONTINUE)
5925 if (ctxt->mode != X86EMUL_MODE_PROT64)
5931 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5933 if (rc != X86EMUL_CONTINUE)
5936 if (!vcpu->mmio_nr_fragments)
5939 gpa = vcpu->mmio_fragments[0].gpa;
5941 vcpu->mmio_needed = 1;
5942 vcpu->mmio_cur_fragment = 0;
5944 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5945 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5946 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5947 vcpu->run->mmio.phys_addr = gpa;
5949 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5952 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5956 struct x86_exception *exception)
5958 return emulator_read_write(ctxt, addr, val, bytes,
5959 exception, &read_emultor);
5962 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5966 struct x86_exception *exception)
5968 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5969 exception, &write_emultor);
5972 #define CMPXCHG_TYPE(t, ptr, old, new) \
5973 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5975 #ifdef CONFIG_X86_64
5976 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5978 # define CMPXCHG64(ptr, old, new) \
5979 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5982 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5987 struct x86_exception *exception)
5989 struct kvm_host_map map;
5990 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5996 /* guests cmpxchg8b have to be emulated atomically */
5997 if (bytes > 8 || (bytes & (bytes - 1)))
6000 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
6002 if (gpa == UNMAPPED_GVA ||
6003 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6007 * Emulate the atomic as a straight write to avoid #AC if SLD is
6008 * enabled in the host and the access splits a cache line.
6010 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
6011 page_line_mask = ~(cache_line_size() - 1);
6013 page_line_mask = PAGE_MASK;
6015 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
6018 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
6021 kaddr = map.hva + offset_in_page(gpa);
6025 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
6028 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
6031 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
6034 exchanged = CMPXCHG64(kaddr, old, new);
6040 kvm_vcpu_unmap(vcpu, &map, true);
6043 return X86EMUL_CMPXCHG_FAILED;
6045 kvm_page_track_write(vcpu, gpa, new, bytes);
6047 return X86EMUL_CONTINUE;
6050 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
6052 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
6055 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
6059 for (i = 0; i < vcpu->arch.pio.count; i++) {
6060 if (vcpu->arch.pio.in)
6061 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
6062 vcpu->arch.pio.size, pd);
6064 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
6065 vcpu->arch.pio.port, vcpu->arch.pio.size,
6069 pd += vcpu->arch.pio.size;
6074 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
6075 unsigned short port, void *val,
6076 unsigned int count, bool in)
6078 vcpu->arch.pio.port = port;
6079 vcpu->arch.pio.in = in;
6080 vcpu->arch.pio.count = count;
6081 vcpu->arch.pio.size = size;
6083 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
6084 vcpu->arch.pio.count = 0;
6088 vcpu->run->exit_reason = KVM_EXIT_IO;
6089 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
6090 vcpu->run->io.size = size;
6091 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
6092 vcpu->run->io.count = count;
6093 vcpu->run->io.port = port;
6098 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
6099 unsigned short port, void *val, unsigned int count)
6103 if (vcpu->arch.pio.count)
6106 memset(vcpu->arch.pio_data, 0, size * count);
6108 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
6111 memcpy(val, vcpu->arch.pio_data, size * count);
6112 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
6113 vcpu->arch.pio.count = 0;
6120 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
6121 int size, unsigned short port, void *val,
6124 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
6128 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
6129 unsigned short port, const void *val,
6132 memcpy(vcpu->arch.pio_data, val, size * count);
6133 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6134 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6137 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
6138 int size, unsigned short port,
6139 const void *val, unsigned int count)
6141 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
6144 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6146 return kvm_x86_ops.get_segment_base(vcpu, seg);
6149 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6151 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6154 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6156 if (!need_emulate_wbinvd(vcpu))
6157 return X86EMUL_CONTINUE;
6159 if (kvm_x86_ops.has_wbinvd_exit()) {
6160 int cpu = get_cpu();
6162 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6163 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6164 wbinvd_ipi, NULL, 1);
6166 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6169 return X86EMUL_CONTINUE;
6172 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6174 kvm_emulate_wbinvd_noskip(vcpu);
6175 return kvm_skip_emulated_instruction(vcpu);
6177 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6181 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6183 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6186 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6187 unsigned long *dest)
6189 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6192 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6193 unsigned long value)
6196 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6199 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6201 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6204 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6206 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6207 unsigned long value;
6211 value = kvm_read_cr0(vcpu);
6214 value = vcpu->arch.cr2;
6217 value = kvm_read_cr3(vcpu);
6220 value = kvm_read_cr4(vcpu);
6223 value = kvm_get_cr8(vcpu);
6226 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6233 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6235 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6240 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6243 vcpu->arch.cr2 = val;
6246 res = kvm_set_cr3(vcpu, val);
6249 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6252 res = kvm_set_cr8(vcpu, val);
6255 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6262 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6264 return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt));
6267 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6269 kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt);
6272 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6274 kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt);
6277 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6279 kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt);
6282 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6284 kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt);
6287 static unsigned long emulator_get_cached_segment_base(
6288 struct x86_emulate_ctxt *ctxt, int seg)
6290 return get_segment_base(emul_to_vcpu(ctxt), seg);
6293 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6294 struct desc_struct *desc, u32 *base3,
6297 struct kvm_segment var;
6299 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6300 *selector = var.selector;
6303 memset(desc, 0, sizeof(*desc));
6311 set_desc_limit(desc, var.limit);
6312 set_desc_base(desc, (unsigned long)var.base);
6313 #ifdef CONFIG_X86_64
6315 *base3 = var.base >> 32;
6317 desc->type = var.type;
6319 desc->dpl = var.dpl;
6320 desc->p = var.present;
6321 desc->avl = var.avl;
6329 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6330 struct desc_struct *desc, u32 base3,
6333 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6334 struct kvm_segment var;
6336 var.selector = selector;
6337 var.base = get_desc_base(desc);
6338 #ifdef CONFIG_X86_64
6339 var.base |= ((u64)base3) << 32;
6341 var.limit = get_desc_limit(desc);
6343 var.limit = (var.limit << 12) | 0xfff;
6344 var.type = desc->type;
6345 var.dpl = desc->dpl;
6350 var.avl = desc->avl;
6351 var.present = desc->p;
6352 var.unusable = !var.present;
6355 kvm_set_segment(vcpu, &var, seg);
6359 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6360 u32 msr_index, u64 *pdata)
6362 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6365 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6366 u32 msr_index, u64 data)
6368 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6371 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6373 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6375 return vcpu->arch.smbase;
6378 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6380 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6382 vcpu->arch.smbase = smbase;
6385 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6388 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6391 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6392 u32 pmc, u64 *pdata)
6394 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6397 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6399 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6402 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6403 struct x86_instruction_info *info,
6404 enum x86_intercept_stage stage)
6406 return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage,
6410 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6411 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6414 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6417 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6419 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6422 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6424 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6427 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6429 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6432 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6434 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6437 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6439 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6442 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6444 kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked);
6447 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6449 return emul_to_vcpu(ctxt)->arch.hflags;
6452 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6454 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6457 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6458 const char *smstate)
6460 return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6463 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6465 kvm_smm_changed(emul_to_vcpu(ctxt));
6468 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6470 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6473 static const struct x86_emulate_ops emulate_ops = {
6474 .read_gpr = emulator_read_gpr,
6475 .write_gpr = emulator_write_gpr,
6476 .read_std = emulator_read_std,
6477 .write_std = emulator_write_std,
6478 .read_phys = kvm_read_guest_phys_system,
6479 .fetch = kvm_fetch_guest_virt,
6480 .read_emulated = emulator_read_emulated,
6481 .write_emulated = emulator_write_emulated,
6482 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6483 .invlpg = emulator_invlpg,
6484 .pio_in_emulated = emulator_pio_in_emulated,
6485 .pio_out_emulated = emulator_pio_out_emulated,
6486 .get_segment = emulator_get_segment,
6487 .set_segment = emulator_set_segment,
6488 .get_cached_segment_base = emulator_get_cached_segment_base,
6489 .get_gdt = emulator_get_gdt,
6490 .get_idt = emulator_get_idt,
6491 .set_gdt = emulator_set_gdt,
6492 .set_idt = emulator_set_idt,
6493 .get_cr = emulator_get_cr,
6494 .set_cr = emulator_set_cr,
6495 .cpl = emulator_get_cpl,
6496 .get_dr = emulator_get_dr,
6497 .set_dr = emulator_set_dr,
6498 .get_smbase = emulator_get_smbase,
6499 .set_smbase = emulator_set_smbase,
6500 .set_msr = emulator_set_msr,
6501 .get_msr = emulator_get_msr,
6502 .check_pmc = emulator_check_pmc,
6503 .read_pmc = emulator_read_pmc,
6504 .halt = emulator_halt,
6505 .wbinvd = emulator_wbinvd,
6506 .fix_hypercall = emulator_fix_hypercall,
6507 .intercept = emulator_intercept,
6508 .get_cpuid = emulator_get_cpuid,
6509 .guest_has_long_mode = emulator_guest_has_long_mode,
6510 .guest_has_movbe = emulator_guest_has_movbe,
6511 .guest_has_fxsr = emulator_guest_has_fxsr,
6512 .set_nmi_mask = emulator_set_nmi_mask,
6513 .get_hflags = emulator_get_hflags,
6514 .set_hflags = emulator_set_hflags,
6515 .pre_leave_smm = emulator_pre_leave_smm,
6516 .post_leave_smm = emulator_post_leave_smm,
6517 .set_xcr = emulator_set_xcr,
6520 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6522 u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
6524 * an sti; sti; sequence only disable interrupts for the first
6525 * instruction. So, if the last instruction, be it emulated or
6526 * not, left the system with the INT_STI flag enabled, it
6527 * means that the last instruction is an sti. We should not
6528 * leave the flag on in this case. The same goes for mov ss
6530 if (int_shadow & mask)
6532 if (unlikely(int_shadow || mask)) {
6533 kvm_x86_ops.set_interrupt_shadow(vcpu, mask);
6535 kvm_make_request(KVM_REQ_EVENT, vcpu);
6539 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6541 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6542 if (ctxt->exception.vector == PF_VECTOR)
6543 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
6545 if (ctxt->exception.error_code_valid)
6546 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6547 ctxt->exception.error_code);
6549 kvm_queue_exception(vcpu, ctxt->exception.vector);
6553 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6555 struct x86_emulate_ctxt *ctxt;
6557 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6559 pr_err("kvm: failed to allocate vcpu's emulator\n");
6564 ctxt->ops = &emulate_ops;
6565 vcpu->arch.emulate_ctxt = ctxt;
6570 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6572 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6575 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6577 ctxt->gpa_available = false;
6578 ctxt->eflags = kvm_get_rflags(vcpu);
6579 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6581 ctxt->eip = kvm_rip_read(vcpu);
6582 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6583 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6584 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6585 cs_db ? X86EMUL_MODE_PROT32 :
6586 X86EMUL_MODE_PROT16;
6587 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6588 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6589 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6591 init_decode_cache(ctxt);
6592 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6595 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6597 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6600 init_emulate_ctxt(vcpu);
6604 ctxt->_eip = ctxt->eip + inc_eip;
6605 ret = emulate_int_real(ctxt, irq);
6607 if (ret != X86EMUL_CONTINUE) {
6608 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6610 ctxt->eip = ctxt->_eip;
6611 kvm_rip_write(vcpu, ctxt->eip);
6612 kvm_set_rflags(vcpu, ctxt->eflags);
6615 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6617 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6619 ++vcpu->stat.insn_emulation_fail;
6620 trace_kvm_emulate_insn_failed(vcpu);
6622 if (emulation_type & EMULTYPE_VMWARE_GP) {
6623 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6627 if (emulation_type & EMULTYPE_SKIP) {
6628 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6629 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6630 vcpu->run->internal.ndata = 0;
6634 kvm_queue_exception(vcpu, UD_VECTOR);
6636 if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) {
6637 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6638 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6639 vcpu->run->internal.ndata = 0;
6646 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6647 bool write_fault_to_shadow_pgtable,
6650 gpa_t gpa = cr2_or_gpa;
6653 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6656 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6657 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6660 if (!vcpu->arch.mmu->direct_map) {
6662 * Write permission should be allowed since only
6663 * write access need to be emulated.
6665 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6668 * If the mapping is invalid in guest, let cpu retry
6669 * it to generate fault.
6671 if (gpa == UNMAPPED_GVA)
6676 * Do not retry the unhandleable instruction if it faults on the
6677 * readonly host memory, otherwise it will goto a infinite loop:
6678 * retry instruction -> write #PF -> emulation fail -> retry
6679 * instruction -> ...
6681 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6684 * If the instruction failed on the error pfn, it can not be fixed,
6685 * report the error to userspace.
6687 if (is_error_noslot_pfn(pfn))
6690 kvm_release_pfn_clean(pfn);
6692 /* The instructions are well-emulated on direct mmu. */
6693 if (vcpu->arch.mmu->direct_map) {
6694 unsigned int indirect_shadow_pages;
6696 spin_lock(&vcpu->kvm->mmu_lock);
6697 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6698 spin_unlock(&vcpu->kvm->mmu_lock);
6700 if (indirect_shadow_pages)
6701 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6707 * if emulation was due to access to shadowed page table
6708 * and it failed try to unshadow page and re-enter the
6709 * guest to let CPU execute the instruction.
6711 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6714 * If the access faults on its page table, it can not
6715 * be fixed by unprotecting shadow page and it should
6716 * be reported to userspace.
6718 return !write_fault_to_shadow_pgtable;
6721 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6722 gpa_t cr2_or_gpa, int emulation_type)
6724 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6725 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
6727 last_retry_eip = vcpu->arch.last_retry_eip;
6728 last_retry_addr = vcpu->arch.last_retry_addr;
6731 * If the emulation is caused by #PF and it is non-page_table
6732 * writing instruction, it means the VM-EXIT is caused by shadow
6733 * page protected, we can zap the shadow page and retry this
6734 * instruction directly.
6736 * Note: if the guest uses a non-page-table modifying instruction
6737 * on the PDE that points to the instruction, then we will unmap
6738 * the instruction and go to an infinite loop. So, we cache the
6739 * last retried eip and the last fault address, if we meet the eip
6740 * and the address again, we can break out of the potential infinite
6743 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6745 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6748 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6749 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6752 if (x86_page_table_writing_insn(ctxt))
6755 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
6758 vcpu->arch.last_retry_eip = ctxt->eip;
6759 vcpu->arch.last_retry_addr = cr2_or_gpa;
6761 if (!vcpu->arch.mmu->direct_map)
6762 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6764 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6769 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6770 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6772 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6774 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6775 /* This is a good place to trace that we are exiting SMM. */
6776 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6778 /* Process a latched INIT or SMI, if any. */
6779 kvm_make_request(KVM_REQ_EVENT, vcpu);
6782 kvm_mmu_reset_context(vcpu);
6785 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6794 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6795 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6800 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6802 struct kvm_run *kvm_run = vcpu->run;
6804 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6805 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6806 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6807 kvm_run->debug.arch.exception = DB_VECTOR;
6808 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6811 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6815 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6817 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
6820 r = kvm_x86_ops.skip_emulated_instruction(vcpu);
6825 * rflags is the old, "raw" value of the flags. The new value has
6826 * not been saved yet.
6828 * This is correct even for TF set by the guest, because "the
6829 * processor will not generate this exception after the instruction
6830 * that sets the TF flag".
6832 if (unlikely(rflags & X86_EFLAGS_TF))
6833 r = kvm_vcpu_do_singlestep(vcpu);
6836 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6838 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6840 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6841 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6842 struct kvm_run *kvm_run = vcpu->run;
6843 unsigned long eip = kvm_get_linear_rip(vcpu);
6844 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6845 vcpu->arch.guest_debug_dr7,
6849 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6850 kvm_run->debug.arch.pc = eip;
6851 kvm_run->debug.arch.exception = DB_VECTOR;
6852 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6858 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6859 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6860 unsigned long eip = kvm_get_linear_rip(vcpu);
6861 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6866 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
6875 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6877 switch (ctxt->opcode_len) {
6884 case 0xe6: /* OUT */
6888 case 0x6c: /* INS */
6890 case 0x6e: /* OUTS */
6897 case 0x33: /* RDPMC */
6906 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6907 int emulation_type, void *insn, int insn_len)
6910 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6911 bool writeback = true;
6912 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6914 vcpu->arch.l1tf_flush_l1d = true;
6917 * Clear write_fault_to_shadow_pgtable here to ensure it is
6920 vcpu->arch.write_fault_to_shadow_pgtable = false;
6921 kvm_clear_exception_queue(vcpu);
6923 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6924 init_emulate_ctxt(vcpu);
6927 * We will reenter on the same instruction since
6928 * we do not set complete_userspace_io. This does not
6929 * handle watchpoints yet, those would be handled in
6932 if (!(emulation_type & EMULTYPE_SKIP) &&
6933 kvm_vcpu_check_breakpoint(vcpu, &r))
6936 ctxt->interruptibility = 0;
6937 ctxt->have_exception = false;
6938 ctxt->exception.vector = -1;
6939 ctxt->perm_ok = false;
6941 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6943 r = x86_decode_insn(ctxt, insn, insn_len);
6945 trace_kvm_emulate_insn_start(vcpu);
6946 ++vcpu->stat.insn_emulation;
6947 if (r != EMULATION_OK) {
6948 if ((emulation_type & EMULTYPE_TRAP_UD) ||
6949 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6950 kvm_queue_exception(vcpu, UD_VECTOR);
6953 if (reexecute_instruction(vcpu, cr2_or_gpa,
6957 if (ctxt->have_exception) {
6959 * #UD should result in just EMULATION_FAILED, and trap-like
6960 * exception should not be encountered during decode.
6962 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6963 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6964 inject_emulated_exception(vcpu);
6967 return handle_emulation_failure(vcpu, emulation_type);
6971 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6972 !is_vmware_backdoor_opcode(ctxt)) {
6973 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6978 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6979 * for kvm_skip_emulated_instruction(). The caller is responsible for
6980 * updating interruptibility state and injecting single-step #DBs.
6982 if (emulation_type & EMULTYPE_SKIP) {
6983 kvm_rip_write(vcpu, ctxt->_eip);
6984 if (ctxt->eflags & X86_EFLAGS_RF)
6985 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6989 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
6992 /* this is needed for vmware backdoor interface to work since it
6993 changes registers values during IO operation */
6994 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6995 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6996 emulator_invalidate_register_cache(ctxt);
7000 if (emulation_type & EMULTYPE_PF) {
7001 /* Save the faulting GPA (cr2) in the address field */
7002 ctxt->exception.address = cr2_or_gpa;
7004 /* With shadow page tables, cr2 contains a GVA or nGPA. */
7005 if (vcpu->arch.mmu->direct_map) {
7006 ctxt->gpa_available = true;
7007 ctxt->gpa_val = cr2_or_gpa;
7010 /* Sanitize the address out of an abundance of paranoia. */
7011 ctxt->exception.address = 0;
7014 r = x86_emulate_insn(ctxt);
7016 if (r == EMULATION_INTERCEPTED)
7019 if (r == EMULATION_FAILED) {
7020 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
7024 return handle_emulation_failure(vcpu, emulation_type);
7027 if (ctxt->have_exception) {
7029 if (inject_emulated_exception(vcpu))
7031 } else if (vcpu->arch.pio.count) {
7032 if (!vcpu->arch.pio.in) {
7033 /* FIXME: return into emulator if single-stepping. */
7034 vcpu->arch.pio.count = 0;
7037 vcpu->arch.complete_userspace_io = complete_emulated_pio;
7040 } else if (vcpu->mmio_needed) {
7041 ++vcpu->stat.mmio_exits;
7043 if (!vcpu->mmio_is_write)
7046 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7047 } else if (r == EMULATION_RESTART)
7053 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7054 toggle_interruptibility(vcpu, ctxt->interruptibility);
7055 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7056 if (!ctxt->have_exception ||
7057 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
7058 kvm_rip_write(vcpu, ctxt->eip);
7059 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
7060 r = kvm_vcpu_do_singlestep(vcpu);
7061 if (kvm_x86_ops.update_emulated_instruction)
7062 kvm_x86_ops.update_emulated_instruction(vcpu);
7063 __kvm_set_rflags(vcpu, ctxt->eflags);
7067 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
7068 * do nothing, and it will be requested again as soon as
7069 * the shadow expires. But we still need to check here,
7070 * because POPF has no interrupt shadow.
7072 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
7073 kvm_make_request(KVM_REQ_EVENT, vcpu);
7075 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
7080 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
7082 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
7084 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
7086 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
7087 void *insn, int insn_len)
7089 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
7091 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
7093 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
7095 vcpu->arch.pio.count = 0;
7099 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
7101 vcpu->arch.pio.count = 0;
7103 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
7106 return kvm_skip_emulated_instruction(vcpu);
7109 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
7110 unsigned short port)
7112 unsigned long val = kvm_rax_read(vcpu);
7113 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
7119 * Workaround userspace that relies on old KVM behavior of %rip being
7120 * incremented prior to exiting to userspace to handle "OUT 0x7e".
7123 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
7124 vcpu->arch.complete_userspace_io =
7125 complete_fast_pio_out_port_0x7e;
7126 kvm_skip_emulated_instruction(vcpu);
7128 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7129 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
7134 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
7138 /* We should only ever be called with arch.pio.count equal to 1 */
7139 BUG_ON(vcpu->arch.pio.count != 1);
7141 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
7142 vcpu->arch.pio.count = 0;
7146 /* For size less than 4 we merge, else we zero extend */
7147 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7150 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7151 * the copy and tracing
7153 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7154 kvm_rax_write(vcpu, val);
7156 return kvm_skip_emulated_instruction(vcpu);
7159 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7160 unsigned short port)
7165 /* For size less than 4 we merge, else we zero extend */
7166 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7168 ret = emulator_pio_in(vcpu, size, port, &val, 1);
7170 kvm_rax_write(vcpu, val);
7174 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7175 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7180 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7185 ret = kvm_fast_pio_in(vcpu, size, port);
7187 ret = kvm_fast_pio_out(vcpu, size, port);
7188 return ret && kvm_skip_emulated_instruction(vcpu);
7190 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7192 static int kvmclock_cpu_down_prep(unsigned int cpu)
7194 __this_cpu_write(cpu_tsc_khz, 0);
7198 static void tsc_khz_changed(void *data)
7200 struct cpufreq_freqs *freq = data;
7201 unsigned long khz = 0;
7205 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7206 khz = cpufreq_quick_get(raw_smp_processor_id());
7209 __this_cpu_write(cpu_tsc_khz, khz);
7212 #ifdef CONFIG_X86_64
7213 static void kvm_hyperv_tsc_notifier(void)
7216 struct kvm_vcpu *vcpu;
7219 mutex_lock(&kvm_lock);
7220 list_for_each_entry(kvm, &vm_list, vm_list)
7221 kvm_make_mclock_inprogress_request(kvm);
7223 hyperv_stop_tsc_emulation();
7225 /* TSC frequency always matches when on Hyper-V */
7226 for_each_present_cpu(cpu)
7227 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7228 kvm_max_guest_tsc_khz = tsc_khz;
7230 list_for_each_entry(kvm, &vm_list, vm_list) {
7231 struct kvm_arch *ka = &kvm->arch;
7233 spin_lock(&ka->pvclock_gtod_sync_lock);
7235 pvclock_update_vm_gtod_copy(kvm);
7237 kvm_for_each_vcpu(cpu, vcpu, kvm)
7238 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7240 kvm_for_each_vcpu(cpu, vcpu, kvm)
7241 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7243 spin_unlock(&ka->pvclock_gtod_sync_lock);
7245 mutex_unlock(&kvm_lock);
7249 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7252 struct kvm_vcpu *vcpu;
7253 int i, send_ipi = 0;
7256 * We allow guests to temporarily run on slowing clocks,
7257 * provided we notify them after, or to run on accelerating
7258 * clocks, provided we notify them before. Thus time never
7261 * However, we have a problem. We can't atomically update
7262 * the frequency of a given CPU from this function; it is
7263 * merely a notifier, which can be called from any CPU.
7264 * Changing the TSC frequency at arbitrary points in time
7265 * requires a recomputation of local variables related to
7266 * the TSC for each VCPU. We must flag these local variables
7267 * to be updated and be sure the update takes place with the
7268 * new frequency before any guests proceed.
7270 * Unfortunately, the combination of hotplug CPU and frequency
7271 * change creates an intractable locking scenario; the order
7272 * of when these callouts happen is undefined with respect to
7273 * CPU hotplug, and they can race with each other. As such,
7274 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7275 * undefined; you can actually have a CPU frequency change take
7276 * place in between the computation of X and the setting of the
7277 * variable. To protect against this problem, all updates of
7278 * the per_cpu tsc_khz variable are done in an interrupt
7279 * protected IPI, and all callers wishing to update the value
7280 * must wait for a synchronous IPI to complete (which is trivial
7281 * if the caller is on the CPU already). This establishes the
7282 * necessary total order on variable updates.
7284 * Note that because a guest time update may take place
7285 * anytime after the setting of the VCPU's request bit, the
7286 * correct TSC value must be set before the request. However,
7287 * to ensure the update actually makes it to any guest which
7288 * starts running in hardware virtualization between the set
7289 * and the acquisition of the spinlock, we must also ping the
7290 * CPU after setting the request bit.
7294 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7296 mutex_lock(&kvm_lock);
7297 list_for_each_entry(kvm, &vm_list, vm_list) {
7298 kvm_for_each_vcpu(i, vcpu, kvm) {
7299 if (vcpu->cpu != cpu)
7301 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7302 if (vcpu->cpu != raw_smp_processor_id())
7306 mutex_unlock(&kvm_lock);
7308 if (freq->old < freq->new && send_ipi) {
7310 * We upscale the frequency. Must make the guest
7311 * doesn't see old kvmclock values while running with
7312 * the new frequency, otherwise we risk the guest sees
7313 * time go backwards.
7315 * In case we update the frequency for another cpu
7316 * (which might be in guest context) send an interrupt
7317 * to kick the cpu out of guest context. Next time
7318 * guest context is entered kvmclock will be updated,
7319 * so the guest will not see stale values.
7321 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7325 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7328 struct cpufreq_freqs *freq = data;
7331 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7333 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7336 for_each_cpu(cpu, freq->policy->cpus)
7337 __kvmclock_cpufreq_notifier(freq, cpu);
7342 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7343 .notifier_call = kvmclock_cpufreq_notifier
7346 static int kvmclock_cpu_online(unsigned int cpu)
7348 tsc_khz_changed(NULL);
7352 static void kvm_timer_init(void)
7354 max_tsc_khz = tsc_khz;
7356 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7357 #ifdef CONFIG_CPU_FREQ
7358 struct cpufreq_policy *policy;
7362 policy = cpufreq_cpu_get(cpu);
7364 if (policy->cpuinfo.max_freq)
7365 max_tsc_khz = policy->cpuinfo.max_freq;
7366 cpufreq_cpu_put(policy);
7370 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7371 CPUFREQ_TRANSITION_NOTIFIER);
7374 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7375 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7378 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7379 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7381 int kvm_is_in_guest(void)
7383 return __this_cpu_read(current_vcpu) != NULL;
7386 static int kvm_is_user_mode(void)
7390 if (__this_cpu_read(current_vcpu))
7391 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu));
7393 return user_mode != 0;
7396 static unsigned long kvm_get_guest_ip(void)
7398 unsigned long ip = 0;
7400 if (__this_cpu_read(current_vcpu))
7401 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7406 static void kvm_handle_intel_pt_intr(void)
7408 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7410 kvm_make_request(KVM_REQ_PMI, vcpu);
7411 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7412 (unsigned long *)&vcpu->arch.pmu.global_status);
7415 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7416 .is_in_guest = kvm_is_in_guest,
7417 .is_user_mode = kvm_is_user_mode,
7418 .get_guest_ip = kvm_get_guest_ip,
7419 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7422 #ifdef CONFIG_X86_64
7423 static void pvclock_gtod_update_fn(struct work_struct *work)
7427 struct kvm_vcpu *vcpu;
7430 mutex_lock(&kvm_lock);
7431 list_for_each_entry(kvm, &vm_list, vm_list)
7432 kvm_for_each_vcpu(i, vcpu, kvm)
7433 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7434 atomic_set(&kvm_guest_has_master_clock, 0);
7435 mutex_unlock(&kvm_lock);
7438 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7441 * Notification about pvclock gtod data update.
7443 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7446 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7447 struct timekeeper *tk = priv;
7449 update_pvclock_gtod(tk);
7451 /* disable master clock if host does not trust, or does not
7452 * use, TSC based clocksource.
7454 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7455 atomic_read(&kvm_guest_has_master_clock) != 0)
7456 queue_work(system_long_wq, &pvclock_gtod_work);
7461 static struct notifier_block pvclock_gtod_notifier = {
7462 .notifier_call = pvclock_gtod_notify,
7466 int kvm_arch_init(void *opaque)
7468 struct kvm_x86_init_ops *ops = opaque;
7471 if (kvm_x86_ops.hardware_enable) {
7472 printk(KERN_ERR "kvm: already loaded the other module\n");
7477 if (!ops->cpu_has_kvm_support()) {
7478 pr_err_ratelimited("kvm: no hardware support\n");
7482 if (ops->disabled_by_bios()) {
7483 pr_err_ratelimited("kvm: disabled by bios\n");
7489 * KVM explicitly assumes that the guest has an FPU and
7490 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7491 * vCPU's FPU state as a fxregs_state struct.
7493 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7494 printk(KERN_ERR "kvm: inadequate fpu\n");
7500 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7501 __alignof__(struct fpu), SLAB_ACCOUNT,
7503 if (!x86_fpu_cache) {
7504 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7508 x86_emulator_cache = kvm_alloc_emulator_cache();
7509 if (!x86_emulator_cache) {
7510 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7511 goto out_free_x86_fpu_cache;
7514 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7516 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7517 goto out_free_x86_emulator_cache;
7520 r = kvm_mmu_module_init();
7522 goto out_free_percpu;
7524 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7525 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7526 PT_PRESENT_MASK, 0, sme_me_mask);
7529 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7531 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7532 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7533 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7537 if (pi_inject_timer == -1)
7538 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7539 #ifdef CONFIG_X86_64
7540 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7542 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7543 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7549 free_percpu(shared_msrs);
7550 out_free_x86_emulator_cache:
7551 kmem_cache_destroy(x86_emulator_cache);
7552 out_free_x86_fpu_cache:
7553 kmem_cache_destroy(x86_fpu_cache);
7558 void kvm_arch_exit(void)
7560 #ifdef CONFIG_X86_64
7561 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7562 clear_hv_tscchange_cb();
7565 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7567 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7568 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7569 CPUFREQ_TRANSITION_NOTIFIER);
7570 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7571 #ifdef CONFIG_X86_64
7572 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7574 kvm_x86_ops.hardware_enable = NULL;
7575 kvm_mmu_module_exit();
7576 free_percpu(shared_msrs);
7577 kmem_cache_destroy(x86_fpu_cache);
7580 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7582 ++vcpu->stat.halt_exits;
7583 if (lapic_in_kernel(vcpu)) {
7584 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7587 vcpu->run->exit_reason = KVM_EXIT_HLT;
7591 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7593 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7595 int ret = kvm_skip_emulated_instruction(vcpu);
7597 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7598 * KVM_EXIT_DEBUG here.
7600 return kvm_vcpu_halt(vcpu) && ret;
7602 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7604 #ifdef CONFIG_X86_64
7605 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7606 unsigned long clock_type)
7608 struct kvm_clock_pairing clock_pairing;
7609 struct timespec64 ts;
7613 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7614 return -KVM_EOPNOTSUPP;
7616 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7617 return -KVM_EOPNOTSUPP;
7619 clock_pairing.sec = ts.tv_sec;
7620 clock_pairing.nsec = ts.tv_nsec;
7621 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7622 clock_pairing.flags = 0;
7623 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7626 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7627 sizeof(struct kvm_clock_pairing)))
7635 * kvm_pv_kick_cpu_op: Kick a vcpu.
7637 * @apicid - apicid of vcpu to be kicked.
7639 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7641 struct kvm_lapic_irq lapic_irq;
7643 lapic_irq.shorthand = APIC_DEST_NOSHORT;
7644 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
7645 lapic_irq.level = 0;
7646 lapic_irq.dest_id = apicid;
7647 lapic_irq.msi_redir_hint = false;
7649 lapic_irq.delivery_mode = APIC_DM_REMRD;
7650 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7653 bool kvm_apicv_activated(struct kvm *kvm)
7655 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
7657 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
7659 void kvm_apicv_init(struct kvm *kvm, bool enable)
7662 clear_bit(APICV_INHIBIT_REASON_DISABLE,
7663 &kvm->arch.apicv_inhibit_reasons);
7665 set_bit(APICV_INHIBIT_REASON_DISABLE,
7666 &kvm->arch.apicv_inhibit_reasons);
7668 EXPORT_SYMBOL_GPL(kvm_apicv_init);
7670 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7672 struct kvm_vcpu *target = NULL;
7673 struct kvm_apic_map *map;
7676 map = rcu_dereference(kvm->arch.apic_map);
7678 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7679 target = map->phys_map[dest_id]->vcpu;
7683 if (target && READ_ONCE(target->ready))
7684 kvm_vcpu_yield_to(target);
7687 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7689 unsigned long nr, a0, a1, a2, a3, ret;
7692 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7693 return kvm_hv_hypercall(vcpu);
7695 nr = kvm_rax_read(vcpu);
7696 a0 = kvm_rbx_read(vcpu);
7697 a1 = kvm_rcx_read(vcpu);
7698 a2 = kvm_rdx_read(vcpu);
7699 a3 = kvm_rsi_read(vcpu);
7701 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7703 op_64_bit = is_64_bit_mode(vcpu);
7712 if (kvm_x86_ops.get_cpl(vcpu) != 0) {
7718 case KVM_HC_VAPIC_POLL_IRQ:
7721 case KVM_HC_KICK_CPU:
7722 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7723 kvm_sched_yield(vcpu->kvm, a1);
7726 #ifdef CONFIG_X86_64
7727 case KVM_HC_CLOCK_PAIRING:
7728 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7731 case KVM_HC_SEND_IPI:
7732 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7734 case KVM_HC_SCHED_YIELD:
7735 kvm_sched_yield(vcpu->kvm, a0);
7745 kvm_rax_write(vcpu, ret);
7747 ++vcpu->stat.hypercalls;
7748 return kvm_skip_emulated_instruction(vcpu);
7750 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7752 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7754 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7755 char instruction[3];
7756 unsigned long rip = kvm_rip_read(vcpu);
7758 kvm_x86_ops.patch_hypercall(vcpu, instruction);
7760 return emulator_write_emulated(ctxt, rip, instruction, 3,
7764 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7766 return vcpu->run->request_interrupt_window &&
7767 likely(!pic_in_kernel(vcpu->kvm));
7770 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7772 struct kvm_run *kvm_run = vcpu->run;
7774 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7775 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7776 kvm_run->cr8 = kvm_get_cr8(vcpu);
7777 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7778 kvm_run->ready_for_interrupt_injection =
7779 pic_in_kernel(vcpu->kvm) ||
7780 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7783 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7787 if (!kvm_x86_ops.update_cr8_intercept)
7790 if (!lapic_in_kernel(vcpu))
7793 if (vcpu->arch.apicv_active)
7796 if (!vcpu->arch.apic->vapic_addr)
7797 max_irr = kvm_lapic_find_highest_irr(vcpu);
7804 tpr = kvm_lapic_get_cr8(vcpu);
7806 kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr);
7809 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
7812 bool can_inject = true;
7814 /* try to reinject previous events if any */
7816 if (vcpu->arch.exception.injected) {
7817 kvm_x86_ops.queue_exception(vcpu);
7821 * Do not inject an NMI or interrupt if there is a pending
7822 * exception. Exceptions and interrupts are recognized at
7823 * instruction boundaries, i.e. the start of an instruction.
7824 * Trap-like exceptions, e.g. #DB, have higher priority than
7825 * NMIs and interrupts, i.e. traps are recognized before an
7826 * NMI/interrupt that's pending on the same instruction.
7827 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7828 * priority, but are only generated (pended) during instruction
7829 * execution, i.e. a pending fault-like exception means the
7830 * fault occurred on the *previous* instruction and must be
7831 * serviced prior to recognizing any new events in order to
7832 * fully complete the previous instruction.
7834 else if (!vcpu->arch.exception.pending) {
7835 if (vcpu->arch.nmi_injected) {
7836 kvm_x86_ops.set_nmi(vcpu);
7838 } else if (vcpu->arch.interrupt.injected) {
7839 kvm_x86_ops.set_irq(vcpu);
7844 WARN_ON_ONCE(vcpu->arch.exception.injected &&
7845 vcpu->arch.exception.pending);
7848 * Call check_nested_events() even if we reinjected a previous event
7849 * in order for caller to determine if it should require immediate-exit
7850 * from L2 to L1 due to pending L1 events which require exit
7853 if (is_guest_mode(vcpu)) {
7854 r = kvm_x86_ops.nested_ops->check_events(vcpu);
7859 /* try to inject new event if pending */
7860 if (vcpu->arch.exception.pending) {
7861 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7862 vcpu->arch.exception.has_error_code,
7863 vcpu->arch.exception.error_code);
7865 vcpu->arch.exception.pending = false;
7866 vcpu->arch.exception.injected = true;
7868 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7869 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7872 if (vcpu->arch.exception.nr == DB_VECTOR) {
7873 kvm_deliver_exception_payload(vcpu);
7874 if (vcpu->arch.dr7 & DR7_GD) {
7875 vcpu->arch.dr7 &= ~DR7_GD;
7876 kvm_update_dr7(vcpu);
7880 kvm_x86_ops.queue_exception(vcpu);
7885 * Finally, inject interrupt events. If an event cannot be injected
7886 * due to architectural conditions (e.g. IF=0) a window-open exit
7887 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
7888 * and can architecturally be injected, but we cannot do it right now:
7889 * an interrupt could have arrived just now and we have to inject it
7890 * as a vmexit, or there could already an event in the queue, which is
7891 * indicated by can_inject. In that case we request an immediate exit
7892 * in order to make progress and get back here for another iteration.
7893 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
7895 if (vcpu->arch.smi_pending) {
7896 r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY;
7900 vcpu->arch.smi_pending = false;
7901 ++vcpu->arch.smi_count;
7905 kvm_x86_ops.enable_smi_window(vcpu);
7908 if (vcpu->arch.nmi_pending) {
7909 r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY;
7913 --vcpu->arch.nmi_pending;
7914 vcpu->arch.nmi_injected = true;
7915 kvm_x86_ops.set_nmi(vcpu);
7917 WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0);
7919 if (vcpu->arch.nmi_pending)
7920 kvm_x86_ops.enable_nmi_window(vcpu);
7923 if (kvm_cpu_has_injectable_intr(vcpu)) {
7924 r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY;
7928 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
7929 kvm_x86_ops.set_irq(vcpu);
7930 WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0);
7932 if (kvm_cpu_has_injectable_intr(vcpu))
7933 kvm_x86_ops.enable_irq_window(vcpu);
7936 if (is_guest_mode(vcpu) &&
7937 kvm_x86_ops.nested_ops->hv_timer_pending &&
7938 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
7939 *req_immediate_exit = true;
7941 WARN_ON(vcpu->arch.exception.pending);
7945 *req_immediate_exit = true;
7949 static void process_nmi(struct kvm_vcpu *vcpu)
7954 * x86 is limited to one NMI running, and one NMI pending after it.
7955 * If an NMI is already in progress, limit further NMIs to just one.
7956 * Otherwise, allow two (and we'll inject the first one immediately).
7958 if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7961 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7962 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7963 kvm_make_request(KVM_REQ_EVENT, vcpu);
7966 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7969 flags |= seg->g << 23;
7970 flags |= seg->db << 22;
7971 flags |= seg->l << 21;
7972 flags |= seg->avl << 20;
7973 flags |= seg->present << 15;
7974 flags |= seg->dpl << 13;
7975 flags |= seg->s << 12;
7976 flags |= seg->type << 8;
7980 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7982 struct kvm_segment seg;
7985 kvm_get_segment(vcpu, &seg, n);
7986 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7989 offset = 0x7f84 + n * 12;
7991 offset = 0x7f2c + (n - 3) * 12;
7993 put_smstate(u32, buf, offset + 8, seg.base);
7994 put_smstate(u32, buf, offset + 4, seg.limit);
7995 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7998 #ifdef CONFIG_X86_64
7999 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
8001 struct kvm_segment seg;
8005 kvm_get_segment(vcpu, &seg, n);
8006 offset = 0x7e00 + n * 16;
8008 flags = enter_smm_get_segment_flags(&seg) >> 8;
8009 put_smstate(u16, buf, offset, seg.selector);
8010 put_smstate(u16, buf, offset + 2, flags);
8011 put_smstate(u32, buf, offset + 4, seg.limit);
8012 put_smstate(u64, buf, offset + 8, seg.base);
8016 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
8019 struct kvm_segment seg;
8023 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
8024 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
8025 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
8026 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
8028 for (i = 0; i < 8; i++)
8029 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
8031 kvm_get_dr(vcpu, 6, &val);
8032 put_smstate(u32, buf, 0x7fcc, (u32)val);
8033 kvm_get_dr(vcpu, 7, &val);
8034 put_smstate(u32, buf, 0x7fc8, (u32)val);
8036 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8037 put_smstate(u32, buf, 0x7fc4, seg.selector);
8038 put_smstate(u32, buf, 0x7f64, seg.base);
8039 put_smstate(u32, buf, 0x7f60, seg.limit);
8040 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
8042 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8043 put_smstate(u32, buf, 0x7fc0, seg.selector);
8044 put_smstate(u32, buf, 0x7f80, seg.base);
8045 put_smstate(u32, buf, 0x7f7c, seg.limit);
8046 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
8048 kvm_x86_ops.get_gdt(vcpu, &dt);
8049 put_smstate(u32, buf, 0x7f74, dt.address);
8050 put_smstate(u32, buf, 0x7f70, dt.size);
8052 kvm_x86_ops.get_idt(vcpu, &dt);
8053 put_smstate(u32, buf, 0x7f58, dt.address);
8054 put_smstate(u32, buf, 0x7f54, dt.size);
8056 for (i = 0; i < 6; i++)
8057 enter_smm_save_seg_32(vcpu, buf, i);
8059 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
8062 put_smstate(u32, buf, 0x7efc, 0x00020000);
8063 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
8066 #ifdef CONFIG_X86_64
8067 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
8070 struct kvm_segment seg;
8074 for (i = 0; i < 16; i++)
8075 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
8077 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
8078 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
8080 kvm_get_dr(vcpu, 6, &val);
8081 put_smstate(u64, buf, 0x7f68, val);
8082 kvm_get_dr(vcpu, 7, &val);
8083 put_smstate(u64, buf, 0x7f60, val);
8085 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
8086 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
8087 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
8089 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
8092 put_smstate(u32, buf, 0x7efc, 0x00020064);
8094 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
8096 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8097 put_smstate(u16, buf, 0x7e90, seg.selector);
8098 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
8099 put_smstate(u32, buf, 0x7e94, seg.limit);
8100 put_smstate(u64, buf, 0x7e98, seg.base);
8102 kvm_x86_ops.get_idt(vcpu, &dt);
8103 put_smstate(u32, buf, 0x7e84, dt.size);
8104 put_smstate(u64, buf, 0x7e88, dt.address);
8106 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8107 put_smstate(u16, buf, 0x7e70, seg.selector);
8108 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
8109 put_smstate(u32, buf, 0x7e74, seg.limit);
8110 put_smstate(u64, buf, 0x7e78, seg.base);
8112 kvm_x86_ops.get_gdt(vcpu, &dt);
8113 put_smstate(u32, buf, 0x7e64, dt.size);
8114 put_smstate(u64, buf, 0x7e68, dt.address);
8116 for (i = 0; i < 6; i++)
8117 enter_smm_save_seg_64(vcpu, buf, i);
8121 static void enter_smm(struct kvm_vcpu *vcpu)
8123 struct kvm_segment cs, ds;
8128 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
8129 memset(buf, 0, 512);
8130 #ifdef CONFIG_X86_64
8131 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8132 enter_smm_save_state_64(vcpu, buf);
8135 enter_smm_save_state_32(vcpu, buf);
8138 * Give pre_enter_smm() a chance to make ISA-specific changes to the
8139 * vCPU state (e.g. leave guest mode) after we've saved the state into
8140 * the SMM state-save area.
8142 kvm_x86_ops.pre_enter_smm(vcpu, buf);
8144 vcpu->arch.hflags |= HF_SMM_MASK;
8145 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
8147 if (kvm_x86_ops.get_nmi_mask(vcpu))
8148 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
8150 kvm_x86_ops.set_nmi_mask(vcpu, true);
8152 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
8153 kvm_rip_write(vcpu, 0x8000);
8155 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
8156 kvm_x86_ops.set_cr0(vcpu, cr0);
8157 vcpu->arch.cr0 = cr0;
8159 kvm_x86_ops.set_cr4(vcpu, 0);
8161 /* Undocumented: IDT limit is set to zero on entry to SMM. */
8162 dt.address = dt.size = 0;
8163 kvm_x86_ops.set_idt(vcpu, &dt);
8165 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
8167 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
8168 cs.base = vcpu->arch.smbase;
8173 cs.limit = ds.limit = 0xffffffff;
8174 cs.type = ds.type = 0x3;
8175 cs.dpl = ds.dpl = 0;
8180 cs.avl = ds.avl = 0;
8181 cs.present = ds.present = 1;
8182 cs.unusable = ds.unusable = 0;
8183 cs.padding = ds.padding = 0;
8185 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8186 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8187 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8188 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8189 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8190 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8192 #ifdef CONFIG_X86_64
8193 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8194 kvm_x86_ops.set_efer(vcpu, 0);
8197 kvm_update_cpuid_runtime(vcpu);
8198 kvm_mmu_reset_context(vcpu);
8201 static void process_smi(struct kvm_vcpu *vcpu)
8203 vcpu->arch.smi_pending = true;
8204 kvm_make_request(KVM_REQ_EVENT, vcpu);
8207 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8208 unsigned long *vcpu_bitmap)
8212 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8214 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8215 NULL, vcpu_bitmap, cpus);
8217 free_cpumask_var(cpus);
8220 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8222 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8225 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8227 if (!lapic_in_kernel(vcpu))
8230 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8231 kvm_apic_update_apicv(vcpu);
8232 kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu);
8234 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8237 * NOTE: Do not hold any lock prior to calling this.
8239 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8240 * locked, because it calls __x86_set_memory_region() which does
8241 * synchronize_srcu(&kvm->srcu).
8243 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8245 struct kvm_vcpu *except;
8246 unsigned long old, new, expected;
8248 if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8249 !kvm_x86_ops.check_apicv_inhibit_reasons(bit))
8252 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8254 expected = new = old;
8256 __clear_bit(bit, &new);
8258 __set_bit(bit, &new);
8261 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8262 } while (old != expected);
8267 trace_kvm_apicv_update_request(activate, bit);
8268 if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8269 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate);
8272 * Sending request to update APICV for all other vcpus,
8273 * while update the calling vcpu immediately instead of
8274 * waiting for another #VMEXIT to handle the request.
8276 except = kvm_get_running_vcpu();
8277 kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE,
8280 kvm_vcpu_update_apicv(except);
8282 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8284 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8286 if (!kvm_apic_present(vcpu))
8289 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8291 if (irqchip_split(vcpu->kvm))
8292 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8294 if (vcpu->arch.apicv_active)
8295 kvm_x86_ops.sync_pir_to_irr(vcpu);
8296 if (ioapic_in_kernel(vcpu->kvm))
8297 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8300 if (is_guest_mode(vcpu))
8301 vcpu->arch.load_eoi_exitmap_pending = true;
8303 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8306 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8308 u64 eoi_exit_bitmap[4];
8310 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8313 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8314 vcpu_to_synic(vcpu)->vec_bitmap, 256);
8315 kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8318 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8319 unsigned long start, unsigned long end)
8321 unsigned long apic_address;
8324 * The physical address of apic access page is stored in the VMCS.
8325 * Update it when it becomes invalid.
8327 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8328 if (start <= apic_address && apic_address < end)
8329 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8332 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8334 if (!lapic_in_kernel(vcpu))
8337 if (!kvm_x86_ops.set_apic_access_page_addr)
8340 kvm_x86_ops.set_apic_access_page_addr(vcpu);
8343 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8345 smp_send_reschedule(vcpu->cpu);
8347 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8350 * Returns 1 to let vcpu_run() continue the guest execution loop without
8351 * exiting to the userspace. Otherwise, the value will be returned to the
8354 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8358 dm_request_for_irq_injection(vcpu) &&
8359 kvm_cpu_accept_dm_intr(vcpu);
8360 fastpath_t exit_fastpath;
8362 bool req_immediate_exit = false;
8364 if (kvm_request_pending(vcpu)) {
8365 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) {
8366 if (unlikely(!kvm_x86_ops.nested_ops->get_vmcs12_pages(vcpu))) {
8371 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8372 kvm_mmu_unload(vcpu);
8373 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8374 __kvm_migrate_timers(vcpu);
8375 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8376 kvm_gen_update_masterclock(vcpu->kvm);
8377 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8378 kvm_gen_kvmclock_update(vcpu);
8379 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8380 r = kvm_guest_time_update(vcpu);
8384 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8385 kvm_mmu_sync_roots(vcpu);
8386 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8387 kvm_mmu_load_pgd(vcpu);
8388 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
8389 kvm_vcpu_flush_tlb_all(vcpu);
8391 /* Flushing all ASIDs flushes the current ASID... */
8392 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
8394 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
8395 kvm_vcpu_flush_tlb_current(vcpu);
8396 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu))
8397 kvm_vcpu_flush_tlb_guest(vcpu);
8399 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8400 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8404 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8405 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8406 vcpu->mmio_needed = 0;
8410 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8411 /* Page is swapped out. Do synthetic halt */
8412 vcpu->arch.apf.halted = true;
8416 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8417 record_steal_time(vcpu);
8418 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8420 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8422 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8423 kvm_pmu_handle_event(vcpu);
8424 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8425 kvm_pmu_deliver_pmi(vcpu);
8426 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8427 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8428 if (test_bit(vcpu->arch.pending_ioapic_eoi,
8429 vcpu->arch.ioapic_handled_vectors)) {
8430 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8431 vcpu->run->eoi.vector =
8432 vcpu->arch.pending_ioapic_eoi;
8437 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8438 vcpu_scan_ioapic(vcpu);
8439 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8440 vcpu_load_eoi_exitmap(vcpu);
8441 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8442 kvm_vcpu_reload_apic_access_page(vcpu);
8443 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8444 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8445 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8449 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8450 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8451 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8455 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8456 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8457 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8463 * KVM_REQ_HV_STIMER has to be processed after
8464 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8465 * depend on the guest clock being up-to-date
8467 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8468 kvm_hv_process_stimers(vcpu);
8469 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8470 kvm_vcpu_update_apicv(vcpu);
8471 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
8472 kvm_check_async_pf_completion(vcpu);
8475 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8476 ++vcpu->stat.req_event;
8477 kvm_apic_accept_events(vcpu);
8478 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8483 inject_pending_event(vcpu, &req_immediate_exit);
8485 kvm_x86_ops.enable_irq_window(vcpu);
8487 if (kvm_lapic_enabled(vcpu)) {
8488 update_cr8_intercept(vcpu);
8489 kvm_lapic_sync_to_vapic(vcpu);
8493 r = kvm_mmu_reload(vcpu);
8495 goto cancel_injection;
8500 kvm_x86_ops.prepare_guest_switch(vcpu);
8503 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8504 * IPI are then delayed after guest entry, which ensures that they
8505 * result in virtual interrupt delivery.
8507 local_irq_disable();
8508 vcpu->mode = IN_GUEST_MODE;
8510 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8513 * 1) We should set ->mode before checking ->requests. Please see
8514 * the comment in kvm_vcpu_exiting_guest_mode().
8516 * 2) For APICv, we should set ->mode before checking PID.ON. This
8517 * pairs with the memory barrier implicit in pi_test_and_set_on
8518 * (see vmx_deliver_posted_interrupt).
8520 * 3) This also orders the write to mode from any reads to the page
8521 * tables done while the VCPU is running. Please see the comment
8522 * in kvm_flush_remote_tlbs.
8524 smp_mb__after_srcu_read_unlock();
8527 * This handles the case where a posted interrupt was
8528 * notified with kvm_vcpu_kick.
8530 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8531 kvm_x86_ops.sync_pir_to_irr(vcpu);
8533 if (kvm_vcpu_exit_request(vcpu)) {
8534 vcpu->mode = OUTSIDE_GUEST_MODE;
8538 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8540 goto cancel_injection;
8543 if (req_immediate_exit) {
8544 kvm_make_request(KVM_REQ_EVENT, vcpu);
8545 kvm_x86_ops.request_immediate_exit(vcpu);
8548 trace_kvm_entry(vcpu->vcpu_id);
8550 fpregs_assert_state_consistent();
8551 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8552 switch_fpu_return();
8554 if (unlikely(vcpu->arch.switch_db_regs)) {
8556 set_debugreg(vcpu->arch.eff_db[0], 0);
8557 set_debugreg(vcpu->arch.eff_db[1], 1);
8558 set_debugreg(vcpu->arch.eff_db[2], 2);
8559 set_debugreg(vcpu->arch.eff_db[3], 3);
8560 set_debugreg(vcpu->arch.dr6, 6);
8561 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8564 exit_fastpath = kvm_x86_ops.run(vcpu);
8567 * Do this here before restoring debug registers on the host. And
8568 * since we do this before handling the vmexit, a DR access vmexit
8569 * can (a) read the correct value of the debug registers, (b) set
8570 * KVM_DEBUGREG_WONT_EXIT again.
8572 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8573 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8574 kvm_x86_ops.sync_dirty_debug_regs(vcpu);
8575 kvm_update_dr0123(vcpu);
8576 kvm_update_dr7(vcpu);
8577 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8581 * If the guest has used debug registers, at least dr7
8582 * will be disabled while returning to the host.
8583 * If we don't have active breakpoints in the host, we don't
8584 * care about the messed up debug address registers. But if
8585 * we have some of them active, restore the old state.
8587 if (hw_breakpoint_active())
8588 hw_breakpoint_restore();
8590 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
8591 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8593 vcpu->mode = OUTSIDE_GUEST_MODE;
8596 kvm_x86_ops.handle_exit_irqoff(vcpu);
8599 * Consume any pending interrupts, including the possible source of
8600 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8601 * An instruction is required after local_irq_enable() to fully unblock
8602 * interrupts on processors that implement an interrupt shadow, the
8603 * stat.exits increment will do nicely.
8605 kvm_before_interrupt(vcpu);
8608 local_irq_disable();
8609 kvm_after_interrupt(vcpu);
8611 if (lapic_in_kernel(vcpu)) {
8612 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8613 if (delta != S64_MIN) {
8614 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8615 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8622 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8625 * Profile KVM exit RIPs:
8627 if (unlikely(prof_on == KVM_PROFILING)) {
8628 unsigned long rip = kvm_rip_read(vcpu);
8629 profile_hit(KVM_PROFILING, (void *)rip);
8632 if (unlikely(vcpu->arch.tsc_always_catchup))
8633 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8635 if (vcpu->arch.apic_attention)
8636 kvm_lapic_sync_from_vapic(vcpu);
8638 r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath);
8642 if (req_immediate_exit)
8643 kvm_make_request(KVM_REQ_EVENT, vcpu);
8644 kvm_x86_ops.cancel_injection(vcpu);
8645 if (unlikely(vcpu->arch.apic_attention))
8646 kvm_lapic_sync_from_vapic(vcpu);
8651 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8653 if (!kvm_arch_vcpu_runnable(vcpu) &&
8654 (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) {
8655 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8656 kvm_vcpu_block(vcpu);
8657 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8659 if (kvm_x86_ops.post_block)
8660 kvm_x86_ops.post_block(vcpu);
8662 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8666 kvm_apic_accept_events(vcpu);
8667 switch(vcpu->arch.mp_state) {
8668 case KVM_MP_STATE_HALTED:
8669 vcpu->arch.pv.pv_unhalted = false;
8670 vcpu->arch.mp_state =
8671 KVM_MP_STATE_RUNNABLE;
8673 case KVM_MP_STATE_RUNNABLE:
8674 vcpu->arch.apf.halted = false;
8676 case KVM_MP_STATE_INIT_RECEIVED:
8684 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8686 if (is_guest_mode(vcpu))
8687 kvm_x86_ops.nested_ops->check_events(vcpu);
8689 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8690 !vcpu->arch.apf.halted);
8693 static int vcpu_run(struct kvm_vcpu *vcpu)
8696 struct kvm *kvm = vcpu->kvm;
8698 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8699 vcpu->arch.l1tf_flush_l1d = true;
8702 if (kvm_vcpu_running(vcpu)) {
8703 r = vcpu_enter_guest(vcpu);
8705 r = vcpu_block(kvm, vcpu);
8711 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8712 if (kvm_cpu_has_pending_timer(vcpu))
8713 kvm_inject_pending_timer_irqs(vcpu);
8715 if (dm_request_for_irq_injection(vcpu) &&
8716 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8718 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8719 ++vcpu->stat.request_irq_exits;
8723 if (__xfer_to_guest_mode_work_pending()) {
8724 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8725 r = xfer_to_guest_mode_handle_work(vcpu);
8728 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8732 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8737 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8741 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8742 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8743 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8747 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8749 BUG_ON(!vcpu->arch.pio.count);
8751 return complete_emulated_io(vcpu);
8755 * Implements the following, as a state machine:
8759 * for each mmio piece in the fragment
8767 * for each mmio piece in the fragment
8772 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8774 struct kvm_run *run = vcpu->run;
8775 struct kvm_mmio_fragment *frag;
8778 BUG_ON(!vcpu->mmio_needed);
8780 /* Complete previous fragment */
8781 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8782 len = min(8u, frag->len);
8783 if (!vcpu->mmio_is_write)
8784 memcpy(frag->data, run->mmio.data, len);
8786 if (frag->len <= 8) {
8787 /* Switch to the next fragment. */
8789 vcpu->mmio_cur_fragment++;
8791 /* Go forward to the next mmio piece. */
8797 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8798 vcpu->mmio_needed = 0;
8800 /* FIXME: return into emulator if single-stepping. */
8801 if (vcpu->mmio_is_write)
8803 vcpu->mmio_read_completed = 1;
8804 return complete_emulated_io(vcpu);
8807 run->exit_reason = KVM_EXIT_MMIO;
8808 run->mmio.phys_addr = frag->gpa;
8809 if (vcpu->mmio_is_write)
8810 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8811 run->mmio.len = min(8u, frag->len);
8812 run->mmio.is_write = vcpu->mmio_is_write;
8813 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8817 static void kvm_save_current_fpu(struct fpu *fpu)
8820 * If the target FPU state is not resident in the CPU registers, just
8821 * memcpy() from current, else save CPU state directly to the target.
8823 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8824 memcpy(&fpu->state, ¤t->thread.fpu.state,
8825 fpu_kernel_xstate_size);
8827 copy_fpregs_to_fpstate(fpu);
8830 /* Swap (qemu) user FPU context for the guest FPU context. */
8831 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8835 kvm_save_current_fpu(vcpu->arch.user_fpu);
8837 /* PKRU is separately restored in kvm_x86_ops.run. */
8838 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8839 ~XFEATURE_MASK_PKRU);
8841 fpregs_mark_activate();
8847 /* When vcpu_run ends, restore user space FPU context. */
8848 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8852 kvm_save_current_fpu(vcpu->arch.guest_fpu);
8854 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8856 fpregs_mark_activate();
8859 ++vcpu->stat.fpu_reload;
8863 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
8865 struct kvm_run *kvm_run = vcpu->run;
8869 kvm_sigset_activate(vcpu);
8870 kvm_load_guest_fpu(vcpu);
8872 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8873 if (kvm_run->immediate_exit) {
8877 kvm_vcpu_block(vcpu);
8878 kvm_apic_accept_events(vcpu);
8879 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8881 if (signal_pending(current)) {
8883 kvm_run->exit_reason = KVM_EXIT_INTR;
8884 ++vcpu->stat.signal_exits;
8889 if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8894 if (kvm_run->kvm_dirty_regs) {
8895 r = sync_regs(vcpu);
8900 /* re-sync apic's tpr */
8901 if (!lapic_in_kernel(vcpu)) {
8902 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8908 if (unlikely(vcpu->arch.complete_userspace_io)) {
8909 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8910 vcpu->arch.complete_userspace_io = NULL;
8915 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8917 if (kvm_run->immediate_exit)
8923 kvm_put_guest_fpu(vcpu);
8924 if (kvm_run->kvm_valid_regs)
8926 post_kvm_run_save(vcpu);
8927 kvm_sigset_deactivate(vcpu);
8933 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8935 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8937 * We are here if userspace calls get_regs() in the middle of
8938 * instruction emulation. Registers state needs to be copied
8939 * back from emulation context to vcpu. Userspace shouldn't do
8940 * that usually, but some bad designed PV devices (vmware
8941 * backdoor interface) need this to work
8943 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
8944 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8946 regs->rax = kvm_rax_read(vcpu);
8947 regs->rbx = kvm_rbx_read(vcpu);
8948 regs->rcx = kvm_rcx_read(vcpu);
8949 regs->rdx = kvm_rdx_read(vcpu);
8950 regs->rsi = kvm_rsi_read(vcpu);
8951 regs->rdi = kvm_rdi_read(vcpu);
8952 regs->rsp = kvm_rsp_read(vcpu);
8953 regs->rbp = kvm_rbp_read(vcpu);
8954 #ifdef CONFIG_X86_64
8955 regs->r8 = kvm_r8_read(vcpu);
8956 regs->r9 = kvm_r9_read(vcpu);
8957 regs->r10 = kvm_r10_read(vcpu);
8958 regs->r11 = kvm_r11_read(vcpu);
8959 regs->r12 = kvm_r12_read(vcpu);
8960 regs->r13 = kvm_r13_read(vcpu);
8961 regs->r14 = kvm_r14_read(vcpu);
8962 regs->r15 = kvm_r15_read(vcpu);
8965 regs->rip = kvm_rip_read(vcpu);
8966 regs->rflags = kvm_get_rflags(vcpu);
8969 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8972 __get_regs(vcpu, regs);
8977 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8979 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8980 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8982 kvm_rax_write(vcpu, regs->rax);
8983 kvm_rbx_write(vcpu, regs->rbx);
8984 kvm_rcx_write(vcpu, regs->rcx);
8985 kvm_rdx_write(vcpu, regs->rdx);
8986 kvm_rsi_write(vcpu, regs->rsi);
8987 kvm_rdi_write(vcpu, regs->rdi);
8988 kvm_rsp_write(vcpu, regs->rsp);
8989 kvm_rbp_write(vcpu, regs->rbp);
8990 #ifdef CONFIG_X86_64
8991 kvm_r8_write(vcpu, regs->r8);
8992 kvm_r9_write(vcpu, regs->r9);
8993 kvm_r10_write(vcpu, regs->r10);
8994 kvm_r11_write(vcpu, regs->r11);
8995 kvm_r12_write(vcpu, regs->r12);
8996 kvm_r13_write(vcpu, regs->r13);
8997 kvm_r14_write(vcpu, regs->r14);
8998 kvm_r15_write(vcpu, regs->r15);
9001 kvm_rip_write(vcpu, regs->rip);
9002 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
9004 vcpu->arch.exception.pending = false;
9006 kvm_make_request(KVM_REQ_EVENT, vcpu);
9009 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9012 __set_regs(vcpu, regs);
9017 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
9019 struct kvm_segment cs;
9021 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9025 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
9027 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9031 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9032 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9033 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9034 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9035 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9036 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9038 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9039 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9041 kvm_x86_ops.get_idt(vcpu, &dt);
9042 sregs->idt.limit = dt.size;
9043 sregs->idt.base = dt.address;
9044 kvm_x86_ops.get_gdt(vcpu, &dt);
9045 sregs->gdt.limit = dt.size;
9046 sregs->gdt.base = dt.address;
9048 sregs->cr0 = kvm_read_cr0(vcpu);
9049 sregs->cr2 = vcpu->arch.cr2;
9050 sregs->cr3 = kvm_read_cr3(vcpu);
9051 sregs->cr4 = kvm_read_cr4(vcpu);
9052 sregs->cr8 = kvm_get_cr8(vcpu);
9053 sregs->efer = vcpu->arch.efer;
9054 sregs->apic_base = kvm_get_apic_base(vcpu);
9056 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
9058 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
9059 set_bit(vcpu->arch.interrupt.nr,
9060 (unsigned long *)sregs->interrupt_bitmap);
9063 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
9064 struct kvm_sregs *sregs)
9067 __get_sregs(vcpu, sregs);
9072 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
9073 struct kvm_mp_state *mp_state)
9076 if (kvm_mpx_supported())
9077 kvm_load_guest_fpu(vcpu);
9079 kvm_apic_accept_events(vcpu);
9080 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
9081 vcpu->arch.pv.pv_unhalted)
9082 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
9084 mp_state->mp_state = vcpu->arch.mp_state;
9086 if (kvm_mpx_supported())
9087 kvm_put_guest_fpu(vcpu);
9092 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
9093 struct kvm_mp_state *mp_state)
9099 if (!lapic_in_kernel(vcpu) &&
9100 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
9104 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
9105 * INIT state; latched init should be reported using
9106 * KVM_SET_VCPU_EVENTS, so reject it here.
9108 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
9109 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
9110 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
9113 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
9114 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
9115 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
9117 vcpu->arch.mp_state = mp_state->mp_state;
9118 kvm_make_request(KVM_REQ_EVENT, vcpu);
9126 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
9127 int reason, bool has_error_code, u32 error_code)
9129 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9132 init_emulate_ctxt(vcpu);
9134 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9135 has_error_code, error_code);
9137 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9138 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
9139 vcpu->run->internal.ndata = 0;
9143 kvm_rip_write(vcpu, ctxt->eip);
9144 kvm_set_rflags(vcpu, ctxt->eflags);
9147 EXPORT_SYMBOL_GPL(kvm_task_switch);
9149 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9151 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
9153 * When EFER.LME and CR0.PG are set, the processor is in
9154 * 64-bit mode (though maybe in a 32-bit code segment).
9155 * CR4.PAE and EFER.LMA must be set.
9157 if (!(sregs->cr4 & X86_CR4_PAE)
9158 || !(sregs->efer & EFER_LMA))
9162 * Not in 64-bit mode: EFER.LMA is clear and the code
9163 * segment cannot be 64-bit.
9165 if (sregs->efer & EFER_LMA || sregs->cs.l)
9169 return kvm_valid_cr4(vcpu, sregs->cr4);
9172 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9174 struct msr_data apic_base_msr;
9175 int mmu_reset_needed = 0;
9176 int cpuid_update_needed = 0;
9177 int pending_vec, max_bits, idx;
9181 if (kvm_valid_sregs(vcpu, sregs))
9184 apic_base_msr.data = sregs->apic_base;
9185 apic_base_msr.host_initiated = true;
9186 if (kvm_set_apic_base(vcpu, &apic_base_msr))
9189 dt.size = sregs->idt.limit;
9190 dt.address = sregs->idt.base;
9191 kvm_x86_ops.set_idt(vcpu, &dt);
9192 dt.size = sregs->gdt.limit;
9193 dt.address = sregs->gdt.base;
9194 kvm_x86_ops.set_gdt(vcpu, &dt);
9196 vcpu->arch.cr2 = sregs->cr2;
9197 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9198 vcpu->arch.cr3 = sregs->cr3;
9199 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9201 kvm_set_cr8(vcpu, sregs->cr8);
9203 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9204 kvm_x86_ops.set_efer(vcpu, sregs->efer);
9206 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9207 kvm_x86_ops.set_cr0(vcpu, sregs->cr0);
9208 vcpu->arch.cr0 = sregs->cr0;
9210 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9211 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
9212 (X86_CR4_OSXSAVE | X86_CR4_PKE));
9213 kvm_x86_ops.set_cr4(vcpu, sregs->cr4);
9214 if (cpuid_update_needed)
9215 kvm_update_cpuid_runtime(vcpu);
9217 idx = srcu_read_lock(&vcpu->kvm->srcu);
9218 if (is_pae_paging(vcpu)) {
9219 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9220 mmu_reset_needed = 1;
9222 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9224 if (mmu_reset_needed)
9225 kvm_mmu_reset_context(vcpu);
9227 max_bits = KVM_NR_INTERRUPTS;
9228 pending_vec = find_first_bit(
9229 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9230 if (pending_vec < max_bits) {
9231 kvm_queue_interrupt(vcpu, pending_vec, false);
9232 pr_debug("Set back pending irq %d\n", pending_vec);
9235 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9236 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9237 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9238 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9239 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9240 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9242 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9243 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9245 update_cr8_intercept(vcpu);
9247 /* Older userspace won't unhalt the vcpu on reset. */
9248 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9249 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9251 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9253 kvm_make_request(KVM_REQ_EVENT, vcpu);
9260 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9261 struct kvm_sregs *sregs)
9266 ret = __set_sregs(vcpu, sregs);
9271 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9272 struct kvm_guest_debug *dbg)
9274 unsigned long rflags;
9279 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9281 if (vcpu->arch.exception.pending)
9283 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9284 kvm_queue_exception(vcpu, DB_VECTOR);
9286 kvm_queue_exception(vcpu, BP_VECTOR);
9290 * Read rflags as long as potentially injected trace flags are still
9293 rflags = kvm_get_rflags(vcpu);
9295 vcpu->guest_debug = dbg->control;
9296 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9297 vcpu->guest_debug = 0;
9299 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9300 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9301 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9302 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9304 for (i = 0; i < KVM_NR_DB_REGS; i++)
9305 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9307 kvm_update_dr7(vcpu);
9309 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9310 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9311 get_segment_base(vcpu, VCPU_SREG_CS);
9314 * Trigger an rflags update that will inject or remove the trace
9317 kvm_set_rflags(vcpu, rflags);
9319 kvm_x86_ops.update_exception_bitmap(vcpu);
9329 * Translate a guest virtual address to a guest physical address.
9331 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9332 struct kvm_translation *tr)
9334 unsigned long vaddr = tr->linear_address;
9340 idx = srcu_read_lock(&vcpu->kvm->srcu);
9341 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9342 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9343 tr->physical_address = gpa;
9344 tr->valid = gpa != UNMAPPED_GVA;
9352 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9354 struct fxregs_state *fxsave;
9358 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9359 memcpy(fpu->fpr, fxsave->st_space, 128);
9360 fpu->fcw = fxsave->cwd;
9361 fpu->fsw = fxsave->swd;
9362 fpu->ftwx = fxsave->twd;
9363 fpu->last_opcode = fxsave->fop;
9364 fpu->last_ip = fxsave->rip;
9365 fpu->last_dp = fxsave->rdp;
9366 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9372 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9374 struct fxregs_state *fxsave;
9378 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9380 memcpy(fxsave->st_space, fpu->fpr, 128);
9381 fxsave->cwd = fpu->fcw;
9382 fxsave->swd = fpu->fsw;
9383 fxsave->twd = fpu->ftwx;
9384 fxsave->fop = fpu->last_opcode;
9385 fxsave->rip = fpu->last_ip;
9386 fxsave->rdp = fpu->last_dp;
9387 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9393 static void store_regs(struct kvm_vcpu *vcpu)
9395 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9397 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9398 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9400 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9401 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9403 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9404 kvm_vcpu_ioctl_x86_get_vcpu_events(
9405 vcpu, &vcpu->run->s.regs.events);
9408 static int sync_regs(struct kvm_vcpu *vcpu)
9410 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9413 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9414 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9415 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9417 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9418 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9420 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9422 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9423 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9424 vcpu, &vcpu->run->s.regs.events))
9426 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9432 static void fx_init(struct kvm_vcpu *vcpu)
9434 fpstate_init(&vcpu->arch.guest_fpu->state);
9435 if (boot_cpu_has(X86_FEATURE_XSAVES))
9436 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9437 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9440 * Ensure guest xcr0 is valid for loading
9442 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9444 vcpu->arch.cr0 |= X86_CR0_ET;
9447 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9449 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9450 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9451 "guest TSC will not be reliable\n");
9456 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9461 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9462 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9464 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9466 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9468 r = kvm_mmu_create(vcpu);
9472 if (irqchip_in_kernel(vcpu->kvm)) {
9473 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9475 goto fail_mmu_destroy;
9476 if (kvm_apicv_activated(vcpu->kvm))
9477 vcpu->arch.apicv_active = true;
9479 static_key_slow_inc(&kvm_no_apic_vcpu);
9483 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9485 goto fail_free_lapic;
9486 vcpu->arch.pio_data = page_address(page);
9488 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9489 GFP_KERNEL_ACCOUNT);
9490 if (!vcpu->arch.mce_banks)
9491 goto fail_free_pio_data;
9492 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9494 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9495 GFP_KERNEL_ACCOUNT))
9496 goto fail_free_mce_banks;
9498 if (!alloc_emulate_ctxt(vcpu))
9499 goto free_wbinvd_dirty_mask;
9501 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9502 GFP_KERNEL_ACCOUNT);
9503 if (!vcpu->arch.user_fpu) {
9504 pr_err("kvm: failed to allocate userspace's fpu\n");
9505 goto free_emulate_ctxt;
9508 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9509 GFP_KERNEL_ACCOUNT);
9510 if (!vcpu->arch.guest_fpu) {
9511 pr_err("kvm: failed to allocate vcpu's fpu\n");
9516 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9518 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9520 kvm_async_pf_hash_reset(vcpu);
9523 vcpu->arch.pending_external_vector = -1;
9524 vcpu->arch.preempted_in_kernel = false;
9526 kvm_hv_vcpu_init(vcpu);
9528 r = kvm_x86_ops.vcpu_create(vcpu);
9530 goto free_guest_fpu;
9532 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9533 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9534 kvm_vcpu_mtrr_init(vcpu);
9536 kvm_vcpu_reset(vcpu, false);
9537 kvm_init_mmu(vcpu, false);
9542 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9544 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9546 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9547 free_wbinvd_dirty_mask:
9548 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9549 fail_free_mce_banks:
9550 kfree(vcpu->arch.mce_banks);
9552 free_page((unsigned long)vcpu->arch.pio_data);
9554 kvm_free_lapic(vcpu);
9556 kvm_mmu_destroy(vcpu);
9560 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9562 struct msr_data msr;
9563 struct kvm *kvm = vcpu->kvm;
9565 kvm_hv_vcpu_postcreate(vcpu);
9567 if (mutex_lock_killable(&vcpu->mutex))
9571 msr.index = MSR_IA32_TSC;
9572 msr.host_initiated = true;
9573 kvm_write_tsc(vcpu, &msr);
9576 /* poll control enabled by default */
9577 vcpu->arch.msr_kvm_poll_control = 1;
9579 mutex_unlock(&vcpu->mutex);
9581 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
9582 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9583 KVMCLOCK_SYNC_PERIOD);
9586 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9588 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9591 kvm_release_pfn(cache->pfn, cache->dirty, cache);
9593 kvmclock_reset(vcpu);
9595 kvm_x86_ops.vcpu_free(vcpu);
9597 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9598 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9599 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9600 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9602 kvm_hv_vcpu_uninit(vcpu);
9603 kvm_pmu_destroy(vcpu);
9604 kfree(vcpu->arch.mce_banks);
9605 kvm_free_lapic(vcpu);
9606 idx = srcu_read_lock(&vcpu->kvm->srcu);
9607 kvm_mmu_destroy(vcpu);
9608 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9609 free_page((unsigned long)vcpu->arch.pio_data);
9610 if (!lapic_in_kernel(vcpu))
9611 static_key_slow_dec(&kvm_no_apic_vcpu);
9614 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9616 kvm_lapic_reset(vcpu, init_event);
9618 vcpu->arch.hflags = 0;
9620 vcpu->arch.smi_pending = 0;
9621 vcpu->arch.smi_count = 0;
9622 atomic_set(&vcpu->arch.nmi_queued, 0);
9623 vcpu->arch.nmi_pending = 0;
9624 vcpu->arch.nmi_injected = false;
9625 kvm_clear_interrupt_queue(vcpu);
9626 kvm_clear_exception_queue(vcpu);
9628 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9629 kvm_update_dr0123(vcpu);
9630 vcpu->arch.dr6 = DR6_INIT;
9631 vcpu->arch.dr7 = DR7_FIXED_1;
9632 kvm_update_dr7(vcpu);
9636 kvm_make_request(KVM_REQ_EVENT, vcpu);
9637 vcpu->arch.apf.msr_en_val = 0;
9638 vcpu->arch.apf.msr_int_val = 0;
9639 vcpu->arch.st.msr_val = 0;
9641 kvmclock_reset(vcpu);
9643 kvm_clear_async_pf_completion_queue(vcpu);
9644 kvm_async_pf_hash_reset(vcpu);
9645 vcpu->arch.apf.halted = false;
9647 if (kvm_mpx_supported()) {
9648 void *mpx_state_buffer;
9651 * To avoid have the INIT path from kvm_apic_has_events() that be
9652 * called with loaded FPU and does not let userspace fix the state.
9655 kvm_put_guest_fpu(vcpu);
9656 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9658 if (mpx_state_buffer)
9659 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9660 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9662 if (mpx_state_buffer)
9663 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9665 kvm_load_guest_fpu(vcpu);
9669 kvm_pmu_reset(vcpu);
9670 vcpu->arch.smbase = 0x30000;
9672 vcpu->arch.msr_misc_features_enables = 0;
9674 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9677 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9678 vcpu->arch.regs_avail = ~0;
9679 vcpu->arch.regs_dirty = ~0;
9681 vcpu->arch.ia32_xss = 0;
9683 kvm_x86_ops.vcpu_reset(vcpu, init_event);
9686 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9688 struct kvm_segment cs;
9690 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9691 cs.selector = vector << 8;
9692 cs.base = vector << 12;
9693 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9694 kvm_rip_write(vcpu, 0);
9697 int kvm_arch_hardware_enable(void)
9700 struct kvm_vcpu *vcpu;
9705 bool stable, backwards_tsc = false;
9707 kvm_shared_msr_cpu_online();
9708 ret = kvm_x86_ops.hardware_enable();
9712 local_tsc = rdtsc();
9713 stable = !kvm_check_tsc_unstable();
9714 list_for_each_entry(kvm, &vm_list, vm_list) {
9715 kvm_for_each_vcpu(i, vcpu, kvm) {
9716 if (!stable && vcpu->cpu == smp_processor_id())
9717 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9718 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9719 backwards_tsc = true;
9720 if (vcpu->arch.last_host_tsc > max_tsc)
9721 max_tsc = vcpu->arch.last_host_tsc;
9727 * Sometimes, even reliable TSCs go backwards. This happens on
9728 * platforms that reset TSC during suspend or hibernate actions, but
9729 * maintain synchronization. We must compensate. Fortunately, we can
9730 * detect that condition here, which happens early in CPU bringup,
9731 * before any KVM threads can be running. Unfortunately, we can't
9732 * bring the TSCs fully up to date with real time, as we aren't yet far
9733 * enough into CPU bringup that we know how much real time has actually
9734 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9735 * variables that haven't been updated yet.
9737 * So we simply find the maximum observed TSC above, then record the
9738 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9739 * the adjustment will be applied. Note that we accumulate
9740 * adjustments, in case multiple suspend cycles happen before some VCPU
9741 * gets a chance to run again. In the event that no KVM threads get a
9742 * chance to run, we will miss the entire elapsed period, as we'll have
9743 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9744 * loose cycle time. This isn't too big a deal, since the loss will be
9745 * uniform across all VCPUs (not to mention the scenario is extremely
9746 * unlikely). It is possible that a second hibernate recovery happens
9747 * much faster than a first, causing the observed TSC here to be
9748 * smaller; this would require additional padding adjustment, which is
9749 * why we set last_host_tsc to the local tsc observed here.
9751 * N.B. - this code below runs only on platforms with reliable TSC,
9752 * as that is the only way backwards_tsc is set above. Also note
9753 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9754 * have the same delta_cyc adjustment applied if backwards_tsc
9755 * is detected. Note further, this adjustment is only done once,
9756 * as we reset last_host_tsc on all VCPUs to stop this from being
9757 * called multiple times (one for each physical CPU bringup).
9759 * Platforms with unreliable TSCs don't have to deal with this, they
9760 * will be compensated by the logic in vcpu_load, which sets the TSC to
9761 * catchup mode. This will catchup all VCPUs to real time, but cannot
9762 * guarantee that they stay in perfect synchronization.
9764 if (backwards_tsc) {
9765 u64 delta_cyc = max_tsc - local_tsc;
9766 list_for_each_entry(kvm, &vm_list, vm_list) {
9767 kvm->arch.backwards_tsc_observed = true;
9768 kvm_for_each_vcpu(i, vcpu, kvm) {
9769 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9770 vcpu->arch.last_host_tsc = local_tsc;
9771 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9775 * We have to disable TSC offset matching.. if you were
9776 * booting a VM while issuing an S4 host suspend....
9777 * you may have some problem. Solving this issue is
9778 * left as an exercise to the reader.
9780 kvm->arch.last_tsc_nsec = 0;
9781 kvm->arch.last_tsc_write = 0;
9788 void kvm_arch_hardware_disable(void)
9790 kvm_x86_ops.hardware_disable();
9791 drop_user_return_notifiers();
9794 int kvm_arch_hardware_setup(void *opaque)
9796 struct kvm_x86_init_ops *ops = opaque;
9799 rdmsrl_safe(MSR_EFER, &host_efer);
9801 if (boot_cpu_has(X86_FEATURE_XSAVES))
9802 rdmsrl(MSR_IA32_XSS, host_xss);
9804 r = ops->hardware_setup();
9808 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
9810 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
9813 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
9814 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
9815 #undef __kvm_cpu_cap_has
9817 if (kvm_has_tsc_control) {
9819 * Make sure the user can only configure tsc_khz values that
9820 * fit into a signed integer.
9821 * A min value is not calculated because it will always
9822 * be 1 on all machines.
9824 u64 max = min(0x7fffffffULL,
9825 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9826 kvm_max_guest_tsc_khz = max;
9828 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9831 kvm_init_msr_list();
9835 void kvm_arch_hardware_unsetup(void)
9837 kvm_x86_ops.hardware_unsetup();
9840 int kvm_arch_check_processor_compat(void *opaque)
9842 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
9843 struct kvm_x86_init_ops *ops = opaque;
9845 WARN_ON(!irqs_disabled());
9847 if (__cr4_reserved_bits(cpu_has, c) !=
9848 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
9851 return ops->check_processor_compatibility();
9854 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9856 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9858 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9860 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9862 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9865 struct static_key kvm_no_apic_vcpu __read_mostly;
9866 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9868 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9870 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
9872 vcpu->arch.l1tf_flush_l1d = true;
9873 if (pmu->version && unlikely(pmu->event_count)) {
9874 pmu->need_cleanup = true;
9875 kvm_make_request(KVM_REQ_PMU, vcpu);
9877 kvm_x86_ops.sched_in(vcpu, cpu);
9880 void kvm_arch_free_vm(struct kvm *kvm)
9882 kfree(kvm->arch.hyperv.hv_pa_pg);
9887 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9892 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9893 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9894 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9895 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
9896 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9897 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9899 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9900 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9901 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9902 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9903 &kvm->arch.irq_sources_bitmap);
9905 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9906 mutex_init(&kvm->arch.apic_map_lock);
9907 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9909 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
9910 pvclock_update_vm_gtod_copy(kvm);
9912 kvm->arch.guest_can_read_msr_platform_info = true;
9914 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9915 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9917 kvm_hv_init_vm(kvm);
9918 kvm_page_track_init(kvm);
9919 kvm_mmu_init_vm(kvm);
9921 return kvm_x86_ops.vm_init(kvm);
9924 int kvm_arch_post_init_vm(struct kvm *kvm)
9926 return kvm_mmu_post_init_vm(kvm);
9929 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9932 kvm_mmu_unload(vcpu);
9936 static void kvm_free_vcpus(struct kvm *kvm)
9939 struct kvm_vcpu *vcpu;
9942 * Unpin any mmu pages first.
9944 kvm_for_each_vcpu(i, vcpu, kvm) {
9945 kvm_clear_async_pf_completion_queue(vcpu);
9946 kvm_unload_vcpu_mmu(vcpu);
9948 kvm_for_each_vcpu(i, vcpu, kvm)
9949 kvm_vcpu_destroy(vcpu);
9951 mutex_lock(&kvm->lock);
9952 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9953 kvm->vcpus[i] = NULL;
9955 atomic_set(&kvm->online_vcpus, 0);
9956 mutex_unlock(&kvm->lock);
9959 void kvm_arch_sync_events(struct kvm *kvm)
9961 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9962 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9966 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9969 unsigned long hva, old_npages;
9970 struct kvm_memslots *slots = kvm_memslots(kvm);
9971 struct kvm_memory_slot *slot;
9973 /* Called with kvm->slots_lock held. */
9974 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9977 slot = id_to_memslot(slots, id);
9979 if (slot && slot->npages)
9983 * MAP_SHARED to prevent internal slot pages from being moved
9986 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9987 MAP_SHARED | MAP_ANONYMOUS, 0);
9988 if (IS_ERR((void *)hva))
9989 return PTR_ERR((void *)hva);
9991 if (!slot || !slot->npages)
9994 old_npages = slot->npages;
9998 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9999 struct kvm_userspace_memory_region m;
10001 m.slot = id | (i << 16);
10003 m.guest_phys_addr = gpa;
10004 m.userspace_addr = hva;
10005 m.memory_size = size;
10006 r = __kvm_set_memory_region(kvm, &m);
10012 vm_munmap(hva, old_npages * PAGE_SIZE);
10016 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
10018 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
10020 kvm_mmu_pre_destroy_vm(kvm);
10023 void kvm_arch_destroy_vm(struct kvm *kvm)
10025 if (current->mm == kvm->mm) {
10027 * Free memory regions allocated on behalf of userspace,
10028 * unless the the memory map has changed due to process exit
10031 mutex_lock(&kvm->slots_lock);
10032 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
10034 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
10036 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
10037 mutex_unlock(&kvm->slots_lock);
10039 if (kvm_x86_ops.vm_destroy)
10040 kvm_x86_ops.vm_destroy(kvm);
10041 kvm_pic_destroy(kvm);
10042 kvm_ioapic_destroy(kvm);
10043 kvm_free_vcpus(kvm);
10044 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
10045 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
10046 kvm_mmu_uninit_vm(kvm);
10047 kvm_page_track_cleanup(kvm);
10048 kvm_hv_destroy_vm(kvm);
10051 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
10055 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10056 kvfree(slot->arch.rmap[i]);
10057 slot->arch.rmap[i] = NULL;
10062 kvfree(slot->arch.lpage_info[i - 1]);
10063 slot->arch.lpage_info[i - 1] = NULL;
10066 kvm_page_track_free_memslot(slot);
10069 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
10070 unsigned long npages)
10075 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
10076 * old arrays will be freed by __kvm_set_memory_region() if installing
10077 * the new memslot is successful.
10079 memset(&slot->arch, 0, sizeof(slot->arch));
10081 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10082 struct kvm_lpage_info *linfo;
10083 unsigned long ugfn;
10087 lpages = gfn_to_index(slot->base_gfn + npages - 1,
10088 slot->base_gfn, level) + 1;
10090 slot->arch.rmap[i] =
10091 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
10092 GFP_KERNEL_ACCOUNT);
10093 if (!slot->arch.rmap[i])
10098 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
10102 slot->arch.lpage_info[i - 1] = linfo;
10104 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
10105 linfo[0].disallow_lpage = 1;
10106 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
10107 linfo[lpages - 1].disallow_lpage = 1;
10108 ugfn = slot->userspace_addr >> PAGE_SHIFT;
10110 * If the gfn and userspace address are not aligned wrt each
10111 * other, disable large page support for this slot.
10113 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
10116 for (j = 0; j < lpages; ++j)
10117 linfo[j].disallow_lpage = 1;
10121 if (kvm_page_track_create_memslot(slot, npages))
10127 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10128 kvfree(slot->arch.rmap[i]);
10129 slot->arch.rmap[i] = NULL;
10133 kvfree(slot->arch.lpage_info[i - 1]);
10134 slot->arch.lpage_info[i - 1] = NULL;
10139 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
10141 struct kvm_vcpu *vcpu;
10145 * memslots->generation has been incremented.
10146 * mmio generation may have reached its maximum value.
10148 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
10150 /* Force re-initialization of steal_time cache */
10151 kvm_for_each_vcpu(i, vcpu, kvm)
10152 kvm_vcpu_kick(vcpu);
10155 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10156 struct kvm_memory_slot *memslot,
10157 const struct kvm_userspace_memory_region *mem,
10158 enum kvm_mr_change change)
10160 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10161 return kvm_alloc_memslot_metadata(memslot,
10162 mem->memory_size >> PAGE_SHIFT);
10166 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10167 struct kvm_memory_slot *old,
10168 struct kvm_memory_slot *new,
10169 enum kvm_mr_change change)
10172 * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot.
10173 * See comments below.
10175 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY))
10179 * Dirty logging tracks sptes in 4k granularity, meaning that large
10180 * sptes have to be split. If live migration is successful, the guest
10181 * in the source machine will be destroyed and large sptes will be
10182 * created in the destination. However, if the guest continues to run
10183 * in the source machine (for example if live migration fails), small
10184 * sptes will remain around and cause bad performance.
10186 * Scan sptes if dirty logging has been stopped, dropping those
10187 * which can be collapsed into a single large-page spte. Later
10188 * page faults will create the large-page sptes.
10190 * There is no need to do this in any of the following cases:
10191 * CREATE: No dirty mappings will already exist.
10192 * MOVE/DELETE: The old mappings will already have been cleaned up by
10193 * kvm_arch_flush_shadow_memslot()
10195 if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10196 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10197 kvm_mmu_zap_collapsible_sptes(kvm, new);
10200 * Enable or disable dirty logging for the slot.
10202 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old
10203 * slot have been zapped so no dirty logging updates are needed for
10205 * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible
10206 * any mappings that might be created in it will consume the
10207 * properties of the new slot and do not need to be updated here.
10209 * When PML is enabled, the kvm_x86_ops dirty logging hooks are
10210 * called to enable/disable dirty logging.
10212 * When disabling dirty logging with PML enabled, the D-bit is set
10213 * for sptes in the slot in order to prevent unnecessary GPA
10214 * logging in the PML buffer (and potential PML buffer full VMEXIT).
10215 * This guarantees leaving PML enabled for the guest's lifetime
10216 * won't have any additional overhead from PML when the guest is
10217 * running with dirty logging disabled.
10219 * When enabling dirty logging, large sptes are write-protected
10220 * so they can be split on first write. New large sptes cannot
10221 * be created for this slot until the end of the logging.
10222 * See the comments in fast_page_fault().
10223 * For small sptes, nothing is done if the dirty log is in the
10224 * initial-all-set state. Otherwise, depending on whether pml
10225 * is enabled the D-bit or the W-bit will be cleared.
10227 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10228 if (kvm_x86_ops.slot_enable_log_dirty) {
10229 kvm_x86_ops.slot_enable_log_dirty(kvm, new);
10232 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10233 PG_LEVEL_2M : PG_LEVEL_4K;
10236 * If we're with initial-all-set, we don't need
10237 * to write protect any small page because
10238 * they're reported as dirty already. However
10239 * we still need to write-protect huge pages
10240 * so that the page split can happen lazily on
10241 * the first write to the huge page.
10243 kvm_mmu_slot_remove_write_access(kvm, new, level);
10246 if (kvm_x86_ops.slot_disable_log_dirty)
10247 kvm_x86_ops.slot_disable_log_dirty(kvm, new);
10251 void kvm_arch_commit_memory_region(struct kvm *kvm,
10252 const struct kvm_userspace_memory_region *mem,
10253 struct kvm_memory_slot *old,
10254 const struct kvm_memory_slot *new,
10255 enum kvm_mr_change change)
10257 if (!kvm->arch.n_requested_mmu_pages)
10258 kvm_mmu_change_mmu_pages(kvm,
10259 kvm_mmu_calculate_default_mmu_pages(kvm));
10262 * FIXME: const-ify all uses of struct kvm_memory_slot.
10264 kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change);
10266 /* Free the arrays associated with the old memslot. */
10267 if (change == KVM_MR_MOVE)
10268 kvm_arch_free_memslot(kvm, old);
10271 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10273 kvm_mmu_zap_all(kvm);
10276 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10277 struct kvm_memory_slot *slot)
10279 kvm_page_track_flush_slot(kvm, slot);
10282 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10284 return (is_guest_mode(vcpu) &&
10285 kvm_x86_ops.guest_apic_has_interrupt &&
10286 kvm_x86_ops.guest_apic_has_interrupt(vcpu));
10289 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10291 if (!list_empty_careful(&vcpu->async_pf.done))
10294 if (kvm_apic_has_events(vcpu))
10297 if (vcpu->arch.pv.pv_unhalted)
10300 if (vcpu->arch.exception.pending)
10303 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10304 (vcpu->arch.nmi_pending &&
10305 kvm_x86_ops.nmi_allowed(vcpu, false)))
10308 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10309 (vcpu->arch.smi_pending &&
10310 kvm_x86_ops.smi_allowed(vcpu, false)))
10313 if (kvm_arch_interrupt_allowed(vcpu) &&
10314 (kvm_cpu_has_interrupt(vcpu) ||
10315 kvm_guest_apic_has_interrupt(vcpu)))
10318 if (kvm_hv_has_stimer_pending(vcpu))
10321 if (is_guest_mode(vcpu) &&
10322 kvm_x86_ops.nested_ops->hv_timer_pending &&
10323 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
10329 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10331 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10334 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10336 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10339 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10340 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10341 kvm_test_request(KVM_REQ_EVENT, vcpu))
10344 if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu))
10350 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10352 return vcpu->arch.preempted_in_kernel;
10355 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10357 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10360 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10362 return kvm_x86_ops.interrupt_allowed(vcpu, false);
10365 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10367 if (is_64_bit_mode(vcpu))
10368 return kvm_rip_read(vcpu);
10369 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10370 kvm_rip_read(vcpu));
10372 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10374 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10376 return kvm_get_linear_rip(vcpu) == linear_rip;
10378 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10380 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10382 unsigned long rflags;
10384 rflags = kvm_x86_ops.get_rflags(vcpu);
10385 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10386 rflags &= ~X86_EFLAGS_TF;
10389 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10391 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10393 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10394 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10395 rflags |= X86_EFLAGS_TF;
10396 kvm_x86_ops.set_rflags(vcpu, rflags);
10399 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10401 __kvm_set_rflags(vcpu, rflags);
10402 kvm_make_request(KVM_REQ_EVENT, vcpu);
10404 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10406 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10410 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10414 r = kvm_mmu_reload(vcpu);
10418 if (!vcpu->arch.mmu->direct_map &&
10419 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10422 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10425 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10427 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
10429 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10432 static inline u32 kvm_async_pf_next_probe(u32 key)
10434 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
10437 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10439 u32 key = kvm_async_pf_hash_fn(gfn);
10441 while (vcpu->arch.apf.gfns[key] != ~0)
10442 key = kvm_async_pf_next_probe(key);
10444 vcpu->arch.apf.gfns[key] = gfn;
10447 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10450 u32 key = kvm_async_pf_hash_fn(gfn);
10452 for (i = 0; i < ASYNC_PF_PER_VCPU &&
10453 (vcpu->arch.apf.gfns[key] != gfn &&
10454 vcpu->arch.apf.gfns[key] != ~0); i++)
10455 key = kvm_async_pf_next_probe(key);
10460 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10462 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10465 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10469 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10471 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
10475 vcpu->arch.apf.gfns[i] = ~0;
10477 j = kvm_async_pf_next_probe(j);
10478 if (vcpu->arch.apf.gfns[j] == ~0)
10480 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10482 * k lies cyclically in ]i,j]
10484 * |....j i.k.| or |.k..j i...|
10486 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10487 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10492 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
10494 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
10496 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
10500 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
10502 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
10504 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
10505 &token, offset, sizeof(token));
10508 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
10510 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
10513 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
10514 &val, offset, sizeof(val)))
10520 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10522 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10525 if (!kvm_pv_async_pf_enabled(vcpu) ||
10526 (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0))
10532 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10534 if (unlikely(!lapic_in_kernel(vcpu) ||
10535 kvm_event_needs_reinjection(vcpu) ||
10536 vcpu->arch.exception.pending))
10539 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10543 * If interrupts are off we cannot even use an artificial
10546 return kvm_arch_interrupt_allowed(vcpu);
10549 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10550 struct kvm_async_pf *work)
10552 struct x86_exception fault;
10554 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10555 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10557 if (kvm_can_deliver_async_pf(vcpu) &&
10558 !apf_put_user_notpresent(vcpu)) {
10559 fault.vector = PF_VECTOR;
10560 fault.error_code_valid = true;
10561 fault.error_code = 0;
10562 fault.nested_page_fault = false;
10563 fault.address = work->arch.token;
10564 fault.async_page_fault = true;
10565 kvm_inject_page_fault(vcpu, &fault);
10569 * It is not possible to deliver a paravirtualized asynchronous
10570 * page fault, but putting the guest in an artificial halt state
10571 * can be beneficial nevertheless: if an interrupt arrives, we
10572 * can deliver it timely and perhaps the guest will schedule
10573 * another process. When the instruction that triggered a page
10574 * fault is retried, hopefully the page will be ready in the host.
10576 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10581 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10582 struct kvm_async_pf *work)
10584 struct kvm_lapic_irq irq = {
10585 .delivery_mode = APIC_DM_FIXED,
10586 .vector = vcpu->arch.apf.vec
10589 if (work->wakeup_all)
10590 work->arch.token = ~0; /* broadcast wakeup */
10592 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10593 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
10595 if ((work->wakeup_all || work->notpresent_injected) &&
10596 kvm_pv_async_pf_enabled(vcpu) &&
10597 !apf_put_user_ready(vcpu, work->arch.token)) {
10598 vcpu->arch.apf.pageready_pending = true;
10599 kvm_apic_set_irq(vcpu, &irq, NULL);
10602 vcpu->arch.apf.halted = false;
10603 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10606 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
10608 kvm_make_request(KVM_REQ_APF_READY, vcpu);
10609 if (!vcpu->arch.apf.pageready_pending)
10610 kvm_vcpu_kick(vcpu);
10613 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
10615 if (!kvm_pv_async_pf_enabled(vcpu))
10618 return apf_pageready_slot_free(vcpu);
10621 void kvm_arch_start_assignment(struct kvm *kvm)
10623 atomic_inc(&kvm->arch.assigned_device_count);
10625 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10627 void kvm_arch_end_assignment(struct kvm *kvm)
10629 atomic_dec(&kvm->arch.assigned_device_count);
10631 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10633 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10635 return atomic_read(&kvm->arch.assigned_device_count);
10637 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10639 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10641 atomic_inc(&kvm->arch.noncoherent_dma_count);
10643 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10645 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10647 atomic_dec(&kvm->arch.noncoherent_dma_count);
10649 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10651 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10653 return atomic_read(&kvm->arch.noncoherent_dma_count);
10655 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10657 bool kvm_arch_has_irq_bypass(void)
10662 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10663 struct irq_bypass_producer *prod)
10665 struct kvm_kernel_irqfd *irqfd =
10666 container_of(cons, struct kvm_kernel_irqfd, consumer);
10669 irqfd->producer = prod;
10670 kvm_arch_start_assignment(irqfd->kvm);
10671 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm,
10672 prod->irq, irqfd->gsi, 1);
10675 kvm_arch_end_assignment(irqfd->kvm);
10680 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10681 struct irq_bypass_producer *prod)
10684 struct kvm_kernel_irqfd *irqfd =
10685 container_of(cons, struct kvm_kernel_irqfd, consumer);
10687 WARN_ON(irqfd->producer != prod);
10688 irqfd->producer = NULL;
10691 * When producer of consumer is unregistered, we change back to
10692 * remapped mode, so we can re-use the current implementation
10693 * when the irq is masked/disabled or the consumer side (KVM
10694 * int this case doesn't want to receive the interrupts.
10696 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10698 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10699 " fails: %d\n", irqfd->consumer.token, ret);
10701 kvm_arch_end_assignment(irqfd->kvm);
10704 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10705 uint32_t guest_irq, bool set)
10707 return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set);
10710 bool kvm_vector_hashing_enabled(void)
10712 return vector_hashing;
10715 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10717 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10719 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10722 int kvm_spec_ctrl_test_value(u64 value)
10725 * test that setting IA32_SPEC_CTRL to given value
10726 * is allowed by the host processor
10730 unsigned long flags;
10733 local_irq_save(flags);
10735 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
10737 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
10740 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
10742 local_irq_restore(flags);
10746 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
10748 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
10750 struct x86_exception fault;
10751 u32 access = error_code &
10752 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
10754 if (!(error_code & PFERR_PRESENT_MASK) ||
10755 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) {
10757 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
10758 * tables probably do not match the TLB. Just proceed
10759 * with the error code that the processor gave.
10761 fault.vector = PF_VECTOR;
10762 fault.error_code_valid = true;
10763 fault.error_code = error_code;
10764 fault.nested_page_fault = false;
10765 fault.address = gva;
10767 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
10769 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
10771 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10772 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10773 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10774 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10775 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10776 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10777 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10778 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10779 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10780 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10781 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10782 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10783 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10784 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10785 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10786 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10787 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10788 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10789 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10790 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
10791 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
10792 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);