arch/x86/kvm/x86.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * derived from drivers/kvm/kvm_main.c
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright (C) 2008 Qumranet, Inc.
   9  * Copyright IBM Corporation, 2008
  10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  11  *
  12  * Authors:
  13  *   Avi Kivity   <avi@qumranet.com>
  14  *   Yaniv Kamay  <yaniv@qumranet.com>
  15  *   Amit Shah    <amit.shah@qumranet.com>
  16  *   Ben-Ami Yassour <benami@il.ibm.com>
  17  */
  18
  19 #include <linux/kvm_host.h>
  20 #include "irq.h"
  21 #include "mmu.h"
  22 #include "i8254.h"
  23 #include "tss.h"
  24 #include "kvm_cache_regs.h"
  25 #include "kvm_emulate.h"
  26 #include "x86.h"
  27 #include "cpuid.h"
  28 #include "pmu.h"
  29 #include "hyperv.h"
  30 #include "lapic.h"
  31
  32 #include <linux/clocksource.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/kvm.h>
  35 #include <linux/fs.h>
  36 #include <linux/vmalloc.h>
  37 #include <linux/export.h>
  38 #include <linux/moduleparam.h>
  39 #include <linux/mman.h>
  40 #include <linux/highmem.h>
  41 #include <linux/iommu.h>
  42 #include <linux/intel-iommu.h>
  43 #include <linux/cpufreq.h>
  44 #include <linux/user-return-notifier.h>
  45 #include <linux/srcu.h>
  46 #include <linux/slab.h>
  47 #include <linux/perf_event.h>
  48 #include <linux/uaccess.h>
  49 #include <linux/hash.h>
  50 #include <linux/pci.h>
  51 #include <linux/timekeeper_internal.h>
  52 #include <linux/pvclock_gtod.h>
  53 #include <linux/kvm_irqfd.h>
  54 #include <linux/irqbypass.h>
  55 #include <linux/sched/stat.h>
  56 #include <linux/sched/isolation.h>
  57 #include <linux/mem_encrypt.h>
  58
  59 #include <trace/events/kvm.h>
  60
  61 #include <asm/debugreg.h>
  62 #include <asm/msr.h>
  63 #include <asm/desc.h>
  64 #include <asm/mce.h>
  65 #include <linux/kernel_stat.h>
  66 #include <asm/fpu/internal.h> /* Ugh! */
  67 #include <asm/pvclock.h>
  68 #include <asm/div64.h>
  69 #include <asm/irq_remapping.h>
  70 #include <asm/mshyperv.h>
  71 #include <asm/hypervisor.h>
  72 #include <asm/intel_pt.h>
  73 #include <asm/emulate_prefix.h>
  74 #include <clocksource/hyperv_timer.h>
  75
  76 #define CREATE_TRACE_POINTS
  77 #include "trace.h"
  78
  79 #define MAX_IO_MSRS 256
  80 #define KVM_MAX_MCE_BANKS 32
  81 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
  82 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
  83
  84 #define emul_to_vcpu(ctxt) \
  85         ((struct kvm_vcpu *)(ctxt)->vcpu)
  86
  87 /* EFER defaults:
  88  * - enable syscall per default because its emulated by KVM
  89  * - enable LME and LMA per default on 64 bit KVM
  90  */
  91 #ifdef CONFIG_X86_64
  92 static
  93 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
  94 #else
  95 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
  96 #endif
  97
  98 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
  99
 100 #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__
 101 #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__
 102
 103 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
 104                                     KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
 105
 106 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
 107 static void process_nmi(struct kvm_vcpu *vcpu);
 108 static void enter_smm(struct kvm_vcpu *vcpu);
 109 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
 110 static void store_regs(struct kvm_vcpu *vcpu);
 111 static int sync_regs(struct kvm_vcpu *vcpu);
 112
 113 struct kvm_x86_ops kvm_x86_ops __read_mostly;
 114 EXPORT_SYMBOL_GPL(kvm_x86_ops);
 115
 116 static bool __read_mostly ignore_msrs = 0;
 117 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
 118
 119 static bool __read_mostly report_ignored_msrs = true;
 120 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
 121
 122 unsigned int min_timer_period_us = 200;
 123 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
 124
 125 static bool __read_mostly kvmclock_periodic_sync = true;
 126 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
 127
 128 bool __read_mostly kvm_has_tsc_control;
 129 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
 130 u32  __read_mostly kvm_max_guest_tsc_khz;
 131 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
 132 u8   __read_mostly kvm_tsc_scaling_ratio_frac_bits;
 133 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
 134 u64  __read_mostly kvm_max_tsc_scaling_ratio;
 135 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
 136 u64 __read_mostly kvm_default_tsc_scaling_ratio;
 137 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
 138
 139 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
 140 static u32 __read_mostly tsc_tolerance_ppm = 250;
 141 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
 142
 143 /*
 144  * lapic timer advance (tscdeadline mode only) in nanoseconds.  '-1' enables
 145  * adaptive tuning starting from default advancment of 1000ns.  '0' disables
 146  * advancement entirely.  Any other value is used as-is and disables adaptive
 147  * tuning, i.e. allows priveleged userspace to set an exact advancement time.
 148  */
 149 static int __read_mostly lapic_timer_advance_ns = -1;
 150 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
 151
 152 static bool __read_mostly vector_hashing = true;
 153 module_param(vector_hashing, bool, S_IRUGO);
 154
 155 bool __read_mostly enable_vmware_backdoor = false;
 156 module_param(enable_vmware_backdoor, bool, S_IRUGO);
 157 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
 158
 159 static bool __read_mostly force_emulation_prefix = false;
 160 module_param(force_emulation_prefix, bool, S_IRUGO);
 161
 162 int __read_mostly pi_inject_timer = -1;
 163 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
 164
 165 #define KVM_NR_SHARED_MSRS 16
 166
 167 struct kvm_shared_msrs_global {
 168         int nr;
 169         u32 msrs[KVM_NR_SHARED_MSRS];
 170 };
 171
 172 struct kvm_shared_msrs {
 173         struct user_return_notifier urn;
 174         bool registered;
 175         struct kvm_shared_msr_values {
 176                 u64 host;
 177                 u64 curr;
 178         } values[KVM_NR_SHARED_MSRS];
 179 };
 180
 181 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
 182 static struct kvm_shared_msrs __percpu *shared_msrs;
 183
 184 #define KVM_SUPPORTED_XCR0     (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
 185                                 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
 186                                 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
 187                                 | XFEATURE_MASK_PKRU)
 188
 189 u64 __read_mostly host_efer;
 190 EXPORT_SYMBOL_GPL(host_efer);
 191
 192 static u64 __read_mostly host_xss;
 193 u64 __read_mostly supported_xss;
 194 EXPORT_SYMBOL_GPL(supported_xss);
 195
 196 struct kvm_stats_debugfs_item debugfs_entries[] = {
 197         { "pf_fixed", VCPU_STAT(pf_fixed) },
 198         { "pf_guest", VCPU_STAT(pf_guest) },
 199         { "tlb_flush", VCPU_STAT(tlb_flush) },
 200         { "invlpg", VCPU_STAT(invlpg) },
 201         { "exits", VCPU_STAT(exits) },
 202         { "io_exits", VCPU_STAT(io_exits) },
 203         { "mmio_exits", VCPU_STAT(mmio_exits) },
 204         { "signal_exits", VCPU_STAT(signal_exits) },
 205         { "irq_window", VCPU_STAT(irq_window_exits) },
 206         { "nmi_window", VCPU_STAT(nmi_window_exits) },
 207         { "halt_exits", VCPU_STAT(halt_exits) },
 208         { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
 209         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
 210         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
 211         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
 212         { "hypercalls", VCPU_STAT(hypercalls) },
 213         { "request_irq", VCPU_STAT(request_irq_exits) },
 214         { "irq_exits", VCPU_STAT(irq_exits) },
 215         { "host_state_reload", VCPU_STAT(host_state_reload) },
 216         { "fpu_reload", VCPU_STAT(fpu_reload) },
 217         { "insn_emulation", VCPU_STAT(insn_emulation) },
 218         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
 219         { "irq_injections", VCPU_STAT(irq_injections) },
 220         { "nmi_injections", VCPU_STAT(nmi_injections) },
 221         { "req_event", VCPU_STAT(req_event) },
 222         { "l1d_flush", VCPU_STAT(l1d_flush) },
 223         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
 224         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
 225         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
 226         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
 227         { "mmu_flooded", VM_STAT(mmu_flooded) },
 228         { "mmu_recycled", VM_STAT(mmu_recycled) },
 229         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
 230         { "mmu_unsync", VM_STAT(mmu_unsync) },
 231         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
 232         { "largepages", VM_STAT(lpages, .mode = 0444) },
 233         { "nx_largepages_splitted", VM_STAT(nx_lpage_splits, .mode = 0444) },
 234         { "max_mmu_page_hash_collisions",
 235                 VM_STAT(max_mmu_page_hash_collisions) },
 236         { NULL }
 237 };
 238
 239 u64 __read_mostly host_xcr0;
 240 u64 __read_mostly supported_xcr0;
 241 EXPORT_SYMBOL_GPL(supported_xcr0);
 242
 243 struct kmem_cache *x86_fpu_cache;
 244 EXPORT_SYMBOL_GPL(x86_fpu_cache);
 245
 246 static struct kmem_cache *x86_emulator_cache;
 247
 248 static struct kmem_cache *kvm_alloc_emulator_cache(void)
 249 {
 250         unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
 251         unsigned int size = sizeof(struct x86_emulate_ctxt);
 252
 253         return kmem_cache_create_usercopy("x86_emulator", size,
 254                                           __alignof__(struct x86_emulate_ctxt),
 255                                           SLAB_ACCOUNT, useroffset,
 256                                           size - useroffset, NULL);
 257 }
 258
 259 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
 260
 261 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
 262 {
 263         int i;
 264         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
 265                 vcpu->arch.apf.gfns[i] = ~0;
 266 }
 267
 268 static void kvm_on_user_return(struct user_return_notifier *urn)
 269 {
 270         unsigned slot;
 271         struct kvm_shared_msrs *locals
 272                 = container_of(urn, struct kvm_shared_msrs, urn);
 273         struct kvm_shared_msr_values *values;
 274         unsigned long flags;
 275
 276         /*
 277          * Disabling irqs at this point since the following code could be
 278          * interrupted and executed through kvm_arch_hardware_disable()
 279          */
 280         local_irq_save(flags);
 281         if (locals->registered) {
 282                 locals->registered = false;
 283                 user_return_notifier_unregister(urn);
 284         }
 285         local_irq_restore(flags);
 286         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
 287                 values = &locals->values[slot];
 288                 if (values->host != values->curr) {
 289                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
 290                         values->curr = values->host;
 291                 }
 292         }
 293 }
 294
 295 void kvm_define_shared_msr(unsigned slot, u32 msr)
 296 {
 297         BUG_ON(slot >= KVM_NR_SHARED_MSRS);
 298         shared_msrs_global.msrs[slot] = msr;
 299         if (slot >= shared_msrs_global.nr)
 300                 shared_msrs_global.nr = slot + 1;
 301 }
 302 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
 303
 304 static void kvm_shared_msr_cpu_online(void)
 305 {
 306         unsigned int cpu = smp_processor_id();
 307         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 308         u64 value;
 309         int i;
 310
 311         for (i = 0; i < shared_msrs_global.nr; ++i) {
 312                 rdmsrl_safe(shared_msrs_global.msrs[i], &value);
 313                 smsr->values[i].host = value;
 314                 smsr->values[i].curr = value;
 315         }
 316 }
 317
 318 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
 319 {
 320         unsigned int cpu = smp_processor_id();
 321         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 322         int err;
 323
 324         value = (value & mask) | (smsr->values[slot].host & ~mask);
 325         if (value == smsr->values[slot].curr)
 326                 return 0;
 327         err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
 328         if (err)
 329                 return 1;
 330
 331         smsr->values[slot].curr = value;
 332         if (!smsr->registered) {
 333                 smsr->urn.on_user_return = kvm_on_user_return;
 334                 user_return_notifier_register(&smsr->urn);
 335                 smsr->registered = true;
 336         }
 337         return 0;
 338 }
 339 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
 340
 341 static void drop_user_return_notifiers(void)
 342 {
 343         unsigned int cpu = smp_processor_id();
 344         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 345
 346         if (smsr->registered)
 347                 kvm_on_user_return(&smsr->urn);
 348 }
 349
 350 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
 351 {
 352         return vcpu->arch.apic_base;
 353 }
 354 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
 355
 356 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
 357 {
 358         return kvm_apic_mode(kvm_get_apic_base(vcpu));
 359 }
 360 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
 361
 362 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 363 {
 364         enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
 365         enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
 366         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
 367                 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
 368
 369         if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
 370                 return 1;
 371         if (!msr_info->host_initiated) {
 372                 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
 373                         return 1;
 374                 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
 375                         return 1;
 376         }
 377
 378         kvm_lapic_set_base(vcpu, msr_info->data);
 379         kvm_recalculate_apic_map(vcpu->kvm);
 380         return 0;
 381 }
 382 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
 383
 384 asmlinkage __visible void kvm_spurious_fault(void)
 385 {
 386         /* Fault while not rebooting.  We want the trace. */
 387         BUG_ON(!kvm_rebooting);
 388 }
 389 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
 390
 391 #define EXCPT_BENIGN            0
 392 #define EXCPT_CONTRIBUTORY      1
 393 #define EXCPT_PF                2
 394
 395 static int exception_class(int vector)
 396 {
 397         switch (vector) {
 398         case PF_VECTOR:
 399                 return EXCPT_PF;
 400         case DE_VECTOR:
 401         case TS_VECTOR:
 402         case NP_VECTOR:
 403         case SS_VECTOR:
 404         case GP_VECTOR:
 405                 return EXCPT_CONTRIBUTORY;
 406         default:
 407                 break;
 408         }
 409         return EXCPT_BENIGN;
 410 }
 411
 412 #define EXCPT_FAULT             0
 413 #define EXCPT_TRAP              1
 414 #define EXCPT_ABORT             2
 415 #define EXCPT_INTERRUPT         3
 416
 417 static int exception_type(int vector)
 418 {
 419         unsigned int mask;
 420
 421         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
 422                 return EXCPT_INTERRUPT;
 423
 424         mask = 1 << vector;
 425
 426         /* #DB is trap, as instruction watchpoints are handled elsewhere */
 427         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
 428                 return EXCPT_TRAP;
 429
 430         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
 431                 return EXCPT_ABORT;
 432
 433         /* Reserved exceptions will result in fault */
 434         return EXCPT_FAULT;
 435 }
 436
 437 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
 438 {
 439         unsigned nr = vcpu->arch.exception.nr;
 440         bool has_payload = vcpu->arch.exception.has_payload;
 441         unsigned long payload = vcpu->arch.exception.payload;
 442
 443         if (!has_payload)
 444                 return;
 445
 446         switch (nr) {
 447         case DB_VECTOR:
 448                 /*
 449                  * "Certain debug exceptions may clear bit 0-3.  The
 450                  * remaining contents of the DR6 register are never
 451                  * cleared by the processor".
 452                  */
 453                 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
 454                 /*
 455                  * DR6.RTM is set by all #DB exceptions that don't clear it.
 456                  */
 457                 vcpu->arch.dr6 |= DR6_RTM;
 458                 vcpu->arch.dr6 |= payload;
 459                 /*
 460                  * Bit 16 should be set in the payload whenever the #DB
 461                  * exception should clear DR6.RTM. This makes the payload
 462                  * compatible with the pending debug exceptions under VMX.
 463                  * Though not currently documented in the SDM, this also
 464                  * makes the payload compatible with the exit qualification
 465                  * for #DB exceptions under VMX.
 466                  */
 467                 vcpu->arch.dr6 ^= payload & DR6_RTM;
 468
 469                 /*
 470                  * The #DB payload is defined as compatible with the 'pending
 471                  * debug exceptions' field under VMX, not DR6. While bit 12 is
 472                  * defined in the 'pending debug exceptions' field (enabled
 473                  * breakpoint), it is reserved and must be zero in DR6.
 474                  */
 475                 vcpu->arch.dr6 &= ~BIT(12);
 476                 break;
 477         case PF_VECTOR:
 478                 vcpu->arch.cr2 = payload;
 479                 break;
 480         }
 481
 482         vcpu->arch.exception.has_payload = false;
 483         vcpu->arch.exception.payload = 0;
 484 }
 485 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
 486
 487 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
 488                 unsigned nr, bool has_error, u32 error_code,
 489                 bool has_payload, unsigned long payload, bool reinject)
 490 {
 491         u32 prev_nr;
 492         int class1, class2;
 493
 494         kvm_make_request(KVM_REQ_EVENT, vcpu);
 495
 496         if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
 497         queue:
 498                 if (has_error && !is_protmode(vcpu))
 499                         has_error = false;
 500                 if (reinject) {
 501                         /*
 502                          * On vmentry, vcpu->arch.exception.pending is only
 503                          * true if an event injection was blocked by
 504                          * nested_run_pending.  In that case, however,
 505                          * vcpu_enter_guest requests an immediate exit,
 506                          * and the guest shouldn't proceed far enough to
 507                          * need reinjection.
 508                          */
 509                         WARN_ON_ONCE(vcpu->arch.exception.pending);
 510                         vcpu->arch.exception.injected = true;
 511                         if (WARN_ON_ONCE(has_payload)) {
 512                                 /*
 513                                  * A reinjected event has already
 514                                  * delivered its payload.
 515                                  */
 516                                 has_payload = false;
 517                                 payload = 0;
 518                         }
 519                 } else {
 520                         vcpu->arch.exception.pending = true;
 521                         vcpu->arch.exception.injected = false;
 522                 }
 523                 vcpu->arch.exception.has_error_code = has_error;
 524                 vcpu->arch.exception.nr = nr;
 525                 vcpu->arch.exception.error_code = error_code;
 526                 vcpu->arch.exception.has_payload = has_payload;
 527                 vcpu->arch.exception.payload = payload;
 528                 if (!is_guest_mode(vcpu))
 529                         kvm_deliver_exception_payload(vcpu);
 530                 return;
 531         }
 532
 533         /* to check exception */
 534         prev_nr = vcpu->arch.exception.nr;
 535         if (prev_nr == DF_VECTOR) {
 536                 /* triple fault -> shutdown */
 537                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
 538                 return;
 539         }
 540         class1 = exception_class(prev_nr);
 541         class2 = exception_class(nr);
 542         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
 543                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
 544                 /*
 545                  * Generate double fault per SDM Table 5-5.  Set
 546                  * exception.pending = true so that the double fault
 547                  * can trigger a nested vmexit.
 548                  */
 549                 vcpu->arch.exception.pending = true;
 550                 vcpu->arch.exception.injected = false;
 551                 vcpu->arch.exception.has_error_code = true;
 552                 vcpu->arch.exception.nr = DF_VECTOR;
 553                 vcpu->arch.exception.error_code = 0;
 554                 vcpu->arch.exception.has_payload = false;
 555                 vcpu->arch.exception.payload = 0;
 556         } else
 557                 /* replace previous exception with a new one in a hope
 558                    that instruction re-execution will regenerate lost
 559                    exception */
 560                 goto queue;
 561 }
 562
 563 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 564 {
 565         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
 566 }
 567 EXPORT_SYMBOL_GPL(kvm_queue_exception);
 568
 569 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 570 {
 571         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
 572 }
 573 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
 574
 575 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
 576                            unsigned long payload)
 577 {
 578         kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
 579 }
 580 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
 581
 582 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
 583                                     u32 error_code, unsigned long payload)
 584 {
 585         kvm_multiple_exception(vcpu, nr, true, error_code,
 586                                true, payload, false);
 587 }
 588
 589 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
 590 {
 591         if (err)
 592                 kvm_inject_gp(vcpu, 0);
 593         else
 594                 return kvm_skip_emulated_instruction(vcpu);
 595
 596         return 1;
 597 }
 598 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
 599
 600 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 601 {
 602         ++vcpu->stat.pf_guest;
 603         vcpu->arch.exception.nested_apf =
 604                 is_guest_mode(vcpu) && fault->async_page_fault;
 605         if (vcpu->arch.exception.nested_apf) {
 606                 vcpu->arch.apf.nested_apf_token = fault->address;
 607                 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
 608         } else {
 609                 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
 610                                         fault->address);
 611         }
 612 }
 613 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
 614
 615 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 616 {
 617         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
 618                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
 619         else
 620                 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
 621
 622         return fault->nested_page_fault;
 623 }
 624
 625 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
 626 {
 627         atomic_inc(&vcpu->arch.nmi_queued);
 628         kvm_make_request(KVM_REQ_NMI, vcpu);
 629 }
 630 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
 631
 632 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 633 {
 634         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
 635 }
 636 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
 637
 638 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 639 {
 640         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
 641 }
 642 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
 643
 644 /*
 645  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
 646  * a #GP and return false.
 647  */
 648 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
 649 {
 650         if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl)
 651                 return true;
 652         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
 653         return false;
 654 }
 655 EXPORT_SYMBOL_GPL(kvm_require_cpl);
 656
 657 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
 658 {
 659         if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 660                 return true;
 661
 662         kvm_queue_exception(vcpu, UD_VECTOR);
 663         return false;
 664 }
 665 EXPORT_SYMBOL_GPL(kvm_require_dr);
 666
 667 /*
 668  * This function will be used to read from the physical memory of the currently
 669  * running guest. The difference to kvm_vcpu_read_guest_page is that this function
 670  * can read from guest physical or from the guest's guest physical memory.
 671  */
 672 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 673                             gfn_t ngfn, void *data, int offset, int len,
 674                             u32 access)
 675 {
 676         struct x86_exception exception;
 677         gfn_t real_gfn;
 678         gpa_t ngpa;
 679
 680         ngpa     = gfn_to_gpa(ngfn);
 681         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
 682         if (real_gfn == UNMAPPED_GVA)
 683                 return -EFAULT;
 684
 685         real_gfn = gpa_to_gfn(real_gfn);
 686
 687         return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
 688 }
 689 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
 690
 691 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
 692                                void *data, int offset, int len, u32 access)
 693 {
 694         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
 695                                        data, offset, len, access);
 696 }
 697
 698 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
 699 {
 700         return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
 701                rsvd_bits(1, 2);
 702 }
 703
 704 /*
 705  * Load the pae pdptrs.  Return 1 if they are all valid, 0 otherwise.
 706  */
 707 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
 708 {
 709         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
 710         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
 711         int i;
 712         int ret;
 713         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
 714
 715         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
 716                                       offset * sizeof(u64), sizeof(pdpte),
 717                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
 718         if (ret < 0) {
 719                 ret = 0;
 720                 goto out;
 721         }
 722         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
 723                 if ((pdpte[i] & PT_PRESENT_MASK) &&
 724                     (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
 725                         ret = 0;
 726                         goto out;
 727                 }
 728         }
 729         ret = 1;
 730
 731         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
 732         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
 733
 734 out:
 735
 736         return ret;
 737 }
 738 EXPORT_SYMBOL_GPL(load_pdptrs);
 739
 740 bool pdptrs_changed(struct kvm_vcpu *vcpu)
 741 {
 742         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
 743         int offset;
 744         gfn_t gfn;
 745         int r;
 746
 747         if (!is_pae_paging(vcpu))
 748                 return false;
 749
 750         if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
 751                 return true;
 752
 753         gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
 754         offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
 755         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
 756                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
 757         if (r < 0)
 758                 return true;
 759
 760         return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
 761 }
 762 EXPORT_SYMBOL_GPL(pdptrs_changed);
 763
 764 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 765 {
 766         unsigned long old_cr0 = kvm_read_cr0(vcpu);
 767         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
 768
 769         cr0 |= X86_CR0_ET;
 770
 771 #ifdef CONFIG_X86_64
 772         if (cr0 & 0xffffffff00000000UL)
 773                 return 1;
 774 #endif
 775
 776         cr0 &= ~CR0_RESERVED_BITS;
 777
 778         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
 779                 return 1;
 780
 781         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
 782                 return 1;
 783
 784         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 785 #ifdef CONFIG_X86_64
 786                 if ((vcpu->arch.efer & EFER_LME)) {
 787                         int cs_db, cs_l;
 788
 789                         if (!is_pae(vcpu))
 790                                 return 1;
 791                         kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
 792                         if (cs_l)
 793                                 return 1;
 794                 } else
 795 #endif
 796                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 797                                                  kvm_read_cr3(vcpu)))
 798                         return 1;
 799         }
 800
 801         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
 802                 return 1;
 803
 804         kvm_x86_ops.set_cr0(vcpu, cr0);
 805
 806         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
 807                 kvm_clear_async_pf_completion_queue(vcpu);
 808                 kvm_async_pf_hash_reset(vcpu);
 809         }
 810
 811         if ((cr0 ^ old_cr0) & update_bits)
 812                 kvm_mmu_reset_context(vcpu);
 813
 814         if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
 815             kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
 816             !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
 817                 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
 818
 819         return 0;
 820 }
 821 EXPORT_SYMBOL_GPL(kvm_set_cr0);
 822
 823 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 824 {
 825         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
 826 }
 827 EXPORT_SYMBOL_GPL(kvm_lmsw);
 828
 829 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
 830 {
 831         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
 832
 833                 if (vcpu->arch.xcr0 != host_xcr0)
 834                         xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
 835
 836                 if (vcpu->arch.xsaves_enabled &&
 837                     vcpu->arch.ia32_xss != host_xss)
 838                         wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
 839         }
 840
 841         if (static_cpu_has(X86_FEATURE_PKU) &&
 842             (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
 843              (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
 844             vcpu->arch.pkru != vcpu->arch.host_pkru)
 845                 __write_pkru(vcpu->arch.pkru);
 846 }
 847 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
 848
 849 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
 850 {
 851         if (static_cpu_has(X86_FEATURE_PKU) &&
 852             (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
 853              (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
 854                 vcpu->arch.pkru = rdpkru();
 855                 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
 856                         __write_pkru(vcpu->arch.host_pkru);
 857         }
 858
 859         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
 860
 861                 if (vcpu->arch.xcr0 != host_xcr0)
 862                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
 863
 864                 if (vcpu->arch.xsaves_enabled &&
 865                     vcpu->arch.ia32_xss != host_xss)
 866                         wrmsrl(MSR_IA32_XSS, host_xss);
 867         }
 868
 869 }
 870 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
 871
 872 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 873 {
 874         u64 xcr0 = xcr;
 875         u64 old_xcr0 = vcpu->arch.xcr0;
 876         u64 valid_bits;
 877
 878         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
 879         if (index != XCR_XFEATURE_ENABLED_MASK)
 880                 return 1;
 881         if (!(xcr0 & XFEATURE_MASK_FP))
 882                 return 1;
 883         if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
 884                 return 1;
 885
 886         /*
 887          * Do not allow the guest to set bits that we do not support
 888          * saving.  However, xcr0 bit 0 is always set, even if the
 889          * emulated CPU does not support XSAVE (see fx_init).
 890          */
 891         valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
 892         if (xcr0 & ~valid_bits)
 893                 return 1;
 894
 895         if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
 896             (!(xcr0 & XFEATURE_MASK_BNDCSR)))
 897                 return 1;
 898
 899         if (xcr0 & XFEATURE_MASK_AVX512) {
 900                 if (!(xcr0 & XFEATURE_MASK_YMM))
 901                         return 1;
 902                 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
 903                         return 1;
 904         }
 905         vcpu->arch.xcr0 = xcr0;
 906
 907         if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
 908                 kvm_update_cpuid(vcpu);
 909         return 0;
 910 }
 911
 912 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 913 {
 914         if (kvm_x86_ops.get_cpl(vcpu) != 0 ||
 915             __kvm_set_xcr(vcpu, index, xcr)) {
 916                 kvm_inject_gp(vcpu, 0);
 917                 return 1;
 918         }
 919         return 0;
 920 }
 921 EXPORT_SYMBOL_GPL(kvm_set_xcr);
 922
 923 #define __cr4_reserved_bits(__cpu_has, __c)             \
 924 ({                                                      \
 925         u64 __reserved_bits = CR4_RESERVED_BITS;        \
 926                                                         \
 927         if (!__cpu_has(__c, X86_FEATURE_XSAVE))         \
 928                 __reserved_bits |= X86_CR4_OSXSAVE;     \
 929         if (!__cpu_has(__c, X86_FEATURE_SMEP))          \
 930                 __reserved_bits |= X86_CR4_SMEP;        \
 931         if (!__cpu_has(__c, X86_FEATURE_SMAP))          \
 932                 __reserved_bits |= X86_CR4_SMAP;        \
 933         if (!__cpu_has(__c, X86_FEATURE_FSGSBASE))      \
 934                 __reserved_bits |= X86_CR4_FSGSBASE;    \
 935         if (!__cpu_has(__c, X86_FEATURE_PKU))           \
 936                 __reserved_bits |= X86_CR4_PKE;         \
 937         if (!__cpu_has(__c, X86_FEATURE_LA57))          \
 938                 __reserved_bits |= X86_CR4_LA57;        \
 939         if (!__cpu_has(__c, X86_FEATURE_UMIP))          \
 940                 __reserved_bits |= X86_CR4_UMIP;        \
 941         __reserved_bits;                                \
 942 })
 943
 944 static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 945 {
 946         if (cr4 & cr4_reserved_bits)
 947                 return -EINVAL;
 948
 949         if (cr4 & __cr4_reserved_bits(guest_cpuid_has, vcpu))
 950                 return -EINVAL;
 951
 952         return 0;
 953 }
 954
 955 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 956 {
 957         unsigned long old_cr4 = kvm_read_cr4(vcpu);
 958         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
 959                                    X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
 960
 961         if (kvm_valid_cr4(vcpu, cr4))
 962                 return 1;
 963
 964         if (is_long_mode(vcpu)) {
 965                 if (!(cr4 & X86_CR4_PAE))
 966                         return 1;
 967         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
 968                    && ((cr4 ^ old_cr4) & pdptr_bits)
 969                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 970                                    kvm_read_cr3(vcpu)))
 971                 return 1;
 972
 973         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
 974                 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
 975                         return 1;
 976
 977                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
 978                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
 979                         return 1;
 980         }
 981
 982         if (kvm_x86_ops.set_cr4(vcpu, cr4))
 983                 return 1;
 984
 985         if (((cr4 ^ old_cr4) & pdptr_bits) ||
 986             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
 987                 kvm_mmu_reset_context(vcpu);
 988
 989         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
 990                 kvm_update_cpuid(vcpu);
 991
 992         return 0;
 993 }
 994 EXPORT_SYMBOL_GPL(kvm_set_cr4);
 995
 996 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
 997 {
 998         bool skip_tlb_flush = false;
 999 #ifdef CONFIG_X86_64
1000         bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1001
1002         if (pcid_enabled) {
1003                 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1004                 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1005         }
1006 #endif
1007
1008         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1009                 if (!skip_tlb_flush) {
1010                         kvm_mmu_sync_roots(vcpu);
1011                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1012                 }
1013                 return 0;
1014         }
1015
1016         if (is_long_mode(vcpu) &&
1017             (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
1018                 return 1;
1019         else if (is_pae_paging(vcpu) &&
1020                  !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1021                 return 1;
1022
1023         kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
1024         vcpu->arch.cr3 = cr3;
1025         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1026
1027         return 0;
1028 }
1029 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1030
1031 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1032 {
1033         if (cr8 & CR8_RESERVED_BITS)
1034                 return 1;
1035         if (lapic_in_kernel(vcpu))
1036                 kvm_lapic_set_tpr(vcpu, cr8);
1037         else
1038                 vcpu->arch.cr8 = cr8;
1039         return 0;
1040 }
1041 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1042
1043 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1044 {
1045         if (lapic_in_kernel(vcpu))
1046                 return kvm_lapic_get_cr8(vcpu);
1047         else
1048                 return vcpu->arch.cr8;
1049 }
1050 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1051
1052 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1053 {
1054         int i;
1055
1056         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1057                 for (i = 0; i < KVM_NR_DB_REGS; i++)
1058                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1059                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1060         }
1061 }
1062
1063 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1064 {
1065         unsigned long dr7;
1066
1067         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1068                 dr7 = vcpu->arch.guest_debug_dr7;
1069         else
1070                 dr7 = vcpu->arch.dr7;
1071         kvm_x86_ops.set_dr7(vcpu, dr7);
1072         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1073         if (dr7 & DR7_BP_EN_MASK)
1074                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1075 }
1076
1077 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1078 {
1079         u64 fixed = DR6_FIXED_1;
1080
1081         if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1082                 fixed |= DR6_RTM;
1083         return fixed;
1084 }
1085
1086 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1087 {
1088         size_t size = ARRAY_SIZE(vcpu->arch.db);
1089
1090         switch (dr) {
1091         case 0 ... 3:
1092                 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1093                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1094                         vcpu->arch.eff_db[dr] = val;
1095                 break;
1096         case 4:
1097                 /* fall through */
1098         case 6:
1099                 if (val & 0xffffffff00000000ULL)
1100                         return -1; /* #GP */
1101                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1102                 break;
1103         case 5:
1104                 /* fall through */
1105         default: /* 7 */
1106                 if (!kvm_dr7_valid(val))
1107                         return -1; /* #GP */
1108                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1109                 kvm_update_dr7(vcpu);
1110                 break;
1111         }
1112
1113         return 0;
1114 }
1115
1116 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1117 {
1118         if (__kvm_set_dr(vcpu, dr, val)) {
1119                 kvm_inject_gp(vcpu, 0);
1120                 return 1;
1121         }
1122         return 0;
1123 }
1124 EXPORT_SYMBOL_GPL(kvm_set_dr);
1125
1126 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1127 {
1128         size_t size = ARRAY_SIZE(vcpu->arch.db);
1129
1130         switch (dr) {
1131         case 0 ... 3:
1132                 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1133                 break;
1134         case 4:
1135                 /* fall through */
1136         case 6:
1137                 *val = vcpu->arch.dr6;
1138                 break;
1139         case 5:
1140                 /* fall through */
1141         default: /* 7 */
1142                 *val = vcpu->arch.dr7;
1143                 break;
1144         }
1145         return 0;
1146 }
1147 EXPORT_SYMBOL_GPL(kvm_get_dr);
1148
1149 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1150 {
1151         u32 ecx = kvm_rcx_read(vcpu);
1152         u64 data;
1153         int err;
1154
1155         err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1156         if (err)
1157                 return err;
1158         kvm_rax_write(vcpu, (u32)data);
1159         kvm_rdx_write(vcpu, data >> 32);
1160         return err;
1161 }
1162 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1163
1164 /*
1165  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1166  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1167  *
1168  * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1169  * extract the supported MSRs from the related const lists.
1170  * msrs_to_save is selected from the msrs_to_save_all to reflect the
1171  * capabilities of the host cpu. This capabilities test skips MSRs that are
1172  * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1173  * may depend on host virtualization features rather than host cpu features.
1174  */
1175
1176 static const u32 msrs_to_save_all[] = {
1177         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1178         MSR_STAR,
1179 #ifdef CONFIG_X86_64
1180         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1181 #endif
1182         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1183         MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1184         MSR_IA32_SPEC_CTRL,
1185         MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1186         MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1187         MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1188         MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1189         MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1190         MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1191         MSR_IA32_UMWAIT_CONTROL,
1192
1193         MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1194         MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1195         MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1196         MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1197         MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1198         MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1199         MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1200         MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1201         MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1202         MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1203         MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1204         MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1205         MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1206         MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1207         MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1208         MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1209         MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1210         MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1211         MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1212         MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1213         MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1214         MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1215 };
1216
1217 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1218 static unsigned num_msrs_to_save;
1219
1220 static const u32 emulated_msrs_all[] = {
1221         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1222         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1223         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1224         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1225         HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1226         HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1227         HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1228         HV_X64_MSR_RESET,
1229         HV_X64_MSR_VP_INDEX,
1230         HV_X64_MSR_VP_RUNTIME,
1231         HV_X64_MSR_SCONTROL,
1232         HV_X64_MSR_STIMER0_CONFIG,
1233         HV_X64_MSR_VP_ASSIST_PAGE,
1234         HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1235         HV_X64_MSR_TSC_EMULATION_STATUS,
1236
1237         MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1238         MSR_KVM_PV_EOI_EN,
1239
1240         MSR_IA32_TSC_ADJUST,
1241         MSR_IA32_TSCDEADLINE,
1242         MSR_IA32_ARCH_CAPABILITIES,
1243         MSR_IA32_MISC_ENABLE,
1244         MSR_IA32_MCG_STATUS,
1245         MSR_IA32_MCG_CTL,
1246         MSR_IA32_MCG_EXT_CTL,
1247         MSR_IA32_SMBASE,
1248         MSR_SMI_COUNT,
1249         MSR_PLATFORM_INFO,
1250         MSR_MISC_FEATURES_ENABLES,
1251         MSR_AMD64_VIRT_SPEC_CTRL,
1252         MSR_IA32_POWER_CTL,
1253         MSR_IA32_UCODE_REV,
1254
1255         /*
1256          * The following list leaves out MSRs whose values are determined
1257          * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1258          * We always support the "true" VMX control MSRs, even if the host
1259          * processor does not, so I am putting these registers here rather
1260          * than in msrs_to_save_all.
1261          */
1262         MSR_IA32_VMX_BASIC,
1263         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1264         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1265         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1266         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1267         MSR_IA32_VMX_MISC,
1268         MSR_IA32_VMX_CR0_FIXED0,
1269         MSR_IA32_VMX_CR4_FIXED0,
1270         MSR_IA32_VMX_VMCS_ENUM,
1271         MSR_IA32_VMX_PROCBASED_CTLS2,
1272         MSR_IA32_VMX_EPT_VPID_CAP,
1273         MSR_IA32_VMX_VMFUNC,
1274
1275         MSR_K7_HWCR,
1276         MSR_KVM_POLL_CONTROL,
1277 };
1278
1279 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1280 static unsigned num_emulated_msrs;
1281
1282 /*
1283  * List of msr numbers which are used to expose MSR-based features that
1284  * can be used by a hypervisor to validate requested CPU features.
1285  */
1286 static const u32 msr_based_features_all[] = {
1287         MSR_IA32_VMX_BASIC,
1288         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1289         MSR_IA32_VMX_PINBASED_CTLS,
1290         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1291         MSR_IA32_VMX_PROCBASED_CTLS,
1292         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1293         MSR_IA32_VMX_EXIT_CTLS,
1294         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1295         MSR_IA32_VMX_ENTRY_CTLS,
1296         MSR_IA32_VMX_MISC,
1297         MSR_IA32_VMX_CR0_FIXED0,
1298         MSR_IA32_VMX_CR0_FIXED1,
1299         MSR_IA32_VMX_CR4_FIXED0,
1300         MSR_IA32_VMX_CR4_FIXED1,
1301         MSR_IA32_VMX_VMCS_ENUM,
1302         MSR_IA32_VMX_PROCBASED_CTLS2,
1303         MSR_IA32_VMX_EPT_VPID_CAP,
1304         MSR_IA32_VMX_VMFUNC,
1305
1306         MSR_F10H_DECFG,
1307         MSR_IA32_UCODE_REV,
1308         MSR_IA32_ARCH_CAPABILITIES,
1309 };
1310
1311 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1312 static unsigned int num_msr_based_features;
1313
1314 static u64 kvm_get_arch_capabilities(void)
1315 {
1316         u64 data = 0;
1317
1318         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1319                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1320
1321         /*
1322          * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1323          * the nested hypervisor runs with NX huge pages.  If it is not,
1324          * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1325          * L1 guests, so it need not worry about its own (L2) guests.
1326          */
1327         data |= ARCH_CAP_PSCHANGE_MC_NO;
1328
1329         /*
1330          * If we're doing cache flushes (either "always" or "cond")
1331          * we will do one whenever the guest does a vmlaunch/vmresume.
1332          * If an outer hypervisor is doing the cache flush for us
1333          * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1334          * capability to the guest too, and if EPT is disabled we're not
1335          * vulnerable.  Overall, only VMENTER_L1D_FLUSH_NEVER will
1336          * require a nested hypervisor to do a flush of its own.
1337          */
1338         if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1339                 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1340
1341         if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1342                 data |= ARCH_CAP_RDCL_NO;
1343         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1344                 data |= ARCH_CAP_SSB_NO;
1345         if (!boot_cpu_has_bug(X86_BUG_MDS))
1346                 data |= ARCH_CAP_MDS_NO;
1347
1348         /*
1349          * On TAA affected systems:
1350          *      - nothing to do if TSX is disabled on the host.
1351          *      - we emulate TSX_CTRL if present on the host.
1352          *        This lets the guest use VERW to clear CPU buffers.
1353          */
1354         if (!boot_cpu_has(X86_FEATURE_RTM))
1355                 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1356         else if (!boot_cpu_has_bug(X86_BUG_TAA))
1357                 data |= ARCH_CAP_TAA_NO;
1358
1359         return data;
1360 }
1361
1362 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1363 {
1364         switch (msr->index) {
1365         case MSR_IA32_ARCH_CAPABILITIES:
1366                 msr->data = kvm_get_arch_capabilities();
1367                 break;
1368         case MSR_IA32_UCODE_REV:
1369                 rdmsrl_safe(msr->index, &msr->data);
1370                 break;
1371         default:
1372                 if (kvm_x86_ops.get_msr_feature(msr))
1373                         return 1;
1374         }
1375         return 0;
1376 }
1377
1378 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1379 {
1380         struct kvm_msr_entry msr;
1381         int r;
1382
1383         msr.index = index;
1384         r = kvm_get_msr_feature(&msr);
1385         if (r)
1386                 return r;
1387
1388         *data = msr.data;
1389
1390         return 0;
1391 }
1392
1393 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1394 {
1395         if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1396                 return false;
1397
1398         if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1399                 return false;
1400
1401         if (efer & (EFER_LME | EFER_LMA) &&
1402             !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1403                 return false;
1404
1405         if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1406                 return false;
1407
1408         return true;
1409
1410 }
1411 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1412 {
1413         if (efer & efer_reserved_bits)
1414                 return false;
1415
1416         return __kvm_valid_efer(vcpu, efer);
1417 }
1418 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1419
1420 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1421 {
1422         u64 old_efer = vcpu->arch.efer;
1423         u64 efer = msr_info->data;
1424
1425         if (efer & efer_reserved_bits)
1426                 return 1;
1427
1428         if (!msr_info->host_initiated) {
1429                 if (!__kvm_valid_efer(vcpu, efer))
1430                         return 1;
1431
1432                 if (is_paging(vcpu) &&
1433                     (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1434                         return 1;
1435         }
1436
1437         efer &= ~EFER_LMA;
1438         efer |= vcpu->arch.efer & EFER_LMA;
1439
1440         kvm_x86_ops.set_efer(vcpu, efer);
1441
1442         /* Update reserved bits */
1443         if ((efer ^ old_efer) & EFER_NX)
1444                 kvm_mmu_reset_context(vcpu);
1445
1446         return 0;
1447 }
1448
1449 void kvm_enable_efer_bits(u64 mask)
1450 {
1451        efer_reserved_bits &= ~mask;
1452 }
1453 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1454
1455 /*
1456  * Write @data into the MSR specified by @index.  Select MSR specific fault
1457  * checks are bypassed if @host_initiated is %true.
1458  * Returns 0 on success, non-0 otherwise.
1459  * Assumes vcpu_load() was already called.
1460  */
1461 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1462                          bool host_initiated)
1463 {
1464         struct msr_data msr;
1465
1466         switch (index) {
1467         case MSR_FS_BASE:
1468         case MSR_GS_BASE:
1469         case MSR_KERNEL_GS_BASE:
1470         case MSR_CSTAR:
1471         case MSR_LSTAR:
1472                 if (is_noncanonical_address(data, vcpu))
1473                         return 1;
1474                 break;
1475         case MSR_IA32_SYSENTER_EIP:
1476         case MSR_IA32_SYSENTER_ESP:
1477                 /*
1478                  * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1479                  * non-canonical address is written on Intel but not on
1480                  * AMD (which ignores the top 32-bits, because it does
1481                  * not implement 64-bit SYSENTER).
1482                  *
1483                  * 64-bit code should hence be able to write a non-canonical
1484                  * value on AMD.  Making the address canonical ensures that
1485                  * vmentry does not fail on Intel after writing a non-canonical
1486                  * value, and that something deterministic happens if the guest
1487                  * invokes 64-bit SYSENTER.
1488                  */
1489                 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1490         }
1491
1492         msr.data = data;
1493         msr.index = index;
1494         msr.host_initiated = host_initiated;
1495
1496         return kvm_x86_ops.set_msr(vcpu, &msr);
1497 }
1498
1499 /*
1500  * Read the MSR specified by @index into @data.  Select MSR specific fault
1501  * checks are bypassed if @host_initiated is %true.
1502  * Returns 0 on success, non-0 otherwise.
1503  * Assumes vcpu_load() was already called.
1504  */
1505 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1506                   bool host_initiated)
1507 {
1508         struct msr_data msr;
1509         int ret;
1510
1511         msr.index = index;
1512         msr.host_initiated = host_initiated;
1513
1514         ret = kvm_x86_ops.get_msr(vcpu, &msr);
1515         if (!ret)
1516                 *data = msr.data;
1517         return ret;
1518 }
1519
1520 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1521 {
1522         return __kvm_get_msr(vcpu, index, data, false);
1523 }
1524 EXPORT_SYMBOL_GPL(kvm_get_msr);
1525
1526 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1527 {
1528         return __kvm_set_msr(vcpu, index, data, false);
1529 }
1530 EXPORT_SYMBOL_GPL(kvm_set_msr);
1531
1532 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1533 {
1534         u32 ecx = kvm_rcx_read(vcpu);
1535         u64 data;
1536
1537         if (kvm_get_msr(vcpu, ecx, &data)) {
1538                 trace_kvm_msr_read_ex(ecx);
1539                 kvm_inject_gp(vcpu, 0);
1540                 return 1;
1541         }
1542
1543         trace_kvm_msr_read(ecx, data);
1544
1545         kvm_rax_write(vcpu, data & -1u);
1546         kvm_rdx_write(vcpu, (data >> 32) & -1u);
1547         return kvm_skip_emulated_instruction(vcpu);
1548 }
1549 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1550
1551 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1552 {
1553         u32 ecx = kvm_rcx_read(vcpu);
1554         u64 data = kvm_read_edx_eax(vcpu);
1555
1556         if (kvm_set_msr(vcpu, ecx, data)) {
1557                 trace_kvm_msr_write_ex(ecx, data);
1558                 kvm_inject_gp(vcpu, 0);
1559                 return 1;
1560         }
1561
1562         trace_kvm_msr_write(ecx, data);
1563         return kvm_skip_emulated_instruction(vcpu);
1564 }
1565 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1566
1567 /*
1568  * The fast path for frequent and performance sensitive wrmsr emulation,
1569  * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1570  * the latency of virtual IPI by avoiding the expensive bits of transitioning
1571  * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1572  * other cases which must be called after interrupts are enabled on the host.
1573  */
1574 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1575 {
1576         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1577                 return 1;
1578
1579         if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1580                 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1581                 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1582                 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1583
1584                 data &= ~(1 << 12);
1585                 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1586                 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1587                 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1588                 trace_kvm_apic_write(APIC_ICR, (u32)data);
1589                 return 0;
1590         }
1591
1592         return 1;
1593 }
1594
1595 enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1596 {
1597         u32 msr = kvm_rcx_read(vcpu);
1598         u64 data;
1599         int ret = 0;
1600
1601         switch (msr) {
1602         case APIC_BASE_MSR + (APIC_ICR >> 4):
1603                 data = kvm_read_edx_eax(vcpu);
1604                 ret = handle_fastpath_set_x2apic_icr_irqoff(vcpu, data);
1605                 break;
1606         default:
1607                 return EXIT_FASTPATH_NONE;
1608         }
1609
1610         if (!ret) {
1611                 trace_kvm_msr_write(msr, data);
1612                 return EXIT_FASTPATH_SKIP_EMUL_INS;
1613         }
1614
1615         return EXIT_FASTPATH_NONE;
1616 }
1617 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1618
1619 /*
1620  * Adapt set_msr() to msr_io()'s calling convention
1621  */
1622 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1623 {
1624         return __kvm_get_msr(vcpu, index, data, true);
1625 }
1626
1627 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1628 {
1629         return __kvm_set_msr(vcpu, index, *data, true);
1630 }
1631
1632 #ifdef CONFIG_X86_64
1633 struct pvclock_clock {
1634         int vclock_mode;
1635         u64 cycle_last;
1636         u64 mask;
1637         u32 mult;
1638         u32 shift;
1639         u64 base_cycles;
1640         u64 offset;
1641 };
1642
1643 struct pvclock_gtod_data {
1644         seqcount_t      seq;
1645
1646         struct pvclock_clock clock; /* extract of a clocksource struct */
1647         struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1648
1649         ktime_t         offs_boot;
1650         u64             wall_time_sec;
1651 };
1652
1653 static struct pvclock_gtod_data pvclock_gtod_data;
1654
1655 static void update_pvclock_gtod(struct timekeeper *tk)
1656 {
1657         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1658
1659         write_seqcount_begin(&vdata->seq);
1660
1661         /* copy pvclock gtod data */
1662         vdata->clock.vclock_mode        = tk->tkr_mono.clock->vdso_clock_mode;
1663         vdata->clock.cycle_last         = tk->tkr_mono.cycle_last;
1664         vdata->clock.mask               = tk->tkr_mono.mask;
1665         vdata->clock.mult               = tk->tkr_mono.mult;
1666         vdata->clock.shift              = tk->tkr_mono.shift;
1667         vdata->clock.base_cycles        = tk->tkr_mono.xtime_nsec;
1668         vdata->clock.offset             = tk->tkr_mono.base;
1669
1670         vdata->raw_clock.vclock_mode    = tk->tkr_raw.clock->vdso_clock_mode;
1671         vdata->raw_clock.cycle_last     = tk->tkr_raw.cycle_last;
1672         vdata->raw_clock.mask           = tk->tkr_raw.mask;
1673         vdata->raw_clock.mult           = tk->tkr_raw.mult;
1674         vdata->raw_clock.shift          = tk->tkr_raw.shift;
1675         vdata->raw_clock.base_cycles    = tk->tkr_raw.xtime_nsec;
1676         vdata->raw_clock.offset         = tk->tkr_raw.base;
1677
1678         vdata->wall_time_sec            = tk->xtime_sec;
1679
1680         vdata->offs_boot                = tk->offs_boot;
1681
1682         write_seqcount_end(&vdata->seq);
1683 }
1684
1685 static s64 get_kvmclock_base_ns(void)
1686 {
1687         /* Count up from boot time, but with the frequency of the raw clock.  */
1688         return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1689 }
1690 #else
1691 static s64 get_kvmclock_base_ns(void)
1692 {
1693         /* Master clock not used, so we can just use CLOCK_BOOTTIME.  */
1694         return ktime_get_boottime_ns();
1695 }
1696 #endif
1697
1698 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1699 {
1700         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1701         kvm_vcpu_kick(vcpu);
1702 }
1703
1704 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1705 {
1706         int version;
1707         int r;
1708         struct pvclock_wall_clock wc;
1709         u64 wall_nsec;
1710
1711         if (!wall_clock)
1712                 return;
1713
1714         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1715         if (r)
1716                 return;
1717
1718         if (version & 1)
1719                 ++version;  /* first time write, random junk */
1720
1721         ++version;
1722
1723         if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1724                 return;
1725
1726         /*
1727          * The guest calculates current wall clock time by adding
1728          * system time (updated by kvm_guest_time_update below) to the
1729          * wall clock specified here.  We do the reverse here.
1730          */
1731         wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1732
1733         wc.nsec = do_div(wall_nsec, 1000000000);
1734         wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1735         wc.version = version;
1736
1737         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1738
1739         version++;
1740         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1741 }
1742
1743 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1744 {
1745         do_shl32_div32(dividend, divisor);
1746         return dividend;
1747 }
1748
1749 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1750                                s8 *pshift, u32 *pmultiplier)
1751 {
1752         uint64_t scaled64;
1753         int32_t  shift = 0;
1754         uint64_t tps64;
1755         uint32_t tps32;
1756
1757         tps64 = base_hz;
1758         scaled64 = scaled_hz;
1759         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1760                 tps64 >>= 1;
1761                 shift--;
1762         }
1763
1764         tps32 = (uint32_t)tps64;
1765         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1766                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1767                         scaled64 >>= 1;
1768                 else
1769                         tps32 <<= 1;
1770                 shift++;
1771         }
1772
1773         *pshift = shift;
1774         *pmultiplier = div_frac(scaled64, tps32);
1775 }
1776
1777 #ifdef CONFIG_X86_64
1778 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1779 #endif
1780
1781 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1782 static unsigned long max_tsc_khz;
1783
1784 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1785 {
1786         u64 v = (u64)khz * (1000000 + ppm);
1787         do_div(v, 1000000);
1788         return v;
1789 }
1790
1791 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1792 {
1793         u64 ratio;
1794
1795         /* Guest TSC same frequency as host TSC? */
1796         if (!scale) {
1797                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1798                 return 0;
1799         }
1800
1801         /* TSC scaling supported? */
1802         if (!kvm_has_tsc_control) {
1803                 if (user_tsc_khz > tsc_khz) {
1804                         vcpu->arch.tsc_catchup = 1;
1805                         vcpu->arch.tsc_always_catchup = 1;
1806                         return 0;
1807                 } else {
1808                         pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1809                         return -1;
1810                 }
1811         }
1812
1813         /* TSC scaling required  - calculate ratio */
1814         ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1815                                 user_tsc_khz, tsc_khz);
1816
1817         if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1818                 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1819                                     user_tsc_khz);
1820                 return -1;
1821         }
1822
1823         vcpu->arch.tsc_scaling_ratio = ratio;
1824         return 0;
1825 }
1826
1827 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1828 {
1829         u32 thresh_lo, thresh_hi;
1830         int use_scaling = 0;
1831
1832         /* tsc_khz can be zero if TSC calibration fails */
1833         if (user_tsc_khz == 0) {
1834                 /* set tsc_scaling_ratio to a safe value */
1835                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1836                 return -1;
1837         }
1838
1839         /* Compute a scale to convert nanoseconds in TSC cycles */
1840         kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1841                            &vcpu->arch.virtual_tsc_shift,
1842                            &vcpu->arch.virtual_tsc_mult);
1843         vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1844
1845         /*
1846          * Compute the variation in TSC rate which is acceptable
1847          * within the range of tolerance and decide if the
1848          * rate being applied is within that bounds of the hardware
1849          * rate.  If so, no scaling or compensation need be done.
1850          */
1851         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1852         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1853         if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1854                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1855                 use_scaling = 1;
1856         }
1857         return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1858 }
1859
1860 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1861 {
1862         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1863                                       vcpu->arch.virtual_tsc_mult,
1864                                       vcpu->arch.virtual_tsc_shift);
1865         tsc += vcpu->arch.this_tsc_write;
1866         return tsc;
1867 }
1868
1869 static inline int gtod_is_based_on_tsc(int mode)
1870 {
1871         return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
1872 }
1873
1874 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1875 {
1876 #ifdef CONFIG_X86_64
1877         bool vcpus_matched;
1878         struct kvm_arch *ka = &vcpu->kvm->arch;
1879         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1880
1881         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1882                          atomic_read(&vcpu->kvm->online_vcpus));
1883
1884         /*
1885          * Once the masterclock is enabled, always perform request in
1886          * order to update it.
1887          *
1888          * In order to enable masterclock, the host clocksource must be TSC
1889          * and the vcpus need to have matched TSCs.  When that happens,
1890          * perform request to enable masterclock.
1891          */
1892         if (ka->use_master_clock ||
1893             (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1894                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1895
1896         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1897                             atomic_read(&vcpu->kvm->online_vcpus),
1898                             ka->use_master_clock, gtod->clock.vclock_mode);
1899 #endif
1900 }
1901
1902 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1903 {
1904         u64 curr_offset = kvm_x86_ops.read_l1_tsc_offset(vcpu);
1905         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1906 }
1907
1908 /*
1909  * Multiply tsc by a fixed point number represented by ratio.
1910  *
1911  * The most significant 64-N bits (mult) of ratio represent the
1912  * integral part of the fixed point number; the remaining N bits
1913  * (frac) represent the fractional part, ie. ratio represents a fixed
1914  * point number (mult + frac * 2^(-N)).
1915  *
1916  * N equals to kvm_tsc_scaling_ratio_frac_bits.
1917  */
1918 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1919 {
1920         return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1921 }
1922
1923 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1924 {
1925         u64 _tsc = tsc;
1926         u64 ratio = vcpu->arch.tsc_scaling_ratio;
1927
1928         if (ratio != kvm_default_tsc_scaling_ratio)
1929                 _tsc = __scale_tsc(ratio, tsc);
1930
1931         return _tsc;
1932 }
1933 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1934
1935 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1936 {
1937         u64 tsc;
1938
1939         tsc = kvm_scale_tsc(vcpu, rdtsc());
1940
1941         return target_tsc - tsc;
1942 }
1943
1944 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1945 {
1946         u64 tsc_offset = kvm_x86_ops.read_l1_tsc_offset(vcpu);
1947
1948         return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1949 }
1950 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1951
1952 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1953 {
1954         vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset);
1955 }
1956
1957 static inline bool kvm_check_tsc_unstable(void)
1958 {
1959 #ifdef CONFIG_X86_64
1960         /*
1961          * TSC is marked unstable when we're running on Hyper-V,
1962          * 'TSC page' clocksource is good.
1963          */
1964         if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
1965                 return false;
1966 #endif
1967         return check_tsc_unstable();
1968 }
1969
1970 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1971 {
1972         struct kvm *kvm = vcpu->kvm;
1973         u64 offset, ns, elapsed;
1974         unsigned long flags;
1975         bool matched;
1976         bool already_matched;
1977         u64 data = msr->data;
1978         bool synchronizing = false;
1979
1980         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1981         offset = kvm_compute_tsc_offset(vcpu, data);
1982         ns = get_kvmclock_base_ns();
1983         elapsed = ns - kvm->arch.last_tsc_nsec;
1984
1985         if (vcpu->arch.virtual_tsc_khz) {
1986                 if (data == 0 && msr->host_initiated) {
1987                         /*
1988                          * detection of vcpu initialization -- need to sync
1989                          * with other vCPUs. This particularly helps to keep
1990                          * kvm_clock stable after CPU hotplug
1991                          */
1992                         synchronizing = true;
1993                 } else {
1994                         u64 tsc_exp = kvm->arch.last_tsc_write +
1995                                                 nsec_to_cycles(vcpu, elapsed);
1996                         u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1997                         /*
1998                          * Special case: TSC write with a small delta (1 second)
1999                          * of virtual cycle time against real time is
2000                          * interpreted as an attempt to synchronize the CPU.
2001                          */
2002                         synchronizing = data < tsc_exp + tsc_hz &&
2003                                         data + tsc_hz > tsc_exp;
2004                 }
2005         }
2006
2007         /*
2008          * For a reliable TSC, we can match TSC offsets, and for an unstable
2009          * TSC, we add elapsed time in this computation.  We could let the
2010          * compensation code attempt to catch up if we fall behind, but
2011          * it's better to try to match offsets from the beginning.
2012          */
2013         if (synchronizing &&
2014             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2015                 if (!kvm_check_tsc_unstable()) {
2016                         offset = kvm->arch.cur_tsc_offset;
2017                 } else {
2018                         u64 delta = nsec_to_cycles(vcpu, elapsed);
2019                         data += delta;
2020                         offset = kvm_compute_tsc_offset(vcpu, data);
2021                 }
2022                 matched = true;
2023                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2024         } else {
2025                 /*
2026                  * We split periods of matched TSC writes into generations.
2027                  * For each generation, we track the original measured
2028                  * nanosecond time, offset, and write, so if TSCs are in
2029                  * sync, we can match exact offset, and if not, we can match
2030                  * exact software computation in compute_guest_tsc()
2031                  *
2032                  * These values are tracked in kvm->arch.cur_xxx variables.
2033                  */
2034                 kvm->arch.cur_tsc_generation++;
2035                 kvm->arch.cur_tsc_nsec = ns;
2036                 kvm->arch.cur_tsc_write = data;
2037                 kvm->arch.cur_tsc_offset = offset;
2038                 matched = false;
2039         }
2040
2041         /*
2042          * We also track th most recent recorded KHZ, write and time to
2043          * allow the matching interval to be extended at each write.
2044          */
2045         kvm->arch.last_tsc_nsec = ns;
2046         kvm->arch.last_tsc_write = data;
2047         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2048
2049         vcpu->arch.last_guest_tsc = data;
2050
2051         /* Keep track of which generation this VCPU has synchronized to */
2052         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2053         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2054         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2055
2056         if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
2057                 update_ia32_tsc_adjust_msr(vcpu, offset);
2058
2059         kvm_vcpu_write_tsc_offset(vcpu, offset);
2060         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2061
2062         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2063         if (!matched) {
2064                 kvm->arch.nr_vcpus_matched_tsc = 0;
2065         } else if (!already_matched) {
2066                 kvm->arch.nr_vcpus_matched_tsc++;
2067         }
2068
2069         kvm_track_tsc_matching(vcpu);
2070         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2071 }
2072
2073 EXPORT_SYMBOL_GPL(kvm_write_tsc);
2074
2075 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2076                                            s64 adjustment)
2077 {
2078         u64 tsc_offset = kvm_x86_ops.read_l1_tsc_offset(vcpu);
2079         kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2080 }
2081
2082 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2083 {
2084         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2085                 WARN_ON(adjustment < 0);
2086         adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2087         adjust_tsc_offset_guest(vcpu, adjustment);
2088 }
2089
2090 #ifdef CONFIG_X86_64
2091
2092 static u64 read_tsc(void)
2093 {
2094         u64 ret = (u64)rdtsc_ordered();
2095         u64 last = pvclock_gtod_data.clock.cycle_last;
2096
2097         if (likely(ret >= last))
2098                 return ret;
2099
2100         /*
2101          * GCC likes to generate cmov here, but this branch is extremely
2102          * predictable (it's just a function of time and the likely is
2103          * very likely) and there's a data dependence, so force GCC
2104          * to generate a branch instead.  I don't barrier() because
2105          * we don't actually need a barrier, and if this function
2106          * ever gets inlined it will generate worse code.
2107          */
2108         asm volatile ("");
2109         return last;
2110 }
2111
2112 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2113                           int *mode)
2114 {
2115         long v;
2116         u64 tsc_pg_val;
2117
2118         switch (clock->vclock_mode) {
2119         case VDSO_CLOCKMODE_HVCLOCK:
2120                 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2121                                                   tsc_timestamp);
2122                 if (tsc_pg_val != U64_MAX) {
2123                         /* TSC page valid */
2124                         *mode = VDSO_CLOCKMODE_HVCLOCK;
2125                         v = (tsc_pg_val - clock->cycle_last) &
2126                                 clock->mask;
2127                 } else {
2128                         /* TSC page invalid */
2129                         *mode = VDSO_CLOCKMODE_NONE;
2130                 }
2131                 break;
2132         case VDSO_CLOCKMODE_TSC:
2133                 *mode = VDSO_CLOCKMODE_TSC;
2134                 *tsc_timestamp = read_tsc();
2135                 v = (*tsc_timestamp - clock->cycle_last) &
2136                         clock->mask;
2137                 break;
2138         default:
2139                 *mode = VDSO_CLOCKMODE_NONE;
2140         }
2141
2142         if (*mode == VDSO_CLOCKMODE_NONE)
2143                 *tsc_timestamp = v = 0;
2144
2145         return v * clock->mult;
2146 }
2147
2148 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2149 {
2150         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2151         unsigned long seq;
2152         int mode;
2153         u64 ns;
2154
2155         do {
2156                 seq = read_seqcount_begin(&gtod->seq);
2157                 ns = gtod->raw_clock.base_cycles;
2158                 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2159                 ns >>= gtod->raw_clock.shift;
2160                 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2161         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2162         *t = ns;
2163
2164         return mode;
2165 }
2166
2167 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2168 {
2169         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2170         unsigned long seq;
2171         int mode;
2172         u64 ns;
2173
2174         do {
2175                 seq = read_seqcount_begin(&gtod->seq);
2176                 ts->tv_sec = gtod->wall_time_sec;
2177                 ns = gtod->clock.base_cycles;
2178                 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2179                 ns >>= gtod->clock.shift;
2180         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2181
2182         ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2183         ts->tv_nsec = ns;
2184
2185         return mode;
2186 }
2187
2188 /* returns true if host is using TSC based clocksource */
2189 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2190 {
2191         /* checked again under seqlock below */
2192         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2193                 return false;
2194
2195         return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2196                                                       tsc_timestamp));
2197 }
2198
2199 /* returns true if host is using TSC based clocksource */
2200 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2201                                            u64 *tsc_timestamp)
2202 {
2203         /* checked again under seqlock below */
2204         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2205                 return false;
2206
2207         return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2208 }
2209 #endif
2210
2211 /*
2212  *
2213  * Assuming a stable TSC across physical CPUS, and a stable TSC
2214  * across virtual CPUs, the following condition is possible.
2215  * Each numbered line represents an event visible to both
2216  * CPUs at the next numbered event.
2217  *
2218  * "timespecX" represents host monotonic time. "tscX" represents
2219  * RDTSC value.
2220  *
2221  *              VCPU0 on CPU0           |       VCPU1 on CPU1
2222  *
2223  * 1.  read timespec0,tsc0
2224  * 2.                                   | timespec1 = timespec0 + N
2225  *                                      | tsc1 = tsc0 + M
2226  * 3. transition to guest               | transition to guest
2227  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2228  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
2229  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2230  *
2231  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2232  *
2233  *      - ret0 < ret1
2234  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2235  *              ...
2236  *      - 0 < N - M => M < N
2237  *
2238  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2239  * always the case (the difference between two distinct xtime instances
2240  * might be smaller then the difference between corresponding TSC reads,
2241  * when updating guest vcpus pvclock areas).
2242  *
2243  * To avoid that problem, do not allow visibility of distinct
2244  * system_timestamp/tsc_timestamp values simultaneously: use a master
2245  * copy of host monotonic time values. Update that master copy
2246  * in lockstep.
2247  *
2248  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2249  *
2250  */
2251
2252 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2253 {
2254 #ifdef CONFIG_X86_64
2255         struct kvm_arch *ka = &kvm->arch;
2256         int vclock_mode;
2257         bool host_tsc_clocksource, vcpus_matched;
2258
2259         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2260                         atomic_read(&kvm->online_vcpus));
2261
2262         /*
2263          * If the host uses TSC clock, then passthrough TSC as stable
2264          * to the guest.
2265          */
2266         host_tsc_clocksource = kvm_get_time_and_clockread(
2267                                         &ka->master_kernel_ns,
2268                                         &ka->master_cycle_now);
2269
2270         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2271                                 && !ka->backwards_tsc_observed
2272                                 && !ka->boot_vcpu_runs_old_kvmclock;
2273
2274         if (ka->use_master_clock)
2275                 atomic_set(&kvm_guest_has_master_clock, 1);
2276
2277         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2278         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2279                                         vcpus_matched);
2280 #endif
2281 }
2282
2283 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2284 {
2285         kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2286 }
2287
2288 static void kvm_gen_update_masterclock(struct kvm *kvm)
2289 {
2290 #ifdef CONFIG_X86_64
2291         int i;
2292         struct kvm_vcpu *vcpu;
2293         struct kvm_arch *ka = &kvm->arch;
2294
2295         spin_lock(&ka->pvclock_gtod_sync_lock);
2296         kvm_make_mclock_inprogress_request(kvm);
2297         /* no guest entries from this point */
2298         pvclock_update_vm_gtod_copy(kvm);
2299
2300         kvm_for_each_vcpu(i, vcpu, kvm)
2301                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2302
2303         /* guest entries allowed */
2304         kvm_for_each_vcpu(i, vcpu, kvm)
2305                 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2306
2307         spin_unlock(&ka->pvclock_gtod_sync_lock);
2308 #endif
2309 }
2310
2311 u64 get_kvmclock_ns(struct kvm *kvm)
2312 {
2313         struct kvm_arch *ka = &kvm->arch;
2314         struct pvclock_vcpu_time_info hv_clock;
2315         u64 ret;
2316
2317         spin_lock(&ka->pvclock_gtod_sync_lock);
2318         if (!ka->use_master_clock) {
2319                 spin_unlock(&ka->pvclock_gtod_sync_lock);
2320                 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2321         }
2322
2323         hv_clock.tsc_timestamp = ka->master_cycle_now;
2324         hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2325         spin_unlock(&ka->pvclock_gtod_sync_lock);
2326
2327         /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2328         get_cpu();
2329
2330         if (__this_cpu_read(cpu_tsc_khz)) {
2331                 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2332                                    &hv_clock.tsc_shift,
2333                                    &hv_clock.tsc_to_system_mul);
2334                 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2335         } else
2336                 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2337
2338         put_cpu();
2339
2340         return ret;
2341 }
2342
2343 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2344 {
2345         struct kvm_vcpu_arch *vcpu = &v->arch;
2346         struct pvclock_vcpu_time_info guest_hv_clock;
2347
2348         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2349                 &guest_hv_clock, sizeof(guest_hv_clock))))
2350                 return;
2351
2352         /* This VCPU is paused, but it's legal for a guest to read another
2353          * VCPU's kvmclock, so we really have to follow the specification where
2354          * it says that version is odd if data is being modified, and even after
2355          * it is consistent.
2356          *
2357          * Version field updates must be kept separate.  This is because
2358          * kvm_write_guest_cached might use a "rep movs" instruction, and
2359          * writes within a string instruction are weakly ordered.  So there
2360          * are three writes overall.
2361          *
2362          * As a small optimization, only write the version field in the first
2363          * and third write.  The vcpu->pv_time cache is still valid, because the
2364          * version field is the first in the struct.
2365          */
2366         BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2367
2368         if (guest_hv_clock.version & 1)
2369                 ++guest_hv_clock.version;  /* first time write, random junk */
2370
2371         vcpu->hv_clock.version = guest_hv_clock.version + 1;
2372         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2373                                 &vcpu->hv_clock,
2374                                 sizeof(vcpu->hv_clock.version));
2375
2376         smp_wmb();
2377
2378         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2379         vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2380
2381         if (vcpu->pvclock_set_guest_stopped_request) {
2382                 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2383                 vcpu->pvclock_set_guest_stopped_request = false;
2384         }
2385
2386         trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2387
2388         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2389                                 &vcpu->hv_clock,
2390                                 sizeof(vcpu->hv_clock));
2391
2392         smp_wmb();
2393
2394         vcpu->hv_clock.version++;
2395         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2396                                 &vcpu->hv_clock,
2397                                 sizeof(vcpu->hv_clock.version));
2398 }
2399
2400 static int kvm_guest_time_update(struct kvm_vcpu *v)
2401 {
2402         unsigned long flags, tgt_tsc_khz;
2403         struct kvm_vcpu_arch *vcpu = &v->arch;
2404         struct kvm_arch *ka = &v->kvm->arch;
2405         s64 kernel_ns;
2406         u64 tsc_timestamp, host_tsc;
2407         u8 pvclock_flags;
2408         bool use_master_clock;
2409
2410         kernel_ns = 0;
2411         host_tsc = 0;
2412
2413         /*
2414          * If the host uses TSC clock, then passthrough TSC as stable
2415          * to the guest.
2416          */
2417         spin_lock(&ka->pvclock_gtod_sync_lock);
2418         use_master_clock = ka->use_master_clock;
2419         if (use_master_clock) {
2420                 host_tsc = ka->master_cycle_now;
2421                 kernel_ns = ka->master_kernel_ns;
2422         }
2423         spin_unlock(&ka->pvclock_gtod_sync_lock);
2424
2425         /* Keep irq disabled to prevent changes to the clock */
2426         local_irq_save(flags);
2427         tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2428         if (unlikely(tgt_tsc_khz == 0)) {
2429                 local_irq_restore(flags);
2430                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2431                 return 1;
2432         }
2433         if (!use_master_clock) {
2434                 host_tsc = rdtsc();
2435                 kernel_ns = get_kvmclock_base_ns();
2436         }
2437
2438         tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2439
2440         /*
2441          * We may have to catch up the TSC to match elapsed wall clock
2442          * time for two reasons, even if kvmclock is used.
2443          *   1) CPU could have been running below the maximum TSC rate
2444          *   2) Broken TSC compensation resets the base at each VCPU
2445          *      entry to avoid unknown leaps of TSC even when running
2446          *      again on the same CPU.  This may cause apparent elapsed
2447          *      time to disappear, and the guest to stand still or run
2448          *      very slowly.
2449          */
2450         if (vcpu->tsc_catchup) {
2451                 u64 tsc = compute_guest_tsc(v, kernel_ns);
2452                 if (tsc > tsc_timestamp) {
2453                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2454                         tsc_timestamp = tsc;
2455                 }
2456         }
2457
2458         local_irq_restore(flags);
2459
2460         /* With all the info we got, fill in the values */
2461
2462         if (kvm_has_tsc_control)
2463                 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2464
2465         if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2466                 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2467                                    &vcpu->hv_clock.tsc_shift,
2468                                    &vcpu->hv_clock.tsc_to_system_mul);
2469                 vcpu->hw_tsc_khz = tgt_tsc_khz;
2470         }
2471
2472         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2473         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2474         vcpu->last_guest_tsc = tsc_timestamp;
2475
2476         /* If the host uses TSC clocksource, then it is stable */
2477         pvclock_flags = 0;
2478         if (use_master_clock)
2479                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2480
2481         vcpu->hv_clock.flags = pvclock_flags;
2482
2483         if (vcpu->pv_time_enabled)
2484                 kvm_setup_pvclock_page(v);
2485         if (v == kvm_get_vcpu(v->kvm, 0))
2486                 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2487         return 0;
2488 }
2489
2490 /*
2491  * kvmclock updates which are isolated to a given vcpu, such as
2492  * vcpu->cpu migration, should not allow system_timestamp from
2493  * the rest of the vcpus to remain static. Otherwise ntp frequency
2494  * correction applies to one vcpu's system_timestamp but not
2495  * the others.
2496  *
2497  * So in those cases, request a kvmclock update for all vcpus.
2498  * We need to rate-limit these requests though, as they can
2499  * considerably slow guests that have a large number of vcpus.
2500  * The time for a remote vcpu to update its kvmclock is bound
2501  * by the delay we use to rate-limit the updates.
2502  */
2503
2504 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2505
2506 static void kvmclock_update_fn(struct work_struct *work)
2507 {
2508         int i;
2509         struct delayed_work *dwork = to_delayed_work(work);
2510         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2511                                            kvmclock_update_work);
2512         struct kvm *kvm = container_of(ka, struct kvm, arch);
2513         struct kvm_vcpu *vcpu;
2514
2515         kvm_for_each_vcpu(i, vcpu, kvm) {
2516                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2517                 kvm_vcpu_kick(vcpu);
2518         }
2519 }
2520
2521 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2522 {
2523         struct kvm *kvm = v->kvm;
2524
2525         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2526         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2527                                         KVMCLOCK_UPDATE_DELAY);
2528 }
2529
2530 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2531
2532 static void kvmclock_sync_fn(struct work_struct *work)
2533 {
2534         struct delayed_work *dwork = to_delayed_work(work);
2535         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2536                                            kvmclock_sync_work);
2537         struct kvm *kvm = container_of(ka, struct kvm, arch);
2538
2539         if (!kvmclock_periodic_sync)
2540                 return;
2541
2542         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2543         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2544                                         KVMCLOCK_SYNC_PERIOD);
2545 }
2546
2547 /*
2548  * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2549  */
2550 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2551 {
2552         /* McStatusWrEn enabled? */
2553         if (guest_cpuid_is_amd_or_hygon(vcpu))
2554                 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2555
2556         return false;
2557 }
2558
2559 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2560 {
2561         u64 mcg_cap = vcpu->arch.mcg_cap;
2562         unsigned bank_num = mcg_cap & 0xff;
2563         u32 msr = msr_info->index;
2564         u64 data = msr_info->data;
2565
2566         switch (msr) {
2567         case MSR_IA32_MCG_STATUS:
2568                 vcpu->arch.mcg_status = data;
2569                 break;
2570         case MSR_IA32_MCG_CTL:
2571                 if (!(mcg_cap & MCG_CTL_P) &&
2572                     (data || !msr_info->host_initiated))
2573                         return 1;
2574                 if (data != 0 && data != ~(u64)0)
2575                         return 1;
2576                 vcpu->arch.mcg_ctl = data;
2577                 break;
2578         default:
2579                 if (msr >= MSR_IA32_MC0_CTL &&
2580                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2581                         u32 offset = array_index_nospec(
2582                                 msr - MSR_IA32_MC0_CTL,
2583                                 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2584
2585                         /* only 0 or all 1s can be written to IA32_MCi_CTL
2586                          * some Linux kernels though clear bit 10 in bank 4 to
2587                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2588                          * this to avoid an uncatched #GP in the guest
2589                          */
2590                         if ((offset & 0x3) == 0 &&
2591                             data != 0 && (data | (1 << 10)) != ~(u64)0)
2592                                 return -1;
2593
2594                         /* MCi_STATUS */
2595                         if (!msr_info->host_initiated &&
2596                             (offset & 0x3) == 1 && data != 0) {
2597                                 if (!can_set_mci_status(vcpu))
2598                                         return -1;
2599                         }
2600
2601                         vcpu->arch.mce_banks[offset] = data;
2602                         break;
2603                 }
2604                 return 1;
2605         }
2606         return 0;
2607 }
2608
2609 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2610 {
2611         struct kvm *kvm = vcpu->kvm;
2612         int lm = is_long_mode(vcpu);
2613         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2614                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2615         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2616                 : kvm->arch.xen_hvm_config.blob_size_32;
2617         u32 page_num = data & ~PAGE_MASK;
2618         u64 page_addr = data & PAGE_MASK;
2619         u8 *page;
2620         int r;
2621
2622         r = -E2BIG;
2623         if (page_num >= blob_size)
2624                 goto out;
2625         r = -ENOMEM;
2626         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2627         if (IS_ERR(page)) {
2628                 r = PTR_ERR(page);
2629                 goto out;
2630         }
2631         if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2632                 goto out_free;
2633         r = 0;
2634 out_free:
2635         kfree(page);
2636 out:
2637         return r;
2638 }
2639
2640 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2641 {
2642         gpa_t gpa = data & ~0x3f;
2643
2644         /* Bits 3:5 are reserved, Should be zero */
2645         if (data & 0x38)
2646                 return 1;
2647
2648         vcpu->arch.apf.msr_val = data;
2649
2650         if (!(data & KVM_ASYNC_PF_ENABLED)) {
2651                 kvm_clear_async_pf_completion_queue(vcpu);
2652                 kvm_async_pf_hash_reset(vcpu);
2653                 return 0;
2654         }
2655
2656         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2657                                         sizeof(u32)))
2658                 return 1;
2659
2660         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2661         vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2662         kvm_async_pf_wakeup_all(vcpu);
2663         return 0;
2664 }
2665
2666 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2667 {
2668         vcpu->arch.pv_time_enabled = false;
2669         vcpu->arch.time = 0;
2670 }
2671
2672 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2673 {
2674         ++vcpu->stat.tlb_flush;
2675         kvm_x86_ops.tlb_flush(vcpu, invalidate_gpa);
2676 }
2677
2678 static void record_steal_time(struct kvm_vcpu *vcpu)
2679 {
2680         struct kvm_host_map map;
2681         struct kvm_steal_time *st;
2682
2683         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2684                 return;
2685
2686         /* -EAGAIN is returned in atomic context so we can just return. */
2687         if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2688                         &map, &vcpu->arch.st.cache, false))
2689                 return;
2690
2691         st = map.hva +
2692                 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2693
2694         /*
2695          * Doing a TLB flush here, on the guest's behalf, can avoid
2696          * expensive IPIs.
2697          */
2698         trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2699                 st->preempted & KVM_VCPU_FLUSH_TLB);
2700         if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2701                 kvm_vcpu_flush_tlb(vcpu, false);
2702
2703         vcpu->arch.st.preempted = 0;
2704
2705         if (st->version & 1)
2706                 st->version += 1;  /* first time write, random junk */
2707
2708         st->version += 1;
2709
2710         smp_wmb();
2711
2712         st->steal += current->sched_info.run_delay -
2713                 vcpu->arch.st.last_steal;
2714         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2715
2716         smp_wmb();
2717
2718         st->version += 1;
2719
2720         kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2721 }
2722
2723 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2724 {
2725         bool pr = false;
2726         u32 msr = msr_info->index;
2727         u64 data = msr_info->data;
2728
2729         switch (msr) {
2730         case MSR_AMD64_NB_CFG:
2731         case MSR_IA32_UCODE_WRITE:
2732         case MSR_VM_HSAVE_PA:
2733         case MSR_AMD64_PATCH_LOADER:
2734         case MSR_AMD64_BU_CFG2:
2735         case MSR_AMD64_DC_CFG:
2736         case MSR_F15H_EX_CFG:
2737                 break;
2738
2739         case MSR_IA32_UCODE_REV:
2740                 if (msr_info->host_initiated)
2741                         vcpu->arch.microcode_version = data;
2742                 break;
2743         case MSR_IA32_ARCH_CAPABILITIES:
2744                 if (!msr_info->host_initiated)
2745                         return 1;
2746                 vcpu->arch.arch_capabilities = data;
2747                 break;
2748         case MSR_EFER:
2749                 return set_efer(vcpu, msr_info);
2750         case MSR_K7_HWCR:
2751                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2752                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2753                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2754
2755                 /* Handle McStatusWrEn */
2756                 if (data == BIT_ULL(18)) {
2757                         vcpu->arch.msr_hwcr = data;
2758                 } else if (data != 0) {
2759                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2760                                     data);
2761                         return 1;
2762                 }
2763                 break;
2764         case MSR_FAM10H_MMIO_CONF_BASE:
2765                 if (data != 0) {
2766                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2767                                     "0x%llx\n", data);
2768                         return 1;
2769                 }
2770                 break;
2771         case MSR_IA32_DEBUGCTLMSR:
2772                 if (!data) {
2773                         /* We support the non-activated case already */
2774                         break;
2775                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2776                         /* Values other than LBR and BTF are vendor-specific,
2777                            thus reserved and should throw a #GP */
2778                         return 1;
2779                 }
2780                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2781                             __func__, data);
2782                 break;
2783         case 0x200 ... 0x2ff:
2784                 return kvm_mtrr_set_msr(vcpu, msr, data);
2785         case MSR_IA32_APICBASE:
2786                 return kvm_set_apic_base(vcpu, msr_info);
2787         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2788                 return kvm_x2apic_msr_write(vcpu, msr, data);
2789         case MSR_IA32_TSCDEADLINE:
2790                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2791                 break;
2792         case MSR_IA32_TSC_ADJUST:
2793                 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2794                         if (!msr_info->host_initiated) {
2795                                 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2796                                 adjust_tsc_offset_guest(vcpu, adj);
2797                         }
2798                         vcpu->arch.ia32_tsc_adjust_msr = data;
2799                 }
2800                 break;
2801         case MSR_IA32_MISC_ENABLE:
2802                 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2803                     ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2804                         if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2805                                 return 1;
2806                         vcpu->arch.ia32_misc_enable_msr = data;
2807                         kvm_update_cpuid(vcpu);
2808                 } else {
2809                         vcpu->arch.ia32_misc_enable_msr = data;
2810                 }
2811                 break;
2812         case MSR_IA32_SMBASE:
2813                 if (!msr_info->host_initiated)
2814                         return 1;
2815                 vcpu->arch.smbase = data;
2816                 break;
2817         case MSR_IA32_POWER_CTL:
2818                 vcpu->arch.msr_ia32_power_ctl = data;
2819                 break;
2820         case MSR_IA32_TSC:
2821                 kvm_write_tsc(vcpu, msr_info);
2822                 break;
2823         case MSR_IA32_XSS:
2824                 if (!msr_info->host_initiated &&
2825                     !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
2826                         return 1;
2827                 /*
2828                  * KVM supports exposing PT to the guest, but does not support
2829                  * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
2830                  * XSAVES/XRSTORS to save/restore PT MSRs.
2831                  */
2832                 if (data & ~supported_xss)
2833                         return 1;
2834                 vcpu->arch.ia32_xss = data;
2835                 break;
2836         case MSR_SMI_COUNT:
2837                 if (!msr_info->host_initiated)
2838                         return 1;
2839                 vcpu->arch.smi_count = data;
2840                 break;
2841         case MSR_KVM_WALL_CLOCK_NEW:
2842         case MSR_KVM_WALL_CLOCK:
2843                 vcpu->kvm->arch.wall_clock = data;
2844                 kvm_write_wall_clock(vcpu->kvm, data);
2845                 break;
2846         case MSR_KVM_SYSTEM_TIME_NEW:
2847         case MSR_KVM_SYSTEM_TIME: {
2848                 struct kvm_arch *ka = &vcpu->kvm->arch;
2849
2850                 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2851                         bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2852
2853                         if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2854                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2855
2856                         ka->boot_vcpu_runs_old_kvmclock = tmp;
2857                 }
2858
2859                 vcpu->arch.time = data;
2860                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2861
2862                 /* we verify if the enable bit is set... */
2863                 vcpu->arch.pv_time_enabled = false;
2864                 if (!(data & 1))
2865                         break;
2866
2867                 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2868                      &vcpu->arch.pv_time, data & ~1ULL,
2869                      sizeof(struct pvclock_vcpu_time_info)))
2870                         vcpu->arch.pv_time_enabled = true;
2871
2872                 break;
2873         }
2874         case MSR_KVM_ASYNC_PF_EN:
2875                 if (kvm_pv_enable_async_pf(vcpu, data))
2876                         return 1;
2877                 break;
2878         case MSR_KVM_STEAL_TIME:
2879
2880                 if (unlikely(!sched_info_on()))
2881                         return 1;
2882
2883                 if (data & KVM_STEAL_RESERVED_MASK)
2884                         return 1;
2885
2886                 vcpu->arch.st.msr_val = data;
2887
2888                 if (!(data & KVM_MSR_ENABLED))
2889                         break;
2890
2891                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2892
2893                 break;
2894         case MSR_KVM_PV_EOI_EN:
2895                 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2896                         return 1;
2897                 break;
2898
2899         case MSR_KVM_POLL_CONTROL:
2900                 /* only enable bit supported */
2901                 if (data & (-1ULL << 1))
2902                         return 1;
2903
2904                 vcpu->arch.msr_kvm_poll_control = data;
2905                 break;
2906
2907         case MSR_IA32_MCG_CTL:
2908         case MSR_IA32_MCG_STATUS:
2909         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2910                 return set_msr_mce(vcpu, msr_info);
2911
2912         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2913         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2914                 pr = true; /* fall through */
2915         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2916         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2917                 if (kvm_pmu_is_valid_msr(vcpu, msr))
2918                         return kvm_pmu_set_msr(vcpu, msr_info);
2919
2920                 if (pr || data != 0)
2921                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2922                                     "0x%x data 0x%llx\n", msr, data);
2923                 break;
2924         case MSR_K7_CLK_CTL:
2925                 /*
2926                  * Ignore all writes to this no longer documented MSR.
2927                  * Writes are only relevant for old K7 processors,
2928                  * all pre-dating SVM, but a recommended workaround from
2929                  * AMD for these chips. It is possible to specify the
2930                  * affected processor models on the command line, hence
2931                  * the need to ignore the workaround.
2932                  */
2933                 break;
2934         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2935         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2936         case HV_X64_MSR_CRASH_CTL:
2937         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2938         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2939         case HV_X64_MSR_TSC_EMULATION_CONTROL:
2940         case HV_X64_MSR_TSC_EMULATION_STATUS:
2941                 return kvm_hv_set_msr_common(vcpu, msr, data,
2942                                              msr_info->host_initiated);
2943         case MSR_IA32_BBL_CR_CTL3:
2944                 /* Drop writes to this legacy MSR -- see rdmsr
2945                  * counterpart for further detail.
2946                  */
2947                 if (report_ignored_msrs)
2948                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2949                                 msr, data);
2950                 break;
2951         case MSR_AMD64_OSVW_ID_LENGTH:
2952                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2953                         return 1;
2954                 vcpu->arch.osvw.length = data;
2955                 break;
2956         case MSR_AMD64_OSVW_STATUS:
2957                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2958                         return 1;
2959                 vcpu->arch.osvw.status = data;
2960                 break;
2961         case MSR_PLATFORM_INFO:
2962                 if (!msr_info->host_initiated ||
2963                     (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2964                      cpuid_fault_enabled(vcpu)))
2965                         return 1;
2966                 vcpu->arch.msr_platform_info = data;
2967                 break;
2968         case MSR_MISC_FEATURES_ENABLES:
2969                 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2970                     (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2971                      !supports_cpuid_fault(vcpu)))
2972                         return 1;
2973                 vcpu->arch.msr_misc_features_enables = data;
2974                 break;
2975         default:
2976                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2977                         return xen_hvm_config(vcpu, data);
2978                 if (kvm_pmu_is_valid_msr(vcpu, msr))
2979                         return kvm_pmu_set_msr(vcpu, msr_info);
2980                 if (!ignore_msrs) {
2981                         vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2982                                     msr, data);
2983                         return 1;
2984                 } else {
2985                         if (report_ignored_msrs)
2986                                 vcpu_unimpl(vcpu,
2987                                         "ignored wrmsr: 0x%x data 0x%llx\n",
2988                                         msr, data);
2989                         break;
2990                 }
2991         }
2992         return 0;
2993 }
2994 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2995
2996 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2997 {
2998         u64 data;
2999         u64 mcg_cap = vcpu->arch.mcg_cap;
3000         unsigned bank_num = mcg_cap & 0xff;
3001
3002         switch (msr) {
3003         case MSR_IA32_P5_MC_ADDR:
3004         case MSR_IA32_P5_MC_TYPE:
3005                 data = 0;
3006                 break;
3007         case MSR_IA32_MCG_CAP:
3008                 data = vcpu->arch.mcg_cap;
3009                 break;
3010         case MSR_IA32_MCG_CTL:
3011                 if (!(mcg_cap & MCG_CTL_P) && !host)
3012                         return 1;
3013                 data = vcpu->arch.mcg_ctl;
3014                 break;
3015         case MSR_IA32_MCG_STATUS:
3016                 data = vcpu->arch.mcg_status;
3017                 break;
3018         default:
3019                 if (msr >= MSR_IA32_MC0_CTL &&
3020                     msr < MSR_IA32_MCx_CTL(bank_num)) {
3021                         u32 offset = array_index_nospec(
3022                                 msr - MSR_IA32_MC0_CTL,
3023                                 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3024
3025                         data = vcpu->arch.mce_banks[offset];
3026                         break;
3027                 }
3028                 return 1;
3029         }
3030         *pdata = data;
3031         return 0;
3032 }
3033
3034 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3035 {
3036         switch (msr_info->index) {
3037         case MSR_IA32_PLATFORM_ID:
3038         case MSR_IA32_EBL_CR_POWERON:
3039         case MSR_IA32_DEBUGCTLMSR:
3040         case MSR_IA32_LASTBRANCHFROMIP:
3041         case MSR_IA32_LASTBRANCHTOIP:
3042         case MSR_IA32_LASTINTFROMIP:
3043         case MSR_IA32_LASTINTTOIP:
3044         case MSR_K8_SYSCFG:
3045         case MSR_K8_TSEG_ADDR:
3046         case MSR_K8_TSEG_MASK:
3047         case MSR_VM_HSAVE_PA:
3048         case MSR_K8_INT_PENDING_MSG:
3049         case MSR_AMD64_NB_CFG:
3050         case MSR_FAM10H_MMIO_CONF_BASE:
3051         case MSR_AMD64_BU_CFG2:
3052         case MSR_IA32_PERF_CTL:
3053         case MSR_AMD64_DC_CFG:
3054         case MSR_F15H_EX_CFG:
3055         /*
3056          * Intel Sandy Bridge CPUs must support the RAPL (running average power
3057          * limit) MSRs. Just return 0, as we do not want to expose the host
3058          * data here. Do not conditionalize this on CPUID, as KVM does not do
3059          * so for existing CPU-specific MSRs.
3060          */
3061         case MSR_RAPL_POWER_UNIT:
3062         case MSR_PP0_ENERGY_STATUS:     /* Power plane 0 (core) */
3063         case MSR_PP1_ENERGY_STATUS:     /* Power plane 1 (graphics uncore) */
3064         case MSR_PKG_ENERGY_STATUS:     /* Total package */
3065         case MSR_DRAM_ENERGY_STATUS:    /* DRAM controller */
3066                 msr_info->data = 0;
3067                 break;
3068         case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3069         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3070         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3071         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3072         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3073                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3074                         return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3075                 msr_info->data = 0;
3076                 break;
3077         case MSR_IA32_UCODE_REV:
3078                 msr_info->data = vcpu->arch.microcode_version;
3079                 break;
3080         case MSR_IA32_ARCH_CAPABILITIES:
3081                 if (!msr_info->host_initiated &&
3082                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3083                         return 1;
3084                 msr_info->data = vcpu->arch.arch_capabilities;
3085                 break;
3086         case MSR_IA32_POWER_CTL:
3087                 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3088                 break;
3089         case MSR_IA32_TSC:
3090                 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
3091                 break;
3092         case MSR_MTRRcap:
3093         case 0x200 ... 0x2ff:
3094                 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3095         case 0xcd: /* fsb frequency */
3096                 msr_info->data = 3;
3097                 break;
3098                 /*
3099                  * MSR_EBC_FREQUENCY_ID
3100                  * Conservative value valid for even the basic CPU models.
3101                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3102                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3103                  * and 266MHz for model 3, or 4. Set Core Clock
3104                  * Frequency to System Bus Frequency Ratio to 1 (bits
3105                  * 31:24) even though these are only valid for CPU
3106                  * models > 2, however guests may end up dividing or
3107                  * multiplying by zero otherwise.
3108                  */
3109         case MSR_EBC_FREQUENCY_ID:
3110                 msr_info->data = 1 << 24;
3111                 break;
3112         case MSR_IA32_APICBASE:
3113                 msr_info->data = kvm_get_apic_base(vcpu);
3114                 break;
3115         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
3116                 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3117         case MSR_IA32_TSCDEADLINE:
3118                 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3119                 break;
3120         case MSR_IA32_TSC_ADJUST:
3121                 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3122                 break;
3123         case MSR_IA32_MISC_ENABLE:
3124                 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3125                 break;
3126         case MSR_IA32_SMBASE:
3127                 if (!msr_info->host_initiated)
3128                         return 1;
3129                 msr_info->data = vcpu->arch.smbase;
3130                 break;
3131         case MSR_SMI_COUNT:
3132                 msr_info->data = vcpu->arch.smi_count;
3133                 break;
3134         case MSR_IA32_PERF_STATUS:
3135                 /* TSC increment by tick */
3136                 msr_info->data = 1000ULL;
3137                 /* CPU multiplier */
3138                 msr_info->data |= (((uint64_t)4ULL) << 40);
3139                 break;
3140         case MSR_EFER:
3141                 msr_info->data = vcpu->arch.efer;
3142                 break;
3143         case MSR_KVM_WALL_CLOCK:
3144         case MSR_KVM_WALL_CLOCK_NEW:
3145                 msr_info->data = vcpu->kvm->arch.wall_clock;
3146                 break;
3147         case MSR_KVM_SYSTEM_TIME:
3148         case MSR_KVM_SYSTEM_TIME_NEW:
3149                 msr_info->data = vcpu->arch.time;
3150                 break;
3151         case MSR_KVM_ASYNC_PF_EN:
3152                 msr_info->data = vcpu->arch.apf.msr_val;
3153                 break;
3154         case MSR_KVM_STEAL_TIME:
3155                 msr_info->data = vcpu->arch.st.msr_val;
3156                 break;
3157         case MSR_KVM_PV_EOI_EN:
3158                 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3159                 break;
3160         case MSR_KVM_POLL_CONTROL:
3161                 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3162                 break;
3163         case MSR_IA32_P5_MC_ADDR:
3164         case MSR_IA32_P5_MC_TYPE:
3165         case MSR_IA32_MCG_CAP:
3166         case MSR_IA32_MCG_CTL:
3167         case MSR_IA32_MCG_STATUS:
3168         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3169                 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3170                                    msr_info->host_initiated);
3171         case MSR_IA32_XSS:
3172                 if (!msr_info->host_initiated &&
3173                     !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3174                         return 1;
3175                 msr_info->data = vcpu->arch.ia32_xss;
3176                 break;
3177         case MSR_K7_CLK_CTL:
3178                 /*
3179                  * Provide expected ramp-up count for K7. All other
3180                  * are set to zero, indicating minimum divisors for
3181                  * every field.
3182                  *
3183                  * This prevents guest kernels on AMD host with CPU
3184                  * type 6, model 8 and higher from exploding due to
3185                  * the rdmsr failing.
3186                  */
3187                 msr_info->data = 0x20000000;
3188                 break;
3189         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3190         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3191         case HV_X64_MSR_CRASH_CTL:
3192         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3193         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3194         case HV_X64_MSR_TSC_EMULATION_CONTROL:
3195         case HV_X64_MSR_TSC_EMULATION_STATUS:
3196                 return kvm_hv_get_msr_common(vcpu,
3197                                              msr_info->index, &msr_info->data,
3198                                              msr_info->host_initiated);
3199         case MSR_IA32_BBL_CR_CTL3:
3200                 /* This legacy MSR exists but isn't fully documented in current
3201                  * silicon.  It is however accessed by winxp in very narrow
3202                  * scenarios where it sets bit #19, itself documented as
3203                  * a "reserved" bit.  Best effort attempt to source coherent
3204                  * read data here should the balance of the register be
3205                  * interpreted by the guest:
3206                  *
3207                  * L2 cache control register 3: 64GB range, 256KB size,
3208                  * enabled, latency 0x1, configured
3209                  */
3210                 msr_info->data = 0xbe702111;
3211                 break;
3212         case MSR_AMD64_OSVW_ID_LENGTH:
3213                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3214                         return 1;
3215                 msr_info->data = vcpu->arch.osvw.length;
3216                 break;
3217         case MSR_AMD64_OSVW_STATUS:
3218                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3219                         return 1;
3220                 msr_info->data = vcpu->arch.osvw.status;
3221                 break;
3222         case MSR_PLATFORM_INFO:
3223                 if (!msr_info->host_initiated &&
3224                     !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3225                         return 1;
3226                 msr_info->data = vcpu->arch.msr_platform_info;
3227                 break;
3228         case MSR_MISC_FEATURES_ENABLES:
3229                 msr_info->data = vcpu->arch.msr_misc_features_enables;
3230                 break;
3231         case MSR_K7_HWCR:
3232                 msr_info->data = vcpu->arch.msr_hwcr;
3233                 break;
3234         default:
3235                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3236                         return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3237                 if (!ignore_msrs) {
3238                         vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3239                                                msr_info->index);
3240                         return 1;
3241                 } else {
3242                         if (report_ignored_msrs)
3243                                 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3244                                         msr_info->index);
3245                         msr_info->data = 0;
3246                 }
3247                 break;
3248         }
3249         return 0;
3250 }
3251 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3252
3253 /*
3254  * Read or write a bunch of msrs. All parameters are kernel addresses.
3255  *
3256  * @return number of msrs set successfully.
3257  */
3258 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3259                     struct kvm_msr_entry *entries,
3260                     int (*do_msr)(struct kvm_vcpu *vcpu,
3261                                   unsigned index, u64 *data))
3262 {
3263         int i;
3264
3265         for (i = 0; i < msrs->nmsrs; ++i)
3266                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3267                         break;
3268
3269         return i;
3270 }
3271
3272 /*
3273  * Read or write a bunch of msrs. Parameters are user addresses.
3274  *
3275  * @return number of msrs set successfully.
3276  */
3277 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3278                   int (*do_msr)(struct kvm_vcpu *vcpu,
3279                                 unsigned index, u64 *data),
3280                   int writeback)
3281 {
3282         struct kvm_msrs msrs;
3283         struct kvm_msr_entry *entries;
3284         int r, n;
3285         unsigned size;
3286
3287         r = -EFAULT;
3288         if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3289                 goto out;
3290
3291         r = -E2BIG;
3292         if (msrs.nmsrs >= MAX_IO_MSRS)
3293                 goto out;
3294
3295         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3296         entries = memdup_user(user_msrs->entries, size);
3297         if (IS_ERR(entries)) {
3298                 r = PTR_ERR(entries);
3299                 goto out;
3300         }
3301
3302         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3303         if (r < 0)
3304                 goto out_free;
3305
3306         r = -EFAULT;
3307         if (writeback && copy_to_user(user_msrs->entries, entries, size))
3308                 goto out_free;
3309
3310         r = n;
3311
3312 out_free:
3313         kfree(entries);
3314 out:
3315         return r;
3316 }
3317
3318 static inline bool kvm_can_mwait_in_guest(void)
3319 {
3320         return boot_cpu_has(X86_FEATURE_MWAIT) &&
3321                 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3322                 boot_cpu_has(X86_FEATURE_ARAT);
3323 }
3324
3325 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3326 {
3327         int r = 0;
3328
3329         switch (ext) {
3330         case KVM_CAP_IRQCHIP:
3331         case KVM_CAP_HLT:
3332         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3333         case KVM_CAP_SET_TSS_ADDR:
3334         case KVM_CAP_EXT_CPUID:
3335         case KVM_CAP_EXT_EMUL_CPUID:
3336         case KVM_CAP_CLOCKSOURCE:
3337         case KVM_CAP_PIT:
3338         case KVM_CAP_NOP_IO_DELAY:
3339         case KVM_CAP_MP_STATE:
3340         case KVM_CAP_SYNC_MMU:
3341         case KVM_CAP_USER_NMI:
3342         case KVM_CAP_REINJECT_CONTROL:
3343         case KVM_CAP_IRQ_INJECT_STATUS:
3344         case KVM_CAP_IOEVENTFD:
3345         case KVM_CAP_IOEVENTFD_NO_LENGTH:
3346         case KVM_CAP_PIT2:
3347         case KVM_CAP_PIT_STATE2:
3348         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3349         case KVM_CAP_XEN_HVM:
3350         case KVM_CAP_VCPU_EVENTS:
3351         case KVM_CAP_HYPERV:
3352         case KVM_CAP_HYPERV_VAPIC:
3353         case KVM_CAP_HYPERV_SPIN:
3354         case KVM_CAP_HYPERV_SYNIC:
3355         case KVM_CAP_HYPERV_SYNIC2:
3356         case KVM_CAP_HYPERV_VP_INDEX:
3357         case KVM_CAP_HYPERV_EVENTFD:
3358         case KVM_CAP_HYPERV_TLBFLUSH:
3359         case KVM_CAP_HYPERV_SEND_IPI:
3360         case KVM_CAP_HYPERV_CPUID:
3361         case KVM_CAP_PCI_SEGMENT:
3362         case KVM_CAP_DEBUGREGS:
3363         case KVM_CAP_X86_ROBUST_SINGLESTEP:
3364         case KVM_CAP_XSAVE:
3365         case KVM_CAP_ASYNC_PF:
3366         case KVM_CAP_GET_TSC_KHZ:
3367         case KVM_CAP_KVMCLOCK_CTRL:
3368         case KVM_CAP_READONLY_MEM:
3369         case KVM_CAP_HYPERV_TIME:
3370         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3371         case KVM_CAP_TSC_DEADLINE_TIMER:
3372         case KVM_CAP_DISABLE_QUIRKS:
3373         case KVM_CAP_SET_BOOT_CPU_ID:
3374         case KVM_CAP_SPLIT_IRQCHIP:
3375         case KVM_CAP_IMMEDIATE_EXIT:
3376         case KVM_CAP_PMU_EVENT_FILTER:
3377         case KVM_CAP_GET_MSR_FEATURES:
3378         case KVM_CAP_MSR_PLATFORM_INFO:
3379         case KVM_CAP_EXCEPTION_PAYLOAD:
3380         case KVM_CAP_SET_GUEST_DEBUG:
3381                 r = 1;
3382                 break;
3383         case KVM_CAP_SYNC_REGS:
3384                 r = KVM_SYNC_X86_VALID_FIELDS;
3385                 break;
3386         case KVM_CAP_ADJUST_CLOCK:
3387                 r = KVM_CLOCK_TSC_STABLE;
3388                 break;
3389         case KVM_CAP_X86_DISABLE_EXITS:
3390                 r |=  KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3391                       KVM_X86_DISABLE_EXITS_CSTATE;
3392                 if(kvm_can_mwait_in_guest())
3393                         r |= KVM_X86_DISABLE_EXITS_MWAIT;
3394                 break;
3395         case KVM_CAP_X86_SMM:
3396                 /* SMBASE is usually relocated above 1M on modern chipsets,
3397                  * and SMM handlers might indeed rely on 4G segment limits,
3398                  * so do not report SMM to be available if real mode is
3399                  * emulated via vm86 mode.  Still, do not go to great lengths
3400                  * to avoid userspace's usage of the feature, because it is a
3401                  * fringe case that is not enabled except via specific settings
3402                  * of the module parameters.
3403                  */
3404                 r = kvm_x86_ops.has_emulated_msr(MSR_IA32_SMBASE);
3405                 break;
3406         case KVM_CAP_VAPIC:
3407                 r = !kvm_x86_ops.cpu_has_accelerated_tpr();
3408                 break;
3409         case KVM_CAP_NR_VCPUS:
3410                 r = KVM_SOFT_MAX_VCPUS;
3411                 break;
3412         case KVM_CAP_MAX_VCPUS:
3413                 r = KVM_MAX_VCPUS;
3414                 break;
3415         case KVM_CAP_MAX_VCPU_ID:
3416                 r = KVM_MAX_VCPU_ID;
3417                 break;
3418         case KVM_CAP_PV_MMU:    /* obsolete */
3419                 r = 0;
3420                 break;
3421         case KVM_CAP_MCE:
3422                 r = KVM_MAX_MCE_BANKS;
3423                 break;
3424         case KVM_CAP_XCRS:
3425                 r = boot_cpu_has(X86_FEATURE_XSAVE);
3426                 break;
3427         case KVM_CAP_TSC_CONTROL:
3428                 r = kvm_has_tsc_control;
3429                 break;
3430         case KVM_CAP_X2APIC_API:
3431                 r = KVM_X2APIC_API_VALID_FLAGS;
3432                 break;
3433         case KVM_CAP_NESTED_STATE:
3434                 r = kvm_x86_ops.get_nested_state ?
3435                         kvm_x86_ops.get_nested_state(NULL, NULL, 0) : 0;
3436                 break;
3437         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3438                 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3439                 break;
3440         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3441                 r = kvm_x86_ops.nested_enable_evmcs != NULL;
3442                 break;
3443         default:
3444                 break;
3445         }
3446         return r;
3447
3448 }
3449
3450 long kvm_arch_dev_ioctl(struct file *filp,
3451                         unsigned int ioctl, unsigned long arg)
3452 {
3453         void __user *argp = (void __user *)arg;
3454         long r;
3455
3456         switch (ioctl) {
3457         case KVM_GET_MSR_INDEX_LIST: {
3458                 struct kvm_msr_list __user *user_msr_list = argp;
3459                 struct kvm_msr_list msr_list;
3460                 unsigned n;
3461
3462                 r = -EFAULT;
3463                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3464                         goto out;
3465                 n = msr_list.nmsrs;
3466                 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3467                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3468                         goto out;
3469                 r = -E2BIG;
3470                 if (n < msr_list.nmsrs)
3471                         goto out;
3472                 r = -EFAULT;
3473                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3474                                  num_msrs_to_save * sizeof(u32)))
3475                         goto out;
3476                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3477                                  &emulated_msrs,
3478                                  num_emulated_msrs * sizeof(u32)))
3479                         goto out;
3480                 r = 0;
3481                 break;
3482         }
3483         case KVM_GET_SUPPORTED_CPUID:
3484         case KVM_GET_EMULATED_CPUID: {
3485                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3486                 struct kvm_cpuid2 cpuid;
3487
3488                 r = -EFAULT;
3489                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3490                         goto out;
3491
3492                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3493                                             ioctl);
3494                 if (r)
3495                         goto out;
3496
3497                 r = -EFAULT;
3498                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3499                         goto out;
3500                 r = 0;
3501                 break;
3502         }
3503         case KVM_X86_GET_MCE_CAP_SUPPORTED:
3504                 r = -EFAULT;
3505                 if (copy_to_user(argp, &kvm_mce_cap_supported,
3506                                  sizeof(kvm_mce_cap_supported)))
3507                         goto out;
3508                 r = 0;
3509                 break;
3510         case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3511                 struct kvm_msr_list __user *user_msr_list = argp;
3512                 struct kvm_msr_list msr_list;
3513                 unsigned int n;
3514
3515                 r = -EFAULT;
3516                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3517                         goto out;
3518                 n = msr_list.nmsrs;
3519                 msr_list.nmsrs = num_msr_based_features;
3520                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3521                         goto out;
3522                 r = -E2BIG;
3523                 if (n < msr_list.nmsrs)
3524                         goto out;
3525                 r = -EFAULT;
3526                 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3527                                  num_msr_based_features * sizeof(u32)))
3528                         goto out;
3529                 r = 0;
3530                 break;
3531         }
3532         case KVM_GET_MSRS:
3533                 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3534                 break;
3535         default:
3536                 r = -EINVAL;
3537                 break;
3538         }
3539 out:
3540         return r;
3541 }
3542
3543 static void wbinvd_ipi(void *garbage)
3544 {
3545         wbinvd();
3546 }
3547
3548 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3549 {
3550         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3551 }
3552
3553 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3554 {
3555         /* Address WBINVD may be executed by guest */
3556         if (need_emulate_wbinvd(vcpu)) {
3557                 if (kvm_x86_ops.has_wbinvd_exit())
3558                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3559                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3560                         smp_call_function_single(vcpu->cpu,
3561                                         wbinvd_ipi, NULL, 1);
3562         }
3563
3564         kvm_x86_ops.vcpu_load(vcpu, cpu);
3565
3566         /* Save host pkru register if supported */
3567         vcpu->arch.host_pkru = read_pkru();
3568
3569         /* Apply any externally detected TSC adjustments (due to suspend) */
3570         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3571                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3572                 vcpu->arch.tsc_offset_adjustment = 0;
3573                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3574         }
3575
3576         if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3577                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3578                                 rdtsc() - vcpu->arch.last_host_tsc;
3579                 if (tsc_delta < 0)
3580                         mark_tsc_unstable("KVM discovered backwards TSC");
3581
3582                 if (kvm_check_tsc_unstable()) {
3583                         u64 offset = kvm_compute_tsc_offset(vcpu,
3584                                                 vcpu->arch.last_guest_tsc);
3585                         kvm_vcpu_write_tsc_offset(vcpu, offset);
3586                         vcpu->arch.tsc_catchup = 1;
3587                 }
3588
3589                 if (kvm_lapic_hv_timer_in_use(vcpu))
3590                         kvm_lapic_restart_hv_timer(vcpu);
3591
3592                 /*
3593                  * On a host with synchronized TSC, there is no need to update
3594                  * kvmclock on vcpu->cpu migration
3595                  */
3596                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3597                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3598                 if (vcpu->cpu != cpu)
3599                         kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3600                 vcpu->cpu = cpu;
3601         }
3602
3603         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3604 }
3605
3606 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3607 {
3608         struct kvm_host_map map;
3609         struct kvm_steal_time *st;
3610
3611         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3612                 return;
3613
3614         if (vcpu->arch.st.preempted)
3615                 return;
3616
3617         if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3618                         &vcpu->arch.st.cache, true))
3619                 return;
3620
3621         st = map.hva +
3622                 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
3623
3624         st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
3625
3626         kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
3627 }
3628
3629 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3630 {
3631         int idx;
3632
3633         if (vcpu->preempted)
3634                 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu);
3635
3636         /*
3637          * Disable page faults because we're in atomic context here.
3638          * kvm_write_guest_offset_cached() would call might_fault()
3639          * that relies on pagefault_disable() to tell if there's a
3640          * bug. NOTE: the write to guest memory may not go through if
3641          * during postcopy live migration or if there's heavy guest
3642          * paging.
3643          */
3644         pagefault_disable();
3645         /*
3646          * kvm_memslots() will be called by
3647          * kvm_write_guest_offset_cached() so take the srcu lock.
3648          */
3649         idx = srcu_read_lock(&vcpu->kvm->srcu);
3650         kvm_steal_time_set_preempted(vcpu);
3651         srcu_read_unlock(&vcpu->kvm->srcu, idx);
3652         pagefault_enable();
3653         kvm_x86_ops.vcpu_put(vcpu);
3654         vcpu->arch.last_host_tsc = rdtsc();
3655         /*
3656          * If userspace has set any breakpoints or watchpoints, dr6 is restored
3657          * on every vmexit, but if not, we might have a stale dr6 from the
3658          * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3659          */
3660         set_debugreg(0, 6);
3661 }
3662
3663 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3664                                     struct kvm_lapic_state *s)
3665 {
3666         if (vcpu->arch.apicv_active)
3667                 kvm_x86_ops.sync_pir_to_irr(vcpu);
3668
3669         return kvm_apic_get_state(vcpu, s);
3670 }
3671
3672 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3673                                     struct kvm_lapic_state *s)
3674 {
3675         int r;
3676
3677         r = kvm_apic_set_state(vcpu, s);
3678         if (r)
3679                 return r;
3680         update_cr8_intercept(vcpu);
3681
3682         return 0;
3683 }
3684
3685 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3686 {
3687         return (!lapic_in_kernel(vcpu) ||
3688                 kvm_apic_accept_pic_intr(vcpu));
3689 }
3690
3691 /*
3692  * if userspace requested an interrupt window, check that the
3693  * interrupt window is open.
3694  *
3695  * No need to exit to userspace if we already have an interrupt queued.
3696  */
3697 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3698 {
3699         return kvm_arch_interrupt_allowed(vcpu) &&
3700                 !kvm_cpu_has_interrupt(vcpu) &&
3701                 !kvm_event_needs_reinjection(vcpu) &&
3702                 kvm_cpu_accept_dm_intr(vcpu);
3703 }
3704
3705 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3706                                     struct kvm_interrupt *irq)
3707 {
3708         if (irq->irq >= KVM_NR_INTERRUPTS)
3709                 return -EINVAL;
3710
3711         if (!irqchip_in_kernel(vcpu->kvm)) {
3712                 kvm_queue_interrupt(vcpu, irq->irq, false);
3713                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3714                 return 0;
3715         }
3716
3717         /*
3718          * With in-kernel LAPIC, we only use this to inject EXTINT, so
3719          * fail for in-kernel 8259.
3720          */
3721         if (pic_in_kernel(vcpu->kvm))
3722                 return -ENXIO;
3723
3724         if (vcpu->arch.pending_external_vector != -1)
3725                 return -EEXIST;
3726
3727         vcpu->arch.pending_external_vector = irq->irq;
3728         kvm_make_request(KVM_REQ_EVENT, vcpu);
3729         return 0;
3730 }
3731
3732 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3733 {
3734         kvm_inject_nmi(vcpu);
3735
3736         return 0;
3737 }
3738
3739 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3740 {
3741         kvm_make_request(KVM_REQ_SMI, vcpu);
3742
3743         return 0;
3744 }
3745
3746 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3747                                            struct kvm_tpr_access_ctl *tac)
3748 {
3749         if (tac->flags)
3750                 return -EINVAL;
3751         vcpu->arch.tpr_access_reporting = !!tac->enabled;
3752         return 0;
3753 }
3754
3755 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3756                                         u64 mcg_cap)
3757 {
3758         int r;
3759         unsigned bank_num = mcg_cap & 0xff, bank;
3760
3761         r = -EINVAL;
3762         if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
3763                 goto out;
3764         if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3765                 goto out;
3766         r = 0;
3767         vcpu->arch.mcg_cap = mcg_cap;
3768         /* Init IA32_MCG_CTL to all 1s */
3769         if (mcg_cap & MCG_CTL_P)
3770                 vcpu->arch.mcg_ctl = ~(u64)0;
3771         /* Init IA32_MCi_CTL to all 1s */
3772         for (bank = 0; bank < bank_num; bank++)
3773                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3774
3775         kvm_x86_ops.setup_mce(vcpu);
3776 out:
3777         return r;
3778 }
3779
3780 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3781                                       struct kvm_x86_mce *mce)
3782 {
3783         u64 mcg_cap = vcpu->arch.mcg_cap;
3784         unsigned bank_num = mcg_cap & 0xff;
3785         u64 *banks = vcpu->arch.mce_banks;
3786
3787         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3788                 return -EINVAL;
3789         /*
3790          * if IA32_MCG_CTL is not all 1s, the uncorrected error
3791          * reporting is disabled
3792          */
3793         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3794             vcpu->arch.mcg_ctl != ~(u64)0)
3795                 return 0;
3796         banks += 4 * mce->bank;
3797         /*
3798          * if IA32_MCi_CTL is not all 1s, the uncorrected error
3799          * reporting is disabled for the bank
3800          */
3801         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3802                 return 0;
3803         if (mce->status & MCI_STATUS_UC) {
3804                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3805                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3806                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3807                         return 0;
3808                 }
3809                 if (banks[1] & MCI_STATUS_VAL)
3810                         mce->status |= MCI_STATUS_OVER;
3811                 banks[2] = mce->addr;
3812                 banks[3] = mce->misc;
3813                 vcpu->arch.mcg_status = mce->mcg_status;
3814                 banks[1] = mce->status;
3815                 kvm_queue_exception(vcpu, MC_VECTOR);
3816         } else if (!(banks[1] & MCI_STATUS_VAL)
3817                    || !(banks[1] & MCI_STATUS_UC)) {
3818                 if (banks[1] & MCI_STATUS_VAL)
3819                         mce->status |= MCI_STATUS_OVER;
3820                 banks[2] = mce->addr;
3821                 banks[3] = mce->misc;
3822                 banks[1] = mce->status;
3823         } else
3824                 banks[1] |= MCI_STATUS_OVER;
3825         return 0;
3826 }
3827
3828 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3829                                                struct kvm_vcpu_events *events)
3830 {
3831         process_nmi(vcpu);
3832
3833         /*
3834          * In guest mode, payload delivery should be deferred,
3835          * so that the L1 hypervisor can intercept #PF before
3836          * CR2 is modified (or intercept #DB before DR6 is
3837          * modified under nVMX). Unless the per-VM capability,
3838          * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
3839          * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
3840          * opportunistically defer the exception payload, deliver it if the
3841          * capability hasn't been requested before processing a
3842          * KVM_GET_VCPU_EVENTS.
3843          */
3844         if (!vcpu->kvm->arch.exception_payload_enabled &&
3845             vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
3846                 kvm_deliver_exception_payload(vcpu);
3847
3848         /*
3849          * The API doesn't provide the instruction length for software
3850          * exceptions, so don't report them. As long as the guest RIP
3851          * isn't advanced, we should expect to encounter the exception
3852          * again.
3853          */
3854         if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3855                 events->exception.injected = 0;
3856                 events->exception.pending = 0;
3857         } else {
3858                 events->exception.injected = vcpu->arch.exception.injected;
3859                 events->exception.pending = vcpu->arch.exception.pending;
3860                 /*
3861                  * For ABI compatibility, deliberately conflate
3862                  * pending and injected exceptions when
3863                  * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3864                  */
3865                 if (!vcpu->kvm->arch.exception_payload_enabled)
3866                         events->exception.injected |=
3867                                 vcpu->arch.exception.pending;
3868         }
3869         events->exception.nr = vcpu->arch.exception.nr;
3870         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3871         events->exception.error_code = vcpu->arch.exception.error_code;
3872         events->exception_has_payload = vcpu->arch.exception.has_payload;
3873         events->exception_payload = vcpu->arch.exception.payload;
3874
3875         events->interrupt.injected =
3876                 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3877         events->interrupt.nr = vcpu->arch.interrupt.nr;
3878         events->interrupt.soft = 0;
3879         events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
3880
3881         events->nmi.injected = vcpu->arch.nmi_injected;
3882         events->nmi.pending = vcpu->arch.nmi_pending != 0;
3883         events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu);
3884         events->nmi.pad = 0;
3885
3886         events->sipi_vector = 0; /* never valid when reporting to user space */
3887
3888         events->smi.smm = is_smm(vcpu);
3889         events->smi.pending = vcpu->arch.smi_pending;
3890         events->smi.smm_inside_nmi =
3891                 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3892         events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3893
3894         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3895                          | KVM_VCPUEVENT_VALID_SHADOW
3896                          | KVM_VCPUEVENT_VALID_SMM);
3897         if (vcpu->kvm->arch.exception_payload_enabled)
3898                 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3899
3900         memset(&events->reserved, 0, sizeof(events->reserved));
3901 }
3902
3903 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3904
3905 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3906                                               struct kvm_vcpu_events *events)
3907 {
3908         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3909                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3910                               | KVM_VCPUEVENT_VALID_SHADOW
3911                               | KVM_VCPUEVENT_VALID_SMM
3912                               | KVM_VCPUEVENT_VALID_PAYLOAD))
3913                 return -EINVAL;
3914
3915         if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3916                 if (!vcpu->kvm->arch.exception_payload_enabled)
3917                         return -EINVAL;
3918                 if (events->exception.pending)
3919                         events->exception.injected = 0;
3920                 else
3921                         events->exception_has_payload = 0;
3922         } else {
3923                 events->exception.pending = 0;
3924                 events->exception_has_payload = 0;
3925         }
3926
3927         if ((events->exception.injected || events->exception.pending) &&
3928             (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3929                 return -EINVAL;
3930
3931         /* INITs are latched while in SMM */
3932         if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3933             (events->smi.smm || events->smi.pending) &&
3934             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3935                 return -EINVAL;
3936
3937         process_nmi(vcpu);
3938         vcpu->arch.exception.injected = events->exception.injected;
3939         vcpu->arch.exception.pending = events->exception.pending;
3940         vcpu->arch.exception.nr = events->exception.nr;
3941         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3942         vcpu->arch.exception.error_code = events->exception.error_code;
3943         vcpu->arch.exception.has_payload = events->exception_has_payload;
3944         vcpu->arch.exception.payload = events->exception_payload;
3945
3946         vcpu->arch.interrupt.injected = events->interrupt.injected;
3947         vcpu->arch.interrupt.nr = events->interrupt.nr;
3948         vcpu->arch.interrupt.soft = events->interrupt.soft;
3949         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3950                 kvm_x86_ops.set_interrupt_shadow(vcpu,
3951                                                   events->interrupt.shadow);
3952
3953         vcpu->arch.nmi_injected = events->nmi.injected;
3954         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3955                 vcpu->arch.nmi_pending = events->nmi.pending;
3956         kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked);
3957
3958         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3959             lapic_in_kernel(vcpu))
3960                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3961
3962         if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3963                 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3964                         if (events->smi.smm)
3965                                 vcpu->arch.hflags |= HF_SMM_MASK;
3966                         else
3967                                 vcpu->arch.hflags &= ~HF_SMM_MASK;
3968                         kvm_smm_changed(vcpu);
3969                 }
3970
3971                 vcpu->arch.smi_pending = events->smi.pending;
3972
3973                 if (events->smi.smm) {
3974                         if (events->smi.smm_inside_nmi)
3975                                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3976                         else
3977                                 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3978                 }
3979
3980                 if (lapic_in_kernel(vcpu)) {
3981                         if (events->smi.latched_init)
3982                                 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3983                         else
3984                                 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3985                 }
3986         }
3987
3988         kvm_make_request(KVM_REQ_EVENT, vcpu);
3989
3990         return 0;
3991 }
3992
3993 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3994                                              struct kvm_debugregs *dbgregs)
3995 {
3996         unsigned long val;
3997
3998         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3999         kvm_get_dr(vcpu, 6, &val);
4000         dbgregs->dr6 = val;
4001         dbgregs->dr7 = vcpu->arch.dr7;
4002         dbgregs->flags = 0;
4003         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4004 }
4005
4006 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4007                                             struct kvm_debugregs *dbgregs)
4008 {
4009         if (dbgregs->flags)
4010                 return -EINVAL;
4011
4012         if (dbgregs->dr6 & ~0xffffffffull)
4013                 return -EINVAL;
4014         if (dbgregs->dr7 & ~0xffffffffull)
4015                 return -EINVAL;
4016
4017         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4018         kvm_update_dr0123(vcpu);
4019         vcpu->arch.dr6 = dbgregs->dr6;
4020         vcpu->arch.dr7 = dbgregs->dr7;
4021         kvm_update_dr7(vcpu);
4022
4023         return 0;
4024 }
4025
4026 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4027
4028 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4029 {
4030         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4031         u64 xstate_bv = xsave->header.xfeatures;
4032         u64 valid;
4033
4034         /*
4035          * Copy legacy XSAVE area, to avoid complications with CPUID
4036          * leaves 0 and 1 in the loop below.
4037          */
4038         memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4039
4040         /* Set XSTATE_BV */
4041         xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4042         *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4043
4044         /*
4045          * Copy each region from the possibly compacted offset to the
4046          * non-compacted offset.
4047          */
4048         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4049         while (valid) {
4050                 u64 xfeature_mask = valid & -valid;
4051                 int xfeature_nr = fls64(xfeature_mask) - 1;
4052                 void *src = get_xsave_addr(xsave, xfeature_nr);
4053
4054                 if (src) {
4055                         u32 size, offset, ecx, edx;
4056                         cpuid_count(XSTATE_CPUID, xfeature_nr,
4057                                     &size, &offset, &ecx, &edx);
4058                         if (xfeature_nr == XFEATURE_PKRU)
4059                                 memcpy(dest + offset, &vcpu->arch.pkru,
4060                                        sizeof(vcpu->arch.pkru));
4061                         else
4062                                 memcpy(dest + offset, src, size);
4063
4064                 }
4065
4066                 valid -= xfeature_mask;
4067         }
4068 }
4069
4070 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4071 {
4072         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4073         u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4074         u64 valid;
4075
4076         /*
4077          * Copy legacy XSAVE area, to avoid complications with CPUID
4078          * leaves 0 and 1 in the loop below.
4079          */
4080         memcpy(xsave, src, XSAVE_HDR_OFFSET);
4081
4082         /* Set XSTATE_BV and possibly XCOMP_BV.  */
4083         xsave->header.xfeatures = xstate_bv;
4084         if (boot_cpu_has(X86_FEATURE_XSAVES))
4085                 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4086
4087         /*
4088          * Copy each region from the non-compacted offset to the
4089          * possibly compacted offset.
4090          */
4091         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4092         while (valid) {
4093                 u64 xfeature_mask = valid & -valid;
4094                 int xfeature_nr = fls64(xfeature_mask) - 1;
4095                 void *dest = get_xsave_addr(xsave, xfeature_nr);
4096
4097                 if (dest) {
4098                         u32 size, offset, ecx, edx;
4099                         cpuid_count(XSTATE_CPUID, xfeature_nr,
4100                                     &size, &offset, &ecx, &edx);
4101                         if (xfeature_nr == XFEATURE_PKRU)
4102                                 memcpy(&vcpu->arch.pkru, src + offset,
4103                                        sizeof(vcpu->arch.pkru));
4104                         else
4105                                 memcpy(dest, src + offset, size);
4106                 }
4107
4108                 valid -= xfeature_mask;
4109         }
4110 }
4111
4112 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4113                                          struct kvm_xsave *guest_xsave)
4114 {
4115         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4116                 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4117                 fill_xsave((u8 *) guest_xsave->region, vcpu);
4118         } else {
4119                 memcpy(guest_xsave->region,
4120                         &vcpu->arch.guest_fpu->state.fxsave,
4121                         sizeof(struct fxregs_state));
4122                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4123                         XFEATURE_MASK_FPSSE;
4124         }
4125 }
4126
4127 #define XSAVE_MXCSR_OFFSET 24
4128
4129 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4130                                         struct kvm_xsave *guest_xsave)
4131 {
4132         u64 xstate_bv =
4133                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4134         u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4135
4136         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4137                 /*
4138                  * Here we allow setting states that are not present in
4139                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
4140                  * with old userspace.
4141                  */
4142                 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4143                         return -EINVAL;
4144                 load_xsave(vcpu, (u8 *)guest_xsave->region);
4145         } else {
4146                 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4147                         mxcsr & ~mxcsr_feature_mask)
4148                         return -EINVAL;
4149                 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4150                         guest_xsave->region, sizeof(struct fxregs_state));
4151         }
4152         return 0;
4153 }
4154
4155 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4156                                         struct kvm_xcrs *guest_xcrs)
4157 {
4158         if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4159                 guest_xcrs->nr_xcrs = 0;
4160                 return;
4161         }
4162
4163         guest_xcrs->nr_xcrs = 1;
4164         guest_xcrs->flags = 0;
4165         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4166         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4167 }
4168
4169 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4170                                        struct kvm_xcrs *guest_xcrs)
4171 {
4172         int i, r = 0;
4173
4174         if (!boot_cpu_has(X86_FEATURE_XSAVE))
4175                 return -EINVAL;
4176
4177         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4178                 return -EINVAL;
4179
4180         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4181                 /* Only support XCR0 currently */
4182                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4183                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4184                                 guest_xcrs->xcrs[i].value);
4185                         break;
4186                 }
4187         if (r)
4188                 r = -EINVAL;
4189         return r;
4190 }
4191
4192 /*
4193  * kvm_set_guest_paused() indicates to the guest kernel that it has been
4194  * stopped by the hypervisor.  This function will be called from the host only.
4195  * EINVAL is returned when the host attempts to set the flag for a guest that
4196  * does not support pv clocks.
4197  */
4198 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4199 {
4200         if (!vcpu->arch.pv_time_enabled)
4201                 return -EINVAL;
4202         vcpu->arch.pvclock_set_guest_stopped_request = true;
4203         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4204         return 0;
4205 }
4206
4207 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4208                                      struct kvm_enable_cap *cap)
4209 {
4210         int r;
4211         uint16_t vmcs_version;
4212         void __user *user_ptr;
4213
4214         if (cap->flags)
4215                 return -EINVAL;
4216
4217         switch (cap->cap) {
4218         case KVM_CAP_HYPERV_SYNIC2:
4219                 if (cap->args[0])
4220                         return -EINVAL;
4221                 /* fall through */
4222
4223         case KVM_CAP_HYPERV_SYNIC:
4224                 if (!irqchip_in_kernel(vcpu->kvm))
4225                         return -EINVAL;
4226                 return kvm_hv_activate_synic(vcpu, cap->cap ==
4227                                              KVM_CAP_HYPERV_SYNIC2);
4228         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4229                 if (!kvm_x86_ops.nested_enable_evmcs)
4230                         return -ENOTTY;
4231                 r = kvm_x86_ops.nested_enable_evmcs(vcpu, &vmcs_version);
4232                 if (!r) {
4233                         user_ptr = (void __user *)(uintptr_t)cap->args[0];
4234                         if (copy_to_user(user_ptr, &vmcs_version,
4235                                          sizeof(vmcs_version)))
4236                                 r = -EFAULT;
4237                 }
4238                 return r;
4239         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4240                 if (!kvm_x86_ops.enable_direct_tlbflush)
4241                         return -ENOTTY;
4242
4243                 return kvm_x86_ops.enable_direct_tlbflush(vcpu);
4244
4245         default:
4246                 return -EINVAL;
4247         }
4248 }
4249
4250 long kvm_arch_vcpu_ioctl(struct file *filp,
4251                          unsigned int ioctl, unsigned long arg)
4252 {
4253         struct kvm_vcpu *vcpu = filp->private_data;
4254         void __user *argp = (void __user *)arg;
4255         int r;
4256         union {
4257                 struct kvm_lapic_state *lapic;
4258                 struct kvm_xsave *xsave;
4259                 struct kvm_xcrs *xcrs;
4260                 void *buffer;
4261         } u;
4262
4263         vcpu_load(vcpu);
4264
4265         u.buffer = NULL;
4266         switch (ioctl) {
4267         case KVM_GET_LAPIC: {
4268                 r = -EINVAL;
4269                 if (!lapic_in_kernel(vcpu))
4270                         goto out;
4271                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4272                                 GFP_KERNEL_ACCOUNT);
4273
4274                 r = -ENOMEM;
4275                 if (!u.lapic)
4276                         goto out;
4277                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4278                 if (r)
4279                         goto out;
4280                 r = -EFAULT;
4281                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4282                         goto out;
4283                 r = 0;
4284                 break;
4285         }
4286         case KVM_SET_LAPIC: {
4287                 r = -EINVAL;
4288                 if (!lapic_in_kernel(vcpu))
4289                         goto out;
4290                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4291                 if (IS_ERR(u.lapic)) {
4292                         r = PTR_ERR(u.lapic);
4293                         goto out_nofree;
4294                 }
4295
4296                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4297                 break;
4298         }
4299         case KVM_INTERRUPT: {
4300                 struct kvm_interrupt irq;
4301
4302                 r = -EFAULT;
4303                 if (copy_from_user(&irq, argp, sizeof(irq)))
4304                         goto out;
4305                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4306                 break;
4307         }
4308         case KVM_NMI: {
4309                 r = kvm_vcpu_ioctl_nmi(vcpu);
4310                 break;
4311         }
4312         case KVM_SMI: {
4313                 r = kvm_vcpu_ioctl_smi(vcpu);
4314                 break;
4315         }
4316         case KVM_SET_CPUID: {
4317                 struct kvm_cpuid __user *cpuid_arg = argp;
4318                 struct kvm_cpuid cpuid;
4319
4320                 r = -EFAULT;
4321                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4322                         goto out;
4323                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4324                 break;
4325         }
4326         case KVM_SET_CPUID2: {
4327                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4328                 struct kvm_cpuid2 cpuid;
4329
4330                 r = -EFAULT;
4331                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4332                         goto out;
4333                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4334                                               cpuid_arg->entries);
4335                 break;
4336         }
4337         case KVM_GET_CPUID2: {
4338                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4339                 struct kvm_cpuid2 cpuid;
4340
4341                 r = -EFAULT;
4342                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4343                         goto out;
4344                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4345                                               cpuid_arg->entries);
4346                 if (r)
4347                         goto out;
4348                 r = -EFAULT;
4349                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4350                         goto out;
4351                 r = 0;
4352                 break;
4353         }
4354         case KVM_GET_MSRS: {
4355                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4356                 r = msr_io(vcpu, argp, do_get_msr, 1);
4357                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4358                 break;
4359         }
4360         case KVM_SET_MSRS: {
4361                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4362                 r = msr_io(vcpu, argp, do_set_msr, 0);
4363                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4364                 break;
4365         }
4366         case KVM_TPR_ACCESS_REPORTING: {
4367                 struct kvm_tpr_access_ctl tac;
4368
4369                 r = -EFAULT;
4370                 if (copy_from_user(&tac, argp, sizeof(tac)))
4371                         goto out;
4372                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4373                 if (r)
4374                         goto out;
4375                 r = -EFAULT;
4376                 if (copy_to_user(argp, &tac, sizeof(tac)))
4377                         goto out;
4378                 r = 0;
4379                 break;
4380         };
4381         case KVM_SET_VAPIC_ADDR: {
4382                 struct kvm_vapic_addr va;
4383                 int idx;
4384
4385                 r = -EINVAL;
4386                 if (!lapic_in_kernel(vcpu))
4387                         goto out;
4388                 r = -EFAULT;
4389                 if (copy_from_user(&va, argp, sizeof(va)))
4390                         goto out;
4391                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4392                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4393                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4394                 break;
4395         }
4396         case KVM_X86_SETUP_MCE: {
4397                 u64 mcg_cap;
4398
4399                 r = -EFAULT;
4400                 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4401                         goto out;
4402                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4403                 break;
4404         }
4405         case KVM_X86_SET_MCE: {
4406                 struct kvm_x86_mce mce;
4407
4408                 r = -EFAULT;
4409                 if (copy_from_user(&mce, argp, sizeof(mce)))
4410                         goto out;
4411                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4412                 break;
4413         }
4414         case KVM_GET_VCPU_EVENTS: {
4415                 struct kvm_vcpu_events events;
4416
4417                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4418
4419                 r = -EFAULT;
4420                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4421                         break;
4422                 r = 0;
4423                 break;
4424         }
4425         case KVM_SET_VCPU_EVENTS: {
4426                 struct kvm_vcpu_events events;
4427
4428                 r = -EFAULT;
4429                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4430                         break;
4431
4432                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4433                 break;
4434         }
4435         case KVM_GET_DEBUGREGS: {
4436                 struct kvm_debugregs dbgregs;
4437
4438                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4439
4440                 r = -EFAULT;
4441                 if (copy_to_user(argp, &dbgregs,
4442                                  sizeof(struct kvm_debugregs)))
4443                         break;
4444                 r = 0;
4445                 break;
4446         }
4447         case KVM_SET_DEBUGREGS: {
4448                 struct kvm_debugregs dbgregs;
4449
4450                 r = -EFAULT;
4451                 if (copy_from_user(&dbgregs, argp,
4452                                    sizeof(struct kvm_debugregs)))
4453                         break;
4454
4455                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4456                 break;
4457         }
4458         case KVM_GET_XSAVE: {
4459                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4460                 r = -ENOMEM;
4461                 if (!u.xsave)
4462                         break;
4463
4464                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4465
4466                 r = -EFAULT;
4467                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4468                         break;
4469                 r = 0;
4470                 break;
4471         }
4472         case KVM_SET_XSAVE: {
4473                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4474                 if (IS_ERR(u.xsave)) {
4475                         r = PTR_ERR(u.xsave);
4476                         goto out_nofree;
4477                 }
4478
4479                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4480                 break;
4481         }
4482         case KVM_GET_XCRS: {
4483                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4484                 r = -ENOMEM;
4485                 if (!u.xcrs)
4486                         break;
4487
4488                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4489
4490                 r = -EFAULT;
4491                 if (copy_to_user(argp, u.xcrs,
4492                                  sizeof(struct kvm_xcrs)))
4493                         break;
4494                 r = 0;
4495                 break;
4496         }
4497         case KVM_SET_XCRS: {
4498                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4499                 if (IS_ERR(u.xcrs)) {
4500                         r = PTR_ERR(u.xcrs);
4501                         goto out_nofree;
4502                 }
4503
4504                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4505                 break;
4506         }
4507         case KVM_SET_TSC_KHZ: {
4508                 u32 user_tsc_khz;
4509
4510                 r = -EINVAL;
4511                 user_tsc_khz = (u32)arg;
4512
4513                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4514                         goto out;
4515
4516                 if (user_tsc_khz == 0)
4517                         user_tsc_khz = tsc_khz;
4518
4519                 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4520                         r = 0;
4521
4522                 goto out;
4523         }
4524         case KVM_GET_TSC_KHZ: {
4525                 r = vcpu->arch.virtual_tsc_khz;
4526                 goto out;
4527         }
4528         case KVM_KVMCLOCK_CTRL: {
4529                 r = kvm_set_guest_paused(vcpu);
4530                 goto out;
4531         }
4532         case KVM_ENABLE_CAP: {
4533                 struct kvm_enable_cap cap;
4534
4535                 r = -EFAULT;
4536                 if (copy_from_user(&cap, argp, sizeof(cap)))
4537                         goto out;
4538                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4539                 break;
4540         }
4541         case KVM_GET_NESTED_STATE: {
4542                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4543                 u32 user_data_size;
4544
4545                 r = -EINVAL;
4546                 if (!kvm_x86_ops.get_nested_state)
4547                         break;
4548
4549                 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4550                 r = -EFAULT;
4551                 if (get_user(user_data_size, &user_kvm_nested_state->size))
4552                         break;
4553
4554                 r = kvm_x86_ops.get_nested_state(vcpu, user_kvm_nested_state,
4555                                                   user_data_size);
4556                 if (r < 0)
4557                         break;
4558
4559                 if (r > user_data_size) {
4560                         if (put_user(r, &user_kvm_nested_state->size))
4561                                 r = -EFAULT;
4562                         else
4563                                 r = -E2BIG;
4564                         break;
4565                 }
4566
4567                 r = 0;
4568                 break;
4569         }
4570         case KVM_SET_NESTED_STATE: {
4571                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4572                 struct kvm_nested_state kvm_state;
4573                 int idx;
4574
4575                 r = -EINVAL;
4576                 if (!kvm_x86_ops.set_nested_state)
4577                         break;
4578
4579                 r = -EFAULT;
4580                 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4581                         break;
4582
4583                 r = -EINVAL;
4584                 if (kvm_state.size < sizeof(kvm_state))
4585                         break;
4586
4587                 if (kvm_state.flags &
4588                     ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4589                       | KVM_STATE_NESTED_EVMCS))
4590                         break;
4591
4592                 /* nested_run_pending implies guest_mode.  */
4593                 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4594                     && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4595                         break;
4596
4597                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4598                 r = kvm_x86_ops.set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4599                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4600                 break;
4601         }
4602         case KVM_GET_SUPPORTED_HV_CPUID: {
4603                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4604                 struct kvm_cpuid2 cpuid;
4605
4606                 r = -EFAULT;
4607                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4608                         goto out;
4609
4610                 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4611                                                 cpuid_arg->entries);
4612                 if (r)
4613                         goto out;
4614
4615                 r = -EFAULT;
4616                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4617                         goto out;
4618                 r = 0;
4619                 break;
4620         }
4621         default:
4622                 r = -EINVAL;
4623         }
4624 out:
4625         kfree(u.buffer);
4626 out_nofree:
4627         vcpu_put(vcpu);
4628         return r;
4629 }
4630
4631 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4632 {
4633         return VM_FAULT_SIGBUS;
4634 }
4635
4636 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4637 {
4638         int ret;
4639
4640         if (addr > (unsigned int)(-3 * PAGE_SIZE))
4641                 return -EINVAL;
4642         ret = kvm_x86_ops.set_tss_addr(kvm, addr);
4643         return ret;
4644 }
4645
4646 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4647                                               u64 ident_addr)
4648 {
4649         return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr);
4650 }
4651
4652 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4653                                          unsigned long kvm_nr_mmu_pages)
4654 {
4655         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4656                 return -EINVAL;
4657
4658         mutex_lock(&kvm->slots_lock);
4659
4660         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4661         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4662
4663         mutex_unlock(&kvm->slots_lock);
4664         return 0;
4665 }
4666
4667 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4668 {
4669         return kvm->arch.n_max_mmu_pages;
4670 }
4671
4672 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4673 {
4674         struct kvm_pic *pic = kvm->arch.vpic;
4675         int r;
4676
4677         r = 0;
4678         switch (chip->chip_id) {
4679         case KVM_IRQCHIP_PIC_MASTER:
4680                 memcpy(&chip->chip.pic, &pic->pics[0],
4681                         sizeof(struct kvm_pic_state));
4682                 break;
4683         case KVM_IRQCHIP_PIC_SLAVE:
4684                 memcpy(&chip->chip.pic, &pic->pics[1],
4685                         sizeof(struct kvm_pic_state));
4686                 break;
4687         case KVM_IRQCHIP_IOAPIC:
4688                 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4689                 break;
4690         default:
4691                 r = -EINVAL;
4692                 break;
4693         }
4694         return r;
4695 }
4696
4697 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4698 {
4699         struct kvm_pic *pic = kvm->arch.vpic;
4700         int r;
4701
4702         r = 0;
4703         switch (chip->chip_id) {
4704         case KVM_IRQCHIP_PIC_MASTER:
4705                 spin_lock(&pic->lock);
4706                 memcpy(&pic->pics[0], &chip->chip.pic,
4707                         sizeof(struct kvm_pic_state));
4708                 spin_unlock(&pic->lock);
4709                 break;
4710         case KVM_IRQCHIP_PIC_SLAVE:
4711                 spin_lock(&pic->lock);
4712                 memcpy(&pic->pics[1], &chip->chip.pic,
4713                         sizeof(struct kvm_pic_state));
4714                 spin_unlock(&pic->lock);
4715                 break;
4716         case KVM_IRQCHIP_IOAPIC:
4717                 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4718                 break;
4719         default:
4720                 r = -EINVAL;
4721                 break;
4722         }
4723         kvm_pic_update_irq(pic);
4724         return r;
4725 }
4726
4727 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4728 {
4729         struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4730
4731         BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4732
4733         mutex_lock(&kps->lock);
4734         memcpy(ps, &kps->channels, sizeof(*ps));
4735         mutex_unlock(&kps->lock);
4736         return 0;
4737 }
4738
4739 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4740 {
4741         int i;
4742         struct kvm_pit *pit = kvm->arch.vpit;
4743
4744         mutex_lock(&pit->pit_state.lock);
4745         memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4746         for (i = 0; i < 3; i++)
4747                 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4748         mutex_unlock(&pit->pit_state.lock);
4749         return 0;
4750 }
4751
4752 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4753 {
4754         mutex_lock(&kvm->arch.vpit->pit_state.lock);
4755         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4756                 sizeof(ps->channels));
4757         ps->flags = kvm->arch.vpit->pit_state.flags;
4758         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4759         memset(&ps->reserved, 0, sizeof(ps->reserved));
4760         return 0;
4761 }
4762
4763 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4764 {
4765         int start = 0;
4766         int i;
4767         u32 prev_legacy, cur_legacy;
4768         struct kvm_pit *pit = kvm->arch.vpit;
4769
4770         mutex_lock(&pit->pit_state.lock);
4771         prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4772         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4773         if (!prev_legacy && cur_legacy)
4774                 start = 1;
4775         memcpy(&pit->pit_state.channels, &ps->channels,
4776                sizeof(pit->pit_state.channels));
4777         pit->pit_state.flags = ps->flags;
4778         for (i = 0; i < 3; i++)
4779                 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4780                                    start && i == 0);
4781         mutex_unlock(&pit->pit_state.lock);
4782         return 0;
4783 }
4784
4785 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4786                                  struct kvm_reinject_control *control)
4787 {
4788         struct kvm_pit *pit = kvm->arch.vpit;
4789
4790         /* pit->pit_state.lock was overloaded to prevent userspace from getting
4791          * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4792          * ioctls in parallel.  Use a separate lock if that ioctl isn't rare.
4793          */
4794         mutex_lock(&pit->pit_state.lock);
4795         kvm_pit_set_reinject(pit, control->pit_reinject);
4796         mutex_unlock(&pit->pit_state.lock);
4797
4798         return 0;
4799 }
4800
4801 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
4802 {
4803         /*
4804          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4805          */
4806         if (kvm_x86_ops.flush_log_dirty)
4807                 kvm_x86_ops.flush_log_dirty(kvm);
4808 }
4809
4810 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4811                         bool line_status)
4812 {
4813         if (!irqchip_in_kernel(kvm))
4814                 return -ENXIO;
4815
4816         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4817                                         irq_event->irq, irq_event->level,
4818                                         line_status);
4819         return 0;
4820 }
4821
4822 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4823                             struct kvm_enable_cap *cap)
4824 {
4825         int r;
4826
4827         if (cap->flags)
4828                 return -EINVAL;
4829
4830         switch (cap->cap) {
4831         case KVM_CAP_DISABLE_QUIRKS:
4832                 kvm->arch.disabled_quirks = cap->args[0];
4833                 r = 0;
4834                 break;
4835         case KVM_CAP_SPLIT_IRQCHIP: {
4836                 mutex_lock(&kvm->lock);
4837                 r = -EINVAL;
4838                 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4839                         goto split_irqchip_unlock;
4840                 r = -EEXIST;
4841                 if (irqchip_in_kernel(kvm))
4842                         goto split_irqchip_unlock;
4843                 if (kvm->created_vcpus)
4844                         goto split_irqchip_unlock;
4845                 r = kvm_setup_empty_irq_routing(kvm);
4846                 if (r)
4847                         goto split_irqchip_unlock;
4848                 /* Pairs with irqchip_in_kernel. */
4849                 smp_wmb();
4850                 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4851                 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4852                 r = 0;
4853 split_irqchip_unlock:
4854                 mutex_unlock(&kvm->lock);
4855                 break;
4856         }
4857         case KVM_CAP_X2APIC_API:
4858                 r = -EINVAL;
4859                 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4860                         break;
4861
4862                 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4863                         kvm->arch.x2apic_format = true;
4864                 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4865                         kvm->arch.x2apic_broadcast_quirk_disabled = true;
4866
4867                 r = 0;
4868                 break;
4869         case KVM_CAP_X86_DISABLE_EXITS:
4870                 r = -EINVAL;
4871                 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4872                         break;
4873
4874                 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4875                         kvm_can_mwait_in_guest())
4876                         kvm->arch.mwait_in_guest = true;
4877                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4878                         kvm->arch.hlt_in_guest = true;
4879                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4880                         kvm->arch.pause_in_guest = true;
4881                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4882                         kvm->arch.cstate_in_guest = true;
4883                 r = 0;
4884                 break;
4885         case KVM_CAP_MSR_PLATFORM_INFO:
4886                 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4887                 r = 0;
4888                 break;
4889         case KVM_CAP_EXCEPTION_PAYLOAD:
4890                 kvm->arch.exception_payload_enabled = cap->args[0];
4891                 r = 0;
4892                 break;
4893         default:
4894                 r = -EINVAL;
4895                 break;
4896         }
4897         return r;
4898 }
4899
4900 long kvm_arch_vm_ioctl(struct file *filp,
4901                        unsigned int ioctl, unsigned long arg)
4902 {
4903         struct kvm *kvm = filp->private_data;
4904         void __user *argp = (void __user *)arg;
4905         int r = -ENOTTY;
4906         /*
4907          * This union makes it completely explicit to gcc-3.x
4908          * that these two variables' stack usage should be
4909          * combined, not added together.
4910          */
4911         union {
4912                 struct kvm_pit_state ps;
4913                 struct kvm_pit_state2 ps2;
4914                 struct kvm_pit_config pit_config;
4915         } u;
4916
4917         switch (ioctl) {
4918         case KVM_SET_TSS_ADDR:
4919                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4920                 break;
4921         case KVM_SET_IDENTITY_MAP_ADDR: {
4922                 u64 ident_addr;
4923
4924                 mutex_lock(&kvm->lock);
4925                 r = -EINVAL;
4926                 if (kvm->created_vcpus)
4927                         goto set_identity_unlock;
4928                 r = -EFAULT;
4929                 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4930                         goto set_identity_unlock;
4931                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4932 set_identity_unlock:
4933                 mutex_unlock(&kvm->lock);
4934                 break;
4935         }
4936         case KVM_SET_NR_MMU_PAGES:
4937                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4938                 break;
4939         case KVM_GET_NR_MMU_PAGES:
4940                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4941                 break;
4942         case KVM_CREATE_IRQCHIP: {
4943                 mutex_lock(&kvm->lock);
4944
4945                 r = -EEXIST;
4946                 if (irqchip_in_kernel(kvm))
4947                         goto create_irqchip_unlock;
4948
4949                 r = -EINVAL;
4950                 if (kvm->created_vcpus)
4951                         goto create_irqchip_unlock;
4952
4953                 r = kvm_pic_init(kvm);
4954                 if (r)
4955                         goto create_irqchip_unlock;
4956
4957                 r = kvm_ioapic_init(kvm);
4958                 if (r) {
4959                         kvm_pic_destroy(kvm);
4960                         goto create_irqchip_unlock;
4961                 }
4962
4963                 r = kvm_setup_default_irq_routing(kvm);
4964                 if (r) {
4965                         kvm_ioapic_destroy(kvm);
4966                         kvm_pic_destroy(kvm);
4967                         goto create_irqchip_unlock;
4968                 }
4969                 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4970                 smp_wmb();
4971                 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4972         create_irqchip_unlock:
4973                 mutex_unlock(&kvm->lock);
4974                 break;
4975         }
4976         case KVM_CREATE_PIT:
4977                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4978                 goto create_pit;
4979         case KVM_CREATE_PIT2:
4980                 r = -EFAULT;
4981                 if (copy_from_user(&u.pit_config, argp,
4982                                    sizeof(struct kvm_pit_config)))
4983                         goto out;
4984         create_pit:
4985                 mutex_lock(&kvm->lock);
4986                 r = -EEXIST;
4987                 if (kvm->arch.vpit)
4988                         goto create_pit_unlock;
4989                 r = -ENOMEM;
4990                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4991                 if (kvm->arch.vpit)
4992                         r = 0;
4993         create_pit_unlock:
4994                 mutex_unlock(&kvm->lock);
4995                 break;
4996         case KVM_GET_IRQCHIP: {
4997                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4998                 struct kvm_irqchip *chip;
4999
5000                 chip = memdup_user(argp, sizeof(*chip));
5001                 if (IS_ERR(chip)) {
5002                         r = PTR_ERR(chip);
5003                         goto out;
5004                 }
5005
5006                 r = -ENXIO;
5007                 if (!irqchip_kernel(kvm))
5008                         goto get_irqchip_out;
5009                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5010                 if (r)
5011                         goto get_irqchip_out;
5012                 r = -EFAULT;
5013                 if (copy_to_user(argp, chip, sizeof(*chip)))
5014                         goto get_irqchip_out;
5015                 r = 0;
5016         get_irqchip_out:
5017                 kfree(chip);
5018                 break;
5019         }
5020         case KVM_SET_IRQCHIP: {
5021                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5022                 struct kvm_irqchip *chip;
5023
5024                 chip = memdup_user(argp, sizeof(*chip));
5025                 if (IS_ERR(chip)) {
5026                         r = PTR_ERR(chip);
5027                         goto out;
5028                 }
5029
5030                 r = -ENXIO;
5031                 if (!irqchip_kernel(kvm))
5032                         goto set_irqchip_out;
5033                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5034         set_irqchip_out:
5035                 kfree(chip);
5036                 break;
5037         }
5038         case KVM_GET_PIT: {
5039                 r = -EFAULT;
5040                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5041                         goto out;
5042                 r = -ENXIO;
5043                 if (!kvm->arch.vpit)
5044                         goto out;
5045                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5046                 if (r)
5047                         goto out;
5048                 r = -EFAULT;
5049                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5050                         goto out;
5051                 r = 0;
5052                 break;
5053         }
5054         case KVM_SET_PIT: {
5055                 r = -EFAULT;
5056                 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5057                         goto out;
5058                 mutex_lock(&kvm->lock);
5059                 r = -ENXIO;
5060                 if (!kvm->arch.vpit)
5061                         goto set_pit_out;
5062                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5063 set_pit_out:
5064                 mutex_unlock(&kvm->lock);
5065                 break;
5066         }
5067         case KVM_GET_PIT2: {
5068                 r = -ENXIO;
5069                 if (!kvm->arch.vpit)
5070                         goto out;
5071                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5072                 if (r)
5073                         goto out;
5074                 r = -EFAULT;
5075                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5076                         goto out;
5077                 r = 0;
5078                 break;
5079         }
5080         case KVM_SET_PIT2: {
5081                 r = -EFAULT;
5082                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5083                         goto out;
5084                 mutex_lock(&kvm->lock);
5085                 r = -ENXIO;
5086                 if (!kvm->arch.vpit)
5087                         goto set_pit2_out;
5088                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5089 set_pit2_out:
5090                 mutex_unlock(&kvm->lock);
5091                 break;
5092         }
5093         case KVM_REINJECT_CONTROL: {
5094                 struct kvm_reinject_control control;
5095                 r =  -EFAULT;
5096                 if (copy_from_user(&control, argp, sizeof(control)))
5097                         goto out;
5098                 r = -ENXIO;
5099                 if (!kvm->arch.vpit)
5100                         goto out;
5101                 r = kvm_vm_ioctl_reinject(kvm, &control);
5102                 break;
5103         }
5104         case KVM_SET_BOOT_CPU_ID:
5105                 r = 0;
5106                 mutex_lock(&kvm->lock);
5107                 if (kvm->created_vcpus)
5108                         r = -EBUSY;
5109                 else
5110                         kvm->arch.bsp_vcpu_id = arg;
5111                 mutex_unlock(&kvm->lock);
5112                 break;
5113         case KVM_XEN_HVM_CONFIG: {
5114                 struct kvm_xen_hvm_config xhc;
5115                 r = -EFAULT;
5116                 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5117                         goto out;
5118                 r = -EINVAL;
5119                 if (xhc.flags)
5120                         goto out;
5121                 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5122                 r = 0;
5123                 break;
5124         }
5125         case KVM_SET_CLOCK: {
5126                 struct kvm_clock_data user_ns;
5127                 u64 now_ns;
5128
5129                 r = -EFAULT;
5130                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5131                         goto out;
5132
5133                 r = -EINVAL;
5134                 if (user_ns.flags)
5135                         goto out;
5136
5137                 r = 0;
5138                 /*
5139                  * TODO: userspace has to take care of races with VCPU_RUN, so
5140                  * kvm_gen_update_masterclock() can be cut down to locked
5141                  * pvclock_update_vm_gtod_copy().
5142                  */
5143                 kvm_gen_update_masterclock(kvm);
5144                 now_ns = get_kvmclock_ns(kvm);
5145                 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5146                 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5147                 break;
5148         }
5149         case KVM_GET_CLOCK: {
5150                 struct kvm_clock_data user_ns;
5151                 u64 now_ns;
5152
5153                 now_ns = get_kvmclock_ns(kvm);
5154                 user_ns.clock = now_ns;
5155                 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5156                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5157
5158                 r = -EFAULT;
5159                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5160                         goto out;
5161                 r = 0;
5162                 break;
5163         }
5164         case KVM_MEMORY_ENCRYPT_OP: {
5165                 r = -ENOTTY;
5166                 if (kvm_x86_ops.mem_enc_op)
5167                         r = kvm_x86_ops.mem_enc_op(kvm, argp);
5168                 break;
5169         }
5170         case KVM_MEMORY_ENCRYPT_REG_REGION: {
5171                 struct kvm_enc_region region;
5172
5173                 r = -EFAULT;
5174                 if (copy_from_user(&region, argp, sizeof(region)))
5175                         goto out;
5176
5177                 r = -ENOTTY;
5178                 if (kvm_x86_ops.mem_enc_reg_region)
5179                         r = kvm_x86_ops.mem_enc_reg_region(kvm, &region);
5180                 break;
5181         }
5182         case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5183                 struct kvm_enc_region region;
5184
5185                 r = -EFAULT;
5186                 if (copy_from_user(&region, argp, sizeof(region)))
5187                         goto out;
5188
5189                 r = -ENOTTY;
5190                 if (kvm_x86_ops.mem_enc_unreg_region)
5191                         r = kvm_x86_ops.mem_enc_unreg_region(kvm, &region);
5192                 break;
5193         }
5194         case KVM_HYPERV_EVENTFD: {
5195                 struct kvm_hyperv_eventfd hvevfd;
5196
5197                 r = -EFAULT;
5198                 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5199                         goto out;
5200                 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5201                 break;
5202         }
5203         case KVM_SET_PMU_EVENT_FILTER:
5204                 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5205                 break;
5206         default:
5207                 r = -ENOTTY;
5208         }
5209 out:
5210         return r;
5211 }
5212
5213 static void kvm_init_msr_list(void)
5214 {
5215         struct x86_pmu_capability x86_pmu;
5216         u32 dummy[2];
5217         unsigned i;
5218
5219         BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5220                          "Please update the fixed PMCs in msrs_to_saved_all[]");
5221
5222         perf_get_x86_pmu_capability(&x86_pmu);
5223
5224         num_msrs_to_save = 0;
5225         num_emulated_msrs = 0;
5226         num_msr_based_features = 0;
5227
5228         for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5229                 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5230                         continue;
5231
5232                 /*
5233                  * Even MSRs that are valid in the host may not be exposed
5234                  * to the guests in some cases.
5235                  */
5236                 switch (msrs_to_save_all[i]) {
5237                 case MSR_IA32_BNDCFGS:
5238                         if (!kvm_mpx_supported())
5239                                 continue;
5240                         break;
5241                 case MSR_TSC_AUX:
5242                         if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5243                                 continue;
5244                         break;
5245                 case MSR_IA32_RTIT_CTL:
5246                 case MSR_IA32_RTIT_STATUS:
5247                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5248                                 continue;
5249                         break;
5250                 case MSR_IA32_RTIT_CR3_MATCH:
5251                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5252                             !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5253                                 continue;
5254                         break;
5255                 case MSR_IA32_RTIT_OUTPUT_BASE:
5256                 case MSR_IA32_RTIT_OUTPUT_MASK:
5257                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5258                                 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5259                                  !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5260                                 continue;
5261                         break;
5262                 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5263                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5264                                 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5265                                 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5266                                 continue;
5267                         break;
5268                 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5269                         if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5270                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5271                                 continue;
5272                         break;
5273                 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5274                         if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5275                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5276                                 continue;
5277                 }
5278                 default:
5279                         break;
5280                 }
5281
5282                 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5283         }
5284
5285         for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5286                 if (!kvm_x86_ops.has_emulated_msr(emulated_msrs_all[i]))
5287                         continue;
5288
5289                 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5290         }
5291
5292         for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5293                 struct kvm_msr_entry msr;
5294
5295                 msr.index = msr_based_features_all[i];
5296                 if (kvm_get_msr_feature(&msr))
5297                         continue;
5298
5299                 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5300         }
5301 }
5302
5303 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5304                            const void *v)
5305 {
5306         int handled = 0;
5307         int n;
5308
5309         do {
5310                 n = min(len, 8);
5311                 if (!(lapic_in_kernel(vcpu) &&
5312                       !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5313                     && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5314                         break;
5315                 handled += n;
5316                 addr += n;
5317                 len -= n;
5318                 v += n;
5319         } while (len);
5320
5321         return handled;
5322 }
5323
5324 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5325 {
5326         int handled = 0;
5327         int n;
5328
5329         do {
5330                 n = min(len, 8);
5331                 if (!(lapic_in_kernel(vcpu) &&
5332                       !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5333                                          addr, n, v))
5334                     && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5335                         break;
5336                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5337                 handled += n;
5338                 addr += n;
5339                 len -= n;
5340                 v += n;
5341         } while (len);
5342
5343         return handled;
5344 }
5345
5346 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5347                         struct kvm_segment *var, int seg)
5348 {
5349         kvm_x86_ops.set_segment(vcpu, var, seg);
5350 }
5351
5352 void kvm_get_segment(struct kvm_vcpu *vcpu,
5353                      struct kvm_segment *var, int seg)
5354 {
5355         kvm_x86_ops.get_segment(vcpu, var, seg);
5356 }
5357
5358 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5359                            struct x86_exception *exception)
5360 {
5361         gpa_t t_gpa;
5362
5363         BUG_ON(!mmu_is_nested(vcpu));
5364
5365         /* NPT walks are always user-walks */
5366         access |= PFERR_USER_MASK;
5367         t_gpa  = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5368
5369         return t_gpa;
5370 }
5371
5372 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5373                               struct x86_exception *exception)
5374 {
5375         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5376         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5377 }
5378
5379  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5380                                 struct x86_exception *exception)
5381 {
5382         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5383         access |= PFERR_FETCH_MASK;
5384         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5385 }
5386
5387 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5388                                struct x86_exception *exception)
5389 {
5390         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5391         access |= PFERR_WRITE_MASK;
5392         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5393 }
5394
5395 /* uses this to access any guest's mapped memory without checking CPL */
5396 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5397                                 struct x86_exception *exception)
5398 {
5399         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5400 }
5401
5402 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5403                                       struct kvm_vcpu *vcpu, u32 access,
5404                                       struct x86_exception *exception)
5405 {
5406         void *data = val;
5407         int r = X86EMUL_CONTINUE;
5408
5409         while (bytes) {
5410                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5411                                                             exception);
5412                 unsigned offset = addr & (PAGE_SIZE-1);
5413                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5414                 int ret;
5415
5416                 if (gpa == UNMAPPED_GVA)
5417                         return X86EMUL_PROPAGATE_FAULT;
5418                 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5419                                                offset, toread);
5420                 if (ret < 0) {
5421                         r = X86EMUL_IO_NEEDED;
5422                         goto out;
5423                 }
5424
5425                 bytes -= toread;
5426                 data += toread;
5427                 addr += toread;
5428         }
5429 out:
5430         return r;
5431 }
5432
5433 /* used for instruction fetching */
5434 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5435                                 gva_t addr, void *val, unsigned int bytes,
5436                                 struct x86_exception *exception)
5437 {
5438         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5439         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5440         unsigned offset;
5441         int ret;
5442
5443         /* Inline kvm_read_guest_virt_helper for speed.  */
5444         gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5445                                                     exception);
5446         if (unlikely(gpa == UNMAPPED_GVA))
5447                 return X86EMUL_PROPAGATE_FAULT;
5448
5449         offset = addr & (PAGE_SIZE-1);
5450         if (WARN_ON(offset + bytes > PAGE_SIZE))
5451                 bytes = (unsigned)PAGE_SIZE - offset;
5452         ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5453                                        offset, bytes);
5454         if (unlikely(ret < 0))
5455                 return X86EMUL_IO_NEEDED;
5456
5457         return X86EMUL_CONTINUE;
5458 }
5459
5460 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5461                                gva_t addr, void *val, unsigned int bytes,
5462                                struct x86_exception *exception)
5463 {
5464         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5465
5466         /*
5467          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5468          * is returned, but our callers are not ready for that and they blindly
5469          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5470          * uninitialized kernel stack memory into cr2 and error code.
5471          */
5472         memset(exception, 0, sizeof(*exception));
5473         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5474                                           exception);
5475 }
5476 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5477
5478 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5479                              gva_t addr, void *val, unsigned int bytes,
5480                              struct x86_exception *exception, bool system)
5481 {
5482         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5483         u32 access = 0;
5484
5485         if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5486                 access |= PFERR_USER_MASK;
5487
5488         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5489 }
5490
5491 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5492                 unsigned long addr, void *val, unsigned int bytes)
5493 {
5494         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5495         int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5496
5497         return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5498 }
5499
5500 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5501                                       struct kvm_vcpu *vcpu, u32 access,
5502                                       struct x86_exception *exception)
5503 {
5504         void *data = val;
5505         int r = X86EMUL_CONTINUE;
5506
5507         while (bytes) {
5508                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5509                                                              access,
5510                                                              exception);
5511                 unsigned offset = addr & (PAGE_SIZE-1);
5512                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5513                 int ret;
5514
5515                 if (gpa == UNMAPPED_GVA)
5516                         return X86EMUL_PROPAGATE_FAULT;
5517                 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5518                 if (ret < 0) {
5519                         r = X86EMUL_IO_NEEDED;
5520                         goto out;
5521                 }
5522
5523                 bytes -= towrite;
5524                 data += towrite;
5525                 addr += towrite;
5526         }
5527 out:
5528         return r;
5529 }
5530
5531 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5532                               unsigned int bytes, struct x86_exception *exception,
5533                               bool system)
5534 {
5535         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5536         u32 access = PFERR_WRITE_MASK;
5537
5538         if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5539                 access |= PFERR_USER_MASK;
5540
5541         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5542                                            access, exception);
5543 }
5544
5545 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5546                                 unsigned int bytes, struct x86_exception *exception)
5547 {
5548         /* kvm_write_guest_virt_system can pull in tons of pages. */
5549         vcpu->arch.l1tf_flush_l1d = true;
5550
5551         /*
5552          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5553          * is returned, but our callers are not ready for that and they blindly
5554          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5555          * uninitialized kernel stack memory into cr2 and error code.
5556          */
5557         memset(exception, 0, sizeof(*exception));
5558         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5559                                            PFERR_WRITE_MASK, exception);
5560 }
5561 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5562
5563 int handle_ud(struct kvm_vcpu *vcpu)
5564 {
5565         static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
5566         int emul_type = EMULTYPE_TRAP_UD;
5567         char sig[5]; /* ud2; .ascii "kvm" */
5568         struct x86_exception e;
5569
5570         if (force_emulation_prefix &&
5571             kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5572                                 sig, sizeof(sig), &e) == 0 &&
5573             memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
5574                 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5575                 emul_type = EMULTYPE_TRAP_UD_FORCED;
5576         }
5577
5578         return kvm_emulate_instruction(vcpu, emul_type);
5579 }
5580 EXPORT_SYMBOL_GPL(handle_ud);
5581
5582 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5583                             gpa_t gpa, bool write)
5584 {
5585         /* For APIC access vmexit */
5586         if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5587                 return 1;
5588
5589         if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5590                 trace_vcpu_match_mmio(gva, gpa, write, true);
5591                 return 1;
5592         }
5593
5594         return 0;
5595 }
5596
5597 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5598                                 gpa_t *gpa, struct x86_exception *exception,
5599                                 bool write)
5600 {
5601         u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5602                 | (write ? PFERR_WRITE_MASK : 0);
5603
5604         /*
5605          * currently PKRU is only applied to ept enabled guest so
5606          * there is no pkey in EPT page table for L1 guest or EPT
5607          * shadow page table for L2 guest.
5608          */
5609         if (vcpu_match_mmio_gva(vcpu, gva)
5610             && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5611                                  vcpu->arch.mmio_access, 0, access)) {
5612                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5613                                         (gva & (PAGE_SIZE - 1));
5614                 trace_vcpu_match_mmio(gva, *gpa, write, false);
5615                 return 1;
5616         }
5617
5618         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5619
5620         if (*gpa == UNMAPPED_GVA)
5621                 return -1;
5622
5623         return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5624 }
5625
5626 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5627                         const void *val, int bytes)
5628 {
5629         int ret;
5630
5631         ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5632         if (ret < 0)
5633                 return 0;
5634         kvm_page_track_write(vcpu, gpa, val, bytes);
5635         return 1;
5636 }
5637
5638 struct read_write_emulator_ops {
5639         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5640                                   int bytes);
5641         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5642                                   void *val, int bytes);
5643         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5644                                int bytes, void *val);
5645         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5646                                     void *val, int bytes);
5647         bool write;
5648 };
5649
5650 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5651 {
5652         if (vcpu->mmio_read_completed) {
5653                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5654                                vcpu->mmio_fragments[0].gpa, val);
5655                 vcpu->mmio_read_completed = 0;
5656                 return 1;
5657         }
5658
5659         return 0;
5660 }
5661
5662 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5663                         void *val, int bytes)
5664 {
5665         return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5666 }
5667
5668 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5669                          void *val, int bytes)
5670 {
5671         return emulator_write_phys(vcpu, gpa, val, bytes);
5672 }
5673
5674 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5675 {
5676         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5677         return vcpu_mmio_write(vcpu, gpa, bytes, val);
5678 }
5679
5680 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5681                           void *val, int bytes)
5682 {
5683         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5684         return X86EMUL_IO_NEEDED;
5685 }
5686
5687 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5688                            void *val, int bytes)
5689 {
5690         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5691
5692         memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5693         return X86EMUL_CONTINUE;
5694 }
5695
5696 static const struct read_write_emulator_ops read_emultor = {
5697         .read_write_prepare = read_prepare,
5698         .read_write_emulate = read_emulate,
5699         .read_write_mmio = vcpu_mmio_read,
5700         .read_write_exit_mmio = read_exit_mmio,
5701 };
5702
5703 static const struct read_write_emulator_ops write_emultor = {
5704         .read_write_emulate = write_emulate,
5705         .read_write_mmio = write_mmio,
5706         .read_write_exit_mmio = write_exit_mmio,
5707         .write = true,
5708 };
5709
5710 static int emulator_read_write_onepage(unsigned long addr, void *val,
5711                                        unsigned int bytes,
5712                                        struct x86_exception *exception,
5713                                        struct kvm_vcpu *vcpu,
5714                                        const struct read_write_emulator_ops *ops)
5715 {
5716         gpa_t gpa;
5717         int handled, ret;
5718         bool write = ops->write;
5719         struct kvm_mmio_fragment *frag;
5720         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
5721
5722         /*
5723          * If the exit was due to a NPF we may already have a GPA.
5724          * If the GPA is present, use it to avoid the GVA to GPA table walk.
5725          * Note, this cannot be used on string operations since string
5726          * operation using rep will only have the initial GPA from the NPF
5727          * occurred.
5728          */
5729         if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
5730             (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
5731                 gpa = ctxt->gpa_val;
5732                 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5733         } else {
5734                 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5735                 if (ret < 0)
5736                         return X86EMUL_PROPAGATE_FAULT;
5737         }
5738
5739         if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5740                 return X86EMUL_CONTINUE;
5741
5742         /*
5743          * Is this MMIO handled locally?
5744          */
5745         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5746         if (handled == bytes)
5747                 return X86EMUL_CONTINUE;
5748
5749         gpa += handled;
5750         bytes -= handled;
5751         val += handled;
5752
5753         WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5754         frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5755         frag->gpa = gpa;
5756         frag->data = val;
5757         frag->len = bytes;
5758         return X86EMUL_CONTINUE;
5759 }
5760
5761 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5762                         unsigned long addr,
5763                         void *val, unsigned int bytes,
5764                         struct x86_exception *exception,
5765                         const struct read_write_emulator_ops *ops)
5766 {
5767         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5768         gpa_t gpa;
5769         int rc;
5770
5771         if (ops->read_write_prepare &&
5772                   ops->read_write_prepare(vcpu, val, bytes))
5773                 return X86EMUL_CONTINUE;
5774
5775         vcpu->mmio_nr_fragments = 0;
5776
5777         /* Crossing a page boundary? */
5778         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5779                 int now;
5780
5781                 now = -addr & ~PAGE_MASK;
5782                 rc = emulator_read_write_onepage(addr, val, now, exception,
5783                                                  vcpu, ops);
5784
5785                 if (rc != X86EMUL_CONTINUE)
5786                         return rc;
5787                 addr += now;
5788                 if (ctxt->mode != X86EMUL_MODE_PROT64)
5789                         addr = (u32)addr;
5790                 val += now;
5791                 bytes -= now;
5792         }
5793
5794         rc = emulator_read_write_onepage(addr, val, bytes, exception,
5795                                          vcpu, ops);
5796         if (rc != X86EMUL_CONTINUE)
5797                 return rc;
5798
5799         if (!vcpu->mmio_nr_fragments)
5800                 return rc;
5801
5802         gpa = vcpu->mmio_fragments[0].gpa;
5803
5804         vcpu->mmio_needed = 1;
5805         vcpu->mmio_cur_fragment = 0;
5806
5807         vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5808         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5809         vcpu->run->exit_reason = KVM_EXIT_MMIO;
5810         vcpu->run->mmio.phys_addr = gpa;
5811
5812         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5813 }
5814
5815 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5816                                   unsigned long addr,
5817                                   void *val,
5818                                   unsigned int bytes,
5819                                   struct x86_exception *exception)
5820 {
5821         return emulator_read_write(ctxt, addr, val, bytes,
5822                                    exception, &read_emultor);
5823 }
5824
5825 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5826                             unsigned long addr,
5827                             const void *val,
5828                             unsigned int bytes,
5829                             struct x86_exception *exception)
5830 {
5831         return emulator_read_write(ctxt, addr, (void *)val, bytes,
5832                                    exception, &write_emultor);
5833 }
5834
5835 #define CMPXCHG_TYPE(t, ptr, old, new) \
5836         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5837
5838 #ifdef CONFIG_X86_64
5839 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5840 #else
5841 #  define CMPXCHG64(ptr, old, new) \
5842         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5843 #endif
5844
5845 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5846                                      unsigned long addr,
5847                                      const void *old,
5848                                      const void *new,
5849                                      unsigned int bytes,
5850                                      struct x86_exception *exception)
5851 {
5852         struct kvm_host_map map;
5853         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5854         u64 page_line_mask;
5855         gpa_t gpa;
5856         char *kaddr;
5857         bool exchanged;
5858
5859         /* guests cmpxchg8b have to be emulated atomically */
5860         if (bytes > 8 || (bytes & (bytes - 1)))
5861                 goto emul_write;
5862
5863         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5864
5865         if (gpa == UNMAPPED_GVA ||
5866             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5867                 goto emul_write;
5868
5869         /*
5870          * Emulate the atomic as a straight write to avoid #AC if SLD is
5871          * enabled in the host and the access splits a cache line.
5872          */
5873         if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
5874                 page_line_mask = ~(cache_line_size() - 1);
5875         else
5876                 page_line_mask = PAGE_MASK;
5877
5878         if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
5879                 goto emul_write;
5880
5881         if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5882                 goto emul_write;
5883
5884         kaddr = map.hva + offset_in_page(gpa);
5885
5886         switch (bytes) {
5887         case 1:
5888                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5889                 break;
5890         case 2:
5891                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5892                 break;
5893         case 4:
5894                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5895                 break;
5896         case 8:
5897                 exchanged = CMPXCHG64(kaddr, old, new);
5898                 break;
5899         default:
5900                 BUG();
5901         }
5902
5903         kvm_vcpu_unmap(vcpu, &map, true);
5904
5905         if (!exchanged)
5906                 return X86EMUL_CMPXCHG_FAILED;
5907
5908         kvm_page_track_write(vcpu, gpa, new, bytes);
5909
5910         return X86EMUL_CONTINUE;
5911
5912 emul_write:
5913         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5914
5915         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5916 }
5917
5918 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5919 {
5920         int r = 0, i;
5921
5922         for (i = 0; i < vcpu->arch.pio.count; i++) {
5923                 if (vcpu->arch.pio.in)
5924                         r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5925                                             vcpu->arch.pio.size, pd);
5926                 else
5927                         r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5928                                              vcpu->arch.pio.port, vcpu->arch.pio.size,
5929                                              pd);
5930                 if (r)
5931                         break;
5932                 pd += vcpu->arch.pio.size;
5933         }
5934         return r;
5935 }
5936
5937 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5938                                unsigned short port, void *val,
5939                                unsigned int count, bool in)
5940 {
5941         vcpu->arch.pio.port = port;
5942         vcpu->arch.pio.in = in;
5943         vcpu->arch.pio.count  = count;
5944         vcpu->arch.pio.size = size;
5945
5946         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5947                 vcpu->arch.pio.count = 0;
5948                 return 1;
5949         }
5950
5951         vcpu->run->exit_reason = KVM_EXIT_IO;
5952         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5953         vcpu->run->io.size = size;
5954         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5955         vcpu->run->io.count = count;
5956         vcpu->run->io.port = port;
5957
5958         return 0;
5959 }
5960
5961 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
5962                            unsigned short port, void *val, unsigned int count)
5963 {
5964         int ret;
5965
5966         if (vcpu->arch.pio.count)
5967                 goto data_avail;
5968
5969         memset(vcpu->arch.pio_data, 0, size * count);
5970
5971         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5972         if (ret) {
5973 data_avail:
5974                 memcpy(val, vcpu->arch.pio_data, size * count);
5975                 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5976                 vcpu->arch.pio.count = 0;
5977                 return 1;
5978         }
5979
5980         return 0;
5981 }
5982
5983 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5984                                     int size, unsigned short port, void *val,
5985                                     unsigned int count)
5986 {
5987         return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
5988
5989 }
5990
5991 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
5992                             unsigned short port, const void *val,
5993                             unsigned int count)
5994 {
5995         memcpy(vcpu->arch.pio_data, val, size * count);
5996         trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5997         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5998 }
5999
6000 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
6001                                      int size, unsigned short port,
6002                                      const void *val, unsigned int count)
6003 {
6004         return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
6005 }
6006
6007 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6008 {
6009         return kvm_x86_ops.get_segment_base(vcpu, seg);
6010 }
6011
6012 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6013 {
6014         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6015 }
6016
6017 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6018 {
6019         if (!need_emulate_wbinvd(vcpu))
6020                 return X86EMUL_CONTINUE;
6021
6022         if (kvm_x86_ops.has_wbinvd_exit()) {
6023                 int cpu = get_cpu();
6024
6025                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6026                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6027                                 wbinvd_ipi, NULL, 1);
6028                 put_cpu();
6029                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6030         } else
6031                 wbinvd();
6032         return X86EMUL_CONTINUE;
6033 }
6034
6035 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6036 {
6037         kvm_emulate_wbinvd_noskip(vcpu);
6038         return kvm_skip_emulated_instruction(vcpu);
6039 }
6040 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6041
6042
6043
6044 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6045 {
6046         kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6047 }
6048
6049 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6050                            unsigned long *dest)
6051 {
6052         return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6053 }
6054
6055 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6056                            unsigned long value)
6057 {
6058
6059         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6060 }
6061
6062 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6063 {
6064         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6065 }
6066
6067 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6068 {
6069         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6070         unsigned long value;
6071
6072         switch (cr) {
6073         case 0:
6074                 value = kvm_read_cr0(vcpu);
6075                 break;
6076         case 2:
6077                 value = vcpu->arch.cr2;
6078                 break;
6079         case 3:
6080                 value = kvm_read_cr3(vcpu);
6081                 break;
6082         case 4:
6083                 value = kvm_read_cr4(vcpu);
6084                 break;
6085         case 8:
6086                 value = kvm_get_cr8(vcpu);
6087                 break;
6088         default:
6089                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6090                 return 0;
6091         }
6092
6093         return value;
6094 }
6095
6096 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6097 {
6098         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6099         int res = 0;
6100
6101         switch (cr) {
6102         case 0:
6103                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6104                 break;
6105         case 2:
6106                 vcpu->arch.cr2 = val;
6107                 break;
6108         case 3:
6109                 res = kvm_set_cr3(vcpu, val);
6110                 break;
6111         case 4:
6112                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6113                 break;
6114         case 8:
6115                 res = kvm_set_cr8(vcpu, val);
6116                 break;
6117         default:
6118                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6119                 res = -1;
6120         }
6121
6122         return res;
6123 }
6124
6125 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6126 {
6127         return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt));
6128 }
6129
6130 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6131 {
6132         kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt);
6133 }
6134
6135 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6136 {
6137         kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt);
6138 }
6139
6140 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6141 {
6142         kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt);
6143 }
6144
6145 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6146 {
6147         kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt);
6148 }
6149
6150 static unsigned long emulator_get_cached_segment_base(
6151         struct x86_emulate_ctxt *ctxt, int seg)
6152 {
6153         return get_segment_base(emul_to_vcpu(ctxt), seg);
6154 }
6155
6156 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6157                                  struct desc_struct *desc, u32 *base3,
6158                                  int seg)
6159 {
6160         struct kvm_segment var;
6161
6162         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6163         *selector = var.selector;
6164
6165         if (var.unusable) {
6166                 memset(desc, 0, sizeof(*desc));
6167                 if (base3)
6168                         *base3 = 0;
6169                 return false;
6170         }
6171
6172         if (var.g)
6173                 var.limit >>= 12;
6174         set_desc_limit(desc, var.limit);
6175         set_desc_base(desc, (unsigned long)var.base);
6176 #ifdef CONFIG_X86_64
6177         if (base3)
6178                 *base3 = var.base >> 32;
6179 #endif
6180         desc->type = var.type;
6181         desc->s = var.s;
6182         desc->dpl = var.dpl;
6183         desc->p = var.present;
6184         desc->avl = var.avl;
6185         desc->l = var.l;
6186         desc->d = var.db;
6187         desc->g = var.g;
6188
6189         return true;
6190 }
6191
6192 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6193                                  struct desc_struct *desc, u32 base3,
6194                                  int seg)
6195 {
6196         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6197         struct kvm_segment var;
6198
6199         var.selector = selector;
6200         var.base = get_desc_base(desc);
6201 #ifdef CONFIG_X86_64
6202         var.base |= ((u64)base3) << 32;
6203 #endif
6204         var.limit = get_desc_limit(desc);
6205         if (desc->g)
6206                 var.limit = (var.limit << 12) | 0xfff;
6207         var.type = desc->type;
6208         var.dpl = desc->dpl;
6209         var.db = desc->d;
6210         var.s = desc->s;
6211         var.l = desc->l;
6212         var.g = desc->g;
6213         var.avl = desc->avl;
6214         var.present = desc->p;
6215         var.unusable = !var.present;
6216         var.padding = 0;
6217
6218         kvm_set_segment(vcpu, &var, seg);
6219         return;
6220 }
6221
6222 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6223                             u32 msr_index, u64 *pdata)
6224 {
6225         return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6226 }
6227
6228 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6229                             u32 msr_index, u64 data)
6230 {
6231         return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6232 }
6233
6234 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6235 {
6236         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6237
6238         return vcpu->arch.smbase;
6239 }
6240
6241 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6242 {
6243         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6244
6245         vcpu->arch.smbase = smbase;
6246 }
6247
6248 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6249                               u32 pmc)
6250 {
6251         return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6252 }
6253
6254 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6255                              u32 pmc, u64 *pdata)
6256 {
6257         return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6258 }
6259
6260 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6261 {
6262         emul_to_vcpu(ctxt)->arch.halt_request = 1;
6263 }
6264
6265 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6266                               struct x86_instruction_info *info,
6267                               enum x86_intercept_stage stage)
6268 {
6269         return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage,
6270                                             &ctxt->exception);
6271 }
6272
6273 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6274                               u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6275                               bool exact_only)
6276 {
6277         return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6278 }
6279
6280 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6281 {
6282         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6283 }
6284
6285 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6286 {
6287         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6288 }
6289
6290 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6291 {
6292         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6293 }
6294
6295 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6296 {
6297         return kvm_register_read(emul_to_vcpu(ctxt), reg);
6298 }
6299
6300 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6301 {
6302         kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6303 }
6304
6305 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6306 {
6307         kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked);
6308 }
6309
6310 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6311 {
6312         return emul_to_vcpu(ctxt)->arch.hflags;
6313 }
6314
6315 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6316 {
6317         emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6318 }
6319
6320 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6321                                   const char *smstate)
6322 {
6323         return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6324 }
6325
6326 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6327 {
6328         kvm_smm_changed(emul_to_vcpu(ctxt));
6329 }
6330
6331 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6332 {
6333         return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6334 }
6335
6336 static const struct x86_emulate_ops emulate_ops = {
6337         .read_gpr            = emulator_read_gpr,
6338         .write_gpr           = emulator_write_gpr,
6339         .read_std            = emulator_read_std,
6340         .write_std           = emulator_write_std,
6341         .read_phys           = kvm_read_guest_phys_system,
6342         .fetch               = kvm_fetch_guest_virt,
6343         .read_emulated       = emulator_read_emulated,
6344         .write_emulated      = emulator_write_emulated,
6345         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
6346         .invlpg              = emulator_invlpg,
6347         .pio_in_emulated     = emulator_pio_in_emulated,
6348         .pio_out_emulated    = emulator_pio_out_emulated,
6349         .get_segment         = emulator_get_segment,
6350         .set_segment         = emulator_set_segment,
6351         .get_cached_segment_base = emulator_get_cached_segment_base,
6352         .get_gdt             = emulator_get_gdt,
6353         .get_idt             = emulator_get_idt,
6354         .set_gdt             = emulator_set_gdt,
6355         .set_idt             = emulator_set_idt,
6356         .get_cr              = emulator_get_cr,
6357         .set_cr              = emulator_set_cr,
6358         .cpl                 = emulator_get_cpl,
6359         .get_dr              = emulator_get_dr,
6360         .set_dr              = emulator_set_dr,
6361         .get_smbase          = emulator_get_smbase,
6362         .set_smbase          = emulator_set_smbase,
6363         .set_msr             = emulator_set_msr,
6364         .get_msr             = emulator_get_msr,
6365         .check_pmc           = emulator_check_pmc,
6366         .read_pmc            = emulator_read_pmc,
6367         .halt                = emulator_halt,
6368         .wbinvd              = emulator_wbinvd,
6369         .fix_hypercall       = emulator_fix_hypercall,
6370         .intercept           = emulator_intercept,
6371         .get_cpuid           = emulator_get_cpuid,
6372         .guest_has_long_mode = emulator_guest_has_long_mode,
6373         .guest_has_movbe     = emulator_guest_has_movbe,
6374         .guest_has_fxsr      = emulator_guest_has_fxsr,
6375         .set_nmi_mask        = emulator_set_nmi_mask,
6376         .get_hflags          = emulator_get_hflags,
6377         .set_hflags          = emulator_set_hflags,
6378         .pre_leave_smm       = emulator_pre_leave_smm,
6379         .post_leave_smm      = emulator_post_leave_smm,
6380         .set_xcr             = emulator_set_xcr,
6381 };
6382
6383 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6384 {
6385         u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
6386         /*
6387          * an sti; sti; sequence only disable interrupts for the first
6388          * instruction. So, if the last instruction, be it emulated or
6389          * not, left the system with the INT_STI flag enabled, it
6390          * means that the last instruction is an sti. We should not
6391          * leave the flag on in this case. The same goes for mov ss
6392          */
6393         if (int_shadow & mask)
6394                 mask = 0;
6395         if (unlikely(int_shadow || mask)) {
6396                 kvm_x86_ops.set_interrupt_shadow(vcpu, mask);
6397                 if (!mask)
6398                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6399         }
6400 }
6401
6402 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6403 {
6404         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6405         if (ctxt->exception.vector == PF_VECTOR)
6406                 return kvm_propagate_fault(vcpu, &ctxt->exception);
6407
6408         if (ctxt->exception.error_code_valid)
6409                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6410                                       ctxt->exception.error_code);
6411         else
6412                 kvm_queue_exception(vcpu, ctxt->exception.vector);
6413         return false;
6414 }
6415
6416 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6417 {
6418         struct x86_emulate_ctxt *ctxt;
6419
6420         ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6421         if (!ctxt) {
6422                 pr_err("kvm: failed to allocate vcpu's emulator\n");
6423                 return NULL;
6424         }
6425
6426         ctxt->vcpu = vcpu;
6427         ctxt->ops = &emulate_ops;
6428         vcpu->arch.emulate_ctxt = ctxt;
6429
6430         return ctxt;
6431 }
6432
6433 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6434 {
6435         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6436         int cs_db, cs_l;
6437
6438         kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6439
6440         ctxt->gpa_available = false;
6441         ctxt->eflags = kvm_get_rflags(vcpu);
6442         ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6443
6444         ctxt->eip = kvm_rip_read(vcpu);
6445         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
6446                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
6447                      (cs_l && is_long_mode(vcpu))       ? X86EMUL_MODE_PROT64 :
6448                      cs_db                              ? X86EMUL_MODE_PROT32 :
6449                                                           X86EMUL_MODE_PROT16;
6450         BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6451         BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6452         BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6453
6454         init_decode_cache(ctxt);
6455         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6456 }
6457
6458 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6459 {
6460         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6461         int ret;
6462
6463         init_emulate_ctxt(vcpu);
6464
6465         ctxt->op_bytes = 2;
6466         ctxt->ad_bytes = 2;
6467         ctxt->_eip = ctxt->eip + inc_eip;
6468         ret = emulate_int_real(ctxt, irq);
6469
6470         if (ret != X86EMUL_CONTINUE) {
6471                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6472         } else {
6473                 ctxt->eip = ctxt->_eip;
6474                 kvm_rip_write(vcpu, ctxt->eip);
6475                 kvm_set_rflags(vcpu, ctxt->eflags);
6476         }
6477 }
6478 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6479
6480 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6481 {
6482         ++vcpu->stat.insn_emulation_fail;
6483         trace_kvm_emulate_insn_failed(vcpu);
6484
6485         if (emulation_type & EMULTYPE_VMWARE_GP) {
6486                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6487                 return 1;
6488         }
6489
6490         if (emulation_type & EMULTYPE_SKIP) {
6491                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6492                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6493                 vcpu->run->internal.ndata = 0;
6494                 return 0;
6495         }
6496
6497         kvm_queue_exception(vcpu, UD_VECTOR);
6498
6499         if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) {
6500                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6501                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6502                 vcpu->run->internal.ndata = 0;
6503                 return 0;
6504         }
6505
6506         return 1;
6507 }
6508
6509 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6510                                   bool write_fault_to_shadow_pgtable,
6511                                   int emulation_type)
6512 {
6513         gpa_t gpa = cr2_or_gpa;
6514         kvm_pfn_t pfn;
6515
6516         if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6517                 return false;
6518
6519         if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6520             WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6521                 return false;
6522
6523         if (!vcpu->arch.mmu->direct_map) {
6524                 /*
6525                  * Write permission should be allowed since only
6526                  * write access need to be emulated.
6527                  */
6528                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6529
6530                 /*
6531                  * If the mapping is invalid in guest, let cpu retry
6532                  * it to generate fault.
6533                  */
6534                 if (gpa == UNMAPPED_GVA)
6535                         return true;
6536         }
6537
6538         /*
6539          * Do not retry the unhandleable instruction if it faults on the
6540          * readonly host memory, otherwise it will goto a infinite loop:
6541          * retry instruction -> write #PF -> emulation fail -> retry
6542          * instruction -> ...
6543          */
6544         pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6545
6546         /*
6547          * If the instruction failed on the error pfn, it can not be fixed,
6548          * report the error to userspace.
6549          */
6550         if (is_error_noslot_pfn(pfn))
6551                 return false;
6552
6553         kvm_release_pfn_clean(pfn);
6554
6555         /* The instructions are well-emulated on direct mmu. */
6556         if (vcpu->arch.mmu->direct_map) {
6557                 unsigned int indirect_shadow_pages;
6558
6559                 spin_lock(&vcpu->kvm->mmu_lock);
6560                 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6561                 spin_unlock(&vcpu->kvm->mmu_lock);
6562
6563                 if (indirect_shadow_pages)
6564                         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6565
6566                 return true;
6567         }
6568
6569         /*
6570          * if emulation was due to access to shadowed page table
6571          * and it failed try to unshadow page and re-enter the
6572          * guest to let CPU execute the instruction.
6573          */
6574         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6575
6576         /*
6577          * If the access faults on its page table, it can not
6578          * be fixed by unprotecting shadow page and it should
6579          * be reported to userspace.
6580          */
6581         return !write_fault_to_shadow_pgtable;
6582 }
6583
6584 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6585                               gpa_t cr2_or_gpa,  int emulation_type)
6586 {
6587         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6588         unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
6589
6590         last_retry_eip = vcpu->arch.last_retry_eip;
6591         last_retry_addr = vcpu->arch.last_retry_addr;
6592
6593         /*
6594          * If the emulation is caused by #PF and it is non-page_table
6595          * writing instruction, it means the VM-EXIT is caused by shadow
6596          * page protected, we can zap the shadow page and retry this
6597          * instruction directly.
6598          *
6599          * Note: if the guest uses a non-page-table modifying instruction
6600          * on the PDE that points to the instruction, then we will unmap
6601          * the instruction and go to an infinite loop. So, we cache the
6602          * last retried eip and the last fault address, if we meet the eip
6603          * and the address again, we can break out of the potential infinite
6604          * loop.
6605          */
6606         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6607
6608         if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6609                 return false;
6610
6611         if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6612             WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6613                 return false;
6614
6615         if (x86_page_table_writing_insn(ctxt))
6616                 return false;
6617
6618         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
6619                 return false;
6620
6621         vcpu->arch.last_retry_eip = ctxt->eip;
6622         vcpu->arch.last_retry_addr = cr2_or_gpa;
6623
6624         if (!vcpu->arch.mmu->direct_map)
6625                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6626
6627         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6628
6629         return true;
6630 }
6631
6632 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6633 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6634
6635 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6636 {
6637         if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6638                 /* This is a good place to trace that we are exiting SMM.  */
6639                 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6640
6641                 /* Process a latched INIT or SMI, if any.  */
6642                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6643         }
6644
6645         kvm_mmu_reset_context(vcpu);
6646 }
6647
6648 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6649                                 unsigned long *db)
6650 {
6651         u32 dr6 = 0;
6652         int i;
6653         u32 enable, rwlen;
6654
6655         enable = dr7;
6656         rwlen = dr7 >> 16;
6657         for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6658                 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6659                         dr6 |= (1 << i);
6660         return dr6;
6661 }
6662
6663 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6664 {
6665         struct kvm_run *kvm_run = vcpu->run;
6666
6667         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6668                 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6669                 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6670                 kvm_run->debug.arch.exception = DB_VECTOR;
6671                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6672                 return 0;
6673         }
6674         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6675         return 1;
6676 }
6677
6678 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6679 {
6680         unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
6681         int r;
6682
6683         r = kvm_x86_ops.skip_emulated_instruction(vcpu);
6684         if (unlikely(!r))
6685                 return 0;
6686
6687         /*
6688          * rflags is the old, "raw" value of the flags.  The new value has
6689          * not been saved yet.
6690          *
6691          * This is correct even for TF set by the guest, because "the
6692          * processor will not generate this exception after the instruction
6693          * that sets the TF flag".
6694          */
6695         if (unlikely(rflags & X86_EFLAGS_TF))
6696                 r = kvm_vcpu_do_singlestep(vcpu);
6697         return r;
6698 }
6699 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6700
6701 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6702 {
6703         if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6704             (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6705                 struct kvm_run *kvm_run = vcpu->run;
6706                 unsigned long eip = kvm_get_linear_rip(vcpu);
6707                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6708                                            vcpu->arch.guest_debug_dr7,
6709                                            vcpu->arch.eff_db);
6710
6711                 if (dr6 != 0) {
6712                         kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6713                         kvm_run->debug.arch.pc = eip;
6714                         kvm_run->debug.arch.exception = DB_VECTOR;
6715                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
6716                         *r = 0;
6717                         return true;
6718                 }
6719         }
6720
6721         if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6722             !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6723                 unsigned long eip = kvm_get_linear_rip(vcpu);
6724                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6725                                            vcpu->arch.dr7,
6726                                            vcpu->arch.db);
6727
6728                 if (dr6 != 0) {
6729                         kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
6730                         *r = 1;
6731                         return true;
6732                 }
6733         }
6734
6735         return false;
6736 }
6737
6738 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6739 {
6740         switch (ctxt->opcode_len) {
6741         case 1:
6742                 switch (ctxt->b) {
6743                 case 0xe4:      /* IN */
6744                 case 0xe5:
6745                 case 0xec:
6746                 case 0xed:
6747                 case 0xe6:      /* OUT */
6748                 case 0xe7:
6749                 case 0xee:
6750                 case 0xef:
6751                 case 0x6c:      /* INS */
6752                 case 0x6d:
6753                 case 0x6e:      /* OUTS */
6754                 case 0x6f:
6755                         return true;
6756                 }
6757                 break;
6758         case 2:
6759                 switch (ctxt->b) {
6760                 case 0x33:      /* RDPMC */
6761                         return true;
6762                 }
6763                 break;
6764         }
6765
6766         return false;
6767 }
6768
6769 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6770                             int emulation_type, void *insn, int insn_len)
6771 {
6772         int r;
6773         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6774         bool writeback = true;
6775         bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6776
6777         vcpu->arch.l1tf_flush_l1d = true;
6778
6779         /*
6780          * Clear write_fault_to_shadow_pgtable here to ensure it is
6781          * never reused.
6782          */
6783         vcpu->arch.write_fault_to_shadow_pgtable = false;
6784         kvm_clear_exception_queue(vcpu);
6785
6786         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6787                 init_emulate_ctxt(vcpu);
6788
6789                 /*
6790                  * We will reenter on the same instruction since
6791                  * we do not set complete_userspace_io.  This does not
6792                  * handle watchpoints yet, those would be handled in
6793                  * the emulate_ops.
6794                  */
6795                 if (!(emulation_type & EMULTYPE_SKIP) &&
6796                     kvm_vcpu_check_breakpoint(vcpu, &r))
6797                         return r;
6798
6799                 ctxt->interruptibility = 0;
6800                 ctxt->have_exception = false;
6801                 ctxt->exception.vector = -1;
6802                 ctxt->perm_ok = false;
6803
6804                 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6805
6806                 r = x86_decode_insn(ctxt, insn, insn_len);
6807
6808                 trace_kvm_emulate_insn_start(vcpu);
6809                 ++vcpu->stat.insn_emulation;
6810                 if (r != EMULATION_OK)  {
6811                         if ((emulation_type & EMULTYPE_TRAP_UD) ||
6812                             (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6813                                 kvm_queue_exception(vcpu, UD_VECTOR);
6814                                 return 1;
6815                         }
6816                         if (reexecute_instruction(vcpu, cr2_or_gpa,
6817                                                   write_fault_to_spt,
6818                                                   emulation_type))
6819                                 return 1;
6820                         if (ctxt->have_exception) {
6821                                 /*
6822                                  * #UD should result in just EMULATION_FAILED, and trap-like
6823                                  * exception should not be encountered during decode.
6824                                  */
6825                                 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6826                                              exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6827                                 inject_emulated_exception(vcpu);
6828                                 return 1;
6829                         }
6830                         return handle_emulation_failure(vcpu, emulation_type);
6831                 }
6832         }
6833
6834         if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6835             !is_vmware_backdoor_opcode(ctxt)) {
6836                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6837                 return 1;
6838         }
6839
6840         /*
6841          * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6842          * for kvm_skip_emulated_instruction().  The caller is responsible for
6843          * updating interruptibility state and injecting single-step #DBs.
6844          */
6845         if (emulation_type & EMULTYPE_SKIP) {
6846                 kvm_rip_write(vcpu, ctxt->_eip);
6847                 if (ctxt->eflags & X86_EFLAGS_RF)
6848                         kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6849                 return 1;
6850         }
6851
6852         if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
6853                 return 1;
6854
6855         /* this is needed for vmware backdoor interface to work since it
6856            changes registers values  during IO operation */
6857         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6858                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6859                 emulator_invalidate_register_cache(ctxt);
6860         }
6861
6862 restart:
6863         if (emulation_type & EMULTYPE_PF) {
6864                 /* Save the faulting GPA (cr2) in the address field */
6865                 ctxt->exception.address = cr2_or_gpa;
6866
6867                 /* With shadow page tables, cr2 contains a GVA or nGPA. */
6868                 if (vcpu->arch.mmu->direct_map) {
6869                         ctxt->gpa_available = true;
6870                         ctxt->gpa_val = cr2_or_gpa;
6871                 }
6872         } else {
6873                 /* Sanitize the address out of an abundance of paranoia. */
6874                 ctxt->exception.address = 0;
6875         }
6876
6877         r = x86_emulate_insn(ctxt);
6878
6879         if (r == EMULATION_INTERCEPTED)
6880                 return 1;
6881
6882         if (r == EMULATION_FAILED) {
6883                 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
6884                                         emulation_type))
6885                         return 1;
6886
6887                 return handle_emulation_failure(vcpu, emulation_type);
6888         }
6889
6890         if (ctxt->have_exception) {
6891                 r = 1;
6892                 if (inject_emulated_exception(vcpu))
6893                         return r;
6894         } else if (vcpu->arch.pio.count) {
6895                 if (!vcpu->arch.pio.in) {
6896                         /* FIXME: return into emulator if single-stepping.  */
6897                         vcpu->arch.pio.count = 0;
6898                 } else {
6899                         writeback = false;
6900                         vcpu->arch.complete_userspace_io = complete_emulated_pio;
6901                 }
6902                 r = 0;
6903         } else if (vcpu->mmio_needed) {
6904                 ++vcpu->stat.mmio_exits;
6905
6906                 if (!vcpu->mmio_is_write)
6907                         writeback = false;
6908                 r = 0;
6909                 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6910         } else if (r == EMULATION_RESTART)
6911                 goto restart;
6912         else
6913                 r = 1;
6914
6915         if (writeback) {
6916                 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
6917                 toggle_interruptibility(vcpu, ctxt->interruptibility);
6918                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6919                 if (!ctxt->have_exception ||
6920                     exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6921                         kvm_rip_write(vcpu, ctxt->eip);
6922                         if (r && ctxt->tf)
6923                                 r = kvm_vcpu_do_singlestep(vcpu);
6924                         if (kvm_x86_ops.update_emulated_instruction)
6925                                 kvm_x86_ops.update_emulated_instruction(vcpu);
6926                         __kvm_set_rflags(vcpu, ctxt->eflags);
6927                 }
6928
6929                 /*
6930                  * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6931                  * do nothing, and it will be requested again as soon as
6932                  * the shadow expires.  But we still need to check here,
6933                  * because POPF has no interrupt shadow.
6934                  */
6935                 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6936                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6937         } else
6938                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6939
6940         return r;
6941 }
6942
6943 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6944 {
6945         return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6946 }
6947 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6948
6949 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6950                                         void *insn, int insn_len)
6951 {
6952         return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6953 }
6954 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6955
6956 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6957 {
6958         vcpu->arch.pio.count = 0;
6959         return 1;
6960 }
6961
6962 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6963 {
6964         vcpu->arch.pio.count = 0;
6965
6966         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6967                 return 1;
6968
6969         return kvm_skip_emulated_instruction(vcpu);
6970 }
6971
6972 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6973                             unsigned short port)
6974 {
6975         unsigned long val = kvm_rax_read(vcpu);
6976         int ret = emulator_pio_out(vcpu, size, port, &val, 1);
6977
6978         if (ret)
6979                 return ret;
6980
6981         /*
6982          * Workaround userspace that relies on old KVM behavior of %rip being
6983          * incremented prior to exiting to userspace to handle "OUT 0x7e".
6984          */
6985         if (port == 0x7e &&
6986             kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6987                 vcpu->arch.complete_userspace_io =
6988                         complete_fast_pio_out_port_0x7e;
6989                 kvm_skip_emulated_instruction(vcpu);
6990         } else {
6991                 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6992                 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6993         }
6994         return 0;
6995 }
6996
6997 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6998 {
6999         unsigned long val;
7000
7001         /* We should only ever be called with arch.pio.count equal to 1 */
7002         BUG_ON(vcpu->arch.pio.count != 1);
7003
7004         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
7005                 vcpu->arch.pio.count = 0;
7006                 return 1;
7007         }
7008
7009         /* For size less than 4 we merge, else we zero extend */
7010         val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7011
7012         /*
7013          * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7014          * the copy and tracing
7015          */
7016         emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7017         kvm_rax_write(vcpu, val);
7018
7019         return kvm_skip_emulated_instruction(vcpu);
7020 }
7021
7022 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7023                            unsigned short port)
7024 {
7025         unsigned long val;
7026         int ret;
7027
7028         /* For size less than 4 we merge, else we zero extend */
7029         val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7030
7031         ret = emulator_pio_in(vcpu, size, port, &val, 1);
7032         if (ret) {
7033                 kvm_rax_write(vcpu, val);
7034                 return ret;
7035         }
7036
7037         vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7038         vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7039
7040         return 0;
7041 }
7042
7043 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7044 {
7045         int ret;
7046
7047         if (in)
7048                 ret = kvm_fast_pio_in(vcpu, size, port);
7049         else
7050                 ret = kvm_fast_pio_out(vcpu, size, port);
7051         return ret && kvm_skip_emulated_instruction(vcpu);
7052 }
7053 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7054
7055 static int kvmclock_cpu_down_prep(unsigned int cpu)
7056 {
7057         __this_cpu_write(cpu_tsc_khz, 0);
7058         return 0;
7059 }
7060
7061 static void tsc_khz_changed(void *data)
7062 {
7063         struct cpufreq_freqs *freq = data;
7064         unsigned long khz = 0;
7065
7066         if (data)
7067                 khz = freq->new;
7068         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7069                 khz = cpufreq_quick_get(raw_smp_processor_id());
7070         if (!khz)
7071                 khz = tsc_khz;
7072         __this_cpu_write(cpu_tsc_khz, khz);
7073 }
7074
7075 #ifdef CONFIG_X86_64
7076 static void kvm_hyperv_tsc_notifier(void)
7077 {
7078         struct kvm *kvm;
7079         struct kvm_vcpu *vcpu;
7080         int cpu;
7081
7082         mutex_lock(&kvm_lock);
7083         list_for_each_entry(kvm, &vm_list, vm_list)
7084                 kvm_make_mclock_inprogress_request(kvm);
7085
7086         hyperv_stop_tsc_emulation();
7087
7088         /* TSC frequency always matches when on Hyper-V */
7089         for_each_present_cpu(cpu)
7090                 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7091         kvm_max_guest_tsc_khz = tsc_khz;
7092
7093         list_for_each_entry(kvm, &vm_list, vm_list) {
7094                 struct kvm_arch *ka = &kvm->arch;
7095
7096                 spin_lock(&ka->pvclock_gtod_sync_lock);
7097
7098                 pvclock_update_vm_gtod_copy(kvm);
7099
7100                 kvm_for_each_vcpu(cpu, vcpu, kvm)
7101                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7102
7103                 kvm_for_each_vcpu(cpu, vcpu, kvm)
7104                         kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7105
7106                 spin_unlock(&ka->pvclock_gtod_sync_lock);
7107         }
7108         mutex_unlock(&kvm_lock);
7109 }
7110 #endif
7111
7112 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7113 {
7114         struct kvm *kvm;
7115         struct kvm_vcpu *vcpu;
7116         int i, send_ipi = 0;
7117
7118         /*
7119          * We allow guests to temporarily run on slowing clocks,
7120          * provided we notify them after, or to run on accelerating
7121          * clocks, provided we notify them before.  Thus time never
7122          * goes backwards.
7123          *
7124          * However, we have a problem.  We can't atomically update
7125          * the frequency of a given CPU from this function; it is
7126          * merely a notifier, which can be called from any CPU.
7127          * Changing the TSC frequency at arbitrary points in time
7128          * requires a recomputation of local variables related to
7129          * the TSC for each VCPU.  We must flag these local variables
7130          * to be updated and be sure the update takes place with the
7131          * new frequency before any guests proceed.
7132          *
7133          * Unfortunately, the combination of hotplug CPU and frequency
7134          * change creates an intractable locking scenario; the order
7135          * of when these callouts happen is undefined with respect to
7136          * CPU hotplug, and they can race with each other.  As such,
7137          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7138          * undefined; you can actually have a CPU frequency change take
7139          * place in between the computation of X and the setting of the
7140          * variable.  To protect against this problem, all updates of
7141          * the per_cpu tsc_khz variable are done in an interrupt
7142          * protected IPI, and all callers wishing to update the value
7143          * must wait for a synchronous IPI to complete (which is trivial
7144          * if the caller is on the CPU already).  This establishes the
7145          * necessary total order on variable updates.
7146          *
7147          * Note that because a guest time update may take place
7148          * anytime after the setting of the VCPU's request bit, the
7149          * correct TSC value must be set before the request.  However,
7150          * to ensure the update actually makes it to any guest which
7151          * starts running in hardware virtualization between the set
7152          * and the acquisition of the spinlock, we must also ping the
7153          * CPU after setting the request bit.
7154          *
7155          */
7156
7157         smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7158
7159         mutex_lock(&kvm_lock);
7160         list_for_each_entry(kvm, &vm_list, vm_list) {
7161                 kvm_for_each_vcpu(i, vcpu, kvm) {
7162                         if (vcpu->cpu != cpu)
7163                                 continue;
7164                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7165                         if (vcpu->cpu != raw_smp_processor_id())
7166                                 send_ipi = 1;
7167                 }
7168         }
7169         mutex_unlock(&kvm_lock);
7170
7171         if (freq->old < freq->new && send_ipi) {
7172                 /*
7173                  * We upscale the frequency.  Must make the guest
7174                  * doesn't see old kvmclock values while running with
7175                  * the new frequency, otherwise we risk the guest sees
7176                  * time go backwards.
7177                  *
7178                  * In case we update the frequency for another cpu
7179                  * (which might be in guest context) send an interrupt
7180                  * to kick the cpu out of guest context.  Next time
7181                  * guest context is entered kvmclock will be updated,
7182                  * so the guest will not see stale values.
7183                  */
7184                 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7185         }
7186 }
7187
7188 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7189                                      void *data)
7190 {
7191         struct cpufreq_freqs *freq = data;
7192         int cpu;
7193
7194         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7195                 return 0;
7196         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7197                 return 0;
7198
7199         for_each_cpu(cpu, freq->policy->cpus)
7200                 __kvmclock_cpufreq_notifier(freq, cpu);
7201
7202         return 0;
7203 }
7204
7205 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7206         .notifier_call  = kvmclock_cpufreq_notifier
7207 };
7208
7209 static int kvmclock_cpu_online(unsigned int cpu)
7210 {
7211         tsc_khz_changed(NULL);
7212         return 0;
7213 }
7214
7215 static void kvm_timer_init(void)
7216 {
7217         max_tsc_khz = tsc_khz;
7218
7219         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7220 #ifdef CONFIG_CPU_FREQ
7221                 struct cpufreq_policy *policy;
7222                 int cpu;
7223
7224                 cpu = get_cpu();
7225                 policy = cpufreq_cpu_get(cpu);
7226                 if (policy) {
7227                         if (policy->cpuinfo.max_freq)
7228                                 max_tsc_khz = policy->cpuinfo.max_freq;
7229                         cpufreq_cpu_put(policy);
7230                 }
7231                 put_cpu();
7232 #endif
7233                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7234                                           CPUFREQ_TRANSITION_NOTIFIER);
7235         }
7236
7237         cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7238                           kvmclock_cpu_online, kvmclock_cpu_down_prep);
7239 }
7240
7241 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7242 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7243
7244 int kvm_is_in_guest(void)
7245 {
7246         return __this_cpu_read(current_vcpu) != NULL;
7247 }
7248
7249 static int kvm_is_user_mode(void)
7250 {
7251         int user_mode = 3;
7252
7253         if (__this_cpu_read(current_vcpu))
7254                 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu));
7255
7256         return user_mode != 0;
7257 }
7258
7259 static unsigned long kvm_get_guest_ip(void)
7260 {
7261         unsigned long ip = 0;
7262
7263         if (__this_cpu_read(current_vcpu))
7264                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7265
7266         return ip;
7267 }
7268
7269 static void kvm_handle_intel_pt_intr(void)
7270 {
7271         struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7272
7273         kvm_make_request(KVM_REQ_PMI, vcpu);
7274         __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7275                         (unsigned long *)&vcpu->arch.pmu.global_status);
7276 }
7277
7278 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7279         .is_in_guest            = kvm_is_in_guest,
7280         .is_user_mode           = kvm_is_user_mode,
7281         .get_guest_ip           = kvm_get_guest_ip,
7282         .handle_intel_pt_intr   = kvm_handle_intel_pt_intr,
7283 };
7284
7285 #ifdef CONFIG_X86_64
7286 static void pvclock_gtod_update_fn(struct work_struct *work)
7287 {
7288         struct kvm *kvm;
7289
7290         struct kvm_vcpu *vcpu;
7291         int i;
7292
7293         mutex_lock(&kvm_lock);
7294         list_for_each_entry(kvm, &vm_list, vm_list)
7295                 kvm_for_each_vcpu(i, vcpu, kvm)
7296                         kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7297         atomic_set(&kvm_guest_has_master_clock, 0);
7298         mutex_unlock(&kvm_lock);
7299 }
7300
7301 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7302
7303 /*
7304  * Notification about pvclock gtod data update.
7305  */
7306 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7307                                void *priv)
7308 {
7309         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7310         struct timekeeper *tk = priv;
7311
7312         update_pvclock_gtod(tk);
7313
7314         /* disable master clock if host does not trust, or does not
7315          * use, TSC based clocksource.
7316          */
7317         if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7318             atomic_read(&kvm_guest_has_master_clock) != 0)
7319                 queue_work(system_long_wq, &pvclock_gtod_work);
7320
7321         return 0;
7322 }
7323
7324 static struct notifier_block pvclock_gtod_notifier = {
7325         .notifier_call = pvclock_gtod_notify,
7326 };
7327 #endif
7328
7329 int kvm_arch_init(void *opaque)
7330 {
7331         struct kvm_x86_init_ops *ops = opaque;
7332         int r;
7333
7334         if (kvm_x86_ops.hardware_enable) {
7335                 printk(KERN_ERR "kvm: already loaded the other module\n");
7336                 r = -EEXIST;
7337                 goto out;
7338         }
7339
7340         if (!ops->cpu_has_kvm_support()) {
7341                 pr_err_ratelimited("kvm: no hardware support\n");
7342                 r = -EOPNOTSUPP;
7343                 goto out;
7344         }
7345         if (ops->disabled_by_bios()) {
7346                 pr_err_ratelimited("kvm: disabled by bios\n");
7347                 r = -EOPNOTSUPP;
7348                 goto out;
7349         }
7350
7351         /*
7352          * KVM explicitly assumes that the guest has an FPU and
7353          * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7354          * vCPU's FPU state as a fxregs_state struct.
7355          */
7356         if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7357                 printk(KERN_ERR "kvm: inadequate fpu\n");
7358                 r = -EOPNOTSUPP;
7359                 goto out;
7360         }
7361
7362         r = -ENOMEM;
7363         x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7364                                           __alignof__(struct fpu), SLAB_ACCOUNT,
7365                                           NULL);
7366         if (!x86_fpu_cache) {
7367                 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7368                 goto out;
7369         }
7370
7371         x86_emulator_cache = kvm_alloc_emulator_cache();
7372         if (!x86_emulator_cache) {
7373                 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7374                 goto out_free_x86_fpu_cache;
7375         }
7376
7377         shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7378         if (!shared_msrs) {
7379                 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7380                 goto out_free_x86_emulator_cache;
7381         }
7382
7383         r = kvm_mmu_module_init();
7384         if (r)
7385                 goto out_free_percpu;
7386
7387         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7388                         PT_DIRTY_MASK, PT64_NX_MASK, 0,
7389                         PT_PRESENT_MASK, 0, sme_me_mask);
7390         kvm_timer_init();
7391
7392         perf_register_guest_info_callbacks(&kvm_guest_cbs);
7393
7394         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7395                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7396                 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7397         }
7398
7399         kvm_lapic_init();
7400         if (pi_inject_timer == -1)
7401                 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7402 #ifdef CONFIG_X86_64
7403         pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7404
7405         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7406                 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7407 #endif
7408
7409         return 0;
7410
7411 out_free_percpu:
7412         free_percpu(shared_msrs);
7413 out_free_x86_emulator_cache:
7414         kmem_cache_destroy(x86_emulator_cache);
7415 out_free_x86_fpu_cache:
7416         kmem_cache_destroy(x86_fpu_cache);
7417 out:
7418         return r;
7419 }
7420
7421 void kvm_arch_exit(void)
7422 {
7423 #ifdef CONFIG_X86_64
7424         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7425                 clear_hv_tscchange_cb();
7426 #endif
7427         kvm_lapic_exit();
7428         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7429
7430         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7431                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7432                                             CPUFREQ_TRANSITION_NOTIFIER);
7433         cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7434 #ifdef CONFIG_X86_64
7435         pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7436 #endif
7437         kvm_x86_ops.hardware_enable = NULL;
7438         kvm_mmu_module_exit();
7439         free_percpu(shared_msrs);
7440         kmem_cache_destroy(x86_fpu_cache);
7441 }
7442
7443 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7444 {
7445         ++vcpu->stat.halt_exits;
7446         if (lapic_in_kernel(vcpu)) {
7447                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7448                 return 1;
7449         } else {
7450                 vcpu->run->exit_reason = KVM_EXIT_HLT;
7451                 return 0;
7452         }
7453 }
7454 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7455
7456 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7457 {
7458         int ret = kvm_skip_emulated_instruction(vcpu);
7459         /*
7460          * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7461          * KVM_EXIT_DEBUG here.
7462          */
7463         return kvm_vcpu_halt(vcpu) && ret;
7464 }
7465 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7466
7467 #ifdef CONFIG_X86_64
7468 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7469                                 unsigned long clock_type)
7470 {
7471         struct kvm_clock_pairing clock_pairing;
7472         struct timespec64 ts;
7473         u64 cycle;
7474         int ret;
7475
7476         if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7477                 return -KVM_EOPNOTSUPP;
7478
7479         if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7480                 return -KVM_EOPNOTSUPP;
7481
7482         clock_pairing.sec = ts.tv_sec;
7483         clock_pairing.nsec = ts.tv_nsec;
7484         clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7485         clock_pairing.flags = 0;
7486         memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7487
7488         ret = 0;
7489         if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7490                             sizeof(struct kvm_clock_pairing)))
7491                 ret = -KVM_EFAULT;
7492
7493         return ret;
7494 }
7495 #endif
7496
7497 /*
7498  * kvm_pv_kick_cpu_op:  Kick a vcpu.
7499  *
7500  * @apicid - apicid of vcpu to be kicked.
7501  */
7502 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7503 {
7504         struct kvm_lapic_irq lapic_irq;
7505
7506         lapic_irq.shorthand = APIC_DEST_NOSHORT;
7507         lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
7508         lapic_irq.level = 0;
7509         lapic_irq.dest_id = apicid;
7510         lapic_irq.msi_redir_hint = false;
7511
7512         lapic_irq.delivery_mode = APIC_DM_REMRD;
7513         kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7514 }
7515
7516 bool kvm_apicv_activated(struct kvm *kvm)
7517 {
7518         return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
7519 }
7520 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
7521
7522 void kvm_apicv_init(struct kvm *kvm, bool enable)
7523 {
7524         if (enable)
7525                 clear_bit(APICV_INHIBIT_REASON_DISABLE,
7526                           &kvm->arch.apicv_inhibit_reasons);
7527         else
7528                 set_bit(APICV_INHIBIT_REASON_DISABLE,
7529                         &kvm->arch.apicv_inhibit_reasons);
7530 }
7531 EXPORT_SYMBOL_GPL(kvm_apicv_init);
7532
7533 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7534 {
7535         struct kvm_vcpu *target = NULL;
7536         struct kvm_apic_map *map;
7537
7538         rcu_read_lock();
7539         map = rcu_dereference(kvm->arch.apic_map);
7540
7541         if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7542                 target = map->phys_map[dest_id]->vcpu;
7543
7544         rcu_read_unlock();
7545
7546         if (target && READ_ONCE(target->ready))
7547                 kvm_vcpu_yield_to(target);
7548 }
7549
7550 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7551 {
7552         unsigned long nr, a0, a1, a2, a3, ret;
7553         int op_64_bit;
7554
7555         if (kvm_hv_hypercall_enabled(vcpu->kvm))
7556                 return kvm_hv_hypercall(vcpu);
7557
7558         nr = kvm_rax_read(vcpu);
7559         a0 = kvm_rbx_read(vcpu);
7560         a1 = kvm_rcx_read(vcpu);
7561         a2 = kvm_rdx_read(vcpu);
7562         a3 = kvm_rsi_read(vcpu);
7563
7564         trace_kvm_hypercall(nr, a0, a1, a2, a3);
7565
7566         op_64_bit = is_64_bit_mode(vcpu);
7567         if (!op_64_bit) {
7568                 nr &= 0xFFFFFFFF;
7569                 a0 &= 0xFFFFFFFF;
7570                 a1 &= 0xFFFFFFFF;
7571                 a2 &= 0xFFFFFFFF;
7572                 a3 &= 0xFFFFFFFF;
7573         }
7574
7575         if (kvm_x86_ops.get_cpl(vcpu) != 0) {
7576                 ret = -KVM_EPERM;
7577                 goto out;
7578         }
7579
7580         switch (nr) {
7581         case KVM_HC_VAPIC_POLL_IRQ:
7582                 ret = 0;
7583                 break;
7584         case KVM_HC_KICK_CPU:
7585                 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7586                 kvm_sched_yield(vcpu->kvm, a1);
7587                 ret = 0;
7588                 break;
7589 #ifdef CONFIG_X86_64
7590         case KVM_HC_CLOCK_PAIRING:
7591                 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7592                 break;
7593 #endif
7594         case KVM_HC_SEND_IPI:
7595                 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7596                 break;
7597         case KVM_HC_SCHED_YIELD:
7598                 kvm_sched_yield(vcpu->kvm, a0);
7599                 ret = 0;
7600                 break;
7601         default:
7602                 ret = -KVM_ENOSYS;
7603                 break;
7604         }
7605 out:
7606         if (!op_64_bit)
7607                 ret = (u32)ret;
7608         kvm_rax_write(vcpu, ret);
7609
7610         ++vcpu->stat.hypercalls;
7611         return kvm_skip_emulated_instruction(vcpu);
7612 }
7613 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7614
7615 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7616 {
7617         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7618         char instruction[3];
7619         unsigned long rip = kvm_rip_read(vcpu);
7620
7621         kvm_x86_ops.patch_hypercall(vcpu, instruction);
7622
7623         return emulator_write_emulated(ctxt, rip, instruction, 3,
7624                 &ctxt->exception);
7625 }
7626
7627 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7628 {
7629         return vcpu->run->request_interrupt_window &&
7630                 likely(!pic_in_kernel(vcpu->kvm));
7631 }
7632
7633 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7634 {
7635         struct kvm_run *kvm_run = vcpu->run;
7636
7637         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7638         kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7639         kvm_run->cr8 = kvm_get_cr8(vcpu);
7640         kvm_run->apic_base = kvm_get_apic_base(vcpu);
7641         kvm_run->ready_for_interrupt_injection =
7642                 pic_in_kernel(vcpu->kvm) ||
7643                 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7644 }
7645
7646 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7647 {
7648         int max_irr, tpr;
7649
7650         if (!kvm_x86_ops.update_cr8_intercept)
7651                 return;
7652
7653         if (!lapic_in_kernel(vcpu))
7654                 return;
7655
7656         if (vcpu->arch.apicv_active)
7657                 return;
7658
7659         if (!vcpu->arch.apic->vapic_addr)
7660                 max_irr = kvm_lapic_find_highest_irr(vcpu);
7661         else
7662                 max_irr = -1;
7663
7664         if (max_irr != -1)
7665                 max_irr >>= 4;
7666
7667         tpr = kvm_lapic_get_cr8(vcpu);
7668
7669         kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr);
7670 }
7671
7672 static int inject_pending_event(struct kvm_vcpu *vcpu)
7673 {
7674         int r;
7675
7676         /* try to reinject previous events if any */
7677
7678         if (vcpu->arch.exception.injected)
7679                 kvm_x86_ops.queue_exception(vcpu);
7680         /*
7681          * Do not inject an NMI or interrupt if there is a pending
7682          * exception.  Exceptions and interrupts are recognized at
7683          * instruction boundaries, i.e. the start of an instruction.
7684          * Trap-like exceptions, e.g. #DB, have higher priority than
7685          * NMIs and interrupts, i.e. traps are recognized before an
7686          * NMI/interrupt that's pending on the same instruction.
7687          * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7688          * priority, but are only generated (pended) during instruction
7689          * execution, i.e. a pending fault-like exception means the
7690          * fault occurred on the *previous* instruction and must be
7691          * serviced prior to recognizing any new events in order to
7692          * fully complete the previous instruction.
7693          */
7694         else if (!vcpu->arch.exception.pending) {
7695                 if (vcpu->arch.nmi_injected)
7696                         kvm_x86_ops.set_nmi(vcpu);
7697                 else if (vcpu->arch.interrupt.injected)
7698                         kvm_x86_ops.set_irq(vcpu);
7699         }
7700
7701         /*
7702          * Call check_nested_events() even if we reinjected a previous event
7703          * in order for caller to determine if it should require immediate-exit
7704          * from L2 to L1 due to pending L1 events which require exit
7705          * from L2 to L1.
7706          */
7707         if (is_guest_mode(vcpu) && kvm_x86_ops.check_nested_events) {
7708                 r = kvm_x86_ops.check_nested_events(vcpu);
7709                 if (r != 0)
7710                         return r;
7711         }
7712
7713         /* try to inject new event if pending */
7714         if (vcpu->arch.exception.pending) {
7715                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7716                                         vcpu->arch.exception.has_error_code,
7717                                         vcpu->arch.exception.error_code);
7718
7719                 WARN_ON_ONCE(vcpu->arch.exception.injected);
7720                 vcpu->arch.exception.pending = false;
7721                 vcpu->arch.exception.injected = true;
7722
7723                 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7724                         __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7725                                              X86_EFLAGS_RF);
7726
7727                 if (vcpu->arch.exception.nr == DB_VECTOR) {
7728                         /*
7729                          * This code assumes that nSVM doesn't use
7730                          * check_nested_events(). If it does, the
7731                          * DR6/DR7 changes should happen before L1
7732                          * gets a #VMEXIT for an intercepted #DB in
7733                          * L2.  (Under VMX, on the other hand, the
7734                          * DR6/DR7 changes should not happen in the
7735                          * event of a VM-exit to L1 for an intercepted
7736                          * #DB in L2.)
7737                          */
7738                         kvm_deliver_exception_payload(vcpu);
7739                         if (vcpu->arch.dr7 & DR7_GD) {
7740                                 vcpu->arch.dr7 &= ~DR7_GD;
7741                                 kvm_update_dr7(vcpu);
7742                         }
7743                 }
7744
7745                 kvm_x86_ops.queue_exception(vcpu);
7746         }
7747
7748         /* Don't consider new event if we re-injected an event */
7749         if (kvm_event_needs_reinjection(vcpu))
7750                 return 0;
7751
7752         if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7753             kvm_x86_ops.smi_allowed(vcpu)) {
7754                 vcpu->arch.smi_pending = false;
7755                 ++vcpu->arch.smi_count;
7756                 enter_smm(vcpu);
7757         } else if (vcpu->arch.nmi_pending && kvm_x86_ops.nmi_allowed(vcpu)) {
7758                 --vcpu->arch.nmi_pending;
7759                 vcpu->arch.nmi_injected = true;
7760                 kvm_x86_ops.set_nmi(vcpu);
7761         } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7762                 /*
7763                  * Because interrupts can be injected asynchronously, we are
7764                  * calling check_nested_events again here to avoid a race condition.
7765                  * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7766                  * proposal and current concerns.  Perhaps we should be setting
7767                  * KVM_REQ_EVENT only on certain events and not unconditionally?
7768                  */
7769                 if (is_guest_mode(vcpu) && kvm_x86_ops.check_nested_events) {
7770                         r = kvm_x86_ops.check_nested_events(vcpu);
7771                         if (r != 0)
7772                                 return r;
7773                 }
7774                 if (kvm_x86_ops.interrupt_allowed(vcpu)) {
7775                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7776                                             false);
7777                         kvm_x86_ops.set_irq(vcpu);
7778                 }
7779         }
7780
7781         return 0;
7782 }
7783
7784 static void process_nmi(struct kvm_vcpu *vcpu)
7785 {
7786         unsigned limit = 2;
7787
7788         /*
7789          * x86 is limited to one NMI running, and one NMI pending after it.
7790          * If an NMI is already in progress, limit further NMIs to just one.
7791          * Otherwise, allow two (and we'll inject the first one immediately).
7792          */
7793         if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7794                 limit = 1;
7795
7796         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7797         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7798         kvm_make_request(KVM_REQ_EVENT, vcpu);
7799 }
7800
7801 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7802 {
7803         u32 flags = 0;
7804         flags |= seg->g       << 23;
7805         flags |= seg->db      << 22;
7806         flags |= seg->l       << 21;
7807         flags |= seg->avl     << 20;
7808         flags |= seg->present << 15;
7809         flags |= seg->dpl     << 13;
7810         flags |= seg->s       << 12;
7811         flags |= seg->type    << 8;
7812         return flags;
7813 }
7814
7815 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7816 {
7817         struct kvm_segment seg;
7818         int offset;
7819
7820         kvm_get_segment(vcpu, &seg, n);
7821         put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7822
7823         if (n < 3)
7824                 offset = 0x7f84 + n * 12;
7825         else
7826                 offset = 0x7f2c + (n - 3) * 12;
7827
7828         put_smstate(u32, buf, offset + 8, seg.base);
7829         put_smstate(u32, buf, offset + 4, seg.limit);
7830         put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7831 }
7832
7833 #ifdef CONFIG_X86_64
7834 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7835 {
7836         struct kvm_segment seg;
7837         int offset;
7838         u16 flags;
7839
7840         kvm_get_segment(vcpu, &seg, n);
7841         offset = 0x7e00 + n * 16;
7842
7843         flags = enter_smm_get_segment_flags(&seg) >> 8;
7844         put_smstate(u16, buf, offset, seg.selector);
7845         put_smstate(u16, buf, offset + 2, flags);
7846         put_smstate(u32, buf, offset + 4, seg.limit);
7847         put_smstate(u64, buf, offset + 8, seg.base);
7848 }
7849 #endif
7850
7851 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7852 {
7853         struct desc_ptr dt;
7854         struct kvm_segment seg;
7855         unsigned long val;
7856         int i;
7857
7858         put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7859         put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7860         put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7861         put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7862
7863         for (i = 0; i < 8; i++)
7864                 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7865
7866         kvm_get_dr(vcpu, 6, &val);
7867         put_smstate(u32, buf, 0x7fcc, (u32)val);
7868         kvm_get_dr(vcpu, 7, &val);
7869         put_smstate(u32, buf, 0x7fc8, (u32)val);
7870
7871         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7872         put_smstate(u32, buf, 0x7fc4, seg.selector);
7873         put_smstate(u32, buf, 0x7f64, seg.base);
7874         put_smstate(u32, buf, 0x7f60, seg.limit);
7875         put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7876
7877         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7878         put_smstate(u32, buf, 0x7fc0, seg.selector);
7879         put_smstate(u32, buf, 0x7f80, seg.base);
7880         put_smstate(u32, buf, 0x7f7c, seg.limit);
7881         put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7882
7883         kvm_x86_ops.get_gdt(vcpu, &dt);
7884         put_smstate(u32, buf, 0x7f74, dt.address);
7885         put_smstate(u32, buf, 0x7f70, dt.size);
7886
7887         kvm_x86_ops.get_idt(vcpu, &dt);
7888         put_smstate(u32, buf, 0x7f58, dt.address);
7889         put_smstate(u32, buf, 0x7f54, dt.size);
7890
7891         for (i = 0; i < 6; i++)
7892                 enter_smm_save_seg_32(vcpu, buf, i);
7893
7894         put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7895
7896         /* revision id */
7897         put_smstate(u32, buf, 0x7efc, 0x00020000);
7898         put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7899 }
7900
7901 #ifdef CONFIG_X86_64
7902 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7903 {
7904         struct desc_ptr dt;
7905         struct kvm_segment seg;
7906         unsigned long val;
7907         int i;
7908
7909         for (i = 0; i < 16; i++)
7910                 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7911
7912         put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7913         put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7914
7915         kvm_get_dr(vcpu, 6, &val);
7916         put_smstate(u64, buf, 0x7f68, val);
7917         kvm_get_dr(vcpu, 7, &val);
7918         put_smstate(u64, buf, 0x7f60, val);
7919
7920         put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7921         put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7922         put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7923
7924         put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7925
7926         /* revision id */
7927         put_smstate(u32, buf, 0x7efc, 0x00020064);
7928
7929         put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7930
7931         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7932         put_smstate(u16, buf, 0x7e90, seg.selector);
7933         put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7934         put_smstate(u32, buf, 0x7e94, seg.limit);
7935         put_smstate(u64, buf, 0x7e98, seg.base);
7936
7937         kvm_x86_ops.get_idt(vcpu, &dt);
7938         put_smstate(u32, buf, 0x7e84, dt.size);
7939         put_smstate(u64, buf, 0x7e88, dt.address);
7940
7941         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7942         put_smstate(u16, buf, 0x7e70, seg.selector);
7943         put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7944         put_smstate(u32, buf, 0x7e74, seg.limit);
7945         put_smstate(u64, buf, 0x7e78, seg.base);
7946
7947         kvm_x86_ops.get_gdt(vcpu, &dt);
7948         put_smstate(u32, buf, 0x7e64, dt.size);
7949         put_smstate(u64, buf, 0x7e68, dt.address);
7950
7951         for (i = 0; i < 6; i++)
7952                 enter_smm_save_seg_64(vcpu, buf, i);
7953 }
7954 #endif
7955
7956 static void enter_smm(struct kvm_vcpu *vcpu)
7957 {
7958         struct kvm_segment cs, ds;
7959         struct desc_ptr dt;
7960         char buf[512];
7961         u32 cr0;
7962
7963         trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7964         memset(buf, 0, 512);
7965 #ifdef CONFIG_X86_64
7966         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7967                 enter_smm_save_state_64(vcpu, buf);
7968         else
7969 #endif
7970                 enter_smm_save_state_32(vcpu, buf);
7971
7972         /*
7973          * Give pre_enter_smm() a chance to make ISA-specific changes to the
7974          * vCPU state (e.g. leave guest mode) after we've saved the state into
7975          * the SMM state-save area.
7976          */
7977         kvm_x86_ops.pre_enter_smm(vcpu, buf);
7978
7979         vcpu->arch.hflags |= HF_SMM_MASK;
7980         kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7981
7982         if (kvm_x86_ops.get_nmi_mask(vcpu))
7983                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7984         else
7985                 kvm_x86_ops.set_nmi_mask(vcpu, true);
7986
7987         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7988         kvm_rip_write(vcpu, 0x8000);
7989
7990         cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7991         kvm_x86_ops.set_cr0(vcpu, cr0);
7992         vcpu->arch.cr0 = cr0;
7993
7994         kvm_x86_ops.set_cr4(vcpu, 0);
7995
7996         /* Undocumented: IDT limit is set to zero on entry to SMM.  */
7997         dt.address = dt.size = 0;
7998         kvm_x86_ops.set_idt(vcpu, &dt);
7999
8000         __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
8001
8002         cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
8003         cs.base = vcpu->arch.smbase;
8004
8005         ds.selector = 0;
8006         ds.base = 0;
8007
8008         cs.limit    = ds.limit = 0xffffffff;
8009         cs.type     = ds.type = 0x3;
8010         cs.dpl      = ds.dpl = 0;
8011         cs.db       = ds.db = 0;
8012         cs.s        = ds.s = 1;
8013         cs.l        = ds.l = 0;
8014         cs.g        = ds.g = 1;
8015         cs.avl      = ds.avl = 0;
8016         cs.present  = ds.present = 1;
8017         cs.unusable = ds.unusable = 0;
8018         cs.padding  = ds.padding = 0;
8019
8020         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8021         kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8022         kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8023         kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8024         kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8025         kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8026
8027 #ifdef CONFIG_X86_64
8028         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8029                 kvm_x86_ops.set_efer(vcpu, 0);
8030 #endif
8031
8032         kvm_update_cpuid(vcpu);
8033         kvm_mmu_reset_context(vcpu);
8034 }
8035
8036 static void process_smi(struct kvm_vcpu *vcpu)
8037 {
8038         vcpu->arch.smi_pending = true;
8039         kvm_make_request(KVM_REQ_EVENT, vcpu);
8040 }
8041
8042 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8043                                        unsigned long *vcpu_bitmap)
8044 {
8045         cpumask_var_t cpus;
8046
8047         zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8048
8049         kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8050                                     NULL, vcpu_bitmap, cpus);
8051
8052         free_cpumask_var(cpus);
8053 }
8054
8055 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8056 {
8057         kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8058 }
8059
8060 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8061 {
8062         if (!lapic_in_kernel(vcpu))
8063                 return;
8064
8065         vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8066         kvm_apic_update_apicv(vcpu);
8067         kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu);
8068 }
8069 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8070
8071 /*
8072  * NOTE: Do not hold any lock prior to calling this.
8073  *
8074  * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8075  * locked, because it calls __x86_set_memory_region() which does
8076  * synchronize_srcu(&kvm->srcu).
8077  */
8078 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8079 {
8080         struct kvm_vcpu *except;
8081         unsigned long old, new, expected;
8082
8083         if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8084             !kvm_x86_ops.check_apicv_inhibit_reasons(bit))
8085                 return;
8086
8087         old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8088         do {
8089                 expected = new = old;
8090                 if (activate)
8091                         __clear_bit(bit, &new);
8092                 else
8093                         __set_bit(bit, &new);
8094                 if (new == old)
8095                         break;
8096                 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8097         } while (old != expected);
8098
8099         if (!!old == !!new)
8100                 return;
8101
8102         trace_kvm_apicv_update_request(activate, bit);
8103         if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8104                 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate);
8105
8106         /*
8107          * Sending request to update APICV for all other vcpus,
8108          * while update the calling vcpu immediately instead of
8109          * waiting for another #VMEXIT to handle the request.
8110          */
8111         except = kvm_get_running_vcpu();
8112         kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE,
8113                                          except);
8114         if (except)
8115                 kvm_vcpu_update_apicv(except);
8116 }
8117 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8118
8119 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8120 {
8121         if (!kvm_apic_present(vcpu))
8122                 return;
8123
8124         bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8125
8126         if (irqchip_split(vcpu->kvm))
8127                 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8128         else {
8129                 if (vcpu->arch.apicv_active)
8130                         kvm_x86_ops.sync_pir_to_irr(vcpu);
8131                 if (ioapic_in_kernel(vcpu->kvm))
8132                         kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8133         }
8134
8135         if (is_guest_mode(vcpu))
8136                 vcpu->arch.load_eoi_exitmap_pending = true;
8137         else
8138                 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8139 }
8140
8141 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8142 {
8143         u64 eoi_exit_bitmap[4];
8144
8145         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8146                 return;
8147
8148         bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8149                   vcpu_to_synic(vcpu)->vec_bitmap, 256);
8150         kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8151 }
8152
8153 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8154                 unsigned long start, unsigned long end,
8155                 bool blockable)
8156 {
8157         unsigned long apic_address;
8158
8159         /*
8160          * The physical address of apic access page is stored in the VMCS.
8161          * Update it when it becomes invalid.
8162          */
8163         apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8164         if (start <= apic_address && apic_address < end)
8165                 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8166
8167         return 0;
8168 }
8169
8170 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8171 {
8172         struct page *page = NULL;
8173
8174         if (!lapic_in_kernel(vcpu))
8175                 return;
8176
8177         if (!kvm_x86_ops.set_apic_access_page_addr)
8178                 return;
8179
8180         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8181         if (is_error_page(page))
8182                 return;
8183         kvm_x86_ops.set_apic_access_page_addr(vcpu, page_to_phys(page));
8184
8185         /*
8186          * Do not pin apic access page in memory, the MMU notifier
8187          * will call us again if it is migrated or swapped out.
8188          */
8189         put_page(page);
8190 }
8191
8192 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8193 {
8194         smp_send_reschedule(vcpu->cpu);
8195 }
8196 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8197
8198 /*
8199  * Returns 1 to let vcpu_run() continue the guest execution loop without
8200  * exiting to the userspace.  Otherwise, the value will be returned to the
8201  * userspace.
8202  */
8203 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8204 {
8205         int r;
8206         bool req_int_win =
8207                 dm_request_for_irq_injection(vcpu) &&
8208                 kvm_cpu_accept_dm_intr(vcpu);
8209         enum exit_fastpath_completion exit_fastpath = EXIT_FASTPATH_NONE;
8210
8211         bool req_immediate_exit = false;
8212
8213         if (kvm_request_pending(vcpu)) {
8214                 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) {
8215                         if (unlikely(!kvm_x86_ops.get_vmcs12_pages(vcpu))) {
8216                                 r = 0;
8217                                 goto out;
8218                         }
8219                 }
8220                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8221                         kvm_mmu_unload(vcpu);
8222                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8223                         __kvm_migrate_timers(vcpu);
8224                 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8225                         kvm_gen_update_masterclock(vcpu->kvm);
8226                 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8227                         kvm_gen_kvmclock_update(vcpu);
8228                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8229                         r = kvm_guest_time_update(vcpu);
8230                         if (unlikely(r))
8231                                 goto out;
8232                 }
8233                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8234                         kvm_mmu_sync_roots(vcpu);
8235                 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8236                         kvm_mmu_load_pgd(vcpu);
8237                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
8238                         kvm_vcpu_flush_tlb(vcpu, true);
8239                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8240                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8241                         r = 0;
8242                         goto out;
8243                 }
8244                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8245                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8246                         vcpu->mmio_needed = 0;
8247                         r = 0;
8248                         goto out;
8249                 }
8250                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8251                         /* Page is swapped out. Do synthetic halt */
8252                         vcpu->arch.apf.halted = true;
8253                         r = 1;
8254                         goto out;
8255                 }
8256                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8257                         record_steal_time(vcpu);
8258                 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8259                         process_smi(vcpu);
8260                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8261                         process_nmi(vcpu);
8262                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8263                         kvm_pmu_handle_event(vcpu);
8264                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8265                         kvm_pmu_deliver_pmi(vcpu);
8266                 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8267                         BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8268                         if (test_bit(vcpu->arch.pending_ioapic_eoi,
8269                                      vcpu->arch.ioapic_handled_vectors)) {
8270                                 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8271                                 vcpu->run->eoi.vector =
8272                                                 vcpu->arch.pending_ioapic_eoi;
8273                                 r = 0;
8274                                 goto out;
8275                         }
8276                 }
8277                 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8278                         vcpu_scan_ioapic(vcpu);
8279                 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8280                         vcpu_load_eoi_exitmap(vcpu);
8281                 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8282                         kvm_vcpu_reload_apic_access_page(vcpu);
8283                 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8284                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8285                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8286                         r = 0;
8287                         goto out;
8288                 }
8289                 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8290                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8291                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8292                         r = 0;
8293                         goto out;
8294                 }
8295                 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8296                         vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8297                         vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8298                         r = 0;
8299                         goto out;
8300                 }
8301
8302                 /*
8303                  * KVM_REQ_HV_STIMER has to be processed after
8304                  * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8305                  * depend on the guest clock being up-to-date
8306                  */
8307                 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8308                         kvm_hv_process_stimers(vcpu);
8309                 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8310                         kvm_vcpu_update_apicv(vcpu);
8311         }
8312
8313         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8314                 ++vcpu->stat.req_event;
8315                 kvm_apic_accept_events(vcpu);
8316                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8317                         r = 1;
8318                         goto out;
8319                 }
8320
8321                 if (inject_pending_event(vcpu) != 0)
8322                         req_immediate_exit = true;
8323                 else {
8324                         /* Enable SMI/NMI/IRQ window open exits if needed.
8325                          *
8326                          * SMIs have three cases:
8327                          * 1) They can be nested, and then there is nothing to
8328                          *    do here because RSM will cause a vmexit anyway.
8329                          * 2) There is an ISA-specific reason why SMI cannot be
8330                          *    injected, and the moment when this changes can be
8331                          *    intercepted.
8332                          * 3) Or the SMI can be pending because
8333                          *    inject_pending_event has completed the injection
8334                          *    of an IRQ or NMI from the previous vmexit, and
8335                          *    then we request an immediate exit to inject the
8336                          *    SMI.
8337                          */
8338                         if (vcpu->arch.smi_pending && !is_smm(vcpu))
8339                                 if (!kvm_x86_ops.enable_smi_window(vcpu))
8340                                         req_immediate_exit = true;
8341                         if (vcpu->arch.nmi_pending)
8342                                 kvm_x86_ops.enable_nmi_window(vcpu);
8343                         if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8344                                 kvm_x86_ops.enable_irq_window(vcpu);
8345                         WARN_ON(vcpu->arch.exception.pending);
8346                 }
8347
8348                 if (kvm_lapic_enabled(vcpu)) {
8349                         update_cr8_intercept(vcpu);
8350                         kvm_lapic_sync_to_vapic(vcpu);
8351                 }
8352         }
8353
8354         r = kvm_mmu_reload(vcpu);
8355         if (unlikely(r)) {
8356                 goto cancel_injection;
8357         }
8358
8359         preempt_disable();
8360
8361         kvm_x86_ops.prepare_guest_switch(vcpu);
8362
8363         /*
8364          * Disable IRQs before setting IN_GUEST_MODE.  Posted interrupt
8365          * IPI are then delayed after guest entry, which ensures that they
8366          * result in virtual interrupt delivery.
8367          */
8368         local_irq_disable();
8369         vcpu->mode = IN_GUEST_MODE;
8370
8371         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8372
8373         /*
8374          * 1) We should set ->mode before checking ->requests.  Please see
8375          * the comment in kvm_vcpu_exiting_guest_mode().
8376          *
8377          * 2) For APICv, we should set ->mode before checking PID.ON. This
8378          * pairs with the memory barrier implicit in pi_test_and_set_on
8379          * (see vmx_deliver_posted_interrupt).
8380          *
8381          * 3) This also orders the write to mode from any reads to the page
8382          * tables done while the VCPU is running.  Please see the comment
8383          * in kvm_flush_remote_tlbs.
8384          */
8385         smp_mb__after_srcu_read_unlock();
8386
8387         /*
8388          * This handles the case where a posted interrupt was
8389          * notified with kvm_vcpu_kick.
8390          */
8391         if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8392                 kvm_x86_ops.sync_pir_to_irr(vcpu);
8393
8394         if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
8395             || need_resched() || signal_pending(current)) {
8396                 vcpu->mode = OUTSIDE_GUEST_MODE;
8397                 smp_wmb();
8398                 local_irq_enable();
8399                 preempt_enable();
8400                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8401                 r = 1;
8402                 goto cancel_injection;
8403         }
8404
8405         if (req_immediate_exit) {
8406                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8407                 kvm_x86_ops.request_immediate_exit(vcpu);
8408         }
8409
8410         trace_kvm_entry(vcpu->vcpu_id);
8411         guest_enter_irqoff();
8412
8413         fpregs_assert_state_consistent();
8414         if (test_thread_flag(TIF_NEED_FPU_LOAD))
8415                 switch_fpu_return();
8416
8417         if (unlikely(vcpu->arch.switch_db_regs)) {
8418                 set_debugreg(0, 7);
8419                 set_debugreg(vcpu->arch.eff_db[0], 0);
8420                 set_debugreg(vcpu->arch.eff_db[1], 1);
8421                 set_debugreg(vcpu->arch.eff_db[2], 2);
8422                 set_debugreg(vcpu->arch.eff_db[3], 3);
8423                 set_debugreg(vcpu->arch.dr6, 6);
8424                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8425         }
8426
8427         kvm_x86_ops.run(vcpu);
8428
8429         /*
8430          * Do this here before restoring debug registers on the host.  And
8431          * since we do this before handling the vmexit, a DR access vmexit
8432          * can (a) read the correct value of the debug registers, (b) set
8433          * KVM_DEBUGREG_WONT_EXIT again.
8434          */
8435         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8436                 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8437                 kvm_x86_ops.sync_dirty_debug_regs(vcpu);
8438                 kvm_update_dr0123(vcpu);
8439                 kvm_update_dr7(vcpu);
8440                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8441         }
8442
8443         /*
8444          * If the guest has used debug registers, at least dr7
8445          * will be disabled while returning to the host.
8446          * If we don't have active breakpoints in the host, we don't
8447          * care about the messed up debug address registers. But if
8448          * we have some of them active, restore the old state.
8449          */
8450         if (hw_breakpoint_active())
8451                 hw_breakpoint_restore();
8452
8453         vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8454
8455         vcpu->mode = OUTSIDE_GUEST_MODE;
8456         smp_wmb();
8457
8458         kvm_x86_ops.handle_exit_irqoff(vcpu, &exit_fastpath);
8459
8460         /*
8461          * Consume any pending interrupts, including the possible source of
8462          * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8463          * An instruction is required after local_irq_enable() to fully unblock
8464          * interrupts on processors that implement an interrupt shadow, the
8465          * stat.exits increment will do nicely.
8466          */
8467         kvm_before_interrupt(vcpu);
8468         local_irq_enable();
8469         ++vcpu->stat.exits;
8470         local_irq_disable();
8471         kvm_after_interrupt(vcpu);
8472
8473         guest_exit_irqoff();
8474         if (lapic_in_kernel(vcpu)) {
8475                 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8476                 if (delta != S64_MIN) {
8477                         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8478                         vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8479                 }
8480         }
8481
8482         local_irq_enable();
8483         preempt_enable();
8484
8485         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8486
8487         /*
8488          * Profile KVM exit RIPs:
8489          */
8490         if (unlikely(prof_on == KVM_PROFILING)) {
8491                 unsigned long rip = kvm_rip_read(vcpu);
8492                 profile_hit(KVM_PROFILING, (void *)rip);
8493         }
8494
8495         if (unlikely(vcpu->arch.tsc_always_catchup))
8496                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8497
8498         if (vcpu->arch.apic_attention)
8499                 kvm_lapic_sync_from_vapic(vcpu);
8500
8501         r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath);
8502         return r;
8503
8504 cancel_injection:
8505         kvm_x86_ops.cancel_injection(vcpu);
8506         if (unlikely(vcpu->arch.apic_attention))
8507                 kvm_lapic_sync_from_vapic(vcpu);
8508 out:
8509         return r;
8510 }
8511
8512 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8513 {
8514         if (!kvm_arch_vcpu_runnable(vcpu) &&
8515             (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) {
8516                 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8517                 kvm_vcpu_block(vcpu);
8518                 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8519
8520                 if (kvm_x86_ops.post_block)
8521                         kvm_x86_ops.post_block(vcpu);
8522
8523                 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8524                         return 1;
8525         }
8526
8527         kvm_apic_accept_events(vcpu);
8528         switch(vcpu->arch.mp_state) {
8529         case KVM_MP_STATE_HALTED:
8530                 vcpu->arch.pv.pv_unhalted = false;
8531                 vcpu->arch.mp_state =
8532                         KVM_MP_STATE_RUNNABLE;
8533                 /* fall through */
8534         case KVM_MP_STATE_RUNNABLE:
8535                 vcpu->arch.apf.halted = false;
8536                 break;
8537         case KVM_MP_STATE_INIT_RECEIVED:
8538                 break;
8539         default:
8540                 return -EINTR;
8541         }
8542         return 1;
8543 }
8544
8545 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8546 {
8547         if (is_guest_mode(vcpu) && kvm_x86_ops.check_nested_events)
8548                 kvm_x86_ops.check_nested_events(vcpu);
8549
8550         return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8551                 !vcpu->arch.apf.halted);
8552 }
8553
8554 static int vcpu_run(struct kvm_vcpu *vcpu)
8555 {
8556         int r;
8557         struct kvm *kvm = vcpu->kvm;
8558
8559         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8560         vcpu->arch.l1tf_flush_l1d = true;
8561
8562         for (;;) {
8563                 if (kvm_vcpu_running(vcpu)) {
8564                         r = vcpu_enter_guest(vcpu);
8565                 } else {
8566                         r = vcpu_block(kvm, vcpu);
8567                 }
8568
8569                 if (r <= 0)
8570                         break;
8571
8572                 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8573                 if (kvm_cpu_has_pending_timer(vcpu))
8574                         kvm_inject_pending_timer_irqs(vcpu);
8575
8576                 if (dm_request_for_irq_injection(vcpu) &&
8577                         kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8578                         r = 0;
8579                         vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8580                         ++vcpu->stat.request_irq_exits;
8581                         break;
8582                 }
8583
8584                 kvm_check_async_pf_completion(vcpu);
8585
8586                 if (signal_pending(current)) {
8587                         r = -EINTR;
8588                         vcpu->run->exit_reason = KVM_EXIT_INTR;
8589                         ++vcpu->stat.signal_exits;
8590                         break;
8591                 }
8592                 if (need_resched()) {
8593                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8594                         cond_resched();
8595                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8596                 }
8597         }
8598
8599         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8600
8601         return r;
8602 }
8603
8604 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8605 {
8606         int r;
8607
8608         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8609         r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8610         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8611         return r;
8612 }
8613
8614 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8615 {
8616         BUG_ON(!vcpu->arch.pio.count);
8617
8618         return complete_emulated_io(vcpu);
8619 }
8620
8621 /*
8622  * Implements the following, as a state machine:
8623  *
8624  * read:
8625  *   for each fragment
8626  *     for each mmio piece in the fragment
8627  *       write gpa, len
8628  *       exit
8629  *       copy data
8630  *   execute insn
8631  *
8632  * write:
8633  *   for each fragment
8634  *     for each mmio piece in the fragment
8635  *       write gpa, len
8636  *       copy data
8637  *       exit
8638  */
8639 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8640 {
8641         struct kvm_run *run = vcpu->run;
8642         struct kvm_mmio_fragment *frag;
8643         unsigned len;
8644
8645         BUG_ON(!vcpu->mmio_needed);
8646
8647         /* Complete previous fragment */
8648         frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8649         len = min(8u, frag->len);
8650         if (!vcpu->mmio_is_write)
8651                 memcpy(frag->data, run->mmio.data, len);
8652
8653         if (frag->len <= 8) {
8654                 /* Switch to the next fragment. */
8655                 frag++;
8656                 vcpu->mmio_cur_fragment++;
8657         } else {
8658                 /* Go forward to the next mmio piece. */
8659                 frag->data += len;
8660                 frag->gpa += len;
8661                 frag->len -= len;
8662         }
8663
8664         if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8665                 vcpu->mmio_needed = 0;
8666
8667                 /* FIXME: return into emulator if single-stepping.  */
8668                 if (vcpu->mmio_is_write)
8669                         return 1;
8670                 vcpu->mmio_read_completed = 1;
8671                 return complete_emulated_io(vcpu);
8672         }
8673
8674         run->exit_reason = KVM_EXIT_MMIO;
8675         run->mmio.phys_addr = frag->gpa;
8676         if (vcpu->mmio_is_write)
8677                 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8678         run->mmio.len = min(8u, frag->len);
8679         run->mmio.is_write = vcpu->mmio_is_write;
8680         vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8681         return 0;
8682 }
8683
8684 static void kvm_save_current_fpu(struct fpu *fpu)
8685 {
8686         /*
8687          * If the target FPU state is not resident in the CPU registers, just
8688          * memcpy() from current, else save CPU state directly to the target.
8689          */
8690         if (test_thread_flag(TIF_NEED_FPU_LOAD))
8691                 memcpy(&fpu->state, &current->thread.fpu.state,
8692                        fpu_kernel_xstate_size);
8693         else
8694                 copy_fpregs_to_fpstate(fpu);
8695 }
8696
8697 /* Swap (qemu) user FPU context for the guest FPU context. */
8698 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8699 {
8700         fpregs_lock();
8701
8702         kvm_save_current_fpu(vcpu->arch.user_fpu);
8703
8704         /* PKRU is separately restored in kvm_x86_ops.run.  */
8705         __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8706                                 ~XFEATURE_MASK_PKRU);
8707
8708         fpregs_mark_activate();
8709         fpregs_unlock();
8710
8711         trace_kvm_fpu(1);
8712 }
8713
8714 /* When vcpu_run ends, restore user space FPU context. */
8715 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8716 {
8717         fpregs_lock();
8718
8719         kvm_save_current_fpu(vcpu->arch.guest_fpu);
8720
8721         copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8722
8723         fpregs_mark_activate();
8724         fpregs_unlock();
8725
8726         ++vcpu->stat.fpu_reload;
8727         trace_kvm_fpu(0);
8728 }
8729
8730 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8731 {
8732         int r;
8733
8734         vcpu_load(vcpu);
8735         kvm_sigset_activate(vcpu);
8736         kvm_load_guest_fpu(vcpu);
8737
8738         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8739                 if (kvm_run->immediate_exit) {
8740                         r = -EINTR;
8741                         goto out;
8742                 }
8743                 kvm_vcpu_block(vcpu);
8744                 kvm_apic_accept_events(vcpu);
8745                 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8746                 r = -EAGAIN;
8747                 if (signal_pending(current)) {
8748                         r = -EINTR;
8749                         vcpu->run->exit_reason = KVM_EXIT_INTR;
8750                         ++vcpu->stat.signal_exits;
8751                 }
8752                 goto out;
8753         }
8754
8755         if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8756                 r = -EINVAL;
8757                 goto out;
8758         }
8759
8760         if (vcpu->run->kvm_dirty_regs) {
8761                 r = sync_regs(vcpu);
8762                 if (r != 0)
8763                         goto out;
8764         }
8765
8766         /* re-sync apic's tpr */
8767         if (!lapic_in_kernel(vcpu)) {
8768                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8769                         r = -EINVAL;
8770                         goto out;
8771                 }
8772         }
8773
8774         if (unlikely(vcpu->arch.complete_userspace_io)) {
8775                 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8776                 vcpu->arch.complete_userspace_io = NULL;
8777                 r = cui(vcpu);
8778                 if (r <= 0)
8779                         goto out;
8780         } else
8781                 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8782
8783         if (kvm_run->immediate_exit)
8784                 r = -EINTR;
8785         else
8786                 r = vcpu_run(vcpu);
8787
8788 out:
8789         kvm_put_guest_fpu(vcpu);
8790         if (vcpu->run->kvm_valid_regs)
8791                 store_regs(vcpu);
8792         post_kvm_run_save(vcpu);
8793         kvm_sigset_deactivate(vcpu);
8794
8795         vcpu_put(vcpu);
8796         return r;
8797 }
8798
8799 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8800 {
8801         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8802                 /*
8803                  * We are here if userspace calls get_regs() in the middle of
8804                  * instruction emulation. Registers state needs to be copied
8805                  * back from emulation context to vcpu. Userspace shouldn't do
8806                  * that usually, but some bad designed PV devices (vmware
8807                  * backdoor interface) need this to work
8808                  */
8809                 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
8810                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8811         }
8812         regs->rax = kvm_rax_read(vcpu);
8813         regs->rbx = kvm_rbx_read(vcpu);
8814         regs->rcx = kvm_rcx_read(vcpu);
8815         regs->rdx = kvm_rdx_read(vcpu);
8816         regs->rsi = kvm_rsi_read(vcpu);
8817         regs->rdi = kvm_rdi_read(vcpu);
8818         regs->rsp = kvm_rsp_read(vcpu);
8819         regs->rbp = kvm_rbp_read(vcpu);
8820 #ifdef CONFIG_X86_64
8821         regs->r8 = kvm_r8_read(vcpu);
8822         regs->r9 = kvm_r9_read(vcpu);
8823         regs->r10 = kvm_r10_read(vcpu);
8824         regs->r11 = kvm_r11_read(vcpu);
8825         regs->r12 = kvm_r12_read(vcpu);
8826         regs->r13 = kvm_r13_read(vcpu);
8827         regs->r14 = kvm_r14_read(vcpu);
8828         regs->r15 = kvm_r15_read(vcpu);
8829 #endif
8830
8831         regs->rip = kvm_rip_read(vcpu);
8832         regs->rflags = kvm_get_rflags(vcpu);
8833 }
8834
8835 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8836 {
8837         vcpu_load(vcpu);
8838         __get_regs(vcpu, regs);
8839         vcpu_put(vcpu);
8840         return 0;
8841 }
8842
8843 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8844 {
8845         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8846         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8847
8848         kvm_rax_write(vcpu, regs->rax);
8849         kvm_rbx_write(vcpu, regs->rbx);
8850         kvm_rcx_write(vcpu, regs->rcx);
8851         kvm_rdx_write(vcpu, regs->rdx);
8852         kvm_rsi_write(vcpu, regs->rsi);
8853         kvm_rdi_write(vcpu, regs->rdi);
8854         kvm_rsp_write(vcpu, regs->rsp);
8855         kvm_rbp_write(vcpu, regs->rbp);
8856 #ifdef CONFIG_X86_64
8857         kvm_r8_write(vcpu, regs->r8);
8858         kvm_r9_write(vcpu, regs->r9);
8859         kvm_r10_write(vcpu, regs->r10);
8860         kvm_r11_write(vcpu, regs->r11);
8861         kvm_r12_write(vcpu, regs->r12);
8862         kvm_r13_write(vcpu, regs->r13);
8863         kvm_r14_write(vcpu, regs->r14);
8864         kvm_r15_write(vcpu, regs->r15);
8865 #endif
8866
8867         kvm_rip_write(vcpu, regs->rip);
8868         kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8869
8870         vcpu->arch.exception.pending = false;
8871
8872         kvm_make_request(KVM_REQ_EVENT, vcpu);
8873 }
8874
8875 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8876 {
8877         vcpu_load(vcpu);
8878         __set_regs(vcpu, regs);
8879         vcpu_put(vcpu);
8880         return 0;
8881 }
8882
8883 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8884 {
8885         struct kvm_segment cs;
8886
8887         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8888         *db = cs.db;
8889         *l = cs.l;
8890 }
8891 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8892
8893 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8894 {
8895         struct desc_ptr dt;
8896
8897         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8898         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8899         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8900         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8901         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8902         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8903
8904         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8905         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8906
8907         kvm_x86_ops.get_idt(vcpu, &dt);
8908         sregs->idt.limit = dt.size;
8909         sregs->idt.base = dt.address;
8910         kvm_x86_ops.get_gdt(vcpu, &dt);
8911         sregs->gdt.limit = dt.size;
8912         sregs->gdt.base = dt.address;
8913
8914         sregs->cr0 = kvm_read_cr0(vcpu);
8915         sregs->cr2 = vcpu->arch.cr2;
8916         sregs->cr3 = kvm_read_cr3(vcpu);
8917         sregs->cr4 = kvm_read_cr4(vcpu);
8918         sregs->cr8 = kvm_get_cr8(vcpu);
8919         sregs->efer = vcpu->arch.efer;
8920         sregs->apic_base = kvm_get_apic_base(vcpu);
8921
8922         memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8923
8924         if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8925                 set_bit(vcpu->arch.interrupt.nr,
8926                         (unsigned long *)sregs->interrupt_bitmap);
8927 }
8928
8929 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8930                                   struct kvm_sregs *sregs)
8931 {
8932         vcpu_load(vcpu);
8933         __get_sregs(vcpu, sregs);
8934         vcpu_put(vcpu);
8935         return 0;
8936 }
8937
8938 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8939                                     struct kvm_mp_state *mp_state)
8940 {
8941         vcpu_load(vcpu);
8942         if (kvm_mpx_supported())
8943                 kvm_load_guest_fpu(vcpu);
8944
8945         kvm_apic_accept_events(vcpu);
8946         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8947                                         vcpu->arch.pv.pv_unhalted)
8948                 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8949         else
8950                 mp_state->mp_state = vcpu->arch.mp_state;
8951
8952         if (kvm_mpx_supported())
8953                 kvm_put_guest_fpu(vcpu);
8954         vcpu_put(vcpu);
8955         return 0;
8956 }
8957
8958 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8959                                     struct kvm_mp_state *mp_state)
8960 {
8961         int ret = -EINVAL;
8962
8963         vcpu_load(vcpu);
8964
8965         if (!lapic_in_kernel(vcpu) &&
8966             mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8967                 goto out;
8968
8969         /*
8970          * KVM_MP_STATE_INIT_RECEIVED means the processor is in
8971          * INIT state; latched init should be reported using
8972          * KVM_SET_VCPU_EVENTS, so reject it here.
8973          */
8974         if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
8975             (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8976              mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8977                 goto out;
8978
8979         if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8980                 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8981                 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8982         } else
8983                 vcpu->arch.mp_state = mp_state->mp_state;
8984         kvm_make_request(KVM_REQ_EVENT, vcpu);
8985
8986         ret = 0;
8987 out:
8988         vcpu_put(vcpu);
8989         return ret;
8990 }
8991
8992 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8993                     int reason, bool has_error_code, u32 error_code)
8994 {
8995         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8996         int ret;
8997
8998         init_emulate_ctxt(vcpu);
8999
9000         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9001                                    has_error_code, error_code);
9002         if (ret) {
9003                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9004                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
9005                 vcpu->run->internal.ndata = 0;
9006                 return 0;
9007         }
9008
9009         kvm_rip_write(vcpu, ctxt->eip);
9010         kvm_set_rflags(vcpu, ctxt->eflags);
9011         return 1;
9012 }
9013 EXPORT_SYMBOL_GPL(kvm_task_switch);
9014
9015 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9016 {
9017         if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
9018                 /*
9019                  * When EFER.LME and CR0.PG are set, the processor is in
9020                  * 64-bit mode (though maybe in a 32-bit code segment).
9021                  * CR4.PAE and EFER.LMA must be set.
9022                  */
9023                 if (!(sregs->cr4 & X86_CR4_PAE)
9024                     || !(sregs->efer & EFER_LMA))
9025                         return -EINVAL;
9026         } else {
9027                 /*
9028                  * Not in 64-bit mode: EFER.LMA is clear and the code
9029                  * segment cannot be 64-bit.
9030                  */
9031                 if (sregs->efer & EFER_LMA || sregs->cs.l)
9032                         return -EINVAL;
9033         }
9034
9035         return kvm_valid_cr4(vcpu, sregs->cr4);
9036 }
9037
9038 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9039 {
9040         struct msr_data apic_base_msr;
9041         int mmu_reset_needed = 0;
9042         int cpuid_update_needed = 0;
9043         int pending_vec, max_bits, idx;
9044         struct desc_ptr dt;
9045         int ret = -EINVAL;
9046
9047         if (kvm_valid_sregs(vcpu, sregs))
9048                 goto out;
9049
9050         apic_base_msr.data = sregs->apic_base;
9051         apic_base_msr.host_initiated = true;
9052         if (kvm_set_apic_base(vcpu, &apic_base_msr))
9053                 goto out;
9054
9055         dt.size = sregs->idt.limit;
9056         dt.address = sregs->idt.base;
9057         kvm_x86_ops.set_idt(vcpu, &dt);
9058         dt.size = sregs->gdt.limit;
9059         dt.address = sregs->gdt.base;
9060         kvm_x86_ops.set_gdt(vcpu, &dt);
9061
9062         vcpu->arch.cr2 = sregs->cr2;
9063         mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9064         vcpu->arch.cr3 = sregs->cr3;
9065         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9066
9067         kvm_set_cr8(vcpu, sregs->cr8);
9068
9069         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9070         kvm_x86_ops.set_efer(vcpu, sregs->efer);
9071
9072         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9073         kvm_x86_ops.set_cr0(vcpu, sregs->cr0);
9074         vcpu->arch.cr0 = sregs->cr0;
9075
9076         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9077         cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
9078                                 (X86_CR4_OSXSAVE | X86_CR4_PKE));
9079         kvm_x86_ops.set_cr4(vcpu, sregs->cr4);
9080         if (cpuid_update_needed)
9081                 kvm_update_cpuid(vcpu);
9082
9083         idx = srcu_read_lock(&vcpu->kvm->srcu);
9084         if (is_pae_paging(vcpu)) {
9085                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9086                 mmu_reset_needed = 1;
9087         }
9088         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9089
9090         if (mmu_reset_needed)
9091                 kvm_mmu_reset_context(vcpu);
9092
9093         max_bits = KVM_NR_INTERRUPTS;
9094         pending_vec = find_first_bit(
9095                 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9096         if (pending_vec < max_bits) {
9097                 kvm_queue_interrupt(vcpu, pending_vec, false);
9098                 pr_debug("Set back pending irq %d\n", pending_vec);
9099         }
9100
9101         kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9102         kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9103         kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9104         kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9105         kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9106         kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9107
9108         kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9109         kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9110
9111         update_cr8_intercept(vcpu);
9112
9113         /* Older userspace won't unhalt the vcpu on reset. */
9114         if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9115             sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9116             !is_protmode(vcpu))
9117                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9118
9119         kvm_make_request(KVM_REQ_EVENT, vcpu);
9120
9121         ret = 0;
9122 out:
9123         return ret;
9124 }
9125
9126 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9127                                   struct kvm_sregs *sregs)
9128 {
9129         int ret;
9130
9131         vcpu_load(vcpu);
9132         ret = __set_sregs(vcpu, sregs);
9133         vcpu_put(vcpu);
9134         return ret;
9135 }
9136
9137 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9138                                         struct kvm_guest_debug *dbg)
9139 {
9140         unsigned long rflags;
9141         int i, r;
9142
9143         vcpu_load(vcpu);
9144
9145         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9146                 r = -EBUSY;
9147                 if (vcpu->arch.exception.pending)
9148                         goto out;
9149                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9150                         kvm_queue_exception(vcpu, DB_VECTOR);
9151                 else
9152                         kvm_queue_exception(vcpu, BP_VECTOR);
9153         }
9154
9155         /*
9156          * Read rflags as long as potentially injected trace flags are still
9157          * filtered out.
9158          */
9159         rflags = kvm_get_rflags(vcpu);
9160
9161         vcpu->guest_debug = dbg->control;
9162         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9163                 vcpu->guest_debug = 0;
9164
9165         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9166                 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9167                         vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9168                 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9169         } else {
9170                 for (i = 0; i < KVM_NR_DB_REGS; i++)
9171                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9172         }
9173         kvm_update_dr7(vcpu);
9174
9175         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9176                 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9177                         get_segment_base(vcpu, VCPU_SREG_CS);
9178
9179         /*
9180          * Trigger an rflags update that will inject or remove the trace
9181          * flags.
9182          */
9183         kvm_set_rflags(vcpu, rflags);
9184
9185         kvm_x86_ops.update_bp_intercept(vcpu);
9186
9187         r = 0;
9188
9189 out:
9190         vcpu_put(vcpu);
9191         return r;
9192 }
9193
9194 /*
9195  * Translate a guest virtual address to a guest physical address.
9196  */
9197 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9198                                     struct kvm_translation *tr)
9199 {
9200         unsigned long vaddr = tr->linear_address;
9201         gpa_t gpa;
9202         int idx;
9203
9204         vcpu_load(vcpu);
9205
9206         idx = srcu_read_lock(&vcpu->kvm->srcu);
9207         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9208         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9209         tr->physical_address = gpa;
9210         tr->valid = gpa != UNMAPPED_GVA;
9211         tr->writeable = 1;
9212         tr->usermode = 0;
9213
9214         vcpu_put(vcpu);
9215         return 0;
9216 }
9217
9218 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9219 {
9220         struct fxregs_state *fxsave;
9221
9222         vcpu_load(vcpu);
9223
9224         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9225         memcpy(fpu->fpr, fxsave->st_space, 128);
9226         fpu->fcw = fxsave->cwd;
9227         fpu->fsw = fxsave->swd;
9228         fpu->ftwx = fxsave->twd;
9229         fpu->last_opcode = fxsave->fop;
9230         fpu->last_ip = fxsave->rip;
9231         fpu->last_dp = fxsave->rdp;
9232         memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9233
9234         vcpu_put(vcpu);
9235         return 0;
9236 }
9237
9238 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9239 {
9240         struct fxregs_state *fxsave;
9241
9242         vcpu_load(vcpu);
9243
9244         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9245
9246         memcpy(fxsave->st_space, fpu->fpr, 128);
9247         fxsave->cwd = fpu->fcw;
9248         fxsave->swd = fpu->fsw;
9249         fxsave->twd = fpu->ftwx;
9250         fxsave->fop = fpu->last_opcode;
9251         fxsave->rip = fpu->last_ip;
9252         fxsave->rdp = fpu->last_dp;
9253         memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9254
9255         vcpu_put(vcpu);
9256         return 0;
9257 }
9258
9259 static void store_regs(struct kvm_vcpu *vcpu)
9260 {
9261         BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9262
9263         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9264                 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9265
9266         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9267                 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9268
9269         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9270                 kvm_vcpu_ioctl_x86_get_vcpu_events(
9271                                 vcpu, &vcpu->run->s.regs.events);
9272 }
9273
9274 static int sync_regs(struct kvm_vcpu *vcpu)
9275 {
9276         if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9277                 return -EINVAL;
9278
9279         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9280                 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9281                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9282         }
9283         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9284                 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9285                         return -EINVAL;
9286                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9287         }
9288         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9289                 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9290                                 vcpu, &vcpu->run->s.regs.events))
9291                         return -EINVAL;
9292                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9293         }
9294
9295         return 0;
9296 }
9297
9298 static void fx_init(struct kvm_vcpu *vcpu)
9299 {
9300         fpstate_init(&vcpu->arch.guest_fpu->state);
9301         if (boot_cpu_has(X86_FEATURE_XSAVES))
9302                 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9303                         host_xcr0 | XSTATE_COMPACTION_ENABLED;
9304
9305         /*
9306          * Ensure guest xcr0 is valid for loading
9307          */
9308         vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9309
9310         vcpu->arch.cr0 |= X86_CR0_ET;
9311 }
9312
9313 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9314 {
9315         if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9316                 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9317                              "guest TSC will not be reliable\n");
9318
9319         return 0;
9320 }
9321
9322 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9323 {
9324         struct page *page;
9325         int r;
9326
9327         if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9328                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9329         else
9330                 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9331
9332         kvm_set_tsc_khz(vcpu, max_tsc_khz);
9333
9334         r = kvm_mmu_create(vcpu);
9335         if (r < 0)
9336                 return r;
9337
9338         if (irqchip_in_kernel(vcpu->kvm)) {
9339                 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9340                 if (r < 0)
9341                         goto fail_mmu_destroy;
9342                 if (kvm_apicv_activated(vcpu->kvm))
9343                         vcpu->arch.apicv_active = true;
9344         } else
9345                 static_key_slow_inc(&kvm_no_apic_vcpu);
9346
9347         r = -ENOMEM;
9348
9349         page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9350         if (!page)
9351                 goto fail_free_lapic;
9352         vcpu->arch.pio_data = page_address(page);
9353
9354         vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9355                                        GFP_KERNEL_ACCOUNT);
9356         if (!vcpu->arch.mce_banks)
9357                 goto fail_free_pio_data;
9358         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9359
9360         if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9361                                 GFP_KERNEL_ACCOUNT))
9362                 goto fail_free_mce_banks;
9363
9364         if (!alloc_emulate_ctxt(vcpu))
9365                 goto free_wbinvd_dirty_mask;
9366
9367         vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9368                                                 GFP_KERNEL_ACCOUNT);
9369         if (!vcpu->arch.user_fpu) {
9370                 pr_err("kvm: failed to allocate userspace's fpu\n");
9371                 goto free_emulate_ctxt;
9372         }
9373
9374         vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9375                                                  GFP_KERNEL_ACCOUNT);
9376         if (!vcpu->arch.guest_fpu) {
9377                 pr_err("kvm: failed to allocate vcpu's fpu\n");
9378                 goto free_user_fpu;
9379         }
9380         fx_init(vcpu);
9381
9382         vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9383
9384         vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9385
9386         vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9387
9388         kvm_async_pf_hash_reset(vcpu);
9389         kvm_pmu_init(vcpu);
9390
9391         vcpu->arch.pending_external_vector = -1;
9392         vcpu->arch.preempted_in_kernel = false;
9393
9394         kvm_hv_vcpu_init(vcpu);
9395
9396         r = kvm_x86_ops.vcpu_create(vcpu);
9397         if (r)
9398                 goto free_guest_fpu;
9399
9400         vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9401         vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9402         kvm_vcpu_mtrr_init(vcpu);
9403         vcpu_load(vcpu);
9404         kvm_vcpu_reset(vcpu, false);
9405         kvm_init_mmu(vcpu, false);
9406         vcpu_put(vcpu);
9407         return 0;
9408
9409 free_guest_fpu:
9410         kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9411 free_user_fpu:
9412         kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9413 free_emulate_ctxt:
9414         kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9415 free_wbinvd_dirty_mask:
9416         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9417 fail_free_mce_banks:
9418         kfree(vcpu->arch.mce_banks);
9419 fail_free_pio_data:
9420         free_page((unsigned long)vcpu->arch.pio_data);
9421 fail_free_lapic:
9422         kvm_free_lapic(vcpu);
9423 fail_mmu_destroy:
9424         kvm_mmu_destroy(vcpu);
9425         return r;
9426 }
9427
9428 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9429 {
9430         struct msr_data msr;
9431         struct kvm *kvm = vcpu->kvm;
9432
9433         kvm_hv_vcpu_postcreate(vcpu);
9434
9435         if (mutex_lock_killable(&vcpu->mutex))
9436                 return;
9437         vcpu_load(vcpu);
9438         msr.data = 0x0;
9439         msr.index = MSR_IA32_TSC;
9440         msr.host_initiated = true;
9441         kvm_write_tsc(vcpu, &msr);
9442         vcpu_put(vcpu);
9443
9444         /* poll control enabled by default */
9445         vcpu->arch.msr_kvm_poll_control = 1;
9446
9447         mutex_unlock(&vcpu->mutex);
9448
9449         if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
9450                 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9451                                                 KVMCLOCK_SYNC_PERIOD);
9452 }
9453
9454 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9455 {
9456         struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9457         int idx;
9458
9459         kvm_release_pfn(cache->pfn, cache->dirty, cache);
9460
9461         kvmclock_reset(vcpu);
9462
9463         kvm_x86_ops.vcpu_free(vcpu);
9464
9465         kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9466         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9467         kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9468         kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9469
9470         kvm_hv_vcpu_uninit(vcpu);
9471         kvm_pmu_destroy(vcpu);
9472         kfree(vcpu->arch.mce_banks);
9473         kvm_free_lapic(vcpu);
9474         idx = srcu_read_lock(&vcpu->kvm->srcu);
9475         kvm_mmu_destroy(vcpu);
9476         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9477         free_page((unsigned long)vcpu->arch.pio_data);
9478         if (!lapic_in_kernel(vcpu))
9479                 static_key_slow_dec(&kvm_no_apic_vcpu);
9480 }
9481
9482 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9483 {
9484         kvm_lapic_reset(vcpu, init_event);
9485
9486         vcpu->arch.hflags = 0;
9487
9488         vcpu->arch.smi_pending = 0;
9489         vcpu->arch.smi_count = 0;
9490         atomic_set(&vcpu->arch.nmi_queued, 0);
9491         vcpu->arch.nmi_pending = 0;
9492         vcpu->arch.nmi_injected = false;
9493         kvm_clear_interrupt_queue(vcpu);
9494         kvm_clear_exception_queue(vcpu);
9495
9496         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9497         kvm_update_dr0123(vcpu);
9498         vcpu->arch.dr6 = DR6_INIT;
9499         vcpu->arch.dr7 = DR7_FIXED_1;
9500         kvm_update_dr7(vcpu);
9501
9502         vcpu->arch.cr2 = 0;
9503
9504         kvm_make_request(KVM_REQ_EVENT, vcpu);
9505         vcpu->arch.apf.msr_val = 0;
9506         vcpu->arch.st.msr_val = 0;
9507
9508         kvmclock_reset(vcpu);
9509
9510         kvm_clear_async_pf_completion_queue(vcpu);
9511         kvm_async_pf_hash_reset(vcpu);
9512         vcpu->arch.apf.halted = false;
9513
9514         if (kvm_mpx_supported()) {
9515                 void *mpx_state_buffer;
9516
9517                 /*
9518                  * To avoid have the INIT path from kvm_apic_has_events() that be
9519                  * called with loaded FPU and does not let userspace fix the state.
9520                  */
9521                 if (init_event)
9522                         kvm_put_guest_fpu(vcpu);
9523                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9524                                         XFEATURE_BNDREGS);
9525                 if (mpx_state_buffer)
9526                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9527                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9528                                         XFEATURE_BNDCSR);
9529                 if (mpx_state_buffer)
9530                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9531                 if (init_event)
9532                         kvm_load_guest_fpu(vcpu);
9533         }
9534
9535         if (!init_event) {
9536                 kvm_pmu_reset(vcpu);
9537                 vcpu->arch.smbase = 0x30000;
9538
9539                 vcpu->arch.msr_misc_features_enables = 0;
9540
9541                 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9542         }
9543
9544         memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9545         vcpu->arch.regs_avail = ~0;
9546         vcpu->arch.regs_dirty = ~0;
9547
9548         vcpu->arch.ia32_xss = 0;
9549
9550         kvm_x86_ops.vcpu_reset(vcpu, init_event);
9551 }
9552
9553 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9554 {
9555         struct kvm_segment cs;
9556
9557         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9558         cs.selector = vector << 8;
9559         cs.base = vector << 12;
9560         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9561         kvm_rip_write(vcpu, 0);
9562 }
9563
9564 int kvm_arch_hardware_enable(void)
9565 {
9566         struct kvm *kvm;
9567         struct kvm_vcpu *vcpu;
9568         int i;
9569         int ret;
9570         u64 local_tsc;
9571         u64 max_tsc = 0;
9572         bool stable, backwards_tsc = false;
9573
9574         kvm_shared_msr_cpu_online();
9575         ret = kvm_x86_ops.hardware_enable();
9576         if (ret != 0)
9577                 return ret;
9578
9579         local_tsc = rdtsc();
9580         stable = !kvm_check_tsc_unstable();
9581         list_for_each_entry(kvm, &vm_list, vm_list) {
9582                 kvm_for_each_vcpu(i, vcpu, kvm) {
9583                         if (!stable && vcpu->cpu == smp_processor_id())
9584                                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9585                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9586                                 backwards_tsc = true;
9587                                 if (vcpu->arch.last_host_tsc > max_tsc)
9588                                         max_tsc = vcpu->arch.last_host_tsc;
9589                         }
9590                 }
9591         }
9592
9593         /*
9594          * Sometimes, even reliable TSCs go backwards.  This happens on
9595          * platforms that reset TSC during suspend or hibernate actions, but
9596          * maintain synchronization.  We must compensate.  Fortunately, we can
9597          * detect that condition here, which happens early in CPU bringup,
9598          * before any KVM threads can be running.  Unfortunately, we can't
9599          * bring the TSCs fully up to date with real time, as we aren't yet far
9600          * enough into CPU bringup that we know how much real time has actually
9601          * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9602          * variables that haven't been updated yet.
9603          *
9604          * So we simply find the maximum observed TSC above, then record the
9605          * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
9606          * the adjustment will be applied.  Note that we accumulate
9607          * adjustments, in case multiple suspend cycles happen before some VCPU
9608          * gets a chance to run again.  In the event that no KVM threads get a
9609          * chance to run, we will miss the entire elapsed period, as we'll have
9610          * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9611          * loose cycle time.  This isn't too big a deal, since the loss will be
9612          * uniform across all VCPUs (not to mention the scenario is extremely
9613          * unlikely). It is possible that a second hibernate recovery happens
9614          * much faster than a first, causing the observed TSC here to be
9615          * smaller; this would require additional padding adjustment, which is
9616          * why we set last_host_tsc to the local tsc observed here.
9617          *
9618          * N.B. - this code below runs only on platforms with reliable TSC,
9619          * as that is the only way backwards_tsc is set above.  Also note
9620          * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9621          * have the same delta_cyc adjustment applied if backwards_tsc
9622          * is detected.  Note further, this adjustment is only done once,
9623          * as we reset last_host_tsc on all VCPUs to stop this from being
9624          * called multiple times (one for each physical CPU bringup).
9625          *
9626          * Platforms with unreliable TSCs don't have to deal with this, they
9627          * will be compensated by the logic in vcpu_load, which sets the TSC to
9628          * catchup mode.  This will catchup all VCPUs to real time, but cannot
9629          * guarantee that they stay in perfect synchronization.
9630          */
9631         if (backwards_tsc) {
9632                 u64 delta_cyc = max_tsc - local_tsc;
9633                 list_for_each_entry(kvm, &vm_list, vm_list) {
9634                         kvm->arch.backwards_tsc_observed = true;
9635                         kvm_for_each_vcpu(i, vcpu, kvm) {
9636                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9637                                 vcpu->arch.last_host_tsc = local_tsc;
9638                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9639                         }
9640
9641                         /*
9642                          * We have to disable TSC offset matching.. if you were
9643                          * booting a VM while issuing an S4 host suspend....
9644                          * you may have some problem.  Solving this issue is
9645                          * left as an exercise to the reader.
9646                          */
9647                         kvm->arch.last_tsc_nsec = 0;
9648                         kvm->arch.last_tsc_write = 0;
9649                 }
9650
9651         }
9652         return 0;
9653 }
9654
9655 void kvm_arch_hardware_disable(void)
9656 {
9657         kvm_x86_ops.hardware_disable();
9658         drop_user_return_notifiers();
9659 }
9660
9661 int kvm_arch_hardware_setup(void *opaque)
9662 {
9663         struct kvm_x86_init_ops *ops = opaque;
9664         int r;
9665
9666         rdmsrl_safe(MSR_EFER, &host_efer);
9667
9668         if (boot_cpu_has(X86_FEATURE_XSAVES))
9669                 rdmsrl(MSR_IA32_XSS, host_xss);
9670
9671         r = ops->hardware_setup();
9672         if (r != 0)
9673                 return r;
9674
9675         memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
9676
9677         if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
9678                 supported_xss = 0;
9679
9680 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
9681         cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
9682 #undef __kvm_cpu_cap_has
9683
9684         if (kvm_has_tsc_control) {
9685                 /*
9686                  * Make sure the user can only configure tsc_khz values that
9687                  * fit into a signed integer.
9688                  * A min value is not calculated because it will always
9689                  * be 1 on all machines.
9690                  */
9691                 u64 max = min(0x7fffffffULL,
9692                               __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9693                 kvm_max_guest_tsc_khz = max;
9694
9695                 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9696         }
9697
9698         kvm_init_msr_list();
9699         return 0;
9700 }
9701
9702 void kvm_arch_hardware_unsetup(void)
9703 {
9704         kvm_x86_ops.hardware_unsetup();
9705 }
9706
9707 int kvm_arch_check_processor_compat(void *opaque)
9708 {
9709         struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
9710         struct kvm_x86_init_ops *ops = opaque;
9711
9712         WARN_ON(!irqs_disabled());
9713
9714         if (__cr4_reserved_bits(cpu_has, c) !=
9715             __cr4_reserved_bits(cpu_has, &boot_cpu_data))
9716                 return -EIO;
9717
9718         return ops->check_processor_compatibility();
9719 }
9720
9721 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9722 {
9723         return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9724 }
9725 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9726
9727 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9728 {
9729         return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9730 }
9731
9732 struct static_key kvm_no_apic_vcpu __read_mostly;
9733 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9734
9735 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9736 {
9737         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
9738
9739         vcpu->arch.l1tf_flush_l1d = true;
9740         if (pmu->version && unlikely(pmu->event_count)) {
9741                 pmu->need_cleanup = true;
9742                 kvm_make_request(KVM_REQ_PMU, vcpu);
9743         }
9744         kvm_x86_ops.sched_in(vcpu, cpu);
9745 }
9746
9747 void kvm_arch_free_vm(struct kvm *kvm)
9748 {
9749         kfree(kvm->arch.hyperv.hv_pa_pg);
9750         vfree(kvm);
9751 }
9752
9753
9754 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9755 {
9756         if (type)
9757                 return -EINVAL;
9758
9759         INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9760         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9761         INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9762         INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
9763         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9764         atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9765
9766         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9767         set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9768         /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9769         set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9770                 &kvm->arch.irq_sources_bitmap);
9771
9772         raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9773         mutex_init(&kvm->arch.apic_map_lock);
9774         spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9775
9776         kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
9777         pvclock_update_vm_gtod_copy(kvm);
9778
9779         kvm->arch.guest_can_read_msr_platform_info = true;
9780
9781         INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9782         INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9783
9784         kvm_hv_init_vm(kvm);
9785         kvm_page_track_init(kvm);
9786         kvm_mmu_init_vm(kvm);
9787
9788         return kvm_x86_ops.vm_init(kvm);
9789 }
9790
9791 int kvm_arch_post_init_vm(struct kvm *kvm)
9792 {
9793         return kvm_mmu_post_init_vm(kvm);
9794 }
9795
9796 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9797 {
9798         vcpu_load(vcpu);
9799         kvm_mmu_unload(vcpu);
9800         vcpu_put(vcpu);
9801 }
9802
9803 static void kvm_free_vcpus(struct kvm *kvm)
9804 {
9805         unsigned int i;
9806         struct kvm_vcpu *vcpu;
9807
9808         /*
9809          * Unpin any mmu pages first.
9810          */
9811         kvm_for_each_vcpu(i, vcpu, kvm) {
9812                 kvm_clear_async_pf_completion_queue(vcpu);
9813                 kvm_unload_vcpu_mmu(vcpu);
9814         }
9815         kvm_for_each_vcpu(i, vcpu, kvm)
9816                 kvm_vcpu_destroy(vcpu);
9817
9818         mutex_lock(&kvm->lock);
9819         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9820                 kvm->vcpus[i] = NULL;
9821
9822         atomic_set(&kvm->online_vcpus, 0);
9823         mutex_unlock(&kvm->lock);
9824 }
9825
9826 void kvm_arch_sync_events(struct kvm *kvm)
9827 {
9828         cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9829         cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9830         kvm_free_pit(kvm);
9831 }
9832
9833 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9834 {
9835         int i, r;
9836         unsigned long hva, uninitialized_var(old_npages);
9837         struct kvm_memslots *slots = kvm_memslots(kvm);
9838         struct kvm_memory_slot *slot;
9839
9840         /* Called with kvm->slots_lock held.  */
9841         if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9842                 return -EINVAL;
9843
9844         slot = id_to_memslot(slots, id);
9845         if (size) {
9846                 if (slot && slot->npages)
9847                         return -EEXIST;
9848
9849                 /*
9850                  * MAP_SHARED to prevent internal slot pages from being moved
9851                  * by fork()/COW.
9852                  */
9853                 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9854                               MAP_SHARED | MAP_ANONYMOUS, 0);
9855                 if (IS_ERR((void *)hva))
9856                         return PTR_ERR((void *)hva);
9857         } else {
9858                 if (!slot || !slot->npages)
9859                         return 0;
9860
9861                 /*
9862                  * Stuff a non-canonical value to catch use-after-delete.  This
9863                  * ends up being 0 on 32-bit KVM, but there's no better
9864                  * alternative.
9865                  */
9866                 hva = (unsigned long)(0xdeadull << 48);
9867                 old_npages = slot->npages;
9868         }
9869
9870         for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9871                 struct kvm_userspace_memory_region m;
9872
9873                 m.slot = id | (i << 16);
9874                 m.flags = 0;
9875                 m.guest_phys_addr = gpa;
9876                 m.userspace_addr = hva;
9877                 m.memory_size = size;
9878                 r = __kvm_set_memory_region(kvm, &m);
9879                 if (r < 0)
9880                         return r;
9881         }
9882
9883         if (!size)
9884                 vm_munmap(hva, old_npages * PAGE_SIZE);
9885
9886         return 0;
9887 }
9888 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9889
9890 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
9891 {
9892         kvm_mmu_pre_destroy_vm(kvm);
9893 }
9894
9895 void kvm_arch_destroy_vm(struct kvm *kvm)
9896 {
9897         if (current->mm == kvm->mm) {
9898                 /*
9899                  * Free memory regions allocated on behalf of userspace,
9900                  * unless the the memory map has changed due to process exit
9901                  * or fd copying.
9902                  */
9903                 mutex_lock(&kvm->slots_lock);
9904                 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
9905                                         0, 0);
9906                 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
9907                                         0, 0);
9908                 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9909                 mutex_unlock(&kvm->slots_lock);
9910         }
9911         if (kvm_x86_ops.vm_destroy)
9912                 kvm_x86_ops.vm_destroy(kvm);
9913         kvm_pic_destroy(kvm);
9914         kvm_ioapic_destroy(kvm);
9915         kvm_free_vcpus(kvm);
9916         kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9917         kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9918         kvm_mmu_uninit_vm(kvm);
9919         kvm_page_track_cleanup(kvm);
9920         kvm_hv_destroy_vm(kvm);
9921 }
9922
9923 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
9924 {
9925         int i;
9926
9927         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9928                 kvfree(slot->arch.rmap[i]);
9929                 slot->arch.rmap[i] = NULL;
9930
9931                 if (i == 0)
9932                         continue;
9933
9934                 kvfree(slot->arch.lpage_info[i - 1]);
9935                 slot->arch.lpage_info[i - 1] = NULL;
9936         }
9937
9938         kvm_page_track_free_memslot(slot);
9939 }
9940
9941 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
9942                                       unsigned long npages)
9943 {
9944         int i;
9945
9946         /*
9947          * Clear out the previous array pointers for the KVM_MR_MOVE case.  The
9948          * old arrays will be freed by __kvm_set_memory_region() if installing
9949          * the new memslot is successful.
9950          */
9951         memset(&slot->arch, 0, sizeof(slot->arch));
9952
9953         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9954                 struct kvm_lpage_info *linfo;
9955                 unsigned long ugfn;
9956                 int lpages;
9957                 int level = i + 1;
9958
9959                 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9960                                       slot->base_gfn, level) + 1;
9961
9962                 slot->arch.rmap[i] =
9963                         kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9964                                  GFP_KERNEL_ACCOUNT);
9965                 if (!slot->arch.rmap[i])
9966                         goto out_free;
9967                 if (i == 0)
9968                         continue;
9969
9970                 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9971                 if (!linfo)
9972                         goto out_free;
9973
9974                 slot->arch.lpage_info[i - 1] = linfo;
9975
9976                 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9977                         linfo[0].disallow_lpage = 1;
9978                 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9979                         linfo[lpages - 1].disallow_lpage = 1;
9980                 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9981                 /*
9982                  * If the gfn and userspace address are not aligned wrt each
9983                  * other, disable large page support for this slot.
9984                  */
9985                 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
9986                         unsigned long j;
9987
9988                         for (j = 0; j < lpages; ++j)
9989                                 linfo[j].disallow_lpage = 1;
9990                 }
9991         }
9992
9993         if (kvm_page_track_create_memslot(slot, npages))
9994                 goto out_free;
9995
9996         return 0;
9997
9998 out_free:
9999         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10000                 kvfree(slot->arch.rmap[i]);
10001                 slot->arch.rmap[i] = NULL;
10002                 if (i == 0)
10003                         continue;
10004
10005                 kvfree(slot->arch.lpage_info[i - 1]);
10006                 slot->arch.lpage_info[i - 1] = NULL;
10007         }
10008         return -ENOMEM;
10009 }
10010
10011 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
10012 {
10013         struct kvm_vcpu *vcpu;
10014         int i;
10015
10016         /*
10017          * memslots->generation has been incremented.
10018          * mmio generation may have reached its maximum value.
10019          */
10020         kvm_mmu_invalidate_mmio_sptes(kvm, gen);
10021
10022         /* Force re-initialization of steal_time cache */
10023         kvm_for_each_vcpu(i, vcpu, kvm)
10024                 kvm_vcpu_kick(vcpu);
10025 }
10026
10027 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10028                                 struct kvm_memory_slot *memslot,
10029                                 const struct kvm_userspace_memory_region *mem,
10030                                 enum kvm_mr_change change)
10031 {
10032         if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10033                 return kvm_alloc_memslot_metadata(memslot,
10034                                                   mem->memory_size >> PAGE_SHIFT);
10035         return 0;
10036 }
10037
10038 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10039                                      struct kvm_memory_slot *new)
10040 {
10041         /* Still write protect RO slot */
10042         if (new->flags & KVM_MEM_READONLY) {
10043                 kvm_mmu_slot_remove_write_access(kvm, new, PT_PAGE_TABLE_LEVEL);
10044                 return;
10045         }
10046
10047         /*
10048          * Call kvm_x86_ops dirty logging hooks when they are valid.
10049          *
10050          * kvm_x86_ops.slot_disable_log_dirty is called when:
10051          *
10052          *  - KVM_MR_CREATE with dirty logging is disabled
10053          *  - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
10054          *
10055          * The reason is, in case of PML, we need to set D-bit for any slots
10056          * with dirty logging disabled in order to eliminate unnecessary GPA
10057          * logging in PML buffer (and potential PML buffer full VMEXIT). This
10058          * guarantees leaving PML enabled during guest's lifetime won't have
10059          * any additional overhead from PML when guest is running with dirty
10060          * logging disabled for memory slots.
10061          *
10062          * kvm_x86_ops.slot_enable_log_dirty is called when switching new slot
10063          * to dirty logging mode.
10064          *
10065          * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
10066          *
10067          * In case of write protect:
10068          *
10069          * Write protect all pages for dirty logging.
10070          *
10071          * All the sptes including the large sptes which point to this
10072          * slot are set to readonly. We can not create any new large
10073          * spte on this slot until the end of the logging.
10074          *
10075          * See the comments in fast_page_fault().
10076          */
10077         if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10078                 if (kvm_x86_ops.slot_enable_log_dirty) {
10079                         kvm_x86_ops.slot_enable_log_dirty(kvm, new);
10080                 } else {
10081                         int level =
10082                                 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10083                                 PT_DIRECTORY_LEVEL : PT_PAGE_TABLE_LEVEL;
10084
10085                         /*
10086                          * If we're with initial-all-set, we don't need
10087                          * to write protect any small page because
10088                          * they're reported as dirty already.  However
10089                          * we still need to write-protect huge pages
10090                          * so that the page split can happen lazily on
10091                          * the first write to the huge page.
10092                          */
10093                         kvm_mmu_slot_remove_write_access(kvm, new, level);
10094                 }
10095         } else {
10096                 if (kvm_x86_ops.slot_disable_log_dirty)
10097                         kvm_x86_ops.slot_disable_log_dirty(kvm, new);
10098         }
10099 }
10100
10101 void kvm_arch_commit_memory_region(struct kvm *kvm,
10102                                 const struct kvm_userspace_memory_region *mem,
10103                                 struct kvm_memory_slot *old,
10104                                 const struct kvm_memory_slot *new,
10105                                 enum kvm_mr_change change)
10106 {
10107         if (!kvm->arch.n_requested_mmu_pages)
10108                 kvm_mmu_change_mmu_pages(kvm,
10109                                 kvm_mmu_calculate_default_mmu_pages(kvm));
10110
10111         /*
10112          * Dirty logging tracks sptes in 4k granularity, meaning that large
10113          * sptes have to be split.  If live migration is successful, the guest
10114          * in the source machine will be destroyed and large sptes will be
10115          * created in the destination. However, if the guest continues to run
10116          * in the source machine (for example if live migration fails), small
10117          * sptes will remain around and cause bad performance.
10118          *
10119          * Scan sptes if dirty logging has been stopped, dropping those
10120          * which can be collapsed into a single large-page spte.  Later
10121          * page faults will create the large-page sptes.
10122          *
10123          * There is no need to do this in any of the following cases:
10124          * CREATE:      No dirty mappings will already exist.
10125          * MOVE/DELETE: The old mappings will already have been cleaned up by
10126          *              kvm_arch_flush_shadow_memslot()
10127          */
10128         if (change == KVM_MR_FLAGS_ONLY &&
10129                 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10130                 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10131                 kvm_mmu_zap_collapsible_sptes(kvm, new);
10132
10133         /*
10134          * Set up write protection and/or dirty logging for the new slot.
10135          *
10136          * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
10137          * been zapped so no dirty logging staff is needed for old slot. For
10138          * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
10139          * new and it's also covered when dealing with the new slot.
10140          *
10141          * FIXME: const-ify all uses of struct kvm_memory_slot.
10142          */
10143         if (change != KVM_MR_DELETE)
10144                 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
10145
10146         /* Free the arrays associated with the old memslot. */
10147         if (change == KVM_MR_MOVE)
10148                 kvm_arch_free_memslot(kvm, old);
10149 }
10150
10151 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10152 {
10153         kvm_mmu_zap_all(kvm);
10154 }
10155
10156 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10157                                    struct kvm_memory_slot *slot)
10158 {
10159         kvm_page_track_flush_slot(kvm, slot);
10160 }
10161
10162 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10163 {
10164         return (is_guest_mode(vcpu) &&
10165                         kvm_x86_ops.guest_apic_has_interrupt &&
10166                         kvm_x86_ops.guest_apic_has_interrupt(vcpu));
10167 }
10168
10169 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10170 {
10171         if (!list_empty_careful(&vcpu->async_pf.done))
10172                 return true;
10173
10174         if (kvm_apic_has_events(vcpu))
10175                 return true;
10176
10177         if (vcpu->arch.pv.pv_unhalted)
10178                 return true;
10179
10180         if (vcpu->arch.exception.pending)
10181                 return true;
10182
10183         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10184             (vcpu->arch.nmi_pending &&
10185              kvm_x86_ops.nmi_allowed(vcpu)))
10186                 return true;
10187
10188         if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10189             (vcpu->arch.smi_pending && !is_smm(vcpu)))
10190                 return true;
10191
10192         if (kvm_arch_interrupt_allowed(vcpu) &&
10193             (kvm_cpu_has_interrupt(vcpu) ||
10194             kvm_guest_apic_has_interrupt(vcpu)))
10195                 return true;
10196
10197         if (kvm_hv_has_stimer_pending(vcpu))
10198                 return true;
10199
10200         return false;
10201 }
10202
10203 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10204 {
10205         return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10206 }
10207
10208 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10209 {
10210         if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10211                 return true;
10212
10213         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10214                 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10215                  kvm_test_request(KVM_REQ_EVENT, vcpu))
10216                 return true;
10217
10218         if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu))
10219                 return true;
10220
10221         return false;
10222 }
10223
10224 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10225 {
10226         return vcpu->arch.preempted_in_kernel;
10227 }
10228
10229 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10230 {
10231         return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10232 }
10233
10234 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10235 {
10236         return kvm_x86_ops.interrupt_allowed(vcpu);
10237 }
10238
10239 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10240 {
10241         if (is_64_bit_mode(vcpu))
10242                 return kvm_rip_read(vcpu);
10243         return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10244                      kvm_rip_read(vcpu));
10245 }
10246 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10247
10248 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10249 {
10250         return kvm_get_linear_rip(vcpu) == linear_rip;
10251 }
10252 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10253
10254 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10255 {
10256         unsigned long rflags;
10257
10258         rflags = kvm_x86_ops.get_rflags(vcpu);
10259         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10260                 rflags &= ~X86_EFLAGS_TF;
10261         return rflags;
10262 }
10263 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10264
10265 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10266 {
10267         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10268             kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10269                 rflags |= X86_EFLAGS_TF;
10270         kvm_x86_ops.set_rflags(vcpu, rflags);
10271 }
10272
10273 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10274 {
10275         __kvm_set_rflags(vcpu, rflags);
10276         kvm_make_request(KVM_REQ_EVENT, vcpu);
10277 }
10278 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10279
10280 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10281 {
10282         int r;
10283
10284         if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10285               work->wakeup_all)
10286                 return;
10287
10288         r = kvm_mmu_reload(vcpu);
10289         if (unlikely(r))
10290                 return;
10291
10292         if (!vcpu->arch.mmu->direct_map &&
10293               work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10294                 return;
10295
10296         kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10297 }
10298
10299 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10300 {
10301         return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10302 }
10303
10304 static inline u32 kvm_async_pf_next_probe(u32 key)
10305 {
10306         return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
10307 }
10308
10309 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10310 {
10311         u32 key = kvm_async_pf_hash_fn(gfn);
10312
10313         while (vcpu->arch.apf.gfns[key] != ~0)
10314                 key = kvm_async_pf_next_probe(key);
10315
10316         vcpu->arch.apf.gfns[key] = gfn;
10317 }
10318
10319 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10320 {
10321         int i;
10322         u32 key = kvm_async_pf_hash_fn(gfn);
10323
10324         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
10325                      (vcpu->arch.apf.gfns[key] != gfn &&
10326                       vcpu->arch.apf.gfns[key] != ~0); i++)
10327                 key = kvm_async_pf_next_probe(key);
10328
10329         return key;
10330 }
10331
10332 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10333 {
10334         return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10335 }
10336
10337 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10338 {
10339         u32 i, j, k;
10340
10341         i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10342         while (true) {
10343                 vcpu->arch.apf.gfns[i] = ~0;
10344                 do {
10345                         j = kvm_async_pf_next_probe(j);
10346                         if (vcpu->arch.apf.gfns[j] == ~0)
10347                                 return;
10348                         k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10349                         /*
10350                          * k lies cyclically in ]i,j]
10351                          * |    i.k.j |
10352                          * |....j i.k.| or  |.k..j i...|
10353                          */
10354                 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10355                 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10356                 i = j;
10357         }
10358 }
10359
10360 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
10361 {
10362
10363         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
10364                                       sizeof(val));
10365 }
10366
10367 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
10368 {
10369
10370         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10371                                       sizeof(u32));
10372 }
10373
10374 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10375 {
10376         if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10377                 return false;
10378
10379         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10380             (vcpu->arch.apf.send_user_only &&
10381              kvm_x86_ops.get_cpl(vcpu) == 0))
10382                 return false;
10383
10384         return true;
10385 }
10386
10387 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10388 {
10389         if (unlikely(!lapic_in_kernel(vcpu) ||
10390                      kvm_event_needs_reinjection(vcpu) ||
10391                      vcpu->arch.exception.pending))
10392                 return false;
10393
10394         if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10395                 return false;
10396
10397         /*
10398          * If interrupts are off we cannot even use an artificial
10399          * halt state.
10400          */
10401         return kvm_x86_ops.interrupt_allowed(vcpu);
10402 }
10403
10404 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10405                                      struct kvm_async_pf *work)
10406 {
10407         struct x86_exception fault;
10408
10409         trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10410         kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10411
10412         if (kvm_can_deliver_async_pf(vcpu) &&
10413             !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
10414                 fault.vector = PF_VECTOR;
10415                 fault.error_code_valid = true;
10416                 fault.error_code = 0;
10417                 fault.nested_page_fault = false;
10418                 fault.address = work->arch.token;
10419                 fault.async_page_fault = true;
10420                 kvm_inject_page_fault(vcpu, &fault);
10421         } else {
10422                 /*
10423                  * It is not possible to deliver a paravirtualized asynchronous
10424                  * page fault, but putting the guest in an artificial halt state
10425                  * can be beneficial nevertheless: if an interrupt arrives, we
10426                  * can deliver it timely and perhaps the guest will schedule
10427                  * another process.  When the instruction that triggered a page
10428                  * fault is retried, hopefully the page will be ready in the host.
10429                  */
10430                 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10431         }
10432 }
10433
10434 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10435                                  struct kvm_async_pf *work)
10436 {
10437         struct x86_exception fault;
10438         u32 val;
10439
10440         if (work->wakeup_all)
10441                 work->arch.token = ~0; /* broadcast wakeup */
10442         else
10443                 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10444         trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
10445
10446         if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10447             !apf_get_user(vcpu, &val)) {
10448                 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10449                     vcpu->arch.exception.pending &&
10450                     vcpu->arch.exception.nr == PF_VECTOR &&
10451                     !apf_put_user(vcpu, 0)) {
10452                         vcpu->arch.exception.injected = false;
10453                         vcpu->arch.exception.pending = false;
10454                         vcpu->arch.exception.nr = 0;
10455                         vcpu->arch.exception.has_error_code = false;
10456                         vcpu->arch.exception.error_code = 0;
10457                         vcpu->arch.exception.has_payload = false;
10458                         vcpu->arch.exception.payload = 0;
10459                 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10460                         fault.vector = PF_VECTOR;
10461                         fault.error_code_valid = true;
10462                         fault.error_code = 0;
10463                         fault.nested_page_fault = false;
10464                         fault.address = work->arch.token;
10465                         fault.async_page_fault = true;
10466                         kvm_inject_page_fault(vcpu, &fault);
10467                 }
10468         }
10469         vcpu->arch.apf.halted = false;
10470         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10471 }
10472
10473 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10474 {
10475         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10476                 return true;
10477         else
10478                 return kvm_can_do_async_pf(vcpu);
10479 }
10480
10481 void kvm_arch_start_assignment(struct kvm *kvm)
10482 {
10483         atomic_inc(&kvm->arch.assigned_device_count);
10484 }
10485 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10486
10487 void kvm_arch_end_assignment(struct kvm *kvm)
10488 {
10489         atomic_dec(&kvm->arch.assigned_device_count);
10490 }
10491 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10492
10493 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10494 {
10495         return atomic_read(&kvm->arch.assigned_device_count);
10496 }
10497 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10498
10499 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10500 {
10501         atomic_inc(&kvm->arch.noncoherent_dma_count);
10502 }
10503 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10504
10505 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10506 {
10507         atomic_dec(&kvm->arch.noncoherent_dma_count);
10508 }
10509 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10510
10511 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10512 {
10513         return atomic_read(&kvm->arch.noncoherent_dma_count);
10514 }
10515 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10516
10517 bool kvm_arch_has_irq_bypass(void)
10518 {
10519         return true;
10520 }
10521
10522 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10523                                       struct irq_bypass_producer *prod)
10524 {
10525         struct kvm_kernel_irqfd *irqfd =
10526                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10527
10528         irqfd->producer = prod;
10529
10530         return kvm_x86_ops.update_pi_irte(irqfd->kvm,
10531                                            prod->irq, irqfd->gsi, 1);
10532 }
10533
10534 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10535                                       struct irq_bypass_producer *prod)
10536 {
10537         int ret;
10538         struct kvm_kernel_irqfd *irqfd =
10539                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10540
10541         WARN_ON(irqfd->producer != prod);
10542         irqfd->producer = NULL;
10543
10544         /*
10545          * When producer of consumer is unregistered, we change back to
10546          * remapped mode, so we can re-use the current implementation
10547          * when the irq is masked/disabled or the consumer side (KVM
10548          * int this case doesn't want to receive the interrupts.
10549         */
10550         ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10551         if (ret)
10552                 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10553                        " fails: %d\n", irqfd->consumer.token, ret);
10554 }
10555
10556 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10557                                    uint32_t guest_irq, bool set)
10558 {
10559         return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set);
10560 }
10561
10562 bool kvm_vector_hashing_enabled(void)
10563 {
10564         return vector_hashing;
10565 }
10566
10567 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10568 {
10569         return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10570 }
10571 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10572
10573 u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu)
10574 {
10575         uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD;
10576
10577         /* The STIBP bit doesn't fault even if it's not advertised */
10578         if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
10579             !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
10580                 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10581         if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
10582             !boot_cpu_has(X86_FEATURE_AMD_IBRS))
10583                 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10584
10585         if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) &&
10586             !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
10587                 bits &= ~SPEC_CTRL_SSBD;
10588         if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
10589             !boot_cpu_has(X86_FEATURE_AMD_SSBD))
10590                 bits &= ~SPEC_CTRL_SSBD;
10591
10592         return bits;
10593 }
10594 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits);
10595
10596 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10597 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10598 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10599 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10600 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10601 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10602 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10603 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10604 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10605 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10606 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10607 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10608 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10609 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10610 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10611 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10612 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10613 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10614 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10615 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
10616 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
10617 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);