arch/x86/kvm/x86.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * derived from drivers/kvm/kvm_main.c
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright (C) 2008 Qumranet, Inc.
   9  * Copyright IBM Corporation, 2008
  10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  11  *
  12  * Authors:
  13  *   Avi Kivity   <avi@qumranet.com>
  14  *   Yaniv Kamay  <yaniv@qumranet.com>
  15  *   Amit Shah    <amit.shah@qumranet.com>
  16  *   Ben-Ami Yassour <benami@il.ibm.com>
  17  */
  18
  19 #include <linux/kvm_host.h>
  20 #include "irq.h"
  21 #include "mmu.h"
  22 #include "i8254.h"
  23 #include "tss.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28 #include "hyperv.h"
  29
  30 #include <linux/clocksource.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/kvm.h>
  33 #include <linux/fs.h>
  34 #include <linux/vmalloc.h>
  35 #include <linux/export.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/mman.h>
  38 #include <linux/highmem.h>
  39 #include <linux/iommu.h>
  40 #include <linux/intel-iommu.h>
  41 #include <linux/cpufreq.h>
  42 #include <linux/user-return-notifier.h>
  43 #include <linux/srcu.h>
  44 #include <linux/slab.h>
  45 #include <linux/perf_event.h>
  46 #include <linux/uaccess.h>
  47 #include <linux/hash.h>
  48 #include <linux/pci.h>
  49 #include <linux/timekeeper_internal.h>
  50 #include <linux/pvclock_gtod.h>
  51 #include <linux/kvm_irqfd.h>
  52 #include <linux/irqbypass.h>
  53 #include <linux/sched/stat.h>
  54 #include <linux/sched/isolation.h>
  55 #include <linux/mem_encrypt.h>
  56
  57 #include <trace/events/kvm.h>
  58
  59 #include <asm/debugreg.h>
  60 #include <asm/msr.h>
  61 #include <asm/desc.h>
  62 #include <asm/mce.h>
  63 #include <linux/kernel_stat.h>
  64 #include <asm/fpu/internal.h> /* Ugh! */
  65 #include <asm/pvclock.h>
  66 #include <asm/div64.h>
  67 #include <asm/irq_remapping.h>
  68 #include <asm/mshyperv.h>
  69 #include <asm/hypervisor.h>
  70 #include <asm/intel_pt.h>
  71 #include <clocksource/hyperv_timer.h>
  72
  73 #define CREATE_TRACE_POINTS
  74 #include "trace.h"
  75
  76 #define MAX_IO_MSRS 256
  77 #define KVM_MAX_MCE_BANKS 32
  78 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
  79 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
  80
  81 #define emul_to_vcpu(ctxt) \
  82         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
  83
  84 /* EFER defaults:
  85  * - enable syscall per default because its emulated by KVM
  86  * - enable LME and LMA per default on 64 bit KVM
  87  */
  88 #ifdef CONFIG_X86_64
  89 static
  90 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
  91 #else
  92 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
  93 #endif
  94
  95 #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__
  96 #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__
  97
  98 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
  99                                     KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
 100
 101 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
 102 static void process_nmi(struct kvm_vcpu *vcpu);
 103 static void enter_smm(struct kvm_vcpu *vcpu);
 104 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
 105 static void store_regs(struct kvm_vcpu *vcpu);
 106 static int sync_regs(struct kvm_vcpu *vcpu);
 107
 108 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
 109 EXPORT_SYMBOL_GPL(kvm_x86_ops);
 110
 111 static bool __read_mostly ignore_msrs = 0;
 112 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
 113
 114 static bool __read_mostly report_ignored_msrs = true;
 115 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
 116
 117 unsigned int min_timer_period_us = 200;
 118 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
 119
 120 static bool __read_mostly kvmclock_periodic_sync = true;
 121 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
 122
 123 bool __read_mostly kvm_has_tsc_control;
 124 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
 125 u32  __read_mostly kvm_max_guest_tsc_khz;
 126 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
 127 u8   __read_mostly kvm_tsc_scaling_ratio_frac_bits;
 128 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
 129 u64  __read_mostly kvm_max_tsc_scaling_ratio;
 130 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
 131 u64 __read_mostly kvm_default_tsc_scaling_ratio;
 132 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
 133
 134 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
 135 static u32 __read_mostly tsc_tolerance_ppm = 250;
 136 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
 137
 138 /*
 139  * lapic timer advance (tscdeadline mode only) in nanoseconds.  '-1' enables
 140  * adaptive tuning starting from default advancment of 1000ns.  '0' disables
 141  * advancement entirely.  Any other value is used as-is and disables adaptive
 142  * tuning, i.e. allows priveleged userspace to set an exact advancement time.
 143  */
 144 static int __read_mostly lapic_timer_advance_ns = -1;
 145 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
 146
 147 static bool __read_mostly vector_hashing = true;
 148 module_param(vector_hashing, bool, S_IRUGO);
 149
 150 bool __read_mostly enable_vmware_backdoor = false;
 151 module_param(enable_vmware_backdoor, bool, S_IRUGO);
 152 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
 153
 154 static bool __read_mostly force_emulation_prefix = false;
 155 module_param(force_emulation_prefix, bool, S_IRUGO);
 156
 157 int __read_mostly pi_inject_timer = -1;
 158 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
 159
 160 #define KVM_NR_SHARED_MSRS 16
 161
 162 struct kvm_shared_msrs_global {
 163         int nr;
 164         u32 msrs[KVM_NR_SHARED_MSRS];
 165 };
 166
 167 struct kvm_shared_msrs {
 168         struct user_return_notifier urn;
 169         bool registered;
 170         struct kvm_shared_msr_values {
 171                 u64 host;
 172                 u64 curr;
 173         } values[KVM_NR_SHARED_MSRS];
 174 };
 175
 176 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
 177 static struct kvm_shared_msrs __percpu *shared_msrs;
 178
 179 struct kvm_stats_debugfs_item debugfs_entries[] = {
 180         { "pf_fixed", VCPU_STAT(pf_fixed) },
 181         { "pf_guest", VCPU_STAT(pf_guest) },
 182         { "tlb_flush", VCPU_STAT(tlb_flush) },
 183         { "invlpg", VCPU_STAT(invlpg) },
 184         { "exits", VCPU_STAT(exits) },
 185         { "io_exits", VCPU_STAT(io_exits) },
 186         { "mmio_exits", VCPU_STAT(mmio_exits) },
 187         { "signal_exits", VCPU_STAT(signal_exits) },
 188         { "irq_window", VCPU_STAT(irq_window_exits) },
 189         { "nmi_window", VCPU_STAT(nmi_window_exits) },
 190         { "halt_exits", VCPU_STAT(halt_exits) },
 191         { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
 192         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
 193         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
 194         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
 195         { "hypercalls", VCPU_STAT(hypercalls) },
 196         { "request_irq", VCPU_STAT(request_irq_exits) },
 197         { "irq_exits", VCPU_STAT(irq_exits) },
 198         { "host_state_reload", VCPU_STAT(host_state_reload) },
 199         { "fpu_reload", VCPU_STAT(fpu_reload) },
 200         { "insn_emulation", VCPU_STAT(insn_emulation) },
 201         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
 202         { "irq_injections", VCPU_STAT(irq_injections) },
 203         { "nmi_injections", VCPU_STAT(nmi_injections) },
 204         { "req_event", VCPU_STAT(req_event) },
 205         { "l1d_flush", VCPU_STAT(l1d_flush) },
 206         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
 207         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
 208         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
 209         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
 210         { "mmu_flooded", VM_STAT(mmu_flooded) },
 211         { "mmu_recycled", VM_STAT(mmu_recycled) },
 212         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
 213         { "mmu_unsync", VM_STAT(mmu_unsync) },
 214         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
 215         { "largepages", VM_STAT(lpages, .mode = 0444) },
 216         { "max_mmu_page_hash_collisions",
 217                 VM_STAT(max_mmu_page_hash_collisions) },
 218         { NULL }
 219 };
 220
 221 u64 __read_mostly host_xcr0;
 222
 223 struct kmem_cache *x86_fpu_cache;
 224 EXPORT_SYMBOL_GPL(x86_fpu_cache);
 225
 226 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
 227
 228 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
 229 {
 230         int i;
 231         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
 232                 vcpu->arch.apf.gfns[i] = ~0;
 233 }
 234
 235 static void kvm_on_user_return(struct user_return_notifier *urn)
 236 {
 237         unsigned slot;
 238         struct kvm_shared_msrs *locals
 239                 = container_of(urn, struct kvm_shared_msrs, urn);
 240         struct kvm_shared_msr_values *values;
 241         unsigned long flags;
 242
 243         /*
 244          * Disabling irqs at this point since the following code could be
 245          * interrupted and executed through kvm_arch_hardware_disable()
 246          */
 247         local_irq_save(flags);
 248         if (locals->registered) {
 249                 locals->registered = false;
 250                 user_return_notifier_unregister(urn);
 251         }
 252         local_irq_restore(flags);
 253         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
 254                 values = &locals->values[slot];
 255                 if (values->host != values->curr) {
 256                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
 257                         values->curr = values->host;
 258                 }
 259         }
 260 }
 261
 262 static void shared_msr_update(unsigned slot, u32 msr)
 263 {
 264         u64 value;
 265         unsigned int cpu = smp_processor_id();
 266         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 267
 268         /* only read, and nobody should modify it at this time,
 269          * so don't need lock */
 270         if (slot >= shared_msrs_global.nr) {
 271                 printk(KERN_ERR "kvm: invalid MSR slot!");
 272                 return;
 273         }
 274         rdmsrl_safe(msr, &value);
 275         smsr->values[slot].host = value;
 276         smsr->values[slot].curr = value;
 277 }
 278
 279 void kvm_define_shared_msr(unsigned slot, u32 msr)
 280 {
 281         BUG_ON(slot >= KVM_NR_SHARED_MSRS);
 282         shared_msrs_global.msrs[slot] = msr;
 283         if (slot >= shared_msrs_global.nr)
 284                 shared_msrs_global.nr = slot + 1;
 285 }
 286 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
 287
 288 static void kvm_shared_msr_cpu_online(void)
 289 {
 290         unsigned i;
 291
 292         for (i = 0; i < shared_msrs_global.nr; ++i)
 293                 shared_msr_update(i, shared_msrs_global.msrs[i]);
 294 }
 295
 296 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
 297 {
 298         unsigned int cpu = smp_processor_id();
 299         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 300         int err;
 301
 302         if (((value ^ smsr->values[slot].curr) & mask) == 0)
 303                 return 0;
 304         smsr->values[slot].curr = value;
 305         err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
 306         if (err)
 307                 return 1;
 308
 309         if (!smsr->registered) {
 310                 smsr->urn.on_user_return = kvm_on_user_return;
 311                 user_return_notifier_register(&smsr->urn);
 312                 smsr->registered = true;
 313         }
 314         return 0;
 315 }
 316 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
 317
 318 static void drop_user_return_notifiers(void)
 319 {
 320         unsigned int cpu = smp_processor_id();
 321         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 322
 323         if (smsr->registered)
 324                 kvm_on_user_return(&smsr->urn);
 325 }
 326
 327 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
 328 {
 329         return vcpu->arch.apic_base;
 330 }
 331 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
 332
 333 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
 334 {
 335         return kvm_apic_mode(kvm_get_apic_base(vcpu));
 336 }
 337 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
 338
 339 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 340 {
 341         enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
 342         enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
 343         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
 344                 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
 345
 346         if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
 347                 return 1;
 348         if (!msr_info->host_initiated) {
 349                 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
 350                         return 1;
 351                 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
 352                         return 1;
 353         }
 354
 355         kvm_lapic_set_base(vcpu, msr_info->data);
 356         return 0;
 357 }
 358 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
 359
 360 asmlinkage __visible void kvm_spurious_fault(void)
 361 {
 362         /* Fault while not rebooting.  We want the trace. */
 363         BUG_ON(!kvm_rebooting);
 364 }
 365 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
 366
 367 #define EXCPT_BENIGN            0
 368 #define EXCPT_CONTRIBUTORY      1
 369 #define EXCPT_PF                2
 370
 371 static int exception_class(int vector)
 372 {
 373         switch (vector) {
 374         case PF_VECTOR:
 375                 return EXCPT_PF;
 376         case DE_VECTOR:
 377         case TS_VECTOR:
 378         case NP_VECTOR:
 379         case SS_VECTOR:
 380         case GP_VECTOR:
 381                 return EXCPT_CONTRIBUTORY;
 382         default:
 383                 break;
 384         }
 385         return EXCPT_BENIGN;
 386 }
 387
 388 #define EXCPT_FAULT             0
 389 #define EXCPT_TRAP              1
 390 #define EXCPT_ABORT             2
 391 #define EXCPT_INTERRUPT         3
 392
 393 static int exception_type(int vector)
 394 {
 395         unsigned int mask;
 396
 397         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
 398                 return EXCPT_INTERRUPT;
 399
 400         mask = 1 << vector;
 401
 402         /* #DB is trap, as instruction watchpoints are handled elsewhere */
 403         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
 404                 return EXCPT_TRAP;
 405
 406         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
 407                 return EXCPT_ABORT;
 408
 409         /* Reserved exceptions will result in fault */
 410         return EXCPT_FAULT;
 411 }
 412
 413 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
 414 {
 415         unsigned nr = vcpu->arch.exception.nr;
 416         bool has_payload = vcpu->arch.exception.has_payload;
 417         unsigned long payload = vcpu->arch.exception.payload;
 418
 419         if (!has_payload)
 420                 return;
 421
 422         switch (nr) {
 423         case DB_VECTOR:
 424                 /*
 425                  * "Certain debug exceptions may clear bit 0-3.  The
 426                  * remaining contents of the DR6 register are never
 427                  * cleared by the processor".
 428                  */
 429                 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
 430                 /*
 431                  * DR6.RTM is set by all #DB exceptions that don't clear it.
 432                  */
 433                 vcpu->arch.dr6 |= DR6_RTM;
 434                 vcpu->arch.dr6 |= payload;
 435                 /*
 436                  * Bit 16 should be set in the payload whenever the #DB
 437                  * exception should clear DR6.RTM. This makes the payload
 438                  * compatible with the pending debug exceptions under VMX.
 439                  * Though not currently documented in the SDM, this also
 440                  * makes the payload compatible with the exit qualification
 441                  * for #DB exceptions under VMX.
 442                  */
 443                 vcpu->arch.dr6 ^= payload & DR6_RTM;
 444                 break;
 445         case PF_VECTOR:
 446                 vcpu->arch.cr2 = payload;
 447                 break;
 448         }
 449
 450         vcpu->arch.exception.has_payload = false;
 451         vcpu->arch.exception.payload = 0;
 452 }
 453 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
 454
 455 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
 456                 unsigned nr, bool has_error, u32 error_code,
 457                 bool has_payload, unsigned long payload, bool reinject)
 458 {
 459         u32 prev_nr;
 460         int class1, class2;
 461
 462         kvm_make_request(KVM_REQ_EVENT, vcpu);
 463
 464         if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
 465         queue:
 466                 if (has_error && !is_protmode(vcpu))
 467                         has_error = false;
 468                 if (reinject) {
 469                         /*
 470                          * On vmentry, vcpu->arch.exception.pending is only
 471                          * true if an event injection was blocked by
 472                          * nested_run_pending.  In that case, however,
 473                          * vcpu_enter_guest requests an immediate exit,
 474                          * and the guest shouldn't proceed far enough to
 475                          * need reinjection.
 476                          */
 477                         WARN_ON_ONCE(vcpu->arch.exception.pending);
 478                         vcpu->arch.exception.injected = true;
 479                         if (WARN_ON_ONCE(has_payload)) {
 480                                 /*
 481                                  * A reinjected event has already
 482                                  * delivered its payload.
 483                                  */
 484                                 has_payload = false;
 485                                 payload = 0;
 486                         }
 487                 } else {
 488                         vcpu->arch.exception.pending = true;
 489                         vcpu->arch.exception.injected = false;
 490                 }
 491                 vcpu->arch.exception.has_error_code = has_error;
 492                 vcpu->arch.exception.nr = nr;
 493                 vcpu->arch.exception.error_code = error_code;
 494                 vcpu->arch.exception.has_payload = has_payload;
 495                 vcpu->arch.exception.payload = payload;
 496                 /*
 497                  * In guest mode, payload delivery should be deferred,
 498                  * so that the L1 hypervisor can intercept #PF before
 499                  * CR2 is modified (or intercept #DB before DR6 is
 500                  * modified under nVMX).  However, for ABI
 501                  * compatibility with KVM_GET_VCPU_EVENTS and
 502                  * KVM_SET_VCPU_EVENTS, we can't delay payload
 503                  * delivery unless userspace has enabled this
 504                  * functionality via the per-VM capability,
 505                  * KVM_CAP_EXCEPTION_PAYLOAD.
 506                  */
 507                 if (!vcpu->kvm->arch.exception_payload_enabled ||
 508                     !is_guest_mode(vcpu))
 509                         kvm_deliver_exception_payload(vcpu);
 510                 return;
 511         }
 512
 513         /* to check exception */
 514         prev_nr = vcpu->arch.exception.nr;
 515         if (prev_nr == DF_VECTOR) {
 516                 /* triple fault -> shutdown */
 517                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
 518                 return;
 519         }
 520         class1 = exception_class(prev_nr);
 521         class2 = exception_class(nr);
 522         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
 523                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
 524                 /*
 525                  * Generate double fault per SDM Table 5-5.  Set
 526                  * exception.pending = true so that the double fault
 527                  * can trigger a nested vmexit.
 528                  */
 529                 vcpu->arch.exception.pending = true;
 530                 vcpu->arch.exception.injected = false;
 531                 vcpu->arch.exception.has_error_code = true;
 532                 vcpu->arch.exception.nr = DF_VECTOR;
 533                 vcpu->arch.exception.error_code = 0;
 534                 vcpu->arch.exception.has_payload = false;
 535                 vcpu->arch.exception.payload = 0;
 536         } else
 537                 /* replace previous exception with a new one in a hope
 538                    that instruction re-execution will regenerate lost
 539                    exception */
 540                 goto queue;
 541 }
 542
 543 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 544 {
 545         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
 546 }
 547 EXPORT_SYMBOL_GPL(kvm_queue_exception);
 548
 549 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 550 {
 551         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
 552 }
 553 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
 554
 555 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
 556                                   unsigned long payload)
 557 {
 558         kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
 559 }
 560
 561 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
 562                                     u32 error_code, unsigned long payload)
 563 {
 564         kvm_multiple_exception(vcpu, nr, true, error_code,
 565                                true, payload, false);
 566 }
 567
 568 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
 569 {
 570         if (err)
 571                 kvm_inject_gp(vcpu, 0);
 572         else
 573                 return kvm_skip_emulated_instruction(vcpu);
 574
 575         return 1;
 576 }
 577 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
 578
 579 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 580 {
 581         ++vcpu->stat.pf_guest;
 582         vcpu->arch.exception.nested_apf =
 583                 is_guest_mode(vcpu) && fault->async_page_fault;
 584         if (vcpu->arch.exception.nested_apf) {
 585                 vcpu->arch.apf.nested_apf_token = fault->address;
 586                 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
 587         } else {
 588                 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
 589                                         fault->address);
 590         }
 591 }
 592 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
 593
 594 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 595 {
 596         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
 597                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
 598         else
 599                 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
 600
 601         return fault->nested_page_fault;
 602 }
 603
 604 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
 605 {
 606         atomic_inc(&vcpu->arch.nmi_queued);
 607         kvm_make_request(KVM_REQ_NMI, vcpu);
 608 }
 609 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
 610
 611 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 612 {
 613         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
 614 }
 615 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
 616
 617 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 618 {
 619         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
 620 }
 621 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
 622
 623 /*
 624  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
 625  * a #GP and return false.
 626  */
 627 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
 628 {
 629         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
 630                 return true;
 631         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
 632         return false;
 633 }
 634 EXPORT_SYMBOL_GPL(kvm_require_cpl);
 635
 636 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
 637 {
 638         if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 639                 return true;
 640
 641         kvm_queue_exception(vcpu, UD_VECTOR);
 642         return false;
 643 }
 644 EXPORT_SYMBOL_GPL(kvm_require_dr);
 645
 646 /*
 647  * This function will be used to read from the physical memory of the currently
 648  * running guest. The difference to kvm_vcpu_read_guest_page is that this function
 649  * can read from guest physical or from the guest's guest physical memory.
 650  */
 651 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 652                             gfn_t ngfn, void *data, int offset, int len,
 653                             u32 access)
 654 {
 655         struct x86_exception exception;
 656         gfn_t real_gfn;
 657         gpa_t ngpa;
 658
 659         ngpa     = gfn_to_gpa(ngfn);
 660         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
 661         if (real_gfn == UNMAPPED_GVA)
 662                 return -EFAULT;
 663
 664         real_gfn = gpa_to_gfn(real_gfn);
 665
 666         return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
 667 }
 668 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
 669
 670 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
 671                                void *data, int offset, int len, u32 access)
 672 {
 673         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
 674                                        data, offset, len, access);
 675 }
 676
 677 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
 678 {
 679         return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
 680                rsvd_bits(1, 2);
 681 }
 682
 683 /*
 684  * Load the pae pdptrs.  Return 1 if they are all valid, 0 otherwise.
 685  */
 686 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
 687 {
 688         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
 689         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
 690         int i;
 691         int ret;
 692         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
 693
 694         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
 695                                       offset * sizeof(u64), sizeof(pdpte),
 696                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
 697         if (ret < 0) {
 698                 ret = 0;
 699                 goto out;
 700         }
 701         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
 702                 if ((pdpte[i] & PT_PRESENT_MASK) &&
 703                     (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
 704                         ret = 0;
 705                         goto out;
 706                 }
 707         }
 708         ret = 1;
 709
 710         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
 711         __set_bit(VCPU_EXREG_PDPTR,
 712                   (unsigned long *)&vcpu->arch.regs_avail);
 713         __set_bit(VCPU_EXREG_PDPTR,
 714                   (unsigned long *)&vcpu->arch.regs_dirty);
 715 out:
 716
 717         return ret;
 718 }
 719 EXPORT_SYMBOL_GPL(load_pdptrs);
 720
 721 bool pdptrs_changed(struct kvm_vcpu *vcpu)
 722 {
 723         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
 724         bool changed = true;
 725         int offset;
 726         gfn_t gfn;
 727         int r;
 728
 729         if (!is_pae_paging(vcpu))
 730                 return false;
 731
 732         if (!test_bit(VCPU_EXREG_PDPTR,
 733                       (unsigned long *)&vcpu->arch.regs_avail))
 734                 return true;
 735
 736         gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
 737         offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
 738         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
 739                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
 740         if (r < 0)
 741                 goto out;
 742         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
 743 out:
 744
 745         return changed;
 746 }
 747 EXPORT_SYMBOL_GPL(pdptrs_changed);
 748
 749 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 750 {
 751         unsigned long old_cr0 = kvm_read_cr0(vcpu);
 752         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
 753
 754         cr0 |= X86_CR0_ET;
 755
 756 #ifdef CONFIG_X86_64
 757         if (cr0 & 0xffffffff00000000UL)
 758                 return 1;
 759 #endif
 760
 761         cr0 &= ~CR0_RESERVED_BITS;
 762
 763         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
 764                 return 1;
 765
 766         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
 767                 return 1;
 768
 769         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 770 #ifdef CONFIG_X86_64
 771                 if ((vcpu->arch.efer & EFER_LME)) {
 772                         int cs_db, cs_l;
 773
 774                         if (!is_pae(vcpu))
 775                                 return 1;
 776                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
 777                         if (cs_l)
 778                                 return 1;
 779                 } else
 780 #endif
 781                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 782                                                  kvm_read_cr3(vcpu)))
 783                         return 1;
 784         }
 785
 786         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
 787                 return 1;
 788
 789         kvm_x86_ops->set_cr0(vcpu, cr0);
 790
 791         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
 792                 kvm_clear_async_pf_completion_queue(vcpu);
 793                 kvm_async_pf_hash_reset(vcpu);
 794         }
 795
 796         if ((cr0 ^ old_cr0) & update_bits)
 797                 kvm_mmu_reset_context(vcpu);
 798
 799         if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
 800             kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
 801             !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
 802                 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
 803
 804         return 0;
 805 }
 806 EXPORT_SYMBOL_GPL(kvm_set_cr0);
 807
 808 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 809 {
 810         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
 811 }
 812 EXPORT_SYMBOL_GPL(kvm_lmsw);
 813
 814 void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
 815 {
 816         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
 817                         !vcpu->guest_xcr0_loaded) {
 818                 /* kvm_set_xcr() also depends on this */
 819                 if (vcpu->arch.xcr0 != host_xcr0)
 820                         xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
 821                 vcpu->guest_xcr0_loaded = 1;
 822         }
 823 }
 824 EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
 825
 826 void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
 827 {
 828         if (vcpu->guest_xcr0_loaded) {
 829                 if (vcpu->arch.xcr0 != host_xcr0)
 830                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
 831                 vcpu->guest_xcr0_loaded = 0;
 832         }
 833 }
 834 EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
 835
 836 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 837 {
 838         u64 xcr0 = xcr;
 839         u64 old_xcr0 = vcpu->arch.xcr0;
 840         u64 valid_bits;
 841
 842         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
 843         if (index != XCR_XFEATURE_ENABLED_MASK)
 844                 return 1;
 845         if (!(xcr0 & XFEATURE_MASK_FP))
 846                 return 1;
 847         if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
 848                 return 1;
 849
 850         /*
 851          * Do not allow the guest to set bits that we do not support
 852          * saving.  However, xcr0 bit 0 is always set, even if the
 853          * emulated CPU does not support XSAVE (see fx_init).
 854          */
 855         valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
 856         if (xcr0 & ~valid_bits)
 857                 return 1;
 858
 859         if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
 860             (!(xcr0 & XFEATURE_MASK_BNDCSR)))
 861                 return 1;
 862
 863         if (xcr0 & XFEATURE_MASK_AVX512) {
 864                 if (!(xcr0 & XFEATURE_MASK_YMM))
 865                         return 1;
 866                 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
 867                         return 1;
 868         }
 869         vcpu->arch.xcr0 = xcr0;
 870
 871         if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
 872                 kvm_update_cpuid(vcpu);
 873         return 0;
 874 }
 875
 876 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 877 {
 878         if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
 879             __kvm_set_xcr(vcpu, index, xcr)) {
 880                 kvm_inject_gp(vcpu, 0);
 881                 return 1;
 882         }
 883         return 0;
 884 }
 885 EXPORT_SYMBOL_GPL(kvm_set_xcr);
 886
 887 static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 888 {
 889         if (cr4 & CR4_RESERVED_BITS)
 890                 return -EINVAL;
 891
 892         if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
 893                 return -EINVAL;
 894
 895         if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
 896                 return -EINVAL;
 897
 898         if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
 899                 return -EINVAL;
 900
 901         if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
 902                 return -EINVAL;
 903
 904         if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
 905                 return -EINVAL;
 906
 907         if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
 908                 return -EINVAL;
 909
 910         if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
 911                 return -EINVAL;
 912
 913         return 0;
 914 }
 915
 916 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 917 {
 918         unsigned long old_cr4 = kvm_read_cr4(vcpu);
 919         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
 920                                    X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
 921
 922         if (kvm_valid_cr4(vcpu, cr4))
 923                 return 1;
 924
 925         if (is_long_mode(vcpu)) {
 926                 if (!(cr4 & X86_CR4_PAE))
 927                         return 1;
 928         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
 929                    && ((cr4 ^ old_cr4) & pdptr_bits)
 930                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 931                                    kvm_read_cr3(vcpu)))
 932                 return 1;
 933
 934         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
 935                 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
 936                         return 1;
 937
 938                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
 939                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
 940                         return 1;
 941         }
 942
 943         if (kvm_x86_ops->set_cr4(vcpu, cr4))
 944                 return 1;
 945
 946         if (((cr4 ^ old_cr4) & pdptr_bits) ||
 947             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
 948                 kvm_mmu_reset_context(vcpu);
 949
 950         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
 951                 kvm_update_cpuid(vcpu);
 952
 953         return 0;
 954 }
 955 EXPORT_SYMBOL_GPL(kvm_set_cr4);
 956
 957 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
 958 {
 959         bool skip_tlb_flush = false;
 960 #ifdef CONFIG_X86_64
 961         bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
 962
 963         if (pcid_enabled) {
 964                 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
 965                 cr3 &= ~X86_CR3_PCID_NOFLUSH;
 966         }
 967 #endif
 968
 969         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
 970                 if (!skip_tlb_flush) {
 971                         kvm_mmu_sync_roots(vcpu);
 972                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 973                 }
 974                 return 0;
 975         }
 976
 977         if (is_long_mode(vcpu) &&
 978             (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
 979                 return 1;
 980         else if (is_pae_paging(vcpu) &&
 981                  !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
 982                 return 1;
 983
 984         kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
 985         vcpu->arch.cr3 = cr3;
 986         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
 987
 988         return 0;
 989 }
 990 EXPORT_SYMBOL_GPL(kvm_set_cr3);
 991
 992 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
 993 {
 994         if (cr8 & CR8_RESERVED_BITS)
 995                 return 1;
 996         if (lapic_in_kernel(vcpu))
 997                 kvm_lapic_set_tpr(vcpu, cr8);
 998         else
 999                 vcpu->arch.cr8 = cr8;
1000         return 0;
1001 }
1002 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1003
1004 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1005 {
1006         if (lapic_in_kernel(vcpu))
1007                 return kvm_lapic_get_cr8(vcpu);
1008         else
1009                 return vcpu->arch.cr8;
1010 }
1011 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1012
1013 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1014 {
1015         int i;
1016
1017         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1018                 for (i = 0; i < KVM_NR_DB_REGS; i++)
1019                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1020                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1021         }
1022 }
1023
1024 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1025 {
1026         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1027                 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1028 }
1029
1030 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1031 {
1032         unsigned long dr7;
1033
1034         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1035                 dr7 = vcpu->arch.guest_debug_dr7;
1036         else
1037                 dr7 = vcpu->arch.dr7;
1038         kvm_x86_ops->set_dr7(vcpu, dr7);
1039         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1040         if (dr7 & DR7_BP_EN_MASK)
1041                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1042 }
1043
1044 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1045 {
1046         u64 fixed = DR6_FIXED_1;
1047
1048         if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1049                 fixed |= DR6_RTM;
1050         return fixed;
1051 }
1052
1053 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1054 {
1055         switch (dr) {
1056         case 0 ... 3:
1057                 vcpu->arch.db[dr] = val;
1058                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1059                         vcpu->arch.eff_db[dr] = val;
1060                 break;
1061         case 4:
1062                 /* fall through */
1063         case 6:
1064                 if (val & 0xffffffff00000000ULL)
1065                         return -1; /* #GP */
1066                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1067                 kvm_update_dr6(vcpu);
1068                 break;
1069         case 5:
1070                 /* fall through */
1071         default: /* 7 */
1072                 if (val & 0xffffffff00000000ULL)
1073                         return -1; /* #GP */
1074                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1075                 kvm_update_dr7(vcpu);
1076                 break;
1077         }
1078
1079         return 0;
1080 }
1081
1082 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1083 {
1084         if (__kvm_set_dr(vcpu, dr, val)) {
1085                 kvm_inject_gp(vcpu, 0);
1086                 return 1;
1087         }
1088         return 0;
1089 }
1090 EXPORT_SYMBOL_GPL(kvm_set_dr);
1091
1092 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1093 {
1094         switch (dr) {
1095         case 0 ... 3:
1096                 *val = vcpu->arch.db[dr];
1097                 break;
1098         case 4:
1099                 /* fall through */
1100         case 6:
1101                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1102                         *val = vcpu->arch.dr6;
1103                 else
1104                         *val = kvm_x86_ops->get_dr6(vcpu);
1105                 break;
1106         case 5:
1107                 /* fall through */
1108         default: /* 7 */
1109                 *val = vcpu->arch.dr7;
1110                 break;
1111         }
1112         return 0;
1113 }
1114 EXPORT_SYMBOL_GPL(kvm_get_dr);
1115
1116 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1117 {
1118         u32 ecx = kvm_rcx_read(vcpu);
1119         u64 data;
1120         int err;
1121
1122         err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1123         if (err)
1124                 return err;
1125         kvm_rax_write(vcpu, (u32)data);
1126         kvm_rdx_write(vcpu, data >> 32);
1127         return err;
1128 }
1129 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1130
1131 /*
1132  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1133  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1134  *
1135  * This list is modified at module load time to reflect the
1136  * capabilities of the host cpu. This capabilities test skips MSRs that are
1137  * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1138  * may depend on host virtualization features rather than host cpu features.
1139  */
1140
1141 static u32 msrs_to_save[] = {
1142         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1143         MSR_STAR,
1144 #ifdef CONFIG_X86_64
1145         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1146 #endif
1147         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1148         MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1149         MSR_IA32_SPEC_CTRL,
1150         MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1151         MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1152         MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1153         MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1154         MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1155         MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1156         MSR_IA32_UMWAIT_CONTROL,
1157
1158         MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1159         MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1160         MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1161         MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1162         MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1163         MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1164         MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1165         MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1166         MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1167         MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1168         MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1169         MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1170         MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1171         MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1172         MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1173         MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1174         MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1175         MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1176         MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1177         MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1178         MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1179         MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1180 };
1181
1182 static unsigned num_msrs_to_save;
1183
1184 static u32 emulated_msrs[] = {
1185         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1186         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1187         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1188         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1189         HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1190         HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1191         HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1192         HV_X64_MSR_RESET,
1193         HV_X64_MSR_VP_INDEX,
1194         HV_X64_MSR_VP_RUNTIME,
1195         HV_X64_MSR_SCONTROL,
1196         HV_X64_MSR_STIMER0_CONFIG,
1197         HV_X64_MSR_VP_ASSIST_PAGE,
1198         HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1199         HV_X64_MSR_TSC_EMULATION_STATUS,
1200
1201         MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1202         MSR_KVM_PV_EOI_EN,
1203
1204         MSR_IA32_TSC_ADJUST,
1205         MSR_IA32_TSCDEADLINE,
1206         MSR_IA32_ARCH_CAPABILITIES,
1207         MSR_IA32_MISC_ENABLE,
1208         MSR_IA32_MCG_STATUS,
1209         MSR_IA32_MCG_CTL,
1210         MSR_IA32_MCG_EXT_CTL,
1211         MSR_IA32_SMBASE,
1212         MSR_SMI_COUNT,
1213         MSR_PLATFORM_INFO,
1214         MSR_MISC_FEATURES_ENABLES,
1215         MSR_AMD64_VIRT_SPEC_CTRL,
1216         MSR_IA32_POWER_CTL,
1217
1218         /*
1219          * The following list leaves out MSRs whose values are determined
1220          * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1221          * We always support the "true" VMX control MSRs, even if the host
1222          * processor does not, so I am putting these registers here rather
1223          * than in msrs_to_save.
1224          */
1225         MSR_IA32_VMX_BASIC,
1226         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1227         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1228         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1229         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1230         MSR_IA32_VMX_MISC,
1231         MSR_IA32_VMX_CR0_FIXED0,
1232         MSR_IA32_VMX_CR4_FIXED0,
1233         MSR_IA32_VMX_VMCS_ENUM,
1234         MSR_IA32_VMX_PROCBASED_CTLS2,
1235         MSR_IA32_VMX_EPT_VPID_CAP,
1236         MSR_IA32_VMX_VMFUNC,
1237
1238         MSR_K7_HWCR,
1239         MSR_KVM_POLL_CONTROL,
1240 };
1241
1242 static unsigned num_emulated_msrs;
1243
1244 /*
1245  * List of msr numbers which are used to expose MSR-based features that
1246  * can be used by a hypervisor to validate requested CPU features.
1247  */
1248 static u32 msr_based_features[] = {
1249         MSR_IA32_VMX_BASIC,
1250         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1251         MSR_IA32_VMX_PINBASED_CTLS,
1252         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1253         MSR_IA32_VMX_PROCBASED_CTLS,
1254         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1255         MSR_IA32_VMX_EXIT_CTLS,
1256         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1257         MSR_IA32_VMX_ENTRY_CTLS,
1258         MSR_IA32_VMX_MISC,
1259         MSR_IA32_VMX_CR0_FIXED0,
1260         MSR_IA32_VMX_CR0_FIXED1,
1261         MSR_IA32_VMX_CR4_FIXED0,
1262         MSR_IA32_VMX_CR4_FIXED1,
1263         MSR_IA32_VMX_VMCS_ENUM,
1264         MSR_IA32_VMX_PROCBASED_CTLS2,
1265         MSR_IA32_VMX_EPT_VPID_CAP,
1266         MSR_IA32_VMX_VMFUNC,
1267
1268         MSR_F10H_DECFG,
1269         MSR_IA32_UCODE_REV,
1270         MSR_IA32_ARCH_CAPABILITIES,
1271 };
1272
1273 static unsigned int num_msr_based_features;
1274
1275 static u64 kvm_get_arch_capabilities(void)
1276 {
1277         u64 data = 0;
1278
1279         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1280                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1281
1282         /*
1283          * If we're doing cache flushes (either "always" or "cond")
1284          * we will do one whenever the guest does a vmlaunch/vmresume.
1285          * If an outer hypervisor is doing the cache flush for us
1286          * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1287          * capability to the guest too, and if EPT is disabled we're not
1288          * vulnerable.  Overall, only VMENTER_L1D_FLUSH_NEVER will
1289          * require a nested hypervisor to do a flush of its own.
1290          */
1291         if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1292                 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1293
1294         if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1295                 data |= ARCH_CAP_RDCL_NO;
1296         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1297                 data |= ARCH_CAP_SSB_NO;
1298         if (!boot_cpu_has_bug(X86_BUG_MDS))
1299                 data |= ARCH_CAP_MDS_NO;
1300
1301         return data;
1302 }
1303
1304 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1305 {
1306         switch (msr->index) {
1307         case MSR_IA32_ARCH_CAPABILITIES:
1308                 msr->data = kvm_get_arch_capabilities();
1309                 break;
1310         case MSR_IA32_UCODE_REV:
1311                 rdmsrl_safe(msr->index, &msr->data);
1312                 break;
1313         default:
1314                 if (kvm_x86_ops->get_msr_feature(msr))
1315                         return 1;
1316         }
1317         return 0;
1318 }
1319
1320 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1321 {
1322         struct kvm_msr_entry msr;
1323         int r;
1324
1325         msr.index = index;
1326         r = kvm_get_msr_feature(&msr);
1327         if (r)
1328                 return r;
1329
1330         *data = msr.data;
1331
1332         return 0;
1333 }
1334
1335 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1336 {
1337         if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1338                 return false;
1339
1340         if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1341                 return false;
1342
1343         if (efer & (EFER_LME | EFER_LMA) &&
1344             !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1345                 return false;
1346
1347         if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1348                 return false;
1349
1350         return true;
1351
1352 }
1353 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1354 {
1355         if (efer & efer_reserved_bits)
1356                 return false;
1357
1358         return __kvm_valid_efer(vcpu, efer);
1359 }
1360 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1361
1362 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1363 {
1364         u64 old_efer = vcpu->arch.efer;
1365         u64 efer = msr_info->data;
1366
1367         if (efer & efer_reserved_bits)
1368                 return 1;
1369
1370         if (!msr_info->host_initiated) {
1371                 if (!__kvm_valid_efer(vcpu, efer))
1372                         return 1;
1373
1374                 if (is_paging(vcpu) &&
1375                     (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1376                         return 1;
1377         }
1378
1379         efer &= ~EFER_LMA;
1380         efer |= vcpu->arch.efer & EFER_LMA;
1381
1382         kvm_x86_ops->set_efer(vcpu, efer);
1383
1384         /* Update reserved bits */
1385         if ((efer ^ old_efer) & EFER_NX)
1386                 kvm_mmu_reset_context(vcpu);
1387
1388         return 0;
1389 }
1390
1391 void kvm_enable_efer_bits(u64 mask)
1392 {
1393        efer_reserved_bits &= ~mask;
1394 }
1395 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1396
1397 /*
1398  * Write @data into the MSR specified by @index.  Select MSR specific fault
1399  * checks are bypassed if @host_initiated is %true.
1400  * Returns 0 on success, non-0 otherwise.
1401  * Assumes vcpu_load() was already called.
1402  */
1403 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1404                          bool host_initiated)
1405 {
1406         struct msr_data msr;
1407
1408         switch (index) {
1409         case MSR_FS_BASE:
1410         case MSR_GS_BASE:
1411         case MSR_KERNEL_GS_BASE:
1412         case MSR_CSTAR:
1413         case MSR_LSTAR:
1414                 if (is_noncanonical_address(data, vcpu))
1415                         return 1;
1416                 break;
1417         case MSR_IA32_SYSENTER_EIP:
1418         case MSR_IA32_SYSENTER_ESP:
1419                 /*
1420                  * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1421                  * non-canonical address is written on Intel but not on
1422                  * AMD (which ignores the top 32-bits, because it does
1423                  * not implement 64-bit SYSENTER).
1424                  *
1425                  * 64-bit code should hence be able to write a non-canonical
1426                  * value on AMD.  Making the address canonical ensures that
1427                  * vmentry does not fail on Intel after writing a non-canonical
1428                  * value, and that something deterministic happens if the guest
1429                  * invokes 64-bit SYSENTER.
1430                  */
1431                 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1432         }
1433
1434         msr.data = data;
1435         msr.index = index;
1436         msr.host_initiated = host_initiated;
1437
1438         return kvm_x86_ops->set_msr(vcpu, &msr);
1439 }
1440
1441 /*
1442  * Read the MSR specified by @index into @data.  Select MSR specific fault
1443  * checks are bypassed if @host_initiated is %true.
1444  * Returns 0 on success, non-0 otherwise.
1445  * Assumes vcpu_load() was already called.
1446  */
1447 static int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1448                          bool host_initiated)
1449 {
1450         struct msr_data msr;
1451         int ret;
1452
1453         msr.index = index;
1454         msr.host_initiated = host_initiated;
1455
1456         ret = kvm_x86_ops->get_msr(vcpu, &msr);
1457         if (!ret)
1458                 *data = msr.data;
1459         return ret;
1460 }
1461
1462 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1463 {
1464         return __kvm_get_msr(vcpu, index, data, false);
1465 }
1466 EXPORT_SYMBOL_GPL(kvm_get_msr);
1467
1468 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1469 {
1470         return __kvm_set_msr(vcpu, index, data, false);
1471 }
1472 EXPORT_SYMBOL_GPL(kvm_set_msr);
1473
1474 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1475 {
1476         u32 ecx = kvm_rcx_read(vcpu);
1477         u64 data;
1478
1479         if (kvm_get_msr(vcpu, ecx, &data)) {
1480                 trace_kvm_msr_read_ex(ecx);
1481                 kvm_inject_gp(vcpu, 0);
1482                 return 1;
1483         }
1484
1485         trace_kvm_msr_read(ecx, data);
1486
1487         kvm_rax_write(vcpu, data & -1u);
1488         kvm_rdx_write(vcpu, (data >> 32) & -1u);
1489         return kvm_skip_emulated_instruction(vcpu);
1490 }
1491 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1492
1493 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1494 {
1495         u32 ecx = kvm_rcx_read(vcpu);
1496         u64 data = kvm_read_edx_eax(vcpu);
1497
1498         if (kvm_set_msr(vcpu, ecx, data)) {
1499                 trace_kvm_msr_write_ex(ecx, data);
1500                 kvm_inject_gp(vcpu, 0);
1501                 return 1;
1502         }
1503
1504         trace_kvm_msr_write(ecx, data);
1505         return kvm_skip_emulated_instruction(vcpu);
1506 }
1507 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1508
1509 /*
1510  * Adapt set_msr() to msr_io()'s calling convention
1511  */
1512 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1513 {
1514         return __kvm_get_msr(vcpu, index, data, true);
1515 }
1516
1517 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1518 {
1519         return __kvm_set_msr(vcpu, index, *data, true);
1520 }
1521
1522 #ifdef CONFIG_X86_64
1523 struct pvclock_gtod_data {
1524         seqcount_t      seq;
1525
1526         struct { /* extract of a clocksource struct */
1527                 int vclock_mode;
1528                 u64     cycle_last;
1529                 u64     mask;
1530                 u32     mult;
1531                 u32     shift;
1532         } clock;
1533
1534         u64             boot_ns;
1535         u64             nsec_base;
1536         u64             wall_time_sec;
1537 };
1538
1539 static struct pvclock_gtod_data pvclock_gtod_data;
1540
1541 static void update_pvclock_gtod(struct timekeeper *tk)
1542 {
1543         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1544         u64 boot_ns;
1545
1546         boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1547
1548         write_seqcount_begin(&vdata->seq);
1549
1550         /* copy pvclock gtod data */
1551         vdata->clock.vclock_mode        = tk->tkr_mono.clock->archdata.vclock_mode;
1552         vdata->clock.cycle_last         = tk->tkr_mono.cycle_last;
1553         vdata->clock.mask               = tk->tkr_mono.mask;
1554         vdata->clock.mult               = tk->tkr_mono.mult;
1555         vdata->clock.shift              = tk->tkr_mono.shift;
1556
1557         vdata->boot_ns                  = boot_ns;
1558         vdata->nsec_base                = tk->tkr_mono.xtime_nsec;
1559
1560         vdata->wall_time_sec            = tk->xtime_sec;
1561
1562         write_seqcount_end(&vdata->seq);
1563 }
1564 #endif
1565
1566 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1567 {
1568         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1569         kvm_vcpu_kick(vcpu);
1570 }
1571
1572 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1573 {
1574         int version;
1575         int r;
1576         struct pvclock_wall_clock wc;
1577         struct timespec64 boot;
1578
1579         if (!wall_clock)
1580                 return;
1581
1582         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1583         if (r)
1584                 return;
1585
1586         if (version & 1)
1587                 ++version;  /* first time write, random junk */
1588
1589         ++version;
1590
1591         if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1592                 return;
1593
1594         /*
1595          * The guest calculates current wall clock time by adding
1596          * system time (updated by kvm_guest_time_update below) to the
1597          * wall clock specified here.  guest system time equals host
1598          * system time for us, thus we must fill in host boot time here.
1599          */
1600         getboottime64(&boot);
1601
1602         if (kvm->arch.kvmclock_offset) {
1603                 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1604                 boot = timespec64_sub(boot, ts);
1605         }
1606         wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1607         wc.nsec = boot.tv_nsec;
1608         wc.version = version;
1609
1610         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1611
1612         version++;
1613         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1614 }
1615
1616 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1617 {
1618         do_shl32_div32(dividend, divisor);
1619         return dividend;
1620 }
1621
1622 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1623                                s8 *pshift, u32 *pmultiplier)
1624 {
1625         uint64_t scaled64;
1626         int32_t  shift = 0;
1627         uint64_t tps64;
1628         uint32_t tps32;
1629
1630         tps64 = base_hz;
1631         scaled64 = scaled_hz;
1632         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1633                 tps64 >>= 1;
1634                 shift--;
1635         }
1636
1637         tps32 = (uint32_t)tps64;
1638         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1639                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1640                         scaled64 >>= 1;
1641                 else
1642                         tps32 <<= 1;
1643                 shift++;
1644         }
1645
1646         *pshift = shift;
1647         *pmultiplier = div_frac(scaled64, tps32);
1648 }
1649
1650 #ifdef CONFIG_X86_64
1651 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1652 #endif
1653
1654 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1655 static unsigned long max_tsc_khz;
1656
1657 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1658 {
1659         u64 v = (u64)khz * (1000000 + ppm);
1660         do_div(v, 1000000);
1661         return v;
1662 }
1663
1664 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1665 {
1666         u64 ratio;
1667
1668         /* Guest TSC same frequency as host TSC? */
1669         if (!scale) {
1670                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1671                 return 0;
1672         }
1673
1674         /* TSC scaling supported? */
1675         if (!kvm_has_tsc_control) {
1676                 if (user_tsc_khz > tsc_khz) {
1677                         vcpu->arch.tsc_catchup = 1;
1678                         vcpu->arch.tsc_always_catchup = 1;
1679                         return 0;
1680                 } else {
1681                         pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1682                         return -1;
1683                 }
1684         }
1685
1686         /* TSC scaling required  - calculate ratio */
1687         ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1688                                 user_tsc_khz, tsc_khz);
1689
1690         if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1691                 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1692                                     user_tsc_khz);
1693                 return -1;
1694         }
1695
1696         vcpu->arch.tsc_scaling_ratio = ratio;
1697         return 0;
1698 }
1699
1700 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1701 {
1702         u32 thresh_lo, thresh_hi;
1703         int use_scaling = 0;
1704
1705         /* tsc_khz can be zero if TSC calibration fails */
1706         if (user_tsc_khz == 0) {
1707                 /* set tsc_scaling_ratio to a safe value */
1708                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1709                 return -1;
1710         }
1711
1712         /* Compute a scale to convert nanoseconds in TSC cycles */
1713         kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1714                            &vcpu->arch.virtual_tsc_shift,
1715                            &vcpu->arch.virtual_tsc_mult);
1716         vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1717
1718         /*
1719          * Compute the variation in TSC rate which is acceptable
1720          * within the range of tolerance and decide if the
1721          * rate being applied is within that bounds of the hardware
1722          * rate.  If so, no scaling or compensation need be done.
1723          */
1724         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1725         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1726         if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1727                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1728                 use_scaling = 1;
1729         }
1730         return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1731 }
1732
1733 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1734 {
1735         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1736                                       vcpu->arch.virtual_tsc_mult,
1737                                       vcpu->arch.virtual_tsc_shift);
1738         tsc += vcpu->arch.this_tsc_write;
1739         return tsc;
1740 }
1741
1742 static inline int gtod_is_based_on_tsc(int mode)
1743 {
1744         return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1745 }
1746
1747 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1748 {
1749 #ifdef CONFIG_X86_64
1750         bool vcpus_matched;
1751         struct kvm_arch *ka = &vcpu->kvm->arch;
1752         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1753
1754         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1755                          atomic_read(&vcpu->kvm->online_vcpus));
1756
1757         /*
1758          * Once the masterclock is enabled, always perform request in
1759          * order to update it.
1760          *
1761          * In order to enable masterclock, the host clocksource must be TSC
1762          * and the vcpus need to have matched TSCs.  When that happens,
1763          * perform request to enable masterclock.
1764          */
1765         if (ka->use_master_clock ||
1766             (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1767                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1768
1769         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1770                             atomic_read(&vcpu->kvm->online_vcpus),
1771                             ka->use_master_clock, gtod->clock.vclock_mode);
1772 #endif
1773 }
1774
1775 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1776 {
1777         u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1778         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1779 }
1780
1781 /*
1782  * Multiply tsc by a fixed point number represented by ratio.
1783  *
1784  * The most significant 64-N bits (mult) of ratio represent the
1785  * integral part of the fixed point number; the remaining N bits
1786  * (frac) represent the fractional part, ie. ratio represents a fixed
1787  * point number (mult + frac * 2^(-N)).
1788  *
1789  * N equals to kvm_tsc_scaling_ratio_frac_bits.
1790  */
1791 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1792 {
1793         return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1794 }
1795
1796 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1797 {
1798         u64 _tsc = tsc;
1799         u64 ratio = vcpu->arch.tsc_scaling_ratio;
1800
1801         if (ratio != kvm_default_tsc_scaling_ratio)
1802                 _tsc = __scale_tsc(ratio, tsc);
1803
1804         return _tsc;
1805 }
1806 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1807
1808 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1809 {
1810         u64 tsc;
1811
1812         tsc = kvm_scale_tsc(vcpu, rdtsc());
1813
1814         return target_tsc - tsc;
1815 }
1816
1817 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1818 {
1819         u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1820
1821         return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1822 }
1823 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1824
1825 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1826 {
1827         vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1828 }
1829
1830 static inline bool kvm_check_tsc_unstable(void)
1831 {
1832 #ifdef CONFIG_X86_64
1833         /*
1834          * TSC is marked unstable when we're running on Hyper-V,
1835          * 'TSC page' clocksource is good.
1836          */
1837         if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1838                 return false;
1839 #endif
1840         return check_tsc_unstable();
1841 }
1842
1843 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1844 {
1845         struct kvm *kvm = vcpu->kvm;
1846         u64 offset, ns, elapsed;
1847         unsigned long flags;
1848         bool matched;
1849         bool already_matched;
1850         u64 data = msr->data;
1851         bool synchronizing = false;
1852
1853         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1854         offset = kvm_compute_tsc_offset(vcpu, data);
1855         ns = ktime_get_boottime_ns();
1856         elapsed = ns - kvm->arch.last_tsc_nsec;
1857
1858         if (vcpu->arch.virtual_tsc_khz) {
1859                 if (data == 0 && msr->host_initiated) {
1860                         /*
1861                          * detection of vcpu initialization -- need to sync
1862                          * with other vCPUs. This particularly helps to keep
1863                          * kvm_clock stable after CPU hotplug
1864                          */
1865                         synchronizing = true;
1866                 } else {
1867                         u64 tsc_exp = kvm->arch.last_tsc_write +
1868                                                 nsec_to_cycles(vcpu, elapsed);
1869                         u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1870                         /*
1871                          * Special case: TSC write with a small delta (1 second)
1872                          * of virtual cycle time against real time is
1873                          * interpreted as an attempt to synchronize the CPU.
1874                          */
1875                         synchronizing = data < tsc_exp + tsc_hz &&
1876                                         data + tsc_hz > tsc_exp;
1877                 }
1878         }
1879
1880         /*
1881          * For a reliable TSC, we can match TSC offsets, and for an unstable
1882          * TSC, we add elapsed time in this computation.  We could let the
1883          * compensation code attempt to catch up if we fall behind, but
1884          * it's better to try to match offsets from the beginning.
1885          */
1886         if (synchronizing &&
1887             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1888                 if (!kvm_check_tsc_unstable()) {
1889                         offset = kvm->arch.cur_tsc_offset;
1890                 } else {
1891                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1892                         data += delta;
1893                         offset = kvm_compute_tsc_offset(vcpu, data);
1894                 }
1895                 matched = true;
1896                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1897         } else {
1898                 /*
1899                  * We split periods of matched TSC writes into generations.
1900                  * For each generation, we track the original measured
1901                  * nanosecond time, offset, and write, so if TSCs are in
1902                  * sync, we can match exact offset, and if not, we can match
1903                  * exact software computation in compute_guest_tsc()
1904                  *
1905                  * These values are tracked in kvm->arch.cur_xxx variables.
1906                  */
1907                 kvm->arch.cur_tsc_generation++;
1908                 kvm->arch.cur_tsc_nsec = ns;
1909                 kvm->arch.cur_tsc_write = data;
1910                 kvm->arch.cur_tsc_offset = offset;
1911                 matched = false;
1912         }
1913
1914         /*
1915          * We also track th most recent recorded KHZ, write and time to
1916          * allow the matching interval to be extended at each write.
1917          */
1918         kvm->arch.last_tsc_nsec = ns;
1919         kvm->arch.last_tsc_write = data;
1920         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1921
1922         vcpu->arch.last_guest_tsc = data;
1923
1924         /* Keep track of which generation this VCPU has synchronized to */
1925         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1926         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1927         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1928
1929         if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1930                 update_ia32_tsc_adjust_msr(vcpu, offset);
1931
1932         kvm_vcpu_write_tsc_offset(vcpu, offset);
1933         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1934
1935         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1936         if (!matched) {
1937                 kvm->arch.nr_vcpus_matched_tsc = 0;
1938         } else if (!already_matched) {
1939                 kvm->arch.nr_vcpus_matched_tsc++;
1940         }
1941
1942         kvm_track_tsc_matching(vcpu);
1943         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1944 }
1945
1946 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1947
1948 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1949                                            s64 adjustment)
1950 {
1951         u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1952         kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
1953 }
1954
1955 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1956 {
1957         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1958                 WARN_ON(adjustment < 0);
1959         adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1960         adjust_tsc_offset_guest(vcpu, adjustment);
1961 }
1962
1963 #ifdef CONFIG_X86_64
1964
1965 static u64 read_tsc(void)
1966 {
1967         u64 ret = (u64)rdtsc_ordered();
1968         u64 last = pvclock_gtod_data.clock.cycle_last;
1969
1970         if (likely(ret >= last))
1971                 return ret;
1972
1973         /*
1974          * GCC likes to generate cmov here, but this branch is extremely
1975          * predictable (it's just a function of time and the likely is
1976          * very likely) and there's a data dependence, so force GCC
1977          * to generate a branch instead.  I don't barrier() because
1978          * we don't actually need a barrier, and if this function
1979          * ever gets inlined it will generate worse code.
1980          */
1981         asm volatile ("");
1982         return last;
1983 }
1984
1985 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
1986 {
1987         long v;
1988         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1989         u64 tsc_pg_val;
1990
1991         switch (gtod->clock.vclock_mode) {
1992         case VCLOCK_HVCLOCK:
1993                 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1994                                                   tsc_timestamp);
1995                 if (tsc_pg_val != U64_MAX) {
1996                         /* TSC page valid */
1997                         *mode = VCLOCK_HVCLOCK;
1998                         v = (tsc_pg_val - gtod->clock.cycle_last) &
1999                                 gtod->clock.mask;
2000                 } else {
2001                         /* TSC page invalid */
2002                         *mode = VCLOCK_NONE;
2003                 }
2004                 break;
2005         case VCLOCK_TSC:
2006                 *mode = VCLOCK_TSC;
2007                 *tsc_timestamp = read_tsc();
2008                 v = (*tsc_timestamp - gtod->clock.cycle_last) &
2009                         gtod->clock.mask;
2010                 break;
2011         default:
2012                 *mode = VCLOCK_NONE;
2013         }
2014
2015         if (*mode == VCLOCK_NONE)
2016                 *tsc_timestamp = v = 0;
2017
2018         return v * gtod->clock.mult;
2019 }
2020
2021 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
2022 {
2023         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2024         unsigned long seq;
2025         int mode;
2026         u64 ns;
2027
2028         do {
2029                 seq = read_seqcount_begin(&gtod->seq);
2030                 ns = gtod->nsec_base;
2031                 ns += vgettsc(tsc_timestamp, &mode);
2032                 ns >>= gtod->clock.shift;
2033                 ns += gtod->boot_ns;
2034         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2035         *t = ns;
2036
2037         return mode;
2038 }
2039
2040 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2041 {
2042         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2043         unsigned long seq;
2044         int mode;
2045         u64 ns;
2046
2047         do {
2048                 seq = read_seqcount_begin(&gtod->seq);
2049                 ts->tv_sec = gtod->wall_time_sec;
2050                 ns = gtod->nsec_base;
2051                 ns += vgettsc(tsc_timestamp, &mode);
2052                 ns >>= gtod->clock.shift;
2053         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2054
2055         ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2056         ts->tv_nsec = ns;
2057
2058         return mode;
2059 }
2060
2061 /* returns true if host is using TSC based clocksource */
2062 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2063 {
2064         /* checked again under seqlock below */
2065         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2066                 return false;
2067
2068         return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
2069                                                       tsc_timestamp));
2070 }
2071
2072 /* returns true if host is using TSC based clocksource */
2073 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2074                                            u64 *tsc_timestamp)
2075 {
2076         /* checked again under seqlock below */
2077         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2078                 return false;
2079
2080         return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2081 }
2082 #endif
2083
2084 /*
2085  *
2086  * Assuming a stable TSC across physical CPUS, and a stable TSC
2087  * across virtual CPUs, the following condition is possible.
2088  * Each numbered line represents an event visible to both
2089  * CPUs at the next numbered event.
2090  *
2091  * "timespecX" represents host monotonic time. "tscX" represents
2092  * RDTSC value.
2093  *
2094  *              VCPU0 on CPU0           |       VCPU1 on CPU1
2095  *
2096  * 1.  read timespec0,tsc0
2097  * 2.                                   | timespec1 = timespec0 + N
2098  *                                      | tsc1 = tsc0 + M
2099  * 3. transition to guest               | transition to guest
2100  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2101  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
2102  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2103  *
2104  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2105  *
2106  *      - ret0 < ret1
2107  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2108  *              ...
2109  *      - 0 < N - M => M < N
2110  *
2111  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2112  * always the case (the difference between two distinct xtime instances
2113  * might be smaller then the difference between corresponding TSC reads,
2114  * when updating guest vcpus pvclock areas).
2115  *
2116  * To avoid that problem, do not allow visibility of distinct
2117  * system_timestamp/tsc_timestamp values simultaneously: use a master
2118  * copy of host monotonic time values. Update that master copy
2119  * in lockstep.
2120  *
2121  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2122  *
2123  */
2124
2125 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2126 {
2127 #ifdef CONFIG_X86_64
2128         struct kvm_arch *ka = &kvm->arch;
2129         int vclock_mode;
2130         bool host_tsc_clocksource, vcpus_matched;
2131
2132         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2133                         atomic_read(&kvm->online_vcpus));
2134
2135         /*
2136          * If the host uses TSC clock, then passthrough TSC as stable
2137          * to the guest.
2138          */
2139         host_tsc_clocksource = kvm_get_time_and_clockread(
2140                                         &ka->master_kernel_ns,
2141                                         &ka->master_cycle_now);
2142
2143         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2144                                 && !ka->backwards_tsc_observed
2145                                 && !ka->boot_vcpu_runs_old_kvmclock;
2146
2147         if (ka->use_master_clock)
2148                 atomic_set(&kvm_guest_has_master_clock, 1);
2149
2150         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2151         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2152                                         vcpus_matched);
2153 #endif
2154 }
2155
2156 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2157 {
2158         kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2159 }
2160
2161 static void kvm_gen_update_masterclock(struct kvm *kvm)
2162 {
2163 #ifdef CONFIG_X86_64
2164         int i;
2165         struct kvm_vcpu *vcpu;
2166         struct kvm_arch *ka = &kvm->arch;
2167
2168         spin_lock(&ka->pvclock_gtod_sync_lock);
2169         kvm_make_mclock_inprogress_request(kvm);
2170         /* no guest entries from this point */
2171         pvclock_update_vm_gtod_copy(kvm);
2172
2173         kvm_for_each_vcpu(i, vcpu, kvm)
2174                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2175
2176         /* guest entries allowed */
2177         kvm_for_each_vcpu(i, vcpu, kvm)
2178                 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2179
2180         spin_unlock(&ka->pvclock_gtod_sync_lock);
2181 #endif
2182 }
2183
2184 u64 get_kvmclock_ns(struct kvm *kvm)
2185 {
2186         struct kvm_arch *ka = &kvm->arch;
2187         struct pvclock_vcpu_time_info hv_clock;
2188         u64 ret;
2189
2190         spin_lock(&ka->pvclock_gtod_sync_lock);
2191         if (!ka->use_master_clock) {
2192                 spin_unlock(&ka->pvclock_gtod_sync_lock);
2193                 return ktime_get_boottime_ns() + ka->kvmclock_offset;
2194         }
2195
2196         hv_clock.tsc_timestamp = ka->master_cycle_now;
2197         hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2198         spin_unlock(&ka->pvclock_gtod_sync_lock);
2199
2200         /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2201         get_cpu();
2202
2203         if (__this_cpu_read(cpu_tsc_khz)) {
2204                 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2205                                    &hv_clock.tsc_shift,
2206                                    &hv_clock.tsc_to_system_mul);
2207                 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2208         } else
2209                 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
2210
2211         put_cpu();
2212
2213         return ret;
2214 }
2215
2216 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2217 {
2218         struct kvm_vcpu_arch *vcpu = &v->arch;
2219         struct pvclock_vcpu_time_info guest_hv_clock;
2220
2221         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2222                 &guest_hv_clock, sizeof(guest_hv_clock))))
2223                 return;
2224
2225         /* This VCPU is paused, but it's legal for a guest to read another
2226          * VCPU's kvmclock, so we really have to follow the specification where
2227          * it says that version is odd if data is being modified, and even after
2228          * it is consistent.
2229          *
2230          * Version field updates must be kept separate.  This is because
2231          * kvm_write_guest_cached might use a "rep movs" instruction, and
2232          * writes within a string instruction are weakly ordered.  So there
2233          * are three writes overall.
2234          *
2235          * As a small optimization, only write the version field in the first
2236          * and third write.  The vcpu->pv_time cache is still valid, because the
2237          * version field is the first in the struct.
2238          */
2239         BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2240
2241         if (guest_hv_clock.version & 1)
2242                 ++guest_hv_clock.version;  /* first time write, random junk */
2243
2244         vcpu->hv_clock.version = guest_hv_clock.version + 1;
2245         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2246                                 &vcpu->hv_clock,
2247                                 sizeof(vcpu->hv_clock.version));
2248
2249         smp_wmb();
2250
2251         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2252         vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2253
2254         if (vcpu->pvclock_set_guest_stopped_request) {
2255                 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2256                 vcpu->pvclock_set_guest_stopped_request = false;
2257         }
2258
2259         trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2260
2261         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2262                                 &vcpu->hv_clock,
2263                                 sizeof(vcpu->hv_clock));
2264
2265         smp_wmb();
2266
2267         vcpu->hv_clock.version++;
2268         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2269                                 &vcpu->hv_clock,
2270                                 sizeof(vcpu->hv_clock.version));
2271 }
2272
2273 static int kvm_guest_time_update(struct kvm_vcpu *v)
2274 {
2275         unsigned long flags, tgt_tsc_khz;
2276         struct kvm_vcpu_arch *vcpu = &v->arch;
2277         struct kvm_arch *ka = &v->kvm->arch;
2278         s64 kernel_ns;
2279         u64 tsc_timestamp, host_tsc;
2280         u8 pvclock_flags;
2281         bool use_master_clock;
2282
2283         kernel_ns = 0;
2284         host_tsc = 0;
2285
2286         /*
2287          * If the host uses TSC clock, then passthrough TSC as stable
2288          * to the guest.
2289          */
2290         spin_lock(&ka->pvclock_gtod_sync_lock);
2291         use_master_clock = ka->use_master_clock;
2292         if (use_master_clock) {
2293                 host_tsc = ka->master_cycle_now;
2294                 kernel_ns = ka->master_kernel_ns;
2295         }
2296         spin_unlock(&ka->pvclock_gtod_sync_lock);
2297
2298         /* Keep irq disabled to prevent changes to the clock */
2299         local_irq_save(flags);
2300         tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2301         if (unlikely(tgt_tsc_khz == 0)) {
2302                 local_irq_restore(flags);
2303                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2304                 return 1;
2305         }
2306         if (!use_master_clock) {
2307                 host_tsc = rdtsc();
2308                 kernel_ns = ktime_get_boottime_ns();
2309         }
2310
2311         tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2312
2313         /*
2314          * We may have to catch up the TSC to match elapsed wall clock
2315          * time for two reasons, even if kvmclock is used.
2316          *   1) CPU could have been running below the maximum TSC rate
2317          *   2) Broken TSC compensation resets the base at each VCPU
2318          *      entry to avoid unknown leaps of TSC even when running
2319          *      again on the same CPU.  This may cause apparent elapsed
2320          *      time to disappear, and the guest to stand still or run
2321          *      very slowly.
2322          */
2323         if (vcpu->tsc_catchup) {
2324                 u64 tsc = compute_guest_tsc(v, kernel_ns);
2325                 if (tsc > tsc_timestamp) {
2326                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2327                         tsc_timestamp = tsc;
2328                 }
2329         }
2330
2331         local_irq_restore(flags);
2332
2333         /* With all the info we got, fill in the values */
2334
2335         if (kvm_has_tsc_control)
2336                 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2337
2338         if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2339                 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2340                                    &vcpu->hv_clock.tsc_shift,
2341                                    &vcpu->hv_clock.tsc_to_system_mul);
2342                 vcpu->hw_tsc_khz = tgt_tsc_khz;
2343         }
2344
2345         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2346         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2347         vcpu->last_guest_tsc = tsc_timestamp;
2348
2349         /* If the host uses TSC clocksource, then it is stable */
2350         pvclock_flags = 0;
2351         if (use_master_clock)
2352                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2353
2354         vcpu->hv_clock.flags = pvclock_flags;
2355
2356         if (vcpu->pv_time_enabled)
2357                 kvm_setup_pvclock_page(v);
2358         if (v == kvm_get_vcpu(v->kvm, 0))
2359                 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2360         return 0;
2361 }
2362
2363 /*
2364  * kvmclock updates which are isolated to a given vcpu, such as
2365  * vcpu->cpu migration, should not allow system_timestamp from
2366  * the rest of the vcpus to remain static. Otherwise ntp frequency
2367  * correction applies to one vcpu's system_timestamp but not
2368  * the others.
2369  *
2370  * So in those cases, request a kvmclock update for all vcpus.
2371  * We need to rate-limit these requests though, as they can
2372  * considerably slow guests that have a large number of vcpus.
2373  * The time for a remote vcpu to update its kvmclock is bound
2374  * by the delay we use to rate-limit the updates.
2375  */
2376
2377 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2378
2379 static void kvmclock_update_fn(struct work_struct *work)
2380 {
2381         int i;
2382         struct delayed_work *dwork = to_delayed_work(work);
2383         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2384                                            kvmclock_update_work);
2385         struct kvm *kvm = container_of(ka, struct kvm, arch);
2386         struct kvm_vcpu *vcpu;
2387
2388         kvm_for_each_vcpu(i, vcpu, kvm) {
2389                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2390                 kvm_vcpu_kick(vcpu);
2391         }
2392 }
2393
2394 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2395 {
2396         struct kvm *kvm = v->kvm;
2397
2398         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2399         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2400                                         KVMCLOCK_UPDATE_DELAY);
2401 }
2402
2403 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2404
2405 static void kvmclock_sync_fn(struct work_struct *work)
2406 {
2407         struct delayed_work *dwork = to_delayed_work(work);
2408         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2409                                            kvmclock_sync_work);
2410         struct kvm *kvm = container_of(ka, struct kvm, arch);
2411
2412         if (!kvmclock_periodic_sync)
2413                 return;
2414
2415         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2416         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2417                                         KVMCLOCK_SYNC_PERIOD);
2418 }
2419
2420 /*
2421  * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2422  */
2423 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2424 {
2425         /* McStatusWrEn enabled? */
2426         if (guest_cpuid_is_amd(vcpu))
2427                 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2428
2429         return false;
2430 }
2431
2432 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2433 {
2434         u64 mcg_cap = vcpu->arch.mcg_cap;
2435         unsigned bank_num = mcg_cap & 0xff;
2436         u32 msr = msr_info->index;
2437         u64 data = msr_info->data;
2438
2439         switch (msr) {
2440         case MSR_IA32_MCG_STATUS:
2441                 vcpu->arch.mcg_status = data;
2442                 break;
2443         case MSR_IA32_MCG_CTL:
2444                 if (!(mcg_cap & MCG_CTL_P) &&
2445                     (data || !msr_info->host_initiated))
2446                         return 1;
2447                 if (data != 0 && data != ~(u64)0)
2448                         return 1;
2449                 vcpu->arch.mcg_ctl = data;
2450                 break;
2451         default:
2452                 if (msr >= MSR_IA32_MC0_CTL &&
2453                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2454                         u32 offset = msr - MSR_IA32_MC0_CTL;
2455                         /* only 0 or all 1s can be written to IA32_MCi_CTL
2456                          * some Linux kernels though clear bit 10 in bank 4 to
2457                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2458                          * this to avoid an uncatched #GP in the guest
2459                          */
2460                         if ((offset & 0x3) == 0 &&
2461                             data != 0 && (data | (1 << 10)) != ~(u64)0)
2462                                 return -1;
2463
2464                         /* MCi_STATUS */
2465                         if (!msr_info->host_initiated &&
2466                             (offset & 0x3) == 1 && data != 0) {
2467                                 if (!can_set_mci_status(vcpu))
2468                                         return -1;
2469                         }
2470
2471                         vcpu->arch.mce_banks[offset] = data;
2472                         break;
2473                 }
2474                 return 1;
2475         }
2476         return 0;
2477 }
2478
2479 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2480 {
2481         struct kvm *kvm = vcpu->kvm;
2482         int lm = is_long_mode(vcpu);
2483         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2484                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2485         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2486                 : kvm->arch.xen_hvm_config.blob_size_32;
2487         u32 page_num = data & ~PAGE_MASK;
2488         u64 page_addr = data & PAGE_MASK;
2489         u8 *page;
2490         int r;
2491
2492         r = -E2BIG;
2493         if (page_num >= blob_size)
2494                 goto out;
2495         r = -ENOMEM;
2496         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2497         if (IS_ERR(page)) {
2498                 r = PTR_ERR(page);
2499                 goto out;
2500         }
2501         if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2502                 goto out_free;
2503         r = 0;
2504 out_free:
2505         kfree(page);
2506 out:
2507         return r;
2508 }
2509
2510 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2511 {
2512         gpa_t gpa = data & ~0x3f;
2513
2514         /* Bits 3:5 are reserved, Should be zero */
2515         if (data & 0x38)
2516                 return 1;
2517
2518         vcpu->arch.apf.msr_val = data;
2519
2520         if (!(data & KVM_ASYNC_PF_ENABLED)) {
2521                 kvm_clear_async_pf_completion_queue(vcpu);
2522                 kvm_async_pf_hash_reset(vcpu);
2523                 return 0;
2524         }
2525
2526         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2527                                         sizeof(u32)))
2528                 return 1;
2529
2530         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2531         vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2532         kvm_async_pf_wakeup_all(vcpu);
2533         return 0;
2534 }
2535
2536 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2537 {
2538         vcpu->arch.pv_time_enabled = false;
2539 }
2540
2541 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2542 {
2543         ++vcpu->stat.tlb_flush;
2544         kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2545 }
2546
2547 static void record_steal_time(struct kvm_vcpu *vcpu)
2548 {
2549         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2550                 return;
2551
2552         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2553                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2554                 return;
2555
2556         /*
2557          * Doing a TLB flush here, on the guest's behalf, can avoid
2558          * expensive IPIs.
2559          */
2560         trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2561                 vcpu->arch.st.steal.preempted & KVM_VCPU_FLUSH_TLB);
2562         if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2563                 kvm_vcpu_flush_tlb(vcpu, false);
2564
2565         if (vcpu->arch.st.steal.version & 1)
2566                 vcpu->arch.st.steal.version += 1;  /* first time write, random junk */
2567
2568         vcpu->arch.st.steal.version += 1;
2569
2570         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2571                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2572
2573         smp_wmb();
2574
2575         vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2576                 vcpu->arch.st.last_steal;
2577         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2578
2579         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2580                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2581
2582         smp_wmb();
2583
2584         vcpu->arch.st.steal.version += 1;
2585
2586         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2587                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2588 }
2589
2590 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2591 {
2592         bool pr = false;
2593         u32 msr = msr_info->index;
2594         u64 data = msr_info->data;
2595
2596         switch (msr) {
2597         case MSR_AMD64_NB_CFG:
2598         case MSR_IA32_UCODE_WRITE:
2599         case MSR_VM_HSAVE_PA:
2600         case MSR_AMD64_PATCH_LOADER:
2601         case MSR_AMD64_BU_CFG2:
2602         case MSR_AMD64_DC_CFG:
2603         case MSR_F15H_EX_CFG:
2604                 break;
2605
2606         case MSR_IA32_UCODE_REV:
2607                 if (msr_info->host_initiated)
2608                         vcpu->arch.microcode_version = data;
2609                 break;
2610         case MSR_IA32_ARCH_CAPABILITIES:
2611                 if (!msr_info->host_initiated)
2612                         return 1;
2613                 vcpu->arch.arch_capabilities = data;
2614                 break;
2615         case MSR_EFER:
2616                 return set_efer(vcpu, msr_info);
2617         case MSR_K7_HWCR:
2618                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2619                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2620                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2621
2622                 /* Handle McStatusWrEn */
2623                 if (data == BIT_ULL(18)) {
2624                         vcpu->arch.msr_hwcr = data;
2625                 } else if (data != 0) {
2626                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2627                                     data);
2628                         return 1;
2629                 }
2630                 break;
2631         case MSR_FAM10H_MMIO_CONF_BASE:
2632                 if (data != 0) {
2633                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2634                                     "0x%llx\n", data);
2635                         return 1;
2636                 }
2637                 break;
2638         case MSR_IA32_DEBUGCTLMSR:
2639                 if (!data) {
2640                         /* We support the non-activated case already */
2641                         break;
2642                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2643                         /* Values other than LBR and BTF are vendor-specific,
2644                            thus reserved and should throw a #GP */
2645                         return 1;
2646                 }
2647                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2648                             __func__, data);
2649                 break;
2650         case 0x200 ... 0x2ff:
2651                 return kvm_mtrr_set_msr(vcpu, msr, data);
2652         case MSR_IA32_APICBASE:
2653                 return kvm_set_apic_base(vcpu, msr_info);
2654         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2655                 return kvm_x2apic_msr_write(vcpu, msr, data);
2656         case MSR_IA32_TSCDEADLINE:
2657                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2658                 break;
2659         case MSR_IA32_TSC_ADJUST:
2660                 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2661                         if (!msr_info->host_initiated) {
2662                                 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2663                                 adjust_tsc_offset_guest(vcpu, adj);
2664                         }
2665                         vcpu->arch.ia32_tsc_adjust_msr = data;
2666                 }
2667                 break;
2668         case MSR_IA32_MISC_ENABLE:
2669                 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2670                     ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2671                         if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2672                                 return 1;
2673                         vcpu->arch.ia32_misc_enable_msr = data;
2674                         kvm_update_cpuid(vcpu);
2675                 } else {
2676                         vcpu->arch.ia32_misc_enable_msr = data;
2677                 }
2678                 break;
2679         case MSR_IA32_SMBASE:
2680                 if (!msr_info->host_initiated)
2681                         return 1;
2682                 vcpu->arch.smbase = data;
2683                 break;
2684         case MSR_IA32_POWER_CTL:
2685                 vcpu->arch.msr_ia32_power_ctl = data;
2686                 break;
2687         case MSR_IA32_TSC:
2688                 kvm_write_tsc(vcpu, msr_info);
2689                 break;
2690         case MSR_SMI_COUNT:
2691                 if (!msr_info->host_initiated)
2692                         return 1;
2693                 vcpu->arch.smi_count = data;
2694                 break;
2695         case MSR_KVM_WALL_CLOCK_NEW:
2696         case MSR_KVM_WALL_CLOCK:
2697                 vcpu->kvm->arch.wall_clock = data;
2698                 kvm_write_wall_clock(vcpu->kvm, data);
2699                 break;
2700         case MSR_KVM_SYSTEM_TIME_NEW:
2701         case MSR_KVM_SYSTEM_TIME: {
2702                 struct kvm_arch *ka = &vcpu->kvm->arch;
2703
2704                 kvmclock_reset(vcpu);
2705
2706                 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2707                         bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2708
2709                         if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2710                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2711
2712                         ka->boot_vcpu_runs_old_kvmclock = tmp;
2713                 }
2714
2715                 vcpu->arch.time = data;
2716                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2717
2718                 /* we verify if the enable bit is set... */
2719                 if (!(data & 1))
2720                         break;
2721
2722                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2723                      &vcpu->arch.pv_time, data & ~1ULL,
2724                      sizeof(struct pvclock_vcpu_time_info)))
2725                         vcpu->arch.pv_time_enabled = false;
2726                 else
2727                         vcpu->arch.pv_time_enabled = true;
2728
2729                 break;
2730         }
2731         case MSR_KVM_ASYNC_PF_EN:
2732                 if (kvm_pv_enable_async_pf(vcpu, data))
2733                         return 1;
2734                 break;
2735         case MSR_KVM_STEAL_TIME:
2736
2737                 if (unlikely(!sched_info_on()))
2738                         return 1;
2739
2740                 if (data & KVM_STEAL_RESERVED_MASK)
2741                         return 1;
2742
2743                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2744                                                 data & KVM_STEAL_VALID_BITS,
2745                                                 sizeof(struct kvm_steal_time)))
2746                         return 1;
2747
2748                 vcpu->arch.st.msr_val = data;
2749
2750                 if (!(data & KVM_MSR_ENABLED))
2751                         break;
2752
2753                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2754
2755                 break;
2756         case MSR_KVM_PV_EOI_EN:
2757                 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2758                         return 1;
2759                 break;
2760
2761         case MSR_KVM_POLL_CONTROL:
2762                 /* only enable bit supported */
2763                 if (data & (-1ULL << 1))
2764                         return 1;
2765
2766                 vcpu->arch.msr_kvm_poll_control = data;
2767                 break;
2768
2769         case MSR_IA32_MCG_CTL:
2770         case MSR_IA32_MCG_STATUS:
2771         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2772                 return set_msr_mce(vcpu, msr_info);
2773
2774         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2775         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2776                 pr = true; /* fall through */
2777         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2778         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2779                 if (kvm_pmu_is_valid_msr(vcpu, msr))
2780                         return kvm_pmu_set_msr(vcpu, msr_info);
2781
2782                 if (pr || data != 0)
2783                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2784                                     "0x%x data 0x%llx\n", msr, data);
2785                 break;
2786         case MSR_K7_CLK_CTL:
2787                 /*
2788                  * Ignore all writes to this no longer documented MSR.
2789                  * Writes are only relevant for old K7 processors,
2790                  * all pre-dating SVM, but a recommended workaround from
2791                  * AMD for these chips. It is possible to specify the
2792                  * affected processor models on the command line, hence
2793                  * the need to ignore the workaround.
2794                  */
2795                 break;
2796         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2797         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2798         case HV_X64_MSR_CRASH_CTL:
2799         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2800         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2801         case HV_X64_MSR_TSC_EMULATION_CONTROL:
2802         case HV_X64_MSR_TSC_EMULATION_STATUS:
2803                 return kvm_hv_set_msr_common(vcpu, msr, data,
2804                                              msr_info->host_initiated);
2805         case MSR_IA32_BBL_CR_CTL3:
2806                 /* Drop writes to this legacy MSR -- see rdmsr
2807                  * counterpart for further detail.
2808                  */
2809                 if (report_ignored_msrs)
2810                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2811                                 msr, data);
2812                 break;
2813         case MSR_AMD64_OSVW_ID_LENGTH:
2814                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2815                         return 1;
2816                 vcpu->arch.osvw.length = data;
2817                 break;
2818         case MSR_AMD64_OSVW_STATUS:
2819                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2820                         return 1;
2821                 vcpu->arch.osvw.status = data;
2822                 break;
2823         case MSR_PLATFORM_INFO:
2824                 if (!msr_info->host_initiated ||
2825                     (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2826                      cpuid_fault_enabled(vcpu)))
2827                         return 1;
2828                 vcpu->arch.msr_platform_info = data;
2829                 break;
2830         case MSR_MISC_FEATURES_ENABLES:
2831                 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2832                     (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2833                      !supports_cpuid_fault(vcpu)))
2834                         return 1;
2835                 vcpu->arch.msr_misc_features_enables = data;
2836                 break;
2837         default:
2838                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2839                         return xen_hvm_config(vcpu, data);
2840                 if (kvm_pmu_is_valid_msr(vcpu, msr))
2841                         return kvm_pmu_set_msr(vcpu, msr_info);
2842                 if (!ignore_msrs) {
2843                         vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2844                                     msr, data);
2845                         return 1;
2846                 } else {
2847                         if (report_ignored_msrs)
2848                                 vcpu_unimpl(vcpu,
2849                                         "ignored wrmsr: 0x%x data 0x%llx\n",
2850                                         msr, data);
2851                         break;
2852                 }
2853         }
2854         return 0;
2855 }
2856 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2857
2858 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2859 {
2860         u64 data;
2861         u64 mcg_cap = vcpu->arch.mcg_cap;
2862         unsigned bank_num = mcg_cap & 0xff;
2863
2864         switch (msr) {
2865         case MSR_IA32_P5_MC_ADDR:
2866         case MSR_IA32_P5_MC_TYPE:
2867                 data = 0;
2868                 break;
2869         case MSR_IA32_MCG_CAP:
2870                 data = vcpu->arch.mcg_cap;
2871                 break;
2872         case MSR_IA32_MCG_CTL:
2873                 if (!(mcg_cap & MCG_CTL_P) && !host)
2874                         return 1;
2875                 data = vcpu->arch.mcg_ctl;
2876                 break;
2877         case MSR_IA32_MCG_STATUS:
2878                 data = vcpu->arch.mcg_status;
2879                 break;
2880         default:
2881                 if (msr >= MSR_IA32_MC0_CTL &&
2882                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2883                         u32 offset = msr - MSR_IA32_MC0_CTL;
2884                         data = vcpu->arch.mce_banks[offset];
2885                         break;
2886                 }
2887                 return 1;
2888         }
2889         *pdata = data;
2890         return 0;
2891 }
2892
2893 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2894 {
2895         switch (msr_info->index) {
2896         case MSR_IA32_PLATFORM_ID:
2897         case MSR_IA32_EBL_CR_POWERON:
2898         case MSR_IA32_DEBUGCTLMSR:
2899         case MSR_IA32_LASTBRANCHFROMIP:
2900         case MSR_IA32_LASTBRANCHTOIP:
2901         case MSR_IA32_LASTINTFROMIP:
2902         case MSR_IA32_LASTINTTOIP:
2903         case MSR_K8_SYSCFG:
2904         case MSR_K8_TSEG_ADDR:
2905         case MSR_K8_TSEG_MASK:
2906         case MSR_VM_HSAVE_PA:
2907         case MSR_K8_INT_PENDING_MSG:
2908         case MSR_AMD64_NB_CFG:
2909         case MSR_FAM10H_MMIO_CONF_BASE:
2910         case MSR_AMD64_BU_CFG2:
2911         case MSR_IA32_PERF_CTL:
2912         case MSR_AMD64_DC_CFG:
2913         case MSR_F15H_EX_CFG:
2914                 msr_info->data = 0;
2915                 break;
2916         case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
2917         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2918         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2919         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2920         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2921                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2922                         return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2923                 msr_info->data = 0;
2924                 break;
2925         case MSR_IA32_UCODE_REV:
2926                 msr_info->data = vcpu->arch.microcode_version;
2927                 break;
2928         case MSR_IA32_ARCH_CAPABILITIES:
2929                 if (!msr_info->host_initiated &&
2930                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2931                         return 1;
2932                 msr_info->data = vcpu->arch.arch_capabilities;
2933                 break;
2934         case MSR_IA32_POWER_CTL:
2935                 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
2936                 break;
2937         case MSR_IA32_TSC:
2938                 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2939                 break;
2940         case MSR_MTRRcap:
2941         case 0x200 ... 0x2ff:
2942                 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2943         case 0xcd: /* fsb frequency */
2944                 msr_info->data = 3;
2945                 break;
2946                 /*
2947                  * MSR_EBC_FREQUENCY_ID
2948                  * Conservative value valid for even the basic CPU models.
2949                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2950                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2951                  * and 266MHz for model 3, or 4. Set Core Clock
2952                  * Frequency to System Bus Frequency Ratio to 1 (bits
2953                  * 31:24) even though these are only valid for CPU
2954                  * models > 2, however guests may end up dividing or
2955                  * multiplying by zero otherwise.
2956                  */
2957         case MSR_EBC_FREQUENCY_ID:
2958                 msr_info->data = 1 << 24;
2959                 break;
2960         case MSR_IA32_APICBASE:
2961                 msr_info->data = kvm_get_apic_base(vcpu);
2962                 break;
2963         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2964                 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2965                 break;
2966         case MSR_IA32_TSCDEADLINE:
2967                 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2968                 break;
2969         case MSR_IA32_TSC_ADJUST:
2970                 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2971                 break;
2972         case MSR_IA32_MISC_ENABLE:
2973                 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2974                 break;
2975         case MSR_IA32_SMBASE:
2976                 if (!msr_info->host_initiated)
2977                         return 1;
2978                 msr_info->data = vcpu->arch.smbase;
2979                 break;
2980         case MSR_SMI_COUNT:
2981                 msr_info->data = vcpu->arch.smi_count;
2982                 break;
2983         case MSR_IA32_PERF_STATUS:
2984                 /* TSC increment by tick */
2985                 msr_info->data = 1000ULL;
2986                 /* CPU multiplier */
2987                 msr_info->data |= (((uint64_t)4ULL) << 40);
2988                 break;
2989         case MSR_EFER:
2990                 msr_info->data = vcpu->arch.efer;
2991                 break;
2992         case MSR_KVM_WALL_CLOCK:
2993         case MSR_KVM_WALL_CLOCK_NEW:
2994                 msr_info->data = vcpu->kvm->arch.wall_clock;
2995                 break;
2996         case MSR_KVM_SYSTEM_TIME:
2997         case MSR_KVM_SYSTEM_TIME_NEW:
2998                 msr_info->data = vcpu->arch.time;
2999                 break;
3000         case MSR_KVM_ASYNC_PF_EN:
3001                 msr_info->data = vcpu->arch.apf.msr_val;
3002                 break;
3003         case MSR_KVM_STEAL_TIME:
3004                 msr_info->data = vcpu->arch.st.msr_val;
3005                 break;
3006         case MSR_KVM_PV_EOI_EN:
3007                 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3008                 break;
3009         case MSR_KVM_POLL_CONTROL:
3010                 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3011                 break;
3012         case MSR_IA32_P5_MC_ADDR:
3013         case MSR_IA32_P5_MC_TYPE:
3014         case MSR_IA32_MCG_CAP:
3015         case MSR_IA32_MCG_CTL:
3016         case MSR_IA32_MCG_STATUS:
3017         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3018                 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3019                                    msr_info->host_initiated);
3020         case MSR_K7_CLK_CTL:
3021                 /*
3022                  * Provide expected ramp-up count for K7. All other
3023                  * are set to zero, indicating minimum divisors for
3024                  * every field.
3025                  *
3026                  * This prevents guest kernels on AMD host with CPU
3027                  * type 6, model 8 and higher from exploding due to
3028                  * the rdmsr failing.
3029                  */
3030                 msr_info->data = 0x20000000;
3031                 break;
3032         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3033         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3034         case HV_X64_MSR_CRASH_CTL:
3035         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3036         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3037         case HV_X64_MSR_TSC_EMULATION_CONTROL:
3038         case HV_X64_MSR_TSC_EMULATION_STATUS:
3039                 return kvm_hv_get_msr_common(vcpu,
3040                                              msr_info->index, &msr_info->data,
3041                                              msr_info->host_initiated);
3042                 break;
3043         case MSR_IA32_BBL_CR_CTL3:
3044                 /* This legacy MSR exists but isn't fully documented in current
3045                  * silicon.  It is however accessed by winxp in very narrow
3046                  * scenarios where it sets bit #19, itself documented as
3047                  * a "reserved" bit.  Best effort attempt to source coherent
3048                  * read data here should the balance of the register be
3049                  * interpreted by the guest:
3050                  *
3051                  * L2 cache control register 3: 64GB range, 256KB size,
3052                  * enabled, latency 0x1, configured
3053                  */
3054                 msr_info->data = 0xbe702111;
3055                 break;
3056         case MSR_AMD64_OSVW_ID_LENGTH:
3057                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3058                         return 1;
3059                 msr_info->data = vcpu->arch.osvw.length;
3060                 break;
3061         case MSR_AMD64_OSVW_STATUS:
3062                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3063                         return 1;
3064                 msr_info->data = vcpu->arch.osvw.status;
3065                 break;
3066         case MSR_PLATFORM_INFO:
3067                 if (!msr_info->host_initiated &&
3068                     !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3069                         return 1;
3070                 msr_info->data = vcpu->arch.msr_platform_info;
3071                 break;
3072         case MSR_MISC_FEATURES_ENABLES:
3073                 msr_info->data = vcpu->arch.msr_misc_features_enables;
3074                 break;
3075         case MSR_K7_HWCR:
3076                 msr_info->data = vcpu->arch.msr_hwcr;
3077                 break;
3078         default:
3079                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3080                         return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3081                 if (!ignore_msrs) {
3082                         vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3083                                                msr_info->index);
3084                         return 1;
3085                 } else {
3086                         if (report_ignored_msrs)
3087                                 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3088                                         msr_info->index);
3089                         msr_info->data = 0;
3090                 }
3091                 break;
3092         }
3093         return 0;
3094 }
3095 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3096
3097 /*
3098  * Read or write a bunch of msrs. All parameters are kernel addresses.
3099  *
3100  * @return number of msrs set successfully.
3101  */
3102 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3103                     struct kvm_msr_entry *entries,
3104                     int (*do_msr)(struct kvm_vcpu *vcpu,
3105                                   unsigned index, u64 *data))
3106 {
3107         int i;
3108
3109         for (i = 0; i < msrs->nmsrs; ++i)
3110                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3111                         break;
3112
3113         return i;
3114 }
3115
3116 /*
3117  * Read or write a bunch of msrs. Parameters are user addresses.
3118  *
3119  * @return number of msrs set successfully.
3120  */
3121 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3122                   int (*do_msr)(struct kvm_vcpu *vcpu,
3123                                 unsigned index, u64 *data),
3124                   int writeback)
3125 {
3126         struct kvm_msrs msrs;
3127         struct kvm_msr_entry *entries;
3128         int r, n;
3129         unsigned size;
3130
3131         r = -EFAULT;
3132         if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3133                 goto out;
3134
3135         r = -E2BIG;
3136         if (msrs.nmsrs >= MAX_IO_MSRS)
3137                 goto out;
3138
3139         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3140         entries = memdup_user(user_msrs->entries, size);
3141         if (IS_ERR(entries)) {
3142                 r = PTR_ERR(entries);
3143                 goto out;
3144         }
3145
3146         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3147         if (r < 0)
3148                 goto out_free;
3149
3150         r = -EFAULT;
3151         if (writeback && copy_to_user(user_msrs->entries, entries, size))
3152                 goto out_free;
3153
3154         r = n;
3155
3156 out_free:
3157         kfree(entries);
3158 out:
3159         return r;
3160 }
3161
3162 static inline bool kvm_can_mwait_in_guest(void)
3163 {
3164         return boot_cpu_has(X86_FEATURE_MWAIT) &&
3165                 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3166                 boot_cpu_has(X86_FEATURE_ARAT);
3167 }
3168
3169 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3170 {
3171         int r = 0;
3172
3173         switch (ext) {
3174         case KVM_CAP_IRQCHIP:
3175         case KVM_CAP_HLT:
3176         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3177         case KVM_CAP_SET_TSS_ADDR:
3178         case KVM_CAP_EXT_CPUID:
3179         case KVM_CAP_EXT_EMUL_CPUID:
3180         case KVM_CAP_CLOCKSOURCE:
3181         case KVM_CAP_PIT:
3182         case KVM_CAP_NOP_IO_DELAY:
3183         case KVM_CAP_MP_STATE:
3184         case KVM_CAP_SYNC_MMU:
3185         case KVM_CAP_USER_NMI:
3186         case KVM_CAP_REINJECT_CONTROL:
3187         case KVM_CAP_IRQ_INJECT_STATUS:
3188         case KVM_CAP_IOEVENTFD:
3189         case KVM_CAP_IOEVENTFD_NO_LENGTH:
3190         case KVM_CAP_PIT2:
3191         case KVM_CAP_PIT_STATE2:
3192         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3193         case KVM_CAP_XEN_HVM:
3194         case KVM_CAP_VCPU_EVENTS:
3195         case KVM_CAP_HYPERV:
3196         case KVM_CAP_HYPERV_VAPIC:
3197         case KVM_CAP_HYPERV_SPIN:
3198         case KVM_CAP_HYPERV_SYNIC:
3199         case KVM_CAP_HYPERV_SYNIC2:
3200         case KVM_CAP_HYPERV_VP_INDEX:
3201         case KVM_CAP_HYPERV_EVENTFD:
3202         case KVM_CAP_HYPERV_TLBFLUSH:
3203         case KVM_CAP_HYPERV_SEND_IPI:
3204         case KVM_CAP_HYPERV_CPUID:
3205         case KVM_CAP_PCI_SEGMENT:
3206         case KVM_CAP_DEBUGREGS:
3207         case KVM_CAP_X86_ROBUST_SINGLESTEP:
3208         case KVM_CAP_XSAVE:
3209         case KVM_CAP_ASYNC_PF:
3210         case KVM_CAP_GET_TSC_KHZ:
3211         case KVM_CAP_KVMCLOCK_CTRL:
3212         case KVM_CAP_READONLY_MEM:
3213         case KVM_CAP_HYPERV_TIME:
3214         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3215         case KVM_CAP_TSC_DEADLINE_TIMER:
3216         case KVM_CAP_DISABLE_QUIRKS:
3217         case KVM_CAP_SET_BOOT_CPU_ID:
3218         case KVM_CAP_SPLIT_IRQCHIP:
3219         case KVM_CAP_IMMEDIATE_EXIT:
3220         case KVM_CAP_PMU_EVENT_FILTER:
3221         case KVM_CAP_GET_MSR_FEATURES:
3222         case KVM_CAP_MSR_PLATFORM_INFO:
3223         case KVM_CAP_EXCEPTION_PAYLOAD:
3224                 r = 1;
3225                 break;
3226         case KVM_CAP_SYNC_REGS:
3227                 r = KVM_SYNC_X86_VALID_FIELDS;
3228                 break;
3229         case KVM_CAP_ADJUST_CLOCK:
3230                 r = KVM_CLOCK_TSC_STABLE;
3231                 break;
3232         case KVM_CAP_X86_DISABLE_EXITS:
3233                 r |=  KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3234                       KVM_X86_DISABLE_EXITS_CSTATE;
3235                 if(kvm_can_mwait_in_guest())
3236                         r |= KVM_X86_DISABLE_EXITS_MWAIT;
3237                 break;
3238         case KVM_CAP_X86_SMM:
3239                 /* SMBASE is usually relocated above 1M on modern chipsets,
3240                  * and SMM handlers might indeed rely on 4G segment limits,
3241                  * so do not report SMM to be available if real mode is
3242                  * emulated via vm86 mode.  Still, do not go to great lengths
3243                  * to avoid userspace's usage of the feature, because it is a
3244                  * fringe case that is not enabled except via specific settings
3245                  * of the module parameters.
3246                  */
3247                 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3248                 break;
3249         case KVM_CAP_VAPIC:
3250                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3251                 break;
3252         case KVM_CAP_NR_VCPUS:
3253                 r = KVM_SOFT_MAX_VCPUS;
3254                 break;
3255         case KVM_CAP_MAX_VCPUS:
3256                 r = KVM_MAX_VCPUS;
3257                 break;
3258         case KVM_CAP_MAX_VCPU_ID:
3259                 r = KVM_MAX_VCPU_ID;
3260                 break;
3261         case KVM_CAP_PV_MMU:    /* obsolete */
3262                 r = 0;
3263                 break;
3264         case KVM_CAP_MCE:
3265                 r = KVM_MAX_MCE_BANKS;
3266                 break;
3267         case KVM_CAP_XCRS:
3268                 r = boot_cpu_has(X86_FEATURE_XSAVE);
3269                 break;
3270         case KVM_CAP_TSC_CONTROL:
3271                 r = kvm_has_tsc_control;
3272                 break;
3273         case KVM_CAP_X2APIC_API:
3274                 r = KVM_X2APIC_API_VALID_FLAGS;
3275                 break;
3276         case KVM_CAP_NESTED_STATE:
3277                 r = kvm_x86_ops->get_nested_state ?
3278                         kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
3279                 break;
3280         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3281                 r = kvm_x86_ops->enable_direct_tlbflush != NULL;
3282                 break;
3283         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3284                 r = kvm_x86_ops->nested_enable_evmcs != NULL;
3285                 break;
3286         default:
3287                 break;
3288         }
3289         return r;
3290
3291 }
3292
3293 long kvm_arch_dev_ioctl(struct file *filp,
3294                         unsigned int ioctl, unsigned long arg)
3295 {
3296         void __user *argp = (void __user *)arg;
3297         long r;
3298
3299         switch (ioctl) {
3300         case KVM_GET_MSR_INDEX_LIST: {
3301                 struct kvm_msr_list __user *user_msr_list = argp;
3302                 struct kvm_msr_list msr_list;
3303                 unsigned n;
3304
3305                 r = -EFAULT;
3306                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3307                         goto out;
3308                 n = msr_list.nmsrs;
3309                 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3310                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3311                         goto out;
3312                 r = -E2BIG;
3313                 if (n < msr_list.nmsrs)
3314                         goto out;
3315                 r = -EFAULT;
3316                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3317                                  num_msrs_to_save * sizeof(u32)))
3318                         goto out;
3319                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3320                                  &emulated_msrs,
3321                                  num_emulated_msrs * sizeof(u32)))
3322                         goto out;
3323                 r = 0;
3324                 break;
3325         }
3326         case KVM_GET_SUPPORTED_CPUID:
3327         case KVM_GET_EMULATED_CPUID: {
3328                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3329                 struct kvm_cpuid2 cpuid;
3330
3331                 r = -EFAULT;
3332                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3333                         goto out;
3334
3335                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3336                                             ioctl);
3337                 if (r)
3338                         goto out;
3339
3340                 r = -EFAULT;
3341                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3342                         goto out;
3343                 r = 0;
3344                 break;
3345         }
3346         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3347                 r = -EFAULT;
3348                 if (copy_to_user(argp, &kvm_mce_cap_supported,
3349                                  sizeof(kvm_mce_cap_supported)))
3350                         goto out;
3351                 r = 0;
3352                 break;
3353         case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3354                 struct kvm_msr_list __user *user_msr_list = argp;
3355                 struct kvm_msr_list msr_list;
3356                 unsigned int n;
3357
3358                 r = -EFAULT;
3359                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3360                         goto out;
3361                 n = msr_list.nmsrs;
3362                 msr_list.nmsrs = num_msr_based_features;
3363                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3364                         goto out;
3365                 r = -E2BIG;
3366                 if (n < msr_list.nmsrs)
3367                         goto out;
3368                 r = -EFAULT;
3369                 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3370                                  num_msr_based_features * sizeof(u32)))
3371                         goto out;
3372                 r = 0;
3373                 break;
3374         }
3375         case KVM_GET_MSRS:
3376                 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3377                 break;
3378         }
3379         default:
3380                 r = -EINVAL;
3381         }
3382 out:
3383         return r;
3384 }
3385
3386 static void wbinvd_ipi(void *garbage)
3387 {
3388         wbinvd();
3389 }
3390
3391 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3392 {
3393         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3394 }
3395
3396 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3397 {
3398         /* Address WBINVD may be executed by guest */
3399         if (need_emulate_wbinvd(vcpu)) {
3400                 if (kvm_x86_ops->has_wbinvd_exit())
3401                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3402                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3403                         smp_call_function_single(vcpu->cpu,
3404                                         wbinvd_ipi, NULL, 1);
3405         }
3406
3407         kvm_x86_ops->vcpu_load(vcpu, cpu);
3408
3409         fpregs_assert_state_consistent();
3410         if (test_thread_flag(TIF_NEED_FPU_LOAD))
3411                 switch_fpu_return();
3412
3413         /* Apply any externally detected TSC adjustments (due to suspend) */
3414         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3415                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3416                 vcpu->arch.tsc_offset_adjustment = 0;
3417                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3418         }
3419
3420         if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3421                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3422                                 rdtsc() - vcpu->arch.last_host_tsc;
3423                 if (tsc_delta < 0)
3424                         mark_tsc_unstable("KVM discovered backwards TSC");
3425
3426                 if (kvm_check_tsc_unstable()) {
3427                         u64 offset = kvm_compute_tsc_offset(vcpu,
3428                                                 vcpu->arch.last_guest_tsc);
3429                         kvm_vcpu_write_tsc_offset(vcpu, offset);
3430                         vcpu->arch.tsc_catchup = 1;
3431                 }
3432
3433                 if (kvm_lapic_hv_timer_in_use(vcpu))
3434                         kvm_lapic_restart_hv_timer(vcpu);
3435
3436                 /*
3437                  * On a host with synchronized TSC, there is no need to update
3438                  * kvmclock on vcpu->cpu migration
3439                  */
3440                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3441                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3442                 if (vcpu->cpu != cpu)
3443                         kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3444                 vcpu->cpu = cpu;
3445         }
3446
3447         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3448 }
3449
3450 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3451 {
3452         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3453                 return;
3454
3455         vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
3456
3457         kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3458                         &vcpu->arch.st.steal.preempted,
3459                         offsetof(struct kvm_steal_time, preempted),
3460                         sizeof(vcpu->arch.st.steal.preempted));
3461 }
3462
3463 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3464 {
3465         int idx;
3466
3467         if (vcpu->preempted)
3468                 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3469
3470         /*
3471          * Disable page faults because we're in atomic context here.
3472          * kvm_write_guest_offset_cached() would call might_fault()
3473          * that relies on pagefault_disable() to tell if there's a
3474          * bug. NOTE: the write to guest memory may not go through if
3475          * during postcopy live migration or if there's heavy guest
3476          * paging.
3477          */
3478         pagefault_disable();
3479         /*
3480          * kvm_memslots() will be called by
3481          * kvm_write_guest_offset_cached() so take the srcu lock.
3482          */
3483         idx = srcu_read_lock(&vcpu->kvm->srcu);
3484         kvm_steal_time_set_preempted(vcpu);
3485         srcu_read_unlock(&vcpu->kvm->srcu, idx);
3486         pagefault_enable();
3487         kvm_x86_ops->vcpu_put(vcpu);
3488         vcpu->arch.last_host_tsc = rdtsc();
3489         /*
3490          * If userspace has set any breakpoints or watchpoints, dr6 is restored
3491          * on every vmexit, but if not, we might have a stale dr6 from the
3492          * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3493          */
3494         set_debugreg(0, 6);
3495 }
3496
3497 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3498                                     struct kvm_lapic_state *s)
3499 {
3500         if (vcpu->arch.apicv_active)
3501                 kvm_x86_ops->sync_pir_to_irr(vcpu);
3502
3503         return kvm_apic_get_state(vcpu, s);
3504 }
3505
3506 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3507                                     struct kvm_lapic_state *s)
3508 {
3509         int r;
3510
3511         r = kvm_apic_set_state(vcpu, s);
3512         if (r)
3513                 return r;
3514         update_cr8_intercept(vcpu);
3515
3516         return 0;
3517 }
3518
3519 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3520 {
3521         return (!lapic_in_kernel(vcpu) ||
3522                 kvm_apic_accept_pic_intr(vcpu));
3523 }
3524
3525 /*
3526  * if userspace requested an interrupt window, check that the
3527  * interrupt window is open.
3528  *
3529  * No need to exit to userspace if we already have an interrupt queued.
3530  */
3531 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3532 {
3533         return kvm_arch_interrupt_allowed(vcpu) &&
3534                 !kvm_cpu_has_interrupt(vcpu) &&
3535                 !kvm_event_needs_reinjection(vcpu) &&
3536                 kvm_cpu_accept_dm_intr(vcpu);
3537 }
3538
3539 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3540                                     struct kvm_interrupt *irq)
3541 {
3542         if (irq->irq >= KVM_NR_INTERRUPTS)
3543                 return -EINVAL;
3544
3545         if (!irqchip_in_kernel(vcpu->kvm)) {
3546                 kvm_queue_interrupt(vcpu, irq->irq, false);
3547                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3548                 return 0;
3549         }
3550
3551         /*
3552          * With in-kernel LAPIC, we only use this to inject EXTINT, so
3553          * fail for in-kernel 8259.
3554          */
3555         if (pic_in_kernel(vcpu->kvm))
3556                 return -ENXIO;
3557
3558         if (vcpu->arch.pending_external_vector != -1)
3559                 return -EEXIST;
3560
3561         vcpu->arch.pending_external_vector = irq->irq;
3562         kvm_make_request(KVM_REQ_EVENT, vcpu);
3563         return 0;
3564 }
3565
3566 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3567 {
3568         kvm_inject_nmi(vcpu);
3569
3570         return 0;
3571 }
3572
3573 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3574 {
3575         kvm_make_request(KVM_REQ_SMI, vcpu);
3576
3577         return 0;
3578 }
3579
3580 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3581                                            struct kvm_tpr_access_ctl *tac)
3582 {
3583         if (tac->flags)
3584                 return -EINVAL;
3585         vcpu->arch.tpr_access_reporting = !!tac->enabled;
3586         return 0;
3587 }
3588
3589 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3590                                         u64 mcg_cap)
3591 {
3592         int r;
3593         unsigned bank_num = mcg_cap & 0xff, bank;
3594
3595         r = -EINVAL;
3596         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3597                 goto out;
3598         if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3599                 goto out;
3600         r = 0;
3601         vcpu->arch.mcg_cap = mcg_cap;
3602         /* Init IA32_MCG_CTL to all 1s */
3603         if (mcg_cap & MCG_CTL_P)
3604                 vcpu->arch.mcg_ctl = ~(u64)0;
3605         /* Init IA32_MCi_CTL to all 1s */
3606         for (bank = 0; bank < bank_num; bank++)
3607                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3608
3609         kvm_x86_ops->setup_mce(vcpu);
3610 out:
3611         return r;
3612 }
3613
3614 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3615                                       struct kvm_x86_mce *mce)
3616 {
3617         u64 mcg_cap = vcpu->arch.mcg_cap;
3618         unsigned bank_num = mcg_cap & 0xff;
3619         u64 *banks = vcpu->arch.mce_banks;
3620
3621         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3622                 return -EINVAL;
3623         /*
3624          * if IA32_MCG_CTL is not all 1s, the uncorrected error
3625          * reporting is disabled
3626          */
3627         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3628             vcpu->arch.mcg_ctl != ~(u64)0)
3629                 return 0;
3630         banks += 4 * mce->bank;
3631         /*
3632          * if IA32_MCi_CTL is not all 1s, the uncorrected error
3633          * reporting is disabled for the bank
3634          */
3635         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3636                 return 0;
3637         if (mce->status & MCI_STATUS_UC) {
3638                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3639                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3640                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3641                         return 0;
3642                 }
3643                 if (banks[1] & MCI_STATUS_VAL)
3644                         mce->status |= MCI_STATUS_OVER;
3645                 banks[2] = mce->addr;
3646                 banks[3] = mce->misc;
3647                 vcpu->arch.mcg_status = mce->mcg_status;
3648                 banks[1] = mce->status;
3649                 kvm_queue_exception(vcpu, MC_VECTOR);
3650         } else if (!(banks[1] & MCI_STATUS_VAL)
3651                    || !(banks[1] & MCI_STATUS_UC)) {
3652                 if (banks[1] & MCI_STATUS_VAL)
3653                         mce->status |= MCI_STATUS_OVER;
3654                 banks[2] = mce->addr;
3655                 banks[3] = mce->misc;
3656                 banks[1] = mce->status;
3657         } else
3658                 banks[1] |= MCI_STATUS_OVER;
3659         return 0;
3660 }
3661
3662 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3663                                                struct kvm_vcpu_events *events)
3664 {
3665         process_nmi(vcpu);
3666
3667         /*
3668          * The API doesn't provide the instruction length for software
3669          * exceptions, so don't report them. As long as the guest RIP
3670          * isn't advanced, we should expect to encounter the exception
3671          * again.
3672          */
3673         if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3674                 events->exception.injected = 0;
3675                 events->exception.pending = 0;
3676         } else {
3677                 events->exception.injected = vcpu->arch.exception.injected;
3678                 events->exception.pending = vcpu->arch.exception.pending;
3679                 /*
3680                  * For ABI compatibility, deliberately conflate
3681                  * pending and injected exceptions when
3682                  * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3683                  */
3684                 if (!vcpu->kvm->arch.exception_payload_enabled)
3685                         events->exception.injected |=
3686                                 vcpu->arch.exception.pending;
3687         }
3688         events->exception.nr = vcpu->arch.exception.nr;
3689         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3690         events->exception.error_code = vcpu->arch.exception.error_code;
3691         events->exception_has_payload = vcpu->arch.exception.has_payload;
3692         events->exception_payload = vcpu->arch.exception.payload;
3693
3694         events->interrupt.injected =
3695                 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3696         events->interrupt.nr = vcpu->arch.interrupt.nr;
3697         events->interrupt.soft = 0;
3698         events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3699
3700         events->nmi.injected = vcpu->arch.nmi_injected;
3701         events->nmi.pending = vcpu->arch.nmi_pending != 0;
3702         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3703         events->nmi.pad = 0;
3704
3705         events->sipi_vector = 0; /* never valid when reporting to user space */
3706
3707         events->smi.smm = is_smm(vcpu);
3708         events->smi.pending = vcpu->arch.smi_pending;
3709         events->smi.smm_inside_nmi =
3710                 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3711         events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3712
3713         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3714                          | KVM_VCPUEVENT_VALID_SHADOW
3715                          | KVM_VCPUEVENT_VALID_SMM);
3716         if (vcpu->kvm->arch.exception_payload_enabled)
3717                 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3718
3719         memset(&events->reserved, 0, sizeof(events->reserved));
3720 }
3721
3722 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3723
3724 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3725                                               struct kvm_vcpu_events *events)
3726 {
3727         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3728                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3729                               | KVM_VCPUEVENT_VALID_SHADOW
3730                               | KVM_VCPUEVENT_VALID_SMM
3731                               | KVM_VCPUEVENT_VALID_PAYLOAD))
3732                 return -EINVAL;
3733
3734         if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3735                 if (!vcpu->kvm->arch.exception_payload_enabled)
3736                         return -EINVAL;
3737                 if (events->exception.pending)
3738                         events->exception.injected = 0;
3739                 else
3740                         events->exception_has_payload = 0;
3741         } else {
3742                 events->exception.pending = 0;
3743                 events->exception_has_payload = 0;
3744         }
3745
3746         if ((events->exception.injected || events->exception.pending) &&
3747             (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3748                 return -EINVAL;
3749
3750         /* INITs are latched while in SMM */
3751         if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3752             (events->smi.smm || events->smi.pending) &&
3753             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3754                 return -EINVAL;
3755
3756         process_nmi(vcpu);
3757         vcpu->arch.exception.injected = events->exception.injected;
3758         vcpu->arch.exception.pending = events->exception.pending;
3759         vcpu->arch.exception.nr = events->exception.nr;
3760         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3761         vcpu->arch.exception.error_code = events->exception.error_code;
3762         vcpu->arch.exception.has_payload = events->exception_has_payload;
3763         vcpu->arch.exception.payload = events->exception_payload;
3764
3765         vcpu->arch.interrupt.injected = events->interrupt.injected;
3766         vcpu->arch.interrupt.nr = events->interrupt.nr;
3767         vcpu->arch.interrupt.soft = events->interrupt.soft;
3768         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3769                 kvm_x86_ops->set_interrupt_shadow(vcpu,
3770                                                   events->interrupt.shadow);
3771
3772         vcpu->arch.nmi_injected = events->nmi.injected;
3773         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3774                 vcpu->arch.nmi_pending = events->nmi.pending;
3775         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3776
3777         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3778             lapic_in_kernel(vcpu))
3779                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3780
3781         if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3782                 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3783                         if (events->smi.smm)
3784                                 vcpu->arch.hflags |= HF_SMM_MASK;
3785                         else
3786                                 vcpu->arch.hflags &= ~HF_SMM_MASK;
3787                         kvm_smm_changed(vcpu);
3788                 }
3789
3790                 vcpu->arch.smi_pending = events->smi.pending;
3791
3792                 if (events->smi.smm) {
3793                         if (events->smi.smm_inside_nmi)
3794                                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3795                         else
3796                                 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3797                         if (lapic_in_kernel(vcpu)) {
3798                                 if (events->smi.latched_init)
3799                                         set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3800                                 else
3801                                         clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3802                         }
3803                 }
3804         }
3805
3806         kvm_make_request(KVM_REQ_EVENT, vcpu);
3807
3808         return 0;
3809 }
3810
3811 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3812                                              struct kvm_debugregs *dbgregs)
3813 {
3814         unsigned long val;
3815
3816         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3817         kvm_get_dr(vcpu, 6, &val);
3818         dbgregs->dr6 = val;
3819         dbgregs->dr7 = vcpu->arch.dr7;
3820         dbgregs->flags = 0;
3821         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3822 }
3823
3824 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3825                                             struct kvm_debugregs *dbgregs)
3826 {
3827         if (dbgregs->flags)
3828                 return -EINVAL;
3829
3830         if (dbgregs->dr6 & ~0xffffffffull)
3831                 return -EINVAL;
3832         if (dbgregs->dr7 & ~0xffffffffull)
3833                 return -EINVAL;
3834
3835         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3836         kvm_update_dr0123(vcpu);
3837         vcpu->arch.dr6 = dbgregs->dr6;
3838         kvm_update_dr6(vcpu);
3839         vcpu->arch.dr7 = dbgregs->dr7;
3840         kvm_update_dr7(vcpu);
3841
3842         return 0;
3843 }
3844
3845 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3846
3847 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3848 {
3849         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3850         u64 xstate_bv = xsave->header.xfeatures;
3851         u64 valid;
3852
3853         /*
3854          * Copy legacy XSAVE area, to avoid complications with CPUID
3855          * leaves 0 and 1 in the loop below.
3856          */
3857         memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3858
3859         /* Set XSTATE_BV */
3860         xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3861         *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3862
3863         /*
3864          * Copy each region from the possibly compacted offset to the
3865          * non-compacted offset.
3866          */
3867         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3868         while (valid) {
3869                 u64 xfeature_mask = valid & -valid;
3870                 int xfeature_nr = fls64(xfeature_mask) - 1;
3871                 void *src = get_xsave_addr(xsave, xfeature_nr);
3872
3873                 if (src) {
3874                         u32 size, offset, ecx, edx;
3875                         cpuid_count(XSTATE_CPUID, xfeature_nr,
3876                                     &size, &offset, &ecx, &edx);
3877                         if (xfeature_nr == XFEATURE_PKRU)
3878                                 memcpy(dest + offset, &vcpu->arch.pkru,
3879                                        sizeof(vcpu->arch.pkru));
3880                         else
3881                                 memcpy(dest + offset, src, size);
3882
3883                 }
3884
3885                 valid -= xfeature_mask;
3886         }
3887 }
3888
3889 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3890 {
3891         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3892         u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3893         u64 valid;
3894
3895         /*
3896          * Copy legacy XSAVE area, to avoid complications with CPUID
3897          * leaves 0 and 1 in the loop below.
3898          */
3899         memcpy(xsave, src, XSAVE_HDR_OFFSET);
3900
3901         /* Set XSTATE_BV and possibly XCOMP_BV.  */
3902         xsave->header.xfeatures = xstate_bv;
3903         if (boot_cpu_has(X86_FEATURE_XSAVES))
3904                 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3905
3906         /*
3907          * Copy each region from the non-compacted offset to the
3908          * possibly compacted offset.
3909          */
3910         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3911         while (valid) {
3912                 u64 xfeature_mask = valid & -valid;
3913                 int xfeature_nr = fls64(xfeature_mask) - 1;
3914                 void *dest = get_xsave_addr(xsave, xfeature_nr);
3915
3916                 if (dest) {
3917                         u32 size, offset, ecx, edx;
3918                         cpuid_count(XSTATE_CPUID, xfeature_nr,
3919                                     &size, &offset, &ecx, &edx);
3920                         if (xfeature_nr == XFEATURE_PKRU)
3921                                 memcpy(&vcpu->arch.pkru, src + offset,
3922                                        sizeof(vcpu->arch.pkru));
3923                         else
3924                                 memcpy(dest, src + offset, size);
3925                 }
3926
3927                 valid -= xfeature_mask;
3928         }
3929 }
3930
3931 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3932                                          struct kvm_xsave *guest_xsave)
3933 {
3934         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3935                 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3936                 fill_xsave((u8 *) guest_xsave->region, vcpu);
3937         } else {
3938                 memcpy(guest_xsave->region,
3939                         &vcpu->arch.guest_fpu->state.fxsave,
3940                         sizeof(struct fxregs_state));
3941                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3942                         XFEATURE_MASK_FPSSE;
3943         }
3944 }
3945
3946 #define XSAVE_MXCSR_OFFSET 24
3947
3948 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3949                                         struct kvm_xsave *guest_xsave)
3950 {
3951         u64 xstate_bv =
3952                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3953         u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3954
3955         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3956                 /*
3957                  * Here we allow setting states that are not present in
3958                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
3959                  * with old userspace.
3960                  */
3961                 if (xstate_bv & ~kvm_supported_xcr0() ||
3962                         mxcsr & ~mxcsr_feature_mask)
3963                         return -EINVAL;
3964                 load_xsave(vcpu, (u8 *)guest_xsave->region);
3965         } else {
3966                 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3967                         mxcsr & ~mxcsr_feature_mask)
3968                         return -EINVAL;
3969                 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
3970                         guest_xsave->region, sizeof(struct fxregs_state));
3971         }
3972         return 0;
3973 }
3974
3975 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3976                                         struct kvm_xcrs *guest_xcrs)
3977 {
3978         if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3979                 guest_xcrs->nr_xcrs = 0;
3980                 return;
3981         }
3982
3983         guest_xcrs->nr_xcrs = 1;
3984         guest_xcrs->flags = 0;
3985         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3986         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3987 }
3988
3989 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3990                                        struct kvm_xcrs *guest_xcrs)
3991 {
3992         int i, r = 0;
3993
3994         if (!boot_cpu_has(X86_FEATURE_XSAVE))
3995                 return -EINVAL;
3996
3997         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3998                 return -EINVAL;
3999
4000         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4001                 /* Only support XCR0 currently */
4002                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4003                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4004                                 guest_xcrs->xcrs[i].value);
4005                         break;
4006                 }
4007         if (r)
4008                 r = -EINVAL;
4009         return r;
4010 }
4011
4012 /*
4013  * kvm_set_guest_paused() indicates to the guest kernel that it has been
4014  * stopped by the hypervisor.  This function will be called from the host only.
4015  * EINVAL is returned when the host attempts to set the flag for a guest that
4016  * does not support pv clocks.
4017  */
4018 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4019 {
4020         if (!vcpu->arch.pv_time_enabled)
4021                 return -EINVAL;
4022         vcpu->arch.pvclock_set_guest_stopped_request = true;
4023         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4024         return 0;
4025 }
4026
4027 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4028                                      struct kvm_enable_cap *cap)
4029 {
4030         int r;
4031         uint16_t vmcs_version;
4032         void __user *user_ptr;
4033
4034         if (cap->flags)
4035                 return -EINVAL;
4036
4037         switch (cap->cap) {
4038         case KVM_CAP_HYPERV_SYNIC2:
4039                 if (cap->args[0])
4040                         return -EINVAL;
4041                 /* fall through */
4042
4043         case KVM_CAP_HYPERV_SYNIC:
4044                 if (!irqchip_in_kernel(vcpu->kvm))
4045                         return -EINVAL;
4046                 return kvm_hv_activate_synic(vcpu, cap->cap ==
4047                                              KVM_CAP_HYPERV_SYNIC2);
4048         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4049                 if (!kvm_x86_ops->nested_enable_evmcs)
4050                         return -ENOTTY;
4051                 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
4052                 if (!r) {
4053                         user_ptr = (void __user *)(uintptr_t)cap->args[0];
4054                         if (copy_to_user(user_ptr, &vmcs_version,
4055                                          sizeof(vmcs_version)))
4056                                 r = -EFAULT;
4057                 }
4058                 return r;
4059         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4060                 if (!kvm_x86_ops->enable_direct_tlbflush)
4061                         return -ENOTTY;
4062
4063                 return kvm_x86_ops->enable_direct_tlbflush(vcpu);
4064
4065         default:
4066                 return -EINVAL;
4067         }
4068 }
4069
4070 long kvm_arch_vcpu_ioctl(struct file *filp,
4071                          unsigned int ioctl, unsigned long arg)
4072 {
4073         struct kvm_vcpu *vcpu = filp->private_data;
4074         void __user *argp = (void __user *)arg;
4075         int r;
4076         union {
4077                 struct kvm_lapic_state *lapic;
4078                 struct kvm_xsave *xsave;
4079                 struct kvm_xcrs *xcrs;
4080                 void *buffer;
4081         } u;
4082
4083         vcpu_load(vcpu);
4084
4085         u.buffer = NULL;
4086         switch (ioctl) {
4087         case KVM_GET_LAPIC: {
4088                 r = -EINVAL;
4089                 if (!lapic_in_kernel(vcpu))
4090                         goto out;
4091                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4092                                 GFP_KERNEL_ACCOUNT);
4093
4094                 r = -ENOMEM;
4095                 if (!u.lapic)
4096                         goto out;
4097                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4098                 if (r)
4099                         goto out;
4100                 r = -EFAULT;
4101                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4102                         goto out;
4103                 r = 0;
4104                 break;
4105         }
4106         case KVM_SET_LAPIC: {
4107                 r = -EINVAL;
4108                 if (!lapic_in_kernel(vcpu))
4109                         goto out;
4110                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4111                 if (IS_ERR(u.lapic)) {
4112                         r = PTR_ERR(u.lapic);
4113                         goto out_nofree;
4114                 }
4115
4116                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4117                 break;
4118         }
4119         case KVM_INTERRUPT: {
4120                 struct kvm_interrupt irq;
4121
4122                 r = -EFAULT;
4123                 if (copy_from_user(&irq, argp, sizeof(irq)))
4124                         goto out;
4125                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4126                 break;
4127         }
4128         case KVM_NMI: {
4129                 r = kvm_vcpu_ioctl_nmi(vcpu);
4130                 break;
4131         }
4132         case KVM_SMI: {
4133                 r = kvm_vcpu_ioctl_smi(vcpu);
4134                 break;
4135         }
4136         case KVM_SET_CPUID: {
4137                 struct kvm_cpuid __user *cpuid_arg = argp;
4138                 struct kvm_cpuid cpuid;
4139
4140                 r = -EFAULT;
4141                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4142                         goto out;
4143                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4144                 break;
4145         }
4146         case KVM_SET_CPUID2: {
4147                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4148                 struct kvm_cpuid2 cpuid;
4149
4150                 r = -EFAULT;
4151                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4152                         goto out;
4153                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4154                                               cpuid_arg->entries);
4155                 break;
4156         }
4157         case KVM_GET_CPUID2: {
4158                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4159                 struct kvm_cpuid2 cpuid;
4160
4161                 r = -EFAULT;
4162                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4163                         goto out;
4164                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4165                                               cpuid_arg->entries);
4166                 if (r)
4167                         goto out;
4168                 r = -EFAULT;
4169                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4170                         goto out;
4171                 r = 0;
4172                 break;
4173         }
4174         case KVM_GET_MSRS: {
4175                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4176                 r = msr_io(vcpu, argp, do_get_msr, 1);
4177                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4178                 break;
4179         }
4180         case KVM_SET_MSRS: {
4181                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4182                 r = msr_io(vcpu, argp, do_set_msr, 0);
4183                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4184                 break;
4185         }
4186         case KVM_TPR_ACCESS_REPORTING: {
4187                 struct kvm_tpr_access_ctl tac;
4188
4189                 r = -EFAULT;
4190                 if (copy_from_user(&tac, argp, sizeof(tac)))
4191                         goto out;
4192                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4193                 if (r)
4194                         goto out;
4195                 r = -EFAULT;
4196                 if (copy_to_user(argp, &tac, sizeof(tac)))
4197                         goto out;
4198                 r = 0;
4199                 break;
4200         };
4201         case KVM_SET_VAPIC_ADDR: {
4202                 struct kvm_vapic_addr va;
4203                 int idx;
4204
4205                 r = -EINVAL;
4206                 if (!lapic_in_kernel(vcpu))
4207                         goto out;
4208                 r = -EFAULT;
4209                 if (copy_from_user(&va, argp, sizeof(va)))
4210                         goto out;
4211                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4212                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4213                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4214                 break;
4215         }
4216         case KVM_X86_SETUP_MCE: {
4217                 u64 mcg_cap;
4218
4219                 r = -EFAULT;
4220                 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4221                         goto out;
4222                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4223                 break;
4224         }
4225         case KVM_X86_SET_MCE: {
4226                 struct kvm_x86_mce mce;
4227
4228                 r = -EFAULT;
4229                 if (copy_from_user(&mce, argp, sizeof(mce)))
4230                         goto out;
4231                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4232                 break;
4233         }
4234         case KVM_GET_VCPU_EVENTS: {
4235                 struct kvm_vcpu_events events;
4236
4237                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4238
4239                 r = -EFAULT;
4240                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4241                         break;
4242                 r = 0;
4243                 break;
4244         }
4245         case KVM_SET_VCPU_EVENTS: {
4246                 struct kvm_vcpu_events events;
4247
4248                 r = -EFAULT;
4249                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4250                         break;
4251
4252                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4253                 break;
4254         }
4255         case KVM_GET_DEBUGREGS: {
4256                 struct kvm_debugregs dbgregs;
4257
4258                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4259
4260                 r = -EFAULT;
4261                 if (copy_to_user(argp, &dbgregs,
4262                                  sizeof(struct kvm_debugregs)))
4263                         break;
4264                 r = 0;
4265                 break;
4266         }
4267         case KVM_SET_DEBUGREGS: {
4268                 struct kvm_debugregs dbgregs;
4269
4270                 r = -EFAULT;
4271                 if (copy_from_user(&dbgregs, argp,
4272                                    sizeof(struct kvm_debugregs)))
4273                         break;
4274
4275                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4276                 break;
4277         }
4278         case KVM_GET_XSAVE: {
4279                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4280                 r = -ENOMEM;
4281                 if (!u.xsave)
4282                         break;
4283
4284                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4285
4286                 r = -EFAULT;
4287                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4288                         break;
4289                 r = 0;
4290                 break;
4291         }
4292         case KVM_SET_XSAVE: {
4293                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4294                 if (IS_ERR(u.xsave)) {
4295                         r = PTR_ERR(u.xsave);
4296                         goto out_nofree;
4297                 }
4298
4299                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4300                 break;
4301         }
4302         case KVM_GET_XCRS: {
4303                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4304                 r = -ENOMEM;
4305                 if (!u.xcrs)
4306                         break;
4307
4308                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4309
4310                 r = -EFAULT;
4311                 if (copy_to_user(argp, u.xcrs,
4312                                  sizeof(struct kvm_xcrs)))
4313                         break;
4314                 r = 0;
4315                 break;
4316         }
4317         case KVM_SET_XCRS: {
4318                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4319                 if (IS_ERR(u.xcrs)) {
4320                         r = PTR_ERR(u.xcrs);
4321                         goto out_nofree;
4322                 }
4323
4324                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4325                 break;
4326         }
4327         case KVM_SET_TSC_KHZ: {
4328                 u32 user_tsc_khz;
4329
4330                 r = -EINVAL;
4331                 user_tsc_khz = (u32)arg;
4332
4333                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4334                         goto out;
4335
4336                 if (user_tsc_khz == 0)
4337                         user_tsc_khz = tsc_khz;
4338
4339                 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4340                         r = 0;
4341
4342                 goto out;
4343         }
4344         case KVM_GET_TSC_KHZ: {
4345                 r = vcpu->arch.virtual_tsc_khz;
4346                 goto out;
4347         }
4348         case KVM_KVMCLOCK_CTRL: {
4349                 r = kvm_set_guest_paused(vcpu);
4350                 goto out;
4351         }
4352         case KVM_ENABLE_CAP: {
4353                 struct kvm_enable_cap cap;
4354
4355                 r = -EFAULT;
4356                 if (copy_from_user(&cap, argp, sizeof(cap)))
4357                         goto out;
4358                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4359                 break;
4360         }
4361         case KVM_GET_NESTED_STATE: {
4362                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4363                 u32 user_data_size;
4364
4365                 r = -EINVAL;
4366                 if (!kvm_x86_ops->get_nested_state)
4367                         break;
4368
4369                 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4370                 r = -EFAULT;
4371                 if (get_user(user_data_size, &user_kvm_nested_state->size))
4372                         break;
4373
4374                 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4375                                                   user_data_size);
4376                 if (r < 0)
4377                         break;
4378
4379                 if (r > user_data_size) {
4380                         if (put_user(r, &user_kvm_nested_state->size))
4381                                 r = -EFAULT;
4382                         else
4383                                 r = -E2BIG;
4384                         break;
4385                 }
4386
4387                 r = 0;
4388                 break;
4389         }
4390         case KVM_SET_NESTED_STATE: {
4391                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4392                 struct kvm_nested_state kvm_state;
4393
4394                 r = -EINVAL;
4395                 if (!kvm_x86_ops->set_nested_state)
4396                         break;
4397
4398                 r = -EFAULT;
4399                 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4400                         break;
4401
4402                 r = -EINVAL;
4403                 if (kvm_state.size < sizeof(kvm_state))
4404                         break;
4405
4406                 if (kvm_state.flags &
4407                     ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4408                       | KVM_STATE_NESTED_EVMCS))
4409                         break;
4410
4411                 /* nested_run_pending implies guest_mode.  */
4412                 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4413                     && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4414                         break;
4415
4416                 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4417                 break;
4418         }
4419         case KVM_GET_SUPPORTED_HV_CPUID: {
4420                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4421                 struct kvm_cpuid2 cpuid;
4422
4423                 r = -EFAULT;
4424                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4425                         goto out;
4426
4427                 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4428                                                 cpuid_arg->entries);
4429                 if (r)
4430                         goto out;
4431
4432                 r = -EFAULT;
4433                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4434                         goto out;
4435                 r = 0;
4436                 break;
4437         }
4438         default:
4439                 r = -EINVAL;
4440         }
4441 out:
4442         kfree(u.buffer);
4443 out_nofree:
4444         vcpu_put(vcpu);
4445         return r;
4446 }
4447
4448 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4449 {
4450         return VM_FAULT_SIGBUS;
4451 }
4452
4453 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4454 {
4455         int ret;
4456
4457         if (addr > (unsigned int)(-3 * PAGE_SIZE))
4458                 return -EINVAL;
4459         ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4460         return ret;
4461 }
4462
4463 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4464                                               u64 ident_addr)
4465 {
4466         return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4467 }
4468
4469 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4470                                          unsigned long kvm_nr_mmu_pages)
4471 {
4472         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4473                 return -EINVAL;
4474
4475         mutex_lock(&kvm->slots_lock);
4476
4477         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4478         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4479
4480         mutex_unlock(&kvm->slots_lock);
4481         return 0;
4482 }
4483
4484 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4485 {
4486         return kvm->arch.n_max_mmu_pages;
4487 }
4488
4489 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4490 {
4491         struct kvm_pic *pic = kvm->arch.vpic;
4492         int r;
4493
4494         r = 0;
4495         switch (chip->chip_id) {
4496         case KVM_IRQCHIP_PIC_MASTER:
4497                 memcpy(&chip->chip.pic, &pic->pics[0],
4498                         sizeof(struct kvm_pic_state));
4499                 break;
4500         case KVM_IRQCHIP_PIC_SLAVE:
4501                 memcpy(&chip->chip.pic, &pic->pics[1],
4502                         sizeof(struct kvm_pic_state));
4503                 break;
4504         case KVM_IRQCHIP_IOAPIC:
4505                 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4506                 break;
4507         default:
4508                 r = -EINVAL;
4509                 break;
4510         }
4511         return r;
4512 }
4513
4514 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4515 {
4516         struct kvm_pic *pic = kvm->arch.vpic;
4517         int r;
4518
4519         r = 0;
4520         switch (chip->chip_id) {
4521         case KVM_IRQCHIP_PIC_MASTER:
4522                 spin_lock(&pic->lock);
4523                 memcpy(&pic->pics[0], &chip->chip.pic,
4524                         sizeof(struct kvm_pic_state));
4525                 spin_unlock(&pic->lock);
4526                 break;
4527         case KVM_IRQCHIP_PIC_SLAVE:
4528                 spin_lock(&pic->lock);
4529                 memcpy(&pic->pics[1], &chip->chip.pic,
4530                         sizeof(struct kvm_pic_state));
4531                 spin_unlock(&pic->lock);
4532                 break;
4533         case KVM_IRQCHIP_IOAPIC:
4534                 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4535                 break;
4536         default:
4537                 r = -EINVAL;
4538                 break;
4539         }
4540         kvm_pic_update_irq(pic);
4541         return r;
4542 }
4543
4544 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4545 {
4546         struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4547
4548         BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4549
4550         mutex_lock(&kps->lock);
4551         memcpy(ps, &kps->channels, sizeof(*ps));
4552         mutex_unlock(&kps->lock);
4553         return 0;
4554 }
4555
4556 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4557 {
4558         int i;
4559         struct kvm_pit *pit = kvm->arch.vpit;
4560
4561         mutex_lock(&pit->pit_state.lock);
4562         memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4563         for (i = 0; i < 3; i++)
4564                 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4565         mutex_unlock(&pit->pit_state.lock);
4566         return 0;
4567 }
4568
4569 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4570 {
4571         mutex_lock(&kvm->arch.vpit->pit_state.lock);
4572         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4573                 sizeof(ps->channels));
4574         ps->flags = kvm->arch.vpit->pit_state.flags;
4575         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4576         memset(&ps->reserved, 0, sizeof(ps->reserved));
4577         return 0;
4578 }
4579
4580 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4581 {
4582         int start = 0;
4583         int i;
4584         u32 prev_legacy, cur_legacy;
4585         struct kvm_pit *pit = kvm->arch.vpit;
4586
4587         mutex_lock(&pit->pit_state.lock);
4588         prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4589         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4590         if (!prev_legacy && cur_legacy)
4591                 start = 1;
4592         memcpy(&pit->pit_state.channels, &ps->channels,
4593                sizeof(pit->pit_state.channels));
4594         pit->pit_state.flags = ps->flags;
4595         for (i = 0; i < 3; i++)
4596                 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4597                                    start && i == 0);
4598         mutex_unlock(&pit->pit_state.lock);
4599         return 0;
4600 }
4601
4602 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4603                                  struct kvm_reinject_control *control)
4604 {
4605         struct kvm_pit *pit = kvm->arch.vpit;
4606
4607         if (!pit)
4608                 return -ENXIO;
4609
4610         /* pit->pit_state.lock was overloaded to prevent userspace from getting
4611          * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4612          * ioctls in parallel.  Use a separate lock if that ioctl isn't rare.
4613          */
4614         mutex_lock(&pit->pit_state.lock);
4615         kvm_pit_set_reinject(pit, control->pit_reinject);
4616         mutex_unlock(&pit->pit_state.lock);
4617
4618         return 0;
4619 }
4620
4621 /**
4622  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4623  * @kvm: kvm instance
4624  * @log: slot id and address to which we copy the log
4625  *
4626  * Steps 1-4 below provide general overview of dirty page logging. See
4627  * kvm_get_dirty_log_protect() function description for additional details.
4628  *
4629  * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4630  * always flush the TLB (step 4) even if previous step failed  and the dirty
4631  * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4632  * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4633  * writes will be marked dirty for next log read.
4634  *
4635  *   1. Take a snapshot of the bit and clear it if needed.
4636  *   2. Write protect the corresponding page.
4637  *   3. Copy the snapshot to the userspace.
4638  *   4. Flush TLB's if needed.
4639  */
4640 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4641 {
4642         bool flush = false;
4643         int r;
4644
4645         mutex_lock(&kvm->slots_lock);
4646
4647         /*
4648          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4649          */
4650         if (kvm_x86_ops->flush_log_dirty)
4651                 kvm_x86_ops->flush_log_dirty(kvm);
4652
4653         r = kvm_get_dirty_log_protect(kvm, log, &flush);
4654
4655         /*
4656          * All the TLBs can be flushed out of mmu lock, see the comments in
4657          * kvm_mmu_slot_remove_write_access().
4658          */
4659         lockdep_assert_held(&kvm->slots_lock);
4660         if (flush)
4661                 kvm_flush_remote_tlbs(kvm);
4662
4663         mutex_unlock(&kvm->slots_lock);
4664         return r;
4665 }
4666
4667 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4668 {
4669         bool flush = false;
4670         int r;
4671
4672         mutex_lock(&kvm->slots_lock);
4673
4674         /*
4675          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4676          */
4677         if (kvm_x86_ops->flush_log_dirty)
4678                 kvm_x86_ops->flush_log_dirty(kvm);
4679
4680         r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4681
4682         /*
4683          * All the TLBs can be flushed out of mmu lock, see the comments in
4684          * kvm_mmu_slot_remove_write_access().
4685          */
4686         lockdep_assert_held(&kvm->slots_lock);
4687         if (flush)
4688                 kvm_flush_remote_tlbs(kvm);
4689
4690         mutex_unlock(&kvm->slots_lock);
4691         return r;
4692 }
4693
4694 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4695                         bool line_status)
4696 {
4697         if (!irqchip_in_kernel(kvm))
4698                 return -ENXIO;
4699
4700         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4701                                         irq_event->irq, irq_event->level,
4702                                         line_status);
4703         return 0;
4704 }
4705
4706 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4707                             struct kvm_enable_cap *cap)
4708 {
4709         int r;
4710
4711         if (cap->flags)
4712                 return -EINVAL;
4713
4714         switch (cap->cap) {
4715         case KVM_CAP_DISABLE_QUIRKS:
4716                 kvm->arch.disabled_quirks = cap->args[0];
4717                 r = 0;
4718                 break;
4719         case KVM_CAP_SPLIT_IRQCHIP: {
4720                 mutex_lock(&kvm->lock);
4721                 r = -EINVAL;
4722                 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4723                         goto split_irqchip_unlock;
4724                 r = -EEXIST;
4725                 if (irqchip_in_kernel(kvm))
4726                         goto split_irqchip_unlock;
4727                 if (kvm->created_vcpus)
4728                         goto split_irqchip_unlock;
4729                 r = kvm_setup_empty_irq_routing(kvm);
4730                 if (r)
4731                         goto split_irqchip_unlock;
4732                 /* Pairs with irqchip_in_kernel. */
4733                 smp_wmb();
4734                 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4735                 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4736                 r = 0;
4737 split_irqchip_unlock:
4738                 mutex_unlock(&kvm->lock);
4739                 break;
4740         }
4741         case KVM_CAP_X2APIC_API:
4742                 r = -EINVAL;
4743                 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4744                         break;
4745
4746                 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4747                         kvm->arch.x2apic_format = true;
4748                 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4749                         kvm->arch.x2apic_broadcast_quirk_disabled = true;
4750
4751                 r = 0;
4752                 break;
4753         case KVM_CAP_X86_DISABLE_EXITS:
4754                 r = -EINVAL;
4755                 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4756                         break;
4757
4758                 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4759                         kvm_can_mwait_in_guest())
4760                         kvm->arch.mwait_in_guest = true;
4761                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4762                         kvm->arch.hlt_in_guest = true;
4763                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4764                         kvm->arch.pause_in_guest = true;
4765                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4766                         kvm->arch.cstate_in_guest = true;
4767                 r = 0;
4768                 break;
4769         case KVM_CAP_MSR_PLATFORM_INFO:
4770                 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4771                 r = 0;
4772                 break;
4773         case KVM_CAP_EXCEPTION_PAYLOAD:
4774                 kvm->arch.exception_payload_enabled = cap->args[0];
4775                 r = 0;
4776                 break;
4777         default:
4778                 r = -EINVAL;
4779                 break;
4780         }
4781         return r;
4782 }
4783
4784 long kvm_arch_vm_ioctl(struct file *filp,
4785                        unsigned int ioctl, unsigned long arg)
4786 {
4787         struct kvm *kvm = filp->private_data;
4788         void __user *argp = (void __user *)arg;
4789         int r = -ENOTTY;
4790         /*
4791          * This union makes it completely explicit to gcc-3.x
4792          * that these two variables' stack usage should be
4793          * combined, not added together.
4794          */
4795         union {
4796                 struct kvm_pit_state ps;
4797                 struct kvm_pit_state2 ps2;
4798                 struct kvm_pit_config pit_config;
4799         } u;
4800
4801         switch (ioctl) {
4802         case KVM_SET_TSS_ADDR:
4803                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4804                 break;
4805         case KVM_SET_IDENTITY_MAP_ADDR: {
4806                 u64 ident_addr;
4807
4808                 mutex_lock(&kvm->lock);
4809                 r = -EINVAL;
4810                 if (kvm->created_vcpus)
4811                         goto set_identity_unlock;
4812                 r = -EFAULT;
4813                 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4814                         goto set_identity_unlock;
4815                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4816 set_identity_unlock:
4817                 mutex_unlock(&kvm->lock);
4818                 break;
4819         }
4820         case KVM_SET_NR_MMU_PAGES:
4821                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4822                 break;
4823         case KVM_GET_NR_MMU_PAGES:
4824                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4825                 break;
4826         case KVM_CREATE_IRQCHIP: {
4827                 mutex_lock(&kvm->lock);
4828
4829                 r = -EEXIST;
4830                 if (irqchip_in_kernel(kvm))
4831                         goto create_irqchip_unlock;
4832
4833                 r = -EINVAL;
4834                 if (kvm->created_vcpus)
4835                         goto create_irqchip_unlock;
4836
4837                 r = kvm_pic_init(kvm);
4838                 if (r)
4839                         goto create_irqchip_unlock;
4840
4841                 r = kvm_ioapic_init(kvm);
4842                 if (r) {
4843                         kvm_pic_destroy(kvm);
4844                         goto create_irqchip_unlock;
4845                 }
4846
4847                 r = kvm_setup_default_irq_routing(kvm);
4848                 if (r) {
4849                         kvm_ioapic_destroy(kvm);
4850                         kvm_pic_destroy(kvm);
4851                         goto create_irqchip_unlock;
4852                 }
4853                 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4854                 smp_wmb();
4855                 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4856         create_irqchip_unlock:
4857                 mutex_unlock(&kvm->lock);
4858                 break;
4859         }
4860         case KVM_CREATE_PIT:
4861                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4862                 goto create_pit;
4863         case KVM_CREATE_PIT2:
4864                 r = -EFAULT;
4865                 if (copy_from_user(&u.pit_config, argp,
4866                                    sizeof(struct kvm_pit_config)))
4867                         goto out;
4868         create_pit:
4869                 mutex_lock(&kvm->lock);
4870                 r = -EEXIST;
4871                 if (kvm->arch.vpit)
4872                         goto create_pit_unlock;
4873                 r = -ENOMEM;
4874                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4875                 if (kvm->arch.vpit)
4876                         r = 0;
4877         create_pit_unlock:
4878                 mutex_unlock(&kvm->lock);
4879                 break;
4880         case KVM_GET_IRQCHIP: {
4881                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4882                 struct kvm_irqchip *chip;
4883
4884                 chip = memdup_user(argp, sizeof(*chip));
4885                 if (IS_ERR(chip)) {
4886                         r = PTR_ERR(chip);
4887                         goto out;
4888                 }
4889
4890                 r = -ENXIO;
4891                 if (!irqchip_kernel(kvm))
4892                         goto get_irqchip_out;
4893                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4894                 if (r)
4895                         goto get_irqchip_out;
4896                 r = -EFAULT;
4897                 if (copy_to_user(argp, chip, sizeof(*chip)))
4898                         goto get_irqchip_out;
4899                 r = 0;
4900         get_irqchip_out:
4901                 kfree(chip);
4902                 break;
4903         }
4904         case KVM_SET_IRQCHIP: {
4905                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4906                 struct kvm_irqchip *chip;
4907
4908                 chip = memdup_user(argp, sizeof(*chip));
4909                 if (IS_ERR(chip)) {
4910                         r = PTR_ERR(chip);
4911                         goto out;
4912                 }
4913
4914                 r = -ENXIO;
4915                 if (!irqchip_kernel(kvm))
4916                         goto set_irqchip_out;
4917                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4918                 if (r)
4919                         goto set_irqchip_out;
4920                 r = 0;
4921         set_irqchip_out:
4922                 kfree(chip);
4923                 break;
4924         }
4925         case KVM_GET_PIT: {
4926                 r = -EFAULT;
4927                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4928                         goto out;
4929                 r = -ENXIO;
4930                 if (!kvm->arch.vpit)
4931                         goto out;
4932                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4933                 if (r)
4934                         goto out;
4935                 r = -EFAULT;
4936                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4937                         goto out;
4938                 r = 0;
4939                 break;
4940         }
4941         case KVM_SET_PIT: {
4942                 r = -EFAULT;
4943                 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
4944                         goto out;
4945                 r = -ENXIO;
4946                 if (!kvm->arch.vpit)
4947                         goto out;
4948                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4949                 break;
4950         }
4951         case KVM_GET_PIT2: {
4952                 r = -ENXIO;
4953                 if (!kvm->arch.vpit)
4954                         goto out;
4955                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4956                 if (r)
4957                         goto out;
4958                 r = -EFAULT;
4959                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4960                         goto out;
4961                 r = 0;
4962                 break;
4963         }
4964         case KVM_SET_PIT2: {
4965                 r = -EFAULT;
4966                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4967                         goto out;
4968                 r = -ENXIO;
4969                 if (!kvm->arch.vpit)
4970                         goto out;
4971                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4972                 break;
4973         }
4974         case KVM_REINJECT_CONTROL: {
4975                 struct kvm_reinject_control control;
4976                 r =  -EFAULT;
4977                 if (copy_from_user(&control, argp, sizeof(control)))
4978                         goto out;
4979                 r = kvm_vm_ioctl_reinject(kvm, &control);
4980                 break;
4981         }
4982         case KVM_SET_BOOT_CPU_ID:
4983                 r = 0;
4984                 mutex_lock(&kvm->lock);
4985                 if (kvm->created_vcpus)
4986                         r = -EBUSY;
4987                 else
4988                         kvm->arch.bsp_vcpu_id = arg;
4989                 mutex_unlock(&kvm->lock);
4990                 break;
4991         case KVM_XEN_HVM_CONFIG: {
4992                 struct kvm_xen_hvm_config xhc;
4993                 r = -EFAULT;
4994                 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4995                         goto out;
4996                 r = -EINVAL;
4997                 if (xhc.flags)
4998                         goto out;
4999                 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5000                 r = 0;
5001                 break;
5002         }
5003         case KVM_SET_CLOCK: {
5004                 struct kvm_clock_data user_ns;
5005                 u64 now_ns;
5006
5007                 r = -EFAULT;
5008                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5009                         goto out;
5010
5011                 r = -EINVAL;
5012                 if (user_ns.flags)
5013                         goto out;
5014
5015                 r = 0;
5016                 /*
5017                  * TODO: userspace has to take care of races with VCPU_RUN, so
5018                  * kvm_gen_update_masterclock() can be cut down to locked
5019                  * pvclock_update_vm_gtod_copy().
5020                  */
5021                 kvm_gen_update_masterclock(kvm);
5022                 now_ns = get_kvmclock_ns(kvm);
5023                 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5024                 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5025                 break;
5026         }
5027         case KVM_GET_CLOCK: {
5028                 struct kvm_clock_data user_ns;
5029                 u64 now_ns;
5030
5031                 now_ns = get_kvmclock_ns(kvm);
5032                 user_ns.clock = now_ns;
5033                 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5034                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5035
5036                 r = -EFAULT;
5037                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5038                         goto out;
5039                 r = 0;
5040                 break;
5041         }
5042         case KVM_MEMORY_ENCRYPT_OP: {
5043                 r = -ENOTTY;
5044                 if (kvm_x86_ops->mem_enc_op)
5045                         r = kvm_x86_ops->mem_enc_op(kvm, argp);
5046                 break;
5047         }
5048         case KVM_MEMORY_ENCRYPT_REG_REGION: {
5049                 struct kvm_enc_region region;
5050
5051                 r = -EFAULT;
5052                 if (copy_from_user(&region, argp, sizeof(region)))
5053                         goto out;
5054
5055                 r = -ENOTTY;
5056                 if (kvm_x86_ops->mem_enc_reg_region)
5057                         r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
5058                 break;
5059         }
5060         case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5061                 struct kvm_enc_region region;
5062
5063                 r = -EFAULT;
5064                 if (copy_from_user(&region, argp, sizeof(region)))
5065                         goto out;
5066
5067                 r = -ENOTTY;
5068                 if (kvm_x86_ops->mem_enc_unreg_region)
5069                         r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
5070                 break;
5071         }
5072         case KVM_HYPERV_EVENTFD: {
5073                 struct kvm_hyperv_eventfd hvevfd;
5074
5075                 r = -EFAULT;
5076                 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5077                         goto out;
5078                 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5079                 break;
5080         }
5081         case KVM_SET_PMU_EVENT_FILTER:
5082                 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5083                 break;
5084         default:
5085                 r = -ENOTTY;
5086         }
5087 out:
5088         return r;
5089 }
5090
5091 static void kvm_init_msr_list(void)
5092 {
5093         struct x86_pmu_capability x86_pmu;
5094         u32 dummy[2];
5095         unsigned i, j;
5096
5097         BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5098                          "Please update the fixed PMCs in msrs_to_save[]");
5099
5100         perf_get_x86_pmu_capability(&x86_pmu);
5101
5102         for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
5103                 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
5104                         continue;
5105
5106                 /*
5107                  * Even MSRs that are valid in the host may not be exposed
5108                  * to the guests in some cases.
5109                  */
5110                 switch (msrs_to_save[i]) {
5111                 case MSR_IA32_BNDCFGS:
5112                         if (!kvm_mpx_supported())
5113                                 continue;
5114                         break;
5115                 case MSR_TSC_AUX:
5116                         if (!kvm_x86_ops->rdtscp_supported())
5117                                 continue;
5118                         break;
5119                 case MSR_IA32_RTIT_CTL:
5120                 case MSR_IA32_RTIT_STATUS:
5121                         if (!kvm_x86_ops->pt_supported())
5122                                 continue;
5123                         break;
5124                 case MSR_IA32_RTIT_CR3_MATCH:
5125                         if (!kvm_x86_ops->pt_supported() ||
5126                             !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5127                                 continue;
5128                         break;
5129                 case MSR_IA32_RTIT_OUTPUT_BASE:
5130                 case MSR_IA32_RTIT_OUTPUT_MASK:
5131                         if (!kvm_x86_ops->pt_supported() ||
5132                                 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5133                                  !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5134                                 continue;
5135                         break;
5136                 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5137                         if (!kvm_x86_ops->pt_supported() ||
5138                                 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
5139                                 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5140                                 continue;
5141                         break;
5142                 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5143                         if (msrs_to_save[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5144                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5145                                 continue;
5146                         break;
5147                 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5148                         if (msrs_to_save[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5149                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5150                                 continue;
5151                 }
5152                 default:
5153                         break;
5154                 }
5155
5156                 if (j < i)
5157                         msrs_to_save[j] = msrs_to_save[i];
5158                 j++;
5159         }
5160         num_msrs_to_save = j;
5161
5162         for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
5163                 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5164                         continue;
5165
5166                 if (j < i)
5167                         emulated_msrs[j] = emulated_msrs[i];
5168                 j++;
5169         }
5170         num_emulated_msrs = j;
5171
5172         for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5173                 struct kvm_msr_entry msr;
5174
5175                 msr.index = msr_based_features[i];
5176                 if (kvm_get_msr_feature(&msr))
5177                         continue;
5178
5179                 if (j < i)
5180                         msr_based_features[j] = msr_based_features[i];
5181                 j++;
5182         }
5183         num_msr_based_features = j;
5184 }
5185
5186 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5187                            const void *v)
5188 {
5189         int handled = 0;
5190         int n;
5191
5192         do {
5193                 n = min(len, 8);
5194                 if (!(lapic_in_kernel(vcpu) &&
5195                       !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5196                     && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5197                         break;
5198                 handled += n;
5199                 addr += n;
5200                 len -= n;
5201                 v += n;
5202         } while (len);
5203
5204         return handled;
5205 }
5206
5207 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5208 {
5209         int handled = 0;
5210         int n;
5211
5212         do {
5213                 n = min(len, 8);
5214                 if (!(lapic_in_kernel(vcpu) &&
5215                       !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5216                                          addr, n, v))
5217                     && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5218                         break;
5219                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5220                 handled += n;
5221                 addr += n;
5222                 len -= n;
5223                 v += n;
5224         } while (len);
5225
5226         return handled;
5227 }
5228
5229 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5230                         struct kvm_segment *var, int seg)
5231 {
5232         kvm_x86_ops->set_segment(vcpu, var, seg);
5233 }
5234
5235 void kvm_get_segment(struct kvm_vcpu *vcpu,
5236                      struct kvm_segment *var, int seg)
5237 {
5238         kvm_x86_ops->get_segment(vcpu, var, seg);
5239 }
5240
5241 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5242                            struct x86_exception *exception)
5243 {
5244         gpa_t t_gpa;
5245
5246         BUG_ON(!mmu_is_nested(vcpu));
5247
5248         /* NPT walks are always user-walks */
5249         access |= PFERR_USER_MASK;
5250         t_gpa  = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5251
5252         return t_gpa;
5253 }
5254
5255 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5256                               struct x86_exception *exception)
5257 {
5258         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5259         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5260 }
5261
5262  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5263                                 struct x86_exception *exception)
5264 {
5265         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5266         access |= PFERR_FETCH_MASK;
5267         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5268 }
5269
5270 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5271                                struct x86_exception *exception)
5272 {
5273         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5274         access |= PFERR_WRITE_MASK;
5275         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5276 }
5277
5278 /* uses this to access any guest's mapped memory without checking CPL */
5279 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5280                                 struct x86_exception *exception)
5281 {
5282         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5283 }
5284
5285 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5286                                       struct kvm_vcpu *vcpu, u32 access,
5287                                       struct x86_exception *exception)
5288 {
5289         void *data = val;
5290         int r = X86EMUL_CONTINUE;
5291
5292         while (bytes) {
5293                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5294                                                             exception);
5295                 unsigned offset = addr & (PAGE_SIZE-1);
5296                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5297                 int ret;
5298
5299                 if (gpa == UNMAPPED_GVA)
5300                         return X86EMUL_PROPAGATE_FAULT;
5301                 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5302                                                offset, toread);
5303                 if (ret < 0) {
5304                         r = X86EMUL_IO_NEEDED;
5305                         goto out;
5306                 }
5307
5308                 bytes -= toread;
5309                 data += toread;
5310                 addr += toread;
5311         }
5312 out:
5313         return r;
5314 }
5315
5316 /* used for instruction fetching */
5317 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5318                                 gva_t addr, void *val, unsigned int bytes,
5319                                 struct x86_exception *exception)
5320 {
5321         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5322         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5323         unsigned offset;
5324         int ret;
5325
5326         /* Inline kvm_read_guest_virt_helper for speed.  */
5327         gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5328                                                     exception);
5329         if (unlikely(gpa == UNMAPPED_GVA))
5330                 return X86EMUL_PROPAGATE_FAULT;
5331
5332         offset = addr & (PAGE_SIZE-1);
5333         if (WARN_ON(offset + bytes > PAGE_SIZE))
5334                 bytes = (unsigned)PAGE_SIZE - offset;
5335         ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5336                                        offset, bytes);
5337         if (unlikely(ret < 0))
5338                 return X86EMUL_IO_NEEDED;
5339
5340         return X86EMUL_CONTINUE;
5341 }
5342
5343 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5344                                gva_t addr, void *val, unsigned int bytes,
5345                                struct x86_exception *exception)
5346 {
5347         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5348
5349         /*
5350          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5351          * is returned, but our callers are not ready for that and they blindly
5352          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5353          * uninitialized kernel stack memory into cr2 and error code.
5354          */
5355         memset(exception, 0, sizeof(*exception));
5356         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5357                                           exception);
5358 }
5359 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5360
5361 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5362                              gva_t addr, void *val, unsigned int bytes,
5363                              struct x86_exception *exception, bool system)
5364 {
5365         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5366         u32 access = 0;
5367
5368         if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5369                 access |= PFERR_USER_MASK;
5370
5371         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5372 }
5373
5374 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5375                 unsigned long addr, void *val, unsigned int bytes)
5376 {
5377         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5378         int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5379
5380         return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5381 }
5382
5383 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5384                                       struct kvm_vcpu *vcpu, u32 access,
5385                                       struct x86_exception *exception)
5386 {
5387         void *data = val;
5388         int r = X86EMUL_CONTINUE;
5389
5390         while (bytes) {
5391                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5392                                                              access,
5393                                                              exception);
5394                 unsigned offset = addr & (PAGE_SIZE-1);
5395                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5396                 int ret;
5397
5398                 if (gpa == UNMAPPED_GVA)
5399                         return X86EMUL_PROPAGATE_FAULT;
5400                 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5401                 if (ret < 0) {
5402                         r = X86EMUL_IO_NEEDED;
5403                         goto out;
5404                 }
5405
5406                 bytes -= towrite;
5407                 data += towrite;
5408                 addr += towrite;
5409         }
5410 out:
5411         return r;
5412 }
5413
5414 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5415                               unsigned int bytes, struct x86_exception *exception,
5416                               bool system)
5417 {
5418         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5419         u32 access = PFERR_WRITE_MASK;
5420
5421         if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5422                 access |= PFERR_USER_MASK;
5423
5424         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5425                                            access, exception);
5426 }
5427
5428 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5429                                 unsigned int bytes, struct x86_exception *exception)
5430 {
5431         /* kvm_write_guest_virt_system can pull in tons of pages. */
5432         vcpu->arch.l1tf_flush_l1d = true;
5433
5434         /*
5435          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5436          * is returned, but our callers are not ready for that and they blindly
5437          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5438          * uninitialized kernel stack memory into cr2 and error code.
5439          */
5440         memset(exception, 0, sizeof(*exception));
5441         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5442                                            PFERR_WRITE_MASK, exception);
5443 }
5444 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5445
5446 int handle_ud(struct kvm_vcpu *vcpu)
5447 {
5448         int emul_type = EMULTYPE_TRAP_UD;
5449         char sig[5]; /* ud2; .ascii "kvm" */
5450         struct x86_exception e;
5451
5452         if (force_emulation_prefix &&
5453             kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5454                                 sig, sizeof(sig), &e) == 0 &&
5455             memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5456                 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5457                 emul_type = EMULTYPE_TRAP_UD_FORCED;
5458         }
5459
5460         return kvm_emulate_instruction(vcpu, emul_type);
5461 }
5462 EXPORT_SYMBOL_GPL(handle_ud);
5463
5464 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5465                             gpa_t gpa, bool write)
5466 {
5467         /* For APIC access vmexit */
5468         if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5469                 return 1;
5470
5471         if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5472                 trace_vcpu_match_mmio(gva, gpa, write, true);
5473                 return 1;
5474         }
5475
5476         return 0;
5477 }
5478
5479 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5480                                 gpa_t *gpa, struct x86_exception *exception,
5481                                 bool write)
5482 {
5483         u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5484                 | (write ? PFERR_WRITE_MASK : 0);
5485
5486         /*
5487          * currently PKRU is only applied to ept enabled guest so
5488          * there is no pkey in EPT page table for L1 guest or EPT
5489          * shadow page table for L2 guest.
5490          */
5491         if (vcpu_match_mmio_gva(vcpu, gva)
5492             && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5493                                  vcpu->arch.mmio_access, 0, access)) {
5494                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5495                                         (gva & (PAGE_SIZE - 1));
5496                 trace_vcpu_match_mmio(gva, *gpa, write, false);
5497                 return 1;
5498         }
5499
5500         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5501
5502         if (*gpa == UNMAPPED_GVA)
5503                 return -1;
5504
5505         return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5506 }
5507
5508 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5509                         const void *val, int bytes)
5510 {
5511         int ret;
5512
5513         ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5514         if (ret < 0)
5515                 return 0;
5516         kvm_page_track_write(vcpu, gpa, val, bytes);
5517         return 1;
5518 }
5519
5520 struct read_write_emulator_ops {
5521         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5522                                   int bytes);
5523         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5524                                   void *val, int bytes);
5525         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5526                                int bytes, void *val);
5527         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5528                                     void *val, int bytes);
5529         bool write;
5530 };
5531
5532 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5533 {
5534         if (vcpu->mmio_read_completed) {
5535                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5536                                vcpu->mmio_fragments[0].gpa, val);
5537                 vcpu->mmio_read_completed = 0;
5538                 return 1;
5539         }
5540
5541         return 0;
5542 }
5543
5544 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5545                         void *val, int bytes)
5546 {
5547         return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5548 }
5549
5550 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5551                          void *val, int bytes)
5552 {
5553         return emulator_write_phys(vcpu, gpa, val, bytes);
5554 }
5555
5556 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5557 {
5558         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5559         return vcpu_mmio_write(vcpu, gpa, bytes, val);
5560 }
5561
5562 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5563                           void *val, int bytes)
5564 {
5565         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5566         return X86EMUL_IO_NEEDED;
5567 }
5568
5569 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5570                            void *val, int bytes)
5571 {
5572         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5573
5574         memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5575         return X86EMUL_CONTINUE;
5576 }
5577
5578 static const struct read_write_emulator_ops read_emultor = {
5579         .read_write_prepare = read_prepare,
5580         .read_write_emulate = read_emulate,
5581         .read_write_mmio = vcpu_mmio_read,
5582         .read_write_exit_mmio = read_exit_mmio,
5583 };
5584
5585 static const struct read_write_emulator_ops write_emultor = {
5586         .read_write_emulate = write_emulate,
5587         .read_write_mmio = write_mmio,
5588         .read_write_exit_mmio = write_exit_mmio,
5589         .write = true,
5590 };
5591
5592 static int emulator_read_write_onepage(unsigned long addr, void *val,
5593                                        unsigned int bytes,
5594                                        struct x86_exception *exception,
5595                                        struct kvm_vcpu *vcpu,
5596                                        const struct read_write_emulator_ops *ops)
5597 {
5598         gpa_t gpa;
5599         int handled, ret;
5600         bool write = ops->write;
5601         struct kvm_mmio_fragment *frag;
5602         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5603
5604         /*
5605          * If the exit was due to a NPF we may already have a GPA.
5606          * If the GPA is present, use it to avoid the GVA to GPA table walk.
5607          * Note, this cannot be used on string operations since string
5608          * operation using rep will only have the initial GPA from the NPF
5609          * occurred.
5610          */
5611         if (vcpu->arch.gpa_available &&
5612             emulator_can_use_gpa(ctxt) &&
5613             (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5614                 gpa = vcpu->arch.gpa_val;
5615                 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5616         } else {
5617                 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5618                 if (ret < 0)
5619                         return X86EMUL_PROPAGATE_FAULT;
5620         }
5621
5622         if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5623                 return X86EMUL_CONTINUE;
5624
5625         /*
5626          * Is this MMIO handled locally?
5627          */
5628         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5629         if (handled == bytes)
5630                 return X86EMUL_CONTINUE;
5631
5632         gpa += handled;
5633         bytes -= handled;
5634         val += handled;
5635
5636         WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5637         frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5638         frag->gpa = gpa;
5639         frag->data = val;
5640         frag->len = bytes;
5641         return X86EMUL_CONTINUE;
5642 }
5643
5644 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5645                         unsigned long addr,
5646                         void *val, unsigned int bytes,
5647                         struct x86_exception *exception,
5648                         const struct read_write_emulator_ops *ops)
5649 {
5650         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5651         gpa_t gpa;
5652         int rc;
5653
5654         if (ops->read_write_prepare &&
5655                   ops->read_write_prepare(vcpu, val, bytes))
5656                 return X86EMUL_CONTINUE;
5657
5658         vcpu->mmio_nr_fragments = 0;
5659
5660         /* Crossing a page boundary? */
5661         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5662                 int now;
5663
5664                 now = -addr & ~PAGE_MASK;
5665                 rc = emulator_read_write_onepage(addr, val, now, exception,
5666                                                  vcpu, ops);
5667
5668                 if (rc != X86EMUL_CONTINUE)
5669                         return rc;
5670                 addr += now;
5671                 if (ctxt->mode != X86EMUL_MODE_PROT64)
5672                         addr = (u32)addr;
5673                 val += now;
5674                 bytes -= now;
5675         }
5676
5677         rc = emulator_read_write_onepage(addr, val, bytes, exception,
5678                                          vcpu, ops);
5679         if (rc != X86EMUL_CONTINUE)
5680                 return rc;
5681
5682         if (!vcpu->mmio_nr_fragments)
5683                 return rc;
5684
5685         gpa = vcpu->mmio_fragments[0].gpa;
5686
5687         vcpu->mmio_needed = 1;
5688         vcpu->mmio_cur_fragment = 0;
5689
5690         vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5691         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5692         vcpu->run->exit_reason = KVM_EXIT_MMIO;
5693         vcpu->run->mmio.phys_addr = gpa;
5694
5695         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5696 }
5697
5698 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5699                                   unsigned long addr,
5700                                   void *val,
5701                                   unsigned int bytes,
5702                                   struct x86_exception *exception)
5703 {
5704         return emulator_read_write(ctxt, addr, val, bytes,
5705                                    exception, &read_emultor);
5706 }
5707
5708 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5709                             unsigned long addr,
5710                             const void *val,
5711                             unsigned int bytes,
5712                             struct x86_exception *exception)
5713 {
5714         return emulator_read_write(ctxt, addr, (void *)val, bytes,
5715                                    exception, &write_emultor);
5716 }
5717
5718 #define CMPXCHG_TYPE(t, ptr, old, new) \
5719         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5720
5721 #ifdef CONFIG_X86_64
5722 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5723 #else
5724 #  define CMPXCHG64(ptr, old, new) \
5725         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5726 #endif
5727
5728 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5729                                      unsigned long addr,
5730                                      const void *old,
5731                                      const void *new,
5732                                      unsigned int bytes,
5733                                      struct x86_exception *exception)
5734 {
5735         struct kvm_host_map map;
5736         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5737         gpa_t gpa;
5738         char *kaddr;
5739         bool exchanged;
5740
5741         /* guests cmpxchg8b have to be emulated atomically */
5742         if (bytes > 8 || (bytes & (bytes - 1)))
5743                 goto emul_write;
5744
5745         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5746
5747         if (gpa == UNMAPPED_GVA ||
5748             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5749                 goto emul_write;
5750
5751         if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5752                 goto emul_write;
5753
5754         if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5755                 goto emul_write;
5756
5757         kaddr = map.hva + offset_in_page(gpa);
5758
5759         switch (bytes) {
5760         case 1:
5761                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5762                 break;
5763         case 2:
5764                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5765                 break;
5766         case 4:
5767                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5768                 break;
5769         case 8:
5770                 exchanged = CMPXCHG64(kaddr, old, new);
5771                 break;
5772         default:
5773                 BUG();
5774         }
5775
5776         kvm_vcpu_unmap(vcpu, &map, true);
5777
5778         if (!exchanged)
5779                 return X86EMUL_CMPXCHG_FAILED;
5780
5781         kvm_page_track_write(vcpu, gpa, new, bytes);
5782
5783         return X86EMUL_CONTINUE;
5784
5785 emul_write:
5786         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5787
5788         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5789 }
5790
5791 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5792 {
5793         int r = 0, i;
5794
5795         for (i = 0; i < vcpu->arch.pio.count; i++) {
5796                 if (vcpu->arch.pio.in)
5797                         r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5798                                             vcpu->arch.pio.size, pd);
5799                 else
5800                         r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5801                                              vcpu->arch.pio.port, vcpu->arch.pio.size,
5802                                              pd);
5803                 if (r)
5804                         break;
5805                 pd += vcpu->arch.pio.size;
5806         }
5807         return r;
5808 }
5809
5810 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5811                                unsigned short port, void *val,
5812                                unsigned int count, bool in)
5813 {
5814         vcpu->arch.pio.port = port;
5815         vcpu->arch.pio.in = in;
5816         vcpu->arch.pio.count  = count;
5817         vcpu->arch.pio.size = size;
5818
5819         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5820                 vcpu->arch.pio.count = 0;
5821                 return 1;
5822         }
5823
5824         vcpu->run->exit_reason = KVM_EXIT_IO;
5825         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5826         vcpu->run->io.size = size;
5827         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5828         vcpu->run->io.count = count;
5829         vcpu->run->io.port = port;
5830
5831         return 0;
5832 }
5833
5834 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5835                                     int size, unsigned short port, void *val,
5836                                     unsigned int count)
5837 {
5838         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5839         int ret;
5840
5841         if (vcpu->arch.pio.count)
5842                 goto data_avail;
5843
5844         memset(vcpu->arch.pio_data, 0, size * count);
5845
5846         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5847         if (ret) {
5848 data_avail:
5849                 memcpy(val, vcpu->arch.pio_data, size * count);
5850                 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5851                 vcpu->arch.pio.count = 0;
5852                 return 1;
5853         }
5854
5855         return 0;
5856 }
5857
5858 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5859                                      int size, unsigned short port,
5860                                      const void *val, unsigned int count)
5861 {
5862         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5863
5864         memcpy(vcpu->arch.pio_data, val, size * count);
5865         trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5866         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5867 }
5868
5869 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5870 {
5871         return kvm_x86_ops->get_segment_base(vcpu, seg);
5872 }
5873
5874 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5875 {
5876         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5877 }
5878
5879 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5880 {
5881         if (!need_emulate_wbinvd(vcpu))
5882                 return X86EMUL_CONTINUE;
5883
5884         if (kvm_x86_ops->has_wbinvd_exit()) {
5885                 int cpu = get_cpu();
5886
5887                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5888                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5889                                 wbinvd_ipi, NULL, 1);
5890                 put_cpu();
5891                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5892         } else
5893                 wbinvd();
5894         return X86EMUL_CONTINUE;
5895 }
5896
5897 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5898 {
5899         kvm_emulate_wbinvd_noskip(vcpu);
5900         return kvm_skip_emulated_instruction(vcpu);
5901 }
5902 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5903
5904
5905
5906 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5907 {
5908         kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5909 }
5910
5911 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5912                            unsigned long *dest)
5913 {
5914         return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5915 }
5916
5917 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5918                            unsigned long value)
5919 {
5920
5921         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5922 }
5923
5924 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5925 {
5926         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5927 }
5928
5929 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5930 {
5931         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5932         unsigned long value;
5933
5934         switch (cr) {
5935         case 0:
5936                 value = kvm_read_cr0(vcpu);
5937                 break;
5938         case 2:
5939                 value = vcpu->arch.cr2;
5940                 break;
5941         case 3:
5942                 value = kvm_read_cr3(vcpu);
5943                 break;
5944         case 4:
5945                 value = kvm_read_cr4(vcpu);
5946                 break;
5947         case 8:
5948                 value = kvm_get_cr8(vcpu);
5949                 break;
5950         default:
5951                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5952                 return 0;
5953         }
5954
5955         return value;
5956 }
5957
5958 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5959 {
5960         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5961         int res = 0;
5962
5963         switch (cr) {
5964         case 0:
5965                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5966                 break;
5967         case 2:
5968                 vcpu->arch.cr2 = val;
5969                 break;
5970         case 3:
5971                 res = kvm_set_cr3(vcpu, val);
5972                 break;
5973         case 4:
5974                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5975                 break;
5976         case 8:
5977                 res = kvm_set_cr8(vcpu, val);
5978                 break;
5979         default:
5980                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5981                 res = -1;
5982         }
5983
5984         return res;
5985 }
5986
5987 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5988 {
5989         return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5990 }
5991
5992 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5993 {
5994         kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5995 }
5996
5997 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5998 {
5999         kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
6000 }
6001
6002 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6003 {
6004         kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
6005 }
6006
6007 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6008 {
6009         kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
6010 }
6011
6012 static unsigned long emulator_get_cached_segment_base(
6013         struct x86_emulate_ctxt *ctxt, int seg)
6014 {
6015         return get_segment_base(emul_to_vcpu(ctxt), seg);
6016 }
6017
6018 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6019                                  struct desc_struct *desc, u32 *base3,
6020                                  int seg)
6021 {
6022         struct kvm_segment var;
6023
6024         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6025         *selector = var.selector;
6026
6027         if (var.unusable) {
6028                 memset(desc, 0, sizeof(*desc));
6029                 if (base3)
6030                         *base3 = 0;
6031                 return false;
6032         }
6033
6034         if (var.g)
6035                 var.limit >>= 12;
6036         set_desc_limit(desc, var.limit);
6037         set_desc_base(desc, (unsigned long)var.base);
6038 #ifdef CONFIG_X86_64
6039         if (base3)
6040                 *base3 = var.base >> 32;
6041 #endif
6042         desc->type = var.type;
6043         desc->s = var.s;
6044         desc->dpl = var.dpl;
6045         desc->p = var.present;
6046         desc->avl = var.avl;
6047         desc->l = var.l;
6048         desc->d = var.db;
6049         desc->g = var.g;
6050
6051         return true;
6052 }
6053
6054 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6055                                  struct desc_struct *desc, u32 base3,
6056                                  int seg)
6057 {
6058         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6059         struct kvm_segment var;
6060
6061         var.selector = selector;
6062         var.base = get_desc_base(desc);
6063 #ifdef CONFIG_X86_64
6064         var.base |= ((u64)base3) << 32;
6065 #endif
6066         var.limit = get_desc_limit(desc);
6067         if (desc->g)
6068                 var.limit = (var.limit << 12) | 0xfff;
6069         var.type = desc->type;
6070         var.dpl = desc->dpl;
6071         var.db = desc->d;
6072         var.s = desc->s;
6073         var.l = desc->l;
6074         var.g = desc->g;
6075         var.avl = desc->avl;
6076         var.present = desc->p;
6077         var.unusable = !var.present;
6078         var.padding = 0;
6079
6080         kvm_set_segment(vcpu, &var, seg);
6081         return;
6082 }
6083
6084 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6085                             u32 msr_index, u64 *pdata)
6086 {
6087         return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6088 }
6089
6090 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6091                             u32 msr_index, u64 data)
6092 {
6093         return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6094 }
6095
6096 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6097 {
6098         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6099
6100         return vcpu->arch.smbase;
6101 }
6102
6103 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6104 {
6105         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6106
6107         vcpu->arch.smbase = smbase;
6108 }
6109
6110 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6111                               u32 pmc)
6112 {
6113         return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
6114 }
6115
6116 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6117                              u32 pmc, u64 *pdata)
6118 {
6119         return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6120 }
6121
6122 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6123 {
6124         emul_to_vcpu(ctxt)->arch.halt_request = 1;
6125 }
6126
6127 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6128                               struct x86_instruction_info *info,
6129                               enum x86_intercept_stage stage)
6130 {
6131         return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
6132 }
6133
6134 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6135                         u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
6136 {
6137         return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
6138 }
6139
6140 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6141 {
6142         return kvm_register_read(emul_to_vcpu(ctxt), reg);
6143 }
6144
6145 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6146 {
6147         kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6148 }
6149
6150 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6151 {
6152         kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6153 }
6154
6155 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6156 {
6157         return emul_to_vcpu(ctxt)->arch.hflags;
6158 }
6159
6160 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6161 {
6162         emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6163 }
6164
6165 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6166                                   const char *smstate)
6167 {
6168         return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6169 }
6170
6171 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6172 {
6173         kvm_smm_changed(emul_to_vcpu(ctxt));
6174 }
6175
6176 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6177 {
6178         return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6179 }
6180
6181 static const struct x86_emulate_ops emulate_ops = {
6182         .read_gpr            = emulator_read_gpr,
6183         .write_gpr           = emulator_write_gpr,
6184         .read_std            = emulator_read_std,
6185         .write_std           = emulator_write_std,
6186         .read_phys           = kvm_read_guest_phys_system,
6187         .fetch               = kvm_fetch_guest_virt,
6188         .read_emulated       = emulator_read_emulated,
6189         .write_emulated      = emulator_write_emulated,
6190         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
6191         .invlpg              = emulator_invlpg,
6192         .pio_in_emulated     = emulator_pio_in_emulated,
6193         .pio_out_emulated    = emulator_pio_out_emulated,
6194         .get_segment         = emulator_get_segment,
6195         .set_segment         = emulator_set_segment,
6196         .get_cached_segment_base = emulator_get_cached_segment_base,
6197         .get_gdt             = emulator_get_gdt,
6198         .get_idt             = emulator_get_idt,
6199         .set_gdt             = emulator_set_gdt,
6200         .set_idt             = emulator_set_idt,
6201         .get_cr              = emulator_get_cr,
6202         .set_cr              = emulator_set_cr,
6203         .cpl                 = emulator_get_cpl,
6204         .get_dr              = emulator_get_dr,
6205         .set_dr              = emulator_set_dr,
6206         .get_smbase          = emulator_get_smbase,
6207         .set_smbase          = emulator_set_smbase,
6208         .set_msr             = emulator_set_msr,
6209         .get_msr             = emulator_get_msr,
6210         .check_pmc           = emulator_check_pmc,
6211         .read_pmc            = emulator_read_pmc,
6212         .halt                = emulator_halt,
6213         .wbinvd              = emulator_wbinvd,
6214         .fix_hypercall       = emulator_fix_hypercall,
6215         .intercept           = emulator_intercept,
6216         .get_cpuid           = emulator_get_cpuid,
6217         .set_nmi_mask        = emulator_set_nmi_mask,
6218         .get_hflags          = emulator_get_hflags,
6219         .set_hflags          = emulator_set_hflags,
6220         .pre_leave_smm       = emulator_pre_leave_smm,
6221         .post_leave_smm      = emulator_post_leave_smm,
6222         .set_xcr             = emulator_set_xcr,
6223 };
6224
6225 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6226 {
6227         u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6228         /*
6229          * an sti; sti; sequence only disable interrupts for the first
6230          * instruction. So, if the last instruction, be it emulated or
6231          * not, left the system with the INT_STI flag enabled, it
6232          * means that the last instruction is an sti. We should not
6233          * leave the flag on in this case. The same goes for mov ss
6234          */
6235         if (int_shadow & mask)
6236                 mask = 0;
6237         if (unlikely(int_shadow || mask)) {
6238                 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6239                 if (!mask)
6240                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6241         }
6242 }
6243
6244 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6245 {
6246         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6247         if (ctxt->exception.vector == PF_VECTOR)
6248                 return kvm_propagate_fault(vcpu, &ctxt->exception);
6249
6250         if (ctxt->exception.error_code_valid)
6251                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6252                                       ctxt->exception.error_code);
6253         else
6254                 kvm_queue_exception(vcpu, ctxt->exception.vector);
6255         return false;
6256 }
6257
6258 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6259 {
6260         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6261         int cs_db, cs_l;
6262
6263         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6264
6265         ctxt->eflags = kvm_get_rflags(vcpu);
6266         ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6267
6268         ctxt->eip = kvm_rip_read(vcpu);
6269         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
6270                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
6271                      (cs_l && is_long_mode(vcpu))       ? X86EMUL_MODE_PROT64 :
6272                      cs_db                              ? X86EMUL_MODE_PROT32 :
6273                                                           X86EMUL_MODE_PROT16;
6274         BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6275         BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6276         BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6277
6278         init_decode_cache(ctxt);
6279         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6280 }
6281
6282 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6283 {
6284         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6285         int ret;
6286
6287         init_emulate_ctxt(vcpu);
6288
6289         ctxt->op_bytes = 2;
6290         ctxt->ad_bytes = 2;
6291         ctxt->_eip = ctxt->eip + inc_eip;
6292         ret = emulate_int_real(ctxt, irq);
6293
6294         if (ret != X86EMUL_CONTINUE) {
6295                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6296         } else {
6297                 ctxt->eip = ctxt->_eip;
6298                 kvm_rip_write(vcpu, ctxt->eip);
6299                 kvm_set_rflags(vcpu, ctxt->eflags);
6300         }
6301 }
6302 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6303
6304 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6305 {
6306         ++vcpu->stat.insn_emulation_fail;
6307         trace_kvm_emulate_insn_failed(vcpu);
6308
6309         if (emulation_type & EMULTYPE_VMWARE_GP) {
6310                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6311                 return 1;
6312         }
6313
6314         if (emulation_type & EMULTYPE_SKIP) {
6315                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6316                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6317                 vcpu->run->internal.ndata = 0;
6318                 return 0;
6319         }
6320
6321         kvm_queue_exception(vcpu, UD_VECTOR);
6322
6323         if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6324                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6325                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6326                 vcpu->run->internal.ndata = 0;
6327                 return 0;
6328         }
6329
6330         return 1;
6331 }
6332
6333 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
6334                                   bool write_fault_to_shadow_pgtable,
6335                                   int emulation_type)
6336 {
6337         gpa_t gpa = cr2;
6338         kvm_pfn_t pfn;
6339
6340         if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6341                 return false;
6342
6343         if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6344                 return false;
6345
6346         if (!vcpu->arch.mmu->direct_map) {
6347                 /*
6348                  * Write permission should be allowed since only
6349                  * write access need to be emulated.
6350                  */
6351                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6352
6353                 /*
6354                  * If the mapping is invalid in guest, let cpu retry
6355                  * it to generate fault.
6356                  */
6357                 if (gpa == UNMAPPED_GVA)
6358                         return true;
6359         }
6360
6361         /*
6362          * Do not retry the unhandleable instruction if it faults on the
6363          * readonly host memory, otherwise it will goto a infinite loop:
6364          * retry instruction -> write #PF -> emulation fail -> retry
6365          * instruction -> ...
6366          */
6367         pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6368
6369         /*
6370          * If the instruction failed on the error pfn, it can not be fixed,
6371          * report the error to userspace.
6372          */
6373         if (is_error_noslot_pfn(pfn))
6374                 return false;
6375
6376         kvm_release_pfn_clean(pfn);
6377
6378         /* The instructions are well-emulated on direct mmu. */
6379         if (vcpu->arch.mmu->direct_map) {
6380                 unsigned int indirect_shadow_pages;
6381
6382                 spin_lock(&vcpu->kvm->mmu_lock);
6383                 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6384                 spin_unlock(&vcpu->kvm->mmu_lock);
6385
6386                 if (indirect_shadow_pages)
6387                         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6388
6389                 return true;
6390         }
6391
6392         /*
6393          * if emulation was due to access to shadowed page table
6394          * and it failed try to unshadow page and re-enter the
6395          * guest to let CPU execute the instruction.
6396          */
6397         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6398
6399         /*
6400          * If the access faults on its page table, it can not
6401          * be fixed by unprotecting shadow page and it should
6402          * be reported to userspace.
6403          */
6404         return !write_fault_to_shadow_pgtable;
6405 }
6406
6407 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6408                               unsigned long cr2,  int emulation_type)
6409 {
6410         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6411         unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6412
6413         last_retry_eip = vcpu->arch.last_retry_eip;
6414         last_retry_addr = vcpu->arch.last_retry_addr;
6415
6416         /*
6417          * If the emulation is caused by #PF and it is non-page_table
6418          * writing instruction, it means the VM-EXIT is caused by shadow
6419          * page protected, we can zap the shadow page and retry this
6420          * instruction directly.
6421          *
6422          * Note: if the guest uses a non-page-table modifying instruction
6423          * on the PDE that points to the instruction, then we will unmap
6424          * the instruction and go to an infinite loop. So, we cache the
6425          * last retried eip and the last fault address, if we meet the eip
6426          * and the address again, we can break out of the potential infinite
6427          * loop.
6428          */
6429         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6430
6431         if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6432                 return false;
6433
6434         if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6435                 return false;
6436
6437         if (x86_page_table_writing_insn(ctxt))
6438                 return false;
6439
6440         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6441                 return false;
6442
6443         vcpu->arch.last_retry_eip = ctxt->eip;
6444         vcpu->arch.last_retry_addr = cr2;
6445
6446         if (!vcpu->arch.mmu->direct_map)
6447                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6448
6449         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6450
6451         return true;
6452 }
6453
6454 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6455 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6456
6457 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6458 {
6459         if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6460                 /* This is a good place to trace that we are exiting SMM.  */
6461                 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6462
6463                 /* Process a latched INIT or SMI, if any.  */
6464                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6465         }
6466
6467         kvm_mmu_reset_context(vcpu);
6468 }
6469
6470 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6471                                 unsigned long *db)
6472 {
6473         u32 dr6 = 0;
6474         int i;
6475         u32 enable, rwlen;
6476
6477         enable = dr7;
6478         rwlen = dr7 >> 16;
6479         for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6480                 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6481                         dr6 |= (1 << i);
6482         return dr6;
6483 }
6484
6485 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6486 {
6487         struct kvm_run *kvm_run = vcpu->run;
6488
6489         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6490                 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6491                 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6492                 kvm_run->debug.arch.exception = DB_VECTOR;
6493                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6494                 return 0;
6495         }
6496         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6497         return 1;
6498 }
6499
6500 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6501 {
6502         unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6503         int r;
6504
6505         r = kvm_x86_ops->skip_emulated_instruction(vcpu);
6506         if (unlikely(!r))
6507                 return 0;
6508
6509         /*
6510          * rflags is the old, "raw" value of the flags.  The new value has
6511          * not been saved yet.
6512          *
6513          * This is correct even for TF set by the guest, because "the
6514          * processor will not generate this exception after the instruction
6515          * that sets the TF flag".
6516          */
6517         if (unlikely(rflags & X86_EFLAGS_TF))
6518                 r = kvm_vcpu_do_singlestep(vcpu);
6519         return r;
6520 }
6521 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6522
6523 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6524 {
6525         if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6526             (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6527                 struct kvm_run *kvm_run = vcpu->run;
6528                 unsigned long eip = kvm_get_linear_rip(vcpu);
6529                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6530                                            vcpu->arch.guest_debug_dr7,
6531                                            vcpu->arch.eff_db);
6532
6533                 if (dr6 != 0) {
6534                         kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6535                         kvm_run->debug.arch.pc = eip;
6536                         kvm_run->debug.arch.exception = DB_VECTOR;
6537                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
6538                         *r = 0;
6539                         return true;
6540                 }
6541         }
6542
6543         if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6544             !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6545                 unsigned long eip = kvm_get_linear_rip(vcpu);
6546                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6547                                            vcpu->arch.dr7,
6548                                            vcpu->arch.db);
6549
6550                 if (dr6 != 0) {
6551                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6552                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
6553                         kvm_queue_exception(vcpu, DB_VECTOR);
6554                         *r = 1;
6555                         return true;
6556                 }
6557         }
6558
6559         return false;
6560 }
6561
6562 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6563 {
6564         switch (ctxt->opcode_len) {
6565         case 1:
6566                 switch (ctxt->b) {
6567                 case 0xe4:      /* IN */
6568                 case 0xe5:
6569                 case 0xec:
6570                 case 0xed:
6571                 case 0xe6:      /* OUT */
6572                 case 0xe7:
6573                 case 0xee:
6574                 case 0xef:
6575                 case 0x6c:      /* INS */
6576                 case 0x6d:
6577                 case 0x6e:      /* OUTS */
6578                 case 0x6f:
6579                         return true;
6580                 }
6581                 break;
6582         case 2:
6583                 switch (ctxt->b) {
6584                 case 0x33:      /* RDPMC */
6585                         return true;
6586                 }
6587                 break;
6588         }
6589
6590         return false;
6591 }
6592
6593 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6594                             unsigned long cr2,
6595                             int emulation_type,
6596                             void *insn,
6597                             int insn_len)
6598 {
6599         int r;
6600         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6601         bool writeback = true;
6602         bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6603
6604         vcpu->arch.l1tf_flush_l1d = true;
6605
6606         /*
6607          * Clear write_fault_to_shadow_pgtable here to ensure it is
6608          * never reused.
6609          */
6610         vcpu->arch.write_fault_to_shadow_pgtable = false;
6611         kvm_clear_exception_queue(vcpu);
6612
6613         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6614                 init_emulate_ctxt(vcpu);
6615
6616                 /*
6617                  * We will reenter on the same instruction since
6618                  * we do not set complete_userspace_io.  This does not
6619                  * handle watchpoints yet, those would be handled in
6620                  * the emulate_ops.
6621                  */
6622                 if (!(emulation_type & EMULTYPE_SKIP) &&
6623                     kvm_vcpu_check_breakpoint(vcpu, &r))
6624                         return r;
6625
6626                 ctxt->interruptibility = 0;
6627                 ctxt->have_exception = false;
6628                 ctxt->exception.vector = -1;
6629                 ctxt->perm_ok = false;
6630
6631                 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6632
6633                 r = x86_decode_insn(ctxt, insn, insn_len);
6634
6635                 trace_kvm_emulate_insn_start(vcpu);
6636                 ++vcpu->stat.insn_emulation;
6637                 if (r != EMULATION_OK)  {
6638                         if ((emulation_type & EMULTYPE_TRAP_UD) ||
6639                             (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6640                                 kvm_queue_exception(vcpu, UD_VECTOR);
6641                                 return 1;
6642                         }
6643                         if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6644                                                 emulation_type))
6645                                 return 1;
6646                         if (ctxt->have_exception) {
6647                                 /*
6648                                  * #UD should result in just EMULATION_FAILED, and trap-like
6649                                  * exception should not be encountered during decode.
6650                                  */
6651                                 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6652                                              exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6653                                 inject_emulated_exception(vcpu);
6654                                 return 1;
6655                         }
6656                         return handle_emulation_failure(vcpu, emulation_type);
6657                 }
6658         }
6659
6660         if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6661             !is_vmware_backdoor_opcode(ctxt)) {
6662                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6663                 return 1;
6664         }
6665
6666         /*
6667          * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6668          * for kvm_skip_emulated_instruction().  The caller is responsible for
6669          * updating interruptibility state and injecting single-step #DBs.
6670          */
6671         if (emulation_type & EMULTYPE_SKIP) {
6672                 kvm_rip_write(vcpu, ctxt->_eip);
6673                 if (ctxt->eflags & X86_EFLAGS_RF)
6674                         kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6675                 return 1;
6676         }
6677
6678         if (retry_instruction(ctxt, cr2, emulation_type))
6679                 return 1;
6680
6681         /* this is needed for vmware backdoor interface to work since it
6682            changes registers values  during IO operation */
6683         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6684                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6685                 emulator_invalidate_register_cache(ctxt);
6686         }
6687
6688 restart:
6689         /* Save the faulting GPA (cr2) in the address field */
6690         ctxt->exception.address = cr2;
6691
6692         r = x86_emulate_insn(ctxt);
6693
6694         if (r == EMULATION_INTERCEPTED)
6695                 return 1;
6696
6697         if (r == EMULATION_FAILED) {
6698                 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6699                                         emulation_type))
6700                         return 1;
6701
6702                 return handle_emulation_failure(vcpu, emulation_type);
6703         }
6704
6705         if (ctxt->have_exception) {
6706                 r = 1;
6707                 if (inject_emulated_exception(vcpu))
6708                         return r;
6709         } else if (vcpu->arch.pio.count) {
6710                 if (!vcpu->arch.pio.in) {
6711                         /* FIXME: return into emulator if single-stepping.  */
6712                         vcpu->arch.pio.count = 0;
6713                 } else {
6714                         writeback = false;
6715                         vcpu->arch.complete_userspace_io = complete_emulated_pio;
6716                 }
6717                 r = 0;
6718         } else if (vcpu->mmio_needed) {
6719                 ++vcpu->stat.mmio_exits;
6720
6721                 if (!vcpu->mmio_is_write)
6722                         writeback = false;
6723                 r = 0;
6724                 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6725         } else if (r == EMULATION_RESTART)
6726                 goto restart;
6727         else
6728                 r = 1;
6729
6730         if (writeback) {
6731                 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6732                 toggle_interruptibility(vcpu, ctxt->interruptibility);
6733                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6734                 if (!ctxt->have_exception ||
6735                     exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6736                         kvm_rip_write(vcpu, ctxt->eip);
6737                         if (r && ctxt->tf)
6738                                 r = kvm_vcpu_do_singlestep(vcpu);
6739                         __kvm_set_rflags(vcpu, ctxt->eflags);
6740                 }
6741
6742                 /*
6743                  * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6744                  * do nothing, and it will be requested again as soon as
6745                  * the shadow expires.  But we still need to check here,
6746                  * because POPF has no interrupt shadow.
6747                  */
6748                 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6749                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6750         } else
6751                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6752
6753         return r;
6754 }
6755
6756 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6757 {
6758         return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6759 }
6760 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6761
6762 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6763                                         void *insn, int insn_len)
6764 {
6765         return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6766 }
6767 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6768
6769 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6770 {
6771         vcpu->arch.pio.count = 0;
6772         return 1;
6773 }
6774
6775 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6776 {
6777         vcpu->arch.pio.count = 0;
6778
6779         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6780                 return 1;
6781
6782         return kvm_skip_emulated_instruction(vcpu);
6783 }
6784
6785 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6786                             unsigned short port)
6787 {
6788         unsigned long val = kvm_rax_read(vcpu);
6789         int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6790                                             size, port, &val, 1);
6791         if (ret)
6792                 return ret;
6793
6794         /*
6795          * Workaround userspace that relies on old KVM behavior of %rip being
6796          * incremented prior to exiting to userspace to handle "OUT 0x7e".
6797          */
6798         if (port == 0x7e &&
6799             kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6800                 vcpu->arch.complete_userspace_io =
6801                         complete_fast_pio_out_port_0x7e;
6802                 kvm_skip_emulated_instruction(vcpu);
6803         } else {
6804                 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6805                 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6806         }
6807         return 0;
6808 }
6809
6810 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6811 {
6812         unsigned long val;
6813
6814         /* We should only ever be called with arch.pio.count equal to 1 */
6815         BUG_ON(vcpu->arch.pio.count != 1);
6816
6817         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6818                 vcpu->arch.pio.count = 0;
6819                 return 1;
6820         }
6821
6822         /* For size less than 4 we merge, else we zero extend */
6823         val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6824
6825         /*
6826          * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6827          * the copy and tracing
6828          */
6829         emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6830                                  vcpu->arch.pio.port, &val, 1);
6831         kvm_rax_write(vcpu, val);
6832
6833         return kvm_skip_emulated_instruction(vcpu);
6834 }
6835
6836 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6837                            unsigned short port)
6838 {
6839         unsigned long val;
6840         int ret;
6841
6842         /* For size less than 4 we merge, else we zero extend */
6843         val = (size < 4) ? kvm_rax_read(vcpu) : 0;
6844
6845         ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6846                                        &val, 1);
6847         if (ret) {
6848                 kvm_rax_write(vcpu, val);
6849                 return ret;
6850         }
6851
6852         vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6853         vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6854
6855         return 0;
6856 }
6857
6858 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6859 {
6860         int ret;
6861
6862         if (in)
6863                 ret = kvm_fast_pio_in(vcpu, size, port);
6864         else
6865                 ret = kvm_fast_pio_out(vcpu, size, port);
6866         return ret && kvm_skip_emulated_instruction(vcpu);
6867 }
6868 EXPORT_SYMBOL_GPL(kvm_fast_pio);
6869
6870 static int kvmclock_cpu_down_prep(unsigned int cpu)
6871 {
6872         __this_cpu_write(cpu_tsc_khz, 0);
6873         return 0;
6874 }
6875
6876 static void tsc_khz_changed(void *data)
6877 {
6878         struct cpufreq_freqs *freq = data;
6879         unsigned long khz = 0;
6880
6881         if (data)
6882                 khz = freq->new;
6883         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6884                 khz = cpufreq_quick_get(raw_smp_processor_id());
6885         if (!khz)
6886                 khz = tsc_khz;
6887         __this_cpu_write(cpu_tsc_khz, khz);
6888 }
6889
6890 #ifdef CONFIG_X86_64
6891 static void kvm_hyperv_tsc_notifier(void)
6892 {
6893         struct kvm *kvm;
6894         struct kvm_vcpu *vcpu;
6895         int cpu;
6896
6897         mutex_lock(&kvm_lock);
6898         list_for_each_entry(kvm, &vm_list, vm_list)
6899                 kvm_make_mclock_inprogress_request(kvm);
6900
6901         hyperv_stop_tsc_emulation();
6902
6903         /* TSC frequency always matches when on Hyper-V */
6904         for_each_present_cpu(cpu)
6905                 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6906         kvm_max_guest_tsc_khz = tsc_khz;
6907
6908         list_for_each_entry(kvm, &vm_list, vm_list) {
6909                 struct kvm_arch *ka = &kvm->arch;
6910
6911                 spin_lock(&ka->pvclock_gtod_sync_lock);
6912
6913                 pvclock_update_vm_gtod_copy(kvm);
6914
6915                 kvm_for_each_vcpu(cpu, vcpu, kvm)
6916                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6917
6918                 kvm_for_each_vcpu(cpu, vcpu, kvm)
6919                         kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6920
6921                 spin_unlock(&ka->pvclock_gtod_sync_lock);
6922         }
6923         mutex_unlock(&kvm_lock);
6924 }
6925 #endif
6926
6927 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
6928 {
6929         struct kvm *kvm;
6930         struct kvm_vcpu *vcpu;
6931         int i, send_ipi = 0;
6932
6933         /*
6934          * We allow guests to temporarily run on slowing clocks,
6935          * provided we notify them after, or to run on accelerating
6936          * clocks, provided we notify them before.  Thus time never
6937          * goes backwards.
6938          *
6939          * However, we have a problem.  We can't atomically update
6940          * the frequency of a given CPU from this function; it is
6941          * merely a notifier, which can be called from any CPU.
6942          * Changing the TSC frequency at arbitrary points in time
6943          * requires a recomputation of local variables related to
6944          * the TSC for each VCPU.  We must flag these local variables
6945          * to be updated and be sure the update takes place with the
6946          * new frequency before any guests proceed.
6947          *
6948          * Unfortunately, the combination of hotplug CPU and frequency
6949          * change creates an intractable locking scenario; the order
6950          * of when these callouts happen is undefined with respect to
6951          * CPU hotplug, and they can race with each other.  As such,
6952          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6953          * undefined; you can actually have a CPU frequency change take
6954          * place in between the computation of X and the setting of the
6955          * variable.  To protect against this problem, all updates of
6956          * the per_cpu tsc_khz variable are done in an interrupt
6957          * protected IPI, and all callers wishing to update the value
6958          * must wait for a synchronous IPI to complete (which is trivial
6959          * if the caller is on the CPU already).  This establishes the
6960          * necessary total order on variable updates.
6961          *
6962          * Note that because a guest time update may take place
6963          * anytime after the setting of the VCPU's request bit, the
6964          * correct TSC value must be set before the request.  However,
6965          * to ensure the update actually makes it to any guest which
6966          * starts running in hardware virtualization between the set
6967          * and the acquisition of the spinlock, we must also ping the
6968          * CPU after setting the request bit.
6969          *
6970          */
6971
6972         smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6973
6974         mutex_lock(&kvm_lock);
6975         list_for_each_entry(kvm, &vm_list, vm_list) {
6976                 kvm_for_each_vcpu(i, vcpu, kvm) {
6977                         if (vcpu->cpu != cpu)
6978                                 continue;
6979                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6980                         if (vcpu->cpu != raw_smp_processor_id())
6981                                 send_ipi = 1;
6982                 }
6983         }
6984         mutex_unlock(&kvm_lock);
6985
6986         if (freq->old < freq->new && send_ipi) {
6987                 /*
6988                  * We upscale the frequency.  Must make the guest
6989                  * doesn't see old kvmclock values while running with
6990                  * the new frequency, otherwise we risk the guest sees
6991                  * time go backwards.
6992                  *
6993                  * In case we update the frequency for another cpu
6994                  * (which might be in guest context) send an interrupt
6995                  * to kick the cpu out of guest context.  Next time
6996                  * guest context is entered kvmclock will be updated,
6997                  * so the guest will not see stale values.
6998                  */
6999                 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7000         }
7001 }
7002
7003 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7004                                      void *data)
7005 {
7006         struct cpufreq_freqs *freq = data;
7007         int cpu;
7008
7009         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7010                 return 0;
7011         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7012                 return 0;
7013
7014         for_each_cpu(cpu, freq->policy->cpus)
7015                 __kvmclock_cpufreq_notifier(freq, cpu);
7016
7017         return 0;
7018 }
7019
7020 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7021         .notifier_call  = kvmclock_cpufreq_notifier
7022 };
7023
7024 static int kvmclock_cpu_online(unsigned int cpu)
7025 {
7026         tsc_khz_changed(NULL);
7027         return 0;
7028 }
7029
7030 static void kvm_timer_init(void)
7031 {
7032         max_tsc_khz = tsc_khz;
7033
7034         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7035 #ifdef CONFIG_CPU_FREQ
7036                 struct cpufreq_policy policy;
7037                 int cpu;
7038
7039                 memset(&policy, 0, sizeof(policy));
7040                 cpu = get_cpu();
7041                 cpufreq_get_policy(&policy, cpu);
7042                 if (policy.cpuinfo.max_freq)
7043                         max_tsc_khz = policy.cpuinfo.max_freq;
7044                 put_cpu();
7045 #endif
7046                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7047                                           CPUFREQ_TRANSITION_NOTIFIER);
7048         }
7049
7050         cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7051                           kvmclock_cpu_online, kvmclock_cpu_down_prep);
7052 }
7053
7054 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7055 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7056
7057 int kvm_is_in_guest(void)
7058 {
7059         return __this_cpu_read(current_vcpu) != NULL;
7060 }
7061
7062 static int kvm_is_user_mode(void)
7063 {
7064         int user_mode = 3;
7065
7066         if (__this_cpu_read(current_vcpu))
7067                 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
7068
7069         return user_mode != 0;
7070 }
7071
7072 static unsigned long kvm_get_guest_ip(void)
7073 {
7074         unsigned long ip = 0;
7075
7076         if (__this_cpu_read(current_vcpu))
7077                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7078
7079         return ip;
7080 }
7081
7082 static void kvm_handle_intel_pt_intr(void)
7083 {
7084         struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7085
7086         kvm_make_request(KVM_REQ_PMI, vcpu);
7087         __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7088                         (unsigned long *)&vcpu->arch.pmu.global_status);
7089 }
7090
7091 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7092         .is_in_guest            = kvm_is_in_guest,
7093         .is_user_mode           = kvm_is_user_mode,
7094         .get_guest_ip           = kvm_get_guest_ip,
7095         .handle_intel_pt_intr   = kvm_handle_intel_pt_intr,
7096 };
7097
7098 #ifdef CONFIG_X86_64
7099 static void pvclock_gtod_update_fn(struct work_struct *work)
7100 {
7101         struct kvm *kvm;
7102
7103         struct kvm_vcpu *vcpu;
7104         int i;
7105
7106         mutex_lock(&kvm_lock);
7107         list_for_each_entry(kvm, &vm_list, vm_list)
7108                 kvm_for_each_vcpu(i, vcpu, kvm)
7109                         kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7110         atomic_set(&kvm_guest_has_master_clock, 0);
7111         mutex_unlock(&kvm_lock);
7112 }
7113
7114 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7115
7116 /*
7117  * Notification about pvclock gtod data update.
7118  */
7119 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7120                                void *priv)
7121 {
7122         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7123         struct timekeeper *tk = priv;
7124
7125         update_pvclock_gtod(tk);
7126
7127         /* disable master clock if host does not trust, or does not
7128          * use, TSC based clocksource.
7129          */
7130         if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7131             atomic_read(&kvm_guest_has_master_clock) != 0)
7132                 queue_work(system_long_wq, &pvclock_gtod_work);
7133
7134         return 0;
7135 }
7136
7137 static struct notifier_block pvclock_gtod_notifier = {
7138         .notifier_call = pvclock_gtod_notify,
7139 };
7140 #endif
7141
7142 int kvm_arch_init(void *opaque)
7143 {
7144         int r;
7145         struct kvm_x86_ops *ops = opaque;
7146
7147         if (kvm_x86_ops) {
7148                 printk(KERN_ERR "kvm: already loaded the other module\n");
7149                 r = -EEXIST;
7150                 goto out;
7151         }
7152
7153         if (!ops->cpu_has_kvm_support()) {
7154                 printk(KERN_ERR "kvm: no hardware support\n");
7155                 r = -EOPNOTSUPP;
7156                 goto out;
7157         }
7158         if (ops->disabled_by_bios()) {
7159                 printk(KERN_ERR "kvm: disabled by bios\n");
7160                 r = -EOPNOTSUPP;
7161                 goto out;
7162         }
7163
7164         /*
7165          * KVM explicitly assumes that the guest has an FPU and
7166          * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7167          * vCPU's FPU state as a fxregs_state struct.
7168          */
7169         if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7170                 printk(KERN_ERR "kvm: inadequate fpu\n");
7171                 r = -EOPNOTSUPP;
7172                 goto out;
7173         }
7174
7175         r = -ENOMEM;
7176         x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7177                                           __alignof__(struct fpu), SLAB_ACCOUNT,
7178                                           NULL);
7179         if (!x86_fpu_cache) {
7180                 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7181                 goto out;
7182         }
7183
7184         shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7185         if (!shared_msrs) {
7186                 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7187                 goto out_free_x86_fpu_cache;
7188         }
7189
7190         r = kvm_mmu_module_init();
7191         if (r)
7192                 goto out_free_percpu;
7193
7194         kvm_x86_ops = ops;
7195
7196         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7197                         PT_DIRTY_MASK, PT64_NX_MASK, 0,
7198                         PT_PRESENT_MASK, 0, sme_me_mask);
7199         kvm_timer_init();
7200
7201         perf_register_guest_info_callbacks(&kvm_guest_cbs);
7202
7203         if (boot_cpu_has(X86_FEATURE_XSAVE))
7204                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7205
7206         kvm_lapic_init();
7207         if (pi_inject_timer == -1)
7208                 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7209 #ifdef CONFIG_X86_64
7210         pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7211
7212         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7213                 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7214 #endif
7215
7216         return 0;
7217
7218 out_free_percpu:
7219         free_percpu(shared_msrs);
7220 out_free_x86_fpu_cache:
7221         kmem_cache_destroy(x86_fpu_cache);
7222 out:
7223         return r;
7224 }
7225
7226 void kvm_arch_exit(void)
7227 {
7228 #ifdef CONFIG_X86_64
7229         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7230                 clear_hv_tscchange_cb();
7231 #endif
7232         kvm_lapic_exit();
7233         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7234
7235         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7236                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7237                                             CPUFREQ_TRANSITION_NOTIFIER);
7238         cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7239 #ifdef CONFIG_X86_64
7240         pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7241 #endif
7242         kvm_x86_ops = NULL;
7243         kvm_mmu_module_exit();
7244         free_percpu(shared_msrs);
7245         kmem_cache_destroy(x86_fpu_cache);
7246 }
7247
7248 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7249 {
7250         ++vcpu->stat.halt_exits;
7251         if (lapic_in_kernel(vcpu)) {
7252                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7253                 return 1;
7254         } else {
7255                 vcpu->run->exit_reason = KVM_EXIT_HLT;
7256                 return 0;
7257         }
7258 }
7259 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7260
7261 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7262 {
7263         int ret = kvm_skip_emulated_instruction(vcpu);
7264         /*
7265          * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7266          * KVM_EXIT_DEBUG here.
7267          */
7268         return kvm_vcpu_halt(vcpu) && ret;
7269 }
7270 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7271
7272 #ifdef CONFIG_X86_64
7273 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7274                                 unsigned long clock_type)
7275 {
7276         struct kvm_clock_pairing clock_pairing;
7277         struct timespec64 ts;
7278         u64 cycle;
7279         int ret;
7280
7281         if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7282                 return -KVM_EOPNOTSUPP;
7283
7284         if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7285                 return -KVM_EOPNOTSUPP;
7286
7287         clock_pairing.sec = ts.tv_sec;
7288         clock_pairing.nsec = ts.tv_nsec;
7289         clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7290         clock_pairing.flags = 0;
7291         memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7292
7293         ret = 0;
7294         if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7295                             sizeof(struct kvm_clock_pairing)))
7296                 ret = -KVM_EFAULT;
7297
7298         return ret;
7299 }
7300 #endif
7301
7302 /*
7303  * kvm_pv_kick_cpu_op:  Kick a vcpu.
7304  *
7305  * @apicid - apicid of vcpu to be kicked.
7306  */
7307 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7308 {
7309         struct kvm_lapic_irq lapic_irq;
7310
7311         lapic_irq.shorthand = 0;
7312         lapic_irq.dest_mode = 0;
7313         lapic_irq.level = 0;
7314         lapic_irq.dest_id = apicid;
7315         lapic_irq.msi_redir_hint = false;
7316
7317         lapic_irq.delivery_mode = APIC_DM_REMRD;
7318         kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7319 }
7320
7321 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7322 {
7323         if (!lapic_in_kernel(vcpu)) {
7324                 WARN_ON_ONCE(vcpu->arch.apicv_active);
7325                 return;
7326         }
7327         if (!vcpu->arch.apicv_active)
7328                 return;
7329
7330         vcpu->arch.apicv_active = false;
7331         kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7332 }
7333
7334 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7335 {
7336         struct kvm_vcpu *target = NULL;
7337         struct kvm_apic_map *map;
7338
7339         rcu_read_lock();
7340         map = rcu_dereference(kvm->arch.apic_map);
7341
7342         if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7343                 target = map->phys_map[dest_id]->vcpu;
7344
7345         rcu_read_unlock();
7346
7347         if (target && READ_ONCE(target->ready))
7348                 kvm_vcpu_yield_to(target);
7349 }
7350
7351 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7352 {
7353         unsigned long nr, a0, a1, a2, a3, ret;
7354         int op_64_bit;
7355
7356         if (kvm_hv_hypercall_enabled(vcpu->kvm))
7357                 return kvm_hv_hypercall(vcpu);
7358
7359         nr = kvm_rax_read(vcpu);
7360         a0 = kvm_rbx_read(vcpu);
7361         a1 = kvm_rcx_read(vcpu);
7362         a2 = kvm_rdx_read(vcpu);
7363         a3 = kvm_rsi_read(vcpu);
7364
7365         trace_kvm_hypercall(nr, a0, a1, a2, a3);
7366
7367         op_64_bit = is_64_bit_mode(vcpu);
7368         if (!op_64_bit) {
7369                 nr &= 0xFFFFFFFF;
7370                 a0 &= 0xFFFFFFFF;
7371                 a1 &= 0xFFFFFFFF;
7372                 a2 &= 0xFFFFFFFF;
7373                 a3 &= 0xFFFFFFFF;
7374         }
7375
7376         if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7377                 ret = -KVM_EPERM;
7378                 goto out;
7379         }
7380
7381         switch (nr) {
7382         case KVM_HC_VAPIC_POLL_IRQ:
7383                 ret = 0;
7384                 break;
7385         case KVM_HC_KICK_CPU:
7386                 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7387                 kvm_sched_yield(vcpu->kvm, a1);
7388                 ret = 0;
7389                 break;
7390 #ifdef CONFIG_X86_64
7391         case KVM_HC_CLOCK_PAIRING:
7392                 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7393                 break;
7394 #endif
7395         case KVM_HC_SEND_IPI:
7396                 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7397                 break;
7398         case KVM_HC_SCHED_YIELD:
7399                 kvm_sched_yield(vcpu->kvm, a0);
7400                 ret = 0;
7401                 break;
7402         default:
7403                 ret = -KVM_ENOSYS;
7404                 break;
7405         }
7406 out:
7407         if (!op_64_bit)
7408                 ret = (u32)ret;
7409         kvm_rax_write(vcpu, ret);
7410
7411         ++vcpu->stat.hypercalls;
7412         return kvm_skip_emulated_instruction(vcpu);
7413 }
7414 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7415
7416 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7417 {
7418         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7419         char instruction[3];
7420         unsigned long rip = kvm_rip_read(vcpu);
7421
7422         kvm_x86_ops->patch_hypercall(vcpu, instruction);
7423
7424         return emulator_write_emulated(ctxt, rip, instruction, 3,
7425                 &ctxt->exception);
7426 }
7427
7428 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7429 {
7430         return vcpu->run->request_interrupt_window &&
7431                 likely(!pic_in_kernel(vcpu->kvm));
7432 }
7433
7434 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7435 {
7436         struct kvm_run *kvm_run = vcpu->run;
7437
7438         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7439         kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7440         kvm_run->cr8 = kvm_get_cr8(vcpu);
7441         kvm_run->apic_base = kvm_get_apic_base(vcpu);
7442         kvm_run->ready_for_interrupt_injection =
7443                 pic_in_kernel(vcpu->kvm) ||
7444                 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7445 }
7446
7447 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7448 {
7449         int max_irr, tpr;
7450
7451         if (!kvm_x86_ops->update_cr8_intercept)
7452                 return;
7453
7454         if (!lapic_in_kernel(vcpu))
7455                 return;
7456
7457         if (vcpu->arch.apicv_active)
7458                 return;
7459
7460         if (!vcpu->arch.apic->vapic_addr)
7461                 max_irr = kvm_lapic_find_highest_irr(vcpu);
7462         else
7463                 max_irr = -1;
7464
7465         if (max_irr != -1)
7466                 max_irr >>= 4;
7467
7468         tpr = kvm_lapic_get_cr8(vcpu);
7469
7470         kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7471 }
7472
7473 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7474 {
7475         int r;
7476
7477         /* try to reinject previous events if any */
7478
7479         if (vcpu->arch.exception.injected)
7480                 kvm_x86_ops->queue_exception(vcpu);
7481         /*
7482          * Do not inject an NMI or interrupt if there is a pending
7483          * exception.  Exceptions and interrupts are recognized at
7484          * instruction boundaries, i.e. the start of an instruction.
7485          * Trap-like exceptions, e.g. #DB, have higher priority than
7486          * NMIs and interrupts, i.e. traps are recognized before an
7487          * NMI/interrupt that's pending on the same instruction.
7488          * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7489          * priority, but are only generated (pended) during instruction
7490          * execution, i.e. a pending fault-like exception means the
7491          * fault occurred on the *previous* instruction and must be
7492          * serviced prior to recognizing any new events in order to
7493          * fully complete the previous instruction.
7494          */
7495         else if (!vcpu->arch.exception.pending) {
7496                 if (vcpu->arch.nmi_injected)
7497                         kvm_x86_ops->set_nmi(vcpu);
7498                 else if (vcpu->arch.interrupt.injected)
7499                         kvm_x86_ops->set_irq(vcpu);
7500         }
7501
7502         /*
7503          * Call check_nested_events() even if we reinjected a previous event
7504          * in order for caller to determine if it should require immediate-exit
7505          * from L2 to L1 due to pending L1 events which require exit
7506          * from L2 to L1.
7507          */
7508         if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7509                 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7510                 if (r != 0)
7511                         return r;
7512         }
7513
7514         /* try to inject new event if pending */
7515         if (vcpu->arch.exception.pending) {
7516                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7517                                         vcpu->arch.exception.has_error_code,
7518                                         vcpu->arch.exception.error_code);
7519
7520                 WARN_ON_ONCE(vcpu->arch.exception.injected);
7521                 vcpu->arch.exception.pending = false;
7522                 vcpu->arch.exception.injected = true;
7523
7524                 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7525                         __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7526                                              X86_EFLAGS_RF);
7527
7528                 if (vcpu->arch.exception.nr == DB_VECTOR) {
7529                         /*
7530                          * This code assumes that nSVM doesn't use
7531                          * check_nested_events(). If it does, the
7532                          * DR6/DR7 changes should happen before L1
7533                          * gets a #VMEXIT for an intercepted #DB in
7534                          * L2.  (Under VMX, on the other hand, the
7535                          * DR6/DR7 changes should not happen in the
7536                          * event of a VM-exit to L1 for an intercepted
7537                          * #DB in L2.)
7538                          */
7539                         kvm_deliver_exception_payload(vcpu);
7540                         if (vcpu->arch.dr7 & DR7_GD) {
7541                                 vcpu->arch.dr7 &= ~DR7_GD;
7542                                 kvm_update_dr7(vcpu);
7543                         }
7544                 }
7545
7546                 kvm_x86_ops->queue_exception(vcpu);
7547         }
7548
7549         /* Don't consider new event if we re-injected an event */
7550         if (kvm_event_needs_reinjection(vcpu))
7551                 return 0;
7552
7553         if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7554             kvm_x86_ops->smi_allowed(vcpu)) {
7555                 vcpu->arch.smi_pending = false;
7556                 ++vcpu->arch.smi_count;
7557                 enter_smm(vcpu);
7558         } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7559                 --vcpu->arch.nmi_pending;
7560                 vcpu->arch.nmi_injected = true;
7561                 kvm_x86_ops->set_nmi(vcpu);
7562         } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7563                 /*
7564                  * Because interrupts can be injected asynchronously, we are
7565                  * calling check_nested_events again here to avoid a race condition.
7566                  * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7567                  * proposal and current concerns.  Perhaps we should be setting
7568                  * KVM_REQ_EVENT only on certain events and not unconditionally?
7569                  */
7570                 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7571                         r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7572                         if (r != 0)
7573                                 return r;
7574                 }
7575                 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7576                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7577                                             false);
7578                         kvm_x86_ops->set_irq(vcpu);
7579                 }
7580         }
7581
7582         return 0;
7583 }
7584
7585 static void process_nmi(struct kvm_vcpu *vcpu)
7586 {
7587         unsigned limit = 2;
7588
7589         /*
7590          * x86 is limited to one NMI running, and one NMI pending after it.
7591          * If an NMI is already in progress, limit further NMIs to just one.
7592          * Otherwise, allow two (and we'll inject the first one immediately).
7593          */
7594         if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7595                 limit = 1;
7596
7597         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7598         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7599         kvm_make_request(KVM_REQ_EVENT, vcpu);
7600 }
7601
7602 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7603 {
7604         u32 flags = 0;
7605         flags |= seg->g       << 23;
7606         flags |= seg->db      << 22;
7607         flags |= seg->l       << 21;
7608         flags |= seg->avl     << 20;
7609         flags |= seg->present << 15;
7610         flags |= seg->dpl     << 13;
7611         flags |= seg->s       << 12;
7612         flags |= seg->type    << 8;
7613         return flags;
7614 }
7615
7616 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7617 {
7618         struct kvm_segment seg;
7619         int offset;
7620
7621         kvm_get_segment(vcpu, &seg, n);
7622         put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7623
7624         if (n < 3)
7625                 offset = 0x7f84 + n * 12;
7626         else
7627                 offset = 0x7f2c + (n - 3) * 12;
7628
7629         put_smstate(u32, buf, offset + 8, seg.base);
7630         put_smstate(u32, buf, offset + 4, seg.limit);
7631         put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7632 }
7633
7634 #ifdef CONFIG_X86_64
7635 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7636 {
7637         struct kvm_segment seg;
7638         int offset;
7639         u16 flags;
7640
7641         kvm_get_segment(vcpu, &seg, n);
7642         offset = 0x7e00 + n * 16;
7643
7644         flags = enter_smm_get_segment_flags(&seg) >> 8;
7645         put_smstate(u16, buf, offset, seg.selector);
7646         put_smstate(u16, buf, offset + 2, flags);
7647         put_smstate(u32, buf, offset + 4, seg.limit);
7648         put_smstate(u64, buf, offset + 8, seg.base);
7649 }
7650 #endif
7651
7652 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7653 {
7654         struct desc_ptr dt;
7655         struct kvm_segment seg;
7656         unsigned long val;
7657         int i;
7658
7659         put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7660         put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7661         put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7662         put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7663
7664         for (i = 0; i < 8; i++)
7665                 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7666
7667         kvm_get_dr(vcpu, 6, &val);
7668         put_smstate(u32, buf, 0x7fcc, (u32)val);
7669         kvm_get_dr(vcpu, 7, &val);
7670         put_smstate(u32, buf, 0x7fc8, (u32)val);
7671
7672         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7673         put_smstate(u32, buf, 0x7fc4, seg.selector);
7674         put_smstate(u32, buf, 0x7f64, seg.base);
7675         put_smstate(u32, buf, 0x7f60, seg.limit);
7676         put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7677
7678         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7679         put_smstate(u32, buf, 0x7fc0, seg.selector);
7680         put_smstate(u32, buf, 0x7f80, seg.base);
7681         put_smstate(u32, buf, 0x7f7c, seg.limit);
7682         put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7683
7684         kvm_x86_ops->get_gdt(vcpu, &dt);
7685         put_smstate(u32, buf, 0x7f74, dt.address);
7686         put_smstate(u32, buf, 0x7f70, dt.size);
7687
7688         kvm_x86_ops->get_idt(vcpu, &dt);
7689         put_smstate(u32, buf, 0x7f58, dt.address);
7690         put_smstate(u32, buf, 0x7f54, dt.size);
7691
7692         for (i = 0; i < 6; i++)
7693                 enter_smm_save_seg_32(vcpu, buf, i);
7694
7695         put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7696
7697         /* revision id */
7698         put_smstate(u32, buf, 0x7efc, 0x00020000);
7699         put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7700 }
7701
7702 #ifdef CONFIG_X86_64
7703 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7704 {
7705         struct desc_ptr dt;
7706         struct kvm_segment seg;
7707         unsigned long val;
7708         int i;
7709
7710         for (i = 0; i < 16; i++)
7711                 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7712
7713         put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7714         put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7715
7716         kvm_get_dr(vcpu, 6, &val);
7717         put_smstate(u64, buf, 0x7f68, val);
7718         kvm_get_dr(vcpu, 7, &val);
7719         put_smstate(u64, buf, 0x7f60, val);
7720
7721         put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7722         put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7723         put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7724
7725         put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7726
7727         /* revision id */
7728         put_smstate(u32, buf, 0x7efc, 0x00020064);
7729
7730         put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7731
7732         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7733         put_smstate(u16, buf, 0x7e90, seg.selector);
7734         put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7735         put_smstate(u32, buf, 0x7e94, seg.limit);
7736         put_smstate(u64, buf, 0x7e98, seg.base);
7737
7738         kvm_x86_ops->get_idt(vcpu, &dt);
7739         put_smstate(u32, buf, 0x7e84, dt.size);
7740         put_smstate(u64, buf, 0x7e88, dt.address);
7741
7742         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7743         put_smstate(u16, buf, 0x7e70, seg.selector);
7744         put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7745         put_smstate(u32, buf, 0x7e74, seg.limit);
7746         put_smstate(u64, buf, 0x7e78, seg.base);
7747
7748         kvm_x86_ops->get_gdt(vcpu, &dt);
7749         put_smstate(u32, buf, 0x7e64, dt.size);
7750         put_smstate(u64, buf, 0x7e68, dt.address);
7751
7752         for (i = 0; i < 6; i++)
7753                 enter_smm_save_seg_64(vcpu, buf, i);
7754 }
7755 #endif
7756
7757 static void enter_smm(struct kvm_vcpu *vcpu)
7758 {
7759         struct kvm_segment cs, ds;
7760         struct desc_ptr dt;
7761         char buf[512];
7762         u32 cr0;
7763
7764         trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7765         memset(buf, 0, 512);
7766 #ifdef CONFIG_X86_64
7767         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7768                 enter_smm_save_state_64(vcpu, buf);
7769         else
7770 #endif
7771                 enter_smm_save_state_32(vcpu, buf);
7772
7773         /*
7774          * Give pre_enter_smm() a chance to make ISA-specific changes to the
7775          * vCPU state (e.g. leave guest mode) after we've saved the state into
7776          * the SMM state-save area.
7777          */
7778         kvm_x86_ops->pre_enter_smm(vcpu, buf);
7779
7780         vcpu->arch.hflags |= HF_SMM_MASK;
7781         kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7782
7783         if (kvm_x86_ops->get_nmi_mask(vcpu))
7784                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7785         else
7786                 kvm_x86_ops->set_nmi_mask(vcpu, true);
7787
7788         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7789         kvm_rip_write(vcpu, 0x8000);
7790
7791         cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7792         kvm_x86_ops->set_cr0(vcpu, cr0);
7793         vcpu->arch.cr0 = cr0;
7794
7795         kvm_x86_ops->set_cr4(vcpu, 0);
7796
7797         /* Undocumented: IDT limit is set to zero on entry to SMM.  */
7798         dt.address = dt.size = 0;
7799         kvm_x86_ops->set_idt(vcpu, &dt);
7800
7801         __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7802
7803         cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7804         cs.base = vcpu->arch.smbase;
7805
7806         ds.selector = 0;
7807         ds.base = 0;
7808
7809         cs.limit    = ds.limit = 0xffffffff;
7810         cs.type     = ds.type = 0x3;
7811         cs.dpl      = ds.dpl = 0;
7812         cs.db       = ds.db = 0;
7813         cs.s        = ds.s = 1;
7814         cs.l        = ds.l = 0;
7815         cs.g        = ds.g = 1;
7816         cs.avl      = ds.avl = 0;
7817         cs.present  = ds.present = 1;
7818         cs.unusable = ds.unusable = 0;
7819         cs.padding  = ds.padding = 0;
7820
7821         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7822         kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7823         kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7824         kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7825         kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7826         kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7827
7828 #ifdef CONFIG_X86_64
7829         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7830                 kvm_x86_ops->set_efer(vcpu, 0);
7831 #endif
7832
7833         kvm_update_cpuid(vcpu);
7834         kvm_mmu_reset_context(vcpu);
7835 }
7836
7837 static void process_smi(struct kvm_vcpu *vcpu)
7838 {
7839         vcpu->arch.smi_pending = true;
7840         kvm_make_request(KVM_REQ_EVENT, vcpu);
7841 }
7842
7843 void kvm_make_scan_ioapic_request(struct kvm *kvm)
7844 {
7845         kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7846 }
7847
7848 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
7849 {
7850         if (!kvm_apic_present(vcpu))
7851                 return;
7852
7853         bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
7854
7855         if (irqchip_split(vcpu->kvm))
7856                 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
7857         else {
7858                 if (vcpu->arch.apicv_active)
7859                         kvm_x86_ops->sync_pir_to_irr(vcpu);
7860                 if (ioapic_in_kernel(vcpu->kvm))
7861                         kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
7862         }
7863
7864         if (is_guest_mode(vcpu))
7865                 vcpu->arch.load_eoi_exitmap_pending = true;
7866         else
7867                 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7868 }
7869
7870 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7871 {
7872         u64 eoi_exit_bitmap[4];
7873
7874         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7875                 return;
7876
7877         bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7878                   vcpu_to_synic(vcpu)->vec_bitmap, 256);
7879         kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
7880 }
7881
7882 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7883                 unsigned long start, unsigned long end,
7884                 bool blockable)
7885 {
7886         unsigned long apic_address;
7887
7888         /*
7889          * The physical address of apic access page is stored in the VMCS.
7890          * Update it when it becomes invalid.
7891          */
7892         apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7893         if (start <= apic_address && apic_address < end)
7894                 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7895
7896         return 0;
7897 }
7898
7899 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7900 {
7901         struct page *page = NULL;
7902
7903         if (!lapic_in_kernel(vcpu))
7904                 return;
7905
7906         if (!kvm_x86_ops->set_apic_access_page_addr)
7907                 return;
7908
7909         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7910         if (is_error_page(page))
7911                 return;
7912         kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7913
7914         /*
7915          * Do not pin apic access page in memory, the MMU notifier
7916          * will call us again if it is migrated or swapped out.
7917          */
7918         put_page(page);
7919 }
7920 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7921
7922 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7923 {
7924         smp_send_reschedule(vcpu->cpu);
7925 }
7926 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7927
7928 /*
7929  * Returns 1 to let vcpu_run() continue the guest execution loop without
7930  * exiting to the userspace.  Otherwise, the value will be returned to the
7931  * userspace.
7932  */
7933 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
7934 {
7935         int r;
7936         bool req_int_win =
7937                 dm_request_for_irq_injection(vcpu) &&
7938                 kvm_cpu_accept_dm_intr(vcpu);
7939
7940         bool req_immediate_exit = false;
7941
7942         if (kvm_request_pending(vcpu)) {
7943                 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7944                         kvm_x86_ops->get_vmcs12_pages(vcpu);
7945                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
7946                         kvm_mmu_unload(vcpu);
7947                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
7948                         __kvm_migrate_timers(vcpu);
7949                 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7950                         kvm_gen_update_masterclock(vcpu->kvm);
7951                 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7952                         kvm_gen_kvmclock_update(vcpu);
7953                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7954                         r = kvm_guest_time_update(vcpu);
7955                         if (unlikely(r))
7956                                 goto out;
7957                 }
7958                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
7959                         kvm_mmu_sync_roots(vcpu);
7960                 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7961                         kvm_mmu_load_cr3(vcpu);
7962                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
7963                         kvm_vcpu_flush_tlb(vcpu, true);
7964                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
7965                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
7966                         r = 0;
7967                         goto out;
7968                 }
7969                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
7970                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7971                         vcpu->mmio_needed = 0;
7972                         r = 0;
7973                         goto out;
7974                 }
7975                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7976                         /* Page is swapped out. Do synthetic halt */
7977                         vcpu->arch.apf.halted = true;
7978                         r = 1;
7979                         goto out;
7980                 }
7981                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7982                         record_steal_time(vcpu);
7983                 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7984                         process_smi(vcpu);
7985                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7986                         process_nmi(vcpu);
7987                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7988                         kvm_pmu_handle_event(vcpu);
7989                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7990                         kvm_pmu_deliver_pmi(vcpu);
7991                 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7992                         BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7993                         if (test_bit(vcpu->arch.pending_ioapic_eoi,
7994                                      vcpu->arch.ioapic_handled_vectors)) {
7995                                 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7996                                 vcpu->run->eoi.vector =
7997                                                 vcpu->arch.pending_ioapic_eoi;
7998                                 r = 0;
7999                                 goto out;
8000                         }
8001                 }
8002                 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8003                         vcpu_scan_ioapic(vcpu);
8004                 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8005                         vcpu_load_eoi_exitmap(vcpu);
8006                 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8007                         kvm_vcpu_reload_apic_access_page(vcpu);
8008                 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8009                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8010                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8011                         r = 0;
8012                         goto out;
8013                 }
8014                 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8015                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8016                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8017                         r = 0;
8018                         goto out;
8019                 }
8020                 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8021                         vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8022                         vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8023                         r = 0;
8024                         goto out;
8025                 }
8026
8027                 /*
8028                  * KVM_REQ_HV_STIMER has to be processed after
8029                  * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8030                  * depend on the guest clock being up-to-date
8031                  */
8032                 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8033                         kvm_hv_process_stimers(vcpu);
8034         }
8035
8036         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8037                 ++vcpu->stat.req_event;
8038                 kvm_apic_accept_events(vcpu);
8039                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8040                         r = 1;
8041                         goto out;
8042                 }
8043
8044                 if (inject_pending_event(vcpu, req_int_win) != 0)
8045                         req_immediate_exit = true;
8046                 else {
8047                         /* Enable SMI/NMI/IRQ window open exits if needed.
8048                          *
8049                          * SMIs have three cases:
8050                          * 1) They can be nested, and then there is nothing to
8051                          *    do here because RSM will cause a vmexit anyway.
8052                          * 2) There is an ISA-specific reason why SMI cannot be
8053                          *    injected, and the moment when this changes can be
8054                          *    intercepted.
8055                          * 3) Or the SMI can be pending because
8056                          *    inject_pending_event has completed the injection
8057                          *    of an IRQ or NMI from the previous vmexit, and
8058                          *    then we request an immediate exit to inject the
8059                          *    SMI.
8060                          */
8061                         if (vcpu->arch.smi_pending && !is_smm(vcpu))
8062                                 if (!kvm_x86_ops->enable_smi_window(vcpu))
8063                                         req_immediate_exit = true;
8064                         if (vcpu->arch.nmi_pending)
8065                                 kvm_x86_ops->enable_nmi_window(vcpu);
8066                         if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8067                                 kvm_x86_ops->enable_irq_window(vcpu);
8068                         WARN_ON(vcpu->arch.exception.pending);
8069                 }
8070
8071                 if (kvm_lapic_enabled(vcpu)) {
8072                         update_cr8_intercept(vcpu);
8073                         kvm_lapic_sync_to_vapic(vcpu);
8074                 }
8075         }
8076
8077         r = kvm_mmu_reload(vcpu);
8078         if (unlikely(r)) {
8079                 goto cancel_injection;
8080         }
8081
8082         preempt_disable();
8083
8084         kvm_x86_ops->prepare_guest_switch(vcpu);
8085
8086         /*
8087          * Disable IRQs before setting IN_GUEST_MODE.  Posted interrupt
8088          * IPI are then delayed after guest entry, which ensures that they
8089          * result in virtual interrupt delivery.
8090          */
8091         local_irq_disable();
8092         vcpu->mode = IN_GUEST_MODE;
8093
8094         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8095
8096         /*
8097          * 1) We should set ->mode before checking ->requests.  Please see
8098          * the comment in kvm_vcpu_exiting_guest_mode().
8099          *
8100          * 2) For APICv, we should set ->mode before checking PID.ON. This
8101          * pairs with the memory barrier implicit in pi_test_and_set_on
8102          * (see vmx_deliver_posted_interrupt).
8103          *
8104          * 3) This also orders the write to mode from any reads to the page
8105          * tables done while the VCPU is running.  Please see the comment
8106          * in kvm_flush_remote_tlbs.
8107          */
8108         smp_mb__after_srcu_read_unlock();
8109
8110         /*
8111          * This handles the case where a posted interrupt was
8112          * notified with kvm_vcpu_kick.
8113          */
8114         if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8115                 kvm_x86_ops->sync_pir_to_irr(vcpu);
8116
8117         if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
8118             || need_resched() || signal_pending(current)) {
8119                 vcpu->mode = OUTSIDE_GUEST_MODE;
8120                 smp_wmb();
8121                 local_irq_enable();
8122                 preempt_enable();
8123                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8124                 r = 1;
8125                 goto cancel_injection;
8126         }
8127
8128         if (req_immediate_exit) {
8129                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8130                 kvm_x86_ops->request_immediate_exit(vcpu);
8131         }
8132
8133         trace_kvm_entry(vcpu->vcpu_id);
8134         guest_enter_irqoff();
8135
8136         /* The preempt notifier should have taken care of the FPU already.  */
8137         WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD));
8138
8139         if (unlikely(vcpu->arch.switch_db_regs)) {
8140                 set_debugreg(0, 7);
8141                 set_debugreg(vcpu->arch.eff_db[0], 0);
8142                 set_debugreg(vcpu->arch.eff_db[1], 1);
8143                 set_debugreg(vcpu->arch.eff_db[2], 2);
8144                 set_debugreg(vcpu->arch.eff_db[3], 3);
8145                 set_debugreg(vcpu->arch.dr6, 6);
8146                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8147         }
8148
8149         kvm_x86_ops->run(vcpu);
8150
8151         /*
8152          * Do this here before restoring debug registers on the host.  And
8153          * since we do this before handling the vmexit, a DR access vmexit
8154          * can (a) read the correct value of the debug registers, (b) set
8155          * KVM_DEBUGREG_WONT_EXIT again.
8156          */
8157         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8158                 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8159                 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
8160                 kvm_update_dr0123(vcpu);
8161                 kvm_update_dr6(vcpu);
8162                 kvm_update_dr7(vcpu);
8163                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8164         }
8165
8166         /*
8167          * If the guest has used debug registers, at least dr7
8168          * will be disabled while returning to the host.
8169          * If we don't have active breakpoints in the host, we don't
8170          * care about the messed up debug address registers. But if
8171          * we have some of them active, restore the old state.
8172          */
8173         if (hw_breakpoint_active())
8174                 hw_breakpoint_restore();
8175
8176         vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8177
8178         vcpu->mode = OUTSIDE_GUEST_MODE;
8179         smp_wmb();
8180
8181         kvm_x86_ops->handle_exit_irqoff(vcpu);
8182
8183         /*
8184          * Consume any pending interrupts, including the possible source of
8185          * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8186          * An instruction is required after local_irq_enable() to fully unblock
8187          * interrupts on processors that implement an interrupt shadow, the
8188          * stat.exits increment will do nicely.
8189          */
8190         kvm_before_interrupt(vcpu);
8191         local_irq_enable();
8192         ++vcpu->stat.exits;
8193         local_irq_disable();
8194         kvm_after_interrupt(vcpu);
8195
8196         guest_exit_irqoff();
8197         if (lapic_in_kernel(vcpu)) {
8198                 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8199                 if (delta != S64_MIN) {
8200                         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8201                         vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8202                 }
8203         }
8204
8205         local_irq_enable();
8206         preempt_enable();
8207
8208         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8209
8210         /*
8211          * Profile KVM exit RIPs:
8212          */
8213         if (unlikely(prof_on == KVM_PROFILING)) {
8214                 unsigned long rip = kvm_rip_read(vcpu);
8215                 profile_hit(KVM_PROFILING, (void *)rip);
8216         }
8217
8218         if (unlikely(vcpu->arch.tsc_always_catchup))
8219                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8220
8221         if (vcpu->arch.apic_attention)
8222                 kvm_lapic_sync_from_vapic(vcpu);
8223
8224         vcpu->arch.gpa_available = false;
8225         r = kvm_x86_ops->handle_exit(vcpu);
8226         return r;
8227
8228 cancel_injection:
8229         kvm_x86_ops->cancel_injection(vcpu);
8230         if (unlikely(vcpu->arch.apic_attention))
8231                 kvm_lapic_sync_from_vapic(vcpu);
8232 out:
8233         return r;
8234 }
8235
8236 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8237 {
8238         if (!kvm_arch_vcpu_runnable(vcpu) &&
8239             (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
8240                 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8241                 kvm_vcpu_block(vcpu);
8242                 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8243
8244                 if (kvm_x86_ops->post_block)
8245                         kvm_x86_ops->post_block(vcpu);
8246
8247                 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8248                         return 1;
8249         }
8250
8251         kvm_apic_accept_events(vcpu);
8252         switch(vcpu->arch.mp_state) {
8253         case KVM_MP_STATE_HALTED:
8254                 vcpu->arch.pv.pv_unhalted = false;
8255                 vcpu->arch.mp_state =
8256                         KVM_MP_STATE_RUNNABLE;
8257                 /* fall through */
8258         case KVM_MP_STATE_RUNNABLE:
8259                 vcpu->arch.apf.halted = false;
8260                 break;
8261         case KVM_MP_STATE_INIT_RECEIVED:
8262                 break;
8263         default:
8264                 return -EINTR;
8265                 break;
8266         }
8267         return 1;
8268 }
8269
8270 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8271 {
8272         if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8273                 kvm_x86_ops->check_nested_events(vcpu, false);
8274
8275         return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8276                 !vcpu->arch.apf.halted);
8277 }
8278
8279 static int vcpu_run(struct kvm_vcpu *vcpu)
8280 {
8281         int r;
8282         struct kvm *kvm = vcpu->kvm;
8283
8284         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8285         vcpu->arch.l1tf_flush_l1d = true;
8286
8287         for (;;) {
8288                 if (kvm_vcpu_running(vcpu)) {
8289                         r = vcpu_enter_guest(vcpu);
8290                 } else {
8291                         r = vcpu_block(kvm, vcpu);
8292                 }
8293
8294                 if (r <= 0)
8295                         break;
8296
8297                 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8298                 if (kvm_cpu_has_pending_timer(vcpu))
8299                         kvm_inject_pending_timer_irqs(vcpu);
8300
8301                 if (dm_request_for_irq_injection(vcpu) &&
8302                         kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8303                         r = 0;
8304                         vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8305                         ++vcpu->stat.request_irq_exits;
8306                         break;
8307                 }
8308
8309                 kvm_check_async_pf_completion(vcpu);
8310
8311                 if (signal_pending(current)) {
8312                         r = -EINTR;
8313                         vcpu->run->exit_reason = KVM_EXIT_INTR;
8314                         ++vcpu->stat.signal_exits;
8315                         break;
8316                 }
8317                 if (need_resched()) {
8318                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8319                         cond_resched();
8320                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8321                 }
8322         }
8323
8324         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8325
8326         return r;
8327 }
8328
8329 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8330 {
8331         int r;
8332
8333         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8334         r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8335         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8336         return r;
8337 }
8338
8339 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8340 {
8341         BUG_ON(!vcpu->arch.pio.count);
8342
8343         return complete_emulated_io(vcpu);
8344 }
8345
8346 /*
8347  * Implements the following, as a state machine:
8348  *
8349  * read:
8350  *   for each fragment
8351  *     for each mmio piece in the fragment
8352  *       write gpa, len
8353  *       exit
8354  *       copy data
8355  *   execute insn
8356  *
8357  * write:
8358  *   for each fragment
8359  *     for each mmio piece in the fragment
8360  *       write gpa, len
8361  *       copy data
8362  *       exit
8363  */
8364 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8365 {
8366         struct kvm_run *run = vcpu->run;
8367         struct kvm_mmio_fragment *frag;
8368         unsigned len;
8369
8370         BUG_ON(!vcpu->mmio_needed);
8371
8372         /* Complete previous fragment */
8373         frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8374         len = min(8u, frag->len);
8375         if (!vcpu->mmio_is_write)
8376                 memcpy(frag->data, run->mmio.data, len);
8377
8378         if (frag->len <= 8) {
8379                 /* Switch to the next fragment. */
8380                 frag++;
8381                 vcpu->mmio_cur_fragment++;
8382         } else {
8383                 /* Go forward to the next mmio piece. */
8384                 frag->data += len;
8385                 frag->gpa += len;
8386                 frag->len -= len;
8387         }
8388
8389         if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8390                 vcpu->mmio_needed = 0;
8391
8392                 /* FIXME: return into emulator if single-stepping.  */
8393                 if (vcpu->mmio_is_write)
8394                         return 1;
8395                 vcpu->mmio_read_completed = 1;
8396                 return complete_emulated_io(vcpu);
8397         }
8398
8399         run->exit_reason = KVM_EXIT_MMIO;
8400         run->mmio.phys_addr = frag->gpa;
8401         if (vcpu->mmio_is_write)
8402                 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8403         run->mmio.len = min(8u, frag->len);
8404         run->mmio.is_write = vcpu->mmio_is_write;
8405         vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8406         return 0;
8407 }
8408
8409 /* Swap (qemu) user FPU context for the guest FPU context. */
8410 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8411 {
8412         fpregs_lock();
8413
8414         copy_fpregs_to_fpstate(vcpu->arch.user_fpu);
8415         /* PKRU is separately restored in kvm_x86_ops->run.  */
8416         __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8417                                 ~XFEATURE_MASK_PKRU);
8418
8419         fpregs_mark_activate();
8420         fpregs_unlock();
8421
8422         trace_kvm_fpu(1);
8423 }
8424
8425 /* When vcpu_run ends, restore user space FPU context. */
8426 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8427 {
8428         fpregs_lock();
8429
8430         copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
8431         copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8432
8433         fpregs_mark_activate();
8434         fpregs_unlock();
8435
8436         ++vcpu->stat.fpu_reload;
8437         trace_kvm_fpu(0);
8438 }
8439
8440 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8441 {
8442         int r;
8443
8444         vcpu_load(vcpu);
8445         kvm_sigset_activate(vcpu);
8446         kvm_load_guest_fpu(vcpu);
8447
8448         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8449                 if (kvm_run->immediate_exit) {
8450                         r = -EINTR;
8451                         goto out;
8452                 }
8453                 kvm_vcpu_block(vcpu);
8454                 kvm_apic_accept_events(vcpu);
8455                 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8456                 r = -EAGAIN;
8457                 if (signal_pending(current)) {
8458                         r = -EINTR;
8459                         vcpu->run->exit_reason = KVM_EXIT_INTR;
8460                         ++vcpu->stat.signal_exits;
8461                 }
8462                 goto out;
8463         }
8464
8465         if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8466                 r = -EINVAL;
8467                 goto out;
8468         }
8469
8470         if (vcpu->run->kvm_dirty_regs) {
8471                 r = sync_regs(vcpu);
8472                 if (r != 0)
8473                         goto out;
8474         }
8475
8476         /* re-sync apic's tpr */
8477         if (!lapic_in_kernel(vcpu)) {
8478                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8479                         r = -EINVAL;
8480                         goto out;
8481                 }
8482         }
8483
8484         if (unlikely(vcpu->arch.complete_userspace_io)) {
8485                 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8486                 vcpu->arch.complete_userspace_io = NULL;
8487                 r = cui(vcpu);
8488                 if (r <= 0)
8489                         goto out;
8490         } else
8491                 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8492
8493         if (kvm_run->immediate_exit)
8494                 r = -EINTR;
8495         else
8496                 r = vcpu_run(vcpu);
8497
8498 out:
8499         kvm_put_guest_fpu(vcpu);
8500         if (vcpu->run->kvm_valid_regs)
8501                 store_regs(vcpu);
8502         post_kvm_run_save(vcpu);
8503         kvm_sigset_deactivate(vcpu);
8504
8505         vcpu_put(vcpu);
8506         return r;
8507 }
8508
8509 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8510 {
8511         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8512                 /*
8513                  * We are here if userspace calls get_regs() in the middle of
8514                  * instruction emulation. Registers state needs to be copied
8515                  * back from emulation context to vcpu. Userspace shouldn't do
8516                  * that usually, but some bad designed PV devices (vmware
8517                  * backdoor interface) need this to work
8518                  */
8519                 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8520                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8521         }
8522         regs->rax = kvm_rax_read(vcpu);
8523         regs->rbx = kvm_rbx_read(vcpu);
8524         regs->rcx = kvm_rcx_read(vcpu);
8525         regs->rdx = kvm_rdx_read(vcpu);
8526         regs->rsi = kvm_rsi_read(vcpu);
8527         regs->rdi = kvm_rdi_read(vcpu);
8528         regs->rsp = kvm_rsp_read(vcpu);
8529         regs->rbp = kvm_rbp_read(vcpu);
8530 #ifdef CONFIG_X86_64
8531         regs->r8 = kvm_r8_read(vcpu);
8532         regs->r9 = kvm_r9_read(vcpu);
8533         regs->r10 = kvm_r10_read(vcpu);
8534         regs->r11 = kvm_r11_read(vcpu);
8535         regs->r12 = kvm_r12_read(vcpu);
8536         regs->r13 = kvm_r13_read(vcpu);
8537         regs->r14 = kvm_r14_read(vcpu);
8538         regs->r15 = kvm_r15_read(vcpu);
8539 #endif
8540
8541         regs->rip = kvm_rip_read(vcpu);
8542         regs->rflags = kvm_get_rflags(vcpu);
8543 }
8544
8545 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8546 {
8547         vcpu_load(vcpu);
8548         __get_regs(vcpu, regs);
8549         vcpu_put(vcpu);
8550         return 0;
8551 }
8552
8553 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8554 {
8555         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8556         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8557
8558         kvm_rax_write(vcpu, regs->rax);
8559         kvm_rbx_write(vcpu, regs->rbx);
8560         kvm_rcx_write(vcpu, regs->rcx);
8561         kvm_rdx_write(vcpu, regs->rdx);
8562         kvm_rsi_write(vcpu, regs->rsi);
8563         kvm_rdi_write(vcpu, regs->rdi);
8564         kvm_rsp_write(vcpu, regs->rsp);
8565         kvm_rbp_write(vcpu, regs->rbp);
8566 #ifdef CONFIG_X86_64
8567         kvm_r8_write(vcpu, regs->r8);
8568         kvm_r9_write(vcpu, regs->r9);
8569         kvm_r10_write(vcpu, regs->r10);
8570         kvm_r11_write(vcpu, regs->r11);
8571         kvm_r12_write(vcpu, regs->r12);
8572         kvm_r13_write(vcpu, regs->r13);
8573         kvm_r14_write(vcpu, regs->r14);
8574         kvm_r15_write(vcpu, regs->r15);
8575 #endif
8576
8577         kvm_rip_write(vcpu, regs->rip);
8578         kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8579
8580         vcpu->arch.exception.pending = false;
8581
8582         kvm_make_request(KVM_REQ_EVENT, vcpu);
8583 }
8584
8585 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8586 {
8587         vcpu_load(vcpu);
8588         __set_regs(vcpu, regs);
8589         vcpu_put(vcpu);
8590         return 0;
8591 }
8592
8593 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8594 {
8595         struct kvm_segment cs;
8596
8597         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8598         *db = cs.db;
8599         *l = cs.l;
8600 }
8601 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8602
8603 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8604 {
8605         struct desc_ptr dt;
8606
8607         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8608         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8609         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8610         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8611         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8612         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8613
8614         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8615         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8616
8617         kvm_x86_ops->get_idt(vcpu, &dt);
8618         sregs->idt.limit = dt.size;
8619         sregs->idt.base = dt.address;
8620         kvm_x86_ops->get_gdt(vcpu, &dt);
8621         sregs->gdt.limit = dt.size;
8622         sregs->gdt.base = dt.address;
8623
8624         sregs->cr0 = kvm_read_cr0(vcpu);
8625         sregs->cr2 = vcpu->arch.cr2;
8626         sregs->cr3 = kvm_read_cr3(vcpu);
8627         sregs->cr4 = kvm_read_cr4(vcpu);
8628         sregs->cr8 = kvm_get_cr8(vcpu);
8629         sregs->efer = vcpu->arch.efer;
8630         sregs->apic_base = kvm_get_apic_base(vcpu);
8631
8632         memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8633
8634         if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8635                 set_bit(vcpu->arch.interrupt.nr,
8636                         (unsigned long *)sregs->interrupt_bitmap);
8637 }
8638
8639 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8640                                   struct kvm_sregs *sregs)
8641 {
8642         vcpu_load(vcpu);
8643         __get_sregs(vcpu, sregs);
8644         vcpu_put(vcpu);
8645         return 0;
8646 }
8647
8648 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8649                                     struct kvm_mp_state *mp_state)
8650 {
8651         vcpu_load(vcpu);
8652
8653         kvm_apic_accept_events(vcpu);
8654         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8655                                         vcpu->arch.pv.pv_unhalted)
8656                 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8657         else
8658                 mp_state->mp_state = vcpu->arch.mp_state;
8659
8660         vcpu_put(vcpu);
8661         return 0;
8662 }
8663
8664 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8665                                     struct kvm_mp_state *mp_state)
8666 {
8667         int ret = -EINVAL;
8668
8669         vcpu_load(vcpu);
8670
8671         if (!lapic_in_kernel(vcpu) &&
8672             mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8673                 goto out;
8674
8675         /* INITs are latched while in SMM */
8676         if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8677             (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8678              mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8679                 goto out;
8680
8681         if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8682                 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8683                 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8684         } else
8685                 vcpu->arch.mp_state = mp_state->mp_state;
8686         kvm_make_request(KVM_REQ_EVENT, vcpu);
8687
8688         ret = 0;
8689 out:
8690         vcpu_put(vcpu);
8691         return ret;
8692 }
8693
8694 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8695                     int reason, bool has_error_code, u32 error_code)
8696 {
8697         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8698         int ret;
8699
8700         init_emulate_ctxt(vcpu);
8701
8702         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8703                                    has_error_code, error_code);
8704         if (ret) {
8705                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8706                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
8707                 vcpu->run->internal.ndata = 0;
8708                 return 0;
8709         }
8710
8711         kvm_rip_write(vcpu, ctxt->eip);
8712         kvm_set_rflags(vcpu, ctxt->eflags);
8713         kvm_make_request(KVM_REQ_EVENT, vcpu);
8714         return 1;
8715 }
8716 EXPORT_SYMBOL_GPL(kvm_task_switch);
8717
8718 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8719 {
8720         if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8721                 /*
8722                  * When EFER.LME and CR0.PG are set, the processor is in
8723                  * 64-bit mode (though maybe in a 32-bit code segment).
8724                  * CR4.PAE and EFER.LMA must be set.
8725                  */
8726                 if (!(sregs->cr4 & X86_CR4_PAE)
8727                     || !(sregs->efer & EFER_LMA))
8728                         return -EINVAL;
8729         } else {
8730                 /*
8731                  * Not in 64-bit mode: EFER.LMA is clear and the code
8732                  * segment cannot be 64-bit.
8733                  */
8734                 if (sregs->efer & EFER_LMA || sregs->cs.l)
8735                         return -EINVAL;
8736         }
8737
8738         return kvm_valid_cr4(vcpu, sregs->cr4);
8739 }
8740
8741 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8742 {
8743         struct msr_data apic_base_msr;
8744         int mmu_reset_needed = 0;
8745         int cpuid_update_needed = 0;
8746         int pending_vec, max_bits, idx;
8747         struct desc_ptr dt;
8748         int ret = -EINVAL;
8749
8750         if (kvm_valid_sregs(vcpu, sregs))
8751                 goto out;
8752
8753         apic_base_msr.data = sregs->apic_base;
8754         apic_base_msr.host_initiated = true;
8755         if (kvm_set_apic_base(vcpu, &apic_base_msr))
8756                 goto out;
8757
8758         dt.size = sregs->idt.limit;
8759         dt.address = sregs->idt.base;
8760         kvm_x86_ops->set_idt(vcpu, &dt);
8761         dt.size = sregs->gdt.limit;
8762         dt.address = sregs->gdt.base;
8763         kvm_x86_ops->set_gdt(vcpu, &dt);
8764
8765         vcpu->arch.cr2 = sregs->cr2;
8766         mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
8767         vcpu->arch.cr3 = sregs->cr3;
8768         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
8769
8770         kvm_set_cr8(vcpu, sregs->cr8);
8771
8772         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
8773         kvm_x86_ops->set_efer(vcpu, sregs->efer);
8774
8775         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
8776         kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
8777         vcpu->arch.cr0 = sregs->cr0;
8778
8779         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
8780         cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8781                                 (X86_CR4_OSXSAVE | X86_CR4_PKE));
8782         kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
8783         if (cpuid_update_needed)
8784                 kvm_update_cpuid(vcpu);
8785
8786         idx = srcu_read_lock(&vcpu->kvm->srcu);
8787         if (is_pae_paging(vcpu)) {
8788                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
8789                 mmu_reset_needed = 1;
8790         }
8791         srcu_read_unlock(&vcpu->kvm->srcu, idx);
8792
8793         if (mmu_reset_needed)
8794                 kvm_mmu_reset_context(vcpu);
8795
8796         max_bits = KVM_NR_INTERRUPTS;
8797         pending_vec = find_first_bit(
8798                 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8799         if (pending_vec < max_bits) {
8800                 kvm_queue_interrupt(vcpu, pending_vec, false);
8801                 pr_debug("Set back pending irq %d\n", pending_vec);
8802         }
8803
8804         kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8805         kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8806         kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8807         kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8808         kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8809         kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8810
8811         kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8812         kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8813
8814         update_cr8_intercept(vcpu);
8815
8816         /* Older userspace won't unhalt the vcpu on reset. */
8817         if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
8818             sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
8819             !is_protmode(vcpu))
8820                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8821
8822         kvm_make_request(KVM_REQ_EVENT, vcpu);
8823
8824         ret = 0;
8825 out:
8826         return ret;
8827 }
8828
8829 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8830                                   struct kvm_sregs *sregs)
8831 {
8832         int ret;
8833
8834         vcpu_load(vcpu);
8835         ret = __set_sregs(vcpu, sregs);
8836         vcpu_put(vcpu);
8837         return ret;
8838 }
8839
8840 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8841                                         struct kvm_guest_debug *dbg)
8842 {
8843         unsigned long rflags;
8844         int i, r;
8845
8846         vcpu_load(vcpu);
8847
8848         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8849                 r = -EBUSY;
8850                 if (vcpu->arch.exception.pending)
8851                         goto out;
8852                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8853                         kvm_queue_exception(vcpu, DB_VECTOR);
8854                 else
8855                         kvm_queue_exception(vcpu, BP_VECTOR);
8856         }
8857
8858         /*
8859          * Read rflags as long as potentially injected trace flags are still
8860          * filtered out.
8861          */
8862         rflags = kvm_get_rflags(vcpu);
8863
8864         vcpu->guest_debug = dbg->control;
8865         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8866                 vcpu->guest_debug = 0;
8867
8868         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
8869                 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8870                         vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
8871                 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
8872         } else {
8873                 for (i = 0; i < KVM_NR_DB_REGS; i++)
8874                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
8875         }
8876         kvm_update_dr7(vcpu);
8877
8878         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8879                 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8880                         get_segment_base(vcpu, VCPU_SREG_CS);
8881
8882         /*
8883          * Trigger an rflags update that will inject or remove the trace
8884          * flags.
8885          */
8886         kvm_set_rflags(vcpu, rflags);
8887
8888         kvm_x86_ops->update_bp_intercept(vcpu);
8889
8890         r = 0;
8891
8892 out:
8893         vcpu_put(vcpu);
8894         return r;
8895 }
8896
8897 /*
8898  * Translate a guest virtual address to a guest physical address.
8899  */
8900 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8901                                     struct kvm_translation *tr)
8902 {
8903         unsigned long vaddr = tr->linear_address;
8904         gpa_t gpa;
8905         int idx;
8906
8907         vcpu_load(vcpu);
8908
8909         idx = srcu_read_lock(&vcpu->kvm->srcu);
8910         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
8911         srcu_read_unlock(&vcpu->kvm->srcu, idx);
8912         tr->physical_address = gpa;
8913         tr->valid = gpa != UNMAPPED_GVA;
8914         tr->writeable = 1;
8915         tr->usermode = 0;
8916
8917         vcpu_put(vcpu);
8918         return 0;
8919 }
8920
8921 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8922 {
8923         struct fxregs_state *fxsave;
8924
8925         vcpu_load(vcpu);
8926
8927         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8928         memcpy(fpu->fpr, fxsave->st_space, 128);
8929         fpu->fcw = fxsave->cwd;
8930         fpu->fsw = fxsave->swd;
8931         fpu->ftwx = fxsave->twd;
8932         fpu->last_opcode = fxsave->fop;
8933         fpu->last_ip = fxsave->rip;
8934         fpu->last_dp = fxsave->rdp;
8935         memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
8936
8937         vcpu_put(vcpu);
8938         return 0;
8939 }
8940
8941 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8942 {
8943         struct fxregs_state *fxsave;
8944
8945         vcpu_load(vcpu);
8946
8947         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8948
8949         memcpy(fxsave->st_space, fpu->fpr, 128);
8950         fxsave->cwd = fpu->fcw;
8951         fxsave->swd = fpu->fsw;
8952         fxsave->twd = fpu->ftwx;
8953         fxsave->fop = fpu->last_opcode;
8954         fxsave->rip = fpu->last_ip;
8955         fxsave->rdp = fpu->last_dp;
8956         memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
8957
8958         vcpu_put(vcpu);
8959         return 0;
8960 }
8961
8962 static void store_regs(struct kvm_vcpu *vcpu)
8963 {
8964         BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8965
8966         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8967                 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8968
8969         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8970                 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8971
8972         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8973                 kvm_vcpu_ioctl_x86_get_vcpu_events(
8974                                 vcpu, &vcpu->run->s.regs.events);
8975 }
8976
8977 static int sync_regs(struct kvm_vcpu *vcpu)
8978 {
8979         if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8980                 return -EINVAL;
8981
8982         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8983                 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8984                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8985         }
8986         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8987                 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8988                         return -EINVAL;
8989                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8990         }
8991         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8992                 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8993                                 vcpu, &vcpu->run->s.regs.events))
8994                         return -EINVAL;
8995                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8996         }
8997
8998         return 0;
8999 }
9000
9001 static void fx_init(struct kvm_vcpu *vcpu)
9002 {
9003         fpstate_init(&vcpu->arch.guest_fpu->state);
9004         if (boot_cpu_has(X86_FEATURE_XSAVES))
9005                 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9006                         host_xcr0 | XSTATE_COMPACTION_ENABLED;
9007
9008         /*
9009          * Ensure guest xcr0 is valid for loading
9010          */
9011         vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9012
9013         vcpu->arch.cr0 |= X86_CR0_ET;
9014 }
9015
9016 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
9017 {
9018         void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
9019
9020         kvmclock_reset(vcpu);
9021
9022         kvm_x86_ops->vcpu_free(vcpu);
9023         free_cpumask_var(wbinvd_dirty_mask);
9024 }
9025
9026 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
9027                                                 unsigned int id)
9028 {
9029         struct kvm_vcpu *vcpu;
9030
9031         if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9032                 printk_once(KERN_WARNING
9033                 "kvm: SMP vm created on host with unstable TSC; "
9034                 "guest TSC will not be reliable\n");
9035
9036         vcpu = kvm_x86_ops->vcpu_create(kvm, id);
9037
9038         return vcpu;
9039 }
9040
9041 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
9042 {
9043         vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9044         vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9045         kvm_vcpu_mtrr_init(vcpu);
9046         vcpu_load(vcpu);
9047         kvm_vcpu_reset(vcpu, false);
9048         kvm_init_mmu(vcpu, false);
9049         vcpu_put(vcpu);
9050         return 0;
9051 }
9052
9053 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9054 {
9055         struct msr_data msr;
9056         struct kvm *kvm = vcpu->kvm;
9057
9058         kvm_hv_vcpu_postcreate(vcpu);
9059
9060         if (mutex_lock_killable(&vcpu->mutex))
9061                 return;
9062         vcpu_load(vcpu);
9063         msr.data = 0x0;
9064         msr.index = MSR_IA32_TSC;
9065         msr.host_initiated = true;
9066         kvm_write_tsc(vcpu, &msr);
9067         vcpu_put(vcpu);
9068
9069         /* poll control enabled by default */
9070         vcpu->arch.msr_kvm_poll_control = 1;
9071
9072         mutex_unlock(&vcpu->mutex);
9073
9074         if (!kvmclock_periodic_sync)
9075                 return;
9076
9077         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9078                                         KVMCLOCK_SYNC_PERIOD);
9079 }
9080
9081 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9082 {
9083         vcpu->arch.apf.msr_val = 0;
9084
9085         vcpu_load(vcpu);
9086         kvm_mmu_unload(vcpu);
9087         vcpu_put(vcpu);
9088
9089         kvm_x86_ops->vcpu_free(vcpu);
9090 }
9091
9092 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9093 {
9094         kvm_lapic_reset(vcpu, init_event);
9095
9096         vcpu->arch.hflags = 0;
9097
9098         vcpu->arch.smi_pending = 0;
9099         vcpu->arch.smi_count = 0;
9100         atomic_set(&vcpu->arch.nmi_queued, 0);
9101         vcpu->arch.nmi_pending = 0;
9102         vcpu->arch.nmi_injected = false;
9103         kvm_clear_interrupt_queue(vcpu);
9104         kvm_clear_exception_queue(vcpu);
9105         vcpu->arch.exception.pending = false;
9106
9107         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9108         kvm_update_dr0123(vcpu);
9109         vcpu->arch.dr6 = DR6_INIT;
9110         kvm_update_dr6(vcpu);
9111         vcpu->arch.dr7 = DR7_FIXED_1;
9112         kvm_update_dr7(vcpu);
9113
9114         vcpu->arch.cr2 = 0;
9115
9116         kvm_make_request(KVM_REQ_EVENT, vcpu);
9117         vcpu->arch.apf.msr_val = 0;
9118         vcpu->arch.st.msr_val = 0;
9119
9120         kvmclock_reset(vcpu);
9121
9122         kvm_clear_async_pf_completion_queue(vcpu);
9123         kvm_async_pf_hash_reset(vcpu);
9124         vcpu->arch.apf.halted = false;
9125
9126         if (kvm_mpx_supported()) {
9127                 void *mpx_state_buffer;
9128
9129                 /*
9130                  * To avoid have the INIT path from kvm_apic_has_events() that be
9131                  * called with loaded FPU and does not let userspace fix the state.
9132                  */
9133                 if (init_event)
9134                         kvm_put_guest_fpu(vcpu);
9135                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9136                                         XFEATURE_BNDREGS);
9137                 if (mpx_state_buffer)
9138                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9139                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9140                                         XFEATURE_BNDCSR);
9141                 if (mpx_state_buffer)
9142                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9143                 if (init_event)
9144                         kvm_load_guest_fpu(vcpu);
9145         }
9146
9147         if (!init_event) {
9148                 kvm_pmu_reset(vcpu);
9149                 vcpu->arch.smbase = 0x30000;
9150
9151                 vcpu->arch.msr_misc_features_enables = 0;
9152
9153                 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9154         }
9155
9156         memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9157         vcpu->arch.regs_avail = ~0;
9158         vcpu->arch.regs_dirty = ~0;
9159
9160         vcpu->arch.ia32_xss = 0;
9161
9162         kvm_x86_ops->vcpu_reset(vcpu, init_event);
9163 }
9164
9165 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9166 {
9167         struct kvm_segment cs;
9168
9169         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9170         cs.selector = vector << 8;
9171         cs.base = vector << 12;
9172         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9173         kvm_rip_write(vcpu, 0);
9174 }
9175
9176 int kvm_arch_hardware_enable(void)
9177 {
9178         struct kvm *kvm;
9179         struct kvm_vcpu *vcpu;
9180         int i;
9181         int ret;
9182         u64 local_tsc;
9183         u64 max_tsc = 0;
9184         bool stable, backwards_tsc = false;
9185
9186         kvm_shared_msr_cpu_online();
9187         ret = kvm_x86_ops->hardware_enable();
9188         if (ret != 0)
9189                 return ret;
9190
9191         local_tsc = rdtsc();
9192         stable = !kvm_check_tsc_unstable();
9193         list_for_each_entry(kvm, &vm_list, vm_list) {
9194                 kvm_for_each_vcpu(i, vcpu, kvm) {
9195                         if (!stable && vcpu->cpu == smp_processor_id())
9196                                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9197                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9198                                 backwards_tsc = true;
9199                                 if (vcpu->arch.last_host_tsc > max_tsc)
9200                                         max_tsc = vcpu->arch.last_host_tsc;
9201                         }
9202                 }
9203         }
9204
9205         /*
9206          * Sometimes, even reliable TSCs go backwards.  This happens on
9207          * platforms that reset TSC during suspend or hibernate actions, but
9208          * maintain synchronization.  We must compensate.  Fortunately, we can
9209          * detect that condition here, which happens early in CPU bringup,
9210          * before any KVM threads can be running.  Unfortunately, we can't
9211          * bring the TSCs fully up to date with real time, as we aren't yet far
9212          * enough into CPU bringup that we know how much real time has actually
9213          * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9214          * variables that haven't been updated yet.
9215          *
9216          * So we simply find the maximum observed TSC above, then record the
9217          * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
9218          * the adjustment will be applied.  Note that we accumulate
9219          * adjustments, in case multiple suspend cycles happen before some VCPU
9220          * gets a chance to run again.  In the event that no KVM threads get a
9221          * chance to run, we will miss the entire elapsed period, as we'll have
9222          * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9223          * loose cycle time.  This isn't too big a deal, since the loss will be
9224          * uniform across all VCPUs (not to mention the scenario is extremely
9225          * unlikely). It is possible that a second hibernate recovery happens
9226          * much faster than a first, causing the observed TSC here to be
9227          * smaller; this would require additional padding adjustment, which is
9228          * why we set last_host_tsc to the local tsc observed here.
9229          *
9230          * N.B. - this code below runs only on platforms with reliable TSC,
9231          * as that is the only way backwards_tsc is set above.  Also note
9232          * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9233          * have the same delta_cyc adjustment applied if backwards_tsc
9234          * is detected.  Note further, this adjustment is only done once,
9235          * as we reset last_host_tsc on all VCPUs to stop this from being
9236          * called multiple times (one for each physical CPU bringup).
9237          *
9238          * Platforms with unreliable TSCs don't have to deal with this, they
9239          * will be compensated by the logic in vcpu_load, which sets the TSC to
9240          * catchup mode.  This will catchup all VCPUs to real time, but cannot
9241          * guarantee that they stay in perfect synchronization.
9242          */
9243         if (backwards_tsc) {
9244                 u64 delta_cyc = max_tsc - local_tsc;
9245                 list_for_each_entry(kvm, &vm_list, vm_list) {
9246                         kvm->arch.backwards_tsc_observed = true;
9247                         kvm_for_each_vcpu(i, vcpu, kvm) {
9248                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9249                                 vcpu->arch.last_host_tsc = local_tsc;
9250                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9251                         }
9252
9253                         /*
9254                          * We have to disable TSC offset matching.. if you were
9255                          * booting a VM while issuing an S4 host suspend....
9256                          * you may have some problem.  Solving this issue is
9257                          * left as an exercise to the reader.
9258                          */
9259                         kvm->arch.last_tsc_nsec = 0;
9260                         kvm->arch.last_tsc_write = 0;
9261                 }
9262
9263         }
9264         return 0;
9265 }
9266
9267 void kvm_arch_hardware_disable(void)
9268 {
9269         kvm_x86_ops->hardware_disable();
9270         drop_user_return_notifiers();
9271 }
9272
9273 int kvm_arch_hardware_setup(void)
9274 {
9275         int r;
9276
9277         r = kvm_x86_ops->hardware_setup();
9278         if (r != 0)
9279                 return r;
9280
9281         if (kvm_has_tsc_control) {
9282                 /*
9283                  * Make sure the user can only configure tsc_khz values that
9284                  * fit into a signed integer.
9285                  * A min value is not calculated because it will always
9286                  * be 1 on all machines.
9287                  */
9288                 u64 max = min(0x7fffffffULL,
9289                               __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9290                 kvm_max_guest_tsc_khz = max;
9291
9292                 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9293         }
9294
9295         kvm_init_msr_list();
9296         return 0;
9297 }
9298
9299 void kvm_arch_hardware_unsetup(void)
9300 {
9301         kvm_x86_ops->hardware_unsetup();
9302 }
9303
9304 int kvm_arch_check_processor_compat(void)
9305 {
9306         return kvm_x86_ops->check_processor_compatibility();
9307 }
9308
9309 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9310 {
9311         return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9312 }
9313 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9314
9315 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9316 {
9317         return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9318 }
9319
9320 struct static_key kvm_no_apic_vcpu __read_mostly;
9321 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9322
9323 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9324 {
9325         struct page *page;
9326         int r;
9327
9328         vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9329         if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9330                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9331         else
9332                 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9333
9334         page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9335         if (!page) {
9336                 r = -ENOMEM;
9337                 goto fail;
9338         }
9339         vcpu->arch.pio_data = page_address(page);
9340
9341         kvm_set_tsc_khz(vcpu, max_tsc_khz);
9342
9343         r = kvm_mmu_create(vcpu);
9344         if (r < 0)
9345                 goto fail_free_pio_data;
9346
9347         if (irqchip_in_kernel(vcpu->kvm)) {
9348                 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9349                 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9350                 if (r < 0)
9351                         goto fail_mmu_destroy;
9352         } else
9353                 static_key_slow_inc(&kvm_no_apic_vcpu);
9354
9355         vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9356                                        GFP_KERNEL_ACCOUNT);
9357         if (!vcpu->arch.mce_banks) {
9358                 r = -ENOMEM;
9359                 goto fail_free_lapic;
9360         }
9361         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9362
9363         if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9364                                 GFP_KERNEL_ACCOUNT)) {
9365                 r = -ENOMEM;
9366                 goto fail_free_mce_banks;
9367         }
9368
9369         fx_init(vcpu);
9370
9371         vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9372
9373         vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9374
9375         vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9376
9377         kvm_async_pf_hash_reset(vcpu);
9378         kvm_pmu_init(vcpu);
9379
9380         vcpu->arch.pending_external_vector = -1;
9381         vcpu->arch.preempted_in_kernel = false;
9382
9383         kvm_hv_vcpu_init(vcpu);
9384
9385         return 0;
9386
9387 fail_free_mce_banks:
9388         kfree(vcpu->arch.mce_banks);
9389 fail_free_lapic:
9390         kvm_free_lapic(vcpu);
9391 fail_mmu_destroy:
9392         kvm_mmu_destroy(vcpu);
9393 fail_free_pio_data:
9394         free_page((unsigned long)vcpu->arch.pio_data);
9395 fail:
9396         return r;
9397 }
9398
9399 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9400 {
9401         int idx;
9402
9403         kvm_hv_vcpu_uninit(vcpu);
9404         kvm_pmu_destroy(vcpu);
9405         kfree(vcpu->arch.mce_banks);
9406         kvm_free_lapic(vcpu);
9407         idx = srcu_read_lock(&vcpu->kvm->srcu);
9408         kvm_mmu_destroy(vcpu);
9409         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9410         free_page((unsigned long)vcpu->arch.pio_data);
9411         if (!lapic_in_kernel(vcpu))
9412                 static_key_slow_dec(&kvm_no_apic_vcpu);
9413 }
9414
9415 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9416 {
9417         vcpu->arch.l1tf_flush_l1d = true;
9418         kvm_x86_ops->sched_in(vcpu, cpu);
9419 }
9420
9421 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9422 {
9423         if (type)
9424                 return -EINVAL;
9425
9426         INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9427         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9428         INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9429         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9430         atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9431
9432         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9433         set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9434         /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9435         set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9436                 &kvm->arch.irq_sources_bitmap);
9437
9438         raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9439         mutex_init(&kvm->arch.apic_map_lock);
9440         spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9441
9442         kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
9443         pvclock_update_vm_gtod_copy(kvm);
9444
9445         kvm->arch.guest_can_read_msr_platform_info = true;
9446
9447         INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9448         INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9449
9450         kvm_hv_init_vm(kvm);
9451         kvm_page_track_init(kvm);
9452         kvm_mmu_init_vm(kvm);
9453
9454         return kvm_x86_ops->vm_init(kvm);
9455 }
9456
9457 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9458 {
9459         vcpu_load(vcpu);
9460         kvm_mmu_unload(vcpu);
9461         vcpu_put(vcpu);
9462 }
9463
9464 static void kvm_free_vcpus(struct kvm *kvm)
9465 {
9466         unsigned int i;
9467         struct kvm_vcpu *vcpu;
9468
9469         /*
9470          * Unpin any mmu pages first.
9471          */
9472         kvm_for_each_vcpu(i, vcpu, kvm) {
9473                 kvm_clear_async_pf_completion_queue(vcpu);
9474                 kvm_unload_vcpu_mmu(vcpu);
9475         }
9476         kvm_for_each_vcpu(i, vcpu, kvm)
9477                 kvm_arch_vcpu_free(vcpu);
9478
9479         mutex_lock(&kvm->lock);
9480         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9481                 kvm->vcpus[i] = NULL;
9482
9483         atomic_set(&kvm->online_vcpus, 0);
9484         mutex_unlock(&kvm->lock);
9485 }
9486
9487 void kvm_arch_sync_events(struct kvm *kvm)
9488 {
9489         cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9490         cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9491         kvm_free_pit(kvm);
9492 }
9493
9494 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9495 {
9496         int i, r;
9497         unsigned long hva;
9498         struct kvm_memslots *slots = kvm_memslots(kvm);
9499         struct kvm_memory_slot *slot, old;
9500
9501         /* Called with kvm->slots_lock held.  */
9502         if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9503                 return -EINVAL;
9504
9505         slot = id_to_memslot(slots, id);
9506         if (size) {
9507                 if (slot->npages)
9508                         return -EEXIST;
9509
9510                 /*
9511                  * MAP_SHARED to prevent internal slot pages from being moved
9512                  * by fork()/COW.
9513                  */
9514                 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9515                               MAP_SHARED | MAP_ANONYMOUS, 0);
9516                 if (IS_ERR((void *)hva))
9517                         return PTR_ERR((void *)hva);
9518         } else {
9519                 if (!slot->npages)
9520                         return 0;
9521
9522                 hva = 0;
9523         }
9524
9525         old = *slot;
9526         for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9527                 struct kvm_userspace_memory_region m;
9528
9529                 m.slot = id | (i << 16);
9530                 m.flags = 0;
9531                 m.guest_phys_addr = gpa;
9532                 m.userspace_addr = hva;
9533                 m.memory_size = size;
9534                 r = __kvm_set_memory_region(kvm, &m);
9535                 if (r < 0)
9536                         return r;
9537         }
9538
9539         if (!size)
9540                 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
9541
9542         return 0;
9543 }
9544 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9545
9546 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9547 {
9548         int r;
9549
9550         mutex_lock(&kvm->slots_lock);
9551         r = __x86_set_memory_region(kvm, id, gpa, size);
9552         mutex_unlock(&kvm->slots_lock);
9553
9554         return r;
9555 }
9556 EXPORT_SYMBOL_GPL(x86_set_memory_region);
9557
9558 void kvm_arch_destroy_vm(struct kvm *kvm)
9559 {
9560         if (current->mm == kvm->mm) {
9561                 /*
9562                  * Free memory regions allocated on behalf of userspace,
9563                  * unless the the memory map has changed due to process exit
9564                  * or fd copying.
9565                  */
9566                 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9567                 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9568                 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9569         }
9570         if (kvm_x86_ops->vm_destroy)
9571                 kvm_x86_ops->vm_destroy(kvm);
9572         kvm_pic_destroy(kvm);
9573         kvm_ioapic_destroy(kvm);
9574         kvm_free_vcpus(kvm);
9575         kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9576         kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9577         kvm_mmu_uninit_vm(kvm);
9578         kvm_page_track_cleanup(kvm);
9579         kvm_hv_destroy_vm(kvm);
9580 }
9581
9582 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
9583                            struct kvm_memory_slot *dont)
9584 {
9585         int i;
9586
9587         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9588                 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
9589                         kvfree(free->arch.rmap[i]);
9590                         free->arch.rmap[i] = NULL;
9591                 }
9592                 if (i == 0)
9593                         continue;
9594
9595                 if (!dont || free->arch.lpage_info[i - 1] !=
9596                              dont->arch.lpage_info[i - 1]) {
9597                         kvfree(free->arch.lpage_info[i - 1]);
9598                         free->arch.lpage_info[i - 1] = NULL;
9599                 }
9600         }
9601
9602         kvm_page_track_free_memslot(free, dont);
9603 }
9604
9605 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9606                             unsigned long npages)
9607 {
9608         int i;
9609
9610         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9611                 struct kvm_lpage_info *linfo;
9612                 unsigned long ugfn;
9613                 int lpages;
9614                 int level = i + 1;
9615
9616                 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9617                                       slot->base_gfn, level) + 1;
9618
9619                 slot->arch.rmap[i] =
9620                         kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9621                                  GFP_KERNEL_ACCOUNT);
9622                 if (!slot->arch.rmap[i])
9623                         goto out_free;
9624                 if (i == 0)
9625                         continue;
9626
9627                 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9628                 if (!linfo)
9629                         goto out_free;
9630
9631                 slot->arch.lpage_info[i - 1] = linfo;
9632
9633                 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9634                         linfo[0].disallow_lpage = 1;
9635                 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9636                         linfo[lpages - 1].disallow_lpage = 1;
9637                 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9638                 /*
9639                  * If the gfn and userspace address are not aligned wrt each
9640                  * other, or if explicitly asked to, disable large page
9641                  * support for this slot
9642                  */
9643                 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9644                     !kvm_largepages_enabled()) {
9645                         unsigned long j;
9646
9647                         for (j = 0; j < lpages; ++j)
9648                                 linfo[j].disallow_lpage = 1;
9649                 }
9650         }
9651
9652         if (kvm_page_track_create_memslot(slot, npages))
9653                 goto out_free;
9654
9655         return 0;
9656
9657 out_free:
9658         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9659                 kvfree(slot->arch.rmap[i]);
9660                 slot->arch.rmap[i] = NULL;
9661                 if (i == 0)
9662                         continue;
9663
9664                 kvfree(slot->arch.lpage_info[i - 1]);
9665                 slot->arch.lpage_info[i - 1] = NULL;
9666         }
9667         return -ENOMEM;
9668 }
9669
9670 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9671 {
9672         /*
9673          * memslots->generation has been incremented.
9674          * mmio generation may have reached its maximum value.
9675          */
9676         kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9677 }
9678
9679 int kvm_arch_prepare_memory_region(struct kvm *kvm,
9680                                 struct kvm_memory_slot *memslot,
9681                                 const struct kvm_userspace_memory_region *mem,
9682                                 enum kvm_mr_change change)
9683 {
9684         return 0;
9685 }
9686
9687 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9688                                      struct kvm_memory_slot *new)
9689 {
9690         /* Still write protect RO slot */
9691         if (new->flags & KVM_MEM_READONLY) {
9692                 kvm_mmu_slot_remove_write_access(kvm, new);
9693                 return;
9694         }
9695
9696         /*
9697          * Call kvm_x86_ops dirty logging hooks when they are valid.
9698          *
9699          * kvm_x86_ops->slot_disable_log_dirty is called when:
9700          *
9701          *  - KVM_MR_CREATE with dirty logging is disabled
9702          *  - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9703          *
9704          * The reason is, in case of PML, we need to set D-bit for any slots
9705          * with dirty logging disabled in order to eliminate unnecessary GPA
9706          * logging in PML buffer (and potential PML buffer full VMEXT). This
9707          * guarantees leaving PML enabled during guest's lifetime won't have
9708          * any additional overhead from PML when guest is running with dirty
9709          * logging disabled for memory slots.
9710          *
9711          * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9712          * to dirty logging mode.
9713          *
9714          * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9715          *
9716          * In case of write protect:
9717          *
9718          * Write protect all pages for dirty logging.
9719          *
9720          * All the sptes including the large sptes which point to this
9721          * slot are set to readonly. We can not create any new large
9722          * spte on this slot until the end of the logging.
9723          *
9724          * See the comments in fast_page_fault().
9725          */
9726         if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9727                 if (kvm_x86_ops->slot_enable_log_dirty)
9728                         kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9729                 else
9730                         kvm_mmu_slot_remove_write_access(kvm, new);
9731         } else {
9732                 if (kvm_x86_ops->slot_disable_log_dirty)
9733                         kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9734         }
9735 }
9736
9737 void kvm_arch_commit_memory_region(struct kvm *kvm,
9738                                 const struct kvm_userspace_memory_region *mem,
9739                                 const struct kvm_memory_slot *old,
9740                                 const struct kvm_memory_slot *new,
9741                                 enum kvm_mr_change change)
9742 {
9743         if (!kvm->arch.n_requested_mmu_pages)
9744                 kvm_mmu_change_mmu_pages(kvm,
9745                                 kvm_mmu_calculate_default_mmu_pages(kvm));
9746
9747         /*
9748          * Dirty logging tracks sptes in 4k granularity, meaning that large
9749          * sptes have to be split.  If live migration is successful, the guest
9750          * in the source machine will be destroyed and large sptes will be
9751          * created in the destination. However, if the guest continues to run
9752          * in the source machine (for example if live migration fails), small
9753          * sptes will remain around and cause bad performance.
9754          *
9755          * Scan sptes if dirty logging has been stopped, dropping those
9756          * which can be collapsed into a single large-page spte.  Later
9757          * page faults will create the large-page sptes.
9758          *
9759          * There is no need to do this in any of the following cases:
9760          * CREATE:      No dirty mappings will already exist.
9761          * MOVE/DELETE: The old mappings will already have been cleaned up by
9762          *              kvm_arch_flush_shadow_memslot()
9763          */
9764         if (change == KVM_MR_FLAGS_ONLY &&
9765                 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9766                 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9767                 kvm_mmu_zap_collapsible_sptes(kvm, new);
9768
9769         /*
9770          * Set up write protection and/or dirty logging for the new slot.
9771          *
9772          * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9773          * been zapped so no dirty logging staff is needed for old slot. For
9774          * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9775          * new and it's also covered when dealing with the new slot.
9776          *
9777          * FIXME: const-ify all uses of struct kvm_memory_slot.
9778          */
9779         if (change != KVM_MR_DELETE)
9780                 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
9781 }
9782
9783 void kvm_arch_flush_shadow_all(struct kvm *kvm)
9784 {
9785         kvm_mmu_zap_all(kvm);
9786 }
9787
9788 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9789                                    struct kvm_memory_slot *slot)
9790 {
9791         kvm_page_track_flush_slot(kvm, slot);
9792 }
9793
9794 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9795 {
9796         return (is_guest_mode(vcpu) &&
9797                         kvm_x86_ops->guest_apic_has_interrupt &&
9798                         kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9799 }
9800
9801 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9802 {
9803         if (!list_empty_careful(&vcpu->async_pf.done))
9804                 return true;
9805
9806         if (kvm_apic_has_events(vcpu))
9807                 return true;
9808
9809         if (vcpu->arch.pv.pv_unhalted)
9810                 return true;
9811
9812         if (vcpu->arch.exception.pending)
9813                 return true;
9814
9815         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9816             (vcpu->arch.nmi_pending &&
9817              kvm_x86_ops->nmi_allowed(vcpu)))
9818                 return true;
9819
9820         if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9821             (vcpu->arch.smi_pending && !is_smm(vcpu)))
9822                 return true;
9823
9824         if (kvm_arch_interrupt_allowed(vcpu) &&
9825             (kvm_cpu_has_interrupt(vcpu) ||
9826             kvm_guest_apic_has_interrupt(vcpu)))
9827                 return true;
9828
9829         if (kvm_hv_has_stimer_pending(vcpu))
9830                 return true;
9831
9832         return false;
9833 }
9834
9835 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9836 {
9837         return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
9838 }
9839
9840 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
9841 {
9842         if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
9843                 return true;
9844
9845         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9846                 kvm_test_request(KVM_REQ_SMI, vcpu) ||
9847                  kvm_test_request(KVM_REQ_EVENT, vcpu))
9848                 return true;
9849
9850         if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
9851                 return true;
9852
9853         return false;
9854 }
9855
9856 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9857 {
9858         return vcpu->arch.preempted_in_kernel;
9859 }
9860
9861 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
9862 {
9863         return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
9864 }
9865
9866 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9867 {
9868         return kvm_x86_ops->interrupt_allowed(vcpu);
9869 }
9870
9871 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
9872 {
9873         if (is_64_bit_mode(vcpu))
9874                 return kvm_rip_read(vcpu);
9875         return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9876                      kvm_rip_read(vcpu));
9877 }
9878 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
9879
9880 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9881 {
9882         return kvm_get_linear_rip(vcpu) == linear_rip;
9883 }
9884 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9885
9886 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9887 {
9888         unsigned long rflags;
9889
9890         rflags = kvm_x86_ops->get_rflags(vcpu);
9891         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9892                 rflags &= ~X86_EFLAGS_TF;
9893         return rflags;
9894 }
9895 EXPORT_SYMBOL_GPL(kvm_get_rflags);
9896
9897 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9898 {
9899         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
9900             kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
9901                 rflags |= X86_EFLAGS_TF;
9902         kvm_x86_ops->set_rflags(vcpu, rflags);
9903 }
9904
9905 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9906 {
9907         __kvm_set_rflags(vcpu, rflags);
9908         kvm_make_request(KVM_REQ_EVENT, vcpu);
9909 }
9910 EXPORT_SYMBOL_GPL(kvm_set_rflags);
9911
9912 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9913 {
9914         int r;
9915
9916         if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
9917               work->wakeup_all)
9918                 return;
9919
9920         r = kvm_mmu_reload(vcpu);
9921         if (unlikely(r))
9922                 return;
9923
9924         if (!vcpu->arch.mmu->direct_map &&
9925               work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
9926                 return;
9927
9928         vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
9929 }
9930
9931 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9932 {
9933         return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9934 }
9935
9936 static inline u32 kvm_async_pf_next_probe(u32 key)
9937 {
9938         return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9939 }
9940
9941 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9942 {
9943         u32 key = kvm_async_pf_hash_fn(gfn);
9944
9945         while (vcpu->arch.apf.gfns[key] != ~0)
9946                 key = kvm_async_pf_next_probe(key);
9947
9948         vcpu->arch.apf.gfns[key] = gfn;
9949 }
9950
9951 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9952 {
9953         int i;
9954         u32 key = kvm_async_pf_hash_fn(gfn);
9955
9956         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
9957                      (vcpu->arch.apf.gfns[key] != gfn &&
9958                       vcpu->arch.apf.gfns[key] != ~0); i++)
9959                 key = kvm_async_pf_next_probe(key);
9960
9961         return key;
9962 }
9963
9964 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9965 {
9966         return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9967 }
9968
9969 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9970 {
9971         u32 i, j, k;
9972
9973         i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9974         while (true) {
9975                 vcpu->arch.apf.gfns[i] = ~0;
9976                 do {
9977                         j = kvm_async_pf_next_probe(j);
9978                         if (vcpu->arch.apf.gfns[j] == ~0)
9979                                 return;
9980                         k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9981                         /*
9982                          * k lies cyclically in ]i,j]
9983                          * |    i.k.j |
9984                          * |....j i.k.| or  |.k..j i...|
9985                          */
9986                 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9987                 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9988                 i = j;
9989         }
9990 }
9991
9992 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9993 {
9994
9995         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9996                                       sizeof(val));
9997 }
9998
9999 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
10000 {
10001
10002         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10003                                       sizeof(u32));
10004 }
10005
10006 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10007 {
10008         if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10009                 return false;
10010
10011         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10012             (vcpu->arch.apf.send_user_only &&
10013              kvm_x86_ops->get_cpl(vcpu) == 0))
10014                 return false;
10015
10016         return true;
10017 }
10018
10019 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10020 {
10021         if (unlikely(!lapic_in_kernel(vcpu) ||
10022                      kvm_event_needs_reinjection(vcpu) ||
10023                      vcpu->arch.exception.pending))
10024                 return false;
10025
10026         if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10027                 return false;
10028
10029         /*
10030          * If interrupts are off we cannot even use an artificial
10031          * halt state.
10032          */
10033         return kvm_x86_ops->interrupt_allowed(vcpu);
10034 }
10035
10036 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10037                                      struct kvm_async_pf *work)
10038 {
10039         struct x86_exception fault;
10040
10041         trace_kvm_async_pf_not_present(work->arch.token, work->gva);
10042         kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10043
10044         if (kvm_can_deliver_async_pf(vcpu) &&
10045             !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
10046                 fault.vector = PF_VECTOR;
10047                 fault.error_code_valid = true;
10048                 fault.error_code = 0;
10049                 fault.nested_page_fault = false;
10050                 fault.address = work->arch.token;
10051                 fault.async_page_fault = true;
10052                 kvm_inject_page_fault(vcpu, &fault);
10053         } else {
10054                 /*
10055                  * It is not possible to deliver a paravirtualized asynchronous
10056                  * page fault, but putting the guest in an artificial halt state
10057                  * can be beneficial nevertheless: if an interrupt arrives, we
10058                  * can deliver it timely and perhaps the guest will schedule
10059                  * another process.  When the instruction that triggered a page
10060                  * fault is retried, hopefully the page will be ready in the host.
10061                  */
10062                 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10063         }
10064 }
10065
10066 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10067                                  struct kvm_async_pf *work)
10068 {
10069         struct x86_exception fault;
10070         u32 val;
10071
10072         if (work->wakeup_all)
10073                 work->arch.token = ~0; /* broadcast wakeup */
10074         else
10075                 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10076         trace_kvm_async_pf_ready(work->arch.token, work->gva);
10077
10078         if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10079             !apf_get_user(vcpu, &val)) {
10080                 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10081                     vcpu->arch.exception.pending &&
10082                     vcpu->arch.exception.nr == PF_VECTOR &&
10083                     !apf_put_user(vcpu, 0)) {
10084                         vcpu->arch.exception.injected = false;
10085                         vcpu->arch.exception.pending = false;
10086                         vcpu->arch.exception.nr = 0;
10087                         vcpu->arch.exception.has_error_code = false;
10088                         vcpu->arch.exception.error_code = 0;
10089                         vcpu->arch.exception.has_payload = false;
10090                         vcpu->arch.exception.payload = 0;
10091                 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10092                         fault.vector = PF_VECTOR;
10093                         fault.error_code_valid = true;
10094                         fault.error_code = 0;
10095                         fault.nested_page_fault = false;
10096                         fault.address = work->arch.token;
10097                         fault.async_page_fault = true;
10098                         kvm_inject_page_fault(vcpu, &fault);
10099                 }
10100         }
10101         vcpu->arch.apf.halted = false;
10102         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10103 }
10104
10105 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10106 {
10107         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10108                 return true;
10109         else
10110                 return kvm_can_do_async_pf(vcpu);
10111 }
10112
10113 void kvm_arch_start_assignment(struct kvm *kvm)
10114 {
10115         atomic_inc(&kvm->arch.assigned_device_count);
10116 }
10117 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10118
10119 void kvm_arch_end_assignment(struct kvm *kvm)
10120 {
10121         atomic_dec(&kvm->arch.assigned_device_count);
10122 }
10123 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10124
10125 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10126 {
10127         return atomic_read(&kvm->arch.assigned_device_count);
10128 }
10129 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10130
10131 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10132 {
10133         atomic_inc(&kvm->arch.noncoherent_dma_count);
10134 }
10135 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10136
10137 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10138 {
10139         atomic_dec(&kvm->arch.noncoherent_dma_count);
10140 }
10141 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10142
10143 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10144 {
10145         return atomic_read(&kvm->arch.noncoherent_dma_count);
10146 }
10147 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10148
10149 bool kvm_arch_has_irq_bypass(void)
10150 {
10151         return true;
10152 }
10153
10154 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10155                                       struct irq_bypass_producer *prod)
10156 {
10157         struct kvm_kernel_irqfd *irqfd =
10158                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10159
10160         irqfd->producer = prod;
10161
10162         return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10163                                            prod->irq, irqfd->gsi, 1);
10164 }
10165
10166 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10167                                       struct irq_bypass_producer *prod)
10168 {
10169         int ret;
10170         struct kvm_kernel_irqfd *irqfd =
10171                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10172
10173         WARN_ON(irqfd->producer != prod);
10174         irqfd->producer = NULL;
10175
10176         /*
10177          * When producer of consumer is unregistered, we change back to
10178          * remapped mode, so we can re-use the current implementation
10179          * when the irq is masked/disabled or the consumer side (KVM
10180          * int this case doesn't want to receive the interrupts.
10181         */
10182         ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10183         if (ret)
10184                 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10185                        " fails: %d\n", irqfd->consumer.token, ret);
10186 }
10187
10188 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10189                                    uint32_t guest_irq, bool set)
10190 {
10191         return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10192 }
10193
10194 bool kvm_vector_hashing_enabled(void)
10195 {
10196         return vector_hashing;
10197 }
10198 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
10199
10200 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10201 {
10202         return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10203 }
10204 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10205
10206
10207 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10208 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10209 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10210 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10211 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10212 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10213 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10214 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10215 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10216 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10217 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10218 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10219 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10220 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10221 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10222 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10223 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10224 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10225 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10226 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);