arch/x86/kvm/x86.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * derived from drivers/kvm/kvm_main.c
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright (C) 2008 Qumranet, Inc.
   9  * Copyright IBM Corporation, 2008
  10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  11  *
  12  * Authors:
  13  *   Avi Kivity   <avi@qumranet.com>
  14  *   Yaniv Kamay  <yaniv@qumranet.com>
  15  *   Amit Shah    <amit.shah@qumranet.com>
  16  *   Ben-Ami Yassour <benami@il.ibm.com>
  17  */
  18
  19 #include <linux/kvm_host.h>
  20 #include "irq.h"
  21 #include "mmu.h"
  22 #include "i8254.h"
  23 #include "tss.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28 #include "hyperv.h"
  29
  30 #include <linux/clocksource.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/kvm.h>
  33 #include <linux/fs.h>
  34 #include <linux/vmalloc.h>
  35 #include <linux/export.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/mman.h>
  38 #include <linux/highmem.h>
  39 #include <linux/iommu.h>
  40 #include <linux/intel-iommu.h>
  41 #include <linux/cpufreq.h>
  42 #include <linux/user-return-notifier.h>
  43 #include <linux/srcu.h>
  44 #include <linux/slab.h>
  45 #include <linux/perf_event.h>
  46 #include <linux/uaccess.h>
  47 #include <linux/hash.h>
  48 #include <linux/pci.h>
  49 #include <linux/timekeeper_internal.h>
  50 #include <linux/pvclock_gtod.h>
  51 #include <linux/kvm_irqfd.h>
  52 #include <linux/irqbypass.h>
  53 #include <linux/sched/stat.h>
  54 #include <linux/sched/isolation.h>
  55 #include <linux/mem_encrypt.h>
  56
  57 #include <trace/events/kvm.h>
  58
  59 #include <asm/debugreg.h>
  60 #include <asm/msr.h>
  61 #include <asm/desc.h>
  62 #include <asm/mce.h>
  63 #include <linux/kernel_stat.h>
  64 #include <asm/fpu/internal.h> /* Ugh! */
  65 #include <asm/pvclock.h>
  66 #include <asm/div64.h>
  67 #include <asm/irq_remapping.h>
  68 #include <asm/mshyperv.h>
  69 #include <asm/hypervisor.h>
  70 #include <asm/intel_pt.h>
  71 #include <clocksource/hyperv_timer.h>
  72
  73 #define CREATE_TRACE_POINTS
  74 #include "trace.h"
  75
  76 #define MAX_IO_MSRS 256
  77 #define KVM_MAX_MCE_BANKS 32
  78 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
  79 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
  80
  81 #define emul_to_vcpu(ctxt) \
  82         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
  83
  84 /* EFER defaults:
  85  * - enable syscall per default because its emulated by KVM
  86  * - enable LME and LMA per default on 64 bit KVM
  87  */
  88 #ifdef CONFIG_X86_64
  89 static
  90 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
  91 #else
  92 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
  93 #endif
  94
  95 #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__
  96 #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__
  97
  98 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
  99                                     KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
 100
 101 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
 102 static void process_nmi(struct kvm_vcpu *vcpu);
 103 static void enter_smm(struct kvm_vcpu *vcpu);
 104 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
 105 static void store_regs(struct kvm_vcpu *vcpu);
 106 static int sync_regs(struct kvm_vcpu *vcpu);
 107
 108 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
 109 EXPORT_SYMBOL_GPL(kvm_x86_ops);
 110
 111 static bool __read_mostly ignore_msrs = 0;
 112 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
 113
 114 static bool __read_mostly report_ignored_msrs = true;
 115 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
 116
 117 unsigned int min_timer_period_us = 200;
 118 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
 119
 120 static bool __read_mostly kvmclock_periodic_sync = true;
 121 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
 122
 123 bool __read_mostly kvm_has_tsc_control;
 124 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
 125 u32  __read_mostly kvm_max_guest_tsc_khz;
 126 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
 127 u8   __read_mostly kvm_tsc_scaling_ratio_frac_bits;
 128 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
 129 u64  __read_mostly kvm_max_tsc_scaling_ratio;
 130 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
 131 u64 __read_mostly kvm_default_tsc_scaling_ratio;
 132 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
 133
 134 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
 135 static u32 __read_mostly tsc_tolerance_ppm = 250;
 136 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
 137
 138 /*
 139  * lapic timer advance (tscdeadline mode only) in nanoseconds.  '-1' enables
 140  * adaptive tuning starting from default advancment of 1000ns.  '0' disables
 141  * advancement entirely.  Any other value is used as-is and disables adaptive
 142  * tuning, i.e. allows priveleged userspace to set an exact advancement time.
 143  */
 144 static int __read_mostly lapic_timer_advance_ns = -1;
 145 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
 146
 147 static bool __read_mostly vector_hashing = true;
 148 module_param(vector_hashing, bool, S_IRUGO);
 149
 150 bool __read_mostly enable_vmware_backdoor = false;
 151 module_param(enable_vmware_backdoor, bool, S_IRUGO);
 152 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
 153
 154 static bool __read_mostly force_emulation_prefix = false;
 155 module_param(force_emulation_prefix, bool, S_IRUGO);
 156
 157 int __read_mostly pi_inject_timer = -1;
 158 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
 159
 160 #define KVM_NR_SHARED_MSRS 16
 161
 162 struct kvm_shared_msrs_global {
 163         int nr;
 164         u32 msrs[KVM_NR_SHARED_MSRS];
 165 };
 166
 167 struct kvm_shared_msrs {
 168         struct user_return_notifier urn;
 169         bool registered;
 170         struct kvm_shared_msr_values {
 171                 u64 host;
 172                 u64 curr;
 173         } values[KVM_NR_SHARED_MSRS];
 174 };
 175
 176 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
 177 static struct kvm_shared_msrs __percpu *shared_msrs;
 178
 179 struct kvm_stats_debugfs_item debugfs_entries[] = {
 180         { "pf_fixed", VCPU_STAT(pf_fixed) },
 181         { "pf_guest", VCPU_STAT(pf_guest) },
 182         { "tlb_flush", VCPU_STAT(tlb_flush) },
 183         { "invlpg", VCPU_STAT(invlpg) },
 184         { "exits", VCPU_STAT(exits) },
 185         { "io_exits", VCPU_STAT(io_exits) },
 186         { "mmio_exits", VCPU_STAT(mmio_exits) },
 187         { "signal_exits", VCPU_STAT(signal_exits) },
 188         { "irq_window", VCPU_STAT(irq_window_exits) },
 189         { "nmi_window", VCPU_STAT(nmi_window_exits) },
 190         { "halt_exits", VCPU_STAT(halt_exits) },
 191         { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
 192         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
 193         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
 194         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
 195         { "hypercalls", VCPU_STAT(hypercalls) },
 196         { "request_irq", VCPU_STAT(request_irq_exits) },
 197         { "irq_exits", VCPU_STAT(irq_exits) },
 198         { "host_state_reload", VCPU_STAT(host_state_reload) },
 199         { "fpu_reload", VCPU_STAT(fpu_reload) },
 200         { "insn_emulation", VCPU_STAT(insn_emulation) },
 201         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
 202         { "irq_injections", VCPU_STAT(irq_injections) },
 203         { "nmi_injections", VCPU_STAT(nmi_injections) },
 204         { "req_event", VCPU_STAT(req_event) },
 205         { "l1d_flush", VCPU_STAT(l1d_flush) },
 206         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
 207         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
 208         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
 209         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
 210         { "mmu_flooded", VM_STAT(mmu_flooded) },
 211         { "mmu_recycled", VM_STAT(mmu_recycled) },
 212         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
 213         { "mmu_unsync", VM_STAT(mmu_unsync) },
 214         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
 215         { "largepages", VM_STAT(lpages, .mode = 0444) },
 216         { "max_mmu_page_hash_collisions",
 217                 VM_STAT(max_mmu_page_hash_collisions) },
 218         { NULL }
 219 };
 220
 221 u64 __read_mostly host_xcr0;
 222
 223 struct kmem_cache *x86_fpu_cache;
 224 EXPORT_SYMBOL_GPL(x86_fpu_cache);
 225
 226 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
 227
 228 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
 229 {
 230         int i;
 231         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
 232                 vcpu->arch.apf.gfns[i] = ~0;
 233 }
 234
 235 static void kvm_on_user_return(struct user_return_notifier *urn)
 236 {
 237         unsigned slot;
 238         struct kvm_shared_msrs *locals
 239                 = container_of(urn, struct kvm_shared_msrs, urn);
 240         struct kvm_shared_msr_values *values;
 241         unsigned long flags;
 242
 243         /*
 244          * Disabling irqs at this point since the following code could be
 245          * interrupted and executed through kvm_arch_hardware_disable()
 246          */
 247         local_irq_save(flags);
 248         if (locals->registered) {
 249                 locals->registered = false;
 250                 user_return_notifier_unregister(urn);
 251         }
 252         local_irq_restore(flags);
 253         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
 254                 values = &locals->values[slot];
 255                 if (values->host != values->curr) {
 256                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
 257                         values->curr = values->host;
 258                 }
 259         }
 260 }
 261
 262 static void shared_msr_update(unsigned slot, u32 msr)
 263 {
 264         u64 value;
 265         unsigned int cpu = smp_processor_id();
 266         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 267
 268         /* only read, and nobody should modify it at this time,
 269          * so don't need lock */
 270         if (slot >= shared_msrs_global.nr) {
 271                 printk(KERN_ERR "kvm: invalid MSR slot!");
 272                 return;
 273         }
 274         rdmsrl_safe(msr, &value);
 275         smsr->values[slot].host = value;
 276         smsr->values[slot].curr = value;
 277 }
 278
 279 void kvm_define_shared_msr(unsigned slot, u32 msr)
 280 {
 281         BUG_ON(slot >= KVM_NR_SHARED_MSRS);
 282         shared_msrs_global.msrs[slot] = msr;
 283         if (slot >= shared_msrs_global.nr)
 284                 shared_msrs_global.nr = slot + 1;
 285 }
 286 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
 287
 288 static void kvm_shared_msr_cpu_online(void)
 289 {
 290         unsigned i;
 291
 292         for (i = 0; i < shared_msrs_global.nr; ++i)
 293                 shared_msr_update(i, shared_msrs_global.msrs[i]);
 294 }
 295
 296 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
 297 {
 298         unsigned int cpu = smp_processor_id();
 299         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 300         int err;
 301
 302         if (((value ^ smsr->values[slot].curr) & mask) == 0)
 303                 return 0;
 304         smsr->values[slot].curr = value;
 305         err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
 306         if (err)
 307                 return 1;
 308
 309         if (!smsr->registered) {
 310                 smsr->urn.on_user_return = kvm_on_user_return;
 311                 user_return_notifier_register(&smsr->urn);
 312                 smsr->registered = true;
 313         }
 314         return 0;
 315 }
 316 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
 317
 318 static void drop_user_return_notifiers(void)
 319 {
 320         unsigned int cpu = smp_processor_id();
 321         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 322
 323         if (smsr->registered)
 324                 kvm_on_user_return(&smsr->urn);
 325 }
 326
 327 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
 328 {
 329         return vcpu->arch.apic_base;
 330 }
 331 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
 332
 333 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
 334 {
 335         return kvm_apic_mode(kvm_get_apic_base(vcpu));
 336 }
 337 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
 338
 339 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 340 {
 341         enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
 342         enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
 343         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
 344                 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
 345
 346         if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
 347                 return 1;
 348         if (!msr_info->host_initiated) {
 349                 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
 350                         return 1;
 351                 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
 352                         return 1;
 353         }
 354
 355         kvm_lapic_set_base(vcpu, msr_info->data);
 356         return 0;
 357 }
 358 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
 359
 360 asmlinkage __visible void kvm_spurious_fault(void)
 361 {
 362         /* Fault while not rebooting.  We want the trace. */
 363         if (!kvm_rebooting)
 364                 BUG();
 365 }
 366 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
 367
 368 #define EXCPT_BENIGN            0
 369 #define EXCPT_CONTRIBUTORY      1
 370 #define EXCPT_PF                2
 371
 372 static int exception_class(int vector)
 373 {
 374         switch (vector) {
 375         case PF_VECTOR:
 376                 return EXCPT_PF;
 377         case DE_VECTOR:
 378         case TS_VECTOR:
 379         case NP_VECTOR:
 380         case SS_VECTOR:
 381         case GP_VECTOR:
 382                 return EXCPT_CONTRIBUTORY;
 383         default:
 384                 break;
 385         }
 386         return EXCPT_BENIGN;
 387 }
 388
 389 #define EXCPT_FAULT             0
 390 #define EXCPT_TRAP              1
 391 #define EXCPT_ABORT             2
 392 #define EXCPT_INTERRUPT         3
 393
 394 static int exception_type(int vector)
 395 {
 396         unsigned int mask;
 397
 398         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
 399                 return EXCPT_INTERRUPT;
 400
 401         mask = 1 << vector;
 402
 403         /* #DB is trap, as instruction watchpoints are handled elsewhere */
 404         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
 405                 return EXCPT_TRAP;
 406
 407         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
 408                 return EXCPT_ABORT;
 409
 410         /* Reserved exceptions will result in fault */
 411         return EXCPT_FAULT;
 412 }
 413
 414 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
 415 {
 416         unsigned nr = vcpu->arch.exception.nr;
 417         bool has_payload = vcpu->arch.exception.has_payload;
 418         unsigned long payload = vcpu->arch.exception.payload;
 419
 420         if (!has_payload)
 421                 return;
 422
 423         switch (nr) {
 424         case DB_VECTOR:
 425                 /*
 426                  * "Certain debug exceptions may clear bit 0-3.  The
 427                  * remaining contents of the DR6 register are never
 428                  * cleared by the processor".
 429                  */
 430                 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
 431                 /*
 432                  * DR6.RTM is set by all #DB exceptions that don't clear it.
 433                  */
 434                 vcpu->arch.dr6 |= DR6_RTM;
 435                 vcpu->arch.dr6 |= payload;
 436                 /*
 437                  * Bit 16 should be set in the payload whenever the #DB
 438                  * exception should clear DR6.RTM. This makes the payload
 439                  * compatible with the pending debug exceptions under VMX.
 440                  * Though not currently documented in the SDM, this also
 441                  * makes the payload compatible with the exit qualification
 442                  * for #DB exceptions under VMX.
 443                  */
 444                 vcpu->arch.dr6 ^= payload & DR6_RTM;
 445                 break;
 446         case PF_VECTOR:
 447                 vcpu->arch.cr2 = payload;
 448                 break;
 449         }
 450
 451         vcpu->arch.exception.has_payload = false;
 452         vcpu->arch.exception.payload = 0;
 453 }
 454 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
 455
 456 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
 457                 unsigned nr, bool has_error, u32 error_code,
 458                 bool has_payload, unsigned long payload, bool reinject)
 459 {
 460         u32 prev_nr;
 461         int class1, class2;
 462
 463         kvm_make_request(KVM_REQ_EVENT, vcpu);
 464
 465         if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
 466         queue:
 467                 if (has_error && !is_protmode(vcpu))
 468                         has_error = false;
 469                 if (reinject) {
 470                         /*
 471                          * On vmentry, vcpu->arch.exception.pending is only
 472                          * true if an event injection was blocked by
 473                          * nested_run_pending.  In that case, however,
 474                          * vcpu_enter_guest requests an immediate exit,
 475                          * and the guest shouldn't proceed far enough to
 476                          * need reinjection.
 477                          */
 478                         WARN_ON_ONCE(vcpu->arch.exception.pending);
 479                         vcpu->arch.exception.injected = true;
 480                         if (WARN_ON_ONCE(has_payload)) {
 481                                 /*
 482                                  * A reinjected event has already
 483                                  * delivered its payload.
 484                                  */
 485                                 has_payload = false;
 486                                 payload = 0;
 487                         }
 488                 } else {
 489                         vcpu->arch.exception.pending = true;
 490                         vcpu->arch.exception.injected = false;
 491                 }
 492                 vcpu->arch.exception.has_error_code = has_error;
 493                 vcpu->arch.exception.nr = nr;
 494                 vcpu->arch.exception.error_code = error_code;
 495                 vcpu->arch.exception.has_payload = has_payload;
 496                 vcpu->arch.exception.payload = payload;
 497                 /*
 498                  * In guest mode, payload delivery should be deferred,
 499                  * so that the L1 hypervisor can intercept #PF before
 500                  * CR2 is modified (or intercept #DB before DR6 is
 501                  * modified under nVMX).  However, for ABI
 502                  * compatibility with KVM_GET_VCPU_EVENTS and
 503                  * KVM_SET_VCPU_EVENTS, we can't delay payload
 504                  * delivery unless userspace has enabled this
 505                  * functionality via the per-VM capability,
 506                  * KVM_CAP_EXCEPTION_PAYLOAD.
 507                  */
 508                 if (!vcpu->kvm->arch.exception_payload_enabled ||
 509                     !is_guest_mode(vcpu))
 510                         kvm_deliver_exception_payload(vcpu);
 511                 return;
 512         }
 513
 514         /* to check exception */
 515         prev_nr = vcpu->arch.exception.nr;
 516         if (prev_nr == DF_VECTOR) {
 517                 /* triple fault -> shutdown */
 518                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
 519                 return;
 520         }
 521         class1 = exception_class(prev_nr);
 522         class2 = exception_class(nr);
 523         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
 524                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
 525                 /*
 526                  * Generate double fault per SDM Table 5-5.  Set
 527                  * exception.pending = true so that the double fault
 528                  * can trigger a nested vmexit.
 529                  */
 530                 vcpu->arch.exception.pending = true;
 531                 vcpu->arch.exception.injected = false;
 532                 vcpu->arch.exception.has_error_code = true;
 533                 vcpu->arch.exception.nr = DF_VECTOR;
 534                 vcpu->arch.exception.error_code = 0;
 535                 vcpu->arch.exception.has_payload = false;
 536                 vcpu->arch.exception.payload = 0;
 537         } else
 538                 /* replace previous exception with a new one in a hope
 539                    that instruction re-execution will regenerate lost
 540                    exception */
 541                 goto queue;
 542 }
 543
 544 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 545 {
 546         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
 547 }
 548 EXPORT_SYMBOL_GPL(kvm_queue_exception);
 549
 550 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 551 {
 552         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
 553 }
 554 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
 555
 556 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
 557                                   unsigned long payload)
 558 {
 559         kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
 560 }
 561
 562 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
 563                                     u32 error_code, unsigned long payload)
 564 {
 565         kvm_multiple_exception(vcpu, nr, true, error_code,
 566                                true, payload, false);
 567 }
 568
 569 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
 570 {
 571         if (err)
 572                 kvm_inject_gp(vcpu, 0);
 573         else
 574                 return kvm_skip_emulated_instruction(vcpu);
 575
 576         return 1;
 577 }
 578 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
 579
 580 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 581 {
 582         ++vcpu->stat.pf_guest;
 583         vcpu->arch.exception.nested_apf =
 584                 is_guest_mode(vcpu) && fault->async_page_fault;
 585         if (vcpu->arch.exception.nested_apf) {
 586                 vcpu->arch.apf.nested_apf_token = fault->address;
 587                 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
 588         } else {
 589                 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
 590                                         fault->address);
 591         }
 592 }
 593 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
 594
 595 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 596 {
 597         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
 598                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
 599         else
 600                 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
 601
 602         return fault->nested_page_fault;
 603 }
 604
 605 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
 606 {
 607         atomic_inc(&vcpu->arch.nmi_queued);
 608         kvm_make_request(KVM_REQ_NMI, vcpu);
 609 }
 610 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
 611
 612 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 613 {
 614         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
 615 }
 616 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
 617
 618 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 619 {
 620         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
 621 }
 622 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
 623
 624 /*
 625  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
 626  * a #GP and return false.
 627  */
 628 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
 629 {
 630         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
 631                 return true;
 632         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
 633         return false;
 634 }
 635 EXPORT_SYMBOL_GPL(kvm_require_cpl);
 636
 637 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
 638 {
 639         if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 640                 return true;
 641
 642         kvm_queue_exception(vcpu, UD_VECTOR);
 643         return false;
 644 }
 645 EXPORT_SYMBOL_GPL(kvm_require_dr);
 646
 647 /*
 648  * This function will be used to read from the physical memory of the currently
 649  * running guest. The difference to kvm_vcpu_read_guest_page is that this function
 650  * can read from guest physical or from the guest's guest physical memory.
 651  */
 652 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 653                             gfn_t ngfn, void *data, int offset, int len,
 654                             u32 access)
 655 {
 656         struct x86_exception exception;
 657         gfn_t real_gfn;
 658         gpa_t ngpa;
 659
 660         ngpa     = gfn_to_gpa(ngfn);
 661         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
 662         if (real_gfn == UNMAPPED_GVA)
 663                 return -EFAULT;
 664
 665         real_gfn = gpa_to_gfn(real_gfn);
 666
 667         return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
 668 }
 669 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
 670
 671 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
 672                                void *data, int offset, int len, u32 access)
 673 {
 674         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
 675                                        data, offset, len, access);
 676 }
 677
 678 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
 679 {
 680         return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
 681                rsvd_bits(1, 2);
 682 }
 683
 684 /*
 685  * Load the pae pdptrs.  Return 1 if they are all valid, 0 otherwise.
 686  */
 687 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
 688 {
 689         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
 690         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
 691         int i;
 692         int ret;
 693         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
 694
 695         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
 696                                       offset * sizeof(u64), sizeof(pdpte),
 697                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
 698         if (ret < 0) {
 699                 ret = 0;
 700                 goto out;
 701         }
 702         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
 703                 if ((pdpte[i] & PT_PRESENT_MASK) &&
 704                     (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
 705                         ret = 0;
 706                         goto out;
 707                 }
 708         }
 709         ret = 1;
 710
 711         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
 712         __set_bit(VCPU_EXREG_PDPTR,
 713                   (unsigned long *)&vcpu->arch.regs_avail);
 714         __set_bit(VCPU_EXREG_PDPTR,
 715                   (unsigned long *)&vcpu->arch.regs_dirty);
 716 out:
 717
 718         return ret;
 719 }
 720 EXPORT_SYMBOL_GPL(load_pdptrs);
 721
 722 bool pdptrs_changed(struct kvm_vcpu *vcpu)
 723 {
 724         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
 725         bool changed = true;
 726         int offset;
 727         gfn_t gfn;
 728         int r;
 729
 730         if (!is_pae_paging(vcpu))
 731                 return false;
 732
 733         if (!test_bit(VCPU_EXREG_PDPTR,
 734                       (unsigned long *)&vcpu->arch.regs_avail))
 735                 return true;
 736
 737         gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
 738         offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
 739         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
 740                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
 741         if (r < 0)
 742                 goto out;
 743         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
 744 out:
 745
 746         return changed;
 747 }
 748 EXPORT_SYMBOL_GPL(pdptrs_changed);
 749
 750 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 751 {
 752         unsigned long old_cr0 = kvm_read_cr0(vcpu);
 753         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
 754
 755         cr0 |= X86_CR0_ET;
 756
 757 #ifdef CONFIG_X86_64
 758         if (cr0 & 0xffffffff00000000UL)
 759                 return 1;
 760 #endif
 761
 762         cr0 &= ~CR0_RESERVED_BITS;
 763
 764         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
 765                 return 1;
 766
 767         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
 768                 return 1;
 769
 770         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 771 #ifdef CONFIG_X86_64
 772                 if ((vcpu->arch.efer & EFER_LME)) {
 773                         int cs_db, cs_l;
 774
 775                         if (!is_pae(vcpu))
 776                                 return 1;
 777                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
 778                         if (cs_l)
 779                                 return 1;
 780                 } else
 781 #endif
 782                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 783                                                  kvm_read_cr3(vcpu)))
 784                         return 1;
 785         }
 786
 787         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
 788                 return 1;
 789
 790         kvm_x86_ops->set_cr0(vcpu, cr0);
 791
 792         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
 793                 kvm_clear_async_pf_completion_queue(vcpu);
 794                 kvm_async_pf_hash_reset(vcpu);
 795         }
 796
 797         if ((cr0 ^ old_cr0) & update_bits)
 798                 kvm_mmu_reset_context(vcpu);
 799
 800         if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
 801             kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
 802             !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
 803                 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
 804
 805         return 0;
 806 }
 807 EXPORT_SYMBOL_GPL(kvm_set_cr0);
 808
 809 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 810 {
 811         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
 812 }
 813 EXPORT_SYMBOL_GPL(kvm_lmsw);
 814
 815 void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
 816 {
 817         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
 818                         !vcpu->guest_xcr0_loaded) {
 819                 /* kvm_set_xcr() also depends on this */
 820                 if (vcpu->arch.xcr0 != host_xcr0)
 821                         xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
 822                 vcpu->guest_xcr0_loaded = 1;
 823         }
 824 }
 825 EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
 826
 827 void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
 828 {
 829         if (vcpu->guest_xcr0_loaded) {
 830                 if (vcpu->arch.xcr0 != host_xcr0)
 831                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
 832                 vcpu->guest_xcr0_loaded = 0;
 833         }
 834 }
 835 EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
 836
 837 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 838 {
 839         u64 xcr0 = xcr;
 840         u64 old_xcr0 = vcpu->arch.xcr0;
 841         u64 valid_bits;
 842
 843         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
 844         if (index != XCR_XFEATURE_ENABLED_MASK)
 845                 return 1;
 846         if (!(xcr0 & XFEATURE_MASK_FP))
 847                 return 1;
 848         if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
 849                 return 1;
 850
 851         /*
 852          * Do not allow the guest to set bits that we do not support
 853          * saving.  However, xcr0 bit 0 is always set, even if the
 854          * emulated CPU does not support XSAVE (see fx_init).
 855          */
 856         valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
 857         if (xcr0 & ~valid_bits)
 858                 return 1;
 859
 860         if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
 861             (!(xcr0 & XFEATURE_MASK_BNDCSR)))
 862                 return 1;
 863
 864         if (xcr0 & XFEATURE_MASK_AVX512) {
 865                 if (!(xcr0 & XFEATURE_MASK_YMM))
 866                         return 1;
 867                 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
 868                         return 1;
 869         }
 870         vcpu->arch.xcr0 = xcr0;
 871
 872         if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
 873                 kvm_update_cpuid(vcpu);
 874         return 0;
 875 }
 876
 877 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 878 {
 879         if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
 880             __kvm_set_xcr(vcpu, index, xcr)) {
 881                 kvm_inject_gp(vcpu, 0);
 882                 return 1;
 883         }
 884         return 0;
 885 }
 886 EXPORT_SYMBOL_GPL(kvm_set_xcr);
 887
 888 static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 889 {
 890         if (cr4 & CR4_RESERVED_BITS)
 891                 return -EINVAL;
 892
 893         if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
 894                 return -EINVAL;
 895
 896         if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
 897                 return -EINVAL;
 898
 899         if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
 900                 return -EINVAL;
 901
 902         if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
 903                 return -EINVAL;
 904
 905         if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
 906                 return -EINVAL;
 907
 908         if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
 909                 return -EINVAL;
 910
 911         if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
 912                 return -EINVAL;
 913
 914         return 0;
 915 }
 916
 917 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 918 {
 919         unsigned long old_cr4 = kvm_read_cr4(vcpu);
 920         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
 921                                    X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
 922
 923         if (kvm_valid_cr4(vcpu, cr4))
 924                 return 1;
 925
 926         if (is_long_mode(vcpu)) {
 927                 if (!(cr4 & X86_CR4_PAE))
 928                         return 1;
 929         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
 930                    && ((cr4 ^ old_cr4) & pdptr_bits)
 931                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 932                                    kvm_read_cr3(vcpu)))
 933                 return 1;
 934
 935         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
 936                 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
 937                         return 1;
 938
 939                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
 940                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
 941                         return 1;
 942         }
 943
 944         if (kvm_x86_ops->set_cr4(vcpu, cr4))
 945                 return 1;
 946
 947         if (((cr4 ^ old_cr4) & pdptr_bits) ||
 948             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
 949                 kvm_mmu_reset_context(vcpu);
 950
 951         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
 952                 kvm_update_cpuid(vcpu);
 953
 954         return 0;
 955 }
 956 EXPORT_SYMBOL_GPL(kvm_set_cr4);
 957
 958 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
 959 {
 960         bool skip_tlb_flush = false;
 961 #ifdef CONFIG_X86_64
 962         bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
 963
 964         if (pcid_enabled) {
 965                 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
 966                 cr3 &= ~X86_CR3_PCID_NOFLUSH;
 967         }
 968 #endif
 969
 970         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
 971                 if (!skip_tlb_flush) {
 972                         kvm_mmu_sync_roots(vcpu);
 973                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 974                 }
 975                 return 0;
 976         }
 977
 978         if (is_long_mode(vcpu) &&
 979             (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
 980                 return 1;
 981         else if (is_pae_paging(vcpu) &&
 982                  !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
 983                 return 1;
 984
 985         kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
 986         vcpu->arch.cr3 = cr3;
 987         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
 988
 989         return 0;
 990 }
 991 EXPORT_SYMBOL_GPL(kvm_set_cr3);
 992
 993 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
 994 {
 995         if (cr8 & CR8_RESERVED_BITS)
 996                 return 1;
 997         if (lapic_in_kernel(vcpu))
 998                 kvm_lapic_set_tpr(vcpu, cr8);
 999         else
1000                 vcpu->arch.cr8 = cr8;
1001         return 0;
1002 }
1003 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1004
1005 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1006 {
1007         if (lapic_in_kernel(vcpu))
1008                 return kvm_lapic_get_cr8(vcpu);
1009         else
1010                 return vcpu->arch.cr8;
1011 }
1012 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1013
1014 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1015 {
1016         int i;
1017
1018         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1019                 for (i = 0; i < KVM_NR_DB_REGS; i++)
1020                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1021                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1022         }
1023 }
1024
1025 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1026 {
1027         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1028                 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1029 }
1030
1031 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1032 {
1033         unsigned long dr7;
1034
1035         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1036                 dr7 = vcpu->arch.guest_debug_dr7;
1037         else
1038                 dr7 = vcpu->arch.dr7;
1039         kvm_x86_ops->set_dr7(vcpu, dr7);
1040         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1041         if (dr7 & DR7_BP_EN_MASK)
1042                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1043 }
1044
1045 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1046 {
1047         u64 fixed = DR6_FIXED_1;
1048
1049         if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1050                 fixed |= DR6_RTM;
1051         return fixed;
1052 }
1053
1054 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1055 {
1056         switch (dr) {
1057         case 0 ... 3:
1058                 vcpu->arch.db[dr] = val;
1059                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1060                         vcpu->arch.eff_db[dr] = val;
1061                 break;
1062         case 4:
1063                 /* fall through */
1064         case 6:
1065                 if (val & 0xffffffff00000000ULL)
1066                         return -1; /* #GP */
1067                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1068                 kvm_update_dr6(vcpu);
1069                 break;
1070         case 5:
1071                 /* fall through */
1072         default: /* 7 */
1073                 if (val & 0xffffffff00000000ULL)
1074                         return -1; /* #GP */
1075                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1076                 kvm_update_dr7(vcpu);
1077                 break;
1078         }
1079
1080         return 0;
1081 }
1082
1083 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1084 {
1085         if (__kvm_set_dr(vcpu, dr, val)) {
1086                 kvm_inject_gp(vcpu, 0);
1087                 return 1;
1088         }
1089         return 0;
1090 }
1091 EXPORT_SYMBOL_GPL(kvm_set_dr);
1092
1093 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1094 {
1095         switch (dr) {
1096         case 0 ... 3:
1097                 *val = vcpu->arch.db[dr];
1098                 break;
1099         case 4:
1100                 /* fall through */
1101         case 6:
1102                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1103                         *val = vcpu->arch.dr6;
1104                 else
1105                         *val = kvm_x86_ops->get_dr6(vcpu);
1106                 break;
1107         case 5:
1108                 /* fall through */
1109         default: /* 7 */
1110                 *val = vcpu->arch.dr7;
1111                 break;
1112         }
1113         return 0;
1114 }
1115 EXPORT_SYMBOL_GPL(kvm_get_dr);
1116
1117 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1118 {
1119         u32 ecx = kvm_rcx_read(vcpu);
1120         u64 data;
1121         int err;
1122
1123         err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1124         if (err)
1125                 return err;
1126         kvm_rax_write(vcpu, (u32)data);
1127         kvm_rdx_write(vcpu, data >> 32);
1128         return err;
1129 }
1130 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1131
1132 /*
1133  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1134  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1135  *
1136  * This list is modified at module load time to reflect the
1137  * capabilities of the host cpu. This capabilities test skips MSRs that are
1138  * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1139  * may depend on host virtualization features rather than host cpu features.
1140  */
1141
1142 static u32 msrs_to_save[] = {
1143         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1144         MSR_STAR,
1145 #ifdef CONFIG_X86_64
1146         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1147 #endif
1148         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1149         MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1150         MSR_IA32_SPEC_CTRL,
1151         MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1152         MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1153         MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1154         MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1155         MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1156         MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1157         MSR_IA32_UMWAIT_CONTROL,
1158
1159         MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1160         MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1161         MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1162         MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1163         MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1164         MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1165         MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1166         MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1167         MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1168         MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1169         MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1170         MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1171         MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1172         MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1173         MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1174         MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1175         MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1176         MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1177         MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1178         MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1179         MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1180         MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1181 };
1182
1183 static unsigned num_msrs_to_save;
1184
1185 static u32 emulated_msrs[] = {
1186         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1187         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1188         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1189         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1190         HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1191         HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1192         HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1193         HV_X64_MSR_RESET,
1194         HV_X64_MSR_VP_INDEX,
1195         HV_X64_MSR_VP_RUNTIME,
1196         HV_X64_MSR_SCONTROL,
1197         HV_X64_MSR_STIMER0_CONFIG,
1198         HV_X64_MSR_VP_ASSIST_PAGE,
1199         HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1200         HV_X64_MSR_TSC_EMULATION_STATUS,
1201
1202         MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1203         MSR_KVM_PV_EOI_EN,
1204
1205         MSR_IA32_TSC_ADJUST,
1206         MSR_IA32_TSCDEADLINE,
1207         MSR_IA32_ARCH_CAPABILITIES,
1208         MSR_IA32_MISC_ENABLE,
1209         MSR_IA32_MCG_STATUS,
1210         MSR_IA32_MCG_CTL,
1211         MSR_IA32_MCG_EXT_CTL,
1212         MSR_IA32_SMBASE,
1213         MSR_SMI_COUNT,
1214         MSR_PLATFORM_INFO,
1215         MSR_MISC_FEATURES_ENABLES,
1216         MSR_AMD64_VIRT_SPEC_CTRL,
1217         MSR_IA32_POWER_CTL,
1218
1219         /*
1220          * The following list leaves out MSRs whose values are determined
1221          * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1222          * We always support the "true" VMX control MSRs, even if the host
1223          * processor does not, so I am putting these registers here rather
1224          * than in msrs_to_save.
1225          */
1226         MSR_IA32_VMX_BASIC,
1227         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1228         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1229         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1230         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1231         MSR_IA32_VMX_MISC,
1232         MSR_IA32_VMX_CR0_FIXED0,
1233         MSR_IA32_VMX_CR4_FIXED0,
1234         MSR_IA32_VMX_VMCS_ENUM,
1235         MSR_IA32_VMX_PROCBASED_CTLS2,
1236         MSR_IA32_VMX_EPT_VPID_CAP,
1237         MSR_IA32_VMX_VMFUNC,
1238
1239         MSR_K7_HWCR,
1240         MSR_KVM_POLL_CONTROL,
1241 };
1242
1243 static unsigned num_emulated_msrs;
1244
1245 /*
1246  * List of msr numbers which are used to expose MSR-based features that
1247  * can be used by a hypervisor to validate requested CPU features.
1248  */
1249 static u32 msr_based_features[] = {
1250         MSR_IA32_VMX_BASIC,
1251         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1252         MSR_IA32_VMX_PINBASED_CTLS,
1253         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1254         MSR_IA32_VMX_PROCBASED_CTLS,
1255         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1256         MSR_IA32_VMX_EXIT_CTLS,
1257         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1258         MSR_IA32_VMX_ENTRY_CTLS,
1259         MSR_IA32_VMX_MISC,
1260         MSR_IA32_VMX_CR0_FIXED0,
1261         MSR_IA32_VMX_CR0_FIXED1,
1262         MSR_IA32_VMX_CR4_FIXED0,
1263         MSR_IA32_VMX_CR4_FIXED1,
1264         MSR_IA32_VMX_VMCS_ENUM,
1265         MSR_IA32_VMX_PROCBASED_CTLS2,
1266         MSR_IA32_VMX_EPT_VPID_CAP,
1267         MSR_IA32_VMX_VMFUNC,
1268
1269         MSR_F10H_DECFG,
1270         MSR_IA32_UCODE_REV,
1271         MSR_IA32_ARCH_CAPABILITIES,
1272 };
1273
1274 static unsigned int num_msr_based_features;
1275
1276 static u64 kvm_get_arch_capabilities(void)
1277 {
1278         u64 data = 0;
1279
1280         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1281                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1282
1283         /*
1284          * If we're doing cache flushes (either "always" or "cond")
1285          * we will do one whenever the guest does a vmlaunch/vmresume.
1286          * If an outer hypervisor is doing the cache flush for us
1287          * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1288          * capability to the guest too, and if EPT is disabled we're not
1289          * vulnerable.  Overall, only VMENTER_L1D_FLUSH_NEVER will
1290          * require a nested hypervisor to do a flush of its own.
1291          */
1292         if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1293                 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1294
1295         if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1296                 data |= ARCH_CAP_RDCL_NO;
1297         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1298                 data |= ARCH_CAP_SSB_NO;
1299         if (!boot_cpu_has_bug(X86_BUG_MDS))
1300                 data |= ARCH_CAP_MDS_NO;
1301
1302         return data;
1303 }
1304
1305 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1306 {
1307         switch (msr->index) {
1308         case MSR_IA32_ARCH_CAPABILITIES:
1309                 msr->data = kvm_get_arch_capabilities();
1310                 break;
1311         case MSR_IA32_UCODE_REV:
1312                 rdmsrl_safe(msr->index, &msr->data);
1313                 break;
1314         default:
1315                 if (kvm_x86_ops->get_msr_feature(msr))
1316                         return 1;
1317         }
1318         return 0;
1319 }
1320
1321 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1322 {
1323         struct kvm_msr_entry msr;
1324         int r;
1325
1326         msr.index = index;
1327         r = kvm_get_msr_feature(&msr);
1328         if (r)
1329                 return r;
1330
1331         *data = msr.data;
1332
1333         return 0;
1334 }
1335
1336 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1337 {
1338         if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1339                 return false;
1340
1341         if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1342                 return false;
1343
1344         if (efer & (EFER_LME | EFER_LMA) &&
1345             !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1346                 return false;
1347
1348         if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1349                 return false;
1350
1351         return true;
1352
1353 }
1354 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1355 {
1356         if (efer & efer_reserved_bits)
1357                 return false;
1358
1359         return __kvm_valid_efer(vcpu, efer);
1360 }
1361 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1362
1363 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1364 {
1365         u64 old_efer = vcpu->arch.efer;
1366         u64 efer = msr_info->data;
1367
1368         if (efer & efer_reserved_bits)
1369                 return 1;
1370
1371         if (!msr_info->host_initiated) {
1372                 if (!__kvm_valid_efer(vcpu, efer))
1373                         return 1;
1374
1375                 if (is_paging(vcpu) &&
1376                     (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1377                         return 1;
1378         }
1379
1380         efer &= ~EFER_LMA;
1381         efer |= vcpu->arch.efer & EFER_LMA;
1382
1383         kvm_x86_ops->set_efer(vcpu, efer);
1384
1385         /* Update reserved bits */
1386         if ((efer ^ old_efer) & EFER_NX)
1387                 kvm_mmu_reset_context(vcpu);
1388
1389         return 0;
1390 }
1391
1392 void kvm_enable_efer_bits(u64 mask)
1393 {
1394        efer_reserved_bits &= ~mask;
1395 }
1396 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1397
1398 /*
1399  * Write @data into the MSR specified by @index.  Select MSR specific fault
1400  * checks are bypassed if @host_initiated is %true.
1401  * Returns 0 on success, non-0 otherwise.
1402  * Assumes vcpu_load() was already called.
1403  */
1404 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1405                          bool host_initiated)
1406 {
1407         struct msr_data msr;
1408
1409         switch (index) {
1410         case MSR_FS_BASE:
1411         case MSR_GS_BASE:
1412         case MSR_KERNEL_GS_BASE:
1413         case MSR_CSTAR:
1414         case MSR_LSTAR:
1415                 if (is_noncanonical_address(data, vcpu))
1416                         return 1;
1417                 break;
1418         case MSR_IA32_SYSENTER_EIP:
1419         case MSR_IA32_SYSENTER_ESP:
1420                 /*
1421                  * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1422                  * non-canonical address is written on Intel but not on
1423                  * AMD (which ignores the top 32-bits, because it does
1424                  * not implement 64-bit SYSENTER).
1425                  *
1426                  * 64-bit code should hence be able to write a non-canonical
1427                  * value on AMD.  Making the address canonical ensures that
1428                  * vmentry does not fail on Intel after writing a non-canonical
1429                  * value, and that something deterministic happens if the guest
1430                  * invokes 64-bit SYSENTER.
1431                  */
1432                 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1433         }
1434
1435         msr.data = data;
1436         msr.index = index;
1437         msr.host_initiated = host_initiated;
1438
1439         return kvm_x86_ops->set_msr(vcpu, &msr);
1440 }
1441
1442 /*
1443  * Read the MSR specified by @index into @data.  Select MSR specific fault
1444  * checks are bypassed if @host_initiated is %true.
1445  * Returns 0 on success, non-0 otherwise.
1446  * Assumes vcpu_load() was already called.
1447  */
1448 static int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1449                          bool host_initiated)
1450 {
1451         struct msr_data msr;
1452         int ret;
1453
1454         msr.index = index;
1455         msr.host_initiated = host_initiated;
1456
1457         ret = kvm_x86_ops->get_msr(vcpu, &msr);
1458         if (!ret)
1459                 *data = msr.data;
1460         return ret;
1461 }
1462
1463 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1464 {
1465         return __kvm_get_msr(vcpu, index, data, false);
1466 }
1467 EXPORT_SYMBOL_GPL(kvm_get_msr);
1468
1469 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1470 {
1471         return __kvm_set_msr(vcpu, index, data, false);
1472 }
1473 EXPORT_SYMBOL_GPL(kvm_set_msr);
1474
1475 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1476 {
1477         u32 ecx = kvm_rcx_read(vcpu);
1478         u64 data;
1479
1480         if (kvm_get_msr(vcpu, ecx, &data)) {
1481                 trace_kvm_msr_read_ex(ecx);
1482                 kvm_inject_gp(vcpu, 0);
1483                 return 1;
1484         }
1485
1486         trace_kvm_msr_read(ecx, data);
1487
1488         kvm_rax_write(vcpu, data & -1u);
1489         kvm_rdx_write(vcpu, (data >> 32) & -1u);
1490         return kvm_skip_emulated_instruction(vcpu);
1491 }
1492 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1493
1494 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1495 {
1496         u32 ecx = kvm_rcx_read(vcpu);
1497         u64 data = kvm_read_edx_eax(vcpu);
1498
1499         if (kvm_set_msr(vcpu, ecx, data)) {
1500                 trace_kvm_msr_write_ex(ecx, data);
1501                 kvm_inject_gp(vcpu, 0);
1502                 return 1;
1503         }
1504
1505         trace_kvm_msr_write(ecx, data);
1506         return kvm_skip_emulated_instruction(vcpu);
1507 }
1508 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1509
1510 /*
1511  * Adapt set_msr() to msr_io()'s calling convention
1512  */
1513 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1514 {
1515         return __kvm_get_msr(vcpu, index, data, true);
1516 }
1517
1518 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1519 {
1520         return __kvm_set_msr(vcpu, index, *data, true);
1521 }
1522
1523 #ifdef CONFIG_X86_64
1524 struct pvclock_gtod_data {
1525         seqcount_t      seq;
1526
1527         struct { /* extract of a clocksource struct */
1528                 int vclock_mode;
1529                 u64     cycle_last;
1530                 u64     mask;
1531                 u32     mult;
1532                 u32     shift;
1533         } clock;
1534
1535         u64             boot_ns;
1536         u64             nsec_base;
1537         u64             wall_time_sec;
1538 };
1539
1540 static struct pvclock_gtod_data pvclock_gtod_data;
1541
1542 static void update_pvclock_gtod(struct timekeeper *tk)
1543 {
1544         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1545         u64 boot_ns;
1546
1547         boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1548
1549         write_seqcount_begin(&vdata->seq);
1550
1551         /* copy pvclock gtod data */
1552         vdata->clock.vclock_mode        = tk->tkr_mono.clock->archdata.vclock_mode;
1553         vdata->clock.cycle_last         = tk->tkr_mono.cycle_last;
1554         vdata->clock.mask               = tk->tkr_mono.mask;
1555         vdata->clock.mult               = tk->tkr_mono.mult;
1556         vdata->clock.shift              = tk->tkr_mono.shift;
1557
1558         vdata->boot_ns                  = boot_ns;
1559         vdata->nsec_base                = tk->tkr_mono.xtime_nsec;
1560
1561         vdata->wall_time_sec            = tk->xtime_sec;
1562
1563         write_seqcount_end(&vdata->seq);
1564 }
1565 #endif
1566
1567 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1568 {
1569         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1570         kvm_vcpu_kick(vcpu);
1571 }
1572
1573 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1574 {
1575         int version;
1576         int r;
1577         struct pvclock_wall_clock wc;
1578         struct timespec64 boot;
1579
1580         if (!wall_clock)
1581                 return;
1582
1583         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1584         if (r)
1585                 return;
1586
1587         if (version & 1)
1588                 ++version;  /* first time write, random junk */
1589
1590         ++version;
1591
1592         if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1593                 return;
1594
1595         /*
1596          * The guest calculates current wall clock time by adding
1597          * system time (updated by kvm_guest_time_update below) to the
1598          * wall clock specified here.  guest system time equals host
1599          * system time for us, thus we must fill in host boot time here.
1600          */
1601         getboottime64(&boot);
1602
1603         if (kvm->arch.kvmclock_offset) {
1604                 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1605                 boot = timespec64_sub(boot, ts);
1606         }
1607         wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1608         wc.nsec = boot.tv_nsec;
1609         wc.version = version;
1610
1611         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1612
1613         version++;
1614         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1615 }
1616
1617 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1618 {
1619         do_shl32_div32(dividend, divisor);
1620         return dividend;
1621 }
1622
1623 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1624                                s8 *pshift, u32 *pmultiplier)
1625 {
1626         uint64_t scaled64;
1627         int32_t  shift = 0;
1628         uint64_t tps64;
1629         uint32_t tps32;
1630
1631         tps64 = base_hz;
1632         scaled64 = scaled_hz;
1633         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1634                 tps64 >>= 1;
1635                 shift--;
1636         }
1637
1638         tps32 = (uint32_t)tps64;
1639         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1640                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1641                         scaled64 >>= 1;
1642                 else
1643                         tps32 <<= 1;
1644                 shift++;
1645         }
1646
1647         *pshift = shift;
1648         *pmultiplier = div_frac(scaled64, tps32);
1649 }
1650
1651 #ifdef CONFIG_X86_64
1652 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1653 #endif
1654
1655 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1656 static unsigned long max_tsc_khz;
1657
1658 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1659 {
1660         u64 v = (u64)khz * (1000000 + ppm);
1661         do_div(v, 1000000);
1662         return v;
1663 }
1664
1665 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1666 {
1667         u64 ratio;
1668
1669         /* Guest TSC same frequency as host TSC? */
1670         if (!scale) {
1671                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1672                 return 0;
1673         }
1674
1675         /* TSC scaling supported? */
1676         if (!kvm_has_tsc_control) {
1677                 if (user_tsc_khz > tsc_khz) {
1678                         vcpu->arch.tsc_catchup = 1;
1679                         vcpu->arch.tsc_always_catchup = 1;
1680                         return 0;
1681                 } else {
1682                         pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1683                         return -1;
1684                 }
1685         }
1686
1687         /* TSC scaling required  - calculate ratio */
1688         ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1689                                 user_tsc_khz, tsc_khz);
1690
1691         if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1692                 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1693                                     user_tsc_khz);
1694                 return -1;
1695         }
1696
1697         vcpu->arch.tsc_scaling_ratio = ratio;
1698         return 0;
1699 }
1700
1701 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1702 {
1703         u32 thresh_lo, thresh_hi;
1704         int use_scaling = 0;
1705
1706         /* tsc_khz can be zero if TSC calibration fails */
1707         if (user_tsc_khz == 0) {
1708                 /* set tsc_scaling_ratio to a safe value */
1709                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1710                 return -1;
1711         }
1712
1713         /* Compute a scale to convert nanoseconds in TSC cycles */
1714         kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1715                            &vcpu->arch.virtual_tsc_shift,
1716                            &vcpu->arch.virtual_tsc_mult);
1717         vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1718
1719         /*
1720          * Compute the variation in TSC rate which is acceptable
1721          * within the range of tolerance and decide if the
1722          * rate being applied is within that bounds of the hardware
1723          * rate.  If so, no scaling or compensation need be done.
1724          */
1725         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1726         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1727         if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1728                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1729                 use_scaling = 1;
1730         }
1731         return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1732 }
1733
1734 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1735 {
1736         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1737                                       vcpu->arch.virtual_tsc_mult,
1738                                       vcpu->arch.virtual_tsc_shift);
1739         tsc += vcpu->arch.this_tsc_write;
1740         return tsc;
1741 }
1742
1743 static inline int gtod_is_based_on_tsc(int mode)
1744 {
1745         return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1746 }
1747
1748 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1749 {
1750 #ifdef CONFIG_X86_64
1751         bool vcpus_matched;
1752         struct kvm_arch *ka = &vcpu->kvm->arch;
1753         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1754
1755         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1756                          atomic_read(&vcpu->kvm->online_vcpus));
1757
1758         /*
1759          * Once the masterclock is enabled, always perform request in
1760          * order to update it.
1761          *
1762          * In order to enable masterclock, the host clocksource must be TSC
1763          * and the vcpus need to have matched TSCs.  When that happens,
1764          * perform request to enable masterclock.
1765          */
1766         if (ka->use_master_clock ||
1767             (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1768                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1769
1770         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1771                             atomic_read(&vcpu->kvm->online_vcpus),
1772                             ka->use_master_clock, gtod->clock.vclock_mode);
1773 #endif
1774 }
1775
1776 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1777 {
1778         u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1779         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1780 }
1781
1782 /*
1783  * Multiply tsc by a fixed point number represented by ratio.
1784  *
1785  * The most significant 64-N bits (mult) of ratio represent the
1786  * integral part of the fixed point number; the remaining N bits
1787  * (frac) represent the fractional part, ie. ratio represents a fixed
1788  * point number (mult + frac * 2^(-N)).
1789  *
1790  * N equals to kvm_tsc_scaling_ratio_frac_bits.
1791  */
1792 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1793 {
1794         return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1795 }
1796
1797 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1798 {
1799         u64 _tsc = tsc;
1800         u64 ratio = vcpu->arch.tsc_scaling_ratio;
1801
1802         if (ratio != kvm_default_tsc_scaling_ratio)
1803                 _tsc = __scale_tsc(ratio, tsc);
1804
1805         return _tsc;
1806 }
1807 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1808
1809 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1810 {
1811         u64 tsc;
1812
1813         tsc = kvm_scale_tsc(vcpu, rdtsc());
1814
1815         return target_tsc - tsc;
1816 }
1817
1818 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1819 {
1820         u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1821
1822         return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1823 }
1824 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1825
1826 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1827 {
1828         vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1829 }
1830
1831 static inline bool kvm_check_tsc_unstable(void)
1832 {
1833 #ifdef CONFIG_X86_64
1834         /*
1835          * TSC is marked unstable when we're running on Hyper-V,
1836          * 'TSC page' clocksource is good.
1837          */
1838         if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1839                 return false;
1840 #endif
1841         return check_tsc_unstable();
1842 }
1843
1844 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1845 {
1846         struct kvm *kvm = vcpu->kvm;
1847         u64 offset, ns, elapsed;
1848         unsigned long flags;
1849         bool matched;
1850         bool already_matched;
1851         u64 data = msr->data;
1852         bool synchronizing = false;
1853
1854         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1855         offset = kvm_compute_tsc_offset(vcpu, data);
1856         ns = ktime_get_boottime_ns();
1857         elapsed = ns - kvm->arch.last_tsc_nsec;
1858
1859         if (vcpu->arch.virtual_tsc_khz) {
1860                 if (data == 0 && msr->host_initiated) {
1861                         /*
1862                          * detection of vcpu initialization -- need to sync
1863                          * with other vCPUs. This particularly helps to keep
1864                          * kvm_clock stable after CPU hotplug
1865                          */
1866                         synchronizing = true;
1867                 } else {
1868                         u64 tsc_exp = kvm->arch.last_tsc_write +
1869                                                 nsec_to_cycles(vcpu, elapsed);
1870                         u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1871                         /*
1872                          * Special case: TSC write with a small delta (1 second)
1873                          * of virtual cycle time against real time is
1874                          * interpreted as an attempt to synchronize the CPU.
1875                          */
1876                         synchronizing = data < tsc_exp + tsc_hz &&
1877                                         data + tsc_hz > tsc_exp;
1878                 }
1879         }
1880
1881         /*
1882          * For a reliable TSC, we can match TSC offsets, and for an unstable
1883          * TSC, we add elapsed time in this computation.  We could let the
1884          * compensation code attempt to catch up if we fall behind, but
1885          * it's better to try to match offsets from the beginning.
1886          */
1887         if (synchronizing &&
1888             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1889                 if (!kvm_check_tsc_unstable()) {
1890                         offset = kvm->arch.cur_tsc_offset;
1891                 } else {
1892                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1893                         data += delta;
1894                         offset = kvm_compute_tsc_offset(vcpu, data);
1895                 }
1896                 matched = true;
1897                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1898         } else {
1899                 /*
1900                  * We split periods of matched TSC writes into generations.
1901                  * For each generation, we track the original measured
1902                  * nanosecond time, offset, and write, so if TSCs are in
1903                  * sync, we can match exact offset, and if not, we can match
1904                  * exact software computation in compute_guest_tsc()
1905                  *
1906                  * These values are tracked in kvm->arch.cur_xxx variables.
1907                  */
1908                 kvm->arch.cur_tsc_generation++;
1909                 kvm->arch.cur_tsc_nsec = ns;
1910                 kvm->arch.cur_tsc_write = data;
1911                 kvm->arch.cur_tsc_offset = offset;
1912                 matched = false;
1913         }
1914
1915         /*
1916          * We also track th most recent recorded KHZ, write and time to
1917          * allow the matching interval to be extended at each write.
1918          */
1919         kvm->arch.last_tsc_nsec = ns;
1920         kvm->arch.last_tsc_write = data;
1921         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1922
1923         vcpu->arch.last_guest_tsc = data;
1924
1925         /* Keep track of which generation this VCPU has synchronized to */
1926         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1927         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1928         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1929
1930         if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1931                 update_ia32_tsc_adjust_msr(vcpu, offset);
1932
1933         kvm_vcpu_write_tsc_offset(vcpu, offset);
1934         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1935
1936         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1937         if (!matched) {
1938                 kvm->arch.nr_vcpus_matched_tsc = 0;
1939         } else if (!already_matched) {
1940                 kvm->arch.nr_vcpus_matched_tsc++;
1941         }
1942
1943         kvm_track_tsc_matching(vcpu);
1944         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1945 }
1946
1947 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1948
1949 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1950                                            s64 adjustment)
1951 {
1952         u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1953         kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
1954 }
1955
1956 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1957 {
1958         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1959                 WARN_ON(adjustment < 0);
1960         adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1961         adjust_tsc_offset_guest(vcpu, adjustment);
1962 }
1963
1964 #ifdef CONFIG_X86_64
1965
1966 static u64 read_tsc(void)
1967 {
1968         u64 ret = (u64)rdtsc_ordered();
1969         u64 last = pvclock_gtod_data.clock.cycle_last;
1970
1971         if (likely(ret >= last))
1972                 return ret;
1973
1974         /*
1975          * GCC likes to generate cmov here, but this branch is extremely
1976          * predictable (it's just a function of time and the likely is
1977          * very likely) and there's a data dependence, so force GCC
1978          * to generate a branch instead.  I don't barrier() because
1979          * we don't actually need a barrier, and if this function
1980          * ever gets inlined it will generate worse code.
1981          */
1982         asm volatile ("");
1983         return last;
1984 }
1985
1986 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
1987 {
1988         long v;
1989         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1990         u64 tsc_pg_val;
1991
1992         switch (gtod->clock.vclock_mode) {
1993         case VCLOCK_HVCLOCK:
1994                 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1995                                                   tsc_timestamp);
1996                 if (tsc_pg_val != U64_MAX) {
1997                         /* TSC page valid */
1998                         *mode = VCLOCK_HVCLOCK;
1999                         v = (tsc_pg_val - gtod->clock.cycle_last) &
2000                                 gtod->clock.mask;
2001                 } else {
2002                         /* TSC page invalid */
2003                         *mode = VCLOCK_NONE;
2004                 }
2005                 break;
2006         case VCLOCK_TSC:
2007                 *mode = VCLOCK_TSC;
2008                 *tsc_timestamp = read_tsc();
2009                 v = (*tsc_timestamp - gtod->clock.cycle_last) &
2010                         gtod->clock.mask;
2011                 break;
2012         default:
2013                 *mode = VCLOCK_NONE;
2014         }
2015
2016         if (*mode == VCLOCK_NONE)
2017                 *tsc_timestamp = v = 0;
2018
2019         return v * gtod->clock.mult;
2020 }
2021
2022 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
2023 {
2024         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2025         unsigned long seq;
2026         int mode;
2027         u64 ns;
2028
2029         do {
2030                 seq = read_seqcount_begin(&gtod->seq);
2031                 ns = gtod->nsec_base;
2032                 ns += vgettsc(tsc_timestamp, &mode);
2033                 ns >>= gtod->clock.shift;
2034                 ns += gtod->boot_ns;
2035         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2036         *t = ns;
2037
2038         return mode;
2039 }
2040
2041 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2042 {
2043         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2044         unsigned long seq;
2045         int mode;
2046         u64 ns;
2047
2048         do {
2049                 seq = read_seqcount_begin(&gtod->seq);
2050                 ts->tv_sec = gtod->wall_time_sec;
2051                 ns = gtod->nsec_base;
2052                 ns += vgettsc(tsc_timestamp, &mode);
2053                 ns >>= gtod->clock.shift;
2054         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2055
2056         ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2057         ts->tv_nsec = ns;
2058
2059         return mode;
2060 }
2061
2062 /* returns true if host is using TSC based clocksource */
2063 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2064 {
2065         /* checked again under seqlock below */
2066         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2067                 return false;
2068
2069         return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
2070                                                       tsc_timestamp));
2071 }
2072
2073 /* returns true if host is using TSC based clocksource */
2074 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2075                                            u64 *tsc_timestamp)
2076 {
2077         /* checked again under seqlock below */
2078         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2079                 return false;
2080
2081         return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2082 }
2083 #endif
2084
2085 /*
2086  *
2087  * Assuming a stable TSC across physical CPUS, and a stable TSC
2088  * across virtual CPUs, the following condition is possible.
2089  * Each numbered line represents an event visible to both
2090  * CPUs at the next numbered event.
2091  *
2092  * "timespecX" represents host monotonic time. "tscX" represents
2093  * RDTSC value.
2094  *
2095  *              VCPU0 on CPU0           |       VCPU1 on CPU1
2096  *
2097  * 1.  read timespec0,tsc0
2098  * 2.                                   | timespec1 = timespec0 + N
2099  *                                      | tsc1 = tsc0 + M
2100  * 3. transition to guest               | transition to guest
2101  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2102  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
2103  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2104  *
2105  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2106  *
2107  *      - ret0 < ret1
2108  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2109  *              ...
2110  *      - 0 < N - M => M < N
2111  *
2112  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2113  * always the case (the difference between two distinct xtime instances
2114  * might be smaller then the difference between corresponding TSC reads,
2115  * when updating guest vcpus pvclock areas).
2116  *
2117  * To avoid that problem, do not allow visibility of distinct
2118  * system_timestamp/tsc_timestamp values simultaneously: use a master
2119  * copy of host monotonic time values. Update that master copy
2120  * in lockstep.
2121  *
2122  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2123  *
2124  */
2125
2126 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2127 {
2128 #ifdef CONFIG_X86_64
2129         struct kvm_arch *ka = &kvm->arch;
2130         int vclock_mode;
2131         bool host_tsc_clocksource, vcpus_matched;
2132
2133         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2134                         atomic_read(&kvm->online_vcpus));
2135
2136         /*
2137          * If the host uses TSC clock, then passthrough TSC as stable
2138          * to the guest.
2139          */
2140         host_tsc_clocksource = kvm_get_time_and_clockread(
2141                                         &ka->master_kernel_ns,
2142                                         &ka->master_cycle_now);
2143
2144         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2145                                 && !ka->backwards_tsc_observed
2146                                 && !ka->boot_vcpu_runs_old_kvmclock;
2147
2148         if (ka->use_master_clock)
2149                 atomic_set(&kvm_guest_has_master_clock, 1);
2150
2151         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2152         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2153                                         vcpus_matched);
2154 #endif
2155 }
2156
2157 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2158 {
2159         kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2160 }
2161
2162 static void kvm_gen_update_masterclock(struct kvm *kvm)
2163 {
2164 #ifdef CONFIG_X86_64
2165         int i;
2166         struct kvm_vcpu *vcpu;
2167         struct kvm_arch *ka = &kvm->arch;
2168
2169         spin_lock(&ka->pvclock_gtod_sync_lock);
2170         kvm_make_mclock_inprogress_request(kvm);
2171         /* no guest entries from this point */
2172         pvclock_update_vm_gtod_copy(kvm);
2173
2174         kvm_for_each_vcpu(i, vcpu, kvm)
2175                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2176
2177         /* guest entries allowed */
2178         kvm_for_each_vcpu(i, vcpu, kvm)
2179                 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2180
2181         spin_unlock(&ka->pvclock_gtod_sync_lock);
2182 #endif
2183 }
2184
2185 u64 get_kvmclock_ns(struct kvm *kvm)
2186 {
2187         struct kvm_arch *ka = &kvm->arch;
2188         struct pvclock_vcpu_time_info hv_clock;
2189         u64 ret;
2190
2191         spin_lock(&ka->pvclock_gtod_sync_lock);
2192         if (!ka->use_master_clock) {
2193                 spin_unlock(&ka->pvclock_gtod_sync_lock);
2194                 return ktime_get_boottime_ns() + ka->kvmclock_offset;
2195         }
2196
2197         hv_clock.tsc_timestamp = ka->master_cycle_now;
2198         hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2199         spin_unlock(&ka->pvclock_gtod_sync_lock);
2200
2201         /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2202         get_cpu();
2203
2204         if (__this_cpu_read(cpu_tsc_khz)) {
2205                 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2206                                    &hv_clock.tsc_shift,
2207                                    &hv_clock.tsc_to_system_mul);
2208                 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2209         } else
2210                 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
2211
2212         put_cpu();
2213
2214         return ret;
2215 }
2216
2217 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2218 {
2219         struct kvm_vcpu_arch *vcpu = &v->arch;
2220         struct pvclock_vcpu_time_info guest_hv_clock;
2221
2222         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2223                 &guest_hv_clock, sizeof(guest_hv_clock))))
2224                 return;
2225
2226         /* This VCPU is paused, but it's legal for a guest to read another
2227          * VCPU's kvmclock, so we really have to follow the specification where
2228          * it says that version is odd if data is being modified, and even after
2229          * it is consistent.
2230          *
2231          * Version field updates must be kept separate.  This is because
2232          * kvm_write_guest_cached might use a "rep movs" instruction, and
2233          * writes within a string instruction are weakly ordered.  So there
2234          * are three writes overall.
2235          *
2236          * As a small optimization, only write the version field in the first
2237          * and third write.  The vcpu->pv_time cache is still valid, because the
2238          * version field is the first in the struct.
2239          */
2240         BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2241
2242         if (guest_hv_clock.version & 1)
2243                 ++guest_hv_clock.version;  /* first time write, random junk */
2244
2245         vcpu->hv_clock.version = guest_hv_clock.version + 1;
2246         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2247                                 &vcpu->hv_clock,
2248                                 sizeof(vcpu->hv_clock.version));
2249
2250         smp_wmb();
2251
2252         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2253         vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2254
2255         if (vcpu->pvclock_set_guest_stopped_request) {
2256                 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2257                 vcpu->pvclock_set_guest_stopped_request = false;
2258         }
2259
2260         trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2261
2262         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2263                                 &vcpu->hv_clock,
2264                                 sizeof(vcpu->hv_clock));
2265
2266         smp_wmb();
2267
2268         vcpu->hv_clock.version++;
2269         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2270                                 &vcpu->hv_clock,
2271                                 sizeof(vcpu->hv_clock.version));
2272 }
2273
2274 static int kvm_guest_time_update(struct kvm_vcpu *v)
2275 {
2276         unsigned long flags, tgt_tsc_khz;
2277         struct kvm_vcpu_arch *vcpu = &v->arch;
2278         struct kvm_arch *ka = &v->kvm->arch;
2279         s64 kernel_ns;
2280         u64 tsc_timestamp, host_tsc;
2281         u8 pvclock_flags;
2282         bool use_master_clock;
2283
2284         kernel_ns = 0;
2285         host_tsc = 0;
2286
2287         /*
2288          * If the host uses TSC clock, then passthrough TSC as stable
2289          * to the guest.
2290          */
2291         spin_lock(&ka->pvclock_gtod_sync_lock);
2292         use_master_clock = ka->use_master_clock;
2293         if (use_master_clock) {
2294                 host_tsc = ka->master_cycle_now;
2295                 kernel_ns = ka->master_kernel_ns;
2296         }
2297         spin_unlock(&ka->pvclock_gtod_sync_lock);
2298
2299         /* Keep irq disabled to prevent changes to the clock */
2300         local_irq_save(flags);
2301         tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2302         if (unlikely(tgt_tsc_khz == 0)) {
2303                 local_irq_restore(flags);
2304                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2305                 return 1;
2306         }
2307         if (!use_master_clock) {
2308                 host_tsc = rdtsc();
2309                 kernel_ns = ktime_get_boottime_ns();
2310         }
2311
2312         tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2313
2314         /*
2315          * We may have to catch up the TSC to match elapsed wall clock
2316          * time for two reasons, even if kvmclock is used.
2317          *   1) CPU could have been running below the maximum TSC rate
2318          *   2) Broken TSC compensation resets the base at each VCPU
2319          *      entry to avoid unknown leaps of TSC even when running
2320          *      again on the same CPU.  This may cause apparent elapsed
2321          *      time to disappear, and the guest to stand still or run
2322          *      very slowly.
2323          */
2324         if (vcpu->tsc_catchup) {
2325                 u64 tsc = compute_guest_tsc(v, kernel_ns);
2326                 if (tsc > tsc_timestamp) {
2327                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2328                         tsc_timestamp = tsc;
2329                 }
2330         }
2331
2332         local_irq_restore(flags);
2333
2334         /* With all the info we got, fill in the values */
2335
2336         if (kvm_has_tsc_control)
2337                 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2338
2339         if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2340                 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2341                                    &vcpu->hv_clock.tsc_shift,
2342                                    &vcpu->hv_clock.tsc_to_system_mul);
2343                 vcpu->hw_tsc_khz = tgt_tsc_khz;
2344         }
2345
2346         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2347         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2348         vcpu->last_guest_tsc = tsc_timestamp;
2349
2350         /* If the host uses TSC clocksource, then it is stable */
2351         pvclock_flags = 0;
2352         if (use_master_clock)
2353                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2354
2355         vcpu->hv_clock.flags = pvclock_flags;
2356
2357         if (vcpu->pv_time_enabled)
2358                 kvm_setup_pvclock_page(v);
2359         if (v == kvm_get_vcpu(v->kvm, 0))
2360                 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2361         return 0;
2362 }
2363
2364 /*
2365  * kvmclock updates which are isolated to a given vcpu, such as
2366  * vcpu->cpu migration, should not allow system_timestamp from
2367  * the rest of the vcpus to remain static. Otherwise ntp frequency
2368  * correction applies to one vcpu's system_timestamp but not
2369  * the others.
2370  *
2371  * So in those cases, request a kvmclock update for all vcpus.
2372  * We need to rate-limit these requests though, as they can
2373  * considerably slow guests that have a large number of vcpus.
2374  * The time for a remote vcpu to update its kvmclock is bound
2375  * by the delay we use to rate-limit the updates.
2376  */
2377
2378 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2379
2380 static void kvmclock_update_fn(struct work_struct *work)
2381 {
2382         int i;
2383         struct delayed_work *dwork = to_delayed_work(work);
2384         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2385                                            kvmclock_update_work);
2386         struct kvm *kvm = container_of(ka, struct kvm, arch);
2387         struct kvm_vcpu *vcpu;
2388
2389         kvm_for_each_vcpu(i, vcpu, kvm) {
2390                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2391                 kvm_vcpu_kick(vcpu);
2392         }
2393 }
2394
2395 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2396 {
2397         struct kvm *kvm = v->kvm;
2398
2399         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2400         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2401                                         KVMCLOCK_UPDATE_DELAY);
2402 }
2403
2404 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2405
2406 static void kvmclock_sync_fn(struct work_struct *work)
2407 {
2408         struct delayed_work *dwork = to_delayed_work(work);
2409         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2410                                            kvmclock_sync_work);
2411         struct kvm *kvm = container_of(ka, struct kvm, arch);
2412
2413         if (!kvmclock_periodic_sync)
2414                 return;
2415
2416         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2417         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2418                                         KVMCLOCK_SYNC_PERIOD);
2419 }
2420
2421 /*
2422  * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2423  */
2424 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2425 {
2426         /* McStatusWrEn enabled? */
2427         if (guest_cpuid_is_amd(vcpu))
2428                 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2429
2430         return false;
2431 }
2432
2433 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2434 {
2435         u64 mcg_cap = vcpu->arch.mcg_cap;
2436         unsigned bank_num = mcg_cap & 0xff;
2437         u32 msr = msr_info->index;
2438         u64 data = msr_info->data;
2439
2440         switch (msr) {
2441         case MSR_IA32_MCG_STATUS:
2442                 vcpu->arch.mcg_status = data;
2443                 break;
2444         case MSR_IA32_MCG_CTL:
2445                 if (!(mcg_cap & MCG_CTL_P) &&
2446                     (data || !msr_info->host_initiated))
2447                         return 1;
2448                 if (data != 0 && data != ~(u64)0)
2449                         return 1;
2450                 vcpu->arch.mcg_ctl = data;
2451                 break;
2452         default:
2453                 if (msr >= MSR_IA32_MC0_CTL &&
2454                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2455                         u32 offset = msr - MSR_IA32_MC0_CTL;
2456                         /* only 0 or all 1s can be written to IA32_MCi_CTL
2457                          * some Linux kernels though clear bit 10 in bank 4 to
2458                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2459                          * this to avoid an uncatched #GP in the guest
2460                          */
2461                         if ((offset & 0x3) == 0 &&
2462                             data != 0 && (data | (1 << 10)) != ~(u64)0)
2463                                 return -1;
2464
2465                         /* MCi_STATUS */
2466                         if (!msr_info->host_initiated &&
2467                             (offset & 0x3) == 1 && data != 0) {
2468                                 if (!can_set_mci_status(vcpu))
2469                                         return -1;
2470                         }
2471
2472                         vcpu->arch.mce_banks[offset] = data;
2473                         break;
2474                 }
2475                 return 1;
2476         }
2477         return 0;
2478 }
2479
2480 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2481 {
2482         struct kvm *kvm = vcpu->kvm;
2483         int lm = is_long_mode(vcpu);
2484         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2485                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2486         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2487                 : kvm->arch.xen_hvm_config.blob_size_32;
2488         u32 page_num = data & ~PAGE_MASK;
2489         u64 page_addr = data & PAGE_MASK;
2490         u8 *page;
2491         int r;
2492
2493         r = -E2BIG;
2494         if (page_num >= blob_size)
2495                 goto out;
2496         r = -ENOMEM;
2497         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2498         if (IS_ERR(page)) {
2499                 r = PTR_ERR(page);
2500                 goto out;
2501         }
2502         if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2503                 goto out_free;
2504         r = 0;
2505 out_free:
2506         kfree(page);
2507 out:
2508         return r;
2509 }
2510
2511 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2512 {
2513         gpa_t gpa = data & ~0x3f;
2514
2515         /* Bits 3:5 are reserved, Should be zero */
2516         if (data & 0x38)
2517                 return 1;
2518
2519         vcpu->arch.apf.msr_val = data;
2520
2521         if (!(data & KVM_ASYNC_PF_ENABLED)) {
2522                 kvm_clear_async_pf_completion_queue(vcpu);
2523                 kvm_async_pf_hash_reset(vcpu);
2524                 return 0;
2525         }
2526
2527         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2528                                         sizeof(u32)))
2529                 return 1;
2530
2531         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2532         vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2533         kvm_async_pf_wakeup_all(vcpu);
2534         return 0;
2535 }
2536
2537 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2538 {
2539         vcpu->arch.pv_time_enabled = false;
2540 }
2541
2542 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2543 {
2544         ++vcpu->stat.tlb_flush;
2545         kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2546 }
2547
2548 static void record_steal_time(struct kvm_vcpu *vcpu)
2549 {
2550         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2551                 return;
2552
2553         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2554                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2555                 return;
2556
2557         /*
2558          * Doing a TLB flush here, on the guest's behalf, can avoid
2559          * expensive IPIs.
2560          */
2561         trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2562                 vcpu->arch.st.steal.preempted & KVM_VCPU_FLUSH_TLB);
2563         if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2564                 kvm_vcpu_flush_tlb(vcpu, false);
2565
2566         if (vcpu->arch.st.steal.version & 1)
2567                 vcpu->arch.st.steal.version += 1;  /* first time write, random junk */
2568
2569         vcpu->arch.st.steal.version += 1;
2570
2571         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2572                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2573
2574         smp_wmb();
2575
2576         vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2577                 vcpu->arch.st.last_steal;
2578         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2579
2580         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2581                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2582
2583         smp_wmb();
2584
2585         vcpu->arch.st.steal.version += 1;
2586
2587         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2588                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2589 }
2590
2591 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2592 {
2593         bool pr = false;
2594         u32 msr = msr_info->index;
2595         u64 data = msr_info->data;
2596
2597         switch (msr) {
2598         case MSR_AMD64_NB_CFG:
2599         case MSR_IA32_UCODE_WRITE:
2600         case MSR_VM_HSAVE_PA:
2601         case MSR_AMD64_PATCH_LOADER:
2602         case MSR_AMD64_BU_CFG2:
2603         case MSR_AMD64_DC_CFG:
2604         case MSR_F15H_EX_CFG:
2605                 break;
2606
2607         case MSR_IA32_UCODE_REV:
2608                 if (msr_info->host_initiated)
2609                         vcpu->arch.microcode_version = data;
2610                 break;
2611         case MSR_IA32_ARCH_CAPABILITIES:
2612                 if (!msr_info->host_initiated)
2613                         return 1;
2614                 vcpu->arch.arch_capabilities = data;
2615                 break;
2616         case MSR_EFER:
2617                 return set_efer(vcpu, msr_info);
2618         case MSR_K7_HWCR:
2619                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2620                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2621                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2622
2623                 /* Handle McStatusWrEn */
2624                 if (data == BIT_ULL(18)) {
2625                         vcpu->arch.msr_hwcr = data;
2626                 } else if (data != 0) {
2627                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2628                                     data);
2629                         return 1;
2630                 }
2631                 break;
2632         case MSR_FAM10H_MMIO_CONF_BASE:
2633                 if (data != 0) {
2634                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2635                                     "0x%llx\n", data);
2636                         return 1;
2637                 }
2638                 break;
2639         case MSR_IA32_DEBUGCTLMSR:
2640                 if (!data) {
2641                         /* We support the non-activated case already */
2642                         break;
2643                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2644                         /* Values other than LBR and BTF are vendor-specific,
2645                            thus reserved and should throw a #GP */
2646                         return 1;
2647                 }
2648                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2649                             __func__, data);
2650                 break;
2651         case 0x200 ... 0x2ff:
2652                 return kvm_mtrr_set_msr(vcpu, msr, data);
2653         case MSR_IA32_APICBASE:
2654                 return kvm_set_apic_base(vcpu, msr_info);
2655         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2656                 return kvm_x2apic_msr_write(vcpu, msr, data);
2657         case MSR_IA32_TSCDEADLINE:
2658                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2659                 break;
2660         case MSR_IA32_TSC_ADJUST:
2661                 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2662                         if (!msr_info->host_initiated) {
2663                                 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2664                                 adjust_tsc_offset_guest(vcpu, adj);
2665                         }
2666                         vcpu->arch.ia32_tsc_adjust_msr = data;
2667                 }
2668                 break;
2669         case MSR_IA32_MISC_ENABLE:
2670                 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2671                     ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2672                         if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2673                                 return 1;
2674                         vcpu->arch.ia32_misc_enable_msr = data;
2675                         kvm_update_cpuid(vcpu);
2676                 } else {
2677                         vcpu->arch.ia32_misc_enable_msr = data;
2678                 }
2679                 break;
2680         case MSR_IA32_SMBASE:
2681                 if (!msr_info->host_initiated)
2682                         return 1;
2683                 vcpu->arch.smbase = data;
2684                 break;
2685         case MSR_IA32_POWER_CTL:
2686                 vcpu->arch.msr_ia32_power_ctl = data;
2687                 break;
2688         case MSR_IA32_TSC:
2689                 kvm_write_tsc(vcpu, msr_info);
2690                 break;
2691         case MSR_SMI_COUNT:
2692                 if (!msr_info->host_initiated)
2693                         return 1;
2694                 vcpu->arch.smi_count = data;
2695                 break;
2696         case MSR_KVM_WALL_CLOCK_NEW:
2697         case MSR_KVM_WALL_CLOCK:
2698                 vcpu->kvm->arch.wall_clock = data;
2699                 kvm_write_wall_clock(vcpu->kvm, data);
2700                 break;
2701         case MSR_KVM_SYSTEM_TIME_NEW:
2702         case MSR_KVM_SYSTEM_TIME: {
2703                 struct kvm_arch *ka = &vcpu->kvm->arch;
2704
2705                 kvmclock_reset(vcpu);
2706
2707                 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2708                         bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2709
2710                         if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2711                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2712
2713                         ka->boot_vcpu_runs_old_kvmclock = tmp;
2714                 }
2715
2716                 vcpu->arch.time = data;
2717                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2718
2719                 /* we verify if the enable bit is set... */
2720                 if (!(data & 1))
2721                         break;
2722
2723                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2724                      &vcpu->arch.pv_time, data & ~1ULL,
2725                      sizeof(struct pvclock_vcpu_time_info)))
2726                         vcpu->arch.pv_time_enabled = false;
2727                 else
2728                         vcpu->arch.pv_time_enabled = true;
2729
2730                 break;
2731         }
2732         case MSR_KVM_ASYNC_PF_EN:
2733                 if (kvm_pv_enable_async_pf(vcpu, data))
2734                         return 1;
2735                 break;
2736         case MSR_KVM_STEAL_TIME:
2737
2738                 if (unlikely(!sched_info_on()))
2739                         return 1;
2740
2741                 if (data & KVM_STEAL_RESERVED_MASK)
2742                         return 1;
2743
2744                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2745                                                 data & KVM_STEAL_VALID_BITS,
2746                                                 sizeof(struct kvm_steal_time)))
2747                         return 1;
2748
2749                 vcpu->arch.st.msr_val = data;
2750
2751                 if (!(data & KVM_MSR_ENABLED))
2752                         break;
2753
2754                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2755
2756                 break;
2757         case MSR_KVM_PV_EOI_EN:
2758                 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2759                         return 1;
2760                 break;
2761
2762         case MSR_KVM_POLL_CONTROL:
2763                 /* only enable bit supported */
2764                 if (data & (-1ULL << 1))
2765                         return 1;
2766
2767                 vcpu->arch.msr_kvm_poll_control = data;
2768                 break;
2769
2770         case MSR_IA32_MCG_CTL:
2771         case MSR_IA32_MCG_STATUS:
2772         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2773                 return set_msr_mce(vcpu, msr_info);
2774
2775         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2776         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2777                 pr = true; /* fall through */
2778         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2779         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2780                 if (kvm_pmu_is_valid_msr(vcpu, msr))
2781                         return kvm_pmu_set_msr(vcpu, msr_info);
2782
2783                 if (pr || data != 0)
2784                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2785                                     "0x%x data 0x%llx\n", msr, data);
2786                 break;
2787         case MSR_K7_CLK_CTL:
2788                 /*
2789                  * Ignore all writes to this no longer documented MSR.
2790                  * Writes are only relevant for old K7 processors,
2791                  * all pre-dating SVM, but a recommended workaround from
2792                  * AMD for these chips. It is possible to specify the
2793                  * affected processor models on the command line, hence
2794                  * the need to ignore the workaround.
2795                  */
2796                 break;
2797         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2798         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2799         case HV_X64_MSR_CRASH_CTL:
2800         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2801         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2802         case HV_X64_MSR_TSC_EMULATION_CONTROL:
2803         case HV_X64_MSR_TSC_EMULATION_STATUS:
2804                 return kvm_hv_set_msr_common(vcpu, msr, data,
2805                                              msr_info->host_initiated);
2806         case MSR_IA32_BBL_CR_CTL3:
2807                 /* Drop writes to this legacy MSR -- see rdmsr
2808                  * counterpart for further detail.
2809                  */
2810                 if (report_ignored_msrs)
2811                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2812                                 msr, data);
2813                 break;
2814         case MSR_AMD64_OSVW_ID_LENGTH:
2815                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2816                         return 1;
2817                 vcpu->arch.osvw.length = data;
2818                 break;
2819         case MSR_AMD64_OSVW_STATUS:
2820                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2821                         return 1;
2822                 vcpu->arch.osvw.status = data;
2823                 break;
2824         case MSR_PLATFORM_INFO:
2825                 if (!msr_info->host_initiated ||
2826                     (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2827                      cpuid_fault_enabled(vcpu)))
2828                         return 1;
2829                 vcpu->arch.msr_platform_info = data;
2830                 break;
2831         case MSR_MISC_FEATURES_ENABLES:
2832                 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2833                     (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2834                      !supports_cpuid_fault(vcpu)))
2835                         return 1;
2836                 vcpu->arch.msr_misc_features_enables = data;
2837                 break;
2838         default:
2839                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2840                         return xen_hvm_config(vcpu, data);
2841                 if (kvm_pmu_is_valid_msr(vcpu, msr))
2842                         return kvm_pmu_set_msr(vcpu, msr_info);
2843                 if (!ignore_msrs) {
2844                         vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2845                                     msr, data);
2846                         return 1;
2847                 } else {
2848                         if (report_ignored_msrs)
2849                                 vcpu_unimpl(vcpu,
2850                                         "ignored wrmsr: 0x%x data 0x%llx\n",
2851                                         msr, data);
2852                         break;
2853                 }
2854         }
2855         return 0;
2856 }
2857 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2858
2859 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2860 {
2861         u64 data;
2862         u64 mcg_cap = vcpu->arch.mcg_cap;
2863         unsigned bank_num = mcg_cap & 0xff;
2864
2865         switch (msr) {
2866         case MSR_IA32_P5_MC_ADDR:
2867         case MSR_IA32_P5_MC_TYPE:
2868                 data = 0;
2869                 break;
2870         case MSR_IA32_MCG_CAP:
2871                 data = vcpu->arch.mcg_cap;
2872                 break;
2873         case MSR_IA32_MCG_CTL:
2874                 if (!(mcg_cap & MCG_CTL_P) && !host)
2875                         return 1;
2876                 data = vcpu->arch.mcg_ctl;
2877                 break;
2878         case MSR_IA32_MCG_STATUS:
2879                 data = vcpu->arch.mcg_status;
2880                 break;
2881         default:
2882                 if (msr >= MSR_IA32_MC0_CTL &&
2883                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2884                         u32 offset = msr - MSR_IA32_MC0_CTL;
2885                         data = vcpu->arch.mce_banks[offset];
2886                         break;
2887                 }
2888                 return 1;
2889         }
2890         *pdata = data;
2891         return 0;
2892 }
2893
2894 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2895 {
2896         switch (msr_info->index) {
2897         case MSR_IA32_PLATFORM_ID:
2898         case MSR_IA32_EBL_CR_POWERON:
2899         case MSR_IA32_DEBUGCTLMSR:
2900         case MSR_IA32_LASTBRANCHFROMIP:
2901         case MSR_IA32_LASTBRANCHTOIP:
2902         case MSR_IA32_LASTINTFROMIP:
2903         case MSR_IA32_LASTINTTOIP:
2904         case MSR_K8_SYSCFG:
2905         case MSR_K8_TSEG_ADDR:
2906         case MSR_K8_TSEG_MASK:
2907         case MSR_VM_HSAVE_PA:
2908         case MSR_K8_INT_PENDING_MSG:
2909         case MSR_AMD64_NB_CFG:
2910         case MSR_FAM10H_MMIO_CONF_BASE:
2911         case MSR_AMD64_BU_CFG2:
2912         case MSR_IA32_PERF_CTL:
2913         case MSR_AMD64_DC_CFG:
2914         case MSR_F15H_EX_CFG:
2915                 msr_info->data = 0;
2916                 break;
2917         case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
2918         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2919         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2920         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2921         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2922                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2923                         return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2924                 msr_info->data = 0;
2925                 break;
2926         case MSR_IA32_UCODE_REV:
2927                 msr_info->data = vcpu->arch.microcode_version;
2928                 break;
2929         case MSR_IA32_ARCH_CAPABILITIES:
2930                 if (!msr_info->host_initiated &&
2931                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2932                         return 1;
2933                 msr_info->data = vcpu->arch.arch_capabilities;
2934                 break;
2935         case MSR_IA32_POWER_CTL:
2936                 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
2937                 break;
2938         case MSR_IA32_TSC:
2939                 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2940                 break;
2941         case MSR_MTRRcap:
2942         case 0x200 ... 0x2ff:
2943                 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2944         case 0xcd: /* fsb frequency */
2945                 msr_info->data = 3;
2946                 break;
2947                 /*
2948                  * MSR_EBC_FREQUENCY_ID
2949                  * Conservative value valid for even the basic CPU models.
2950                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2951                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2952                  * and 266MHz for model 3, or 4. Set Core Clock
2953                  * Frequency to System Bus Frequency Ratio to 1 (bits
2954                  * 31:24) even though these are only valid for CPU
2955                  * models > 2, however guests may end up dividing or
2956                  * multiplying by zero otherwise.
2957                  */
2958         case MSR_EBC_FREQUENCY_ID:
2959                 msr_info->data = 1 << 24;
2960                 break;
2961         case MSR_IA32_APICBASE:
2962                 msr_info->data = kvm_get_apic_base(vcpu);
2963                 break;
2964         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2965                 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2966                 break;
2967         case MSR_IA32_TSCDEADLINE:
2968                 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2969                 break;
2970         case MSR_IA32_TSC_ADJUST:
2971                 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2972                 break;
2973         case MSR_IA32_MISC_ENABLE:
2974                 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2975                 break;
2976         case MSR_IA32_SMBASE:
2977                 if (!msr_info->host_initiated)
2978                         return 1;
2979                 msr_info->data = vcpu->arch.smbase;
2980                 break;
2981         case MSR_SMI_COUNT:
2982                 msr_info->data = vcpu->arch.smi_count;
2983                 break;
2984         case MSR_IA32_PERF_STATUS:
2985                 /* TSC increment by tick */
2986                 msr_info->data = 1000ULL;
2987                 /* CPU multiplier */
2988                 msr_info->data |= (((uint64_t)4ULL) << 40);
2989                 break;
2990         case MSR_EFER:
2991                 msr_info->data = vcpu->arch.efer;
2992                 break;
2993         case MSR_KVM_WALL_CLOCK:
2994         case MSR_KVM_WALL_CLOCK_NEW:
2995                 msr_info->data = vcpu->kvm->arch.wall_clock;
2996                 break;
2997         case MSR_KVM_SYSTEM_TIME:
2998         case MSR_KVM_SYSTEM_TIME_NEW:
2999                 msr_info->data = vcpu->arch.time;
3000                 break;
3001         case MSR_KVM_ASYNC_PF_EN:
3002                 msr_info->data = vcpu->arch.apf.msr_val;
3003                 break;
3004         case MSR_KVM_STEAL_TIME:
3005                 msr_info->data = vcpu->arch.st.msr_val;
3006                 break;
3007         case MSR_KVM_PV_EOI_EN:
3008                 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3009                 break;
3010         case MSR_KVM_POLL_CONTROL:
3011                 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3012                 break;
3013         case MSR_IA32_P5_MC_ADDR:
3014         case MSR_IA32_P5_MC_TYPE:
3015         case MSR_IA32_MCG_CAP:
3016         case MSR_IA32_MCG_CTL:
3017         case MSR_IA32_MCG_STATUS:
3018         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3019                 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3020                                    msr_info->host_initiated);
3021         case MSR_K7_CLK_CTL:
3022                 /*
3023                  * Provide expected ramp-up count for K7. All other
3024                  * are set to zero, indicating minimum divisors for
3025                  * every field.
3026                  *
3027                  * This prevents guest kernels on AMD host with CPU
3028                  * type 6, model 8 and higher from exploding due to
3029                  * the rdmsr failing.
3030                  */
3031                 msr_info->data = 0x20000000;
3032                 break;
3033         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3034         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3035         case HV_X64_MSR_CRASH_CTL:
3036         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3037         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3038         case HV_X64_MSR_TSC_EMULATION_CONTROL:
3039         case HV_X64_MSR_TSC_EMULATION_STATUS:
3040                 return kvm_hv_get_msr_common(vcpu,
3041                                              msr_info->index, &msr_info->data,
3042                                              msr_info->host_initiated);
3043                 break;
3044         case MSR_IA32_BBL_CR_CTL3:
3045                 /* This legacy MSR exists but isn't fully documented in current
3046                  * silicon.  It is however accessed by winxp in very narrow
3047                  * scenarios where it sets bit #19, itself documented as
3048                  * a "reserved" bit.  Best effort attempt to source coherent
3049                  * read data here should the balance of the register be
3050                  * interpreted by the guest:
3051                  *
3052                  * L2 cache control register 3: 64GB range, 256KB size,
3053                  * enabled, latency 0x1, configured
3054                  */
3055                 msr_info->data = 0xbe702111;
3056                 break;
3057         case MSR_AMD64_OSVW_ID_LENGTH:
3058                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3059                         return 1;
3060                 msr_info->data = vcpu->arch.osvw.length;
3061                 break;
3062         case MSR_AMD64_OSVW_STATUS:
3063                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3064                         return 1;
3065                 msr_info->data = vcpu->arch.osvw.status;
3066                 break;
3067         case MSR_PLATFORM_INFO:
3068                 if (!msr_info->host_initiated &&
3069                     !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3070                         return 1;
3071                 msr_info->data = vcpu->arch.msr_platform_info;
3072                 break;
3073         case MSR_MISC_FEATURES_ENABLES:
3074                 msr_info->data = vcpu->arch.msr_misc_features_enables;
3075                 break;
3076         case MSR_K7_HWCR:
3077                 msr_info->data = vcpu->arch.msr_hwcr;
3078                 break;
3079         default:
3080                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3081                         return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3082                 if (!ignore_msrs) {
3083                         vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3084                                                msr_info->index);
3085                         return 1;
3086                 } else {
3087                         if (report_ignored_msrs)
3088                                 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3089                                         msr_info->index);
3090                         msr_info->data = 0;
3091                 }
3092                 break;
3093         }
3094         return 0;
3095 }
3096 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3097
3098 /*
3099  * Read or write a bunch of msrs. All parameters are kernel addresses.
3100  *
3101  * @return number of msrs set successfully.
3102  */
3103 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3104                     struct kvm_msr_entry *entries,
3105                     int (*do_msr)(struct kvm_vcpu *vcpu,
3106                                   unsigned index, u64 *data))
3107 {
3108         int i;
3109
3110         for (i = 0; i < msrs->nmsrs; ++i)
3111                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3112                         break;
3113
3114         return i;
3115 }
3116
3117 /*
3118  * Read or write a bunch of msrs. Parameters are user addresses.
3119  *
3120  * @return number of msrs set successfully.
3121  */
3122 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3123                   int (*do_msr)(struct kvm_vcpu *vcpu,
3124                                 unsigned index, u64 *data),
3125                   int writeback)
3126 {
3127         struct kvm_msrs msrs;
3128         struct kvm_msr_entry *entries;
3129         int r, n;
3130         unsigned size;
3131
3132         r = -EFAULT;
3133         if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3134                 goto out;
3135
3136         r = -E2BIG;
3137         if (msrs.nmsrs >= MAX_IO_MSRS)
3138                 goto out;
3139
3140         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3141         entries = memdup_user(user_msrs->entries, size);
3142         if (IS_ERR(entries)) {
3143                 r = PTR_ERR(entries);
3144                 goto out;
3145         }
3146
3147         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3148         if (r < 0)
3149                 goto out_free;
3150
3151         r = -EFAULT;
3152         if (writeback && copy_to_user(user_msrs->entries, entries, size))
3153                 goto out_free;
3154
3155         r = n;
3156
3157 out_free:
3158         kfree(entries);
3159 out:
3160         return r;
3161 }
3162
3163 static inline bool kvm_can_mwait_in_guest(void)
3164 {
3165         return boot_cpu_has(X86_FEATURE_MWAIT) &&
3166                 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3167                 boot_cpu_has(X86_FEATURE_ARAT);
3168 }
3169
3170 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3171 {
3172         int r = 0;
3173
3174         switch (ext) {
3175         case KVM_CAP_IRQCHIP:
3176         case KVM_CAP_HLT:
3177         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3178         case KVM_CAP_SET_TSS_ADDR:
3179         case KVM_CAP_EXT_CPUID:
3180         case KVM_CAP_EXT_EMUL_CPUID:
3181         case KVM_CAP_CLOCKSOURCE:
3182         case KVM_CAP_PIT:
3183         case KVM_CAP_NOP_IO_DELAY:
3184         case KVM_CAP_MP_STATE:
3185         case KVM_CAP_SYNC_MMU:
3186         case KVM_CAP_USER_NMI:
3187         case KVM_CAP_REINJECT_CONTROL:
3188         case KVM_CAP_IRQ_INJECT_STATUS:
3189         case KVM_CAP_IOEVENTFD:
3190         case KVM_CAP_IOEVENTFD_NO_LENGTH:
3191         case KVM_CAP_PIT2:
3192         case KVM_CAP_PIT_STATE2:
3193         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3194         case KVM_CAP_XEN_HVM:
3195         case KVM_CAP_VCPU_EVENTS:
3196         case KVM_CAP_HYPERV:
3197         case KVM_CAP_HYPERV_VAPIC:
3198         case KVM_CAP_HYPERV_SPIN:
3199         case KVM_CAP_HYPERV_SYNIC:
3200         case KVM_CAP_HYPERV_SYNIC2:
3201         case KVM_CAP_HYPERV_VP_INDEX:
3202         case KVM_CAP_HYPERV_EVENTFD:
3203         case KVM_CAP_HYPERV_TLBFLUSH:
3204         case KVM_CAP_HYPERV_SEND_IPI:
3205         case KVM_CAP_HYPERV_CPUID:
3206         case KVM_CAP_PCI_SEGMENT:
3207         case KVM_CAP_DEBUGREGS:
3208         case KVM_CAP_X86_ROBUST_SINGLESTEP:
3209         case KVM_CAP_XSAVE:
3210         case KVM_CAP_ASYNC_PF:
3211         case KVM_CAP_GET_TSC_KHZ:
3212         case KVM_CAP_KVMCLOCK_CTRL:
3213         case KVM_CAP_READONLY_MEM:
3214         case KVM_CAP_HYPERV_TIME:
3215         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3216         case KVM_CAP_TSC_DEADLINE_TIMER:
3217         case KVM_CAP_DISABLE_QUIRKS:
3218         case KVM_CAP_SET_BOOT_CPU_ID:
3219         case KVM_CAP_SPLIT_IRQCHIP:
3220         case KVM_CAP_IMMEDIATE_EXIT:
3221         case KVM_CAP_PMU_EVENT_FILTER:
3222         case KVM_CAP_GET_MSR_FEATURES:
3223         case KVM_CAP_MSR_PLATFORM_INFO:
3224         case KVM_CAP_EXCEPTION_PAYLOAD:
3225                 r = 1;
3226                 break;
3227         case KVM_CAP_SYNC_REGS:
3228                 r = KVM_SYNC_X86_VALID_FIELDS;
3229                 break;
3230         case KVM_CAP_ADJUST_CLOCK:
3231                 r = KVM_CLOCK_TSC_STABLE;
3232                 break;
3233         case KVM_CAP_X86_DISABLE_EXITS:
3234                 r |=  KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3235                       KVM_X86_DISABLE_EXITS_CSTATE;
3236                 if(kvm_can_mwait_in_guest())
3237                         r |= KVM_X86_DISABLE_EXITS_MWAIT;
3238                 break;
3239         case KVM_CAP_X86_SMM:
3240                 /* SMBASE is usually relocated above 1M on modern chipsets,
3241                  * and SMM handlers might indeed rely on 4G segment limits,
3242                  * so do not report SMM to be available if real mode is
3243                  * emulated via vm86 mode.  Still, do not go to great lengths
3244                  * to avoid userspace's usage of the feature, because it is a
3245                  * fringe case that is not enabled except via specific settings
3246                  * of the module parameters.
3247                  */
3248                 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3249                 break;
3250         case KVM_CAP_VAPIC:
3251                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3252                 break;
3253         case KVM_CAP_NR_VCPUS:
3254                 r = KVM_SOFT_MAX_VCPUS;
3255                 break;
3256         case KVM_CAP_MAX_VCPUS:
3257                 r = KVM_MAX_VCPUS;
3258                 break;
3259         case KVM_CAP_MAX_VCPU_ID:
3260                 r = KVM_MAX_VCPU_ID;
3261                 break;
3262         case KVM_CAP_PV_MMU:    /* obsolete */
3263                 r = 0;
3264                 break;
3265         case KVM_CAP_MCE:
3266                 r = KVM_MAX_MCE_BANKS;
3267                 break;
3268         case KVM_CAP_XCRS:
3269                 r = boot_cpu_has(X86_FEATURE_XSAVE);
3270                 break;
3271         case KVM_CAP_TSC_CONTROL:
3272                 r = kvm_has_tsc_control;
3273                 break;
3274         case KVM_CAP_X2APIC_API:
3275                 r = KVM_X2APIC_API_VALID_FLAGS;
3276                 break;
3277         case KVM_CAP_NESTED_STATE:
3278                 r = kvm_x86_ops->get_nested_state ?
3279                         kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
3280                 break;
3281         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3282                 r = kvm_x86_ops->enable_direct_tlbflush != NULL;
3283                 break;
3284         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3285                 r = kvm_x86_ops->nested_enable_evmcs != NULL;
3286                 break;
3287         default:
3288                 break;
3289         }
3290         return r;
3291
3292 }
3293
3294 long kvm_arch_dev_ioctl(struct file *filp,
3295                         unsigned int ioctl, unsigned long arg)
3296 {
3297         void __user *argp = (void __user *)arg;
3298         long r;
3299
3300         switch (ioctl) {
3301         case KVM_GET_MSR_INDEX_LIST: {
3302                 struct kvm_msr_list __user *user_msr_list = argp;
3303                 struct kvm_msr_list msr_list;
3304                 unsigned n;
3305
3306                 r = -EFAULT;
3307                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3308                         goto out;
3309                 n = msr_list.nmsrs;
3310                 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3311                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3312                         goto out;
3313                 r = -E2BIG;
3314                 if (n < msr_list.nmsrs)
3315                         goto out;
3316                 r = -EFAULT;
3317                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3318                                  num_msrs_to_save * sizeof(u32)))
3319                         goto out;
3320                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3321                                  &emulated_msrs,
3322                                  num_emulated_msrs * sizeof(u32)))
3323                         goto out;
3324                 r = 0;
3325                 break;
3326         }
3327         case KVM_GET_SUPPORTED_CPUID:
3328         case KVM_GET_EMULATED_CPUID: {
3329                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3330                 struct kvm_cpuid2 cpuid;
3331
3332                 r = -EFAULT;
3333                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3334                         goto out;
3335
3336                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3337                                             ioctl);
3338                 if (r)
3339                         goto out;
3340
3341                 r = -EFAULT;
3342                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3343                         goto out;
3344                 r = 0;
3345                 break;
3346         }
3347         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3348                 r = -EFAULT;
3349                 if (copy_to_user(argp, &kvm_mce_cap_supported,
3350                                  sizeof(kvm_mce_cap_supported)))
3351                         goto out;
3352                 r = 0;
3353                 break;
3354         case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3355                 struct kvm_msr_list __user *user_msr_list = argp;
3356                 struct kvm_msr_list msr_list;
3357                 unsigned int n;
3358
3359                 r = -EFAULT;
3360                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3361                         goto out;
3362                 n = msr_list.nmsrs;
3363                 msr_list.nmsrs = num_msr_based_features;
3364                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3365                         goto out;
3366                 r = -E2BIG;
3367                 if (n < msr_list.nmsrs)
3368                         goto out;
3369                 r = -EFAULT;
3370                 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3371                                  num_msr_based_features * sizeof(u32)))
3372                         goto out;
3373                 r = 0;
3374                 break;
3375         }
3376         case KVM_GET_MSRS:
3377                 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3378                 break;
3379         }
3380         default:
3381                 r = -EINVAL;
3382         }
3383 out:
3384         return r;
3385 }
3386
3387 static void wbinvd_ipi(void *garbage)
3388 {
3389         wbinvd();
3390 }
3391
3392 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3393 {
3394         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3395 }
3396
3397 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3398 {
3399         /* Address WBINVD may be executed by guest */
3400         if (need_emulate_wbinvd(vcpu)) {
3401                 if (kvm_x86_ops->has_wbinvd_exit())
3402                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3403                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3404                         smp_call_function_single(vcpu->cpu,
3405                                         wbinvd_ipi, NULL, 1);
3406         }
3407
3408         kvm_x86_ops->vcpu_load(vcpu, cpu);
3409
3410         fpregs_assert_state_consistent();
3411         if (test_thread_flag(TIF_NEED_FPU_LOAD))
3412                 switch_fpu_return();
3413
3414         /* Apply any externally detected TSC adjustments (due to suspend) */
3415         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3416                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3417                 vcpu->arch.tsc_offset_adjustment = 0;
3418                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3419         }
3420
3421         if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3422                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3423                                 rdtsc() - vcpu->arch.last_host_tsc;
3424                 if (tsc_delta < 0)
3425                         mark_tsc_unstable("KVM discovered backwards TSC");
3426
3427                 if (kvm_check_tsc_unstable()) {
3428                         u64 offset = kvm_compute_tsc_offset(vcpu,
3429                                                 vcpu->arch.last_guest_tsc);
3430                         kvm_vcpu_write_tsc_offset(vcpu, offset);
3431                         vcpu->arch.tsc_catchup = 1;
3432                 }
3433
3434                 if (kvm_lapic_hv_timer_in_use(vcpu))
3435                         kvm_lapic_restart_hv_timer(vcpu);
3436
3437                 /*
3438                  * On a host with synchronized TSC, there is no need to update
3439                  * kvmclock on vcpu->cpu migration
3440                  */
3441                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3442                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3443                 if (vcpu->cpu != cpu)
3444                         kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3445                 vcpu->cpu = cpu;
3446         }
3447
3448         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3449 }
3450
3451 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3452 {
3453         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3454                 return;
3455
3456         vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
3457
3458         kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3459                         &vcpu->arch.st.steal.preempted,
3460                         offsetof(struct kvm_steal_time, preempted),
3461                         sizeof(vcpu->arch.st.steal.preempted));
3462 }
3463
3464 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3465 {
3466         int idx;
3467
3468         if (vcpu->preempted)
3469                 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3470
3471         /*
3472          * Disable page faults because we're in atomic context here.
3473          * kvm_write_guest_offset_cached() would call might_fault()
3474          * that relies on pagefault_disable() to tell if there's a
3475          * bug. NOTE: the write to guest memory may not go through if
3476          * during postcopy live migration or if there's heavy guest
3477          * paging.
3478          */
3479         pagefault_disable();
3480         /*
3481          * kvm_memslots() will be called by
3482          * kvm_write_guest_offset_cached() so take the srcu lock.
3483          */
3484         idx = srcu_read_lock(&vcpu->kvm->srcu);
3485         kvm_steal_time_set_preempted(vcpu);
3486         srcu_read_unlock(&vcpu->kvm->srcu, idx);
3487         pagefault_enable();
3488         kvm_x86_ops->vcpu_put(vcpu);
3489         vcpu->arch.last_host_tsc = rdtsc();
3490         /*
3491          * If userspace has set any breakpoints or watchpoints, dr6 is restored
3492          * on every vmexit, but if not, we might have a stale dr6 from the
3493          * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3494          */
3495         set_debugreg(0, 6);
3496 }
3497
3498 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3499                                     struct kvm_lapic_state *s)
3500 {
3501         if (vcpu->arch.apicv_active)
3502                 kvm_x86_ops->sync_pir_to_irr(vcpu);
3503
3504         return kvm_apic_get_state(vcpu, s);
3505 }
3506
3507 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3508                                     struct kvm_lapic_state *s)
3509 {
3510         int r;
3511
3512         r = kvm_apic_set_state(vcpu, s);
3513         if (r)
3514                 return r;
3515         update_cr8_intercept(vcpu);
3516
3517         return 0;
3518 }
3519
3520 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3521 {
3522         return (!lapic_in_kernel(vcpu) ||
3523                 kvm_apic_accept_pic_intr(vcpu));
3524 }
3525
3526 /*
3527  * if userspace requested an interrupt window, check that the
3528  * interrupt window is open.
3529  *
3530  * No need to exit to userspace if we already have an interrupt queued.
3531  */
3532 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3533 {
3534         return kvm_arch_interrupt_allowed(vcpu) &&
3535                 !kvm_cpu_has_interrupt(vcpu) &&
3536                 !kvm_event_needs_reinjection(vcpu) &&
3537                 kvm_cpu_accept_dm_intr(vcpu);
3538 }
3539
3540 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3541                                     struct kvm_interrupt *irq)
3542 {
3543         if (irq->irq >= KVM_NR_INTERRUPTS)
3544                 return -EINVAL;
3545
3546         if (!irqchip_in_kernel(vcpu->kvm)) {
3547                 kvm_queue_interrupt(vcpu, irq->irq, false);
3548                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3549                 return 0;
3550         }
3551
3552         /*
3553          * With in-kernel LAPIC, we only use this to inject EXTINT, so
3554          * fail for in-kernel 8259.
3555          */
3556         if (pic_in_kernel(vcpu->kvm))
3557                 return -ENXIO;
3558
3559         if (vcpu->arch.pending_external_vector != -1)
3560                 return -EEXIST;
3561
3562         vcpu->arch.pending_external_vector = irq->irq;
3563         kvm_make_request(KVM_REQ_EVENT, vcpu);
3564         return 0;
3565 }
3566
3567 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3568 {
3569         kvm_inject_nmi(vcpu);
3570
3571         return 0;
3572 }
3573
3574 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3575 {
3576         kvm_make_request(KVM_REQ_SMI, vcpu);
3577
3578         return 0;
3579 }
3580
3581 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3582                                            struct kvm_tpr_access_ctl *tac)
3583 {
3584         if (tac->flags)
3585                 return -EINVAL;
3586         vcpu->arch.tpr_access_reporting = !!tac->enabled;
3587         return 0;
3588 }
3589
3590 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3591                                         u64 mcg_cap)
3592 {
3593         int r;
3594         unsigned bank_num = mcg_cap & 0xff, bank;
3595
3596         r = -EINVAL;
3597         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3598                 goto out;
3599         if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3600                 goto out;
3601         r = 0;
3602         vcpu->arch.mcg_cap = mcg_cap;
3603         /* Init IA32_MCG_CTL to all 1s */
3604         if (mcg_cap & MCG_CTL_P)
3605                 vcpu->arch.mcg_ctl = ~(u64)0;
3606         /* Init IA32_MCi_CTL to all 1s */
3607         for (bank = 0; bank < bank_num; bank++)
3608                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3609
3610         kvm_x86_ops->setup_mce(vcpu);
3611 out:
3612         return r;
3613 }
3614
3615 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3616                                       struct kvm_x86_mce *mce)
3617 {
3618         u64 mcg_cap = vcpu->arch.mcg_cap;
3619         unsigned bank_num = mcg_cap & 0xff;
3620         u64 *banks = vcpu->arch.mce_banks;
3621
3622         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3623                 return -EINVAL;
3624         /*
3625          * if IA32_MCG_CTL is not all 1s, the uncorrected error
3626          * reporting is disabled
3627          */
3628         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3629             vcpu->arch.mcg_ctl != ~(u64)0)
3630                 return 0;
3631         banks += 4 * mce->bank;
3632         /*
3633          * if IA32_MCi_CTL is not all 1s, the uncorrected error
3634          * reporting is disabled for the bank
3635          */
3636         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3637                 return 0;
3638         if (mce->status & MCI_STATUS_UC) {
3639                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3640                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3641                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3642                         return 0;
3643                 }
3644                 if (banks[1] & MCI_STATUS_VAL)
3645                         mce->status |= MCI_STATUS_OVER;
3646                 banks[2] = mce->addr;
3647                 banks[3] = mce->misc;
3648                 vcpu->arch.mcg_status = mce->mcg_status;
3649                 banks[1] = mce->status;
3650                 kvm_queue_exception(vcpu, MC_VECTOR);
3651         } else if (!(banks[1] & MCI_STATUS_VAL)
3652                    || !(banks[1] & MCI_STATUS_UC)) {
3653                 if (banks[1] & MCI_STATUS_VAL)
3654                         mce->status |= MCI_STATUS_OVER;
3655                 banks[2] = mce->addr;
3656                 banks[3] = mce->misc;
3657                 banks[1] = mce->status;
3658         } else
3659                 banks[1] |= MCI_STATUS_OVER;
3660         return 0;
3661 }
3662
3663 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3664                                                struct kvm_vcpu_events *events)
3665 {
3666         process_nmi(vcpu);
3667
3668         /*
3669          * The API doesn't provide the instruction length for software
3670          * exceptions, so don't report them. As long as the guest RIP
3671          * isn't advanced, we should expect to encounter the exception
3672          * again.
3673          */
3674         if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3675                 events->exception.injected = 0;
3676                 events->exception.pending = 0;
3677         } else {
3678                 events->exception.injected = vcpu->arch.exception.injected;
3679                 events->exception.pending = vcpu->arch.exception.pending;
3680                 /*
3681                  * For ABI compatibility, deliberately conflate
3682                  * pending and injected exceptions when
3683                  * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3684                  */
3685                 if (!vcpu->kvm->arch.exception_payload_enabled)
3686                         events->exception.injected |=
3687                                 vcpu->arch.exception.pending;
3688         }
3689         events->exception.nr = vcpu->arch.exception.nr;
3690         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3691         events->exception.error_code = vcpu->arch.exception.error_code;
3692         events->exception_has_payload = vcpu->arch.exception.has_payload;
3693         events->exception_payload = vcpu->arch.exception.payload;
3694
3695         events->interrupt.injected =
3696                 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3697         events->interrupt.nr = vcpu->arch.interrupt.nr;
3698         events->interrupt.soft = 0;
3699         events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3700
3701         events->nmi.injected = vcpu->arch.nmi_injected;
3702         events->nmi.pending = vcpu->arch.nmi_pending != 0;
3703         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3704         events->nmi.pad = 0;
3705
3706         events->sipi_vector = 0; /* never valid when reporting to user space */
3707
3708         events->smi.smm = is_smm(vcpu);
3709         events->smi.pending = vcpu->arch.smi_pending;
3710         events->smi.smm_inside_nmi =
3711                 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3712         events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3713
3714         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3715                          | KVM_VCPUEVENT_VALID_SHADOW
3716                          | KVM_VCPUEVENT_VALID_SMM);
3717         if (vcpu->kvm->arch.exception_payload_enabled)
3718                 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3719
3720         memset(&events->reserved, 0, sizeof(events->reserved));
3721 }
3722
3723 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3724
3725 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3726                                               struct kvm_vcpu_events *events)
3727 {
3728         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3729                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3730                               | KVM_VCPUEVENT_VALID_SHADOW
3731                               | KVM_VCPUEVENT_VALID_SMM
3732                               | KVM_VCPUEVENT_VALID_PAYLOAD))
3733                 return -EINVAL;
3734
3735         if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3736                 if (!vcpu->kvm->arch.exception_payload_enabled)
3737                         return -EINVAL;
3738                 if (events->exception.pending)
3739                         events->exception.injected = 0;
3740                 else
3741                         events->exception_has_payload = 0;
3742         } else {
3743                 events->exception.pending = 0;
3744                 events->exception_has_payload = 0;
3745         }
3746
3747         if ((events->exception.injected || events->exception.pending) &&
3748             (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3749                 return -EINVAL;
3750
3751         /* INITs are latched while in SMM */
3752         if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3753             (events->smi.smm || events->smi.pending) &&
3754             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3755                 return -EINVAL;
3756
3757         process_nmi(vcpu);
3758         vcpu->arch.exception.injected = events->exception.injected;
3759         vcpu->arch.exception.pending = events->exception.pending;
3760         vcpu->arch.exception.nr = events->exception.nr;
3761         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3762         vcpu->arch.exception.error_code = events->exception.error_code;
3763         vcpu->arch.exception.has_payload = events->exception_has_payload;
3764         vcpu->arch.exception.payload = events->exception_payload;
3765
3766         vcpu->arch.interrupt.injected = events->interrupt.injected;
3767         vcpu->arch.interrupt.nr = events->interrupt.nr;
3768         vcpu->arch.interrupt.soft = events->interrupt.soft;
3769         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3770                 kvm_x86_ops->set_interrupt_shadow(vcpu,
3771                                                   events->interrupt.shadow);
3772
3773         vcpu->arch.nmi_injected = events->nmi.injected;
3774         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3775                 vcpu->arch.nmi_pending = events->nmi.pending;
3776         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3777
3778         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3779             lapic_in_kernel(vcpu))
3780                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3781
3782         if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3783                 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3784                         if (events->smi.smm)
3785                                 vcpu->arch.hflags |= HF_SMM_MASK;
3786                         else
3787                                 vcpu->arch.hflags &= ~HF_SMM_MASK;
3788                         kvm_smm_changed(vcpu);
3789                 }
3790
3791                 vcpu->arch.smi_pending = events->smi.pending;
3792
3793                 if (events->smi.smm) {
3794                         if (events->smi.smm_inside_nmi)
3795                                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3796                         else
3797                                 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3798                         if (lapic_in_kernel(vcpu)) {
3799                                 if (events->smi.latched_init)
3800                                         set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3801                                 else
3802                                         clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3803                         }
3804                 }
3805         }
3806
3807         kvm_make_request(KVM_REQ_EVENT, vcpu);
3808
3809         return 0;
3810 }
3811
3812 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3813                                              struct kvm_debugregs *dbgregs)
3814 {
3815         unsigned long val;
3816
3817         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3818         kvm_get_dr(vcpu, 6, &val);
3819         dbgregs->dr6 = val;
3820         dbgregs->dr7 = vcpu->arch.dr7;
3821         dbgregs->flags = 0;
3822         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3823 }
3824
3825 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3826                                             struct kvm_debugregs *dbgregs)
3827 {
3828         if (dbgregs->flags)
3829                 return -EINVAL;
3830
3831         if (dbgregs->dr6 & ~0xffffffffull)
3832                 return -EINVAL;
3833         if (dbgregs->dr7 & ~0xffffffffull)
3834                 return -EINVAL;
3835
3836         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3837         kvm_update_dr0123(vcpu);
3838         vcpu->arch.dr6 = dbgregs->dr6;
3839         kvm_update_dr6(vcpu);
3840         vcpu->arch.dr7 = dbgregs->dr7;
3841         kvm_update_dr7(vcpu);
3842
3843         return 0;
3844 }
3845
3846 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3847
3848 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3849 {
3850         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3851         u64 xstate_bv = xsave->header.xfeatures;
3852         u64 valid;
3853
3854         /*
3855          * Copy legacy XSAVE area, to avoid complications with CPUID
3856          * leaves 0 and 1 in the loop below.
3857          */
3858         memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3859
3860         /* Set XSTATE_BV */
3861         xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3862         *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3863
3864         /*
3865          * Copy each region from the possibly compacted offset to the
3866          * non-compacted offset.
3867          */
3868         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3869         while (valid) {
3870                 u64 xfeature_mask = valid & -valid;
3871                 int xfeature_nr = fls64(xfeature_mask) - 1;
3872                 void *src = get_xsave_addr(xsave, xfeature_nr);
3873
3874                 if (src) {
3875                         u32 size, offset, ecx, edx;
3876                         cpuid_count(XSTATE_CPUID, xfeature_nr,
3877                                     &size, &offset, &ecx, &edx);
3878                         if (xfeature_nr == XFEATURE_PKRU)
3879                                 memcpy(dest + offset, &vcpu->arch.pkru,
3880                                        sizeof(vcpu->arch.pkru));
3881                         else
3882                                 memcpy(dest + offset, src, size);
3883
3884                 }
3885
3886                 valid -= xfeature_mask;
3887         }
3888 }
3889
3890 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3891 {
3892         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3893         u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3894         u64 valid;
3895
3896         /*
3897          * Copy legacy XSAVE area, to avoid complications with CPUID
3898          * leaves 0 and 1 in the loop below.
3899          */
3900         memcpy(xsave, src, XSAVE_HDR_OFFSET);
3901
3902         /* Set XSTATE_BV and possibly XCOMP_BV.  */
3903         xsave->header.xfeatures = xstate_bv;
3904         if (boot_cpu_has(X86_FEATURE_XSAVES))
3905                 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3906
3907         /*
3908          * Copy each region from the non-compacted offset to the
3909          * possibly compacted offset.
3910          */
3911         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3912         while (valid) {
3913                 u64 xfeature_mask = valid & -valid;
3914                 int xfeature_nr = fls64(xfeature_mask) - 1;
3915                 void *dest = get_xsave_addr(xsave, xfeature_nr);
3916
3917                 if (dest) {
3918                         u32 size, offset, ecx, edx;
3919                         cpuid_count(XSTATE_CPUID, xfeature_nr,
3920                                     &size, &offset, &ecx, &edx);
3921                         if (xfeature_nr == XFEATURE_PKRU)
3922                                 memcpy(&vcpu->arch.pkru, src + offset,
3923                                        sizeof(vcpu->arch.pkru));
3924                         else
3925                                 memcpy(dest, src + offset, size);
3926                 }
3927
3928                 valid -= xfeature_mask;
3929         }
3930 }
3931
3932 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3933                                          struct kvm_xsave *guest_xsave)
3934 {
3935         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3936                 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3937                 fill_xsave((u8 *) guest_xsave->region, vcpu);
3938         } else {
3939                 memcpy(guest_xsave->region,
3940                         &vcpu->arch.guest_fpu->state.fxsave,
3941                         sizeof(struct fxregs_state));
3942                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3943                         XFEATURE_MASK_FPSSE;
3944         }
3945 }
3946
3947 #define XSAVE_MXCSR_OFFSET 24
3948
3949 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3950                                         struct kvm_xsave *guest_xsave)
3951 {
3952         u64 xstate_bv =
3953                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3954         u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3955
3956         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3957                 /*
3958                  * Here we allow setting states that are not present in
3959                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
3960                  * with old userspace.
3961                  */
3962                 if (xstate_bv & ~kvm_supported_xcr0() ||
3963                         mxcsr & ~mxcsr_feature_mask)
3964                         return -EINVAL;
3965                 load_xsave(vcpu, (u8 *)guest_xsave->region);
3966         } else {
3967                 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3968                         mxcsr & ~mxcsr_feature_mask)
3969                         return -EINVAL;
3970                 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
3971                         guest_xsave->region, sizeof(struct fxregs_state));
3972         }
3973         return 0;
3974 }
3975
3976 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3977                                         struct kvm_xcrs *guest_xcrs)
3978 {
3979         if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3980                 guest_xcrs->nr_xcrs = 0;
3981                 return;
3982         }
3983
3984         guest_xcrs->nr_xcrs = 1;
3985         guest_xcrs->flags = 0;
3986         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3987         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3988 }
3989
3990 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3991                                        struct kvm_xcrs *guest_xcrs)
3992 {
3993         int i, r = 0;
3994
3995         if (!boot_cpu_has(X86_FEATURE_XSAVE))
3996                 return -EINVAL;
3997
3998         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3999                 return -EINVAL;
4000
4001         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4002                 /* Only support XCR0 currently */
4003                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4004                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4005                                 guest_xcrs->xcrs[i].value);
4006                         break;
4007                 }
4008         if (r)
4009                 r = -EINVAL;
4010         return r;
4011 }
4012
4013 /*
4014  * kvm_set_guest_paused() indicates to the guest kernel that it has been
4015  * stopped by the hypervisor.  This function will be called from the host only.
4016  * EINVAL is returned when the host attempts to set the flag for a guest that
4017  * does not support pv clocks.
4018  */
4019 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4020 {
4021         if (!vcpu->arch.pv_time_enabled)
4022                 return -EINVAL;
4023         vcpu->arch.pvclock_set_guest_stopped_request = true;
4024         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4025         return 0;
4026 }
4027
4028 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4029                                      struct kvm_enable_cap *cap)
4030 {
4031         int r;
4032         uint16_t vmcs_version;
4033         void __user *user_ptr;
4034
4035         if (cap->flags)
4036                 return -EINVAL;
4037
4038         switch (cap->cap) {
4039         case KVM_CAP_HYPERV_SYNIC2:
4040                 if (cap->args[0])
4041                         return -EINVAL;
4042                 /* fall through */
4043
4044         case KVM_CAP_HYPERV_SYNIC:
4045                 if (!irqchip_in_kernel(vcpu->kvm))
4046                         return -EINVAL;
4047                 return kvm_hv_activate_synic(vcpu, cap->cap ==
4048                                              KVM_CAP_HYPERV_SYNIC2);
4049         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4050                 if (!kvm_x86_ops->nested_enable_evmcs)
4051                         return -ENOTTY;
4052                 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
4053                 if (!r) {
4054                         user_ptr = (void __user *)(uintptr_t)cap->args[0];
4055                         if (copy_to_user(user_ptr, &vmcs_version,
4056                                          sizeof(vmcs_version)))
4057                                 r = -EFAULT;
4058                 }
4059                 return r;
4060         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4061                 if (!kvm_x86_ops->enable_direct_tlbflush)
4062                         return -ENOTTY;
4063
4064                 return kvm_x86_ops->enable_direct_tlbflush(vcpu);
4065
4066         default:
4067                 return -EINVAL;
4068         }
4069 }
4070
4071 long kvm_arch_vcpu_ioctl(struct file *filp,
4072                          unsigned int ioctl, unsigned long arg)
4073 {
4074         struct kvm_vcpu *vcpu = filp->private_data;
4075         void __user *argp = (void __user *)arg;
4076         int r;
4077         union {
4078                 struct kvm_lapic_state *lapic;
4079                 struct kvm_xsave *xsave;
4080                 struct kvm_xcrs *xcrs;
4081                 void *buffer;
4082         } u;
4083
4084         vcpu_load(vcpu);
4085
4086         u.buffer = NULL;
4087         switch (ioctl) {
4088         case KVM_GET_LAPIC: {
4089                 r = -EINVAL;
4090                 if (!lapic_in_kernel(vcpu))
4091                         goto out;
4092                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4093                                 GFP_KERNEL_ACCOUNT);
4094
4095                 r = -ENOMEM;
4096                 if (!u.lapic)
4097                         goto out;
4098                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4099                 if (r)
4100                         goto out;
4101                 r = -EFAULT;
4102                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4103                         goto out;
4104                 r = 0;
4105                 break;
4106         }
4107         case KVM_SET_LAPIC: {
4108                 r = -EINVAL;
4109                 if (!lapic_in_kernel(vcpu))
4110                         goto out;
4111                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4112                 if (IS_ERR(u.lapic)) {
4113                         r = PTR_ERR(u.lapic);
4114                         goto out_nofree;
4115                 }
4116
4117                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4118                 break;
4119         }
4120         case KVM_INTERRUPT: {
4121                 struct kvm_interrupt irq;
4122
4123                 r = -EFAULT;
4124                 if (copy_from_user(&irq, argp, sizeof(irq)))
4125                         goto out;
4126                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4127                 break;
4128         }
4129         case KVM_NMI: {
4130                 r = kvm_vcpu_ioctl_nmi(vcpu);
4131                 break;
4132         }
4133         case KVM_SMI: {
4134                 r = kvm_vcpu_ioctl_smi(vcpu);
4135                 break;
4136         }
4137         case KVM_SET_CPUID: {
4138                 struct kvm_cpuid __user *cpuid_arg = argp;
4139                 struct kvm_cpuid cpuid;
4140
4141                 r = -EFAULT;
4142                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4143                         goto out;
4144                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4145                 break;
4146         }
4147         case KVM_SET_CPUID2: {
4148                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4149                 struct kvm_cpuid2 cpuid;
4150
4151                 r = -EFAULT;
4152                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4153                         goto out;
4154                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4155                                               cpuid_arg->entries);
4156                 break;
4157         }
4158         case KVM_GET_CPUID2: {
4159                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4160                 struct kvm_cpuid2 cpuid;
4161
4162                 r = -EFAULT;
4163                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4164                         goto out;
4165                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4166                                               cpuid_arg->entries);
4167                 if (r)
4168                         goto out;
4169                 r = -EFAULT;
4170                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4171                         goto out;
4172                 r = 0;
4173                 break;
4174         }
4175         case KVM_GET_MSRS: {
4176                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4177                 r = msr_io(vcpu, argp, do_get_msr, 1);
4178                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4179                 break;
4180         }
4181         case KVM_SET_MSRS: {
4182                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4183                 r = msr_io(vcpu, argp, do_set_msr, 0);
4184                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4185                 break;
4186         }
4187         case KVM_TPR_ACCESS_REPORTING: {
4188                 struct kvm_tpr_access_ctl tac;
4189
4190                 r = -EFAULT;
4191                 if (copy_from_user(&tac, argp, sizeof(tac)))
4192                         goto out;
4193                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4194                 if (r)
4195                         goto out;
4196                 r = -EFAULT;
4197                 if (copy_to_user(argp, &tac, sizeof(tac)))
4198                         goto out;
4199                 r = 0;
4200                 break;
4201         };
4202         case KVM_SET_VAPIC_ADDR: {
4203                 struct kvm_vapic_addr va;
4204                 int idx;
4205
4206                 r = -EINVAL;
4207                 if (!lapic_in_kernel(vcpu))
4208                         goto out;
4209                 r = -EFAULT;
4210                 if (copy_from_user(&va, argp, sizeof(va)))
4211                         goto out;
4212                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4213                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4214                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4215                 break;
4216         }
4217         case KVM_X86_SETUP_MCE: {
4218                 u64 mcg_cap;
4219
4220                 r = -EFAULT;
4221                 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4222                         goto out;
4223                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4224                 break;
4225         }
4226         case KVM_X86_SET_MCE: {
4227                 struct kvm_x86_mce mce;
4228
4229                 r = -EFAULT;
4230                 if (copy_from_user(&mce, argp, sizeof(mce)))
4231                         goto out;
4232                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4233                 break;
4234         }
4235         case KVM_GET_VCPU_EVENTS: {
4236                 struct kvm_vcpu_events events;
4237
4238                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4239
4240                 r = -EFAULT;
4241                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4242                         break;
4243                 r = 0;
4244                 break;
4245         }
4246         case KVM_SET_VCPU_EVENTS: {
4247                 struct kvm_vcpu_events events;
4248
4249                 r = -EFAULT;
4250                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4251                         break;
4252
4253                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4254                 break;
4255         }
4256         case KVM_GET_DEBUGREGS: {
4257                 struct kvm_debugregs dbgregs;
4258
4259                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4260
4261                 r = -EFAULT;
4262                 if (copy_to_user(argp, &dbgregs,
4263                                  sizeof(struct kvm_debugregs)))
4264                         break;
4265                 r = 0;
4266                 break;
4267         }
4268         case KVM_SET_DEBUGREGS: {
4269                 struct kvm_debugregs dbgregs;
4270
4271                 r = -EFAULT;
4272                 if (copy_from_user(&dbgregs, argp,
4273                                    sizeof(struct kvm_debugregs)))
4274                         break;
4275
4276                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4277                 break;
4278         }
4279         case KVM_GET_XSAVE: {
4280                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4281                 r = -ENOMEM;
4282                 if (!u.xsave)
4283                         break;
4284
4285                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4286
4287                 r = -EFAULT;
4288                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4289                         break;
4290                 r = 0;
4291                 break;
4292         }
4293         case KVM_SET_XSAVE: {
4294                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4295                 if (IS_ERR(u.xsave)) {
4296                         r = PTR_ERR(u.xsave);
4297                         goto out_nofree;
4298                 }
4299
4300                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4301                 break;
4302         }
4303         case KVM_GET_XCRS: {
4304                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4305                 r = -ENOMEM;
4306                 if (!u.xcrs)
4307                         break;
4308
4309                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4310
4311                 r = -EFAULT;
4312                 if (copy_to_user(argp, u.xcrs,
4313                                  sizeof(struct kvm_xcrs)))
4314                         break;
4315                 r = 0;
4316                 break;
4317         }
4318         case KVM_SET_XCRS: {
4319                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4320                 if (IS_ERR(u.xcrs)) {
4321                         r = PTR_ERR(u.xcrs);
4322                         goto out_nofree;
4323                 }
4324
4325                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4326                 break;
4327         }
4328         case KVM_SET_TSC_KHZ: {
4329                 u32 user_tsc_khz;
4330
4331                 r = -EINVAL;
4332                 user_tsc_khz = (u32)arg;
4333
4334                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4335                         goto out;
4336
4337                 if (user_tsc_khz == 0)
4338                         user_tsc_khz = tsc_khz;
4339
4340                 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4341                         r = 0;
4342
4343                 goto out;
4344         }
4345         case KVM_GET_TSC_KHZ: {
4346                 r = vcpu->arch.virtual_tsc_khz;
4347                 goto out;
4348         }
4349         case KVM_KVMCLOCK_CTRL: {
4350                 r = kvm_set_guest_paused(vcpu);
4351                 goto out;
4352         }
4353         case KVM_ENABLE_CAP: {
4354                 struct kvm_enable_cap cap;
4355
4356                 r = -EFAULT;
4357                 if (copy_from_user(&cap, argp, sizeof(cap)))
4358                         goto out;
4359                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4360                 break;
4361         }
4362         case KVM_GET_NESTED_STATE: {
4363                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4364                 u32 user_data_size;
4365
4366                 r = -EINVAL;
4367                 if (!kvm_x86_ops->get_nested_state)
4368                         break;
4369
4370                 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4371                 r = -EFAULT;
4372                 if (get_user(user_data_size, &user_kvm_nested_state->size))
4373                         break;
4374
4375                 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4376                                                   user_data_size);
4377                 if (r < 0)
4378                         break;
4379
4380                 if (r > user_data_size) {
4381                         if (put_user(r, &user_kvm_nested_state->size))
4382                                 r = -EFAULT;
4383                         else
4384                                 r = -E2BIG;
4385                         break;
4386                 }
4387
4388                 r = 0;
4389                 break;
4390         }
4391         case KVM_SET_NESTED_STATE: {
4392                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4393                 struct kvm_nested_state kvm_state;
4394
4395                 r = -EINVAL;
4396                 if (!kvm_x86_ops->set_nested_state)
4397                         break;
4398
4399                 r = -EFAULT;
4400                 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4401                         break;
4402
4403                 r = -EINVAL;
4404                 if (kvm_state.size < sizeof(kvm_state))
4405                         break;
4406
4407                 if (kvm_state.flags &
4408                     ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4409                       | KVM_STATE_NESTED_EVMCS))
4410                         break;
4411
4412                 /* nested_run_pending implies guest_mode.  */
4413                 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4414                     && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4415                         break;
4416
4417                 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4418                 break;
4419         }
4420         case KVM_GET_SUPPORTED_HV_CPUID: {
4421                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4422                 struct kvm_cpuid2 cpuid;
4423
4424                 r = -EFAULT;
4425                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4426                         goto out;
4427
4428                 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4429                                                 cpuid_arg->entries);
4430                 if (r)
4431                         goto out;
4432
4433                 r = -EFAULT;
4434                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4435                         goto out;
4436                 r = 0;
4437                 break;
4438         }
4439         default:
4440                 r = -EINVAL;
4441         }
4442 out:
4443         kfree(u.buffer);
4444 out_nofree:
4445         vcpu_put(vcpu);
4446         return r;
4447 }
4448
4449 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4450 {
4451         return VM_FAULT_SIGBUS;
4452 }
4453
4454 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4455 {
4456         int ret;
4457
4458         if (addr > (unsigned int)(-3 * PAGE_SIZE))
4459                 return -EINVAL;
4460         ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4461         return ret;
4462 }
4463
4464 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4465                                               u64 ident_addr)
4466 {
4467         return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4468 }
4469
4470 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4471                                          unsigned long kvm_nr_mmu_pages)
4472 {
4473         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4474                 return -EINVAL;
4475
4476         mutex_lock(&kvm->slots_lock);
4477
4478         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4479         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4480
4481         mutex_unlock(&kvm->slots_lock);
4482         return 0;
4483 }
4484
4485 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4486 {
4487         return kvm->arch.n_max_mmu_pages;
4488 }
4489
4490 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4491 {
4492         struct kvm_pic *pic = kvm->arch.vpic;
4493         int r;
4494
4495         r = 0;
4496         switch (chip->chip_id) {
4497         case KVM_IRQCHIP_PIC_MASTER:
4498                 memcpy(&chip->chip.pic, &pic->pics[0],
4499                         sizeof(struct kvm_pic_state));
4500                 break;
4501         case KVM_IRQCHIP_PIC_SLAVE:
4502                 memcpy(&chip->chip.pic, &pic->pics[1],
4503                         sizeof(struct kvm_pic_state));
4504                 break;
4505         case KVM_IRQCHIP_IOAPIC:
4506                 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4507                 break;
4508         default:
4509                 r = -EINVAL;
4510                 break;
4511         }
4512         return r;
4513 }
4514
4515 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4516 {
4517         struct kvm_pic *pic = kvm->arch.vpic;
4518         int r;
4519
4520         r = 0;
4521         switch (chip->chip_id) {
4522         case KVM_IRQCHIP_PIC_MASTER:
4523                 spin_lock(&pic->lock);
4524                 memcpy(&pic->pics[0], &chip->chip.pic,
4525                         sizeof(struct kvm_pic_state));
4526                 spin_unlock(&pic->lock);
4527                 break;
4528         case KVM_IRQCHIP_PIC_SLAVE:
4529                 spin_lock(&pic->lock);
4530                 memcpy(&pic->pics[1], &chip->chip.pic,
4531                         sizeof(struct kvm_pic_state));
4532                 spin_unlock(&pic->lock);
4533                 break;
4534         case KVM_IRQCHIP_IOAPIC:
4535                 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4536                 break;
4537         default:
4538                 r = -EINVAL;
4539                 break;
4540         }
4541         kvm_pic_update_irq(pic);
4542         return r;
4543 }
4544
4545 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4546 {
4547         struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4548
4549         BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4550
4551         mutex_lock(&kps->lock);
4552         memcpy(ps, &kps->channels, sizeof(*ps));
4553         mutex_unlock(&kps->lock);
4554         return 0;
4555 }
4556
4557 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4558 {
4559         int i;
4560         struct kvm_pit *pit = kvm->arch.vpit;
4561
4562         mutex_lock(&pit->pit_state.lock);
4563         memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4564         for (i = 0; i < 3; i++)
4565                 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4566         mutex_unlock(&pit->pit_state.lock);
4567         return 0;
4568 }
4569
4570 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4571 {
4572         mutex_lock(&kvm->arch.vpit->pit_state.lock);
4573         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4574                 sizeof(ps->channels));
4575         ps->flags = kvm->arch.vpit->pit_state.flags;
4576         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4577         memset(&ps->reserved, 0, sizeof(ps->reserved));
4578         return 0;
4579 }
4580
4581 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4582 {
4583         int start = 0;
4584         int i;
4585         u32 prev_legacy, cur_legacy;
4586         struct kvm_pit *pit = kvm->arch.vpit;
4587
4588         mutex_lock(&pit->pit_state.lock);
4589         prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4590         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4591         if (!prev_legacy && cur_legacy)
4592                 start = 1;
4593         memcpy(&pit->pit_state.channels, &ps->channels,
4594                sizeof(pit->pit_state.channels));
4595         pit->pit_state.flags = ps->flags;
4596         for (i = 0; i < 3; i++)
4597                 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4598                                    start && i == 0);
4599         mutex_unlock(&pit->pit_state.lock);
4600         return 0;
4601 }
4602
4603 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4604                                  struct kvm_reinject_control *control)
4605 {
4606         struct kvm_pit *pit = kvm->arch.vpit;
4607
4608         if (!pit)
4609                 return -ENXIO;
4610
4611         /* pit->pit_state.lock was overloaded to prevent userspace from getting
4612          * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4613          * ioctls in parallel.  Use a separate lock if that ioctl isn't rare.
4614          */
4615         mutex_lock(&pit->pit_state.lock);
4616         kvm_pit_set_reinject(pit, control->pit_reinject);
4617         mutex_unlock(&pit->pit_state.lock);
4618
4619         return 0;
4620 }
4621
4622 /**
4623  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4624  * @kvm: kvm instance
4625  * @log: slot id and address to which we copy the log
4626  *
4627  * Steps 1-4 below provide general overview of dirty page logging. See
4628  * kvm_get_dirty_log_protect() function description for additional details.
4629  *
4630  * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4631  * always flush the TLB (step 4) even if previous step failed  and the dirty
4632  * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4633  * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4634  * writes will be marked dirty for next log read.
4635  *
4636  *   1. Take a snapshot of the bit and clear it if needed.
4637  *   2. Write protect the corresponding page.
4638  *   3. Copy the snapshot to the userspace.
4639  *   4. Flush TLB's if needed.
4640  */
4641 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4642 {
4643         bool flush = false;
4644         int r;
4645
4646         mutex_lock(&kvm->slots_lock);
4647
4648         /*
4649          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4650          */
4651         if (kvm_x86_ops->flush_log_dirty)
4652                 kvm_x86_ops->flush_log_dirty(kvm);
4653
4654         r = kvm_get_dirty_log_protect(kvm, log, &flush);
4655
4656         /*
4657          * All the TLBs can be flushed out of mmu lock, see the comments in
4658          * kvm_mmu_slot_remove_write_access().
4659          */
4660         lockdep_assert_held(&kvm->slots_lock);
4661         if (flush)
4662                 kvm_flush_remote_tlbs(kvm);
4663
4664         mutex_unlock(&kvm->slots_lock);
4665         return r;
4666 }
4667
4668 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4669 {
4670         bool flush = false;
4671         int r;
4672
4673         mutex_lock(&kvm->slots_lock);
4674
4675         /*
4676          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4677          */
4678         if (kvm_x86_ops->flush_log_dirty)
4679                 kvm_x86_ops->flush_log_dirty(kvm);
4680
4681         r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4682
4683         /*
4684          * All the TLBs can be flushed out of mmu lock, see the comments in
4685          * kvm_mmu_slot_remove_write_access().
4686          */
4687         lockdep_assert_held(&kvm->slots_lock);
4688         if (flush)
4689                 kvm_flush_remote_tlbs(kvm);
4690
4691         mutex_unlock(&kvm->slots_lock);
4692         return r;
4693 }
4694
4695 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4696                         bool line_status)
4697 {
4698         if (!irqchip_in_kernel(kvm))
4699                 return -ENXIO;
4700
4701         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4702                                         irq_event->irq, irq_event->level,
4703                                         line_status);
4704         return 0;
4705 }
4706
4707 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4708                             struct kvm_enable_cap *cap)
4709 {
4710         int r;
4711
4712         if (cap->flags)
4713                 return -EINVAL;
4714
4715         switch (cap->cap) {
4716         case KVM_CAP_DISABLE_QUIRKS:
4717                 kvm->arch.disabled_quirks = cap->args[0];
4718                 r = 0;
4719                 break;
4720         case KVM_CAP_SPLIT_IRQCHIP: {
4721                 mutex_lock(&kvm->lock);
4722                 r = -EINVAL;
4723                 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4724                         goto split_irqchip_unlock;
4725                 r = -EEXIST;
4726                 if (irqchip_in_kernel(kvm))
4727                         goto split_irqchip_unlock;
4728                 if (kvm->created_vcpus)
4729                         goto split_irqchip_unlock;
4730                 r = kvm_setup_empty_irq_routing(kvm);
4731                 if (r)
4732                         goto split_irqchip_unlock;
4733                 /* Pairs with irqchip_in_kernel. */
4734                 smp_wmb();
4735                 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4736                 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4737                 r = 0;
4738 split_irqchip_unlock:
4739                 mutex_unlock(&kvm->lock);
4740                 break;
4741         }
4742         case KVM_CAP_X2APIC_API:
4743                 r = -EINVAL;
4744                 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4745                         break;
4746
4747                 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4748                         kvm->arch.x2apic_format = true;
4749                 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4750                         kvm->arch.x2apic_broadcast_quirk_disabled = true;
4751
4752                 r = 0;
4753                 break;
4754         case KVM_CAP_X86_DISABLE_EXITS:
4755                 r = -EINVAL;
4756                 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4757                         break;
4758
4759                 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4760                         kvm_can_mwait_in_guest())
4761                         kvm->arch.mwait_in_guest = true;
4762                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4763                         kvm->arch.hlt_in_guest = true;
4764                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4765                         kvm->arch.pause_in_guest = true;
4766                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4767                         kvm->arch.cstate_in_guest = true;
4768                 r = 0;
4769                 break;
4770         case KVM_CAP_MSR_PLATFORM_INFO:
4771                 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4772                 r = 0;
4773                 break;
4774         case KVM_CAP_EXCEPTION_PAYLOAD:
4775                 kvm->arch.exception_payload_enabled = cap->args[0];
4776                 r = 0;
4777                 break;
4778         default:
4779                 r = -EINVAL;
4780                 break;
4781         }
4782         return r;
4783 }
4784
4785 long kvm_arch_vm_ioctl(struct file *filp,
4786                        unsigned int ioctl, unsigned long arg)
4787 {
4788         struct kvm *kvm = filp->private_data;
4789         void __user *argp = (void __user *)arg;
4790         int r = -ENOTTY;
4791         /*
4792          * This union makes it completely explicit to gcc-3.x
4793          * that these two variables' stack usage should be
4794          * combined, not added together.
4795          */
4796         union {
4797                 struct kvm_pit_state ps;
4798                 struct kvm_pit_state2 ps2;
4799                 struct kvm_pit_config pit_config;
4800         } u;
4801
4802         switch (ioctl) {
4803         case KVM_SET_TSS_ADDR:
4804                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4805                 break;
4806         case KVM_SET_IDENTITY_MAP_ADDR: {
4807                 u64 ident_addr;
4808
4809                 mutex_lock(&kvm->lock);
4810                 r = -EINVAL;
4811                 if (kvm->created_vcpus)
4812                         goto set_identity_unlock;
4813                 r = -EFAULT;
4814                 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4815                         goto set_identity_unlock;
4816                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4817 set_identity_unlock:
4818                 mutex_unlock(&kvm->lock);
4819                 break;
4820         }
4821         case KVM_SET_NR_MMU_PAGES:
4822                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4823                 break;
4824         case KVM_GET_NR_MMU_PAGES:
4825                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4826                 break;
4827         case KVM_CREATE_IRQCHIP: {
4828                 mutex_lock(&kvm->lock);
4829
4830                 r = -EEXIST;
4831                 if (irqchip_in_kernel(kvm))
4832                         goto create_irqchip_unlock;
4833
4834                 r = -EINVAL;
4835                 if (kvm->created_vcpus)
4836                         goto create_irqchip_unlock;
4837
4838                 r = kvm_pic_init(kvm);
4839                 if (r)
4840                         goto create_irqchip_unlock;
4841
4842                 r = kvm_ioapic_init(kvm);
4843                 if (r) {
4844                         kvm_pic_destroy(kvm);
4845                         goto create_irqchip_unlock;
4846                 }
4847
4848                 r = kvm_setup_default_irq_routing(kvm);
4849                 if (r) {
4850                         kvm_ioapic_destroy(kvm);
4851                         kvm_pic_destroy(kvm);
4852                         goto create_irqchip_unlock;
4853                 }
4854                 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4855                 smp_wmb();
4856                 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4857         create_irqchip_unlock:
4858                 mutex_unlock(&kvm->lock);
4859                 break;
4860         }
4861         case KVM_CREATE_PIT:
4862                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4863                 goto create_pit;
4864         case KVM_CREATE_PIT2:
4865                 r = -EFAULT;
4866                 if (copy_from_user(&u.pit_config, argp,
4867                                    sizeof(struct kvm_pit_config)))
4868                         goto out;
4869         create_pit:
4870                 mutex_lock(&kvm->lock);
4871                 r = -EEXIST;
4872                 if (kvm->arch.vpit)
4873                         goto create_pit_unlock;
4874                 r = -ENOMEM;
4875                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4876                 if (kvm->arch.vpit)
4877                         r = 0;
4878         create_pit_unlock:
4879                 mutex_unlock(&kvm->lock);
4880                 break;
4881         case KVM_GET_IRQCHIP: {
4882                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4883                 struct kvm_irqchip *chip;
4884
4885                 chip = memdup_user(argp, sizeof(*chip));
4886                 if (IS_ERR(chip)) {
4887                         r = PTR_ERR(chip);
4888                         goto out;
4889                 }
4890
4891                 r = -ENXIO;
4892                 if (!irqchip_kernel(kvm))
4893                         goto get_irqchip_out;
4894                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4895                 if (r)
4896                         goto get_irqchip_out;
4897                 r = -EFAULT;
4898                 if (copy_to_user(argp, chip, sizeof(*chip)))
4899                         goto get_irqchip_out;
4900                 r = 0;
4901         get_irqchip_out:
4902                 kfree(chip);
4903                 break;
4904         }
4905         case KVM_SET_IRQCHIP: {
4906                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4907                 struct kvm_irqchip *chip;
4908
4909                 chip = memdup_user(argp, sizeof(*chip));
4910                 if (IS_ERR(chip)) {
4911                         r = PTR_ERR(chip);
4912                         goto out;
4913                 }
4914
4915                 r = -ENXIO;
4916                 if (!irqchip_kernel(kvm))
4917                         goto set_irqchip_out;
4918                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4919                 if (r)
4920                         goto set_irqchip_out;
4921                 r = 0;
4922         set_irqchip_out:
4923                 kfree(chip);
4924                 break;
4925         }
4926         case KVM_GET_PIT: {
4927                 r = -EFAULT;
4928                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4929                         goto out;
4930                 r = -ENXIO;
4931                 if (!kvm->arch.vpit)
4932                         goto out;
4933                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4934                 if (r)
4935                         goto out;
4936                 r = -EFAULT;
4937                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4938                         goto out;
4939                 r = 0;
4940                 break;
4941         }
4942         case KVM_SET_PIT: {
4943                 r = -EFAULT;
4944                 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
4945                         goto out;
4946                 r = -ENXIO;
4947                 if (!kvm->arch.vpit)
4948                         goto out;
4949                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4950                 break;
4951         }
4952         case KVM_GET_PIT2: {
4953                 r = -ENXIO;
4954                 if (!kvm->arch.vpit)
4955                         goto out;
4956                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4957                 if (r)
4958                         goto out;
4959                 r = -EFAULT;
4960                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4961                         goto out;
4962                 r = 0;
4963                 break;
4964         }
4965         case KVM_SET_PIT2: {
4966                 r = -EFAULT;
4967                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4968                         goto out;
4969                 r = -ENXIO;
4970                 if (!kvm->arch.vpit)
4971                         goto out;
4972                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4973                 break;
4974         }
4975         case KVM_REINJECT_CONTROL: {
4976                 struct kvm_reinject_control control;
4977                 r =  -EFAULT;
4978                 if (copy_from_user(&control, argp, sizeof(control)))
4979                         goto out;
4980                 r = kvm_vm_ioctl_reinject(kvm, &control);
4981                 break;
4982         }
4983         case KVM_SET_BOOT_CPU_ID:
4984                 r = 0;
4985                 mutex_lock(&kvm->lock);
4986                 if (kvm->created_vcpus)
4987                         r = -EBUSY;
4988                 else
4989                         kvm->arch.bsp_vcpu_id = arg;
4990                 mutex_unlock(&kvm->lock);
4991                 break;
4992         case KVM_XEN_HVM_CONFIG: {
4993                 struct kvm_xen_hvm_config xhc;
4994                 r = -EFAULT;
4995                 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4996                         goto out;
4997                 r = -EINVAL;
4998                 if (xhc.flags)
4999                         goto out;
5000                 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5001                 r = 0;
5002                 break;
5003         }
5004         case KVM_SET_CLOCK: {
5005                 struct kvm_clock_data user_ns;
5006                 u64 now_ns;
5007
5008                 r = -EFAULT;
5009                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5010                         goto out;
5011
5012                 r = -EINVAL;
5013                 if (user_ns.flags)
5014                         goto out;
5015
5016                 r = 0;
5017                 /*
5018                  * TODO: userspace has to take care of races with VCPU_RUN, so
5019                  * kvm_gen_update_masterclock() can be cut down to locked
5020                  * pvclock_update_vm_gtod_copy().
5021                  */
5022                 kvm_gen_update_masterclock(kvm);
5023                 now_ns = get_kvmclock_ns(kvm);
5024                 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5025                 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5026                 break;
5027         }
5028         case KVM_GET_CLOCK: {
5029                 struct kvm_clock_data user_ns;
5030                 u64 now_ns;
5031
5032                 now_ns = get_kvmclock_ns(kvm);
5033                 user_ns.clock = now_ns;
5034                 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5035                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5036
5037                 r = -EFAULT;
5038                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5039                         goto out;
5040                 r = 0;
5041                 break;
5042         }
5043         case KVM_MEMORY_ENCRYPT_OP: {
5044                 r = -ENOTTY;
5045                 if (kvm_x86_ops->mem_enc_op)
5046                         r = kvm_x86_ops->mem_enc_op(kvm, argp);
5047                 break;
5048         }
5049         case KVM_MEMORY_ENCRYPT_REG_REGION: {
5050                 struct kvm_enc_region region;
5051
5052                 r = -EFAULT;
5053                 if (copy_from_user(&region, argp, sizeof(region)))
5054                         goto out;
5055
5056                 r = -ENOTTY;
5057                 if (kvm_x86_ops->mem_enc_reg_region)
5058                         r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
5059                 break;
5060         }
5061         case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5062                 struct kvm_enc_region region;
5063
5064                 r = -EFAULT;
5065                 if (copy_from_user(&region, argp, sizeof(region)))
5066                         goto out;
5067
5068                 r = -ENOTTY;
5069                 if (kvm_x86_ops->mem_enc_unreg_region)
5070                         r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
5071                 break;
5072         }
5073         case KVM_HYPERV_EVENTFD: {
5074                 struct kvm_hyperv_eventfd hvevfd;
5075
5076                 r = -EFAULT;
5077                 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5078                         goto out;
5079                 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5080                 break;
5081         }
5082         case KVM_SET_PMU_EVENT_FILTER:
5083                 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5084                 break;
5085         default:
5086                 r = -ENOTTY;
5087         }
5088 out:
5089         return r;
5090 }
5091
5092 static void kvm_init_msr_list(void)
5093 {
5094         struct x86_pmu_capability x86_pmu;
5095         u32 dummy[2];
5096         unsigned i, j;
5097
5098         BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5099                          "Please update the fixed PMCs in msrs_to_save[]");
5100
5101         perf_get_x86_pmu_capability(&x86_pmu);
5102
5103         for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
5104                 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
5105                         continue;
5106
5107                 /*
5108                  * Even MSRs that are valid in the host may not be exposed
5109                  * to the guests in some cases.
5110                  */
5111                 switch (msrs_to_save[i]) {
5112                 case MSR_IA32_BNDCFGS:
5113                         if (!kvm_mpx_supported())
5114                                 continue;
5115                         break;
5116                 case MSR_TSC_AUX:
5117                         if (!kvm_x86_ops->rdtscp_supported())
5118                                 continue;
5119                         break;
5120                 case MSR_IA32_RTIT_CTL:
5121                 case MSR_IA32_RTIT_STATUS:
5122                         if (!kvm_x86_ops->pt_supported())
5123                                 continue;
5124                         break;
5125                 case MSR_IA32_RTIT_CR3_MATCH:
5126                         if (!kvm_x86_ops->pt_supported() ||
5127                             !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5128                                 continue;
5129                         break;
5130                 case MSR_IA32_RTIT_OUTPUT_BASE:
5131                 case MSR_IA32_RTIT_OUTPUT_MASK:
5132                         if (!kvm_x86_ops->pt_supported() ||
5133                                 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5134                                  !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5135                                 continue;
5136                         break;
5137                 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5138                         if (!kvm_x86_ops->pt_supported() ||
5139                                 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
5140                                 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5141                                 continue;
5142                         break;
5143                 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5144                         if (msrs_to_save[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5145                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5146                                 continue;
5147                         break;
5148                 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5149                         if (msrs_to_save[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5150                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5151                                 continue;
5152                 }
5153                 default:
5154                         break;
5155                 }
5156
5157                 if (j < i)
5158                         msrs_to_save[j] = msrs_to_save[i];
5159                 j++;
5160         }
5161         num_msrs_to_save = j;
5162
5163         for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
5164                 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5165                         continue;
5166
5167                 if (j < i)
5168                         emulated_msrs[j] = emulated_msrs[i];
5169                 j++;
5170         }
5171         num_emulated_msrs = j;
5172
5173         for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5174                 struct kvm_msr_entry msr;
5175
5176                 msr.index = msr_based_features[i];
5177                 if (kvm_get_msr_feature(&msr))
5178                         continue;
5179
5180                 if (j < i)
5181                         msr_based_features[j] = msr_based_features[i];
5182                 j++;
5183         }
5184         num_msr_based_features = j;
5185 }
5186
5187 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5188                            const void *v)
5189 {
5190         int handled = 0;
5191         int n;
5192
5193         do {
5194                 n = min(len, 8);
5195                 if (!(lapic_in_kernel(vcpu) &&
5196                       !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5197                     && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5198                         break;
5199                 handled += n;
5200                 addr += n;
5201                 len -= n;
5202                 v += n;
5203         } while (len);
5204
5205         return handled;
5206 }
5207
5208 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5209 {
5210         int handled = 0;
5211         int n;
5212
5213         do {
5214                 n = min(len, 8);
5215                 if (!(lapic_in_kernel(vcpu) &&
5216                       !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5217                                          addr, n, v))
5218                     && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5219                         break;
5220                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5221                 handled += n;
5222                 addr += n;
5223                 len -= n;
5224                 v += n;
5225         } while (len);
5226
5227         return handled;
5228 }
5229
5230 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5231                         struct kvm_segment *var, int seg)
5232 {
5233         kvm_x86_ops->set_segment(vcpu, var, seg);
5234 }
5235
5236 void kvm_get_segment(struct kvm_vcpu *vcpu,
5237                      struct kvm_segment *var, int seg)
5238 {
5239         kvm_x86_ops->get_segment(vcpu, var, seg);
5240 }
5241
5242 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5243                            struct x86_exception *exception)
5244 {
5245         gpa_t t_gpa;
5246
5247         BUG_ON(!mmu_is_nested(vcpu));
5248
5249         /* NPT walks are always user-walks */
5250         access |= PFERR_USER_MASK;
5251         t_gpa  = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5252
5253         return t_gpa;
5254 }
5255
5256 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5257                               struct x86_exception *exception)
5258 {
5259         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5260         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5261 }
5262
5263  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5264                                 struct x86_exception *exception)
5265 {
5266         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5267         access |= PFERR_FETCH_MASK;
5268         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5269 }
5270
5271 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5272                                struct x86_exception *exception)
5273 {
5274         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5275         access |= PFERR_WRITE_MASK;
5276         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5277 }
5278
5279 /* uses this to access any guest's mapped memory without checking CPL */
5280 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5281                                 struct x86_exception *exception)
5282 {
5283         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5284 }
5285
5286 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5287                                       struct kvm_vcpu *vcpu, u32 access,
5288                                       struct x86_exception *exception)
5289 {
5290         void *data = val;
5291         int r = X86EMUL_CONTINUE;
5292
5293         while (bytes) {
5294                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5295                                                             exception);
5296                 unsigned offset = addr & (PAGE_SIZE-1);
5297                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5298                 int ret;
5299
5300                 if (gpa == UNMAPPED_GVA)
5301                         return X86EMUL_PROPAGATE_FAULT;
5302                 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5303                                                offset, toread);
5304                 if (ret < 0) {
5305                         r = X86EMUL_IO_NEEDED;
5306                         goto out;
5307                 }
5308
5309                 bytes -= toread;
5310                 data += toread;
5311                 addr += toread;
5312         }
5313 out:
5314         return r;
5315 }
5316
5317 /* used for instruction fetching */
5318 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5319                                 gva_t addr, void *val, unsigned int bytes,
5320                                 struct x86_exception *exception)
5321 {
5322         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5323         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5324         unsigned offset;
5325         int ret;
5326
5327         /* Inline kvm_read_guest_virt_helper for speed.  */
5328         gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5329                                                     exception);
5330         if (unlikely(gpa == UNMAPPED_GVA))
5331                 return X86EMUL_PROPAGATE_FAULT;
5332
5333         offset = addr & (PAGE_SIZE-1);
5334         if (WARN_ON(offset + bytes > PAGE_SIZE))
5335                 bytes = (unsigned)PAGE_SIZE - offset;
5336         ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5337                                        offset, bytes);
5338         if (unlikely(ret < 0))
5339                 return X86EMUL_IO_NEEDED;
5340
5341         return X86EMUL_CONTINUE;
5342 }
5343
5344 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5345                                gva_t addr, void *val, unsigned int bytes,
5346                                struct x86_exception *exception)
5347 {
5348         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5349
5350         /*
5351          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5352          * is returned, but our callers are not ready for that and they blindly
5353          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5354          * uninitialized kernel stack memory into cr2 and error code.
5355          */
5356         memset(exception, 0, sizeof(*exception));
5357         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5358                                           exception);
5359 }
5360 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5361
5362 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5363                              gva_t addr, void *val, unsigned int bytes,
5364                              struct x86_exception *exception, bool system)
5365 {
5366         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5367         u32 access = 0;
5368
5369         if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5370                 access |= PFERR_USER_MASK;
5371
5372         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5373 }
5374
5375 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5376                 unsigned long addr, void *val, unsigned int bytes)
5377 {
5378         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5379         int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5380
5381         return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5382 }
5383
5384 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5385                                       struct kvm_vcpu *vcpu, u32 access,
5386                                       struct x86_exception *exception)
5387 {
5388         void *data = val;
5389         int r = X86EMUL_CONTINUE;
5390
5391         while (bytes) {
5392                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5393                                                              access,
5394                                                              exception);
5395                 unsigned offset = addr & (PAGE_SIZE-1);
5396                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5397                 int ret;
5398
5399                 if (gpa == UNMAPPED_GVA)
5400                         return X86EMUL_PROPAGATE_FAULT;
5401                 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5402                 if (ret < 0) {
5403                         r = X86EMUL_IO_NEEDED;
5404                         goto out;
5405                 }
5406
5407                 bytes -= towrite;
5408                 data += towrite;
5409                 addr += towrite;
5410         }
5411 out:
5412         return r;
5413 }
5414
5415 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5416                               unsigned int bytes, struct x86_exception *exception,
5417                               bool system)
5418 {
5419         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5420         u32 access = PFERR_WRITE_MASK;
5421
5422         if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5423                 access |= PFERR_USER_MASK;
5424
5425         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5426                                            access, exception);
5427 }
5428
5429 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5430                                 unsigned int bytes, struct x86_exception *exception)
5431 {
5432         /* kvm_write_guest_virt_system can pull in tons of pages. */
5433         vcpu->arch.l1tf_flush_l1d = true;
5434
5435         /*
5436          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5437          * is returned, but our callers are not ready for that and they blindly
5438          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5439          * uninitialized kernel stack memory into cr2 and error code.
5440          */
5441         memset(exception, 0, sizeof(*exception));
5442         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5443                                            PFERR_WRITE_MASK, exception);
5444 }
5445 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5446
5447 int handle_ud(struct kvm_vcpu *vcpu)
5448 {
5449         int emul_type = EMULTYPE_TRAP_UD;
5450         char sig[5]; /* ud2; .ascii "kvm" */
5451         struct x86_exception e;
5452
5453         if (force_emulation_prefix &&
5454             kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5455                                 sig, sizeof(sig), &e) == 0 &&
5456             memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5457                 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5458                 emul_type = EMULTYPE_TRAP_UD_FORCED;
5459         }
5460
5461         return kvm_emulate_instruction(vcpu, emul_type);
5462 }
5463 EXPORT_SYMBOL_GPL(handle_ud);
5464
5465 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5466                             gpa_t gpa, bool write)
5467 {
5468         /* For APIC access vmexit */
5469         if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5470                 return 1;
5471
5472         if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5473                 trace_vcpu_match_mmio(gva, gpa, write, true);
5474                 return 1;
5475         }
5476
5477         return 0;
5478 }
5479
5480 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5481                                 gpa_t *gpa, struct x86_exception *exception,
5482                                 bool write)
5483 {
5484         u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5485                 | (write ? PFERR_WRITE_MASK : 0);
5486
5487         /*
5488          * currently PKRU is only applied to ept enabled guest so
5489          * there is no pkey in EPT page table for L1 guest or EPT
5490          * shadow page table for L2 guest.
5491          */
5492         if (vcpu_match_mmio_gva(vcpu, gva)
5493             && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5494                                  vcpu->arch.mmio_access, 0, access)) {
5495                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5496                                         (gva & (PAGE_SIZE - 1));
5497                 trace_vcpu_match_mmio(gva, *gpa, write, false);
5498                 return 1;
5499         }
5500
5501         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5502
5503         if (*gpa == UNMAPPED_GVA)
5504                 return -1;
5505
5506         return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5507 }
5508
5509 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5510                         const void *val, int bytes)
5511 {
5512         int ret;
5513
5514         ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5515         if (ret < 0)
5516                 return 0;
5517         kvm_page_track_write(vcpu, gpa, val, bytes);
5518         return 1;
5519 }
5520
5521 struct read_write_emulator_ops {
5522         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5523                                   int bytes);
5524         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5525                                   void *val, int bytes);
5526         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5527                                int bytes, void *val);
5528         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5529                                     void *val, int bytes);
5530         bool write;
5531 };
5532
5533 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5534 {
5535         if (vcpu->mmio_read_completed) {
5536                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5537                                vcpu->mmio_fragments[0].gpa, val);
5538                 vcpu->mmio_read_completed = 0;
5539                 return 1;
5540         }
5541
5542         return 0;
5543 }
5544
5545 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5546                         void *val, int bytes)
5547 {
5548         return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5549 }
5550
5551 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5552                          void *val, int bytes)
5553 {
5554         return emulator_write_phys(vcpu, gpa, val, bytes);
5555 }
5556
5557 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5558 {
5559         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5560         return vcpu_mmio_write(vcpu, gpa, bytes, val);
5561 }
5562
5563 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5564                           void *val, int bytes)
5565 {
5566         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5567         return X86EMUL_IO_NEEDED;
5568 }
5569
5570 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5571                            void *val, int bytes)
5572 {
5573         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5574
5575         memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5576         return X86EMUL_CONTINUE;
5577 }
5578
5579 static const struct read_write_emulator_ops read_emultor = {
5580         .read_write_prepare = read_prepare,
5581         .read_write_emulate = read_emulate,
5582         .read_write_mmio = vcpu_mmio_read,
5583         .read_write_exit_mmio = read_exit_mmio,
5584 };
5585
5586 static const struct read_write_emulator_ops write_emultor = {
5587         .read_write_emulate = write_emulate,
5588         .read_write_mmio = write_mmio,
5589         .read_write_exit_mmio = write_exit_mmio,
5590         .write = true,
5591 };
5592
5593 static int emulator_read_write_onepage(unsigned long addr, void *val,
5594                                        unsigned int bytes,
5595                                        struct x86_exception *exception,
5596                                        struct kvm_vcpu *vcpu,
5597                                        const struct read_write_emulator_ops *ops)
5598 {
5599         gpa_t gpa;
5600         int handled, ret;
5601         bool write = ops->write;
5602         struct kvm_mmio_fragment *frag;
5603         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5604
5605         /*
5606          * If the exit was due to a NPF we may already have a GPA.
5607          * If the GPA is present, use it to avoid the GVA to GPA table walk.
5608          * Note, this cannot be used on string operations since string
5609          * operation using rep will only have the initial GPA from the NPF
5610          * occurred.
5611          */
5612         if (vcpu->arch.gpa_available &&
5613             emulator_can_use_gpa(ctxt) &&
5614             (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5615                 gpa = vcpu->arch.gpa_val;
5616                 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5617         } else {
5618                 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5619                 if (ret < 0)
5620                         return X86EMUL_PROPAGATE_FAULT;
5621         }
5622
5623         if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5624                 return X86EMUL_CONTINUE;
5625
5626         /*
5627          * Is this MMIO handled locally?
5628          */
5629         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5630         if (handled == bytes)
5631                 return X86EMUL_CONTINUE;
5632
5633         gpa += handled;
5634         bytes -= handled;
5635         val += handled;
5636
5637         WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5638         frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5639         frag->gpa = gpa;
5640         frag->data = val;
5641         frag->len = bytes;
5642         return X86EMUL_CONTINUE;
5643 }
5644
5645 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5646                         unsigned long addr,
5647                         void *val, unsigned int bytes,
5648                         struct x86_exception *exception,
5649                         const struct read_write_emulator_ops *ops)
5650 {
5651         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5652         gpa_t gpa;
5653         int rc;
5654
5655         if (ops->read_write_prepare &&
5656                   ops->read_write_prepare(vcpu, val, bytes))
5657                 return X86EMUL_CONTINUE;
5658
5659         vcpu->mmio_nr_fragments = 0;
5660
5661         /* Crossing a page boundary? */
5662         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5663                 int now;
5664
5665                 now = -addr & ~PAGE_MASK;
5666                 rc = emulator_read_write_onepage(addr, val, now, exception,
5667                                                  vcpu, ops);
5668
5669                 if (rc != X86EMUL_CONTINUE)
5670                         return rc;
5671                 addr += now;
5672                 if (ctxt->mode != X86EMUL_MODE_PROT64)
5673                         addr = (u32)addr;
5674                 val += now;
5675                 bytes -= now;
5676         }
5677
5678         rc = emulator_read_write_onepage(addr, val, bytes, exception,
5679                                          vcpu, ops);
5680         if (rc != X86EMUL_CONTINUE)
5681                 return rc;
5682
5683         if (!vcpu->mmio_nr_fragments)
5684                 return rc;
5685
5686         gpa = vcpu->mmio_fragments[0].gpa;
5687
5688         vcpu->mmio_needed = 1;
5689         vcpu->mmio_cur_fragment = 0;
5690
5691         vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5692         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5693         vcpu->run->exit_reason = KVM_EXIT_MMIO;
5694         vcpu->run->mmio.phys_addr = gpa;
5695
5696         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5697 }
5698
5699 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5700                                   unsigned long addr,
5701                                   void *val,
5702                                   unsigned int bytes,
5703                                   struct x86_exception *exception)
5704 {
5705         return emulator_read_write(ctxt, addr, val, bytes,
5706                                    exception, &read_emultor);
5707 }
5708
5709 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5710                             unsigned long addr,
5711                             const void *val,
5712                             unsigned int bytes,
5713                             struct x86_exception *exception)
5714 {
5715         return emulator_read_write(ctxt, addr, (void *)val, bytes,
5716                                    exception, &write_emultor);
5717 }
5718
5719 #define CMPXCHG_TYPE(t, ptr, old, new) \
5720         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5721
5722 #ifdef CONFIG_X86_64
5723 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5724 #else
5725 #  define CMPXCHG64(ptr, old, new) \
5726         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5727 #endif
5728
5729 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5730                                      unsigned long addr,
5731                                      const void *old,
5732                                      const void *new,
5733                                      unsigned int bytes,
5734                                      struct x86_exception *exception)
5735 {
5736         struct kvm_host_map map;
5737         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5738         gpa_t gpa;
5739         char *kaddr;
5740         bool exchanged;
5741
5742         /* guests cmpxchg8b have to be emulated atomically */
5743         if (bytes > 8 || (bytes & (bytes - 1)))
5744                 goto emul_write;
5745
5746         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5747
5748         if (gpa == UNMAPPED_GVA ||
5749             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5750                 goto emul_write;
5751
5752         if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5753                 goto emul_write;
5754
5755         if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5756                 goto emul_write;
5757
5758         kaddr = map.hva + offset_in_page(gpa);
5759
5760         switch (bytes) {
5761         case 1:
5762                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5763                 break;
5764         case 2:
5765                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5766                 break;
5767         case 4:
5768                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5769                 break;
5770         case 8:
5771                 exchanged = CMPXCHG64(kaddr, old, new);
5772                 break;
5773         default:
5774                 BUG();
5775         }
5776
5777         kvm_vcpu_unmap(vcpu, &map, true);
5778
5779         if (!exchanged)
5780                 return X86EMUL_CMPXCHG_FAILED;
5781
5782         kvm_page_track_write(vcpu, gpa, new, bytes);
5783
5784         return X86EMUL_CONTINUE;
5785
5786 emul_write:
5787         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5788
5789         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5790 }
5791
5792 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5793 {
5794         int r = 0, i;
5795
5796         for (i = 0; i < vcpu->arch.pio.count; i++) {
5797                 if (vcpu->arch.pio.in)
5798                         r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5799                                             vcpu->arch.pio.size, pd);
5800                 else
5801                         r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5802                                              vcpu->arch.pio.port, vcpu->arch.pio.size,
5803                                              pd);
5804                 if (r)
5805                         break;
5806                 pd += vcpu->arch.pio.size;
5807         }
5808         return r;
5809 }
5810
5811 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5812                                unsigned short port, void *val,
5813                                unsigned int count, bool in)
5814 {
5815         vcpu->arch.pio.port = port;
5816         vcpu->arch.pio.in = in;
5817         vcpu->arch.pio.count  = count;
5818         vcpu->arch.pio.size = size;
5819
5820         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5821                 vcpu->arch.pio.count = 0;
5822                 return 1;
5823         }
5824
5825         vcpu->run->exit_reason = KVM_EXIT_IO;
5826         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5827         vcpu->run->io.size = size;
5828         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5829         vcpu->run->io.count = count;
5830         vcpu->run->io.port = port;
5831
5832         return 0;
5833 }
5834
5835 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5836                                     int size, unsigned short port, void *val,
5837                                     unsigned int count)
5838 {
5839         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5840         int ret;
5841
5842         if (vcpu->arch.pio.count)
5843                 goto data_avail;
5844
5845         memset(vcpu->arch.pio_data, 0, size * count);
5846
5847         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5848         if (ret) {
5849 data_avail:
5850                 memcpy(val, vcpu->arch.pio_data, size * count);
5851                 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5852                 vcpu->arch.pio.count = 0;
5853                 return 1;
5854         }
5855
5856         return 0;
5857 }
5858
5859 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5860                                      int size, unsigned short port,
5861                                      const void *val, unsigned int count)
5862 {
5863         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5864
5865         memcpy(vcpu->arch.pio_data, val, size * count);
5866         trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5867         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5868 }
5869
5870 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5871 {
5872         return kvm_x86_ops->get_segment_base(vcpu, seg);
5873 }
5874
5875 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5876 {
5877         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5878 }
5879
5880 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5881 {
5882         if (!need_emulate_wbinvd(vcpu))
5883                 return X86EMUL_CONTINUE;
5884
5885         if (kvm_x86_ops->has_wbinvd_exit()) {
5886                 int cpu = get_cpu();
5887
5888                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5889                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5890                                 wbinvd_ipi, NULL, 1);
5891                 put_cpu();
5892                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5893         } else
5894                 wbinvd();
5895         return X86EMUL_CONTINUE;
5896 }
5897
5898 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5899 {
5900         kvm_emulate_wbinvd_noskip(vcpu);
5901         return kvm_skip_emulated_instruction(vcpu);
5902 }
5903 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5904
5905
5906
5907 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5908 {
5909         kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5910 }
5911
5912 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5913                            unsigned long *dest)
5914 {
5915         return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5916 }
5917
5918 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5919                            unsigned long value)
5920 {
5921
5922         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5923 }
5924
5925 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5926 {
5927         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5928 }
5929
5930 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5931 {
5932         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5933         unsigned long value;
5934
5935         switch (cr) {
5936         case 0:
5937                 value = kvm_read_cr0(vcpu);
5938                 break;
5939         case 2:
5940                 value = vcpu->arch.cr2;
5941                 break;
5942         case 3:
5943                 value = kvm_read_cr3(vcpu);
5944                 break;
5945         case 4:
5946                 value = kvm_read_cr4(vcpu);
5947                 break;
5948         case 8:
5949                 value = kvm_get_cr8(vcpu);
5950                 break;
5951         default:
5952                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5953                 return 0;
5954         }
5955
5956         return value;
5957 }
5958
5959 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5960 {
5961         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5962         int res = 0;
5963
5964         switch (cr) {
5965         case 0:
5966                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5967                 break;
5968         case 2:
5969                 vcpu->arch.cr2 = val;
5970                 break;
5971         case 3:
5972                 res = kvm_set_cr3(vcpu, val);
5973                 break;
5974         case 4:
5975                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5976                 break;
5977         case 8:
5978                 res = kvm_set_cr8(vcpu, val);
5979                 break;
5980         default:
5981                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5982                 res = -1;
5983         }
5984
5985         return res;
5986 }
5987
5988 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5989 {
5990         return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5991 }
5992
5993 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5994 {
5995         kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5996 }
5997
5998 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5999 {
6000         kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
6001 }
6002
6003 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6004 {
6005         kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
6006 }
6007
6008 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6009 {
6010         kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
6011 }
6012
6013 static unsigned long emulator_get_cached_segment_base(
6014         struct x86_emulate_ctxt *ctxt, int seg)
6015 {
6016         return get_segment_base(emul_to_vcpu(ctxt), seg);
6017 }
6018
6019 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6020                                  struct desc_struct *desc, u32 *base3,
6021                                  int seg)
6022 {
6023         struct kvm_segment var;
6024
6025         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6026         *selector = var.selector;
6027
6028         if (var.unusable) {
6029                 memset(desc, 0, sizeof(*desc));
6030                 if (base3)
6031                         *base3 = 0;
6032                 return false;
6033         }
6034
6035         if (var.g)
6036                 var.limit >>= 12;
6037         set_desc_limit(desc, var.limit);
6038         set_desc_base(desc, (unsigned long)var.base);
6039 #ifdef CONFIG_X86_64
6040         if (base3)
6041                 *base3 = var.base >> 32;
6042 #endif
6043         desc->type = var.type;
6044         desc->s = var.s;
6045         desc->dpl = var.dpl;
6046         desc->p = var.present;
6047         desc->avl = var.avl;
6048         desc->l = var.l;
6049         desc->d = var.db;
6050         desc->g = var.g;
6051
6052         return true;
6053 }
6054
6055 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6056                                  struct desc_struct *desc, u32 base3,
6057                                  int seg)
6058 {
6059         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6060         struct kvm_segment var;
6061
6062         var.selector = selector;
6063         var.base = get_desc_base(desc);
6064 #ifdef CONFIG_X86_64
6065         var.base |= ((u64)base3) << 32;
6066 #endif
6067         var.limit = get_desc_limit(desc);
6068         if (desc->g)
6069                 var.limit = (var.limit << 12) | 0xfff;
6070         var.type = desc->type;
6071         var.dpl = desc->dpl;
6072         var.db = desc->d;
6073         var.s = desc->s;
6074         var.l = desc->l;
6075         var.g = desc->g;
6076         var.avl = desc->avl;
6077         var.present = desc->p;
6078         var.unusable = !var.present;
6079         var.padding = 0;
6080
6081         kvm_set_segment(vcpu, &var, seg);
6082         return;
6083 }
6084
6085 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6086                             u32 msr_index, u64 *pdata)
6087 {
6088         return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6089 }
6090
6091 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6092                             u32 msr_index, u64 data)
6093 {
6094         return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6095 }
6096
6097 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6098 {
6099         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6100
6101         return vcpu->arch.smbase;
6102 }
6103
6104 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6105 {
6106         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6107
6108         vcpu->arch.smbase = smbase;
6109 }
6110
6111 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6112                               u32 pmc)
6113 {
6114         return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
6115 }
6116
6117 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6118                              u32 pmc, u64 *pdata)
6119 {
6120         return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6121 }
6122
6123 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6124 {
6125         emul_to_vcpu(ctxt)->arch.halt_request = 1;
6126 }
6127
6128 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6129                               struct x86_instruction_info *info,
6130                               enum x86_intercept_stage stage)
6131 {
6132         return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
6133 }
6134
6135 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6136                         u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
6137 {
6138         return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
6139 }
6140
6141 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6142 {
6143         return kvm_register_read(emul_to_vcpu(ctxt), reg);
6144 }
6145
6146 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6147 {
6148         kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6149 }
6150
6151 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6152 {
6153         kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6154 }
6155
6156 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6157 {
6158         return emul_to_vcpu(ctxt)->arch.hflags;
6159 }
6160
6161 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6162 {
6163         emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6164 }
6165
6166 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6167                                   const char *smstate)
6168 {
6169         return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6170 }
6171
6172 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6173 {
6174         kvm_smm_changed(emul_to_vcpu(ctxt));
6175 }
6176
6177 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6178 {
6179         return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6180 }
6181
6182 static const struct x86_emulate_ops emulate_ops = {
6183         .read_gpr            = emulator_read_gpr,
6184         .write_gpr           = emulator_write_gpr,
6185         .read_std            = emulator_read_std,
6186         .write_std           = emulator_write_std,
6187         .read_phys           = kvm_read_guest_phys_system,
6188         .fetch               = kvm_fetch_guest_virt,
6189         .read_emulated       = emulator_read_emulated,
6190         .write_emulated      = emulator_write_emulated,
6191         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
6192         .invlpg              = emulator_invlpg,
6193         .pio_in_emulated     = emulator_pio_in_emulated,
6194         .pio_out_emulated    = emulator_pio_out_emulated,
6195         .get_segment         = emulator_get_segment,
6196         .set_segment         = emulator_set_segment,
6197         .get_cached_segment_base = emulator_get_cached_segment_base,
6198         .get_gdt             = emulator_get_gdt,
6199         .get_idt             = emulator_get_idt,
6200         .set_gdt             = emulator_set_gdt,
6201         .set_idt             = emulator_set_idt,
6202         .get_cr              = emulator_get_cr,
6203         .set_cr              = emulator_set_cr,
6204         .cpl                 = emulator_get_cpl,
6205         .get_dr              = emulator_get_dr,
6206         .set_dr              = emulator_set_dr,
6207         .get_smbase          = emulator_get_smbase,
6208         .set_smbase          = emulator_set_smbase,
6209         .set_msr             = emulator_set_msr,
6210         .get_msr             = emulator_get_msr,
6211         .check_pmc           = emulator_check_pmc,
6212         .read_pmc            = emulator_read_pmc,
6213         .halt                = emulator_halt,
6214         .wbinvd              = emulator_wbinvd,
6215         .fix_hypercall       = emulator_fix_hypercall,
6216         .intercept           = emulator_intercept,
6217         .get_cpuid           = emulator_get_cpuid,
6218         .set_nmi_mask        = emulator_set_nmi_mask,
6219         .get_hflags          = emulator_get_hflags,
6220         .set_hflags          = emulator_set_hflags,
6221         .pre_leave_smm       = emulator_pre_leave_smm,
6222         .post_leave_smm      = emulator_post_leave_smm,
6223         .set_xcr             = emulator_set_xcr,
6224 };
6225
6226 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6227 {
6228         u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6229         /*
6230          * an sti; sti; sequence only disable interrupts for the first
6231          * instruction. So, if the last instruction, be it emulated or
6232          * not, left the system with the INT_STI flag enabled, it
6233          * means that the last instruction is an sti. We should not
6234          * leave the flag on in this case. The same goes for mov ss
6235          */
6236         if (int_shadow & mask)
6237                 mask = 0;
6238         if (unlikely(int_shadow || mask)) {
6239                 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6240                 if (!mask)
6241                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6242         }
6243 }
6244
6245 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6246 {
6247         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6248         if (ctxt->exception.vector == PF_VECTOR)
6249                 return kvm_propagate_fault(vcpu, &ctxt->exception);
6250
6251         if (ctxt->exception.error_code_valid)
6252                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6253                                       ctxt->exception.error_code);
6254         else
6255                 kvm_queue_exception(vcpu, ctxt->exception.vector);
6256         return false;
6257 }
6258
6259 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6260 {
6261         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6262         int cs_db, cs_l;
6263
6264         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6265
6266         ctxt->eflags = kvm_get_rflags(vcpu);
6267         ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6268
6269         ctxt->eip = kvm_rip_read(vcpu);
6270         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
6271                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
6272                      (cs_l && is_long_mode(vcpu))       ? X86EMUL_MODE_PROT64 :
6273                      cs_db                              ? X86EMUL_MODE_PROT32 :
6274                                                           X86EMUL_MODE_PROT16;
6275         BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6276         BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6277         BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6278
6279         init_decode_cache(ctxt);
6280         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6281 }
6282
6283 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6284 {
6285         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6286         int ret;
6287
6288         init_emulate_ctxt(vcpu);
6289
6290         ctxt->op_bytes = 2;
6291         ctxt->ad_bytes = 2;
6292         ctxt->_eip = ctxt->eip + inc_eip;
6293         ret = emulate_int_real(ctxt, irq);
6294
6295         if (ret != X86EMUL_CONTINUE) {
6296                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6297         } else {
6298                 ctxt->eip = ctxt->_eip;
6299                 kvm_rip_write(vcpu, ctxt->eip);
6300                 kvm_set_rflags(vcpu, ctxt->eflags);
6301         }
6302 }
6303 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6304
6305 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6306 {
6307         ++vcpu->stat.insn_emulation_fail;
6308         trace_kvm_emulate_insn_failed(vcpu);
6309
6310         if (emulation_type & EMULTYPE_VMWARE_GP) {
6311                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6312                 return 1;
6313         }
6314
6315         if (emulation_type & EMULTYPE_SKIP) {
6316                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6317                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6318                 vcpu->run->internal.ndata = 0;
6319                 return 0;
6320         }
6321
6322         kvm_queue_exception(vcpu, UD_VECTOR);
6323
6324         if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6325                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6326                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6327                 vcpu->run->internal.ndata = 0;
6328                 return 0;
6329         }
6330
6331         return 1;
6332 }
6333
6334 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
6335                                   bool write_fault_to_shadow_pgtable,
6336                                   int emulation_type)
6337 {
6338         gpa_t gpa = cr2;
6339         kvm_pfn_t pfn;
6340
6341         if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6342                 return false;
6343
6344         if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6345                 return false;
6346
6347         if (!vcpu->arch.mmu->direct_map) {
6348                 /*
6349                  * Write permission should be allowed since only
6350                  * write access need to be emulated.
6351                  */
6352                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6353
6354                 /*
6355                  * If the mapping is invalid in guest, let cpu retry
6356                  * it to generate fault.
6357                  */
6358                 if (gpa == UNMAPPED_GVA)
6359                         return true;
6360         }
6361
6362         /*
6363          * Do not retry the unhandleable instruction if it faults on the
6364          * readonly host memory, otherwise it will goto a infinite loop:
6365          * retry instruction -> write #PF -> emulation fail -> retry
6366          * instruction -> ...
6367          */
6368         pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6369
6370         /*
6371          * If the instruction failed on the error pfn, it can not be fixed,
6372          * report the error to userspace.
6373          */
6374         if (is_error_noslot_pfn(pfn))
6375                 return false;
6376
6377         kvm_release_pfn_clean(pfn);
6378
6379         /* The instructions are well-emulated on direct mmu. */
6380         if (vcpu->arch.mmu->direct_map) {
6381                 unsigned int indirect_shadow_pages;
6382
6383                 spin_lock(&vcpu->kvm->mmu_lock);
6384                 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6385                 spin_unlock(&vcpu->kvm->mmu_lock);
6386
6387                 if (indirect_shadow_pages)
6388                         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6389
6390                 return true;
6391         }
6392
6393         /*
6394          * if emulation was due to access to shadowed page table
6395          * and it failed try to unshadow page and re-enter the
6396          * guest to let CPU execute the instruction.
6397          */
6398         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6399
6400         /*
6401          * If the access faults on its page table, it can not
6402          * be fixed by unprotecting shadow page and it should
6403          * be reported to userspace.
6404          */
6405         return !write_fault_to_shadow_pgtable;
6406 }
6407
6408 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6409                               unsigned long cr2,  int emulation_type)
6410 {
6411         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6412         unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6413
6414         last_retry_eip = vcpu->arch.last_retry_eip;
6415         last_retry_addr = vcpu->arch.last_retry_addr;
6416
6417         /*
6418          * If the emulation is caused by #PF and it is non-page_table
6419          * writing instruction, it means the VM-EXIT is caused by shadow
6420          * page protected, we can zap the shadow page and retry this
6421          * instruction directly.
6422          *
6423          * Note: if the guest uses a non-page-table modifying instruction
6424          * on the PDE that points to the instruction, then we will unmap
6425          * the instruction and go to an infinite loop. So, we cache the
6426          * last retried eip and the last fault address, if we meet the eip
6427          * and the address again, we can break out of the potential infinite
6428          * loop.
6429          */
6430         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6431
6432         if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6433                 return false;
6434
6435         if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6436                 return false;
6437
6438         if (x86_page_table_writing_insn(ctxt))
6439                 return false;
6440
6441         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6442                 return false;
6443
6444         vcpu->arch.last_retry_eip = ctxt->eip;
6445         vcpu->arch.last_retry_addr = cr2;
6446
6447         if (!vcpu->arch.mmu->direct_map)
6448                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6449
6450         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6451
6452         return true;
6453 }
6454
6455 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6456 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6457
6458 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6459 {
6460         if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6461                 /* This is a good place to trace that we are exiting SMM.  */
6462                 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6463
6464                 /* Process a latched INIT or SMI, if any.  */
6465                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6466         }
6467
6468         kvm_mmu_reset_context(vcpu);
6469 }
6470
6471 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6472                                 unsigned long *db)
6473 {
6474         u32 dr6 = 0;
6475         int i;
6476         u32 enable, rwlen;
6477
6478         enable = dr7;
6479         rwlen = dr7 >> 16;
6480         for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6481                 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6482                         dr6 |= (1 << i);
6483         return dr6;
6484 }
6485
6486 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6487 {
6488         struct kvm_run *kvm_run = vcpu->run;
6489
6490         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6491                 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6492                 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6493                 kvm_run->debug.arch.exception = DB_VECTOR;
6494                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6495                 return 0;
6496         }
6497         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6498         return 1;
6499 }
6500
6501 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6502 {
6503         unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6504         int r;
6505
6506         r = kvm_x86_ops->skip_emulated_instruction(vcpu);
6507         if (unlikely(!r))
6508                 return 0;
6509
6510         /*
6511          * rflags is the old, "raw" value of the flags.  The new value has
6512          * not been saved yet.
6513          *
6514          * This is correct even for TF set by the guest, because "the
6515          * processor will not generate this exception after the instruction
6516          * that sets the TF flag".
6517          */
6518         if (unlikely(rflags & X86_EFLAGS_TF))
6519                 r = kvm_vcpu_do_singlestep(vcpu);
6520         return r;
6521 }
6522 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6523
6524 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6525 {
6526         if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6527             (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6528                 struct kvm_run *kvm_run = vcpu->run;
6529                 unsigned long eip = kvm_get_linear_rip(vcpu);
6530                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6531                                            vcpu->arch.guest_debug_dr7,
6532                                            vcpu->arch.eff_db);
6533
6534                 if (dr6 != 0) {
6535                         kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6536                         kvm_run->debug.arch.pc = eip;
6537                         kvm_run->debug.arch.exception = DB_VECTOR;
6538                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
6539                         *r = 0;
6540                         return true;
6541                 }
6542         }
6543
6544         if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6545             !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6546                 unsigned long eip = kvm_get_linear_rip(vcpu);
6547                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6548                                            vcpu->arch.dr7,
6549                                            vcpu->arch.db);
6550
6551                 if (dr6 != 0) {
6552                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6553                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
6554                         kvm_queue_exception(vcpu, DB_VECTOR);
6555                         *r = 1;
6556                         return true;
6557                 }
6558         }
6559
6560         return false;
6561 }
6562
6563 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6564 {
6565         switch (ctxt->opcode_len) {
6566         case 1:
6567                 switch (ctxt->b) {
6568                 case 0xe4:      /* IN */
6569                 case 0xe5:
6570                 case 0xec:
6571                 case 0xed:
6572                 case 0xe6:      /* OUT */
6573                 case 0xe7:
6574                 case 0xee:
6575                 case 0xef:
6576                 case 0x6c:      /* INS */
6577                 case 0x6d:
6578                 case 0x6e:      /* OUTS */
6579                 case 0x6f:
6580                         return true;
6581                 }
6582                 break;
6583         case 2:
6584                 switch (ctxt->b) {
6585                 case 0x33:      /* RDPMC */
6586                         return true;
6587                 }
6588                 break;
6589         }
6590
6591         return false;
6592 }
6593
6594 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6595                             unsigned long cr2,
6596                             int emulation_type,
6597                             void *insn,
6598                             int insn_len)
6599 {
6600         int r;
6601         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6602         bool writeback = true;
6603         bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6604
6605         vcpu->arch.l1tf_flush_l1d = true;
6606
6607         /*
6608          * Clear write_fault_to_shadow_pgtable here to ensure it is
6609          * never reused.
6610          */
6611         vcpu->arch.write_fault_to_shadow_pgtable = false;
6612         kvm_clear_exception_queue(vcpu);
6613
6614         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6615                 init_emulate_ctxt(vcpu);
6616
6617                 /*
6618                  * We will reenter on the same instruction since
6619                  * we do not set complete_userspace_io.  This does not
6620                  * handle watchpoints yet, those would be handled in
6621                  * the emulate_ops.
6622                  */
6623                 if (!(emulation_type & EMULTYPE_SKIP) &&
6624                     kvm_vcpu_check_breakpoint(vcpu, &r))
6625                         return r;
6626
6627                 ctxt->interruptibility = 0;
6628                 ctxt->have_exception = false;
6629                 ctxt->exception.vector = -1;
6630                 ctxt->perm_ok = false;
6631
6632                 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6633
6634                 r = x86_decode_insn(ctxt, insn, insn_len);
6635
6636                 trace_kvm_emulate_insn_start(vcpu);
6637                 ++vcpu->stat.insn_emulation;
6638                 if (r != EMULATION_OK)  {
6639                         if ((emulation_type & EMULTYPE_TRAP_UD) ||
6640                             (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6641                                 kvm_queue_exception(vcpu, UD_VECTOR);
6642                                 return 1;
6643                         }
6644                         if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6645                                                 emulation_type))
6646                                 return 1;
6647                         if (ctxt->have_exception) {
6648                                 /*
6649                                  * #UD should result in just EMULATION_FAILED, and trap-like
6650                                  * exception should not be encountered during decode.
6651                                  */
6652                                 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6653                                              exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6654                                 inject_emulated_exception(vcpu);
6655                                 return 1;
6656                         }
6657                         return handle_emulation_failure(vcpu, emulation_type);
6658                 }
6659         }
6660
6661         if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6662             !is_vmware_backdoor_opcode(ctxt)) {
6663                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6664                 return 1;
6665         }
6666
6667         /*
6668          * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6669          * for kvm_skip_emulated_instruction().  The caller is responsible for
6670          * updating interruptibility state and injecting single-step #DBs.
6671          */
6672         if (emulation_type & EMULTYPE_SKIP) {
6673                 kvm_rip_write(vcpu, ctxt->_eip);
6674                 if (ctxt->eflags & X86_EFLAGS_RF)
6675                         kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6676                 return 1;
6677         }
6678
6679         if (retry_instruction(ctxt, cr2, emulation_type))
6680                 return 1;
6681
6682         /* this is needed for vmware backdoor interface to work since it
6683            changes registers values  during IO operation */
6684         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6685                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6686                 emulator_invalidate_register_cache(ctxt);
6687         }
6688
6689 restart:
6690         /* Save the faulting GPA (cr2) in the address field */
6691         ctxt->exception.address = cr2;
6692
6693         r = x86_emulate_insn(ctxt);
6694
6695         if (r == EMULATION_INTERCEPTED)
6696                 return 1;
6697
6698         if (r == EMULATION_FAILED) {
6699                 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6700                                         emulation_type))
6701                         return 1;
6702
6703                 return handle_emulation_failure(vcpu, emulation_type);
6704         }
6705
6706         if (ctxt->have_exception) {
6707                 r = 1;
6708                 if (inject_emulated_exception(vcpu))
6709                         return r;
6710         } else if (vcpu->arch.pio.count) {
6711                 if (!vcpu->arch.pio.in) {
6712                         /* FIXME: return into emulator if single-stepping.  */
6713                         vcpu->arch.pio.count = 0;
6714                 } else {
6715                         writeback = false;
6716                         vcpu->arch.complete_userspace_io = complete_emulated_pio;
6717                 }
6718                 r = 0;
6719         } else if (vcpu->mmio_needed) {
6720                 ++vcpu->stat.mmio_exits;
6721
6722                 if (!vcpu->mmio_is_write)
6723                         writeback = false;
6724                 r = 0;
6725                 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6726         } else if (r == EMULATION_RESTART)
6727                 goto restart;
6728         else
6729                 r = 1;
6730
6731         if (writeback) {
6732                 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6733                 toggle_interruptibility(vcpu, ctxt->interruptibility);
6734                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6735                 if (!ctxt->have_exception ||
6736                     exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6737                         kvm_rip_write(vcpu, ctxt->eip);
6738                         if (r && ctxt->tf)
6739                                 r = kvm_vcpu_do_singlestep(vcpu);
6740                         __kvm_set_rflags(vcpu, ctxt->eflags);
6741                 }
6742
6743                 /*
6744                  * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6745                  * do nothing, and it will be requested again as soon as
6746                  * the shadow expires.  But we still need to check here,
6747                  * because POPF has no interrupt shadow.
6748                  */
6749                 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6750                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6751         } else
6752                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6753
6754         return r;
6755 }
6756
6757 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6758 {
6759         return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6760 }
6761 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6762
6763 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6764                                         void *insn, int insn_len)
6765 {
6766         return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6767 }
6768 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6769
6770 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6771 {
6772         vcpu->arch.pio.count = 0;
6773         return 1;
6774 }
6775
6776 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6777 {
6778         vcpu->arch.pio.count = 0;
6779
6780         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6781                 return 1;
6782
6783         return kvm_skip_emulated_instruction(vcpu);
6784 }
6785
6786 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6787                             unsigned short port)
6788 {
6789         unsigned long val = kvm_rax_read(vcpu);
6790         int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6791                                             size, port, &val, 1);
6792         if (ret)
6793                 return ret;
6794
6795         /*
6796          * Workaround userspace that relies on old KVM behavior of %rip being
6797          * incremented prior to exiting to userspace to handle "OUT 0x7e".
6798          */
6799         if (port == 0x7e &&
6800             kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6801                 vcpu->arch.complete_userspace_io =
6802                         complete_fast_pio_out_port_0x7e;
6803                 kvm_skip_emulated_instruction(vcpu);
6804         } else {
6805                 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6806                 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6807         }
6808         return 0;
6809 }
6810
6811 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6812 {
6813         unsigned long val;
6814
6815         /* We should only ever be called with arch.pio.count equal to 1 */
6816         BUG_ON(vcpu->arch.pio.count != 1);
6817
6818         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6819                 vcpu->arch.pio.count = 0;
6820                 return 1;
6821         }
6822
6823         /* For size less than 4 we merge, else we zero extend */
6824         val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6825
6826         /*
6827          * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6828          * the copy and tracing
6829          */
6830         emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6831                                  vcpu->arch.pio.port, &val, 1);
6832         kvm_rax_write(vcpu, val);
6833
6834         return kvm_skip_emulated_instruction(vcpu);
6835 }
6836
6837 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6838                            unsigned short port)
6839 {
6840         unsigned long val;
6841         int ret;
6842
6843         /* For size less than 4 we merge, else we zero extend */
6844         val = (size < 4) ? kvm_rax_read(vcpu) : 0;
6845
6846         ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6847                                        &val, 1);
6848         if (ret) {
6849                 kvm_rax_write(vcpu, val);
6850                 return ret;
6851         }
6852
6853         vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6854         vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6855
6856         return 0;
6857 }
6858
6859 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6860 {
6861         int ret;
6862
6863         if (in)
6864                 ret = kvm_fast_pio_in(vcpu, size, port);
6865         else
6866                 ret = kvm_fast_pio_out(vcpu, size, port);
6867         return ret && kvm_skip_emulated_instruction(vcpu);
6868 }
6869 EXPORT_SYMBOL_GPL(kvm_fast_pio);
6870
6871 static int kvmclock_cpu_down_prep(unsigned int cpu)
6872 {
6873         __this_cpu_write(cpu_tsc_khz, 0);
6874         return 0;
6875 }
6876
6877 static void tsc_khz_changed(void *data)
6878 {
6879         struct cpufreq_freqs *freq = data;
6880         unsigned long khz = 0;
6881
6882         if (data)
6883                 khz = freq->new;
6884         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6885                 khz = cpufreq_quick_get(raw_smp_processor_id());
6886         if (!khz)
6887                 khz = tsc_khz;
6888         __this_cpu_write(cpu_tsc_khz, khz);
6889 }
6890
6891 #ifdef CONFIG_X86_64
6892 static void kvm_hyperv_tsc_notifier(void)
6893 {
6894         struct kvm *kvm;
6895         struct kvm_vcpu *vcpu;
6896         int cpu;
6897
6898         mutex_lock(&kvm_lock);
6899         list_for_each_entry(kvm, &vm_list, vm_list)
6900                 kvm_make_mclock_inprogress_request(kvm);
6901
6902         hyperv_stop_tsc_emulation();
6903
6904         /* TSC frequency always matches when on Hyper-V */
6905         for_each_present_cpu(cpu)
6906                 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6907         kvm_max_guest_tsc_khz = tsc_khz;
6908
6909         list_for_each_entry(kvm, &vm_list, vm_list) {
6910                 struct kvm_arch *ka = &kvm->arch;
6911
6912                 spin_lock(&ka->pvclock_gtod_sync_lock);
6913
6914                 pvclock_update_vm_gtod_copy(kvm);
6915
6916                 kvm_for_each_vcpu(cpu, vcpu, kvm)
6917                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6918
6919                 kvm_for_each_vcpu(cpu, vcpu, kvm)
6920                         kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6921
6922                 spin_unlock(&ka->pvclock_gtod_sync_lock);
6923         }
6924         mutex_unlock(&kvm_lock);
6925 }
6926 #endif
6927
6928 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
6929 {
6930         struct kvm *kvm;
6931         struct kvm_vcpu *vcpu;
6932         int i, send_ipi = 0;
6933
6934         /*
6935          * We allow guests to temporarily run on slowing clocks,
6936          * provided we notify them after, or to run on accelerating
6937          * clocks, provided we notify them before.  Thus time never
6938          * goes backwards.
6939          *
6940          * However, we have a problem.  We can't atomically update
6941          * the frequency of a given CPU from this function; it is
6942          * merely a notifier, which can be called from any CPU.
6943          * Changing the TSC frequency at arbitrary points in time
6944          * requires a recomputation of local variables related to
6945          * the TSC for each VCPU.  We must flag these local variables
6946          * to be updated and be sure the update takes place with the
6947          * new frequency before any guests proceed.
6948          *
6949          * Unfortunately, the combination of hotplug CPU and frequency
6950          * change creates an intractable locking scenario; the order
6951          * of when these callouts happen is undefined with respect to
6952          * CPU hotplug, and they can race with each other.  As such,
6953          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6954          * undefined; you can actually have a CPU frequency change take
6955          * place in between the computation of X and the setting of the
6956          * variable.  To protect against this problem, all updates of
6957          * the per_cpu tsc_khz variable are done in an interrupt
6958          * protected IPI, and all callers wishing to update the value
6959          * must wait for a synchronous IPI to complete (which is trivial
6960          * if the caller is on the CPU already).  This establishes the
6961          * necessary total order on variable updates.
6962          *
6963          * Note that because a guest time update may take place
6964          * anytime after the setting of the VCPU's request bit, the
6965          * correct TSC value must be set before the request.  However,
6966          * to ensure the update actually makes it to any guest which
6967          * starts running in hardware virtualization between the set
6968          * and the acquisition of the spinlock, we must also ping the
6969          * CPU after setting the request bit.
6970          *
6971          */
6972
6973         smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6974
6975         mutex_lock(&kvm_lock);
6976         list_for_each_entry(kvm, &vm_list, vm_list) {
6977                 kvm_for_each_vcpu(i, vcpu, kvm) {
6978                         if (vcpu->cpu != cpu)
6979                                 continue;
6980                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6981                         if (vcpu->cpu != raw_smp_processor_id())
6982                                 send_ipi = 1;
6983                 }
6984         }
6985         mutex_unlock(&kvm_lock);
6986
6987         if (freq->old < freq->new && send_ipi) {
6988                 /*
6989                  * We upscale the frequency.  Must make the guest
6990                  * doesn't see old kvmclock values while running with
6991                  * the new frequency, otherwise we risk the guest sees
6992                  * time go backwards.
6993                  *
6994                  * In case we update the frequency for another cpu
6995                  * (which might be in guest context) send an interrupt
6996                  * to kick the cpu out of guest context.  Next time
6997                  * guest context is entered kvmclock will be updated,
6998                  * so the guest will not see stale values.
6999                  */
7000                 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7001         }
7002 }
7003
7004 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7005                                      void *data)
7006 {
7007         struct cpufreq_freqs *freq = data;
7008         int cpu;
7009
7010         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7011                 return 0;
7012         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7013                 return 0;
7014
7015         for_each_cpu(cpu, freq->policy->cpus)
7016                 __kvmclock_cpufreq_notifier(freq, cpu);
7017
7018         return 0;
7019 }
7020
7021 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7022         .notifier_call  = kvmclock_cpufreq_notifier
7023 };
7024
7025 static int kvmclock_cpu_online(unsigned int cpu)
7026 {
7027         tsc_khz_changed(NULL);
7028         return 0;
7029 }
7030
7031 static void kvm_timer_init(void)
7032 {
7033         max_tsc_khz = tsc_khz;
7034
7035         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7036 #ifdef CONFIG_CPU_FREQ
7037                 struct cpufreq_policy policy;
7038                 int cpu;
7039
7040                 memset(&policy, 0, sizeof(policy));
7041                 cpu = get_cpu();
7042                 cpufreq_get_policy(&policy, cpu);
7043                 if (policy.cpuinfo.max_freq)
7044                         max_tsc_khz = policy.cpuinfo.max_freq;
7045                 put_cpu();
7046 #endif
7047                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7048                                           CPUFREQ_TRANSITION_NOTIFIER);
7049         }
7050
7051         cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7052                           kvmclock_cpu_online, kvmclock_cpu_down_prep);
7053 }
7054
7055 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7056 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7057
7058 int kvm_is_in_guest(void)
7059 {
7060         return __this_cpu_read(current_vcpu) != NULL;
7061 }
7062
7063 static int kvm_is_user_mode(void)
7064 {
7065         int user_mode = 3;
7066
7067         if (__this_cpu_read(current_vcpu))
7068                 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
7069
7070         return user_mode != 0;
7071 }
7072
7073 static unsigned long kvm_get_guest_ip(void)
7074 {
7075         unsigned long ip = 0;
7076
7077         if (__this_cpu_read(current_vcpu))
7078                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7079
7080         return ip;
7081 }
7082
7083 static void kvm_handle_intel_pt_intr(void)
7084 {
7085         struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7086
7087         kvm_make_request(KVM_REQ_PMI, vcpu);
7088         __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7089                         (unsigned long *)&vcpu->arch.pmu.global_status);
7090 }
7091
7092 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7093         .is_in_guest            = kvm_is_in_guest,
7094         .is_user_mode           = kvm_is_user_mode,
7095         .get_guest_ip           = kvm_get_guest_ip,
7096         .handle_intel_pt_intr   = kvm_handle_intel_pt_intr,
7097 };
7098
7099 #ifdef CONFIG_X86_64
7100 static void pvclock_gtod_update_fn(struct work_struct *work)
7101 {
7102         struct kvm *kvm;
7103
7104         struct kvm_vcpu *vcpu;
7105         int i;
7106
7107         mutex_lock(&kvm_lock);
7108         list_for_each_entry(kvm, &vm_list, vm_list)
7109                 kvm_for_each_vcpu(i, vcpu, kvm)
7110                         kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7111         atomic_set(&kvm_guest_has_master_clock, 0);
7112         mutex_unlock(&kvm_lock);
7113 }
7114
7115 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7116
7117 /*
7118  * Notification about pvclock gtod data update.
7119  */
7120 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7121                                void *priv)
7122 {
7123         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7124         struct timekeeper *tk = priv;
7125
7126         update_pvclock_gtod(tk);
7127
7128         /* disable master clock if host does not trust, or does not
7129          * use, TSC based clocksource.
7130          */
7131         if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7132             atomic_read(&kvm_guest_has_master_clock) != 0)
7133                 queue_work(system_long_wq, &pvclock_gtod_work);
7134
7135         return 0;
7136 }
7137
7138 static struct notifier_block pvclock_gtod_notifier = {
7139         .notifier_call = pvclock_gtod_notify,
7140 };
7141 #endif
7142
7143 int kvm_arch_init(void *opaque)
7144 {
7145         int r;
7146         struct kvm_x86_ops *ops = opaque;
7147
7148         if (kvm_x86_ops) {
7149                 printk(KERN_ERR "kvm: already loaded the other module\n");
7150                 r = -EEXIST;
7151                 goto out;
7152         }
7153
7154         if (!ops->cpu_has_kvm_support()) {
7155                 printk(KERN_ERR "kvm: no hardware support\n");
7156                 r = -EOPNOTSUPP;
7157                 goto out;
7158         }
7159         if (ops->disabled_by_bios()) {
7160                 printk(KERN_ERR "kvm: disabled by bios\n");
7161                 r = -EOPNOTSUPP;
7162                 goto out;
7163         }
7164
7165         /*
7166          * KVM explicitly assumes that the guest has an FPU and
7167          * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7168          * vCPU's FPU state as a fxregs_state struct.
7169          */
7170         if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7171                 printk(KERN_ERR "kvm: inadequate fpu\n");
7172                 r = -EOPNOTSUPP;
7173                 goto out;
7174         }
7175
7176         r = -ENOMEM;
7177         x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7178                                           __alignof__(struct fpu), SLAB_ACCOUNT,
7179                                           NULL);
7180         if (!x86_fpu_cache) {
7181                 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7182                 goto out;
7183         }
7184
7185         shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7186         if (!shared_msrs) {
7187                 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7188                 goto out_free_x86_fpu_cache;
7189         }
7190
7191         r = kvm_mmu_module_init();
7192         if (r)
7193                 goto out_free_percpu;
7194
7195         kvm_x86_ops = ops;
7196
7197         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7198                         PT_DIRTY_MASK, PT64_NX_MASK, 0,
7199                         PT_PRESENT_MASK, 0, sme_me_mask);
7200         kvm_timer_init();
7201
7202         perf_register_guest_info_callbacks(&kvm_guest_cbs);
7203
7204         if (boot_cpu_has(X86_FEATURE_XSAVE))
7205                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7206
7207         kvm_lapic_init();
7208         if (pi_inject_timer == -1)
7209                 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7210 #ifdef CONFIG_X86_64
7211         pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7212
7213         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7214                 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7215 #endif
7216
7217         return 0;
7218
7219 out_free_percpu:
7220         free_percpu(shared_msrs);
7221 out_free_x86_fpu_cache:
7222         kmem_cache_destroy(x86_fpu_cache);
7223 out:
7224         return r;
7225 }
7226
7227 void kvm_arch_exit(void)
7228 {
7229 #ifdef CONFIG_X86_64
7230         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7231                 clear_hv_tscchange_cb();
7232 #endif
7233         kvm_lapic_exit();
7234         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7235
7236         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7237                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7238                                             CPUFREQ_TRANSITION_NOTIFIER);
7239         cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7240 #ifdef CONFIG_X86_64
7241         pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7242 #endif
7243         kvm_x86_ops = NULL;
7244         kvm_mmu_module_exit();
7245         free_percpu(shared_msrs);
7246         kmem_cache_destroy(x86_fpu_cache);
7247 }
7248
7249 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7250 {
7251         ++vcpu->stat.halt_exits;
7252         if (lapic_in_kernel(vcpu)) {
7253                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7254                 return 1;
7255         } else {
7256                 vcpu->run->exit_reason = KVM_EXIT_HLT;
7257                 return 0;
7258         }
7259 }
7260 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7261
7262 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7263 {
7264         int ret = kvm_skip_emulated_instruction(vcpu);
7265         /*
7266          * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7267          * KVM_EXIT_DEBUG here.
7268          */
7269         return kvm_vcpu_halt(vcpu) && ret;
7270 }
7271 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7272
7273 #ifdef CONFIG_X86_64
7274 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7275                                 unsigned long clock_type)
7276 {
7277         struct kvm_clock_pairing clock_pairing;
7278         struct timespec64 ts;
7279         u64 cycle;
7280         int ret;
7281
7282         if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7283                 return -KVM_EOPNOTSUPP;
7284
7285         if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7286                 return -KVM_EOPNOTSUPP;
7287
7288         clock_pairing.sec = ts.tv_sec;
7289         clock_pairing.nsec = ts.tv_nsec;
7290         clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7291         clock_pairing.flags = 0;
7292         memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7293
7294         ret = 0;
7295         if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7296                             sizeof(struct kvm_clock_pairing)))
7297                 ret = -KVM_EFAULT;
7298
7299         return ret;
7300 }
7301 #endif
7302
7303 /*
7304  * kvm_pv_kick_cpu_op:  Kick a vcpu.
7305  *
7306  * @apicid - apicid of vcpu to be kicked.
7307  */
7308 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7309 {
7310         struct kvm_lapic_irq lapic_irq;
7311
7312         lapic_irq.shorthand = 0;
7313         lapic_irq.dest_mode = 0;
7314         lapic_irq.level = 0;
7315         lapic_irq.dest_id = apicid;
7316         lapic_irq.msi_redir_hint = false;
7317
7318         lapic_irq.delivery_mode = APIC_DM_REMRD;
7319         kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7320 }
7321
7322 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7323 {
7324         if (!lapic_in_kernel(vcpu)) {
7325                 WARN_ON_ONCE(vcpu->arch.apicv_active);
7326                 return;
7327         }
7328         if (!vcpu->arch.apicv_active)
7329                 return;
7330
7331         vcpu->arch.apicv_active = false;
7332         kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7333 }
7334
7335 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7336 {
7337         struct kvm_vcpu *target = NULL;
7338         struct kvm_apic_map *map;
7339
7340         rcu_read_lock();
7341         map = rcu_dereference(kvm->arch.apic_map);
7342
7343         if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7344                 target = map->phys_map[dest_id]->vcpu;
7345
7346         rcu_read_unlock();
7347
7348         if (target && READ_ONCE(target->ready))
7349                 kvm_vcpu_yield_to(target);
7350 }
7351
7352 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7353 {
7354         unsigned long nr, a0, a1, a2, a3, ret;
7355         int op_64_bit;
7356
7357         if (kvm_hv_hypercall_enabled(vcpu->kvm))
7358                 return kvm_hv_hypercall(vcpu);
7359
7360         nr = kvm_rax_read(vcpu);
7361         a0 = kvm_rbx_read(vcpu);
7362         a1 = kvm_rcx_read(vcpu);
7363         a2 = kvm_rdx_read(vcpu);
7364         a3 = kvm_rsi_read(vcpu);
7365
7366         trace_kvm_hypercall(nr, a0, a1, a2, a3);
7367
7368         op_64_bit = is_64_bit_mode(vcpu);
7369         if (!op_64_bit) {
7370                 nr &= 0xFFFFFFFF;
7371                 a0 &= 0xFFFFFFFF;
7372                 a1 &= 0xFFFFFFFF;
7373                 a2 &= 0xFFFFFFFF;
7374                 a3 &= 0xFFFFFFFF;
7375         }
7376
7377         if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7378                 ret = -KVM_EPERM;
7379                 goto out;
7380         }
7381
7382         switch (nr) {
7383         case KVM_HC_VAPIC_POLL_IRQ:
7384                 ret = 0;
7385                 break;
7386         case KVM_HC_KICK_CPU:
7387                 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7388                 kvm_sched_yield(vcpu->kvm, a1);
7389                 ret = 0;
7390                 break;
7391 #ifdef CONFIG_X86_64
7392         case KVM_HC_CLOCK_PAIRING:
7393                 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7394                 break;
7395 #endif
7396         case KVM_HC_SEND_IPI:
7397                 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7398                 break;
7399         case KVM_HC_SCHED_YIELD:
7400                 kvm_sched_yield(vcpu->kvm, a0);
7401                 ret = 0;
7402                 break;
7403         default:
7404                 ret = -KVM_ENOSYS;
7405                 break;
7406         }
7407 out:
7408         if (!op_64_bit)
7409                 ret = (u32)ret;
7410         kvm_rax_write(vcpu, ret);
7411
7412         ++vcpu->stat.hypercalls;
7413         return kvm_skip_emulated_instruction(vcpu);
7414 }
7415 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7416
7417 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7418 {
7419         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7420         char instruction[3];
7421         unsigned long rip = kvm_rip_read(vcpu);
7422
7423         kvm_x86_ops->patch_hypercall(vcpu, instruction);
7424
7425         return emulator_write_emulated(ctxt, rip, instruction, 3,
7426                 &ctxt->exception);
7427 }
7428
7429 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7430 {
7431         return vcpu->run->request_interrupt_window &&
7432                 likely(!pic_in_kernel(vcpu->kvm));
7433 }
7434
7435 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7436 {
7437         struct kvm_run *kvm_run = vcpu->run;
7438
7439         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7440         kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7441         kvm_run->cr8 = kvm_get_cr8(vcpu);
7442         kvm_run->apic_base = kvm_get_apic_base(vcpu);
7443         kvm_run->ready_for_interrupt_injection =
7444                 pic_in_kernel(vcpu->kvm) ||
7445                 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7446 }
7447
7448 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7449 {
7450         int max_irr, tpr;
7451
7452         if (!kvm_x86_ops->update_cr8_intercept)
7453                 return;
7454
7455         if (!lapic_in_kernel(vcpu))
7456                 return;
7457
7458         if (vcpu->arch.apicv_active)
7459                 return;
7460
7461         if (!vcpu->arch.apic->vapic_addr)
7462                 max_irr = kvm_lapic_find_highest_irr(vcpu);
7463         else
7464                 max_irr = -1;
7465
7466         if (max_irr != -1)
7467                 max_irr >>= 4;
7468
7469         tpr = kvm_lapic_get_cr8(vcpu);
7470
7471         kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7472 }
7473
7474 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7475 {
7476         int r;
7477
7478         /* try to reinject previous events if any */
7479
7480         if (vcpu->arch.exception.injected)
7481                 kvm_x86_ops->queue_exception(vcpu);
7482         /*
7483          * Do not inject an NMI or interrupt if there is a pending
7484          * exception.  Exceptions and interrupts are recognized at
7485          * instruction boundaries, i.e. the start of an instruction.
7486          * Trap-like exceptions, e.g. #DB, have higher priority than
7487          * NMIs and interrupts, i.e. traps are recognized before an
7488          * NMI/interrupt that's pending on the same instruction.
7489          * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7490          * priority, but are only generated (pended) during instruction
7491          * execution, i.e. a pending fault-like exception means the
7492          * fault occurred on the *previous* instruction and must be
7493          * serviced prior to recognizing any new events in order to
7494          * fully complete the previous instruction.
7495          */
7496         else if (!vcpu->arch.exception.pending) {
7497                 if (vcpu->arch.nmi_injected)
7498                         kvm_x86_ops->set_nmi(vcpu);
7499                 else if (vcpu->arch.interrupt.injected)
7500                         kvm_x86_ops->set_irq(vcpu);
7501         }
7502
7503         /*
7504          * Call check_nested_events() even if we reinjected a previous event
7505          * in order for caller to determine if it should require immediate-exit
7506          * from L2 to L1 due to pending L1 events which require exit
7507          * from L2 to L1.
7508          */
7509         if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7510                 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7511                 if (r != 0)
7512                         return r;
7513         }
7514
7515         /* try to inject new event if pending */
7516         if (vcpu->arch.exception.pending) {
7517                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7518                                         vcpu->arch.exception.has_error_code,
7519                                         vcpu->arch.exception.error_code);
7520
7521                 WARN_ON_ONCE(vcpu->arch.exception.injected);
7522                 vcpu->arch.exception.pending = false;
7523                 vcpu->arch.exception.injected = true;
7524
7525                 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7526                         __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7527                                              X86_EFLAGS_RF);
7528
7529                 if (vcpu->arch.exception.nr == DB_VECTOR) {
7530                         /*
7531                          * This code assumes that nSVM doesn't use
7532                          * check_nested_events(). If it does, the
7533                          * DR6/DR7 changes should happen before L1
7534                          * gets a #VMEXIT for an intercepted #DB in
7535                          * L2.  (Under VMX, on the other hand, the
7536                          * DR6/DR7 changes should not happen in the
7537                          * event of a VM-exit to L1 for an intercepted
7538                          * #DB in L2.)
7539                          */
7540                         kvm_deliver_exception_payload(vcpu);
7541                         if (vcpu->arch.dr7 & DR7_GD) {
7542                                 vcpu->arch.dr7 &= ~DR7_GD;
7543                                 kvm_update_dr7(vcpu);
7544                         }
7545                 }
7546
7547                 kvm_x86_ops->queue_exception(vcpu);
7548         }
7549
7550         /* Don't consider new event if we re-injected an event */
7551         if (kvm_event_needs_reinjection(vcpu))
7552                 return 0;
7553
7554         if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7555             kvm_x86_ops->smi_allowed(vcpu)) {
7556                 vcpu->arch.smi_pending = false;
7557                 ++vcpu->arch.smi_count;
7558                 enter_smm(vcpu);
7559         } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7560                 --vcpu->arch.nmi_pending;
7561                 vcpu->arch.nmi_injected = true;
7562                 kvm_x86_ops->set_nmi(vcpu);
7563         } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7564                 /*
7565                  * Because interrupts can be injected asynchronously, we are
7566                  * calling check_nested_events again here to avoid a race condition.
7567                  * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7568                  * proposal and current concerns.  Perhaps we should be setting
7569                  * KVM_REQ_EVENT only on certain events and not unconditionally?
7570                  */
7571                 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7572                         r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7573                         if (r != 0)
7574                                 return r;
7575                 }
7576                 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7577                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7578                                             false);
7579                         kvm_x86_ops->set_irq(vcpu);
7580                 }
7581         }
7582
7583         return 0;
7584 }
7585
7586 static void process_nmi(struct kvm_vcpu *vcpu)
7587 {
7588         unsigned limit = 2;
7589
7590         /*
7591          * x86 is limited to one NMI running, and one NMI pending after it.
7592          * If an NMI is already in progress, limit further NMIs to just one.
7593          * Otherwise, allow two (and we'll inject the first one immediately).
7594          */
7595         if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7596                 limit = 1;
7597
7598         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7599         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7600         kvm_make_request(KVM_REQ_EVENT, vcpu);
7601 }
7602
7603 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7604 {
7605         u32 flags = 0;
7606         flags |= seg->g       << 23;
7607         flags |= seg->db      << 22;
7608         flags |= seg->l       << 21;
7609         flags |= seg->avl     << 20;
7610         flags |= seg->present << 15;
7611         flags |= seg->dpl     << 13;
7612         flags |= seg->s       << 12;
7613         flags |= seg->type    << 8;
7614         return flags;
7615 }
7616
7617 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7618 {
7619         struct kvm_segment seg;
7620         int offset;
7621
7622         kvm_get_segment(vcpu, &seg, n);
7623         put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7624
7625         if (n < 3)
7626                 offset = 0x7f84 + n * 12;
7627         else
7628                 offset = 0x7f2c + (n - 3) * 12;
7629
7630         put_smstate(u32, buf, offset + 8, seg.base);
7631         put_smstate(u32, buf, offset + 4, seg.limit);
7632         put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7633 }
7634
7635 #ifdef CONFIG_X86_64
7636 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7637 {
7638         struct kvm_segment seg;
7639         int offset;
7640         u16 flags;
7641
7642         kvm_get_segment(vcpu, &seg, n);
7643         offset = 0x7e00 + n * 16;
7644
7645         flags = enter_smm_get_segment_flags(&seg) >> 8;
7646         put_smstate(u16, buf, offset, seg.selector);
7647         put_smstate(u16, buf, offset + 2, flags);
7648         put_smstate(u32, buf, offset + 4, seg.limit);
7649         put_smstate(u64, buf, offset + 8, seg.base);
7650 }
7651 #endif
7652
7653 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7654 {
7655         struct desc_ptr dt;
7656         struct kvm_segment seg;
7657         unsigned long val;
7658         int i;
7659
7660         put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7661         put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7662         put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7663         put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7664
7665         for (i = 0; i < 8; i++)
7666                 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7667
7668         kvm_get_dr(vcpu, 6, &val);
7669         put_smstate(u32, buf, 0x7fcc, (u32)val);
7670         kvm_get_dr(vcpu, 7, &val);
7671         put_smstate(u32, buf, 0x7fc8, (u32)val);
7672
7673         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7674         put_smstate(u32, buf, 0x7fc4, seg.selector);
7675         put_smstate(u32, buf, 0x7f64, seg.base);
7676         put_smstate(u32, buf, 0x7f60, seg.limit);
7677         put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7678
7679         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7680         put_smstate(u32, buf, 0x7fc0, seg.selector);
7681         put_smstate(u32, buf, 0x7f80, seg.base);
7682         put_smstate(u32, buf, 0x7f7c, seg.limit);
7683         put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7684
7685         kvm_x86_ops->get_gdt(vcpu, &dt);
7686         put_smstate(u32, buf, 0x7f74, dt.address);
7687         put_smstate(u32, buf, 0x7f70, dt.size);
7688
7689         kvm_x86_ops->get_idt(vcpu, &dt);
7690         put_smstate(u32, buf, 0x7f58, dt.address);
7691         put_smstate(u32, buf, 0x7f54, dt.size);
7692
7693         for (i = 0; i < 6; i++)
7694                 enter_smm_save_seg_32(vcpu, buf, i);
7695
7696         put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7697
7698         /* revision id */
7699         put_smstate(u32, buf, 0x7efc, 0x00020000);
7700         put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7701 }
7702
7703 #ifdef CONFIG_X86_64
7704 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7705 {
7706         struct desc_ptr dt;
7707         struct kvm_segment seg;
7708         unsigned long val;
7709         int i;
7710
7711         for (i = 0; i < 16; i++)
7712                 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7713
7714         put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7715         put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7716
7717         kvm_get_dr(vcpu, 6, &val);
7718         put_smstate(u64, buf, 0x7f68, val);
7719         kvm_get_dr(vcpu, 7, &val);
7720         put_smstate(u64, buf, 0x7f60, val);
7721
7722         put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7723         put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7724         put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7725
7726         put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7727
7728         /* revision id */
7729         put_smstate(u32, buf, 0x7efc, 0x00020064);
7730
7731         put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7732
7733         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7734         put_smstate(u16, buf, 0x7e90, seg.selector);
7735         put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7736         put_smstate(u32, buf, 0x7e94, seg.limit);
7737         put_smstate(u64, buf, 0x7e98, seg.base);
7738
7739         kvm_x86_ops->get_idt(vcpu, &dt);
7740         put_smstate(u32, buf, 0x7e84, dt.size);
7741         put_smstate(u64, buf, 0x7e88, dt.address);
7742
7743         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7744         put_smstate(u16, buf, 0x7e70, seg.selector);
7745         put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7746         put_smstate(u32, buf, 0x7e74, seg.limit);
7747         put_smstate(u64, buf, 0x7e78, seg.base);
7748
7749         kvm_x86_ops->get_gdt(vcpu, &dt);
7750         put_smstate(u32, buf, 0x7e64, dt.size);
7751         put_smstate(u64, buf, 0x7e68, dt.address);
7752
7753         for (i = 0; i < 6; i++)
7754                 enter_smm_save_seg_64(vcpu, buf, i);
7755 }
7756 #endif
7757
7758 static void enter_smm(struct kvm_vcpu *vcpu)
7759 {
7760         struct kvm_segment cs, ds;
7761         struct desc_ptr dt;
7762         char buf[512];
7763         u32 cr0;
7764
7765         trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7766         memset(buf, 0, 512);
7767 #ifdef CONFIG_X86_64
7768         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7769                 enter_smm_save_state_64(vcpu, buf);
7770         else
7771 #endif
7772                 enter_smm_save_state_32(vcpu, buf);
7773
7774         /*
7775          * Give pre_enter_smm() a chance to make ISA-specific changes to the
7776          * vCPU state (e.g. leave guest mode) after we've saved the state into
7777          * the SMM state-save area.
7778          */
7779         kvm_x86_ops->pre_enter_smm(vcpu, buf);
7780
7781         vcpu->arch.hflags |= HF_SMM_MASK;
7782         kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7783
7784         if (kvm_x86_ops->get_nmi_mask(vcpu))
7785                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7786         else
7787                 kvm_x86_ops->set_nmi_mask(vcpu, true);
7788
7789         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7790         kvm_rip_write(vcpu, 0x8000);
7791
7792         cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7793         kvm_x86_ops->set_cr0(vcpu, cr0);
7794         vcpu->arch.cr0 = cr0;
7795
7796         kvm_x86_ops->set_cr4(vcpu, 0);
7797
7798         /* Undocumented: IDT limit is set to zero on entry to SMM.  */
7799         dt.address = dt.size = 0;
7800         kvm_x86_ops->set_idt(vcpu, &dt);
7801
7802         __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7803
7804         cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7805         cs.base = vcpu->arch.smbase;
7806
7807         ds.selector = 0;
7808         ds.base = 0;
7809
7810         cs.limit    = ds.limit = 0xffffffff;
7811         cs.type     = ds.type = 0x3;
7812         cs.dpl      = ds.dpl = 0;
7813         cs.db       = ds.db = 0;
7814         cs.s        = ds.s = 1;
7815         cs.l        = ds.l = 0;
7816         cs.g        = ds.g = 1;
7817         cs.avl      = ds.avl = 0;
7818         cs.present  = ds.present = 1;
7819         cs.unusable = ds.unusable = 0;
7820         cs.padding  = ds.padding = 0;
7821
7822         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7823         kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7824         kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7825         kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7826         kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7827         kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7828
7829 #ifdef CONFIG_X86_64
7830         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7831                 kvm_x86_ops->set_efer(vcpu, 0);
7832 #endif
7833
7834         kvm_update_cpuid(vcpu);
7835         kvm_mmu_reset_context(vcpu);
7836 }
7837
7838 static void process_smi(struct kvm_vcpu *vcpu)
7839 {
7840         vcpu->arch.smi_pending = true;
7841         kvm_make_request(KVM_REQ_EVENT, vcpu);
7842 }
7843
7844 void kvm_make_scan_ioapic_request(struct kvm *kvm)
7845 {
7846         kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7847 }
7848
7849 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
7850 {
7851         if (!kvm_apic_present(vcpu))
7852                 return;
7853
7854         bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
7855
7856         if (irqchip_split(vcpu->kvm))
7857                 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
7858         else {
7859                 if (vcpu->arch.apicv_active)
7860                         kvm_x86_ops->sync_pir_to_irr(vcpu);
7861                 if (ioapic_in_kernel(vcpu->kvm))
7862                         kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
7863         }
7864
7865         if (is_guest_mode(vcpu))
7866                 vcpu->arch.load_eoi_exitmap_pending = true;
7867         else
7868                 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7869 }
7870
7871 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7872 {
7873         u64 eoi_exit_bitmap[4];
7874
7875         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7876                 return;
7877
7878         bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7879                   vcpu_to_synic(vcpu)->vec_bitmap, 256);
7880         kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
7881 }
7882
7883 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7884                 unsigned long start, unsigned long end,
7885                 bool blockable)
7886 {
7887         unsigned long apic_address;
7888
7889         /*
7890          * The physical address of apic access page is stored in the VMCS.
7891          * Update it when it becomes invalid.
7892          */
7893         apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7894         if (start <= apic_address && apic_address < end)
7895                 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7896
7897         return 0;
7898 }
7899
7900 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7901 {
7902         struct page *page = NULL;
7903
7904         if (!lapic_in_kernel(vcpu))
7905                 return;
7906
7907         if (!kvm_x86_ops->set_apic_access_page_addr)
7908                 return;
7909
7910         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7911         if (is_error_page(page))
7912                 return;
7913         kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7914
7915         /*
7916          * Do not pin apic access page in memory, the MMU notifier
7917          * will call us again if it is migrated or swapped out.
7918          */
7919         put_page(page);
7920 }
7921 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7922
7923 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7924 {
7925         smp_send_reschedule(vcpu->cpu);
7926 }
7927 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7928
7929 /*
7930  * Returns 1 to let vcpu_run() continue the guest execution loop without
7931  * exiting to the userspace.  Otherwise, the value will be returned to the
7932  * userspace.
7933  */
7934 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
7935 {
7936         int r;
7937         bool req_int_win =
7938                 dm_request_for_irq_injection(vcpu) &&
7939                 kvm_cpu_accept_dm_intr(vcpu);
7940
7941         bool req_immediate_exit = false;
7942
7943         if (kvm_request_pending(vcpu)) {
7944                 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7945                         kvm_x86_ops->get_vmcs12_pages(vcpu);
7946                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
7947                         kvm_mmu_unload(vcpu);
7948                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
7949                         __kvm_migrate_timers(vcpu);
7950                 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7951                         kvm_gen_update_masterclock(vcpu->kvm);
7952                 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7953                         kvm_gen_kvmclock_update(vcpu);
7954                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7955                         r = kvm_guest_time_update(vcpu);
7956                         if (unlikely(r))
7957                                 goto out;
7958                 }
7959                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
7960                         kvm_mmu_sync_roots(vcpu);
7961                 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7962                         kvm_mmu_load_cr3(vcpu);
7963                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
7964                         kvm_vcpu_flush_tlb(vcpu, true);
7965                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
7966                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
7967                         r = 0;
7968                         goto out;
7969                 }
7970                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
7971                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7972                         vcpu->mmio_needed = 0;
7973                         r = 0;
7974                         goto out;
7975                 }
7976                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7977                         /* Page is swapped out. Do synthetic halt */
7978                         vcpu->arch.apf.halted = true;
7979                         r = 1;
7980                         goto out;
7981                 }
7982                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7983                         record_steal_time(vcpu);
7984                 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7985                         process_smi(vcpu);
7986                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7987                         process_nmi(vcpu);
7988                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7989                         kvm_pmu_handle_event(vcpu);
7990                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7991                         kvm_pmu_deliver_pmi(vcpu);
7992                 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7993                         BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7994                         if (test_bit(vcpu->arch.pending_ioapic_eoi,
7995                                      vcpu->arch.ioapic_handled_vectors)) {
7996                                 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7997                                 vcpu->run->eoi.vector =
7998                                                 vcpu->arch.pending_ioapic_eoi;
7999                                 r = 0;
8000                                 goto out;
8001                         }
8002                 }
8003                 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8004                         vcpu_scan_ioapic(vcpu);
8005                 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8006                         vcpu_load_eoi_exitmap(vcpu);
8007                 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8008                         kvm_vcpu_reload_apic_access_page(vcpu);
8009                 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8010                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8011                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8012                         r = 0;
8013                         goto out;
8014                 }
8015                 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8016                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8017                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8018                         r = 0;
8019                         goto out;
8020                 }
8021                 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8022                         vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8023                         vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8024                         r = 0;
8025                         goto out;
8026                 }
8027
8028                 /*
8029                  * KVM_REQ_HV_STIMER has to be processed after
8030                  * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8031                  * depend on the guest clock being up-to-date
8032                  */
8033                 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8034                         kvm_hv_process_stimers(vcpu);
8035         }
8036
8037         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8038                 ++vcpu->stat.req_event;
8039                 kvm_apic_accept_events(vcpu);
8040                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8041                         r = 1;
8042                         goto out;
8043                 }
8044
8045                 if (inject_pending_event(vcpu, req_int_win) != 0)
8046                         req_immediate_exit = true;
8047                 else {
8048                         /* Enable SMI/NMI/IRQ window open exits if needed.
8049                          *
8050                          * SMIs have three cases:
8051                          * 1) They can be nested, and then there is nothing to
8052                          *    do here because RSM will cause a vmexit anyway.
8053                          * 2) There is an ISA-specific reason why SMI cannot be
8054                          *    injected, and the moment when this changes can be
8055                          *    intercepted.
8056                          * 3) Or the SMI can be pending because
8057                          *    inject_pending_event has completed the injection
8058                          *    of an IRQ or NMI from the previous vmexit, and
8059                          *    then we request an immediate exit to inject the
8060                          *    SMI.
8061                          */
8062                         if (vcpu->arch.smi_pending && !is_smm(vcpu))
8063                                 if (!kvm_x86_ops->enable_smi_window(vcpu))
8064                                         req_immediate_exit = true;
8065                         if (vcpu->arch.nmi_pending)
8066                                 kvm_x86_ops->enable_nmi_window(vcpu);
8067                         if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8068                                 kvm_x86_ops->enable_irq_window(vcpu);
8069                         WARN_ON(vcpu->arch.exception.pending);
8070                 }
8071
8072                 if (kvm_lapic_enabled(vcpu)) {
8073                         update_cr8_intercept(vcpu);
8074                         kvm_lapic_sync_to_vapic(vcpu);
8075                 }
8076         }
8077
8078         r = kvm_mmu_reload(vcpu);
8079         if (unlikely(r)) {
8080                 goto cancel_injection;
8081         }
8082
8083         preempt_disable();
8084
8085         kvm_x86_ops->prepare_guest_switch(vcpu);
8086
8087         /*
8088          * Disable IRQs before setting IN_GUEST_MODE.  Posted interrupt
8089          * IPI are then delayed after guest entry, which ensures that they
8090          * result in virtual interrupt delivery.
8091          */
8092         local_irq_disable();
8093         vcpu->mode = IN_GUEST_MODE;
8094
8095         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8096
8097         /*
8098          * 1) We should set ->mode before checking ->requests.  Please see
8099          * the comment in kvm_vcpu_exiting_guest_mode().
8100          *
8101          * 2) For APICv, we should set ->mode before checking PID.ON. This
8102          * pairs with the memory barrier implicit in pi_test_and_set_on
8103          * (see vmx_deliver_posted_interrupt).
8104          *
8105          * 3) This also orders the write to mode from any reads to the page
8106          * tables done while the VCPU is running.  Please see the comment
8107          * in kvm_flush_remote_tlbs.
8108          */
8109         smp_mb__after_srcu_read_unlock();
8110
8111         /*
8112          * This handles the case where a posted interrupt was
8113          * notified with kvm_vcpu_kick.
8114          */
8115         if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8116                 kvm_x86_ops->sync_pir_to_irr(vcpu);
8117
8118         if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
8119             || need_resched() || signal_pending(current)) {
8120                 vcpu->mode = OUTSIDE_GUEST_MODE;
8121                 smp_wmb();
8122                 local_irq_enable();
8123                 preempt_enable();
8124                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8125                 r = 1;
8126                 goto cancel_injection;
8127         }
8128
8129         if (req_immediate_exit) {
8130                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8131                 kvm_x86_ops->request_immediate_exit(vcpu);
8132         }
8133
8134         trace_kvm_entry(vcpu->vcpu_id);
8135         guest_enter_irqoff();
8136
8137         /* The preempt notifier should have taken care of the FPU already.  */
8138         WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD));
8139
8140         if (unlikely(vcpu->arch.switch_db_regs)) {
8141                 set_debugreg(0, 7);
8142                 set_debugreg(vcpu->arch.eff_db[0], 0);
8143                 set_debugreg(vcpu->arch.eff_db[1], 1);
8144                 set_debugreg(vcpu->arch.eff_db[2], 2);
8145                 set_debugreg(vcpu->arch.eff_db[3], 3);
8146                 set_debugreg(vcpu->arch.dr6, 6);
8147                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8148         }
8149
8150         kvm_x86_ops->run(vcpu);
8151
8152         /*
8153          * Do this here before restoring debug registers on the host.  And
8154          * since we do this before handling the vmexit, a DR access vmexit
8155          * can (a) read the correct value of the debug registers, (b) set
8156          * KVM_DEBUGREG_WONT_EXIT again.
8157          */
8158         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8159                 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8160                 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
8161                 kvm_update_dr0123(vcpu);
8162                 kvm_update_dr6(vcpu);
8163                 kvm_update_dr7(vcpu);
8164                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8165         }
8166
8167         /*
8168          * If the guest has used debug registers, at least dr7
8169          * will be disabled while returning to the host.
8170          * If we don't have active breakpoints in the host, we don't
8171          * care about the messed up debug address registers. But if
8172          * we have some of them active, restore the old state.
8173          */
8174         if (hw_breakpoint_active())
8175                 hw_breakpoint_restore();
8176
8177         vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8178
8179         vcpu->mode = OUTSIDE_GUEST_MODE;
8180         smp_wmb();
8181
8182         kvm_x86_ops->handle_exit_irqoff(vcpu);
8183
8184         /*
8185          * Consume any pending interrupts, including the possible source of
8186          * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8187          * An instruction is required after local_irq_enable() to fully unblock
8188          * interrupts on processors that implement an interrupt shadow, the
8189          * stat.exits increment will do nicely.
8190          */
8191         kvm_before_interrupt(vcpu);
8192         local_irq_enable();
8193         ++vcpu->stat.exits;
8194         local_irq_disable();
8195         kvm_after_interrupt(vcpu);
8196
8197         guest_exit_irqoff();
8198         if (lapic_in_kernel(vcpu)) {
8199                 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8200                 if (delta != S64_MIN) {
8201                         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8202                         vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8203                 }
8204         }
8205
8206         local_irq_enable();
8207         preempt_enable();
8208
8209         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8210
8211         /*
8212          * Profile KVM exit RIPs:
8213          */
8214         if (unlikely(prof_on == KVM_PROFILING)) {
8215                 unsigned long rip = kvm_rip_read(vcpu);
8216                 profile_hit(KVM_PROFILING, (void *)rip);
8217         }
8218
8219         if (unlikely(vcpu->arch.tsc_always_catchup))
8220                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8221
8222         if (vcpu->arch.apic_attention)
8223                 kvm_lapic_sync_from_vapic(vcpu);
8224
8225         vcpu->arch.gpa_available = false;
8226         r = kvm_x86_ops->handle_exit(vcpu);
8227         return r;
8228
8229 cancel_injection:
8230         kvm_x86_ops->cancel_injection(vcpu);
8231         if (unlikely(vcpu->arch.apic_attention))
8232                 kvm_lapic_sync_from_vapic(vcpu);
8233 out:
8234         return r;
8235 }
8236
8237 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8238 {
8239         if (!kvm_arch_vcpu_runnable(vcpu) &&
8240             (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
8241                 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8242                 kvm_vcpu_block(vcpu);
8243                 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8244
8245                 if (kvm_x86_ops->post_block)
8246                         kvm_x86_ops->post_block(vcpu);
8247
8248                 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8249                         return 1;
8250         }
8251
8252         kvm_apic_accept_events(vcpu);
8253         switch(vcpu->arch.mp_state) {
8254         case KVM_MP_STATE_HALTED:
8255                 vcpu->arch.pv.pv_unhalted = false;
8256                 vcpu->arch.mp_state =
8257                         KVM_MP_STATE_RUNNABLE;
8258                 /* fall through */
8259         case KVM_MP_STATE_RUNNABLE:
8260                 vcpu->arch.apf.halted = false;
8261                 break;
8262         case KVM_MP_STATE_INIT_RECEIVED:
8263                 break;
8264         default:
8265                 return -EINTR;
8266                 break;
8267         }
8268         return 1;
8269 }
8270
8271 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8272 {
8273         if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8274                 kvm_x86_ops->check_nested_events(vcpu, false);
8275
8276         return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8277                 !vcpu->arch.apf.halted);
8278 }
8279
8280 static int vcpu_run(struct kvm_vcpu *vcpu)
8281 {
8282         int r;
8283         struct kvm *kvm = vcpu->kvm;
8284
8285         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8286         vcpu->arch.l1tf_flush_l1d = true;
8287
8288         for (;;) {
8289                 if (kvm_vcpu_running(vcpu)) {
8290                         r = vcpu_enter_guest(vcpu);
8291                 } else {
8292                         r = vcpu_block(kvm, vcpu);
8293                 }
8294
8295                 if (r <= 0)
8296                         break;
8297
8298                 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8299                 if (kvm_cpu_has_pending_timer(vcpu))
8300                         kvm_inject_pending_timer_irqs(vcpu);
8301
8302                 if (dm_request_for_irq_injection(vcpu) &&
8303                         kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8304                         r = 0;
8305                         vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8306                         ++vcpu->stat.request_irq_exits;
8307                         break;
8308                 }
8309
8310                 kvm_check_async_pf_completion(vcpu);
8311
8312                 if (signal_pending(current)) {
8313                         r = -EINTR;
8314                         vcpu->run->exit_reason = KVM_EXIT_INTR;
8315                         ++vcpu->stat.signal_exits;
8316                         break;
8317                 }
8318                 if (need_resched()) {
8319                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8320                         cond_resched();
8321                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8322                 }
8323         }
8324
8325         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8326
8327         return r;
8328 }
8329
8330 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8331 {
8332         int r;
8333
8334         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8335         r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8336         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8337         return r;
8338 }
8339
8340 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8341 {
8342         BUG_ON(!vcpu->arch.pio.count);
8343
8344         return complete_emulated_io(vcpu);
8345 }
8346
8347 /*
8348  * Implements the following, as a state machine:
8349  *
8350  * read:
8351  *   for each fragment
8352  *     for each mmio piece in the fragment
8353  *       write gpa, len
8354  *       exit
8355  *       copy data
8356  *   execute insn
8357  *
8358  * write:
8359  *   for each fragment
8360  *     for each mmio piece in the fragment
8361  *       write gpa, len
8362  *       copy data
8363  *       exit
8364  */
8365 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8366 {
8367         struct kvm_run *run = vcpu->run;
8368         struct kvm_mmio_fragment *frag;
8369         unsigned len;
8370
8371         BUG_ON(!vcpu->mmio_needed);
8372
8373         /* Complete previous fragment */
8374         frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8375         len = min(8u, frag->len);
8376         if (!vcpu->mmio_is_write)
8377                 memcpy(frag->data, run->mmio.data, len);
8378
8379         if (frag->len <= 8) {
8380                 /* Switch to the next fragment. */
8381                 frag++;
8382                 vcpu->mmio_cur_fragment++;
8383         } else {
8384                 /* Go forward to the next mmio piece. */
8385                 frag->data += len;
8386                 frag->gpa += len;
8387                 frag->len -= len;
8388         }
8389
8390         if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8391                 vcpu->mmio_needed = 0;
8392
8393                 /* FIXME: return into emulator if single-stepping.  */
8394                 if (vcpu->mmio_is_write)
8395                         return 1;
8396                 vcpu->mmio_read_completed = 1;
8397                 return complete_emulated_io(vcpu);
8398         }
8399
8400         run->exit_reason = KVM_EXIT_MMIO;
8401         run->mmio.phys_addr = frag->gpa;
8402         if (vcpu->mmio_is_write)
8403                 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8404         run->mmio.len = min(8u, frag->len);
8405         run->mmio.is_write = vcpu->mmio_is_write;
8406         vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8407         return 0;
8408 }
8409
8410 /* Swap (qemu) user FPU context for the guest FPU context. */
8411 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8412 {
8413         fpregs_lock();
8414
8415         copy_fpregs_to_fpstate(vcpu->arch.user_fpu);
8416         /* PKRU is separately restored in kvm_x86_ops->run.  */
8417         __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8418                                 ~XFEATURE_MASK_PKRU);
8419
8420         fpregs_mark_activate();
8421         fpregs_unlock();
8422
8423         trace_kvm_fpu(1);
8424 }
8425
8426 /* When vcpu_run ends, restore user space FPU context. */
8427 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8428 {
8429         fpregs_lock();
8430
8431         copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
8432         copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8433
8434         fpregs_mark_activate();
8435         fpregs_unlock();
8436
8437         ++vcpu->stat.fpu_reload;
8438         trace_kvm_fpu(0);
8439 }
8440
8441 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8442 {
8443         int r;
8444
8445         vcpu_load(vcpu);
8446         kvm_sigset_activate(vcpu);
8447         kvm_load_guest_fpu(vcpu);
8448
8449         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8450                 if (kvm_run->immediate_exit) {
8451                         r = -EINTR;
8452                         goto out;
8453                 }
8454                 kvm_vcpu_block(vcpu);
8455                 kvm_apic_accept_events(vcpu);
8456                 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8457                 r = -EAGAIN;
8458                 if (signal_pending(current)) {
8459                         r = -EINTR;
8460                         vcpu->run->exit_reason = KVM_EXIT_INTR;
8461                         ++vcpu->stat.signal_exits;
8462                 }
8463                 goto out;
8464         }
8465
8466         if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8467                 r = -EINVAL;
8468                 goto out;
8469         }
8470
8471         if (vcpu->run->kvm_dirty_regs) {
8472                 r = sync_regs(vcpu);
8473                 if (r != 0)
8474                         goto out;
8475         }
8476
8477         /* re-sync apic's tpr */
8478         if (!lapic_in_kernel(vcpu)) {
8479                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8480                         r = -EINVAL;
8481                         goto out;
8482                 }
8483         }
8484
8485         if (unlikely(vcpu->arch.complete_userspace_io)) {
8486                 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8487                 vcpu->arch.complete_userspace_io = NULL;
8488                 r = cui(vcpu);
8489                 if (r <= 0)
8490                         goto out;
8491         } else
8492                 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8493
8494         if (kvm_run->immediate_exit)
8495                 r = -EINTR;
8496         else
8497                 r = vcpu_run(vcpu);
8498
8499 out:
8500         kvm_put_guest_fpu(vcpu);
8501         if (vcpu->run->kvm_valid_regs)
8502                 store_regs(vcpu);
8503         post_kvm_run_save(vcpu);
8504         kvm_sigset_deactivate(vcpu);
8505
8506         vcpu_put(vcpu);
8507         return r;
8508 }
8509
8510 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8511 {
8512         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8513                 /*
8514                  * We are here if userspace calls get_regs() in the middle of
8515                  * instruction emulation. Registers state needs to be copied
8516                  * back from emulation context to vcpu. Userspace shouldn't do
8517                  * that usually, but some bad designed PV devices (vmware
8518                  * backdoor interface) need this to work
8519                  */
8520                 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8521                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8522         }
8523         regs->rax = kvm_rax_read(vcpu);
8524         regs->rbx = kvm_rbx_read(vcpu);
8525         regs->rcx = kvm_rcx_read(vcpu);
8526         regs->rdx = kvm_rdx_read(vcpu);
8527         regs->rsi = kvm_rsi_read(vcpu);
8528         regs->rdi = kvm_rdi_read(vcpu);
8529         regs->rsp = kvm_rsp_read(vcpu);
8530         regs->rbp = kvm_rbp_read(vcpu);
8531 #ifdef CONFIG_X86_64
8532         regs->r8 = kvm_r8_read(vcpu);
8533         regs->r9 = kvm_r9_read(vcpu);
8534         regs->r10 = kvm_r10_read(vcpu);
8535         regs->r11 = kvm_r11_read(vcpu);
8536         regs->r12 = kvm_r12_read(vcpu);
8537         regs->r13 = kvm_r13_read(vcpu);
8538         regs->r14 = kvm_r14_read(vcpu);
8539         regs->r15 = kvm_r15_read(vcpu);
8540 #endif
8541
8542         regs->rip = kvm_rip_read(vcpu);
8543         regs->rflags = kvm_get_rflags(vcpu);
8544 }
8545
8546 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8547 {
8548         vcpu_load(vcpu);
8549         __get_regs(vcpu, regs);
8550         vcpu_put(vcpu);
8551         return 0;
8552 }
8553
8554 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8555 {
8556         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8557         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8558
8559         kvm_rax_write(vcpu, regs->rax);
8560         kvm_rbx_write(vcpu, regs->rbx);
8561         kvm_rcx_write(vcpu, regs->rcx);
8562         kvm_rdx_write(vcpu, regs->rdx);
8563         kvm_rsi_write(vcpu, regs->rsi);
8564         kvm_rdi_write(vcpu, regs->rdi);
8565         kvm_rsp_write(vcpu, regs->rsp);
8566         kvm_rbp_write(vcpu, regs->rbp);
8567 #ifdef CONFIG_X86_64
8568         kvm_r8_write(vcpu, regs->r8);
8569         kvm_r9_write(vcpu, regs->r9);
8570         kvm_r10_write(vcpu, regs->r10);
8571         kvm_r11_write(vcpu, regs->r11);
8572         kvm_r12_write(vcpu, regs->r12);
8573         kvm_r13_write(vcpu, regs->r13);
8574         kvm_r14_write(vcpu, regs->r14);
8575         kvm_r15_write(vcpu, regs->r15);
8576 #endif
8577
8578         kvm_rip_write(vcpu, regs->rip);
8579         kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8580
8581         vcpu->arch.exception.pending = false;
8582
8583         kvm_make_request(KVM_REQ_EVENT, vcpu);
8584 }
8585
8586 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8587 {
8588         vcpu_load(vcpu);
8589         __set_regs(vcpu, regs);
8590         vcpu_put(vcpu);
8591         return 0;
8592 }
8593
8594 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8595 {
8596         struct kvm_segment cs;
8597
8598         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8599         *db = cs.db;
8600         *l = cs.l;
8601 }
8602 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8603
8604 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8605 {
8606         struct desc_ptr dt;
8607
8608         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8609         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8610         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8611         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8612         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8613         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8614
8615         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8616         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8617
8618         kvm_x86_ops->get_idt(vcpu, &dt);
8619         sregs->idt.limit = dt.size;
8620         sregs->idt.base = dt.address;
8621         kvm_x86_ops->get_gdt(vcpu, &dt);
8622         sregs->gdt.limit = dt.size;
8623         sregs->gdt.base = dt.address;
8624
8625         sregs->cr0 = kvm_read_cr0(vcpu);
8626         sregs->cr2 = vcpu->arch.cr2;
8627         sregs->cr3 = kvm_read_cr3(vcpu);
8628         sregs->cr4 = kvm_read_cr4(vcpu);
8629         sregs->cr8 = kvm_get_cr8(vcpu);
8630         sregs->efer = vcpu->arch.efer;
8631         sregs->apic_base = kvm_get_apic_base(vcpu);
8632
8633         memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8634
8635         if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8636                 set_bit(vcpu->arch.interrupt.nr,
8637                         (unsigned long *)sregs->interrupt_bitmap);
8638 }
8639
8640 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8641                                   struct kvm_sregs *sregs)
8642 {
8643         vcpu_load(vcpu);
8644         __get_sregs(vcpu, sregs);
8645         vcpu_put(vcpu);
8646         return 0;
8647 }
8648
8649 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8650                                     struct kvm_mp_state *mp_state)
8651 {
8652         vcpu_load(vcpu);
8653
8654         kvm_apic_accept_events(vcpu);
8655         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8656                                         vcpu->arch.pv.pv_unhalted)
8657                 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8658         else
8659                 mp_state->mp_state = vcpu->arch.mp_state;
8660
8661         vcpu_put(vcpu);
8662         return 0;
8663 }
8664
8665 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8666                                     struct kvm_mp_state *mp_state)
8667 {
8668         int ret = -EINVAL;
8669
8670         vcpu_load(vcpu);
8671
8672         if (!lapic_in_kernel(vcpu) &&
8673             mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8674                 goto out;
8675
8676         /* INITs are latched while in SMM */
8677         if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8678             (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8679              mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8680                 goto out;
8681
8682         if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8683                 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8684                 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8685         } else
8686                 vcpu->arch.mp_state = mp_state->mp_state;
8687         kvm_make_request(KVM_REQ_EVENT, vcpu);
8688
8689         ret = 0;
8690 out:
8691         vcpu_put(vcpu);
8692         return ret;
8693 }
8694
8695 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8696                     int reason, bool has_error_code, u32 error_code)
8697 {
8698         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8699         int ret;
8700
8701         init_emulate_ctxt(vcpu);
8702
8703         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8704                                    has_error_code, error_code);
8705         if (ret) {
8706                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8707                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
8708                 vcpu->run->internal.ndata = 0;
8709                 return 0;
8710         }
8711
8712         kvm_rip_write(vcpu, ctxt->eip);
8713         kvm_set_rflags(vcpu, ctxt->eflags);
8714         kvm_make_request(KVM_REQ_EVENT, vcpu);
8715         return 1;
8716 }
8717 EXPORT_SYMBOL_GPL(kvm_task_switch);
8718
8719 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8720 {
8721         if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8722                 /*
8723                  * When EFER.LME and CR0.PG are set, the processor is in
8724                  * 64-bit mode (though maybe in a 32-bit code segment).
8725                  * CR4.PAE and EFER.LMA must be set.
8726                  */
8727                 if (!(sregs->cr4 & X86_CR4_PAE)
8728                     || !(sregs->efer & EFER_LMA))
8729                         return -EINVAL;
8730         } else {
8731                 /*
8732                  * Not in 64-bit mode: EFER.LMA is clear and the code
8733                  * segment cannot be 64-bit.
8734                  */
8735                 if (sregs->efer & EFER_LMA || sregs->cs.l)
8736                         return -EINVAL;
8737         }
8738
8739         return kvm_valid_cr4(vcpu, sregs->cr4);
8740 }
8741
8742 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8743 {
8744         struct msr_data apic_base_msr;
8745         int mmu_reset_needed = 0;
8746         int cpuid_update_needed = 0;
8747         int pending_vec, max_bits, idx;
8748         struct desc_ptr dt;
8749         int ret = -EINVAL;
8750
8751         if (kvm_valid_sregs(vcpu, sregs))
8752                 goto out;
8753
8754         apic_base_msr.data = sregs->apic_base;
8755         apic_base_msr.host_initiated = true;
8756         if (kvm_set_apic_base(vcpu, &apic_base_msr))
8757                 goto out;
8758
8759         dt.size = sregs->idt.limit;
8760         dt.address = sregs->idt.base;
8761         kvm_x86_ops->set_idt(vcpu, &dt);
8762         dt.size = sregs->gdt.limit;
8763         dt.address = sregs->gdt.base;
8764         kvm_x86_ops->set_gdt(vcpu, &dt);
8765
8766         vcpu->arch.cr2 = sregs->cr2;
8767         mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
8768         vcpu->arch.cr3 = sregs->cr3;
8769         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
8770
8771         kvm_set_cr8(vcpu, sregs->cr8);
8772
8773         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
8774         kvm_x86_ops->set_efer(vcpu, sregs->efer);
8775
8776         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
8777         kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
8778         vcpu->arch.cr0 = sregs->cr0;
8779
8780         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
8781         cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8782                                 (X86_CR4_OSXSAVE | X86_CR4_PKE));
8783         kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
8784         if (cpuid_update_needed)
8785                 kvm_update_cpuid(vcpu);
8786
8787         idx = srcu_read_lock(&vcpu->kvm->srcu);
8788         if (is_pae_paging(vcpu)) {
8789                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
8790                 mmu_reset_needed = 1;
8791         }
8792         srcu_read_unlock(&vcpu->kvm->srcu, idx);
8793
8794         if (mmu_reset_needed)
8795                 kvm_mmu_reset_context(vcpu);
8796
8797         max_bits = KVM_NR_INTERRUPTS;
8798         pending_vec = find_first_bit(
8799                 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8800         if (pending_vec < max_bits) {
8801                 kvm_queue_interrupt(vcpu, pending_vec, false);
8802                 pr_debug("Set back pending irq %d\n", pending_vec);
8803         }
8804
8805         kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8806         kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8807         kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8808         kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8809         kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8810         kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8811
8812         kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8813         kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8814
8815         update_cr8_intercept(vcpu);
8816
8817         /* Older userspace won't unhalt the vcpu on reset. */
8818         if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
8819             sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
8820             !is_protmode(vcpu))
8821                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8822
8823         kvm_make_request(KVM_REQ_EVENT, vcpu);
8824
8825         ret = 0;
8826 out:
8827         return ret;
8828 }
8829
8830 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8831                                   struct kvm_sregs *sregs)
8832 {
8833         int ret;
8834
8835         vcpu_load(vcpu);
8836         ret = __set_sregs(vcpu, sregs);
8837         vcpu_put(vcpu);
8838         return ret;
8839 }
8840
8841 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8842                                         struct kvm_guest_debug *dbg)
8843 {
8844         unsigned long rflags;
8845         int i, r;
8846
8847         vcpu_load(vcpu);
8848
8849         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8850                 r = -EBUSY;
8851                 if (vcpu->arch.exception.pending)
8852                         goto out;
8853                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8854                         kvm_queue_exception(vcpu, DB_VECTOR);
8855                 else
8856                         kvm_queue_exception(vcpu, BP_VECTOR);
8857         }
8858
8859         /*
8860          * Read rflags as long as potentially injected trace flags are still
8861          * filtered out.
8862          */
8863         rflags = kvm_get_rflags(vcpu);
8864
8865         vcpu->guest_debug = dbg->control;
8866         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8867                 vcpu->guest_debug = 0;
8868
8869         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
8870                 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8871                         vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
8872                 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
8873         } else {
8874                 for (i = 0; i < KVM_NR_DB_REGS; i++)
8875                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
8876         }
8877         kvm_update_dr7(vcpu);
8878
8879         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8880                 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8881                         get_segment_base(vcpu, VCPU_SREG_CS);
8882
8883         /*
8884          * Trigger an rflags update that will inject or remove the trace
8885          * flags.
8886          */
8887         kvm_set_rflags(vcpu, rflags);
8888
8889         kvm_x86_ops->update_bp_intercept(vcpu);
8890
8891         r = 0;
8892
8893 out:
8894         vcpu_put(vcpu);
8895         return r;
8896 }
8897
8898 /*
8899  * Translate a guest virtual address to a guest physical address.
8900  */
8901 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8902                                     struct kvm_translation *tr)
8903 {
8904         unsigned long vaddr = tr->linear_address;
8905         gpa_t gpa;
8906         int idx;
8907
8908         vcpu_load(vcpu);
8909
8910         idx = srcu_read_lock(&vcpu->kvm->srcu);
8911         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
8912         srcu_read_unlock(&vcpu->kvm->srcu, idx);
8913         tr->physical_address = gpa;
8914         tr->valid = gpa != UNMAPPED_GVA;
8915         tr->writeable = 1;
8916         tr->usermode = 0;
8917
8918         vcpu_put(vcpu);
8919         return 0;
8920 }
8921
8922 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8923 {
8924         struct fxregs_state *fxsave;
8925
8926         vcpu_load(vcpu);
8927
8928         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8929         memcpy(fpu->fpr, fxsave->st_space, 128);
8930         fpu->fcw = fxsave->cwd;
8931         fpu->fsw = fxsave->swd;
8932         fpu->ftwx = fxsave->twd;
8933         fpu->last_opcode = fxsave->fop;
8934         fpu->last_ip = fxsave->rip;
8935         fpu->last_dp = fxsave->rdp;
8936         memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
8937
8938         vcpu_put(vcpu);
8939         return 0;
8940 }
8941
8942 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8943 {
8944         struct fxregs_state *fxsave;
8945
8946         vcpu_load(vcpu);
8947
8948         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8949
8950         memcpy(fxsave->st_space, fpu->fpr, 128);
8951         fxsave->cwd = fpu->fcw;
8952         fxsave->swd = fpu->fsw;
8953         fxsave->twd = fpu->ftwx;
8954         fxsave->fop = fpu->last_opcode;
8955         fxsave->rip = fpu->last_ip;
8956         fxsave->rdp = fpu->last_dp;
8957         memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
8958
8959         vcpu_put(vcpu);
8960         return 0;
8961 }
8962
8963 static void store_regs(struct kvm_vcpu *vcpu)
8964 {
8965         BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8966
8967         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8968                 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8969
8970         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8971                 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8972
8973         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8974                 kvm_vcpu_ioctl_x86_get_vcpu_events(
8975                                 vcpu, &vcpu->run->s.regs.events);
8976 }
8977
8978 static int sync_regs(struct kvm_vcpu *vcpu)
8979 {
8980         if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8981                 return -EINVAL;
8982
8983         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8984                 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8985                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8986         }
8987         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8988                 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8989                         return -EINVAL;
8990                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8991         }
8992         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8993                 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8994                                 vcpu, &vcpu->run->s.regs.events))
8995                         return -EINVAL;
8996                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8997         }
8998
8999         return 0;
9000 }
9001
9002 static void fx_init(struct kvm_vcpu *vcpu)
9003 {
9004         fpstate_init(&vcpu->arch.guest_fpu->state);
9005         if (boot_cpu_has(X86_FEATURE_XSAVES))
9006                 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9007                         host_xcr0 | XSTATE_COMPACTION_ENABLED;
9008
9009         /*
9010          * Ensure guest xcr0 is valid for loading
9011          */
9012         vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9013
9014         vcpu->arch.cr0 |= X86_CR0_ET;
9015 }
9016
9017 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
9018 {
9019         void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
9020
9021         kvmclock_reset(vcpu);
9022
9023         kvm_x86_ops->vcpu_free(vcpu);
9024         free_cpumask_var(wbinvd_dirty_mask);
9025 }
9026
9027 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
9028                                                 unsigned int id)
9029 {
9030         struct kvm_vcpu *vcpu;
9031
9032         if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9033                 printk_once(KERN_WARNING
9034                 "kvm: SMP vm created on host with unstable TSC; "
9035                 "guest TSC will not be reliable\n");
9036
9037         vcpu = kvm_x86_ops->vcpu_create(kvm, id);
9038
9039         return vcpu;
9040 }
9041
9042 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
9043 {
9044         vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9045         vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9046         kvm_vcpu_mtrr_init(vcpu);
9047         vcpu_load(vcpu);
9048         kvm_vcpu_reset(vcpu, false);
9049         kvm_init_mmu(vcpu, false);
9050         vcpu_put(vcpu);
9051         return 0;
9052 }
9053
9054 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9055 {
9056         struct msr_data msr;
9057         struct kvm *kvm = vcpu->kvm;
9058
9059         kvm_hv_vcpu_postcreate(vcpu);
9060
9061         if (mutex_lock_killable(&vcpu->mutex))
9062                 return;
9063         vcpu_load(vcpu);
9064         msr.data = 0x0;
9065         msr.index = MSR_IA32_TSC;
9066         msr.host_initiated = true;
9067         kvm_write_tsc(vcpu, &msr);
9068         vcpu_put(vcpu);
9069
9070         /* poll control enabled by default */
9071         vcpu->arch.msr_kvm_poll_control = 1;
9072
9073         mutex_unlock(&vcpu->mutex);
9074
9075         if (!kvmclock_periodic_sync)
9076                 return;
9077
9078         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9079                                         KVMCLOCK_SYNC_PERIOD);
9080 }
9081
9082 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9083 {
9084         vcpu->arch.apf.msr_val = 0;
9085
9086         vcpu_load(vcpu);
9087         kvm_mmu_unload(vcpu);
9088         vcpu_put(vcpu);
9089
9090         kvm_x86_ops->vcpu_free(vcpu);
9091 }
9092
9093 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9094 {
9095         kvm_lapic_reset(vcpu, init_event);
9096
9097         vcpu->arch.hflags = 0;
9098
9099         vcpu->arch.smi_pending = 0;
9100         vcpu->arch.smi_count = 0;
9101         atomic_set(&vcpu->arch.nmi_queued, 0);
9102         vcpu->arch.nmi_pending = 0;
9103         vcpu->arch.nmi_injected = false;
9104         kvm_clear_interrupt_queue(vcpu);
9105         kvm_clear_exception_queue(vcpu);
9106         vcpu->arch.exception.pending = false;
9107
9108         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9109         kvm_update_dr0123(vcpu);
9110         vcpu->arch.dr6 = DR6_INIT;
9111         kvm_update_dr6(vcpu);
9112         vcpu->arch.dr7 = DR7_FIXED_1;
9113         kvm_update_dr7(vcpu);
9114
9115         vcpu->arch.cr2 = 0;
9116
9117         kvm_make_request(KVM_REQ_EVENT, vcpu);
9118         vcpu->arch.apf.msr_val = 0;
9119         vcpu->arch.st.msr_val = 0;
9120
9121         kvmclock_reset(vcpu);
9122
9123         kvm_clear_async_pf_completion_queue(vcpu);
9124         kvm_async_pf_hash_reset(vcpu);
9125         vcpu->arch.apf.halted = false;
9126
9127         if (kvm_mpx_supported()) {
9128                 void *mpx_state_buffer;
9129
9130                 /*
9131                  * To avoid have the INIT path from kvm_apic_has_events() that be
9132                  * called with loaded FPU and does not let userspace fix the state.
9133                  */
9134                 if (init_event)
9135                         kvm_put_guest_fpu(vcpu);
9136                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9137                                         XFEATURE_BNDREGS);
9138                 if (mpx_state_buffer)
9139                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9140                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9141                                         XFEATURE_BNDCSR);
9142                 if (mpx_state_buffer)
9143                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9144                 if (init_event)
9145                         kvm_load_guest_fpu(vcpu);
9146         }
9147
9148         if (!init_event) {
9149                 kvm_pmu_reset(vcpu);
9150                 vcpu->arch.smbase = 0x30000;
9151
9152                 vcpu->arch.msr_misc_features_enables = 0;
9153
9154                 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9155         }
9156
9157         memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9158         vcpu->arch.regs_avail = ~0;
9159         vcpu->arch.regs_dirty = ~0;
9160
9161         vcpu->arch.ia32_xss = 0;
9162
9163         kvm_x86_ops->vcpu_reset(vcpu, init_event);
9164 }
9165
9166 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9167 {
9168         struct kvm_segment cs;
9169
9170         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9171         cs.selector = vector << 8;
9172         cs.base = vector << 12;
9173         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9174         kvm_rip_write(vcpu, 0);
9175 }
9176
9177 int kvm_arch_hardware_enable(void)
9178 {
9179         struct kvm *kvm;
9180         struct kvm_vcpu *vcpu;
9181         int i;
9182         int ret;
9183         u64 local_tsc;
9184         u64 max_tsc = 0;
9185         bool stable, backwards_tsc = false;
9186
9187         kvm_shared_msr_cpu_online();
9188         ret = kvm_x86_ops->hardware_enable();
9189         if (ret != 0)
9190                 return ret;
9191
9192         local_tsc = rdtsc();
9193         stable = !kvm_check_tsc_unstable();
9194         list_for_each_entry(kvm, &vm_list, vm_list) {
9195                 kvm_for_each_vcpu(i, vcpu, kvm) {
9196                         if (!stable && vcpu->cpu == smp_processor_id())
9197                                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9198                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9199                                 backwards_tsc = true;
9200                                 if (vcpu->arch.last_host_tsc > max_tsc)
9201                                         max_tsc = vcpu->arch.last_host_tsc;
9202                         }
9203                 }
9204         }
9205
9206         /*
9207          * Sometimes, even reliable TSCs go backwards.  This happens on
9208          * platforms that reset TSC during suspend or hibernate actions, but
9209          * maintain synchronization.  We must compensate.  Fortunately, we can
9210          * detect that condition here, which happens early in CPU bringup,
9211          * before any KVM threads can be running.  Unfortunately, we can't
9212          * bring the TSCs fully up to date with real time, as we aren't yet far
9213          * enough into CPU bringup that we know how much real time has actually
9214          * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9215          * variables that haven't been updated yet.
9216          *
9217          * So we simply find the maximum observed TSC above, then record the
9218          * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
9219          * the adjustment will be applied.  Note that we accumulate
9220          * adjustments, in case multiple suspend cycles happen before some VCPU
9221          * gets a chance to run again.  In the event that no KVM threads get a
9222          * chance to run, we will miss the entire elapsed period, as we'll have
9223          * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9224          * loose cycle time.  This isn't too big a deal, since the loss will be
9225          * uniform across all VCPUs (not to mention the scenario is extremely
9226          * unlikely). It is possible that a second hibernate recovery happens
9227          * much faster than a first, causing the observed TSC here to be
9228          * smaller; this would require additional padding adjustment, which is
9229          * why we set last_host_tsc to the local tsc observed here.
9230          *
9231          * N.B. - this code below runs only on platforms with reliable TSC,
9232          * as that is the only way backwards_tsc is set above.  Also note
9233          * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9234          * have the same delta_cyc adjustment applied if backwards_tsc
9235          * is detected.  Note further, this adjustment is only done once,
9236          * as we reset last_host_tsc on all VCPUs to stop this from being
9237          * called multiple times (one for each physical CPU bringup).
9238          *
9239          * Platforms with unreliable TSCs don't have to deal with this, they
9240          * will be compensated by the logic in vcpu_load, which sets the TSC to
9241          * catchup mode.  This will catchup all VCPUs to real time, but cannot
9242          * guarantee that they stay in perfect synchronization.
9243          */
9244         if (backwards_tsc) {
9245                 u64 delta_cyc = max_tsc - local_tsc;
9246                 list_for_each_entry(kvm, &vm_list, vm_list) {
9247                         kvm->arch.backwards_tsc_observed = true;
9248                         kvm_for_each_vcpu(i, vcpu, kvm) {
9249                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9250                                 vcpu->arch.last_host_tsc = local_tsc;
9251                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9252                         }
9253
9254                         /*
9255                          * We have to disable TSC offset matching.. if you were
9256                          * booting a VM while issuing an S4 host suspend....
9257                          * you may have some problem.  Solving this issue is
9258                          * left as an exercise to the reader.
9259                          */
9260                         kvm->arch.last_tsc_nsec = 0;
9261                         kvm->arch.last_tsc_write = 0;
9262                 }
9263
9264         }
9265         return 0;
9266 }
9267
9268 void kvm_arch_hardware_disable(void)
9269 {
9270         kvm_x86_ops->hardware_disable();
9271         drop_user_return_notifiers();
9272 }
9273
9274 int kvm_arch_hardware_setup(void)
9275 {
9276         int r;
9277
9278         r = kvm_x86_ops->hardware_setup();
9279         if (r != 0)
9280                 return r;
9281
9282         if (kvm_has_tsc_control) {
9283                 /*
9284                  * Make sure the user can only configure tsc_khz values that
9285                  * fit into a signed integer.
9286                  * A min value is not calculated because it will always
9287                  * be 1 on all machines.
9288                  */
9289                 u64 max = min(0x7fffffffULL,
9290                               __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9291                 kvm_max_guest_tsc_khz = max;
9292
9293                 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9294         }
9295
9296         kvm_init_msr_list();
9297         return 0;
9298 }
9299
9300 void kvm_arch_hardware_unsetup(void)
9301 {
9302         kvm_x86_ops->hardware_unsetup();
9303 }
9304
9305 int kvm_arch_check_processor_compat(void)
9306 {
9307         return kvm_x86_ops->check_processor_compatibility();
9308 }
9309
9310 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9311 {
9312         return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9313 }
9314 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9315
9316 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9317 {
9318         return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9319 }
9320
9321 struct static_key kvm_no_apic_vcpu __read_mostly;
9322 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9323
9324 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9325 {
9326         struct page *page;
9327         int r;
9328
9329         vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9330         if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9331                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9332         else
9333                 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9334
9335         page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9336         if (!page) {
9337                 r = -ENOMEM;
9338                 goto fail;
9339         }
9340         vcpu->arch.pio_data = page_address(page);
9341
9342         kvm_set_tsc_khz(vcpu, max_tsc_khz);
9343
9344         r = kvm_mmu_create(vcpu);
9345         if (r < 0)
9346                 goto fail_free_pio_data;
9347
9348         if (irqchip_in_kernel(vcpu->kvm)) {
9349                 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9350                 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9351                 if (r < 0)
9352                         goto fail_mmu_destroy;
9353         } else
9354                 static_key_slow_inc(&kvm_no_apic_vcpu);
9355
9356         vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9357                                        GFP_KERNEL_ACCOUNT);
9358         if (!vcpu->arch.mce_banks) {
9359                 r = -ENOMEM;
9360                 goto fail_free_lapic;
9361         }
9362         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9363
9364         if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9365                                 GFP_KERNEL_ACCOUNT)) {
9366                 r = -ENOMEM;
9367                 goto fail_free_mce_banks;
9368         }
9369
9370         fx_init(vcpu);
9371
9372         vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9373
9374         vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9375
9376         vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9377
9378         kvm_async_pf_hash_reset(vcpu);
9379         kvm_pmu_init(vcpu);
9380
9381         vcpu->arch.pending_external_vector = -1;
9382         vcpu->arch.preempted_in_kernel = false;
9383
9384         kvm_hv_vcpu_init(vcpu);
9385
9386         return 0;
9387
9388 fail_free_mce_banks:
9389         kfree(vcpu->arch.mce_banks);
9390 fail_free_lapic:
9391         kvm_free_lapic(vcpu);
9392 fail_mmu_destroy:
9393         kvm_mmu_destroy(vcpu);
9394 fail_free_pio_data:
9395         free_page((unsigned long)vcpu->arch.pio_data);
9396 fail:
9397         return r;
9398 }
9399
9400 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9401 {
9402         int idx;
9403
9404         kvm_hv_vcpu_uninit(vcpu);
9405         kvm_pmu_destroy(vcpu);
9406         kfree(vcpu->arch.mce_banks);
9407         kvm_free_lapic(vcpu);
9408         idx = srcu_read_lock(&vcpu->kvm->srcu);
9409         kvm_mmu_destroy(vcpu);
9410         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9411         free_page((unsigned long)vcpu->arch.pio_data);
9412         if (!lapic_in_kernel(vcpu))
9413                 static_key_slow_dec(&kvm_no_apic_vcpu);
9414 }
9415
9416 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9417 {
9418         vcpu->arch.l1tf_flush_l1d = true;
9419         kvm_x86_ops->sched_in(vcpu, cpu);
9420 }
9421
9422 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9423 {
9424         if (type)
9425                 return -EINVAL;
9426
9427         INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9428         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9429         INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9430         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9431         atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9432
9433         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9434         set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9435         /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9436         set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9437                 &kvm->arch.irq_sources_bitmap);
9438
9439         raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9440         mutex_init(&kvm->arch.apic_map_lock);
9441         spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9442
9443         kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
9444         pvclock_update_vm_gtod_copy(kvm);
9445
9446         kvm->arch.guest_can_read_msr_platform_info = true;
9447
9448         INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9449         INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9450
9451         kvm_hv_init_vm(kvm);
9452         kvm_page_track_init(kvm);
9453         kvm_mmu_init_vm(kvm);
9454
9455         return kvm_x86_ops->vm_init(kvm);
9456 }
9457
9458 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9459 {
9460         vcpu_load(vcpu);
9461         kvm_mmu_unload(vcpu);
9462         vcpu_put(vcpu);
9463 }
9464
9465 static void kvm_free_vcpus(struct kvm *kvm)
9466 {
9467         unsigned int i;
9468         struct kvm_vcpu *vcpu;
9469
9470         /*
9471          * Unpin any mmu pages first.
9472          */
9473         kvm_for_each_vcpu(i, vcpu, kvm) {
9474                 kvm_clear_async_pf_completion_queue(vcpu);
9475                 kvm_unload_vcpu_mmu(vcpu);
9476         }
9477         kvm_for_each_vcpu(i, vcpu, kvm)
9478                 kvm_arch_vcpu_free(vcpu);
9479
9480         mutex_lock(&kvm->lock);
9481         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9482                 kvm->vcpus[i] = NULL;
9483
9484         atomic_set(&kvm->online_vcpus, 0);
9485         mutex_unlock(&kvm->lock);
9486 }
9487
9488 void kvm_arch_sync_events(struct kvm *kvm)
9489 {
9490         cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9491         cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9492         kvm_free_pit(kvm);
9493 }
9494
9495 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9496 {
9497         int i, r;
9498         unsigned long hva;
9499         struct kvm_memslots *slots = kvm_memslots(kvm);
9500         struct kvm_memory_slot *slot, old;
9501
9502         /* Called with kvm->slots_lock held.  */
9503         if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9504                 return -EINVAL;
9505
9506         slot = id_to_memslot(slots, id);
9507         if (size) {
9508                 if (slot->npages)
9509                         return -EEXIST;
9510
9511                 /*
9512                  * MAP_SHARED to prevent internal slot pages from being moved
9513                  * by fork()/COW.
9514                  */
9515                 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9516                               MAP_SHARED | MAP_ANONYMOUS, 0);
9517                 if (IS_ERR((void *)hva))
9518                         return PTR_ERR((void *)hva);
9519         } else {
9520                 if (!slot->npages)
9521                         return 0;
9522
9523                 hva = 0;
9524         }
9525
9526         old = *slot;
9527         for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9528                 struct kvm_userspace_memory_region m;
9529
9530                 m.slot = id | (i << 16);
9531                 m.flags = 0;
9532                 m.guest_phys_addr = gpa;
9533                 m.userspace_addr = hva;
9534                 m.memory_size = size;
9535                 r = __kvm_set_memory_region(kvm, &m);
9536                 if (r < 0)
9537                         return r;
9538         }
9539
9540         if (!size)
9541                 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
9542
9543         return 0;
9544 }
9545 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9546
9547 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9548 {
9549         int r;
9550
9551         mutex_lock(&kvm->slots_lock);
9552         r = __x86_set_memory_region(kvm, id, gpa, size);
9553         mutex_unlock(&kvm->slots_lock);
9554
9555         return r;
9556 }
9557 EXPORT_SYMBOL_GPL(x86_set_memory_region);
9558
9559 void kvm_arch_destroy_vm(struct kvm *kvm)
9560 {
9561         if (current->mm == kvm->mm) {
9562                 /*
9563                  * Free memory regions allocated on behalf of userspace,
9564                  * unless the the memory map has changed due to process exit
9565                  * or fd copying.
9566                  */
9567                 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9568                 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9569                 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9570         }
9571         if (kvm_x86_ops->vm_destroy)
9572                 kvm_x86_ops->vm_destroy(kvm);
9573         kvm_pic_destroy(kvm);
9574         kvm_ioapic_destroy(kvm);
9575         kvm_free_vcpus(kvm);
9576         kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9577         kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9578         kvm_mmu_uninit_vm(kvm);
9579         kvm_page_track_cleanup(kvm);
9580         kvm_hv_destroy_vm(kvm);
9581 }
9582
9583 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
9584                            struct kvm_memory_slot *dont)
9585 {
9586         int i;
9587
9588         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9589                 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
9590                         kvfree(free->arch.rmap[i]);
9591                         free->arch.rmap[i] = NULL;
9592                 }
9593                 if (i == 0)
9594                         continue;
9595
9596                 if (!dont || free->arch.lpage_info[i - 1] !=
9597                              dont->arch.lpage_info[i - 1]) {
9598                         kvfree(free->arch.lpage_info[i - 1]);
9599                         free->arch.lpage_info[i - 1] = NULL;
9600                 }
9601         }
9602
9603         kvm_page_track_free_memslot(free, dont);
9604 }
9605
9606 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9607                             unsigned long npages)
9608 {
9609         int i;
9610
9611         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9612                 struct kvm_lpage_info *linfo;
9613                 unsigned long ugfn;
9614                 int lpages;
9615                 int level = i + 1;
9616
9617                 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9618                                       slot->base_gfn, level) + 1;
9619
9620                 slot->arch.rmap[i] =
9621                         kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9622                                  GFP_KERNEL_ACCOUNT);
9623                 if (!slot->arch.rmap[i])
9624                         goto out_free;
9625                 if (i == 0)
9626                         continue;
9627
9628                 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9629                 if (!linfo)
9630                         goto out_free;
9631
9632                 slot->arch.lpage_info[i - 1] = linfo;
9633
9634                 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9635                         linfo[0].disallow_lpage = 1;
9636                 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9637                         linfo[lpages - 1].disallow_lpage = 1;
9638                 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9639                 /*
9640                  * If the gfn and userspace address are not aligned wrt each
9641                  * other, or if explicitly asked to, disable large page
9642                  * support for this slot
9643                  */
9644                 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9645                     !kvm_largepages_enabled()) {
9646                         unsigned long j;
9647
9648                         for (j = 0; j < lpages; ++j)
9649                                 linfo[j].disallow_lpage = 1;
9650                 }
9651         }
9652
9653         if (kvm_page_track_create_memslot(slot, npages))
9654                 goto out_free;
9655
9656         return 0;
9657
9658 out_free:
9659         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9660                 kvfree(slot->arch.rmap[i]);
9661                 slot->arch.rmap[i] = NULL;
9662                 if (i == 0)
9663                         continue;
9664
9665                 kvfree(slot->arch.lpage_info[i - 1]);
9666                 slot->arch.lpage_info[i - 1] = NULL;
9667         }
9668         return -ENOMEM;
9669 }
9670
9671 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9672 {
9673         /*
9674          * memslots->generation has been incremented.
9675          * mmio generation may have reached its maximum value.
9676          */
9677         kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9678 }
9679
9680 int kvm_arch_prepare_memory_region(struct kvm *kvm,
9681                                 struct kvm_memory_slot *memslot,
9682                                 const struct kvm_userspace_memory_region *mem,
9683                                 enum kvm_mr_change change)
9684 {
9685         return 0;
9686 }
9687
9688 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9689                                      struct kvm_memory_slot *new)
9690 {
9691         /* Still write protect RO slot */
9692         if (new->flags & KVM_MEM_READONLY) {
9693                 kvm_mmu_slot_remove_write_access(kvm, new);
9694                 return;
9695         }
9696
9697         /*
9698          * Call kvm_x86_ops dirty logging hooks when they are valid.
9699          *
9700          * kvm_x86_ops->slot_disable_log_dirty is called when:
9701          *
9702          *  - KVM_MR_CREATE with dirty logging is disabled
9703          *  - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9704          *
9705          * The reason is, in case of PML, we need to set D-bit for any slots
9706          * with dirty logging disabled in order to eliminate unnecessary GPA
9707          * logging in PML buffer (and potential PML buffer full VMEXT). This
9708          * guarantees leaving PML enabled during guest's lifetime won't have
9709          * any additional overhead from PML when guest is running with dirty
9710          * logging disabled for memory slots.
9711          *
9712          * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9713          * to dirty logging mode.
9714          *
9715          * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9716          *
9717          * In case of write protect:
9718          *
9719          * Write protect all pages for dirty logging.
9720          *
9721          * All the sptes including the large sptes which point to this
9722          * slot are set to readonly. We can not create any new large
9723          * spte on this slot until the end of the logging.
9724          *
9725          * See the comments in fast_page_fault().
9726          */
9727         if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9728                 if (kvm_x86_ops->slot_enable_log_dirty)
9729                         kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9730                 else
9731                         kvm_mmu_slot_remove_write_access(kvm, new);
9732         } else {
9733                 if (kvm_x86_ops->slot_disable_log_dirty)
9734                         kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9735         }
9736 }
9737
9738 void kvm_arch_commit_memory_region(struct kvm *kvm,
9739                                 const struct kvm_userspace_memory_region *mem,
9740                                 const struct kvm_memory_slot *old,
9741                                 const struct kvm_memory_slot *new,
9742                                 enum kvm_mr_change change)
9743 {
9744         if (!kvm->arch.n_requested_mmu_pages)
9745                 kvm_mmu_change_mmu_pages(kvm,
9746                                 kvm_mmu_calculate_default_mmu_pages(kvm));
9747
9748         /*
9749          * Dirty logging tracks sptes in 4k granularity, meaning that large
9750          * sptes have to be split.  If live migration is successful, the guest
9751          * in the source machine will be destroyed and large sptes will be
9752          * created in the destination. However, if the guest continues to run
9753          * in the source machine (for example if live migration fails), small
9754          * sptes will remain around and cause bad performance.
9755          *
9756          * Scan sptes if dirty logging has been stopped, dropping those
9757          * which can be collapsed into a single large-page spte.  Later
9758          * page faults will create the large-page sptes.
9759          *
9760          * There is no need to do this in any of the following cases:
9761          * CREATE:      No dirty mappings will already exist.
9762          * MOVE/DELETE: The old mappings will already have been cleaned up by
9763          *              kvm_arch_flush_shadow_memslot()
9764          */
9765         if (change == KVM_MR_FLAGS_ONLY &&
9766                 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9767                 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9768                 kvm_mmu_zap_collapsible_sptes(kvm, new);
9769
9770         /*
9771          * Set up write protection and/or dirty logging for the new slot.
9772          *
9773          * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9774          * been zapped so no dirty logging staff is needed for old slot. For
9775          * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9776          * new and it's also covered when dealing with the new slot.
9777          *
9778          * FIXME: const-ify all uses of struct kvm_memory_slot.
9779          */
9780         if (change != KVM_MR_DELETE)
9781                 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
9782 }
9783
9784 void kvm_arch_flush_shadow_all(struct kvm *kvm)
9785 {
9786         kvm_mmu_zap_all(kvm);
9787 }
9788
9789 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9790                                    struct kvm_memory_slot *slot)
9791 {
9792         kvm_page_track_flush_slot(kvm, slot);
9793 }
9794
9795 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9796 {
9797         return (is_guest_mode(vcpu) &&
9798                         kvm_x86_ops->guest_apic_has_interrupt &&
9799                         kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9800 }
9801
9802 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9803 {
9804         if (!list_empty_careful(&vcpu->async_pf.done))
9805                 return true;
9806
9807         if (kvm_apic_has_events(vcpu))
9808                 return true;
9809
9810         if (vcpu->arch.pv.pv_unhalted)
9811                 return true;
9812
9813         if (vcpu->arch.exception.pending)
9814                 return true;
9815
9816         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9817             (vcpu->arch.nmi_pending &&
9818              kvm_x86_ops->nmi_allowed(vcpu)))
9819                 return true;
9820
9821         if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9822             (vcpu->arch.smi_pending && !is_smm(vcpu)))
9823                 return true;
9824
9825         if (kvm_arch_interrupt_allowed(vcpu) &&
9826             (kvm_cpu_has_interrupt(vcpu) ||
9827             kvm_guest_apic_has_interrupt(vcpu)))
9828                 return true;
9829
9830         if (kvm_hv_has_stimer_pending(vcpu))
9831                 return true;
9832
9833         return false;
9834 }
9835
9836 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9837 {
9838         return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
9839 }
9840
9841 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
9842 {
9843         if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
9844                 return true;
9845
9846         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9847                 kvm_test_request(KVM_REQ_SMI, vcpu) ||
9848                  kvm_test_request(KVM_REQ_EVENT, vcpu))
9849                 return true;
9850
9851         if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
9852                 return true;
9853
9854         return false;
9855 }
9856
9857 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9858 {
9859         return vcpu->arch.preempted_in_kernel;
9860 }
9861
9862 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
9863 {
9864         return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
9865 }
9866
9867 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9868 {
9869         return kvm_x86_ops->interrupt_allowed(vcpu);
9870 }
9871
9872 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
9873 {
9874         if (is_64_bit_mode(vcpu))
9875                 return kvm_rip_read(vcpu);
9876         return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9877                      kvm_rip_read(vcpu));
9878 }
9879 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
9880
9881 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9882 {
9883         return kvm_get_linear_rip(vcpu) == linear_rip;
9884 }
9885 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9886
9887 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9888 {
9889         unsigned long rflags;
9890
9891         rflags = kvm_x86_ops->get_rflags(vcpu);
9892         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9893                 rflags &= ~X86_EFLAGS_TF;
9894         return rflags;
9895 }
9896 EXPORT_SYMBOL_GPL(kvm_get_rflags);
9897
9898 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9899 {
9900         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
9901             kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
9902                 rflags |= X86_EFLAGS_TF;
9903         kvm_x86_ops->set_rflags(vcpu, rflags);
9904 }
9905
9906 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9907 {
9908         __kvm_set_rflags(vcpu, rflags);
9909         kvm_make_request(KVM_REQ_EVENT, vcpu);
9910 }
9911 EXPORT_SYMBOL_GPL(kvm_set_rflags);
9912
9913 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9914 {
9915         int r;
9916
9917         if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
9918               work->wakeup_all)
9919                 return;
9920
9921         r = kvm_mmu_reload(vcpu);
9922         if (unlikely(r))
9923                 return;
9924
9925         if (!vcpu->arch.mmu->direct_map &&
9926               work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
9927                 return;
9928
9929         vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
9930 }
9931
9932 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9933 {
9934         return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9935 }
9936
9937 static inline u32 kvm_async_pf_next_probe(u32 key)
9938 {
9939         return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9940 }
9941
9942 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9943 {
9944         u32 key = kvm_async_pf_hash_fn(gfn);
9945
9946         while (vcpu->arch.apf.gfns[key] != ~0)
9947                 key = kvm_async_pf_next_probe(key);
9948
9949         vcpu->arch.apf.gfns[key] = gfn;
9950 }
9951
9952 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9953 {
9954         int i;
9955         u32 key = kvm_async_pf_hash_fn(gfn);
9956
9957         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
9958                      (vcpu->arch.apf.gfns[key] != gfn &&
9959                       vcpu->arch.apf.gfns[key] != ~0); i++)
9960                 key = kvm_async_pf_next_probe(key);
9961
9962         return key;
9963 }
9964
9965 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9966 {
9967         return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9968 }
9969
9970 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9971 {
9972         u32 i, j, k;
9973
9974         i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9975         while (true) {
9976                 vcpu->arch.apf.gfns[i] = ~0;
9977                 do {
9978                         j = kvm_async_pf_next_probe(j);
9979                         if (vcpu->arch.apf.gfns[j] == ~0)
9980                                 return;
9981                         k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9982                         /*
9983                          * k lies cyclically in ]i,j]
9984                          * |    i.k.j |
9985                          * |....j i.k.| or  |.k..j i...|
9986                          */
9987                 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9988                 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9989                 i = j;
9990         }
9991 }
9992
9993 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9994 {
9995
9996         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9997                                       sizeof(val));
9998 }
9999
10000 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
10001 {
10002
10003         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10004                                       sizeof(u32));
10005 }
10006
10007 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10008 {
10009         if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10010                 return false;
10011
10012         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10013             (vcpu->arch.apf.send_user_only &&
10014              kvm_x86_ops->get_cpl(vcpu) == 0))
10015                 return false;
10016
10017         return true;
10018 }
10019
10020 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10021 {
10022         if (unlikely(!lapic_in_kernel(vcpu) ||
10023                      kvm_event_needs_reinjection(vcpu) ||
10024                      vcpu->arch.exception.pending))
10025                 return false;
10026
10027         if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10028                 return false;
10029
10030         /*
10031          * If interrupts are off we cannot even use an artificial
10032          * halt state.
10033          */
10034         return kvm_x86_ops->interrupt_allowed(vcpu);
10035 }
10036
10037 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10038                                      struct kvm_async_pf *work)
10039 {
10040         struct x86_exception fault;
10041
10042         trace_kvm_async_pf_not_present(work->arch.token, work->gva);
10043         kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10044
10045         if (kvm_can_deliver_async_pf(vcpu) &&
10046             !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
10047                 fault.vector = PF_VECTOR;
10048                 fault.error_code_valid = true;
10049                 fault.error_code = 0;
10050                 fault.nested_page_fault = false;
10051                 fault.address = work->arch.token;
10052                 fault.async_page_fault = true;
10053                 kvm_inject_page_fault(vcpu, &fault);
10054         } else {
10055                 /*
10056                  * It is not possible to deliver a paravirtualized asynchronous
10057                  * page fault, but putting the guest in an artificial halt state
10058                  * can be beneficial nevertheless: if an interrupt arrives, we
10059                  * can deliver it timely and perhaps the guest will schedule
10060                  * another process.  When the instruction that triggered a page
10061                  * fault is retried, hopefully the page will be ready in the host.
10062                  */
10063                 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10064         }
10065 }
10066
10067 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10068                                  struct kvm_async_pf *work)
10069 {
10070         struct x86_exception fault;
10071         u32 val;
10072
10073         if (work->wakeup_all)
10074                 work->arch.token = ~0; /* broadcast wakeup */
10075         else
10076                 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10077         trace_kvm_async_pf_ready(work->arch.token, work->gva);
10078
10079         if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10080             !apf_get_user(vcpu, &val)) {
10081                 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10082                     vcpu->arch.exception.pending &&
10083                     vcpu->arch.exception.nr == PF_VECTOR &&
10084                     !apf_put_user(vcpu, 0)) {
10085                         vcpu->arch.exception.injected = false;
10086                         vcpu->arch.exception.pending = false;
10087                         vcpu->arch.exception.nr = 0;
10088                         vcpu->arch.exception.has_error_code = false;
10089                         vcpu->arch.exception.error_code = 0;
10090                         vcpu->arch.exception.has_payload = false;
10091                         vcpu->arch.exception.payload = 0;
10092                 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10093                         fault.vector = PF_VECTOR;
10094                         fault.error_code_valid = true;
10095                         fault.error_code = 0;
10096                         fault.nested_page_fault = false;
10097                         fault.address = work->arch.token;
10098                         fault.async_page_fault = true;
10099                         kvm_inject_page_fault(vcpu, &fault);
10100                 }
10101         }
10102         vcpu->arch.apf.halted = false;
10103         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10104 }
10105
10106 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10107 {
10108         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10109                 return true;
10110         else
10111                 return kvm_can_do_async_pf(vcpu);
10112 }
10113
10114 void kvm_arch_start_assignment(struct kvm *kvm)
10115 {
10116         atomic_inc(&kvm->arch.assigned_device_count);
10117 }
10118 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10119
10120 void kvm_arch_end_assignment(struct kvm *kvm)
10121 {
10122         atomic_dec(&kvm->arch.assigned_device_count);
10123 }
10124 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10125
10126 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10127 {
10128         return atomic_read(&kvm->arch.assigned_device_count);
10129 }
10130 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10131
10132 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10133 {
10134         atomic_inc(&kvm->arch.noncoherent_dma_count);
10135 }
10136 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10137
10138 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10139 {
10140         atomic_dec(&kvm->arch.noncoherent_dma_count);
10141 }
10142 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10143
10144 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10145 {
10146         return atomic_read(&kvm->arch.noncoherent_dma_count);
10147 }
10148 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10149
10150 bool kvm_arch_has_irq_bypass(void)
10151 {
10152         return true;
10153 }
10154
10155 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10156                                       struct irq_bypass_producer *prod)
10157 {
10158         struct kvm_kernel_irqfd *irqfd =
10159                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10160
10161         irqfd->producer = prod;
10162
10163         return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10164                                            prod->irq, irqfd->gsi, 1);
10165 }
10166
10167 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10168                                       struct irq_bypass_producer *prod)
10169 {
10170         int ret;
10171         struct kvm_kernel_irqfd *irqfd =
10172                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10173
10174         WARN_ON(irqfd->producer != prod);
10175         irqfd->producer = NULL;
10176
10177         /*
10178          * When producer of consumer is unregistered, we change back to
10179          * remapped mode, so we can re-use the current implementation
10180          * when the irq is masked/disabled or the consumer side (KVM
10181          * int this case doesn't want to receive the interrupts.
10182         */
10183         ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10184         if (ret)
10185                 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10186                        " fails: %d\n", irqfd->consumer.token, ret);
10187 }
10188
10189 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10190                                    uint32_t guest_irq, bool set)
10191 {
10192         return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10193 }
10194
10195 bool kvm_vector_hashing_enabled(void)
10196 {
10197         return vector_hashing;
10198 }
10199 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
10200
10201 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10202 {
10203         return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10204 }
10205 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10206
10207
10208 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10209 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10210 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10211 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10212 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10213 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10214 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10215 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10216 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10217 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10218 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10219 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10220 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10221 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10222 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10223 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10224 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10225 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10226 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10227 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);