2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
30 #include <linux/clocksource.h>
31 #include <linux/interrupt.h>
32 #include <linux/kvm.h>
34 #include <linux/vmalloc.h>
35 #include <linux/module.h>
36 #include <linux/mman.h>
37 #include <linux/highmem.h>
38 #include <linux/iommu.h>
39 #include <linux/intel-iommu.h>
40 #include <linux/cpufreq.h>
41 #include <linux/user-return-notifier.h>
42 #include <linux/srcu.h>
43 #include <linux/slab.h>
44 #include <linux/perf_event.h>
45 #include <linux/uaccess.h>
46 #include <linux/hash.h>
47 #include <linux/pci.h>
48 #include <trace/events/kvm.h>
50 #define CREATE_TRACE_POINTS
53 #include <asm/debugreg.h>
60 #include <asm/pvclock.h>
61 #include <asm/div64.h>
63 #define MAX_IO_MSRS 256
64 #define KVM_MAX_MCE_BANKS 32
65 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
67 #define emul_to_vcpu(ctxt) \
68 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
71 * - enable syscall per default because its emulated by KVM
72 * - enable LME and LMA per default on 64 bit KVM
76 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
78 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
81 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
82 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
84 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
85 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
86 struct kvm_cpuid_entry2 __user *entries);
87 static void process_nmi(struct kvm_vcpu *vcpu);
89 struct kvm_x86_ops *kvm_x86_ops;
90 EXPORT_SYMBOL_GPL(kvm_x86_ops);
93 module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
95 bool kvm_has_tsc_control;
96 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97 u32 kvm_max_guest_tsc_khz;
98 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
100 #define KVM_NR_SHARED_MSRS 16
102 struct kvm_shared_msrs_global {
104 u32 msrs[KVM_NR_SHARED_MSRS];
107 struct kvm_shared_msrs {
108 struct user_return_notifier urn;
110 struct kvm_shared_msr_values {
113 } values[KVM_NR_SHARED_MSRS];
116 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
117 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
119 struct kvm_stats_debugfs_item debugfs_entries[] = {
120 { "pf_fixed", VCPU_STAT(pf_fixed) },
121 { "pf_guest", VCPU_STAT(pf_guest) },
122 { "tlb_flush", VCPU_STAT(tlb_flush) },
123 { "invlpg", VCPU_STAT(invlpg) },
124 { "exits", VCPU_STAT(exits) },
125 { "io_exits", VCPU_STAT(io_exits) },
126 { "mmio_exits", VCPU_STAT(mmio_exits) },
127 { "signal_exits", VCPU_STAT(signal_exits) },
128 { "irq_window", VCPU_STAT(irq_window_exits) },
129 { "nmi_window", VCPU_STAT(nmi_window_exits) },
130 { "halt_exits", VCPU_STAT(halt_exits) },
131 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
132 { "hypercalls", VCPU_STAT(hypercalls) },
133 { "request_irq", VCPU_STAT(request_irq_exits) },
134 { "irq_exits", VCPU_STAT(irq_exits) },
135 { "host_state_reload", VCPU_STAT(host_state_reload) },
136 { "efer_reload", VCPU_STAT(efer_reload) },
137 { "fpu_reload", VCPU_STAT(fpu_reload) },
138 { "insn_emulation", VCPU_STAT(insn_emulation) },
139 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
140 { "irq_injections", VCPU_STAT(irq_injections) },
141 { "nmi_injections", VCPU_STAT(nmi_injections) },
142 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
143 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
144 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
145 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
146 { "mmu_flooded", VM_STAT(mmu_flooded) },
147 { "mmu_recycled", VM_STAT(mmu_recycled) },
148 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
149 { "mmu_unsync", VM_STAT(mmu_unsync) },
150 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
151 { "largepages", VM_STAT(lpages) },
155 u64 __read_mostly host_xcr0;
157 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
159 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
162 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
163 vcpu->arch.apf.gfns[i] = ~0;
166 static void kvm_on_user_return(struct user_return_notifier *urn)
169 struct kvm_shared_msrs *locals
170 = container_of(urn, struct kvm_shared_msrs, urn);
171 struct kvm_shared_msr_values *values;
173 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
174 values = &locals->values[slot];
175 if (values->host != values->curr) {
176 wrmsrl(shared_msrs_global.msrs[slot], values->host);
177 values->curr = values->host;
180 locals->registered = false;
181 user_return_notifier_unregister(urn);
184 static void shared_msr_update(unsigned slot, u32 msr)
186 struct kvm_shared_msrs *smsr;
189 smsr = &__get_cpu_var(shared_msrs);
190 /* only read, and nobody should modify it at this time,
191 * so don't need lock */
192 if (slot >= shared_msrs_global.nr) {
193 printk(KERN_ERR "kvm: invalid MSR slot!");
196 rdmsrl_safe(msr, &value);
197 smsr->values[slot].host = value;
198 smsr->values[slot].curr = value;
201 void kvm_define_shared_msr(unsigned slot, u32 msr)
203 if (slot >= shared_msrs_global.nr)
204 shared_msrs_global.nr = slot + 1;
205 shared_msrs_global.msrs[slot] = msr;
206 /* we need ensured the shared_msr_global have been updated */
209 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
211 static void kvm_shared_msr_cpu_online(void)
215 for (i = 0; i < shared_msrs_global.nr; ++i)
216 shared_msr_update(i, shared_msrs_global.msrs[i]);
219 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
223 if (((value ^ smsr->values[slot].curr) & mask) == 0)
225 smsr->values[slot].curr = value;
226 wrmsrl(shared_msrs_global.msrs[slot], value);
227 if (!smsr->registered) {
228 smsr->urn.on_user_return = kvm_on_user_return;
229 user_return_notifier_register(&smsr->urn);
230 smsr->registered = true;
233 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
235 static void drop_user_return_notifiers(void *ignore)
237 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
239 if (smsr->registered)
240 kvm_on_user_return(&smsr->urn);
243 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
245 if (irqchip_in_kernel(vcpu->kvm))
246 return vcpu->arch.apic_base;
248 return vcpu->arch.apic_base;
250 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
252 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
254 /* TODO: reserve bits check */
255 if (irqchip_in_kernel(vcpu->kvm))
256 kvm_lapic_set_base(vcpu, data);
258 vcpu->arch.apic_base = data;
260 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
262 #define EXCPT_BENIGN 0
263 #define EXCPT_CONTRIBUTORY 1
266 static int exception_class(int vector)
276 return EXCPT_CONTRIBUTORY;
283 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
284 unsigned nr, bool has_error, u32 error_code,
290 kvm_make_request(KVM_REQ_EVENT, vcpu);
292 if (!vcpu->arch.exception.pending) {
294 vcpu->arch.exception.pending = true;
295 vcpu->arch.exception.has_error_code = has_error;
296 vcpu->arch.exception.nr = nr;
297 vcpu->arch.exception.error_code = error_code;
298 vcpu->arch.exception.reinject = reinject;
302 /* to check exception */
303 prev_nr = vcpu->arch.exception.nr;
304 if (prev_nr == DF_VECTOR) {
305 /* triple fault -> shutdown */
306 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
309 class1 = exception_class(prev_nr);
310 class2 = exception_class(nr);
311 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
312 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
313 /* generate double fault per SDM Table 5-5 */
314 vcpu->arch.exception.pending = true;
315 vcpu->arch.exception.has_error_code = true;
316 vcpu->arch.exception.nr = DF_VECTOR;
317 vcpu->arch.exception.error_code = 0;
319 /* replace previous exception with a new one in a hope
320 that instruction re-execution will regenerate lost
325 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
327 kvm_multiple_exception(vcpu, nr, false, 0, false);
329 EXPORT_SYMBOL_GPL(kvm_queue_exception);
331 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
333 kvm_multiple_exception(vcpu, nr, false, 0, true);
335 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
337 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
340 kvm_inject_gp(vcpu, 0);
342 kvm_x86_ops->skip_emulated_instruction(vcpu);
344 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
346 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
348 ++vcpu->stat.pf_guest;
349 vcpu->arch.cr2 = fault->address;
350 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
352 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
354 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
356 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
357 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
359 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
362 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
364 atomic_inc(&vcpu->arch.nmi_queued);
365 kvm_make_request(KVM_REQ_NMI, vcpu);
367 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
369 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
371 kvm_multiple_exception(vcpu, nr, true, error_code, false);
373 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
375 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
377 kvm_multiple_exception(vcpu, nr, true, error_code, true);
379 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
382 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
383 * a #GP and return false.
385 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
387 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
389 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
392 EXPORT_SYMBOL_GPL(kvm_require_cpl);
395 * This function will be used to read from the physical memory of the currently
396 * running guest. The difference to kvm_read_guest_page is that this function
397 * can read from guest physical or from the guest's guest physical memory.
399 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
400 gfn_t ngfn, void *data, int offset, int len,
406 ngpa = gfn_to_gpa(ngfn);
407 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
408 if (real_gfn == UNMAPPED_GVA)
411 real_gfn = gpa_to_gfn(real_gfn);
413 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
415 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
417 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
418 void *data, int offset, int len, u32 access)
420 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
421 data, offset, len, access);
425 * Load the pae pdptrs. Return true is they are all valid.
427 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
429 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
430 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
433 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
435 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
436 offset * sizeof(u64), sizeof(pdpte),
437 PFERR_USER_MASK|PFERR_WRITE_MASK);
442 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
443 if (is_present_gpte(pdpte[i]) &&
444 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
451 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
452 __set_bit(VCPU_EXREG_PDPTR,
453 (unsigned long *)&vcpu->arch.regs_avail);
454 __set_bit(VCPU_EXREG_PDPTR,
455 (unsigned long *)&vcpu->arch.regs_dirty);
460 EXPORT_SYMBOL_GPL(load_pdptrs);
462 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
464 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
470 if (is_long_mode(vcpu) || !is_pae(vcpu))
473 if (!test_bit(VCPU_EXREG_PDPTR,
474 (unsigned long *)&vcpu->arch.regs_avail))
477 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
478 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
479 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
480 PFERR_USER_MASK | PFERR_WRITE_MASK);
483 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
489 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
491 unsigned long old_cr0 = kvm_read_cr0(vcpu);
492 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
493 X86_CR0_CD | X86_CR0_NW;
498 if (cr0 & 0xffffffff00000000UL)
502 cr0 &= ~CR0_RESERVED_BITS;
504 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
507 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
510 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
512 if ((vcpu->arch.efer & EFER_LME)) {
517 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
522 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
527 kvm_x86_ops->set_cr0(vcpu, cr0);
529 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
530 kvm_clear_async_pf_completion_queue(vcpu);
531 kvm_async_pf_hash_reset(vcpu);
534 if ((cr0 ^ old_cr0) & update_bits)
535 kvm_mmu_reset_context(vcpu);
538 EXPORT_SYMBOL_GPL(kvm_set_cr0);
540 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
542 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
544 EXPORT_SYMBOL_GPL(kvm_lmsw);
546 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
550 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
551 if (index != XCR_XFEATURE_ENABLED_MASK)
554 if (kvm_x86_ops->get_cpl(vcpu) != 0)
556 if (!(xcr0 & XSTATE_FP))
558 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
560 if (xcr0 & ~host_xcr0)
562 vcpu->arch.xcr0 = xcr0;
563 vcpu->guest_xcr0_loaded = 0;
567 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
569 if (__kvm_set_xcr(vcpu, index, xcr)) {
570 kvm_inject_gp(vcpu, 0);
575 EXPORT_SYMBOL_GPL(kvm_set_xcr);
577 static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
579 struct kvm_cpuid_entry2 *best;
581 best = kvm_find_cpuid_entry(vcpu, 1, 0);
582 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
585 static bool guest_cpuid_has_smep(struct kvm_vcpu *vcpu)
587 struct kvm_cpuid_entry2 *best;
589 best = kvm_find_cpuid_entry(vcpu, 7, 0);
590 return best && (best->ebx & bit(X86_FEATURE_SMEP));
593 static bool guest_cpuid_has_fsgsbase(struct kvm_vcpu *vcpu)
595 struct kvm_cpuid_entry2 *best;
597 best = kvm_find_cpuid_entry(vcpu, 7, 0);
598 return best && (best->ebx & bit(X86_FEATURE_FSGSBASE));
601 static void update_cpuid(struct kvm_vcpu *vcpu)
603 struct kvm_cpuid_entry2 *best;
604 struct kvm_lapic *apic = vcpu->arch.apic;
606 best = kvm_find_cpuid_entry(vcpu, 1, 0);
610 /* Update OSXSAVE bit */
611 if (cpu_has_xsave && best->function == 0x1) {
612 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
613 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
614 best->ecx |= bit(X86_FEATURE_OSXSAVE);
618 if (best->ecx & bit(X86_FEATURE_TSC_DEADLINE_TIMER))
619 apic->lapic_timer.timer_mode_mask = 3 << 17;
621 apic->lapic_timer.timer_mode_mask = 1 << 17;
625 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
627 unsigned long old_cr4 = kvm_read_cr4(vcpu);
628 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
629 X86_CR4_PAE | X86_CR4_SMEP;
630 if (cr4 & CR4_RESERVED_BITS)
633 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
636 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
639 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
642 if (is_long_mode(vcpu)) {
643 if (!(cr4 & X86_CR4_PAE))
645 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
646 && ((cr4 ^ old_cr4) & pdptr_bits)
647 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
651 if (kvm_x86_ops->set_cr4(vcpu, cr4))
654 if ((cr4 ^ old_cr4) & pdptr_bits)
655 kvm_mmu_reset_context(vcpu);
657 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
662 EXPORT_SYMBOL_GPL(kvm_set_cr4);
664 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
666 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
667 kvm_mmu_sync_roots(vcpu);
668 kvm_mmu_flush_tlb(vcpu);
672 if (is_long_mode(vcpu)) {
673 if (cr3 & CR3_L_MODE_RESERVED_BITS)
677 if (cr3 & CR3_PAE_RESERVED_BITS)
679 if (is_paging(vcpu) &&
680 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
684 * We don't check reserved bits in nonpae mode, because
685 * this isn't enforced, and VMware depends on this.
690 * Does the new cr3 value map to physical memory? (Note, we
691 * catch an invalid cr3 even in real-mode, because it would
692 * cause trouble later on when we turn on paging anyway.)
694 * A real CPU would silently accept an invalid cr3 and would
695 * attempt to use it - with largely undefined (and often hard
696 * to debug) behavior on the guest side.
698 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
700 vcpu->arch.cr3 = cr3;
701 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
702 vcpu->arch.mmu.new_cr3(vcpu);
705 EXPORT_SYMBOL_GPL(kvm_set_cr3);
707 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
709 if (cr8 & CR8_RESERVED_BITS)
711 if (irqchip_in_kernel(vcpu->kvm))
712 kvm_lapic_set_tpr(vcpu, cr8);
714 vcpu->arch.cr8 = cr8;
717 EXPORT_SYMBOL_GPL(kvm_set_cr8);
719 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
721 if (irqchip_in_kernel(vcpu->kvm))
722 return kvm_lapic_get_cr8(vcpu);
724 return vcpu->arch.cr8;
726 EXPORT_SYMBOL_GPL(kvm_get_cr8);
728 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
732 vcpu->arch.db[dr] = val;
733 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
734 vcpu->arch.eff_db[dr] = val;
737 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
741 if (val & 0xffffffff00000000ULL)
743 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
750 if (val & 0xffffffff00000000ULL)
752 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
753 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
754 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
755 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
763 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
767 res = __kvm_set_dr(vcpu, dr, val);
769 kvm_queue_exception(vcpu, UD_VECTOR);
771 kvm_inject_gp(vcpu, 0);
775 EXPORT_SYMBOL_GPL(kvm_set_dr);
777 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
781 *val = vcpu->arch.db[dr];
784 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
788 *val = vcpu->arch.dr6;
791 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
795 *val = vcpu->arch.dr7;
802 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
804 if (_kvm_get_dr(vcpu, dr, val)) {
805 kvm_queue_exception(vcpu, UD_VECTOR);
810 EXPORT_SYMBOL_GPL(kvm_get_dr);
813 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
814 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
816 * This list is modified at module load time to reflect the
817 * capabilities of the host cpu. This capabilities test skips MSRs that are
818 * kvm-specific. Those are put in the beginning of the list.
821 #define KVM_SAVE_MSRS_BEGIN 9
822 static u32 msrs_to_save[] = {
823 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
824 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
825 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
826 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
827 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
830 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
832 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
835 static unsigned num_msrs_to_save;
837 static u32 emulated_msrs[] = {
838 MSR_IA32_TSCDEADLINE,
839 MSR_IA32_MISC_ENABLE,
844 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
846 u64 old_efer = vcpu->arch.efer;
848 if (efer & efer_reserved_bits)
852 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
855 if (efer & EFER_FFXSR) {
856 struct kvm_cpuid_entry2 *feat;
858 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
859 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
863 if (efer & EFER_SVME) {
864 struct kvm_cpuid_entry2 *feat;
866 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
867 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
872 efer |= vcpu->arch.efer & EFER_LMA;
874 kvm_x86_ops->set_efer(vcpu, efer);
876 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
878 /* Update reserved bits */
879 if ((efer ^ old_efer) & EFER_NX)
880 kvm_mmu_reset_context(vcpu);
885 void kvm_enable_efer_bits(u64 mask)
887 efer_reserved_bits &= ~mask;
889 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
893 * Writes msr value into into the appropriate "register".
894 * Returns 0 on success, non-0 otherwise.
895 * Assumes vcpu_load() was already called.
897 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
899 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
903 * Adapt set_msr() to msr_io()'s calling convention
905 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
907 return kvm_set_msr(vcpu, index, *data);
910 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
914 struct pvclock_wall_clock wc;
915 struct timespec boot;
920 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
925 ++version; /* first time write, random junk */
929 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
932 * The guest calculates current wall clock time by adding
933 * system time (updated by kvm_guest_time_update below) to the
934 * wall clock specified here. guest system time equals host
935 * system time for us, thus we must fill in host boot time here.
939 wc.sec = boot.tv_sec;
940 wc.nsec = boot.tv_nsec;
941 wc.version = version;
943 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
946 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
949 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
951 uint32_t quotient, remainder;
953 /* Don't try to replace with do_div(), this one calculates
954 * "(dividend << 32) / divisor" */
956 : "=a" (quotient), "=d" (remainder)
957 : "0" (0), "1" (dividend), "r" (divisor) );
961 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
962 s8 *pshift, u32 *pmultiplier)
969 tps64 = base_khz * 1000LL;
970 scaled64 = scaled_khz * 1000LL;
971 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
976 tps32 = (uint32_t)tps64;
977 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
978 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
986 *pmultiplier = div_frac(scaled64, tps32);
988 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
989 __func__, base_khz, scaled_khz, shift, *pmultiplier);
992 static inline u64 get_kernel_ns(void)
996 WARN_ON(preemptible());
998 monotonic_to_bootbased(&ts);
999 return timespec_to_ns(&ts);
1002 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1003 unsigned long max_tsc_khz;
1005 static inline int kvm_tsc_changes_freq(void)
1007 int cpu = get_cpu();
1008 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
1009 cpufreq_quick_get(cpu) != 0;
1014 u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
1016 if (vcpu->arch.virtual_tsc_khz)
1017 return vcpu->arch.virtual_tsc_khz;
1019 return __this_cpu_read(cpu_tsc_khz);
1022 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1026 WARN_ON(preemptible());
1027 if (kvm_tsc_changes_freq())
1028 printk_once(KERN_WARNING
1029 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
1030 ret = nsec * vcpu_tsc_khz(vcpu);
1031 do_div(ret, USEC_PER_SEC);
1035 static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1037 /* Compute a scale to convert nanoseconds in TSC cycles */
1038 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1039 &vcpu->arch.tsc_catchup_shift,
1040 &vcpu->arch.tsc_catchup_mult);
1043 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1045 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1046 vcpu->arch.tsc_catchup_mult,
1047 vcpu->arch.tsc_catchup_shift);
1048 tsc += vcpu->arch.last_tsc_write;
1052 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1054 struct kvm *kvm = vcpu->kvm;
1055 u64 offset, ns, elapsed;
1056 unsigned long flags;
1059 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1060 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1061 ns = get_kernel_ns();
1062 elapsed = ns - kvm->arch.last_tsc_nsec;
1063 sdiff = data - kvm->arch.last_tsc_write;
1068 * Special case: close write to TSC within 5 seconds of
1069 * another CPU is interpreted as an attempt to synchronize
1070 * The 5 seconds is to accommodate host load / swapping as
1071 * well as any reset of TSC during the boot process.
1073 * In that case, for a reliable TSC, we can match TSC offsets,
1074 * or make a best guest using elapsed value.
1076 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
1077 elapsed < 5ULL * NSEC_PER_SEC) {
1078 if (!check_tsc_unstable()) {
1079 offset = kvm->arch.last_tsc_offset;
1080 pr_debug("kvm: matched tsc offset for %llu\n", data);
1082 u64 delta = nsec_to_cycles(vcpu, elapsed);
1084 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1086 ns = kvm->arch.last_tsc_nsec;
1088 kvm->arch.last_tsc_nsec = ns;
1089 kvm->arch.last_tsc_write = data;
1090 kvm->arch.last_tsc_offset = offset;
1091 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1092 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1094 /* Reset of TSC must disable overshoot protection below */
1095 vcpu->arch.hv_clock.tsc_timestamp = 0;
1096 vcpu->arch.last_tsc_write = data;
1097 vcpu->arch.last_tsc_nsec = ns;
1099 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1101 static int kvm_guest_time_update(struct kvm_vcpu *v)
1103 unsigned long flags;
1104 struct kvm_vcpu_arch *vcpu = &v->arch;
1106 unsigned long this_tsc_khz;
1107 s64 kernel_ns, max_kernel_ns;
1110 /* Keep irq disabled to prevent changes to the clock */
1111 local_irq_save(flags);
1112 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
1113 kernel_ns = get_kernel_ns();
1114 this_tsc_khz = vcpu_tsc_khz(v);
1115 if (unlikely(this_tsc_khz == 0)) {
1116 local_irq_restore(flags);
1117 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1122 * We may have to catch up the TSC to match elapsed wall clock
1123 * time for two reasons, even if kvmclock is used.
1124 * 1) CPU could have been running below the maximum TSC rate
1125 * 2) Broken TSC compensation resets the base at each VCPU
1126 * entry to avoid unknown leaps of TSC even when running
1127 * again on the same CPU. This may cause apparent elapsed
1128 * time to disappear, and the guest to stand still or run
1131 if (vcpu->tsc_catchup) {
1132 u64 tsc = compute_guest_tsc(v, kernel_ns);
1133 if (tsc > tsc_timestamp) {
1134 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1135 tsc_timestamp = tsc;
1139 local_irq_restore(flags);
1141 if (!vcpu->time_page)
1145 * Time as measured by the TSC may go backwards when resetting the base
1146 * tsc_timestamp. The reason for this is that the TSC resolution is
1147 * higher than the resolution of the other clock scales. Thus, many
1148 * possible measurments of the TSC correspond to one measurement of any
1149 * other clock, and so a spread of values is possible. This is not a
1150 * problem for the computation of the nanosecond clock; with TSC rates
1151 * around 1GHZ, there can only be a few cycles which correspond to one
1152 * nanosecond value, and any path through this code will inevitably
1153 * take longer than that. However, with the kernel_ns value itself,
1154 * the precision may be much lower, down to HZ granularity. If the
1155 * first sampling of TSC against kernel_ns ends in the low part of the
1156 * range, and the second in the high end of the range, we can get:
1158 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1160 * As the sampling errors potentially range in the thousands of cycles,
1161 * it is possible such a time value has already been observed by the
1162 * guest. To protect against this, we must compute the system time as
1163 * observed by the guest and ensure the new system time is greater.
1166 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1167 max_kernel_ns = vcpu->last_guest_tsc -
1168 vcpu->hv_clock.tsc_timestamp;
1169 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1170 vcpu->hv_clock.tsc_to_system_mul,
1171 vcpu->hv_clock.tsc_shift);
1172 max_kernel_ns += vcpu->last_kernel_ns;
1175 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1176 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1177 &vcpu->hv_clock.tsc_shift,
1178 &vcpu->hv_clock.tsc_to_system_mul);
1179 vcpu->hw_tsc_khz = this_tsc_khz;
1182 if (max_kernel_ns > kernel_ns)
1183 kernel_ns = max_kernel_ns;
1185 /* With all the info we got, fill in the values */
1186 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1187 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1188 vcpu->last_kernel_ns = kernel_ns;
1189 vcpu->last_guest_tsc = tsc_timestamp;
1190 vcpu->hv_clock.flags = 0;
1193 * The interface expects us to write an even number signaling that the
1194 * update is finished. Since the guest won't see the intermediate
1195 * state, we just increase by 2 at the end.
1197 vcpu->hv_clock.version += 2;
1199 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1201 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1202 sizeof(vcpu->hv_clock));
1204 kunmap_atomic(shared_kaddr, KM_USER0);
1206 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1210 static bool msr_mtrr_valid(unsigned msr)
1213 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1214 case MSR_MTRRfix64K_00000:
1215 case MSR_MTRRfix16K_80000:
1216 case MSR_MTRRfix16K_A0000:
1217 case MSR_MTRRfix4K_C0000:
1218 case MSR_MTRRfix4K_C8000:
1219 case MSR_MTRRfix4K_D0000:
1220 case MSR_MTRRfix4K_D8000:
1221 case MSR_MTRRfix4K_E0000:
1222 case MSR_MTRRfix4K_E8000:
1223 case MSR_MTRRfix4K_F0000:
1224 case MSR_MTRRfix4K_F8000:
1225 case MSR_MTRRdefType:
1226 case MSR_IA32_CR_PAT:
1234 static bool valid_pat_type(unsigned t)
1236 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1239 static bool valid_mtrr_type(unsigned t)
1241 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1244 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1248 if (!msr_mtrr_valid(msr))
1251 if (msr == MSR_IA32_CR_PAT) {
1252 for (i = 0; i < 8; i++)
1253 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1256 } else if (msr == MSR_MTRRdefType) {
1259 return valid_mtrr_type(data & 0xff);
1260 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1261 for (i = 0; i < 8 ; i++)
1262 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1267 /* variable MTRRs */
1268 return valid_mtrr_type(data & 0xff);
1271 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1273 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1275 if (!mtrr_valid(vcpu, msr, data))
1278 if (msr == MSR_MTRRdefType) {
1279 vcpu->arch.mtrr_state.def_type = data;
1280 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1281 } else if (msr == MSR_MTRRfix64K_00000)
1283 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1284 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1285 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1286 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1287 else if (msr == MSR_IA32_CR_PAT)
1288 vcpu->arch.pat = data;
1289 else { /* Variable MTRRs */
1290 int idx, is_mtrr_mask;
1293 idx = (msr - 0x200) / 2;
1294 is_mtrr_mask = msr - 0x200 - 2 * idx;
1297 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1300 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1304 kvm_mmu_reset_context(vcpu);
1308 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1310 u64 mcg_cap = vcpu->arch.mcg_cap;
1311 unsigned bank_num = mcg_cap & 0xff;
1314 case MSR_IA32_MCG_STATUS:
1315 vcpu->arch.mcg_status = data;
1317 case MSR_IA32_MCG_CTL:
1318 if (!(mcg_cap & MCG_CTL_P))
1320 if (data != 0 && data != ~(u64)0)
1322 vcpu->arch.mcg_ctl = data;
1325 if (msr >= MSR_IA32_MC0_CTL &&
1326 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1327 u32 offset = msr - MSR_IA32_MC0_CTL;
1328 /* only 0 or all 1s can be written to IA32_MCi_CTL
1329 * some Linux kernels though clear bit 10 in bank 4 to
1330 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1331 * this to avoid an uncatched #GP in the guest
1333 if ((offset & 0x3) == 0 &&
1334 data != 0 && (data | (1 << 10)) != ~(u64)0)
1336 vcpu->arch.mce_banks[offset] = data;
1344 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1346 struct kvm *kvm = vcpu->kvm;
1347 int lm = is_long_mode(vcpu);
1348 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1349 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1350 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1351 : kvm->arch.xen_hvm_config.blob_size_32;
1352 u32 page_num = data & ~PAGE_MASK;
1353 u64 page_addr = data & PAGE_MASK;
1358 if (page_num >= blob_size)
1361 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1365 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1367 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1376 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1378 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1381 static bool kvm_hv_msr_partition_wide(u32 msr)
1385 case HV_X64_MSR_GUEST_OS_ID:
1386 case HV_X64_MSR_HYPERCALL:
1394 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1396 struct kvm *kvm = vcpu->kvm;
1399 case HV_X64_MSR_GUEST_OS_ID:
1400 kvm->arch.hv_guest_os_id = data;
1401 /* setting guest os id to zero disables hypercall page */
1402 if (!kvm->arch.hv_guest_os_id)
1403 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1405 case HV_X64_MSR_HYPERCALL: {
1410 /* if guest os id is not set hypercall should remain disabled */
1411 if (!kvm->arch.hv_guest_os_id)
1413 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1414 kvm->arch.hv_hypercall = data;
1417 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1418 addr = gfn_to_hva(kvm, gfn);
1419 if (kvm_is_error_hva(addr))
1421 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1422 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1423 if (__copy_to_user((void __user *)addr, instructions, 4))
1425 kvm->arch.hv_hypercall = data;
1429 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1430 "data 0x%llx\n", msr, data);
1436 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1439 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1442 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1443 vcpu->arch.hv_vapic = data;
1446 addr = gfn_to_hva(vcpu->kvm, data >>
1447 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1448 if (kvm_is_error_hva(addr))
1450 if (__clear_user((void __user *)addr, PAGE_SIZE))
1452 vcpu->arch.hv_vapic = data;
1455 case HV_X64_MSR_EOI:
1456 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1457 case HV_X64_MSR_ICR:
1458 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1459 case HV_X64_MSR_TPR:
1460 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1462 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1463 "data 0x%llx\n", msr, data);
1470 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1472 gpa_t gpa = data & ~0x3f;
1474 /* Bits 2:5 are resrved, Should be zero */
1478 vcpu->arch.apf.msr_val = data;
1480 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1481 kvm_clear_async_pf_completion_queue(vcpu);
1482 kvm_async_pf_hash_reset(vcpu);
1486 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1489 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1490 kvm_async_pf_wakeup_all(vcpu);
1494 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1496 if (vcpu->arch.time_page) {
1497 kvm_release_page_dirty(vcpu->arch.time_page);
1498 vcpu->arch.time_page = NULL;
1502 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1506 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1509 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1510 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1511 vcpu->arch.st.accum_steal = delta;
1514 static void record_steal_time(struct kvm_vcpu *vcpu)
1516 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1519 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1520 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1523 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1524 vcpu->arch.st.steal.version += 2;
1525 vcpu->arch.st.accum_steal = 0;
1527 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1528 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1531 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1535 return set_efer(vcpu, data);
1537 data &= ~(u64)0x40; /* ignore flush filter disable */
1538 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1540 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1545 case MSR_FAM10H_MMIO_CONF_BASE:
1547 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1552 case MSR_AMD64_NB_CFG:
1554 case MSR_IA32_DEBUGCTLMSR:
1556 /* We support the non-activated case already */
1558 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1559 /* Values other than LBR and BTF are vendor-specific,
1560 thus reserved and should throw a #GP */
1563 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1566 case MSR_IA32_UCODE_REV:
1567 case MSR_IA32_UCODE_WRITE:
1568 case MSR_VM_HSAVE_PA:
1569 case MSR_AMD64_PATCH_LOADER:
1571 case 0x200 ... 0x2ff:
1572 return set_msr_mtrr(vcpu, msr, data);
1573 case MSR_IA32_APICBASE:
1574 kvm_set_apic_base(vcpu, data);
1576 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1577 return kvm_x2apic_msr_write(vcpu, msr, data);
1578 case MSR_IA32_TSCDEADLINE:
1579 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1581 case MSR_IA32_MISC_ENABLE:
1582 vcpu->arch.ia32_misc_enable_msr = data;
1584 case MSR_KVM_WALL_CLOCK_NEW:
1585 case MSR_KVM_WALL_CLOCK:
1586 vcpu->kvm->arch.wall_clock = data;
1587 kvm_write_wall_clock(vcpu->kvm, data);
1589 case MSR_KVM_SYSTEM_TIME_NEW:
1590 case MSR_KVM_SYSTEM_TIME: {
1591 kvmclock_reset(vcpu);
1593 vcpu->arch.time = data;
1594 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1596 /* we verify if the enable bit is set... */
1600 /* ...but clean it before doing the actual write */
1601 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1603 vcpu->arch.time_page =
1604 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1606 if (is_error_page(vcpu->arch.time_page)) {
1607 kvm_release_page_clean(vcpu->arch.time_page);
1608 vcpu->arch.time_page = NULL;
1612 case MSR_KVM_ASYNC_PF_EN:
1613 if (kvm_pv_enable_async_pf(vcpu, data))
1616 case MSR_KVM_STEAL_TIME:
1618 if (unlikely(!sched_info_on()))
1621 if (data & KVM_STEAL_RESERVED_MASK)
1624 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1625 data & KVM_STEAL_VALID_BITS))
1628 vcpu->arch.st.msr_val = data;
1630 if (!(data & KVM_MSR_ENABLED))
1633 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1636 accumulate_steal_time(vcpu);
1639 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1643 case MSR_IA32_MCG_CTL:
1644 case MSR_IA32_MCG_STATUS:
1645 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1646 return set_msr_mce(vcpu, msr, data);
1648 /* Performance counters are not protected by a CPUID bit,
1649 * so we should check all of them in the generic path for the sake of
1650 * cross vendor migration.
1651 * Writing a zero into the event select MSRs disables them,
1652 * which we perfectly emulate ;-). Any other value should be at least
1653 * reported, some guests depend on them.
1655 case MSR_P6_EVNTSEL0:
1656 case MSR_P6_EVNTSEL1:
1657 case MSR_K7_EVNTSEL0:
1658 case MSR_K7_EVNTSEL1:
1659 case MSR_K7_EVNTSEL2:
1660 case MSR_K7_EVNTSEL3:
1662 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1663 "0x%x data 0x%llx\n", msr, data);
1665 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1666 * so we ignore writes to make it happy.
1668 case MSR_P6_PERFCTR0:
1669 case MSR_P6_PERFCTR1:
1670 case MSR_K7_PERFCTR0:
1671 case MSR_K7_PERFCTR1:
1672 case MSR_K7_PERFCTR2:
1673 case MSR_K7_PERFCTR3:
1674 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1675 "0x%x data 0x%llx\n", msr, data);
1677 case MSR_K7_CLK_CTL:
1679 * Ignore all writes to this no longer documented MSR.
1680 * Writes are only relevant for old K7 processors,
1681 * all pre-dating SVM, but a recommended workaround from
1682 * AMD for these chips. It is possible to speicify the
1683 * affected processor models on the command line, hence
1684 * the need to ignore the workaround.
1687 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1688 if (kvm_hv_msr_partition_wide(msr)) {
1690 mutex_lock(&vcpu->kvm->lock);
1691 r = set_msr_hyperv_pw(vcpu, msr, data);
1692 mutex_unlock(&vcpu->kvm->lock);
1695 return set_msr_hyperv(vcpu, msr, data);
1697 case MSR_IA32_BBL_CR_CTL3:
1698 /* Drop writes to this legacy MSR -- see rdmsr
1699 * counterpart for further detail.
1701 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1704 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1705 return xen_hvm_config(vcpu, data);
1707 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1711 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1718 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1722 * Reads an msr value (of 'msr_index') into 'pdata'.
1723 * Returns 0 on success, non-0 otherwise.
1724 * Assumes vcpu_load() was already called.
1726 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1728 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1731 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1733 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1735 if (!msr_mtrr_valid(msr))
1738 if (msr == MSR_MTRRdefType)
1739 *pdata = vcpu->arch.mtrr_state.def_type +
1740 (vcpu->arch.mtrr_state.enabled << 10);
1741 else if (msr == MSR_MTRRfix64K_00000)
1743 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1744 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1745 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1746 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1747 else if (msr == MSR_IA32_CR_PAT)
1748 *pdata = vcpu->arch.pat;
1749 else { /* Variable MTRRs */
1750 int idx, is_mtrr_mask;
1753 idx = (msr - 0x200) / 2;
1754 is_mtrr_mask = msr - 0x200 - 2 * idx;
1757 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1760 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1767 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1770 u64 mcg_cap = vcpu->arch.mcg_cap;
1771 unsigned bank_num = mcg_cap & 0xff;
1774 case MSR_IA32_P5_MC_ADDR:
1775 case MSR_IA32_P5_MC_TYPE:
1778 case MSR_IA32_MCG_CAP:
1779 data = vcpu->arch.mcg_cap;
1781 case MSR_IA32_MCG_CTL:
1782 if (!(mcg_cap & MCG_CTL_P))
1784 data = vcpu->arch.mcg_ctl;
1786 case MSR_IA32_MCG_STATUS:
1787 data = vcpu->arch.mcg_status;
1790 if (msr >= MSR_IA32_MC0_CTL &&
1791 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1792 u32 offset = msr - MSR_IA32_MC0_CTL;
1793 data = vcpu->arch.mce_banks[offset];
1802 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1805 struct kvm *kvm = vcpu->kvm;
1808 case HV_X64_MSR_GUEST_OS_ID:
1809 data = kvm->arch.hv_guest_os_id;
1811 case HV_X64_MSR_HYPERCALL:
1812 data = kvm->arch.hv_hypercall;
1815 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1823 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1828 case HV_X64_MSR_VP_INDEX: {
1831 kvm_for_each_vcpu(r, v, vcpu->kvm)
1836 case HV_X64_MSR_EOI:
1837 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1838 case HV_X64_MSR_ICR:
1839 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1840 case HV_X64_MSR_TPR:
1841 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1842 case HV_X64_MSR_APIC_ASSIST_PAGE:
1843 data = vcpu->arch.hv_vapic;
1846 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1853 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1858 case MSR_IA32_PLATFORM_ID:
1859 case MSR_IA32_EBL_CR_POWERON:
1860 case MSR_IA32_DEBUGCTLMSR:
1861 case MSR_IA32_LASTBRANCHFROMIP:
1862 case MSR_IA32_LASTBRANCHTOIP:
1863 case MSR_IA32_LASTINTFROMIP:
1864 case MSR_IA32_LASTINTTOIP:
1867 case MSR_VM_HSAVE_PA:
1868 case MSR_P6_PERFCTR0:
1869 case MSR_P6_PERFCTR1:
1870 case MSR_P6_EVNTSEL0:
1871 case MSR_P6_EVNTSEL1:
1872 case MSR_K7_EVNTSEL0:
1873 case MSR_K7_PERFCTR0:
1874 case MSR_K8_INT_PENDING_MSG:
1875 case MSR_AMD64_NB_CFG:
1876 case MSR_FAM10H_MMIO_CONF_BASE:
1879 case MSR_IA32_UCODE_REV:
1880 data = 0x100000000ULL;
1883 data = 0x500 | KVM_NR_VAR_MTRR;
1885 case 0x200 ... 0x2ff:
1886 return get_msr_mtrr(vcpu, msr, pdata);
1887 case 0xcd: /* fsb frequency */
1891 * MSR_EBC_FREQUENCY_ID
1892 * Conservative value valid for even the basic CPU models.
1893 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1894 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1895 * and 266MHz for model 3, or 4. Set Core Clock
1896 * Frequency to System Bus Frequency Ratio to 1 (bits
1897 * 31:24) even though these are only valid for CPU
1898 * models > 2, however guests may end up dividing or
1899 * multiplying by zero otherwise.
1901 case MSR_EBC_FREQUENCY_ID:
1904 case MSR_IA32_APICBASE:
1905 data = kvm_get_apic_base(vcpu);
1907 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1908 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1910 case MSR_IA32_TSCDEADLINE:
1911 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1913 case MSR_IA32_MISC_ENABLE:
1914 data = vcpu->arch.ia32_misc_enable_msr;
1916 case MSR_IA32_PERF_STATUS:
1917 /* TSC increment by tick */
1919 /* CPU multiplier */
1920 data |= (((uint64_t)4ULL) << 40);
1923 data = vcpu->arch.efer;
1925 case MSR_KVM_WALL_CLOCK:
1926 case MSR_KVM_WALL_CLOCK_NEW:
1927 data = vcpu->kvm->arch.wall_clock;
1929 case MSR_KVM_SYSTEM_TIME:
1930 case MSR_KVM_SYSTEM_TIME_NEW:
1931 data = vcpu->arch.time;
1933 case MSR_KVM_ASYNC_PF_EN:
1934 data = vcpu->arch.apf.msr_val;
1936 case MSR_KVM_STEAL_TIME:
1937 data = vcpu->arch.st.msr_val;
1939 case MSR_IA32_P5_MC_ADDR:
1940 case MSR_IA32_P5_MC_TYPE:
1941 case MSR_IA32_MCG_CAP:
1942 case MSR_IA32_MCG_CTL:
1943 case MSR_IA32_MCG_STATUS:
1944 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1945 return get_msr_mce(vcpu, msr, pdata);
1946 case MSR_K7_CLK_CTL:
1948 * Provide expected ramp-up count for K7. All other
1949 * are set to zero, indicating minimum divisors for
1952 * This prevents guest kernels on AMD host with CPU
1953 * type 6, model 8 and higher from exploding due to
1954 * the rdmsr failing.
1958 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1959 if (kvm_hv_msr_partition_wide(msr)) {
1961 mutex_lock(&vcpu->kvm->lock);
1962 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1963 mutex_unlock(&vcpu->kvm->lock);
1966 return get_msr_hyperv(vcpu, msr, pdata);
1968 case MSR_IA32_BBL_CR_CTL3:
1969 /* This legacy MSR exists but isn't fully documented in current
1970 * silicon. It is however accessed by winxp in very narrow
1971 * scenarios where it sets bit #19, itself documented as
1972 * a "reserved" bit. Best effort attempt to source coherent
1973 * read data here should the balance of the register be
1974 * interpreted by the guest:
1976 * L2 cache control register 3: 64GB range, 256KB size,
1977 * enabled, latency 0x1, configured
1983 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1986 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1994 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1997 * Read or write a bunch of msrs. All parameters are kernel addresses.
1999 * @return number of msrs set successfully.
2001 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2002 struct kvm_msr_entry *entries,
2003 int (*do_msr)(struct kvm_vcpu *vcpu,
2004 unsigned index, u64 *data))
2008 idx = srcu_read_lock(&vcpu->kvm->srcu);
2009 for (i = 0; i < msrs->nmsrs; ++i)
2010 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2012 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2018 * Read or write a bunch of msrs. Parameters are user addresses.
2020 * @return number of msrs set successfully.
2022 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2023 int (*do_msr)(struct kvm_vcpu *vcpu,
2024 unsigned index, u64 *data),
2027 struct kvm_msrs msrs;
2028 struct kvm_msr_entry *entries;
2033 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2037 if (msrs.nmsrs >= MAX_IO_MSRS)
2041 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2042 entries = kmalloc(size, GFP_KERNEL);
2047 if (copy_from_user(entries, user_msrs->entries, size))
2050 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2055 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2066 int kvm_dev_ioctl_check_extension(long ext)
2071 case KVM_CAP_IRQCHIP:
2073 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2074 case KVM_CAP_SET_TSS_ADDR:
2075 case KVM_CAP_EXT_CPUID:
2076 case KVM_CAP_CLOCKSOURCE:
2078 case KVM_CAP_NOP_IO_DELAY:
2079 case KVM_CAP_MP_STATE:
2080 case KVM_CAP_SYNC_MMU:
2081 case KVM_CAP_USER_NMI:
2082 case KVM_CAP_REINJECT_CONTROL:
2083 case KVM_CAP_IRQ_INJECT_STATUS:
2084 case KVM_CAP_ASSIGN_DEV_IRQ:
2086 case KVM_CAP_IOEVENTFD:
2088 case KVM_CAP_PIT_STATE2:
2089 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2090 case KVM_CAP_XEN_HVM:
2091 case KVM_CAP_ADJUST_CLOCK:
2092 case KVM_CAP_VCPU_EVENTS:
2093 case KVM_CAP_HYPERV:
2094 case KVM_CAP_HYPERV_VAPIC:
2095 case KVM_CAP_HYPERV_SPIN:
2096 case KVM_CAP_PCI_SEGMENT:
2097 case KVM_CAP_DEBUGREGS:
2098 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2100 case KVM_CAP_ASYNC_PF:
2101 case KVM_CAP_GET_TSC_KHZ:
2104 case KVM_CAP_COALESCED_MMIO:
2105 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2108 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2110 case KVM_CAP_NR_VCPUS:
2111 r = KVM_SOFT_MAX_VCPUS;
2113 case KVM_CAP_MAX_VCPUS:
2116 case KVM_CAP_NR_MEMSLOTS:
2117 r = KVM_MEMORY_SLOTS;
2119 case KVM_CAP_PV_MMU: /* obsolete */
2123 r = iommu_present(&pci_bus_type);
2126 r = KVM_MAX_MCE_BANKS;
2131 case KVM_CAP_TSC_CONTROL:
2132 r = kvm_has_tsc_control;
2134 case KVM_CAP_TSC_DEADLINE_TIMER:
2135 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2145 long kvm_arch_dev_ioctl(struct file *filp,
2146 unsigned int ioctl, unsigned long arg)
2148 void __user *argp = (void __user *)arg;
2152 case KVM_GET_MSR_INDEX_LIST: {
2153 struct kvm_msr_list __user *user_msr_list = argp;
2154 struct kvm_msr_list msr_list;
2158 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2161 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2162 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2165 if (n < msr_list.nmsrs)
2168 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2169 num_msrs_to_save * sizeof(u32)))
2171 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2173 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2178 case KVM_GET_SUPPORTED_CPUID: {
2179 struct kvm_cpuid2 __user *cpuid_arg = argp;
2180 struct kvm_cpuid2 cpuid;
2183 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2185 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2186 cpuid_arg->entries);
2191 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2196 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2199 mce_cap = KVM_MCE_CAP_SUPPORTED;
2201 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2213 static void wbinvd_ipi(void *garbage)
2218 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2220 return vcpu->kvm->arch.iommu_domain &&
2221 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2224 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2226 /* Address WBINVD may be executed by guest */
2227 if (need_emulate_wbinvd(vcpu)) {
2228 if (kvm_x86_ops->has_wbinvd_exit())
2229 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2230 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2231 smp_call_function_single(vcpu->cpu,
2232 wbinvd_ipi, NULL, 1);
2235 kvm_x86_ops->vcpu_load(vcpu, cpu);
2236 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2237 /* Make sure TSC doesn't go backwards */
2241 tsc = kvm_x86_ops->read_l1_tsc(vcpu);
2242 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2243 tsc - vcpu->arch.last_guest_tsc;
2246 mark_tsc_unstable("KVM discovered backwards TSC");
2247 if (check_tsc_unstable()) {
2248 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
2249 vcpu->arch.tsc_catchup = 1;
2251 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2252 if (vcpu->cpu != cpu)
2253 kvm_migrate_timers(vcpu);
2257 accumulate_steal_time(vcpu);
2258 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2261 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2263 kvm_x86_ops->vcpu_put(vcpu);
2264 kvm_put_guest_fpu(vcpu);
2265 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
2268 static int is_efer_nx(void)
2270 unsigned long long efer = 0;
2272 rdmsrl_safe(MSR_EFER, &efer);
2273 return efer & EFER_NX;
2276 static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2279 struct kvm_cpuid_entry2 *e, *entry;
2282 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2283 e = &vcpu->arch.cpuid_entries[i];
2284 if (e->function == 0x80000001) {
2289 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
2290 entry->edx &= ~(1 << 20);
2291 printk(KERN_INFO "kvm: guest NX capability removed\n");
2295 /* when an old userspace process fills a new kernel module */
2296 static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2297 struct kvm_cpuid *cpuid,
2298 struct kvm_cpuid_entry __user *entries)
2301 struct kvm_cpuid_entry *cpuid_entries;
2304 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2307 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2311 if (copy_from_user(cpuid_entries, entries,
2312 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2314 for (i = 0; i < cpuid->nent; i++) {
2315 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2316 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2317 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2318 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2319 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2320 vcpu->arch.cpuid_entries[i].index = 0;
2321 vcpu->arch.cpuid_entries[i].flags = 0;
2322 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2323 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2324 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2326 vcpu->arch.cpuid_nent = cpuid->nent;
2327 cpuid_fix_nx_cap(vcpu);
2329 kvm_apic_set_version(vcpu);
2330 kvm_x86_ops->cpuid_update(vcpu);
2334 vfree(cpuid_entries);
2339 static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
2340 struct kvm_cpuid2 *cpuid,
2341 struct kvm_cpuid_entry2 __user *entries)
2346 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2349 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
2350 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
2352 vcpu->arch.cpuid_nent = cpuid->nent;
2353 kvm_apic_set_version(vcpu);
2354 kvm_x86_ops->cpuid_update(vcpu);
2362 static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
2363 struct kvm_cpuid2 *cpuid,
2364 struct kvm_cpuid_entry2 __user *entries)
2369 if (cpuid->nent < vcpu->arch.cpuid_nent)
2372 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
2373 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
2378 cpuid->nent = vcpu->arch.cpuid_nent;
2382 static void cpuid_mask(u32 *word, int wordnum)
2384 *word &= boot_cpu_data.x86_capability[wordnum];
2387 static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2390 entry->function = function;
2391 entry->index = index;
2392 cpuid_count(entry->function, entry->index,
2393 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
2397 static bool supported_xcr0_bit(unsigned bit)
2399 u64 mask = ((u64)1 << bit);
2401 return mask & (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) & host_xcr0;
2404 #define F(x) bit(X86_FEATURE_##x)
2406 static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2407 u32 index, int *nent, int maxnent)
2409 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
2410 #ifdef CONFIG_X86_64
2411 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2413 unsigned f_lm = F(LM);
2415 unsigned f_gbpages = 0;
2418 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
2421 const u32 kvm_supported_word0_x86_features =
2422 F(FPU) | F(VME) | F(DE) | F(PSE) |
2423 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2424 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2425 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2426 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2427 0 /* Reserved, DS, ACPI */ | F(MMX) |
2428 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2429 0 /* HTT, TM, Reserved, PBE */;
2430 /* cpuid 0x80000001.edx */
2431 const u32 kvm_supported_word1_x86_features =
2432 F(FPU) | F(VME) | F(DE) | F(PSE) |
2433 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2434 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2435 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2436 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2437 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
2438 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
2439 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2441 const u32 kvm_supported_word4_x86_features =
2442 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
2443 0 /* DS-CPL, VMX, SMX, EST */ |
2444 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2445 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2446 0 /* Reserved, DCA */ | F(XMM4_1) |
2447 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
2448 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2449 F(F16C) | F(RDRAND);
2450 /* cpuid 0x80000001.ecx */
2451 const u32 kvm_supported_word6_x86_features =
2452 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
2453 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2454 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
2455 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
2457 /* cpuid 0xC0000001.edx */
2458 const u32 kvm_supported_word5_x86_features =
2459 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
2460 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
2464 const u32 kvm_supported_word9_x86_features =
2465 F(SMEP) | F(FSGSBASE) | F(ERMS);
2467 /* all calls to cpuid_count() should be made on the same cpu */
2469 do_cpuid_1_ent(entry, function, index);
2474 entry->eax = min(entry->eax, (u32)0xd);
2477 entry->edx &= kvm_supported_word0_x86_features;
2478 cpuid_mask(&entry->edx, 0);
2479 entry->ecx &= kvm_supported_word4_x86_features;
2480 cpuid_mask(&entry->ecx, 4);
2481 /* we support x2apic emulation even if host does not support
2482 * it since we emulate x2apic in software */
2483 entry->ecx |= F(X2APIC);
2485 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2486 * may return different values. This forces us to get_cpu() before
2487 * issuing the first command, and also to emulate this annoying behavior
2488 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2490 int t, times = entry->eax & 0xff;
2492 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2493 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2494 for (t = 1; t < times && *nent < maxnent; ++t) {
2495 do_cpuid_1_ent(&entry[t], function, 0);
2496 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2501 /* function 4 has additional index. */
2505 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2506 /* read more entries until cache_type is zero */
2507 for (i = 1; *nent < maxnent; ++i) {
2508 cache_type = entry[i - 1].eax & 0x1f;
2511 do_cpuid_1_ent(&entry[i], function, i);
2513 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2519 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2520 /* Mask ebx against host capbability word 9 */
2522 entry->ebx &= kvm_supported_word9_x86_features;
2523 cpuid_mask(&entry->ebx, 9);
2533 /* function 0xb has additional index. */
2537 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2538 /* read more entries until level_type is zero */
2539 for (i = 1; *nent < maxnent; ++i) {
2540 level_type = entry[i - 1].ecx & 0xff00;
2543 do_cpuid_1_ent(&entry[i], function, i);
2545 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2553 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2554 for (idx = 1, i = 1; *nent < maxnent && idx < 64; ++idx) {
2555 do_cpuid_1_ent(&entry[i], function, idx);
2556 if (entry[i].eax == 0 || !supported_xcr0_bit(idx))
2559 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2565 case KVM_CPUID_SIGNATURE: {
2566 char signature[12] = "KVMKVMKVM\0\0";
2567 u32 *sigptr = (u32 *)signature;
2569 entry->ebx = sigptr[0];
2570 entry->ecx = sigptr[1];
2571 entry->edx = sigptr[2];
2574 case KVM_CPUID_FEATURES:
2575 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2576 (1 << KVM_FEATURE_NOP_IO_DELAY) |
2577 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2578 (1 << KVM_FEATURE_ASYNC_PF) |
2579 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
2581 if (sched_info_on())
2582 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
2589 entry->eax = min(entry->eax, 0x8000001a);
2592 entry->edx &= kvm_supported_word1_x86_features;
2593 cpuid_mask(&entry->edx, 1);
2594 entry->ecx &= kvm_supported_word6_x86_features;
2595 cpuid_mask(&entry->ecx, 6);
2598 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
2599 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
2600 unsigned phys_as = entry->eax & 0xff;
2603 g_phys_as = phys_as;
2604 entry->eax = g_phys_as | (virt_as << 8);
2605 entry->ebx = entry->edx = 0;
2609 entry->ecx = entry->edx = 0;
2615 /*Add support for Centaur's CPUID instruction*/
2617 /*Just support up to 0xC0000004 now*/
2618 entry->eax = min(entry->eax, 0xC0000004);
2621 entry->edx &= kvm_supported_word5_x86_features;
2622 cpuid_mask(&entry->edx, 5);
2624 case 3: /* Processor serial number */
2625 case 5: /* MONITOR/MWAIT */
2626 case 6: /* Thermal management */
2627 case 0xA: /* Architectural Performance Monitoring */
2628 case 0x80000007: /* Advanced power management */
2633 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
2637 kvm_x86_ops->set_supported_cpuid(function, entry);
2644 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
2645 struct kvm_cpuid_entry2 __user *entries)
2647 struct kvm_cpuid_entry2 *cpuid_entries;
2648 int limit, nent = 0, r = -E2BIG;
2651 if (cpuid->nent < 1)
2653 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2654 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
2656 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2660 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2661 limit = cpuid_entries[0].eax;
2662 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2663 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2664 &nent, cpuid->nent);
2666 if (nent >= cpuid->nent)
2669 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2670 limit = cpuid_entries[nent - 1].eax;
2671 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2672 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2673 &nent, cpuid->nent);
2678 if (nent >= cpuid->nent)
2681 /* Add support for Centaur's CPUID instruction. */
2682 if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) {
2683 do_cpuid_ent(&cpuid_entries[nent], 0xC0000000, 0,
2684 &nent, cpuid->nent);
2687 if (nent >= cpuid->nent)
2690 limit = cpuid_entries[nent - 1].eax;
2691 for (func = 0xC0000001;
2692 func <= limit && nent < cpuid->nent; ++func)
2693 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2694 &nent, cpuid->nent);
2697 if (nent >= cpuid->nent)
2701 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2705 if (nent >= cpuid->nent)
2708 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2712 if (nent >= cpuid->nent)
2716 if (copy_to_user(entries, cpuid_entries,
2717 nent * sizeof(struct kvm_cpuid_entry2)))
2723 vfree(cpuid_entries);
2728 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2729 struct kvm_lapic_state *s)
2731 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2736 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2737 struct kvm_lapic_state *s)
2739 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2740 kvm_apic_post_state_restore(vcpu);
2741 update_cr8_intercept(vcpu);
2746 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2747 struct kvm_interrupt *irq)
2749 if (irq->irq < 0 || irq->irq >= 256)
2751 if (irqchip_in_kernel(vcpu->kvm))
2754 kvm_queue_interrupt(vcpu, irq->irq, false);
2755 kvm_make_request(KVM_REQ_EVENT, vcpu);
2760 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2762 kvm_inject_nmi(vcpu);
2767 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2768 struct kvm_tpr_access_ctl *tac)
2772 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2776 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2780 unsigned bank_num = mcg_cap & 0xff, bank;
2783 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2785 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2788 vcpu->arch.mcg_cap = mcg_cap;
2789 /* Init IA32_MCG_CTL to all 1s */
2790 if (mcg_cap & MCG_CTL_P)
2791 vcpu->arch.mcg_ctl = ~(u64)0;
2792 /* Init IA32_MCi_CTL to all 1s */
2793 for (bank = 0; bank < bank_num; bank++)
2794 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2799 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2800 struct kvm_x86_mce *mce)
2802 u64 mcg_cap = vcpu->arch.mcg_cap;
2803 unsigned bank_num = mcg_cap & 0xff;
2804 u64 *banks = vcpu->arch.mce_banks;
2806 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2809 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2810 * reporting is disabled
2812 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2813 vcpu->arch.mcg_ctl != ~(u64)0)
2815 banks += 4 * mce->bank;
2817 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2818 * reporting is disabled for the bank
2820 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2822 if (mce->status & MCI_STATUS_UC) {
2823 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2824 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2825 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2828 if (banks[1] & MCI_STATUS_VAL)
2829 mce->status |= MCI_STATUS_OVER;
2830 banks[2] = mce->addr;
2831 banks[3] = mce->misc;
2832 vcpu->arch.mcg_status = mce->mcg_status;
2833 banks[1] = mce->status;
2834 kvm_queue_exception(vcpu, MC_VECTOR);
2835 } else if (!(banks[1] & MCI_STATUS_VAL)
2836 || !(banks[1] & MCI_STATUS_UC)) {
2837 if (banks[1] & MCI_STATUS_VAL)
2838 mce->status |= MCI_STATUS_OVER;
2839 banks[2] = mce->addr;
2840 banks[3] = mce->misc;
2841 banks[1] = mce->status;
2843 banks[1] |= MCI_STATUS_OVER;
2847 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2848 struct kvm_vcpu_events *events)
2851 events->exception.injected =
2852 vcpu->arch.exception.pending &&
2853 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2854 events->exception.nr = vcpu->arch.exception.nr;
2855 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2856 events->exception.pad = 0;
2857 events->exception.error_code = vcpu->arch.exception.error_code;
2859 events->interrupt.injected =
2860 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2861 events->interrupt.nr = vcpu->arch.interrupt.nr;
2862 events->interrupt.soft = 0;
2863 events->interrupt.shadow =
2864 kvm_x86_ops->get_interrupt_shadow(vcpu,
2865 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2867 events->nmi.injected = vcpu->arch.nmi_injected;
2868 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2869 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2870 events->nmi.pad = 0;
2872 events->sipi_vector = vcpu->arch.sipi_vector;
2874 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2875 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2876 | KVM_VCPUEVENT_VALID_SHADOW);
2877 memset(&events->reserved, 0, sizeof(events->reserved));
2880 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2881 struct kvm_vcpu_events *events)
2883 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2884 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2885 | KVM_VCPUEVENT_VALID_SHADOW))
2889 vcpu->arch.exception.pending = events->exception.injected;
2890 vcpu->arch.exception.nr = events->exception.nr;
2891 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2892 vcpu->arch.exception.error_code = events->exception.error_code;
2894 vcpu->arch.interrupt.pending = events->interrupt.injected;
2895 vcpu->arch.interrupt.nr = events->interrupt.nr;
2896 vcpu->arch.interrupt.soft = events->interrupt.soft;
2897 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2898 kvm_x86_ops->set_interrupt_shadow(vcpu,
2899 events->interrupt.shadow);
2901 vcpu->arch.nmi_injected = events->nmi.injected;
2902 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2903 vcpu->arch.nmi_pending = events->nmi.pending;
2904 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2906 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2907 vcpu->arch.sipi_vector = events->sipi_vector;
2909 kvm_make_request(KVM_REQ_EVENT, vcpu);
2914 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2915 struct kvm_debugregs *dbgregs)
2917 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2918 dbgregs->dr6 = vcpu->arch.dr6;
2919 dbgregs->dr7 = vcpu->arch.dr7;
2921 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2924 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2925 struct kvm_debugregs *dbgregs)
2930 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2931 vcpu->arch.dr6 = dbgregs->dr6;
2932 vcpu->arch.dr7 = dbgregs->dr7;
2937 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2938 struct kvm_xsave *guest_xsave)
2941 memcpy(guest_xsave->region,
2942 &vcpu->arch.guest_fpu.state->xsave,
2945 memcpy(guest_xsave->region,
2946 &vcpu->arch.guest_fpu.state->fxsave,
2947 sizeof(struct i387_fxsave_struct));
2948 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2953 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2954 struct kvm_xsave *guest_xsave)
2957 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2960 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2961 guest_xsave->region, xstate_size);
2963 if (xstate_bv & ~XSTATE_FPSSE)
2965 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2966 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2971 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2972 struct kvm_xcrs *guest_xcrs)
2974 if (!cpu_has_xsave) {
2975 guest_xcrs->nr_xcrs = 0;
2979 guest_xcrs->nr_xcrs = 1;
2980 guest_xcrs->flags = 0;
2981 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2982 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2985 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2986 struct kvm_xcrs *guest_xcrs)
2993 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2996 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2997 /* Only support XCR0 currently */
2998 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2999 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3000 guest_xcrs->xcrs[0].value);
3008 long kvm_arch_vcpu_ioctl(struct file *filp,
3009 unsigned int ioctl, unsigned long arg)
3011 struct kvm_vcpu *vcpu = filp->private_data;
3012 void __user *argp = (void __user *)arg;
3015 struct kvm_lapic_state *lapic;
3016 struct kvm_xsave *xsave;
3017 struct kvm_xcrs *xcrs;
3023 case KVM_GET_LAPIC: {
3025 if (!vcpu->arch.apic)
3027 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3032 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3036 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3041 case KVM_SET_LAPIC: {
3043 if (!vcpu->arch.apic)
3045 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3050 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
3052 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3058 case KVM_INTERRUPT: {
3059 struct kvm_interrupt irq;
3062 if (copy_from_user(&irq, argp, sizeof irq))
3064 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3071 r = kvm_vcpu_ioctl_nmi(vcpu);
3077 case KVM_SET_CPUID: {
3078 struct kvm_cpuid __user *cpuid_arg = argp;
3079 struct kvm_cpuid cpuid;
3082 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3084 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3089 case KVM_SET_CPUID2: {
3090 struct kvm_cpuid2 __user *cpuid_arg = argp;
3091 struct kvm_cpuid2 cpuid;
3094 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3096 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3097 cpuid_arg->entries);
3102 case KVM_GET_CPUID2: {
3103 struct kvm_cpuid2 __user *cpuid_arg = argp;
3104 struct kvm_cpuid2 cpuid;
3107 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3109 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3110 cpuid_arg->entries);
3114 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3120 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3123 r = msr_io(vcpu, argp, do_set_msr, 0);
3125 case KVM_TPR_ACCESS_REPORTING: {
3126 struct kvm_tpr_access_ctl tac;
3129 if (copy_from_user(&tac, argp, sizeof tac))
3131 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3135 if (copy_to_user(argp, &tac, sizeof tac))
3140 case KVM_SET_VAPIC_ADDR: {
3141 struct kvm_vapic_addr va;
3144 if (!irqchip_in_kernel(vcpu->kvm))
3147 if (copy_from_user(&va, argp, sizeof va))
3150 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3153 case KVM_X86_SETUP_MCE: {
3157 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3159 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3162 case KVM_X86_SET_MCE: {
3163 struct kvm_x86_mce mce;
3166 if (copy_from_user(&mce, argp, sizeof mce))
3168 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3171 case KVM_GET_VCPU_EVENTS: {
3172 struct kvm_vcpu_events events;
3174 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3177 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3182 case KVM_SET_VCPU_EVENTS: {
3183 struct kvm_vcpu_events events;
3186 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3189 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3192 case KVM_GET_DEBUGREGS: {
3193 struct kvm_debugregs dbgregs;
3195 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3198 if (copy_to_user(argp, &dbgregs,
3199 sizeof(struct kvm_debugregs)))
3204 case KVM_SET_DEBUGREGS: {
3205 struct kvm_debugregs dbgregs;
3208 if (copy_from_user(&dbgregs, argp,
3209 sizeof(struct kvm_debugregs)))
3212 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3215 case KVM_GET_XSAVE: {
3216 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3221 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3224 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3229 case KVM_SET_XSAVE: {
3230 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3236 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
3239 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3242 case KVM_GET_XCRS: {
3243 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3248 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3251 if (copy_to_user(argp, u.xcrs,
3252 sizeof(struct kvm_xcrs)))
3257 case KVM_SET_XCRS: {
3258 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3264 if (copy_from_user(u.xcrs, argp,
3265 sizeof(struct kvm_xcrs)))
3268 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3271 case KVM_SET_TSC_KHZ: {
3275 if (!kvm_has_tsc_control)
3278 user_tsc_khz = (u32)arg;
3280 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3283 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
3288 case KVM_GET_TSC_KHZ: {
3290 if (check_tsc_unstable())
3293 r = vcpu_tsc_khz(vcpu);
3305 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3309 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3311 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3315 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3318 kvm->arch.ept_identity_map_addr = ident_addr;
3322 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3323 u32 kvm_nr_mmu_pages)
3325 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3328 mutex_lock(&kvm->slots_lock);
3329 spin_lock(&kvm->mmu_lock);
3331 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3332 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3334 spin_unlock(&kvm->mmu_lock);
3335 mutex_unlock(&kvm->slots_lock);
3339 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3341 return kvm->arch.n_max_mmu_pages;
3344 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3349 switch (chip->chip_id) {
3350 case KVM_IRQCHIP_PIC_MASTER:
3351 memcpy(&chip->chip.pic,
3352 &pic_irqchip(kvm)->pics[0],
3353 sizeof(struct kvm_pic_state));
3355 case KVM_IRQCHIP_PIC_SLAVE:
3356 memcpy(&chip->chip.pic,
3357 &pic_irqchip(kvm)->pics[1],
3358 sizeof(struct kvm_pic_state));
3360 case KVM_IRQCHIP_IOAPIC:
3361 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3370 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3375 switch (chip->chip_id) {
3376 case KVM_IRQCHIP_PIC_MASTER:
3377 spin_lock(&pic_irqchip(kvm)->lock);
3378 memcpy(&pic_irqchip(kvm)->pics[0],
3380 sizeof(struct kvm_pic_state));
3381 spin_unlock(&pic_irqchip(kvm)->lock);
3383 case KVM_IRQCHIP_PIC_SLAVE:
3384 spin_lock(&pic_irqchip(kvm)->lock);
3385 memcpy(&pic_irqchip(kvm)->pics[1],
3387 sizeof(struct kvm_pic_state));
3388 spin_unlock(&pic_irqchip(kvm)->lock);
3390 case KVM_IRQCHIP_IOAPIC:
3391 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3397 kvm_pic_update_irq(pic_irqchip(kvm));
3401 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3405 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3406 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3407 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3411 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3415 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3416 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3417 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3418 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3422 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3426 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3427 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3428 sizeof(ps->channels));
3429 ps->flags = kvm->arch.vpit->pit_state.flags;
3430 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3431 memset(&ps->reserved, 0, sizeof(ps->reserved));
3435 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3437 int r = 0, start = 0;
3438 u32 prev_legacy, cur_legacy;
3439 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3440 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3441 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3442 if (!prev_legacy && cur_legacy)
3444 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3445 sizeof(kvm->arch.vpit->pit_state.channels));
3446 kvm->arch.vpit->pit_state.flags = ps->flags;
3447 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3448 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3452 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3453 struct kvm_reinject_control *control)
3455 if (!kvm->arch.vpit)
3457 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3458 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
3459 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3464 * Get (and clear) the dirty memory log for a memory slot.
3466 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3467 struct kvm_dirty_log *log)
3470 struct kvm_memory_slot *memslot;
3472 unsigned long is_dirty = 0;
3474 mutex_lock(&kvm->slots_lock);
3477 if (log->slot >= KVM_MEMORY_SLOTS)
3480 memslot = &kvm->memslots->memslots[log->slot];
3482 if (!memslot->dirty_bitmap)
3485 n = kvm_dirty_bitmap_bytes(memslot);
3487 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3488 is_dirty = memslot->dirty_bitmap[i];
3490 /* If nothing is dirty, don't bother messing with page tables. */
3492 struct kvm_memslots *slots, *old_slots;
3493 unsigned long *dirty_bitmap;
3495 dirty_bitmap = memslot->dirty_bitmap_head;
3496 if (memslot->dirty_bitmap == dirty_bitmap)
3497 dirty_bitmap += n / sizeof(long);
3498 memset(dirty_bitmap, 0, n);
3501 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3504 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3505 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3506 slots->generation++;
3508 old_slots = kvm->memslots;
3509 rcu_assign_pointer(kvm->memslots, slots);
3510 synchronize_srcu_expedited(&kvm->srcu);
3511 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3514 spin_lock(&kvm->mmu_lock);
3515 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3516 spin_unlock(&kvm->mmu_lock);
3519 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
3523 if (clear_user(log->dirty_bitmap, n))
3529 mutex_unlock(&kvm->slots_lock);
3533 long kvm_arch_vm_ioctl(struct file *filp,
3534 unsigned int ioctl, unsigned long arg)
3536 struct kvm *kvm = filp->private_data;
3537 void __user *argp = (void __user *)arg;
3540 * This union makes it completely explicit to gcc-3.x
3541 * that these two variables' stack usage should be
3542 * combined, not added together.
3545 struct kvm_pit_state ps;
3546 struct kvm_pit_state2 ps2;
3547 struct kvm_pit_config pit_config;
3551 case KVM_SET_TSS_ADDR:
3552 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3556 case KVM_SET_IDENTITY_MAP_ADDR: {
3560 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3562 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3567 case KVM_SET_NR_MMU_PAGES:
3568 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3572 case KVM_GET_NR_MMU_PAGES:
3573 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3575 case KVM_CREATE_IRQCHIP: {
3576 struct kvm_pic *vpic;
3578 mutex_lock(&kvm->lock);
3581 goto create_irqchip_unlock;
3583 vpic = kvm_create_pic(kvm);
3585 r = kvm_ioapic_init(kvm);
3587 mutex_lock(&kvm->slots_lock);
3588 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3590 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3592 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3594 mutex_unlock(&kvm->slots_lock);
3596 goto create_irqchip_unlock;
3599 goto create_irqchip_unlock;
3601 kvm->arch.vpic = vpic;
3603 r = kvm_setup_default_irq_routing(kvm);
3605 mutex_lock(&kvm->slots_lock);
3606 mutex_lock(&kvm->irq_lock);
3607 kvm_ioapic_destroy(kvm);
3608 kvm_destroy_pic(kvm);
3609 mutex_unlock(&kvm->irq_lock);
3610 mutex_unlock(&kvm->slots_lock);
3612 create_irqchip_unlock:
3613 mutex_unlock(&kvm->lock);
3616 case KVM_CREATE_PIT:
3617 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3619 case KVM_CREATE_PIT2:
3621 if (copy_from_user(&u.pit_config, argp,
3622 sizeof(struct kvm_pit_config)))
3625 mutex_lock(&kvm->slots_lock);
3628 goto create_pit_unlock;
3630 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3634 mutex_unlock(&kvm->slots_lock);
3636 case KVM_IRQ_LINE_STATUS:
3637 case KVM_IRQ_LINE: {
3638 struct kvm_irq_level irq_event;
3641 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3644 if (irqchip_in_kernel(kvm)) {
3646 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3647 irq_event.irq, irq_event.level);
3648 if (ioctl == KVM_IRQ_LINE_STATUS) {
3650 irq_event.status = status;
3651 if (copy_to_user(argp, &irq_event,
3659 case KVM_GET_IRQCHIP: {
3660 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3661 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
3667 if (copy_from_user(chip, argp, sizeof *chip))
3668 goto get_irqchip_out;
3670 if (!irqchip_in_kernel(kvm))
3671 goto get_irqchip_out;
3672 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3674 goto get_irqchip_out;
3676 if (copy_to_user(argp, chip, sizeof *chip))
3677 goto get_irqchip_out;
3685 case KVM_SET_IRQCHIP: {
3686 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3687 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
3693 if (copy_from_user(chip, argp, sizeof *chip))
3694 goto set_irqchip_out;
3696 if (!irqchip_in_kernel(kvm))
3697 goto set_irqchip_out;
3698 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3700 goto set_irqchip_out;
3710 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3713 if (!kvm->arch.vpit)
3715 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3719 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3726 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3729 if (!kvm->arch.vpit)
3731 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3737 case KVM_GET_PIT2: {
3739 if (!kvm->arch.vpit)
3741 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3745 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3750 case KVM_SET_PIT2: {
3752 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3755 if (!kvm->arch.vpit)
3757 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3763 case KVM_REINJECT_CONTROL: {
3764 struct kvm_reinject_control control;
3766 if (copy_from_user(&control, argp, sizeof(control)))
3768 r = kvm_vm_ioctl_reinject(kvm, &control);
3774 case KVM_XEN_HVM_CONFIG: {
3776 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3777 sizeof(struct kvm_xen_hvm_config)))
3780 if (kvm->arch.xen_hvm_config.flags)
3785 case KVM_SET_CLOCK: {
3786 struct kvm_clock_data user_ns;
3791 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3799 local_irq_disable();
3800 now_ns = get_kernel_ns();
3801 delta = user_ns.clock - now_ns;
3803 kvm->arch.kvmclock_offset = delta;
3806 case KVM_GET_CLOCK: {
3807 struct kvm_clock_data user_ns;
3810 local_irq_disable();
3811 now_ns = get_kernel_ns();
3812 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3815 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3818 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3831 static void kvm_init_msr_list(void)
3836 /* skip the first msrs in the list. KVM-specific */
3837 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3838 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3841 msrs_to_save[j] = msrs_to_save[i];
3844 num_msrs_to_save = j;
3847 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3855 if (!(vcpu->arch.apic &&
3856 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3857 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3868 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3875 if (!(vcpu->arch.apic &&
3876 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3877 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3879 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3889 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3890 struct kvm_segment *var, int seg)
3892 kvm_x86_ops->set_segment(vcpu, var, seg);
3895 void kvm_get_segment(struct kvm_vcpu *vcpu,
3896 struct kvm_segment *var, int seg)
3898 kvm_x86_ops->get_segment(vcpu, var, seg);
3901 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3906 static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3909 struct x86_exception exception;
3911 BUG_ON(!mmu_is_nested(vcpu));
3913 /* NPT walks are always user-walks */
3914 access |= PFERR_USER_MASK;
3915 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3920 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3921 struct x86_exception *exception)
3923 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3924 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3927 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3928 struct x86_exception *exception)
3930 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3931 access |= PFERR_FETCH_MASK;
3932 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3935 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3936 struct x86_exception *exception)
3938 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3939 access |= PFERR_WRITE_MASK;
3940 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3943 /* uses this to access any guest's mapped memory without checking CPL */
3944 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3945 struct x86_exception *exception)
3947 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3950 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3951 struct kvm_vcpu *vcpu, u32 access,
3952 struct x86_exception *exception)
3955 int r = X86EMUL_CONTINUE;
3958 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3960 unsigned offset = addr & (PAGE_SIZE-1);
3961 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3964 if (gpa == UNMAPPED_GVA)
3965 return X86EMUL_PROPAGATE_FAULT;
3966 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3968 r = X86EMUL_IO_NEEDED;
3980 /* used for instruction fetching */
3981 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3982 gva_t addr, void *val, unsigned int bytes,
3983 struct x86_exception *exception)
3985 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3986 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3988 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3989 access | PFERR_FETCH_MASK,
3993 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3994 gva_t addr, void *val, unsigned int bytes,
3995 struct x86_exception *exception)
3997 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3998 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4000 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4003 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4005 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4006 gva_t addr, void *val, unsigned int bytes,
4007 struct x86_exception *exception)
4009 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4010 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4013 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4014 gva_t addr, void *val,
4016 struct x86_exception *exception)
4018 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4020 int r = X86EMUL_CONTINUE;
4023 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4026 unsigned offset = addr & (PAGE_SIZE-1);
4027 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4030 if (gpa == UNMAPPED_GVA)
4031 return X86EMUL_PROPAGATE_FAULT;
4032 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4034 r = X86EMUL_IO_NEEDED;
4045 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4047 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4048 gpa_t *gpa, struct x86_exception *exception,
4051 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4053 if (vcpu_match_mmio_gva(vcpu, gva) &&
4054 check_write_user_access(vcpu, write, access,
4055 vcpu->arch.access)) {
4056 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4057 (gva & (PAGE_SIZE - 1));
4058 trace_vcpu_match_mmio(gva, *gpa, write, false);
4063 access |= PFERR_WRITE_MASK;
4065 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4067 if (*gpa == UNMAPPED_GVA)
4070 /* For APIC access vmexit */
4071 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4074 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4075 trace_vcpu_match_mmio(gva, *gpa, write, true);
4082 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4083 const void *val, int bytes)
4087 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4090 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
4094 struct read_write_emulator_ops {
4095 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4097 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4098 void *val, int bytes);
4099 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4100 int bytes, void *val);
4101 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4102 void *val, int bytes);
4106 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4108 if (vcpu->mmio_read_completed) {
4109 memcpy(val, vcpu->mmio_data, bytes);
4110 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4111 vcpu->mmio_phys_addr, *(u64 *)val);
4112 vcpu->mmio_read_completed = 0;
4119 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4120 void *val, int bytes)
4122 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4125 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4126 void *val, int bytes)
4128 return emulator_write_phys(vcpu, gpa, val, bytes);
4131 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4133 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4134 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4137 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4138 void *val, int bytes)
4140 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4141 return X86EMUL_IO_NEEDED;
4144 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4145 void *val, int bytes)
4147 memcpy(vcpu->mmio_data, val, bytes);
4148 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
4149 return X86EMUL_CONTINUE;
4152 static struct read_write_emulator_ops read_emultor = {
4153 .read_write_prepare = read_prepare,
4154 .read_write_emulate = read_emulate,
4155 .read_write_mmio = vcpu_mmio_read,
4156 .read_write_exit_mmio = read_exit_mmio,
4159 static struct read_write_emulator_ops write_emultor = {
4160 .read_write_emulate = write_emulate,
4161 .read_write_mmio = write_mmio,
4162 .read_write_exit_mmio = write_exit_mmio,
4166 static int emulator_read_write_onepage(unsigned long addr, void *val,
4168 struct x86_exception *exception,
4169 struct kvm_vcpu *vcpu,
4170 struct read_write_emulator_ops *ops)
4174 bool write = ops->write;
4176 if (ops->read_write_prepare &&
4177 ops->read_write_prepare(vcpu, val, bytes))
4178 return X86EMUL_CONTINUE;
4180 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4183 return X86EMUL_PROPAGATE_FAULT;
4185 /* For APIC access vmexit */
4189 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4190 return X86EMUL_CONTINUE;
4194 * Is this MMIO handled locally?
4196 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4197 if (handled == bytes)
4198 return X86EMUL_CONTINUE;
4204 vcpu->mmio_needed = 1;
4205 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4206 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
4207 vcpu->mmio_size = bytes;
4208 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
4209 vcpu->run->mmio.is_write = vcpu->mmio_is_write = write;
4210 vcpu->mmio_index = 0;
4212 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4215 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4216 void *val, unsigned int bytes,
4217 struct x86_exception *exception,
4218 struct read_write_emulator_ops *ops)
4220 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4222 /* Crossing a page boundary? */
4223 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4226 now = -addr & ~PAGE_MASK;
4227 rc = emulator_read_write_onepage(addr, val, now, exception,
4230 if (rc != X86EMUL_CONTINUE)
4237 return emulator_read_write_onepage(addr, val, bytes, exception,
4241 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4245 struct x86_exception *exception)
4247 return emulator_read_write(ctxt, addr, val, bytes,
4248 exception, &read_emultor);
4251 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4255 struct x86_exception *exception)
4257 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4258 exception, &write_emultor);
4261 #define CMPXCHG_TYPE(t, ptr, old, new) \
4262 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4264 #ifdef CONFIG_X86_64
4265 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4267 # define CMPXCHG64(ptr, old, new) \
4268 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4271 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4276 struct x86_exception *exception)
4278 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4284 /* guests cmpxchg8b have to be emulated atomically */
4285 if (bytes > 8 || (bytes & (bytes - 1)))
4288 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4290 if (gpa == UNMAPPED_GVA ||
4291 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4294 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4297 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4298 if (is_error_page(page)) {
4299 kvm_release_page_clean(page);
4303 kaddr = kmap_atomic(page, KM_USER0);
4304 kaddr += offset_in_page(gpa);
4307 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4310 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4313 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4316 exchanged = CMPXCHG64(kaddr, old, new);
4321 kunmap_atomic(kaddr, KM_USER0);
4322 kvm_release_page_dirty(page);
4325 return X86EMUL_CMPXCHG_FAILED;
4327 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
4329 return X86EMUL_CONTINUE;
4332 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4334 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4337 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4339 /* TODO: String I/O for in kernel device */
4342 if (vcpu->arch.pio.in)
4343 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4344 vcpu->arch.pio.size, pd);
4346 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4347 vcpu->arch.pio.port, vcpu->arch.pio.size,
4353 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4354 int size, unsigned short port, void *val,
4357 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4359 if (vcpu->arch.pio.count)
4362 trace_kvm_pio(0, port, size, count);
4364 vcpu->arch.pio.port = port;
4365 vcpu->arch.pio.in = 1;
4366 vcpu->arch.pio.count = count;
4367 vcpu->arch.pio.size = size;
4369 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4371 memcpy(val, vcpu->arch.pio_data, size * count);
4372 vcpu->arch.pio.count = 0;
4376 vcpu->run->exit_reason = KVM_EXIT_IO;
4377 vcpu->run->io.direction = KVM_EXIT_IO_IN;
4378 vcpu->run->io.size = size;
4379 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4380 vcpu->run->io.count = count;
4381 vcpu->run->io.port = port;
4386 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4387 int size, unsigned short port,
4388 const void *val, unsigned int count)
4390 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4392 trace_kvm_pio(1, port, size, count);
4394 vcpu->arch.pio.port = port;
4395 vcpu->arch.pio.in = 0;
4396 vcpu->arch.pio.count = count;
4397 vcpu->arch.pio.size = size;
4399 memcpy(vcpu->arch.pio_data, val, size * count);
4401 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4402 vcpu->arch.pio.count = 0;
4406 vcpu->run->exit_reason = KVM_EXIT_IO;
4407 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4408 vcpu->run->io.size = size;
4409 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4410 vcpu->run->io.count = count;
4411 vcpu->run->io.port = port;
4416 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4418 return kvm_x86_ops->get_segment_base(vcpu, seg);
4421 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4423 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4426 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4428 if (!need_emulate_wbinvd(vcpu))
4429 return X86EMUL_CONTINUE;
4431 if (kvm_x86_ops->has_wbinvd_exit()) {
4432 int cpu = get_cpu();
4434 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4435 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4436 wbinvd_ipi, NULL, 1);
4438 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4441 return X86EMUL_CONTINUE;
4443 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4445 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4447 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4450 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4452 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4455 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4458 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4461 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4463 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4466 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4468 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4469 unsigned long value;
4473 value = kvm_read_cr0(vcpu);
4476 value = vcpu->arch.cr2;
4479 value = kvm_read_cr3(vcpu);
4482 value = kvm_read_cr4(vcpu);
4485 value = kvm_get_cr8(vcpu);
4488 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4495 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4497 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4502 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4505 vcpu->arch.cr2 = val;
4508 res = kvm_set_cr3(vcpu, val);
4511 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4514 res = kvm_set_cr8(vcpu, val);
4517 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4524 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4526 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4529 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4531 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4534 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4536 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4539 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4541 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4544 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4546 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4549 static unsigned long emulator_get_cached_segment_base(
4550 struct x86_emulate_ctxt *ctxt, int seg)
4552 return get_segment_base(emul_to_vcpu(ctxt), seg);
4555 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4556 struct desc_struct *desc, u32 *base3,
4559 struct kvm_segment var;
4561 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4562 *selector = var.selector;
4569 set_desc_limit(desc, var.limit);
4570 set_desc_base(desc, (unsigned long)var.base);
4571 #ifdef CONFIG_X86_64
4573 *base3 = var.base >> 32;
4575 desc->type = var.type;
4577 desc->dpl = var.dpl;
4578 desc->p = var.present;
4579 desc->avl = var.avl;
4587 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4588 struct desc_struct *desc, u32 base3,
4591 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4592 struct kvm_segment var;
4594 var.selector = selector;
4595 var.base = get_desc_base(desc);
4596 #ifdef CONFIG_X86_64
4597 var.base |= ((u64)base3) << 32;
4599 var.limit = get_desc_limit(desc);
4601 var.limit = (var.limit << 12) | 0xfff;
4602 var.type = desc->type;
4603 var.present = desc->p;
4604 var.dpl = desc->dpl;
4609 var.avl = desc->avl;
4610 var.present = desc->p;
4611 var.unusable = !var.present;
4614 kvm_set_segment(vcpu, &var, seg);
4618 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4619 u32 msr_index, u64 *pdata)
4621 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4624 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4625 u32 msr_index, u64 data)
4627 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4630 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4632 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4635 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4638 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4640 * CR0.TS may reference the host fpu state, not the guest fpu state,
4641 * so it may be clear at this point.
4646 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4651 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4652 struct x86_instruction_info *info,
4653 enum x86_intercept_stage stage)
4655 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4658 static struct x86_emulate_ops emulate_ops = {
4659 .read_std = kvm_read_guest_virt_system,
4660 .write_std = kvm_write_guest_virt_system,
4661 .fetch = kvm_fetch_guest_virt,
4662 .read_emulated = emulator_read_emulated,
4663 .write_emulated = emulator_write_emulated,
4664 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4665 .invlpg = emulator_invlpg,
4666 .pio_in_emulated = emulator_pio_in_emulated,
4667 .pio_out_emulated = emulator_pio_out_emulated,
4668 .get_segment = emulator_get_segment,
4669 .set_segment = emulator_set_segment,
4670 .get_cached_segment_base = emulator_get_cached_segment_base,
4671 .get_gdt = emulator_get_gdt,
4672 .get_idt = emulator_get_idt,
4673 .set_gdt = emulator_set_gdt,
4674 .set_idt = emulator_set_idt,
4675 .get_cr = emulator_get_cr,
4676 .set_cr = emulator_set_cr,
4677 .cpl = emulator_get_cpl,
4678 .get_dr = emulator_get_dr,
4679 .set_dr = emulator_set_dr,
4680 .set_msr = emulator_set_msr,
4681 .get_msr = emulator_get_msr,
4682 .halt = emulator_halt,
4683 .wbinvd = emulator_wbinvd,
4684 .fix_hypercall = emulator_fix_hypercall,
4685 .get_fpu = emulator_get_fpu,
4686 .put_fpu = emulator_put_fpu,
4687 .intercept = emulator_intercept,
4690 static void cache_all_regs(struct kvm_vcpu *vcpu)
4692 kvm_register_read(vcpu, VCPU_REGS_RAX);
4693 kvm_register_read(vcpu, VCPU_REGS_RSP);
4694 kvm_register_read(vcpu, VCPU_REGS_RIP);
4695 vcpu->arch.regs_dirty = ~0;
4698 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4700 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4702 * an sti; sti; sequence only disable interrupts for the first
4703 * instruction. So, if the last instruction, be it emulated or
4704 * not, left the system with the INT_STI flag enabled, it
4705 * means that the last instruction is an sti. We should not
4706 * leave the flag on in this case. The same goes for mov ss
4708 if (!(int_shadow & mask))
4709 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4712 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4714 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4715 if (ctxt->exception.vector == PF_VECTOR)
4716 kvm_propagate_fault(vcpu, &ctxt->exception);
4717 else if (ctxt->exception.error_code_valid)
4718 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4719 ctxt->exception.error_code);
4721 kvm_queue_exception(vcpu, ctxt->exception.vector);
4724 static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
4725 const unsigned long *regs)
4727 memset(&ctxt->twobyte, 0,
4728 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4729 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
4731 ctxt->fetch.start = 0;
4732 ctxt->fetch.end = 0;
4733 ctxt->io_read.pos = 0;
4734 ctxt->io_read.end = 0;
4735 ctxt->mem_read.pos = 0;
4736 ctxt->mem_read.end = 0;
4739 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4741 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4745 * TODO: fix emulate.c to use guest_read/write_register
4746 * instead of direct ->regs accesses, can save hundred cycles
4747 * on Intel for instructions that don't read/change RSP, for
4750 cache_all_regs(vcpu);
4752 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4754 ctxt->eflags = kvm_get_rflags(vcpu);
4755 ctxt->eip = kvm_rip_read(vcpu);
4756 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4757 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4758 cs_l ? X86EMUL_MODE_PROT64 :
4759 cs_db ? X86EMUL_MODE_PROT32 :
4760 X86EMUL_MODE_PROT16;
4761 ctxt->guest_mode = is_guest_mode(vcpu);
4763 init_decode_cache(ctxt, vcpu->arch.regs);
4764 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4767 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4769 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4772 init_emulate_ctxt(vcpu);
4776 ctxt->_eip = ctxt->eip + inc_eip;
4777 ret = emulate_int_real(ctxt, irq);
4779 if (ret != X86EMUL_CONTINUE)
4780 return EMULATE_FAIL;
4782 ctxt->eip = ctxt->_eip;
4783 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4784 kvm_rip_write(vcpu, ctxt->eip);
4785 kvm_set_rflags(vcpu, ctxt->eflags);
4787 if (irq == NMI_VECTOR)
4788 vcpu->arch.nmi_pending = 0;
4790 vcpu->arch.interrupt.pending = false;
4792 return EMULATE_DONE;
4794 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4796 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4798 int r = EMULATE_DONE;
4800 ++vcpu->stat.insn_emulation_fail;
4801 trace_kvm_emulate_insn_failed(vcpu);
4802 if (!is_guest_mode(vcpu)) {
4803 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4804 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4805 vcpu->run->internal.ndata = 0;
4808 kvm_queue_exception(vcpu, UD_VECTOR);
4813 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4821 * if emulation was due to access to shadowed page table
4822 * and it failed try to unshadow page and re-entetr the
4823 * guest to let CPU execute the instruction.
4825 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4828 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4830 if (gpa == UNMAPPED_GVA)
4831 return true; /* let cpu generate fault */
4833 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4839 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4846 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4847 bool writeback = true;
4849 kvm_clear_exception_queue(vcpu);
4851 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4852 init_emulate_ctxt(vcpu);
4853 ctxt->interruptibility = 0;
4854 ctxt->have_exception = false;
4855 ctxt->perm_ok = false;
4857 ctxt->only_vendor_specific_insn
4858 = emulation_type & EMULTYPE_TRAP_UD;
4860 r = x86_decode_insn(ctxt, insn, insn_len);
4862 trace_kvm_emulate_insn_start(vcpu);
4863 ++vcpu->stat.insn_emulation;
4864 if (r != EMULATION_OK) {
4865 if (emulation_type & EMULTYPE_TRAP_UD)
4866 return EMULATE_FAIL;
4867 if (reexecute_instruction(vcpu, cr2))
4868 return EMULATE_DONE;
4869 if (emulation_type & EMULTYPE_SKIP)
4870 return EMULATE_FAIL;
4871 return handle_emulation_failure(vcpu);
4875 if (emulation_type & EMULTYPE_SKIP) {
4876 kvm_rip_write(vcpu, ctxt->_eip);
4877 return EMULATE_DONE;
4880 /* this is needed for vmware backdoor interface to work since it
4881 changes registers values during IO operation */
4882 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4883 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4884 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
4888 r = x86_emulate_insn(ctxt);
4890 if (r == EMULATION_INTERCEPTED)
4891 return EMULATE_DONE;
4893 if (r == EMULATION_FAILED) {
4894 if (reexecute_instruction(vcpu, cr2))
4895 return EMULATE_DONE;
4897 return handle_emulation_failure(vcpu);
4900 if (ctxt->have_exception) {
4901 inject_emulated_exception(vcpu);
4903 } else if (vcpu->arch.pio.count) {
4904 if (!vcpu->arch.pio.in)
4905 vcpu->arch.pio.count = 0;
4908 r = EMULATE_DO_MMIO;
4909 } else if (vcpu->mmio_needed) {
4910 if (!vcpu->mmio_is_write)
4912 r = EMULATE_DO_MMIO;
4913 } else if (r == EMULATION_RESTART)
4919 toggle_interruptibility(vcpu, ctxt->interruptibility);
4920 kvm_set_rflags(vcpu, ctxt->eflags);
4921 kvm_make_request(KVM_REQ_EVENT, vcpu);
4922 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4923 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4924 kvm_rip_write(vcpu, ctxt->eip);
4926 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
4930 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
4932 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4934 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4935 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4936 size, port, &val, 1);
4937 /* do not return to emulator after return from userspace */
4938 vcpu->arch.pio.count = 0;
4941 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4943 static void tsc_bad(void *info)
4945 __this_cpu_write(cpu_tsc_khz, 0);
4948 static void tsc_khz_changed(void *data)
4950 struct cpufreq_freqs *freq = data;
4951 unsigned long khz = 0;
4955 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4956 khz = cpufreq_quick_get(raw_smp_processor_id());
4959 __this_cpu_write(cpu_tsc_khz, khz);
4962 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4965 struct cpufreq_freqs *freq = data;
4967 struct kvm_vcpu *vcpu;
4968 int i, send_ipi = 0;
4971 * We allow guests to temporarily run on slowing clocks,
4972 * provided we notify them after, or to run on accelerating
4973 * clocks, provided we notify them before. Thus time never
4976 * However, we have a problem. We can't atomically update
4977 * the frequency of a given CPU from this function; it is
4978 * merely a notifier, which can be called from any CPU.
4979 * Changing the TSC frequency at arbitrary points in time
4980 * requires a recomputation of local variables related to
4981 * the TSC for each VCPU. We must flag these local variables
4982 * to be updated and be sure the update takes place with the
4983 * new frequency before any guests proceed.
4985 * Unfortunately, the combination of hotplug CPU and frequency
4986 * change creates an intractable locking scenario; the order
4987 * of when these callouts happen is undefined with respect to
4988 * CPU hotplug, and they can race with each other. As such,
4989 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4990 * undefined; you can actually have a CPU frequency change take
4991 * place in between the computation of X and the setting of the
4992 * variable. To protect against this problem, all updates of
4993 * the per_cpu tsc_khz variable are done in an interrupt
4994 * protected IPI, and all callers wishing to update the value
4995 * must wait for a synchronous IPI to complete (which is trivial
4996 * if the caller is on the CPU already). This establishes the
4997 * necessary total order on variable updates.
4999 * Note that because a guest time update may take place
5000 * anytime after the setting of the VCPU's request bit, the
5001 * correct TSC value must be set before the request. However,
5002 * to ensure the update actually makes it to any guest which
5003 * starts running in hardware virtualization between the set
5004 * and the acquisition of the spinlock, we must also ping the
5005 * CPU after setting the request bit.
5009 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5011 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5014 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5016 raw_spin_lock(&kvm_lock);
5017 list_for_each_entry(kvm, &vm_list, vm_list) {
5018 kvm_for_each_vcpu(i, vcpu, kvm) {
5019 if (vcpu->cpu != freq->cpu)
5021 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5022 if (vcpu->cpu != smp_processor_id())
5026 raw_spin_unlock(&kvm_lock);
5028 if (freq->old < freq->new && send_ipi) {
5030 * We upscale the frequency. Must make the guest
5031 * doesn't see old kvmclock values while running with
5032 * the new frequency, otherwise we risk the guest sees
5033 * time go backwards.
5035 * In case we update the frequency for another cpu
5036 * (which might be in guest context) send an interrupt
5037 * to kick the cpu out of guest context. Next time
5038 * guest context is entered kvmclock will be updated,
5039 * so the guest will not see stale values.
5041 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5046 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5047 .notifier_call = kvmclock_cpufreq_notifier
5050 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5051 unsigned long action, void *hcpu)
5053 unsigned int cpu = (unsigned long)hcpu;
5057 case CPU_DOWN_FAILED:
5058 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5060 case CPU_DOWN_PREPARE:
5061 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5067 static struct notifier_block kvmclock_cpu_notifier_block = {
5068 .notifier_call = kvmclock_cpu_notifier,
5069 .priority = -INT_MAX
5072 static void kvm_timer_init(void)
5076 max_tsc_khz = tsc_khz;
5077 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5078 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5079 #ifdef CONFIG_CPU_FREQ
5080 struct cpufreq_policy policy;
5081 memset(&policy, 0, sizeof(policy));
5083 cpufreq_get_policy(&policy, cpu);
5084 if (policy.cpuinfo.max_freq)
5085 max_tsc_khz = policy.cpuinfo.max_freq;
5088 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5089 CPUFREQ_TRANSITION_NOTIFIER);
5091 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5092 for_each_online_cpu(cpu)
5093 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5096 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5098 static int kvm_is_in_guest(void)
5100 return percpu_read(current_vcpu) != NULL;
5103 static int kvm_is_user_mode(void)
5107 if (percpu_read(current_vcpu))
5108 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
5110 return user_mode != 0;
5113 static unsigned long kvm_get_guest_ip(void)
5115 unsigned long ip = 0;
5117 if (percpu_read(current_vcpu))
5118 ip = kvm_rip_read(percpu_read(current_vcpu));
5123 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5124 .is_in_guest = kvm_is_in_guest,
5125 .is_user_mode = kvm_is_user_mode,
5126 .get_guest_ip = kvm_get_guest_ip,
5129 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5131 percpu_write(current_vcpu, vcpu);
5133 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5135 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5137 percpu_write(current_vcpu, NULL);
5139 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5141 static void kvm_set_mmio_spte_mask(void)
5144 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5147 * Set the reserved bits and the present bit of an paging-structure
5148 * entry to generate page fault with PFER.RSV = 1.
5150 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5153 #ifdef CONFIG_X86_64
5155 * If reserved bit is not supported, clear the present bit to disable
5158 if (maxphyaddr == 52)
5162 kvm_mmu_set_mmio_spte_mask(mask);
5165 int kvm_arch_init(void *opaque)
5168 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5171 printk(KERN_ERR "kvm: already loaded the other module\n");
5176 if (!ops->cpu_has_kvm_support()) {
5177 printk(KERN_ERR "kvm: no hardware support\n");
5181 if (ops->disabled_by_bios()) {
5182 printk(KERN_ERR "kvm: disabled by bios\n");
5187 r = kvm_mmu_module_init();
5191 kvm_set_mmio_spte_mask();
5192 kvm_init_msr_list();
5195 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5196 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5200 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5203 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5211 void kvm_arch_exit(void)
5213 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5215 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5216 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5217 CPUFREQ_TRANSITION_NOTIFIER);
5218 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5220 kvm_mmu_module_exit();
5223 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5225 ++vcpu->stat.halt_exits;
5226 if (irqchip_in_kernel(vcpu->kvm)) {
5227 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5230 vcpu->run->exit_reason = KVM_EXIT_HLT;
5234 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5236 static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
5239 if (is_long_mode(vcpu))
5242 return a0 | ((gpa_t)a1 << 32);
5245 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5247 u64 param, ingpa, outgpa, ret;
5248 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5249 bool fast, longmode;
5253 * hypercall generates UD from non zero cpl and real mode
5256 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5257 kvm_queue_exception(vcpu, UD_VECTOR);
5261 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5262 longmode = is_long_mode(vcpu) && cs_l == 1;
5265 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5266 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5267 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5268 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5269 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5270 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5272 #ifdef CONFIG_X86_64
5274 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5275 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5276 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5280 code = param & 0xffff;
5281 fast = (param >> 16) & 0x1;
5282 rep_cnt = (param >> 32) & 0xfff;
5283 rep_idx = (param >> 48) & 0xfff;
5285 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5288 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5289 kvm_vcpu_on_spin(vcpu);
5292 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5296 ret = res | (((u64)rep_done & 0xfff) << 32);
5298 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5300 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5301 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5307 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5309 unsigned long nr, a0, a1, a2, a3, ret;
5312 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5313 return kvm_hv_hypercall(vcpu);
5315 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5316 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5317 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5318 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5319 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5321 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5323 if (!is_long_mode(vcpu)) {
5331 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5337 case KVM_HC_VAPIC_POLL_IRQ:
5341 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
5348 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5349 ++vcpu->stat.hypercalls;
5352 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5354 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5356 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5357 char instruction[3];
5358 unsigned long rip = kvm_rip_read(vcpu);
5361 * Blow out the MMU to ensure that no other VCPU has an active mapping
5362 * to ensure that the updated hypercall appears atomically across all
5365 kvm_mmu_zap_all(vcpu->kvm);
5367 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5369 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5372 static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
5374 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
5375 int j, nent = vcpu->arch.cpuid_nent;
5377 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
5378 /* when no next entry is found, the current entry[i] is reselected */
5379 for (j = i + 1; ; j = (j + 1) % nent) {
5380 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
5381 if (ej->function == e->function) {
5382 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
5386 return 0; /* silence gcc, even though control never reaches here */
5389 /* find an entry with matching function, matching index (if needed), and that
5390 * should be read next (if it's stateful) */
5391 static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
5392 u32 function, u32 index)
5394 if (e->function != function)
5396 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
5398 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
5399 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
5404 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
5405 u32 function, u32 index)
5408 struct kvm_cpuid_entry2 *best = NULL;
5410 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
5411 struct kvm_cpuid_entry2 *e;
5413 e = &vcpu->arch.cpuid_entries[i];
5414 if (is_matching_cpuid_entry(e, function, index)) {
5415 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
5416 move_to_next_stateful_cpuid_entry(vcpu, i);
5423 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
5425 int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
5427 struct kvm_cpuid_entry2 *best;
5429 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
5430 if (!best || best->eax < 0x80000008)
5432 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
5434 return best->eax & 0xff;
5440 * If no match is found, check whether we exceed the vCPU's limit
5441 * and return the content of the highest valid _standard_ leaf instead.
5442 * This is to satisfy the CPUID specification.
5444 static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
5445 u32 function, u32 index)
5447 struct kvm_cpuid_entry2 *maxlevel;
5449 maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
5450 if (!maxlevel || maxlevel->eax >= function)
5452 if (function & 0x80000000) {
5453 maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
5457 return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
5460 void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
5462 u32 function, index;
5463 struct kvm_cpuid_entry2 *best;
5465 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
5466 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5467 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
5468 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
5469 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
5470 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
5471 best = kvm_find_cpuid_entry(vcpu, function, index);
5474 best = check_cpuid_limit(vcpu, function, index);
5477 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
5478 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
5479 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
5480 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
5482 kvm_x86_ops->skip_emulated_instruction(vcpu);
5483 trace_kvm_cpuid(function,
5484 kvm_register_read(vcpu, VCPU_REGS_RAX),
5485 kvm_register_read(vcpu, VCPU_REGS_RBX),
5486 kvm_register_read(vcpu, VCPU_REGS_RCX),
5487 kvm_register_read(vcpu, VCPU_REGS_RDX));
5489 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
5492 * Check if userspace requested an interrupt window, and that the
5493 * interrupt window is open.
5495 * No need to exit to userspace if we already have an interrupt queued.
5497 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5499 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5500 vcpu->run->request_interrupt_window &&
5501 kvm_arch_interrupt_allowed(vcpu));
5504 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5506 struct kvm_run *kvm_run = vcpu->run;
5508 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5509 kvm_run->cr8 = kvm_get_cr8(vcpu);
5510 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5511 if (irqchip_in_kernel(vcpu->kvm))
5512 kvm_run->ready_for_interrupt_injection = 1;
5514 kvm_run->ready_for_interrupt_injection =
5515 kvm_arch_interrupt_allowed(vcpu) &&
5516 !kvm_cpu_has_interrupt(vcpu) &&
5517 !kvm_event_needs_reinjection(vcpu);
5520 static void vapic_enter(struct kvm_vcpu *vcpu)
5522 struct kvm_lapic *apic = vcpu->arch.apic;
5525 if (!apic || !apic->vapic_addr)
5528 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5530 vcpu->arch.apic->vapic_page = page;
5533 static void vapic_exit(struct kvm_vcpu *vcpu)
5535 struct kvm_lapic *apic = vcpu->arch.apic;
5538 if (!apic || !apic->vapic_addr)
5541 idx = srcu_read_lock(&vcpu->kvm->srcu);
5542 kvm_release_page_dirty(apic->vapic_page);
5543 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5544 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5547 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5551 if (!kvm_x86_ops->update_cr8_intercept)
5554 if (!vcpu->arch.apic)
5557 if (!vcpu->arch.apic->vapic_addr)
5558 max_irr = kvm_lapic_find_highest_irr(vcpu);
5565 tpr = kvm_lapic_get_cr8(vcpu);
5567 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5570 static void inject_pending_event(struct kvm_vcpu *vcpu)
5572 /* try to reinject previous events if any */
5573 if (vcpu->arch.exception.pending) {
5574 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5575 vcpu->arch.exception.has_error_code,
5576 vcpu->arch.exception.error_code);
5577 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5578 vcpu->arch.exception.has_error_code,
5579 vcpu->arch.exception.error_code,
5580 vcpu->arch.exception.reinject);
5584 if (vcpu->arch.nmi_injected) {
5585 kvm_x86_ops->set_nmi(vcpu);
5589 if (vcpu->arch.interrupt.pending) {
5590 kvm_x86_ops->set_irq(vcpu);
5594 /* try to inject new event if pending */
5595 if (vcpu->arch.nmi_pending) {
5596 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5597 --vcpu->arch.nmi_pending;
5598 vcpu->arch.nmi_injected = true;
5599 kvm_x86_ops->set_nmi(vcpu);
5601 } else if (kvm_cpu_has_interrupt(vcpu)) {
5602 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5603 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5605 kvm_x86_ops->set_irq(vcpu);
5610 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5612 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5613 !vcpu->guest_xcr0_loaded) {
5614 /* kvm_set_xcr() also depends on this */
5615 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5616 vcpu->guest_xcr0_loaded = 1;
5620 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5622 if (vcpu->guest_xcr0_loaded) {
5623 if (vcpu->arch.xcr0 != host_xcr0)
5624 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5625 vcpu->guest_xcr0_loaded = 0;
5629 static void process_nmi(struct kvm_vcpu *vcpu)
5634 * x86 is limited to one NMI running, and one NMI pending after it.
5635 * If an NMI is already in progress, limit further NMIs to just one.
5636 * Otherwise, allow two (and we'll inject the first one immediately).
5638 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5641 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5642 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5643 kvm_make_request(KVM_REQ_EVENT, vcpu);
5646 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5649 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5650 vcpu->run->request_interrupt_window;
5652 if (vcpu->requests) {
5653 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5654 kvm_mmu_unload(vcpu);
5655 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5656 __kvm_migrate_timers(vcpu);
5657 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5658 r = kvm_guest_time_update(vcpu);
5662 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5663 kvm_mmu_sync_roots(vcpu);
5664 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5665 kvm_x86_ops->tlb_flush(vcpu);
5666 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5667 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5671 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5672 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5676 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5677 vcpu->fpu_active = 0;
5678 kvm_x86_ops->fpu_deactivate(vcpu);
5680 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5681 /* Page is swapped out. Do synthetic halt */
5682 vcpu->arch.apf.halted = true;
5686 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5687 record_steal_time(vcpu);
5688 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5693 r = kvm_mmu_reload(vcpu);
5697 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5698 inject_pending_event(vcpu);
5700 /* enable NMI/IRQ window open exits if needed */
5701 if (vcpu->arch.nmi_pending)
5702 kvm_x86_ops->enable_nmi_window(vcpu);
5703 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5704 kvm_x86_ops->enable_irq_window(vcpu);
5706 if (kvm_lapic_enabled(vcpu)) {
5707 update_cr8_intercept(vcpu);
5708 kvm_lapic_sync_to_vapic(vcpu);
5714 kvm_x86_ops->prepare_guest_switch(vcpu);
5715 if (vcpu->fpu_active)
5716 kvm_load_guest_fpu(vcpu);
5717 kvm_load_guest_xcr0(vcpu);
5719 vcpu->mode = IN_GUEST_MODE;
5721 /* We should set ->mode before check ->requests,
5722 * see the comment in make_all_cpus_request.
5726 local_irq_disable();
5728 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5729 || need_resched() || signal_pending(current)) {
5730 vcpu->mode = OUTSIDE_GUEST_MODE;
5734 kvm_x86_ops->cancel_injection(vcpu);
5739 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5743 if (unlikely(vcpu->arch.switch_db_regs)) {
5745 set_debugreg(vcpu->arch.eff_db[0], 0);
5746 set_debugreg(vcpu->arch.eff_db[1], 1);
5747 set_debugreg(vcpu->arch.eff_db[2], 2);
5748 set_debugreg(vcpu->arch.eff_db[3], 3);
5751 trace_kvm_entry(vcpu->vcpu_id);
5752 kvm_x86_ops->run(vcpu);
5755 * If the guest has used debug registers, at least dr7
5756 * will be disabled while returning to the host.
5757 * If we don't have active breakpoints in the host, we don't
5758 * care about the messed up debug address registers. But if
5759 * we have some of them active, restore the old state.
5761 if (hw_breakpoint_active())
5762 hw_breakpoint_restore();
5764 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
5766 vcpu->mode = OUTSIDE_GUEST_MODE;
5773 * We must have an instruction between local_irq_enable() and
5774 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5775 * the interrupt shadow. The stat.exits increment will do nicely.
5776 * But we need to prevent reordering, hence this barrier():
5784 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5787 * Profile KVM exit RIPs:
5789 if (unlikely(prof_on == KVM_PROFILING)) {
5790 unsigned long rip = kvm_rip_read(vcpu);
5791 profile_hit(KVM_PROFILING, (void *)rip);
5795 kvm_lapic_sync_from_vapic(vcpu);
5797 r = kvm_x86_ops->handle_exit(vcpu);
5803 static int __vcpu_run(struct kvm_vcpu *vcpu)
5806 struct kvm *kvm = vcpu->kvm;
5808 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5809 pr_debug("vcpu %d received sipi with vector # %x\n",
5810 vcpu->vcpu_id, vcpu->arch.sipi_vector);
5811 kvm_lapic_reset(vcpu);
5812 r = kvm_arch_vcpu_reset(vcpu);
5815 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5818 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5823 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5824 !vcpu->arch.apf.halted)
5825 r = vcpu_enter_guest(vcpu);
5827 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5828 kvm_vcpu_block(vcpu);
5829 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5830 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5832 switch(vcpu->arch.mp_state) {
5833 case KVM_MP_STATE_HALTED:
5834 vcpu->arch.mp_state =
5835 KVM_MP_STATE_RUNNABLE;
5836 case KVM_MP_STATE_RUNNABLE:
5837 vcpu->arch.apf.halted = false;
5839 case KVM_MP_STATE_SIPI_RECEIVED:
5850 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5851 if (kvm_cpu_has_pending_timer(vcpu))
5852 kvm_inject_pending_timer_irqs(vcpu);
5854 if (dm_request_for_irq_injection(vcpu)) {
5856 vcpu->run->exit_reason = KVM_EXIT_INTR;
5857 ++vcpu->stat.request_irq_exits;
5860 kvm_check_async_pf_completion(vcpu);
5862 if (signal_pending(current)) {
5864 vcpu->run->exit_reason = KVM_EXIT_INTR;
5865 ++vcpu->stat.signal_exits;
5867 if (need_resched()) {
5868 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5870 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5874 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5881 static int complete_mmio(struct kvm_vcpu *vcpu)
5883 struct kvm_run *run = vcpu->run;
5886 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5889 if (vcpu->mmio_needed) {
5890 vcpu->mmio_needed = 0;
5891 if (!vcpu->mmio_is_write)
5892 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5894 vcpu->mmio_index += 8;
5895 if (vcpu->mmio_index < vcpu->mmio_size) {
5896 run->exit_reason = KVM_EXIT_MMIO;
5897 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5898 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5899 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5900 run->mmio.is_write = vcpu->mmio_is_write;
5901 vcpu->mmio_needed = 1;
5904 if (vcpu->mmio_is_write)
5906 vcpu->mmio_read_completed = 1;
5908 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5909 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5910 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5911 if (r != EMULATE_DONE)
5916 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5921 if (!tsk_used_math(current) && init_fpu(current))
5924 if (vcpu->sigset_active)
5925 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5927 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5928 kvm_vcpu_block(vcpu);
5929 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5934 /* re-sync apic's tpr */
5935 if (!irqchip_in_kernel(vcpu->kvm)) {
5936 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5942 r = complete_mmio(vcpu);
5946 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5947 kvm_register_write(vcpu, VCPU_REGS_RAX,
5948 kvm_run->hypercall.ret);
5950 r = __vcpu_run(vcpu);
5953 post_kvm_run_save(vcpu);
5954 if (vcpu->sigset_active)
5955 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5960 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5962 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5964 * We are here if userspace calls get_regs() in the middle of
5965 * instruction emulation. Registers state needs to be copied
5966 * back from emulation context to vcpu. Usrapace shouldn't do
5967 * that usually, but some bad designed PV devices (vmware
5968 * backdoor interface) need this to work
5970 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5971 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5972 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5974 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5975 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5976 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5977 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5978 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5979 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5980 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5981 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5982 #ifdef CONFIG_X86_64
5983 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5984 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5985 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5986 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5987 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5988 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5989 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5990 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
5993 regs->rip = kvm_rip_read(vcpu);
5994 regs->rflags = kvm_get_rflags(vcpu);
5999 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6001 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6002 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6004 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6005 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6006 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6007 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6008 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6009 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6010 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6011 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6012 #ifdef CONFIG_X86_64
6013 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6014 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6015 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6016 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6017 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6018 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6019 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6020 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6023 kvm_rip_write(vcpu, regs->rip);
6024 kvm_set_rflags(vcpu, regs->rflags);
6026 vcpu->arch.exception.pending = false;
6028 kvm_make_request(KVM_REQ_EVENT, vcpu);
6033 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6035 struct kvm_segment cs;
6037 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6041 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6043 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6044 struct kvm_sregs *sregs)
6048 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6049 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6050 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6051 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6052 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6053 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6055 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6056 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6058 kvm_x86_ops->get_idt(vcpu, &dt);
6059 sregs->idt.limit = dt.size;
6060 sregs->idt.base = dt.address;
6061 kvm_x86_ops->get_gdt(vcpu, &dt);
6062 sregs->gdt.limit = dt.size;
6063 sregs->gdt.base = dt.address;
6065 sregs->cr0 = kvm_read_cr0(vcpu);
6066 sregs->cr2 = vcpu->arch.cr2;
6067 sregs->cr3 = kvm_read_cr3(vcpu);
6068 sregs->cr4 = kvm_read_cr4(vcpu);
6069 sregs->cr8 = kvm_get_cr8(vcpu);
6070 sregs->efer = vcpu->arch.efer;
6071 sregs->apic_base = kvm_get_apic_base(vcpu);
6073 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6075 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6076 set_bit(vcpu->arch.interrupt.nr,
6077 (unsigned long *)sregs->interrupt_bitmap);
6082 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6083 struct kvm_mp_state *mp_state)
6085 mp_state->mp_state = vcpu->arch.mp_state;
6089 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6090 struct kvm_mp_state *mp_state)
6092 vcpu->arch.mp_state = mp_state->mp_state;
6093 kvm_make_request(KVM_REQ_EVENT, vcpu);
6097 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
6098 bool has_error_code, u32 error_code)
6100 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6103 init_emulate_ctxt(vcpu);
6105 ret = emulator_task_switch(ctxt, tss_selector, reason,
6106 has_error_code, error_code);
6109 return EMULATE_FAIL;
6111 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
6112 kvm_rip_write(vcpu, ctxt->eip);
6113 kvm_set_rflags(vcpu, ctxt->eflags);
6114 kvm_make_request(KVM_REQ_EVENT, vcpu);
6115 return EMULATE_DONE;
6117 EXPORT_SYMBOL_GPL(kvm_task_switch);
6119 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6120 struct kvm_sregs *sregs)
6122 int mmu_reset_needed = 0;
6123 int pending_vec, max_bits, idx;
6126 dt.size = sregs->idt.limit;
6127 dt.address = sregs->idt.base;
6128 kvm_x86_ops->set_idt(vcpu, &dt);
6129 dt.size = sregs->gdt.limit;
6130 dt.address = sregs->gdt.base;
6131 kvm_x86_ops->set_gdt(vcpu, &dt);
6133 vcpu->arch.cr2 = sregs->cr2;
6134 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6135 vcpu->arch.cr3 = sregs->cr3;
6136 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6138 kvm_set_cr8(vcpu, sregs->cr8);
6140 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6141 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6142 kvm_set_apic_base(vcpu, sregs->apic_base);
6144 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6145 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6146 vcpu->arch.cr0 = sregs->cr0;
6148 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6149 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6150 if (sregs->cr4 & X86_CR4_OSXSAVE)
6153 idx = srcu_read_lock(&vcpu->kvm->srcu);
6154 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6155 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6156 mmu_reset_needed = 1;
6158 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6160 if (mmu_reset_needed)
6161 kvm_mmu_reset_context(vcpu);
6163 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
6164 pending_vec = find_first_bit(
6165 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6166 if (pending_vec < max_bits) {
6167 kvm_queue_interrupt(vcpu, pending_vec, false);
6168 pr_debug("Set back pending irq %d\n", pending_vec);
6171 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6172 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6173 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6174 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6175 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6176 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6178 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6179 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6181 update_cr8_intercept(vcpu);
6183 /* Older userspace won't unhalt the vcpu on reset. */
6184 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6185 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6187 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6189 kvm_make_request(KVM_REQ_EVENT, vcpu);
6194 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6195 struct kvm_guest_debug *dbg)
6197 unsigned long rflags;
6200 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6202 if (vcpu->arch.exception.pending)
6204 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6205 kvm_queue_exception(vcpu, DB_VECTOR);
6207 kvm_queue_exception(vcpu, BP_VECTOR);
6211 * Read rflags as long as potentially injected trace flags are still
6214 rflags = kvm_get_rflags(vcpu);
6216 vcpu->guest_debug = dbg->control;
6217 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6218 vcpu->guest_debug = 0;
6220 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6221 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6222 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6223 vcpu->arch.switch_db_regs =
6224 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
6226 for (i = 0; i < KVM_NR_DB_REGS; i++)
6227 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6228 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
6231 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6232 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6233 get_segment_base(vcpu, VCPU_SREG_CS);
6236 * Trigger an rflags update that will inject or remove the trace
6239 kvm_set_rflags(vcpu, rflags);
6241 kvm_x86_ops->set_guest_debug(vcpu, dbg);
6251 * Translate a guest virtual address to a guest physical address.
6253 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6254 struct kvm_translation *tr)
6256 unsigned long vaddr = tr->linear_address;
6260 idx = srcu_read_lock(&vcpu->kvm->srcu);
6261 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6262 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6263 tr->physical_address = gpa;
6264 tr->valid = gpa != UNMAPPED_GVA;
6271 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6273 struct i387_fxsave_struct *fxsave =
6274 &vcpu->arch.guest_fpu.state->fxsave;
6276 memcpy(fpu->fpr, fxsave->st_space, 128);
6277 fpu->fcw = fxsave->cwd;
6278 fpu->fsw = fxsave->swd;
6279 fpu->ftwx = fxsave->twd;
6280 fpu->last_opcode = fxsave->fop;
6281 fpu->last_ip = fxsave->rip;
6282 fpu->last_dp = fxsave->rdp;
6283 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6288 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6290 struct i387_fxsave_struct *fxsave =
6291 &vcpu->arch.guest_fpu.state->fxsave;
6293 memcpy(fxsave->st_space, fpu->fpr, 128);
6294 fxsave->cwd = fpu->fcw;
6295 fxsave->swd = fpu->fsw;
6296 fxsave->twd = fpu->ftwx;
6297 fxsave->fop = fpu->last_opcode;
6298 fxsave->rip = fpu->last_ip;
6299 fxsave->rdp = fpu->last_dp;
6300 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6305 int fx_init(struct kvm_vcpu *vcpu)
6309 err = fpu_alloc(&vcpu->arch.guest_fpu);
6313 fpu_finit(&vcpu->arch.guest_fpu);
6316 * Ensure guest xcr0 is valid for loading
6318 vcpu->arch.xcr0 = XSTATE_FP;
6320 vcpu->arch.cr0 |= X86_CR0_ET;
6324 EXPORT_SYMBOL_GPL(fx_init);
6326 static void fx_free(struct kvm_vcpu *vcpu)
6328 fpu_free(&vcpu->arch.guest_fpu);
6331 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6333 if (vcpu->guest_fpu_loaded)
6337 * Restore all possible states in the guest,
6338 * and assume host would use all available bits.
6339 * Guest xcr0 would be loaded later.
6341 kvm_put_guest_xcr0(vcpu);
6342 vcpu->guest_fpu_loaded = 1;
6343 unlazy_fpu(current);
6344 fpu_restore_checking(&vcpu->arch.guest_fpu);
6348 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6350 kvm_put_guest_xcr0(vcpu);
6352 if (!vcpu->guest_fpu_loaded)
6355 vcpu->guest_fpu_loaded = 0;
6356 fpu_save_init(&vcpu->arch.guest_fpu);
6357 ++vcpu->stat.fpu_reload;
6358 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6362 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6364 kvmclock_reset(vcpu);
6366 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6368 kvm_x86_ops->vcpu_free(vcpu);
6371 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6374 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6375 printk_once(KERN_WARNING
6376 "kvm: SMP vm created on host with unstable TSC; "
6377 "guest TSC will not be reliable\n");
6378 return kvm_x86_ops->vcpu_create(kvm, id);
6381 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6385 vcpu->arch.mtrr_state.have_fixed = 1;
6387 r = kvm_arch_vcpu_reset(vcpu);
6389 r = kvm_mmu_setup(vcpu);
6395 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6397 vcpu->arch.apf.msr_val = 0;
6400 kvm_mmu_unload(vcpu);
6404 kvm_x86_ops->vcpu_free(vcpu);
6407 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6409 atomic_set(&vcpu->arch.nmi_queued, 0);
6410 vcpu->arch.nmi_pending = 0;
6411 vcpu->arch.nmi_injected = false;
6413 vcpu->arch.switch_db_regs = 0;
6414 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6415 vcpu->arch.dr6 = DR6_FIXED_1;
6416 vcpu->arch.dr7 = DR7_FIXED_1;
6418 kvm_make_request(KVM_REQ_EVENT, vcpu);
6419 vcpu->arch.apf.msr_val = 0;
6420 vcpu->arch.st.msr_val = 0;
6422 kvmclock_reset(vcpu);
6424 kvm_clear_async_pf_completion_queue(vcpu);
6425 kvm_async_pf_hash_reset(vcpu);
6426 vcpu->arch.apf.halted = false;
6428 return kvm_x86_ops->vcpu_reset(vcpu);
6431 int kvm_arch_hardware_enable(void *garbage)
6434 struct kvm_vcpu *vcpu;
6437 kvm_shared_msr_cpu_online();
6438 list_for_each_entry(kvm, &vm_list, vm_list)
6439 kvm_for_each_vcpu(i, vcpu, kvm)
6440 if (vcpu->cpu == smp_processor_id())
6441 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6442 return kvm_x86_ops->hardware_enable(garbage);
6445 void kvm_arch_hardware_disable(void *garbage)
6447 kvm_x86_ops->hardware_disable(garbage);
6448 drop_user_return_notifiers(garbage);
6451 int kvm_arch_hardware_setup(void)
6453 return kvm_x86_ops->hardware_setup();
6456 void kvm_arch_hardware_unsetup(void)
6458 kvm_x86_ops->hardware_unsetup();
6461 void kvm_arch_check_processor_compat(void *rtn)
6463 kvm_x86_ops->check_processor_compatibility(rtn);
6466 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6472 BUG_ON(vcpu->kvm == NULL);
6475 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6476 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
6477 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
6478 vcpu->arch.mmu.translate_gpa = translate_gpa;
6479 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
6480 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6481 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6483 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6485 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6490 vcpu->arch.pio_data = page_address(page);
6492 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
6494 r = kvm_mmu_create(vcpu);
6496 goto fail_free_pio_data;
6498 if (irqchip_in_kernel(kvm)) {
6499 r = kvm_create_lapic(vcpu);
6501 goto fail_mmu_destroy;
6504 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6506 if (!vcpu->arch.mce_banks) {
6508 goto fail_free_lapic;
6510 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6512 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6513 goto fail_free_mce_banks;
6515 kvm_async_pf_hash_reset(vcpu);
6518 fail_free_mce_banks:
6519 kfree(vcpu->arch.mce_banks);
6521 kvm_free_lapic(vcpu);
6523 kvm_mmu_destroy(vcpu);
6525 free_page((unsigned long)vcpu->arch.pio_data);
6530 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6534 kfree(vcpu->arch.mce_banks);
6535 kvm_free_lapic(vcpu);
6536 idx = srcu_read_lock(&vcpu->kvm->srcu);
6537 kvm_mmu_destroy(vcpu);
6538 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6539 free_page((unsigned long)vcpu->arch.pio_data);
6542 int kvm_arch_init_vm(struct kvm *kvm)
6544 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6545 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6547 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6548 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6550 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6555 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6558 kvm_mmu_unload(vcpu);
6562 static void kvm_free_vcpus(struct kvm *kvm)
6565 struct kvm_vcpu *vcpu;
6568 * Unpin any mmu pages first.
6570 kvm_for_each_vcpu(i, vcpu, kvm) {
6571 kvm_clear_async_pf_completion_queue(vcpu);
6572 kvm_unload_vcpu_mmu(vcpu);
6574 kvm_for_each_vcpu(i, vcpu, kvm)
6575 kvm_arch_vcpu_free(vcpu);
6577 mutex_lock(&kvm->lock);
6578 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6579 kvm->vcpus[i] = NULL;
6581 atomic_set(&kvm->online_vcpus, 0);
6582 mutex_unlock(&kvm->lock);
6585 void kvm_arch_sync_events(struct kvm *kvm)
6587 kvm_free_all_assigned_devices(kvm);
6591 void kvm_arch_destroy_vm(struct kvm *kvm)
6593 kvm_iommu_unmap_guest(kvm);
6594 kfree(kvm->arch.vpic);
6595 kfree(kvm->arch.vioapic);
6596 kvm_free_vcpus(kvm);
6597 if (kvm->arch.apic_access_page)
6598 put_page(kvm->arch.apic_access_page);
6599 if (kvm->arch.ept_identity_pagetable)
6600 put_page(kvm->arch.ept_identity_pagetable);
6603 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6604 struct kvm_memory_slot *memslot,
6605 struct kvm_memory_slot old,
6606 struct kvm_userspace_memory_region *mem,
6609 int npages = memslot->npages;
6610 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6612 /* Prevent internal slot pages from being moved by fork()/COW. */
6613 if (memslot->id >= KVM_MEMORY_SLOTS)
6614 map_flags = MAP_SHARED | MAP_ANONYMOUS;
6616 /*To keep backward compatibility with older userspace,
6617 *x86 needs to hanlde !user_alloc case.
6620 if (npages && !old.rmap) {
6621 unsigned long userspace_addr;
6623 down_write(¤t->mm->mmap_sem);
6624 userspace_addr = do_mmap(NULL, 0,
6626 PROT_READ | PROT_WRITE,
6629 up_write(¤t->mm->mmap_sem);
6631 if (IS_ERR((void *)userspace_addr))
6632 return PTR_ERR((void *)userspace_addr);
6634 memslot->userspace_addr = userspace_addr;
6642 void kvm_arch_commit_memory_region(struct kvm *kvm,
6643 struct kvm_userspace_memory_region *mem,
6644 struct kvm_memory_slot old,
6648 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
6650 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6653 down_write(¤t->mm->mmap_sem);
6654 ret = do_munmap(current->mm, old.userspace_addr,
6655 old.npages * PAGE_SIZE);
6656 up_write(¤t->mm->mmap_sem);
6659 "kvm_vm_ioctl_set_memory_region: "
6660 "failed to munmap memory\n");
6663 if (!kvm->arch.n_requested_mmu_pages)
6664 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6666 spin_lock(&kvm->mmu_lock);
6668 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6669 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
6670 spin_unlock(&kvm->mmu_lock);
6673 void kvm_arch_flush_shadow(struct kvm *kvm)
6675 kvm_mmu_zap_all(kvm);
6676 kvm_reload_remote_mmus(kvm);
6679 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6681 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6682 !vcpu->arch.apf.halted)
6683 || !list_empty_careful(&vcpu->async_pf.done)
6684 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6685 || atomic_read(&vcpu->arch.nmi_queued) ||
6686 (kvm_arch_interrupt_allowed(vcpu) &&
6687 kvm_cpu_has_interrupt(vcpu));
6690 void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6693 int cpu = vcpu->cpu;
6695 if (waitqueue_active(&vcpu->wq)) {
6696 wake_up_interruptible(&vcpu->wq);
6697 ++vcpu->stat.halt_wakeup;
6701 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6702 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
6703 smp_send_reschedule(cpu);
6707 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6709 return kvm_x86_ops->interrupt_allowed(vcpu);
6712 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6714 unsigned long current_rip = kvm_rip_read(vcpu) +
6715 get_segment_base(vcpu, VCPU_SREG_CS);
6717 return current_rip == linear_rip;
6719 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6721 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6723 unsigned long rflags;
6725 rflags = kvm_x86_ops->get_rflags(vcpu);
6726 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6727 rflags &= ~X86_EFLAGS_TF;
6730 EXPORT_SYMBOL_GPL(kvm_get_rflags);
6732 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6734 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
6735 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
6736 rflags |= X86_EFLAGS_TF;
6737 kvm_x86_ops->set_rflags(vcpu, rflags);
6738 kvm_make_request(KVM_REQ_EVENT, vcpu);
6740 EXPORT_SYMBOL_GPL(kvm_set_rflags);
6742 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6746 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
6747 is_error_page(work->page))
6750 r = kvm_mmu_reload(vcpu);
6754 if (!vcpu->arch.mmu.direct_map &&
6755 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6758 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6761 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6763 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6766 static inline u32 kvm_async_pf_next_probe(u32 key)
6768 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6771 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6773 u32 key = kvm_async_pf_hash_fn(gfn);
6775 while (vcpu->arch.apf.gfns[key] != ~0)
6776 key = kvm_async_pf_next_probe(key);
6778 vcpu->arch.apf.gfns[key] = gfn;
6781 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6784 u32 key = kvm_async_pf_hash_fn(gfn);
6786 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
6787 (vcpu->arch.apf.gfns[key] != gfn &&
6788 vcpu->arch.apf.gfns[key] != ~0); i++)
6789 key = kvm_async_pf_next_probe(key);
6794 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6796 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6799 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6803 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6805 vcpu->arch.apf.gfns[i] = ~0;
6807 j = kvm_async_pf_next_probe(j);
6808 if (vcpu->arch.apf.gfns[j] == ~0)
6810 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6812 * k lies cyclically in ]i,j]
6814 * |....j i.k.| or |.k..j i...|
6816 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6817 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6822 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6825 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6829 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6830 struct kvm_async_pf *work)
6832 struct x86_exception fault;
6834 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
6835 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
6837 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
6838 (vcpu->arch.apf.send_user_only &&
6839 kvm_x86_ops->get_cpl(vcpu) == 0))
6840 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6841 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6842 fault.vector = PF_VECTOR;
6843 fault.error_code_valid = true;
6844 fault.error_code = 0;
6845 fault.nested_page_fault = false;
6846 fault.address = work->arch.token;
6847 kvm_inject_page_fault(vcpu, &fault);
6851 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6852 struct kvm_async_pf *work)
6854 struct x86_exception fault;
6856 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6857 if (is_error_page(work->page))
6858 work->arch.token = ~0; /* broadcast wakeup */
6860 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6862 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6863 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6864 fault.vector = PF_VECTOR;
6865 fault.error_code_valid = true;
6866 fault.error_code = 0;
6867 fault.nested_page_fault = false;
6868 fault.address = work->arch.token;
6869 kvm_inject_page_fault(vcpu, &fault);
6871 vcpu->arch.apf.halted = false;
6874 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6876 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6879 return !kvm_event_needs_reinjection(vcpu) &&
6880 kvm_x86_ops->interrupt_allowed(vcpu);
6883 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6884 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6885 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6886 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6887 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
6888 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
6889 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
6890 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
6891 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
6892 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
6893 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
6894 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);