arch/x86/kvm/x86.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * derived from drivers/kvm/kvm_main.c
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright (C) 2008 Qumranet, Inc.
   9  * Copyright IBM Corporation, 2008
  10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  11  *
  12  * Authors:
  13  *   Avi Kivity   <avi@qumranet.com>
  14  *   Yaniv Kamay  <yaniv@qumranet.com>
  15  *   Amit Shah    <amit.shah@qumranet.com>
  16  *   Ben-Ami Yassour <benami@il.ibm.com>
  17  */
  18
  19 #include <linux/kvm_host.h>
  20 #include "irq.h"
  21 #include "ioapic.h"
  22 #include "mmu.h"
  23 #include "i8254.h"
  24 #include "tss.h"
  25 #include "kvm_cache_regs.h"
  26 #include "kvm_emulate.h"
  27 #include "x86.h"
  28 #include "cpuid.h"
  29 #include "pmu.h"
  30 #include "hyperv.h"
  31 #include "lapic.h"
  32
  33 #include <linux/clocksource.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/kvm.h>
  36 #include <linux/fs.h>
  37 #include <linux/vmalloc.h>
  38 #include <linux/export.h>
  39 #include <linux/moduleparam.h>
  40 #include <linux/mman.h>
  41 #include <linux/highmem.h>
  42 #include <linux/iommu.h>
  43 #include <linux/intel-iommu.h>
  44 #include <linux/cpufreq.h>
  45 #include <linux/user-return-notifier.h>
  46 #include <linux/srcu.h>
  47 #include <linux/slab.h>
  48 #include <linux/perf_event.h>
  49 #include <linux/uaccess.h>
  50 #include <linux/hash.h>
  51 #include <linux/pci.h>
  52 #include <linux/timekeeper_internal.h>
  53 #include <linux/pvclock_gtod.h>
  54 #include <linux/kvm_irqfd.h>
  55 #include <linux/irqbypass.h>
  56 #include <linux/sched/stat.h>
  57 #include <linux/sched/isolation.h>
  58 #include <linux/mem_encrypt.h>
  59 #include <linux/entry-kvm.h>
  60
  61 #include <trace/events/kvm.h>
  62
  63 #include <asm/debugreg.h>
  64 #include <asm/msr.h>
  65 #include <asm/desc.h>
  66 #include <asm/mce.h>
  67 #include <linux/kernel_stat.h>
  68 #include <asm/fpu/internal.h> /* Ugh! */
  69 #include <asm/pvclock.h>
  70 #include <asm/div64.h>
  71 #include <asm/irq_remapping.h>
  72 #include <asm/mshyperv.h>
  73 #include <asm/hypervisor.h>
  74 #include <asm/tlbflush.h>
  75 #include <asm/intel_pt.h>
  76 #include <asm/emulate_prefix.h>
  77 #include <clocksource/hyperv_timer.h>
  78
  79 #define CREATE_TRACE_POINTS
  80 #include "trace.h"
  81
  82 #define MAX_IO_MSRS 256
  83 #define KVM_MAX_MCE_BANKS 32
  84 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
  85 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
  86
  87 #define emul_to_vcpu(ctxt) \
  88         ((struct kvm_vcpu *)(ctxt)->vcpu)
  89
  90 /* EFER defaults:
  91  * - enable syscall per default because its emulated by KVM
  92  * - enable LME and LMA per default on 64 bit KVM
  93  */
  94 #ifdef CONFIG_X86_64
  95 static
  96 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
  97 #else
  98 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
  99 #endif
 100
 101 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
 102
 103 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
 104                                     KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
 105
 106 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
 107 static void process_nmi(struct kvm_vcpu *vcpu);
 108 static void enter_smm(struct kvm_vcpu *vcpu);
 109 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
 110 static void store_regs(struct kvm_vcpu *vcpu);
 111 static int sync_regs(struct kvm_vcpu *vcpu);
 112
 113 struct kvm_x86_ops kvm_x86_ops __read_mostly;
 114 EXPORT_SYMBOL_GPL(kvm_x86_ops);
 115
 116 static bool __read_mostly ignore_msrs = 0;
 117 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
 118
 119 static bool __read_mostly report_ignored_msrs = true;
 120 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
 121
 122 unsigned int min_timer_period_us = 200;
 123 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
 124
 125 static bool __read_mostly kvmclock_periodic_sync = true;
 126 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
 127
 128 bool __read_mostly kvm_has_tsc_control;
 129 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
 130 u32  __read_mostly kvm_max_guest_tsc_khz;
 131 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
 132 u8   __read_mostly kvm_tsc_scaling_ratio_frac_bits;
 133 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
 134 u64  __read_mostly kvm_max_tsc_scaling_ratio;
 135 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
 136 u64 __read_mostly kvm_default_tsc_scaling_ratio;
 137 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
 138
 139 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
 140 static u32 __read_mostly tsc_tolerance_ppm = 250;
 141 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
 142
 143 /*
 144  * lapic timer advance (tscdeadline mode only) in nanoseconds.  '-1' enables
 145  * adaptive tuning starting from default advancment of 1000ns.  '0' disables
 146  * advancement entirely.  Any other value is used as-is and disables adaptive
 147  * tuning, i.e. allows priveleged userspace to set an exact advancement time.
 148  */
 149 static int __read_mostly lapic_timer_advance_ns = -1;
 150 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
 151
 152 static bool __read_mostly vector_hashing = true;
 153 module_param(vector_hashing, bool, S_IRUGO);
 154
 155 bool __read_mostly enable_vmware_backdoor = false;
 156 module_param(enable_vmware_backdoor, bool, S_IRUGO);
 157 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
 158
 159 static bool __read_mostly force_emulation_prefix = false;
 160 module_param(force_emulation_prefix, bool, S_IRUGO);
 161
 162 int __read_mostly pi_inject_timer = -1;
 163 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
 164
 165 /*
 166  * Restoring the host value for MSRs that are only consumed when running in
 167  * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
 168  * returns to userspace, i.e. the kernel can run with the guest's value.
 169  */
 170 #define KVM_MAX_NR_USER_RETURN_MSRS 16
 171
 172 struct kvm_user_return_msrs_global {
 173         int nr;
 174         u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS];
 175 };
 176
 177 struct kvm_user_return_msrs {
 178         struct user_return_notifier urn;
 179         bool registered;
 180         struct kvm_user_return_msr_values {
 181                 u64 host;
 182                 u64 curr;
 183         } values[KVM_MAX_NR_USER_RETURN_MSRS];
 184 };
 185
 186 static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global;
 187 static struct kvm_user_return_msrs __percpu *user_return_msrs;
 188
 189 #define KVM_SUPPORTED_XCR0     (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
 190                                 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
 191                                 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
 192                                 | XFEATURE_MASK_PKRU)
 193
 194 u64 __read_mostly host_efer;
 195 EXPORT_SYMBOL_GPL(host_efer);
 196
 197 bool __read_mostly allow_smaller_maxphyaddr;
 198 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
 199
 200 static u64 __read_mostly host_xss;
 201 u64 __read_mostly supported_xss;
 202 EXPORT_SYMBOL_GPL(supported_xss);
 203
 204 struct kvm_stats_debugfs_item debugfs_entries[] = {
 205         VCPU_STAT("pf_fixed", pf_fixed),
 206         VCPU_STAT("pf_guest", pf_guest),
 207         VCPU_STAT("tlb_flush", tlb_flush),
 208         VCPU_STAT("invlpg", invlpg),
 209         VCPU_STAT("exits", exits),
 210         VCPU_STAT("io_exits", io_exits),
 211         VCPU_STAT("mmio_exits", mmio_exits),
 212         VCPU_STAT("signal_exits", signal_exits),
 213         VCPU_STAT("irq_window", irq_window_exits),
 214         VCPU_STAT("nmi_window", nmi_window_exits),
 215         VCPU_STAT("halt_exits", halt_exits),
 216         VCPU_STAT("halt_successful_poll", halt_successful_poll),
 217         VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
 218         VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
 219         VCPU_STAT("halt_wakeup", halt_wakeup),
 220         VCPU_STAT("hypercalls", hypercalls),
 221         VCPU_STAT("request_irq", request_irq_exits),
 222         VCPU_STAT("irq_exits", irq_exits),
 223         VCPU_STAT("host_state_reload", host_state_reload),
 224         VCPU_STAT("fpu_reload", fpu_reload),
 225         VCPU_STAT("insn_emulation", insn_emulation),
 226         VCPU_STAT("insn_emulation_fail", insn_emulation_fail),
 227         VCPU_STAT("irq_injections", irq_injections),
 228         VCPU_STAT("nmi_injections", nmi_injections),
 229         VCPU_STAT("req_event", req_event),
 230         VCPU_STAT("l1d_flush", l1d_flush),
 231         VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
 232         VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
 233         VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped),
 234         VM_STAT("mmu_pte_write", mmu_pte_write),
 235         VM_STAT("mmu_pte_updated", mmu_pte_updated),
 236         VM_STAT("mmu_pde_zapped", mmu_pde_zapped),
 237         VM_STAT("mmu_flooded", mmu_flooded),
 238         VM_STAT("mmu_recycled", mmu_recycled),
 239         VM_STAT("mmu_cache_miss", mmu_cache_miss),
 240         VM_STAT("mmu_unsync", mmu_unsync),
 241         VM_STAT("remote_tlb_flush", remote_tlb_flush),
 242         VM_STAT("largepages", lpages, .mode = 0444),
 243         VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444),
 244         VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions),
 245         { NULL }
 246 };
 247
 248 u64 __read_mostly host_xcr0;
 249 u64 __read_mostly supported_xcr0;
 250 EXPORT_SYMBOL_GPL(supported_xcr0);
 251
 252 static struct kmem_cache *x86_fpu_cache;
 253
 254 static struct kmem_cache *x86_emulator_cache;
 255
 256 /*
 257  * When called, it means the previous get/set msr reached an invalid msr.
 258  * Return 0 if we want to ignore/silent this failed msr access, or 1 if we want
 259  * to fail the caller.
 260  */
 261 static int kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr,
 262                                  u64 data, bool write)
 263 {
 264         const char *op = write ? "wrmsr" : "rdmsr";
 265
 266         if (ignore_msrs) {
 267                 if (report_ignored_msrs)
 268                         vcpu_unimpl(vcpu, "ignored %s: 0x%x data 0x%llx\n",
 269                                     op, msr, data);
 270                 /* Mask the error */
 271                 return 0;
 272         } else {
 273                 vcpu_debug_ratelimited(vcpu, "unhandled %s: 0x%x data 0x%llx\n",
 274                                        op, msr, data);
 275                 return -ENOENT;
 276         }
 277 }
 278
 279 static struct kmem_cache *kvm_alloc_emulator_cache(void)
 280 {
 281         unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
 282         unsigned int size = sizeof(struct x86_emulate_ctxt);
 283
 284         return kmem_cache_create_usercopy("x86_emulator", size,
 285                                           __alignof__(struct x86_emulate_ctxt),
 286                                           SLAB_ACCOUNT, useroffset,
 287                                           size - useroffset, NULL);
 288 }
 289
 290 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
 291
 292 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
 293 {
 294         int i;
 295         for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
 296                 vcpu->arch.apf.gfns[i] = ~0;
 297 }
 298
 299 static void kvm_on_user_return(struct user_return_notifier *urn)
 300 {
 301         unsigned slot;
 302         struct kvm_user_return_msrs *msrs
 303                 = container_of(urn, struct kvm_user_return_msrs, urn);
 304         struct kvm_user_return_msr_values *values;
 305         unsigned long flags;
 306
 307         /*
 308          * Disabling irqs at this point since the following code could be
 309          * interrupted and executed through kvm_arch_hardware_disable()
 310          */
 311         local_irq_save(flags);
 312         if (msrs->registered) {
 313                 msrs->registered = false;
 314                 user_return_notifier_unregister(urn);
 315         }
 316         local_irq_restore(flags);
 317         for (slot = 0; slot < user_return_msrs_global.nr; ++slot) {
 318                 values = &msrs->values[slot];
 319                 if (values->host != values->curr) {
 320                         wrmsrl(user_return_msrs_global.msrs[slot], values->host);
 321                         values->curr = values->host;
 322                 }
 323         }
 324 }
 325
 326 void kvm_define_user_return_msr(unsigned slot, u32 msr)
 327 {
 328         BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS);
 329         user_return_msrs_global.msrs[slot] = msr;
 330         if (slot >= user_return_msrs_global.nr)
 331                 user_return_msrs_global.nr = slot + 1;
 332 }
 333 EXPORT_SYMBOL_GPL(kvm_define_user_return_msr);
 334
 335 static void kvm_user_return_msr_cpu_online(void)
 336 {
 337         unsigned int cpu = smp_processor_id();
 338         struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
 339         u64 value;
 340         int i;
 341
 342         for (i = 0; i < user_return_msrs_global.nr; ++i) {
 343                 rdmsrl_safe(user_return_msrs_global.msrs[i], &value);
 344                 msrs->values[i].host = value;
 345                 msrs->values[i].curr = value;
 346         }
 347 }
 348
 349 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
 350 {
 351         unsigned int cpu = smp_processor_id();
 352         struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
 353         int err;
 354
 355         value = (value & mask) | (msrs->values[slot].host & ~mask);
 356         if (value == msrs->values[slot].curr)
 357                 return 0;
 358         err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value);
 359         if (err)
 360                 return 1;
 361
 362         msrs->values[slot].curr = value;
 363         if (!msrs->registered) {
 364                 msrs->urn.on_user_return = kvm_on_user_return;
 365                 user_return_notifier_register(&msrs->urn);
 366                 msrs->registered = true;
 367         }
 368         return 0;
 369 }
 370 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
 371
 372 static void drop_user_return_notifiers(void)
 373 {
 374         unsigned int cpu = smp_processor_id();
 375         struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
 376
 377         if (msrs->registered)
 378                 kvm_on_user_return(&msrs->urn);
 379 }
 380
 381 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
 382 {
 383         return vcpu->arch.apic_base;
 384 }
 385 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
 386
 387 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
 388 {
 389         return kvm_apic_mode(kvm_get_apic_base(vcpu));
 390 }
 391 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
 392
 393 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 394 {
 395         enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
 396         enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
 397         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
 398                 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
 399
 400         if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
 401                 return 1;
 402         if (!msr_info->host_initiated) {
 403                 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
 404                         return 1;
 405                 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
 406                         return 1;
 407         }
 408
 409         kvm_lapic_set_base(vcpu, msr_info->data);
 410         kvm_recalculate_apic_map(vcpu->kvm);
 411         return 0;
 412 }
 413 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
 414
 415 asmlinkage __visible noinstr void kvm_spurious_fault(void)
 416 {
 417         /* Fault while not rebooting.  We want the trace. */
 418         BUG_ON(!kvm_rebooting);
 419 }
 420 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
 421
 422 #define EXCPT_BENIGN            0
 423 #define EXCPT_CONTRIBUTORY      1
 424 #define EXCPT_PF                2
 425
 426 static int exception_class(int vector)
 427 {
 428         switch (vector) {
 429         case PF_VECTOR:
 430                 return EXCPT_PF;
 431         case DE_VECTOR:
 432         case TS_VECTOR:
 433         case NP_VECTOR:
 434         case SS_VECTOR:
 435         case GP_VECTOR:
 436                 return EXCPT_CONTRIBUTORY;
 437         default:
 438                 break;
 439         }
 440         return EXCPT_BENIGN;
 441 }
 442
 443 #define EXCPT_FAULT             0
 444 #define EXCPT_TRAP              1
 445 #define EXCPT_ABORT             2
 446 #define EXCPT_INTERRUPT         3
 447
 448 static int exception_type(int vector)
 449 {
 450         unsigned int mask;
 451
 452         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
 453                 return EXCPT_INTERRUPT;
 454
 455         mask = 1 << vector;
 456
 457         /* #DB is trap, as instruction watchpoints are handled elsewhere */
 458         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
 459                 return EXCPT_TRAP;
 460
 461         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
 462                 return EXCPT_ABORT;
 463
 464         /* Reserved exceptions will result in fault */
 465         return EXCPT_FAULT;
 466 }
 467
 468 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
 469 {
 470         unsigned nr = vcpu->arch.exception.nr;
 471         bool has_payload = vcpu->arch.exception.has_payload;
 472         unsigned long payload = vcpu->arch.exception.payload;
 473
 474         if (!has_payload)
 475                 return;
 476
 477         switch (nr) {
 478         case DB_VECTOR:
 479                 /*
 480                  * "Certain debug exceptions may clear bit 0-3.  The
 481                  * remaining contents of the DR6 register are never
 482                  * cleared by the processor".
 483                  */
 484                 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
 485                 /*
 486                  * DR6.RTM is set by all #DB exceptions that don't clear it.
 487                  */
 488                 vcpu->arch.dr6 |= DR6_RTM;
 489                 vcpu->arch.dr6 |= payload;
 490                 /*
 491                  * Bit 16 should be set in the payload whenever the #DB
 492                  * exception should clear DR6.RTM. This makes the payload
 493                  * compatible with the pending debug exceptions under VMX.
 494                  * Though not currently documented in the SDM, this also
 495                  * makes the payload compatible with the exit qualification
 496                  * for #DB exceptions under VMX.
 497                  */
 498                 vcpu->arch.dr6 ^= payload & DR6_RTM;
 499
 500                 /*
 501                  * The #DB payload is defined as compatible with the 'pending
 502                  * debug exceptions' field under VMX, not DR6. While bit 12 is
 503                  * defined in the 'pending debug exceptions' field (enabled
 504                  * breakpoint), it is reserved and must be zero in DR6.
 505                  */
 506                 vcpu->arch.dr6 &= ~BIT(12);
 507                 break;
 508         case PF_VECTOR:
 509                 vcpu->arch.cr2 = payload;
 510                 break;
 511         }
 512
 513         vcpu->arch.exception.has_payload = false;
 514         vcpu->arch.exception.payload = 0;
 515 }
 516 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
 517
 518 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
 519                 unsigned nr, bool has_error, u32 error_code,
 520                 bool has_payload, unsigned long payload, bool reinject)
 521 {
 522         u32 prev_nr;
 523         int class1, class2;
 524
 525         kvm_make_request(KVM_REQ_EVENT, vcpu);
 526
 527         if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
 528         queue:
 529                 if (has_error && !is_protmode(vcpu))
 530                         has_error = false;
 531                 if (reinject) {
 532                         /*
 533                          * On vmentry, vcpu->arch.exception.pending is only
 534                          * true if an event injection was blocked by
 535                          * nested_run_pending.  In that case, however,
 536                          * vcpu_enter_guest requests an immediate exit,
 537                          * and the guest shouldn't proceed far enough to
 538                          * need reinjection.
 539                          */
 540                         WARN_ON_ONCE(vcpu->arch.exception.pending);
 541                         vcpu->arch.exception.injected = true;
 542                         if (WARN_ON_ONCE(has_payload)) {
 543                                 /*
 544                                  * A reinjected event has already
 545                                  * delivered its payload.
 546                                  */
 547                                 has_payload = false;
 548                                 payload = 0;
 549                         }
 550                 } else {
 551                         vcpu->arch.exception.pending = true;
 552                         vcpu->arch.exception.injected = false;
 553                 }
 554                 vcpu->arch.exception.has_error_code = has_error;
 555                 vcpu->arch.exception.nr = nr;
 556                 vcpu->arch.exception.error_code = error_code;
 557                 vcpu->arch.exception.has_payload = has_payload;
 558                 vcpu->arch.exception.payload = payload;
 559                 if (!is_guest_mode(vcpu))
 560                         kvm_deliver_exception_payload(vcpu);
 561                 return;
 562         }
 563
 564         /* to check exception */
 565         prev_nr = vcpu->arch.exception.nr;
 566         if (prev_nr == DF_VECTOR) {
 567                 /* triple fault -> shutdown */
 568                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
 569                 return;
 570         }
 571         class1 = exception_class(prev_nr);
 572         class2 = exception_class(nr);
 573         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
 574                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
 575                 /*
 576                  * Generate double fault per SDM Table 5-5.  Set
 577                  * exception.pending = true so that the double fault
 578                  * can trigger a nested vmexit.
 579                  */
 580                 vcpu->arch.exception.pending = true;
 581                 vcpu->arch.exception.injected = false;
 582                 vcpu->arch.exception.has_error_code = true;
 583                 vcpu->arch.exception.nr = DF_VECTOR;
 584                 vcpu->arch.exception.error_code = 0;
 585                 vcpu->arch.exception.has_payload = false;
 586                 vcpu->arch.exception.payload = 0;
 587         } else
 588                 /* replace previous exception with a new one in a hope
 589                    that instruction re-execution will regenerate lost
 590                    exception */
 591                 goto queue;
 592 }
 593
 594 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 595 {
 596         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
 597 }
 598 EXPORT_SYMBOL_GPL(kvm_queue_exception);
 599
 600 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 601 {
 602         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
 603 }
 604 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
 605
 606 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
 607                            unsigned long payload)
 608 {
 609         kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
 610 }
 611 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
 612
 613 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
 614                                     u32 error_code, unsigned long payload)
 615 {
 616         kvm_multiple_exception(vcpu, nr, true, error_code,
 617                                true, payload, false);
 618 }
 619
 620 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
 621 {
 622         if (err)
 623                 kvm_inject_gp(vcpu, 0);
 624         else
 625                 return kvm_skip_emulated_instruction(vcpu);
 626
 627         return 1;
 628 }
 629 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
 630
 631 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 632 {
 633         ++vcpu->stat.pf_guest;
 634         vcpu->arch.exception.nested_apf =
 635                 is_guest_mode(vcpu) && fault->async_page_fault;
 636         if (vcpu->arch.exception.nested_apf) {
 637                 vcpu->arch.apf.nested_apf_token = fault->address;
 638                 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
 639         } else {
 640                 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
 641                                         fault->address);
 642         }
 643 }
 644 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
 645
 646 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
 647                                     struct x86_exception *fault)
 648 {
 649         struct kvm_mmu *fault_mmu;
 650         WARN_ON_ONCE(fault->vector != PF_VECTOR);
 651
 652         fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
 653                                                vcpu->arch.walk_mmu;
 654
 655         /*
 656          * Invalidate the TLB entry for the faulting address, if it exists,
 657          * else the access will fault indefinitely (and to emulate hardware).
 658          */
 659         if ((fault->error_code & PFERR_PRESENT_MASK) &&
 660             !(fault->error_code & PFERR_RSVD_MASK))
 661                 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
 662                                        fault_mmu->root_hpa);
 663
 664         fault_mmu->inject_page_fault(vcpu, fault);
 665         return fault->nested_page_fault;
 666 }
 667 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
 668
 669 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
 670 {
 671         atomic_inc(&vcpu->arch.nmi_queued);
 672         kvm_make_request(KVM_REQ_NMI, vcpu);
 673 }
 674 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
 675
 676 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 677 {
 678         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
 679 }
 680 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
 681
 682 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 683 {
 684         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
 685 }
 686 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
 687
 688 /*
 689  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
 690  * a #GP and return false.
 691  */
 692 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
 693 {
 694         if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl)
 695                 return true;
 696         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
 697         return false;
 698 }
 699 EXPORT_SYMBOL_GPL(kvm_require_cpl);
 700
 701 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
 702 {
 703         if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 704                 return true;
 705
 706         kvm_queue_exception(vcpu, UD_VECTOR);
 707         return false;
 708 }
 709 EXPORT_SYMBOL_GPL(kvm_require_dr);
 710
 711 /*
 712  * This function will be used to read from the physical memory of the currently
 713  * running guest. The difference to kvm_vcpu_read_guest_page is that this function
 714  * can read from guest physical or from the guest's guest physical memory.
 715  */
 716 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 717                             gfn_t ngfn, void *data, int offset, int len,
 718                             u32 access)
 719 {
 720         struct x86_exception exception;
 721         gfn_t real_gfn;
 722         gpa_t ngpa;
 723
 724         ngpa     = gfn_to_gpa(ngfn);
 725         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
 726         if (real_gfn == UNMAPPED_GVA)
 727                 return -EFAULT;
 728
 729         real_gfn = gpa_to_gfn(real_gfn);
 730
 731         return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
 732 }
 733 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
 734
 735 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
 736                                void *data, int offset, int len, u32 access)
 737 {
 738         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
 739                                        data, offset, len, access);
 740 }
 741
 742 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
 743 {
 744         return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
 745                rsvd_bits(1, 2);
 746 }
 747
 748 /*
 749  * Load the pae pdptrs.  Return 1 if they are all valid, 0 otherwise.
 750  */
 751 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
 752 {
 753         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
 754         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
 755         int i;
 756         int ret;
 757         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
 758
 759         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
 760                                       offset * sizeof(u64), sizeof(pdpte),
 761                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
 762         if (ret < 0) {
 763                 ret = 0;
 764                 goto out;
 765         }
 766         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
 767                 if ((pdpte[i] & PT_PRESENT_MASK) &&
 768                     (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
 769                         ret = 0;
 770                         goto out;
 771                 }
 772         }
 773         ret = 1;
 774
 775         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
 776         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
 777
 778 out:
 779
 780         return ret;
 781 }
 782 EXPORT_SYMBOL_GPL(load_pdptrs);
 783
 784 bool pdptrs_changed(struct kvm_vcpu *vcpu)
 785 {
 786         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
 787         int offset;
 788         gfn_t gfn;
 789         int r;
 790
 791         if (!is_pae_paging(vcpu))
 792                 return false;
 793
 794         if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
 795                 return true;
 796
 797         gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
 798         offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
 799         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
 800                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
 801         if (r < 0)
 802                 return true;
 803
 804         return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
 805 }
 806 EXPORT_SYMBOL_GPL(pdptrs_changed);
 807
 808 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 809 {
 810         unsigned long old_cr0 = kvm_read_cr0(vcpu);
 811         unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG;
 812         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
 813
 814         cr0 |= X86_CR0_ET;
 815
 816 #ifdef CONFIG_X86_64
 817         if (cr0 & 0xffffffff00000000UL)
 818                 return 1;
 819 #endif
 820
 821         cr0 &= ~CR0_RESERVED_BITS;
 822
 823         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
 824                 return 1;
 825
 826         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
 827                 return 1;
 828
 829 #ifdef CONFIG_X86_64
 830         if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
 831             (cr0 & X86_CR0_PG)) {
 832                 int cs_db, cs_l;
 833
 834                 if (!is_pae(vcpu))
 835                         return 1;
 836                 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
 837                 if (cs_l)
 838                         return 1;
 839         }
 840 #endif
 841         if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
 842             is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) &&
 843             !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)))
 844                 return 1;
 845
 846         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
 847                 return 1;
 848
 849         kvm_x86_ops.set_cr0(vcpu, cr0);
 850
 851         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
 852                 kvm_clear_async_pf_completion_queue(vcpu);
 853                 kvm_async_pf_hash_reset(vcpu);
 854         }
 855
 856         if ((cr0 ^ old_cr0) & update_bits)
 857                 kvm_mmu_reset_context(vcpu);
 858
 859         if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
 860             kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
 861             !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
 862                 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
 863
 864         return 0;
 865 }
 866 EXPORT_SYMBOL_GPL(kvm_set_cr0);
 867
 868 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 869 {
 870         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
 871 }
 872 EXPORT_SYMBOL_GPL(kvm_lmsw);
 873
 874 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
 875 {
 876         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
 877
 878                 if (vcpu->arch.xcr0 != host_xcr0)
 879                         xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
 880
 881                 if (vcpu->arch.xsaves_enabled &&
 882                     vcpu->arch.ia32_xss != host_xss)
 883                         wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
 884         }
 885
 886         if (static_cpu_has(X86_FEATURE_PKU) &&
 887             (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
 888              (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
 889             vcpu->arch.pkru != vcpu->arch.host_pkru)
 890                 __write_pkru(vcpu->arch.pkru);
 891 }
 892 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
 893
 894 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
 895 {
 896         if (static_cpu_has(X86_FEATURE_PKU) &&
 897             (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
 898              (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
 899                 vcpu->arch.pkru = rdpkru();
 900                 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
 901                         __write_pkru(vcpu->arch.host_pkru);
 902         }
 903
 904         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
 905
 906                 if (vcpu->arch.xcr0 != host_xcr0)
 907                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
 908
 909                 if (vcpu->arch.xsaves_enabled &&
 910                     vcpu->arch.ia32_xss != host_xss)
 911                         wrmsrl(MSR_IA32_XSS, host_xss);
 912         }
 913
 914 }
 915 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
 916
 917 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 918 {
 919         u64 xcr0 = xcr;
 920         u64 old_xcr0 = vcpu->arch.xcr0;
 921         u64 valid_bits;
 922
 923         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
 924         if (index != XCR_XFEATURE_ENABLED_MASK)
 925                 return 1;
 926         if (!(xcr0 & XFEATURE_MASK_FP))
 927                 return 1;
 928         if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
 929                 return 1;
 930
 931         /*
 932          * Do not allow the guest to set bits that we do not support
 933          * saving.  However, xcr0 bit 0 is always set, even if the
 934          * emulated CPU does not support XSAVE (see fx_init).
 935          */
 936         valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
 937         if (xcr0 & ~valid_bits)
 938                 return 1;
 939
 940         if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
 941             (!(xcr0 & XFEATURE_MASK_BNDCSR)))
 942                 return 1;
 943
 944         if (xcr0 & XFEATURE_MASK_AVX512) {
 945                 if (!(xcr0 & XFEATURE_MASK_YMM))
 946                         return 1;
 947                 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
 948                         return 1;
 949         }
 950         vcpu->arch.xcr0 = xcr0;
 951
 952         if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
 953                 kvm_update_cpuid_runtime(vcpu);
 954         return 0;
 955 }
 956
 957 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 958 {
 959         if (kvm_x86_ops.get_cpl(vcpu) != 0 ||
 960             __kvm_set_xcr(vcpu, index, xcr)) {
 961                 kvm_inject_gp(vcpu, 0);
 962                 return 1;
 963         }
 964         return 0;
 965 }
 966 EXPORT_SYMBOL_GPL(kvm_set_xcr);
 967
 968 int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 969 {
 970         if (cr4 & cr4_reserved_bits)
 971                 return -EINVAL;
 972
 973         if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
 974                 return -EINVAL;
 975
 976         return 0;
 977 }
 978 EXPORT_SYMBOL_GPL(kvm_valid_cr4);
 979
 980 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 981 {
 982         unsigned long old_cr4 = kvm_read_cr4(vcpu);
 983         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
 984                                    X86_CR4_SMEP;
 985
 986         if (kvm_valid_cr4(vcpu, cr4))
 987                 return 1;
 988
 989         if (is_long_mode(vcpu)) {
 990                 if (!(cr4 & X86_CR4_PAE))
 991                         return 1;
 992                 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
 993                         return 1;
 994         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
 995                    && ((cr4 ^ old_cr4) & pdptr_bits)
 996                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 997                                    kvm_read_cr3(vcpu)))
 998                 return 1;
 999
1000         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1001                 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1002                         return 1;
1003
1004                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1005                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1006                         return 1;
1007         }
1008
1009         if (kvm_x86_ops.set_cr4(vcpu, cr4))
1010                 return 1;
1011
1012         if (((cr4 ^ old_cr4) & pdptr_bits) ||
1013             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1014                 kvm_mmu_reset_context(vcpu);
1015
1016         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1017                 kvm_update_cpuid_runtime(vcpu);
1018
1019         return 0;
1020 }
1021 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1022
1023 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1024 {
1025         bool skip_tlb_flush = false;
1026 #ifdef CONFIG_X86_64
1027         bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1028
1029         if (pcid_enabled) {
1030                 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1031                 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1032         }
1033 #endif
1034
1035         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1036                 if (!skip_tlb_flush) {
1037                         kvm_mmu_sync_roots(vcpu);
1038                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1039                 }
1040                 return 0;
1041         }
1042
1043         if (is_long_mode(vcpu) &&
1044             (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
1045                 return 1;
1046         else if (is_pae_paging(vcpu) &&
1047                  !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1048                 return 1;
1049
1050         kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush);
1051         vcpu->arch.cr3 = cr3;
1052         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1053
1054         return 0;
1055 }
1056 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1057
1058 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1059 {
1060         if (cr8 & CR8_RESERVED_BITS)
1061                 return 1;
1062         if (lapic_in_kernel(vcpu))
1063                 kvm_lapic_set_tpr(vcpu, cr8);
1064         else
1065                 vcpu->arch.cr8 = cr8;
1066         return 0;
1067 }
1068 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1069
1070 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1071 {
1072         if (lapic_in_kernel(vcpu))
1073                 return kvm_lapic_get_cr8(vcpu);
1074         else
1075                 return vcpu->arch.cr8;
1076 }
1077 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1078
1079 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1080 {
1081         int i;
1082
1083         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1084                 for (i = 0; i < KVM_NR_DB_REGS; i++)
1085                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1086                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1087         }
1088 }
1089
1090 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1091 {
1092         unsigned long dr7;
1093
1094         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1095                 dr7 = vcpu->arch.guest_debug_dr7;
1096         else
1097                 dr7 = vcpu->arch.dr7;
1098         kvm_x86_ops.set_dr7(vcpu, dr7);
1099         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1100         if (dr7 & DR7_BP_EN_MASK)
1101                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1102 }
1103 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1104
1105 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1106 {
1107         u64 fixed = DR6_FIXED_1;
1108
1109         if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1110                 fixed |= DR6_RTM;
1111         return fixed;
1112 }
1113
1114 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1115 {
1116         size_t size = ARRAY_SIZE(vcpu->arch.db);
1117
1118         switch (dr) {
1119         case 0 ... 3:
1120                 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1121                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1122                         vcpu->arch.eff_db[dr] = val;
1123                 break;
1124         case 4:
1125         case 6:
1126                 if (!kvm_dr6_valid(val))
1127                         return -1; /* #GP */
1128                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1129                 break;
1130         case 5:
1131         default: /* 7 */
1132                 if (!kvm_dr7_valid(val))
1133                         return -1; /* #GP */
1134                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1135                 kvm_update_dr7(vcpu);
1136                 break;
1137         }
1138
1139         return 0;
1140 }
1141
1142 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1143 {
1144         if (__kvm_set_dr(vcpu, dr, val)) {
1145                 kvm_inject_gp(vcpu, 0);
1146                 return 1;
1147         }
1148         return 0;
1149 }
1150 EXPORT_SYMBOL_GPL(kvm_set_dr);
1151
1152 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1153 {
1154         size_t size = ARRAY_SIZE(vcpu->arch.db);
1155
1156         switch (dr) {
1157         case 0 ... 3:
1158                 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1159                 break;
1160         case 4:
1161         case 6:
1162                 *val = vcpu->arch.dr6;
1163                 break;
1164         case 5:
1165         default: /* 7 */
1166                 *val = vcpu->arch.dr7;
1167                 break;
1168         }
1169         return 0;
1170 }
1171 EXPORT_SYMBOL_GPL(kvm_get_dr);
1172
1173 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1174 {
1175         u32 ecx = kvm_rcx_read(vcpu);
1176         u64 data;
1177         int err;
1178
1179         err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1180         if (err)
1181                 return err;
1182         kvm_rax_write(vcpu, (u32)data);
1183         kvm_rdx_write(vcpu, data >> 32);
1184         return err;
1185 }
1186 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1187
1188 /*
1189  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1190  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1191  *
1192  * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1193  * extract the supported MSRs from the related const lists.
1194  * msrs_to_save is selected from the msrs_to_save_all to reflect the
1195  * capabilities of the host cpu. This capabilities test skips MSRs that are
1196  * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1197  * may depend on host virtualization features rather than host cpu features.
1198  */
1199
1200 static const u32 msrs_to_save_all[] = {
1201         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1202         MSR_STAR,
1203 #ifdef CONFIG_X86_64
1204         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1205 #endif
1206         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1207         MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1208         MSR_IA32_SPEC_CTRL,
1209         MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1210         MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1211         MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1212         MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1213         MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1214         MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1215         MSR_IA32_UMWAIT_CONTROL,
1216
1217         MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1218         MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1219         MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1220         MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1221         MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1222         MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1223         MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1224         MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1225         MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1226         MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1227         MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1228         MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1229         MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1230         MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1231         MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1232         MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1233         MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1234         MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1235         MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1236         MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1237         MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1238         MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1239 };
1240
1241 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1242 static unsigned num_msrs_to_save;
1243
1244 static const u32 emulated_msrs_all[] = {
1245         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1246         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1247         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1248         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1249         HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1250         HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1251         HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1252         HV_X64_MSR_RESET,
1253         HV_X64_MSR_VP_INDEX,
1254         HV_X64_MSR_VP_RUNTIME,
1255         HV_X64_MSR_SCONTROL,
1256         HV_X64_MSR_STIMER0_CONFIG,
1257         HV_X64_MSR_VP_ASSIST_PAGE,
1258         HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1259         HV_X64_MSR_TSC_EMULATION_STATUS,
1260         HV_X64_MSR_SYNDBG_OPTIONS,
1261         HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1262         HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1263         HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1264
1265         MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1266         MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1267
1268         MSR_IA32_TSC_ADJUST,
1269         MSR_IA32_TSCDEADLINE,
1270         MSR_IA32_ARCH_CAPABILITIES,
1271         MSR_IA32_PERF_CAPABILITIES,
1272         MSR_IA32_MISC_ENABLE,
1273         MSR_IA32_MCG_STATUS,
1274         MSR_IA32_MCG_CTL,
1275         MSR_IA32_MCG_EXT_CTL,
1276         MSR_IA32_SMBASE,
1277         MSR_SMI_COUNT,
1278         MSR_PLATFORM_INFO,
1279         MSR_MISC_FEATURES_ENABLES,
1280         MSR_AMD64_VIRT_SPEC_CTRL,
1281         MSR_IA32_POWER_CTL,
1282         MSR_IA32_UCODE_REV,
1283
1284         /*
1285          * The following list leaves out MSRs whose values are determined
1286          * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1287          * We always support the "true" VMX control MSRs, even if the host
1288          * processor does not, so I am putting these registers here rather
1289          * than in msrs_to_save_all.
1290          */
1291         MSR_IA32_VMX_BASIC,
1292         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1293         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1294         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1295         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1296         MSR_IA32_VMX_MISC,
1297         MSR_IA32_VMX_CR0_FIXED0,
1298         MSR_IA32_VMX_CR4_FIXED0,
1299         MSR_IA32_VMX_VMCS_ENUM,
1300         MSR_IA32_VMX_PROCBASED_CTLS2,
1301         MSR_IA32_VMX_EPT_VPID_CAP,
1302         MSR_IA32_VMX_VMFUNC,
1303
1304         MSR_K7_HWCR,
1305         MSR_KVM_POLL_CONTROL,
1306 };
1307
1308 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1309 static unsigned num_emulated_msrs;
1310
1311 /*
1312  * List of msr numbers which are used to expose MSR-based features that
1313  * can be used by a hypervisor to validate requested CPU features.
1314  */
1315 static const u32 msr_based_features_all[] = {
1316         MSR_IA32_VMX_BASIC,
1317         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1318         MSR_IA32_VMX_PINBASED_CTLS,
1319         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1320         MSR_IA32_VMX_PROCBASED_CTLS,
1321         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1322         MSR_IA32_VMX_EXIT_CTLS,
1323         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1324         MSR_IA32_VMX_ENTRY_CTLS,
1325         MSR_IA32_VMX_MISC,
1326         MSR_IA32_VMX_CR0_FIXED0,
1327         MSR_IA32_VMX_CR0_FIXED1,
1328         MSR_IA32_VMX_CR4_FIXED0,
1329         MSR_IA32_VMX_CR4_FIXED1,
1330         MSR_IA32_VMX_VMCS_ENUM,
1331         MSR_IA32_VMX_PROCBASED_CTLS2,
1332         MSR_IA32_VMX_EPT_VPID_CAP,
1333         MSR_IA32_VMX_VMFUNC,
1334
1335         MSR_F10H_DECFG,
1336         MSR_IA32_UCODE_REV,
1337         MSR_IA32_ARCH_CAPABILITIES,
1338         MSR_IA32_PERF_CAPABILITIES,
1339 };
1340
1341 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1342 static unsigned int num_msr_based_features;
1343
1344 static u64 kvm_get_arch_capabilities(void)
1345 {
1346         u64 data = 0;
1347
1348         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1349                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1350
1351         /*
1352          * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1353          * the nested hypervisor runs with NX huge pages.  If it is not,
1354          * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1355          * L1 guests, so it need not worry about its own (L2) guests.
1356          */
1357         data |= ARCH_CAP_PSCHANGE_MC_NO;
1358
1359         /*
1360          * If we're doing cache flushes (either "always" or "cond")
1361          * we will do one whenever the guest does a vmlaunch/vmresume.
1362          * If an outer hypervisor is doing the cache flush for us
1363          * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1364          * capability to the guest too, and if EPT is disabled we're not
1365          * vulnerable.  Overall, only VMENTER_L1D_FLUSH_NEVER will
1366          * require a nested hypervisor to do a flush of its own.
1367          */
1368         if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1369                 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1370
1371         if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1372                 data |= ARCH_CAP_RDCL_NO;
1373         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1374                 data |= ARCH_CAP_SSB_NO;
1375         if (!boot_cpu_has_bug(X86_BUG_MDS))
1376                 data |= ARCH_CAP_MDS_NO;
1377
1378         /*
1379          * On TAA affected systems:
1380          *      - nothing to do if TSX is disabled on the host.
1381          *      - we emulate TSX_CTRL if present on the host.
1382          *        This lets the guest use VERW to clear CPU buffers.
1383          */
1384         if (!boot_cpu_has(X86_FEATURE_RTM))
1385                 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1386         else if (!boot_cpu_has_bug(X86_BUG_TAA))
1387                 data |= ARCH_CAP_TAA_NO;
1388
1389         return data;
1390 }
1391
1392 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1393 {
1394         switch (msr->index) {
1395         case MSR_IA32_ARCH_CAPABILITIES:
1396                 msr->data = kvm_get_arch_capabilities();
1397                 break;
1398         case MSR_IA32_UCODE_REV:
1399                 rdmsrl_safe(msr->index, &msr->data);
1400                 break;
1401         default:
1402                 return kvm_x86_ops.get_msr_feature(msr);
1403         }
1404         return 0;
1405 }
1406
1407 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1408 {
1409         struct kvm_msr_entry msr;
1410         int r;
1411
1412         msr.index = index;
1413         r = kvm_get_msr_feature(&msr);
1414
1415         if (r == KVM_MSR_RET_INVALID) {
1416                 /* Unconditionally clear the output for simplicity */
1417                 *data = 0;
1418                 r = kvm_msr_ignored_check(vcpu, index, 0, false);
1419         }
1420
1421         if (r)
1422                 return r;
1423
1424         *data = msr.data;
1425
1426         return 0;
1427 }
1428
1429 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1430 {
1431         if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1432                 return false;
1433
1434         if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1435                 return false;
1436
1437         if (efer & (EFER_LME | EFER_LMA) &&
1438             !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1439                 return false;
1440
1441         if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1442                 return false;
1443
1444         return true;
1445
1446 }
1447 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1448 {
1449         if (efer & efer_reserved_bits)
1450                 return false;
1451
1452         return __kvm_valid_efer(vcpu, efer);
1453 }
1454 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1455
1456 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1457 {
1458         u64 old_efer = vcpu->arch.efer;
1459         u64 efer = msr_info->data;
1460
1461         if (efer & efer_reserved_bits)
1462                 return 1;
1463
1464         if (!msr_info->host_initiated) {
1465                 if (!__kvm_valid_efer(vcpu, efer))
1466                         return 1;
1467
1468                 if (is_paging(vcpu) &&
1469                     (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1470                         return 1;
1471         }
1472
1473         efer &= ~EFER_LMA;
1474         efer |= vcpu->arch.efer & EFER_LMA;
1475
1476         kvm_x86_ops.set_efer(vcpu, efer);
1477
1478         /* Update reserved bits */
1479         if ((efer ^ old_efer) & EFER_NX)
1480                 kvm_mmu_reset_context(vcpu);
1481
1482         return 0;
1483 }
1484
1485 void kvm_enable_efer_bits(u64 mask)
1486 {
1487        efer_reserved_bits &= ~mask;
1488 }
1489 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1490
1491 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1492 {
1493         struct kvm *kvm = vcpu->kvm;
1494         struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
1495         u32 count = kvm->arch.msr_filter.count;
1496         u32 i;
1497         bool r = kvm->arch.msr_filter.default_allow;
1498         int idx;
1499
1500         /* MSR filtering not set up or x2APIC enabled, allow everything */
1501         if (!count || (index >= 0x800 && index <= 0x8ff))
1502                 return true;
1503
1504         /* Prevent collision with set_msr_filter */
1505         idx = srcu_read_lock(&kvm->srcu);
1506
1507         for (i = 0; i < count; i++) {
1508                 u32 start = ranges[i].base;
1509                 u32 end = start + ranges[i].nmsrs;
1510                 u32 flags = ranges[i].flags;
1511                 unsigned long *bitmap = ranges[i].bitmap;
1512
1513                 if ((index >= start) && (index < end) && (flags & type)) {
1514                         r = !!test_bit(index - start, bitmap);
1515                         break;
1516                 }
1517         }
1518
1519         srcu_read_unlock(&kvm->srcu, idx);
1520
1521         return r;
1522 }
1523 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1524
1525 /*
1526  * Write @data into the MSR specified by @index.  Select MSR specific fault
1527  * checks are bypassed if @host_initiated is %true.
1528  * Returns 0 on success, non-0 otherwise.
1529  * Assumes vcpu_load() was already called.
1530  */
1531 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1532                          bool host_initiated)
1533 {
1534         struct msr_data msr;
1535
1536         if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1537                 return -EPERM;
1538
1539         switch (index) {
1540         case MSR_FS_BASE:
1541         case MSR_GS_BASE:
1542         case MSR_KERNEL_GS_BASE:
1543         case MSR_CSTAR:
1544         case MSR_LSTAR:
1545                 if (is_noncanonical_address(data, vcpu))
1546                         return 1;
1547                 break;
1548         case MSR_IA32_SYSENTER_EIP:
1549         case MSR_IA32_SYSENTER_ESP:
1550                 /*
1551                  * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1552                  * non-canonical address is written on Intel but not on
1553                  * AMD (which ignores the top 32-bits, because it does
1554                  * not implement 64-bit SYSENTER).
1555                  *
1556                  * 64-bit code should hence be able to write a non-canonical
1557                  * value on AMD.  Making the address canonical ensures that
1558                  * vmentry does not fail on Intel after writing a non-canonical
1559                  * value, and that something deterministic happens if the guest
1560                  * invokes 64-bit SYSENTER.
1561                  */
1562                 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1563         }
1564
1565         msr.data = data;
1566         msr.index = index;
1567         msr.host_initiated = host_initiated;
1568
1569         return kvm_x86_ops.set_msr(vcpu, &msr);
1570 }
1571
1572 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1573                                      u32 index, u64 data, bool host_initiated)
1574 {
1575         int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1576
1577         if (ret == KVM_MSR_RET_INVALID)
1578                 ret = kvm_msr_ignored_check(vcpu, index, data, true);
1579
1580         return ret;
1581 }
1582
1583 /*
1584  * Read the MSR specified by @index into @data.  Select MSR specific fault
1585  * checks are bypassed if @host_initiated is %true.
1586  * Returns 0 on success, non-0 otherwise.
1587  * Assumes vcpu_load() was already called.
1588  */
1589 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1590                   bool host_initiated)
1591 {
1592         struct msr_data msr;
1593         int ret;
1594
1595         if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1596                 return -EPERM;
1597
1598         msr.index = index;
1599         msr.host_initiated = host_initiated;
1600
1601         ret = kvm_x86_ops.get_msr(vcpu, &msr);
1602         if (!ret)
1603                 *data = msr.data;
1604         return ret;
1605 }
1606
1607 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1608                                      u32 index, u64 *data, bool host_initiated)
1609 {
1610         int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1611
1612         if (ret == KVM_MSR_RET_INVALID) {
1613                 /* Unconditionally clear *data for simplicity */
1614                 *data = 0;
1615                 ret = kvm_msr_ignored_check(vcpu, index, 0, false);
1616         }
1617
1618         return ret;
1619 }
1620
1621 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1622 {
1623         return kvm_get_msr_ignored_check(vcpu, index, data, false);
1624 }
1625 EXPORT_SYMBOL_GPL(kvm_get_msr);
1626
1627 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1628 {
1629         return kvm_set_msr_ignored_check(vcpu, index, data, false);
1630 }
1631 EXPORT_SYMBOL_GPL(kvm_set_msr);
1632
1633 static int complete_emulated_msr(struct kvm_vcpu *vcpu, bool is_read)
1634 {
1635         if (vcpu->run->msr.error) {
1636                 kvm_inject_gp(vcpu, 0);
1637                 return 1;
1638         } else if (is_read) {
1639                 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1640                 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1641         }
1642
1643         return kvm_skip_emulated_instruction(vcpu);
1644 }
1645
1646 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1647 {
1648         return complete_emulated_msr(vcpu, true);
1649 }
1650
1651 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu)
1652 {
1653         return complete_emulated_msr(vcpu, false);
1654 }
1655
1656 static u64 kvm_msr_reason(int r)
1657 {
1658         switch (r) {
1659         case -ENOENT:
1660                 return KVM_MSR_EXIT_REASON_UNKNOWN;
1661         case -EPERM:
1662                 return KVM_MSR_EXIT_REASON_FILTER;
1663         default:
1664                 return KVM_MSR_EXIT_REASON_INVAL;
1665         }
1666 }
1667
1668 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1669                               u32 exit_reason, u64 data,
1670                               int (*completion)(struct kvm_vcpu *vcpu),
1671                               int r)
1672 {
1673         u64 msr_reason = kvm_msr_reason(r);
1674
1675         /* Check if the user wanted to know about this MSR fault */
1676         if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
1677                 return 0;
1678
1679         vcpu->run->exit_reason = exit_reason;
1680         vcpu->run->msr.error = 0;
1681         memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
1682         vcpu->run->msr.reason = msr_reason;
1683         vcpu->run->msr.index = index;
1684         vcpu->run->msr.data = data;
1685         vcpu->arch.complete_userspace_io = completion;
1686
1687         return 1;
1688 }
1689
1690 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r)
1691 {
1692         return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0,
1693                                    complete_emulated_rdmsr, r);
1694 }
1695
1696 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r)
1697 {
1698         return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data,
1699                                    complete_emulated_wrmsr, r);
1700 }
1701
1702 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1703 {
1704         u32 ecx = kvm_rcx_read(vcpu);
1705         u64 data;
1706         int r;
1707
1708         r = kvm_get_msr(vcpu, ecx, &data);
1709
1710         /* MSR read failed? See if we should ask user space */
1711         if (r && kvm_get_msr_user_space(vcpu, ecx, r)) {
1712                 /* Bounce to user space */
1713                 return 0;
1714         }
1715
1716         /* MSR read failed? Inject a #GP */
1717         if (r) {
1718                 trace_kvm_msr_read_ex(ecx);
1719                 kvm_inject_gp(vcpu, 0);
1720                 return 1;
1721         }
1722
1723         trace_kvm_msr_read(ecx, data);
1724
1725         kvm_rax_write(vcpu, data & -1u);
1726         kvm_rdx_write(vcpu, (data >> 32) & -1u);
1727         return kvm_skip_emulated_instruction(vcpu);
1728 }
1729 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1730
1731 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1732 {
1733         u32 ecx = kvm_rcx_read(vcpu);
1734         u64 data = kvm_read_edx_eax(vcpu);
1735         int r;
1736
1737         r = kvm_set_msr(vcpu, ecx, data);
1738
1739         /* MSR write failed? See if we should ask user space */
1740         if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) {
1741                 /* Bounce to user space */
1742                 return 0;
1743         }
1744
1745         /* MSR write failed? Inject a #GP */
1746         if (r) {
1747                 trace_kvm_msr_write_ex(ecx, data);
1748                 kvm_inject_gp(vcpu, 0);
1749                 return 1;
1750         }
1751
1752         trace_kvm_msr_write(ecx, data);
1753         return kvm_skip_emulated_instruction(vcpu);
1754 }
1755 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1756
1757 bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
1758 {
1759         return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
1760                 xfer_to_guest_mode_work_pending();
1761 }
1762 EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request);
1763
1764 /*
1765  * The fast path for frequent and performance sensitive wrmsr emulation,
1766  * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1767  * the latency of virtual IPI by avoiding the expensive bits of transitioning
1768  * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1769  * other cases which must be called after interrupts are enabled on the host.
1770  */
1771 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1772 {
1773         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1774                 return 1;
1775
1776         if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1777                 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1778                 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1779                 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1780
1781                 data &= ~(1 << 12);
1782                 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1783                 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1784                 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1785                 trace_kvm_apic_write(APIC_ICR, (u32)data);
1786                 return 0;
1787         }
1788
1789         return 1;
1790 }
1791
1792 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
1793 {
1794         if (!kvm_can_use_hv_timer(vcpu))
1795                 return 1;
1796
1797         kvm_set_lapic_tscdeadline_msr(vcpu, data);
1798         return 0;
1799 }
1800
1801 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1802 {
1803         u32 msr = kvm_rcx_read(vcpu);
1804         u64 data;
1805         fastpath_t ret = EXIT_FASTPATH_NONE;
1806
1807         switch (msr) {
1808         case APIC_BASE_MSR + (APIC_ICR >> 4):
1809                 data = kvm_read_edx_eax(vcpu);
1810                 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
1811                         kvm_skip_emulated_instruction(vcpu);
1812                         ret = EXIT_FASTPATH_EXIT_HANDLED;
1813                 }
1814                 break;
1815         case MSR_IA32_TSCDEADLINE:
1816                 data = kvm_read_edx_eax(vcpu);
1817                 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
1818                         kvm_skip_emulated_instruction(vcpu);
1819                         ret = EXIT_FASTPATH_REENTER_GUEST;
1820                 }
1821                 break;
1822         default:
1823                 break;
1824         }
1825
1826         if (ret != EXIT_FASTPATH_NONE)
1827                 trace_kvm_msr_write(msr, data);
1828
1829         return ret;
1830 }
1831 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1832
1833 /*
1834  * Adapt set_msr() to msr_io()'s calling convention
1835  */
1836 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1837 {
1838         return kvm_get_msr_ignored_check(vcpu, index, data, true);
1839 }
1840
1841 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1842 {
1843         return kvm_set_msr_ignored_check(vcpu, index, *data, true);
1844 }
1845
1846 #ifdef CONFIG_X86_64
1847 struct pvclock_clock {
1848         int vclock_mode;
1849         u64 cycle_last;
1850         u64 mask;
1851         u32 mult;
1852         u32 shift;
1853         u64 base_cycles;
1854         u64 offset;
1855 };
1856
1857 struct pvclock_gtod_data {
1858         seqcount_t      seq;
1859
1860         struct pvclock_clock clock; /* extract of a clocksource struct */
1861         struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1862
1863         ktime_t         offs_boot;
1864         u64             wall_time_sec;
1865 };
1866
1867 static struct pvclock_gtod_data pvclock_gtod_data;
1868
1869 static void update_pvclock_gtod(struct timekeeper *tk)
1870 {
1871         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1872
1873         write_seqcount_begin(&vdata->seq);
1874
1875         /* copy pvclock gtod data */
1876         vdata->clock.vclock_mode        = tk->tkr_mono.clock->vdso_clock_mode;
1877         vdata->clock.cycle_last         = tk->tkr_mono.cycle_last;
1878         vdata->clock.mask               = tk->tkr_mono.mask;
1879         vdata->clock.mult               = tk->tkr_mono.mult;
1880         vdata->clock.shift              = tk->tkr_mono.shift;
1881         vdata->clock.base_cycles        = tk->tkr_mono.xtime_nsec;
1882         vdata->clock.offset             = tk->tkr_mono.base;
1883
1884         vdata->raw_clock.vclock_mode    = tk->tkr_raw.clock->vdso_clock_mode;
1885         vdata->raw_clock.cycle_last     = tk->tkr_raw.cycle_last;
1886         vdata->raw_clock.mask           = tk->tkr_raw.mask;
1887         vdata->raw_clock.mult           = tk->tkr_raw.mult;
1888         vdata->raw_clock.shift          = tk->tkr_raw.shift;
1889         vdata->raw_clock.base_cycles    = tk->tkr_raw.xtime_nsec;
1890         vdata->raw_clock.offset         = tk->tkr_raw.base;
1891
1892         vdata->wall_time_sec            = tk->xtime_sec;
1893
1894         vdata->offs_boot                = tk->offs_boot;
1895
1896         write_seqcount_end(&vdata->seq);
1897 }
1898
1899 static s64 get_kvmclock_base_ns(void)
1900 {
1901         /* Count up from boot time, but with the frequency of the raw clock.  */
1902         return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1903 }
1904 #else
1905 static s64 get_kvmclock_base_ns(void)
1906 {
1907         /* Master clock not used, so we can just use CLOCK_BOOTTIME.  */
1908         return ktime_get_boottime_ns();
1909 }
1910 #endif
1911
1912 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1913 {
1914         int version;
1915         int r;
1916         struct pvclock_wall_clock wc;
1917         u64 wall_nsec;
1918
1919         if (!wall_clock)
1920                 return;
1921
1922         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1923         if (r)
1924                 return;
1925
1926         if (version & 1)
1927                 ++version;  /* first time write, random junk */
1928
1929         ++version;
1930
1931         if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1932                 return;
1933
1934         /*
1935          * The guest calculates current wall clock time by adding
1936          * system time (updated by kvm_guest_time_update below) to the
1937          * wall clock specified here.  We do the reverse here.
1938          */
1939         wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1940
1941         wc.nsec = do_div(wall_nsec, 1000000000);
1942         wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1943         wc.version = version;
1944
1945         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1946
1947         version++;
1948         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1949 }
1950
1951 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
1952                                   bool old_msr, bool host_initiated)
1953 {
1954         struct kvm_arch *ka = &vcpu->kvm->arch;
1955
1956         if (vcpu->vcpu_id == 0 && !host_initiated) {
1957                 if (ka->boot_vcpu_runs_old_kvmclock && old_msr)
1958                         kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1959
1960                 ka->boot_vcpu_runs_old_kvmclock = old_msr;
1961         }
1962
1963         vcpu->arch.time = system_time;
1964         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
1965
1966         /* we verify if the enable bit is set... */
1967         vcpu->arch.pv_time_enabled = false;
1968         if (!(system_time & 1))
1969                 return;
1970
1971         if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
1972                                        &vcpu->arch.pv_time, system_time & ~1ULL,
1973                                        sizeof(struct pvclock_vcpu_time_info)))
1974                 vcpu->arch.pv_time_enabled = true;
1975
1976         return;
1977 }
1978
1979 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1980 {
1981         do_shl32_div32(dividend, divisor);
1982         return dividend;
1983 }
1984
1985 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1986                                s8 *pshift, u32 *pmultiplier)
1987 {
1988         uint64_t scaled64;
1989         int32_t  shift = 0;
1990         uint64_t tps64;
1991         uint32_t tps32;
1992
1993         tps64 = base_hz;
1994         scaled64 = scaled_hz;
1995         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1996                 tps64 >>= 1;
1997                 shift--;
1998         }
1999
2000         tps32 = (uint32_t)tps64;
2001         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2002                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2003                         scaled64 >>= 1;
2004                 else
2005                         tps32 <<= 1;
2006                 shift++;
2007         }
2008
2009         *pshift = shift;
2010         *pmultiplier = div_frac(scaled64, tps32);
2011 }
2012
2013 #ifdef CONFIG_X86_64
2014 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2015 #endif
2016
2017 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2018 static unsigned long max_tsc_khz;
2019
2020 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2021 {
2022         u64 v = (u64)khz * (1000000 + ppm);
2023         do_div(v, 1000000);
2024         return v;
2025 }
2026
2027 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2028 {
2029         u64 ratio;
2030
2031         /* Guest TSC same frequency as host TSC? */
2032         if (!scale) {
2033                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2034                 return 0;
2035         }
2036
2037         /* TSC scaling supported? */
2038         if (!kvm_has_tsc_control) {
2039                 if (user_tsc_khz > tsc_khz) {
2040                         vcpu->arch.tsc_catchup = 1;
2041                         vcpu->arch.tsc_always_catchup = 1;
2042                         return 0;
2043                 } else {
2044                         pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2045                         return -1;
2046                 }
2047         }
2048
2049         /* TSC scaling required  - calculate ratio */
2050         ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
2051                                 user_tsc_khz, tsc_khz);
2052
2053         if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
2054                 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2055                                     user_tsc_khz);
2056                 return -1;
2057         }
2058
2059         vcpu->arch.tsc_scaling_ratio = ratio;
2060         return 0;
2061 }
2062
2063 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2064 {
2065         u32 thresh_lo, thresh_hi;
2066         int use_scaling = 0;
2067
2068         /* tsc_khz can be zero if TSC calibration fails */
2069         if (user_tsc_khz == 0) {
2070                 /* set tsc_scaling_ratio to a safe value */
2071                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2072                 return -1;
2073         }
2074
2075         /* Compute a scale to convert nanoseconds in TSC cycles */
2076         kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2077                            &vcpu->arch.virtual_tsc_shift,
2078                            &vcpu->arch.virtual_tsc_mult);
2079         vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2080
2081         /*
2082          * Compute the variation in TSC rate which is acceptable
2083          * within the range of tolerance and decide if the
2084          * rate being applied is within that bounds of the hardware
2085          * rate.  If so, no scaling or compensation need be done.
2086          */
2087         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2088         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2089         if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2090                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2091                 use_scaling = 1;
2092         }
2093         return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2094 }
2095
2096 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2097 {
2098         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2099                                       vcpu->arch.virtual_tsc_mult,
2100                                       vcpu->arch.virtual_tsc_shift);
2101         tsc += vcpu->arch.this_tsc_write;
2102         return tsc;
2103 }
2104
2105 static inline int gtod_is_based_on_tsc(int mode)
2106 {
2107         return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2108 }
2109
2110 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2111 {
2112 #ifdef CONFIG_X86_64
2113         bool vcpus_matched;
2114         struct kvm_arch *ka = &vcpu->kvm->arch;
2115         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2116
2117         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2118                          atomic_read(&vcpu->kvm->online_vcpus));
2119
2120         /*
2121          * Once the masterclock is enabled, always perform request in
2122          * order to update it.
2123          *
2124          * In order to enable masterclock, the host clocksource must be TSC
2125          * and the vcpus need to have matched TSCs.  When that happens,
2126          * perform request to enable masterclock.
2127          */
2128         if (ka->use_master_clock ||
2129             (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2130                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2131
2132         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2133                             atomic_read(&vcpu->kvm->online_vcpus),
2134                             ka->use_master_clock, gtod->clock.vclock_mode);
2135 #endif
2136 }
2137
2138 /*
2139  * Multiply tsc by a fixed point number represented by ratio.
2140  *
2141  * The most significant 64-N bits (mult) of ratio represent the
2142  * integral part of the fixed point number; the remaining N bits
2143  * (frac) represent the fractional part, ie. ratio represents a fixed
2144  * point number (mult + frac * 2^(-N)).
2145  *
2146  * N equals to kvm_tsc_scaling_ratio_frac_bits.
2147  */
2148 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2149 {
2150         return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
2151 }
2152
2153 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
2154 {
2155         u64 _tsc = tsc;
2156         u64 ratio = vcpu->arch.tsc_scaling_ratio;
2157
2158         if (ratio != kvm_default_tsc_scaling_ratio)
2159                 _tsc = __scale_tsc(ratio, tsc);
2160
2161         return _tsc;
2162 }
2163 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2164
2165 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2166 {
2167         u64 tsc;
2168
2169         tsc = kvm_scale_tsc(vcpu, rdtsc());
2170
2171         return target_tsc - tsc;
2172 }
2173
2174 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2175 {
2176         return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
2177 }
2178 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2179
2180 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2181 {
2182         vcpu->arch.l1_tsc_offset = offset;
2183         vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset);
2184 }
2185
2186 static inline bool kvm_check_tsc_unstable(void)
2187 {
2188 #ifdef CONFIG_X86_64
2189         /*
2190          * TSC is marked unstable when we're running on Hyper-V,
2191          * 'TSC page' clocksource is good.
2192          */
2193         if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2194                 return false;
2195 #endif
2196         return check_tsc_unstable();
2197 }
2198
2199 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2200 {
2201         struct kvm *kvm = vcpu->kvm;
2202         u64 offset, ns, elapsed;
2203         unsigned long flags;
2204         bool matched;
2205         bool already_matched;
2206         bool synchronizing = false;
2207
2208         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2209         offset = kvm_compute_tsc_offset(vcpu, data);
2210         ns = get_kvmclock_base_ns();
2211         elapsed = ns - kvm->arch.last_tsc_nsec;
2212
2213         if (vcpu->arch.virtual_tsc_khz) {
2214                 if (data == 0) {
2215                         /*
2216                          * detection of vcpu initialization -- need to sync
2217                          * with other vCPUs. This particularly helps to keep
2218                          * kvm_clock stable after CPU hotplug
2219                          */
2220                         synchronizing = true;
2221                 } else {
2222                         u64 tsc_exp = kvm->arch.last_tsc_write +
2223                                                 nsec_to_cycles(vcpu, elapsed);
2224                         u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2225                         /*
2226                          * Special case: TSC write with a small delta (1 second)
2227                          * of virtual cycle time against real time is
2228                          * interpreted as an attempt to synchronize the CPU.
2229                          */
2230                         synchronizing = data < tsc_exp + tsc_hz &&
2231                                         data + tsc_hz > tsc_exp;
2232                 }
2233         }
2234
2235         /*
2236          * For a reliable TSC, we can match TSC offsets, and for an unstable
2237          * TSC, we add elapsed time in this computation.  We could let the
2238          * compensation code attempt to catch up if we fall behind, but
2239          * it's better to try to match offsets from the beginning.
2240          */
2241         if (synchronizing &&
2242             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2243                 if (!kvm_check_tsc_unstable()) {
2244                         offset = kvm->arch.cur_tsc_offset;
2245                 } else {
2246                         u64 delta = nsec_to_cycles(vcpu, elapsed);
2247                         data += delta;
2248                         offset = kvm_compute_tsc_offset(vcpu, data);
2249                 }
2250                 matched = true;
2251                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2252         } else {
2253                 /*
2254                  * We split periods of matched TSC writes into generations.
2255                  * For each generation, we track the original measured
2256                  * nanosecond time, offset, and write, so if TSCs are in
2257                  * sync, we can match exact offset, and if not, we can match
2258                  * exact software computation in compute_guest_tsc()
2259                  *
2260                  * These values are tracked in kvm->arch.cur_xxx variables.
2261                  */
2262                 kvm->arch.cur_tsc_generation++;
2263                 kvm->arch.cur_tsc_nsec = ns;
2264                 kvm->arch.cur_tsc_write = data;
2265                 kvm->arch.cur_tsc_offset = offset;
2266                 matched = false;
2267         }
2268
2269         /*
2270          * We also track th most recent recorded KHZ, write and time to
2271          * allow the matching interval to be extended at each write.
2272          */
2273         kvm->arch.last_tsc_nsec = ns;
2274         kvm->arch.last_tsc_write = data;
2275         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2276
2277         vcpu->arch.last_guest_tsc = data;
2278
2279         /* Keep track of which generation this VCPU has synchronized to */
2280         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2281         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2282         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2283
2284         kvm_vcpu_write_tsc_offset(vcpu, offset);
2285         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2286
2287         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2288         if (!matched) {
2289                 kvm->arch.nr_vcpus_matched_tsc = 0;
2290         } else if (!already_matched) {
2291                 kvm->arch.nr_vcpus_matched_tsc++;
2292         }
2293
2294         kvm_track_tsc_matching(vcpu);
2295         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2296 }
2297
2298 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2299                                            s64 adjustment)
2300 {
2301         u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2302         kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2303 }
2304
2305 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2306 {
2307         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2308                 WARN_ON(adjustment < 0);
2309         adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2310         adjust_tsc_offset_guest(vcpu, adjustment);
2311 }
2312
2313 #ifdef CONFIG_X86_64
2314
2315 static u64 read_tsc(void)
2316 {
2317         u64 ret = (u64)rdtsc_ordered();
2318         u64 last = pvclock_gtod_data.clock.cycle_last;
2319
2320         if (likely(ret >= last))
2321                 return ret;
2322
2323         /*
2324          * GCC likes to generate cmov here, but this branch is extremely
2325          * predictable (it's just a function of time and the likely is
2326          * very likely) and there's a data dependence, so force GCC
2327          * to generate a branch instead.  I don't barrier() because
2328          * we don't actually need a barrier, and if this function
2329          * ever gets inlined it will generate worse code.
2330          */
2331         asm volatile ("");
2332         return last;
2333 }
2334
2335 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2336                           int *mode)
2337 {
2338         long v;
2339         u64 tsc_pg_val;
2340
2341         switch (clock->vclock_mode) {
2342         case VDSO_CLOCKMODE_HVCLOCK:
2343                 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2344                                                   tsc_timestamp);
2345                 if (tsc_pg_val != U64_MAX) {
2346                         /* TSC page valid */
2347                         *mode = VDSO_CLOCKMODE_HVCLOCK;
2348                         v = (tsc_pg_val - clock->cycle_last) &
2349                                 clock->mask;
2350                 } else {
2351                         /* TSC page invalid */
2352                         *mode = VDSO_CLOCKMODE_NONE;
2353                 }
2354                 break;
2355         case VDSO_CLOCKMODE_TSC:
2356                 *mode = VDSO_CLOCKMODE_TSC;
2357                 *tsc_timestamp = read_tsc();
2358                 v = (*tsc_timestamp - clock->cycle_last) &
2359                         clock->mask;
2360                 break;
2361         default:
2362                 *mode = VDSO_CLOCKMODE_NONE;
2363         }
2364
2365         if (*mode == VDSO_CLOCKMODE_NONE)
2366                 *tsc_timestamp = v = 0;
2367
2368         return v * clock->mult;
2369 }
2370
2371 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2372 {
2373         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2374         unsigned long seq;
2375         int mode;
2376         u64 ns;
2377
2378         do {
2379                 seq = read_seqcount_begin(&gtod->seq);
2380                 ns = gtod->raw_clock.base_cycles;
2381                 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2382                 ns >>= gtod->raw_clock.shift;
2383                 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2384         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2385         *t = ns;
2386
2387         return mode;
2388 }
2389
2390 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2391 {
2392         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2393         unsigned long seq;
2394         int mode;
2395         u64 ns;
2396
2397         do {
2398                 seq = read_seqcount_begin(&gtod->seq);
2399                 ts->tv_sec = gtod->wall_time_sec;
2400                 ns = gtod->clock.base_cycles;
2401                 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2402                 ns >>= gtod->clock.shift;
2403         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2404
2405         ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2406         ts->tv_nsec = ns;
2407
2408         return mode;
2409 }
2410
2411 /* returns true if host is using TSC based clocksource */
2412 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2413 {
2414         /* checked again under seqlock below */
2415         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2416                 return false;
2417
2418         return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2419                                                       tsc_timestamp));
2420 }
2421
2422 /* returns true if host is using TSC based clocksource */
2423 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2424                                            u64 *tsc_timestamp)
2425 {
2426         /* checked again under seqlock below */
2427         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2428                 return false;
2429
2430         return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2431 }
2432 #endif
2433
2434 /*
2435  *
2436  * Assuming a stable TSC across physical CPUS, and a stable TSC
2437  * across virtual CPUs, the following condition is possible.
2438  * Each numbered line represents an event visible to both
2439  * CPUs at the next numbered event.
2440  *
2441  * "timespecX" represents host monotonic time. "tscX" represents
2442  * RDTSC value.
2443  *
2444  *              VCPU0 on CPU0           |       VCPU1 on CPU1
2445  *
2446  * 1.  read timespec0,tsc0
2447  * 2.                                   | timespec1 = timespec0 + N
2448  *                                      | tsc1 = tsc0 + M
2449  * 3. transition to guest               | transition to guest
2450  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2451  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
2452  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2453  *
2454  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2455  *
2456  *      - ret0 < ret1
2457  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2458  *              ...
2459  *      - 0 < N - M => M < N
2460  *
2461  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2462  * always the case (the difference between two distinct xtime instances
2463  * might be smaller then the difference between corresponding TSC reads,
2464  * when updating guest vcpus pvclock areas).
2465  *
2466  * To avoid that problem, do not allow visibility of distinct
2467  * system_timestamp/tsc_timestamp values simultaneously: use a master
2468  * copy of host monotonic time values. Update that master copy
2469  * in lockstep.
2470  *
2471  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2472  *
2473  */
2474
2475 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2476 {
2477 #ifdef CONFIG_X86_64
2478         struct kvm_arch *ka = &kvm->arch;
2479         int vclock_mode;
2480         bool host_tsc_clocksource, vcpus_matched;
2481
2482         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2483                         atomic_read(&kvm->online_vcpus));
2484
2485         /*
2486          * If the host uses TSC clock, then passthrough TSC as stable
2487          * to the guest.
2488          */
2489         host_tsc_clocksource = kvm_get_time_and_clockread(
2490                                         &ka->master_kernel_ns,
2491                                         &ka->master_cycle_now);
2492
2493         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2494                                 && !ka->backwards_tsc_observed
2495                                 && !ka->boot_vcpu_runs_old_kvmclock;
2496
2497         if (ka->use_master_clock)
2498                 atomic_set(&kvm_guest_has_master_clock, 1);
2499
2500         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2501         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2502                                         vcpus_matched);
2503 #endif
2504 }
2505
2506 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2507 {
2508         kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2509 }
2510
2511 static void kvm_gen_update_masterclock(struct kvm *kvm)
2512 {
2513 #ifdef CONFIG_X86_64
2514         int i;
2515         struct kvm_vcpu *vcpu;
2516         struct kvm_arch *ka = &kvm->arch;
2517
2518         spin_lock(&ka->pvclock_gtod_sync_lock);
2519         kvm_make_mclock_inprogress_request(kvm);
2520         /* no guest entries from this point */
2521         pvclock_update_vm_gtod_copy(kvm);
2522
2523         kvm_for_each_vcpu(i, vcpu, kvm)
2524                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2525
2526         /* guest entries allowed */
2527         kvm_for_each_vcpu(i, vcpu, kvm)
2528                 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2529
2530         spin_unlock(&ka->pvclock_gtod_sync_lock);
2531 #endif
2532 }
2533
2534 u64 get_kvmclock_ns(struct kvm *kvm)
2535 {
2536         struct kvm_arch *ka = &kvm->arch;
2537         struct pvclock_vcpu_time_info hv_clock;
2538         u64 ret;
2539
2540         spin_lock(&ka->pvclock_gtod_sync_lock);
2541         if (!ka->use_master_clock) {
2542                 spin_unlock(&ka->pvclock_gtod_sync_lock);
2543                 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2544         }
2545
2546         hv_clock.tsc_timestamp = ka->master_cycle_now;
2547         hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2548         spin_unlock(&ka->pvclock_gtod_sync_lock);
2549
2550         /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2551         get_cpu();
2552
2553         if (__this_cpu_read(cpu_tsc_khz)) {
2554                 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2555                                    &hv_clock.tsc_shift,
2556                                    &hv_clock.tsc_to_system_mul);
2557                 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2558         } else
2559                 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2560
2561         put_cpu();
2562
2563         return ret;
2564 }
2565
2566 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2567 {
2568         struct kvm_vcpu_arch *vcpu = &v->arch;
2569         struct pvclock_vcpu_time_info guest_hv_clock;
2570
2571         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2572                 &guest_hv_clock, sizeof(guest_hv_clock))))
2573                 return;
2574
2575         /* This VCPU is paused, but it's legal for a guest to read another
2576          * VCPU's kvmclock, so we really have to follow the specification where
2577          * it says that version is odd if data is being modified, and even after
2578          * it is consistent.
2579          *
2580          * Version field updates must be kept separate.  This is because
2581          * kvm_write_guest_cached might use a "rep movs" instruction, and
2582          * writes within a string instruction are weakly ordered.  So there
2583          * are three writes overall.
2584          *
2585          * As a small optimization, only write the version field in the first
2586          * and third write.  The vcpu->pv_time cache is still valid, because the
2587          * version field is the first in the struct.
2588          */
2589         BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2590
2591         if (guest_hv_clock.version & 1)
2592                 ++guest_hv_clock.version;  /* first time write, random junk */
2593
2594         vcpu->hv_clock.version = guest_hv_clock.version + 1;
2595         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2596                                 &vcpu->hv_clock,
2597                                 sizeof(vcpu->hv_clock.version));
2598
2599         smp_wmb();
2600
2601         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2602         vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2603
2604         if (vcpu->pvclock_set_guest_stopped_request) {
2605                 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2606                 vcpu->pvclock_set_guest_stopped_request = false;
2607         }
2608
2609         trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2610
2611         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2612                                 &vcpu->hv_clock,
2613                                 sizeof(vcpu->hv_clock));
2614
2615         smp_wmb();
2616
2617         vcpu->hv_clock.version++;
2618         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2619                                 &vcpu->hv_clock,
2620                                 sizeof(vcpu->hv_clock.version));
2621 }
2622
2623 static int kvm_guest_time_update(struct kvm_vcpu *v)
2624 {
2625         unsigned long flags, tgt_tsc_khz;
2626         struct kvm_vcpu_arch *vcpu = &v->arch;
2627         struct kvm_arch *ka = &v->kvm->arch;
2628         s64 kernel_ns;
2629         u64 tsc_timestamp, host_tsc;
2630         u8 pvclock_flags;
2631         bool use_master_clock;
2632
2633         kernel_ns = 0;
2634         host_tsc = 0;
2635
2636         /*
2637          * If the host uses TSC clock, then passthrough TSC as stable
2638          * to the guest.
2639          */
2640         spin_lock(&ka->pvclock_gtod_sync_lock);
2641         use_master_clock = ka->use_master_clock;
2642         if (use_master_clock) {
2643                 host_tsc = ka->master_cycle_now;
2644                 kernel_ns = ka->master_kernel_ns;
2645         }
2646         spin_unlock(&ka->pvclock_gtod_sync_lock);
2647
2648         /* Keep irq disabled to prevent changes to the clock */
2649         local_irq_save(flags);
2650         tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2651         if (unlikely(tgt_tsc_khz == 0)) {
2652                 local_irq_restore(flags);
2653                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2654                 return 1;
2655         }
2656         if (!use_master_clock) {
2657                 host_tsc = rdtsc();
2658                 kernel_ns = get_kvmclock_base_ns();
2659         }
2660
2661         tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2662
2663         /*
2664          * We may have to catch up the TSC to match elapsed wall clock
2665          * time for two reasons, even if kvmclock is used.
2666          *   1) CPU could have been running below the maximum TSC rate
2667          *   2) Broken TSC compensation resets the base at each VCPU
2668          *      entry to avoid unknown leaps of TSC even when running
2669          *      again on the same CPU.  This may cause apparent elapsed
2670          *      time to disappear, and the guest to stand still or run
2671          *      very slowly.
2672          */
2673         if (vcpu->tsc_catchup) {
2674                 u64 tsc = compute_guest_tsc(v, kernel_ns);
2675                 if (tsc > tsc_timestamp) {
2676                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2677                         tsc_timestamp = tsc;
2678                 }
2679         }
2680
2681         local_irq_restore(flags);
2682
2683         /* With all the info we got, fill in the values */
2684
2685         if (kvm_has_tsc_control)
2686                 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2687
2688         if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2689                 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2690                                    &vcpu->hv_clock.tsc_shift,
2691                                    &vcpu->hv_clock.tsc_to_system_mul);
2692                 vcpu->hw_tsc_khz = tgt_tsc_khz;
2693         }
2694
2695         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2696         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2697         vcpu->last_guest_tsc = tsc_timestamp;
2698
2699         /* If the host uses TSC clocksource, then it is stable */
2700         pvclock_flags = 0;
2701         if (use_master_clock)
2702                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2703
2704         vcpu->hv_clock.flags = pvclock_flags;
2705
2706         if (vcpu->pv_time_enabled)
2707                 kvm_setup_pvclock_page(v);
2708         if (v == kvm_get_vcpu(v->kvm, 0))
2709                 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2710         return 0;
2711 }
2712
2713 /*
2714  * kvmclock updates which are isolated to a given vcpu, such as
2715  * vcpu->cpu migration, should not allow system_timestamp from
2716  * the rest of the vcpus to remain static. Otherwise ntp frequency
2717  * correction applies to one vcpu's system_timestamp but not
2718  * the others.
2719  *
2720  * So in those cases, request a kvmclock update for all vcpus.
2721  * We need to rate-limit these requests though, as they can
2722  * considerably slow guests that have a large number of vcpus.
2723  * The time for a remote vcpu to update its kvmclock is bound
2724  * by the delay we use to rate-limit the updates.
2725  */
2726
2727 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2728
2729 static void kvmclock_update_fn(struct work_struct *work)
2730 {
2731         int i;
2732         struct delayed_work *dwork = to_delayed_work(work);
2733         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2734                                            kvmclock_update_work);
2735         struct kvm *kvm = container_of(ka, struct kvm, arch);
2736         struct kvm_vcpu *vcpu;
2737
2738         kvm_for_each_vcpu(i, vcpu, kvm) {
2739                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2740                 kvm_vcpu_kick(vcpu);
2741         }
2742 }
2743
2744 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2745 {
2746         struct kvm *kvm = v->kvm;
2747
2748         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2749         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2750                                         KVMCLOCK_UPDATE_DELAY);
2751 }
2752
2753 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2754
2755 static void kvmclock_sync_fn(struct work_struct *work)
2756 {
2757         struct delayed_work *dwork = to_delayed_work(work);
2758         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2759                                            kvmclock_sync_work);
2760         struct kvm *kvm = container_of(ka, struct kvm, arch);
2761
2762         if (!kvmclock_periodic_sync)
2763                 return;
2764
2765         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2766         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2767                                         KVMCLOCK_SYNC_PERIOD);
2768 }
2769
2770 /*
2771  * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2772  */
2773 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2774 {
2775         /* McStatusWrEn enabled? */
2776         if (guest_cpuid_is_amd_or_hygon(vcpu))
2777                 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2778
2779         return false;
2780 }
2781
2782 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2783 {
2784         u64 mcg_cap = vcpu->arch.mcg_cap;
2785         unsigned bank_num = mcg_cap & 0xff;
2786         u32 msr = msr_info->index;
2787         u64 data = msr_info->data;
2788
2789         switch (msr) {
2790         case MSR_IA32_MCG_STATUS:
2791                 vcpu->arch.mcg_status = data;
2792                 break;
2793         case MSR_IA32_MCG_CTL:
2794                 if (!(mcg_cap & MCG_CTL_P) &&
2795                     (data || !msr_info->host_initiated))
2796                         return 1;
2797                 if (data != 0 && data != ~(u64)0)
2798                         return 1;
2799                 vcpu->arch.mcg_ctl = data;
2800                 break;
2801         default:
2802                 if (msr >= MSR_IA32_MC0_CTL &&
2803                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2804                         u32 offset = array_index_nospec(
2805                                 msr - MSR_IA32_MC0_CTL,
2806                                 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2807
2808                         /* only 0 or all 1s can be written to IA32_MCi_CTL
2809                          * some Linux kernels though clear bit 10 in bank 4 to
2810                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2811                          * this to avoid an uncatched #GP in the guest
2812                          */
2813                         if ((offset & 0x3) == 0 &&
2814                             data != 0 && (data | (1 << 10)) != ~(u64)0)
2815                                 return -1;
2816
2817                         /* MCi_STATUS */
2818                         if (!msr_info->host_initiated &&
2819                             (offset & 0x3) == 1 && data != 0) {
2820                                 if (!can_set_mci_status(vcpu))
2821                                         return -1;
2822                         }
2823
2824                         vcpu->arch.mce_banks[offset] = data;
2825                         break;
2826                 }
2827                 return 1;
2828         }
2829         return 0;
2830 }
2831
2832 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2833 {
2834         struct kvm *kvm = vcpu->kvm;
2835         int lm = is_long_mode(vcpu);
2836         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2837                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2838         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2839                 : kvm->arch.xen_hvm_config.blob_size_32;
2840         u32 page_num = data & ~PAGE_MASK;
2841         u64 page_addr = data & PAGE_MASK;
2842         u8 *page;
2843         int r;
2844
2845         r = -E2BIG;
2846         if (page_num >= blob_size)
2847                 goto out;
2848         r = -ENOMEM;
2849         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2850         if (IS_ERR(page)) {
2851                 r = PTR_ERR(page);
2852                 goto out;
2853         }
2854         if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2855                 goto out_free;
2856         r = 0;
2857 out_free:
2858         kfree(page);
2859 out:
2860         return r;
2861 }
2862
2863 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
2864 {
2865         u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
2866
2867         return (vcpu->arch.apf.msr_en_val & mask) == mask;
2868 }
2869
2870 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2871 {
2872         gpa_t gpa = data & ~0x3f;
2873
2874         /* Bits 4:5 are reserved, Should be zero */
2875         if (data & 0x30)
2876                 return 1;
2877
2878         if (!lapic_in_kernel(vcpu))
2879                 return data ? 1 : 0;
2880
2881         vcpu->arch.apf.msr_en_val = data;
2882
2883         if (!kvm_pv_async_pf_enabled(vcpu)) {
2884                 kvm_clear_async_pf_completion_queue(vcpu);
2885                 kvm_async_pf_hash_reset(vcpu);
2886                 return 0;
2887         }
2888
2889         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2890                                         sizeof(u64)))
2891                 return 1;
2892
2893         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2894         vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2895
2896         kvm_async_pf_wakeup_all(vcpu);
2897
2898         return 0;
2899 }
2900
2901 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
2902 {
2903         /* Bits 8-63 are reserved */
2904         if (data >> 8)
2905                 return 1;
2906
2907         if (!lapic_in_kernel(vcpu))
2908                 return 1;
2909
2910         vcpu->arch.apf.msr_int_val = data;
2911
2912         vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
2913
2914         return 0;
2915 }
2916
2917 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2918 {
2919         vcpu->arch.pv_time_enabled = false;
2920         vcpu->arch.time = 0;
2921 }
2922
2923 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
2924 {
2925         ++vcpu->stat.tlb_flush;
2926         kvm_x86_ops.tlb_flush_all(vcpu);
2927 }
2928
2929 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
2930 {
2931         ++vcpu->stat.tlb_flush;
2932         kvm_x86_ops.tlb_flush_guest(vcpu);
2933 }
2934
2935 static void record_steal_time(struct kvm_vcpu *vcpu)
2936 {
2937         struct kvm_host_map map;
2938         struct kvm_steal_time *st;
2939
2940         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2941                 return;
2942
2943         /* -EAGAIN is returned in atomic context so we can just return. */
2944         if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2945                         &map, &vcpu->arch.st.cache, false))
2946                 return;
2947
2948         st = map.hva +
2949                 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2950
2951         /*
2952          * Doing a TLB flush here, on the guest's behalf, can avoid
2953          * expensive IPIs.
2954          */
2955         trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2956                 st->preempted & KVM_VCPU_FLUSH_TLB);
2957         if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2958                 kvm_vcpu_flush_tlb_guest(vcpu);
2959
2960         vcpu->arch.st.preempted = 0;
2961
2962         if (st->version & 1)
2963                 st->version += 1;  /* first time write, random junk */
2964
2965         st->version += 1;
2966
2967         smp_wmb();
2968
2969         st->steal += current->sched_info.run_delay -
2970                 vcpu->arch.st.last_steal;
2971         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2972
2973         smp_wmb();
2974
2975         st->version += 1;
2976
2977         kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2978 }
2979
2980 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2981 {
2982         bool pr = false;
2983         u32 msr = msr_info->index;
2984         u64 data = msr_info->data;
2985
2986         switch (msr) {
2987         case MSR_AMD64_NB_CFG:
2988         case MSR_IA32_UCODE_WRITE:
2989         case MSR_VM_HSAVE_PA:
2990         case MSR_AMD64_PATCH_LOADER:
2991         case MSR_AMD64_BU_CFG2:
2992         case MSR_AMD64_DC_CFG:
2993         case MSR_F15H_EX_CFG:
2994                 break;
2995
2996         case MSR_IA32_UCODE_REV:
2997                 if (msr_info->host_initiated)
2998                         vcpu->arch.microcode_version = data;
2999                 break;
3000         case MSR_IA32_ARCH_CAPABILITIES:
3001                 if (!msr_info->host_initiated)
3002                         return 1;
3003                 vcpu->arch.arch_capabilities = data;
3004                 break;
3005         case MSR_IA32_PERF_CAPABILITIES: {
3006                 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
3007
3008                 if (!msr_info->host_initiated)
3009                         return 1;
3010                 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent))
3011                         return 1;
3012                 if (data & ~msr_ent.data)
3013                         return 1;
3014
3015                 vcpu->arch.perf_capabilities = data;
3016
3017                 return 0;
3018                 }
3019         case MSR_EFER:
3020                 return set_efer(vcpu, msr_info);
3021         case MSR_K7_HWCR:
3022                 data &= ~(u64)0x40;     /* ignore flush filter disable */
3023                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
3024                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
3025
3026                 /* Handle McStatusWrEn */
3027                 if (data == BIT_ULL(18)) {
3028                         vcpu->arch.msr_hwcr = data;
3029                 } else if (data != 0) {
3030                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3031                                     data);
3032                         return 1;
3033                 }
3034                 break;
3035         case MSR_FAM10H_MMIO_CONF_BASE:
3036                 if (data != 0) {
3037                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3038                                     "0x%llx\n", data);
3039                         return 1;
3040                 }
3041                 break;
3042         case MSR_IA32_DEBUGCTLMSR:
3043                 if (!data) {
3044                         /* We support the non-activated case already */
3045                         break;
3046                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
3047                         /* Values other than LBR and BTF are vendor-specific,
3048                            thus reserved and should throw a #GP */
3049                         return 1;
3050                 }
3051                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
3052                             __func__, data);
3053                 break;
3054         case 0x200 ... 0x2ff:
3055                 return kvm_mtrr_set_msr(vcpu, msr, data);
3056         case MSR_IA32_APICBASE:
3057                 return kvm_set_apic_base(vcpu, msr_info);
3058         case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3059                 return kvm_x2apic_msr_write(vcpu, msr, data);
3060         case MSR_IA32_TSCDEADLINE:
3061                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3062                 break;
3063         case MSR_IA32_TSC_ADJUST:
3064                 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3065                         if (!msr_info->host_initiated) {
3066                                 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3067                                 adjust_tsc_offset_guest(vcpu, adj);
3068                         }
3069                         vcpu->arch.ia32_tsc_adjust_msr = data;
3070                 }
3071                 break;
3072         case MSR_IA32_MISC_ENABLE:
3073                 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3074                     ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3075                         if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3076                                 return 1;
3077                         vcpu->arch.ia32_misc_enable_msr = data;
3078                         kvm_update_cpuid_runtime(vcpu);
3079                 } else {
3080                         vcpu->arch.ia32_misc_enable_msr = data;
3081                 }
3082                 break;
3083         case MSR_IA32_SMBASE:
3084                 if (!msr_info->host_initiated)
3085                         return 1;
3086                 vcpu->arch.smbase = data;
3087                 break;
3088         case MSR_IA32_POWER_CTL:
3089                 vcpu->arch.msr_ia32_power_ctl = data;
3090                 break;
3091         case MSR_IA32_TSC:
3092                 if (msr_info->host_initiated) {
3093                         kvm_synchronize_tsc(vcpu, data);
3094                 } else {
3095                         u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3096                         adjust_tsc_offset_guest(vcpu, adj);
3097                         vcpu->arch.ia32_tsc_adjust_msr += adj;
3098                 }
3099                 break;
3100         case MSR_IA32_XSS:
3101                 if (!msr_info->host_initiated &&
3102                     !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3103                         return 1;
3104                 /*
3105                  * KVM supports exposing PT to the guest, but does not support
3106                  * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3107                  * XSAVES/XRSTORS to save/restore PT MSRs.
3108                  */
3109                 if (data & ~supported_xss)
3110                         return 1;
3111                 vcpu->arch.ia32_xss = data;
3112                 break;
3113         case MSR_SMI_COUNT:
3114                 if (!msr_info->host_initiated)
3115                         return 1;
3116                 vcpu->arch.smi_count = data;
3117                 break;
3118         case MSR_KVM_WALL_CLOCK_NEW:
3119         case MSR_KVM_WALL_CLOCK:
3120                 vcpu->kvm->arch.wall_clock = data;
3121                 kvm_write_wall_clock(vcpu->kvm, data);
3122                 break;
3123         case MSR_KVM_SYSTEM_TIME_NEW:
3124                 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3125                 break;
3126         case MSR_KVM_SYSTEM_TIME:
3127                 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3128                 break;
3129         case MSR_KVM_ASYNC_PF_EN:
3130                 if (kvm_pv_enable_async_pf(vcpu, data))
3131                         return 1;
3132                 break;
3133         case MSR_KVM_ASYNC_PF_INT:
3134                 if (kvm_pv_enable_async_pf_int(vcpu, data))
3135                         return 1;
3136                 break;
3137         case MSR_KVM_ASYNC_PF_ACK:
3138                 if (data & 0x1) {
3139                         vcpu->arch.apf.pageready_pending = false;
3140                         kvm_check_async_pf_completion(vcpu);
3141                 }
3142                 break;
3143         case MSR_KVM_STEAL_TIME:
3144
3145                 if (unlikely(!sched_info_on()))
3146                         return 1;
3147
3148                 if (data & KVM_STEAL_RESERVED_MASK)
3149                         return 1;
3150
3151                 vcpu->arch.st.msr_val = data;
3152
3153                 if (!(data & KVM_MSR_ENABLED))
3154                         break;
3155
3156                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3157
3158                 break;
3159         case MSR_KVM_PV_EOI_EN:
3160                 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
3161                         return 1;
3162                 break;
3163
3164         case MSR_KVM_POLL_CONTROL:
3165                 /* only enable bit supported */
3166                 if (data & (-1ULL << 1))
3167                         return 1;
3168
3169                 vcpu->arch.msr_kvm_poll_control = data;
3170                 break;
3171
3172         case MSR_IA32_MCG_CTL:
3173         case MSR_IA32_MCG_STATUS:
3174         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3175                 return set_msr_mce(vcpu, msr_info);
3176
3177         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3178         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3179                 pr = true;
3180                 fallthrough;
3181         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3182         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3183                 if (kvm_pmu_is_valid_msr(vcpu, msr))
3184                         return kvm_pmu_set_msr(vcpu, msr_info);
3185
3186                 if (pr || data != 0)
3187                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3188                                     "0x%x data 0x%llx\n", msr, data);
3189                 break;
3190         case MSR_K7_CLK_CTL:
3191                 /*
3192                  * Ignore all writes to this no longer documented MSR.
3193                  * Writes are only relevant for old K7 processors,
3194                  * all pre-dating SVM, but a recommended workaround from
3195                  * AMD for these chips. It is possible to specify the
3196                  * affected processor models on the command line, hence
3197                  * the need to ignore the workaround.
3198                  */
3199                 break;
3200         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3201         case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3202         case HV_X64_MSR_SYNDBG_OPTIONS:
3203         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3204         case HV_X64_MSR_CRASH_CTL:
3205         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3206         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3207         case HV_X64_MSR_TSC_EMULATION_CONTROL:
3208         case HV_X64_MSR_TSC_EMULATION_STATUS:
3209                 return kvm_hv_set_msr_common(vcpu, msr, data,
3210                                              msr_info->host_initiated);
3211         case MSR_IA32_BBL_CR_CTL3:
3212                 /* Drop writes to this legacy MSR -- see rdmsr
3213                  * counterpart for further detail.
3214                  */
3215                 if (report_ignored_msrs)
3216                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3217                                 msr, data);
3218                 break;
3219         case MSR_AMD64_OSVW_ID_LENGTH:
3220                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3221                         return 1;
3222                 vcpu->arch.osvw.length = data;
3223                 break;
3224         case MSR_AMD64_OSVW_STATUS:
3225                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3226                         return 1;
3227                 vcpu->arch.osvw.status = data;
3228                 break;
3229         case MSR_PLATFORM_INFO:
3230                 if (!msr_info->host_initiated ||
3231                     (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3232                      cpuid_fault_enabled(vcpu)))
3233                         return 1;
3234                 vcpu->arch.msr_platform_info = data;
3235                 break;
3236         case MSR_MISC_FEATURES_ENABLES:
3237                 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3238                     (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3239                      !supports_cpuid_fault(vcpu)))
3240                         return 1;
3241                 vcpu->arch.msr_misc_features_enables = data;
3242                 break;
3243         default:
3244                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
3245                         return xen_hvm_config(vcpu, data);
3246                 if (kvm_pmu_is_valid_msr(vcpu, msr))
3247                         return kvm_pmu_set_msr(vcpu, msr_info);
3248                 return KVM_MSR_RET_INVALID;
3249         }
3250         return 0;
3251 }
3252 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3253
3254 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3255 {
3256         u64 data;
3257         u64 mcg_cap = vcpu->arch.mcg_cap;
3258         unsigned bank_num = mcg_cap & 0xff;
3259
3260         switch (msr) {
3261         case MSR_IA32_P5_MC_ADDR:
3262         case MSR_IA32_P5_MC_TYPE:
3263                 data = 0;
3264                 break;
3265         case MSR_IA32_MCG_CAP:
3266                 data = vcpu->arch.mcg_cap;
3267                 break;
3268         case MSR_IA32_MCG_CTL:
3269                 if (!(mcg_cap & MCG_CTL_P) && !host)
3270                         return 1;
3271                 data = vcpu->arch.mcg_ctl;
3272                 break;
3273         case MSR_IA32_MCG_STATUS:
3274                 data = vcpu->arch.mcg_status;
3275                 break;
3276         default:
3277                 if (msr >= MSR_IA32_MC0_CTL &&
3278                     msr < MSR_IA32_MCx_CTL(bank_num)) {
3279                         u32 offset = array_index_nospec(
3280                                 msr - MSR_IA32_MC0_CTL,
3281                                 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3282
3283                         data = vcpu->arch.mce_banks[offset];
3284                         break;
3285                 }
3286                 return 1;
3287         }
3288         *pdata = data;
3289         return 0;
3290 }
3291
3292 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3293 {
3294         switch (msr_info->index) {
3295         case MSR_IA32_PLATFORM_ID:
3296         case MSR_IA32_EBL_CR_POWERON:
3297         case MSR_IA32_DEBUGCTLMSR:
3298         case MSR_IA32_LASTBRANCHFROMIP:
3299         case MSR_IA32_LASTBRANCHTOIP:
3300         case MSR_IA32_LASTINTFROMIP:
3301         case MSR_IA32_LASTINTTOIP:
3302         case MSR_K8_SYSCFG:
3303         case MSR_K8_TSEG_ADDR:
3304         case MSR_K8_TSEG_MASK:
3305         case MSR_VM_HSAVE_PA:
3306         case MSR_K8_INT_PENDING_MSG:
3307         case MSR_AMD64_NB_CFG:
3308         case MSR_FAM10H_MMIO_CONF_BASE:
3309         case MSR_AMD64_BU_CFG2:
3310         case MSR_IA32_PERF_CTL:
3311         case MSR_AMD64_DC_CFG:
3312         case MSR_F15H_EX_CFG:
3313         /*
3314          * Intel Sandy Bridge CPUs must support the RAPL (running average power
3315          * limit) MSRs. Just return 0, as we do not want to expose the host
3316          * data here. Do not conditionalize this on CPUID, as KVM does not do
3317          * so for existing CPU-specific MSRs.
3318          */
3319         case MSR_RAPL_POWER_UNIT:
3320         case MSR_PP0_ENERGY_STATUS:     /* Power plane 0 (core) */
3321         case MSR_PP1_ENERGY_STATUS:     /* Power plane 1 (graphics uncore) */
3322         case MSR_PKG_ENERGY_STATUS:     /* Total package */
3323         case MSR_DRAM_ENERGY_STATUS:    /* DRAM controller */
3324                 msr_info->data = 0;
3325                 break;
3326         case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3327         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3328         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3329         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3330         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3331                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3332                         return kvm_pmu_get_msr(vcpu, msr_info);
3333                 msr_info->data = 0;
3334                 break;
3335         case MSR_IA32_UCODE_REV:
3336                 msr_info->data = vcpu->arch.microcode_version;
3337                 break;
3338         case MSR_IA32_ARCH_CAPABILITIES:
3339                 if (!msr_info->host_initiated &&
3340                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3341                         return 1;
3342                 msr_info->data = vcpu->arch.arch_capabilities;
3343                 break;
3344         case MSR_IA32_PERF_CAPABILITIES:
3345                 if (!msr_info->host_initiated &&
3346                     !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3347                         return 1;
3348                 msr_info->data = vcpu->arch.perf_capabilities;
3349                 break;
3350         case MSR_IA32_POWER_CTL:
3351                 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3352                 break;
3353         case MSR_IA32_TSC: {
3354                 /*
3355                  * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
3356                  * even when not intercepted. AMD manual doesn't explicitly
3357                  * state this but appears to behave the same.
3358                  *
3359                  * Unconditionally return L1's TSC offset on userspace reads
3360                  * so that userspace reads and writes always operate on L1's
3361                  * offset, e.g. to ensure deterministic behavior for migration.
3362                  */
3363                 u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset :
3364                                                             vcpu->arch.tsc_offset;
3365
3366                 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset;
3367                 break;
3368         }
3369         case MSR_MTRRcap:
3370         case 0x200 ... 0x2ff:
3371                 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3372         case 0xcd: /* fsb frequency */
3373                 msr_info->data = 3;
3374                 break;
3375                 /*
3376                  * MSR_EBC_FREQUENCY_ID
3377                  * Conservative value valid for even the basic CPU models.
3378                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3379                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3380                  * and 266MHz for model 3, or 4. Set Core Clock
3381                  * Frequency to System Bus Frequency Ratio to 1 (bits
3382                  * 31:24) even though these are only valid for CPU
3383                  * models > 2, however guests may end up dividing or
3384                  * multiplying by zero otherwise.
3385                  */
3386         case MSR_EBC_FREQUENCY_ID:
3387                 msr_info->data = 1 << 24;
3388                 break;
3389         case MSR_IA32_APICBASE:
3390                 msr_info->data = kvm_get_apic_base(vcpu);
3391                 break;
3392         case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3393                 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3394         case MSR_IA32_TSCDEADLINE:
3395                 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3396                 break;
3397         case MSR_IA32_TSC_ADJUST:
3398                 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3399                 break;
3400         case MSR_IA32_MISC_ENABLE:
3401                 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3402                 break;
3403         case MSR_IA32_SMBASE:
3404                 if (!msr_info->host_initiated)
3405                         return 1;
3406                 msr_info->data = vcpu->arch.smbase;
3407                 break;
3408         case MSR_SMI_COUNT:
3409                 msr_info->data = vcpu->arch.smi_count;
3410                 break;
3411         case MSR_IA32_PERF_STATUS:
3412                 /* TSC increment by tick */
3413                 msr_info->data = 1000ULL;
3414                 /* CPU multiplier */
3415                 msr_info->data |= (((uint64_t)4ULL) << 40);
3416                 break;
3417         case MSR_EFER:
3418                 msr_info->data = vcpu->arch.efer;
3419                 break;
3420         case MSR_KVM_WALL_CLOCK:
3421         case MSR_KVM_WALL_CLOCK_NEW:
3422                 msr_info->data = vcpu->kvm->arch.wall_clock;
3423                 break;
3424         case MSR_KVM_SYSTEM_TIME:
3425         case MSR_KVM_SYSTEM_TIME_NEW:
3426                 msr_info->data = vcpu->arch.time;
3427                 break;
3428         case MSR_KVM_ASYNC_PF_EN:
3429                 msr_info->data = vcpu->arch.apf.msr_en_val;
3430                 break;
3431         case MSR_KVM_ASYNC_PF_INT:
3432                 msr_info->data = vcpu->arch.apf.msr_int_val;
3433                 break;
3434         case MSR_KVM_ASYNC_PF_ACK:
3435                 msr_info->data = 0;
3436                 break;
3437         case MSR_KVM_STEAL_TIME:
3438                 msr_info->data = vcpu->arch.st.msr_val;
3439                 break;
3440         case MSR_KVM_PV_EOI_EN:
3441                 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3442                 break;
3443         case MSR_KVM_POLL_CONTROL:
3444                 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3445                 break;
3446         case MSR_IA32_P5_MC_ADDR:
3447         case MSR_IA32_P5_MC_TYPE:
3448         case MSR_IA32_MCG_CAP:
3449         case MSR_IA32_MCG_CTL:
3450         case MSR_IA32_MCG_STATUS:
3451         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3452                 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3453                                    msr_info->host_initiated);
3454         case MSR_IA32_XSS:
3455                 if (!msr_info->host_initiated &&
3456                     !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3457                         return 1;
3458                 msr_info->data = vcpu->arch.ia32_xss;
3459                 break;
3460         case MSR_K7_CLK_CTL:
3461                 /*
3462                  * Provide expected ramp-up count for K7. All other
3463                  * are set to zero, indicating minimum divisors for
3464                  * every field.
3465                  *
3466                  * This prevents guest kernels on AMD host with CPU
3467                  * type 6, model 8 and higher from exploding due to
3468                  * the rdmsr failing.
3469                  */
3470                 msr_info->data = 0x20000000;
3471                 break;
3472         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3473         case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3474         case HV_X64_MSR_SYNDBG_OPTIONS:
3475         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3476         case HV_X64_MSR_CRASH_CTL:
3477         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3478         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3479         case HV_X64_MSR_TSC_EMULATION_CONTROL:
3480         case HV_X64_MSR_TSC_EMULATION_STATUS:
3481                 return kvm_hv_get_msr_common(vcpu,
3482                                              msr_info->index, &msr_info->data,
3483                                              msr_info->host_initiated);
3484         case MSR_IA32_BBL_CR_CTL3:
3485                 /* This legacy MSR exists but isn't fully documented in current
3486                  * silicon.  It is however accessed by winxp in very narrow
3487                  * scenarios where it sets bit #19, itself documented as
3488                  * a "reserved" bit.  Best effort attempt to source coherent
3489                  * read data here should the balance of the register be
3490                  * interpreted by the guest:
3491                  *
3492                  * L2 cache control register 3: 64GB range, 256KB size,
3493                  * enabled, latency 0x1, configured
3494                  */
3495                 msr_info->data = 0xbe702111;
3496                 break;
3497         case MSR_AMD64_OSVW_ID_LENGTH:
3498                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3499                         return 1;
3500                 msr_info->data = vcpu->arch.osvw.length;
3501                 break;
3502         case MSR_AMD64_OSVW_STATUS:
3503                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3504                         return 1;
3505                 msr_info->data = vcpu->arch.osvw.status;
3506                 break;
3507         case MSR_PLATFORM_INFO:
3508                 if (!msr_info->host_initiated &&
3509                     !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3510                         return 1;
3511                 msr_info->data = vcpu->arch.msr_platform_info;
3512                 break;
3513         case MSR_MISC_FEATURES_ENABLES:
3514                 msr_info->data = vcpu->arch.msr_misc_features_enables;
3515                 break;
3516         case MSR_K7_HWCR:
3517                 msr_info->data = vcpu->arch.msr_hwcr;
3518                 break;
3519         default:
3520                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3521                         return kvm_pmu_get_msr(vcpu, msr_info);
3522                 return KVM_MSR_RET_INVALID;
3523         }
3524         return 0;
3525 }
3526 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3527
3528 /*
3529  * Read or write a bunch of msrs. All parameters are kernel addresses.
3530  *
3531  * @return number of msrs set successfully.
3532  */
3533 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3534                     struct kvm_msr_entry *entries,
3535                     int (*do_msr)(struct kvm_vcpu *vcpu,
3536                                   unsigned index, u64 *data))
3537 {
3538         int i;
3539
3540         for (i = 0; i < msrs->nmsrs; ++i)
3541                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3542                         break;
3543
3544         return i;
3545 }
3546
3547 /*
3548  * Read or write a bunch of msrs. Parameters are user addresses.
3549  *
3550  * @return number of msrs set successfully.
3551  */
3552 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3553                   int (*do_msr)(struct kvm_vcpu *vcpu,
3554                                 unsigned index, u64 *data),
3555                   int writeback)
3556 {
3557         struct kvm_msrs msrs;
3558         struct kvm_msr_entry *entries;
3559         int r, n;
3560         unsigned size;
3561
3562         r = -EFAULT;
3563         if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3564                 goto out;
3565
3566         r = -E2BIG;
3567         if (msrs.nmsrs >= MAX_IO_MSRS)
3568                 goto out;
3569
3570         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3571         entries = memdup_user(user_msrs->entries, size);
3572         if (IS_ERR(entries)) {
3573                 r = PTR_ERR(entries);
3574                 goto out;
3575         }
3576
3577         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3578         if (r < 0)
3579                 goto out_free;
3580
3581         r = -EFAULT;
3582         if (writeback && copy_to_user(user_msrs->entries, entries, size))
3583                 goto out_free;
3584
3585         r = n;
3586
3587 out_free:
3588         kfree(entries);
3589 out:
3590         return r;
3591 }
3592
3593 static inline bool kvm_can_mwait_in_guest(void)
3594 {
3595         return boot_cpu_has(X86_FEATURE_MWAIT) &&
3596                 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3597                 boot_cpu_has(X86_FEATURE_ARAT);
3598 }
3599
3600 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3601 {
3602         int r = 0;
3603
3604         switch (ext) {
3605         case KVM_CAP_IRQCHIP:
3606         case KVM_CAP_HLT:
3607         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3608         case KVM_CAP_SET_TSS_ADDR:
3609         case KVM_CAP_EXT_CPUID:
3610         case KVM_CAP_EXT_EMUL_CPUID:
3611         case KVM_CAP_CLOCKSOURCE:
3612         case KVM_CAP_PIT:
3613         case KVM_CAP_NOP_IO_DELAY:
3614         case KVM_CAP_MP_STATE:
3615         case KVM_CAP_SYNC_MMU:
3616         case KVM_CAP_USER_NMI:
3617         case KVM_CAP_REINJECT_CONTROL:
3618         case KVM_CAP_IRQ_INJECT_STATUS:
3619         case KVM_CAP_IOEVENTFD:
3620         case KVM_CAP_IOEVENTFD_NO_LENGTH:
3621         case KVM_CAP_PIT2:
3622         case KVM_CAP_PIT_STATE2:
3623         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3624         case KVM_CAP_XEN_HVM:
3625         case KVM_CAP_VCPU_EVENTS:
3626         case KVM_CAP_HYPERV:
3627         case KVM_CAP_HYPERV_VAPIC:
3628         case KVM_CAP_HYPERV_SPIN:
3629         case KVM_CAP_HYPERV_SYNIC:
3630         case KVM_CAP_HYPERV_SYNIC2:
3631         case KVM_CAP_HYPERV_VP_INDEX:
3632         case KVM_CAP_HYPERV_EVENTFD:
3633         case KVM_CAP_HYPERV_TLBFLUSH:
3634         case KVM_CAP_HYPERV_SEND_IPI:
3635         case KVM_CAP_HYPERV_CPUID:
3636         case KVM_CAP_PCI_SEGMENT:
3637         case KVM_CAP_DEBUGREGS:
3638         case KVM_CAP_X86_ROBUST_SINGLESTEP:
3639         case KVM_CAP_XSAVE:
3640         case KVM_CAP_ASYNC_PF:
3641         case KVM_CAP_ASYNC_PF_INT:
3642         case KVM_CAP_GET_TSC_KHZ:
3643         case KVM_CAP_KVMCLOCK_CTRL:
3644         case KVM_CAP_READONLY_MEM:
3645         case KVM_CAP_HYPERV_TIME:
3646         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3647         case KVM_CAP_TSC_DEADLINE_TIMER:
3648         case KVM_CAP_DISABLE_QUIRKS:
3649         case KVM_CAP_SET_BOOT_CPU_ID:
3650         case KVM_CAP_SPLIT_IRQCHIP:
3651         case KVM_CAP_IMMEDIATE_EXIT:
3652         case KVM_CAP_PMU_EVENT_FILTER:
3653         case KVM_CAP_GET_MSR_FEATURES:
3654         case KVM_CAP_MSR_PLATFORM_INFO:
3655         case KVM_CAP_EXCEPTION_PAYLOAD:
3656         case KVM_CAP_SET_GUEST_DEBUG:
3657         case KVM_CAP_LAST_CPU:
3658         case KVM_CAP_X86_USER_SPACE_MSR:
3659         case KVM_CAP_X86_MSR_FILTER:
3660                 r = 1;
3661                 break;
3662         case KVM_CAP_SYNC_REGS:
3663                 r = KVM_SYNC_X86_VALID_FIELDS;
3664                 break;
3665         case KVM_CAP_ADJUST_CLOCK:
3666                 r = KVM_CLOCK_TSC_STABLE;
3667                 break;
3668         case KVM_CAP_X86_DISABLE_EXITS:
3669                 r |=  KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3670                       KVM_X86_DISABLE_EXITS_CSTATE;
3671                 if(kvm_can_mwait_in_guest())
3672                         r |= KVM_X86_DISABLE_EXITS_MWAIT;
3673                 break;
3674         case KVM_CAP_X86_SMM:
3675                 /* SMBASE is usually relocated above 1M on modern chipsets,
3676                  * and SMM handlers might indeed rely on 4G segment limits,
3677                  * so do not report SMM to be available if real mode is
3678                  * emulated via vm86 mode.  Still, do not go to great lengths
3679                  * to avoid userspace's usage of the feature, because it is a
3680                  * fringe case that is not enabled except via specific settings
3681                  * of the module parameters.
3682                  */
3683                 r = kvm_x86_ops.has_emulated_msr(MSR_IA32_SMBASE);
3684                 break;
3685         case KVM_CAP_VAPIC:
3686                 r = !kvm_x86_ops.cpu_has_accelerated_tpr();
3687                 break;
3688         case KVM_CAP_NR_VCPUS:
3689                 r = KVM_SOFT_MAX_VCPUS;
3690                 break;
3691         case KVM_CAP_MAX_VCPUS:
3692                 r = KVM_MAX_VCPUS;
3693                 break;
3694         case KVM_CAP_MAX_VCPU_ID:
3695                 r = KVM_MAX_VCPU_ID;
3696                 break;
3697         case KVM_CAP_PV_MMU:    /* obsolete */
3698                 r = 0;
3699                 break;
3700         case KVM_CAP_MCE:
3701                 r = KVM_MAX_MCE_BANKS;
3702                 break;
3703         case KVM_CAP_XCRS:
3704                 r = boot_cpu_has(X86_FEATURE_XSAVE);
3705                 break;
3706         case KVM_CAP_TSC_CONTROL:
3707                 r = kvm_has_tsc_control;
3708                 break;
3709         case KVM_CAP_X2APIC_API:
3710                 r = KVM_X2APIC_API_VALID_FLAGS;
3711                 break;
3712         case KVM_CAP_NESTED_STATE:
3713                 r = kvm_x86_ops.nested_ops->get_state ?
3714                         kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
3715                 break;
3716         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3717                 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3718                 break;
3719         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3720                 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
3721                 break;
3722         case KVM_CAP_SMALLER_MAXPHYADDR:
3723                 r = (int) allow_smaller_maxphyaddr;
3724                 break;
3725         case KVM_CAP_STEAL_TIME:
3726                 r = sched_info_on();
3727                 break;
3728         default:
3729                 break;
3730         }
3731         return r;
3732
3733 }
3734
3735 long kvm_arch_dev_ioctl(struct file *filp,
3736                         unsigned int ioctl, unsigned long arg)
3737 {
3738         void __user *argp = (void __user *)arg;
3739         long r;
3740
3741         switch (ioctl) {
3742         case KVM_GET_MSR_INDEX_LIST: {
3743                 struct kvm_msr_list __user *user_msr_list = argp;
3744                 struct kvm_msr_list msr_list;
3745                 unsigned n;
3746
3747                 r = -EFAULT;
3748                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3749                         goto out;
3750                 n = msr_list.nmsrs;
3751                 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3752                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3753                         goto out;
3754                 r = -E2BIG;
3755                 if (n < msr_list.nmsrs)
3756                         goto out;
3757                 r = -EFAULT;
3758                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3759                                  num_msrs_to_save * sizeof(u32)))
3760                         goto out;
3761                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3762                                  &emulated_msrs,
3763                                  num_emulated_msrs * sizeof(u32)))
3764                         goto out;
3765                 r = 0;
3766                 break;
3767         }
3768         case KVM_GET_SUPPORTED_CPUID:
3769         case KVM_GET_EMULATED_CPUID: {
3770                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3771                 struct kvm_cpuid2 cpuid;
3772
3773                 r = -EFAULT;
3774                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3775                         goto out;
3776
3777                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3778                                             ioctl);
3779                 if (r)
3780                         goto out;
3781
3782                 r = -EFAULT;
3783                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3784                         goto out;
3785                 r = 0;
3786                 break;
3787         }
3788         case KVM_X86_GET_MCE_CAP_SUPPORTED:
3789                 r = -EFAULT;
3790                 if (copy_to_user(argp, &kvm_mce_cap_supported,
3791                                  sizeof(kvm_mce_cap_supported)))
3792                         goto out;
3793                 r = 0;
3794                 break;
3795         case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3796                 struct kvm_msr_list __user *user_msr_list = argp;
3797                 struct kvm_msr_list msr_list;
3798                 unsigned int n;
3799
3800                 r = -EFAULT;
3801                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3802                         goto out;
3803                 n = msr_list.nmsrs;
3804                 msr_list.nmsrs = num_msr_based_features;
3805                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3806                         goto out;
3807                 r = -E2BIG;
3808                 if (n < msr_list.nmsrs)
3809                         goto out;
3810                 r = -EFAULT;
3811                 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3812                                  num_msr_based_features * sizeof(u32)))
3813                         goto out;
3814                 r = 0;
3815                 break;
3816         }
3817         case KVM_GET_MSRS:
3818                 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3819                 break;
3820         default:
3821                 r = -EINVAL;
3822                 break;
3823         }
3824 out:
3825         return r;
3826 }
3827
3828 static void wbinvd_ipi(void *garbage)
3829 {
3830         wbinvd();
3831 }
3832
3833 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3834 {
3835         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3836 }
3837
3838 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3839 {
3840         /* Address WBINVD may be executed by guest */
3841         if (need_emulate_wbinvd(vcpu)) {
3842                 if (kvm_x86_ops.has_wbinvd_exit())
3843                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3844                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3845                         smp_call_function_single(vcpu->cpu,
3846                                         wbinvd_ipi, NULL, 1);
3847         }
3848
3849         kvm_x86_ops.vcpu_load(vcpu, cpu);
3850
3851         /* Save host pkru register if supported */
3852         vcpu->arch.host_pkru = read_pkru();
3853
3854         /* Apply any externally detected TSC adjustments (due to suspend) */
3855         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3856                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3857                 vcpu->arch.tsc_offset_adjustment = 0;
3858                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3859         }
3860
3861         if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3862                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3863                                 rdtsc() - vcpu->arch.last_host_tsc;
3864                 if (tsc_delta < 0)
3865                         mark_tsc_unstable("KVM discovered backwards TSC");
3866
3867                 if (kvm_check_tsc_unstable()) {
3868                         u64 offset = kvm_compute_tsc_offset(vcpu,
3869                                                 vcpu->arch.last_guest_tsc);
3870                         kvm_vcpu_write_tsc_offset(vcpu, offset);
3871                         vcpu->arch.tsc_catchup = 1;
3872                 }
3873
3874                 if (kvm_lapic_hv_timer_in_use(vcpu))
3875                         kvm_lapic_restart_hv_timer(vcpu);
3876
3877                 /*
3878                  * On a host with synchronized TSC, there is no need to update
3879                  * kvmclock on vcpu->cpu migration
3880                  */
3881                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3882                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3883                 if (vcpu->cpu != cpu)
3884                         kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3885                 vcpu->cpu = cpu;
3886         }
3887
3888         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3889 }
3890
3891 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3892 {
3893         struct kvm_host_map map;
3894         struct kvm_steal_time *st;
3895
3896         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3897                 return;
3898
3899         if (vcpu->arch.st.preempted)
3900                 return;
3901
3902         if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3903                         &vcpu->arch.st.cache, true))
3904                 return;
3905
3906         st = map.hva +
3907                 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
3908
3909         st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
3910
3911         kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
3912 }
3913
3914 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3915 {
3916         int idx;
3917
3918         if (vcpu->preempted)
3919                 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu);
3920
3921         /*
3922          * Disable page faults because we're in atomic context here.
3923          * kvm_write_guest_offset_cached() would call might_fault()
3924          * that relies on pagefault_disable() to tell if there's a
3925          * bug. NOTE: the write to guest memory may not go through if
3926          * during postcopy live migration or if there's heavy guest
3927          * paging.
3928          */
3929         pagefault_disable();
3930         /*
3931          * kvm_memslots() will be called by
3932          * kvm_write_guest_offset_cached() so take the srcu lock.
3933          */
3934         idx = srcu_read_lock(&vcpu->kvm->srcu);
3935         kvm_steal_time_set_preempted(vcpu);
3936         srcu_read_unlock(&vcpu->kvm->srcu, idx);
3937         pagefault_enable();
3938         kvm_x86_ops.vcpu_put(vcpu);
3939         vcpu->arch.last_host_tsc = rdtsc();
3940         /*
3941          * If userspace has set any breakpoints or watchpoints, dr6 is restored
3942          * on every vmexit, but if not, we might have a stale dr6 from the
3943          * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3944          */
3945         set_debugreg(0, 6);
3946 }
3947
3948 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3949                                     struct kvm_lapic_state *s)
3950 {
3951         if (vcpu->arch.apicv_active)
3952                 kvm_x86_ops.sync_pir_to_irr(vcpu);
3953
3954         return kvm_apic_get_state(vcpu, s);
3955 }
3956
3957 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3958                                     struct kvm_lapic_state *s)
3959 {
3960         int r;
3961
3962         r = kvm_apic_set_state(vcpu, s);
3963         if (r)
3964                 return r;
3965         update_cr8_intercept(vcpu);
3966
3967         return 0;
3968 }
3969
3970 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3971 {
3972         return (!lapic_in_kernel(vcpu) ||
3973                 kvm_apic_accept_pic_intr(vcpu));
3974 }
3975
3976 /*
3977  * if userspace requested an interrupt window, check that the
3978  * interrupt window is open.
3979  *
3980  * No need to exit to userspace if we already have an interrupt queued.
3981  */
3982 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3983 {
3984         return kvm_arch_interrupt_allowed(vcpu) &&
3985                 !kvm_cpu_has_interrupt(vcpu) &&
3986                 !kvm_event_needs_reinjection(vcpu) &&
3987                 kvm_cpu_accept_dm_intr(vcpu);
3988 }
3989
3990 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3991                                     struct kvm_interrupt *irq)
3992 {
3993         if (irq->irq >= KVM_NR_INTERRUPTS)
3994                 return -EINVAL;
3995
3996         if (!irqchip_in_kernel(vcpu->kvm)) {
3997                 kvm_queue_interrupt(vcpu, irq->irq, false);
3998                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3999                 return 0;
4000         }
4001
4002         /*
4003          * With in-kernel LAPIC, we only use this to inject EXTINT, so
4004          * fail for in-kernel 8259.
4005          */
4006         if (pic_in_kernel(vcpu->kvm))
4007                 return -ENXIO;
4008
4009         if (vcpu->arch.pending_external_vector != -1)
4010                 return -EEXIST;
4011
4012         vcpu->arch.pending_external_vector = irq->irq;
4013         kvm_make_request(KVM_REQ_EVENT, vcpu);
4014         return 0;
4015 }
4016
4017 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4018 {
4019         kvm_inject_nmi(vcpu);
4020
4021         return 0;
4022 }
4023
4024 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
4025 {
4026         kvm_make_request(KVM_REQ_SMI, vcpu);
4027
4028         return 0;
4029 }
4030
4031 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4032                                            struct kvm_tpr_access_ctl *tac)
4033 {
4034         if (tac->flags)
4035                 return -EINVAL;
4036         vcpu->arch.tpr_access_reporting = !!tac->enabled;
4037         return 0;
4038 }
4039
4040 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4041                                         u64 mcg_cap)
4042 {
4043         int r;
4044         unsigned bank_num = mcg_cap & 0xff, bank;
4045
4046         r = -EINVAL;
4047         if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4048                 goto out;
4049         if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
4050                 goto out;
4051         r = 0;
4052         vcpu->arch.mcg_cap = mcg_cap;
4053         /* Init IA32_MCG_CTL to all 1s */
4054         if (mcg_cap & MCG_CTL_P)
4055                 vcpu->arch.mcg_ctl = ~(u64)0;
4056         /* Init IA32_MCi_CTL to all 1s */
4057         for (bank = 0; bank < bank_num; bank++)
4058                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4059
4060         kvm_x86_ops.setup_mce(vcpu);
4061 out:
4062         return r;
4063 }
4064
4065 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4066                                       struct kvm_x86_mce *mce)
4067 {
4068         u64 mcg_cap = vcpu->arch.mcg_cap;
4069         unsigned bank_num = mcg_cap & 0xff;
4070         u64 *banks = vcpu->arch.mce_banks;
4071
4072         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
4073                 return -EINVAL;
4074         /*
4075          * if IA32_MCG_CTL is not all 1s, the uncorrected error
4076          * reporting is disabled
4077          */
4078         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
4079             vcpu->arch.mcg_ctl != ~(u64)0)
4080                 return 0;
4081         banks += 4 * mce->bank;
4082         /*
4083          * if IA32_MCi_CTL is not all 1s, the uncorrected error
4084          * reporting is disabled for the bank
4085          */
4086         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
4087                 return 0;
4088         if (mce->status & MCI_STATUS_UC) {
4089                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
4090                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
4091                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4092                         return 0;
4093                 }
4094                 if (banks[1] & MCI_STATUS_VAL)
4095                         mce->status |= MCI_STATUS_OVER;
4096                 banks[2] = mce->addr;
4097                 banks[3] = mce->misc;
4098                 vcpu->arch.mcg_status = mce->mcg_status;
4099                 banks[1] = mce->status;
4100                 kvm_queue_exception(vcpu, MC_VECTOR);
4101         } else if (!(banks[1] & MCI_STATUS_VAL)
4102                    || !(banks[1] & MCI_STATUS_UC)) {
4103                 if (banks[1] & MCI_STATUS_VAL)
4104                         mce->status |= MCI_STATUS_OVER;
4105                 banks[2] = mce->addr;
4106                 banks[3] = mce->misc;
4107                 banks[1] = mce->status;
4108         } else
4109                 banks[1] |= MCI_STATUS_OVER;
4110         return 0;
4111 }
4112
4113 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
4114                                                struct kvm_vcpu_events *events)
4115 {
4116         process_nmi(vcpu);
4117
4118         /*
4119          * In guest mode, payload delivery should be deferred,
4120          * so that the L1 hypervisor can intercept #PF before
4121          * CR2 is modified (or intercept #DB before DR6 is
4122          * modified under nVMX). Unless the per-VM capability,
4123          * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
4124          * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
4125          * opportunistically defer the exception payload, deliver it if the
4126          * capability hasn't been requested before processing a
4127          * KVM_GET_VCPU_EVENTS.
4128          */
4129         if (!vcpu->kvm->arch.exception_payload_enabled &&
4130             vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
4131                 kvm_deliver_exception_payload(vcpu);
4132
4133         /*
4134          * The API doesn't provide the instruction length for software
4135          * exceptions, so don't report them. As long as the guest RIP
4136          * isn't advanced, we should expect to encounter the exception
4137          * again.
4138          */
4139         if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
4140                 events->exception.injected = 0;
4141                 events->exception.pending = 0;
4142         } else {
4143                 events->exception.injected = vcpu->arch.exception.injected;
4144                 events->exception.pending = vcpu->arch.exception.pending;
4145                 /*
4146                  * For ABI compatibility, deliberately conflate
4147                  * pending and injected exceptions when
4148                  * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
4149                  */
4150                 if (!vcpu->kvm->arch.exception_payload_enabled)
4151                         events->exception.injected |=
4152                                 vcpu->arch.exception.pending;
4153         }
4154         events->exception.nr = vcpu->arch.exception.nr;
4155         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
4156         events->exception.error_code = vcpu->arch.exception.error_code;
4157         events->exception_has_payload = vcpu->arch.exception.has_payload;
4158         events->exception_payload = vcpu->arch.exception.payload;
4159
4160         events->interrupt.injected =
4161                 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
4162         events->interrupt.nr = vcpu->arch.interrupt.nr;
4163         events->interrupt.soft = 0;
4164         events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
4165
4166         events->nmi.injected = vcpu->arch.nmi_injected;
4167         events->nmi.pending = vcpu->arch.nmi_pending != 0;
4168         events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu);
4169         events->nmi.pad = 0;
4170
4171         events->sipi_vector = 0; /* never valid when reporting to user space */
4172
4173         events->smi.smm = is_smm(vcpu);
4174         events->smi.pending = vcpu->arch.smi_pending;
4175         events->smi.smm_inside_nmi =
4176                 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
4177         events->smi.latched_init = kvm_lapic_latched_init(vcpu);
4178
4179         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
4180                          | KVM_VCPUEVENT_VALID_SHADOW
4181                          | KVM_VCPUEVENT_VALID_SMM);
4182         if (vcpu->kvm->arch.exception_payload_enabled)
4183                 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4184
4185         memset(&events->reserved, 0, sizeof(events->reserved));
4186 }
4187
4188 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
4189
4190 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4191                                               struct kvm_vcpu_events *events)
4192 {
4193         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4194                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4195                               | KVM_VCPUEVENT_VALID_SHADOW
4196                               | KVM_VCPUEVENT_VALID_SMM
4197                               | KVM_VCPUEVENT_VALID_PAYLOAD))
4198                 return -EINVAL;
4199
4200         if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4201                 if (!vcpu->kvm->arch.exception_payload_enabled)
4202                         return -EINVAL;
4203                 if (events->exception.pending)
4204                         events->exception.injected = 0;
4205                 else
4206                         events->exception_has_payload = 0;
4207         } else {
4208                 events->exception.pending = 0;
4209                 events->exception_has_payload = 0;
4210         }
4211
4212         if ((events->exception.injected || events->exception.pending) &&
4213             (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4214                 return -EINVAL;
4215
4216         /* INITs are latched while in SMM */
4217         if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4218             (events->smi.smm || events->smi.pending) &&
4219             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4220                 return -EINVAL;
4221
4222         process_nmi(vcpu);
4223         vcpu->arch.exception.injected = events->exception.injected;
4224         vcpu->arch.exception.pending = events->exception.pending;
4225         vcpu->arch.exception.nr = events->exception.nr;
4226         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4227         vcpu->arch.exception.error_code = events->exception.error_code;
4228         vcpu->arch.exception.has_payload = events->exception_has_payload;
4229         vcpu->arch.exception.payload = events->exception_payload;
4230
4231         vcpu->arch.interrupt.injected = events->interrupt.injected;
4232         vcpu->arch.interrupt.nr = events->interrupt.nr;
4233         vcpu->arch.interrupt.soft = events->interrupt.soft;
4234         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4235                 kvm_x86_ops.set_interrupt_shadow(vcpu,
4236                                                   events->interrupt.shadow);
4237
4238         vcpu->arch.nmi_injected = events->nmi.injected;
4239         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4240                 vcpu->arch.nmi_pending = events->nmi.pending;
4241         kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked);
4242
4243         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4244             lapic_in_kernel(vcpu))
4245                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4246
4247         if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4248                 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4249                         if (events->smi.smm)
4250                                 vcpu->arch.hflags |= HF_SMM_MASK;
4251                         else
4252                                 vcpu->arch.hflags &= ~HF_SMM_MASK;
4253                         kvm_smm_changed(vcpu);
4254                 }
4255
4256                 vcpu->arch.smi_pending = events->smi.pending;
4257
4258                 if (events->smi.smm) {
4259                         if (events->smi.smm_inside_nmi)
4260                                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4261                         else
4262                                 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4263                 }
4264
4265                 if (lapic_in_kernel(vcpu)) {
4266                         if (events->smi.latched_init)
4267                                 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4268                         else
4269                                 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4270                 }
4271         }
4272
4273         kvm_make_request(KVM_REQ_EVENT, vcpu);
4274
4275         return 0;
4276 }
4277
4278 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4279                                              struct kvm_debugregs *dbgregs)
4280 {
4281         unsigned long val;
4282
4283         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4284         kvm_get_dr(vcpu, 6, &val);
4285         dbgregs->dr6 = val;
4286         dbgregs->dr7 = vcpu->arch.dr7;
4287         dbgregs->flags = 0;
4288         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4289 }
4290
4291 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4292                                             struct kvm_debugregs *dbgregs)
4293 {
4294         if (dbgregs->flags)
4295                 return -EINVAL;
4296
4297         if (dbgregs->dr6 & ~0xffffffffull)
4298                 return -EINVAL;
4299         if (dbgregs->dr7 & ~0xffffffffull)
4300                 return -EINVAL;
4301
4302         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4303         kvm_update_dr0123(vcpu);
4304         vcpu->arch.dr6 = dbgregs->dr6;
4305         vcpu->arch.dr7 = dbgregs->dr7;
4306         kvm_update_dr7(vcpu);
4307
4308         return 0;
4309 }
4310
4311 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4312
4313 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4314 {
4315         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4316         u64 xstate_bv = xsave->header.xfeatures;
4317         u64 valid;
4318
4319         /*
4320          * Copy legacy XSAVE area, to avoid complications with CPUID
4321          * leaves 0 and 1 in the loop below.
4322          */
4323         memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4324
4325         /* Set XSTATE_BV */
4326         xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4327         *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4328
4329         /*
4330          * Copy each region from the possibly compacted offset to the
4331          * non-compacted offset.
4332          */
4333         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4334         while (valid) {
4335                 u64 xfeature_mask = valid & -valid;
4336                 int xfeature_nr = fls64(xfeature_mask) - 1;
4337                 void *src = get_xsave_addr(xsave, xfeature_nr);
4338
4339                 if (src) {
4340                         u32 size, offset, ecx, edx;
4341                         cpuid_count(XSTATE_CPUID, xfeature_nr,
4342                                     &size, &offset, &ecx, &edx);
4343                         if (xfeature_nr == XFEATURE_PKRU)
4344                                 memcpy(dest + offset, &vcpu->arch.pkru,
4345                                        sizeof(vcpu->arch.pkru));
4346                         else
4347                                 memcpy(dest + offset, src, size);
4348
4349                 }
4350
4351                 valid -= xfeature_mask;
4352         }
4353 }
4354
4355 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4356 {
4357         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4358         u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4359         u64 valid;
4360
4361         /*
4362          * Copy legacy XSAVE area, to avoid complications with CPUID
4363          * leaves 0 and 1 in the loop below.
4364          */
4365         memcpy(xsave, src, XSAVE_HDR_OFFSET);
4366
4367         /* Set XSTATE_BV and possibly XCOMP_BV.  */
4368         xsave->header.xfeatures = xstate_bv;
4369         if (boot_cpu_has(X86_FEATURE_XSAVES))
4370                 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4371
4372         /*
4373          * Copy each region from the non-compacted offset to the
4374          * possibly compacted offset.
4375          */
4376         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4377         while (valid) {
4378                 u64 xfeature_mask = valid & -valid;
4379                 int xfeature_nr = fls64(xfeature_mask) - 1;
4380                 void *dest = get_xsave_addr(xsave, xfeature_nr);
4381
4382                 if (dest) {
4383                         u32 size, offset, ecx, edx;
4384                         cpuid_count(XSTATE_CPUID, xfeature_nr,
4385                                     &size, &offset, &ecx, &edx);
4386                         if (xfeature_nr == XFEATURE_PKRU)
4387                                 memcpy(&vcpu->arch.pkru, src + offset,
4388                                        sizeof(vcpu->arch.pkru));
4389                         else
4390                                 memcpy(dest, src + offset, size);
4391                 }
4392
4393                 valid -= xfeature_mask;
4394         }
4395 }
4396
4397 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4398                                          struct kvm_xsave *guest_xsave)
4399 {
4400         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4401                 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4402                 fill_xsave((u8 *) guest_xsave->region, vcpu);
4403         } else {
4404                 memcpy(guest_xsave->region,
4405                         &vcpu->arch.guest_fpu->state.fxsave,
4406                         sizeof(struct fxregs_state));
4407                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4408                         XFEATURE_MASK_FPSSE;
4409         }
4410 }
4411
4412 #define XSAVE_MXCSR_OFFSET 24
4413
4414 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4415                                         struct kvm_xsave *guest_xsave)
4416 {
4417         u64 xstate_bv =
4418                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4419         u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4420
4421         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4422                 /*
4423                  * Here we allow setting states that are not present in
4424                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
4425                  * with old userspace.
4426                  */
4427                 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4428                         return -EINVAL;
4429                 load_xsave(vcpu, (u8 *)guest_xsave->region);
4430         } else {
4431                 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4432                         mxcsr & ~mxcsr_feature_mask)
4433                         return -EINVAL;
4434                 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4435                         guest_xsave->region, sizeof(struct fxregs_state));
4436         }
4437         return 0;
4438 }
4439
4440 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4441                                         struct kvm_xcrs *guest_xcrs)
4442 {
4443         if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4444                 guest_xcrs->nr_xcrs = 0;
4445                 return;
4446         }
4447
4448         guest_xcrs->nr_xcrs = 1;
4449         guest_xcrs->flags = 0;
4450         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4451         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4452 }
4453
4454 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4455                                        struct kvm_xcrs *guest_xcrs)
4456 {
4457         int i, r = 0;
4458
4459         if (!boot_cpu_has(X86_FEATURE_XSAVE))
4460                 return -EINVAL;
4461
4462         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4463                 return -EINVAL;
4464
4465         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4466                 /* Only support XCR0 currently */
4467                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4468                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4469                                 guest_xcrs->xcrs[i].value);
4470                         break;
4471                 }
4472         if (r)
4473                 r = -EINVAL;
4474         return r;
4475 }
4476
4477 /*
4478  * kvm_set_guest_paused() indicates to the guest kernel that it has been
4479  * stopped by the hypervisor.  This function will be called from the host only.
4480  * EINVAL is returned when the host attempts to set the flag for a guest that
4481  * does not support pv clocks.
4482  */
4483 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4484 {
4485         if (!vcpu->arch.pv_time_enabled)
4486                 return -EINVAL;
4487         vcpu->arch.pvclock_set_guest_stopped_request = true;
4488         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4489         return 0;
4490 }
4491
4492 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4493                                      struct kvm_enable_cap *cap)
4494 {
4495         int r;
4496         uint16_t vmcs_version;
4497         void __user *user_ptr;
4498
4499         if (cap->flags)
4500                 return -EINVAL;
4501
4502         switch (cap->cap) {
4503         case KVM_CAP_HYPERV_SYNIC2:
4504                 if (cap->args[0])
4505                         return -EINVAL;
4506                 fallthrough;
4507
4508         case KVM_CAP_HYPERV_SYNIC:
4509                 if (!irqchip_in_kernel(vcpu->kvm))
4510                         return -EINVAL;
4511                 return kvm_hv_activate_synic(vcpu, cap->cap ==
4512                                              KVM_CAP_HYPERV_SYNIC2);
4513         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4514                 if (!kvm_x86_ops.nested_ops->enable_evmcs)
4515                         return -ENOTTY;
4516                 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
4517                 if (!r) {
4518                         user_ptr = (void __user *)(uintptr_t)cap->args[0];
4519                         if (copy_to_user(user_ptr, &vmcs_version,
4520                                          sizeof(vmcs_version)))
4521                                 r = -EFAULT;
4522                 }
4523                 return r;
4524         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4525                 if (!kvm_x86_ops.enable_direct_tlbflush)
4526                         return -ENOTTY;
4527
4528                 return kvm_x86_ops.enable_direct_tlbflush(vcpu);
4529
4530         default:
4531                 return -EINVAL;
4532         }
4533 }
4534
4535 long kvm_arch_vcpu_ioctl(struct file *filp,
4536                          unsigned int ioctl, unsigned long arg)
4537 {
4538         struct kvm_vcpu *vcpu = filp->private_data;
4539         void __user *argp = (void __user *)arg;
4540         int r;
4541         union {
4542                 struct kvm_lapic_state *lapic;
4543                 struct kvm_xsave *xsave;
4544                 struct kvm_xcrs *xcrs;
4545                 void *buffer;
4546         } u;
4547
4548         vcpu_load(vcpu);
4549
4550         u.buffer = NULL;
4551         switch (ioctl) {
4552         case KVM_GET_LAPIC: {
4553                 r = -EINVAL;
4554                 if (!lapic_in_kernel(vcpu))
4555                         goto out;
4556                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4557                                 GFP_KERNEL_ACCOUNT);
4558
4559                 r = -ENOMEM;
4560                 if (!u.lapic)
4561                         goto out;
4562                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4563                 if (r)
4564                         goto out;
4565                 r = -EFAULT;
4566                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4567                         goto out;
4568                 r = 0;
4569                 break;
4570         }
4571         case KVM_SET_LAPIC: {
4572                 r = -EINVAL;
4573                 if (!lapic_in_kernel(vcpu))
4574                         goto out;
4575                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4576                 if (IS_ERR(u.lapic)) {
4577                         r = PTR_ERR(u.lapic);
4578                         goto out_nofree;
4579                 }
4580
4581                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4582                 break;
4583         }
4584         case KVM_INTERRUPT: {
4585                 struct kvm_interrupt irq;
4586
4587                 r = -EFAULT;
4588                 if (copy_from_user(&irq, argp, sizeof(irq)))
4589                         goto out;
4590                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4591                 break;
4592         }
4593         case KVM_NMI: {
4594                 r = kvm_vcpu_ioctl_nmi(vcpu);
4595                 break;
4596         }
4597         case KVM_SMI: {
4598                 r = kvm_vcpu_ioctl_smi(vcpu);
4599                 break;
4600         }
4601         case KVM_SET_CPUID: {
4602                 struct kvm_cpuid __user *cpuid_arg = argp;
4603                 struct kvm_cpuid cpuid;
4604
4605                 r = -EFAULT;
4606                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4607                         goto out;
4608                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4609                 break;
4610         }
4611         case KVM_SET_CPUID2: {
4612                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4613                 struct kvm_cpuid2 cpuid;
4614
4615                 r = -EFAULT;
4616                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4617                         goto out;
4618                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4619                                               cpuid_arg->entries);
4620                 break;
4621         }
4622         case KVM_GET_CPUID2: {
4623                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4624                 struct kvm_cpuid2 cpuid;
4625
4626                 r = -EFAULT;
4627                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4628                         goto out;
4629                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4630                                               cpuid_arg->entries);
4631                 if (r)
4632                         goto out;
4633                 r = -EFAULT;
4634                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4635                         goto out;
4636                 r = 0;
4637                 break;
4638         }
4639         case KVM_GET_MSRS: {
4640                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4641                 r = msr_io(vcpu, argp, do_get_msr, 1);
4642                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4643                 break;
4644         }
4645         case KVM_SET_MSRS: {
4646                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4647                 r = msr_io(vcpu, argp, do_set_msr, 0);
4648                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4649                 break;
4650         }
4651         case KVM_TPR_ACCESS_REPORTING: {
4652                 struct kvm_tpr_access_ctl tac;
4653
4654                 r = -EFAULT;
4655                 if (copy_from_user(&tac, argp, sizeof(tac)))
4656                         goto out;
4657                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4658                 if (r)
4659                         goto out;
4660                 r = -EFAULT;
4661                 if (copy_to_user(argp, &tac, sizeof(tac)))
4662                         goto out;
4663                 r = 0;
4664                 break;
4665         };
4666         case KVM_SET_VAPIC_ADDR: {
4667                 struct kvm_vapic_addr va;
4668                 int idx;
4669
4670                 r = -EINVAL;
4671                 if (!lapic_in_kernel(vcpu))
4672                         goto out;
4673                 r = -EFAULT;
4674                 if (copy_from_user(&va, argp, sizeof(va)))
4675                         goto out;
4676                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4677                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4678                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4679                 break;
4680         }
4681         case KVM_X86_SETUP_MCE: {
4682                 u64 mcg_cap;
4683
4684                 r = -EFAULT;
4685                 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4686                         goto out;
4687                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4688                 break;
4689         }
4690         case KVM_X86_SET_MCE: {
4691                 struct kvm_x86_mce mce;
4692
4693                 r = -EFAULT;
4694                 if (copy_from_user(&mce, argp, sizeof(mce)))
4695                         goto out;
4696                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4697                 break;
4698         }
4699         case KVM_GET_VCPU_EVENTS: {
4700                 struct kvm_vcpu_events events;
4701
4702                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4703
4704                 r = -EFAULT;
4705                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4706                         break;
4707                 r = 0;
4708                 break;
4709         }
4710         case KVM_SET_VCPU_EVENTS: {
4711                 struct kvm_vcpu_events events;
4712
4713                 r = -EFAULT;
4714                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4715                         break;
4716
4717                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4718                 break;
4719         }
4720         case KVM_GET_DEBUGREGS: {
4721                 struct kvm_debugregs dbgregs;
4722
4723                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4724
4725                 r = -EFAULT;
4726                 if (copy_to_user(argp, &dbgregs,
4727                                  sizeof(struct kvm_debugregs)))
4728                         break;
4729                 r = 0;
4730                 break;
4731         }
4732         case KVM_SET_DEBUGREGS: {
4733                 struct kvm_debugregs dbgregs;
4734
4735                 r = -EFAULT;
4736                 if (copy_from_user(&dbgregs, argp,
4737                                    sizeof(struct kvm_debugregs)))
4738                         break;
4739
4740                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4741                 break;
4742         }
4743         case KVM_GET_XSAVE: {
4744                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4745                 r = -ENOMEM;
4746                 if (!u.xsave)
4747                         break;
4748
4749                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4750
4751                 r = -EFAULT;
4752                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4753                         break;
4754                 r = 0;
4755                 break;
4756         }
4757         case KVM_SET_XSAVE: {
4758                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4759                 if (IS_ERR(u.xsave)) {
4760                         r = PTR_ERR(u.xsave);
4761                         goto out_nofree;
4762                 }
4763
4764                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4765                 break;
4766         }
4767         case KVM_GET_XCRS: {
4768                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4769                 r = -ENOMEM;
4770                 if (!u.xcrs)
4771                         break;
4772
4773                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4774
4775                 r = -EFAULT;
4776                 if (copy_to_user(argp, u.xcrs,
4777                                  sizeof(struct kvm_xcrs)))
4778                         break;
4779                 r = 0;
4780                 break;
4781         }
4782         case KVM_SET_XCRS: {
4783                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4784                 if (IS_ERR(u.xcrs)) {
4785                         r = PTR_ERR(u.xcrs);
4786                         goto out_nofree;
4787                 }
4788
4789                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4790                 break;
4791         }
4792         case KVM_SET_TSC_KHZ: {
4793                 u32 user_tsc_khz;
4794
4795                 r = -EINVAL;
4796                 user_tsc_khz = (u32)arg;
4797
4798                 if (kvm_has_tsc_control &&
4799                     user_tsc_khz >= kvm_max_guest_tsc_khz)
4800                         goto out;
4801
4802                 if (user_tsc_khz == 0)
4803                         user_tsc_khz = tsc_khz;
4804
4805                 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4806                         r = 0;
4807
4808                 goto out;
4809         }
4810         case KVM_GET_TSC_KHZ: {
4811                 r = vcpu->arch.virtual_tsc_khz;
4812                 goto out;
4813         }
4814         case KVM_KVMCLOCK_CTRL: {
4815                 r = kvm_set_guest_paused(vcpu);
4816                 goto out;
4817         }
4818         case KVM_ENABLE_CAP: {
4819                 struct kvm_enable_cap cap;
4820
4821                 r = -EFAULT;
4822                 if (copy_from_user(&cap, argp, sizeof(cap)))
4823                         goto out;
4824                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4825                 break;
4826         }
4827         case KVM_GET_NESTED_STATE: {
4828                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4829                 u32 user_data_size;
4830
4831                 r = -EINVAL;
4832                 if (!kvm_x86_ops.nested_ops->get_state)
4833                         break;
4834
4835                 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4836                 r = -EFAULT;
4837                 if (get_user(user_data_size, &user_kvm_nested_state->size))
4838                         break;
4839
4840                 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
4841                                                      user_data_size);
4842                 if (r < 0)
4843                         break;
4844
4845                 if (r > user_data_size) {
4846                         if (put_user(r, &user_kvm_nested_state->size))
4847                                 r = -EFAULT;
4848                         else
4849                                 r = -E2BIG;
4850                         break;
4851                 }
4852
4853                 r = 0;
4854                 break;
4855         }
4856         case KVM_SET_NESTED_STATE: {
4857                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4858                 struct kvm_nested_state kvm_state;
4859                 int idx;
4860
4861                 r = -EINVAL;
4862                 if (!kvm_x86_ops.nested_ops->set_state)
4863                         break;
4864
4865                 r = -EFAULT;
4866                 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4867                         break;
4868
4869                 r = -EINVAL;
4870                 if (kvm_state.size < sizeof(kvm_state))
4871                         break;
4872
4873                 if (kvm_state.flags &
4874                     ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4875                       | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
4876                       | KVM_STATE_NESTED_GIF_SET))
4877                         break;
4878
4879                 /* nested_run_pending implies guest_mode.  */
4880                 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4881                     && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4882                         break;
4883
4884                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4885                 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
4886                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4887                 break;
4888         }
4889         case KVM_GET_SUPPORTED_HV_CPUID: {
4890                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4891                 struct kvm_cpuid2 cpuid;
4892
4893                 r = -EFAULT;
4894                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4895                         goto out;
4896
4897                 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4898                                                 cpuid_arg->entries);
4899                 if (r)
4900                         goto out;
4901
4902                 r = -EFAULT;
4903                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4904                         goto out;
4905                 r = 0;
4906                 break;
4907         }
4908         default:
4909                 r = -EINVAL;
4910         }
4911 out:
4912         kfree(u.buffer);
4913 out_nofree:
4914         vcpu_put(vcpu);
4915         return r;
4916 }
4917
4918 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4919 {
4920         return VM_FAULT_SIGBUS;
4921 }
4922
4923 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4924 {
4925         int ret;
4926
4927         if (addr > (unsigned int)(-3 * PAGE_SIZE))
4928                 return -EINVAL;
4929         ret = kvm_x86_ops.set_tss_addr(kvm, addr);
4930         return ret;
4931 }
4932
4933 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4934                                               u64 ident_addr)
4935 {
4936         return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr);
4937 }
4938
4939 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4940                                          unsigned long kvm_nr_mmu_pages)
4941 {
4942         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4943                 return -EINVAL;
4944
4945         mutex_lock(&kvm->slots_lock);
4946
4947         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4948         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4949
4950         mutex_unlock(&kvm->slots_lock);
4951         return 0;
4952 }
4953
4954 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4955 {
4956         return kvm->arch.n_max_mmu_pages;
4957 }
4958
4959 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4960 {
4961         struct kvm_pic *pic = kvm->arch.vpic;
4962         int r;
4963
4964         r = 0;
4965         switch (chip->chip_id) {
4966         case KVM_IRQCHIP_PIC_MASTER:
4967                 memcpy(&chip->chip.pic, &pic->pics[0],
4968                         sizeof(struct kvm_pic_state));
4969                 break;
4970         case KVM_IRQCHIP_PIC_SLAVE:
4971                 memcpy(&chip->chip.pic, &pic->pics[1],
4972                         sizeof(struct kvm_pic_state));
4973                 break;
4974         case KVM_IRQCHIP_IOAPIC:
4975                 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4976                 break;
4977         default:
4978                 r = -EINVAL;
4979                 break;
4980         }
4981         return r;
4982 }
4983
4984 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4985 {
4986         struct kvm_pic *pic = kvm->arch.vpic;
4987         int r;
4988
4989         r = 0;
4990         switch (chip->chip_id) {
4991         case KVM_IRQCHIP_PIC_MASTER:
4992                 spin_lock(&pic->lock);
4993                 memcpy(&pic->pics[0], &chip->chip.pic,
4994                         sizeof(struct kvm_pic_state));
4995                 spin_unlock(&pic->lock);
4996                 break;
4997         case KVM_IRQCHIP_PIC_SLAVE:
4998                 spin_lock(&pic->lock);
4999                 memcpy(&pic->pics[1], &chip->chip.pic,
5000                         sizeof(struct kvm_pic_state));
5001                 spin_unlock(&pic->lock);
5002                 break;
5003         case KVM_IRQCHIP_IOAPIC:
5004                 kvm_set_ioapic(kvm, &chip->chip.ioapic);
5005                 break;
5006         default:
5007                 r = -EINVAL;
5008                 break;
5009         }
5010         kvm_pic_update_irq(pic);
5011         return r;
5012 }
5013
5014 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5015 {
5016         struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
5017
5018         BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
5019
5020         mutex_lock(&kps->lock);
5021         memcpy(ps, &kps->channels, sizeof(*ps));
5022         mutex_unlock(&kps->lock);
5023         return 0;
5024 }
5025
5026 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5027 {
5028         int i;
5029         struct kvm_pit *pit = kvm->arch.vpit;
5030
5031         mutex_lock(&pit->pit_state.lock);
5032         memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
5033         for (i = 0; i < 3; i++)
5034                 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
5035         mutex_unlock(&pit->pit_state.lock);
5036         return 0;
5037 }
5038
5039 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5040 {
5041         mutex_lock(&kvm->arch.vpit->pit_state.lock);
5042         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
5043                 sizeof(ps->channels));
5044         ps->flags = kvm->arch.vpit->pit_state.flags;
5045         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
5046         memset(&ps->reserved, 0, sizeof(ps->reserved));
5047         return 0;
5048 }
5049
5050 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5051 {
5052         int start = 0;
5053         int i;
5054         u32 prev_legacy, cur_legacy;
5055         struct kvm_pit *pit = kvm->arch.vpit;
5056
5057         mutex_lock(&pit->pit_state.lock);
5058         prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
5059         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
5060         if (!prev_legacy && cur_legacy)
5061                 start = 1;
5062         memcpy(&pit->pit_state.channels, &ps->channels,
5063                sizeof(pit->pit_state.channels));
5064         pit->pit_state.flags = ps->flags;
5065         for (i = 0; i < 3; i++)
5066                 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
5067                                    start && i == 0);
5068         mutex_unlock(&pit->pit_state.lock);
5069         return 0;
5070 }
5071
5072 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
5073                                  struct kvm_reinject_control *control)
5074 {
5075         struct kvm_pit *pit = kvm->arch.vpit;
5076
5077         /* pit->pit_state.lock was overloaded to prevent userspace from getting
5078          * an inconsistent state after running multiple KVM_REINJECT_CONTROL
5079          * ioctls in parallel.  Use a separate lock if that ioctl isn't rare.
5080          */
5081         mutex_lock(&pit->pit_state.lock);
5082         kvm_pit_set_reinject(pit, control->pit_reinject);
5083         mutex_unlock(&pit->pit_state.lock);
5084
5085         return 0;
5086 }
5087
5088 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
5089 {
5090         /*
5091          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
5092          */
5093         if (kvm_x86_ops.flush_log_dirty)
5094                 kvm_x86_ops.flush_log_dirty(kvm);
5095 }
5096
5097 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
5098                         bool line_status)
5099 {
5100         if (!irqchip_in_kernel(kvm))
5101                 return -ENXIO;
5102
5103         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
5104                                         irq_event->irq, irq_event->level,
5105                                         line_status);
5106         return 0;
5107 }
5108
5109 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
5110                             struct kvm_enable_cap *cap)
5111 {
5112         int r;
5113
5114         if (cap->flags)
5115                 return -EINVAL;
5116
5117         switch (cap->cap) {
5118         case KVM_CAP_DISABLE_QUIRKS:
5119                 kvm->arch.disabled_quirks = cap->args[0];
5120                 r = 0;
5121                 break;
5122         case KVM_CAP_SPLIT_IRQCHIP: {
5123                 mutex_lock(&kvm->lock);
5124                 r = -EINVAL;
5125                 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
5126                         goto split_irqchip_unlock;
5127                 r = -EEXIST;
5128                 if (irqchip_in_kernel(kvm))
5129                         goto split_irqchip_unlock;
5130                 if (kvm->created_vcpus)
5131                         goto split_irqchip_unlock;
5132                 r = kvm_setup_empty_irq_routing(kvm);
5133                 if (r)
5134                         goto split_irqchip_unlock;
5135                 /* Pairs with irqchip_in_kernel. */
5136                 smp_wmb();
5137                 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
5138                 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
5139                 r = 0;
5140 split_irqchip_unlock:
5141                 mutex_unlock(&kvm->lock);
5142                 break;
5143         }
5144         case KVM_CAP_X2APIC_API:
5145                 r = -EINVAL;
5146                 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
5147                         break;
5148
5149                 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
5150                         kvm->arch.x2apic_format = true;
5151                 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
5152                         kvm->arch.x2apic_broadcast_quirk_disabled = true;
5153
5154                 r = 0;
5155                 break;
5156         case KVM_CAP_X86_DISABLE_EXITS:
5157                 r = -EINVAL;
5158                 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
5159                         break;
5160
5161                 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
5162                         kvm_can_mwait_in_guest())
5163                         kvm->arch.mwait_in_guest = true;
5164                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
5165                         kvm->arch.hlt_in_guest = true;
5166                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
5167                         kvm->arch.pause_in_guest = true;
5168                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
5169                         kvm->arch.cstate_in_guest = true;
5170                 r = 0;
5171                 break;
5172         case KVM_CAP_MSR_PLATFORM_INFO:
5173                 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
5174                 r = 0;
5175                 break;
5176         case KVM_CAP_EXCEPTION_PAYLOAD:
5177                 kvm->arch.exception_payload_enabled = cap->args[0];
5178                 r = 0;
5179                 break;
5180         case KVM_CAP_X86_USER_SPACE_MSR:
5181                 kvm->arch.user_space_msr_mask = cap->args[0];
5182                 r = 0;
5183                 break;
5184         default:
5185                 r = -EINVAL;
5186                 break;
5187         }
5188         return r;
5189 }
5190
5191 static void kvm_clear_msr_filter(struct kvm *kvm)
5192 {
5193         u32 i;
5194         u32 count = kvm->arch.msr_filter.count;
5195         struct msr_bitmap_range ranges[16];
5196
5197         mutex_lock(&kvm->lock);
5198         kvm->arch.msr_filter.count = 0;
5199         memcpy(ranges, kvm->arch.msr_filter.ranges, count * sizeof(ranges[0]));
5200         mutex_unlock(&kvm->lock);
5201         synchronize_srcu(&kvm->srcu);
5202
5203         for (i = 0; i < count; i++)
5204                 kfree(ranges[i].bitmap);
5205 }
5206
5207 static int kvm_add_msr_filter(struct kvm *kvm, struct kvm_msr_filter_range *user_range)
5208 {
5209         struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
5210         struct msr_bitmap_range range;
5211         unsigned long *bitmap = NULL;
5212         size_t bitmap_size;
5213         int r;
5214
5215         if (!user_range->nmsrs)
5216                 return 0;
5217
5218         bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
5219         if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
5220                 return -EINVAL;
5221
5222         bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
5223         if (IS_ERR(bitmap))
5224                 return PTR_ERR(bitmap);
5225
5226         range = (struct msr_bitmap_range) {
5227                 .flags = user_range->flags,
5228                 .base = user_range->base,
5229                 .nmsrs = user_range->nmsrs,
5230                 .bitmap = bitmap,
5231         };
5232
5233         if (range.flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) {
5234                 r = -EINVAL;
5235                 goto err;
5236         }
5237
5238         if (!range.flags) {
5239                 r = -EINVAL;
5240                 goto err;
5241         }
5242
5243         /* Everything ok, add this range identifier to our global pool */
5244         ranges[kvm->arch.msr_filter.count] = range;
5245         /* Make sure we filled the array before we tell anyone to walk it */
5246         smp_wmb();
5247         kvm->arch.msr_filter.count++;
5248
5249         return 0;
5250 err:
5251         kfree(bitmap);
5252         return r;
5253 }
5254
5255 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp)
5256 {
5257         struct kvm_msr_filter __user *user_msr_filter = argp;
5258         struct kvm_msr_filter filter;
5259         bool default_allow;
5260         int r = 0;
5261         bool empty = true;
5262         u32 i;
5263
5264         if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
5265                 return -EFAULT;
5266
5267         for (i = 0; i < ARRAY_SIZE(filter.ranges); i++)
5268                 empty &= !filter.ranges[i].nmsrs;
5269
5270         default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY);
5271         if (empty && !default_allow)
5272                 return -EINVAL;
5273
5274         kvm_clear_msr_filter(kvm);
5275
5276         kvm->arch.msr_filter.default_allow = default_allow;
5277
5278         /*
5279          * Protect from concurrent calls to this function that could trigger
5280          * a TOCTOU violation on kvm->arch.msr_filter.count.
5281          */
5282         mutex_lock(&kvm->lock);
5283         for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
5284                 r = kvm_add_msr_filter(kvm, &filter.ranges[i]);
5285                 if (r)
5286                         break;
5287         }
5288
5289         kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
5290         mutex_unlock(&kvm->lock);
5291
5292         return r;
5293 }
5294
5295 long kvm_arch_vm_ioctl(struct file *filp,
5296                        unsigned int ioctl, unsigned long arg)
5297 {
5298         struct kvm *kvm = filp->private_data;
5299         void __user *argp = (void __user *)arg;
5300         int r = -ENOTTY;
5301         /*
5302          * This union makes it completely explicit to gcc-3.x
5303          * that these two variables' stack usage should be
5304          * combined, not added together.
5305          */
5306         union {
5307                 struct kvm_pit_state ps;
5308                 struct kvm_pit_state2 ps2;
5309                 struct kvm_pit_config pit_config;
5310         } u;
5311
5312         switch (ioctl) {
5313         case KVM_SET_TSS_ADDR:
5314                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
5315                 break;
5316         case KVM_SET_IDENTITY_MAP_ADDR: {
5317                 u64 ident_addr;
5318
5319                 mutex_lock(&kvm->lock);
5320                 r = -EINVAL;
5321                 if (kvm->created_vcpus)
5322                         goto set_identity_unlock;
5323                 r = -EFAULT;
5324                 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
5325                         goto set_identity_unlock;
5326                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
5327 set_identity_unlock:
5328                 mutex_unlock(&kvm->lock);
5329                 break;
5330         }
5331         case KVM_SET_NR_MMU_PAGES:
5332                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
5333                 break;
5334         case KVM_GET_NR_MMU_PAGES:
5335                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
5336                 break;
5337         case KVM_CREATE_IRQCHIP: {
5338                 mutex_lock(&kvm->lock);
5339
5340                 r = -EEXIST;
5341                 if (irqchip_in_kernel(kvm))
5342                         goto create_irqchip_unlock;
5343
5344                 r = -EINVAL;
5345                 if (kvm->created_vcpus)
5346                         goto create_irqchip_unlock;
5347
5348                 r = kvm_pic_init(kvm);
5349                 if (r)
5350                         goto create_irqchip_unlock;
5351
5352                 r = kvm_ioapic_init(kvm);
5353                 if (r) {
5354                         kvm_pic_destroy(kvm);
5355                         goto create_irqchip_unlock;
5356                 }
5357
5358                 r = kvm_setup_default_irq_routing(kvm);
5359                 if (r) {
5360                         kvm_ioapic_destroy(kvm);
5361                         kvm_pic_destroy(kvm);
5362                         goto create_irqchip_unlock;
5363                 }
5364                 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
5365                 smp_wmb();
5366                 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
5367         create_irqchip_unlock:
5368                 mutex_unlock(&kvm->lock);
5369                 break;
5370         }
5371         case KVM_CREATE_PIT:
5372                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
5373                 goto create_pit;
5374         case KVM_CREATE_PIT2:
5375                 r = -EFAULT;
5376                 if (copy_from_user(&u.pit_config, argp,
5377                                    sizeof(struct kvm_pit_config)))
5378                         goto out;
5379         create_pit:
5380                 mutex_lock(&kvm->lock);
5381                 r = -EEXIST;
5382                 if (kvm->arch.vpit)
5383                         goto create_pit_unlock;
5384                 r = -ENOMEM;
5385                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5386                 if (kvm->arch.vpit)
5387                         r = 0;
5388         create_pit_unlock:
5389                 mutex_unlock(&kvm->lock);
5390                 break;
5391         case KVM_GET_IRQCHIP: {
5392                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5393                 struct kvm_irqchip *chip;
5394
5395                 chip = memdup_user(argp, sizeof(*chip));
5396                 if (IS_ERR(chip)) {
5397                         r = PTR_ERR(chip);
5398                         goto out;
5399                 }
5400
5401                 r = -ENXIO;
5402                 if (!irqchip_kernel(kvm))
5403                         goto get_irqchip_out;
5404                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5405                 if (r)
5406                         goto get_irqchip_out;
5407                 r = -EFAULT;
5408                 if (copy_to_user(argp, chip, sizeof(*chip)))
5409                         goto get_irqchip_out;
5410                 r = 0;
5411         get_irqchip_out:
5412                 kfree(chip);
5413                 break;
5414         }
5415         case KVM_SET_IRQCHIP: {
5416                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5417                 struct kvm_irqchip *chip;
5418
5419                 chip = memdup_user(argp, sizeof(*chip));
5420                 if (IS_ERR(chip)) {
5421                         r = PTR_ERR(chip);
5422                         goto out;
5423                 }
5424
5425                 r = -ENXIO;
5426                 if (!irqchip_kernel(kvm))
5427                         goto set_irqchip_out;
5428                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5429         set_irqchip_out:
5430                 kfree(chip);
5431                 break;
5432         }
5433         case KVM_GET_PIT: {
5434                 r = -EFAULT;
5435                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5436                         goto out;
5437                 r = -ENXIO;
5438                 if (!kvm->arch.vpit)
5439                         goto out;
5440                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5441                 if (r)
5442                         goto out;
5443                 r = -EFAULT;
5444                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5445                         goto out;
5446                 r = 0;
5447                 break;
5448         }
5449         case KVM_SET_PIT: {
5450                 r = -EFAULT;
5451                 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5452                         goto out;
5453                 mutex_lock(&kvm->lock);
5454                 r = -ENXIO;
5455                 if (!kvm->arch.vpit)
5456                         goto set_pit_out;
5457                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5458 set_pit_out:
5459                 mutex_unlock(&kvm->lock);
5460                 break;
5461         }
5462         case KVM_GET_PIT2: {
5463                 r = -ENXIO;
5464                 if (!kvm->arch.vpit)
5465                         goto out;
5466                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5467                 if (r)
5468                         goto out;
5469                 r = -EFAULT;
5470                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5471                         goto out;
5472                 r = 0;
5473                 break;
5474         }
5475         case KVM_SET_PIT2: {
5476                 r = -EFAULT;
5477                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5478                         goto out;
5479                 mutex_lock(&kvm->lock);
5480                 r = -ENXIO;
5481                 if (!kvm->arch.vpit)
5482                         goto set_pit2_out;
5483                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5484 set_pit2_out:
5485                 mutex_unlock(&kvm->lock);
5486                 break;
5487         }
5488         case KVM_REINJECT_CONTROL: {
5489                 struct kvm_reinject_control control;
5490                 r =  -EFAULT;
5491                 if (copy_from_user(&control, argp, sizeof(control)))
5492                         goto out;
5493                 r = -ENXIO;
5494                 if (!kvm->arch.vpit)
5495                         goto out;
5496                 r = kvm_vm_ioctl_reinject(kvm, &control);
5497                 break;
5498         }
5499         case KVM_SET_BOOT_CPU_ID:
5500                 r = 0;
5501                 mutex_lock(&kvm->lock);
5502                 if (kvm->created_vcpus)
5503                         r = -EBUSY;
5504                 else
5505                         kvm->arch.bsp_vcpu_id = arg;
5506                 mutex_unlock(&kvm->lock);
5507                 break;
5508         case KVM_XEN_HVM_CONFIG: {
5509                 struct kvm_xen_hvm_config xhc;
5510                 r = -EFAULT;
5511                 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5512                         goto out;
5513                 r = -EINVAL;
5514                 if (xhc.flags)
5515                         goto out;
5516                 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5517                 r = 0;
5518                 break;
5519         }
5520         case KVM_SET_CLOCK: {
5521                 struct kvm_clock_data user_ns;
5522                 u64 now_ns;
5523
5524                 r = -EFAULT;
5525                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5526                         goto out;
5527
5528                 r = -EINVAL;
5529                 if (user_ns.flags)
5530                         goto out;
5531
5532                 r = 0;
5533                 /*
5534                  * TODO: userspace has to take care of races with VCPU_RUN, so
5535                  * kvm_gen_update_masterclock() can be cut down to locked
5536                  * pvclock_update_vm_gtod_copy().
5537                  */
5538                 kvm_gen_update_masterclock(kvm);
5539                 now_ns = get_kvmclock_ns(kvm);
5540                 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5541                 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5542                 break;
5543         }
5544         case KVM_GET_CLOCK: {
5545                 struct kvm_clock_data user_ns;
5546                 u64 now_ns;
5547
5548                 now_ns = get_kvmclock_ns(kvm);
5549                 user_ns.clock = now_ns;
5550                 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5551                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5552
5553                 r = -EFAULT;
5554                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5555                         goto out;
5556                 r = 0;
5557                 break;
5558         }
5559         case KVM_MEMORY_ENCRYPT_OP: {
5560                 r = -ENOTTY;
5561                 if (kvm_x86_ops.mem_enc_op)
5562                         r = kvm_x86_ops.mem_enc_op(kvm, argp);
5563                 break;
5564         }
5565         case KVM_MEMORY_ENCRYPT_REG_REGION: {
5566                 struct kvm_enc_region region;
5567
5568                 r = -EFAULT;
5569                 if (copy_from_user(&region, argp, sizeof(region)))
5570                         goto out;
5571
5572                 r = -ENOTTY;
5573                 if (kvm_x86_ops.mem_enc_reg_region)
5574                         r = kvm_x86_ops.mem_enc_reg_region(kvm, &region);
5575                 break;
5576         }
5577         case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5578                 struct kvm_enc_region region;
5579
5580                 r = -EFAULT;
5581                 if (copy_from_user(&region, argp, sizeof(region)))
5582                         goto out;
5583
5584                 r = -ENOTTY;
5585                 if (kvm_x86_ops.mem_enc_unreg_region)
5586                         r = kvm_x86_ops.mem_enc_unreg_region(kvm, &region);
5587                 break;
5588         }
5589         case KVM_HYPERV_EVENTFD: {
5590                 struct kvm_hyperv_eventfd hvevfd;
5591
5592                 r = -EFAULT;
5593                 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5594                         goto out;
5595                 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5596                 break;
5597         }
5598         case KVM_SET_PMU_EVENT_FILTER:
5599                 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5600                 break;
5601         case KVM_X86_SET_MSR_FILTER:
5602                 r = kvm_vm_ioctl_set_msr_filter(kvm, argp);
5603                 break;
5604         default:
5605                 r = -ENOTTY;
5606         }
5607 out:
5608         return r;
5609 }
5610
5611 static void kvm_init_msr_list(void)
5612 {
5613         struct x86_pmu_capability x86_pmu;
5614         u32 dummy[2];
5615         unsigned i;
5616
5617         BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5618                          "Please update the fixed PMCs in msrs_to_saved_all[]");
5619
5620         perf_get_x86_pmu_capability(&x86_pmu);
5621
5622         num_msrs_to_save = 0;
5623         num_emulated_msrs = 0;
5624         num_msr_based_features = 0;
5625
5626         for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5627                 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5628                         continue;
5629
5630                 /*
5631                  * Even MSRs that are valid in the host may not be exposed
5632                  * to the guests in some cases.
5633                  */
5634                 switch (msrs_to_save_all[i]) {
5635                 case MSR_IA32_BNDCFGS:
5636                         if (!kvm_mpx_supported())
5637                                 continue;
5638                         break;
5639                 case MSR_TSC_AUX:
5640                         if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5641                                 continue;
5642                         break;
5643                 case MSR_IA32_UMWAIT_CONTROL:
5644                         if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
5645                                 continue;
5646                         break;
5647                 case MSR_IA32_RTIT_CTL:
5648                 case MSR_IA32_RTIT_STATUS:
5649                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5650                                 continue;
5651                         break;
5652                 case MSR_IA32_RTIT_CR3_MATCH:
5653                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5654                             !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5655                                 continue;
5656                         break;
5657                 case MSR_IA32_RTIT_OUTPUT_BASE:
5658                 case MSR_IA32_RTIT_OUTPUT_MASK:
5659                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5660                                 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5661                                  !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5662                                 continue;
5663                         break;
5664                 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
5665                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5666                                 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5667                                 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5668                                 continue;
5669                         break;
5670                 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5671                         if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5672                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5673                                 continue;
5674                         break;
5675                 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5676                         if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5677                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5678                                 continue;
5679                         break;
5680                 default:
5681                         break;
5682                 }
5683
5684                 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5685         }
5686
5687         for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5688                 if (!kvm_x86_ops.has_emulated_msr(emulated_msrs_all[i]))
5689                         continue;
5690
5691                 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5692         }
5693
5694         for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5695                 struct kvm_msr_entry msr;
5696
5697                 msr.index = msr_based_features_all[i];
5698                 if (kvm_get_msr_feature(&msr))
5699                         continue;
5700
5701                 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5702         }
5703 }
5704
5705 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5706                            const void *v)
5707 {
5708         int handled = 0;
5709         int n;
5710
5711         do {
5712                 n = min(len, 8);
5713                 if (!(lapic_in_kernel(vcpu) &&
5714                       !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5715                     && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5716                         break;
5717                 handled += n;
5718                 addr += n;
5719                 len -= n;
5720                 v += n;
5721         } while (len);
5722
5723         return handled;
5724 }
5725
5726 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5727 {
5728         int handled = 0;
5729         int n;
5730
5731         do {
5732                 n = min(len, 8);
5733                 if (!(lapic_in_kernel(vcpu) &&
5734                       !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5735                                          addr, n, v))
5736                     && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5737                         break;
5738                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5739                 handled += n;
5740                 addr += n;
5741                 len -= n;
5742                 v += n;
5743         } while (len);
5744
5745         return handled;
5746 }
5747
5748 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5749                         struct kvm_segment *var, int seg)
5750 {
5751         kvm_x86_ops.set_segment(vcpu, var, seg);
5752 }
5753
5754 void kvm_get_segment(struct kvm_vcpu *vcpu,
5755                      struct kvm_segment *var, int seg)
5756 {
5757         kvm_x86_ops.get_segment(vcpu, var, seg);
5758 }
5759
5760 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5761                            struct x86_exception *exception)
5762 {
5763         gpa_t t_gpa;
5764
5765         BUG_ON(!mmu_is_nested(vcpu));
5766
5767         /* NPT walks are always user-walks */
5768         access |= PFERR_USER_MASK;
5769         t_gpa  = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5770
5771         return t_gpa;
5772 }
5773
5774 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5775                               struct x86_exception *exception)
5776 {
5777         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5778         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5779 }
5780
5781  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5782                                 struct x86_exception *exception)
5783 {
5784         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5785         access |= PFERR_FETCH_MASK;
5786         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5787 }
5788
5789 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5790                                struct x86_exception *exception)
5791 {
5792         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5793         access |= PFERR_WRITE_MASK;
5794         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5795 }
5796
5797 /* uses this to access any guest's mapped memory without checking CPL */
5798 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5799                                 struct x86_exception *exception)
5800 {
5801         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5802 }
5803
5804 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5805                                       struct kvm_vcpu *vcpu, u32 access,
5806                                       struct x86_exception *exception)
5807 {
5808         void *data = val;
5809         int r = X86EMUL_CONTINUE;
5810
5811         while (bytes) {
5812                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5813                                                             exception);
5814                 unsigned offset = addr & (PAGE_SIZE-1);
5815                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5816                 int ret;
5817
5818                 if (gpa == UNMAPPED_GVA)
5819                         return X86EMUL_PROPAGATE_FAULT;
5820                 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5821                                                offset, toread);
5822                 if (ret < 0) {
5823                         r = X86EMUL_IO_NEEDED;
5824                         goto out;
5825                 }
5826
5827                 bytes -= toread;
5828                 data += toread;
5829                 addr += toread;
5830         }
5831 out:
5832         return r;
5833 }
5834
5835 /* used for instruction fetching */
5836 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5837                                 gva_t addr, void *val, unsigned int bytes,
5838                                 struct x86_exception *exception)
5839 {
5840         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5841         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5842         unsigned offset;
5843         int ret;
5844
5845         /* Inline kvm_read_guest_virt_helper for speed.  */
5846         gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5847                                                     exception);
5848         if (unlikely(gpa == UNMAPPED_GVA))
5849                 return X86EMUL_PROPAGATE_FAULT;
5850
5851         offset = addr & (PAGE_SIZE-1);
5852         if (WARN_ON(offset + bytes > PAGE_SIZE))
5853                 bytes = (unsigned)PAGE_SIZE - offset;
5854         ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5855                                        offset, bytes);
5856         if (unlikely(ret < 0))
5857                 return X86EMUL_IO_NEEDED;
5858
5859         return X86EMUL_CONTINUE;
5860 }
5861
5862 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5863                                gva_t addr, void *val, unsigned int bytes,
5864                                struct x86_exception *exception)
5865 {
5866         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5867
5868         /*
5869          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5870          * is returned, but our callers are not ready for that and they blindly
5871          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5872          * uninitialized kernel stack memory into cr2 and error code.
5873          */
5874         memset(exception, 0, sizeof(*exception));
5875         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5876                                           exception);
5877 }
5878 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5879
5880 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5881                              gva_t addr, void *val, unsigned int bytes,
5882                              struct x86_exception *exception, bool system)
5883 {
5884         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5885         u32 access = 0;
5886
5887         if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5888                 access |= PFERR_USER_MASK;
5889
5890         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5891 }
5892
5893 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5894                 unsigned long addr, void *val, unsigned int bytes)
5895 {
5896         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5897         int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5898
5899         return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5900 }
5901
5902 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5903                                       struct kvm_vcpu *vcpu, u32 access,
5904                                       struct x86_exception *exception)
5905 {
5906         void *data = val;
5907         int r = X86EMUL_CONTINUE;
5908
5909         while (bytes) {
5910                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5911                                                              access,
5912                                                              exception);
5913                 unsigned offset = addr & (PAGE_SIZE-1);
5914                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5915                 int ret;
5916
5917                 if (gpa == UNMAPPED_GVA)
5918                         return X86EMUL_PROPAGATE_FAULT;
5919                 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5920                 if (ret < 0) {
5921                         r = X86EMUL_IO_NEEDED;
5922                         goto out;
5923                 }
5924
5925                 bytes -= towrite;
5926                 data += towrite;
5927                 addr += towrite;
5928         }
5929 out:
5930         return r;
5931 }
5932
5933 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5934                               unsigned int bytes, struct x86_exception *exception,
5935                               bool system)
5936 {
5937         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5938         u32 access = PFERR_WRITE_MASK;
5939
5940         if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5941                 access |= PFERR_USER_MASK;
5942
5943         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5944                                            access, exception);
5945 }
5946
5947 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5948                                 unsigned int bytes, struct x86_exception *exception)
5949 {
5950         /* kvm_write_guest_virt_system can pull in tons of pages. */
5951         vcpu->arch.l1tf_flush_l1d = true;
5952
5953         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5954                                            PFERR_WRITE_MASK, exception);
5955 }
5956 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5957
5958 int handle_ud(struct kvm_vcpu *vcpu)
5959 {
5960         static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
5961         int emul_type = EMULTYPE_TRAP_UD;
5962         char sig[5]; /* ud2; .ascii "kvm" */
5963         struct x86_exception e;
5964
5965         if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, NULL, 0)))
5966                 return 1;
5967
5968         if (force_emulation_prefix &&
5969             kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5970                                 sig, sizeof(sig), &e) == 0 &&
5971             memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
5972                 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5973                 emul_type = EMULTYPE_TRAP_UD_FORCED;
5974         }
5975
5976         return kvm_emulate_instruction(vcpu, emul_type);
5977 }
5978 EXPORT_SYMBOL_GPL(handle_ud);
5979
5980 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5981                             gpa_t gpa, bool write)
5982 {
5983         /* For APIC access vmexit */
5984         if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5985                 return 1;
5986
5987         if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5988                 trace_vcpu_match_mmio(gva, gpa, write, true);
5989                 return 1;
5990         }
5991
5992         return 0;
5993 }
5994
5995 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5996                                 gpa_t *gpa, struct x86_exception *exception,
5997                                 bool write)
5998 {
5999         u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
6000                 | (write ? PFERR_WRITE_MASK : 0);
6001
6002         /*
6003          * currently PKRU is only applied to ept enabled guest so
6004          * there is no pkey in EPT page table for L1 guest or EPT
6005          * shadow page table for L2 guest.
6006          */
6007         if (vcpu_match_mmio_gva(vcpu, gva)
6008             && !permission_fault(vcpu, vcpu->arch.walk_mmu,
6009                                  vcpu->arch.mmio_access, 0, access)) {
6010                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
6011                                         (gva & (PAGE_SIZE - 1));
6012                 trace_vcpu_match_mmio(gva, *gpa, write, false);
6013                 return 1;
6014         }
6015
6016         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
6017
6018         if (*gpa == UNMAPPED_GVA)
6019                 return -1;
6020
6021         return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
6022 }
6023
6024 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
6025                         const void *val, int bytes)
6026 {
6027         int ret;
6028
6029         ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
6030         if (ret < 0)
6031                 return 0;
6032         kvm_page_track_write(vcpu, gpa, val, bytes);
6033         return 1;
6034 }
6035
6036 struct read_write_emulator_ops {
6037         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
6038                                   int bytes);
6039         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
6040                                   void *val, int bytes);
6041         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6042                                int bytes, void *val);
6043         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6044                                     void *val, int bytes);
6045         bool write;
6046 };
6047
6048 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
6049 {
6050         if (vcpu->mmio_read_completed) {
6051                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
6052                                vcpu->mmio_fragments[0].gpa, val);
6053                 vcpu->mmio_read_completed = 0;
6054                 return 1;
6055         }
6056
6057         return 0;
6058 }
6059
6060 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6061                         void *val, int bytes)
6062 {
6063         return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
6064 }
6065
6066 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6067                          void *val, int bytes)
6068 {
6069         return emulator_write_phys(vcpu, gpa, val, bytes);
6070 }
6071
6072 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
6073 {
6074         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
6075         return vcpu_mmio_write(vcpu, gpa, bytes, val);
6076 }
6077
6078 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6079                           void *val, int bytes)
6080 {
6081         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
6082         return X86EMUL_IO_NEEDED;
6083 }
6084
6085 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6086                            void *val, int bytes)
6087 {
6088         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
6089
6090         memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
6091         return X86EMUL_CONTINUE;
6092 }
6093
6094 static const struct read_write_emulator_ops read_emultor = {
6095         .read_write_prepare = read_prepare,
6096         .read_write_emulate = read_emulate,
6097         .read_write_mmio = vcpu_mmio_read,
6098         .read_write_exit_mmio = read_exit_mmio,
6099 };
6100
6101 static const struct read_write_emulator_ops write_emultor = {
6102         .read_write_emulate = write_emulate,
6103         .read_write_mmio = write_mmio,
6104         .read_write_exit_mmio = write_exit_mmio,
6105         .write = true,
6106 };
6107
6108 static int emulator_read_write_onepage(unsigned long addr, void *val,
6109                                        unsigned int bytes,
6110                                        struct x86_exception *exception,
6111                                        struct kvm_vcpu *vcpu,
6112                                        const struct read_write_emulator_ops *ops)
6113 {
6114         gpa_t gpa;
6115         int handled, ret;
6116         bool write = ops->write;
6117         struct kvm_mmio_fragment *frag;
6118         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6119
6120         /*
6121          * If the exit was due to a NPF we may already have a GPA.
6122          * If the GPA is present, use it to avoid the GVA to GPA table walk.
6123          * Note, this cannot be used on string operations since string
6124          * operation using rep will only have the initial GPA from the NPF
6125          * occurred.
6126          */
6127         if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
6128             (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
6129                 gpa = ctxt->gpa_val;
6130                 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
6131         } else {
6132                 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
6133                 if (ret < 0)
6134                         return X86EMUL_PROPAGATE_FAULT;
6135         }
6136
6137         if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
6138                 return X86EMUL_CONTINUE;
6139
6140         /*
6141          * Is this MMIO handled locally?
6142          */
6143         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
6144         if (handled == bytes)
6145                 return X86EMUL_CONTINUE;
6146
6147         gpa += handled;
6148         bytes -= handled;
6149         val += handled;
6150
6151         WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
6152         frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
6153         frag->gpa = gpa;
6154         frag->data = val;
6155         frag->len = bytes;
6156         return X86EMUL_CONTINUE;
6157 }
6158
6159 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
6160                         unsigned long addr,
6161                         void *val, unsigned int bytes,
6162                         struct x86_exception *exception,
6163                         const struct read_write_emulator_ops *ops)
6164 {
6165         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6166         gpa_t gpa;
6167         int rc;
6168
6169         if (ops->read_write_prepare &&
6170                   ops->read_write_prepare(vcpu, val, bytes))
6171                 return X86EMUL_CONTINUE;
6172
6173         vcpu->mmio_nr_fragments = 0;
6174
6175         /* Crossing a page boundary? */
6176         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
6177                 int now;
6178
6179                 now = -addr & ~PAGE_MASK;
6180                 rc = emulator_read_write_onepage(addr, val, now, exception,
6181                                                  vcpu, ops);
6182
6183                 if (rc != X86EMUL_CONTINUE)
6184                         return rc;
6185                 addr += now;
6186                 if (ctxt->mode != X86EMUL_MODE_PROT64)
6187                         addr = (u32)addr;
6188                 val += now;
6189                 bytes -= now;
6190         }
6191
6192         rc = emulator_read_write_onepage(addr, val, bytes, exception,
6193                                          vcpu, ops);
6194         if (rc != X86EMUL_CONTINUE)
6195                 return rc;
6196
6197         if (!vcpu->mmio_nr_fragments)
6198                 return rc;
6199
6200         gpa = vcpu->mmio_fragments[0].gpa;
6201
6202         vcpu->mmio_needed = 1;
6203         vcpu->mmio_cur_fragment = 0;
6204
6205         vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
6206         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
6207         vcpu->run->exit_reason = KVM_EXIT_MMIO;
6208         vcpu->run->mmio.phys_addr = gpa;
6209
6210         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
6211 }
6212
6213 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
6214                                   unsigned long addr,
6215                                   void *val,
6216                                   unsigned int bytes,
6217                                   struct x86_exception *exception)
6218 {
6219         return emulator_read_write(ctxt, addr, val, bytes,
6220                                    exception, &read_emultor);
6221 }
6222
6223 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
6224                             unsigned long addr,
6225                             const void *val,
6226                             unsigned int bytes,
6227                             struct x86_exception *exception)
6228 {
6229         return emulator_read_write(ctxt, addr, (void *)val, bytes,
6230                                    exception, &write_emultor);
6231 }
6232
6233 #define CMPXCHG_TYPE(t, ptr, old, new) \
6234         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
6235
6236 #ifdef CONFIG_X86_64
6237 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
6238 #else
6239 #  define CMPXCHG64(ptr, old, new) \
6240         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
6241 #endif
6242
6243 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
6244                                      unsigned long addr,
6245                                      const void *old,
6246                                      const void *new,
6247                                      unsigned int bytes,
6248                                      struct x86_exception *exception)
6249 {
6250         struct kvm_host_map map;
6251         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6252         u64 page_line_mask;
6253         gpa_t gpa;
6254         char *kaddr;
6255         bool exchanged;
6256
6257         /* guests cmpxchg8b have to be emulated atomically */
6258         if (bytes > 8 || (bytes & (bytes - 1)))
6259                 goto emul_write;
6260
6261         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
6262
6263         if (gpa == UNMAPPED_GVA ||
6264             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6265                 goto emul_write;
6266
6267         /*
6268          * Emulate the atomic as a straight write to avoid #AC if SLD is
6269          * enabled in the host and the access splits a cache line.
6270          */
6271         if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
6272                 page_line_mask = ~(cache_line_size() - 1);
6273         else
6274                 page_line_mask = PAGE_MASK;
6275
6276         if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
6277                 goto emul_write;
6278
6279         if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
6280                 goto emul_write;
6281
6282         kaddr = map.hva + offset_in_page(gpa);
6283
6284         switch (bytes) {
6285         case 1:
6286                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
6287                 break;
6288         case 2:
6289                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
6290                 break;
6291         case 4:
6292                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
6293                 break;
6294         case 8:
6295                 exchanged = CMPXCHG64(kaddr, old, new);
6296                 break;
6297         default:
6298                 BUG();
6299         }
6300
6301         kvm_vcpu_unmap(vcpu, &map, true);
6302
6303         if (!exchanged)
6304                 return X86EMUL_CMPXCHG_FAILED;
6305
6306         kvm_page_track_write(vcpu, gpa, new, bytes);
6307
6308         return X86EMUL_CONTINUE;
6309
6310 emul_write:
6311         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
6312
6313         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
6314 }
6315
6316 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
6317 {
6318         int r = 0, i;
6319
6320         for (i = 0; i < vcpu->arch.pio.count; i++) {
6321                 if (vcpu->arch.pio.in)
6322                         r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
6323                                             vcpu->arch.pio.size, pd);
6324                 else
6325                         r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
6326                                              vcpu->arch.pio.port, vcpu->arch.pio.size,
6327                                              pd);
6328                 if (r)
6329                         break;
6330                 pd += vcpu->arch.pio.size;
6331         }
6332         return r;
6333 }
6334
6335 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
6336                                unsigned short port, void *val,
6337                                unsigned int count, bool in)
6338 {
6339         vcpu->arch.pio.port = port;
6340         vcpu->arch.pio.in = in;
6341         vcpu->arch.pio.count  = count;
6342         vcpu->arch.pio.size = size;
6343
6344         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
6345                 vcpu->arch.pio.count = 0;
6346                 return 1;
6347         }
6348
6349         vcpu->run->exit_reason = KVM_EXIT_IO;
6350         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
6351         vcpu->run->io.size = size;
6352         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
6353         vcpu->run->io.count = count;
6354         vcpu->run->io.port = port;
6355
6356         return 0;
6357 }
6358
6359 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
6360                            unsigned short port, void *val, unsigned int count)
6361 {
6362         int ret;
6363
6364         if (vcpu->arch.pio.count)
6365                 goto data_avail;
6366
6367         memset(vcpu->arch.pio_data, 0, size * count);
6368
6369         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
6370         if (ret) {
6371 data_avail:
6372                 memcpy(val, vcpu->arch.pio_data, size * count);
6373                 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
6374                 vcpu->arch.pio.count = 0;
6375                 return 1;
6376         }
6377
6378         return 0;
6379 }
6380
6381 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
6382                                     int size, unsigned short port, void *val,
6383                                     unsigned int count)
6384 {
6385         return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
6386
6387 }
6388
6389 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
6390                             unsigned short port, const void *val,
6391                             unsigned int count)
6392 {
6393         memcpy(vcpu->arch.pio_data, val, size * count);
6394         trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6395         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6396 }
6397
6398 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
6399                                      int size, unsigned short port,
6400                                      const void *val, unsigned int count)
6401 {
6402         return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
6403 }
6404
6405 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6406 {
6407         return kvm_x86_ops.get_segment_base(vcpu, seg);
6408 }
6409
6410 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6411 {
6412         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6413 }
6414
6415 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6416 {
6417         if (!need_emulate_wbinvd(vcpu))
6418                 return X86EMUL_CONTINUE;
6419
6420         if (kvm_x86_ops.has_wbinvd_exit()) {
6421                 int cpu = get_cpu();
6422
6423                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6424                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6425                                 wbinvd_ipi, NULL, 1);
6426                 put_cpu();
6427                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6428         } else
6429                 wbinvd();
6430         return X86EMUL_CONTINUE;
6431 }
6432
6433 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6434 {
6435         kvm_emulate_wbinvd_noskip(vcpu);
6436         return kvm_skip_emulated_instruction(vcpu);
6437 }
6438 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6439
6440
6441
6442 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6443 {
6444         kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6445 }
6446
6447 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6448                            unsigned long *dest)
6449 {
6450         return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6451 }
6452
6453 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6454                            unsigned long value)
6455 {
6456
6457         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6458 }
6459
6460 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6461 {
6462         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6463 }
6464
6465 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6466 {
6467         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6468         unsigned long value;
6469
6470         switch (cr) {
6471         case 0:
6472                 value = kvm_read_cr0(vcpu);
6473                 break;
6474         case 2:
6475                 value = vcpu->arch.cr2;
6476                 break;
6477         case 3:
6478                 value = kvm_read_cr3(vcpu);
6479                 break;
6480         case 4:
6481                 value = kvm_read_cr4(vcpu);
6482                 break;
6483         case 8:
6484                 value = kvm_get_cr8(vcpu);
6485                 break;
6486         default:
6487                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6488                 return 0;
6489         }
6490
6491         return value;
6492 }
6493
6494 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6495 {
6496         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6497         int res = 0;
6498
6499         switch (cr) {
6500         case 0:
6501                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6502                 break;
6503         case 2:
6504                 vcpu->arch.cr2 = val;
6505                 break;
6506         case 3:
6507                 res = kvm_set_cr3(vcpu, val);
6508                 break;
6509         case 4:
6510                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6511                 break;
6512         case 8:
6513                 res = kvm_set_cr8(vcpu, val);
6514                 break;
6515         default:
6516                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6517                 res = -1;
6518         }
6519
6520         return res;
6521 }
6522
6523 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6524 {
6525         return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt));
6526 }
6527
6528 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6529 {
6530         kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt);
6531 }
6532
6533 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6534 {
6535         kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt);
6536 }
6537
6538 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6539 {
6540         kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt);
6541 }
6542
6543 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6544 {
6545         kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt);
6546 }
6547
6548 static unsigned long emulator_get_cached_segment_base(
6549         struct x86_emulate_ctxt *ctxt, int seg)
6550 {
6551         return get_segment_base(emul_to_vcpu(ctxt), seg);
6552 }
6553
6554 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6555                                  struct desc_struct *desc, u32 *base3,
6556                                  int seg)
6557 {
6558         struct kvm_segment var;
6559
6560         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6561         *selector = var.selector;
6562
6563         if (var.unusable) {
6564                 memset(desc, 0, sizeof(*desc));
6565                 if (base3)
6566                         *base3 = 0;
6567                 return false;
6568         }
6569
6570         if (var.g)
6571                 var.limit >>= 12;
6572         set_desc_limit(desc, var.limit);
6573         set_desc_base(desc, (unsigned long)var.base);
6574 #ifdef CONFIG_X86_64
6575         if (base3)
6576                 *base3 = var.base >> 32;
6577 #endif
6578         desc->type = var.type;
6579         desc->s = var.s;
6580         desc->dpl = var.dpl;
6581         desc->p = var.present;
6582         desc->avl = var.avl;
6583         desc->l = var.l;
6584         desc->d = var.db;
6585         desc->g = var.g;
6586
6587         return true;
6588 }
6589
6590 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6591                                  struct desc_struct *desc, u32 base3,
6592                                  int seg)
6593 {
6594         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6595         struct kvm_segment var;
6596
6597         var.selector = selector;
6598         var.base = get_desc_base(desc);
6599 #ifdef CONFIG_X86_64
6600         var.base |= ((u64)base3) << 32;
6601 #endif
6602         var.limit = get_desc_limit(desc);
6603         if (desc->g)
6604                 var.limit = (var.limit << 12) | 0xfff;
6605         var.type = desc->type;
6606         var.dpl = desc->dpl;
6607         var.db = desc->d;
6608         var.s = desc->s;
6609         var.l = desc->l;
6610         var.g = desc->g;
6611         var.avl = desc->avl;
6612         var.present = desc->p;
6613         var.unusable = !var.present;
6614         var.padding = 0;
6615
6616         kvm_set_segment(vcpu, &var, seg);
6617         return;
6618 }
6619
6620 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6621                             u32 msr_index, u64 *pdata)
6622 {
6623         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6624         int r;
6625
6626         r = kvm_get_msr(vcpu, msr_index, pdata);
6627
6628         if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) {
6629                 /* Bounce to user space */
6630                 return X86EMUL_IO_NEEDED;
6631         }
6632
6633         return r;
6634 }
6635
6636 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6637                             u32 msr_index, u64 data)
6638 {
6639         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6640         int r;
6641
6642         r = kvm_set_msr(vcpu, msr_index, data);
6643
6644         if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) {
6645                 /* Bounce to user space */
6646                 return X86EMUL_IO_NEEDED;
6647         }
6648
6649         return r;
6650 }
6651
6652 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6653 {
6654         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6655
6656         return vcpu->arch.smbase;
6657 }
6658
6659 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6660 {
6661         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6662
6663         vcpu->arch.smbase = smbase;
6664 }
6665
6666 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6667                               u32 pmc)
6668 {
6669         return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6670 }
6671
6672 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6673                              u32 pmc, u64 *pdata)
6674 {
6675         return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6676 }
6677
6678 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6679 {
6680         emul_to_vcpu(ctxt)->arch.halt_request = 1;
6681 }
6682
6683 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6684                               struct x86_instruction_info *info,
6685                               enum x86_intercept_stage stage)
6686 {
6687         return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage,
6688                                             &ctxt->exception);
6689 }
6690
6691 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6692                               u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6693                               bool exact_only)
6694 {
6695         return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6696 }
6697
6698 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6699 {
6700         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6701 }
6702
6703 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6704 {
6705         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6706 }
6707
6708 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6709 {
6710         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6711 }
6712
6713 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6714 {
6715         return kvm_register_read(emul_to_vcpu(ctxt), reg);
6716 }
6717
6718 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6719 {
6720         kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6721 }
6722
6723 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6724 {
6725         kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked);
6726 }
6727
6728 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6729 {
6730         return emul_to_vcpu(ctxt)->arch.hflags;
6731 }
6732
6733 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6734 {
6735         emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6736 }
6737
6738 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6739                                   const char *smstate)
6740 {
6741         return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6742 }
6743
6744 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6745 {
6746         kvm_smm_changed(emul_to_vcpu(ctxt));
6747 }
6748
6749 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6750 {
6751         return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6752 }
6753
6754 static const struct x86_emulate_ops emulate_ops = {
6755         .read_gpr            = emulator_read_gpr,
6756         .write_gpr           = emulator_write_gpr,
6757         .read_std            = emulator_read_std,
6758         .write_std           = emulator_write_std,
6759         .read_phys           = kvm_read_guest_phys_system,
6760         .fetch               = kvm_fetch_guest_virt,
6761         .read_emulated       = emulator_read_emulated,
6762         .write_emulated      = emulator_write_emulated,
6763         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
6764         .invlpg              = emulator_invlpg,
6765         .pio_in_emulated     = emulator_pio_in_emulated,
6766         .pio_out_emulated    = emulator_pio_out_emulated,
6767         .get_segment         = emulator_get_segment,
6768         .set_segment         = emulator_set_segment,
6769         .get_cached_segment_base = emulator_get_cached_segment_base,
6770         .get_gdt             = emulator_get_gdt,
6771         .get_idt             = emulator_get_idt,
6772         .set_gdt             = emulator_set_gdt,
6773         .set_idt             = emulator_set_idt,
6774         .get_cr              = emulator_get_cr,
6775         .set_cr              = emulator_set_cr,
6776         .cpl                 = emulator_get_cpl,
6777         .get_dr              = emulator_get_dr,
6778         .set_dr              = emulator_set_dr,
6779         .get_smbase          = emulator_get_smbase,
6780         .set_smbase          = emulator_set_smbase,
6781         .set_msr             = emulator_set_msr,
6782         .get_msr             = emulator_get_msr,
6783         .check_pmc           = emulator_check_pmc,
6784         .read_pmc            = emulator_read_pmc,
6785         .halt                = emulator_halt,
6786         .wbinvd              = emulator_wbinvd,
6787         .fix_hypercall       = emulator_fix_hypercall,
6788         .intercept           = emulator_intercept,
6789         .get_cpuid           = emulator_get_cpuid,
6790         .guest_has_long_mode = emulator_guest_has_long_mode,
6791         .guest_has_movbe     = emulator_guest_has_movbe,
6792         .guest_has_fxsr      = emulator_guest_has_fxsr,
6793         .set_nmi_mask        = emulator_set_nmi_mask,
6794         .get_hflags          = emulator_get_hflags,
6795         .set_hflags          = emulator_set_hflags,
6796         .pre_leave_smm       = emulator_pre_leave_smm,
6797         .post_leave_smm      = emulator_post_leave_smm,
6798         .set_xcr             = emulator_set_xcr,
6799 };
6800
6801 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6802 {
6803         u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
6804         /*
6805          * an sti; sti; sequence only disable interrupts for the first
6806          * instruction. So, if the last instruction, be it emulated or
6807          * not, left the system with the INT_STI flag enabled, it
6808          * means that the last instruction is an sti. We should not
6809          * leave the flag on in this case. The same goes for mov ss
6810          */
6811         if (int_shadow & mask)
6812                 mask = 0;
6813         if (unlikely(int_shadow || mask)) {
6814                 kvm_x86_ops.set_interrupt_shadow(vcpu, mask);
6815                 if (!mask)
6816                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6817         }
6818 }
6819
6820 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6821 {
6822         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6823         if (ctxt->exception.vector == PF_VECTOR)
6824                 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
6825
6826         if (ctxt->exception.error_code_valid)
6827                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6828                                       ctxt->exception.error_code);
6829         else
6830                 kvm_queue_exception(vcpu, ctxt->exception.vector);
6831         return false;
6832 }
6833
6834 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6835 {
6836         struct x86_emulate_ctxt *ctxt;
6837
6838         ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6839         if (!ctxt) {
6840                 pr_err("kvm: failed to allocate vcpu's emulator\n");
6841                 return NULL;
6842         }
6843
6844         ctxt->vcpu = vcpu;
6845         ctxt->ops = &emulate_ops;
6846         vcpu->arch.emulate_ctxt = ctxt;
6847
6848         return ctxt;
6849 }
6850
6851 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6852 {
6853         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6854         int cs_db, cs_l;
6855
6856         kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6857
6858         ctxt->gpa_available = false;
6859         ctxt->eflags = kvm_get_rflags(vcpu);
6860         ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6861
6862         ctxt->eip = kvm_rip_read(vcpu);
6863         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
6864                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
6865                      (cs_l && is_long_mode(vcpu))       ? X86EMUL_MODE_PROT64 :
6866                      cs_db                              ? X86EMUL_MODE_PROT32 :
6867                                                           X86EMUL_MODE_PROT16;
6868         BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6869         BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6870         BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6871
6872         init_decode_cache(ctxt);
6873         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6874 }
6875
6876 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6877 {
6878         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6879         int ret;
6880
6881         init_emulate_ctxt(vcpu);
6882
6883         ctxt->op_bytes = 2;
6884         ctxt->ad_bytes = 2;
6885         ctxt->_eip = ctxt->eip + inc_eip;
6886         ret = emulate_int_real(ctxt, irq);
6887
6888         if (ret != X86EMUL_CONTINUE) {
6889                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6890         } else {
6891                 ctxt->eip = ctxt->_eip;
6892                 kvm_rip_write(vcpu, ctxt->eip);
6893                 kvm_set_rflags(vcpu, ctxt->eflags);
6894         }
6895 }
6896 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6897
6898 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6899 {
6900         ++vcpu->stat.insn_emulation_fail;
6901         trace_kvm_emulate_insn_failed(vcpu);
6902
6903         if (emulation_type & EMULTYPE_VMWARE_GP) {
6904                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6905                 return 1;
6906         }
6907
6908         if (emulation_type & EMULTYPE_SKIP) {
6909                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6910                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6911                 vcpu->run->internal.ndata = 0;
6912                 return 0;
6913         }
6914
6915         kvm_queue_exception(vcpu, UD_VECTOR);
6916
6917         if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) {
6918                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6919                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6920                 vcpu->run->internal.ndata = 0;
6921                 return 0;
6922         }
6923
6924         return 1;
6925 }
6926
6927 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6928                                   bool write_fault_to_shadow_pgtable,
6929                                   int emulation_type)
6930 {
6931         gpa_t gpa = cr2_or_gpa;
6932         kvm_pfn_t pfn;
6933
6934         if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6935                 return false;
6936
6937         if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6938             WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6939                 return false;
6940
6941         if (!vcpu->arch.mmu->direct_map) {
6942                 /*
6943                  * Write permission should be allowed since only
6944                  * write access need to be emulated.
6945                  */
6946                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6947
6948                 /*
6949                  * If the mapping is invalid in guest, let cpu retry
6950                  * it to generate fault.
6951                  */
6952                 if (gpa == UNMAPPED_GVA)
6953                         return true;
6954         }
6955
6956         /*
6957          * Do not retry the unhandleable instruction if it faults on the
6958          * readonly host memory, otherwise it will goto a infinite loop:
6959          * retry instruction -> write #PF -> emulation fail -> retry
6960          * instruction -> ...
6961          */
6962         pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6963
6964         /*
6965          * If the instruction failed on the error pfn, it can not be fixed,
6966          * report the error to userspace.
6967          */
6968         if (is_error_noslot_pfn(pfn))
6969                 return false;
6970
6971         kvm_release_pfn_clean(pfn);
6972
6973         /* The instructions are well-emulated on direct mmu. */
6974         if (vcpu->arch.mmu->direct_map) {
6975                 unsigned int indirect_shadow_pages;
6976
6977                 spin_lock(&vcpu->kvm->mmu_lock);
6978                 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6979                 spin_unlock(&vcpu->kvm->mmu_lock);
6980
6981                 if (indirect_shadow_pages)
6982                         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6983
6984                 return true;
6985         }
6986
6987         /*
6988          * if emulation was due to access to shadowed page table
6989          * and it failed try to unshadow page and re-enter the
6990          * guest to let CPU execute the instruction.
6991          */
6992         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6993
6994         /*
6995          * If the access faults on its page table, it can not
6996          * be fixed by unprotecting shadow page and it should
6997          * be reported to userspace.
6998          */
6999         return !write_fault_to_shadow_pgtable;
7000 }
7001
7002 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
7003                               gpa_t cr2_or_gpa,  int emulation_type)
7004 {
7005         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7006         unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
7007
7008         last_retry_eip = vcpu->arch.last_retry_eip;
7009         last_retry_addr = vcpu->arch.last_retry_addr;
7010
7011         /*
7012          * If the emulation is caused by #PF and it is non-page_table
7013          * writing instruction, it means the VM-EXIT is caused by shadow
7014          * page protected, we can zap the shadow page and retry this
7015          * instruction directly.
7016          *
7017          * Note: if the guest uses a non-page-table modifying instruction
7018          * on the PDE that points to the instruction, then we will unmap
7019          * the instruction and go to an infinite loop. So, we cache the
7020          * last retried eip and the last fault address, if we meet the eip
7021          * and the address again, we can break out of the potential infinite
7022          * loop.
7023          */
7024         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
7025
7026         if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7027                 return false;
7028
7029         if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7030             WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7031                 return false;
7032
7033         if (x86_page_table_writing_insn(ctxt))
7034                 return false;
7035
7036         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
7037                 return false;
7038
7039         vcpu->arch.last_retry_eip = ctxt->eip;
7040         vcpu->arch.last_retry_addr = cr2_or_gpa;
7041
7042         if (!vcpu->arch.mmu->direct_map)
7043                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7044
7045         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7046
7047         return true;
7048 }
7049
7050 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
7051 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
7052
7053 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
7054 {
7055         if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
7056                 /* This is a good place to trace that we are exiting SMM.  */
7057                 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
7058
7059                 /* Process a latched INIT or SMI, if any.  */
7060                 kvm_make_request(KVM_REQ_EVENT, vcpu);
7061         }
7062
7063         kvm_mmu_reset_context(vcpu);
7064 }
7065
7066 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
7067                                 unsigned long *db)
7068 {
7069         u32 dr6 = 0;
7070         int i;
7071         u32 enable, rwlen;
7072
7073         enable = dr7;
7074         rwlen = dr7 >> 16;
7075         for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
7076                 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
7077                         dr6 |= (1 << i);
7078         return dr6;
7079 }
7080
7081 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
7082 {
7083         struct kvm_run *kvm_run = vcpu->run;
7084
7085         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
7086                 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
7087                 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
7088                 kvm_run->debug.arch.exception = DB_VECTOR;
7089                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7090                 return 0;
7091         }
7092         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
7093         return 1;
7094 }
7095
7096 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
7097 {
7098         unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7099         int r;
7100
7101         r = kvm_x86_ops.skip_emulated_instruction(vcpu);
7102         if (unlikely(!r))
7103                 return 0;
7104
7105         /*
7106          * rflags is the old, "raw" value of the flags.  The new value has
7107          * not been saved yet.
7108          *
7109          * This is correct even for TF set by the guest, because "the
7110          * processor will not generate this exception after the instruction
7111          * that sets the TF flag".
7112          */
7113         if (unlikely(rflags & X86_EFLAGS_TF))
7114                 r = kvm_vcpu_do_singlestep(vcpu);
7115         return r;
7116 }
7117 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
7118
7119 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
7120 {
7121         if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
7122             (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
7123                 struct kvm_run *kvm_run = vcpu->run;
7124                 unsigned long eip = kvm_get_linear_rip(vcpu);
7125                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7126                                            vcpu->arch.guest_debug_dr7,
7127                                            vcpu->arch.eff_db);
7128
7129                 if (dr6 != 0) {
7130                         kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
7131                         kvm_run->debug.arch.pc = eip;
7132                         kvm_run->debug.arch.exception = DB_VECTOR;
7133                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
7134                         *r = 0;
7135                         return true;
7136                 }
7137         }
7138
7139         if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
7140             !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
7141                 unsigned long eip = kvm_get_linear_rip(vcpu);
7142                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7143                                            vcpu->arch.dr7,
7144                                            vcpu->arch.db);
7145
7146                 if (dr6 != 0) {
7147                         kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
7148                         *r = 1;
7149                         return true;
7150                 }
7151         }
7152
7153         return false;
7154 }
7155
7156 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
7157 {
7158         switch (ctxt->opcode_len) {
7159         case 1:
7160                 switch (ctxt->b) {
7161                 case 0xe4:      /* IN */
7162                 case 0xe5:
7163                 case 0xec:
7164                 case 0xed:
7165                 case 0xe6:      /* OUT */
7166                 case 0xe7:
7167                 case 0xee:
7168                 case 0xef:
7169                 case 0x6c:      /* INS */
7170                 case 0x6d:
7171                 case 0x6e:      /* OUTS */
7172                 case 0x6f:
7173                         return true;
7174                 }
7175                 break;
7176         case 2:
7177                 switch (ctxt->b) {
7178                 case 0x33:      /* RDPMC */
7179                         return true;
7180                 }
7181                 break;
7182         }
7183
7184         return false;
7185 }
7186
7187 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7188                             int emulation_type, void *insn, int insn_len)
7189 {
7190         int r;
7191         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7192         bool writeback = true;
7193         bool write_fault_to_spt;
7194
7195         if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, insn, insn_len)))
7196                 return 1;
7197
7198         vcpu->arch.l1tf_flush_l1d = true;
7199
7200         /*
7201          * Clear write_fault_to_shadow_pgtable here to ensure it is
7202          * never reused.
7203          */
7204         write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
7205         vcpu->arch.write_fault_to_shadow_pgtable = false;
7206         kvm_clear_exception_queue(vcpu);
7207
7208         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
7209                 init_emulate_ctxt(vcpu);
7210
7211                 /*
7212                  * We will reenter on the same instruction since
7213                  * we do not set complete_userspace_io.  This does not
7214                  * handle watchpoints yet, those would be handled in
7215                  * the emulate_ops.
7216                  */
7217                 if (!(emulation_type & EMULTYPE_SKIP) &&
7218                     kvm_vcpu_check_breakpoint(vcpu, &r))
7219                         return r;
7220
7221                 ctxt->interruptibility = 0;
7222                 ctxt->have_exception = false;
7223                 ctxt->exception.vector = -1;
7224                 ctxt->perm_ok = false;
7225
7226                 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
7227
7228                 r = x86_decode_insn(ctxt, insn, insn_len);
7229
7230                 trace_kvm_emulate_insn_start(vcpu);
7231                 ++vcpu->stat.insn_emulation;
7232                 if (r != EMULATION_OK)  {
7233                         if ((emulation_type & EMULTYPE_TRAP_UD) ||
7234                             (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
7235                                 kvm_queue_exception(vcpu, UD_VECTOR);
7236                                 return 1;
7237                         }
7238                         if (reexecute_instruction(vcpu, cr2_or_gpa,
7239                                                   write_fault_to_spt,
7240                                                   emulation_type))
7241                                 return 1;
7242                         if (ctxt->have_exception) {
7243                                 /*
7244                                  * #UD should result in just EMULATION_FAILED, and trap-like
7245                                  * exception should not be encountered during decode.
7246                                  */
7247                                 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
7248                                              exception_type(ctxt->exception.vector) == EXCPT_TRAP);
7249                                 inject_emulated_exception(vcpu);
7250                                 return 1;
7251                         }
7252                         return handle_emulation_failure(vcpu, emulation_type);
7253                 }
7254         }
7255
7256         if ((emulation_type & EMULTYPE_VMWARE_GP) &&
7257             !is_vmware_backdoor_opcode(ctxt)) {
7258                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7259                 return 1;
7260         }
7261
7262         /*
7263          * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
7264          * for kvm_skip_emulated_instruction().  The caller is responsible for
7265          * updating interruptibility state and injecting single-step #DBs.
7266          */
7267         if (emulation_type & EMULTYPE_SKIP) {
7268                 kvm_rip_write(vcpu, ctxt->_eip);
7269                 if (ctxt->eflags & X86_EFLAGS_RF)
7270                         kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
7271                 return 1;
7272         }
7273
7274         if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
7275                 return 1;
7276
7277         /* this is needed for vmware backdoor interface to work since it
7278            changes registers values  during IO operation */
7279         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
7280                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7281                 emulator_invalidate_register_cache(ctxt);
7282         }
7283
7284 restart:
7285         if (emulation_type & EMULTYPE_PF) {
7286                 /* Save the faulting GPA (cr2) in the address field */
7287                 ctxt->exception.address = cr2_or_gpa;
7288
7289                 /* With shadow page tables, cr2 contains a GVA or nGPA. */
7290                 if (vcpu->arch.mmu->direct_map) {
7291                         ctxt->gpa_available = true;
7292                         ctxt->gpa_val = cr2_or_gpa;
7293                 }
7294         } else {
7295                 /* Sanitize the address out of an abundance of paranoia. */
7296                 ctxt->exception.address = 0;
7297         }
7298
7299         r = x86_emulate_insn(ctxt);
7300
7301         if (r == EMULATION_INTERCEPTED)
7302                 return 1;
7303
7304         if (r == EMULATION_FAILED) {
7305                 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
7306                                         emulation_type))
7307                         return 1;
7308
7309                 return handle_emulation_failure(vcpu, emulation_type);
7310         }
7311
7312         if (ctxt->have_exception) {
7313                 r = 1;
7314                 if (inject_emulated_exception(vcpu))
7315                         return r;
7316         } else if (vcpu->arch.pio.count) {
7317                 if (!vcpu->arch.pio.in) {
7318                         /* FIXME: return into emulator if single-stepping.  */
7319                         vcpu->arch.pio.count = 0;
7320                 } else {
7321                         writeback = false;
7322                         vcpu->arch.complete_userspace_io = complete_emulated_pio;
7323                 }
7324                 r = 0;
7325         } else if (vcpu->mmio_needed) {
7326                 ++vcpu->stat.mmio_exits;
7327
7328                 if (!vcpu->mmio_is_write)
7329                         writeback = false;
7330                 r = 0;
7331                 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7332         } else if (r == EMULATION_RESTART)
7333                 goto restart;
7334         else
7335                 r = 1;
7336
7337         if (writeback) {
7338                 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7339                 toggle_interruptibility(vcpu, ctxt->interruptibility);
7340                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7341                 if (!ctxt->have_exception ||
7342                     exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
7343                         kvm_rip_write(vcpu, ctxt->eip);
7344                         if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
7345                                 r = kvm_vcpu_do_singlestep(vcpu);
7346                         if (kvm_x86_ops.update_emulated_instruction)
7347                                 kvm_x86_ops.update_emulated_instruction(vcpu);
7348                         __kvm_set_rflags(vcpu, ctxt->eflags);
7349                 }
7350
7351                 /*
7352                  * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
7353                  * do nothing, and it will be requested again as soon as
7354                  * the shadow expires.  But we still need to check here,
7355                  * because POPF has no interrupt shadow.
7356                  */
7357                 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
7358                         kvm_make_request(KVM_REQ_EVENT, vcpu);
7359         } else
7360                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
7361
7362         return r;
7363 }
7364
7365 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
7366 {
7367         return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
7368 }
7369 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
7370
7371 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
7372                                         void *insn, int insn_len)
7373 {
7374         return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
7375 }
7376 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
7377
7378 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
7379 {
7380         vcpu->arch.pio.count = 0;
7381         return 1;
7382 }
7383
7384 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
7385 {
7386         vcpu->arch.pio.count = 0;
7387
7388         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
7389                 return 1;
7390
7391         return kvm_skip_emulated_instruction(vcpu);
7392 }
7393
7394 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
7395                             unsigned short port)
7396 {
7397         unsigned long val = kvm_rax_read(vcpu);
7398         int ret = emulator_pio_out(vcpu, size, port, &val, 1);
7399
7400         if (ret)
7401                 return ret;
7402
7403         /*
7404          * Workaround userspace that relies on old KVM behavior of %rip being
7405          * incremented prior to exiting to userspace to handle "OUT 0x7e".
7406          */
7407         if (port == 0x7e &&
7408             kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
7409                 vcpu->arch.complete_userspace_io =
7410                         complete_fast_pio_out_port_0x7e;
7411                 kvm_skip_emulated_instruction(vcpu);
7412         } else {
7413                 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7414                 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
7415         }
7416         return 0;
7417 }
7418
7419 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
7420 {
7421         unsigned long val;
7422
7423         /* We should only ever be called with arch.pio.count equal to 1 */
7424         BUG_ON(vcpu->arch.pio.count != 1);
7425
7426         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
7427                 vcpu->arch.pio.count = 0;
7428                 return 1;
7429         }
7430
7431         /* For size less than 4 we merge, else we zero extend */
7432         val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7433
7434         /*
7435          * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7436          * the copy and tracing
7437          */
7438         emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7439         kvm_rax_write(vcpu, val);
7440
7441         return kvm_skip_emulated_instruction(vcpu);
7442 }
7443
7444 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7445                            unsigned short port)
7446 {
7447         unsigned long val;
7448         int ret;
7449
7450         /* For size less than 4 we merge, else we zero extend */
7451         val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7452
7453         ret = emulator_pio_in(vcpu, size, port, &val, 1);
7454         if (ret) {
7455                 kvm_rax_write(vcpu, val);
7456                 return ret;
7457         }
7458
7459         vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7460         vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7461
7462         return 0;
7463 }
7464
7465 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7466 {
7467         int ret;
7468
7469         if (in)
7470                 ret = kvm_fast_pio_in(vcpu, size, port);
7471         else
7472                 ret = kvm_fast_pio_out(vcpu, size, port);
7473         return ret && kvm_skip_emulated_instruction(vcpu);
7474 }
7475 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7476
7477 static int kvmclock_cpu_down_prep(unsigned int cpu)
7478 {
7479         __this_cpu_write(cpu_tsc_khz, 0);
7480         return 0;
7481 }
7482
7483 static void tsc_khz_changed(void *data)
7484 {
7485         struct cpufreq_freqs *freq = data;
7486         unsigned long khz = 0;
7487
7488         if (data)
7489                 khz = freq->new;
7490         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7491                 khz = cpufreq_quick_get(raw_smp_processor_id());
7492         if (!khz)
7493                 khz = tsc_khz;
7494         __this_cpu_write(cpu_tsc_khz, khz);
7495 }
7496
7497 #ifdef CONFIG_X86_64
7498 static void kvm_hyperv_tsc_notifier(void)
7499 {
7500         struct kvm *kvm;
7501         struct kvm_vcpu *vcpu;
7502         int cpu;
7503
7504         mutex_lock(&kvm_lock);
7505         list_for_each_entry(kvm, &vm_list, vm_list)
7506                 kvm_make_mclock_inprogress_request(kvm);
7507
7508         hyperv_stop_tsc_emulation();
7509
7510         /* TSC frequency always matches when on Hyper-V */
7511         for_each_present_cpu(cpu)
7512                 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7513         kvm_max_guest_tsc_khz = tsc_khz;
7514
7515         list_for_each_entry(kvm, &vm_list, vm_list) {
7516                 struct kvm_arch *ka = &kvm->arch;
7517
7518                 spin_lock(&ka->pvclock_gtod_sync_lock);
7519
7520                 pvclock_update_vm_gtod_copy(kvm);
7521
7522                 kvm_for_each_vcpu(cpu, vcpu, kvm)
7523                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7524
7525                 kvm_for_each_vcpu(cpu, vcpu, kvm)
7526                         kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7527
7528                 spin_unlock(&ka->pvclock_gtod_sync_lock);
7529         }
7530         mutex_unlock(&kvm_lock);
7531 }
7532 #endif
7533
7534 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7535 {
7536         struct kvm *kvm;
7537         struct kvm_vcpu *vcpu;
7538         int i, send_ipi = 0;
7539
7540         /*
7541          * We allow guests to temporarily run on slowing clocks,
7542          * provided we notify them after, or to run on accelerating
7543          * clocks, provided we notify them before.  Thus time never
7544          * goes backwards.
7545          *
7546          * However, we have a problem.  We can't atomically update
7547          * the frequency of a given CPU from this function; it is
7548          * merely a notifier, which can be called from any CPU.
7549          * Changing the TSC frequency at arbitrary points in time
7550          * requires a recomputation of local variables related to
7551          * the TSC for each VCPU.  We must flag these local variables
7552          * to be updated and be sure the update takes place with the
7553          * new frequency before any guests proceed.
7554          *
7555          * Unfortunately, the combination of hotplug CPU and frequency
7556          * change creates an intractable locking scenario; the order
7557          * of when these callouts happen is undefined with respect to
7558          * CPU hotplug, and they can race with each other.  As such,
7559          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7560          * undefined; you can actually have a CPU frequency change take
7561          * place in between the computation of X and the setting of the
7562          * variable.  To protect against this problem, all updates of
7563          * the per_cpu tsc_khz variable are done in an interrupt
7564          * protected IPI, and all callers wishing to update the value
7565          * must wait for a synchronous IPI to complete (which is trivial
7566          * if the caller is on the CPU already).  This establishes the
7567          * necessary total order on variable updates.
7568          *
7569          * Note that because a guest time update may take place
7570          * anytime after the setting of the VCPU's request bit, the
7571          * correct TSC value must be set before the request.  However,
7572          * to ensure the update actually makes it to any guest which
7573          * starts running in hardware virtualization between the set
7574          * and the acquisition of the spinlock, we must also ping the
7575          * CPU after setting the request bit.
7576          *
7577          */
7578
7579         smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7580
7581         mutex_lock(&kvm_lock);
7582         list_for_each_entry(kvm, &vm_list, vm_list) {
7583                 kvm_for_each_vcpu(i, vcpu, kvm) {
7584                         if (vcpu->cpu != cpu)
7585                                 continue;
7586                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7587                         if (vcpu->cpu != raw_smp_processor_id())
7588                                 send_ipi = 1;
7589                 }
7590         }
7591         mutex_unlock(&kvm_lock);
7592
7593         if (freq->old < freq->new && send_ipi) {
7594                 /*
7595                  * We upscale the frequency.  Must make the guest
7596                  * doesn't see old kvmclock values while running with
7597                  * the new frequency, otherwise we risk the guest sees
7598                  * time go backwards.
7599                  *
7600                  * In case we update the frequency for another cpu
7601                  * (which might be in guest context) send an interrupt
7602                  * to kick the cpu out of guest context.  Next time
7603                  * guest context is entered kvmclock will be updated,
7604                  * so the guest will not see stale values.
7605                  */
7606                 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7607         }
7608 }
7609
7610 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7611                                      void *data)
7612 {
7613         struct cpufreq_freqs *freq = data;
7614         int cpu;
7615
7616         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7617                 return 0;
7618         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7619                 return 0;
7620
7621         for_each_cpu(cpu, freq->policy->cpus)
7622                 __kvmclock_cpufreq_notifier(freq, cpu);
7623
7624         return 0;
7625 }
7626
7627 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7628         .notifier_call  = kvmclock_cpufreq_notifier
7629 };
7630
7631 static int kvmclock_cpu_online(unsigned int cpu)
7632 {
7633         tsc_khz_changed(NULL);
7634         return 0;
7635 }
7636
7637 static void kvm_timer_init(void)
7638 {
7639         max_tsc_khz = tsc_khz;
7640
7641         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7642 #ifdef CONFIG_CPU_FREQ
7643                 struct cpufreq_policy *policy;
7644                 int cpu;
7645
7646                 cpu = get_cpu();
7647                 policy = cpufreq_cpu_get(cpu);
7648                 if (policy) {
7649                         if (policy->cpuinfo.max_freq)
7650                                 max_tsc_khz = policy->cpuinfo.max_freq;
7651                         cpufreq_cpu_put(policy);
7652                 }
7653                 put_cpu();
7654 #endif
7655                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7656                                           CPUFREQ_TRANSITION_NOTIFIER);
7657         }
7658
7659         cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7660                           kvmclock_cpu_online, kvmclock_cpu_down_prep);
7661 }
7662
7663 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7664 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7665
7666 int kvm_is_in_guest(void)
7667 {
7668         return __this_cpu_read(current_vcpu) != NULL;
7669 }
7670
7671 static int kvm_is_user_mode(void)
7672 {
7673         int user_mode = 3;
7674
7675         if (__this_cpu_read(current_vcpu))
7676                 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu));
7677
7678         return user_mode != 0;
7679 }
7680
7681 static unsigned long kvm_get_guest_ip(void)
7682 {
7683         unsigned long ip = 0;
7684
7685         if (__this_cpu_read(current_vcpu))
7686                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7687
7688         return ip;
7689 }
7690
7691 static void kvm_handle_intel_pt_intr(void)
7692 {
7693         struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7694
7695         kvm_make_request(KVM_REQ_PMI, vcpu);
7696         __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7697                         (unsigned long *)&vcpu->arch.pmu.global_status);
7698 }
7699
7700 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7701         .is_in_guest            = kvm_is_in_guest,
7702         .is_user_mode           = kvm_is_user_mode,
7703         .get_guest_ip           = kvm_get_guest_ip,
7704         .handle_intel_pt_intr   = kvm_handle_intel_pt_intr,
7705 };
7706
7707 #ifdef CONFIG_X86_64
7708 static void pvclock_gtod_update_fn(struct work_struct *work)
7709 {
7710         struct kvm *kvm;
7711
7712         struct kvm_vcpu *vcpu;
7713         int i;
7714
7715         mutex_lock(&kvm_lock);
7716         list_for_each_entry(kvm, &vm_list, vm_list)
7717                 kvm_for_each_vcpu(i, vcpu, kvm)
7718                         kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7719         atomic_set(&kvm_guest_has_master_clock, 0);
7720         mutex_unlock(&kvm_lock);
7721 }
7722
7723 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7724
7725 /*
7726  * Notification about pvclock gtod data update.
7727  */
7728 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7729                                void *priv)
7730 {
7731         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7732         struct timekeeper *tk = priv;
7733
7734         update_pvclock_gtod(tk);
7735
7736         /* disable master clock if host does not trust, or does not
7737          * use, TSC based clocksource.
7738          */
7739         if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7740             atomic_read(&kvm_guest_has_master_clock) != 0)
7741                 queue_work(system_long_wq, &pvclock_gtod_work);
7742
7743         return 0;
7744 }
7745
7746 static struct notifier_block pvclock_gtod_notifier = {
7747         .notifier_call = pvclock_gtod_notify,
7748 };
7749 #endif
7750
7751 int kvm_arch_init(void *opaque)
7752 {
7753         struct kvm_x86_init_ops *ops = opaque;
7754         int r;
7755
7756         if (kvm_x86_ops.hardware_enable) {
7757                 printk(KERN_ERR "kvm: already loaded the other module\n");
7758                 r = -EEXIST;
7759                 goto out;
7760         }
7761
7762         if (!ops->cpu_has_kvm_support()) {
7763                 pr_err_ratelimited("kvm: no hardware support\n");
7764                 r = -EOPNOTSUPP;
7765                 goto out;
7766         }
7767         if (ops->disabled_by_bios()) {
7768                 pr_err_ratelimited("kvm: disabled by bios\n");
7769                 r = -EOPNOTSUPP;
7770                 goto out;
7771         }
7772
7773         /*
7774          * KVM explicitly assumes that the guest has an FPU and
7775          * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7776          * vCPU's FPU state as a fxregs_state struct.
7777          */
7778         if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7779                 printk(KERN_ERR "kvm: inadequate fpu\n");
7780                 r = -EOPNOTSUPP;
7781                 goto out;
7782         }
7783
7784         r = -ENOMEM;
7785         x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7786                                           __alignof__(struct fpu), SLAB_ACCOUNT,
7787                                           NULL);
7788         if (!x86_fpu_cache) {
7789                 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7790                 goto out;
7791         }
7792
7793         x86_emulator_cache = kvm_alloc_emulator_cache();
7794         if (!x86_emulator_cache) {
7795                 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7796                 goto out_free_x86_fpu_cache;
7797         }
7798
7799         user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
7800         if (!user_return_msrs) {
7801                 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
7802                 goto out_free_x86_emulator_cache;
7803         }
7804
7805         r = kvm_mmu_module_init();
7806         if (r)
7807                 goto out_free_percpu;
7808
7809         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7810                         PT_DIRTY_MASK, PT64_NX_MASK, 0,
7811                         PT_PRESENT_MASK, 0, sme_me_mask);
7812         kvm_timer_init();
7813
7814         perf_register_guest_info_callbacks(&kvm_guest_cbs);
7815
7816         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7817                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7818                 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7819         }
7820
7821         kvm_lapic_init();
7822         if (pi_inject_timer == -1)
7823                 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7824 #ifdef CONFIG_X86_64
7825         pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7826
7827         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7828                 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7829 #endif
7830
7831         return 0;
7832
7833 out_free_percpu:
7834         free_percpu(user_return_msrs);
7835 out_free_x86_emulator_cache:
7836         kmem_cache_destroy(x86_emulator_cache);
7837 out_free_x86_fpu_cache:
7838         kmem_cache_destroy(x86_fpu_cache);
7839 out:
7840         return r;
7841 }
7842
7843 void kvm_arch_exit(void)
7844 {
7845 #ifdef CONFIG_X86_64
7846         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7847                 clear_hv_tscchange_cb();
7848 #endif
7849         kvm_lapic_exit();
7850         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7851
7852         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7853                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7854                                             CPUFREQ_TRANSITION_NOTIFIER);
7855         cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7856 #ifdef CONFIG_X86_64
7857         pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7858 #endif
7859         kvm_x86_ops.hardware_enable = NULL;
7860         kvm_mmu_module_exit();
7861         free_percpu(user_return_msrs);
7862         kmem_cache_destroy(x86_fpu_cache);
7863 }
7864
7865 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7866 {
7867         ++vcpu->stat.halt_exits;
7868         if (lapic_in_kernel(vcpu)) {
7869                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7870                 return 1;
7871         } else {
7872                 vcpu->run->exit_reason = KVM_EXIT_HLT;
7873                 return 0;
7874         }
7875 }
7876 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7877
7878 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7879 {
7880         int ret = kvm_skip_emulated_instruction(vcpu);
7881         /*
7882          * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7883          * KVM_EXIT_DEBUG here.
7884          */
7885         return kvm_vcpu_halt(vcpu) && ret;
7886 }
7887 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7888
7889 #ifdef CONFIG_X86_64
7890 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7891                                 unsigned long clock_type)
7892 {
7893         struct kvm_clock_pairing clock_pairing;
7894         struct timespec64 ts;
7895         u64 cycle;
7896         int ret;
7897
7898         if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7899                 return -KVM_EOPNOTSUPP;
7900
7901         if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7902                 return -KVM_EOPNOTSUPP;
7903
7904         clock_pairing.sec = ts.tv_sec;
7905         clock_pairing.nsec = ts.tv_nsec;
7906         clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7907         clock_pairing.flags = 0;
7908         memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7909
7910         ret = 0;
7911         if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7912                             sizeof(struct kvm_clock_pairing)))
7913                 ret = -KVM_EFAULT;
7914
7915         return ret;
7916 }
7917 #endif
7918
7919 /*
7920  * kvm_pv_kick_cpu_op:  Kick a vcpu.
7921  *
7922  * @apicid - apicid of vcpu to be kicked.
7923  */
7924 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7925 {
7926         struct kvm_lapic_irq lapic_irq;
7927
7928         lapic_irq.shorthand = APIC_DEST_NOSHORT;
7929         lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
7930         lapic_irq.level = 0;
7931         lapic_irq.dest_id = apicid;
7932         lapic_irq.msi_redir_hint = false;
7933
7934         lapic_irq.delivery_mode = APIC_DM_REMRD;
7935         kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7936 }
7937
7938 bool kvm_apicv_activated(struct kvm *kvm)
7939 {
7940         return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
7941 }
7942 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
7943
7944 void kvm_apicv_init(struct kvm *kvm, bool enable)
7945 {
7946         if (enable)
7947                 clear_bit(APICV_INHIBIT_REASON_DISABLE,
7948                           &kvm->arch.apicv_inhibit_reasons);
7949         else
7950                 set_bit(APICV_INHIBIT_REASON_DISABLE,
7951                         &kvm->arch.apicv_inhibit_reasons);
7952 }
7953 EXPORT_SYMBOL_GPL(kvm_apicv_init);
7954
7955 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7956 {
7957         struct kvm_vcpu *target = NULL;
7958         struct kvm_apic_map *map;
7959
7960         rcu_read_lock();
7961         map = rcu_dereference(kvm->arch.apic_map);
7962
7963         if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7964                 target = map->phys_map[dest_id]->vcpu;
7965
7966         rcu_read_unlock();
7967
7968         if (target && READ_ONCE(target->ready))
7969                 kvm_vcpu_yield_to(target);
7970 }
7971
7972 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7973 {
7974         unsigned long nr, a0, a1, a2, a3, ret;
7975         int op_64_bit;
7976
7977         if (kvm_hv_hypercall_enabled(vcpu->kvm))
7978                 return kvm_hv_hypercall(vcpu);
7979
7980         nr = kvm_rax_read(vcpu);
7981         a0 = kvm_rbx_read(vcpu);
7982         a1 = kvm_rcx_read(vcpu);
7983         a2 = kvm_rdx_read(vcpu);
7984         a3 = kvm_rsi_read(vcpu);
7985
7986         trace_kvm_hypercall(nr, a0, a1, a2, a3);
7987
7988         op_64_bit = is_64_bit_mode(vcpu);
7989         if (!op_64_bit) {
7990                 nr &= 0xFFFFFFFF;
7991                 a0 &= 0xFFFFFFFF;
7992                 a1 &= 0xFFFFFFFF;
7993                 a2 &= 0xFFFFFFFF;
7994                 a3 &= 0xFFFFFFFF;
7995         }
7996
7997         if (kvm_x86_ops.get_cpl(vcpu) != 0) {
7998                 ret = -KVM_EPERM;
7999                 goto out;
8000         }
8001
8002         switch (nr) {
8003         case KVM_HC_VAPIC_POLL_IRQ:
8004                 ret = 0;
8005                 break;
8006         case KVM_HC_KICK_CPU:
8007                 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
8008                 kvm_sched_yield(vcpu->kvm, a1);
8009                 ret = 0;
8010                 break;
8011 #ifdef CONFIG_X86_64
8012         case KVM_HC_CLOCK_PAIRING:
8013                 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
8014                 break;
8015 #endif
8016         case KVM_HC_SEND_IPI:
8017                 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
8018                 break;
8019         case KVM_HC_SCHED_YIELD:
8020                 kvm_sched_yield(vcpu->kvm, a0);
8021                 ret = 0;
8022                 break;
8023         default:
8024                 ret = -KVM_ENOSYS;
8025                 break;
8026         }
8027 out:
8028         if (!op_64_bit)
8029                 ret = (u32)ret;
8030         kvm_rax_write(vcpu, ret);
8031
8032         ++vcpu->stat.hypercalls;
8033         return kvm_skip_emulated_instruction(vcpu);
8034 }
8035 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
8036
8037 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8038 {
8039         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8040         char instruction[3];
8041         unsigned long rip = kvm_rip_read(vcpu);
8042
8043         kvm_x86_ops.patch_hypercall(vcpu, instruction);
8044
8045         return emulator_write_emulated(ctxt, rip, instruction, 3,
8046                 &ctxt->exception);
8047 }
8048
8049 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
8050 {
8051         return vcpu->run->request_interrupt_window &&
8052                 likely(!pic_in_kernel(vcpu->kvm));
8053 }
8054
8055 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
8056 {
8057         struct kvm_run *kvm_run = vcpu->run;
8058
8059         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
8060         kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
8061         kvm_run->cr8 = kvm_get_cr8(vcpu);
8062         kvm_run->apic_base = kvm_get_apic_base(vcpu);
8063         kvm_run->ready_for_interrupt_injection =
8064                 pic_in_kernel(vcpu->kvm) ||
8065                 kvm_vcpu_ready_for_interrupt_injection(vcpu);
8066 }
8067
8068 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
8069 {
8070         int max_irr, tpr;
8071
8072         if (!kvm_x86_ops.update_cr8_intercept)
8073                 return;
8074
8075         if (!lapic_in_kernel(vcpu))
8076                 return;
8077
8078         if (vcpu->arch.apicv_active)
8079                 return;
8080
8081         if (!vcpu->arch.apic->vapic_addr)
8082                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8083         else
8084                 max_irr = -1;
8085
8086         if (max_irr != -1)
8087                 max_irr >>= 4;
8088
8089         tpr = kvm_lapic_get_cr8(vcpu);
8090
8091         kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr);
8092 }
8093
8094 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
8095 {
8096         int r;
8097         bool can_inject = true;
8098
8099         /* try to reinject previous events if any */
8100
8101         if (vcpu->arch.exception.injected) {
8102                 kvm_x86_ops.queue_exception(vcpu);
8103                 can_inject = false;
8104         }
8105         /*
8106          * Do not inject an NMI or interrupt if there is a pending
8107          * exception.  Exceptions and interrupts are recognized at
8108          * instruction boundaries, i.e. the start of an instruction.
8109          * Trap-like exceptions, e.g. #DB, have higher priority than
8110          * NMIs and interrupts, i.e. traps are recognized before an
8111          * NMI/interrupt that's pending on the same instruction.
8112          * Fault-like exceptions, e.g. #GP and #PF, are the lowest
8113          * priority, but are only generated (pended) during instruction
8114          * execution, i.e. a pending fault-like exception means the
8115          * fault occurred on the *previous* instruction and must be
8116          * serviced prior to recognizing any new events in order to
8117          * fully complete the previous instruction.
8118          */
8119         else if (!vcpu->arch.exception.pending) {
8120                 if (vcpu->arch.nmi_injected) {
8121                         kvm_x86_ops.set_nmi(vcpu);
8122                         can_inject = false;
8123                 } else if (vcpu->arch.interrupt.injected) {
8124                         kvm_x86_ops.set_irq(vcpu);
8125                         can_inject = false;
8126                 }
8127         }
8128
8129         WARN_ON_ONCE(vcpu->arch.exception.injected &&
8130                      vcpu->arch.exception.pending);
8131
8132         /*
8133          * Call check_nested_events() even if we reinjected a previous event
8134          * in order for caller to determine if it should require immediate-exit
8135          * from L2 to L1 due to pending L1 events which require exit
8136          * from L2 to L1.
8137          */
8138         if (is_guest_mode(vcpu)) {
8139                 r = kvm_x86_ops.nested_ops->check_events(vcpu);
8140                 if (r < 0)
8141                         goto busy;
8142         }
8143
8144         /* try to inject new event if pending */
8145         if (vcpu->arch.exception.pending) {
8146                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
8147                                         vcpu->arch.exception.has_error_code,
8148                                         vcpu->arch.exception.error_code);
8149
8150                 vcpu->arch.exception.pending = false;
8151                 vcpu->arch.exception.injected = true;
8152
8153                 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
8154                         __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
8155                                              X86_EFLAGS_RF);
8156
8157                 if (vcpu->arch.exception.nr == DB_VECTOR) {
8158                         kvm_deliver_exception_payload(vcpu);
8159                         if (vcpu->arch.dr7 & DR7_GD) {
8160                                 vcpu->arch.dr7 &= ~DR7_GD;
8161                                 kvm_update_dr7(vcpu);
8162                         }
8163                 }
8164
8165                 kvm_x86_ops.queue_exception(vcpu);
8166                 can_inject = false;
8167         }
8168
8169         /*
8170          * Finally, inject interrupt events.  If an event cannot be injected
8171          * due to architectural conditions (e.g. IF=0) a window-open exit
8172          * will re-request KVM_REQ_EVENT.  Sometimes however an event is pending
8173          * and can architecturally be injected, but we cannot do it right now:
8174          * an interrupt could have arrived just now and we have to inject it
8175          * as a vmexit, or there could already an event in the queue, which is
8176          * indicated by can_inject.  In that case we request an immediate exit
8177          * in order to make progress and get back here for another iteration.
8178          * The kvm_x86_ops hooks communicate this by returning -EBUSY.
8179          */
8180         if (vcpu->arch.smi_pending) {
8181                 r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY;
8182                 if (r < 0)
8183                         goto busy;
8184                 if (r) {
8185                         vcpu->arch.smi_pending = false;
8186                         ++vcpu->arch.smi_count;
8187                         enter_smm(vcpu);
8188                         can_inject = false;
8189                 } else
8190                         kvm_x86_ops.enable_smi_window(vcpu);
8191         }
8192
8193         if (vcpu->arch.nmi_pending) {
8194                 r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY;
8195                 if (r < 0)
8196                         goto busy;
8197                 if (r) {
8198                         --vcpu->arch.nmi_pending;
8199                         vcpu->arch.nmi_injected = true;
8200                         kvm_x86_ops.set_nmi(vcpu);
8201                         can_inject = false;
8202                         WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0);
8203                 }
8204                 if (vcpu->arch.nmi_pending)
8205                         kvm_x86_ops.enable_nmi_window(vcpu);
8206         }
8207
8208         if (kvm_cpu_has_injectable_intr(vcpu)) {
8209                 r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY;
8210                 if (r < 0)
8211                         goto busy;
8212                 if (r) {
8213                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
8214                         kvm_x86_ops.set_irq(vcpu);
8215                         WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0);
8216                 }
8217                 if (kvm_cpu_has_injectable_intr(vcpu))
8218                         kvm_x86_ops.enable_irq_window(vcpu);
8219         }
8220
8221         if (is_guest_mode(vcpu) &&
8222             kvm_x86_ops.nested_ops->hv_timer_pending &&
8223             kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
8224                 *req_immediate_exit = true;
8225
8226         WARN_ON(vcpu->arch.exception.pending);
8227         return;
8228
8229 busy:
8230         *req_immediate_exit = true;
8231         return;
8232 }
8233
8234 static void process_nmi(struct kvm_vcpu *vcpu)
8235 {
8236         unsigned limit = 2;
8237
8238         /*
8239          * x86 is limited to one NMI running, and one NMI pending after it.
8240          * If an NMI is already in progress, limit further NMIs to just one.
8241          * Otherwise, allow two (and we'll inject the first one immediately).
8242          */
8243         if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
8244                 limit = 1;
8245
8246         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
8247         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
8248         kvm_make_request(KVM_REQ_EVENT, vcpu);
8249 }
8250
8251 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
8252 {
8253         u32 flags = 0;
8254         flags |= seg->g       << 23;
8255         flags |= seg->db      << 22;
8256         flags |= seg->l       << 21;
8257         flags |= seg->avl     << 20;
8258         flags |= seg->present << 15;
8259         flags |= seg->dpl     << 13;
8260         flags |= seg->s       << 12;
8261         flags |= seg->type    << 8;
8262         return flags;
8263 }
8264
8265 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
8266 {
8267         struct kvm_segment seg;
8268         int offset;
8269
8270         kvm_get_segment(vcpu, &seg, n);
8271         put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
8272
8273         if (n < 3)
8274                 offset = 0x7f84 + n * 12;
8275         else
8276                 offset = 0x7f2c + (n - 3) * 12;
8277
8278         put_smstate(u32, buf, offset + 8, seg.base);
8279         put_smstate(u32, buf, offset + 4, seg.limit);
8280         put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
8281 }
8282
8283 #ifdef CONFIG_X86_64
8284 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
8285 {
8286         struct kvm_segment seg;
8287         int offset;
8288         u16 flags;
8289
8290         kvm_get_segment(vcpu, &seg, n);
8291         offset = 0x7e00 + n * 16;
8292
8293         flags = enter_smm_get_segment_flags(&seg) >> 8;
8294         put_smstate(u16, buf, offset, seg.selector);
8295         put_smstate(u16, buf, offset + 2, flags);
8296         put_smstate(u32, buf, offset + 4, seg.limit);
8297         put_smstate(u64, buf, offset + 8, seg.base);
8298 }
8299 #endif
8300
8301 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
8302 {
8303         struct desc_ptr dt;
8304         struct kvm_segment seg;
8305         unsigned long val;
8306         int i;
8307
8308         put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
8309         put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
8310         put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
8311         put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
8312
8313         for (i = 0; i < 8; i++)
8314                 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
8315
8316         kvm_get_dr(vcpu, 6, &val);
8317         put_smstate(u32, buf, 0x7fcc, (u32)val);
8318         kvm_get_dr(vcpu, 7, &val);
8319         put_smstate(u32, buf, 0x7fc8, (u32)val);
8320
8321         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8322         put_smstate(u32, buf, 0x7fc4, seg.selector);
8323         put_smstate(u32, buf, 0x7f64, seg.base);
8324         put_smstate(u32, buf, 0x7f60, seg.limit);
8325         put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
8326
8327         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8328         put_smstate(u32, buf, 0x7fc0, seg.selector);
8329         put_smstate(u32, buf, 0x7f80, seg.base);
8330         put_smstate(u32, buf, 0x7f7c, seg.limit);
8331         put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
8332
8333         kvm_x86_ops.get_gdt(vcpu, &dt);
8334         put_smstate(u32, buf, 0x7f74, dt.address);
8335         put_smstate(u32, buf, 0x7f70, dt.size);
8336
8337         kvm_x86_ops.get_idt(vcpu, &dt);
8338         put_smstate(u32, buf, 0x7f58, dt.address);
8339         put_smstate(u32, buf, 0x7f54, dt.size);
8340
8341         for (i = 0; i < 6; i++)
8342                 enter_smm_save_seg_32(vcpu, buf, i);
8343
8344         put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
8345
8346         /* revision id */
8347         put_smstate(u32, buf, 0x7efc, 0x00020000);
8348         put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
8349 }
8350
8351 #ifdef CONFIG_X86_64
8352 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
8353 {
8354         struct desc_ptr dt;
8355         struct kvm_segment seg;
8356         unsigned long val;
8357         int i;
8358
8359         for (i = 0; i < 16; i++)
8360                 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
8361
8362         put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
8363         put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
8364
8365         kvm_get_dr(vcpu, 6, &val);
8366         put_smstate(u64, buf, 0x7f68, val);
8367         kvm_get_dr(vcpu, 7, &val);
8368         put_smstate(u64, buf, 0x7f60, val);
8369
8370         put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
8371         put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
8372         put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
8373
8374         put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
8375
8376         /* revision id */
8377         put_smstate(u32, buf, 0x7efc, 0x00020064);
8378
8379         put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
8380
8381         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8382         put_smstate(u16, buf, 0x7e90, seg.selector);
8383         put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
8384         put_smstate(u32, buf, 0x7e94, seg.limit);
8385         put_smstate(u64, buf, 0x7e98, seg.base);
8386
8387         kvm_x86_ops.get_idt(vcpu, &dt);
8388         put_smstate(u32, buf, 0x7e84, dt.size);
8389         put_smstate(u64, buf, 0x7e88, dt.address);
8390
8391         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8392         put_smstate(u16, buf, 0x7e70, seg.selector);
8393         put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
8394         put_smstate(u32, buf, 0x7e74, seg.limit);
8395         put_smstate(u64, buf, 0x7e78, seg.base);
8396
8397         kvm_x86_ops.get_gdt(vcpu, &dt);
8398         put_smstate(u32, buf, 0x7e64, dt.size);
8399         put_smstate(u64, buf, 0x7e68, dt.address);
8400
8401         for (i = 0; i < 6; i++)
8402                 enter_smm_save_seg_64(vcpu, buf, i);
8403 }
8404 #endif
8405
8406 static void enter_smm(struct kvm_vcpu *vcpu)
8407 {
8408         struct kvm_segment cs, ds;
8409         struct desc_ptr dt;
8410         char buf[512];
8411         u32 cr0;
8412
8413         trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
8414         memset(buf, 0, 512);
8415 #ifdef CONFIG_X86_64
8416         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8417                 enter_smm_save_state_64(vcpu, buf);
8418         else
8419 #endif
8420                 enter_smm_save_state_32(vcpu, buf);
8421
8422         /*
8423          * Give pre_enter_smm() a chance to make ISA-specific changes to the
8424          * vCPU state (e.g. leave guest mode) after we've saved the state into
8425          * the SMM state-save area.
8426          */
8427         kvm_x86_ops.pre_enter_smm(vcpu, buf);
8428
8429         vcpu->arch.hflags |= HF_SMM_MASK;
8430         kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
8431
8432         if (kvm_x86_ops.get_nmi_mask(vcpu))
8433                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
8434         else
8435                 kvm_x86_ops.set_nmi_mask(vcpu, true);
8436
8437         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
8438         kvm_rip_write(vcpu, 0x8000);
8439
8440         cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
8441         kvm_x86_ops.set_cr0(vcpu, cr0);
8442         vcpu->arch.cr0 = cr0;
8443
8444         kvm_x86_ops.set_cr4(vcpu, 0);
8445
8446         /* Undocumented: IDT limit is set to zero on entry to SMM.  */
8447         dt.address = dt.size = 0;
8448         kvm_x86_ops.set_idt(vcpu, &dt);
8449
8450         __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
8451
8452         cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
8453         cs.base = vcpu->arch.smbase;
8454
8455         ds.selector = 0;
8456         ds.base = 0;
8457
8458         cs.limit    = ds.limit = 0xffffffff;
8459         cs.type     = ds.type = 0x3;
8460         cs.dpl      = ds.dpl = 0;
8461         cs.db       = ds.db = 0;
8462         cs.s        = ds.s = 1;
8463         cs.l        = ds.l = 0;
8464         cs.g        = ds.g = 1;
8465         cs.avl      = ds.avl = 0;
8466         cs.present  = ds.present = 1;
8467         cs.unusable = ds.unusable = 0;
8468         cs.padding  = ds.padding = 0;
8469
8470         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8471         kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8472         kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8473         kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8474         kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8475         kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8476
8477 #ifdef CONFIG_X86_64
8478         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8479                 kvm_x86_ops.set_efer(vcpu, 0);
8480 #endif
8481
8482         kvm_update_cpuid_runtime(vcpu);
8483         kvm_mmu_reset_context(vcpu);
8484 }
8485
8486 static void process_smi(struct kvm_vcpu *vcpu)
8487 {
8488         vcpu->arch.smi_pending = true;
8489         kvm_make_request(KVM_REQ_EVENT, vcpu);
8490 }
8491
8492 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8493                                        unsigned long *vcpu_bitmap)
8494 {
8495         cpumask_var_t cpus;
8496
8497         zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8498
8499         kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8500                                     NULL, vcpu_bitmap, cpus);
8501
8502         free_cpumask_var(cpus);
8503 }
8504
8505 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8506 {
8507         kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8508 }
8509
8510 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8511 {
8512         if (!lapic_in_kernel(vcpu))
8513                 return;
8514
8515         vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8516         kvm_apic_update_apicv(vcpu);
8517         kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu);
8518 }
8519 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8520
8521 /*
8522  * NOTE: Do not hold any lock prior to calling this.
8523  *
8524  * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8525  * locked, because it calls __x86_set_memory_region() which does
8526  * synchronize_srcu(&kvm->srcu).
8527  */
8528 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8529 {
8530         struct kvm_vcpu *except;
8531         unsigned long old, new, expected;
8532
8533         if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8534             !kvm_x86_ops.check_apicv_inhibit_reasons(bit))
8535                 return;
8536
8537         old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8538         do {
8539                 expected = new = old;
8540                 if (activate)
8541                         __clear_bit(bit, &new);
8542                 else
8543                         __set_bit(bit, &new);
8544                 if (new == old)
8545                         break;
8546                 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8547         } while (old != expected);
8548
8549         if (!!old == !!new)
8550                 return;
8551
8552         trace_kvm_apicv_update_request(activate, bit);
8553         if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8554                 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate);
8555
8556         /*
8557          * Sending request to update APICV for all other vcpus,
8558          * while update the calling vcpu immediately instead of
8559          * waiting for another #VMEXIT to handle the request.
8560          */
8561         except = kvm_get_running_vcpu();
8562         kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE,
8563                                          except);
8564         if (except)
8565                 kvm_vcpu_update_apicv(except);
8566 }
8567 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8568
8569 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8570 {
8571         if (!kvm_apic_present(vcpu))
8572                 return;
8573
8574         bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8575
8576         if (irqchip_split(vcpu->kvm))
8577                 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8578         else {
8579                 if (vcpu->arch.apicv_active)
8580                         kvm_x86_ops.sync_pir_to_irr(vcpu);
8581                 if (ioapic_in_kernel(vcpu->kvm))
8582                         kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8583         }
8584
8585         if (is_guest_mode(vcpu))
8586                 vcpu->arch.load_eoi_exitmap_pending = true;
8587         else
8588                 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8589 }
8590
8591 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8592 {
8593         u64 eoi_exit_bitmap[4];
8594
8595         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8596                 return;
8597
8598         bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8599                   vcpu_to_synic(vcpu)->vec_bitmap, 256);
8600         kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8601 }
8602
8603 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8604                                             unsigned long start, unsigned long end)
8605 {
8606         unsigned long apic_address;
8607
8608         /*
8609          * The physical address of apic access page is stored in the VMCS.
8610          * Update it when it becomes invalid.
8611          */
8612         apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8613         if (start <= apic_address && apic_address < end)
8614                 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8615 }
8616
8617 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8618 {
8619         if (!lapic_in_kernel(vcpu))
8620                 return;
8621
8622         if (!kvm_x86_ops.set_apic_access_page_addr)
8623                 return;
8624
8625         kvm_x86_ops.set_apic_access_page_addr(vcpu);
8626 }
8627
8628 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8629 {
8630         smp_send_reschedule(vcpu->cpu);
8631 }
8632 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8633
8634 /*
8635  * Returns 1 to let vcpu_run() continue the guest execution loop without
8636  * exiting to the userspace.  Otherwise, the value will be returned to the
8637  * userspace.
8638  */
8639 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8640 {
8641         int r;
8642         bool req_int_win =
8643                 dm_request_for_irq_injection(vcpu) &&
8644                 kvm_cpu_accept_dm_intr(vcpu);
8645         fastpath_t exit_fastpath;
8646
8647         bool req_immediate_exit = false;
8648
8649         if (kvm_request_pending(vcpu)) {
8650                 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
8651                         if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
8652                                 r = 0;
8653                                 goto out;
8654                         }
8655                 }
8656                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8657                         kvm_mmu_unload(vcpu);
8658                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8659                         __kvm_migrate_timers(vcpu);
8660                 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8661                         kvm_gen_update_masterclock(vcpu->kvm);
8662                 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8663                         kvm_gen_kvmclock_update(vcpu);
8664                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8665                         r = kvm_guest_time_update(vcpu);
8666                         if (unlikely(r))
8667                                 goto out;
8668                 }
8669                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8670                         kvm_mmu_sync_roots(vcpu);
8671                 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8672                         kvm_mmu_load_pgd(vcpu);
8673                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
8674                         kvm_vcpu_flush_tlb_all(vcpu);
8675
8676                         /* Flushing all ASIDs flushes the current ASID... */
8677                         kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
8678                 }
8679                 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
8680                         kvm_vcpu_flush_tlb_current(vcpu);
8681                 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu))
8682                         kvm_vcpu_flush_tlb_guest(vcpu);
8683
8684                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8685                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8686                         r = 0;
8687                         goto out;
8688                 }
8689                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8690                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8691                         vcpu->mmio_needed = 0;
8692                         r = 0;
8693                         goto out;
8694                 }
8695                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8696                         /* Page is swapped out. Do synthetic halt */
8697                         vcpu->arch.apf.halted = true;
8698                         r = 1;
8699                         goto out;
8700                 }
8701                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8702                         record_steal_time(vcpu);
8703                 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8704                         process_smi(vcpu);
8705                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8706                         process_nmi(vcpu);
8707                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8708                         kvm_pmu_handle_event(vcpu);
8709                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8710                         kvm_pmu_deliver_pmi(vcpu);
8711                 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8712                         BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8713                         if (test_bit(vcpu->arch.pending_ioapic_eoi,
8714                                      vcpu->arch.ioapic_handled_vectors)) {
8715                                 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8716                                 vcpu->run->eoi.vector =
8717                                                 vcpu->arch.pending_ioapic_eoi;
8718                                 r = 0;
8719                                 goto out;
8720                         }
8721                 }
8722                 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8723                         vcpu_scan_ioapic(vcpu);
8724                 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8725                         vcpu_load_eoi_exitmap(vcpu);
8726                 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8727                         kvm_vcpu_reload_apic_access_page(vcpu);
8728                 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8729                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8730                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8731                         r = 0;
8732                         goto out;
8733                 }
8734                 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8735                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8736                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8737                         r = 0;
8738                         goto out;
8739                 }
8740                 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8741                         vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8742                         vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8743                         r = 0;
8744                         goto out;
8745                 }
8746
8747                 /*
8748                  * KVM_REQ_HV_STIMER has to be processed after
8749                  * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8750                  * depend on the guest clock being up-to-date
8751                  */
8752                 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8753                         kvm_hv_process_stimers(vcpu);
8754                 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8755                         kvm_vcpu_update_apicv(vcpu);
8756                 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
8757                         kvm_check_async_pf_completion(vcpu);
8758                 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
8759                         kvm_x86_ops.msr_filter_changed(vcpu);
8760         }
8761
8762         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8763                 ++vcpu->stat.req_event;
8764                 kvm_apic_accept_events(vcpu);
8765                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8766                         r = 1;
8767                         goto out;
8768                 }
8769
8770                 inject_pending_event(vcpu, &req_immediate_exit);
8771                 if (req_int_win)
8772                         kvm_x86_ops.enable_irq_window(vcpu);
8773
8774                 if (kvm_lapic_enabled(vcpu)) {
8775                         update_cr8_intercept(vcpu);
8776                         kvm_lapic_sync_to_vapic(vcpu);
8777                 }
8778         }
8779
8780         r = kvm_mmu_reload(vcpu);
8781         if (unlikely(r)) {
8782                 goto cancel_injection;
8783         }
8784
8785         preempt_disable();
8786
8787         kvm_x86_ops.prepare_guest_switch(vcpu);
8788
8789         /*
8790          * Disable IRQs before setting IN_GUEST_MODE.  Posted interrupt
8791          * IPI are then delayed after guest entry, which ensures that they
8792          * result in virtual interrupt delivery.
8793          */
8794         local_irq_disable();
8795         vcpu->mode = IN_GUEST_MODE;
8796
8797         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8798
8799         /*
8800          * 1) We should set ->mode before checking ->requests.  Please see
8801          * the comment in kvm_vcpu_exiting_guest_mode().
8802          *
8803          * 2) For APICv, we should set ->mode before checking PID.ON. This
8804          * pairs with the memory barrier implicit in pi_test_and_set_on
8805          * (see vmx_deliver_posted_interrupt).
8806          *
8807          * 3) This also orders the write to mode from any reads to the page
8808          * tables done while the VCPU is running.  Please see the comment
8809          * in kvm_flush_remote_tlbs.
8810          */
8811         smp_mb__after_srcu_read_unlock();
8812
8813         /*
8814          * This handles the case where a posted interrupt was
8815          * notified with kvm_vcpu_kick.
8816          */
8817         if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8818                 kvm_x86_ops.sync_pir_to_irr(vcpu);
8819
8820         if (kvm_vcpu_exit_request(vcpu)) {
8821                 vcpu->mode = OUTSIDE_GUEST_MODE;
8822                 smp_wmb();
8823                 local_irq_enable();
8824                 preempt_enable();
8825                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8826                 r = 1;
8827                 goto cancel_injection;
8828         }
8829
8830         if (req_immediate_exit) {
8831                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8832                 kvm_x86_ops.request_immediate_exit(vcpu);
8833         }
8834
8835         trace_kvm_entry(vcpu);
8836
8837         fpregs_assert_state_consistent();
8838         if (test_thread_flag(TIF_NEED_FPU_LOAD))
8839                 switch_fpu_return();
8840
8841         if (unlikely(vcpu->arch.switch_db_regs)) {
8842                 set_debugreg(0, 7);
8843                 set_debugreg(vcpu->arch.eff_db[0], 0);
8844                 set_debugreg(vcpu->arch.eff_db[1], 1);
8845                 set_debugreg(vcpu->arch.eff_db[2], 2);
8846                 set_debugreg(vcpu->arch.eff_db[3], 3);
8847                 set_debugreg(vcpu->arch.dr6, 6);
8848                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8849         }
8850
8851         exit_fastpath = kvm_x86_ops.run(vcpu);
8852
8853         /*
8854          * Do this here before restoring debug registers on the host.  And
8855          * since we do this before handling the vmexit, a DR access vmexit
8856          * can (a) read the correct value of the debug registers, (b) set
8857          * KVM_DEBUGREG_WONT_EXIT again.
8858          */
8859         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8860                 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8861                 kvm_x86_ops.sync_dirty_debug_regs(vcpu);
8862                 kvm_update_dr0123(vcpu);
8863                 kvm_update_dr7(vcpu);
8864                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8865         }
8866
8867         /*
8868          * If the guest has used debug registers, at least dr7
8869          * will be disabled while returning to the host.
8870          * If we don't have active breakpoints in the host, we don't
8871          * care about the messed up debug address registers. But if
8872          * we have some of them active, restore the old state.
8873          */
8874         if (hw_breakpoint_active())
8875                 hw_breakpoint_restore();
8876
8877         vcpu->arch.last_vmentry_cpu = vcpu->cpu;
8878         vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8879
8880         vcpu->mode = OUTSIDE_GUEST_MODE;
8881         smp_wmb();
8882
8883         kvm_x86_ops.handle_exit_irqoff(vcpu);
8884
8885         /*
8886          * Consume any pending interrupts, including the possible source of
8887          * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8888          * An instruction is required after local_irq_enable() to fully unblock
8889          * interrupts on processors that implement an interrupt shadow, the
8890          * stat.exits increment will do nicely.
8891          */
8892         kvm_before_interrupt(vcpu);
8893         local_irq_enable();
8894         ++vcpu->stat.exits;
8895         local_irq_disable();
8896         kvm_after_interrupt(vcpu);
8897
8898         if (lapic_in_kernel(vcpu)) {
8899                 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8900                 if (delta != S64_MIN) {
8901                         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8902                         vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8903                 }
8904         }
8905
8906         local_irq_enable();
8907         preempt_enable();
8908
8909         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8910
8911         /*
8912          * Profile KVM exit RIPs:
8913          */
8914         if (unlikely(prof_on == KVM_PROFILING)) {
8915                 unsigned long rip = kvm_rip_read(vcpu);
8916                 profile_hit(KVM_PROFILING, (void *)rip);
8917         }
8918
8919         if (unlikely(vcpu->arch.tsc_always_catchup))
8920                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8921
8922         if (vcpu->arch.apic_attention)
8923                 kvm_lapic_sync_from_vapic(vcpu);
8924
8925         r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath);
8926         return r;
8927
8928 cancel_injection:
8929         if (req_immediate_exit)
8930                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8931         kvm_x86_ops.cancel_injection(vcpu);
8932         if (unlikely(vcpu->arch.apic_attention))
8933                 kvm_lapic_sync_from_vapic(vcpu);
8934 out:
8935         return r;
8936 }
8937
8938 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8939 {
8940         if (!kvm_arch_vcpu_runnable(vcpu) &&
8941             (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) {
8942                 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8943                 kvm_vcpu_block(vcpu);
8944                 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8945
8946                 if (kvm_x86_ops.post_block)
8947                         kvm_x86_ops.post_block(vcpu);
8948
8949                 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8950                         return 1;
8951         }
8952
8953         kvm_apic_accept_events(vcpu);
8954         switch(vcpu->arch.mp_state) {
8955         case KVM_MP_STATE_HALTED:
8956                 vcpu->arch.pv.pv_unhalted = false;
8957                 vcpu->arch.mp_state =
8958                         KVM_MP_STATE_RUNNABLE;
8959                 fallthrough;
8960         case KVM_MP_STATE_RUNNABLE:
8961                 vcpu->arch.apf.halted = false;
8962                 break;
8963         case KVM_MP_STATE_INIT_RECEIVED:
8964                 break;
8965         default:
8966                 return -EINTR;
8967         }
8968         return 1;
8969 }
8970
8971 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8972 {
8973         if (is_guest_mode(vcpu))
8974                 kvm_x86_ops.nested_ops->check_events(vcpu);
8975
8976         return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8977                 !vcpu->arch.apf.halted);
8978 }
8979
8980 static int vcpu_run(struct kvm_vcpu *vcpu)
8981 {
8982         int r;
8983         struct kvm *kvm = vcpu->kvm;
8984
8985         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8986         vcpu->arch.l1tf_flush_l1d = true;
8987
8988         for (;;) {
8989                 if (kvm_vcpu_running(vcpu)) {
8990                         r = vcpu_enter_guest(vcpu);
8991                 } else {
8992                         r = vcpu_block(kvm, vcpu);
8993                 }
8994
8995                 if (r <= 0)
8996                         break;
8997
8998                 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8999                 if (kvm_cpu_has_pending_timer(vcpu))
9000                         kvm_inject_pending_timer_irqs(vcpu);
9001
9002                 if (dm_request_for_irq_injection(vcpu) &&
9003                         kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
9004                         r = 0;
9005                         vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
9006                         ++vcpu->stat.request_irq_exits;
9007                         break;
9008                 }
9009
9010                 if (__xfer_to_guest_mode_work_pending()) {
9011                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9012                         r = xfer_to_guest_mode_handle_work(vcpu);
9013                         if (r)
9014                                 return r;
9015                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9016                 }
9017         }
9018
9019         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9020
9021         return r;
9022 }
9023
9024 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
9025 {
9026         int r;
9027
9028         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9029         r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
9030         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
9031         return r;
9032 }
9033
9034 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
9035 {
9036         BUG_ON(!vcpu->arch.pio.count);
9037
9038         return complete_emulated_io(vcpu);
9039 }
9040
9041 /*
9042  * Implements the following, as a state machine:
9043  *
9044  * read:
9045  *   for each fragment
9046  *     for each mmio piece in the fragment
9047  *       write gpa, len
9048  *       exit
9049  *       copy data
9050  *   execute insn
9051  *
9052  * write:
9053  *   for each fragment
9054  *     for each mmio piece in the fragment
9055  *       write gpa, len
9056  *       copy data
9057  *       exit
9058  */
9059 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
9060 {
9061         struct kvm_run *run = vcpu->run;
9062         struct kvm_mmio_fragment *frag;
9063         unsigned len;
9064
9065         BUG_ON(!vcpu->mmio_needed);
9066
9067         /* Complete previous fragment */
9068         frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
9069         len = min(8u, frag->len);
9070         if (!vcpu->mmio_is_write)
9071                 memcpy(frag->data, run->mmio.data, len);
9072
9073         if (frag->len <= 8) {
9074                 /* Switch to the next fragment. */
9075                 frag++;
9076                 vcpu->mmio_cur_fragment++;
9077         } else {
9078                 /* Go forward to the next mmio piece. */
9079                 frag->data += len;
9080                 frag->gpa += len;
9081                 frag->len -= len;
9082         }
9083
9084         if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
9085                 vcpu->mmio_needed = 0;
9086
9087                 /* FIXME: return into emulator if single-stepping.  */
9088                 if (vcpu->mmio_is_write)
9089                         return 1;
9090                 vcpu->mmio_read_completed = 1;
9091                 return complete_emulated_io(vcpu);
9092         }
9093
9094         run->exit_reason = KVM_EXIT_MMIO;
9095         run->mmio.phys_addr = frag->gpa;
9096         if (vcpu->mmio_is_write)
9097                 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
9098         run->mmio.len = min(8u, frag->len);
9099         run->mmio.is_write = vcpu->mmio_is_write;
9100         vcpu->arch.complete_userspace_io = complete_emulated_mmio;
9101         return 0;
9102 }
9103
9104 static void kvm_save_current_fpu(struct fpu *fpu)
9105 {
9106         /*
9107          * If the target FPU state is not resident in the CPU registers, just
9108          * memcpy() from current, else save CPU state directly to the target.
9109          */
9110         if (test_thread_flag(TIF_NEED_FPU_LOAD))
9111                 memcpy(&fpu->state, &current->thread.fpu.state,
9112                        fpu_kernel_xstate_size);
9113         else
9114                 copy_fpregs_to_fpstate(fpu);
9115 }
9116
9117 /* Swap (qemu) user FPU context for the guest FPU context. */
9118 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
9119 {
9120         fpregs_lock();
9121
9122         kvm_save_current_fpu(vcpu->arch.user_fpu);
9123
9124         /* PKRU is separately restored in kvm_x86_ops.run.  */
9125         __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
9126                                 ~XFEATURE_MASK_PKRU);
9127
9128         fpregs_mark_activate();
9129         fpregs_unlock();
9130
9131         trace_kvm_fpu(1);
9132 }
9133
9134 /* When vcpu_run ends, restore user space FPU context. */
9135 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
9136 {
9137         fpregs_lock();
9138
9139         kvm_save_current_fpu(vcpu->arch.guest_fpu);
9140
9141         copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
9142
9143         fpregs_mark_activate();
9144         fpregs_unlock();
9145
9146         ++vcpu->stat.fpu_reload;
9147         trace_kvm_fpu(0);
9148 }
9149
9150 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
9151 {
9152         struct kvm_run *kvm_run = vcpu->run;
9153         int r;
9154
9155         vcpu_load(vcpu);
9156         kvm_sigset_activate(vcpu);
9157         kvm_load_guest_fpu(vcpu);
9158
9159         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
9160                 if (kvm_run->immediate_exit) {
9161                         r = -EINTR;
9162                         goto out;
9163                 }
9164                 kvm_vcpu_block(vcpu);
9165                 kvm_apic_accept_events(vcpu);
9166                 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
9167                 r = -EAGAIN;
9168                 if (signal_pending(current)) {
9169                         r = -EINTR;
9170                         kvm_run->exit_reason = KVM_EXIT_INTR;
9171                         ++vcpu->stat.signal_exits;
9172                 }
9173                 goto out;
9174         }
9175
9176         if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
9177                 r = -EINVAL;
9178                 goto out;
9179         }
9180
9181         if (kvm_run->kvm_dirty_regs) {
9182                 r = sync_regs(vcpu);
9183                 if (r != 0)
9184                         goto out;
9185         }
9186
9187         /* re-sync apic's tpr */
9188         if (!lapic_in_kernel(vcpu)) {
9189                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
9190                         r = -EINVAL;
9191                         goto out;
9192                 }
9193         }
9194
9195         if (unlikely(vcpu->arch.complete_userspace_io)) {
9196                 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
9197                 vcpu->arch.complete_userspace_io = NULL;
9198                 r = cui(vcpu);
9199                 if (r <= 0)
9200                         goto out;
9201         } else
9202                 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
9203
9204         if (kvm_run->immediate_exit)
9205                 r = -EINTR;
9206         else
9207                 r = vcpu_run(vcpu);
9208
9209 out:
9210         kvm_put_guest_fpu(vcpu);
9211         if (kvm_run->kvm_valid_regs)
9212                 store_regs(vcpu);
9213         post_kvm_run_save(vcpu);
9214         kvm_sigset_deactivate(vcpu);
9215
9216         vcpu_put(vcpu);
9217         return r;
9218 }
9219
9220 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9221 {
9222         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
9223                 /*
9224                  * We are here if userspace calls get_regs() in the middle of
9225                  * instruction emulation. Registers state needs to be copied
9226                  * back from emulation context to vcpu. Userspace shouldn't do
9227                  * that usually, but some bad designed PV devices (vmware
9228                  * backdoor interface) need this to work
9229                  */
9230                 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
9231                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9232         }
9233         regs->rax = kvm_rax_read(vcpu);
9234         regs->rbx = kvm_rbx_read(vcpu);
9235         regs->rcx = kvm_rcx_read(vcpu);
9236         regs->rdx = kvm_rdx_read(vcpu);
9237         regs->rsi = kvm_rsi_read(vcpu);
9238         regs->rdi = kvm_rdi_read(vcpu);
9239         regs->rsp = kvm_rsp_read(vcpu);
9240         regs->rbp = kvm_rbp_read(vcpu);
9241 #ifdef CONFIG_X86_64
9242         regs->r8 = kvm_r8_read(vcpu);
9243         regs->r9 = kvm_r9_read(vcpu);
9244         regs->r10 = kvm_r10_read(vcpu);
9245         regs->r11 = kvm_r11_read(vcpu);
9246         regs->r12 = kvm_r12_read(vcpu);
9247         regs->r13 = kvm_r13_read(vcpu);
9248         regs->r14 = kvm_r14_read(vcpu);
9249         regs->r15 = kvm_r15_read(vcpu);
9250 #endif
9251
9252         regs->rip = kvm_rip_read(vcpu);
9253         regs->rflags = kvm_get_rflags(vcpu);
9254 }
9255
9256 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9257 {
9258         vcpu_load(vcpu);
9259         __get_regs(vcpu, regs);
9260         vcpu_put(vcpu);
9261         return 0;
9262 }
9263
9264 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9265 {
9266         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
9267         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9268
9269         kvm_rax_write(vcpu, regs->rax);
9270         kvm_rbx_write(vcpu, regs->rbx);
9271         kvm_rcx_write(vcpu, regs->rcx);
9272         kvm_rdx_write(vcpu, regs->rdx);
9273         kvm_rsi_write(vcpu, regs->rsi);
9274         kvm_rdi_write(vcpu, regs->rdi);
9275         kvm_rsp_write(vcpu, regs->rsp);
9276         kvm_rbp_write(vcpu, regs->rbp);
9277 #ifdef CONFIG_X86_64
9278         kvm_r8_write(vcpu, regs->r8);
9279         kvm_r9_write(vcpu, regs->r9);
9280         kvm_r10_write(vcpu, regs->r10);
9281         kvm_r11_write(vcpu, regs->r11);
9282         kvm_r12_write(vcpu, regs->r12);
9283         kvm_r13_write(vcpu, regs->r13);
9284         kvm_r14_write(vcpu, regs->r14);
9285         kvm_r15_write(vcpu, regs->r15);
9286 #endif
9287
9288         kvm_rip_write(vcpu, regs->rip);
9289         kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
9290
9291         vcpu->arch.exception.pending = false;
9292
9293         kvm_make_request(KVM_REQ_EVENT, vcpu);
9294 }
9295
9296 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9297 {
9298         vcpu_load(vcpu);
9299         __set_regs(vcpu, regs);
9300         vcpu_put(vcpu);
9301         return 0;
9302 }
9303
9304 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
9305 {
9306         struct kvm_segment cs;
9307
9308         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9309         *db = cs.db;
9310         *l = cs.l;
9311 }
9312 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
9313
9314 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9315 {
9316         struct desc_ptr dt;
9317
9318         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9319         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9320         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9321         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9322         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9323         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9324
9325         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9326         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9327
9328         kvm_x86_ops.get_idt(vcpu, &dt);
9329         sregs->idt.limit = dt.size;
9330         sregs->idt.base = dt.address;
9331         kvm_x86_ops.get_gdt(vcpu, &dt);
9332         sregs->gdt.limit = dt.size;
9333         sregs->gdt.base = dt.address;
9334
9335         sregs->cr0 = kvm_read_cr0(vcpu);
9336         sregs->cr2 = vcpu->arch.cr2;
9337         sregs->cr3 = kvm_read_cr3(vcpu);
9338         sregs->cr4 = kvm_read_cr4(vcpu);
9339         sregs->cr8 = kvm_get_cr8(vcpu);
9340         sregs->efer = vcpu->arch.efer;
9341         sregs->apic_base = kvm_get_apic_base(vcpu);
9342
9343         memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
9344
9345         if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
9346                 set_bit(vcpu->arch.interrupt.nr,
9347                         (unsigned long *)sregs->interrupt_bitmap);
9348 }
9349
9350 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
9351                                   struct kvm_sregs *sregs)
9352 {
9353         vcpu_load(vcpu);
9354         __get_sregs(vcpu, sregs);
9355         vcpu_put(vcpu);
9356         return 0;
9357 }
9358
9359 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
9360                                     struct kvm_mp_state *mp_state)
9361 {
9362         vcpu_load(vcpu);
9363         if (kvm_mpx_supported())
9364                 kvm_load_guest_fpu(vcpu);
9365
9366         kvm_apic_accept_events(vcpu);
9367         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
9368                                         vcpu->arch.pv.pv_unhalted)
9369                 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
9370         else
9371                 mp_state->mp_state = vcpu->arch.mp_state;
9372
9373         if (kvm_mpx_supported())
9374                 kvm_put_guest_fpu(vcpu);
9375         vcpu_put(vcpu);
9376         return 0;
9377 }
9378
9379 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
9380                                     struct kvm_mp_state *mp_state)
9381 {
9382         int ret = -EINVAL;
9383
9384         vcpu_load(vcpu);
9385
9386         if (!lapic_in_kernel(vcpu) &&
9387             mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
9388                 goto out;
9389
9390         /*
9391          * KVM_MP_STATE_INIT_RECEIVED means the processor is in
9392          * INIT state; latched init should be reported using
9393          * KVM_SET_VCPU_EVENTS, so reject it here.
9394          */
9395         if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
9396             (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
9397              mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
9398                 goto out;
9399
9400         if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
9401                 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
9402                 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
9403         } else
9404                 vcpu->arch.mp_state = mp_state->mp_state;
9405         kvm_make_request(KVM_REQ_EVENT, vcpu);
9406
9407         ret = 0;
9408 out:
9409         vcpu_put(vcpu);
9410         return ret;
9411 }
9412
9413 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
9414                     int reason, bool has_error_code, u32 error_code)
9415 {
9416         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9417         int ret;
9418
9419         init_emulate_ctxt(vcpu);
9420
9421         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9422                                    has_error_code, error_code);
9423         if (ret) {
9424                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9425                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
9426                 vcpu->run->internal.ndata = 0;
9427                 return 0;
9428         }
9429
9430         kvm_rip_write(vcpu, ctxt->eip);
9431         kvm_set_rflags(vcpu, ctxt->eflags);
9432         return 1;
9433 }
9434 EXPORT_SYMBOL_GPL(kvm_task_switch);
9435
9436 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9437 {
9438         if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
9439                 /*
9440                  * When EFER.LME and CR0.PG are set, the processor is in
9441                  * 64-bit mode (though maybe in a 32-bit code segment).
9442                  * CR4.PAE and EFER.LMA must be set.
9443                  */
9444                 if (!(sregs->cr4 & X86_CR4_PAE)
9445                     || !(sregs->efer & EFER_LMA))
9446                         return -EINVAL;
9447         } else {
9448                 /*
9449                  * Not in 64-bit mode: EFER.LMA is clear and the code
9450                  * segment cannot be 64-bit.
9451                  */
9452                 if (sregs->efer & EFER_LMA || sregs->cs.l)
9453                         return -EINVAL;
9454         }
9455
9456         return kvm_valid_cr4(vcpu, sregs->cr4);
9457 }
9458
9459 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9460 {
9461         struct msr_data apic_base_msr;
9462         int mmu_reset_needed = 0;
9463         int cpuid_update_needed = 0;
9464         int pending_vec, max_bits, idx;
9465         struct desc_ptr dt;
9466         int ret = -EINVAL;
9467
9468         if (kvm_valid_sregs(vcpu, sregs))
9469                 goto out;
9470
9471         apic_base_msr.data = sregs->apic_base;
9472         apic_base_msr.host_initiated = true;
9473         if (kvm_set_apic_base(vcpu, &apic_base_msr))
9474                 goto out;
9475
9476         dt.size = sregs->idt.limit;
9477         dt.address = sregs->idt.base;
9478         kvm_x86_ops.set_idt(vcpu, &dt);
9479         dt.size = sregs->gdt.limit;
9480         dt.address = sregs->gdt.base;
9481         kvm_x86_ops.set_gdt(vcpu, &dt);
9482
9483         vcpu->arch.cr2 = sregs->cr2;
9484         mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9485         vcpu->arch.cr3 = sregs->cr3;
9486         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9487
9488         kvm_set_cr8(vcpu, sregs->cr8);
9489
9490         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9491         kvm_x86_ops.set_efer(vcpu, sregs->efer);
9492
9493         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9494         kvm_x86_ops.set_cr0(vcpu, sregs->cr0);
9495         vcpu->arch.cr0 = sregs->cr0;
9496
9497         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9498         cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
9499                                 (X86_CR4_OSXSAVE | X86_CR4_PKE));
9500         kvm_x86_ops.set_cr4(vcpu, sregs->cr4);
9501         if (cpuid_update_needed)
9502                 kvm_update_cpuid_runtime(vcpu);
9503
9504         idx = srcu_read_lock(&vcpu->kvm->srcu);
9505         if (is_pae_paging(vcpu)) {
9506                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9507                 mmu_reset_needed = 1;
9508         }
9509         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9510
9511         if (mmu_reset_needed)
9512                 kvm_mmu_reset_context(vcpu);
9513
9514         max_bits = KVM_NR_INTERRUPTS;
9515         pending_vec = find_first_bit(
9516                 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9517         if (pending_vec < max_bits) {
9518                 kvm_queue_interrupt(vcpu, pending_vec, false);
9519                 pr_debug("Set back pending irq %d\n", pending_vec);
9520         }
9521
9522         kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9523         kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9524         kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9525         kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9526         kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9527         kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9528
9529         kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9530         kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9531
9532         update_cr8_intercept(vcpu);
9533
9534         /* Older userspace won't unhalt the vcpu on reset. */
9535         if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9536             sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9537             !is_protmode(vcpu))
9538                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9539
9540         kvm_make_request(KVM_REQ_EVENT, vcpu);
9541
9542         ret = 0;
9543 out:
9544         return ret;
9545 }
9546
9547 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9548                                   struct kvm_sregs *sregs)
9549 {
9550         int ret;
9551
9552         vcpu_load(vcpu);
9553         ret = __set_sregs(vcpu, sregs);
9554         vcpu_put(vcpu);
9555         return ret;
9556 }
9557
9558 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9559                                         struct kvm_guest_debug *dbg)
9560 {
9561         unsigned long rflags;
9562         int i, r;
9563
9564         vcpu_load(vcpu);
9565
9566         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9567                 r = -EBUSY;
9568                 if (vcpu->arch.exception.pending)
9569                         goto out;
9570                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9571                         kvm_queue_exception(vcpu, DB_VECTOR);
9572                 else
9573                         kvm_queue_exception(vcpu, BP_VECTOR);
9574         }
9575
9576         /*
9577          * Read rflags as long as potentially injected trace flags are still
9578          * filtered out.
9579          */
9580         rflags = kvm_get_rflags(vcpu);
9581
9582         vcpu->guest_debug = dbg->control;
9583         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9584                 vcpu->guest_debug = 0;
9585
9586         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9587                 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9588                         vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9589                 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9590         } else {
9591                 for (i = 0; i < KVM_NR_DB_REGS; i++)
9592                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9593         }
9594         kvm_update_dr7(vcpu);
9595
9596         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9597                 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9598                         get_segment_base(vcpu, VCPU_SREG_CS);
9599
9600         /*
9601          * Trigger an rflags update that will inject or remove the trace
9602          * flags.
9603          */
9604         kvm_set_rflags(vcpu, rflags);
9605
9606         kvm_x86_ops.update_exception_bitmap(vcpu);
9607
9608         r = 0;
9609
9610 out:
9611         vcpu_put(vcpu);
9612         return r;
9613 }
9614
9615 /*
9616  * Translate a guest virtual address to a guest physical address.
9617  */
9618 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9619                                     struct kvm_translation *tr)
9620 {
9621         unsigned long vaddr = tr->linear_address;
9622         gpa_t gpa;
9623         int idx;
9624
9625         vcpu_load(vcpu);
9626
9627         idx = srcu_read_lock(&vcpu->kvm->srcu);
9628         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9629         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9630         tr->physical_address = gpa;
9631         tr->valid = gpa != UNMAPPED_GVA;
9632         tr->writeable = 1;
9633         tr->usermode = 0;
9634
9635         vcpu_put(vcpu);
9636         return 0;
9637 }
9638
9639 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9640 {
9641         struct fxregs_state *fxsave;
9642
9643         vcpu_load(vcpu);
9644
9645         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9646         memcpy(fpu->fpr, fxsave->st_space, 128);
9647         fpu->fcw = fxsave->cwd;
9648         fpu->fsw = fxsave->swd;
9649         fpu->ftwx = fxsave->twd;
9650         fpu->last_opcode = fxsave->fop;
9651         fpu->last_ip = fxsave->rip;
9652         fpu->last_dp = fxsave->rdp;
9653         memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9654
9655         vcpu_put(vcpu);
9656         return 0;
9657 }
9658
9659 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9660 {
9661         struct fxregs_state *fxsave;
9662
9663         vcpu_load(vcpu);
9664
9665         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9666
9667         memcpy(fxsave->st_space, fpu->fpr, 128);
9668         fxsave->cwd = fpu->fcw;
9669         fxsave->swd = fpu->fsw;
9670         fxsave->twd = fpu->ftwx;
9671         fxsave->fop = fpu->last_opcode;
9672         fxsave->rip = fpu->last_ip;
9673         fxsave->rdp = fpu->last_dp;
9674         memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9675
9676         vcpu_put(vcpu);
9677         return 0;
9678 }
9679
9680 static void store_regs(struct kvm_vcpu *vcpu)
9681 {
9682         BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9683
9684         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9685                 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9686
9687         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9688                 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9689
9690         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9691                 kvm_vcpu_ioctl_x86_get_vcpu_events(
9692                                 vcpu, &vcpu->run->s.regs.events);
9693 }
9694
9695 static int sync_regs(struct kvm_vcpu *vcpu)
9696 {
9697         if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9698                 return -EINVAL;
9699
9700         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9701                 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9702                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9703         }
9704         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9705                 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9706                         return -EINVAL;
9707                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9708         }
9709         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9710                 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9711                                 vcpu, &vcpu->run->s.regs.events))
9712                         return -EINVAL;
9713                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9714         }
9715
9716         return 0;
9717 }
9718
9719 static void fx_init(struct kvm_vcpu *vcpu)
9720 {
9721         fpstate_init(&vcpu->arch.guest_fpu->state);
9722         if (boot_cpu_has(X86_FEATURE_XSAVES))
9723                 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9724                         host_xcr0 | XSTATE_COMPACTION_ENABLED;
9725
9726         /*
9727          * Ensure guest xcr0 is valid for loading
9728          */
9729         vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9730
9731         vcpu->arch.cr0 |= X86_CR0_ET;
9732 }
9733
9734 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9735 {
9736         if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9737                 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9738                              "guest TSC will not be reliable\n");
9739
9740         return 0;
9741 }
9742
9743 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9744 {
9745         struct page *page;
9746         int r;
9747
9748         if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9749                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9750         else
9751                 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9752
9753         kvm_set_tsc_khz(vcpu, max_tsc_khz);
9754
9755         r = kvm_mmu_create(vcpu);
9756         if (r < 0)
9757                 return r;
9758
9759         if (irqchip_in_kernel(vcpu->kvm)) {
9760                 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9761                 if (r < 0)
9762                         goto fail_mmu_destroy;
9763                 if (kvm_apicv_activated(vcpu->kvm))
9764                         vcpu->arch.apicv_active = true;
9765         } else
9766                 static_key_slow_inc(&kvm_no_apic_vcpu);
9767
9768         r = -ENOMEM;
9769
9770         page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9771         if (!page)
9772                 goto fail_free_lapic;
9773         vcpu->arch.pio_data = page_address(page);
9774
9775         vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9776                                        GFP_KERNEL_ACCOUNT);
9777         if (!vcpu->arch.mce_banks)
9778                 goto fail_free_pio_data;
9779         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9780
9781         if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9782                                 GFP_KERNEL_ACCOUNT))
9783                 goto fail_free_mce_banks;
9784
9785         if (!alloc_emulate_ctxt(vcpu))
9786                 goto free_wbinvd_dirty_mask;
9787
9788         vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9789                                                 GFP_KERNEL_ACCOUNT);
9790         if (!vcpu->arch.user_fpu) {
9791                 pr_err("kvm: failed to allocate userspace's fpu\n");
9792                 goto free_emulate_ctxt;
9793         }
9794
9795         vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9796                                                  GFP_KERNEL_ACCOUNT);
9797         if (!vcpu->arch.guest_fpu) {
9798                 pr_err("kvm: failed to allocate vcpu's fpu\n");
9799                 goto free_user_fpu;
9800         }
9801         fx_init(vcpu);
9802
9803         vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9804
9805         vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9806
9807         kvm_async_pf_hash_reset(vcpu);
9808         kvm_pmu_init(vcpu);
9809
9810         vcpu->arch.pending_external_vector = -1;
9811         vcpu->arch.preempted_in_kernel = false;
9812
9813         kvm_hv_vcpu_init(vcpu);
9814
9815         r = kvm_x86_ops.vcpu_create(vcpu);
9816         if (r)
9817                 goto free_guest_fpu;
9818
9819         vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9820         vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9821         kvm_vcpu_mtrr_init(vcpu);
9822         vcpu_load(vcpu);
9823         kvm_vcpu_reset(vcpu, false);
9824         kvm_init_mmu(vcpu, false);
9825         vcpu_put(vcpu);
9826         return 0;
9827
9828 free_guest_fpu:
9829         kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9830 free_user_fpu:
9831         kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9832 free_emulate_ctxt:
9833         kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9834 free_wbinvd_dirty_mask:
9835         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9836 fail_free_mce_banks:
9837         kfree(vcpu->arch.mce_banks);
9838 fail_free_pio_data:
9839         free_page((unsigned long)vcpu->arch.pio_data);
9840 fail_free_lapic:
9841         kvm_free_lapic(vcpu);
9842 fail_mmu_destroy:
9843         kvm_mmu_destroy(vcpu);
9844         return r;
9845 }
9846
9847 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9848 {
9849         struct kvm *kvm = vcpu->kvm;
9850
9851         kvm_hv_vcpu_postcreate(vcpu);
9852
9853         if (mutex_lock_killable(&vcpu->mutex))
9854                 return;
9855         vcpu_load(vcpu);
9856         kvm_synchronize_tsc(vcpu, 0);
9857         vcpu_put(vcpu);
9858
9859         /* poll control enabled by default */
9860         vcpu->arch.msr_kvm_poll_control = 1;
9861
9862         mutex_unlock(&vcpu->mutex);
9863
9864         if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
9865                 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9866                                                 KVMCLOCK_SYNC_PERIOD);
9867 }
9868
9869 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9870 {
9871         struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9872         int idx;
9873
9874         kvm_release_pfn(cache->pfn, cache->dirty, cache);
9875
9876         kvmclock_reset(vcpu);
9877
9878         kvm_x86_ops.vcpu_free(vcpu);
9879
9880         kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9881         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9882         kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9883         kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9884
9885         kvm_hv_vcpu_uninit(vcpu);
9886         kvm_pmu_destroy(vcpu);
9887         kfree(vcpu->arch.mce_banks);
9888         kvm_free_lapic(vcpu);
9889         idx = srcu_read_lock(&vcpu->kvm->srcu);
9890         kvm_mmu_destroy(vcpu);
9891         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9892         free_page((unsigned long)vcpu->arch.pio_data);
9893         if (!lapic_in_kernel(vcpu))
9894                 static_key_slow_dec(&kvm_no_apic_vcpu);
9895 }
9896
9897 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9898 {
9899         kvm_lapic_reset(vcpu, init_event);
9900
9901         vcpu->arch.hflags = 0;
9902
9903         vcpu->arch.smi_pending = 0;
9904         vcpu->arch.smi_count = 0;
9905         atomic_set(&vcpu->arch.nmi_queued, 0);
9906         vcpu->arch.nmi_pending = 0;
9907         vcpu->arch.nmi_injected = false;
9908         kvm_clear_interrupt_queue(vcpu);
9909         kvm_clear_exception_queue(vcpu);
9910
9911         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9912         kvm_update_dr0123(vcpu);
9913         vcpu->arch.dr6 = DR6_INIT;
9914         vcpu->arch.dr7 = DR7_FIXED_1;
9915         kvm_update_dr7(vcpu);
9916
9917         vcpu->arch.cr2 = 0;
9918
9919         kvm_make_request(KVM_REQ_EVENT, vcpu);
9920         vcpu->arch.apf.msr_en_val = 0;
9921         vcpu->arch.apf.msr_int_val = 0;
9922         vcpu->arch.st.msr_val = 0;
9923
9924         kvmclock_reset(vcpu);
9925
9926         kvm_clear_async_pf_completion_queue(vcpu);
9927         kvm_async_pf_hash_reset(vcpu);
9928         vcpu->arch.apf.halted = false;
9929
9930         if (kvm_mpx_supported()) {
9931                 void *mpx_state_buffer;
9932
9933                 /*
9934                  * To avoid have the INIT path from kvm_apic_has_events() that be
9935                  * called with loaded FPU and does not let userspace fix the state.
9936                  */
9937                 if (init_event)
9938                         kvm_put_guest_fpu(vcpu);
9939                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9940                                         XFEATURE_BNDREGS);
9941                 if (mpx_state_buffer)
9942                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9943                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9944                                         XFEATURE_BNDCSR);
9945                 if (mpx_state_buffer)
9946                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9947                 if (init_event)
9948                         kvm_load_guest_fpu(vcpu);
9949         }
9950
9951         if (!init_event) {
9952                 kvm_pmu_reset(vcpu);
9953                 vcpu->arch.smbase = 0x30000;
9954
9955                 vcpu->arch.msr_misc_features_enables = 0;
9956
9957                 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9958         }
9959
9960         memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9961         vcpu->arch.regs_avail = ~0;
9962         vcpu->arch.regs_dirty = ~0;
9963
9964         vcpu->arch.ia32_xss = 0;
9965
9966         kvm_x86_ops.vcpu_reset(vcpu, init_event);
9967 }
9968
9969 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9970 {
9971         struct kvm_segment cs;
9972
9973         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9974         cs.selector = vector << 8;
9975         cs.base = vector << 12;
9976         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9977         kvm_rip_write(vcpu, 0);
9978 }
9979
9980 int kvm_arch_hardware_enable(void)
9981 {
9982         struct kvm *kvm;
9983         struct kvm_vcpu *vcpu;
9984         int i;
9985         int ret;
9986         u64 local_tsc;
9987         u64 max_tsc = 0;
9988         bool stable, backwards_tsc = false;
9989
9990         kvm_user_return_msr_cpu_online();
9991         ret = kvm_x86_ops.hardware_enable();
9992         if (ret != 0)
9993                 return ret;
9994
9995         local_tsc = rdtsc();
9996         stable = !kvm_check_tsc_unstable();
9997         list_for_each_entry(kvm, &vm_list, vm_list) {
9998                 kvm_for_each_vcpu(i, vcpu, kvm) {
9999                         if (!stable && vcpu->cpu == smp_processor_id())
10000                                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10001                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
10002                                 backwards_tsc = true;
10003                                 if (vcpu->arch.last_host_tsc > max_tsc)
10004                                         max_tsc = vcpu->arch.last_host_tsc;
10005                         }
10006                 }
10007         }
10008
10009         /*
10010          * Sometimes, even reliable TSCs go backwards.  This happens on
10011          * platforms that reset TSC during suspend or hibernate actions, but
10012          * maintain synchronization.  We must compensate.  Fortunately, we can
10013          * detect that condition here, which happens early in CPU bringup,
10014          * before any KVM threads can be running.  Unfortunately, we can't
10015          * bring the TSCs fully up to date with real time, as we aren't yet far
10016          * enough into CPU bringup that we know how much real time has actually
10017          * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
10018          * variables that haven't been updated yet.
10019          *
10020          * So we simply find the maximum observed TSC above, then record the
10021          * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
10022          * the adjustment will be applied.  Note that we accumulate
10023          * adjustments, in case multiple suspend cycles happen before some VCPU
10024          * gets a chance to run again.  In the event that no KVM threads get a
10025          * chance to run, we will miss the entire elapsed period, as we'll have
10026          * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
10027          * loose cycle time.  This isn't too big a deal, since the loss will be
10028          * uniform across all VCPUs (not to mention the scenario is extremely
10029          * unlikely). It is possible that a second hibernate recovery happens
10030          * much faster than a first, causing the observed TSC here to be
10031          * smaller; this would require additional padding adjustment, which is
10032          * why we set last_host_tsc to the local tsc observed here.
10033          *
10034          * N.B. - this code below runs only on platforms with reliable TSC,
10035          * as that is the only way backwards_tsc is set above.  Also note
10036          * that this runs for ALL vcpus, which is not a bug; all VCPUs should
10037          * have the same delta_cyc adjustment applied if backwards_tsc
10038          * is detected.  Note further, this adjustment is only done once,
10039          * as we reset last_host_tsc on all VCPUs to stop this from being
10040          * called multiple times (one for each physical CPU bringup).
10041          *
10042          * Platforms with unreliable TSCs don't have to deal with this, they
10043          * will be compensated by the logic in vcpu_load, which sets the TSC to
10044          * catchup mode.  This will catchup all VCPUs to real time, but cannot
10045          * guarantee that they stay in perfect synchronization.
10046          */
10047         if (backwards_tsc) {
10048                 u64 delta_cyc = max_tsc - local_tsc;
10049                 list_for_each_entry(kvm, &vm_list, vm_list) {
10050                         kvm->arch.backwards_tsc_observed = true;
10051                         kvm_for_each_vcpu(i, vcpu, kvm) {
10052                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
10053                                 vcpu->arch.last_host_tsc = local_tsc;
10054                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
10055                         }
10056
10057                         /*
10058                          * We have to disable TSC offset matching.. if you were
10059                          * booting a VM while issuing an S4 host suspend....
10060                          * you may have some problem.  Solving this issue is
10061                          * left as an exercise to the reader.
10062                          */
10063                         kvm->arch.last_tsc_nsec = 0;
10064                         kvm->arch.last_tsc_write = 0;
10065                 }
10066
10067         }
10068         return 0;
10069 }
10070
10071 void kvm_arch_hardware_disable(void)
10072 {
10073         kvm_x86_ops.hardware_disable();
10074         drop_user_return_notifiers();
10075 }
10076
10077 int kvm_arch_hardware_setup(void *opaque)
10078 {
10079         struct kvm_x86_init_ops *ops = opaque;
10080         int r;
10081
10082         rdmsrl_safe(MSR_EFER, &host_efer);
10083
10084         if (boot_cpu_has(X86_FEATURE_XSAVES))
10085                 rdmsrl(MSR_IA32_XSS, host_xss);
10086
10087         r = ops->hardware_setup();
10088         if (r != 0)
10089                 return r;
10090
10091         memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
10092
10093         if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
10094                 supported_xss = 0;
10095
10096 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
10097         cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
10098 #undef __kvm_cpu_cap_has
10099
10100         if (kvm_has_tsc_control) {
10101                 /*
10102                  * Make sure the user can only configure tsc_khz values that
10103                  * fit into a signed integer.
10104                  * A min value is not calculated because it will always
10105                  * be 1 on all machines.
10106                  */
10107                 u64 max = min(0x7fffffffULL,
10108                               __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
10109                 kvm_max_guest_tsc_khz = max;
10110
10111                 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
10112         }
10113
10114         kvm_init_msr_list();
10115         return 0;
10116 }
10117
10118 void kvm_arch_hardware_unsetup(void)
10119 {
10120         kvm_x86_ops.hardware_unsetup();
10121 }
10122
10123 int kvm_arch_check_processor_compat(void *opaque)
10124 {
10125         struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
10126         struct kvm_x86_init_ops *ops = opaque;
10127
10128         WARN_ON(!irqs_disabled());
10129
10130         if (__cr4_reserved_bits(cpu_has, c) !=
10131             __cr4_reserved_bits(cpu_has, &boot_cpu_data))
10132                 return -EIO;
10133
10134         return ops->check_processor_compatibility();
10135 }
10136
10137 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
10138 {
10139         return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
10140 }
10141 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
10142
10143 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
10144 {
10145         return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
10146 }
10147
10148 struct static_key kvm_no_apic_vcpu __read_mostly;
10149 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
10150
10151 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
10152 {
10153         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
10154
10155         vcpu->arch.l1tf_flush_l1d = true;
10156         if (pmu->version && unlikely(pmu->event_count)) {
10157                 pmu->need_cleanup = true;
10158                 kvm_make_request(KVM_REQ_PMU, vcpu);
10159         }
10160         kvm_x86_ops.sched_in(vcpu, cpu);
10161 }
10162
10163 void kvm_arch_free_vm(struct kvm *kvm)
10164 {
10165         kfree(kvm->arch.hyperv.hv_pa_pg);
10166         vfree(kvm);
10167 }
10168
10169
10170 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
10171 {
10172         if (type)
10173                 return -EINVAL;
10174
10175         INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
10176         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
10177         INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
10178         INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
10179         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
10180         atomic_set(&kvm->arch.noncoherent_dma_count, 0);
10181
10182         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
10183         set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
10184         /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
10185         set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
10186                 &kvm->arch.irq_sources_bitmap);
10187
10188         raw_spin_lock_init(&kvm->arch.tsc_write_lock);
10189         mutex_init(&kvm->arch.apic_map_lock);
10190         spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
10191
10192         kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
10193         pvclock_update_vm_gtod_copy(kvm);
10194
10195         kvm->arch.guest_can_read_msr_platform_info = true;
10196
10197         INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
10198         INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
10199
10200         kvm_hv_init_vm(kvm);
10201         kvm_page_track_init(kvm);
10202         kvm_mmu_init_vm(kvm);
10203
10204         return kvm_x86_ops.vm_init(kvm);
10205 }
10206
10207 int kvm_arch_post_init_vm(struct kvm *kvm)
10208 {
10209         return kvm_mmu_post_init_vm(kvm);
10210 }
10211
10212 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
10213 {
10214         vcpu_load(vcpu);
10215         kvm_mmu_unload(vcpu);
10216         vcpu_put(vcpu);
10217 }
10218
10219 static void kvm_free_vcpus(struct kvm *kvm)
10220 {
10221         unsigned int i;
10222         struct kvm_vcpu *vcpu;
10223
10224         /*
10225          * Unpin any mmu pages first.
10226          */
10227         kvm_for_each_vcpu(i, vcpu, kvm) {
10228                 kvm_clear_async_pf_completion_queue(vcpu);
10229                 kvm_unload_vcpu_mmu(vcpu);
10230         }
10231         kvm_for_each_vcpu(i, vcpu, kvm)
10232                 kvm_vcpu_destroy(vcpu);
10233
10234         mutex_lock(&kvm->lock);
10235         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
10236                 kvm->vcpus[i] = NULL;
10237
10238         atomic_set(&kvm->online_vcpus, 0);
10239         mutex_unlock(&kvm->lock);
10240 }
10241
10242 void kvm_arch_sync_events(struct kvm *kvm)
10243 {
10244         cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
10245         cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
10246         kvm_free_pit(kvm);
10247 }
10248
10249 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
10250 {
10251         int i, r;
10252         unsigned long hva, old_npages;
10253         struct kvm_memslots *slots = kvm_memslots(kvm);
10254         struct kvm_memory_slot *slot;
10255
10256         /* Called with kvm->slots_lock held.  */
10257         if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
10258                 return -EINVAL;
10259
10260         slot = id_to_memslot(slots, id);
10261         if (size) {
10262                 if (slot && slot->npages)
10263                         return -EEXIST;
10264
10265                 /*
10266                  * MAP_SHARED to prevent internal slot pages from being moved
10267                  * by fork()/COW.
10268                  */
10269                 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
10270                               MAP_SHARED | MAP_ANONYMOUS, 0);
10271                 if (IS_ERR((void *)hva))
10272                         return PTR_ERR((void *)hva);
10273         } else {
10274                 if (!slot || !slot->npages)
10275                         return 0;
10276
10277                 old_npages = slot->npages;
10278                 hva = 0;
10279         }
10280
10281         for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
10282                 struct kvm_userspace_memory_region m;
10283
10284                 m.slot = id | (i << 16);
10285                 m.flags = 0;
10286                 m.guest_phys_addr = gpa;
10287                 m.userspace_addr = hva;
10288                 m.memory_size = size;
10289                 r = __kvm_set_memory_region(kvm, &m);
10290                 if (r < 0)
10291                         return r;
10292         }
10293
10294         if (!size)
10295                 vm_munmap(hva, old_npages * PAGE_SIZE);
10296
10297         return 0;
10298 }
10299 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
10300
10301 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
10302 {
10303         kvm_mmu_pre_destroy_vm(kvm);
10304 }
10305
10306 void kvm_arch_destroy_vm(struct kvm *kvm)
10307 {
10308         u32 i;
10309
10310         if (current->mm == kvm->mm) {
10311                 /*
10312                  * Free memory regions allocated on behalf of userspace,
10313                  * unless the the memory map has changed due to process exit
10314                  * or fd copying.
10315                  */
10316                 mutex_lock(&kvm->slots_lock);
10317                 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
10318                                         0, 0);
10319                 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
10320                                         0, 0);
10321                 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
10322                 mutex_unlock(&kvm->slots_lock);
10323         }
10324         if (kvm_x86_ops.vm_destroy)
10325                 kvm_x86_ops.vm_destroy(kvm);
10326         for (i = 0; i < kvm->arch.msr_filter.count; i++)
10327                 kfree(kvm->arch.msr_filter.ranges[i].bitmap);
10328         kvm_pic_destroy(kvm);
10329         kvm_ioapic_destroy(kvm);
10330         kvm_free_vcpus(kvm);
10331         kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
10332         kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
10333         kvm_mmu_uninit_vm(kvm);
10334         kvm_page_track_cleanup(kvm);
10335         kvm_hv_destroy_vm(kvm);
10336 }
10337
10338 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
10339 {
10340         int i;
10341
10342         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10343                 kvfree(slot->arch.rmap[i]);
10344                 slot->arch.rmap[i] = NULL;
10345
10346                 if (i == 0)
10347                         continue;
10348
10349                 kvfree(slot->arch.lpage_info[i - 1]);
10350                 slot->arch.lpage_info[i - 1] = NULL;
10351         }
10352
10353         kvm_page_track_free_memslot(slot);
10354 }
10355
10356 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
10357                                       unsigned long npages)
10358 {
10359         int i;
10360
10361         /*
10362          * Clear out the previous array pointers for the KVM_MR_MOVE case.  The
10363          * old arrays will be freed by __kvm_set_memory_region() if installing
10364          * the new memslot is successful.
10365          */
10366         memset(&slot->arch, 0, sizeof(slot->arch));
10367
10368         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10369                 struct kvm_lpage_info *linfo;
10370                 unsigned long ugfn;
10371                 int lpages;
10372                 int level = i + 1;
10373
10374                 lpages = gfn_to_index(slot->base_gfn + npages - 1,
10375                                       slot->base_gfn, level) + 1;
10376
10377                 slot->arch.rmap[i] =
10378                         kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
10379                                  GFP_KERNEL_ACCOUNT);
10380                 if (!slot->arch.rmap[i])
10381                         goto out_free;
10382                 if (i == 0)
10383                         continue;
10384
10385                 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
10386                 if (!linfo)
10387                         goto out_free;
10388
10389                 slot->arch.lpage_info[i - 1] = linfo;
10390
10391                 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
10392                         linfo[0].disallow_lpage = 1;
10393                 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
10394                         linfo[lpages - 1].disallow_lpage = 1;
10395                 ugfn = slot->userspace_addr >> PAGE_SHIFT;
10396                 /*
10397                  * If the gfn and userspace address are not aligned wrt each
10398                  * other, disable large page support for this slot.
10399                  */
10400                 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
10401                         unsigned long j;
10402
10403                         for (j = 0; j < lpages; ++j)
10404                                 linfo[j].disallow_lpage = 1;
10405                 }
10406         }
10407
10408         if (kvm_page_track_create_memslot(slot, npages))
10409                 goto out_free;
10410
10411         return 0;
10412
10413 out_free:
10414         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10415                 kvfree(slot->arch.rmap[i]);
10416                 slot->arch.rmap[i] = NULL;
10417                 if (i == 0)
10418                         continue;
10419
10420                 kvfree(slot->arch.lpage_info[i - 1]);
10421                 slot->arch.lpage_info[i - 1] = NULL;
10422         }
10423         return -ENOMEM;
10424 }
10425
10426 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
10427 {
10428         struct kvm_vcpu *vcpu;
10429         int i;
10430
10431         /*
10432          * memslots->generation has been incremented.
10433          * mmio generation may have reached its maximum value.
10434          */
10435         kvm_mmu_invalidate_mmio_sptes(kvm, gen);
10436
10437         /* Force re-initialization of steal_time cache */
10438         kvm_for_each_vcpu(i, vcpu, kvm)
10439                 kvm_vcpu_kick(vcpu);
10440 }
10441
10442 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10443                                 struct kvm_memory_slot *memslot,
10444                                 const struct kvm_userspace_memory_region *mem,
10445                                 enum kvm_mr_change change)
10446 {
10447         if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10448                 return kvm_alloc_memslot_metadata(memslot,
10449                                                   mem->memory_size >> PAGE_SHIFT);
10450         return 0;
10451 }
10452
10453 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10454                                      struct kvm_memory_slot *old,
10455                                      struct kvm_memory_slot *new,
10456                                      enum kvm_mr_change change)
10457 {
10458         /*
10459          * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot.
10460          * See comments below.
10461          */
10462         if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY))
10463                 return;
10464
10465         /*
10466          * Dirty logging tracks sptes in 4k granularity, meaning that large
10467          * sptes have to be split.  If live migration is successful, the guest
10468          * in the source machine will be destroyed and large sptes will be
10469          * created in the destination. However, if the guest continues to run
10470          * in the source machine (for example if live migration fails), small
10471          * sptes will remain around and cause bad performance.
10472          *
10473          * Scan sptes if dirty logging has been stopped, dropping those
10474          * which can be collapsed into a single large-page spte.  Later
10475          * page faults will create the large-page sptes.
10476          *
10477          * There is no need to do this in any of the following cases:
10478          * CREATE:      No dirty mappings will already exist.
10479          * MOVE/DELETE: The old mappings will already have been cleaned up by
10480          *              kvm_arch_flush_shadow_memslot()
10481          */
10482         if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10483             !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10484                 kvm_mmu_zap_collapsible_sptes(kvm, new);
10485
10486         /*
10487          * Enable or disable dirty logging for the slot.
10488          *
10489          * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old
10490          * slot have been zapped so no dirty logging updates are needed for
10491          * the old slot.
10492          * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible
10493          * any mappings that might be created in it will consume the
10494          * properties of the new slot and do not need to be updated here.
10495          *
10496          * When PML is enabled, the kvm_x86_ops dirty logging hooks are
10497          * called to enable/disable dirty logging.
10498          *
10499          * When disabling dirty logging with PML enabled, the D-bit is set
10500          * for sptes in the slot in order to prevent unnecessary GPA
10501          * logging in the PML buffer (and potential PML buffer full VMEXIT).
10502          * This guarantees leaving PML enabled for the guest's lifetime
10503          * won't have any additional overhead from PML when the guest is
10504          * running with dirty logging disabled.
10505          *
10506          * When enabling dirty logging, large sptes are write-protected
10507          * so they can be split on first write.  New large sptes cannot
10508          * be created for this slot until the end of the logging.
10509          * See the comments in fast_page_fault().
10510          * For small sptes, nothing is done if the dirty log is in the
10511          * initial-all-set state.  Otherwise, depending on whether pml
10512          * is enabled the D-bit or the W-bit will be cleared.
10513          */
10514         if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10515                 if (kvm_x86_ops.slot_enable_log_dirty) {
10516                         kvm_x86_ops.slot_enable_log_dirty(kvm, new);
10517                 } else {
10518                         int level =
10519                                 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10520                                 PG_LEVEL_2M : PG_LEVEL_4K;
10521
10522                         /*
10523                          * If we're with initial-all-set, we don't need
10524                          * to write protect any small page because
10525                          * they're reported as dirty already.  However
10526                          * we still need to write-protect huge pages
10527                          * so that the page split can happen lazily on
10528                          * the first write to the huge page.
10529                          */
10530                         kvm_mmu_slot_remove_write_access(kvm, new, level);
10531                 }
10532         } else {
10533                 if (kvm_x86_ops.slot_disable_log_dirty)
10534                         kvm_x86_ops.slot_disable_log_dirty(kvm, new);
10535         }
10536 }
10537
10538 void kvm_arch_commit_memory_region(struct kvm *kvm,
10539                                 const struct kvm_userspace_memory_region *mem,
10540                                 struct kvm_memory_slot *old,
10541                                 const struct kvm_memory_slot *new,
10542                                 enum kvm_mr_change change)
10543 {
10544         if (!kvm->arch.n_requested_mmu_pages)
10545                 kvm_mmu_change_mmu_pages(kvm,
10546                                 kvm_mmu_calculate_default_mmu_pages(kvm));
10547
10548         /*
10549          * FIXME: const-ify all uses of struct kvm_memory_slot.
10550          */
10551         kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change);
10552
10553         /* Free the arrays associated with the old memslot. */
10554         if (change == KVM_MR_MOVE)
10555                 kvm_arch_free_memslot(kvm, old);
10556 }
10557
10558 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10559 {
10560         kvm_mmu_zap_all(kvm);
10561 }
10562
10563 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10564                                    struct kvm_memory_slot *slot)
10565 {
10566         kvm_page_track_flush_slot(kvm, slot);
10567 }
10568
10569 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10570 {
10571         return (is_guest_mode(vcpu) &&
10572                         kvm_x86_ops.guest_apic_has_interrupt &&
10573                         kvm_x86_ops.guest_apic_has_interrupt(vcpu));
10574 }
10575
10576 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10577 {
10578         if (!list_empty_careful(&vcpu->async_pf.done))
10579                 return true;
10580
10581         if (kvm_apic_has_events(vcpu))
10582                 return true;
10583
10584         if (vcpu->arch.pv.pv_unhalted)
10585                 return true;
10586
10587         if (vcpu->arch.exception.pending)
10588                 return true;
10589
10590         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10591             (vcpu->arch.nmi_pending &&
10592              kvm_x86_ops.nmi_allowed(vcpu, false)))
10593                 return true;
10594
10595         if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10596             (vcpu->arch.smi_pending &&
10597              kvm_x86_ops.smi_allowed(vcpu, false)))
10598                 return true;
10599
10600         if (kvm_arch_interrupt_allowed(vcpu) &&
10601             (kvm_cpu_has_interrupt(vcpu) ||
10602             kvm_guest_apic_has_interrupt(vcpu)))
10603                 return true;
10604
10605         if (kvm_hv_has_stimer_pending(vcpu))
10606                 return true;
10607
10608         if (is_guest_mode(vcpu) &&
10609             kvm_x86_ops.nested_ops->hv_timer_pending &&
10610             kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
10611                 return true;
10612
10613         return false;
10614 }
10615
10616 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10617 {
10618         return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10619 }
10620
10621 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10622 {
10623         if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10624                 return true;
10625
10626         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10627                 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10628                  kvm_test_request(KVM_REQ_EVENT, vcpu))
10629                 return true;
10630
10631         if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu))
10632                 return true;
10633
10634         return false;
10635 }
10636
10637 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10638 {
10639         return vcpu->arch.preempted_in_kernel;
10640 }
10641
10642 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10643 {
10644         return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10645 }
10646
10647 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10648 {
10649         return kvm_x86_ops.interrupt_allowed(vcpu, false);
10650 }
10651
10652 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10653 {
10654         if (is_64_bit_mode(vcpu))
10655                 return kvm_rip_read(vcpu);
10656         return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10657                      kvm_rip_read(vcpu));
10658 }
10659 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10660
10661 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10662 {
10663         return kvm_get_linear_rip(vcpu) == linear_rip;
10664 }
10665 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10666
10667 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10668 {
10669         unsigned long rflags;
10670
10671         rflags = kvm_x86_ops.get_rflags(vcpu);
10672         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10673                 rflags &= ~X86_EFLAGS_TF;
10674         return rflags;
10675 }
10676 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10677
10678 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10679 {
10680         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10681             kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10682                 rflags |= X86_EFLAGS_TF;
10683         kvm_x86_ops.set_rflags(vcpu, rflags);
10684 }
10685
10686 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10687 {
10688         __kvm_set_rflags(vcpu, rflags);
10689         kvm_make_request(KVM_REQ_EVENT, vcpu);
10690 }
10691 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10692
10693 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10694 {
10695         int r;
10696
10697         if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10698               work->wakeup_all)
10699                 return;
10700
10701         r = kvm_mmu_reload(vcpu);
10702         if (unlikely(r))
10703                 return;
10704
10705         if (!vcpu->arch.mmu->direct_map &&
10706               work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10707                 return;
10708
10709         kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10710 }
10711
10712 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10713 {
10714         BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
10715
10716         return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10717 }
10718
10719 static inline u32 kvm_async_pf_next_probe(u32 key)
10720 {
10721         return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
10722 }
10723
10724 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10725 {
10726         u32 key = kvm_async_pf_hash_fn(gfn);
10727
10728         while (vcpu->arch.apf.gfns[key] != ~0)
10729                 key = kvm_async_pf_next_probe(key);
10730
10731         vcpu->arch.apf.gfns[key] = gfn;
10732 }
10733
10734 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10735 {
10736         int i;
10737         u32 key = kvm_async_pf_hash_fn(gfn);
10738
10739         for (i = 0; i < ASYNC_PF_PER_VCPU &&
10740                      (vcpu->arch.apf.gfns[key] != gfn &&
10741                       vcpu->arch.apf.gfns[key] != ~0); i++)
10742                 key = kvm_async_pf_next_probe(key);
10743
10744         return key;
10745 }
10746
10747 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10748 {
10749         return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10750 }
10751
10752 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10753 {
10754         u32 i, j, k;
10755
10756         i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10757
10758         if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
10759                 return;
10760
10761         while (true) {
10762                 vcpu->arch.apf.gfns[i] = ~0;
10763                 do {
10764                         j = kvm_async_pf_next_probe(j);
10765                         if (vcpu->arch.apf.gfns[j] == ~0)
10766                                 return;
10767                         k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10768                         /*
10769                          * k lies cyclically in ]i,j]
10770                          * |    i.k.j |
10771                          * |....j i.k.| or  |.k..j i...|
10772                          */
10773                 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10774                 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10775                 i = j;
10776         }
10777 }
10778
10779 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
10780 {
10781         u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
10782
10783         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
10784                                       sizeof(reason));
10785 }
10786
10787 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
10788 {
10789         unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
10790
10791         return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
10792                                              &token, offset, sizeof(token));
10793 }
10794
10795 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
10796 {
10797         unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
10798         u32 val;
10799
10800         if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
10801                                          &val, offset, sizeof(val)))
10802                 return false;
10803
10804         return !val;
10805 }
10806
10807 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10808 {
10809         if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10810                 return false;
10811
10812         if (!kvm_pv_async_pf_enabled(vcpu) ||
10813             (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0))
10814                 return false;
10815
10816         return true;
10817 }
10818
10819 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10820 {
10821         if (unlikely(!lapic_in_kernel(vcpu) ||
10822                      kvm_event_needs_reinjection(vcpu) ||
10823                      vcpu->arch.exception.pending))
10824                 return false;
10825
10826         if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10827                 return false;
10828
10829         /*
10830          * If interrupts are off we cannot even use an artificial
10831          * halt state.
10832          */
10833         return kvm_arch_interrupt_allowed(vcpu);
10834 }
10835
10836 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10837                                      struct kvm_async_pf *work)
10838 {
10839         struct x86_exception fault;
10840
10841         trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10842         kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10843
10844         if (kvm_can_deliver_async_pf(vcpu) &&
10845             !apf_put_user_notpresent(vcpu)) {
10846                 fault.vector = PF_VECTOR;
10847                 fault.error_code_valid = true;
10848                 fault.error_code = 0;
10849                 fault.nested_page_fault = false;
10850                 fault.address = work->arch.token;
10851                 fault.async_page_fault = true;
10852                 kvm_inject_page_fault(vcpu, &fault);
10853                 return true;
10854         } else {
10855                 /*
10856                  * It is not possible to deliver a paravirtualized asynchronous
10857                  * page fault, but putting the guest in an artificial halt state
10858                  * can be beneficial nevertheless: if an interrupt arrives, we
10859                  * can deliver it timely and perhaps the guest will schedule
10860                  * another process.  When the instruction that triggered a page
10861                  * fault is retried, hopefully the page will be ready in the host.
10862                  */
10863                 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10864                 return false;
10865         }
10866 }
10867
10868 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10869                                  struct kvm_async_pf *work)
10870 {
10871         struct kvm_lapic_irq irq = {
10872                 .delivery_mode = APIC_DM_FIXED,
10873                 .vector = vcpu->arch.apf.vec
10874         };
10875
10876         if (work->wakeup_all)
10877                 work->arch.token = ~0; /* broadcast wakeup */
10878         else
10879                 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10880         trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
10881
10882         if ((work->wakeup_all || work->notpresent_injected) &&
10883             kvm_pv_async_pf_enabled(vcpu) &&
10884             !apf_put_user_ready(vcpu, work->arch.token)) {
10885                 vcpu->arch.apf.pageready_pending = true;
10886                 kvm_apic_set_irq(vcpu, &irq, NULL);
10887         }
10888
10889         vcpu->arch.apf.halted = false;
10890         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10891 }
10892
10893 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
10894 {
10895         kvm_make_request(KVM_REQ_APF_READY, vcpu);
10896         if (!vcpu->arch.apf.pageready_pending)
10897                 kvm_vcpu_kick(vcpu);
10898 }
10899
10900 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
10901 {
10902         if (!kvm_pv_async_pf_enabled(vcpu))
10903                 return true;
10904         else
10905                 return apf_pageready_slot_free(vcpu);
10906 }
10907
10908 void kvm_arch_start_assignment(struct kvm *kvm)
10909 {
10910         atomic_inc(&kvm->arch.assigned_device_count);
10911 }
10912 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10913
10914 void kvm_arch_end_assignment(struct kvm *kvm)
10915 {
10916         atomic_dec(&kvm->arch.assigned_device_count);
10917 }
10918 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10919
10920 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10921 {
10922         return atomic_read(&kvm->arch.assigned_device_count);
10923 }
10924 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10925
10926 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10927 {
10928         atomic_inc(&kvm->arch.noncoherent_dma_count);
10929 }
10930 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10931
10932 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10933 {
10934         atomic_dec(&kvm->arch.noncoherent_dma_count);
10935 }
10936 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10937
10938 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10939 {
10940         return atomic_read(&kvm->arch.noncoherent_dma_count);
10941 }
10942 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10943
10944 bool kvm_arch_has_irq_bypass(void)
10945 {
10946         return true;
10947 }
10948
10949 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10950                                       struct irq_bypass_producer *prod)
10951 {
10952         struct kvm_kernel_irqfd *irqfd =
10953                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10954         int ret;
10955
10956         irqfd->producer = prod;
10957         kvm_arch_start_assignment(irqfd->kvm);
10958         ret = kvm_x86_ops.update_pi_irte(irqfd->kvm,
10959                                          prod->irq, irqfd->gsi, 1);
10960
10961         if (ret)
10962                 kvm_arch_end_assignment(irqfd->kvm);
10963
10964         return ret;
10965 }
10966
10967 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10968                                       struct irq_bypass_producer *prod)
10969 {
10970         int ret;
10971         struct kvm_kernel_irqfd *irqfd =
10972                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10973
10974         WARN_ON(irqfd->producer != prod);
10975         irqfd->producer = NULL;
10976
10977         /*
10978          * When producer of consumer is unregistered, we change back to
10979          * remapped mode, so we can re-use the current implementation
10980          * when the irq is masked/disabled or the consumer side (KVM
10981          * int this case doesn't want to receive the interrupts.
10982         */
10983         ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10984         if (ret)
10985                 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10986                        " fails: %d\n", irqfd->consumer.token, ret);
10987
10988         kvm_arch_end_assignment(irqfd->kvm);
10989 }
10990
10991 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10992                                    uint32_t guest_irq, bool set)
10993 {
10994         return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set);
10995 }
10996
10997 bool kvm_vector_hashing_enabled(void)
10998 {
10999         return vector_hashing;
11000 }
11001
11002 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
11003 {
11004         return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
11005 }
11006 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
11007
11008
11009 int kvm_spec_ctrl_test_value(u64 value)
11010 {
11011         /*
11012          * test that setting IA32_SPEC_CTRL to given value
11013          * is allowed by the host processor
11014          */
11015
11016         u64 saved_value;
11017         unsigned long flags;
11018         int ret = 0;
11019
11020         local_irq_save(flags);
11021
11022         if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
11023                 ret = 1;
11024         else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
11025                 ret = 1;
11026         else
11027                 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
11028
11029         local_irq_restore(flags);
11030
11031         return ret;
11032 }
11033 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
11034
11035 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
11036 {
11037         struct x86_exception fault;
11038         u32 access = error_code &
11039                 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
11040
11041         if (!(error_code & PFERR_PRESENT_MASK) ||
11042             vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) {
11043                 /*
11044                  * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
11045                  * tables probably do not match the TLB.  Just proceed
11046                  * with the error code that the processor gave.
11047                  */
11048                 fault.vector = PF_VECTOR;
11049                 fault.error_code_valid = true;
11050                 fault.error_code = error_code;
11051                 fault.nested_page_fault = false;
11052                 fault.address = gva;
11053         }
11054         vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
11055 }
11056 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
11057
11058 /*
11059  * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
11060  * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
11061  * indicates whether exit to userspace is needed.
11062  */
11063 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
11064                               struct x86_exception *e)
11065 {
11066         if (r == X86EMUL_PROPAGATE_FAULT) {
11067                 kvm_inject_emulated_page_fault(vcpu, e);
11068                 return 1;
11069         }
11070
11071         /*
11072          * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
11073          * while handling a VMX instruction KVM could've handled the request
11074          * correctly by exiting to userspace and performing I/O but there
11075          * doesn't seem to be a real use-case behind such requests, just return
11076          * KVM_EXIT_INTERNAL_ERROR for now.
11077          */
11078         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11079         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11080         vcpu->run->internal.ndata = 0;
11081
11082         return 0;
11083 }
11084 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
11085
11086 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
11087 {
11088         bool pcid_enabled;
11089         struct x86_exception e;
11090         unsigned i;
11091         unsigned long roots_to_free = 0;
11092         struct {
11093                 u64 pcid;
11094                 u64 gla;
11095         } operand;
11096         int r;
11097
11098         r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
11099         if (r != X86EMUL_CONTINUE)
11100                 return kvm_handle_memory_failure(vcpu, r, &e);
11101
11102         if (operand.pcid >> 12 != 0) {
11103                 kvm_inject_gp(vcpu, 0);
11104                 return 1;
11105         }
11106
11107         pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
11108
11109         switch (type) {
11110         case INVPCID_TYPE_INDIV_ADDR:
11111                 if ((!pcid_enabled && (operand.pcid != 0)) ||
11112                     is_noncanonical_address(operand.gla, vcpu)) {
11113                         kvm_inject_gp(vcpu, 0);
11114                         return 1;
11115                 }
11116                 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
11117                 return kvm_skip_emulated_instruction(vcpu);
11118
11119         case INVPCID_TYPE_SINGLE_CTXT:
11120                 if (!pcid_enabled && (operand.pcid != 0)) {
11121                         kvm_inject_gp(vcpu, 0);
11122                         return 1;
11123                 }
11124
11125                 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
11126                         kvm_mmu_sync_roots(vcpu);
11127                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
11128                 }
11129
11130                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
11131                         if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd)
11132                             == operand.pcid)
11133                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
11134
11135                 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
11136                 /*
11137                  * If neither the current cr3 nor any of the prev_roots use the
11138                  * given PCID, then nothing needs to be done here because a
11139                  * resync will happen anyway before switching to any other CR3.
11140                  */
11141
11142                 return kvm_skip_emulated_instruction(vcpu);
11143
11144         case INVPCID_TYPE_ALL_NON_GLOBAL:
11145                 /*
11146                  * Currently, KVM doesn't mark global entries in the shadow
11147                  * page tables, so a non-global flush just degenerates to a
11148                  * global flush. If needed, we could optimize this later by
11149                  * keeping track of global entries in shadow page tables.
11150                  */
11151
11152                 fallthrough;
11153         case INVPCID_TYPE_ALL_INCL_GLOBAL:
11154                 kvm_mmu_unload(vcpu);
11155                 return kvm_skip_emulated_instruction(vcpu);
11156
11157         default:
11158                 BUG(); /* We have already checked above that type <= 3 */
11159         }
11160 }
11161 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
11162
11163 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
11164 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
11165 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
11166 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
11167 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
11168 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
11169 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
11170 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
11171 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
11172 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
11173 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
11174 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
11175 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
11176 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
11177 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
11178 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
11179 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
11180 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
11181 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
11182 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
11183 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
11184 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);