2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <trace/events/kvm.h>
51 #define CREATE_TRACE_POINTS
54 #include <asm/debugreg.h>
61 #include <asm/pvclock.h>
62 #include <asm/div64.h>
64 #define MAX_IO_MSRS 256
65 #define KVM_MAX_MCE_BANKS 32
66 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
68 #define emul_to_vcpu(ctxt) \
69 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
72 * - enable syscall per default because its emulated by KVM
73 * - enable LME and LMA per default on 64 bit KVM
77 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
79 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
82 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
83 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
85 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
86 static void process_nmi(struct kvm_vcpu *vcpu);
88 struct kvm_x86_ops *kvm_x86_ops;
89 EXPORT_SYMBOL_GPL(kvm_x86_ops);
91 static bool ignore_msrs = 0;
92 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
94 bool kvm_has_tsc_control;
95 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
96 u32 kvm_max_guest_tsc_khz;
97 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
100 static u32 tsc_tolerance_ppm = 250;
101 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
103 #define KVM_NR_SHARED_MSRS 16
105 struct kvm_shared_msrs_global {
107 u32 msrs[KVM_NR_SHARED_MSRS];
110 struct kvm_shared_msrs {
111 struct user_return_notifier urn;
113 struct kvm_shared_msr_values {
116 } values[KVM_NR_SHARED_MSRS];
119 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
120 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
122 struct kvm_stats_debugfs_item debugfs_entries[] = {
123 { "pf_fixed", VCPU_STAT(pf_fixed) },
124 { "pf_guest", VCPU_STAT(pf_guest) },
125 { "tlb_flush", VCPU_STAT(tlb_flush) },
126 { "invlpg", VCPU_STAT(invlpg) },
127 { "exits", VCPU_STAT(exits) },
128 { "io_exits", VCPU_STAT(io_exits) },
129 { "mmio_exits", VCPU_STAT(mmio_exits) },
130 { "signal_exits", VCPU_STAT(signal_exits) },
131 { "irq_window", VCPU_STAT(irq_window_exits) },
132 { "nmi_window", VCPU_STAT(nmi_window_exits) },
133 { "halt_exits", VCPU_STAT(halt_exits) },
134 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
135 { "hypercalls", VCPU_STAT(hypercalls) },
136 { "request_irq", VCPU_STAT(request_irq_exits) },
137 { "irq_exits", VCPU_STAT(irq_exits) },
138 { "host_state_reload", VCPU_STAT(host_state_reload) },
139 { "efer_reload", VCPU_STAT(efer_reload) },
140 { "fpu_reload", VCPU_STAT(fpu_reload) },
141 { "insn_emulation", VCPU_STAT(insn_emulation) },
142 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
143 { "irq_injections", VCPU_STAT(irq_injections) },
144 { "nmi_injections", VCPU_STAT(nmi_injections) },
145 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
146 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
147 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
148 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
149 { "mmu_flooded", VM_STAT(mmu_flooded) },
150 { "mmu_recycled", VM_STAT(mmu_recycled) },
151 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
152 { "mmu_unsync", VM_STAT(mmu_unsync) },
153 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
154 { "largepages", VM_STAT(lpages) },
158 u64 __read_mostly host_xcr0;
160 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
162 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
165 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
166 vcpu->arch.apf.gfns[i] = ~0;
169 static void kvm_on_user_return(struct user_return_notifier *urn)
172 struct kvm_shared_msrs *locals
173 = container_of(urn, struct kvm_shared_msrs, urn);
174 struct kvm_shared_msr_values *values;
176 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
177 values = &locals->values[slot];
178 if (values->host != values->curr) {
179 wrmsrl(shared_msrs_global.msrs[slot], values->host);
180 values->curr = values->host;
183 locals->registered = false;
184 user_return_notifier_unregister(urn);
187 static void shared_msr_update(unsigned slot, u32 msr)
189 struct kvm_shared_msrs *smsr;
192 smsr = &__get_cpu_var(shared_msrs);
193 /* only read, and nobody should modify it at this time,
194 * so don't need lock */
195 if (slot >= shared_msrs_global.nr) {
196 printk(KERN_ERR "kvm: invalid MSR slot!");
199 rdmsrl_safe(msr, &value);
200 smsr->values[slot].host = value;
201 smsr->values[slot].curr = value;
204 void kvm_define_shared_msr(unsigned slot, u32 msr)
206 if (slot >= shared_msrs_global.nr)
207 shared_msrs_global.nr = slot + 1;
208 shared_msrs_global.msrs[slot] = msr;
209 /* we need ensured the shared_msr_global have been updated */
212 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
214 static void kvm_shared_msr_cpu_online(void)
218 for (i = 0; i < shared_msrs_global.nr; ++i)
219 shared_msr_update(i, shared_msrs_global.msrs[i]);
222 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
224 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
226 if (((value ^ smsr->values[slot].curr) & mask) == 0)
228 smsr->values[slot].curr = value;
229 wrmsrl(shared_msrs_global.msrs[slot], value);
230 if (!smsr->registered) {
231 smsr->urn.on_user_return = kvm_on_user_return;
232 user_return_notifier_register(&smsr->urn);
233 smsr->registered = true;
236 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
238 static void drop_user_return_notifiers(void *ignore)
240 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
242 if (smsr->registered)
243 kvm_on_user_return(&smsr->urn);
246 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
248 if (irqchip_in_kernel(vcpu->kvm))
249 return vcpu->arch.apic_base;
251 return vcpu->arch.apic_base;
253 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
255 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
257 /* TODO: reserve bits check */
258 if (irqchip_in_kernel(vcpu->kvm))
259 kvm_lapic_set_base(vcpu, data);
261 vcpu->arch.apic_base = data;
263 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
265 #define EXCPT_BENIGN 0
266 #define EXCPT_CONTRIBUTORY 1
269 static int exception_class(int vector)
279 return EXCPT_CONTRIBUTORY;
286 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
287 unsigned nr, bool has_error, u32 error_code,
293 kvm_make_request(KVM_REQ_EVENT, vcpu);
295 if (!vcpu->arch.exception.pending) {
297 vcpu->arch.exception.pending = true;
298 vcpu->arch.exception.has_error_code = has_error;
299 vcpu->arch.exception.nr = nr;
300 vcpu->arch.exception.error_code = error_code;
301 vcpu->arch.exception.reinject = reinject;
305 /* to check exception */
306 prev_nr = vcpu->arch.exception.nr;
307 if (prev_nr == DF_VECTOR) {
308 /* triple fault -> shutdown */
309 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
312 class1 = exception_class(prev_nr);
313 class2 = exception_class(nr);
314 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
315 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
316 /* generate double fault per SDM Table 5-5 */
317 vcpu->arch.exception.pending = true;
318 vcpu->arch.exception.has_error_code = true;
319 vcpu->arch.exception.nr = DF_VECTOR;
320 vcpu->arch.exception.error_code = 0;
322 /* replace previous exception with a new one in a hope
323 that instruction re-execution will regenerate lost
328 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330 kvm_multiple_exception(vcpu, nr, false, 0, false);
332 EXPORT_SYMBOL_GPL(kvm_queue_exception);
334 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
336 kvm_multiple_exception(vcpu, nr, false, 0, true);
338 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
340 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
343 kvm_inject_gp(vcpu, 0);
345 kvm_x86_ops->skip_emulated_instruction(vcpu);
347 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
349 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
351 ++vcpu->stat.pf_guest;
352 vcpu->arch.cr2 = fault->address;
353 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
355 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
357 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
359 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
360 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
362 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
365 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
367 atomic_inc(&vcpu->arch.nmi_queued);
368 kvm_make_request(KVM_REQ_NMI, vcpu);
370 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
372 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374 kvm_multiple_exception(vcpu, nr, true, error_code, false);
376 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
378 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
380 kvm_multiple_exception(vcpu, nr, true, error_code, true);
382 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
385 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
386 * a #GP and return false.
388 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
390 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
392 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
395 EXPORT_SYMBOL_GPL(kvm_require_cpl);
398 * This function will be used to read from the physical memory of the currently
399 * running guest. The difference to kvm_read_guest_page is that this function
400 * can read from guest physical or from the guest's guest physical memory.
402 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
403 gfn_t ngfn, void *data, int offset, int len,
409 ngpa = gfn_to_gpa(ngfn);
410 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
411 if (real_gfn == UNMAPPED_GVA)
414 real_gfn = gpa_to_gfn(real_gfn);
416 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
418 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
420 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
421 void *data, int offset, int len, u32 access)
423 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
424 data, offset, len, access);
428 * Load the pae pdptrs. Return true is they are all valid.
430 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
432 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
433 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
436 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
438 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
439 offset * sizeof(u64), sizeof(pdpte),
440 PFERR_USER_MASK|PFERR_WRITE_MASK);
445 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
446 if (is_present_gpte(pdpte[i]) &&
447 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
454 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
455 __set_bit(VCPU_EXREG_PDPTR,
456 (unsigned long *)&vcpu->arch.regs_avail);
457 __set_bit(VCPU_EXREG_PDPTR,
458 (unsigned long *)&vcpu->arch.regs_dirty);
463 EXPORT_SYMBOL_GPL(load_pdptrs);
465 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
467 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
473 if (is_long_mode(vcpu) || !is_pae(vcpu))
476 if (!test_bit(VCPU_EXREG_PDPTR,
477 (unsigned long *)&vcpu->arch.regs_avail))
480 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
481 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
482 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
483 PFERR_USER_MASK | PFERR_WRITE_MASK);
486 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
492 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
494 unsigned long old_cr0 = kvm_read_cr0(vcpu);
495 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
496 X86_CR0_CD | X86_CR0_NW;
501 if (cr0 & 0xffffffff00000000UL)
505 cr0 &= ~CR0_RESERVED_BITS;
507 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
510 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
513 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
515 if ((vcpu->arch.efer & EFER_LME)) {
520 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
525 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
530 kvm_x86_ops->set_cr0(vcpu, cr0);
532 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
533 kvm_clear_async_pf_completion_queue(vcpu);
534 kvm_async_pf_hash_reset(vcpu);
537 if ((cr0 ^ old_cr0) & update_bits)
538 kvm_mmu_reset_context(vcpu);
541 EXPORT_SYMBOL_GPL(kvm_set_cr0);
543 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
545 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
547 EXPORT_SYMBOL_GPL(kvm_lmsw);
549 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
553 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
554 if (index != XCR_XFEATURE_ENABLED_MASK)
557 if (kvm_x86_ops->get_cpl(vcpu) != 0)
559 if (!(xcr0 & XSTATE_FP))
561 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
563 if (xcr0 & ~host_xcr0)
565 vcpu->arch.xcr0 = xcr0;
566 vcpu->guest_xcr0_loaded = 0;
570 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
572 if (__kvm_set_xcr(vcpu, index, xcr)) {
573 kvm_inject_gp(vcpu, 0);
578 EXPORT_SYMBOL_GPL(kvm_set_xcr);
580 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
582 unsigned long old_cr4 = kvm_read_cr4(vcpu);
583 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
584 X86_CR4_PAE | X86_CR4_SMEP;
585 if (cr4 & CR4_RESERVED_BITS)
588 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
591 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
594 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
597 if (is_long_mode(vcpu)) {
598 if (!(cr4 & X86_CR4_PAE))
600 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
601 && ((cr4 ^ old_cr4) & pdptr_bits)
602 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
606 if (kvm_x86_ops->set_cr4(vcpu, cr4))
609 if ((cr4 ^ old_cr4) & pdptr_bits)
610 kvm_mmu_reset_context(vcpu);
612 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
613 kvm_update_cpuid(vcpu);
617 EXPORT_SYMBOL_GPL(kvm_set_cr4);
619 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
621 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
622 kvm_mmu_sync_roots(vcpu);
623 kvm_mmu_flush_tlb(vcpu);
627 if (is_long_mode(vcpu)) {
628 if (cr3 & CR3_L_MODE_RESERVED_BITS)
632 if (cr3 & CR3_PAE_RESERVED_BITS)
634 if (is_paging(vcpu) &&
635 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
639 * We don't check reserved bits in nonpae mode, because
640 * this isn't enforced, and VMware depends on this.
645 * Does the new cr3 value map to physical memory? (Note, we
646 * catch an invalid cr3 even in real-mode, because it would
647 * cause trouble later on when we turn on paging anyway.)
649 * A real CPU would silently accept an invalid cr3 and would
650 * attempt to use it - with largely undefined (and often hard
651 * to debug) behavior on the guest side.
653 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
655 vcpu->arch.cr3 = cr3;
656 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
657 vcpu->arch.mmu.new_cr3(vcpu);
660 EXPORT_SYMBOL_GPL(kvm_set_cr3);
662 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
664 if (cr8 & CR8_RESERVED_BITS)
666 if (irqchip_in_kernel(vcpu->kvm))
667 kvm_lapic_set_tpr(vcpu, cr8);
669 vcpu->arch.cr8 = cr8;
672 EXPORT_SYMBOL_GPL(kvm_set_cr8);
674 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
676 if (irqchip_in_kernel(vcpu->kvm))
677 return kvm_lapic_get_cr8(vcpu);
679 return vcpu->arch.cr8;
681 EXPORT_SYMBOL_GPL(kvm_get_cr8);
683 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
687 vcpu->arch.db[dr] = val;
688 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
689 vcpu->arch.eff_db[dr] = val;
692 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
696 if (val & 0xffffffff00000000ULL)
698 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
701 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705 if (val & 0xffffffff00000000ULL)
707 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
708 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
709 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
710 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
718 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
722 res = __kvm_set_dr(vcpu, dr, val);
724 kvm_queue_exception(vcpu, UD_VECTOR);
726 kvm_inject_gp(vcpu, 0);
730 EXPORT_SYMBOL_GPL(kvm_set_dr);
732 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
736 *val = vcpu->arch.db[dr];
739 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
743 *val = vcpu->arch.dr6;
746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
750 *val = vcpu->arch.dr7;
757 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
759 if (_kvm_get_dr(vcpu, dr, val)) {
760 kvm_queue_exception(vcpu, UD_VECTOR);
765 EXPORT_SYMBOL_GPL(kvm_get_dr);
767 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
769 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
773 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
776 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
777 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
780 EXPORT_SYMBOL_GPL(kvm_rdpmc);
783 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
784 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
786 * This list is modified at module load time to reflect the
787 * capabilities of the host cpu. This capabilities test skips MSRs that are
788 * kvm-specific. Those are put in the beginning of the list.
791 #define KVM_SAVE_MSRS_BEGIN 9
792 static u32 msrs_to_save[] = {
793 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
794 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
795 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
796 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
797 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
800 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
802 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
805 static unsigned num_msrs_to_save;
807 static u32 emulated_msrs[] = {
808 MSR_IA32_TSCDEADLINE,
809 MSR_IA32_MISC_ENABLE,
814 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
816 u64 old_efer = vcpu->arch.efer;
818 if (efer & efer_reserved_bits)
822 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
825 if (efer & EFER_FFXSR) {
826 struct kvm_cpuid_entry2 *feat;
828 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
829 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
833 if (efer & EFER_SVME) {
834 struct kvm_cpuid_entry2 *feat;
836 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
837 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
842 efer |= vcpu->arch.efer & EFER_LMA;
844 kvm_x86_ops->set_efer(vcpu, efer);
846 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
848 /* Update reserved bits */
849 if ((efer ^ old_efer) & EFER_NX)
850 kvm_mmu_reset_context(vcpu);
855 void kvm_enable_efer_bits(u64 mask)
857 efer_reserved_bits &= ~mask;
859 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
863 * Writes msr value into into the appropriate "register".
864 * Returns 0 on success, non-0 otherwise.
865 * Assumes vcpu_load() was already called.
867 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
869 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
873 * Adapt set_msr() to msr_io()'s calling convention
875 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
877 return kvm_set_msr(vcpu, index, *data);
880 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
884 struct pvclock_wall_clock wc;
885 struct timespec boot;
890 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
895 ++version; /* first time write, random junk */
899 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
902 * The guest calculates current wall clock time by adding
903 * system time (updated by kvm_guest_time_update below) to the
904 * wall clock specified here. guest system time equals host
905 * system time for us, thus we must fill in host boot time here.
909 wc.sec = boot.tv_sec;
910 wc.nsec = boot.tv_nsec;
911 wc.version = version;
913 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
916 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
919 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
921 uint32_t quotient, remainder;
923 /* Don't try to replace with do_div(), this one calculates
924 * "(dividend << 32) / divisor" */
926 : "=a" (quotient), "=d" (remainder)
927 : "0" (0), "1" (dividend), "r" (divisor) );
931 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
932 s8 *pshift, u32 *pmultiplier)
939 tps64 = base_khz * 1000LL;
940 scaled64 = scaled_khz * 1000LL;
941 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
946 tps32 = (uint32_t)tps64;
947 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
948 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
956 *pmultiplier = div_frac(scaled64, tps32);
958 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
959 __func__, base_khz, scaled_khz, shift, *pmultiplier);
962 static inline u64 get_kernel_ns(void)
966 WARN_ON(preemptible());
968 monotonic_to_bootbased(&ts);
969 return timespec_to_ns(&ts);
972 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
973 unsigned long max_tsc_khz;
975 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
977 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
978 vcpu->arch.virtual_tsc_shift);
981 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
983 u64 v = (u64)khz * (1000000 + ppm);
988 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
990 u32 thresh_lo, thresh_hi;
993 /* Compute a scale to convert nanoseconds in TSC cycles */
994 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
995 &vcpu->arch.virtual_tsc_shift,
996 &vcpu->arch.virtual_tsc_mult);
997 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1000 * Compute the variation in TSC rate which is acceptable
1001 * within the range of tolerance and decide if the
1002 * rate being applied is within that bounds of the hardware
1003 * rate. If so, no scaling or compensation need be done.
1005 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1006 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1007 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1008 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1011 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1014 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1016 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1017 vcpu->arch.virtual_tsc_mult,
1018 vcpu->arch.virtual_tsc_shift);
1019 tsc += vcpu->arch.last_tsc_write;
1023 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1025 struct kvm *kvm = vcpu->kvm;
1026 u64 offset, ns, elapsed;
1027 unsigned long flags;
1030 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1031 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1032 ns = get_kernel_ns();
1033 elapsed = ns - kvm->arch.last_tsc_nsec;
1035 /* n.b - signed multiplication and division required */
1036 nsdiff = data - kvm->arch.last_tsc_write;
1037 #ifdef CONFIG_X86_64
1038 nsdiff = (nsdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1040 /* do_div() only does unsigned */
1041 asm("idivl %2; xor %%edx, %%edx"
1043 : "A"(nsdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1050 * Special case: TSC write with a small delta (1 second) of virtual
1051 * cycle time against real time is interpreted as an attempt to
1052 * synchronize the CPU.
1054 * For a reliable TSC, we can match TSC offsets, and for an unstable
1055 * TSC, we add elapsed time in this computation. We could let the
1056 * compensation code attempt to catch up if we fall behind, but
1057 * it's better to try to match offsets from the beginning.
1059 if (nsdiff < NSEC_PER_SEC &&
1060 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1061 if (!check_tsc_unstable()) {
1062 offset = kvm->arch.last_tsc_offset;
1063 pr_debug("kvm: matched tsc offset for %llu\n", data);
1065 u64 delta = nsec_to_cycles(vcpu, elapsed);
1067 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1068 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1071 kvm->arch.last_tsc_nsec = ns;
1072 kvm->arch.last_tsc_write = data;
1073 kvm->arch.last_tsc_offset = offset;
1074 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1075 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1076 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1078 /* Reset of TSC must disable overshoot protection below */
1079 vcpu->arch.hv_clock.tsc_timestamp = 0;
1080 vcpu->arch.last_tsc_write = data;
1081 vcpu->arch.last_tsc_nsec = ns;
1083 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1085 static int kvm_guest_time_update(struct kvm_vcpu *v)
1087 unsigned long flags;
1088 struct kvm_vcpu_arch *vcpu = &v->arch;
1090 unsigned long this_tsc_khz;
1091 s64 kernel_ns, max_kernel_ns;
1094 /* Keep irq disabled to prevent changes to the clock */
1095 local_irq_save(flags);
1096 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
1097 kernel_ns = get_kernel_ns();
1098 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1099 if (unlikely(this_tsc_khz == 0)) {
1100 local_irq_restore(flags);
1101 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1106 * We may have to catch up the TSC to match elapsed wall clock
1107 * time for two reasons, even if kvmclock is used.
1108 * 1) CPU could have been running below the maximum TSC rate
1109 * 2) Broken TSC compensation resets the base at each VCPU
1110 * entry to avoid unknown leaps of TSC even when running
1111 * again on the same CPU. This may cause apparent elapsed
1112 * time to disappear, and the guest to stand still or run
1115 if (vcpu->tsc_catchup) {
1116 u64 tsc = compute_guest_tsc(v, kernel_ns);
1117 if (tsc > tsc_timestamp) {
1118 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1119 tsc_timestamp = tsc;
1123 local_irq_restore(flags);
1125 if (!vcpu->time_page)
1129 * Time as measured by the TSC may go backwards when resetting the base
1130 * tsc_timestamp. The reason for this is that the TSC resolution is
1131 * higher than the resolution of the other clock scales. Thus, many
1132 * possible measurments of the TSC correspond to one measurement of any
1133 * other clock, and so a spread of values is possible. This is not a
1134 * problem for the computation of the nanosecond clock; with TSC rates
1135 * around 1GHZ, there can only be a few cycles which correspond to one
1136 * nanosecond value, and any path through this code will inevitably
1137 * take longer than that. However, with the kernel_ns value itself,
1138 * the precision may be much lower, down to HZ granularity. If the
1139 * first sampling of TSC against kernel_ns ends in the low part of the
1140 * range, and the second in the high end of the range, we can get:
1142 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1144 * As the sampling errors potentially range in the thousands of cycles,
1145 * it is possible such a time value has already been observed by the
1146 * guest. To protect against this, we must compute the system time as
1147 * observed by the guest and ensure the new system time is greater.
1150 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1151 max_kernel_ns = vcpu->last_guest_tsc -
1152 vcpu->hv_clock.tsc_timestamp;
1153 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1154 vcpu->hv_clock.tsc_to_system_mul,
1155 vcpu->hv_clock.tsc_shift);
1156 max_kernel_ns += vcpu->last_kernel_ns;
1159 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1160 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1161 &vcpu->hv_clock.tsc_shift,
1162 &vcpu->hv_clock.tsc_to_system_mul);
1163 vcpu->hw_tsc_khz = this_tsc_khz;
1166 if (max_kernel_ns > kernel_ns)
1167 kernel_ns = max_kernel_ns;
1169 /* With all the info we got, fill in the values */
1170 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1171 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1172 vcpu->last_kernel_ns = kernel_ns;
1173 vcpu->last_guest_tsc = tsc_timestamp;
1174 vcpu->hv_clock.flags = 0;
1177 * The interface expects us to write an even number signaling that the
1178 * update is finished. Since the guest won't see the intermediate
1179 * state, we just increase by 2 at the end.
1181 vcpu->hv_clock.version += 2;
1183 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1185 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1186 sizeof(vcpu->hv_clock));
1188 kunmap_atomic(shared_kaddr, KM_USER0);
1190 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1194 static bool msr_mtrr_valid(unsigned msr)
1197 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1198 case MSR_MTRRfix64K_00000:
1199 case MSR_MTRRfix16K_80000:
1200 case MSR_MTRRfix16K_A0000:
1201 case MSR_MTRRfix4K_C0000:
1202 case MSR_MTRRfix4K_C8000:
1203 case MSR_MTRRfix4K_D0000:
1204 case MSR_MTRRfix4K_D8000:
1205 case MSR_MTRRfix4K_E0000:
1206 case MSR_MTRRfix4K_E8000:
1207 case MSR_MTRRfix4K_F0000:
1208 case MSR_MTRRfix4K_F8000:
1209 case MSR_MTRRdefType:
1210 case MSR_IA32_CR_PAT:
1218 static bool valid_pat_type(unsigned t)
1220 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1223 static bool valid_mtrr_type(unsigned t)
1225 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1228 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1232 if (!msr_mtrr_valid(msr))
1235 if (msr == MSR_IA32_CR_PAT) {
1236 for (i = 0; i < 8; i++)
1237 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1240 } else if (msr == MSR_MTRRdefType) {
1243 return valid_mtrr_type(data & 0xff);
1244 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1245 for (i = 0; i < 8 ; i++)
1246 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1251 /* variable MTRRs */
1252 return valid_mtrr_type(data & 0xff);
1255 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1257 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1259 if (!mtrr_valid(vcpu, msr, data))
1262 if (msr == MSR_MTRRdefType) {
1263 vcpu->arch.mtrr_state.def_type = data;
1264 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1265 } else if (msr == MSR_MTRRfix64K_00000)
1267 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1268 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1269 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1270 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1271 else if (msr == MSR_IA32_CR_PAT)
1272 vcpu->arch.pat = data;
1273 else { /* Variable MTRRs */
1274 int idx, is_mtrr_mask;
1277 idx = (msr - 0x200) / 2;
1278 is_mtrr_mask = msr - 0x200 - 2 * idx;
1281 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1284 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1288 kvm_mmu_reset_context(vcpu);
1292 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1294 u64 mcg_cap = vcpu->arch.mcg_cap;
1295 unsigned bank_num = mcg_cap & 0xff;
1298 case MSR_IA32_MCG_STATUS:
1299 vcpu->arch.mcg_status = data;
1301 case MSR_IA32_MCG_CTL:
1302 if (!(mcg_cap & MCG_CTL_P))
1304 if (data != 0 && data != ~(u64)0)
1306 vcpu->arch.mcg_ctl = data;
1309 if (msr >= MSR_IA32_MC0_CTL &&
1310 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1311 u32 offset = msr - MSR_IA32_MC0_CTL;
1312 /* only 0 or all 1s can be written to IA32_MCi_CTL
1313 * some Linux kernels though clear bit 10 in bank 4 to
1314 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1315 * this to avoid an uncatched #GP in the guest
1317 if ((offset & 0x3) == 0 &&
1318 data != 0 && (data | (1 << 10)) != ~(u64)0)
1320 vcpu->arch.mce_banks[offset] = data;
1328 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1330 struct kvm *kvm = vcpu->kvm;
1331 int lm = is_long_mode(vcpu);
1332 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1333 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1334 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1335 : kvm->arch.xen_hvm_config.blob_size_32;
1336 u32 page_num = data & ~PAGE_MASK;
1337 u64 page_addr = data & PAGE_MASK;
1342 if (page_num >= blob_size)
1345 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1350 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1359 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1361 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1364 static bool kvm_hv_msr_partition_wide(u32 msr)
1368 case HV_X64_MSR_GUEST_OS_ID:
1369 case HV_X64_MSR_HYPERCALL:
1377 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1379 struct kvm *kvm = vcpu->kvm;
1382 case HV_X64_MSR_GUEST_OS_ID:
1383 kvm->arch.hv_guest_os_id = data;
1384 /* setting guest os id to zero disables hypercall page */
1385 if (!kvm->arch.hv_guest_os_id)
1386 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1388 case HV_X64_MSR_HYPERCALL: {
1393 /* if guest os id is not set hypercall should remain disabled */
1394 if (!kvm->arch.hv_guest_os_id)
1396 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1397 kvm->arch.hv_hypercall = data;
1400 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1401 addr = gfn_to_hva(kvm, gfn);
1402 if (kvm_is_error_hva(addr))
1404 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1405 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1406 if (__copy_to_user((void __user *)addr, instructions, 4))
1408 kvm->arch.hv_hypercall = data;
1412 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1413 "data 0x%llx\n", msr, data);
1419 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1422 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1425 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1426 vcpu->arch.hv_vapic = data;
1429 addr = gfn_to_hva(vcpu->kvm, data >>
1430 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1431 if (kvm_is_error_hva(addr))
1433 if (__clear_user((void __user *)addr, PAGE_SIZE))
1435 vcpu->arch.hv_vapic = data;
1438 case HV_X64_MSR_EOI:
1439 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1440 case HV_X64_MSR_ICR:
1441 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1442 case HV_X64_MSR_TPR:
1443 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1445 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1446 "data 0x%llx\n", msr, data);
1453 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1455 gpa_t gpa = data & ~0x3f;
1457 /* Bits 2:5 are resrved, Should be zero */
1461 vcpu->arch.apf.msr_val = data;
1463 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1464 kvm_clear_async_pf_completion_queue(vcpu);
1465 kvm_async_pf_hash_reset(vcpu);
1469 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1472 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1473 kvm_async_pf_wakeup_all(vcpu);
1477 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1479 if (vcpu->arch.time_page) {
1480 kvm_release_page_dirty(vcpu->arch.time_page);
1481 vcpu->arch.time_page = NULL;
1485 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1489 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1492 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1493 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1494 vcpu->arch.st.accum_steal = delta;
1497 static void record_steal_time(struct kvm_vcpu *vcpu)
1499 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1502 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1503 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1506 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1507 vcpu->arch.st.steal.version += 2;
1508 vcpu->arch.st.accum_steal = 0;
1510 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1511 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1514 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1520 return set_efer(vcpu, data);
1522 data &= ~(u64)0x40; /* ignore flush filter disable */
1523 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1525 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1530 case MSR_FAM10H_MMIO_CONF_BASE:
1532 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1537 case MSR_AMD64_NB_CFG:
1539 case MSR_IA32_DEBUGCTLMSR:
1541 /* We support the non-activated case already */
1543 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1544 /* Values other than LBR and BTF are vendor-specific,
1545 thus reserved and should throw a #GP */
1548 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1551 case MSR_IA32_UCODE_REV:
1552 case MSR_IA32_UCODE_WRITE:
1553 case MSR_VM_HSAVE_PA:
1554 case MSR_AMD64_PATCH_LOADER:
1556 case 0x200 ... 0x2ff:
1557 return set_msr_mtrr(vcpu, msr, data);
1558 case MSR_IA32_APICBASE:
1559 kvm_set_apic_base(vcpu, data);
1561 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1562 return kvm_x2apic_msr_write(vcpu, msr, data);
1563 case MSR_IA32_TSCDEADLINE:
1564 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1566 case MSR_IA32_MISC_ENABLE:
1567 vcpu->arch.ia32_misc_enable_msr = data;
1569 case MSR_KVM_WALL_CLOCK_NEW:
1570 case MSR_KVM_WALL_CLOCK:
1571 vcpu->kvm->arch.wall_clock = data;
1572 kvm_write_wall_clock(vcpu->kvm, data);
1574 case MSR_KVM_SYSTEM_TIME_NEW:
1575 case MSR_KVM_SYSTEM_TIME: {
1576 kvmclock_reset(vcpu);
1578 vcpu->arch.time = data;
1579 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1581 /* we verify if the enable bit is set... */
1585 /* ...but clean it before doing the actual write */
1586 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1588 vcpu->arch.time_page =
1589 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1591 if (is_error_page(vcpu->arch.time_page)) {
1592 kvm_release_page_clean(vcpu->arch.time_page);
1593 vcpu->arch.time_page = NULL;
1597 case MSR_KVM_ASYNC_PF_EN:
1598 if (kvm_pv_enable_async_pf(vcpu, data))
1601 case MSR_KVM_STEAL_TIME:
1603 if (unlikely(!sched_info_on()))
1606 if (data & KVM_STEAL_RESERVED_MASK)
1609 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1610 data & KVM_STEAL_VALID_BITS))
1613 vcpu->arch.st.msr_val = data;
1615 if (!(data & KVM_MSR_ENABLED))
1618 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1621 accumulate_steal_time(vcpu);
1624 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1628 case MSR_IA32_MCG_CTL:
1629 case MSR_IA32_MCG_STATUS:
1630 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1631 return set_msr_mce(vcpu, msr, data);
1633 /* Performance counters are not protected by a CPUID bit,
1634 * so we should check all of them in the generic path for the sake of
1635 * cross vendor migration.
1636 * Writing a zero into the event select MSRs disables them,
1637 * which we perfectly emulate ;-). Any other value should be at least
1638 * reported, some guests depend on them.
1640 case MSR_K7_EVNTSEL0:
1641 case MSR_K7_EVNTSEL1:
1642 case MSR_K7_EVNTSEL2:
1643 case MSR_K7_EVNTSEL3:
1645 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1646 "0x%x data 0x%llx\n", msr, data);
1648 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1649 * so we ignore writes to make it happy.
1651 case MSR_K7_PERFCTR0:
1652 case MSR_K7_PERFCTR1:
1653 case MSR_K7_PERFCTR2:
1654 case MSR_K7_PERFCTR3:
1655 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1656 "0x%x data 0x%llx\n", msr, data);
1658 case MSR_P6_PERFCTR0:
1659 case MSR_P6_PERFCTR1:
1661 case MSR_P6_EVNTSEL0:
1662 case MSR_P6_EVNTSEL1:
1663 if (kvm_pmu_msr(vcpu, msr))
1664 return kvm_pmu_set_msr(vcpu, msr, data);
1666 if (pr || data != 0)
1667 pr_unimpl(vcpu, "disabled perfctr wrmsr: "
1668 "0x%x data 0x%llx\n", msr, data);
1670 case MSR_K7_CLK_CTL:
1672 * Ignore all writes to this no longer documented MSR.
1673 * Writes are only relevant for old K7 processors,
1674 * all pre-dating SVM, but a recommended workaround from
1675 * AMD for these chips. It is possible to speicify the
1676 * affected processor models on the command line, hence
1677 * the need to ignore the workaround.
1680 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1681 if (kvm_hv_msr_partition_wide(msr)) {
1683 mutex_lock(&vcpu->kvm->lock);
1684 r = set_msr_hyperv_pw(vcpu, msr, data);
1685 mutex_unlock(&vcpu->kvm->lock);
1688 return set_msr_hyperv(vcpu, msr, data);
1690 case MSR_IA32_BBL_CR_CTL3:
1691 /* Drop writes to this legacy MSR -- see rdmsr
1692 * counterpart for further detail.
1694 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1696 case MSR_AMD64_OSVW_ID_LENGTH:
1697 if (!guest_cpuid_has_osvw(vcpu))
1699 vcpu->arch.osvw.length = data;
1701 case MSR_AMD64_OSVW_STATUS:
1702 if (!guest_cpuid_has_osvw(vcpu))
1704 vcpu->arch.osvw.status = data;
1707 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1708 return xen_hvm_config(vcpu, data);
1709 if (kvm_pmu_msr(vcpu, msr))
1710 return kvm_pmu_set_msr(vcpu, msr, data);
1712 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1716 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1723 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1727 * Reads an msr value (of 'msr_index') into 'pdata'.
1728 * Returns 0 on success, non-0 otherwise.
1729 * Assumes vcpu_load() was already called.
1731 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1733 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1736 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1738 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1740 if (!msr_mtrr_valid(msr))
1743 if (msr == MSR_MTRRdefType)
1744 *pdata = vcpu->arch.mtrr_state.def_type +
1745 (vcpu->arch.mtrr_state.enabled << 10);
1746 else if (msr == MSR_MTRRfix64K_00000)
1748 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1749 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1750 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1751 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1752 else if (msr == MSR_IA32_CR_PAT)
1753 *pdata = vcpu->arch.pat;
1754 else { /* Variable MTRRs */
1755 int idx, is_mtrr_mask;
1758 idx = (msr - 0x200) / 2;
1759 is_mtrr_mask = msr - 0x200 - 2 * idx;
1762 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1765 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1772 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1775 u64 mcg_cap = vcpu->arch.mcg_cap;
1776 unsigned bank_num = mcg_cap & 0xff;
1779 case MSR_IA32_P5_MC_ADDR:
1780 case MSR_IA32_P5_MC_TYPE:
1783 case MSR_IA32_MCG_CAP:
1784 data = vcpu->arch.mcg_cap;
1786 case MSR_IA32_MCG_CTL:
1787 if (!(mcg_cap & MCG_CTL_P))
1789 data = vcpu->arch.mcg_ctl;
1791 case MSR_IA32_MCG_STATUS:
1792 data = vcpu->arch.mcg_status;
1795 if (msr >= MSR_IA32_MC0_CTL &&
1796 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1797 u32 offset = msr - MSR_IA32_MC0_CTL;
1798 data = vcpu->arch.mce_banks[offset];
1807 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1810 struct kvm *kvm = vcpu->kvm;
1813 case HV_X64_MSR_GUEST_OS_ID:
1814 data = kvm->arch.hv_guest_os_id;
1816 case HV_X64_MSR_HYPERCALL:
1817 data = kvm->arch.hv_hypercall;
1820 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1828 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1833 case HV_X64_MSR_VP_INDEX: {
1836 kvm_for_each_vcpu(r, v, vcpu->kvm)
1841 case HV_X64_MSR_EOI:
1842 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1843 case HV_X64_MSR_ICR:
1844 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1845 case HV_X64_MSR_TPR:
1846 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1847 case HV_X64_MSR_APIC_ASSIST_PAGE:
1848 data = vcpu->arch.hv_vapic;
1851 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1858 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1863 case MSR_IA32_PLATFORM_ID:
1864 case MSR_IA32_EBL_CR_POWERON:
1865 case MSR_IA32_DEBUGCTLMSR:
1866 case MSR_IA32_LASTBRANCHFROMIP:
1867 case MSR_IA32_LASTBRANCHTOIP:
1868 case MSR_IA32_LASTINTFROMIP:
1869 case MSR_IA32_LASTINTTOIP:
1872 case MSR_VM_HSAVE_PA:
1873 case MSR_K7_EVNTSEL0:
1874 case MSR_K7_PERFCTR0:
1875 case MSR_K8_INT_PENDING_MSG:
1876 case MSR_AMD64_NB_CFG:
1877 case MSR_FAM10H_MMIO_CONF_BASE:
1880 case MSR_P6_PERFCTR0:
1881 case MSR_P6_PERFCTR1:
1882 case MSR_P6_EVNTSEL0:
1883 case MSR_P6_EVNTSEL1:
1884 if (kvm_pmu_msr(vcpu, msr))
1885 return kvm_pmu_get_msr(vcpu, msr, pdata);
1888 case MSR_IA32_UCODE_REV:
1889 data = 0x100000000ULL;
1892 data = 0x500 | KVM_NR_VAR_MTRR;
1894 case 0x200 ... 0x2ff:
1895 return get_msr_mtrr(vcpu, msr, pdata);
1896 case 0xcd: /* fsb frequency */
1900 * MSR_EBC_FREQUENCY_ID
1901 * Conservative value valid for even the basic CPU models.
1902 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1903 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1904 * and 266MHz for model 3, or 4. Set Core Clock
1905 * Frequency to System Bus Frequency Ratio to 1 (bits
1906 * 31:24) even though these are only valid for CPU
1907 * models > 2, however guests may end up dividing or
1908 * multiplying by zero otherwise.
1910 case MSR_EBC_FREQUENCY_ID:
1913 case MSR_IA32_APICBASE:
1914 data = kvm_get_apic_base(vcpu);
1916 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1917 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1919 case MSR_IA32_TSCDEADLINE:
1920 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1922 case MSR_IA32_MISC_ENABLE:
1923 data = vcpu->arch.ia32_misc_enable_msr;
1925 case MSR_IA32_PERF_STATUS:
1926 /* TSC increment by tick */
1928 /* CPU multiplier */
1929 data |= (((uint64_t)4ULL) << 40);
1932 data = vcpu->arch.efer;
1934 case MSR_KVM_WALL_CLOCK:
1935 case MSR_KVM_WALL_CLOCK_NEW:
1936 data = vcpu->kvm->arch.wall_clock;
1938 case MSR_KVM_SYSTEM_TIME:
1939 case MSR_KVM_SYSTEM_TIME_NEW:
1940 data = vcpu->arch.time;
1942 case MSR_KVM_ASYNC_PF_EN:
1943 data = vcpu->arch.apf.msr_val;
1945 case MSR_KVM_STEAL_TIME:
1946 data = vcpu->arch.st.msr_val;
1948 case MSR_IA32_P5_MC_ADDR:
1949 case MSR_IA32_P5_MC_TYPE:
1950 case MSR_IA32_MCG_CAP:
1951 case MSR_IA32_MCG_CTL:
1952 case MSR_IA32_MCG_STATUS:
1953 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1954 return get_msr_mce(vcpu, msr, pdata);
1955 case MSR_K7_CLK_CTL:
1957 * Provide expected ramp-up count for K7. All other
1958 * are set to zero, indicating minimum divisors for
1961 * This prevents guest kernels on AMD host with CPU
1962 * type 6, model 8 and higher from exploding due to
1963 * the rdmsr failing.
1967 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1968 if (kvm_hv_msr_partition_wide(msr)) {
1970 mutex_lock(&vcpu->kvm->lock);
1971 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1972 mutex_unlock(&vcpu->kvm->lock);
1975 return get_msr_hyperv(vcpu, msr, pdata);
1977 case MSR_IA32_BBL_CR_CTL3:
1978 /* This legacy MSR exists but isn't fully documented in current
1979 * silicon. It is however accessed by winxp in very narrow
1980 * scenarios where it sets bit #19, itself documented as
1981 * a "reserved" bit. Best effort attempt to source coherent
1982 * read data here should the balance of the register be
1983 * interpreted by the guest:
1985 * L2 cache control register 3: 64GB range, 256KB size,
1986 * enabled, latency 0x1, configured
1990 case MSR_AMD64_OSVW_ID_LENGTH:
1991 if (!guest_cpuid_has_osvw(vcpu))
1993 data = vcpu->arch.osvw.length;
1995 case MSR_AMD64_OSVW_STATUS:
1996 if (!guest_cpuid_has_osvw(vcpu))
1998 data = vcpu->arch.osvw.status;
2001 if (kvm_pmu_msr(vcpu, msr))
2002 return kvm_pmu_get_msr(vcpu, msr, pdata);
2004 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2007 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2015 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2018 * Read or write a bunch of msrs. All parameters are kernel addresses.
2020 * @return number of msrs set successfully.
2022 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2023 struct kvm_msr_entry *entries,
2024 int (*do_msr)(struct kvm_vcpu *vcpu,
2025 unsigned index, u64 *data))
2029 idx = srcu_read_lock(&vcpu->kvm->srcu);
2030 for (i = 0; i < msrs->nmsrs; ++i)
2031 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2033 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2039 * Read or write a bunch of msrs. Parameters are user addresses.
2041 * @return number of msrs set successfully.
2043 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2044 int (*do_msr)(struct kvm_vcpu *vcpu,
2045 unsigned index, u64 *data),
2048 struct kvm_msrs msrs;
2049 struct kvm_msr_entry *entries;
2054 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2058 if (msrs.nmsrs >= MAX_IO_MSRS)
2061 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2062 entries = memdup_user(user_msrs->entries, size);
2063 if (IS_ERR(entries)) {
2064 r = PTR_ERR(entries);
2068 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2073 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2084 int kvm_dev_ioctl_check_extension(long ext)
2089 case KVM_CAP_IRQCHIP:
2091 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2092 case KVM_CAP_SET_TSS_ADDR:
2093 case KVM_CAP_EXT_CPUID:
2094 case KVM_CAP_CLOCKSOURCE:
2096 case KVM_CAP_NOP_IO_DELAY:
2097 case KVM_CAP_MP_STATE:
2098 case KVM_CAP_SYNC_MMU:
2099 case KVM_CAP_USER_NMI:
2100 case KVM_CAP_REINJECT_CONTROL:
2101 case KVM_CAP_IRQ_INJECT_STATUS:
2102 case KVM_CAP_ASSIGN_DEV_IRQ:
2104 case KVM_CAP_IOEVENTFD:
2106 case KVM_CAP_PIT_STATE2:
2107 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2108 case KVM_CAP_XEN_HVM:
2109 case KVM_CAP_ADJUST_CLOCK:
2110 case KVM_CAP_VCPU_EVENTS:
2111 case KVM_CAP_HYPERV:
2112 case KVM_CAP_HYPERV_VAPIC:
2113 case KVM_CAP_HYPERV_SPIN:
2114 case KVM_CAP_PCI_SEGMENT:
2115 case KVM_CAP_DEBUGREGS:
2116 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2118 case KVM_CAP_ASYNC_PF:
2119 case KVM_CAP_GET_TSC_KHZ:
2122 case KVM_CAP_COALESCED_MMIO:
2123 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2126 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2128 case KVM_CAP_NR_VCPUS:
2129 r = KVM_SOFT_MAX_VCPUS;
2131 case KVM_CAP_MAX_VCPUS:
2134 case KVM_CAP_NR_MEMSLOTS:
2135 r = KVM_MEMORY_SLOTS;
2137 case KVM_CAP_PV_MMU: /* obsolete */
2141 r = iommu_present(&pci_bus_type);
2144 r = KVM_MAX_MCE_BANKS;
2149 case KVM_CAP_TSC_CONTROL:
2150 r = kvm_has_tsc_control;
2152 case KVM_CAP_TSC_DEADLINE_TIMER:
2153 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2163 long kvm_arch_dev_ioctl(struct file *filp,
2164 unsigned int ioctl, unsigned long arg)
2166 void __user *argp = (void __user *)arg;
2170 case KVM_GET_MSR_INDEX_LIST: {
2171 struct kvm_msr_list __user *user_msr_list = argp;
2172 struct kvm_msr_list msr_list;
2176 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2179 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2180 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2183 if (n < msr_list.nmsrs)
2186 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2187 num_msrs_to_save * sizeof(u32)))
2189 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2191 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2196 case KVM_GET_SUPPORTED_CPUID: {
2197 struct kvm_cpuid2 __user *cpuid_arg = argp;
2198 struct kvm_cpuid2 cpuid;
2201 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2203 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2204 cpuid_arg->entries);
2209 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2214 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2217 mce_cap = KVM_MCE_CAP_SUPPORTED;
2219 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2231 static void wbinvd_ipi(void *garbage)
2236 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2238 return vcpu->kvm->arch.iommu_domain &&
2239 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2242 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2244 /* Address WBINVD may be executed by guest */
2245 if (need_emulate_wbinvd(vcpu)) {
2246 if (kvm_x86_ops->has_wbinvd_exit())
2247 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2248 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2249 smp_call_function_single(vcpu->cpu,
2250 wbinvd_ipi, NULL, 1);
2253 kvm_x86_ops->vcpu_load(vcpu, cpu);
2254 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2255 /* Make sure TSC doesn't go backwards */
2259 tsc = kvm_x86_ops->read_l1_tsc(vcpu);
2260 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2261 tsc - vcpu->arch.last_guest_tsc;
2264 mark_tsc_unstable("KVM discovered backwards TSC");
2265 if (check_tsc_unstable()) {
2266 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
2267 vcpu->arch.tsc_catchup = 1;
2269 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2270 if (vcpu->cpu != cpu)
2271 kvm_migrate_timers(vcpu);
2275 accumulate_steal_time(vcpu);
2276 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2279 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2281 kvm_x86_ops->vcpu_put(vcpu);
2282 kvm_put_guest_fpu(vcpu);
2283 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
2286 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2287 struct kvm_lapic_state *s)
2289 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2294 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2295 struct kvm_lapic_state *s)
2297 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2298 kvm_apic_post_state_restore(vcpu);
2299 update_cr8_intercept(vcpu);
2304 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2305 struct kvm_interrupt *irq)
2307 if (irq->irq < 0 || irq->irq >= 256)
2309 if (irqchip_in_kernel(vcpu->kvm))
2312 kvm_queue_interrupt(vcpu, irq->irq, false);
2313 kvm_make_request(KVM_REQ_EVENT, vcpu);
2318 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2320 kvm_inject_nmi(vcpu);
2325 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2326 struct kvm_tpr_access_ctl *tac)
2330 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2334 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2338 unsigned bank_num = mcg_cap & 0xff, bank;
2341 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2343 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2346 vcpu->arch.mcg_cap = mcg_cap;
2347 /* Init IA32_MCG_CTL to all 1s */
2348 if (mcg_cap & MCG_CTL_P)
2349 vcpu->arch.mcg_ctl = ~(u64)0;
2350 /* Init IA32_MCi_CTL to all 1s */
2351 for (bank = 0; bank < bank_num; bank++)
2352 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2357 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2358 struct kvm_x86_mce *mce)
2360 u64 mcg_cap = vcpu->arch.mcg_cap;
2361 unsigned bank_num = mcg_cap & 0xff;
2362 u64 *banks = vcpu->arch.mce_banks;
2364 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2367 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2368 * reporting is disabled
2370 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2371 vcpu->arch.mcg_ctl != ~(u64)0)
2373 banks += 4 * mce->bank;
2375 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2376 * reporting is disabled for the bank
2378 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2380 if (mce->status & MCI_STATUS_UC) {
2381 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2382 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2383 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2386 if (banks[1] & MCI_STATUS_VAL)
2387 mce->status |= MCI_STATUS_OVER;
2388 banks[2] = mce->addr;
2389 banks[3] = mce->misc;
2390 vcpu->arch.mcg_status = mce->mcg_status;
2391 banks[1] = mce->status;
2392 kvm_queue_exception(vcpu, MC_VECTOR);
2393 } else if (!(banks[1] & MCI_STATUS_VAL)
2394 || !(banks[1] & MCI_STATUS_UC)) {
2395 if (banks[1] & MCI_STATUS_VAL)
2396 mce->status |= MCI_STATUS_OVER;
2397 banks[2] = mce->addr;
2398 banks[3] = mce->misc;
2399 banks[1] = mce->status;
2401 banks[1] |= MCI_STATUS_OVER;
2405 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2406 struct kvm_vcpu_events *events)
2409 events->exception.injected =
2410 vcpu->arch.exception.pending &&
2411 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2412 events->exception.nr = vcpu->arch.exception.nr;
2413 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2414 events->exception.pad = 0;
2415 events->exception.error_code = vcpu->arch.exception.error_code;
2417 events->interrupt.injected =
2418 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2419 events->interrupt.nr = vcpu->arch.interrupt.nr;
2420 events->interrupt.soft = 0;
2421 events->interrupt.shadow =
2422 kvm_x86_ops->get_interrupt_shadow(vcpu,
2423 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2425 events->nmi.injected = vcpu->arch.nmi_injected;
2426 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2427 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2428 events->nmi.pad = 0;
2430 events->sipi_vector = vcpu->arch.sipi_vector;
2432 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2433 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2434 | KVM_VCPUEVENT_VALID_SHADOW);
2435 memset(&events->reserved, 0, sizeof(events->reserved));
2438 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2439 struct kvm_vcpu_events *events)
2441 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2442 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2443 | KVM_VCPUEVENT_VALID_SHADOW))
2447 vcpu->arch.exception.pending = events->exception.injected;
2448 vcpu->arch.exception.nr = events->exception.nr;
2449 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2450 vcpu->arch.exception.error_code = events->exception.error_code;
2452 vcpu->arch.interrupt.pending = events->interrupt.injected;
2453 vcpu->arch.interrupt.nr = events->interrupt.nr;
2454 vcpu->arch.interrupt.soft = events->interrupt.soft;
2455 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2456 kvm_x86_ops->set_interrupt_shadow(vcpu,
2457 events->interrupt.shadow);
2459 vcpu->arch.nmi_injected = events->nmi.injected;
2460 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2461 vcpu->arch.nmi_pending = events->nmi.pending;
2462 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2464 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2465 vcpu->arch.sipi_vector = events->sipi_vector;
2467 kvm_make_request(KVM_REQ_EVENT, vcpu);
2472 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2473 struct kvm_debugregs *dbgregs)
2475 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2476 dbgregs->dr6 = vcpu->arch.dr6;
2477 dbgregs->dr7 = vcpu->arch.dr7;
2479 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2482 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2483 struct kvm_debugregs *dbgregs)
2488 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2489 vcpu->arch.dr6 = dbgregs->dr6;
2490 vcpu->arch.dr7 = dbgregs->dr7;
2495 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2496 struct kvm_xsave *guest_xsave)
2499 memcpy(guest_xsave->region,
2500 &vcpu->arch.guest_fpu.state->xsave,
2503 memcpy(guest_xsave->region,
2504 &vcpu->arch.guest_fpu.state->fxsave,
2505 sizeof(struct i387_fxsave_struct));
2506 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2511 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2512 struct kvm_xsave *guest_xsave)
2515 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2518 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2519 guest_xsave->region, xstate_size);
2521 if (xstate_bv & ~XSTATE_FPSSE)
2523 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2524 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2529 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2530 struct kvm_xcrs *guest_xcrs)
2532 if (!cpu_has_xsave) {
2533 guest_xcrs->nr_xcrs = 0;
2537 guest_xcrs->nr_xcrs = 1;
2538 guest_xcrs->flags = 0;
2539 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2540 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2543 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2544 struct kvm_xcrs *guest_xcrs)
2551 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2554 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2555 /* Only support XCR0 currently */
2556 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2557 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2558 guest_xcrs->xcrs[0].value);
2566 long kvm_arch_vcpu_ioctl(struct file *filp,
2567 unsigned int ioctl, unsigned long arg)
2569 struct kvm_vcpu *vcpu = filp->private_data;
2570 void __user *argp = (void __user *)arg;
2573 struct kvm_lapic_state *lapic;
2574 struct kvm_xsave *xsave;
2575 struct kvm_xcrs *xcrs;
2581 case KVM_GET_LAPIC: {
2583 if (!vcpu->arch.apic)
2585 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2590 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
2594 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
2599 case KVM_SET_LAPIC: {
2601 if (!vcpu->arch.apic)
2603 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2604 if (IS_ERR(u.lapic)) {
2605 r = PTR_ERR(u.lapic);
2609 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
2615 case KVM_INTERRUPT: {
2616 struct kvm_interrupt irq;
2619 if (copy_from_user(&irq, argp, sizeof irq))
2621 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2628 r = kvm_vcpu_ioctl_nmi(vcpu);
2634 case KVM_SET_CPUID: {
2635 struct kvm_cpuid __user *cpuid_arg = argp;
2636 struct kvm_cpuid cpuid;
2639 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2641 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2646 case KVM_SET_CPUID2: {
2647 struct kvm_cpuid2 __user *cpuid_arg = argp;
2648 struct kvm_cpuid2 cpuid;
2651 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2653 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
2654 cpuid_arg->entries);
2659 case KVM_GET_CPUID2: {
2660 struct kvm_cpuid2 __user *cpuid_arg = argp;
2661 struct kvm_cpuid2 cpuid;
2664 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2666 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
2667 cpuid_arg->entries);
2671 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2677 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2680 r = msr_io(vcpu, argp, do_set_msr, 0);
2682 case KVM_TPR_ACCESS_REPORTING: {
2683 struct kvm_tpr_access_ctl tac;
2686 if (copy_from_user(&tac, argp, sizeof tac))
2688 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2692 if (copy_to_user(argp, &tac, sizeof tac))
2697 case KVM_SET_VAPIC_ADDR: {
2698 struct kvm_vapic_addr va;
2701 if (!irqchip_in_kernel(vcpu->kvm))
2704 if (copy_from_user(&va, argp, sizeof va))
2707 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2710 case KVM_X86_SETUP_MCE: {
2714 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2716 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2719 case KVM_X86_SET_MCE: {
2720 struct kvm_x86_mce mce;
2723 if (copy_from_user(&mce, argp, sizeof mce))
2725 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2728 case KVM_GET_VCPU_EVENTS: {
2729 struct kvm_vcpu_events events;
2731 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2734 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2739 case KVM_SET_VCPU_EVENTS: {
2740 struct kvm_vcpu_events events;
2743 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2746 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2749 case KVM_GET_DEBUGREGS: {
2750 struct kvm_debugregs dbgregs;
2752 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2755 if (copy_to_user(argp, &dbgregs,
2756 sizeof(struct kvm_debugregs)))
2761 case KVM_SET_DEBUGREGS: {
2762 struct kvm_debugregs dbgregs;
2765 if (copy_from_user(&dbgregs, argp,
2766 sizeof(struct kvm_debugregs)))
2769 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2772 case KVM_GET_XSAVE: {
2773 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2778 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2781 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2786 case KVM_SET_XSAVE: {
2787 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2788 if (IS_ERR(u.xsave)) {
2789 r = PTR_ERR(u.xsave);
2793 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2796 case KVM_GET_XCRS: {
2797 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2802 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2805 if (copy_to_user(argp, u.xcrs,
2806 sizeof(struct kvm_xcrs)))
2811 case KVM_SET_XCRS: {
2812 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2813 if (IS_ERR(u.xcrs)) {
2814 r = PTR_ERR(u.xcrs);
2818 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2821 case KVM_SET_TSC_KHZ: {
2825 user_tsc_khz = (u32)arg;
2827 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2830 if (user_tsc_khz == 0)
2831 user_tsc_khz = tsc_khz;
2833 kvm_set_tsc_khz(vcpu, user_tsc_khz);
2838 case KVM_GET_TSC_KHZ: {
2839 r = vcpu->arch.virtual_tsc_khz;
2850 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2852 return VM_FAULT_SIGBUS;
2855 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2859 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2861 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2865 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2868 kvm->arch.ept_identity_map_addr = ident_addr;
2872 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2873 u32 kvm_nr_mmu_pages)
2875 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2878 mutex_lock(&kvm->slots_lock);
2879 spin_lock(&kvm->mmu_lock);
2881 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
2882 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
2884 spin_unlock(&kvm->mmu_lock);
2885 mutex_unlock(&kvm->slots_lock);
2889 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2891 return kvm->arch.n_max_mmu_pages;
2894 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2899 switch (chip->chip_id) {
2900 case KVM_IRQCHIP_PIC_MASTER:
2901 memcpy(&chip->chip.pic,
2902 &pic_irqchip(kvm)->pics[0],
2903 sizeof(struct kvm_pic_state));
2905 case KVM_IRQCHIP_PIC_SLAVE:
2906 memcpy(&chip->chip.pic,
2907 &pic_irqchip(kvm)->pics[1],
2908 sizeof(struct kvm_pic_state));
2910 case KVM_IRQCHIP_IOAPIC:
2911 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
2920 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2925 switch (chip->chip_id) {
2926 case KVM_IRQCHIP_PIC_MASTER:
2927 spin_lock(&pic_irqchip(kvm)->lock);
2928 memcpy(&pic_irqchip(kvm)->pics[0],
2930 sizeof(struct kvm_pic_state));
2931 spin_unlock(&pic_irqchip(kvm)->lock);
2933 case KVM_IRQCHIP_PIC_SLAVE:
2934 spin_lock(&pic_irqchip(kvm)->lock);
2935 memcpy(&pic_irqchip(kvm)->pics[1],
2937 sizeof(struct kvm_pic_state));
2938 spin_unlock(&pic_irqchip(kvm)->lock);
2940 case KVM_IRQCHIP_IOAPIC:
2941 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
2947 kvm_pic_update_irq(pic_irqchip(kvm));
2951 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2955 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2956 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
2957 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2961 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2965 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2966 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
2967 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2968 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2972 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2976 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2977 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2978 sizeof(ps->channels));
2979 ps->flags = kvm->arch.vpit->pit_state.flags;
2980 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2981 memset(&ps->reserved, 0, sizeof(ps->reserved));
2985 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2987 int r = 0, start = 0;
2988 u32 prev_legacy, cur_legacy;
2989 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2990 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2991 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2992 if (!prev_legacy && cur_legacy)
2994 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2995 sizeof(kvm->arch.vpit->pit_state.channels));
2996 kvm->arch.vpit->pit_state.flags = ps->flags;
2997 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
2998 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3002 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3003 struct kvm_reinject_control *control)
3005 if (!kvm->arch.vpit)
3007 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3008 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
3009 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3014 * write_protect_slot - write protect a slot for dirty logging
3015 * @kvm: the kvm instance
3016 * @memslot: the slot we protect
3017 * @dirty_bitmap: the bitmap indicating which pages are dirty
3018 * @nr_dirty_pages: the number of dirty pages
3020 * We have two ways to find all sptes to protect:
3021 * 1. Use kvm_mmu_slot_remove_write_access() which walks all shadow pages and
3022 * checks ones that have a spte mapping a page in the slot.
3023 * 2. Use kvm_mmu_rmap_write_protect() for each gfn found in the bitmap.
3025 * Generally speaking, if there are not so many dirty pages compared to the
3026 * number of shadow pages, we should use the latter.
3028 * Note that letting others write into a page marked dirty in the old bitmap
3029 * by using the remaining tlb entry is not a problem. That page will become
3030 * write protected again when we flush the tlb and then be reported dirty to
3031 * the user space by copying the old bitmap.
3033 static void write_protect_slot(struct kvm *kvm,
3034 struct kvm_memory_slot *memslot,
3035 unsigned long *dirty_bitmap,
3036 unsigned long nr_dirty_pages)
3038 /* Not many dirty pages compared to # of shadow pages. */
3039 if (nr_dirty_pages < kvm->arch.n_used_mmu_pages) {
3040 unsigned long gfn_offset;
3042 for_each_set_bit(gfn_offset, dirty_bitmap, memslot->npages) {
3043 unsigned long gfn = memslot->base_gfn + gfn_offset;
3045 spin_lock(&kvm->mmu_lock);
3046 kvm_mmu_rmap_write_protect(kvm, gfn, memslot);
3047 spin_unlock(&kvm->mmu_lock);
3049 kvm_flush_remote_tlbs(kvm);
3051 spin_lock(&kvm->mmu_lock);
3052 kvm_mmu_slot_remove_write_access(kvm, memslot->id);
3053 spin_unlock(&kvm->mmu_lock);
3058 * Get (and clear) the dirty memory log for a memory slot.
3060 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3061 struct kvm_dirty_log *log)
3064 struct kvm_memory_slot *memslot;
3065 unsigned long n, nr_dirty_pages;
3067 mutex_lock(&kvm->slots_lock);
3070 if (log->slot >= KVM_MEMORY_SLOTS)
3073 memslot = id_to_memslot(kvm->memslots, log->slot);
3075 if (!memslot->dirty_bitmap)
3078 n = kvm_dirty_bitmap_bytes(memslot);
3079 nr_dirty_pages = memslot->nr_dirty_pages;
3081 /* If nothing is dirty, don't bother messing with page tables. */
3082 if (nr_dirty_pages) {
3083 struct kvm_memslots *slots, *old_slots;
3084 unsigned long *dirty_bitmap, *dirty_bitmap_head;
3086 dirty_bitmap = memslot->dirty_bitmap;
3087 dirty_bitmap_head = memslot->dirty_bitmap_head;
3088 if (dirty_bitmap == dirty_bitmap_head)
3089 dirty_bitmap_head += n / sizeof(long);
3090 memset(dirty_bitmap_head, 0, n);
3093 slots = kmemdup(kvm->memslots, sizeof(*kvm->memslots), GFP_KERNEL);
3097 memslot = id_to_memslot(slots, log->slot);
3098 memslot->nr_dirty_pages = 0;
3099 memslot->dirty_bitmap = dirty_bitmap_head;
3100 update_memslots(slots, NULL);
3102 old_slots = kvm->memslots;
3103 rcu_assign_pointer(kvm->memslots, slots);
3104 synchronize_srcu_expedited(&kvm->srcu);
3107 write_protect_slot(kvm, memslot, dirty_bitmap, nr_dirty_pages);
3110 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
3114 if (clear_user(log->dirty_bitmap, n))
3120 mutex_unlock(&kvm->slots_lock);
3124 long kvm_arch_vm_ioctl(struct file *filp,
3125 unsigned int ioctl, unsigned long arg)
3127 struct kvm *kvm = filp->private_data;
3128 void __user *argp = (void __user *)arg;
3131 * This union makes it completely explicit to gcc-3.x
3132 * that these two variables' stack usage should be
3133 * combined, not added together.
3136 struct kvm_pit_state ps;
3137 struct kvm_pit_state2 ps2;
3138 struct kvm_pit_config pit_config;
3142 case KVM_SET_TSS_ADDR:
3143 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3147 case KVM_SET_IDENTITY_MAP_ADDR: {
3151 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3153 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3158 case KVM_SET_NR_MMU_PAGES:
3159 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3163 case KVM_GET_NR_MMU_PAGES:
3164 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3166 case KVM_CREATE_IRQCHIP: {
3167 struct kvm_pic *vpic;
3169 mutex_lock(&kvm->lock);
3172 goto create_irqchip_unlock;
3174 vpic = kvm_create_pic(kvm);
3176 r = kvm_ioapic_init(kvm);
3178 mutex_lock(&kvm->slots_lock);
3179 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3181 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3183 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3185 mutex_unlock(&kvm->slots_lock);
3187 goto create_irqchip_unlock;
3190 goto create_irqchip_unlock;
3192 kvm->arch.vpic = vpic;
3194 r = kvm_setup_default_irq_routing(kvm);
3196 mutex_lock(&kvm->slots_lock);
3197 mutex_lock(&kvm->irq_lock);
3198 kvm_ioapic_destroy(kvm);
3199 kvm_destroy_pic(kvm);
3200 mutex_unlock(&kvm->irq_lock);
3201 mutex_unlock(&kvm->slots_lock);
3203 create_irqchip_unlock:
3204 mutex_unlock(&kvm->lock);
3207 case KVM_CREATE_PIT:
3208 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3210 case KVM_CREATE_PIT2:
3212 if (copy_from_user(&u.pit_config, argp,
3213 sizeof(struct kvm_pit_config)))
3216 mutex_lock(&kvm->slots_lock);
3219 goto create_pit_unlock;
3221 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3225 mutex_unlock(&kvm->slots_lock);
3227 case KVM_IRQ_LINE_STATUS:
3228 case KVM_IRQ_LINE: {
3229 struct kvm_irq_level irq_event;
3232 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3235 if (irqchip_in_kernel(kvm)) {
3237 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3238 irq_event.irq, irq_event.level);
3239 if (ioctl == KVM_IRQ_LINE_STATUS) {
3241 irq_event.status = status;
3242 if (copy_to_user(argp, &irq_event,
3250 case KVM_GET_IRQCHIP: {
3251 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3252 struct kvm_irqchip *chip;
3254 chip = memdup_user(argp, sizeof(*chip));
3261 if (!irqchip_in_kernel(kvm))
3262 goto get_irqchip_out;
3263 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3265 goto get_irqchip_out;
3267 if (copy_to_user(argp, chip, sizeof *chip))
3268 goto get_irqchip_out;
3276 case KVM_SET_IRQCHIP: {
3277 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3278 struct kvm_irqchip *chip;
3280 chip = memdup_user(argp, sizeof(*chip));
3287 if (!irqchip_in_kernel(kvm))
3288 goto set_irqchip_out;
3289 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3291 goto set_irqchip_out;
3301 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3304 if (!kvm->arch.vpit)
3306 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3310 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3317 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3320 if (!kvm->arch.vpit)
3322 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3328 case KVM_GET_PIT2: {
3330 if (!kvm->arch.vpit)
3332 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3336 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3341 case KVM_SET_PIT2: {
3343 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3346 if (!kvm->arch.vpit)
3348 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3354 case KVM_REINJECT_CONTROL: {
3355 struct kvm_reinject_control control;
3357 if (copy_from_user(&control, argp, sizeof(control)))
3359 r = kvm_vm_ioctl_reinject(kvm, &control);
3365 case KVM_XEN_HVM_CONFIG: {
3367 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3368 sizeof(struct kvm_xen_hvm_config)))
3371 if (kvm->arch.xen_hvm_config.flags)
3376 case KVM_SET_CLOCK: {
3377 struct kvm_clock_data user_ns;
3382 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3390 local_irq_disable();
3391 now_ns = get_kernel_ns();
3392 delta = user_ns.clock - now_ns;
3394 kvm->arch.kvmclock_offset = delta;
3397 case KVM_GET_CLOCK: {
3398 struct kvm_clock_data user_ns;
3401 local_irq_disable();
3402 now_ns = get_kernel_ns();
3403 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3406 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3409 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3422 static void kvm_init_msr_list(void)
3427 /* skip the first msrs in the list. KVM-specific */
3428 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3429 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3432 msrs_to_save[j] = msrs_to_save[i];
3435 num_msrs_to_save = j;
3438 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3446 if (!(vcpu->arch.apic &&
3447 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3448 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3459 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3466 if (!(vcpu->arch.apic &&
3467 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3468 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3470 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3480 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3481 struct kvm_segment *var, int seg)
3483 kvm_x86_ops->set_segment(vcpu, var, seg);
3486 void kvm_get_segment(struct kvm_vcpu *vcpu,
3487 struct kvm_segment *var, int seg)
3489 kvm_x86_ops->get_segment(vcpu, var, seg);
3492 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3495 struct x86_exception exception;
3497 BUG_ON(!mmu_is_nested(vcpu));
3499 /* NPT walks are always user-walks */
3500 access |= PFERR_USER_MASK;
3501 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3506 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3507 struct x86_exception *exception)
3509 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3510 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3513 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3514 struct x86_exception *exception)
3516 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3517 access |= PFERR_FETCH_MASK;
3518 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3521 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3522 struct x86_exception *exception)
3524 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3525 access |= PFERR_WRITE_MASK;
3526 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3529 /* uses this to access any guest's mapped memory without checking CPL */
3530 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3531 struct x86_exception *exception)
3533 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3536 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3537 struct kvm_vcpu *vcpu, u32 access,
3538 struct x86_exception *exception)
3541 int r = X86EMUL_CONTINUE;
3544 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3546 unsigned offset = addr & (PAGE_SIZE-1);
3547 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3550 if (gpa == UNMAPPED_GVA)
3551 return X86EMUL_PROPAGATE_FAULT;
3552 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3554 r = X86EMUL_IO_NEEDED;
3566 /* used for instruction fetching */
3567 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3568 gva_t addr, void *val, unsigned int bytes,
3569 struct x86_exception *exception)
3571 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3572 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3574 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3575 access | PFERR_FETCH_MASK,
3579 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3580 gva_t addr, void *val, unsigned int bytes,
3581 struct x86_exception *exception)
3583 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3584 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3586 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3589 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3591 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3592 gva_t addr, void *val, unsigned int bytes,
3593 struct x86_exception *exception)
3595 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3596 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3599 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3600 gva_t addr, void *val,
3602 struct x86_exception *exception)
3604 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3606 int r = X86EMUL_CONTINUE;
3609 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3612 unsigned offset = addr & (PAGE_SIZE-1);
3613 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3616 if (gpa == UNMAPPED_GVA)
3617 return X86EMUL_PROPAGATE_FAULT;
3618 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3620 r = X86EMUL_IO_NEEDED;
3631 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
3633 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3634 gpa_t *gpa, struct x86_exception *exception,
3637 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3639 if (vcpu_match_mmio_gva(vcpu, gva) &&
3640 check_write_user_access(vcpu, write, access,
3641 vcpu->arch.access)) {
3642 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3643 (gva & (PAGE_SIZE - 1));
3644 trace_vcpu_match_mmio(gva, *gpa, write, false);
3649 access |= PFERR_WRITE_MASK;
3651 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3653 if (*gpa == UNMAPPED_GVA)
3656 /* For APIC access vmexit */
3657 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3660 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3661 trace_vcpu_match_mmio(gva, *gpa, write, true);
3668 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3669 const void *val, int bytes)
3673 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
3676 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
3680 struct read_write_emulator_ops {
3681 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3683 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3684 void *val, int bytes);
3685 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3686 int bytes, void *val);
3687 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3688 void *val, int bytes);
3692 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3694 if (vcpu->mmio_read_completed) {
3695 memcpy(val, vcpu->mmio_data, bytes);
3696 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3697 vcpu->mmio_phys_addr, *(u64 *)val);
3698 vcpu->mmio_read_completed = 0;
3705 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3706 void *val, int bytes)
3708 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3711 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3712 void *val, int bytes)
3714 return emulator_write_phys(vcpu, gpa, val, bytes);
3717 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3719 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3720 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3723 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3724 void *val, int bytes)
3726 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3727 return X86EMUL_IO_NEEDED;
3730 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3731 void *val, int bytes)
3733 memcpy(vcpu->mmio_data, val, bytes);
3734 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
3735 return X86EMUL_CONTINUE;
3738 static struct read_write_emulator_ops read_emultor = {
3739 .read_write_prepare = read_prepare,
3740 .read_write_emulate = read_emulate,
3741 .read_write_mmio = vcpu_mmio_read,
3742 .read_write_exit_mmio = read_exit_mmio,
3745 static struct read_write_emulator_ops write_emultor = {
3746 .read_write_emulate = write_emulate,
3747 .read_write_mmio = write_mmio,
3748 .read_write_exit_mmio = write_exit_mmio,
3752 static int emulator_read_write_onepage(unsigned long addr, void *val,
3754 struct x86_exception *exception,
3755 struct kvm_vcpu *vcpu,
3756 struct read_write_emulator_ops *ops)
3760 bool write = ops->write;
3762 if (ops->read_write_prepare &&
3763 ops->read_write_prepare(vcpu, val, bytes))
3764 return X86EMUL_CONTINUE;
3766 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
3769 return X86EMUL_PROPAGATE_FAULT;
3771 /* For APIC access vmexit */
3775 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
3776 return X86EMUL_CONTINUE;
3780 * Is this MMIO handled locally?
3782 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
3783 if (handled == bytes)
3784 return X86EMUL_CONTINUE;
3790 vcpu->mmio_needed = 1;
3791 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3792 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3793 vcpu->mmio_size = bytes;
3794 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
3795 vcpu->run->mmio.is_write = vcpu->mmio_is_write = write;
3796 vcpu->mmio_index = 0;
3798 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
3801 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3802 void *val, unsigned int bytes,
3803 struct x86_exception *exception,
3804 struct read_write_emulator_ops *ops)
3806 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3808 /* Crossing a page boundary? */
3809 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3812 now = -addr & ~PAGE_MASK;
3813 rc = emulator_read_write_onepage(addr, val, now, exception,
3816 if (rc != X86EMUL_CONTINUE)
3823 return emulator_read_write_onepage(addr, val, bytes, exception,
3827 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3831 struct x86_exception *exception)
3833 return emulator_read_write(ctxt, addr, val, bytes,
3834 exception, &read_emultor);
3837 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3841 struct x86_exception *exception)
3843 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3844 exception, &write_emultor);
3847 #define CMPXCHG_TYPE(t, ptr, old, new) \
3848 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3850 #ifdef CONFIG_X86_64
3851 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3853 # define CMPXCHG64(ptr, old, new) \
3854 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
3857 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3862 struct x86_exception *exception)
3864 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3870 /* guests cmpxchg8b have to be emulated atomically */
3871 if (bytes > 8 || (bytes & (bytes - 1)))
3874 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
3876 if (gpa == UNMAPPED_GVA ||
3877 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3880 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3883 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3884 if (is_error_page(page)) {
3885 kvm_release_page_clean(page);
3889 kaddr = kmap_atomic(page, KM_USER0);
3890 kaddr += offset_in_page(gpa);
3893 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3896 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3899 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3902 exchanged = CMPXCHG64(kaddr, old, new);
3907 kunmap_atomic(kaddr, KM_USER0);
3908 kvm_release_page_dirty(page);
3911 return X86EMUL_CMPXCHG_FAILED;
3913 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
3915 return X86EMUL_CONTINUE;
3918 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
3920 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
3923 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3925 /* TODO: String I/O for in kernel device */
3928 if (vcpu->arch.pio.in)
3929 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3930 vcpu->arch.pio.size, pd);
3932 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3933 vcpu->arch.pio.port, vcpu->arch.pio.size,
3938 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
3939 unsigned short port, void *val,
3940 unsigned int count, bool in)
3942 trace_kvm_pio(!in, port, size, count);
3944 vcpu->arch.pio.port = port;
3945 vcpu->arch.pio.in = in;
3946 vcpu->arch.pio.count = count;
3947 vcpu->arch.pio.size = size;
3949 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3950 vcpu->arch.pio.count = 0;
3954 vcpu->run->exit_reason = KVM_EXIT_IO;
3955 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
3956 vcpu->run->io.size = size;
3957 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3958 vcpu->run->io.count = count;
3959 vcpu->run->io.port = port;
3964 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
3965 int size, unsigned short port, void *val,
3968 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3971 if (vcpu->arch.pio.count)
3974 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
3977 memcpy(val, vcpu->arch.pio_data, size * count);
3978 vcpu->arch.pio.count = 0;
3985 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
3986 int size, unsigned short port,
3987 const void *val, unsigned int count)
3989 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3991 memcpy(vcpu->arch.pio_data, val, size * count);
3992 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
3995 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3997 return kvm_x86_ops->get_segment_base(vcpu, seg);
4000 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4002 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4005 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4007 if (!need_emulate_wbinvd(vcpu))
4008 return X86EMUL_CONTINUE;
4010 if (kvm_x86_ops->has_wbinvd_exit()) {
4011 int cpu = get_cpu();
4013 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4014 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4015 wbinvd_ipi, NULL, 1);
4017 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4020 return X86EMUL_CONTINUE;
4022 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4024 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4026 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4029 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4031 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4034 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4037 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4040 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4042 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4045 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4047 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4048 unsigned long value;
4052 value = kvm_read_cr0(vcpu);
4055 value = vcpu->arch.cr2;
4058 value = kvm_read_cr3(vcpu);
4061 value = kvm_read_cr4(vcpu);
4064 value = kvm_get_cr8(vcpu);
4067 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4074 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4076 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4081 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4084 vcpu->arch.cr2 = val;
4087 res = kvm_set_cr3(vcpu, val);
4090 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4093 res = kvm_set_cr8(vcpu, val);
4096 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4103 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4105 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4108 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4110 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4113 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4115 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4118 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4120 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4123 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4125 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4128 static unsigned long emulator_get_cached_segment_base(
4129 struct x86_emulate_ctxt *ctxt, int seg)
4131 return get_segment_base(emul_to_vcpu(ctxt), seg);
4134 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4135 struct desc_struct *desc, u32 *base3,
4138 struct kvm_segment var;
4140 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4141 *selector = var.selector;
4148 set_desc_limit(desc, var.limit);
4149 set_desc_base(desc, (unsigned long)var.base);
4150 #ifdef CONFIG_X86_64
4152 *base3 = var.base >> 32;
4154 desc->type = var.type;
4156 desc->dpl = var.dpl;
4157 desc->p = var.present;
4158 desc->avl = var.avl;
4166 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4167 struct desc_struct *desc, u32 base3,
4170 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4171 struct kvm_segment var;
4173 var.selector = selector;
4174 var.base = get_desc_base(desc);
4175 #ifdef CONFIG_X86_64
4176 var.base |= ((u64)base3) << 32;
4178 var.limit = get_desc_limit(desc);
4180 var.limit = (var.limit << 12) | 0xfff;
4181 var.type = desc->type;
4182 var.present = desc->p;
4183 var.dpl = desc->dpl;
4188 var.avl = desc->avl;
4189 var.present = desc->p;
4190 var.unusable = !var.present;
4193 kvm_set_segment(vcpu, &var, seg);
4197 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4198 u32 msr_index, u64 *pdata)
4200 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4203 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4204 u32 msr_index, u64 data)
4206 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4209 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4210 u32 pmc, u64 *pdata)
4212 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4215 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4217 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4220 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4223 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4225 * CR0.TS may reference the host fpu state, not the guest fpu state,
4226 * so it may be clear at this point.
4231 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4236 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4237 struct x86_instruction_info *info,
4238 enum x86_intercept_stage stage)
4240 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4243 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4244 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4246 struct kvm_cpuid_entry2 *cpuid = NULL;
4249 cpuid = kvm_find_cpuid_entry(emul_to_vcpu(ctxt),
4265 static struct x86_emulate_ops emulate_ops = {
4266 .read_std = kvm_read_guest_virt_system,
4267 .write_std = kvm_write_guest_virt_system,
4268 .fetch = kvm_fetch_guest_virt,
4269 .read_emulated = emulator_read_emulated,
4270 .write_emulated = emulator_write_emulated,
4271 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4272 .invlpg = emulator_invlpg,
4273 .pio_in_emulated = emulator_pio_in_emulated,
4274 .pio_out_emulated = emulator_pio_out_emulated,
4275 .get_segment = emulator_get_segment,
4276 .set_segment = emulator_set_segment,
4277 .get_cached_segment_base = emulator_get_cached_segment_base,
4278 .get_gdt = emulator_get_gdt,
4279 .get_idt = emulator_get_idt,
4280 .set_gdt = emulator_set_gdt,
4281 .set_idt = emulator_set_idt,
4282 .get_cr = emulator_get_cr,
4283 .set_cr = emulator_set_cr,
4284 .cpl = emulator_get_cpl,
4285 .get_dr = emulator_get_dr,
4286 .set_dr = emulator_set_dr,
4287 .set_msr = emulator_set_msr,
4288 .get_msr = emulator_get_msr,
4289 .read_pmc = emulator_read_pmc,
4290 .halt = emulator_halt,
4291 .wbinvd = emulator_wbinvd,
4292 .fix_hypercall = emulator_fix_hypercall,
4293 .get_fpu = emulator_get_fpu,
4294 .put_fpu = emulator_put_fpu,
4295 .intercept = emulator_intercept,
4296 .get_cpuid = emulator_get_cpuid,
4299 static void cache_all_regs(struct kvm_vcpu *vcpu)
4301 kvm_register_read(vcpu, VCPU_REGS_RAX);
4302 kvm_register_read(vcpu, VCPU_REGS_RSP);
4303 kvm_register_read(vcpu, VCPU_REGS_RIP);
4304 vcpu->arch.regs_dirty = ~0;
4307 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4309 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4311 * an sti; sti; sequence only disable interrupts for the first
4312 * instruction. So, if the last instruction, be it emulated or
4313 * not, left the system with the INT_STI flag enabled, it
4314 * means that the last instruction is an sti. We should not
4315 * leave the flag on in this case. The same goes for mov ss
4317 if (!(int_shadow & mask))
4318 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4321 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4323 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4324 if (ctxt->exception.vector == PF_VECTOR)
4325 kvm_propagate_fault(vcpu, &ctxt->exception);
4326 else if (ctxt->exception.error_code_valid)
4327 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4328 ctxt->exception.error_code);
4330 kvm_queue_exception(vcpu, ctxt->exception.vector);
4333 static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
4334 const unsigned long *regs)
4336 memset(&ctxt->twobyte, 0,
4337 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4338 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
4340 ctxt->fetch.start = 0;
4341 ctxt->fetch.end = 0;
4342 ctxt->io_read.pos = 0;
4343 ctxt->io_read.end = 0;
4344 ctxt->mem_read.pos = 0;
4345 ctxt->mem_read.end = 0;
4348 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4350 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4354 * TODO: fix emulate.c to use guest_read/write_register
4355 * instead of direct ->regs accesses, can save hundred cycles
4356 * on Intel for instructions that don't read/change RSP, for
4359 cache_all_regs(vcpu);
4361 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4363 ctxt->eflags = kvm_get_rflags(vcpu);
4364 ctxt->eip = kvm_rip_read(vcpu);
4365 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4366 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4367 cs_l ? X86EMUL_MODE_PROT64 :
4368 cs_db ? X86EMUL_MODE_PROT32 :
4369 X86EMUL_MODE_PROT16;
4370 ctxt->guest_mode = is_guest_mode(vcpu);
4372 init_decode_cache(ctxt, vcpu->arch.regs);
4373 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4376 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4378 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4381 init_emulate_ctxt(vcpu);
4385 ctxt->_eip = ctxt->eip + inc_eip;
4386 ret = emulate_int_real(ctxt, irq);
4388 if (ret != X86EMUL_CONTINUE)
4389 return EMULATE_FAIL;
4391 ctxt->eip = ctxt->_eip;
4392 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4393 kvm_rip_write(vcpu, ctxt->eip);
4394 kvm_set_rflags(vcpu, ctxt->eflags);
4396 if (irq == NMI_VECTOR)
4397 vcpu->arch.nmi_pending = 0;
4399 vcpu->arch.interrupt.pending = false;
4401 return EMULATE_DONE;
4403 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4405 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4407 int r = EMULATE_DONE;
4409 ++vcpu->stat.insn_emulation_fail;
4410 trace_kvm_emulate_insn_failed(vcpu);
4411 if (!is_guest_mode(vcpu)) {
4412 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4413 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4414 vcpu->run->internal.ndata = 0;
4417 kvm_queue_exception(vcpu, UD_VECTOR);
4422 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4430 * if emulation was due to access to shadowed page table
4431 * and it failed try to unshadow page and re-entetr the
4432 * guest to let CPU execute the instruction.
4434 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4437 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4439 if (gpa == UNMAPPED_GVA)
4440 return true; /* let cpu generate fault */
4442 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4448 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4449 unsigned long cr2, int emulation_type)
4451 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4452 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4454 last_retry_eip = vcpu->arch.last_retry_eip;
4455 last_retry_addr = vcpu->arch.last_retry_addr;
4458 * If the emulation is caused by #PF and it is non-page_table
4459 * writing instruction, it means the VM-EXIT is caused by shadow
4460 * page protected, we can zap the shadow page and retry this
4461 * instruction directly.
4463 * Note: if the guest uses a non-page-table modifying instruction
4464 * on the PDE that points to the instruction, then we will unmap
4465 * the instruction and go to an infinite loop. So, we cache the
4466 * last retried eip and the last fault address, if we meet the eip
4467 * and the address again, we can break out of the potential infinite
4470 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4472 if (!(emulation_type & EMULTYPE_RETRY))
4475 if (x86_page_table_writing_insn(ctxt))
4478 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4481 vcpu->arch.last_retry_eip = ctxt->eip;
4482 vcpu->arch.last_retry_addr = cr2;
4484 if (!vcpu->arch.mmu.direct_map)
4485 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4487 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4492 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4499 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4500 bool writeback = true;
4502 kvm_clear_exception_queue(vcpu);
4504 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4505 init_emulate_ctxt(vcpu);
4506 ctxt->interruptibility = 0;
4507 ctxt->have_exception = false;
4508 ctxt->perm_ok = false;
4510 ctxt->only_vendor_specific_insn
4511 = emulation_type & EMULTYPE_TRAP_UD;
4513 r = x86_decode_insn(ctxt, insn, insn_len);
4515 trace_kvm_emulate_insn_start(vcpu);
4516 ++vcpu->stat.insn_emulation;
4517 if (r != EMULATION_OK) {
4518 if (emulation_type & EMULTYPE_TRAP_UD)
4519 return EMULATE_FAIL;
4520 if (reexecute_instruction(vcpu, cr2))
4521 return EMULATE_DONE;
4522 if (emulation_type & EMULTYPE_SKIP)
4523 return EMULATE_FAIL;
4524 return handle_emulation_failure(vcpu);
4528 if (emulation_type & EMULTYPE_SKIP) {
4529 kvm_rip_write(vcpu, ctxt->_eip);
4530 return EMULATE_DONE;
4533 if (retry_instruction(ctxt, cr2, emulation_type))
4534 return EMULATE_DONE;
4536 /* this is needed for vmware backdoor interface to work since it
4537 changes registers values during IO operation */
4538 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4539 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4540 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
4544 r = x86_emulate_insn(ctxt);
4546 if (r == EMULATION_INTERCEPTED)
4547 return EMULATE_DONE;
4549 if (r == EMULATION_FAILED) {
4550 if (reexecute_instruction(vcpu, cr2))
4551 return EMULATE_DONE;
4553 return handle_emulation_failure(vcpu);
4556 if (ctxt->have_exception) {
4557 inject_emulated_exception(vcpu);
4559 } else if (vcpu->arch.pio.count) {
4560 if (!vcpu->arch.pio.in)
4561 vcpu->arch.pio.count = 0;
4564 r = EMULATE_DO_MMIO;
4565 } else if (vcpu->mmio_needed) {
4566 if (!vcpu->mmio_is_write)
4568 r = EMULATE_DO_MMIO;
4569 } else if (r == EMULATION_RESTART)
4575 toggle_interruptibility(vcpu, ctxt->interruptibility);
4576 kvm_set_rflags(vcpu, ctxt->eflags);
4577 kvm_make_request(KVM_REQ_EVENT, vcpu);
4578 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4579 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4580 kvm_rip_write(vcpu, ctxt->eip);
4582 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
4586 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
4588 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4590 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4591 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4592 size, port, &val, 1);
4593 /* do not return to emulator after return from userspace */
4594 vcpu->arch.pio.count = 0;
4597 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4599 static void tsc_bad(void *info)
4601 __this_cpu_write(cpu_tsc_khz, 0);
4604 static void tsc_khz_changed(void *data)
4606 struct cpufreq_freqs *freq = data;
4607 unsigned long khz = 0;
4611 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4612 khz = cpufreq_quick_get(raw_smp_processor_id());
4615 __this_cpu_write(cpu_tsc_khz, khz);
4618 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4621 struct cpufreq_freqs *freq = data;
4623 struct kvm_vcpu *vcpu;
4624 int i, send_ipi = 0;
4627 * We allow guests to temporarily run on slowing clocks,
4628 * provided we notify them after, or to run on accelerating
4629 * clocks, provided we notify them before. Thus time never
4632 * However, we have a problem. We can't atomically update
4633 * the frequency of a given CPU from this function; it is
4634 * merely a notifier, which can be called from any CPU.
4635 * Changing the TSC frequency at arbitrary points in time
4636 * requires a recomputation of local variables related to
4637 * the TSC for each VCPU. We must flag these local variables
4638 * to be updated and be sure the update takes place with the
4639 * new frequency before any guests proceed.
4641 * Unfortunately, the combination of hotplug CPU and frequency
4642 * change creates an intractable locking scenario; the order
4643 * of when these callouts happen is undefined with respect to
4644 * CPU hotplug, and they can race with each other. As such,
4645 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4646 * undefined; you can actually have a CPU frequency change take
4647 * place in between the computation of X and the setting of the
4648 * variable. To protect against this problem, all updates of
4649 * the per_cpu tsc_khz variable are done in an interrupt
4650 * protected IPI, and all callers wishing to update the value
4651 * must wait for a synchronous IPI to complete (which is trivial
4652 * if the caller is on the CPU already). This establishes the
4653 * necessary total order on variable updates.
4655 * Note that because a guest time update may take place
4656 * anytime after the setting of the VCPU's request bit, the
4657 * correct TSC value must be set before the request. However,
4658 * to ensure the update actually makes it to any guest which
4659 * starts running in hardware virtualization between the set
4660 * and the acquisition of the spinlock, we must also ping the
4661 * CPU after setting the request bit.
4665 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4667 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4670 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4672 raw_spin_lock(&kvm_lock);
4673 list_for_each_entry(kvm, &vm_list, vm_list) {
4674 kvm_for_each_vcpu(i, vcpu, kvm) {
4675 if (vcpu->cpu != freq->cpu)
4677 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4678 if (vcpu->cpu != smp_processor_id())
4682 raw_spin_unlock(&kvm_lock);
4684 if (freq->old < freq->new && send_ipi) {
4686 * We upscale the frequency. Must make the guest
4687 * doesn't see old kvmclock values while running with
4688 * the new frequency, otherwise we risk the guest sees
4689 * time go backwards.
4691 * In case we update the frequency for another cpu
4692 * (which might be in guest context) send an interrupt
4693 * to kick the cpu out of guest context. Next time
4694 * guest context is entered kvmclock will be updated,
4695 * so the guest will not see stale values.
4697 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4702 static struct notifier_block kvmclock_cpufreq_notifier_block = {
4703 .notifier_call = kvmclock_cpufreq_notifier
4706 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4707 unsigned long action, void *hcpu)
4709 unsigned int cpu = (unsigned long)hcpu;
4713 case CPU_DOWN_FAILED:
4714 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4716 case CPU_DOWN_PREPARE:
4717 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4723 static struct notifier_block kvmclock_cpu_notifier_block = {
4724 .notifier_call = kvmclock_cpu_notifier,
4725 .priority = -INT_MAX
4728 static void kvm_timer_init(void)
4732 max_tsc_khz = tsc_khz;
4733 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4734 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
4735 #ifdef CONFIG_CPU_FREQ
4736 struct cpufreq_policy policy;
4737 memset(&policy, 0, sizeof(policy));
4739 cpufreq_get_policy(&policy, cpu);
4740 if (policy.cpuinfo.max_freq)
4741 max_tsc_khz = policy.cpuinfo.max_freq;
4744 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4745 CPUFREQ_TRANSITION_NOTIFIER);
4747 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
4748 for_each_online_cpu(cpu)
4749 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4752 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4754 int kvm_is_in_guest(void)
4756 return __this_cpu_read(current_vcpu) != NULL;
4759 static int kvm_is_user_mode(void)
4763 if (__this_cpu_read(current_vcpu))
4764 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
4766 return user_mode != 0;
4769 static unsigned long kvm_get_guest_ip(void)
4771 unsigned long ip = 0;
4773 if (__this_cpu_read(current_vcpu))
4774 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
4779 static struct perf_guest_info_callbacks kvm_guest_cbs = {
4780 .is_in_guest = kvm_is_in_guest,
4781 .is_user_mode = kvm_is_user_mode,
4782 .get_guest_ip = kvm_get_guest_ip,
4785 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4787 __this_cpu_write(current_vcpu, vcpu);
4789 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4791 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4793 __this_cpu_write(current_vcpu, NULL);
4795 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4797 static void kvm_set_mmio_spte_mask(void)
4800 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4803 * Set the reserved bits and the present bit of an paging-structure
4804 * entry to generate page fault with PFER.RSV = 1.
4806 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4809 #ifdef CONFIG_X86_64
4811 * If reserved bit is not supported, clear the present bit to disable
4814 if (maxphyaddr == 52)
4818 kvm_mmu_set_mmio_spte_mask(mask);
4821 int kvm_arch_init(void *opaque)
4824 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4827 printk(KERN_ERR "kvm: already loaded the other module\n");
4832 if (!ops->cpu_has_kvm_support()) {
4833 printk(KERN_ERR "kvm: no hardware support\n");
4837 if (ops->disabled_by_bios()) {
4838 printk(KERN_ERR "kvm: disabled by bios\n");
4843 r = kvm_mmu_module_init();
4847 kvm_set_mmio_spte_mask();
4848 kvm_init_msr_list();
4851 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4852 PT_DIRTY_MASK, PT64_NX_MASK, 0);
4856 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4859 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4867 void kvm_arch_exit(void)
4869 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4871 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4872 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4873 CPUFREQ_TRANSITION_NOTIFIER);
4874 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4876 kvm_mmu_module_exit();
4879 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4881 ++vcpu->stat.halt_exits;
4882 if (irqchip_in_kernel(vcpu->kvm)) {
4883 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
4886 vcpu->run->exit_reason = KVM_EXIT_HLT;
4890 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4892 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4894 u64 param, ingpa, outgpa, ret;
4895 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4896 bool fast, longmode;
4900 * hypercall generates UD from non zero cpl and real mode
4903 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
4904 kvm_queue_exception(vcpu, UD_VECTOR);
4908 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4909 longmode = is_long_mode(vcpu) && cs_l == 1;
4912 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4913 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4914 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4915 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4916 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4917 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
4919 #ifdef CONFIG_X86_64
4921 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4922 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4923 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4927 code = param & 0xffff;
4928 fast = (param >> 16) & 0x1;
4929 rep_cnt = (param >> 32) & 0xfff;
4930 rep_idx = (param >> 48) & 0xfff;
4932 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4935 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4936 kvm_vcpu_on_spin(vcpu);
4939 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4943 ret = res | (((u64)rep_done & 0xfff) << 32);
4945 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4947 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4948 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4954 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4956 unsigned long nr, a0, a1, a2, a3, ret;
4959 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4960 return kvm_hv_hypercall(vcpu);
4962 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4963 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4964 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4965 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4966 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
4968 trace_kvm_hypercall(nr, a0, a1, a2, a3);
4970 if (!is_long_mode(vcpu)) {
4978 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4984 case KVM_HC_VAPIC_POLL_IRQ:
4992 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4993 ++vcpu->stat.hypercalls;
4996 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4998 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5000 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5001 char instruction[3];
5002 unsigned long rip = kvm_rip_read(vcpu);
5005 * Blow out the MMU to ensure that no other VCPU has an active mapping
5006 * to ensure that the updated hypercall appears atomically across all
5009 kvm_mmu_zap_all(vcpu->kvm);
5011 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5013 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5017 * Check if userspace requested an interrupt window, and that the
5018 * interrupt window is open.
5020 * No need to exit to userspace if we already have an interrupt queued.
5022 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5024 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5025 vcpu->run->request_interrupt_window &&
5026 kvm_arch_interrupt_allowed(vcpu));
5029 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5031 struct kvm_run *kvm_run = vcpu->run;
5033 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5034 kvm_run->cr8 = kvm_get_cr8(vcpu);
5035 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5036 if (irqchip_in_kernel(vcpu->kvm))
5037 kvm_run->ready_for_interrupt_injection = 1;
5039 kvm_run->ready_for_interrupt_injection =
5040 kvm_arch_interrupt_allowed(vcpu) &&
5041 !kvm_cpu_has_interrupt(vcpu) &&
5042 !kvm_event_needs_reinjection(vcpu);
5045 static void vapic_enter(struct kvm_vcpu *vcpu)
5047 struct kvm_lapic *apic = vcpu->arch.apic;
5050 if (!apic || !apic->vapic_addr)
5053 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5055 vcpu->arch.apic->vapic_page = page;
5058 static void vapic_exit(struct kvm_vcpu *vcpu)
5060 struct kvm_lapic *apic = vcpu->arch.apic;
5063 if (!apic || !apic->vapic_addr)
5066 idx = srcu_read_lock(&vcpu->kvm->srcu);
5067 kvm_release_page_dirty(apic->vapic_page);
5068 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5069 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5072 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5076 if (!kvm_x86_ops->update_cr8_intercept)
5079 if (!vcpu->arch.apic)
5082 if (!vcpu->arch.apic->vapic_addr)
5083 max_irr = kvm_lapic_find_highest_irr(vcpu);
5090 tpr = kvm_lapic_get_cr8(vcpu);
5092 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5095 static void inject_pending_event(struct kvm_vcpu *vcpu)
5097 /* try to reinject previous events if any */
5098 if (vcpu->arch.exception.pending) {
5099 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5100 vcpu->arch.exception.has_error_code,
5101 vcpu->arch.exception.error_code);
5102 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5103 vcpu->arch.exception.has_error_code,
5104 vcpu->arch.exception.error_code,
5105 vcpu->arch.exception.reinject);
5109 if (vcpu->arch.nmi_injected) {
5110 kvm_x86_ops->set_nmi(vcpu);
5114 if (vcpu->arch.interrupt.pending) {
5115 kvm_x86_ops->set_irq(vcpu);
5119 /* try to inject new event if pending */
5120 if (vcpu->arch.nmi_pending) {
5121 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5122 --vcpu->arch.nmi_pending;
5123 vcpu->arch.nmi_injected = true;
5124 kvm_x86_ops->set_nmi(vcpu);
5126 } else if (kvm_cpu_has_interrupt(vcpu)) {
5127 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5128 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5130 kvm_x86_ops->set_irq(vcpu);
5135 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5137 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5138 !vcpu->guest_xcr0_loaded) {
5139 /* kvm_set_xcr() also depends on this */
5140 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5141 vcpu->guest_xcr0_loaded = 1;
5145 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5147 if (vcpu->guest_xcr0_loaded) {
5148 if (vcpu->arch.xcr0 != host_xcr0)
5149 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5150 vcpu->guest_xcr0_loaded = 0;
5154 static void process_nmi(struct kvm_vcpu *vcpu)
5159 * x86 is limited to one NMI running, and one NMI pending after it.
5160 * If an NMI is already in progress, limit further NMIs to just one.
5161 * Otherwise, allow two (and we'll inject the first one immediately).
5163 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5166 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5167 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5168 kvm_make_request(KVM_REQ_EVENT, vcpu);
5171 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5174 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5175 vcpu->run->request_interrupt_window;
5176 bool req_immediate_exit = 0;
5178 if (vcpu->requests) {
5179 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5180 kvm_mmu_unload(vcpu);
5181 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5182 __kvm_migrate_timers(vcpu);
5183 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5184 r = kvm_guest_time_update(vcpu);
5188 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5189 kvm_mmu_sync_roots(vcpu);
5190 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5191 kvm_x86_ops->tlb_flush(vcpu);
5192 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5193 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5197 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5198 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5202 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5203 vcpu->fpu_active = 0;
5204 kvm_x86_ops->fpu_deactivate(vcpu);
5206 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5207 /* Page is swapped out. Do synthetic halt */
5208 vcpu->arch.apf.halted = true;
5212 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5213 record_steal_time(vcpu);
5214 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5216 req_immediate_exit =
5217 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
5218 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5219 kvm_handle_pmu_event(vcpu);
5220 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5221 kvm_deliver_pmi(vcpu);
5224 r = kvm_mmu_reload(vcpu);
5228 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5229 inject_pending_event(vcpu);
5231 /* enable NMI/IRQ window open exits if needed */
5232 if (vcpu->arch.nmi_pending)
5233 kvm_x86_ops->enable_nmi_window(vcpu);
5234 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5235 kvm_x86_ops->enable_irq_window(vcpu);
5237 if (kvm_lapic_enabled(vcpu)) {
5238 update_cr8_intercept(vcpu);
5239 kvm_lapic_sync_to_vapic(vcpu);
5245 kvm_x86_ops->prepare_guest_switch(vcpu);
5246 if (vcpu->fpu_active)
5247 kvm_load_guest_fpu(vcpu);
5248 kvm_load_guest_xcr0(vcpu);
5250 vcpu->mode = IN_GUEST_MODE;
5252 /* We should set ->mode before check ->requests,
5253 * see the comment in make_all_cpus_request.
5257 local_irq_disable();
5259 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5260 || need_resched() || signal_pending(current)) {
5261 vcpu->mode = OUTSIDE_GUEST_MODE;
5265 kvm_x86_ops->cancel_injection(vcpu);
5270 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5272 if (req_immediate_exit)
5273 smp_send_reschedule(vcpu->cpu);
5277 if (unlikely(vcpu->arch.switch_db_regs)) {
5279 set_debugreg(vcpu->arch.eff_db[0], 0);
5280 set_debugreg(vcpu->arch.eff_db[1], 1);
5281 set_debugreg(vcpu->arch.eff_db[2], 2);
5282 set_debugreg(vcpu->arch.eff_db[3], 3);
5285 trace_kvm_entry(vcpu->vcpu_id);
5286 kvm_x86_ops->run(vcpu);
5289 * If the guest has used debug registers, at least dr7
5290 * will be disabled while returning to the host.
5291 * If we don't have active breakpoints in the host, we don't
5292 * care about the messed up debug address registers. But if
5293 * we have some of them active, restore the old state.
5295 if (hw_breakpoint_active())
5296 hw_breakpoint_restore();
5298 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
5300 vcpu->mode = OUTSIDE_GUEST_MODE;
5307 * We must have an instruction between local_irq_enable() and
5308 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5309 * the interrupt shadow. The stat.exits increment will do nicely.
5310 * But we need to prevent reordering, hence this barrier():
5318 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5321 * Profile KVM exit RIPs:
5323 if (unlikely(prof_on == KVM_PROFILING)) {
5324 unsigned long rip = kvm_rip_read(vcpu);
5325 profile_hit(KVM_PROFILING, (void *)rip);
5328 if (unlikely(vcpu->arch.tsc_always_catchup))
5329 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5331 kvm_lapic_sync_from_vapic(vcpu);
5333 r = kvm_x86_ops->handle_exit(vcpu);
5339 static int __vcpu_run(struct kvm_vcpu *vcpu)
5342 struct kvm *kvm = vcpu->kvm;
5344 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5345 pr_debug("vcpu %d received sipi with vector # %x\n",
5346 vcpu->vcpu_id, vcpu->arch.sipi_vector);
5347 kvm_lapic_reset(vcpu);
5348 r = kvm_arch_vcpu_reset(vcpu);
5351 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5354 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5359 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5360 !vcpu->arch.apf.halted)
5361 r = vcpu_enter_guest(vcpu);
5363 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5364 kvm_vcpu_block(vcpu);
5365 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5366 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5368 switch(vcpu->arch.mp_state) {
5369 case KVM_MP_STATE_HALTED:
5370 vcpu->arch.mp_state =
5371 KVM_MP_STATE_RUNNABLE;
5372 case KVM_MP_STATE_RUNNABLE:
5373 vcpu->arch.apf.halted = false;
5375 case KVM_MP_STATE_SIPI_RECEIVED:
5386 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5387 if (kvm_cpu_has_pending_timer(vcpu))
5388 kvm_inject_pending_timer_irqs(vcpu);
5390 if (dm_request_for_irq_injection(vcpu)) {
5392 vcpu->run->exit_reason = KVM_EXIT_INTR;
5393 ++vcpu->stat.request_irq_exits;
5396 kvm_check_async_pf_completion(vcpu);
5398 if (signal_pending(current)) {
5400 vcpu->run->exit_reason = KVM_EXIT_INTR;
5401 ++vcpu->stat.signal_exits;
5403 if (need_resched()) {
5404 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5406 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5410 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5417 static int complete_mmio(struct kvm_vcpu *vcpu)
5419 struct kvm_run *run = vcpu->run;
5422 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5425 if (vcpu->mmio_needed) {
5426 vcpu->mmio_needed = 0;
5427 if (!vcpu->mmio_is_write)
5428 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5430 vcpu->mmio_index += 8;
5431 if (vcpu->mmio_index < vcpu->mmio_size) {
5432 run->exit_reason = KVM_EXIT_MMIO;
5433 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5434 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5435 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5436 run->mmio.is_write = vcpu->mmio_is_write;
5437 vcpu->mmio_needed = 1;
5440 if (vcpu->mmio_is_write)
5442 vcpu->mmio_read_completed = 1;
5444 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5445 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5446 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5447 if (r != EMULATE_DONE)
5452 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5457 if (!tsk_used_math(current) && init_fpu(current))
5460 if (vcpu->sigset_active)
5461 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5463 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5464 kvm_vcpu_block(vcpu);
5465 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5470 /* re-sync apic's tpr */
5471 if (!irqchip_in_kernel(vcpu->kvm)) {
5472 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5478 r = complete_mmio(vcpu);
5482 r = __vcpu_run(vcpu);
5485 post_kvm_run_save(vcpu);
5486 if (vcpu->sigset_active)
5487 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5492 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5494 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5496 * We are here if userspace calls get_regs() in the middle of
5497 * instruction emulation. Registers state needs to be copied
5498 * back from emulation context to vcpu. Usrapace shouldn't do
5499 * that usually, but some bad designed PV devices (vmware
5500 * backdoor interface) need this to work
5502 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5503 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5504 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5506 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5507 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5508 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5509 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5510 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5511 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5512 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5513 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5514 #ifdef CONFIG_X86_64
5515 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5516 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5517 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5518 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5519 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5520 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5521 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5522 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
5525 regs->rip = kvm_rip_read(vcpu);
5526 regs->rflags = kvm_get_rflags(vcpu);
5531 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5533 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5534 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5536 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5537 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5538 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5539 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5540 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5541 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5542 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5543 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
5544 #ifdef CONFIG_X86_64
5545 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5546 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5547 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5548 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5549 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5550 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5551 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5552 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
5555 kvm_rip_write(vcpu, regs->rip);
5556 kvm_set_rflags(vcpu, regs->rflags);
5558 vcpu->arch.exception.pending = false;
5560 kvm_make_request(KVM_REQ_EVENT, vcpu);
5565 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5567 struct kvm_segment cs;
5569 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
5573 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5575 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5576 struct kvm_sregs *sregs)
5580 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5581 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5582 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5583 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5584 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5585 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5587 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5588 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5590 kvm_x86_ops->get_idt(vcpu, &dt);
5591 sregs->idt.limit = dt.size;
5592 sregs->idt.base = dt.address;
5593 kvm_x86_ops->get_gdt(vcpu, &dt);
5594 sregs->gdt.limit = dt.size;
5595 sregs->gdt.base = dt.address;
5597 sregs->cr0 = kvm_read_cr0(vcpu);
5598 sregs->cr2 = vcpu->arch.cr2;
5599 sregs->cr3 = kvm_read_cr3(vcpu);
5600 sregs->cr4 = kvm_read_cr4(vcpu);
5601 sregs->cr8 = kvm_get_cr8(vcpu);
5602 sregs->efer = vcpu->arch.efer;
5603 sregs->apic_base = kvm_get_apic_base(vcpu);
5605 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
5607 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
5608 set_bit(vcpu->arch.interrupt.nr,
5609 (unsigned long *)sregs->interrupt_bitmap);
5614 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5615 struct kvm_mp_state *mp_state)
5617 mp_state->mp_state = vcpu->arch.mp_state;
5621 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5622 struct kvm_mp_state *mp_state)
5624 vcpu->arch.mp_state = mp_state->mp_state;
5625 kvm_make_request(KVM_REQ_EVENT, vcpu);
5629 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5630 bool has_error_code, u32 error_code)
5632 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5635 init_emulate_ctxt(vcpu);
5637 ret = emulator_task_switch(ctxt, tss_selector, reason,
5638 has_error_code, error_code);
5641 return EMULATE_FAIL;
5643 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5644 kvm_rip_write(vcpu, ctxt->eip);
5645 kvm_set_rflags(vcpu, ctxt->eflags);
5646 kvm_make_request(KVM_REQ_EVENT, vcpu);
5647 return EMULATE_DONE;
5649 EXPORT_SYMBOL_GPL(kvm_task_switch);
5651 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5652 struct kvm_sregs *sregs)
5654 int mmu_reset_needed = 0;
5655 int pending_vec, max_bits, idx;
5658 dt.size = sregs->idt.limit;
5659 dt.address = sregs->idt.base;
5660 kvm_x86_ops->set_idt(vcpu, &dt);
5661 dt.size = sregs->gdt.limit;
5662 dt.address = sregs->gdt.base;
5663 kvm_x86_ops->set_gdt(vcpu, &dt);
5665 vcpu->arch.cr2 = sregs->cr2;
5666 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
5667 vcpu->arch.cr3 = sregs->cr3;
5668 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
5670 kvm_set_cr8(vcpu, sregs->cr8);
5672 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
5673 kvm_x86_ops->set_efer(vcpu, sregs->efer);
5674 kvm_set_apic_base(vcpu, sregs->apic_base);
5676 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
5677 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
5678 vcpu->arch.cr0 = sregs->cr0;
5680 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
5681 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
5682 if (sregs->cr4 & X86_CR4_OSXSAVE)
5683 kvm_update_cpuid(vcpu);
5685 idx = srcu_read_lock(&vcpu->kvm->srcu);
5686 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
5687 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
5688 mmu_reset_needed = 1;
5690 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5692 if (mmu_reset_needed)
5693 kvm_mmu_reset_context(vcpu);
5695 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5696 pending_vec = find_first_bit(
5697 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5698 if (pending_vec < max_bits) {
5699 kvm_queue_interrupt(vcpu, pending_vec, false);
5700 pr_debug("Set back pending irq %d\n", pending_vec);
5703 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5704 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5705 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5706 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5707 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5708 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5710 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5711 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5713 update_cr8_intercept(vcpu);
5715 /* Older userspace won't unhalt the vcpu on reset. */
5716 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
5717 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
5719 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5721 kvm_make_request(KVM_REQ_EVENT, vcpu);
5726 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5727 struct kvm_guest_debug *dbg)
5729 unsigned long rflags;
5732 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5734 if (vcpu->arch.exception.pending)
5736 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5737 kvm_queue_exception(vcpu, DB_VECTOR);
5739 kvm_queue_exception(vcpu, BP_VECTOR);
5743 * Read rflags as long as potentially injected trace flags are still
5746 rflags = kvm_get_rflags(vcpu);
5748 vcpu->guest_debug = dbg->control;
5749 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5750 vcpu->guest_debug = 0;
5752 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5753 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5754 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5755 vcpu->arch.switch_db_regs =
5756 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5758 for (i = 0; i < KVM_NR_DB_REGS; i++)
5759 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5760 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5763 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5764 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5765 get_segment_base(vcpu, VCPU_SREG_CS);
5768 * Trigger an rflags update that will inject or remove the trace
5771 kvm_set_rflags(vcpu, rflags);
5773 kvm_x86_ops->set_guest_debug(vcpu, dbg);
5783 * Translate a guest virtual address to a guest physical address.
5785 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5786 struct kvm_translation *tr)
5788 unsigned long vaddr = tr->linear_address;
5792 idx = srcu_read_lock(&vcpu->kvm->srcu);
5793 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
5794 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5795 tr->physical_address = gpa;
5796 tr->valid = gpa != UNMAPPED_GVA;
5803 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5805 struct i387_fxsave_struct *fxsave =
5806 &vcpu->arch.guest_fpu.state->fxsave;
5808 memcpy(fpu->fpr, fxsave->st_space, 128);
5809 fpu->fcw = fxsave->cwd;
5810 fpu->fsw = fxsave->swd;
5811 fpu->ftwx = fxsave->twd;
5812 fpu->last_opcode = fxsave->fop;
5813 fpu->last_ip = fxsave->rip;
5814 fpu->last_dp = fxsave->rdp;
5815 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5820 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5822 struct i387_fxsave_struct *fxsave =
5823 &vcpu->arch.guest_fpu.state->fxsave;
5825 memcpy(fxsave->st_space, fpu->fpr, 128);
5826 fxsave->cwd = fpu->fcw;
5827 fxsave->swd = fpu->fsw;
5828 fxsave->twd = fpu->ftwx;
5829 fxsave->fop = fpu->last_opcode;
5830 fxsave->rip = fpu->last_ip;
5831 fxsave->rdp = fpu->last_dp;
5832 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5837 int fx_init(struct kvm_vcpu *vcpu)
5841 err = fpu_alloc(&vcpu->arch.guest_fpu);
5845 fpu_finit(&vcpu->arch.guest_fpu);
5848 * Ensure guest xcr0 is valid for loading
5850 vcpu->arch.xcr0 = XSTATE_FP;
5852 vcpu->arch.cr0 |= X86_CR0_ET;
5856 EXPORT_SYMBOL_GPL(fx_init);
5858 static void fx_free(struct kvm_vcpu *vcpu)
5860 fpu_free(&vcpu->arch.guest_fpu);
5863 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5865 if (vcpu->guest_fpu_loaded)
5869 * Restore all possible states in the guest,
5870 * and assume host would use all available bits.
5871 * Guest xcr0 would be loaded later.
5873 kvm_put_guest_xcr0(vcpu);
5874 vcpu->guest_fpu_loaded = 1;
5875 unlazy_fpu(current);
5876 fpu_restore_checking(&vcpu->arch.guest_fpu);
5880 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5882 kvm_put_guest_xcr0(vcpu);
5884 if (!vcpu->guest_fpu_loaded)
5887 vcpu->guest_fpu_loaded = 0;
5888 fpu_save_init(&vcpu->arch.guest_fpu);
5889 ++vcpu->stat.fpu_reload;
5890 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
5894 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5896 kvmclock_reset(vcpu);
5898 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
5900 kvm_x86_ops->vcpu_free(vcpu);
5903 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5906 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5907 printk_once(KERN_WARNING
5908 "kvm: SMP vm created on host with unstable TSC; "
5909 "guest TSC will not be reliable\n");
5910 return kvm_x86_ops->vcpu_create(kvm, id);
5913 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5917 vcpu->arch.mtrr_state.have_fixed = 1;
5919 r = kvm_arch_vcpu_reset(vcpu);
5921 r = kvm_mmu_setup(vcpu);
5927 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
5929 vcpu->arch.apf.msr_val = 0;
5932 kvm_mmu_unload(vcpu);
5936 kvm_x86_ops->vcpu_free(vcpu);
5939 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5941 atomic_set(&vcpu->arch.nmi_queued, 0);
5942 vcpu->arch.nmi_pending = 0;
5943 vcpu->arch.nmi_injected = false;
5945 vcpu->arch.switch_db_regs = 0;
5946 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5947 vcpu->arch.dr6 = DR6_FIXED_1;
5948 vcpu->arch.dr7 = DR7_FIXED_1;
5950 kvm_make_request(KVM_REQ_EVENT, vcpu);
5951 vcpu->arch.apf.msr_val = 0;
5952 vcpu->arch.st.msr_val = 0;
5954 kvmclock_reset(vcpu);
5956 kvm_clear_async_pf_completion_queue(vcpu);
5957 kvm_async_pf_hash_reset(vcpu);
5958 vcpu->arch.apf.halted = false;
5960 kvm_pmu_reset(vcpu);
5962 return kvm_x86_ops->vcpu_reset(vcpu);
5965 int kvm_arch_hardware_enable(void *garbage)
5968 struct kvm_vcpu *vcpu;
5971 kvm_shared_msr_cpu_online();
5972 list_for_each_entry(kvm, &vm_list, vm_list)
5973 kvm_for_each_vcpu(i, vcpu, kvm)
5974 if (vcpu->cpu == smp_processor_id())
5975 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5976 return kvm_x86_ops->hardware_enable(garbage);
5979 void kvm_arch_hardware_disable(void *garbage)
5981 kvm_x86_ops->hardware_disable(garbage);
5982 drop_user_return_notifiers(garbage);
5985 int kvm_arch_hardware_setup(void)
5987 return kvm_x86_ops->hardware_setup();
5990 void kvm_arch_hardware_unsetup(void)
5992 kvm_x86_ops->hardware_unsetup();
5995 void kvm_arch_check_processor_compat(void *rtn)
5997 kvm_x86_ops->check_processor_compatibility(rtn);
6000 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6006 BUG_ON(vcpu->kvm == NULL);
6009 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6010 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6011 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6013 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6015 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6020 vcpu->arch.pio_data = page_address(page);
6022 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6024 r = kvm_mmu_create(vcpu);
6026 goto fail_free_pio_data;
6028 if (irqchip_in_kernel(kvm)) {
6029 r = kvm_create_lapic(vcpu);
6031 goto fail_mmu_destroy;
6034 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6036 if (!vcpu->arch.mce_banks) {
6038 goto fail_free_lapic;
6040 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6042 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6043 goto fail_free_mce_banks;
6045 kvm_async_pf_hash_reset(vcpu);
6049 fail_free_mce_banks:
6050 kfree(vcpu->arch.mce_banks);
6052 kvm_free_lapic(vcpu);
6054 kvm_mmu_destroy(vcpu);
6056 free_page((unsigned long)vcpu->arch.pio_data);
6061 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6065 kvm_pmu_destroy(vcpu);
6066 kfree(vcpu->arch.mce_banks);
6067 kvm_free_lapic(vcpu);
6068 idx = srcu_read_lock(&vcpu->kvm->srcu);
6069 kvm_mmu_destroy(vcpu);
6070 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6071 free_page((unsigned long)vcpu->arch.pio_data);
6074 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6079 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6080 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6082 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6083 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6085 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6090 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6093 kvm_mmu_unload(vcpu);
6097 static void kvm_free_vcpus(struct kvm *kvm)
6100 struct kvm_vcpu *vcpu;
6103 * Unpin any mmu pages first.
6105 kvm_for_each_vcpu(i, vcpu, kvm) {
6106 kvm_clear_async_pf_completion_queue(vcpu);
6107 kvm_unload_vcpu_mmu(vcpu);
6109 kvm_for_each_vcpu(i, vcpu, kvm)
6110 kvm_arch_vcpu_free(vcpu);
6112 mutex_lock(&kvm->lock);
6113 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6114 kvm->vcpus[i] = NULL;
6116 atomic_set(&kvm->online_vcpus, 0);
6117 mutex_unlock(&kvm->lock);
6120 void kvm_arch_sync_events(struct kvm *kvm)
6122 kvm_free_all_assigned_devices(kvm);
6126 void kvm_arch_destroy_vm(struct kvm *kvm)
6128 kvm_iommu_unmap_guest(kvm);
6129 kfree(kvm->arch.vpic);
6130 kfree(kvm->arch.vioapic);
6131 kvm_free_vcpus(kvm);
6132 if (kvm->arch.apic_access_page)
6133 put_page(kvm->arch.apic_access_page);
6134 if (kvm->arch.ept_identity_pagetable)
6135 put_page(kvm->arch.ept_identity_pagetable);
6138 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6139 struct kvm_memory_slot *memslot,
6140 struct kvm_memory_slot old,
6141 struct kvm_userspace_memory_region *mem,
6144 int npages = memslot->npages;
6145 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6147 /* Prevent internal slot pages from being moved by fork()/COW. */
6148 if (memslot->id >= KVM_MEMORY_SLOTS)
6149 map_flags = MAP_SHARED | MAP_ANONYMOUS;
6151 /*To keep backward compatibility with older userspace,
6152 *x86 needs to hanlde !user_alloc case.
6155 if (npages && !old.rmap) {
6156 unsigned long userspace_addr;
6158 down_write(¤t->mm->mmap_sem);
6159 userspace_addr = do_mmap(NULL, 0,
6161 PROT_READ | PROT_WRITE,
6164 up_write(¤t->mm->mmap_sem);
6166 if (IS_ERR((void *)userspace_addr))
6167 return PTR_ERR((void *)userspace_addr);
6169 memslot->userspace_addr = userspace_addr;
6177 void kvm_arch_commit_memory_region(struct kvm *kvm,
6178 struct kvm_userspace_memory_region *mem,
6179 struct kvm_memory_slot old,
6183 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
6185 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6188 down_write(¤t->mm->mmap_sem);
6189 ret = do_munmap(current->mm, old.userspace_addr,
6190 old.npages * PAGE_SIZE);
6191 up_write(¤t->mm->mmap_sem);
6194 "kvm_vm_ioctl_set_memory_region: "
6195 "failed to munmap memory\n");
6198 if (!kvm->arch.n_requested_mmu_pages)
6199 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6201 spin_lock(&kvm->mmu_lock);
6203 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6204 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
6205 spin_unlock(&kvm->mmu_lock);
6208 void kvm_arch_flush_shadow(struct kvm *kvm)
6210 kvm_mmu_zap_all(kvm);
6211 kvm_reload_remote_mmus(kvm);
6214 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6216 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6217 !vcpu->arch.apf.halted)
6218 || !list_empty_careful(&vcpu->async_pf.done)
6219 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6220 || atomic_read(&vcpu->arch.nmi_queued) ||
6221 (kvm_arch_interrupt_allowed(vcpu) &&
6222 kvm_cpu_has_interrupt(vcpu));
6225 void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6228 int cpu = vcpu->cpu;
6230 if (waitqueue_active(&vcpu->wq)) {
6231 wake_up_interruptible(&vcpu->wq);
6232 ++vcpu->stat.halt_wakeup;
6236 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6237 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
6238 smp_send_reschedule(cpu);
6242 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6244 return kvm_x86_ops->interrupt_allowed(vcpu);
6247 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6249 unsigned long current_rip = kvm_rip_read(vcpu) +
6250 get_segment_base(vcpu, VCPU_SREG_CS);
6252 return current_rip == linear_rip;
6254 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6256 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6258 unsigned long rflags;
6260 rflags = kvm_x86_ops->get_rflags(vcpu);
6261 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6262 rflags &= ~X86_EFLAGS_TF;
6265 EXPORT_SYMBOL_GPL(kvm_get_rflags);
6267 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6269 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
6270 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
6271 rflags |= X86_EFLAGS_TF;
6272 kvm_x86_ops->set_rflags(vcpu, rflags);
6273 kvm_make_request(KVM_REQ_EVENT, vcpu);
6275 EXPORT_SYMBOL_GPL(kvm_set_rflags);
6277 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6281 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
6282 is_error_page(work->page))
6285 r = kvm_mmu_reload(vcpu);
6289 if (!vcpu->arch.mmu.direct_map &&
6290 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6293 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6296 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6298 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6301 static inline u32 kvm_async_pf_next_probe(u32 key)
6303 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6306 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6308 u32 key = kvm_async_pf_hash_fn(gfn);
6310 while (vcpu->arch.apf.gfns[key] != ~0)
6311 key = kvm_async_pf_next_probe(key);
6313 vcpu->arch.apf.gfns[key] = gfn;
6316 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6319 u32 key = kvm_async_pf_hash_fn(gfn);
6321 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
6322 (vcpu->arch.apf.gfns[key] != gfn &&
6323 vcpu->arch.apf.gfns[key] != ~0); i++)
6324 key = kvm_async_pf_next_probe(key);
6329 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6331 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6334 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6338 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6340 vcpu->arch.apf.gfns[i] = ~0;
6342 j = kvm_async_pf_next_probe(j);
6343 if (vcpu->arch.apf.gfns[j] == ~0)
6345 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6347 * k lies cyclically in ]i,j]
6349 * |....j i.k.| or |.k..j i...|
6351 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6352 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6357 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6360 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6364 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6365 struct kvm_async_pf *work)
6367 struct x86_exception fault;
6369 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
6370 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
6372 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
6373 (vcpu->arch.apf.send_user_only &&
6374 kvm_x86_ops->get_cpl(vcpu) == 0))
6375 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6376 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6377 fault.vector = PF_VECTOR;
6378 fault.error_code_valid = true;
6379 fault.error_code = 0;
6380 fault.nested_page_fault = false;
6381 fault.address = work->arch.token;
6382 kvm_inject_page_fault(vcpu, &fault);
6386 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6387 struct kvm_async_pf *work)
6389 struct x86_exception fault;
6391 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6392 if (is_error_page(work->page))
6393 work->arch.token = ~0; /* broadcast wakeup */
6395 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6397 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6398 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6399 fault.vector = PF_VECTOR;
6400 fault.error_code_valid = true;
6401 fault.error_code = 0;
6402 fault.nested_page_fault = false;
6403 fault.address = work->arch.token;
6404 kvm_inject_page_fault(vcpu, &fault);
6406 vcpu->arch.apf.halted = false;
6409 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6411 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6414 return !kvm_event_needs_reinjection(vcpu) &&
6415 kvm_x86_ops->interrupt_allowed(vcpu);
6418 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6419 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6420 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6421 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6422 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
6423 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
6424 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
6425 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
6426 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
6427 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
6428 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
6429 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);