arch/x86/kvm/x86.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * derived from drivers/kvm/kvm_main.c
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright (C) 2008 Qumranet, Inc.
   9  * Copyright IBM Corporation, 2008
  10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  11  *
  12  * Authors:
  13  *   Avi Kivity   <avi@qumranet.com>
  14  *   Yaniv Kamay  <yaniv@qumranet.com>
  15  *   Amit Shah    <amit.shah@qumranet.com>
  16  *   Ben-Ami Yassour <benami@il.ibm.com>
  17  */
  18
  19 #include <linux/kvm_host.h>
  20 #include "irq.h"
  21 #include "mmu.h"
  22 #include "i8254.h"
  23 #include "tss.h"
  24 #include "kvm_cache_regs.h"
  25 #include "kvm_emulate.h"
  26 #include "x86.h"
  27 #include "cpuid.h"
  28 #include "pmu.h"
  29 #include "hyperv.h"
  30 #include "lapic.h"
  31
  32 #include <linux/clocksource.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/kvm.h>
  35 #include <linux/fs.h>
  36 #include <linux/vmalloc.h>
  37 #include <linux/export.h>
  38 #include <linux/moduleparam.h>
  39 #include <linux/mman.h>
  40 #include <linux/highmem.h>
  41 #include <linux/iommu.h>
  42 #include <linux/intel-iommu.h>
  43 #include <linux/cpufreq.h>
  44 #include <linux/user-return-notifier.h>
  45 #include <linux/srcu.h>
  46 #include <linux/slab.h>
  47 #include <linux/perf_event.h>
  48 #include <linux/uaccess.h>
  49 #include <linux/hash.h>
  50 #include <linux/pci.h>
  51 #include <linux/timekeeper_internal.h>
  52 #include <linux/pvclock_gtod.h>
  53 #include <linux/kvm_irqfd.h>
  54 #include <linux/irqbypass.h>
  55 #include <linux/sched/stat.h>
  56 #include <linux/sched/isolation.h>
  57 #include <linux/mem_encrypt.h>
  58
  59 #include <trace/events/kvm.h>
  60
  61 #include <asm/debugreg.h>
  62 #include <asm/msr.h>
  63 #include <asm/desc.h>
  64 #include <asm/mce.h>
  65 #include <linux/kernel_stat.h>
  66 #include <asm/fpu/internal.h> /* Ugh! */
  67 #include <asm/pvclock.h>
  68 #include <asm/div64.h>
  69 #include <asm/irq_remapping.h>
  70 #include <asm/mshyperv.h>
  71 #include <asm/hypervisor.h>
  72 #include <asm/intel_pt.h>
  73 #include <asm/emulate_prefix.h>
  74 #include <clocksource/hyperv_timer.h>
  75
  76 #define CREATE_TRACE_POINTS
  77 #include "trace.h"
  78
  79 #define MAX_IO_MSRS 256
  80 #define KVM_MAX_MCE_BANKS 32
  81 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
  82 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
  83
  84 #define emul_to_vcpu(ctxt) \
  85         ((struct kvm_vcpu *)(ctxt)->vcpu)
  86
  87 /* EFER defaults:
  88  * - enable syscall per default because its emulated by KVM
  89  * - enable LME and LMA per default on 64 bit KVM
  90  */
  91 #ifdef CONFIG_X86_64
  92 static
  93 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
  94 #else
  95 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
  96 #endif
  97
  98 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
  99
 100 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
 101                                     KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
 102
 103 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
 104 static void process_nmi(struct kvm_vcpu *vcpu);
 105 static void enter_smm(struct kvm_vcpu *vcpu);
 106 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
 107 static void store_regs(struct kvm_vcpu *vcpu);
 108 static int sync_regs(struct kvm_vcpu *vcpu);
 109
 110 struct kvm_x86_ops kvm_x86_ops __read_mostly;
 111 EXPORT_SYMBOL_GPL(kvm_x86_ops);
 112
 113 static bool __read_mostly ignore_msrs = 0;
 114 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
 115
 116 static bool __read_mostly report_ignored_msrs = true;
 117 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
 118
 119 unsigned int min_timer_period_us = 200;
 120 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
 121
 122 static bool __read_mostly kvmclock_periodic_sync = true;
 123 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
 124
 125 bool __read_mostly kvm_has_tsc_control;
 126 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
 127 u32  __read_mostly kvm_max_guest_tsc_khz;
 128 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
 129 u8   __read_mostly kvm_tsc_scaling_ratio_frac_bits;
 130 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
 131 u64  __read_mostly kvm_max_tsc_scaling_ratio;
 132 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
 133 u64 __read_mostly kvm_default_tsc_scaling_ratio;
 134 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
 135
 136 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
 137 static u32 __read_mostly tsc_tolerance_ppm = 250;
 138 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
 139
 140 /*
 141  * lapic timer advance (tscdeadline mode only) in nanoseconds.  '-1' enables
 142  * adaptive tuning starting from default advancment of 1000ns.  '0' disables
 143  * advancement entirely.  Any other value is used as-is and disables adaptive
 144  * tuning, i.e. allows priveleged userspace to set an exact advancement time.
 145  */
 146 static int __read_mostly lapic_timer_advance_ns = -1;
 147 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
 148
 149 static bool __read_mostly vector_hashing = true;
 150 module_param(vector_hashing, bool, S_IRUGO);
 151
 152 bool __read_mostly enable_vmware_backdoor = false;
 153 module_param(enable_vmware_backdoor, bool, S_IRUGO);
 154 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
 155
 156 static bool __read_mostly force_emulation_prefix = false;
 157 module_param(force_emulation_prefix, bool, S_IRUGO);
 158
 159 int __read_mostly pi_inject_timer = -1;
 160 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
 161
 162 #define KVM_NR_SHARED_MSRS 16
 163
 164 struct kvm_shared_msrs_global {
 165         int nr;
 166         u32 msrs[KVM_NR_SHARED_MSRS];
 167 };
 168
 169 struct kvm_shared_msrs {
 170         struct user_return_notifier urn;
 171         bool registered;
 172         struct kvm_shared_msr_values {
 173                 u64 host;
 174                 u64 curr;
 175         } values[KVM_NR_SHARED_MSRS];
 176 };
 177
 178 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
 179 static struct kvm_shared_msrs __percpu *shared_msrs;
 180
 181 #define KVM_SUPPORTED_XCR0     (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
 182                                 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
 183                                 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
 184                                 | XFEATURE_MASK_PKRU)
 185
 186 u64 __read_mostly host_efer;
 187 EXPORT_SYMBOL_GPL(host_efer);
 188
 189 static u64 __read_mostly host_xss;
 190 u64 __read_mostly supported_xss;
 191 EXPORT_SYMBOL_GPL(supported_xss);
 192
 193 struct kvm_stats_debugfs_item debugfs_entries[] = {
 194         VCPU_STAT("pf_fixed", pf_fixed),
 195         VCPU_STAT("pf_guest", pf_guest),
 196         VCPU_STAT("tlb_flush", tlb_flush),
 197         VCPU_STAT("invlpg", invlpg),
 198         VCPU_STAT("exits", exits),
 199         VCPU_STAT("io_exits", io_exits),
 200         VCPU_STAT("mmio_exits", mmio_exits),
 201         VCPU_STAT("signal_exits", signal_exits),
 202         VCPU_STAT("irq_window", irq_window_exits),
 203         VCPU_STAT("nmi_window", nmi_window_exits),
 204         VCPU_STAT("halt_exits", halt_exits),
 205         VCPU_STAT("halt_successful_poll", halt_successful_poll),
 206         VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
 207         VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
 208         VCPU_STAT("halt_wakeup", halt_wakeup),
 209         VCPU_STAT("hypercalls", hypercalls),
 210         VCPU_STAT("request_irq", request_irq_exits),
 211         VCPU_STAT("irq_exits", irq_exits),
 212         VCPU_STAT("host_state_reload", host_state_reload),
 213         VCPU_STAT("fpu_reload", fpu_reload),
 214         VCPU_STAT("insn_emulation", insn_emulation),
 215         VCPU_STAT("insn_emulation_fail", insn_emulation_fail),
 216         VCPU_STAT("irq_injections", irq_injections),
 217         VCPU_STAT("nmi_injections", nmi_injections),
 218         VCPU_STAT("req_event", req_event),
 219         VCPU_STAT("l1d_flush", l1d_flush),
 220         VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped),
 221         VM_STAT("mmu_pte_write", mmu_pte_write),
 222         VM_STAT("mmu_pte_updated", mmu_pte_updated),
 223         VM_STAT("mmu_pde_zapped", mmu_pde_zapped),
 224         VM_STAT("mmu_flooded", mmu_flooded),
 225         VM_STAT("mmu_recycled", mmu_recycled),
 226         VM_STAT("mmu_cache_miss", mmu_cache_miss),
 227         VM_STAT("mmu_unsync", mmu_unsync),
 228         VM_STAT("remote_tlb_flush", remote_tlb_flush),
 229         VM_STAT("largepages", lpages, .mode = 0444),
 230         VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444),
 231         VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions),
 232         { NULL }
 233 };
 234
 235 u64 __read_mostly host_xcr0;
 236 u64 __read_mostly supported_xcr0;
 237 EXPORT_SYMBOL_GPL(supported_xcr0);
 238
 239 struct kmem_cache *x86_fpu_cache;
 240 EXPORT_SYMBOL_GPL(x86_fpu_cache);
 241
 242 static struct kmem_cache *x86_emulator_cache;
 243
 244 static struct kmem_cache *kvm_alloc_emulator_cache(void)
 245 {
 246         unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
 247         unsigned int size = sizeof(struct x86_emulate_ctxt);
 248
 249         return kmem_cache_create_usercopy("x86_emulator", size,
 250                                           __alignof__(struct x86_emulate_ctxt),
 251                                           SLAB_ACCOUNT, useroffset,
 252                                           size - useroffset, NULL);
 253 }
 254
 255 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
 256
 257 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
 258 {
 259         int i;
 260         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
 261                 vcpu->arch.apf.gfns[i] = ~0;
 262 }
 263
 264 static void kvm_on_user_return(struct user_return_notifier *urn)
 265 {
 266         unsigned slot;
 267         struct kvm_shared_msrs *locals
 268                 = container_of(urn, struct kvm_shared_msrs, urn);
 269         struct kvm_shared_msr_values *values;
 270         unsigned long flags;
 271
 272         /*
 273          * Disabling irqs at this point since the following code could be
 274          * interrupted and executed through kvm_arch_hardware_disable()
 275          */
 276         local_irq_save(flags);
 277         if (locals->registered) {
 278                 locals->registered = false;
 279                 user_return_notifier_unregister(urn);
 280         }
 281         local_irq_restore(flags);
 282         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
 283                 values = &locals->values[slot];
 284                 if (values->host != values->curr) {
 285                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
 286                         values->curr = values->host;
 287                 }
 288         }
 289 }
 290
 291 void kvm_define_shared_msr(unsigned slot, u32 msr)
 292 {
 293         BUG_ON(slot >= KVM_NR_SHARED_MSRS);
 294         shared_msrs_global.msrs[slot] = msr;
 295         if (slot >= shared_msrs_global.nr)
 296                 shared_msrs_global.nr = slot + 1;
 297 }
 298 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
 299
 300 static void kvm_shared_msr_cpu_online(void)
 301 {
 302         unsigned int cpu = smp_processor_id();
 303         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 304         u64 value;
 305         int i;
 306
 307         for (i = 0; i < shared_msrs_global.nr; ++i) {
 308                 rdmsrl_safe(shared_msrs_global.msrs[i], &value);
 309                 smsr->values[i].host = value;
 310                 smsr->values[i].curr = value;
 311         }
 312 }
 313
 314 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
 315 {
 316         unsigned int cpu = smp_processor_id();
 317         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 318         int err;
 319
 320         value = (value & mask) | (smsr->values[slot].host & ~mask);
 321         if (value == smsr->values[slot].curr)
 322                 return 0;
 323         err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
 324         if (err)
 325                 return 1;
 326
 327         smsr->values[slot].curr = value;
 328         if (!smsr->registered) {
 329                 smsr->urn.on_user_return = kvm_on_user_return;
 330                 user_return_notifier_register(&smsr->urn);
 331                 smsr->registered = true;
 332         }
 333         return 0;
 334 }
 335 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
 336
 337 static void drop_user_return_notifiers(void)
 338 {
 339         unsigned int cpu = smp_processor_id();
 340         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 341
 342         if (smsr->registered)
 343                 kvm_on_user_return(&smsr->urn);
 344 }
 345
 346 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
 347 {
 348         return vcpu->arch.apic_base;
 349 }
 350 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
 351
 352 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
 353 {
 354         return kvm_apic_mode(kvm_get_apic_base(vcpu));
 355 }
 356 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
 357
 358 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 359 {
 360         enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
 361         enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
 362         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
 363                 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
 364
 365         if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
 366                 return 1;
 367         if (!msr_info->host_initiated) {
 368                 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
 369                         return 1;
 370                 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
 371                         return 1;
 372         }
 373
 374         kvm_lapic_set_base(vcpu, msr_info->data);
 375         kvm_recalculate_apic_map(vcpu->kvm);
 376         return 0;
 377 }
 378 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
 379
 380 asmlinkage __visible void kvm_spurious_fault(void)
 381 {
 382         /* Fault while not rebooting.  We want the trace. */
 383         BUG_ON(!kvm_rebooting);
 384 }
 385 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
 386
 387 #define EXCPT_BENIGN            0
 388 #define EXCPT_CONTRIBUTORY      1
 389 #define EXCPT_PF                2
 390
 391 static int exception_class(int vector)
 392 {
 393         switch (vector) {
 394         case PF_VECTOR:
 395                 return EXCPT_PF;
 396         case DE_VECTOR:
 397         case TS_VECTOR:
 398         case NP_VECTOR:
 399         case SS_VECTOR:
 400         case GP_VECTOR:
 401                 return EXCPT_CONTRIBUTORY;
 402         default:
 403                 break;
 404         }
 405         return EXCPT_BENIGN;
 406 }
 407
 408 #define EXCPT_FAULT             0
 409 #define EXCPT_TRAP              1
 410 #define EXCPT_ABORT             2
 411 #define EXCPT_INTERRUPT         3
 412
 413 static int exception_type(int vector)
 414 {
 415         unsigned int mask;
 416
 417         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
 418                 return EXCPT_INTERRUPT;
 419
 420         mask = 1 << vector;
 421
 422         /* #DB is trap, as instruction watchpoints are handled elsewhere */
 423         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
 424                 return EXCPT_TRAP;
 425
 426         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
 427                 return EXCPT_ABORT;
 428
 429         /* Reserved exceptions will result in fault */
 430         return EXCPT_FAULT;
 431 }
 432
 433 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
 434 {
 435         unsigned nr = vcpu->arch.exception.nr;
 436         bool has_payload = vcpu->arch.exception.has_payload;
 437         unsigned long payload = vcpu->arch.exception.payload;
 438
 439         if (!has_payload)
 440                 return;
 441
 442         switch (nr) {
 443         case DB_VECTOR:
 444                 /*
 445                  * "Certain debug exceptions may clear bit 0-3.  The
 446                  * remaining contents of the DR6 register are never
 447                  * cleared by the processor".
 448                  */
 449                 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
 450                 /*
 451                  * DR6.RTM is set by all #DB exceptions that don't clear it.
 452                  */
 453                 vcpu->arch.dr6 |= DR6_RTM;
 454                 vcpu->arch.dr6 |= payload;
 455                 /*
 456                  * Bit 16 should be set in the payload whenever the #DB
 457                  * exception should clear DR6.RTM. This makes the payload
 458                  * compatible with the pending debug exceptions under VMX.
 459                  * Though not currently documented in the SDM, this also
 460                  * makes the payload compatible with the exit qualification
 461                  * for #DB exceptions under VMX.
 462                  */
 463                 vcpu->arch.dr6 ^= payload & DR6_RTM;
 464
 465                 /*
 466                  * The #DB payload is defined as compatible with the 'pending
 467                  * debug exceptions' field under VMX, not DR6. While bit 12 is
 468                  * defined in the 'pending debug exceptions' field (enabled
 469                  * breakpoint), it is reserved and must be zero in DR6.
 470                  */
 471                 vcpu->arch.dr6 &= ~BIT(12);
 472                 break;
 473         case PF_VECTOR:
 474                 vcpu->arch.cr2 = payload;
 475                 break;
 476         }
 477
 478         vcpu->arch.exception.has_payload = false;
 479         vcpu->arch.exception.payload = 0;
 480 }
 481 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
 482
 483 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
 484                 unsigned nr, bool has_error, u32 error_code,
 485                 bool has_payload, unsigned long payload, bool reinject)
 486 {
 487         u32 prev_nr;
 488         int class1, class2;
 489
 490         kvm_make_request(KVM_REQ_EVENT, vcpu);
 491
 492         if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
 493         queue:
 494                 if (has_error && !is_protmode(vcpu))
 495                         has_error = false;
 496                 if (reinject) {
 497                         /*
 498                          * On vmentry, vcpu->arch.exception.pending is only
 499                          * true if an event injection was blocked by
 500                          * nested_run_pending.  In that case, however,
 501                          * vcpu_enter_guest requests an immediate exit,
 502                          * and the guest shouldn't proceed far enough to
 503                          * need reinjection.
 504                          */
 505                         WARN_ON_ONCE(vcpu->arch.exception.pending);
 506                         vcpu->arch.exception.injected = true;
 507                         if (WARN_ON_ONCE(has_payload)) {
 508                                 /*
 509                                  * A reinjected event has already
 510                                  * delivered its payload.
 511                                  */
 512                                 has_payload = false;
 513                                 payload = 0;
 514                         }
 515                 } else {
 516                         vcpu->arch.exception.pending = true;
 517                         vcpu->arch.exception.injected = false;
 518                 }
 519                 vcpu->arch.exception.has_error_code = has_error;
 520                 vcpu->arch.exception.nr = nr;
 521                 vcpu->arch.exception.error_code = error_code;
 522                 vcpu->arch.exception.has_payload = has_payload;
 523                 vcpu->arch.exception.payload = payload;
 524                 if (!is_guest_mode(vcpu))
 525                         kvm_deliver_exception_payload(vcpu);
 526                 return;
 527         }
 528
 529         /* to check exception */
 530         prev_nr = vcpu->arch.exception.nr;
 531         if (prev_nr == DF_VECTOR) {
 532                 /* triple fault -> shutdown */
 533                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
 534                 return;
 535         }
 536         class1 = exception_class(prev_nr);
 537         class2 = exception_class(nr);
 538         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
 539                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
 540                 /*
 541                  * Generate double fault per SDM Table 5-5.  Set
 542                  * exception.pending = true so that the double fault
 543                  * can trigger a nested vmexit.
 544                  */
 545                 vcpu->arch.exception.pending = true;
 546                 vcpu->arch.exception.injected = false;
 547                 vcpu->arch.exception.has_error_code = true;
 548                 vcpu->arch.exception.nr = DF_VECTOR;
 549                 vcpu->arch.exception.error_code = 0;
 550                 vcpu->arch.exception.has_payload = false;
 551                 vcpu->arch.exception.payload = 0;
 552         } else
 553                 /* replace previous exception with a new one in a hope
 554                    that instruction re-execution will regenerate lost
 555                    exception */
 556                 goto queue;
 557 }
 558
 559 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 560 {
 561         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
 562 }
 563 EXPORT_SYMBOL_GPL(kvm_queue_exception);
 564
 565 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 566 {
 567         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
 568 }
 569 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
 570
 571 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
 572                            unsigned long payload)
 573 {
 574         kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
 575 }
 576 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
 577
 578 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
 579                                     u32 error_code, unsigned long payload)
 580 {
 581         kvm_multiple_exception(vcpu, nr, true, error_code,
 582                                true, payload, false);
 583 }
 584
 585 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
 586 {
 587         if (err)
 588                 kvm_inject_gp(vcpu, 0);
 589         else
 590                 return kvm_skip_emulated_instruction(vcpu);
 591
 592         return 1;
 593 }
 594 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
 595
 596 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 597 {
 598         ++vcpu->stat.pf_guest;
 599         vcpu->arch.exception.nested_apf =
 600                 is_guest_mode(vcpu) && fault->async_page_fault;
 601         if (vcpu->arch.exception.nested_apf) {
 602                 vcpu->arch.apf.nested_apf_token = fault->address;
 603                 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
 604         } else {
 605                 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
 606                                         fault->address);
 607         }
 608 }
 609 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
 610
 611 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
 612                                     struct x86_exception *fault)
 613 {
 614         struct kvm_mmu *fault_mmu;
 615         WARN_ON_ONCE(fault->vector != PF_VECTOR);
 616
 617         fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
 618                                                vcpu->arch.walk_mmu;
 619
 620         /*
 621          * Invalidate the TLB entry for the faulting address, if it exists,
 622          * else the access will fault indefinitely (and to emulate hardware).
 623          */
 624         if ((fault->error_code & PFERR_PRESENT_MASK) &&
 625             !(fault->error_code & PFERR_RSVD_MASK))
 626                 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
 627                                        fault_mmu->root_hpa);
 628
 629         fault_mmu->inject_page_fault(vcpu, fault);
 630         return fault->nested_page_fault;
 631 }
 632 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
 633
 634 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
 635 {
 636         atomic_inc(&vcpu->arch.nmi_queued);
 637         kvm_make_request(KVM_REQ_NMI, vcpu);
 638 }
 639 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
 640
 641 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 642 {
 643         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
 644 }
 645 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
 646
 647 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 648 {
 649         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
 650 }
 651 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
 652
 653 /*
 654  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
 655  * a #GP and return false.
 656  */
 657 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
 658 {
 659         if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl)
 660                 return true;
 661         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
 662         return false;
 663 }
 664 EXPORT_SYMBOL_GPL(kvm_require_cpl);
 665
 666 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
 667 {
 668         if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 669                 return true;
 670
 671         kvm_queue_exception(vcpu, UD_VECTOR);
 672         return false;
 673 }
 674 EXPORT_SYMBOL_GPL(kvm_require_dr);
 675
 676 /*
 677  * This function will be used to read from the physical memory of the currently
 678  * running guest. The difference to kvm_vcpu_read_guest_page is that this function
 679  * can read from guest physical or from the guest's guest physical memory.
 680  */
 681 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 682                             gfn_t ngfn, void *data, int offset, int len,
 683                             u32 access)
 684 {
 685         struct x86_exception exception;
 686         gfn_t real_gfn;
 687         gpa_t ngpa;
 688
 689         ngpa     = gfn_to_gpa(ngfn);
 690         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
 691         if (real_gfn == UNMAPPED_GVA)
 692                 return -EFAULT;
 693
 694         real_gfn = gpa_to_gfn(real_gfn);
 695
 696         return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
 697 }
 698 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
 699
 700 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
 701                                void *data, int offset, int len, u32 access)
 702 {
 703         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
 704                                        data, offset, len, access);
 705 }
 706
 707 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
 708 {
 709         return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
 710                rsvd_bits(1, 2);
 711 }
 712
 713 /*
 714  * Load the pae pdptrs.  Return 1 if they are all valid, 0 otherwise.
 715  */
 716 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
 717 {
 718         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
 719         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
 720         int i;
 721         int ret;
 722         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
 723
 724         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
 725                                       offset * sizeof(u64), sizeof(pdpte),
 726                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
 727         if (ret < 0) {
 728                 ret = 0;
 729                 goto out;
 730         }
 731         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
 732                 if ((pdpte[i] & PT_PRESENT_MASK) &&
 733                     (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
 734                         ret = 0;
 735                         goto out;
 736                 }
 737         }
 738         ret = 1;
 739
 740         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
 741         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
 742
 743 out:
 744
 745         return ret;
 746 }
 747 EXPORT_SYMBOL_GPL(load_pdptrs);
 748
 749 bool pdptrs_changed(struct kvm_vcpu *vcpu)
 750 {
 751         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
 752         int offset;
 753         gfn_t gfn;
 754         int r;
 755
 756         if (!is_pae_paging(vcpu))
 757                 return false;
 758
 759         if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
 760                 return true;
 761
 762         gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
 763         offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
 764         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
 765                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
 766         if (r < 0)
 767                 return true;
 768
 769         return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
 770 }
 771 EXPORT_SYMBOL_GPL(pdptrs_changed);
 772
 773 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 774 {
 775         unsigned long old_cr0 = kvm_read_cr0(vcpu);
 776         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
 777
 778         cr0 |= X86_CR0_ET;
 779
 780 #ifdef CONFIG_X86_64
 781         if (cr0 & 0xffffffff00000000UL)
 782                 return 1;
 783 #endif
 784
 785         cr0 &= ~CR0_RESERVED_BITS;
 786
 787         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
 788                 return 1;
 789
 790         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
 791                 return 1;
 792
 793         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 794 #ifdef CONFIG_X86_64
 795                 if ((vcpu->arch.efer & EFER_LME)) {
 796                         int cs_db, cs_l;
 797
 798                         if (!is_pae(vcpu))
 799                                 return 1;
 800                         kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
 801                         if (cs_l)
 802                                 return 1;
 803                 } else
 804 #endif
 805                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 806                                                  kvm_read_cr3(vcpu)))
 807                         return 1;
 808         }
 809
 810         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
 811                 return 1;
 812
 813         kvm_x86_ops.set_cr0(vcpu, cr0);
 814
 815         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
 816                 kvm_clear_async_pf_completion_queue(vcpu);
 817                 kvm_async_pf_hash_reset(vcpu);
 818         }
 819
 820         if ((cr0 ^ old_cr0) & update_bits)
 821                 kvm_mmu_reset_context(vcpu);
 822
 823         if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
 824             kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
 825             !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
 826                 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
 827
 828         return 0;
 829 }
 830 EXPORT_SYMBOL_GPL(kvm_set_cr0);
 831
 832 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 833 {
 834         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
 835 }
 836 EXPORT_SYMBOL_GPL(kvm_lmsw);
 837
 838 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
 839 {
 840         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
 841
 842                 if (vcpu->arch.xcr0 != host_xcr0)
 843                         xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
 844
 845                 if (vcpu->arch.xsaves_enabled &&
 846                     vcpu->arch.ia32_xss != host_xss)
 847                         wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
 848         }
 849
 850         if (static_cpu_has(X86_FEATURE_PKU) &&
 851             (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
 852              (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
 853             vcpu->arch.pkru != vcpu->arch.host_pkru)
 854                 __write_pkru(vcpu->arch.pkru);
 855 }
 856 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
 857
 858 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
 859 {
 860         if (static_cpu_has(X86_FEATURE_PKU) &&
 861             (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
 862              (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
 863                 vcpu->arch.pkru = rdpkru();
 864                 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
 865                         __write_pkru(vcpu->arch.host_pkru);
 866         }
 867
 868         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
 869
 870                 if (vcpu->arch.xcr0 != host_xcr0)
 871                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
 872
 873                 if (vcpu->arch.xsaves_enabled &&
 874                     vcpu->arch.ia32_xss != host_xss)
 875                         wrmsrl(MSR_IA32_XSS, host_xss);
 876         }
 877
 878 }
 879 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
 880
 881 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 882 {
 883         u64 xcr0 = xcr;
 884         u64 old_xcr0 = vcpu->arch.xcr0;
 885         u64 valid_bits;
 886
 887         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
 888         if (index != XCR_XFEATURE_ENABLED_MASK)
 889                 return 1;
 890         if (!(xcr0 & XFEATURE_MASK_FP))
 891                 return 1;
 892         if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
 893                 return 1;
 894
 895         /*
 896          * Do not allow the guest to set bits that we do not support
 897          * saving.  However, xcr0 bit 0 is always set, even if the
 898          * emulated CPU does not support XSAVE (see fx_init).
 899          */
 900         valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
 901         if (xcr0 & ~valid_bits)
 902                 return 1;
 903
 904         if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
 905             (!(xcr0 & XFEATURE_MASK_BNDCSR)))
 906                 return 1;
 907
 908         if (xcr0 & XFEATURE_MASK_AVX512) {
 909                 if (!(xcr0 & XFEATURE_MASK_YMM))
 910                         return 1;
 911                 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
 912                         return 1;
 913         }
 914         vcpu->arch.xcr0 = xcr0;
 915
 916         if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
 917                 kvm_update_cpuid(vcpu);
 918         return 0;
 919 }
 920
 921 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 922 {
 923         if (kvm_x86_ops.get_cpl(vcpu) != 0 ||
 924             __kvm_set_xcr(vcpu, index, xcr)) {
 925                 kvm_inject_gp(vcpu, 0);
 926                 return 1;
 927         }
 928         return 0;
 929 }
 930 EXPORT_SYMBOL_GPL(kvm_set_xcr);
 931
 932 #define __cr4_reserved_bits(__cpu_has, __c)             \
 933 ({                                                      \
 934         u64 __reserved_bits = CR4_RESERVED_BITS;        \
 935                                                         \
 936         if (!__cpu_has(__c, X86_FEATURE_XSAVE))         \
 937                 __reserved_bits |= X86_CR4_OSXSAVE;     \
 938         if (!__cpu_has(__c, X86_FEATURE_SMEP))          \
 939                 __reserved_bits |= X86_CR4_SMEP;        \
 940         if (!__cpu_has(__c, X86_FEATURE_SMAP))          \
 941                 __reserved_bits |= X86_CR4_SMAP;        \
 942         if (!__cpu_has(__c, X86_FEATURE_FSGSBASE))      \
 943                 __reserved_bits |= X86_CR4_FSGSBASE;    \
 944         if (!__cpu_has(__c, X86_FEATURE_PKU))           \
 945                 __reserved_bits |= X86_CR4_PKE;         \
 946         if (!__cpu_has(__c, X86_FEATURE_LA57))          \
 947                 __reserved_bits |= X86_CR4_LA57;        \
 948         if (!__cpu_has(__c, X86_FEATURE_UMIP))          \
 949                 __reserved_bits |= X86_CR4_UMIP;        \
 950         __reserved_bits;                                \
 951 })
 952
 953 static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 954 {
 955         if (cr4 & cr4_reserved_bits)
 956                 return -EINVAL;
 957
 958         if (cr4 & __cr4_reserved_bits(guest_cpuid_has, vcpu))
 959                 return -EINVAL;
 960
 961         return 0;
 962 }
 963
 964 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 965 {
 966         unsigned long old_cr4 = kvm_read_cr4(vcpu);
 967         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
 968                                    X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
 969
 970         if (kvm_valid_cr4(vcpu, cr4))
 971                 return 1;
 972
 973         if (is_long_mode(vcpu)) {
 974                 if (!(cr4 & X86_CR4_PAE))
 975                         return 1;
 976         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
 977                    && ((cr4 ^ old_cr4) & pdptr_bits)
 978                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 979                                    kvm_read_cr3(vcpu)))
 980                 return 1;
 981
 982         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
 983                 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
 984                         return 1;
 985
 986                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
 987                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
 988                         return 1;
 989         }
 990
 991         if (kvm_x86_ops.set_cr4(vcpu, cr4))
 992                 return 1;
 993
 994         if (((cr4 ^ old_cr4) & pdptr_bits) ||
 995             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
 996                 kvm_mmu_reset_context(vcpu);
 997
 998         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
 999                 kvm_update_cpuid(vcpu);
1000
1001         return 0;
1002 }
1003 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1004
1005 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1006 {
1007         bool skip_tlb_flush = false;
1008 #ifdef CONFIG_X86_64
1009         bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1010
1011         if (pcid_enabled) {
1012                 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1013                 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1014         }
1015 #endif
1016
1017         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1018                 if (!skip_tlb_flush) {
1019                         kvm_mmu_sync_roots(vcpu);
1020                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1021                 }
1022                 return 0;
1023         }
1024
1025         if (is_long_mode(vcpu) &&
1026             (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
1027                 return 1;
1028         else if (is_pae_paging(vcpu) &&
1029                  !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1030                 return 1;
1031
1032         kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush);
1033         vcpu->arch.cr3 = cr3;
1034         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1035
1036         return 0;
1037 }
1038 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1039
1040 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1041 {
1042         if (cr8 & CR8_RESERVED_BITS)
1043                 return 1;
1044         if (lapic_in_kernel(vcpu))
1045                 kvm_lapic_set_tpr(vcpu, cr8);
1046         else
1047                 vcpu->arch.cr8 = cr8;
1048         return 0;
1049 }
1050 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1051
1052 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1053 {
1054         if (lapic_in_kernel(vcpu))
1055                 return kvm_lapic_get_cr8(vcpu);
1056         else
1057                 return vcpu->arch.cr8;
1058 }
1059 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1060
1061 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1062 {
1063         int i;
1064
1065         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1066                 for (i = 0; i < KVM_NR_DB_REGS; i++)
1067                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1068                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1069         }
1070 }
1071
1072 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1073 {
1074         unsigned long dr7;
1075
1076         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1077                 dr7 = vcpu->arch.guest_debug_dr7;
1078         else
1079                 dr7 = vcpu->arch.dr7;
1080         kvm_x86_ops.set_dr7(vcpu, dr7);
1081         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1082         if (dr7 & DR7_BP_EN_MASK)
1083                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1084 }
1085
1086 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1087 {
1088         u64 fixed = DR6_FIXED_1;
1089
1090         if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1091                 fixed |= DR6_RTM;
1092         return fixed;
1093 }
1094
1095 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1096 {
1097         size_t size = ARRAY_SIZE(vcpu->arch.db);
1098
1099         switch (dr) {
1100         case 0 ... 3:
1101                 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1102                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1103                         vcpu->arch.eff_db[dr] = val;
1104                 break;
1105         case 4:
1106                 /* fall through */
1107         case 6:
1108                 if (val & 0xffffffff00000000ULL)
1109                         return -1; /* #GP */
1110                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1111                 break;
1112         case 5:
1113                 /* fall through */
1114         default: /* 7 */
1115                 if (!kvm_dr7_valid(val))
1116                         return -1; /* #GP */
1117                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1118                 kvm_update_dr7(vcpu);
1119                 break;
1120         }
1121
1122         return 0;
1123 }
1124
1125 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1126 {
1127         if (__kvm_set_dr(vcpu, dr, val)) {
1128                 kvm_inject_gp(vcpu, 0);
1129                 return 1;
1130         }
1131         return 0;
1132 }
1133 EXPORT_SYMBOL_GPL(kvm_set_dr);
1134
1135 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1136 {
1137         size_t size = ARRAY_SIZE(vcpu->arch.db);
1138
1139         switch (dr) {
1140         case 0 ... 3:
1141                 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1142                 break;
1143         case 4:
1144                 /* fall through */
1145         case 6:
1146                 *val = vcpu->arch.dr6;
1147                 break;
1148         case 5:
1149                 /* fall through */
1150         default: /* 7 */
1151                 *val = vcpu->arch.dr7;
1152                 break;
1153         }
1154         return 0;
1155 }
1156 EXPORT_SYMBOL_GPL(kvm_get_dr);
1157
1158 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1159 {
1160         u32 ecx = kvm_rcx_read(vcpu);
1161         u64 data;
1162         int err;
1163
1164         err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1165         if (err)
1166                 return err;
1167         kvm_rax_write(vcpu, (u32)data);
1168         kvm_rdx_write(vcpu, data >> 32);
1169         return err;
1170 }
1171 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1172
1173 /*
1174  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1175  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1176  *
1177  * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1178  * extract the supported MSRs from the related const lists.
1179  * msrs_to_save is selected from the msrs_to_save_all to reflect the
1180  * capabilities of the host cpu. This capabilities test skips MSRs that are
1181  * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1182  * may depend on host virtualization features rather than host cpu features.
1183  */
1184
1185 static const u32 msrs_to_save_all[] = {
1186         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1187         MSR_STAR,
1188 #ifdef CONFIG_X86_64
1189         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1190 #endif
1191         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1192         MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1193         MSR_IA32_SPEC_CTRL,
1194         MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1195         MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1196         MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1197         MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1198         MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1199         MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1200         MSR_IA32_UMWAIT_CONTROL,
1201
1202         MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1203         MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1204         MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1205         MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1206         MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1207         MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1208         MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1209         MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1210         MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1211         MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1212         MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1213         MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1214         MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1215         MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1216         MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1217         MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1218         MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1219         MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1220         MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1221         MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1222         MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1223         MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1224 };
1225
1226 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1227 static unsigned num_msrs_to_save;
1228
1229 static const u32 emulated_msrs_all[] = {
1230         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1231         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1232         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1233         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1234         HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1235         HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1236         HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1237         HV_X64_MSR_RESET,
1238         HV_X64_MSR_VP_INDEX,
1239         HV_X64_MSR_VP_RUNTIME,
1240         HV_X64_MSR_SCONTROL,
1241         HV_X64_MSR_STIMER0_CONFIG,
1242         HV_X64_MSR_VP_ASSIST_PAGE,
1243         HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1244         HV_X64_MSR_TSC_EMULATION_STATUS,
1245
1246         MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1247         MSR_KVM_PV_EOI_EN,
1248
1249         MSR_IA32_TSC_ADJUST,
1250         MSR_IA32_TSCDEADLINE,
1251         MSR_IA32_ARCH_CAPABILITIES,
1252         MSR_IA32_MISC_ENABLE,
1253         MSR_IA32_MCG_STATUS,
1254         MSR_IA32_MCG_CTL,
1255         MSR_IA32_MCG_EXT_CTL,
1256         MSR_IA32_SMBASE,
1257         MSR_SMI_COUNT,
1258         MSR_PLATFORM_INFO,
1259         MSR_MISC_FEATURES_ENABLES,
1260         MSR_AMD64_VIRT_SPEC_CTRL,
1261         MSR_IA32_POWER_CTL,
1262         MSR_IA32_UCODE_REV,
1263
1264         /*
1265          * The following list leaves out MSRs whose values are determined
1266          * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1267          * We always support the "true" VMX control MSRs, even if the host
1268          * processor does not, so I am putting these registers here rather
1269          * than in msrs_to_save_all.
1270          */
1271         MSR_IA32_VMX_BASIC,
1272         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1273         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1274         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1275         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1276         MSR_IA32_VMX_MISC,
1277         MSR_IA32_VMX_CR0_FIXED0,
1278         MSR_IA32_VMX_CR4_FIXED0,
1279         MSR_IA32_VMX_VMCS_ENUM,
1280         MSR_IA32_VMX_PROCBASED_CTLS2,
1281         MSR_IA32_VMX_EPT_VPID_CAP,
1282         MSR_IA32_VMX_VMFUNC,
1283
1284         MSR_K7_HWCR,
1285         MSR_KVM_POLL_CONTROL,
1286 };
1287
1288 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1289 static unsigned num_emulated_msrs;
1290
1291 /*
1292  * List of msr numbers which are used to expose MSR-based features that
1293  * can be used by a hypervisor to validate requested CPU features.
1294  */
1295 static const u32 msr_based_features_all[] = {
1296         MSR_IA32_VMX_BASIC,
1297         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1298         MSR_IA32_VMX_PINBASED_CTLS,
1299         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1300         MSR_IA32_VMX_PROCBASED_CTLS,
1301         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1302         MSR_IA32_VMX_EXIT_CTLS,
1303         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1304         MSR_IA32_VMX_ENTRY_CTLS,
1305         MSR_IA32_VMX_MISC,
1306         MSR_IA32_VMX_CR0_FIXED0,
1307         MSR_IA32_VMX_CR0_FIXED1,
1308         MSR_IA32_VMX_CR4_FIXED0,
1309         MSR_IA32_VMX_CR4_FIXED1,
1310         MSR_IA32_VMX_VMCS_ENUM,
1311         MSR_IA32_VMX_PROCBASED_CTLS2,
1312         MSR_IA32_VMX_EPT_VPID_CAP,
1313         MSR_IA32_VMX_VMFUNC,
1314
1315         MSR_F10H_DECFG,
1316         MSR_IA32_UCODE_REV,
1317         MSR_IA32_ARCH_CAPABILITIES,
1318 };
1319
1320 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1321 static unsigned int num_msr_based_features;
1322
1323 static u64 kvm_get_arch_capabilities(void)
1324 {
1325         u64 data = 0;
1326
1327         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1328                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1329
1330         /*
1331          * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1332          * the nested hypervisor runs with NX huge pages.  If it is not,
1333          * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1334          * L1 guests, so it need not worry about its own (L2) guests.
1335          */
1336         data |= ARCH_CAP_PSCHANGE_MC_NO;
1337
1338         /*
1339          * If we're doing cache flushes (either "always" or "cond")
1340          * we will do one whenever the guest does a vmlaunch/vmresume.
1341          * If an outer hypervisor is doing the cache flush for us
1342          * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1343          * capability to the guest too, and if EPT is disabled we're not
1344          * vulnerable.  Overall, only VMENTER_L1D_FLUSH_NEVER will
1345          * require a nested hypervisor to do a flush of its own.
1346          */
1347         if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1348                 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1349
1350         if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1351                 data |= ARCH_CAP_RDCL_NO;
1352         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1353                 data |= ARCH_CAP_SSB_NO;
1354         if (!boot_cpu_has_bug(X86_BUG_MDS))
1355                 data |= ARCH_CAP_MDS_NO;
1356
1357         /*
1358          * On TAA affected systems:
1359          *      - nothing to do if TSX is disabled on the host.
1360          *      - we emulate TSX_CTRL if present on the host.
1361          *        This lets the guest use VERW to clear CPU buffers.
1362          */
1363         if (!boot_cpu_has(X86_FEATURE_RTM))
1364                 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1365         else if (!boot_cpu_has_bug(X86_BUG_TAA))
1366                 data |= ARCH_CAP_TAA_NO;
1367
1368         return data;
1369 }
1370
1371 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1372 {
1373         switch (msr->index) {
1374         case MSR_IA32_ARCH_CAPABILITIES:
1375                 msr->data = kvm_get_arch_capabilities();
1376                 break;
1377         case MSR_IA32_UCODE_REV:
1378                 rdmsrl_safe(msr->index, &msr->data);
1379                 break;
1380         default:
1381                 if (kvm_x86_ops.get_msr_feature(msr))
1382                         return 1;
1383         }
1384         return 0;
1385 }
1386
1387 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1388 {
1389         struct kvm_msr_entry msr;
1390         int r;
1391
1392         msr.index = index;
1393         r = kvm_get_msr_feature(&msr);
1394         if (r)
1395                 return r;
1396
1397         *data = msr.data;
1398
1399         return 0;
1400 }
1401
1402 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1403 {
1404         if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1405                 return false;
1406
1407         if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1408                 return false;
1409
1410         if (efer & (EFER_LME | EFER_LMA) &&
1411             !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1412                 return false;
1413
1414         if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1415                 return false;
1416
1417         return true;
1418
1419 }
1420 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1421 {
1422         if (efer & efer_reserved_bits)
1423                 return false;
1424
1425         return __kvm_valid_efer(vcpu, efer);
1426 }
1427 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1428
1429 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1430 {
1431         u64 old_efer = vcpu->arch.efer;
1432         u64 efer = msr_info->data;
1433
1434         if (efer & efer_reserved_bits)
1435                 return 1;
1436
1437         if (!msr_info->host_initiated) {
1438                 if (!__kvm_valid_efer(vcpu, efer))
1439                         return 1;
1440
1441                 if (is_paging(vcpu) &&
1442                     (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1443                         return 1;
1444         }
1445
1446         efer &= ~EFER_LMA;
1447         efer |= vcpu->arch.efer & EFER_LMA;
1448
1449         kvm_x86_ops.set_efer(vcpu, efer);
1450
1451         /* Update reserved bits */
1452         if ((efer ^ old_efer) & EFER_NX)
1453                 kvm_mmu_reset_context(vcpu);
1454
1455         return 0;
1456 }
1457
1458 void kvm_enable_efer_bits(u64 mask)
1459 {
1460        efer_reserved_bits &= ~mask;
1461 }
1462 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1463
1464 /*
1465  * Write @data into the MSR specified by @index.  Select MSR specific fault
1466  * checks are bypassed if @host_initiated is %true.
1467  * Returns 0 on success, non-0 otherwise.
1468  * Assumes vcpu_load() was already called.
1469  */
1470 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1471                          bool host_initiated)
1472 {
1473         struct msr_data msr;
1474
1475         switch (index) {
1476         case MSR_FS_BASE:
1477         case MSR_GS_BASE:
1478         case MSR_KERNEL_GS_BASE:
1479         case MSR_CSTAR:
1480         case MSR_LSTAR:
1481                 if (is_noncanonical_address(data, vcpu))
1482                         return 1;
1483                 break;
1484         case MSR_IA32_SYSENTER_EIP:
1485         case MSR_IA32_SYSENTER_ESP:
1486                 /*
1487                  * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1488                  * non-canonical address is written on Intel but not on
1489                  * AMD (which ignores the top 32-bits, because it does
1490                  * not implement 64-bit SYSENTER).
1491                  *
1492                  * 64-bit code should hence be able to write a non-canonical
1493                  * value on AMD.  Making the address canonical ensures that
1494                  * vmentry does not fail on Intel after writing a non-canonical
1495                  * value, and that something deterministic happens if the guest
1496                  * invokes 64-bit SYSENTER.
1497                  */
1498                 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1499         }
1500
1501         msr.data = data;
1502         msr.index = index;
1503         msr.host_initiated = host_initiated;
1504
1505         return kvm_x86_ops.set_msr(vcpu, &msr);
1506 }
1507
1508 /*
1509  * Read the MSR specified by @index into @data.  Select MSR specific fault
1510  * checks are bypassed if @host_initiated is %true.
1511  * Returns 0 on success, non-0 otherwise.
1512  * Assumes vcpu_load() was already called.
1513  */
1514 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1515                   bool host_initiated)
1516 {
1517         struct msr_data msr;
1518         int ret;
1519
1520         msr.index = index;
1521         msr.host_initiated = host_initiated;
1522
1523         ret = kvm_x86_ops.get_msr(vcpu, &msr);
1524         if (!ret)
1525                 *data = msr.data;
1526         return ret;
1527 }
1528
1529 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1530 {
1531         return __kvm_get_msr(vcpu, index, data, false);
1532 }
1533 EXPORT_SYMBOL_GPL(kvm_get_msr);
1534
1535 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1536 {
1537         return __kvm_set_msr(vcpu, index, data, false);
1538 }
1539 EXPORT_SYMBOL_GPL(kvm_set_msr);
1540
1541 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1542 {
1543         u32 ecx = kvm_rcx_read(vcpu);
1544         u64 data;
1545
1546         if (kvm_get_msr(vcpu, ecx, &data)) {
1547                 trace_kvm_msr_read_ex(ecx);
1548                 kvm_inject_gp(vcpu, 0);
1549                 return 1;
1550         }
1551
1552         trace_kvm_msr_read(ecx, data);
1553
1554         kvm_rax_write(vcpu, data & -1u);
1555         kvm_rdx_write(vcpu, (data >> 32) & -1u);
1556         return kvm_skip_emulated_instruction(vcpu);
1557 }
1558 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1559
1560 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1561 {
1562         u32 ecx = kvm_rcx_read(vcpu);
1563         u64 data = kvm_read_edx_eax(vcpu);
1564
1565         if (kvm_set_msr(vcpu, ecx, data)) {
1566                 trace_kvm_msr_write_ex(ecx, data);
1567                 kvm_inject_gp(vcpu, 0);
1568                 return 1;
1569         }
1570
1571         trace_kvm_msr_write(ecx, data);
1572         return kvm_skip_emulated_instruction(vcpu);
1573 }
1574 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1575
1576 /*
1577  * The fast path for frequent and performance sensitive wrmsr emulation,
1578  * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1579  * the latency of virtual IPI by avoiding the expensive bits of transitioning
1580  * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1581  * other cases which must be called after interrupts are enabled on the host.
1582  */
1583 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1584 {
1585         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1586                 return 1;
1587
1588         if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1589                 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1590                 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1591                 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1592
1593                 data &= ~(1 << 12);
1594                 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1595                 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1596                 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1597                 trace_kvm_apic_write(APIC_ICR, (u32)data);
1598                 return 0;
1599         }
1600
1601         return 1;
1602 }
1603
1604 enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1605 {
1606         u32 msr = kvm_rcx_read(vcpu);
1607         u64 data;
1608         int ret = 0;
1609
1610         switch (msr) {
1611         case APIC_BASE_MSR + (APIC_ICR >> 4):
1612                 data = kvm_read_edx_eax(vcpu);
1613                 ret = handle_fastpath_set_x2apic_icr_irqoff(vcpu, data);
1614                 break;
1615         default:
1616                 return EXIT_FASTPATH_NONE;
1617         }
1618
1619         if (!ret) {
1620                 trace_kvm_msr_write(msr, data);
1621                 return EXIT_FASTPATH_SKIP_EMUL_INS;
1622         }
1623
1624         return EXIT_FASTPATH_NONE;
1625 }
1626 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1627
1628 /*
1629  * Adapt set_msr() to msr_io()'s calling convention
1630  */
1631 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1632 {
1633         return __kvm_get_msr(vcpu, index, data, true);
1634 }
1635
1636 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1637 {
1638         return __kvm_set_msr(vcpu, index, *data, true);
1639 }
1640
1641 #ifdef CONFIG_X86_64
1642 struct pvclock_clock {
1643         int vclock_mode;
1644         u64 cycle_last;
1645         u64 mask;
1646         u32 mult;
1647         u32 shift;
1648         u64 base_cycles;
1649         u64 offset;
1650 };
1651
1652 struct pvclock_gtod_data {
1653         seqcount_t      seq;
1654
1655         struct pvclock_clock clock; /* extract of a clocksource struct */
1656         struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1657
1658         ktime_t         offs_boot;
1659         u64             wall_time_sec;
1660 };
1661
1662 static struct pvclock_gtod_data pvclock_gtod_data;
1663
1664 static void update_pvclock_gtod(struct timekeeper *tk)
1665 {
1666         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1667
1668         write_seqcount_begin(&vdata->seq);
1669
1670         /* copy pvclock gtod data */
1671         vdata->clock.vclock_mode        = tk->tkr_mono.clock->vdso_clock_mode;
1672         vdata->clock.cycle_last         = tk->tkr_mono.cycle_last;
1673         vdata->clock.mask               = tk->tkr_mono.mask;
1674         vdata->clock.mult               = tk->tkr_mono.mult;
1675         vdata->clock.shift              = tk->tkr_mono.shift;
1676         vdata->clock.base_cycles        = tk->tkr_mono.xtime_nsec;
1677         vdata->clock.offset             = tk->tkr_mono.base;
1678
1679         vdata->raw_clock.vclock_mode    = tk->tkr_raw.clock->vdso_clock_mode;
1680         vdata->raw_clock.cycle_last     = tk->tkr_raw.cycle_last;
1681         vdata->raw_clock.mask           = tk->tkr_raw.mask;
1682         vdata->raw_clock.mult           = tk->tkr_raw.mult;
1683         vdata->raw_clock.shift          = tk->tkr_raw.shift;
1684         vdata->raw_clock.base_cycles    = tk->tkr_raw.xtime_nsec;
1685         vdata->raw_clock.offset         = tk->tkr_raw.base;
1686
1687         vdata->wall_time_sec            = tk->xtime_sec;
1688
1689         vdata->offs_boot                = tk->offs_boot;
1690
1691         write_seqcount_end(&vdata->seq);
1692 }
1693
1694 static s64 get_kvmclock_base_ns(void)
1695 {
1696         /* Count up from boot time, but with the frequency of the raw clock.  */
1697         return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1698 }
1699 #else
1700 static s64 get_kvmclock_base_ns(void)
1701 {
1702         /* Master clock not used, so we can just use CLOCK_BOOTTIME.  */
1703         return ktime_get_boottime_ns();
1704 }
1705 #endif
1706
1707 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1708 {
1709         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1710         kvm_vcpu_kick(vcpu);
1711 }
1712
1713 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1714 {
1715         int version;
1716         int r;
1717         struct pvclock_wall_clock wc;
1718         u64 wall_nsec;
1719
1720         if (!wall_clock)
1721                 return;
1722
1723         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1724         if (r)
1725                 return;
1726
1727         if (version & 1)
1728                 ++version;  /* first time write, random junk */
1729
1730         ++version;
1731
1732         if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1733                 return;
1734
1735         /*
1736          * The guest calculates current wall clock time by adding
1737          * system time (updated by kvm_guest_time_update below) to the
1738          * wall clock specified here.  We do the reverse here.
1739          */
1740         wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1741
1742         wc.nsec = do_div(wall_nsec, 1000000000);
1743         wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1744         wc.version = version;
1745
1746         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1747
1748         version++;
1749         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1750 }
1751
1752 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1753 {
1754         do_shl32_div32(dividend, divisor);
1755         return dividend;
1756 }
1757
1758 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1759                                s8 *pshift, u32 *pmultiplier)
1760 {
1761         uint64_t scaled64;
1762         int32_t  shift = 0;
1763         uint64_t tps64;
1764         uint32_t tps32;
1765
1766         tps64 = base_hz;
1767         scaled64 = scaled_hz;
1768         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1769                 tps64 >>= 1;
1770                 shift--;
1771         }
1772
1773         tps32 = (uint32_t)tps64;
1774         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1775                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1776                         scaled64 >>= 1;
1777                 else
1778                         tps32 <<= 1;
1779                 shift++;
1780         }
1781
1782         *pshift = shift;
1783         *pmultiplier = div_frac(scaled64, tps32);
1784 }
1785
1786 #ifdef CONFIG_X86_64
1787 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1788 #endif
1789
1790 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1791 static unsigned long max_tsc_khz;
1792
1793 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1794 {
1795         u64 v = (u64)khz * (1000000 + ppm);
1796         do_div(v, 1000000);
1797         return v;
1798 }
1799
1800 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1801 {
1802         u64 ratio;
1803
1804         /* Guest TSC same frequency as host TSC? */
1805         if (!scale) {
1806                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1807                 return 0;
1808         }
1809
1810         /* TSC scaling supported? */
1811         if (!kvm_has_tsc_control) {
1812                 if (user_tsc_khz > tsc_khz) {
1813                         vcpu->arch.tsc_catchup = 1;
1814                         vcpu->arch.tsc_always_catchup = 1;
1815                         return 0;
1816                 } else {
1817                         pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1818                         return -1;
1819                 }
1820         }
1821
1822         /* TSC scaling required  - calculate ratio */
1823         ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1824                                 user_tsc_khz, tsc_khz);
1825
1826         if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1827                 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1828                                     user_tsc_khz);
1829                 return -1;
1830         }
1831
1832         vcpu->arch.tsc_scaling_ratio = ratio;
1833         return 0;
1834 }
1835
1836 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1837 {
1838         u32 thresh_lo, thresh_hi;
1839         int use_scaling = 0;
1840
1841         /* tsc_khz can be zero if TSC calibration fails */
1842         if (user_tsc_khz == 0) {
1843                 /* set tsc_scaling_ratio to a safe value */
1844                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1845                 return -1;
1846         }
1847
1848         /* Compute a scale to convert nanoseconds in TSC cycles */
1849         kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1850                            &vcpu->arch.virtual_tsc_shift,
1851                            &vcpu->arch.virtual_tsc_mult);
1852         vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1853
1854         /*
1855          * Compute the variation in TSC rate which is acceptable
1856          * within the range of tolerance and decide if the
1857          * rate being applied is within that bounds of the hardware
1858          * rate.  If so, no scaling or compensation need be done.
1859          */
1860         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1861         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1862         if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1863                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1864                 use_scaling = 1;
1865         }
1866         return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1867 }
1868
1869 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1870 {
1871         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1872                                       vcpu->arch.virtual_tsc_mult,
1873                                       vcpu->arch.virtual_tsc_shift);
1874         tsc += vcpu->arch.this_tsc_write;
1875         return tsc;
1876 }
1877
1878 static inline int gtod_is_based_on_tsc(int mode)
1879 {
1880         return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
1881 }
1882
1883 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1884 {
1885 #ifdef CONFIG_X86_64
1886         bool vcpus_matched;
1887         struct kvm_arch *ka = &vcpu->kvm->arch;
1888         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1889
1890         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1891                          atomic_read(&vcpu->kvm->online_vcpus));
1892
1893         /*
1894          * Once the masterclock is enabled, always perform request in
1895          * order to update it.
1896          *
1897          * In order to enable masterclock, the host clocksource must be TSC
1898          * and the vcpus need to have matched TSCs.  When that happens,
1899          * perform request to enable masterclock.
1900          */
1901         if (ka->use_master_clock ||
1902             (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1903                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1904
1905         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1906                             atomic_read(&vcpu->kvm->online_vcpus),
1907                             ka->use_master_clock, gtod->clock.vclock_mode);
1908 #endif
1909 }
1910
1911 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1912 {
1913         u64 curr_offset = vcpu->arch.l1_tsc_offset;
1914         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1915 }
1916
1917 /*
1918  * Multiply tsc by a fixed point number represented by ratio.
1919  *
1920  * The most significant 64-N bits (mult) of ratio represent the
1921  * integral part of the fixed point number; the remaining N bits
1922  * (frac) represent the fractional part, ie. ratio represents a fixed
1923  * point number (mult + frac * 2^(-N)).
1924  *
1925  * N equals to kvm_tsc_scaling_ratio_frac_bits.
1926  */
1927 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1928 {
1929         return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1930 }
1931
1932 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1933 {
1934         u64 _tsc = tsc;
1935         u64 ratio = vcpu->arch.tsc_scaling_ratio;
1936
1937         if (ratio != kvm_default_tsc_scaling_ratio)
1938                 _tsc = __scale_tsc(ratio, tsc);
1939
1940         return _tsc;
1941 }
1942 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1943
1944 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1945 {
1946         u64 tsc;
1947
1948         tsc = kvm_scale_tsc(vcpu, rdtsc());
1949
1950         return target_tsc - tsc;
1951 }
1952
1953 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1954 {
1955         return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1956 }
1957 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1958
1959 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1960 {
1961         vcpu->arch.l1_tsc_offset = offset;
1962         vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset);
1963 }
1964
1965 static inline bool kvm_check_tsc_unstable(void)
1966 {
1967 #ifdef CONFIG_X86_64
1968         /*
1969          * TSC is marked unstable when we're running on Hyper-V,
1970          * 'TSC page' clocksource is good.
1971          */
1972         if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
1973                 return false;
1974 #endif
1975         return check_tsc_unstable();
1976 }
1977
1978 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1979 {
1980         struct kvm *kvm = vcpu->kvm;
1981         u64 offset, ns, elapsed;
1982         unsigned long flags;
1983         bool matched;
1984         bool already_matched;
1985         u64 data = msr->data;
1986         bool synchronizing = false;
1987
1988         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1989         offset = kvm_compute_tsc_offset(vcpu, data);
1990         ns = get_kvmclock_base_ns();
1991         elapsed = ns - kvm->arch.last_tsc_nsec;
1992
1993         if (vcpu->arch.virtual_tsc_khz) {
1994                 if (data == 0 && msr->host_initiated) {
1995                         /*
1996                          * detection of vcpu initialization -- need to sync
1997                          * with other vCPUs. This particularly helps to keep
1998                          * kvm_clock stable after CPU hotplug
1999                          */
2000                         synchronizing = true;
2001                 } else {
2002                         u64 tsc_exp = kvm->arch.last_tsc_write +
2003                                                 nsec_to_cycles(vcpu, elapsed);
2004                         u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2005                         /*
2006                          * Special case: TSC write with a small delta (1 second)
2007                          * of virtual cycle time against real time is
2008                          * interpreted as an attempt to synchronize the CPU.
2009                          */
2010                         synchronizing = data < tsc_exp + tsc_hz &&
2011                                         data + tsc_hz > tsc_exp;
2012                 }
2013         }
2014
2015         /*
2016          * For a reliable TSC, we can match TSC offsets, and for an unstable
2017          * TSC, we add elapsed time in this computation.  We could let the
2018          * compensation code attempt to catch up if we fall behind, but
2019          * it's better to try to match offsets from the beginning.
2020          */
2021         if (synchronizing &&
2022             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2023                 if (!kvm_check_tsc_unstable()) {
2024                         offset = kvm->arch.cur_tsc_offset;
2025                 } else {
2026                         u64 delta = nsec_to_cycles(vcpu, elapsed);
2027                         data += delta;
2028                         offset = kvm_compute_tsc_offset(vcpu, data);
2029                 }
2030                 matched = true;
2031                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2032         } else {
2033                 /*
2034                  * We split periods of matched TSC writes into generations.
2035                  * For each generation, we track the original measured
2036                  * nanosecond time, offset, and write, so if TSCs are in
2037                  * sync, we can match exact offset, and if not, we can match
2038                  * exact software computation in compute_guest_tsc()
2039                  *
2040                  * These values are tracked in kvm->arch.cur_xxx variables.
2041                  */
2042                 kvm->arch.cur_tsc_generation++;
2043                 kvm->arch.cur_tsc_nsec = ns;
2044                 kvm->arch.cur_tsc_write = data;
2045                 kvm->arch.cur_tsc_offset = offset;
2046                 matched = false;
2047         }
2048
2049         /*
2050          * We also track th most recent recorded KHZ, write and time to
2051          * allow the matching interval to be extended at each write.
2052          */
2053         kvm->arch.last_tsc_nsec = ns;
2054         kvm->arch.last_tsc_write = data;
2055         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2056
2057         vcpu->arch.last_guest_tsc = data;
2058
2059         /* Keep track of which generation this VCPU has synchronized to */
2060         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2061         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2062         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2063
2064         if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
2065                 update_ia32_tsc_adjust_msr(vcpu, offset);
2066
2067         kvm_vcpu_write_tsc_offset(vcpu, offset);
2068         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2069
2070         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2071         if (!matched) {
2072                 kvm->arch.nr_vcpus_matched_tsc = 0;
2073         } else if (!already_matched) {
2074                 kvm->arch.nr_vcpus_matched_tsc++;
2075         }
2076
2077         kvm_track_tsc_matching(vcpu);
2078         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2079 }
2080
2081 EXPORT_SYMBOL_GPL(kvm_write_tsc);
2082
2083 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2084                                            s64 adjustment)
2085 {
2086         u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2087         kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2088 }
2089
2090 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2091 {
2092         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2093                 WARN_ON(adjustment < 0);
2094         adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2095         adjust_tsc_offset_guest(vcpu, adjustment);
2096 }
2097
2098 #ifdef CONFIG_X86_64
2099
2100 static u64 read_tsc(void)
2101 {
2102         u64 ret = (u64)rdtsc_ordered();
2103         u64 last = pvclock_gtod_data.clock.cycle_last;
2104
2105         if (likely(ret >= last))
2106                 return ret;
2107
2108         /*
2109          * GCC likes to generate cmov here, but this branch is extremely
2110          * predictable (it's just a function of time and the likely is
2111          * very likely) and there's a data dependence, so force GCC
2112          * to generate a branch instead.  I don't barrier() because
2113          * we don't actually need a barrier, and if this function
2114          * ever gets inlined it will generate worse code.
2115          */
2116         asm volatile ("");
2117         return last;
2118 }
2119
2120 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2121                           int *mode)
2122 {
2123         long v;
2124         u64 tsc_pg_val;
2125
2126         switch (clock->vclock_mode) {
2127         case VDSO_CLOCKMODE_HVCLOCK:
2128                 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2129                                                   tsc_timestamp);
2130                 if (tsc_pg_val != U64_MAX) {
2131                         /* TSC page valid */
2132                         *mode = VDSO_CLOCKMODE_HVCLOCK;
2133                         v = (tsc_pg_val - clock->cycle_last) &
2134                                 clock->mask;
2135                 } else {
2136                         /* TSC page invalid */
2137                         *mode = VDSO_CLOCKMODE_NONE;
2138                 }
2139                 break;
2140         case VDSO_CLOCKMODE_TSC:
2141                 *mode = VDSO_CLOCKMODE_TSC;
2142                 *tsc_timestamp = read_tsc();
2143                 v = (*tsc_timestamp - clock->cycle_last) &
2144                         clock->mask;
2145                 break;
2146         default:
2147                 *mode = VDSO_CLOCKMODE_NONE;
2148         }
2149
2150         if (*mode == VDSO_CLOCKMODE_NONE)
2151                 *tsc_timestamp = v = 0;
2152
2153         return v * clock->mult;
2154 }
2155
2156 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2157 {
2158         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2159         unsigned long seq;
2160         int mode;
2161         u64 ns;
2162
2163         do {
2164                 seq = read_seqcount_begin(&gtod->seq);
2165                 ns = gtod->raw_clock.base_cycles;
2166                 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2167                 ns >>= gtod->raw_clock.shift;
2168                 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2169         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2170         *t = ns;
2171
2172         return mode;
2173 }
2174
2175 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2176 {
2177         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2178         unsigned long seq;
2179         int mode;
2180         u64 ns;
2181
2182         do {
2183                 seq = read_seqcount_begin(&gtod->seq);
2184                 ts->tv_sec = gtod->wall_time_sec;
2185                 ns = gtod->clock.base_cycles;
2186                 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2187                 ns >>= gtod->clock.shift;
2188         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2189
2190         ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2191         ts->tv_nsec = ns;
2192
2193         return mode;
2194 }
2195
2196 /* returns true if host is using TSC based clocksource */
2197 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2198 {
2199         /* checked again under seqlock below */
2200         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2201                 return false;
2202
2203         return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2204                                                       tsc_timestamp));
2205 }
2206
2207 /* returns true if host is using TSC based clocksource */
2208 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2209                                            u64 *tsc_timestamp)
2210 {
2211         /* checked again under seqlock below */
2212         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2213                 return false;
2214
2215         return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2216 }
2217 #endif
2218
2219 /*
2220  *
2221  * Assuming a stable TSC across physical CPUS, and a stable TSC
2222  * across virtual CPUs, the following condition is possible.
2223  * Each numbered line represents an event visible to both
2224  * CPUs at the next numbered event.
2225  *
2226  * "timespecX" represents host monotonic time. "tscX" represents
2227  * RDTSC value.
2228  *
2229  *              VCPU0 on CPU0           |       VCPU1 on CPU1
2230  *
2231  * 1.  read timespec0,tsc0
2232  * 2.                                   | timespec1 = timespec0 + N
2233  *                                      | tsc1 = tsc0 + M
2234  * 3. transition to guest               | transition to guest
2235  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2236  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
2237  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2238  *
2239  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2240  *
2241  *      - ret0 < ret1
2242  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2243  *              ...
2244  *      - 0 < N - M => M < N
2245  *
2246  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2247  * always the case (the difference between two distinct xtime instances
2248  * might be smaller then the difference between corresponding TSC reads,
2249  * when updating guest vcpus pvclock areas).
2250  *
2251  * To avoid that problem, do not allow visibility of distinct
2252  * system_timestamp/tsc_timestamp values simultaneously: use a master
2253  * copy of host monotonic time values. Update that master copy
2254  * in lockstep.
2255  *
2256  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2257  *
2258  */
2259
2260 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2261 {
2262 #ifdef CONFIG_X86_64
2263         struct kvm_arch *ka = &kvm->arch;
2264         int vclock_mode;
2265         bool host_tsc_clocksource, vcpus_matched;
2266
2267         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2268                         atomic_read(&kvm->online_vcpus));
2269
2270         /*
2271          * If the host uses TSC clock, then passthrough TSC as stable
2272          * to the guest.
2273          */
2274         host_tsc_clocksource = kvm_get_time_and_clockread(
2275                                         &ka->master_kernel_ns,
2276                                         &ka->master_cycle_now);
2277
2278         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2279                                 && !ka->backwards_tsc_observed
2280                                 && !ka->boot_vcpu_runs_old_kvmclock;
2281
2282         if (ka->use_master_clock)
2283                 atomic_set(&kvm_guest_has_master_clock, 1);
2284
2285         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2286         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2287                                         vcpus_matched);
2288 #endif
2289 }
2290
2291 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2292 {
2293         kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2294 }
2295
2296 static void kvm_gen_update_masterclock(struct kvm *kvm)
2297 {
2298 #ifdef CONFIG_X86_64
2299         int i;
2300         struct kvm_vcpu *vcpu;
2301         struct kvm_arch *ka = &kvm->arch;
2302
2303         spin_lock(&ka->pvclock_gtod_sync_lock);
2304         kvm_make_mclock_inprogress_request(kvm);
2305         /* no guest entries from this point */
2306         pvclock_update_vm_gtod_copy(kvm);
2307
2308         kvm_for_each_vcpu(i, vcpu, kvm)
2309                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2310
2311         /* guest entries allowed */
2312         kvm_for_each_vcpu(i, vcpu, kvm)
2313                 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2314
2315         spin_unlock(&ka->pvclock_gtod_sync_lock);
2316 #endif
2317 }
2318
2319 u64 get_kvmclock_ns(struct kvm *kvm)
2320 {
2321         struct kvm_arch *ka = &kvm->arch;
2322         struct pvclock_vcpu_time_info hv_clock;
2323         u64 ret;
2324
2325         spin_lock(&ka->pvclock_gtod_sync_lock);
2326         if (!ka->use_master_clock) {
2327                 spin_unlock(&ka->pvclock_gtod_sync_lock);
2328                 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2329         }
2330
2331         hv_clock.tsc_timestamp = ka->master_cycle_now;
2332         hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2333         spin_unlock(&ka->pvclock_gtod_sync_lock);
2334
2335         /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2336         get_cpu();
2337
2338         if (__this_cpu_read(cpu_tsc_khz)) {
2339                 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2340                                    &hv_clock.tsc_shift,
2341                                    &hv_clock.tsc_to_system_mul);
2342                 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2343         } else
2344                 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2345
2346         put_cpu();
2347
2348         return ret;
2349 }
2350
2351 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2352 {
2353         struct kvm_vcpu_arch *vcpu = &v->arch;
2354         struct pvclock_vcpu_time_info guest_hv_clock;
2355
2356         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2357                 &guest_hv_clock, sizeof(guest_hv_clock))))
2358                 return;
2359
2360         /* This VCPU is paused, but it's legal for a guest to read another
2361          * VCPU's kvmclock, so we really have to follow the specification where
2362          * it says that version is odd if data is being modified, and even after
2363          * it is consistent.
2364          *
2365          * Version field updates must be kept separate.  This is because
2366          * kvm_write_guest_cached might use a "rep movs" instruction, and
2367          * writes within a string instruction are weakly ordered.  So there
2368          * are three writes overall.
2369          *
2370          * As a small optimization, only write the version field in the first
2371          * and third write.  The vcpu->pv_time cache is still valid, because the
2372          * version field is the first in the struct.
2373          */
2374         BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2375
2376         if (guest_hv_clock.version & 1)
2377                 ++guest_hv_clock.version;  /* first time write, random junk */
2378
2379         vcpu->hv_clock.version = guest_hv_clock.version + 1;
2380         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2381                                 &vcpu->hv_clock,
2382                                 sizeof(vcpu->hv_clock.version));
2383
2384         smp_wmb();
2385
2386         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2387         vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2388
2389         if (vcpu->pvclock_set_guest_stopped_request) {
2390                 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2391                 vcpu->pvclock_set_guest_stopped_request = false;
2392         }
2393
2394         trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2395
2396         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2397                                 &vcpu->hv_clock,
2398                                 sizeof(vcpu->hv_clock));
2399
2400         smp_wmb();
2401
2402         vcpu->hv_clock.version++;
2403         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2404                                 &vcpu->hv_clock,
2405                                 sizeof(vcpu->hv_clock.version));
2406 }
2407
2408 static int kvm_guest_time_update(struct kvm_vcpu *v)
2409 {
2410         unsigned long flags, tgt_tsc_khz;
2411         struct kvm_vcpu_arch *vcpu = &v->arch;
2412         struct kvm_arch *ka = &v->kvm->arch;
2413         s64 kernel_ns;
2414         u64 tsc_timestamp, host_tsc;
2415         u8 pvclock_flags;
2416         bool use_master_clock;
2417
2418         kernel_ns = 0;
2419         host_tsc = 0;
2420
2421         /*
2422          * If the host uses TSC clock, then passthrough TSC as stable
2423          * to the guest.
2424          */
2425         spin_lock(&ka->pvclock_gtod_sync_lock);
2426         use_master_clock = ka->use_master_clock;
2427         if (use_master_clock) {
2428                 host_tsc = ka->master_cycle_now;
2429                 kernel_ns = ka->master_kernel_ns;
2430         }
2431         spin_unlock(&ka->pvclock_gtod_sync_lock);
2432
2433         /* Keep irq disabled to prevent changes to the clock */
2434         local_irq_save(flags);
2435         tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2436         if (unlikely(tgt_tsc_khz == 0)) {
2437                 local_irq_restore(flags);
2438                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2439                 return 1;
2440         }
2441         if (!use_master_clock) {
2442                 host_tsc = rdtsc();
2443                 kernel_ns = get_kvmclock_base_ns();
2444         }
2445
2446         tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2447
2448         /*
2449          * We may have to catch up the TSC to match elapsed wall clock
2450          * time for two reasons, even if kvmclock is used.
2451          *   1) CPU could have been running below the maximum TSC rate
2452          *   2) Broken TSC compensation resets the base at each VCPU
2453          *      entry to avoid unknown leaps of TSC even when running
2454          *      again on the same CPU.  This may cause apparent elapsed
2455          *      time to disappear, and the guest to stand still or run
2456          *      very slowly.
2457          */
2458         if (vcpu->tsc_catchup) {
2459                 u64 tsc = compute_guest_tsc(v, kernel_ns);
2460                 if (tsc > tsc_timestamp) {
2461                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2462                         tsc_timestamp = tsc;
2463                 }
2464         }
2465
2466         local_irq_restore(flags);
2467
2468         /* With all the info we got, fill in the values */
2469
2470         if (kvm_has_tsc_control)
2471                 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2472
2473         if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2474                 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2475                                    &vcpu->hv_clock.tsc_shift,
2476                                    &vcpu->hv_clock.tsc_to_system_mul);
2477                 vcpu->hw_tsc_khz = tgt_tsc_khz;
2478         }
2479
2480         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2481         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2482         vcpu->last_guest_tsc = tsc_timestamp;
2483
2484         /* If the host uses TSC clocksource, then it is stable */
2485         pvclock_flags = 0;
2486         if (use_master_clock)
2487                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2488
2489         vcpu->hv_clock.flags = pvclock_flags;
2490
2491         if (vcpu->pv_time_enabled)
2492                 kvm_setup_pvclock_page(v);
2493         if (v == kvm_get_vcpu(v->kvm, 0))
2494                 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2495         return 0;
2496 }
2497
2498 /*
2499  * kvmclock updates which are isolated to a given vcpu, such as
2500  * vcpu->cpu migration, should not allow system_timestamp from
2501  * the rest of the vcpus to remain static. Otherwise ntp frequency
2502  * correction applies to one vcpu's system_timestamp but not
2503  * the others.
2504  *
2505  * So in those cases, request a kvmclock update for all vcpus.
2506  * We need to rate-limit these requests though, as they can
2507  * considerably slow guests that have a large number of vcpus.
2508  * The time for a remote vcpu to update its kvmclock is bound
2509  * by the delay we use to rate-limit the updates.
2510  */
2511
2512 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2513
2514 static void kvmclock_update_fn(struct work_struct *work)
2515 {
2516         int i;
2517         struct delayed_work *dwork = to_delayed_work(work);
2518         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2519                                            kvmclock_update_work);
2520         struct kvm *kvm = container_of(ka, struct kvm, arch);
2521         struct kvm_vcpu *vcpu;
2522
2523         kvm_for_each_vcpu(i, vcpu, kvm) {
2524                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2525                 kvm_vcpu_kick(vcpu);
2526         }
2527 }
2528
2529 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2530 {
2531         struct kvm *kvm = v->kvm;
2532
2533         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2534         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2535                                         KVMCLOCK_UPDATE_DELAY);
2536 }
2537
2538 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2539
2540 static void kvmclock_sync_fn(struct work_struct *work)
2541 {
2542         struct delayed_work *dwork = to_delayed_work(work);
2543         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2544                                            kvmclock_sync_work);
2545         struct kvm *kvm = container_of(ka, struct kvm, arch);
2546
2547         if (!kvmclock_periodic_sync)
2548                 return;
2549
2550         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2551         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2552                                         KVMCLOCK_SYNC_PERIOD);
2553 }
2554
2555 /*
2556  * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2557  */
2558 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2559 {
2560         /* McStatusWrEn enabled? */
2561         if (guest_cpuid_is_amd_or_hygon(vcpu))
2562                 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2563
2564         return false;
2565 }
2566
2567 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2568 {
2569         u64 mcg_cap = vcpu->arch.mcg_cap;
2570         unsigned bank_num = mcg_cap & 0xff;
2571         u32 msr = msr_info->index;
2572         u64 data = msr_info->data;
2573
2574         switch (msr) {
2575         case MSR_IA32_MCG_STATUS:
2576                 vcpu->arch.mcg_status = data;
2577                 break;
2578         case MSR_IA32_MCG_CTL:
2579                 if (!(mcg_cap & MCG_CTL_P) &&
2580                     (data || !msr_info->host_initiated))
2581                         return 1;
2582                 if (data != 0 && data != ~(u64)0)
2583                         return 1;
2584                 vcpu->arch.mcg_ctl = data;
2585                 break;
2586         default:
2587                 if (msr >= MSR_IA32_MC0_CTL &&
2588                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2589                         u32 offset = array_index_nospec(
2590                                 msr - MSR_IA32_MC0_CTL,
2591                                 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2592
2593                         /* only 0 or all 1s can be written to IA32_MCi_CTL
2594                          * some Linux kernels though clear bit 10 in bank 4 to
2595                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2596                          * this to avoid an uncatched #GP in the guest
2597                          */
2598                         if ((offset & 0x3) == 0 &&
2599                             data != 0 && (data | (1 << 10)) != ~(u64)0)
2600                                 return -1;
2601
2602                         /* MCi_STATUS */
2603                         if (!msr_info->host_initiated &&
2604                             (offset & 0x3) == 1 && data != 0) {
2605                                 if (!can_set_mci_status(vcpu))
2606                                         return -1;
2607                         }
2608
2609                         vcpu->arch.mce_banks[offset] = data;
2610                         break;
2611                 }
2612                 return 1;
2613         }
2614         return 0;
2615 }
2616
2617 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2618 {
2619         struct kvm *kvm = vcpu->kvm;
2620         int lm = is_long_mode(vcpu);
2621         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2622                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2623         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2624                 : kvm->arch.xen_hvm_config.blob_size_32;
2625         u32 page_num = data & ~PAGE_MASK;
2626         u64 page_addr = data & PAGE_MASK;
2627         u8 *page;
2628         int r;
2629
2630         r = -E2BIG;
2631         if (page_num >= blob_size)
2632                 goto out;
2633         r = -ENOMEM;
2634         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2635         if (IS_ERR(page)) {
2636                 r = PTR_ERR(page);
2637                 goto out;
2638         }
2639         if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2640                 goto out_free;
2641         r = 0;
2642 out_free:
2643         kfree(page);
2644 out:
2645         return r;
2646 }
2647
2648 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2649 {
2650         gpa_t gpa = data & ~0x3f;
2651
2652         /* Bits 3:5 are reserved, Should be zero */
2653         if (data & 0x38)
2654                 return 1;
2655
2656         vcpu->arch.apf.msr_val = data;
2657
2658         if (!(data & KVM_ASYNC_PF_ENABLED)) {
2659                 kvm_clear_async_pf_completion_queue(vcpu);
2660                 kvm_async_pf_hash_reset(vcpu);
2661                 return 0;
2662         }
2663
2664         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2665                                         sizeof(u32)))
2666                 return 1;
2667
2668         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2669         vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2670         kvm_async_pf_wakeup_all(vcpu);
2671         return 0;
2672 }
2673
2674 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2675 {
2676         vcpu->arch.pv_time_enabled = false;
2677         vcpu->arch.time = 0;
2678 }
2679
2680 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
2681 {
2682         ++vcpu->stat.tlb_flush;
2683         kvm_x86_ops.tlb_flush_all(vcpu);
2684 }
2685
2686 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
2687 {
2688         ++vcpu->stat.tlb_flush;
2689         kvm_x86_ops.tlb_flush_guest(vcpu);
2690 }
2691
2692 static void record_steal_time(struct kvm_vcpu *vcpu)
2693 {
2694         struct kvm_host_map map;
2695         struct kvm_steal_time *st;
2696
2697         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2698                 return;
2699
2700         /* -EAGAIN is returned in atomic context so we can just return. */
2701         if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2702                         &map, &vcpu->arch.st.cache, false))
2703                 return;
2704
2705         st = map.hva +
2706                 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2707
2708         /*
2709          * Doing a TLB flush here, on the guest's behalf, can avoid
2710          * expensive IPIs.
2711          */
2712         trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2713                 st->preempted & KVM_VCPU_FLUSH_TLB);
2714         if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2715                 kvm_vcpu_flush_tlb_guest(vcpu);
2716
2717         vcpu->arch.st.preempted = 0;
2718
2719         if (st->version & 1)
2720                 st->version += 1;  /* first time write, random junk */
2721
2722         st->version += 1;
2723
2724         smp_wmb();
2725
2726         st->steal += current->sched_info.run_delay -
2727                 vcpu->arch.st.last_steal;
2728         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2729
2730         smp_wmb();
2731
2732         st->version += 1;
2733
2734         kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2735 }
2736
2737 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2738 {
2739         bool pr = false;
2740         u32 msr = msr_info->index;
2741         u64 data = msr_info->data;
2742
2743         switch (msr) {
2744         case MSR_AMD64_NB_CFG:
2745         case MSR_IA32_UCODE_WRITE:
2746         case MSR_VM_HSAVE_PA:
2747         case MSR_AMD64_PATCH_LOADER:
2748         case MSR_AMD64_BU_CFG2:
2749         case MSR_AMD64_DC_CFG:
2750         case MSR_F15H_EX_CFG:
2751                 break;
2752
2753         case MSR_IA32_UCODE_REV:
2754                 if (msr_info->host_initiated)
2755                         vcpu->arch.microcode_version = data;
2756                 break;
2757         case MSR_IA32_ARCH_CAPABILITIES:
2758                 if (!msr_info->host_initiated)
2759                         return 1;
2760                 vcpu->arch.arch_capabilities = data;
2761                 break;
2762         case MSR_EFER:
2763                 return set_efer(vcpu, msr_info);
2764         case MSR_K7_HWCR:
2765                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2766                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2767                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2768
2769                 /* Handle McStatusWrEn */
2770                 if (data == BIT_ULL(18)) {
2771                         vcpu->arch.msr_hwcr = data;
2772                 } else if (data != 0) {
2773                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2774                                     data);
2775                         return 1;
2776                 }
2777                 break;
2778         case MSR_FAM10H_MMIO_CONF_BASE:
2779                 if (data != 0) {
2780                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2781                                     "0x%llx\n", data);
2782                         return 1;
2783                 }
2784                 break;
2785         case MSR_IA32_DEBUGCTLMSR:
2786                 if (!data) {
2787                         /* We support the non-activated case already */
2788                         break;
2789                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2790                         /* Values other than LBR and BTF are vendor-specific,
2791                            thus reserved and should throw a #GP */
2792                         return 1;
2793                 }
2794                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2795                             __func__, data);
2796                 break;
2797         case 0x200 ... 0x2ff:
2798                 return kvm_mtrr_set_msr(vcpu, msr, data);
2799         case MSR_IA32_APICBASE:
2800                 return kvm_set_apic_base(vcpu, msr_info);
2801         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2802                 return kvm_x2apic_msr_write(vcpu, msr, data);
2803         case MSR_IA32_TSCDEADLINE:
2804                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2805                 break;
2806         case MSR_IA32_TSC_ADJUST:
2807                 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2808                         if (!msr_info->host_initiated) {
2809                                 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2810                                 adjust_tsc_offset_guest(vcpu, adj);
2811                         }
2812                         vcpu->arch.ia32_tsc_adjust_msr = data;
2813                 }
2814                 break;
2815         case MSR_IA32_MISC_ENABLE:
2816                 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2817                     ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2818                         if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2819                                 return 1;
2820                         vcpu->arch.ia32_misc_enable_msr = data;
2821                         kvm_update_cpuid(vcpu);
2822                 } else {
2823                         vcpu->arch.ia32_misc_enable_msr = data;
2824                 }
2825                 break;
2826         case MSR_IA32_SMBASE:
2827                 if (!msr_info->host_initiated)
2828                         return 1;
2829                 vcpu->arch.smbase = data;
2830                 break;
2831         case MSR_IA32_POWER_CTL:
2832                 vcpu->arch.msr_ia32_power_ctl = data;
2833                 break;
2834         case MSR_IA32_TSC:
2835                 kvm_write_tsc(vcpu, msr_info);
2836                 break;
2837         case MSR_IA32_XSS:
2838                 if (!msr_info->host_initiated &&
2839                     !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
2840                         return 1;
2841                 /*
2842                  * KVM supports exposing PT to the guest, but does not support
2843                  * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
2844                  * XSAVES/XRSTORS to save/restore PT MSRs.
2845                  */
2846                 if (data & ~supported_xss)
2847                         return 1;
2848                 vcpu->arch.ia32_xss = data;
2849                 break;
2850         case MSR_SMI_COUNT:
2851                 if (!msr_info->host_initiated)
2852                         return 1;
2853                 vcpu->arch.smi_count = data;
2854                 break;
2855         case MSR_KVM_WALL_CLOCK_NEW:
2856         case MSR_KVM_WALL_CLOCK:
2857                 vcpu->kvm->arch.wall_clock = data;
2858                 kvm_write_wall_clock(vcpu->kvm, data);
2859                 break;
2860         case MSR_KVM_SYSTEM_TIME_NEW:
2861         case MSR_KVM_SYSTEM_TIME: {
2862                 struct kvm_arch *ka = &vcpu->kvm->arch;
2863
2864                 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2865                         bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2866
2867                         if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2868                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2869
2870                         ka->boot_vcpu_runs_old_kvmclock = tmp;
2871                 }
2872
2873                 vcpu->arch.time = data;
2874                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2875
2876                 /* we verify if the enable bit is set... */
2877                 vcpu->arch.pv_time_enabled = false;
2878                 if (!(data & 1))
2879                         break;
2880
2881                 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2882                      &vcpu->arch.pv_time, data & ~1ULL,
2883                      sizeof(struct pvclock_vcpu_time_info)))
2884                         vcpu->arch.pv_time_enabled = true;
2885
2886                 break;
2887         }
2888         case MSR_KVM_ASYNC_PF_EN:
2889                 if (kvm_pv_enable_async_pf(vcpu, data))
2890                         return 1;
2891                 break;
2892         case MSR_KVM_STEAL_TIME:
2893
2894                 if (unlikely(!sched_info_on()))
2895                         return 1;
2896
2897                 if (data & KVM_STEAL_RESERVED_MASK)
2898                         return 1;
2899
2900                 vcpu->arch.st.msr_val = data;
2901
2902                 if (!(data & KVM_MSR_ENABLED))
2903                         break;
2904
2905                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2906
2907                 break;
2908         case MSR_KVM_PV_EOI_EN:
2909                 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2910                         return 1;
2911                 break;
2912
2913         case MSR_KVM_POLL_CONTROL:
2914                 /* only enable bit supported */
2915                 if (data & (-1ULL << 1))
2916                         return 1;
2917
2918                 vcpu->arch.msr_kvm_poll_control = data;
2919                 break;
2920
2921         case MSR_IA32_MCG_CTL:
2922         case MSR_IA32_MCG_STATUS:
2923         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2924                 return set_msr_mce(vcpu, msr_info);
2925
2926         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2927         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2928                 pr = true; /* fall through */
2929         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2930         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2931                 if (kvm_pmu_is_valid_msr(vcpu, msr))
2932                         return kvm_pmu_set_msr(vcpu, msr_info);
2933
2934                 if (pr || data != 0)
2935                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2936                                     "0x%x data 0x%llx\n", msr, data);
2937                 break;
2938         case MSR_K7_CLK_CTL:
2939                 /*
2940                  * Ignore all writes to this no longer documented MSR.
2941                  * Writes are only relevant for old K7 processors,
2942                  * all pre-dating SVM, but a recommended workaround from
2943                  * AMD for these chips. It is possible to specify the
2944                  * affected processor models on the command line, hence
2945                  * the need to ignore the workaround.
2946                  */
2947                 break;
2948         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2949         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2950         case HV_X64_MSR_CRASH_CTL:
2951         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2952         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2953         case HV_X64_MSR_TSC_EMULATION_CONTROL:
2954         case HV_X64_MSR_TSC_EMULATION_STATUS:
2955                 return kvm_hv_set_msr_common(vcpu, msr, data,
2956                                              msr_info->host_initiated);
2957         case MSR_IA32_BBL_CR_CTL3:
2958                 /* Drop writes to this legacy MSR -- see rdmsr
2959                  * counterpart for further detail.
2960                  */
2961                 if (report_ignored_msrs)
2962                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2963                                 msr, data);
2964                 break;
2965         case MSR_AMD64_OSVW_ID_LENGTH:
2966                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2967                         return 1;
2968                 vcpu->arch.osvw.length = data;
2969                 break;
2970         case MSR_AMD64_OSVW_STATUS:
2971                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2972                         return 1;
2973                 vcpu->arch.osvw.status = data;
2974                 break;
2975         case MSR_PLATFORM_INFO:
2976                 if (!msr_info->host_initiated ||
2977                     (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2978                      cpuid_fault_enabled(vcpu)))
2979                         return 1;
2980                 vcpu->arch.msr_platform_info = data;
2981                 break;
2982         case MSR_MISC_FEATURES_ENABLES:
2983                 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2984                     (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2985                      !supports_cpuid_fault(vcpu)))
2986                         return 1;
2987                 vcpu->arch.msr_misc_features_enables = data;
2988                 break;
2989         default:
2990                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2991                         return xen_hvm_config(vcpu, data);
2992                 if (kvm_pmu_is_valid_msr(vcpu, msr))
2993                         return kvm_pmu_set_msr(vcpu, msr_info);
2994                 if (!ignore_msrs) {
2995                         vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2996                                     msr, data);
2997                         return 1;
2998                 } else {
2999                         if (report_ignored_msrs)
3000                                 vcpu_unimpl(vcpu,
3001                                         "ignored wrmsr: 0x%x data 0x%llx\n",
3002                                         msr, data);
3003                         break;
3004                 }
3005         }
3006         return 0;
3007 }
3008 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3009
3010 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3011 {
3012         u64 data;
3013         u64 mcg_cap = vcpu->arch.mcg_cap;
3014         unsigned bank_num = mcg_cap & 0xff;
3015
3016         switch (msr) {
3017         case MSR_IA32_P5_MC_ADDR:
3018         case MSR_IA32_P5_MC_TYPE:
3019                 data = 0;
3020                 break;
3021         case MSR_IA32_MCG_CAP:
3022                 data = vcpu->arch.mcg_cap;
3023                 break;
3024         case MSR_IA32_MCG_CTL:
3025                 if (!(mcg_cap & MCG_CTL_P) && !host)
3026                         return 1;
3027                 data = vcpu->arch.mcg_ctl;
3028                 break;
3029         case MSR_IA32_MCG_STATUS:
3030                 data = vcpu->arch.mcg_status;
3031                 break;
3032         default:
3033                 if (msr >= MSR_IA32_MC0_CTL &&
3034                     msr < MSR_IA32_MCx_CTL(bank_num)) {
3035                         u32 offset = array_index_nospec(
3036                                 msr - MSR_IA32_MC0_CTL,
3037                                 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3038
3039                         data = vcpu->arch.mce_banks[offset];
3040                         break;
3041                 }
3042                 return 1;
3043         }
3044         *pdata = data;
3045         return 0;
3046 }
3047
3048 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3049 {
3050         switch (msr_info->index) {
3051         case MSR_IA32_PLATFORM_ID:
3052         case MSR_IA32_EBL_CR_POWERON:
3053         case MSR_IA32_DEBUGCTLMSR:
3054         case MSR_IA32_LASTBRANCHFROMIP:
3055         case MSR_IA32_LASTBRANCHTOIP:
3056         case MSR_IA32_LASTINTFROMIP:
3057         case MSR_IA32_LASTINTTOIP:
3058         case MSR_K8_SYSCFG:
3059         case MSR_K8_TSEG_ADDR:
3060         case MSR_K8_TSEG_MASK:
3061         case MSR_VM_HSAVE_PA:
3062         case MSR_K8_INT_PENDING_MSG:
3063         case MSR_AMD64_NB_CFG:
3064         case MSR_FAM10H_MMIO_CONF_BASE:
3065         case MSR_AMD64_BU_CFG2:
3066         case MSR_IA32_PERF_CTL:
3067         case MSR_AMD64_DC_CFG:
3068         case MSR_F15H_EX_CFG:
3069         /*
3070          * Intel Sandy Bridge CPUs must support the RAPL (running average power
3071          * limit) MSRs. Just return 0, as we do not want to expose the host
3072          * data here. Do not conditionalize this on CPUID, as KVM does not do
3073          * so for existing CPU-specific MSRs.
3074          */
3075         case MSR_RAPL_POWER_UNIT:
3076         case MSR_PP0_ENERGY_STATUS:     /* Power plane 0 (core) */
3077         case MSR_PP1_ENERGY_STATUS:     /* Power plane 1 (graphics uncore) */
3078         case MSR_PKG_ENERGY_STATUS:     /* Total package */
3079         case MSR_DRAM_ENERGY_STATUS:    /* DRAM controller */
3080                 msr_info->data = 0;
3081                 break;
3082         case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3083         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3084         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3085         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3086         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3087                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3088                         return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3089                 msr_info->data = 0;
3090                 break;
3091         case MSR_IA32_UCODE_REV:
3092                 msr_info->data = vcpu->arch.microcode_version;
3093                 break;
3094         case MSR_IA32_ARCH_CAPABILITIES:
3095                 if (!msr_info->host_initiated &&
3096                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3097                         return 1;
3098                 msr_info->data = vcpu->arch.arch_capabilities;
3099                 break;
3100         case MSR_IA32_POWER_CTL:
3101                 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3102                 break;
3103         case MSR_IA32_TSC:
3104                 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
3105                 break;
3106         case MSR_MTRRcap:
3107         case 0x200 ... 0x2ff:
3108                 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3109         case 0xcd: /* fsb frequency */
3110                 msr_info->data = 3;
3111                 break;
3112                 /*
3113                  * MSR_EBC_FREQUENCY_ID
3114                  * Conservative value valid for even the basic CPU models.
3115                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3116                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3117                  * and 266MHz for model 3, or 4. Set Core Clock
3118                  * Frequency to System Bus Frequency Ratio to 1 (bits
3119                  * 31:24) even though these are only valid for CPU
3120                  * models > 2, however guests may end up dividing or
3121                  * multiplying by zero otherwise.
3122                  */
3123         case MSR_EBC_FREQUENCY_ID:
3124                 msr_info->data = 1 << 24;
3125                 break;
3126         case MSR_IA32_APICBASE:
3127                 msr_info->data = kvm_get_apic_base(vcpu);
3128                 break;
3129         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
3130                 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3131         case MSR_IA32_TSCDEADLINE:
3132                 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3133                 break;
3134         case MSR_IA32_TSC_ADJUST:
3135                 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3136                 break;
3137         case MSR_IA32_MISC_ENABLE:
3138                 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3139                 break;
3140         case MSR_IA32_SMBASE:
3141                 if (!msr_info->host_initiated)
3142                         return 1;
3143                 msr_info->data = vcpu->arch.smbase;
3144                 break;
3145         case MSR_SMI_COUNT:
3146                 msr_info->data = vcpu->arch.smi_count;
3147                 break;
3148         case MSR_IA32_PERF_STATUS:
3149                 /* TSC increment by tick */
3150                 msr_info->data = 1000ULL;
3151                 /* CPU multiplier */
3152                 msr_info->data |= (((uint64_t)4ULL) << 40);
3153                 break;
3154         case MSR_EFER:
3155                 msr_info->data = vcpu->arch.efer;
3156                 break;
3157         case MSR_KVM_WALL_CLOCK:
3158         case MSR_KVM_WALL_CLOCK_NEW:
3159                 msr_info->data = vcpu->kvm->arch.wall_clock;
3160                 break;
3161         case MSR_KVM_SYSTEM_TIME:
3162         case MSR_KVM_SYSTEM_TIME_NEW:
3163                 msr_info->data = vcpu->arch.time;
3164                 break;
3165         case MSR_KVM_ASYNC_PF_EN:
3166                 msr_info->data = vcpu->arch.apf.msr_val;
3167                 break;
3168         case MSR_KVM_STEAL_TIME:
3169                 msr_info->data = vcpu->arch.st.msr_val;
3170                 break;
3171         case MSR_KVM_PV_EOI_EN:
3172                 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3173                 break;
3174         case MSR_KVM_POLL_CONTROL:
3175                 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3176                 break;
3177         case MSR_IA32_P5_MC_ADDR:
3178         case MSR_IA32_P5_MC_TYPE:
3179         case MSR_IA32_MCG_CAP:
3180         case MSR_IA32_MCG_CTL:
3181         case MSR_IA32_MCG_STATUS:
3182         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3183                 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3184                                    msr_info->host_initiated);
3185         case MSR_IA32_XSS:
3186                 if (!msr_info->host_initiated &&
3187                     !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3188                         return 1;
3189                 msr_info->data = vcpu->arch.ia32_xss;
3190                 break;
3191         case MSR_K7_CLK_CTL:
3192                 /*
3193                  * Provide expected ramp-up count for K7. All other
3194                  * are set to zero, indicating minimum divisors for
3195                  * every field.
3196                  *
3197                  * This prevents guest kernels on AMD host with CPU
3198                  * type 6, model 8 and higher from exploding due to
3199                  * the rdmsr failing.
3200                  */
3201                 msr_info->data = 0x20000000;
3202                 break;
3203         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3204         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3205         case HV_X64_MSR_CRASH_CTL:
3206         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3207         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3208         case HV_X64_MSR_TSC_EMULATION_CONTROL:
3209         case HV_X64_MSR_TSC_EMULATION_STATUS:
3210                 return kvm_hv_get_msr_common(vcpu,
3211                                              msr_info->index, &msr_info->data,
3212                                              msr_info->host_initiated);
3213         case MSR_IA32_BBL_CR_CTL3:
3214                 /* This legacy MSR exists but isn't fully documented in current
3215                  * silicon.  It is however accessed by winxp in very narrow
3216                  * scenarios where it sets bit #19, itself documented as
3217                  * a "reserved" bit.  Best effort attempt to source coherent
3218                  * read data here should the balance of the register be
3219                  * interpreted by the guest:
3220                  *
3221                  * L2 cache control register 3: 64GB range, 256KB size,
3222                  * enabled, latency 0x1, configured
3223                  */
3224                 msr_info->data = 0xbe702111;
3225                 break;
3226         case MSR_AMD64_OSVW_ID_LENGTH:
3227                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3228                         return 1;
3229                 msr_info->data = vcpu->arch.osvw.length;
3230                 break;
3231         case MSR_AMD64_OSVW_STATUS:
3232                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3233                         return 1;
3234                 msr_info->data = vcpu->arch.osvw.status;
3235                 break;
3236         case MSR_PLATFORM_INFO:
3237                 if (!msr_info->host_initiated &&
3238                     !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3239                         return 1;
3240                 msr_info->data = vcpu->arch.msr_platform_info;
3241                 break;
3242         case MSR_MISC_FEATURES_ENABLES:
3243                 msr_info->data = vcpu->arch.msr_misc_features_enables;
3244                 break;
3245         case MSR_K7_HWCR:
3246                 msr_info->data = vcpu->arch.msr_hwcr;
3247                 break;
3248         default:
3249                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3250                         return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3251                 if (!ignore_msrs) {
3252                         vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3253                                                msr_info->index);
3254                         return 1;
3255                 } else {
3256                         if (report_ignored_msrs)
3257                                 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3258                                         msr_info->index);
3259                         msr_info->data = 0;
3260                 }
3261                 break;
3262         }
3263         return 0;
3264 }
3265 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3266
3267 /*
3268  * Read or write a bunch of msrs. All parameters are kernel addresses.
3269  *
3270  * @return number of msrs set successfully.
3271  */
3272 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3273                     struct kvm_msr_entry *entries,
3274                     int (*do_msr)(struct kvm_vcpu *vcpu,
3275                                   unsigned index, u64 *data))
3276 {
3277         int i;
3278
3279         for (i = 0; i < msrs->nmsrs; ++i)
3280                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3281                         break;
3282
3283         return i;
3284 }
3285
3286 /*
3287  * Read or write a bunch of msrs. Parameters are user addresses.
3288  *
3289  * @return number of msrs set successfully.
3290  */
3291 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3292                   int (*do_msr)(struct kvm_vcpu *vcpu,
3293                                 unsigned index, u64 *data),
3294                   int writeback)
3295 {
3296         struct kvm_msrs msrs;
3297         struct kvm_msr_entry *entries;
3298         int r, n;
3299         unsigned size;
3300
3301         r = -EFAULT;
3302         if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3303                 goto out;
3304
3305         r = -E2BIG;
3306         if (msrs.nmsrs >= MAX_IO_MSRS)
3307                 goto out;
3308
3309         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3310         entries = memdup_user(user_msrs->entries, size);
3311         if (IS_ERR(entries)) {
3312                 r = PTR_ERR(entries);
3313                 goto out;
3314         }
3315
3316         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3317         if (r < 0)
3318                 goto out_free;
3319
3320         r = -EFAULT;
3321         if (writeback && copy_to_user(user_msrs->entries, entries, size))
3322                 goto out_free;
3323
3324         r = n;
3325
3326 out_free:
3327         kfree(entries);
3328 out:
3329         return r;
3330 }
3331
3332 static inline bool kvm_can_mwait_in_guest(void)
3333 {
3334         return boot_cpu_has(X86_FEATURE_MWAIT) &&
3335                 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3336                 boot_cpu_has(X86_FEATURE_ARAT);
3337 }
3338
3339 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3340 {
3341         int r = 0;
3342
3343         switch (ext) {
3344         case KVM_CAP_IRQCHIP:
3345         case KVM_CAP_HLT:
3346         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3347         case KVM_CAP_SET_TSS_ADDR:
3348         case KVM_CAP_EXT_CPUID:
3349         case KVM_CAP_EXT_EMUL_CPUID:
3350         case KVM_CAP_CLOCKSOURCE:
3351         case KVM_CAP_PIT:
3352         case KVM_CAP_NOP_IO_DELAY:
3353         case KVM_CAP_MP_STATE:
3354         case KVM_CAP_SYNC_MMU:
3355         case KVM_CAP_USER_NMI:
3356         case KVM_CAP_REINJECT_CONTROL:
3357         case KVM_CAP_IRQ_INJECT_STATUS:
3358         case KVM_CAP_IOEVENTFD:
3359         case KVM_CAP_IOEVENTFD_NO_LENGTH:
3360         case KVM_CAP_PIT2:
3361         case KVM_CAP_PIT_STATE2:
3362         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3363         case KVM_CAP_XEN_HVM:
3364         case KVM_CAP_VCPU_EVENTS:
3365         case KVM_CAP_HYPERV:
3366         case KVM_CAP_HYPERV_VAPIC:
3367         case KVM_CAP_HYPERV_SPIN:
3368         case KVM_CAP_HYPERV_SYNIC:
3369         case KVM_CAP_HYPERV_SYNIC2:
3370         case KVM_CAP_HYPERV_VP_INDEX:
3371         case KVM_CAP_HYPERV_EVENTFD:
3372         case KVM_CAP_HYPERV_TLBFLUSH:
3373         case KVM_CAP_HYPERV_SEND_IPI:
3374         case KVM_CAP_HYPERV_CPUID:
3375         case KVM_CAP_PCI_SEGMENT:
3376         case KVM_CAP_DEBUGREGS:
3377         case KVM_CAP_X86_ROBUST_SINGLESTEP:
3378         case KVM_CAP_XSAVE:
3379         case KVM_CAP_ASYNC_PF:
3380         case KVM_CAP_GET_TSC_KHZ:
3381         case KVM_CAP_KVMCLOCK_CTRL:
3382         case KVM_CAP_READONLY_MEM:
3383         case KVM_CAP_HYPERV_TIME:
3384         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3385         case KVM_CAP_TSC_DEADLINE_TIMER:
3386         case KVM_CAP_DISABLE_QUIRKS:
3387         case KVM_CAP_SET_BOOT_CPU_ID:
3388         case KVM_CAP_SPLIT_IRQCHIP:
3389         case KVM_CAP_IMMEDIATE_EXIT:
3390         case KVM_CAP_PMU_EVENT_FILTER:
3391         case KVM_CAP_GET_MSR_FEATURES:
3392         case KVM_CAP_MSR_PLATFORM_INFO:
3393         case KVM_CAP_EXCEPTION_PAYLOAD:
3394         case KVM_CAP_SET_GUEST_DEBUG:
3395                 r = 1;
3396                 break;
3397         case KVM_CAP_SYNC_REGS:
3398                 r = KVM_SYNC_X86_VALID_FIELDS;
3399                 break;
3400         case KVM_CAP_ADJUST_CLOCK:
3401                 r = KVM_CLOCK_TSC_STABLE;
3402                 break;
3403         case KVM_CAP_X86_DISABLE_EXITS:
3404                 r |=  KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3405                       KVM_X86_DISABLE_EXITS_CSTATE;
3406                 if(kvm_can_mwait_in_guest())
3407                         r |= KVM_X86_DISABLE_EXITS_MWAIT;
3408                 break;
3409         case KVM_CAP_X86_SMM:
3410                 /* SMBASE is usually relocated above 1M on modern chipsets,
3411                  * and SMM handlers might indeed rely on 4G segment limits,
3412                  * so do not report SMM to be available if real mode is
3413                  * emulated via vm86 mode.  Still, do not go to great lengths
3414                  * to avoid userspace's usage of the feature, because it is a
3415                  * fringe case that is not enabled except via specific settings
3416                  * of the module parameters.
3417                  */
3418                 r = kvm_x86_ops.has_emulated_msr(MSR_IA32_SMBASE);
3419                 break;
3420         case KVM_CAP_VAPIC:
3421                 r = !kvm_x86_ops.cpu_has_accelerated_tpr();
3422                 break;
3423         case KVM_CAP_NR_VCPUS:
3424                 r = KVM_SOFT_MAX_VCPUS;
3425                 break;
3426         case KVM_CAP_MAX_VCPUS:
3427                 r = KVM_MAX_VCPUS;
3428                 break;
3429         case KVM_CAP_MAX_VCPU_ID:
3430                 r = KVM_MAX_VCPU_ID;
3431                 break;
3432         case KVM_CAP_PV_MMU:    /* obsolete */
3433                 r = 0;
3434                 break;
3435         case KVM_CAP_MCE:
3436                 r = KVM_MAX_MCE_BANKS;
3437                 break;
3438         case KVM_CAP_XCRS:
3439                 r = boot_cpu_has(X86_FEATURE_XSAVE);
3440                 break;
3441         case KVM_CAP_TSC_CONTROL:
3442                 r = kvm_has_tsc_control;
3443                 break;
3444         case KVM_CAP_X2APIC_API:
3445                 r = KVM_X2APIC_API_VALID_FLAGS;
3446                 break;
3447         case KVM_CAP_NESTED_STATE:
3448                 r = kvm_x86_ops.nested_ops->get_state ?
3449                         kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
3450                 break;
3451         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3452                 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3453                 break;
3454         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3455                 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
3456                 break;
3457         default:
3458                 break;
3459         }
3460         return r;
3461
3462 }
3463
3464 long kvm_arch_dev_ioctl(struct file *filp,
3465                         unsigned int ioctl, unsigned long arg)
3466 {
3467         void __user *argp = (void __user *)arg;
3468         long r;
3469
3470         switch (ioctl) {
3471         case KVM_GET_MSR_INDEX_LIST: {
3472                 struct kvm_msr_list __user *user_msr_list = argp;
3473                 struct kvm_msr_list msr_list;
3474                 unsigned n;
3475
3476                 r = -EFAULT;
3477                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3478                         goto out;
3479                 n = msr_list.nmsrs;
3480                 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3481                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3482                         goto out;
3483                 r = -E2BIG;
3484                 if (n < msr_list.nmsrs)
3485                         goto out;
3486                 r = -EFAULT;
3487                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3488                                  num_msrs_to_save * sizeof(u32)))
3489                         goto out;
3490                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3491                                  &emulated_msrs,
3492                                  num_emulated_msrs * sizeof(u32)))
3493                         goto out;
3494                 r = 0;
3495                 break;
3496         }
3497         case KVM_GET_SUPPORTED_CPUID:
3498         case KVM_GET_EMULATED_CPUID: {
3499                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3500                 struct kvm_cpuid2 cpuid;
3501
3502                 r = -EFAULT;
3503                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3504                         goto out;
3505
3506                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3507                                             ioctl);
3508                 if (r)
3509                         goto out;
3510
3511                 r = -EFAULT;
3512                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3513                         goto out;
3514                 r = 0;
3515                 break;
3516         }
3517         case KVM_X86_GET_MCE_CAP_SUPPORTED:
3518                 r = -EFAULT;
3519                 if (copy_to_user(argp, &kvm_mce_cap_supported,
3520                                  sizeof(kvm_mce_cap_supported)))
3521                         goto out;
3522                 r = 0;
3523                 break;
3524         case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3525                 struct kvm_msr_list __user *user_msr_list = argp;
3526                 struct kvm_msr_list msr_list;
3527                 unsigned int n;
3528
3529                 r = -EFAULT;
3530                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3531                         goto out;
3532                 n = msr_list.nmsrs;
3533                 msr_list.nmsrs = num_msr_based_features;
3534                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3535                         goto out;
3536                 r = -E2BIG;
3537                 if (n < msr_list.nmsrs)
3538                         goto out;
3539                 r = -EFAULT;
3540                 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3541                                  num_msr_based_features * sizeof(u32)))
3542                         goto out;
3543                 r = 0;
3544                 break;
3545         }
3546         case KVM_GET_MSRS:
3547                 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3548                 break;
3549         default:
3550                 r = -EINVAL;
3551                 break;
3552         }
3553 out:
3554         return r;
3555 }
3556
3557 static void wbinvd_ipi(void *garbage)
3558 {
3559         wbinvd();
3560 }
3561
3562 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3563 {
3564         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3565 }
3566
3567 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3568 {
3569         /* Address WBINVD may be executed by guest */
3570         if (need_emulate_wbinvd(vcpu)) {
3571                 if (kvm_x86_ops.has_wbinvd_exit())
3572                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3573                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3574                         smp_call_function_single(vcpu->cpu,
3575                                         wbinvd_ipi, NULL, 1);
3576         }
3577
3578         kvm_x86_ops.vcpu_load(vcpu, cpu);
3579
3580         /* Save host pkru register if supported */
3581         vcpu->arch.host_pkru = read_pkru();
3582
3583         /* Apply any externally detected TSC adjustments (due to suspend) */
3584         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3585                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3586                 vcpu->arch.tsc_offset_adjustment = 0;
3587                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3588         }
3589
3590         if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3591                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3592                                 rdtsc() - vcpu->arch.last_host_tsc;
3593                 if (tsc_delta < 0)
3594                         mark_tsc_unstable("KVM discovered backwards TSC");
3595
3596                 if (kvm_check_tsc_unstable()) {
3597                         u64 offset = kvm_compute_tsc_offset(vcpu,
3598                                                 vcpu->arch.last_guest_tsc);
3599                         kvm_vcpu_write_tsc_offset(vcpu, offset);
3600                         vcpu->arch.tsc_catchup = 1;
3601                 }
3602
3603                 if (kvm_lapic_hv_timer_in_use(vcpu))
3604                         kvm_lapic_restart_hv_timer(vcpu);
3605
3606                 /*
3607                  * On a host with synchronized TSC, there is no need to update
3608                  * kvmclock on vcpu->cpu migration
3609                  */
3610                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3611                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3612                 if (vcpu->cpu != cpu)
3613                         kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3614                 vcpu->cpu = cpu;
3615         }
3616
3617         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3618 }
3619
3620 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3621 {
3622         struct kvm_host_map map;
3623         struct kvm_steal_time *st;
3624
3625         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3626                 return;
3627
3628         if (vcpu->arch.st.preempted)
3629                 return;
3630
3631         if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3632                         &vcpu->arch.st.cache, true))
3633                 return;
3634
3635         st = map.hva +
3636                 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
3637
3638         st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
3639
3640         kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
3641 }
3642
3643 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3644 {
3645         int idx;
3646
3647         if (vcpu->preempted)
3648                 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu);
3649
3650         /*
3651          * Disable page faults because we're in atomic context here.
3652          * kvm_write_guest_offset_cached() would call might_fault()
3653          * that relies on pagefault_disable() to tell if there's a
3654          * bug. NOTE: the write to guest memory may not go through if
3655          * during postcopy live migration or if there's heavy guest
3656          * paging.
3657          */
3658         pagefault_disable();
3659         /*
3660          * kvm_memslots() will be called by
3661          * kvm_write_guest_offset_cached() so take the srcu lock.
3662          */
3663         idx = srcu_read_lock(&vcpu->kvm->srcu);
3664         kvm_steal_time_set_preempted(vcpu);
3665         srcu_read_unlock(&vcpu->kvm->srcu, idx);
3666         pagefault_enable();
3667         kvm_x86_ops.vcpu_put(vcpu);
3668         vcpu->arch.last_host_tsc = rdtsc();
3669         /*
3670          * If userspace has set any breakpoints or watchpoints, dr6 is restored
3671          * on every vmexit, but if not, we might have a stale dr6 from the
3672          * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3673          */
3674         set_debugreg(0, 6);
3675 }
3676
3677 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3678                                     struct kvm_lapic_state *s)
3679 {
3680         if (vcpu->arch.apicv_active)
3681                 kvm_x86_ops.sync_pir_to_irr(vcpu);
3682
3683         return kvm_apic_get_state(vcpu, s);
3684 }
3685
3686 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3687                                     struct kvm_lapic_state *s)
3688 {
3689         int r;
3690
3691         r = kvm_apic_set_state(vcpu, s);
3692         if (r)
3693                 return r;
3694         update_cr8_intercept(vcpu);
3695
3696         return 0;
3697 }
3698
3699 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3700 {
3701         return (!lapic_in_kernel(vcpu) ||
3702                 kvm_apic_accept_pic_intr(vcpu));
3703 }
3704
3705 /*
3706  * if userspace requested an interrupt window, check that the
3707  * interrupt window is open.
3708  *
3709  * No need to exit to userspace if we already have an interrupt queued.
3710  */
3711 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3712 {
3713         return kvm_arch_interrupt_allowed(vcpu) &&
3714                 !kvm_cpu_has_interrupt(vcpu) &&
3715                 !kvm_event_needs_reinjection(vcpu) &&
3716                 kvm_cpu_accept_dm_intr(vcpu);
3717 }
3718
3719 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3720                                     struct kvm_interrupt *irq)
3721 {
3722         if (irq->irq >= KVM_NR_INTERRUPTS)
3723                 return -EINVAL;
3724
3725         if (!irqchip_in_kernel(vcpu->kvm)) {
3726                 kvm_queue_interrupt(vcpu, irq->irq, false);
3727                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3728                 return 0;
3729         }
3730
3731         /*
3732          * With in-kernel LAPIC, we only use this to inject EXTINT, so
3733          * fail for in-kernel 8259.
3734          */
3735         if (pic_in_kernel(vcpu->kvm))
3736                 return -ENXIO;
3737
3738         if (vcpu->arch.pending_external_vector != -1)
3739                 return -EEXIST;
3740
3741         vcpu->arch.pending_external_vector = irq->irq;
3742         kvm_make_request(KVM_REQ_EVENT, vcpu);
3743         return 0;
3744 }
3745
3746 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3747 {
3748         kvm_inject_nmi(vcpu);
3749
3750         return 0;
3751 }
3752
3753 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3754 {
3755         kvm_make_request(KVM_REQ_SMI, vcpu);
3756
3757         return 0;
3758 }
3759
3760 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3761                                            struct kvm_tpr_access_ctl *tac)
3762 {
3763         if (tac->flags)
3764                 return -EINVAL;
3765         vcpu->arch.tpr_access_reporting = !!tac->enabled;
3766         return 0;
3767 }
3768
3769 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3770                                         u64 mcg_cap)
3771 {
3772         int r;
3773         unsigned bank_num = mcg_cap & 0xff, bank;
3774
3775         r = -EINVAL;
3776         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3777                 goto out;
3778         if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3779                 goto out;
3780         r = 0;
3781         vcpu->arch.mcg_cap = mcg_cap;
3782         /* Init IA32_MCG_CTL to all 1s */
3783         if (mcg_cap & MCG_CTL_P)
3784                 vcpu->arch.mcg_ctl = ~(u64)0;
3785         /* Init IA32_MCi_CTL to all 1s */
3786         for (bank = 0; bank < bank_num; bank++)
3787                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3788
3789         kvm_x86_ops.setup_mce(vcpu);
3790 out:
3791         return r;
3792 }
3793
3794 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3795                                       struct kvm_x86_mce *mce)
3796 {
3797         u64 mcg_cap = vcpu->arch.mcg_cap;
3798         unsigned bank_num = mcg_cap & 0xff;
3799         u64 *banks = vcpu->arch.mce_banks;
3800
3801         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3802                 return -EINVAL;
3803         /*
3804          * if IA32_MCG_CTL is not all 1s, the uncorrected error
3805          * reporting is disabled
3806          */
3807         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3808             vcpu->arch.mcg_ctl != ~(u64)0)
3809                 return 0;
3810         banks += 4 * mce->bank;
3811         /*
3812          * if IA32_MCi_CTL is not all 1s, the uncorrected error
3813          * reporting is disabled for the bank
3814          */
3815         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3816                 return 0;
3817         if (mce->status & MCI_STATUS_UC) {
3818                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3819                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3820                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3821                         return 0;
3822                 }
3823                 if (banks[1] & MCI_STATUS_VAL)
3824                         mce->status |= MCI_STATUS_OVER;
3825                 banks[2] = mce->addr;
3826                 banks[3] = mce->misc;
3827                 vcpu->arch.mcg_status = mce->mcg_status;
3828                 banks[1] = mce->status;
3829                 kvm_queue_exception(vcpu, MC_VECTOR);
3830         } else if (!(banks[1] & MCI_STATUS_VAL)
3831                    || !(banks[1] & MCI_STATUS_UC)) {
3832                 if (banks[1] & MCI_STATUS_VAL)
3833                         mce->status |= MCI_STATUS_OVER;
3834                 banks[2] = mce->addr;
3835                 banks[3] = mce->misc;
3836                 banks[1] = mce->status;
3837         } else
3838                 banks[1] |= MCI_STATUS_OVER;
3839         return 0;
3840 }
3841
3842 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3843                                                struct kvm_vcpu_events *events)
3844 {
3845         process_nmi(vcpu);
3846
3847         /*
3848          * In guest mode, payload delivery should be deferred,
3849          * so that the L1 hypervisor can intercept #PF before
3850          * CR2 is modified (or intercept #DB before DR6 is
3851          * modified under nVMX). Unless the per-VM capability,
3852          * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
3853          * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
3854          * opportunistically defer the exception payload, deliver it if the
3855          * capability hasn't been requested before processing a
3856          * KVM_GET_VCPU_EVENTS.
3857          */
3858         if (!vcpu->kvm->arch.exception_payload_enabled &&
3859             vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
3860                 kvm_deliver_exception_payload(vcpu);
3861
3862         /*
3863          * The API doesn't provide the instruction length for software
3864          * exceptions, so don't report them. As long as the guest RIP
3865          * isn't advanced, we should expect to encounter the exception
3866          * again.
3867          */
3868         if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3869                 events->exception.injected = 0;
3870                 events->exception.pending = 0;
3871         } else {
3872                 events->exception.injected = vcpu->arch.exception.injected;
3873                 events->exception.pending = vcpu->arch.exception.pending;
3874                 /*
3875                  * For ABI compatibility, deliberately conflate
3876                  * pending and injected exceptions when
3877                  * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3878                  */
3879                 if (!vcpu->kvm->arch.exception_payload_enabled)
3880                         events->exception.injected |=
3881                                 vcpu->arch.exception.pending;
3882         }
3883         events->exception.nr = vcpu->arch.exception.nr;
3884         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3885         events->exception.error_code = vcpu->arch.exception.error_code;
3886         events->exception_has_payload = vcpu->arch.exception.has_payload;
3887         events->exception_payload = vcpu->arch.exception.payload;
3888
3889         events->interrupt.injected =
3890                 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3891         events->interrupt.nr = vcpu->arch.interrupt.nr;
3892         events->interrupt.soft = 0;
3893         events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
3894
3895         events->nmi.injected = vcpu->arch.nmi_injected;
3896         events->nmi.pending = vcpu->arch.nmi_pending != 0;
3897         events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu);
3898         events->nmi.pad = 0;
3899
3900         events->sipi_vector = 0; /* never valid when reporting to user space */
3901
3902         events->smi.smm = is_smm(vcpu);
3903         events->smi.pending = vcpu->arch.smi_pending;
3904         events->smi.smm_inside_nmi =
3905                 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3906         events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3907
3908         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3909                          | KVM_VCPUEVENT_VALID_SHADOW
3910                          | KVM_VCPUEVENT_VALID_SMM);
3911         if (vcpu->kvm->arch.exception_payload_enabled)
3912                 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3913
3914         memset(&events->reserved, 0, sizeof(events->reserved));
3915 }
3916
3917 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3918
3919 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3920                                               struct kvm_vcpu_events *events)
3921 {
3922         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3923                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3924                               | KVM_VCPUEVENT_VALID_SHADOW
3925                               | KVM_VCPUEVENT_VALID_SMM
3926                               | KVM_VCPUEVENT_VALID_PAYLOAD))
3927                 return -EINVAL;
3928
3929         if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3930                 if (!vcpu->kvm->arch.exception_payload_enabled)
3931                         return -EINVAL;
3932                 if (events->exception.pending)
3933                         events->exception.injected = 0;
3934                 else
3935                         events->exception_has_payload = 0;
3936         } else {
3937                 events->exception.pending = 0;
3938                 events->exception_has_payload = 0;
3939         }
3940
3941         if ((events->exception.injected || events->exception.pending) &&
3942             (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3943                 return -EINVAL;
3944
3945         /* INITs are latched while in SMM */
3946         if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3947             (events->smi.smm || events->smi.pending) &&
3948             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3949                 return -EINVAL;
3950
3951         process_nmi(vcpu);
3952         vcpu->arch.exception.injected = events->exception.injected;
3953         vcpu->arch.exception.pending = events->exception.pending;
3954         vcpu->arch.exception.nr = events->exception.nr;
3955         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3956         vcpu->arch.exception.error_code = events->exception.error_code;
3957         vcpu->arch.exception.has_payload = events->exception_has_payload;
3958         vcpu->arch.exception.payload = events->exception_payload;
3959
3960         vcpu->arch.interrupt.injected = events->interrupt.injected;
3961         vcpu->arch.interrupt.nr = events->interrupt.nr;
3962         vcpu->arch.interrupt.soft = events->interrupt.soft;
3963         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3964                 kvm_x86_ops.set_interrupt_shadow(vcpu,
3965                                                   events->interrupt.shadow);
3966
3967         vcpu->arch.nmi_injected = events->nmi.injected;
3968         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3969                 vcpu->arch.nmi_pending = events->nmi.pending;
3970         kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked);
3971
3972         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3973             lapic_in_kernel(vcpu))
3974                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3975
3976         if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3977                 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3978                         if (events->smi.smm)
3979                                 vcpu->arch.hflags |= HF_SMM_MASK;
3980                         else
3981                                 vcpu->arch.hflags &= ~HF_SMM_MASK;
3982                         kvm_smm_changed(vcpu);
3983                 }
3984
3985                 vcpu->arch.smi_pending = events->smi.pending;
3986
3987                 if (events->smi.smm) {
3988                         if (events->smi.smm_inside_nmi)
3989                                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3990                         else
3991                                 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3992                 }
3993
3994                 if (lapic_in_kernel(vcpu)) {
3995                         if (events->smi.latched_init)
3996                                 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3997                         else
3998                                 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3999                 }
4000         }
4001
4002         kvm_make_request(KVM_REQ_EVENT, vcpu);
4003
4004         return 0;
4005 }
4006
4007 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4008                                              struct kvm_debugregs *dbgregs)
4009 {
4010         unsigned long val;
4011
4012         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4013         kvm_get_dr(vcpu, 6, &val);
4014         dbgregs->dr6 = val;
4015         dbgregs->dr7 = vcpu->arch.dr7;
4016         dbgregs->flags = 0;
4017         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4018 }
4019
4020 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4021                                             struct kvm_debugregs *dbgregs)
4022 {
4023         if (dbgregs->flags)
4024                 return -EINVAL;
4025
4026         if (dbgregs->dr6 & ~0xffffffffull)
4027                 return -EINVAL;
4028         if (dbgregs->dr7 & ~0xffffffffull)
4029                 return -EINVAL;
4030
4031         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4032         kvm_update_dr0123(vcpu);
4033         vcpu->arch.dr6 = dbgregs->dr6;
4034         vcpu->arch.dr7 = dbgregs->dr7;
4035         kvm_update_dr7(vcpu);
4036
4037         return 0;
4038 }
4039
4040 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4041
4042 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4043 {
4044         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4045         u64 xstate_bv = xsave->header.xfeatures;
4046         u64 valid;
4047
4048         /*
4049          * Copy legacy XSAVE area, to avoid complications with CPUID
4050          * leaves 0 and 1 in the loop below.
4051          */
4052         memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4053
4054         /* Set XSTATE_BV */
4055         xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4056         *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4057
4058         /*
4059          * Copy each region from the possibly compacted offset to the
4060          * non-compacted offset.
4061          */
4062         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4063         while (valid) {
4064                 u64 xfeature_mask = valid & -valid;
4065                 int xfeature_nr = fls64(xfeature_mask) - 1;
4066                 void *src = get_xsave_addr(xsave, xfeature_nr);
4067
4068                 if (src) {
4069                         u32 size, offset, ecx, edx;
4070                         cpuid_count(XSTATE_CPUID, xfeature_nr,
4071                                     &size, &offset, &ecx, &edx);
4072                         if (xfeature_nr == XFEATURE_PKRU)
4073                                 memcpy(dest + offset, &vcpu->arch.pkru,
4074                                        sizeof(vcpu->arch.pkru));
4075                         else
4076                                 memcpy(dest + offset, src, size);
4077
4078                 }
4079
4080                 valid -= xfeature_mask;
4081         }
4082 }
4083
4084 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4085 {
4086         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4087         u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4088         u64 valid;
4089
4090         /*
4091          * Copy legacy XSAVE area, to avoid complications with CPUID
4092          * leaves 0 and 1 in the loop below.
4093          */
4094         memcpy(xsave, src, XSAVE_HDR_OFFSET);
4095
4096         /* Set XSTATE_BV and possibly XCOMP_BV.  */
4097         xsave->header.xfeatures = xstate_bv;
4098         if (boot_cpu_has(X86_FEATURE_XSAVES))
4099                 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4100
4101         /*
4102          * Copy each region from the non-compacted offset to the
4103          * possibly compacted offset.
4104          */
4105         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4106         while (valid) {
4107                 u64 xfeature_mask = valid & -valid;
4108                 int xfeature_nr = fls64(xfeature_mask) - 1;
4109                 void *dest = get_xsave_addr(xsave, xfeature_nr);
4110
4111                 if (dest) {
4112                         u32 size, offset, ecx, edx;
4113                         cpuid_count(XSTATE_CPUID, xfeature_nr,
4114                                     &size, &offset, &ecx, &edx);
4115                         if (xfeature_nr == XFEATURE_PKRU)
4116                                 memcpy(&vcpu->arch.pkru, src + offset,
4117                                        sizeof(vcpu->arch.pkru));
4118                         else
4119                                 memcpy(dest, src + offset, size);
4120                 }
4121
4122                 valid -= xfeature_mask;
4123         }
4124 }
4125
4126 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4127                                          struct kvm_xsave *guest_xsave)
4128 {
4129         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4130                 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4131                 fill_xsave((u8 *) guest_xsave->region, vcpu);
4132         } else {
4133                 memcpy(guest_xsave->region,
4134                         &vcpu->arch.guest_fpu->state.fxsave,
4135                         sizeof(struct fxregs_state));
4136                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4137                         XFEATURE_MASK_FPSSE;
4138         }
4139 }
4140
4141 #define XSAVE_MXCSR_OFFSET 24
4142
4143 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4144                                         struct kvm_xsave *guest_xsave)
4145 {
4146         u64 xstate_bv =
4147                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4148         u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4149
4150         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4151                 /*
4152                  * Here we allow setting states that are not present in
4153                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
4154                  * with old userspace.
4155                  */
4156                 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4157                         return -EINVAL;
4158                 load_xsave(vcpu, (u8 *)guest_xsave->region);
4159         } else {
4160                 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4161                         mxcsr & ~mxcsr_feature_mask)
4162                         return -EINVAL;
4163                 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4164                         guest_xsave->region, sizeof(struct fxregs_state));
4165         }
4166         return 0;
4167 }
4168
4169 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4170                                         struct kvm_xcrs *guest_xcrs)
4171 {
4172         if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4173                 guest_xcrs->nr_xcrs = 0;
4174                 return;
4175         }
4176
4177         guest_xcrs->nr_xcrs = 1;
4178         guest_xcrs->flags = 0;
4179         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4180         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4181 }
4182
4183 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4184                                        struct kvm_xcrs *guest_xcrs)
4185 {
4186         int i, r = 0;
4187
4188         if (!boot_cpu_has(X86_FEATURE_XSAVE))
4189                 return -EINVAL;
4190
4191         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4192                 return -EINVAL;
4193
4194         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4195                 /* Only support XCR0 currently */
4196                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4197                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4198                                 guest_xcrs->xcrs[i].value);
4199                         break;
4200                 }
4201         if (r)
4202                 r = -EINVAL;
4203         return r;
4204 }
4205
4206 /*
4207  * kvm_set_guest_paused() indicates to the guest kernel that it has been
4208  * stopped by the hypervisor.  This function will be called from the host only.
4209  * EINVAL is returned when the host attempts to set the flag for a guest that
4210  * does not support pv clocks.
4211  */
4212 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4213 {
4214         if (!vcpu->arch.pv_time_enabled)
4215                 return -EINVAL;
4216         vcpu->arch.pvclock_set_guest_stopped_request = true;
4217         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4218         return 0;
4219 }
4220
4221 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4222                                      struct kvm_enable_cap *cap)
4223 {
4224         int r;
4225         uint16_t vmcs_version;
4226         void __user *user_ptr;
4227
4228         if (cap->flags)
4229                 return -EINVAL;
4230
4231         switch (cap->cap) {
4232         case KVM_CAP_HYPERV_SYNIC2:
4233                 if (cap->args[0])
4234                         return -EINVAL;
4235                 /* fall through */
4236
4237         case KVM_CAP_HYPERV_SYNIC:
4238                 if (!irqchip_in_kernel(vcpu->kvm))
4239                         return -EINVAL;
4240                 return kvm_hv_activate_synic(vcpu, cap->cap ==
4241                                              KVM_CAP_HYPERV_SYNIC2);
4242         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4243                 if (!kvm_x86_ops.nested_ops->enable_evmcs)
4244                         return -ENOTTY;
4245                 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
4246                 if (!r) {
4247                         user_ptr = (void __user *)(uintptr_t)cap->args[0];
4248                         if (copy_to_user(user_ptr, &vmcs_version,
4249                                          sizeof(vmcs_version)))
4250                                 r = -EFAULT;
4251                 }
4252                 return r;
4253         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4254                 if (!kvm_x86_ops.enable_direct_tlbflush)
4255                         return -ENOTTY;
4256
4257                 return kvm_x86_ops.enable_direct_tlbflush(vcpu);
4258
4259         default:
4260                 return -EINVAL;
4261         }
4262 }
4263
4264 long kvm_arch_vcpu_ioctl(struct file *filp,
4265                          unsigned int ioctl, unsigned long arg)
4266 {
4267         struct kvm_vcpu *vcpu = filp->private_data;
4268         void __user *argp = (void __user *)arg;
4269         int r;
4270         union {
4271                 struct kvm_lapic_state *lapic;
4272                 struct kvm_xsave *xsave;
4273                 struct kvm_xcrs *xcrs;
4274                 void *buffer;
4275         } u;
4276
4277         vcpu_load(vcpu);
4278
4279         u.buffer = NULL;
4280         switch (ioctl) {
4281         case KVM_GET_LAPIC: {
4282                 r = -EINVAL;
4283                 if (!lapic_in_kernel(vcpu))
4284                         goto out;
4285                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4286                                 GFP_KERNEL_ACCOUNT);
4287
4288                 r = -ENOMEM;
4289                 if (!u.lapic)
4290                         goto out;
4291                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4292                 if (r)
4293                         goto out;
4294                 r = -EFAULT;
4295                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4296                         goto out;
4297                 r = 0;
4298                 break;
4299         }
4300         case KVM_SET_LAPIC: {
4301                 r = -EINVAL;
4302                 if (!lapic_in_kernel(vcpu))
4303                         goto out;
4304                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4305                 if (IS_ERR(u.lapic)) {
4306                         r = PTR_ERR(u.lapic);
4307                         goto out_nofree;
4308                 }
4309
4310                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4311                 break;
4312         }
4313         case KVM_INTERRUPT: {
4314                 struct kvm_interrupt irq;
4315
4316                 r = -EFAULT;
4317                 if (copy_from_user(&irq, argp, sizeof(irq)))
4318                         goto out;
4319                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4320                 break;
4321         }
4322         case KVM_NMI: {
4323                 r = kvm_vcpu_ioctl_nmi(vcpu);
4324                 break;
4325         }
4326         case KVM_SMI: {
4327                 r = kvm_vcpu_ioctl_smi(vcpu);
4328                 break;
4329         }
4330         case KVM_SET_CPUID: {
4331                 struct kvm_cpuid __user *cpuid_arg = argp;
4332                 struct kvm_cpuid cpuid;
4333
4334                 r = -EFAULT;
4335                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4336                         goto out;
4337                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4338                 break;
4339         }
4340         case KVM_SET_CPUID2: {
4341                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4342                 struct kvm_cpuid2 cpuid;
4343
4344                 r = -EFAULT;
4345                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4346                         goto out;
4347                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4348                                               cpuid_arg->entries);
4349                 break;
4350         }
4351         case KVM_GET_CPUID2: {
4352                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4353                 struct kvm_cpuid2 cpuid;
4354
4355                 r = -EFAULT;
4356                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4357                         goto out;
4358                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4359                                               cpuid_arg->entries);
4360                 if (r)
4361                         goto out;
4362                 r = -EFAULT;
4363                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4364                         goto out;
4365                 r = 0;
4366                 break;
4367         }
4368         case KVM_GET_MSRS: {
4369                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4370                 r = msr_io(vcpu, argp, do_get_msr, 1);
4371                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4372                 break;
4373         }
4374         case KVM_SET_MSRS: {
4375                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4376                 r = msr_io(vcpu, argp, do_set_msr, 0);
4377                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4378                 break;
4379         }
4380         case KVM_TPR_ACCESS_REPORTING: {
4381                 struct kvm_tpr_access_ctl tac;
4382
4383                 r = -EFAULT;
4384                 if (copy_from_user(&tac, argp, sizeof(tac)))
4385                         goto out;
4386                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4387                 if (r)
4388                         goto out;
4389                 r = -EFAULT;
4390                 if (copy_to_user(argp, &tac, sizeof(tac)))
4391                         goto out;
4392                 r = 0;
4393                 break;
4394         };
4395         case KVM_SET_VAPIC_ADDR: {
4396                 struct kvm_vapic_addr va;
4397                 int idx;
4398
4399                 r = -EINVAL;
4400                 if (!lapic_in_kernel(vcpu))
4401                         goto out;
4402                 r = -EFAULT;
4403                 if (copy_from_user(&va, argp, sizeof(va)))
4404                         goto out;
4405                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4406                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4407                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4408                 break;
4409         }
4410         case KVM_X86_SETUP_MCE: {
4411                 u64 mcg_cap;
4412
4413                 r = -EFAULT;
4414                 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4415                         goto out;
4416                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4417                 break;
4418         }
4419         case KVM_X86_SET_MCE: {
4420                 struct kvm_x86_mce mce;
4421
4422                 r = -EFAULT;
4423                 if (copy_from_user(&mce, argp, sizeof(mce)))
4424                         goto out;
4425                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4426                 break;
4427         }
4428         case KVM_GET_VCPU_EVENTS: {
4429                 struct kvm_vcpu_events events;
4430
4431                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4432
4433                 r = -EFAULT;
4434                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4435                         break;
4436                 r = 0;
4437                 break;
4438         }
4439         case KVM_SET_VCPU_EVENTS: {
4440                 struct kvm_vcpu_events events;
4441
4442                 r = -EFAULT;
4443                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4444                         break;
4445
4446                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4447                 break;
4448         }
4449         case KVM_GET_DEBUGREGS: {
4450                 struct kvm_debugregs dbgregs;
4451
4452                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4453
4454                 r = -EFAULT;
4455                 if (copy_to_user(argp, &dbgregs,
4456                                  sizeof(struct kvm_debugregs)))
4457                         break;
4458                 r = 0;
4459                 break;
4460         }
4461         case KVM_SET_DEBUGREGS: {
4462                 struct kvm_debugregs dbgregs;
4463
4464                 r = -EFAULT;
4465                 if (copy_from_user(&dbgregs, argp,
4466                                    sizeof(struct kvm_debugregs)))
4467                         break;
4468
4469                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4470                 break;
4471         }
4472         case KVM_GET_XSAVE: {
4473                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4474                 r = -ENOMEM;
4475                 if (!u.xsave)
4476                         break;
4477
4478                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4479
4480                 r = -EFAULT;
4481                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4482                         break;
4483                 r = 0;
4484                 break;
4485         }
4486         case KVM_SET_XSAVE: {
4487                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4488                 if (IS_ERR(u.xsave)) {
4489                         r = PTR_ERR(u.xsave);
4490                         goto out_nofree;
4491                 }
4492
4493                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4494                 break;
4495         }
4496         case KVM_GET_XCRS: {
4497                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4498                 r = -ENOMEM;
4499                 if (!u.xcrs)
4500                         break;
4501
4502                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4503
4504                 r = -EFAULT;
4505                 if (copy_to_user(argp, u.xcrs,
4506                                  sizeof(struct kvm_xcrs)))
4507                         break;
4508                 r = 0;
4509                 break;
4510         }
4511         case KVM_SET_XCRS: {
4512                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4513                 if (IS_ERR(u.xcrs)) {
4514                         r = PTR_ERR(u.xcrs);
4515                         goto out_nofree;
4516                 }
4517
4518                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4519                 break;
4520         }
4521         case KVM_SET_TSC_KHZ: {
4522                 u32 user_tsc_khz;
4523
4524                 r = -EINVAL;
4525                 user_tsc_khz = (u32)arg;
4526
4527                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4528                         goto out;
4529
4530                 if (user_tsc_khz == 0)
4531                         user_tsc_khz = tsc_khz;
4532
4533                 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4534                         r = 0;
4535
4536                 goto out;
4537         }
4538         case KVM_GET_TSC_KHZ: {
4539                 r = vcpu->arch.virtual_tsc_khz;
4540                 goto out;
4541         }
4542         case KVM_KVMCLOCK_CTRL: {
4543                 r = kvm_set_guest_paused(vcpu);
4544                 goto out;
4545         }
4546         case KVM_ENABLE_CAP: {
4547                 struct kvm_enable_cap cap;
4548
4549                 r = -EFAULT;
4550                 if (copy_from_user(&cap, argp, sizeof(cap)))
4551                         goto out;
4552                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4553                 break;
4554         }
4555         case KVM_GET_NESTED_STATE: {
4556                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4557                 u32 user_data_size;
4558
4559                 r = -EINVAL;
4560                 if (!kvm_x86_ops.nested_ops->get_state)
4561                         break;
4562
4563                 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4564                 r = -EFAULT;
4565                 if (get_user(user_data_size, &user_kvm_nested_state->size))
4566                         break;
4567
4568                 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
4569                                                      user_data_size);
4570                 if (r < 0)
4571                         break;
4572
4573                 if (r > user_data_size) {
4574                         if (put_user(r, &user_kvm_nested_state->size))
4575                                 r = -EFAULT;
4576                         else
4577                                 r = -E2BIG;
4578                         break;
4579                 }
4580
4581                 r = 0;
4582                 break;
4583         }
4584         case KVM_SET_NESTED_STATE: {
4585                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4586                 struct kvm_nested_state kvm_state;
4587                 int idx;
4588
4589                 r = -EINVAL;
4590                 if (!kvm_x86_ops.nested_ops->set_state)
4591                         break;
4592
4593                 r = -EFAULT;
4594                 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4595                         break;
4596
4597                 r = -EINVAL;
4598                 if (kvm_state.size < sizeof(kvm_state))
4599                         break;
4600
4601                 if (kvm_state.flags &
4602                     ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4603                       | KVM_STATE_NESTED_EVMCS))
4604                         break;
4605
4606                 /* nested_run_pending implies guest_mode.  */
4607                 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4608                     && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4609                         break;
4610
4611                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4612                 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
4613                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4614                 break;
4615         }
4616         case KVM_GET_SUPPORTED_HV_CPUID: {
4617                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4618                 struct kvm_cpuid2 cpuid;
4619
4620                 r = -EFAULT;
4621                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4622                         goto out;
4623
4624                 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4625                                                 cpuid_arg->entries);
4626                 if (r)
4627                         goto out;
4628
4629                 r = -EFAULT;
4630                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4631                         goto out;
4632                 r = 0;
4633                 break;
4634         }
4635         default:
4636                 r = -EINVAL;
4637         }
4638 out:
4639         kfree(u.buffer);
4640 out_nofree:
4641         vcpu_put(vcpu);
4642         return r;
4643 }
4644
4645 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4646 {
4647         return VM_FAULT_SIGBUS;
4648 }
4649
4650 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4651 {
4652         int ret;
4653
4654         if (addr > (unsigned int)(-3 * PAGE_SIZE))
4655                 return -EINVAL;
4656         ret = kvm_x86_ops.set_tss_addr(kvm, addr);
4657         return ret;
4658 }
4659
4660 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4661                                               u64 ident_addr)
4662 {
4663         return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr);
4664 }
4665
4666 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4667                                          unsigned long kvm_nr_mmu_pages)
4668 {
4669         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4670                 return -EINVAL;
4671
4672         mutex_lock(&kvm->slots_lock);
4673
4674         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4675         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4676
4677         mutex_unlock(&kvm->slots_lock);
4678         return 0;
4679 }
4680
4681 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4682 {
4683         return kvm->arch.n_max_mmu_pages;
4684 }
4685
4686 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4687 {
4688         struct kvm_pic *pic = kvm->arch.vpic;
4689         int r;
4690
4691         r = 0;
4692         switch (chip->chip_id) {
4693         case KVM_IRQCHIP_PIC_MASTER:
4694                 memcpy(&chip->chip.pic, &pic->pics[0],
4695                         sizeof(struct kvm_pic_state));
4696                 break;
4697         case KVM_IRQCHIP_PIC_SLAVE:
4698                 memcpy(&chip->chip.pic, &pic->pics[1],
4699                         sizeof(struct kvm_pic_state));
4700                 break;
4701         case KVM_IRQCHIP_IOAPIC:
4702                 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4703                 break;
4704         default:
4705                 r = -EINVAL;
4706                 break;
4707         }
4708         return r;
4709 }
4710
4711 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4712 {
4713         struct kvm_pic *pic = kvm->arch.vpic;
4714         int r;
4715
4716         r = 0;
4717         switch (chip->chip_id) {
4718         case KVM_IRQCHIP_PIC_MASTER:
4719                 spin_lock(&pic->lock);
4720                 memcpy(&pic->pics[0], &chip->chip.pic,
4721                         sizeof(struct kvm_pic_state));
4722                 spin_unlock(&pic->lock);
4723                 break;
4724         case KVM_IRQCHIP_PIC_SLAVE:
4725                 spin_lock(&pic->lock);
4726                 memcpy(&pic->pics[1], &chip->chip.pic,
4727                         sizeof(struct kvm_pic_state));
4728                 spin_unlock(&pic->lock);
4729                 break;
4730         case KVM_IRQCHIP_IOAPIC:
4731                 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4732                 break;
4733         default:
4734                 r = -EINVAL;
4735                 break;
4736         }
4737         kvm_pic_update_irq(pic);
4738         return r;
4739 }
4740
4741 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4742 {
4743         struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4744
4745         BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4746
4747         mutex_lock(&kps->lock);
4748         memcpy(ps, &kps->channels, sizeof(*ps));
4749         mutex_unlock(&kps->lock);
4750         return 0;
4751 }
4752
4753 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4754 {
4755         int i;
4756         struct kvm_pit *pit = kvm->arch.vpit;
4757
4758         mutex_lock(&pit->pit_state.lock);
4759         memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4760         for (i = 0; i < 3; i++)
4761                 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4762         mutex_unlock(&pit->pit_state.lock);
4763         return 0;
4764 }
4765
4766 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4767 {
4768         mutex_lock(&kvm->arch.vpit->pit_state.lock);
4769         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4770                 sizeof(ps->channels));
4771         ps->flags = kvm->arch.vpit->pit_state.flags;
4772         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4773         memset(&ps->reserved, 0, sizeof(ps->reserved));
4774         return 0;
4775 }
4776
4777 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4778 {
4779         int start = 0;
4780         int i;
4781         u32 prev_legacy, cur_legacy;
4782         struct kvm_pit *pit = kvm->arch.vpit;
4783
4784         mutex_lock(&pit->pit_state.lock);
4785         prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4786         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4787         if (!prev_legacy && cur_legacy)
4788                 start = 1;
4789         memcpy(&pit->pit_state.channels, &ps->channels,
4790                sizeof(pit->pit_state.channels));
4791         pit->pit_state.flags = ps->flags;
4792         for (i = 0; i < 3; i++)
4793                 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4794                                    start && i == 0);
4795         mutex_unlock(&pit->pit_state.lock);
4796         return 0;
4797 }
4798
4799 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4800                                  struct kvm_reinject_control *control)
4801 {
4802         struct kvm_pit *pit = kvm->arch.vpit;
4803
4804         /* pit->pit_state.lock was overloaded to prevent userspace from getting
4805          * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4806          * ioctls in parallel.  Use a separate lock if that ioctl isn't rare.
4807          */
4808         mutex_lock(&pit->pit_state.lock);
4809         kvm_pit_set_reinject(pit, control->pit_reinject);
4810         mutex_unlock(&pit->pit_state.lock);
4811
4812         return 0;
4813 }
4814
4815 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
4816 {
4817         /*
4818          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4819          */
4820         if (kvm_x86_ops.flush_log_dirty)
4821                 kvm_x86_ops.flush_log_dirty(kvm);
4822 }
4823
4824 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4825                         bool line_status)
4826 {
4827         if (!irqchip_in_kernel(kvm))
4828                 return -ENXIO;
4829
4830         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4831                                         irq_event->irq, irq_event->level,
4832                                         line_status);
4833         return 0;
4834 }
4835
4836 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4837                             struct kvm_enable_cap *cap)
4838 {
4839         int r;
4840
4841         if (cap->flags)
4842                 return -EINVAL;
4843
4844         switch (cap->cap) {
4845         case KVM_CAP_DISABLE_QUIRKS:
4846                 kvm->arch.disabled_quirks = cap->args[0];
4847                 r = 0;
4848                 break;
4849         case KVM_CAP_SPLIT_IRQCHIP: {
4850                 mutex_lock(&kvm->lock);
4851                 r = -EINVAL;
4852                 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4853                         goto split_irqchip_unlock;
4854                 r = -EEXIST;
4855                 if (irqchip_in_kernel(kvm))
4856                         goto split_irqchip_unlock;
4857                 if (kvm->created_vcpus)
4858                         goto split_irqchip_unlock;
4859                 r = kvm_setup_empty_irq_routing(kvm);
4860                 if (r)
4861                         goto split_irqchip_unlock;
4862                 /* Pairs with irqchip_in_kernel. */
4863                 smp_wmb();
4864                 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4865                 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4866                 r = 0;
4867 split_irqchip_unlock:
4868                 mutex_unlock(&kvm->lock);
4869                 break;
4870         }
4871         case KVM_CAP_X2APIC_API:
4872                 r = -EINVAL;
4873                 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4874                         break;
4875
4876                 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4877                         kvm->arch.x2apic_format = true;
4878                 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4879                         kvm->arch.x2apic_broadcast_quirk_disabled = true;
4880
4881                 r = 0;
4882                 break;
4883         case KVM_CAP_X86_DISABLE_EXITS:
4884                 r = -EINVAL;
4885                 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4886                         break;
4887
4888                 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4889                         kvm_can_mwait_in_guest())
4890                         kvm->arch.mwait_in_guest = true;
4891                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4892                         kvm->arch.hlt_in_guest = true;
4893                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4894                         kvm->arch.pause_in_guest = true;
4895                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4896                         kvm->arch.cstate_in_guest = true;
4897                 r = 0;
4898                 break;
4899         case KVM_CAP_MSR_PLATFORM_INFO:
4900                 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4901                 r = 0;
4902                 break;
4903         case KVM_CAP_EXCEPTION_PAYLOAD:
4904                 kvm->arch.exception_payload_enabled = cap->args[0];
4905                 r = 0;
4906                 break;
4907         default:
4908                 r = -EINVAL;
4909                 break;
4910         }
4911         return r;
4912 }
4913
4914 long kvm_arch_vm_ioctl(struct file *filp,
4915                        unsigned int ioctl, unsigned long arg)
4916 {
4917         struct kvm *kvm = filp->private_data;
4918         void __user *argp = (void __user *)arg;
4919         int r = -ENOTTY;
4920         /*
4921          * This union makes it completely explicit to gcc-3.x
4922          * that these two variables' stack usage should be
4923          * combined, not added together.
4924          */
4925         union {
4926                 struct kvm_pit_state ps;
4927                 struct kvm_pit_state2 ps2;
4928                 struct kvm_pit_config pit_config;
4929         } u;
4930
4931         switch (ioctl) {
4932         case KVM_SET_TSS_ADDR:
4933                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4934                 break;
4935         case KVM_SET_IDENTITY_MAP_ADDR: {
4936                 u64 ident_addr;
4937
4938                 mutex_lock(&kvm->lock);
4939                 r = -EINVAL;
4940                 if (kvm->created_vcpus)
4941                         goto set_identity_unlock;
4942                 r = -EFAULT;
4943                 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4944                         goto set_identity_unlock;
4945                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4946 set_identity_unlock:
4947                 mutex_unlock(&kvm->lock);
4948                 break;
4949         }
4950         case KVM_SET_NR_MMU_PAGES:
4951                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4952                 break;
4953         case KVM_GET_NR_MMU_PAGES:
4954                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4955                 break;
4956         case KVM_CREATE_IRQCHIP: {
4957                 mutex_lock(&kvm->lock);
4958
4959                 r = -EEXIST;
4960                 if (irqchip_in_kernel(kvm))
4961                         goto create_irqchip_unlock;
4962
4963                 r = -EINVAL;
4964                 if (kvm->created_vcpus)
4965                         goto create_irqchip_unlock;
4966
4967                 r = kvm_pic_init(kvm);
4968                 if (r)
4969                         goto create_irqchip_unlock;
4970
4971                 r = kvm_ioapic_init(kvm);
4972                 if (r) {
4973                         kvm_pic_destroy(kvm);
4974                         goto create_irqchip_unlock;
4975                 }
4976
4977                 r = kvm_setup_default_irq_routing(kvm);
4978                 if (r) {
4979                         kvm_ioapic_destroy(kvm);
4980                         kvm_pic_destroy(kvm);
4981                         goto create_irqchip_unlock;
4982                 }
4983                 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4984                 smp_wmb();
4985                 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4986         create_irqchip_unlock:
4987                 mutex_unlock(&kvm->lock);
4988                 break;
4989         }
4990         case KVM_CREATE_PIT:
4991                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4992                 goto create_pit;
4993         case KVM_CREATE_PIT2:
4994                 r = -EFAULT;
4995                 if (copy_from_user(&u.pit_config, argp,
4996                                    sizeof(struct kvm_pit_config)))
4997                         goto out;
4998         create_pit:
4999                 mutex_lock(&kvm->lock);
5000                 r = -EEXIST;
5001                 if (kvm->arch.vpit)
5002                         goto create_pit_unlock;
5003                 r = -ENOMEM;
5004                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5005                 if (kvm->arch.vpit)
5006                         r = 0;
5007         create_pit_unlock:
5008                 mutex_unlock(&kvm->lock);
5009                 break;
5010         case KVM_GET_IRQCHIP: {
5011                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5012                 struct kvm_irqchip *chip;
5013
5014                 chip = memdup_user(argp, sizeof(*chip));
5015                 if (IS_ERR(chip)) {
5016                         r = PTR_ERR(chip);
5017                         goto out;
5018                 }
5019
5020                 r = -ENXIO;
5021                 if (!irqchip_kernel(kvm))
5022                         goto get_irqchip_out;
5023                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5024                 if (r)
5025                         goto get_irqchip_out;
5026                 r = -EFAULT;
5027                 if (copy_to_user(argp, chip, sizeof(*chip)))
5028                         goto get_irqchip_out;
5029                 r = 0;
5030         get_irqchip_out:
5031                 kfree(chip);
5032                 break;
5033         }
5034         case KVM_SET_IRQCHIP: {
5035                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5036                 struct kvm_irqchip *chip;
5037
5038                 chip = memdup_user(argp, sizeof(*chip));
5039                 if (IS_ERR(chip)) {
5040                         r = PTR_ERR(chip);
5041                         goto out;
5042                 }
5043
5044                 r = -ENXIO;
5045                 if (!irqchip_kernel(kvm))
5046                         goto set_irqchip_out;
5047                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5048         set_irqchip_out:
5049                 kfree(chip);
5050                 break;
5051         }
5052         case KVM_GET_PIT: {
5053                 r = -EFAULT;
5054                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5055                         goto out;
5056                 r = -ENXIO;
5057                 if (!kvm->arch.vpit)
5058                         goto out;
5059                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5060                 if (r)
5061                         goto out;
5062                 r = -EFAULT;
5063                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5064                         goto out;
5065                 r = 0;
5066                 break;
5067         }
5068         case KVM_SET_PIT: {
5069                 r = -EFAULT;
5070                 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5071                         goto out;
5072                 mutex_lock(&kvm->lock);
5073                 r = -ENXIO;
5074                 if (!kvm->arch.vpit)
5075                         goto set_pit_out;
5076                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5077 set_pit_out:
5078                 mutex_unlock(&kvm->lock);
5079                 break;
5080         }
5081         case KVM_GET_PIT2: {
5082                 r = -ENXIO;
5083                 if (!kvm->arch.vpit)
5084                         goto out;
5085                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5086                 if (r)
5087                         goto out;
5088                 r = -EFAULT;
5089                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5090                         goto out;
5091                 r = 0;
5092                 break;
5093         }
5094         case KVM_SET_PIT2: {
5095                 r = -EFAULT;
5096                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5097                         goto out;
5098                 mutex_lock(&kvm->lock);
5099                 r = -ENXIO;
5100                 if (!kvm->arch.vpit)
5101                         goto set_pit2_out;
5102                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5103 set_pit2_out:
5104                 mutex_unlock(&kvm->lock);
5105                 break;
5106         }
5107         case KVM_REINJECT_CONTROL: {
5108                 struct kvm_reinject_control control;
5109                 r =  -EFAULT;
5110                 if (copy_from_user(&control, argp, sizeof(control)))
5111                         goto out;
5112                 r = -ENXIO;
5113                 if (!kvm->arch.vpit)
5114                         goto out;
5115                 r = kvm_vm_ioctl_reinject(kvm, &control);
5116                 break;
5117         }
5118         case KVM_SET_BOOT_CPU_ID:
5119                 r = 0;
5120                 mutex_lock(&kvm->lock);
5121                 if (kvm->created_vcpus)
5122                         r = -EBUSY;
5123                 else
5124                         kvm->arch.bsp_vcpu_id = arg;
5125                 mutex_unlock(&kvm->lock);
5126                 break;
5127         case KVM_XEN_HVM_CONFIG: {
5128                 struct kvm_xen_hvm_config xhc;
5129                 r = -EFAULT;
5130                 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5131                         goto out;
5132                 r = -EINVAL;
5133                 if (xhc.flags)
5134                         goto out;
5135                 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5136                 r = 0;
5137                 break;
5138         }
5139         case KVM_SET_CLOCK: {
5140                 struct kvm_clock_data user_ns;
5141                 u64 now_ns;
5142
5143                 r = -EFAULT;
5144                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5145                         goto out;
5146
5147                 r = -EINVAL;
5148                 if (user_ns.flags)
5149                         goto out;
5150
5151                 r = 0;
5152                 /*
5153                  * TODO: userspace has to take care of races with VCPU_RUN, so
5154                  * kvm_gen_update_masterclock() can be cut down to locked
5155                  * pvclock_update_vm_gtod_copy().
5156                  */
5157                 kvm_gen_update_masterclock(kvm);
5158                 now_ns = get_kvmclock_ns(kvm);
5159                 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5160                 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5161                 break;
5162         }
5163         case KVM_GET_CLOCK: {
5164                 struct kvm_clock_data user_ns;
5165                 u64 now_ns;
5166
5167                 now_ns = get_kvmclock_ns(kvm);
5168                 user_ns.clock = now_ns;
5169                 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5170                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5171
5172                 r = -EFAULT;
5173                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5174                         goto out;
5175                 r = 0;
5176                 break;
5177         }
5178         case KVM_MEMORY_ENCRYPT_OP: {
5179                 r = -ENOTTY;
5180                 if (kvm_x86_ops.mem_enc_op)
5181                         r = kvm_x86_ops.mem_enc_op(kvm, argp);
5182                 break;
5183         }
5184         case KVM_MEMORY_ENCRYPT_REG_REGION: {
5185                 struct kvm_enc_region region;
5186
5187                 r = -EFAULT;
5188                 if (copy_from_user(&region, argp, sizeof(region)))
5189                         goto out;
5190
5191                 r = -ENOTTY;
5192                 if (kvm_x86_ops.mem_enc_reg_region)
5193                         r = kvm_x86_ops.mem_enc_reg_region(kvm, &region);
5194                 break;
5195         }
5196         case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5197                 struct kvm_enc_region region;
5198
5199                 r = -EFAULT;
5200                 if (copy_from_user(&region, argp, sizeof(region)))
5201                         goto out;
5202
5203                 r = -ENOTTY;
5204                 if (kvm_x86_ops.mem_enc_unreg_region)
5205                         r = kvm_x86_ops.mem_enc_unreg_region(kvm, &region);
5206                 break;
5207         }
5208         case KVM_HYPERV_EVENTFD: {
5209                 struct kvm_hyperv_eventfd hvevfd;
5210
5211                 r = -EFAULT;
5212                 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5213                         goto out;
5214                 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5215                 break;
5216         }
5217         case KVM_SET_PMU_EVENT_FILTER:
5218                 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5219                 break;
5220         default:
5221                 r = -ENOTTY;
5222         }
5223 out:
5224         return r;
5225 }
5226
5227 static void kvm_init_msr_list(void)
5228 {
5229         struct x86_pmu_capability x86_pmu;
5230         u32 dummy[2];
5231         unsigned i;
5232
5233         BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5234                          "Please update the fixed PMCs in msrs_to_saved_all[]");
5235
5236         perf_get_x86_pmu_capability(&x86_pmu);
5237
5238         num_msrs_to_save = 0;
5239         num_emulated_msrs = 0;
5240         num_msr_based_features = 0;
5241
5242         for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5243                 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5244                         continue;
5245
5246                 /*
5247                  * Even MSRs that are valid in the host may not be exposed
5248                  * to the guests in some cases.
5249                  */
5250                 switch (msrs_to_save_all[i]) {
5251                 case MSR_IA32_BNDCFGS:
5252                         if (!kvm_mpx_supported())
5253                                 continue;
5254                         break;
5255                 case MSR_TSC_AUX:
5256                         if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5257                                 continue;
5258                         break;
5259                 case MSR_IA32_RTIT_CTL:
5260                 case MSR_IA32_RTIT_STATUS:
5261                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5262                                 continue;
5263                         break;
5264                 case MSR_IA32_RTIT_CR3_MATCH:
5265                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5266                             !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5267                                 continue;
5268                         break;
5269                 case MSR_IA32_RTIT_OUTPUT_BASE:
5270                 case MSR_IA32_RTIT_OUTPUT_MASK:
5271                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5272                                 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5273                                  !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5274                                 continue;
5275                         break;
5276                 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5277                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5278                                 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5279                                 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5280                                 continue;
5281                         break;
5282                 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5283                         if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5284                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5285                                 continue;
5286                         break;
5287                 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5288                         if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5289                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5290                                 continue;
5291                 }
5292                 default:
5293                         break;
5294                 }
5295
5296                 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5297         }
5298
5299         for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5300                 if (!kvm_x86_ops.has_emulated_msr(emulated_msrs_all[i]))
5301                         continue;
5302
5303                 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5304         }
5305
5306         for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5307                 struct kvm_msr_entry msr;
5308
5309                 msr.index = msr_based_features_all[i];
5310                 if (kvm_get_msr_feature(&msr))
5311                         continue;
5312
5313                 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5314         }
5315 }
5316
5317 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5318                            const void *v)
5319 {
5320         int handled = 0;
5321         int n;
5322
5323         do {
5324                 n = min(len, 8);
5325                 if (!(lapic_in_kernel(vcpu) &&
5326                       !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5327                     && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5328                         break;
5329                 handled += n;
5330                 addr += n;
5331                 len -= n;
5332                 v += n;
5333         } while (len);
5334
5335         return handled;
5336 }
5337
5338 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5339 {
5340         int handled = 0;
5341         int n;
5342
5343         do {
5344                 n = min(len, 8);
5345                 if (!(lapic_in_kernel(vcpu) &&
5346                       !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5347                                          addr, n, v))
5348                     && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5349                         break;
5350                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5351                 handled += n;
5352                 addr += n;
5353                 len -= n;
5354                 v += n;
5355         } while (len);
5356
5357         return handled;
5358 }
5359
5360 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5361                         struct kvm_segment *var, int seg)
5362 {
5363         kvm_x86_ops.set_segment(vcpu, var, seg);
5364 }
5365
5366 void kvm_get_segment(struct kvm_vcpu *vcpu,
5367                      struct kvm_segment *var, int seg)
5368 {
5369         kvm_x86_ops.get_segment(vcpu, var, seg);
5370 }
5371
5372 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5373                            struct x86_exception *exception)
5374 {
5375         gpa_t t_gpa;
5376
5377         BUG_ON(!mmu_is_nested(vcpu));
5378
5379         /* NPT walks are always user-walks */
5380         access |= PFERR_USER_MASK;
5381         t_gpa  = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5382
5383         return t_gpa;
5384 }
5385
5386 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5387                               struct x86_exception *exception)
5388 {
5389         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5390         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5391 }
5392
5393  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5394                                 struct x86_exception *exception)
5395 {
5396         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5397         access |= PFERR_FETCH_MASK;
5398         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5399 }
5400
5401 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5402                                struct x86_exception *exception)
5403 {
5404         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5405         access |= PFERR_WRITE_MASK;
5406         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5407 }
5408
5409 /* uses this to access any guest's mapped memory without checking CPL */
5410 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5411                                 struct x86_exception *exception)
5412 {
5413         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5414 }
5415
5416 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5417                                       struct kvm_vcpu *vcpu, u32 access,
5418                                       struct x86_exception *exception)
5419 {
5420         void *data = val;
5421         int r = X86EMUL_CONTINUE;
5422
5423         while (bytes) {
5424                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5425                                                             exception);
5426                 unsigned offset = addr & (PAGE_SIZE-1);
5427                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5428                 int ret;
5429
5430                 if (gpa == UNMAPPED_GVA)
5431                         return X86EMUL_PROPAGATE_FAULT;
5432                 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5433                                                offset, toread);
5434                 if (ret < 0) {
5435                         r = X86EMUL_IO_NEEDED;
5436                         goto out;
5437                 }
5438
5439                 bytes -= toread;
5440                 data += toread;
5441                 addr += toread;
5442         }
5443 out:
5444         return r;
5445 }
5446
5447 /* used for instruction fetching */
5448 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5449                                 gva_t addr, void *val, unsigned int bytes,
5450                                 struct x86_exception *exception)
5451 {
5452         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5453         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5454         unsigned offset;
5455         int ret;
5456
5457         /* Inline kvm_read_guest_virt_helper for speed.  */
5458         gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5459                                                     exception);
5460         if (unlikely(gpa == UNMAPPED_GVA))
5461                 return X86EMUL_PROPAGATE_FAULT;
5462
5463         offset = addr & (PAGE_SIZE-1);
5464         if (WARN_ON(offset + bytes > PAGE_SIZE))
5465                 bytes = (unsigned)PAGE_SIZE - offset;
5466         ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5467                                        offset, bytes);
5468         if (unlikely(ret < 0))
5469                 return X86EMUL_IO_NEEDED;
5470
5471         return X86EMUL_CONTINUE;
5472 }
5473
5474 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5475                                gva_t addr, void *val, unsigned int bytes,
5476                                struct x86_exception *exception)
5477 {
5478         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5479
5480         /*
5481          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5482          * is returned, but our callers are not ready for that and they blindly
5483          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5484          * uninitialized kernel stack memory into cr2 and error code.
5485          */
5486         memset(exception, 0, sizeof(*exception));
5487         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5488                                           exception);
5489 }
5490 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5491
5492 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5493                              gva_t addr, void *val, unsigned int bytes,
5494                              struct x86_exception *exception, bool system)
5495 {
5496         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5497         u32 access = 0;
5498
5499         if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5500                 access |= PFERR_USER_MASK;
5501
5502         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5503 }
5504
5505 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5506                 unsigned long addr, void *val, unsigned int bytes)
5507 {
5508         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5509         int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5510
5511         return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5512 }
5513
5514 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5515                                       struct kvm_vcpu *vcpu, u32 access,
5516                                       struct x86_exception *exception)
5517 {
5518         void *data = val;
5519         int r = X86EMUL_CONTINUE;
5520
5521         while (bytes) {
5522                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5523                                                              access,
5524                                                              exception);
5525                 unsigned offset = addr & (PAGE_SIZE-1);
5526                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5527                 int ret;
5528
5529                 if (gpa == UNMAPPED_GVA)
5530                         return X86EMUL_PROPAGATE_FAULT;
5531                 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5532                 if (ret < 0) {
5533                         r = X86EMUL_IO_NEEDED;
5534                         goto out;
5535                 }
5536
5537                 bytes -= towrite;
5538                 data += towrite;
5539                 addr += towrite;
5540         }
5541 out:
5542         return r;
5543 }
5544
5545 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5546                               unsigned int bytes, struct x86_exception *exception,
5547                               bool system)
5548 {
5549         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5550         u32 access = PFERR_WRITE_MASK;
5551
5552         if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5553                 access |= PFERR_USER_MASK;
5554
5555         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5556                                            access, exception);
5557 }
5558
5559 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5560                                 unsigned int bytes, struct x86_exception *exception)
5561 {
5562         /* kvm_write_guest_virt_system can pull in tons of pages. */
5563         vcpu->arch.l1tf_flush_l1d = true;
5564
5565         /*
5566          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5567          * is returned, but our callers are not ready for that and they blindly
5568          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5569          * uninitialized kernel stack memory into cr2 and error code.
5570          */
5571         memset(exception, 0, sizeof(*exception));
5572         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5573                                            PFERR_WRITE_MASK, exception);
5574 }
5575 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5576
5577 int handle_ud(struct kvm_vcpu *vcpu)
5578 {
5579         static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
5580         int emul_type = EMULTYPE_TRAP_UD;
5581         char sig[5]; /* ud2; .ascii "kvm" */
5582         struct x86_exception e;
5583
5584         if (force_emulation_prefix &&
5585             kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5586                                 sig, sizeof(sig), &e) == 0 &&
5587             memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
5588                 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5589                 emul_type = EMULTYPE_TRAP_UD_FORCED;
5590         }
5591
5592         return kvm_emulate_instruction(vcpu, emul_type);
5593 }
5594 EXPORT_SYMBOL_GPL(handle_ud);
5595
5596 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5597                             gpa_t gpa, bool write)
5598 {
5599         /* For APIC access vmexit */
5600         if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5601                 return 1;
5602
5603         if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5604                 trace_vcpu_match_mmio(gva, gpa, write, true);
5605                 return 1;
5606         }
5607
5608         return 0;
5609 }
5610
5611 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5612                                 gpa_t *gpa, struct x86_exception *exception,
5613                                 bool write)
5614 {
5615         u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5616                 | (write ? PFERR_WRITE_MASK : 0);
5617
5618         /*
5619          * currently PKRU is only applied to ept enabled guest so
5620          * there is no pkey in EPT page table for L1 guest or EPT
5621          * shadow page table for L2 guest.
5622          */
5623         if (vcpu_match_mmio_gva(vcpu, gva)
5624             && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5625                                  vcpu->arch.mmio_access, 0, access)) {
5626                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5627                                         (gva & (PAGE_SIZE - 1));
5628                 trace_vcpu_match_mmio(gva, *gpa, write, false);
5629                 return 1;
5630         }
5631
5632         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5633
5634         if (*gpa == UNMAPPED_GVA)
5635                 return -1;
5636
5637         return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5638 }
5639
5640 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5641                         const void *val, int bytes)
5642 {
5643         int ret;
5644
5645         ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5646         if (ret < 0)
5647                 return 0;
5648         kvm_page_track_write(vcpu, gpa, val, bytes);
5649         return 1;
5650 }
5651
5652 struct read_write_emulator_ops {
5653         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5654                                   int bytes);
5655         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5656                                   void *val, int bytes);
5657         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5658                                int bytes, void *val);
5659         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5660                                     void *val, int bytes);
5661         bool write;
5662 };
5663
5664 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5665 {
5666         if (vcpu->mmio_read_completed) {
5667                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5668                                vcpu->mmio_fragments[0].gpa, val);
5669                 vcpu->mmio_read_completed = 0;
5670                 return 1;
5671         }
5672
5673         return 0;
5674 }
5675
5676 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5677                         void *val, int bytes)
5678 {
5679         return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5680 }
5681
5682 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5683                          void *val, int bytes)
5684 {
5685         return emulator_write_phys(vcpu, gpa, val, bytes);
5686 }
5687
5688 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5689 {
5690         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5691         return vcpu_mmio_write(vcpu, gpa, bytes, val);
5692 }
5693
5694 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5695                           void *val, int bytes)
5696 {
5697         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5698         return X86EMUL_IO_NEEDED;
5699 }
5700
5701 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5702                            void *val, int bytes)
5703 {
5704         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5705
5706         memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5707         return X86EMUL_CONTINUE;
5708 }
5709
5710 static const struct read_write_emulator_ops read_emultor = {
5711         .read_write_prepare = read_prepare,
5712         .read_write_emulate = read_emulate,
5713         .read_write_mmio = vcpu_mmio_read,
5714         .read_write_exit_mmio = read_exit_mmio,
5715 };
5716
5717 static const struct read_write_emulator_ops write_emultor = {
5718         .read_write_emulate = write_emulate,
5719         .read_write_mmio = write_mmio,
5720         .read_write_exit_mmio = write_exit_mmio,
5721         .write = true,
5722 };
5723
5724 static int emulator_read_write_onepage(unsigned long addr, void *val,
5725                                        unsigned int bytes,
5726                                        struct x86_exception *exception,
5727                                        struct kvm_vcpu *vcpu,
5728                                        const struct read_write_emulator_ops *ops)
5729 {
5730         gpa_t gpa;
5731         int handled, ret;
5732         bool write = ops->write;
5733         struct kvm_mmio_fragment *frag;
5734         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
5735
5736         /*
5737          * If the exit was due to a NPF we may already have a GPA.
5738          * If the GPA is present, use it to avoid the GVA to GPA table walk.
5739          * Note, this cannot be used on string operations since string
5740          * operation using rep will only have the initial GPA from the NPF
5741          * occurred.
5742          */
5743         if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
5744             (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
5745                 gpa = ctxt->gpa_val;
5746                 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5747         } else {
5748                 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5749                 if (ret < 0)
5750                         return X86EMUL_PROPAGATE_FAULT;
5751         }
5752
5753         if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5754                 return X86EMUL_CONTINUE;
5755
5756         /*
5757          * Is this MMIO handled locally?
5758          */
5759         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5760         if (handled == bytes)
5761                 return X86EMUL_CONTINUE;
5762
5763         gpa += handled;
5764         bytes -= handled;
5765         val += handled;
5766
5767         WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5768         frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5769         frag->gpa = gpa;
5770         frag->data = val;
5771         frag->len = bytes;
5772         return X86EMUL_CONTINUE;
5773 }
5774
5775 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5776                         unsigned long addr,
5777                         void *val, unsigned int bytes,
5778                         struct x86_exception *exception,
5779                         const struct read_write_emulator_ops *ops)
5780 {
5781         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5782         gpa_t gpa;
5783         int rc;
5784
5785         if (ops->read_write_prepare &&
5786                   ops->read_write_prepare(vcpu, val, bytes))
5787                 return X86EMUL_CONTINUE;
5788
5789         vcpu->mmio_nr_fragments = 0;
5790
5791         /* Crossing a page boundary? */
5792         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5793                 int now;
5794
5795                 now = -addr & ~PAGE_MASK;
5796                 rc = emulator_read_write_onepage(addr, val, now, exception,
5797                                                  vcpu, ops);
5798
5799                 if (rc != X86EMUL_CONTINUE)
5800                         return rc;
5801                 addr += now;
5802                 if (ctxt->mode != X86EMUL_MODE_PROT64)
5803                         addr = (u32)addr;
5804                 val += now;
5805                 bytes -= now;
5806         }
5807
5808         rc = emulator_read_write_onepage(addr, val, bytes, exception,
5809                                          vcpu, ops);
5810         if (rc != X86EMUL_CONTINUE)
5811                 return rc;
5812
5813         if (!vcpu->mmio_nr_fragments)
5814                 return rc;
5815
5816         gpa = vcpu->mmio_fragments[0].gpa;
5817
5818         vcpu->mmio_needed = 1;
5819         vcpu->mmio_cur_fragment = 0;
5820
5821         vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5822         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5823         vcpu->run->exit_reason = KVM_EXIT_MMIO;
5824         vcpu->run->mmio.phys_addr = gpa;
5825
5826         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5827 }
5828
5829 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5830                                   unsigned long addr,
5831                                   void *val,
5832                                   unsigned int bytes,
5833                                   struct x86_exception *exception)
5834 {
5835         return emulator_read_write(ctxt, addr, val, bytes,
5836                                    exception, &read_emultor);
5837 }
5838
5839 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5840                             unsigned long addr,
5841                             const void *val,
5842                             unsigned int bytes,
5843                             struct x86_exception *exception)
5844 {
5845         return emulator_read_write(ctxt, addr, (void *)val, bytes,
5846                                    exception, &write_emultor);
5847 }
5848
5849 #define CMPXCHG_TYPE(t, ptr, old, new) \
5850         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5851
5852 #ifdef CONFIG_X86_64
5853 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5854 #else
5855 #  define CMPXCHG64(ptr, old, new) \
5856         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5857 #endif
5858
5859 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5860                                      unsigned long addr,
5861                                      const void *old,
5862                                      const void *new,
5863                                      unsigned int bytes,
5864                                      struct x86_exception *exception)
5865 {
5866         struct kvm_host_map map;
5867         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5868         u64 page_line_mask;
5869         gpa_t gpa;
5870         char *kaddr;
5871         bool exchanged;
5872
5873         /* guests cmpxchg8b have to be emulated atomically */
5874         if (bytes > 8 || (bytes & (bytes - 1)))
5875                 goto emul_write;
5876
5877         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5878
5879         if (gpa == UNMAPPED_GVA ||
5880             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5881                 goto emul_write;
5882
5883         /*
5884          * Emulate the atomic as a straight write to avoid #AC if SLD is
5885          * enabled in the host and the access splits a cache line.
5886          */
5887         if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
5888                 page_line_mask = ~(cache_line_size() - 1);
5889         else
5890                 page_line_mask = PAGE_MASK;
5891
5892         if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
5893                 goto emul_write;
5894
5895         if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5896                 goto emul_write;
5897
5898         kaddr = map.hva + offset_in_page(gpa);
5899
5900         switch (bytes) {
5901         case 1:
5902                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5903                 break;
5904         case 2:
5905                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5906                 break;
5907         case 4:
5908                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5909                 break;
5910         case 8:
5911                 exchanged = CMPXCHG64(kaddr, old, new);
5912                 break;
5913         default:
5914                 BUG();
5915         }
5916
5917         kvm_vcpu_unmap(vcpu, &map, true);
5918
5919         if (!exchanged)
5920                 return X86EMUL_CMPXCHG_FAILED;
5921
5922         kvm_page_track_write(vcpu, gpa, new, bytes);
5923
5924         return X86EMUL_CONTINUE;
5925
5926 emul_write:
5927         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5928
5929         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5930 }
5931
5932 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5933 {
5934         int r = 0, i;
5935
5936         for (i = 0; i < vcpu->arch.pio.count; i++) {
5937                 if (vcpu->arch.pio.in)
5938                         r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5939                                             vcpu->arch.pio.size, pd);
5940                 else
5941                         r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5942                                              vcpu->arch.pio.port, vcpu->arch.pio.size,
5943                                              pd);
5944                 if (r)
5945                         break;
5946                 pd += vcpu->arch.pio.size;
5947         }
5948         return r;
5949 }
5950
5951 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5952                                unsigned short port, void *val,
5953                                unsigned int count, bool in)
5954 {
5955         vcpu->arch.pio.port = port;
5956         vcpu->arch.pio.in = in;
5957         vcpu->arch.pio.count  = count;
5958         vcpu->arch.pio.size = size;
5959
5960         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5961                 vcpu->arch.pio.count = 0;
5962                 return 1;
5963         }
5964
5965         vcpu->run->exit_reason = KVM_EXIT_IO;
5966         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5967         vcpu->run->io.size = size;
5968         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5969         vcpu->run->io.count = count;
5970         vcpu->run->io.port = port;
5971
5972         return 0;
5973 }
5974
5975 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
5976                            unsigned short port, void *val, unsigned int count)
5977 {
5978         int ret;
5979
5980         if (vcpu->arch.pio.count)
5981                 goto data_avail;
5982
5983         memset(vcpu->arch.pio_data, 0, size * count);
5984
5985         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5986         if (ret) {
5987 data_avail:
5988                 memcpy(val, vcpu->arch.pio_data, size * count);
5989                 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5990                 vcpu->arch.pio.count = 0;
5991                 return 1;
5992         }
5993
5994         return 0;
5995 }
5996
5997 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5998                                     int size, unsigned short port, void *val,
5999                                     unsigned int count)
6000 {
6001         return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
6002
6003 }
6004
6005 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
6006                             unsigned short port, const void *val,
6007                             unsigned int count)
6008 {
6009         memcpy(vcpu->arch.pio_data, val, size * count);
6010         trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6011         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6012 }
6013
6014 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
6015                                      int size, unsigned short port,
6016                                      const void *val, unsigned int count)
6017 {
6018         return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
6019 }
6020
6021 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6022 {
6023         return kvm_x86_ops.get_segment_base(vcpu, seg);
6024 }
6025
6026 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6027 {
6028         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6029 }
6030
6031 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6032 {
6033         if (!need_emulate_wbinvd(vcpu))
6034                 return X86EMUL_CONTINUE;
6035
6036         if (kvm_x86_ops.has_wbinvd_exit()) {
6037                 int cpu = get_cpu();
6038
6039                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6040                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6041                                 wbinvd_ipi, NULL, 1);
6042                 put_cpu();
6043                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6044         } else
6045                 wbinvd();
6046         return X86EMUL_CONTINUE;
6047 }
6048
6049 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6050 {
6051         kvm_emulate_wbinvd_noskip(vcpu);
6052         return kvm_skip_emulated_instruction(vcpu);
6053 }
6054 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6055
6056
6057
6058 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6059 {
6060         kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6061 }
6062
6063 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6064                            unsigned long *dest)
6065 {
6066         return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6067 }
6068
6069 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6070                            unsigned long value)
6071 {
6072
6073         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6074 }
6075
6076 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6077 {
6078         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6079 }
6080
6081 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6082 {
6083         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6084         unsigned long value;
6085
6086         switch (cr) {
6087         case 0:
6088                 value = kvm_read_cr0(vcpu);
6089                 break;
6090         case 2:
6091                 value = vcpu->arch.cr2;
6092                 break;
6093         case 3:
6094                 value = kvm_read_cr3(vcpu);
6095                 break;
6096         case 4:
6097                 value = kvm_read_cr4(vcpu);
6098                 break;
6099         case 8:
6100                 value = kvm_get_cr8(vcpu);
6101                 break;
6102         default:
6103                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6104                 return 0;
6105         }
6106
6107         return value;
6108 }
6109
6110 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6111 {
6112         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6113         int res = 0;
6114
6115         switch (cr) {
6116         case 0:
6117                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6118                 break;
6119         case 2:
6120                 vcpu->arch.cr2 = val;
6121                 break;
6122         case 3:
6123                 res = kvm_set_cr3(vcpu, val);
6124                 break;
6125         case 4:
6126                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6127                 break;
6128         case 8:
6129                 res = kvm_set_cr8(vcpu, val);
6130                 break;
6131         default:
6132                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6133                 res = -1;
6134         }
6135
6136         return res;
6137 }
6138
6139 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6140 {
6141         return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt));
6142 }
6143
6144 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6145 {
6146         kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt);
6147 }
6148
6149 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6150 {
6151         kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt);
6152 }
6153
6154 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6155 {
6156         kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt);
6157 }
6158
6159 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6160 {
6161         kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt);
6162 }
6163
6164 static unsigned long emulator_get_cached_segment_base(
6165         struct x86_emulate_ctxt *ctxt, int seg)
6166 {
6167         return get_segment_base(emul_to_vcpu(ctxt), seg);
6168 }
6169
6170 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6171                                  struct desc_struct *desc, u32 *base3,
6172                                  int seg)
6173 {
6174         struct kvm_segment var;
6175
6176         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6177         *selector = var.selector;
6178
6179         if (var.unusable) {
6180                 memset(desc, 0, sizeof(*desc));
6181                 if (base3)
6182                         *base3 = 0;
6183                 return false;
6184         }
6185
6186         if (var.g)
6187                 var.limit >>= 12;
6188         set_desc_limit(desc, var.limit);
6189         set_desc_base(desc, (unsigned long)var.base);
6190 #ifdef CONFIG_X86_64
6191         if (base3)
6192                 *base3 = var.base >> 32;
6193 #endif
6194         desc->type = var.type;
6195         desc->s = var.s;
6196         desc->dpl = var.dpl;
6197         desc->p = var.present;
6198         desc->avl = var.avl;
6199         desc->l = var.l;
6200         desc->d = var.db;
6201         desc->g = var.g;
6202
6203         return true;
6204 }
6205
6206 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6207                                  struct desc_struct *desc, u32 base3,
6208                                  int seg)
6209 {
6210         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6211         struct kvm_segment var;
6212
6213         var.selector = selector;
6214         var.base = get_desc_base(desc);
6215 #ifdef CONFIG_X86_64
6216         var.base |= ((u64)base3) << 32;
6217 #endif
6218         var.limit = get_desc_limit(desc);
6219         if (desc->g)
6220                 var.limit = (var.limit << 12) | 0xfff;
6221         var.type = desc->type;
6222         var.dpl = desc->dpl;
6223         var.db = desc->d;
6224         var.s = desc->s;
6225         var.l = desc->l;
6226         var.g = desc->g;
6227         var.avl = desc->avl;
6228         var.present = desc->p;
6229         var.unusable = !var.present;
6230         var.padding = 0;
6231
6232         kvm_set_segment(vcpu, &var, seg);
6233         return;
6234 }
6235
6236 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6237                             u32 msr_index, u64 *pdata)
6238 {
6239         return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6240 }
6241
6242 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6243                             u32 msr_index, u64 data)
6244 {
6245         return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6246 }
6247
6248 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6249 {
6250         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6251
6252         return vcpu->arch.smbase;
6253 }
6254
6255 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6256 {
6257         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6258
6259         vcpu->arch.smbase = smbase;
6260 }
6261
6262 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6263                               u32 pmc)
6264 {
6265         return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6266 }
6267
6268 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6269                              u32 pmc, u64 *pdata)
6270 {
6271         return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6272 }
6273
6274 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6275 {
6276         emul_to_vcpu(ctxt)->arch.halt_request = 1;
6277 }
6278
6279 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6280                               struct x86_instruction_info *info,
6281                               enum x86_intercept_stage stage)
6282 {
6283         return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage,
6284                                             &ctxt->exception);
6285 }
6286
6287 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6288                               u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6289                               bool exact_only)
6290 {
6291         return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6292 }
6293
6294 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6295 {
6296         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6297 }
6298
6299 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6300 {
6301         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6302 }
6303
6304 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6305 {
6306         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6307 }
6308
6309 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6310 {
6311         return kvm_register_read(emul_to_vcpu(ctxt), reg);
6312 }
6313
6314 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6315 {
6316         kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6317 }
6318
6319 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6320 {
6321         kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked);
6322 }
6323
6324 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6325 {
6326         return emul_to_vcpu(ctxt)->arch.hflags;
6327 }
6328
6329 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6330 {
6331         emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6332 }
6333
6334 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6335                                   const char *smstate)
6336 {
6337         return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6338 }
6339
6340 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6341 {
6342         kvm_smm_changed(emul_to_vcpu(ctxt));
6343 }
6344
6345 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6346 {
6347         return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6348 }
6349
6350 static const struct x86_emulate_ops emulate_ops = {
6351         .read_gpr            = emulator_read_gpr,
6352         .write_gpr           = emulator_write_gpr,
6353         .read_std            = emulator_read_std,
6354         .write_std           = emulator_write_std,
6355         .read_phys           = kvm_read_guest_phys_system,
6356         .fetch               = kvm_fetch_guest_virt,
6357         .read_emulated       = emulator_read_emulated,
6358         .write_emulated      = emulator_write_emulated,
6359         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
6360         .invlpg              = emulator_invlpg,
6361         .pio_in_emulated     = emulator_pio_in_emulated,
6362         .pio_out_emulated    = emulator_pio_out_emulated,
6363         .get_segment         = emulator_get_segment,
6364         .set_segment         = emulator_set_segment,
6365         .get_cached_segment_base = emulator_get_cached_segment_base,
6366         .get_gdt             = emulator_get_gdt,
6367         .get_idt             = emulator_get_idt,
6368         .set_gdt             = emulator_set_gdt,
6369         .set_idt             = emulator_set_idt,
6370         .get_cr              = emulator_get_cr,
6371         .set_cr              = emulator_set_cr,
6372         .cpl                 = emulator_get_cpl,
6373         .get_dr              = emulator_get_dr,
6374         .set_dr              = emulator_set_dr,
6375         .get_smbase          = emulator_get_smbase,
6376         .set_smbase          = emulator_set_smbase,
6377         .set_msr             = emulator_set_msr,
6378         .get_msr             = emulator_get_msr,
6379         .check_pmc           = emulator_check_pmc,
6380         .read_pmc            = emulator_read_pmc,
6381         .halt                = emulator_halt,
6382         .wbinvd              = emulator_wbinvd,
6383         .fix_hypercall       = emulator_fix_hypercall,
6384         .intercept           = emulator_intercept,
6385         .get_cpuid           = emulator_get_cpuid,
6386         .guest_has_long_mode = emulator_guest_has_long_mode,
6387         .guest_has_movbe     = emulator_guest_has_movbe,
6388         .guest_has_fxsr      = emulator_guest_has_fxsr,
6389         .set_nmi_mask        = emulator_set_nmi_mask,
6390         .get_hflags          = emulator_get_hflags,
6391         .set_hflags          = emulator_set_hflags,
6392         .pre_leave_smm       = emulator_pre_leave_smm,
6393         .post_leave_smm      = emulator_post_leave_smm,
6394         .set_xcr             = emulator_set_xcr,
6395 };
6396
6397 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6398 {
6399         u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
6400         /*
6401          * an sti; sti; sequence only disable interrupts for the first
6402          * instruction. So, if the last instruction, be it emulated or
6403          * not, left the system with the INT_STI flag enabled, it
6404          * means that the last instruction is an sti. We should not
6405          * leave the flag on in this case. The same goes for mov ss
6406          */
6407         if (int_shadow & mask)
6408                 mask = 0;
6409         if (unlikely(int_shadow || mask)) {
6410                 kvm_x86_ops.set_interrupt_shadow(vcpu, mask);
6411                 if (!mask)
6412                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6413         }
6414 }
6415
6416 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6417 {
6418         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6419         if (ctxt->exception.vector == PF_VECTOR)
6420                 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
6421
6422         if (ctxt->exception.error_code_valid)
6423                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6424                                       ctxt->exception.error_code);
6425         else
6426                 kvm_queue_exception(vcpu, ctxt->exception.vector);
6427         return false;
6428 }
6429
6430 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6431 {
6432         struct x86_emulate_ctxt *ctxt;
6433
6434         ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6435         if (!ctxt) {
6436                 pr_err("kvm: failed to allocate vcpu's emulator\n");
6437                 return NULL;
6438         }
6439
6440         ctxt->vcpu = vcpu;
6441         ctxt->ops = &emulate_ops;
6442         vcpu->arch.emulate_ctxt = ctxt;
6443
6444         return ctxt;
6445 }
6446
6447 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6448 {
6449         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6450         int cs_db, cs_l;
6451
6452         kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6453
6454         ctxt->gpa_available = false;
6455         ctxt->eflags = kvm_get_rflags(vcpu);
6456         ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6457
6458         ctxt->eip = kvm_rip_read(vcpu);
6459         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
6460                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
6461                      (cs_l && is_long_mode(vcpu))       ? X86EMUL_MODE_PROT64 :
6462                      cs_db                              ? X86EMUL_MODE_PROT32 :
6463                                                           X86EMUL_MODE_PROT16;
6464         BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6465         BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6466         BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6467
6468         init_decode_cache(ctxt);
6469         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6470 }
6471
6472 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6473 {
6474         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6475         int ret;
6476
6477         init_emulate_ctxt(vcpu);
6478
6479         ctxt->op_bytes = 2;
6480         ctxt->ad_bytes = 2;
6481         ctxt->_eip = ctxt->eip + inc_eip;
6482         ret = emulate_int_real(ctxt, irq);
6483
6484         if (ret != X86EMUL_CONTINUE) {
6485                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6486         } else {
6487                 ctxt->eip = ctxt->_eip;
6488                 kvm_rip_write(vcpu, ctxt->eip);
6489                 kvm_set_rflags(vcpu, ctxt->eflags);
6490         }
6491 }
6492 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6493
6494 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6495 {
6496         ++vcpu->stat.insn_emulation_fail;
6497         trace_kvm_emulate_insn_failed(vcpu);
6498
6499         if (emulation_type & EMULTYPE_VMWARE_GP) {
6500                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6501                 return 1;
6502         }
6503
6504         if (emulation_type & EMULTYPE_SKIP) {
6505                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6506                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6507                 vcpu->run->internal.ndata = 0;
6508                 return 0;
6509         }
6510
6511         kvm_queue_exception(vcpu, UD_VECTOR);
6512
6513         if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) {
6514                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6515                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6516                 vcpu->run->internal.ndata = 0;
6517                 return 0;
6518         }
6519
6520         return 1;
6521 }
6522
6523 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6524                                   bool write_fault_to_shadow_pgtable,
6525                                   int emulation_type)
6526 {
6527         gpa_t gpa = cr2_or_gpa;
6528         kvm_pfn_t pfn;
6529
6530         if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6531                 return false;
6532
6533         if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6534             WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6535                 return false;
6536
6537         if (!vcpu->arch.mmu->direct_map) {
6538                 /*
6539                  * Write permission should be allowed since only
6540                  * write access need to be emulated.
6541                  */
6542                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6543
6544                 /*
6545                  * If the mapping is invalid in guest, let cpu retry
6546                  * it to generate fault.
6547                  */
6548                 if (gpa == UNMAPPED_GVA)
6549                         return true;
6550         }
6551
6552         /*
6553          * Do not retry the unhandleable instruction if it faults on the
6554          * readonly host memory, otherwise it will goto a infinite loop:
6555          * retry instruction -> write #PF -> emulation fail -> retry
6556          * instruction -> ...
6557          */
6558         pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6559
6560         /*
6561          * If the instruction failed on the error pfn, it can not be fixed,
6562          * report the error to userspace.
6563          */
6564         if (is_error_noslot_pfn(pfn))
6565                 return false;
6566
6567         kvm_release_pfn_clean(pfn);
6568
6569         /* The instructions are well-emulated on direct mmu. */
6570         if (vcpu->arch.mmu->direct_map) {
6571                 unsigned int indirect_shadow_pages;
6572
6573                 spin_lock(&vcpu->kvm->mmu_lock);
6574                 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6575                 spin_unlock(&vcpu->kvm->mmu_lock);
6576
6577                 if (indirect_shadow_pages)
6578                         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6579
6580                 return true;
6581         }
6582
6583         /*
6584          * if emulation was due to access to shadowed page table
6585          * and it failed try to unshadow page and re-enter the
6586          * guest to let CPU execute the instruction.
6587          */
6588         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6589
6590         /*
6591          * If the access faults on its page table, it can not
6592          * be fixed by unprotecting shadow page and it should
6593          * be reported to userspace.
6594          */
6595         return !write_fault_to_shadow_pgtable;
6596 }
6597
6598 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6599                               gpa_t cr2_or_gpa,  int emulation_type)
6600 {
6601         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6602         unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
6603
6604         last_retry_eip = vcpu->arch.last_retry_eip;
6605         last_retry_addr = vcpu->arch.last_retry_addr;
6606
6607         /*
6608          * If the emulation is caused by #PF and it is non-page_table
6609          * writing instruction, it means the VM-EXIT is caused by shadow
6610          * page protected, we can zap the shadow page and retry this
6611          * instruction directly.
6612          *
6613          * Note: if the guest uses a non-page-table modifying instruction
6614          * on the PDE that points to the instruction, then we will unmap
6615          * the instruction and go to an infinite loop. So, we cache the
6616          * last retried eip and the last fault address, if we meet the eip
6617          * and the address again, we can break out of the potential infinite
6618          * loop.
6619          */
6620         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6621
6622         if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6623                 return false;
6624
6625         if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6626             WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6627                 return false;
6628
6629         if (x86_page_table_writing_insn(ctxt))
6630                 return false;
6631
6632         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
6633                 return false;
6634
6635         vcpu->arch.last_retry_eip = ctxt->eip;
6636         vcpu->arch.last_retry_addr = cr2_or_gpa;
6637
6638         if (!vcpu->arch.mmu->direct_map)
6639                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6640
6641         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6642
6643         return true;
6644 }
6645
6646 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6647 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6648
6649 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6650 {
6651         if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6652                 /* This is a good place to trace that we are exiting SMM.  */
6653                 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6654
6655                 /* Process a latched INIT or SMI, if any.  */
6656                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6657         }
6658
6659         kvm_mmu_reset_context(vcpu);
6660 }
6661
6662 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6663                                 unsigned long *db)
6664 {
6665         u32 dr6 = 0;
6666         int i;
6667         u32 enable, rwlen;
6668
6669         enable = dr7;
6670         rwlen = dr7 >> 16;
6671         for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6672                 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6673                         dr6 |= (1 << i);
6674         return dr6;
6675 }
6676
6677 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6678 {
6679         struct kvm_run *kvm_run = vcpu->run;
6680
6681         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6682                 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6683                 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6684                 kvm_run->debug.arch.exception = DB_VECTOR;
6685                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6686                 return 0;
6687         }
6688         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6689         return 1;
6690 }
6691
6692 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6693 {
6694         unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
6695         int r;
6696
6697         r = kvm_x86_ops.skip_emulated_instruction(vcpu);
6698         if (unlikely(!r))
6699                 return 0;
6700
6701         /*
6702          * rflags is the old, "raw" value of the flags.  The new value has
6703          * not been saved yet.
6704          *
6705          * This is correct even for TF set by the guest, because "the
6706          * processor will not generate this exception after the instruction
6707          * that sets the TF flag".
6708          */
6709         if (unlikely(rflags & X86_EFLAGS_TF))
6710                 r = kvm_vcpu_do_singlestep(vcpu);
6711         return r;
6712 }
6713 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6714
6715 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6716 {
6717         if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6718             (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6719                 struct kvm_run *kvm_run = vcpu->run;
6720                 unsigned long eip = kvm_get_linear_rip(vcpu);
6721                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6722                                            vcpu->arch.guest_debug_dr7,
6723                                            vcpu->arch.eff_db);
6724
6725                 if (dr6 != 0) {
6726                         kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6727                         kvm_run->debug.arch.pc = eip;
6728                         kvm_run->debug.arch.exception = DB_VECTOR;
6729                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
6730                         *r = 0;
6731                         return true;
6732                 }
6733         }
6734
6735         if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6736             !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6737                 unsigned long eip = kvm_get_linear_rip(vcpu);
6738                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6739                                            vcpu->arch.dr7,
6740                                            vcpu->arch.db);
6741
6742                 if (dr6 != 0) {
6743                         kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
6744                         *r = 1;
6745                         return true;
6746                 }
6747         }
6748
6749         return false;
6750 }
6751
6752 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6753 {
6754         switch (ctxt->opcode_len) {
6755         case 1:
6756                 switch (ctxt->b) {
6757                 case 0xe4:      /* IN */
6758                 case 0xe5:
6759                 case 0xec:
6760                 case 0xed:
6761                 case 0xe6:      /* OUT */
6762                 case 0xe7:
6763                 case 0xee:
6764                 case 0xef:
6765                 case 0x6c:      /* INS */
6766                 case 0x6d:
6767                 case 0x6e:      /* OUTS */
6768                 case 0x6f:
6769                         return true;
6770                 }
6771                 break;
6772         case 2:
6773                 switch (ctxt->b) {
6774                 case 0x33:      /* RDPMC */
6775                         return true;
6776                 }
6777                 break;
6778         }
6779
6780         return false;
6781 }
6782
6783 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6784                             int emulation_type, void *insn, int insn_len)
6785 {
6786         int r;
6787         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6788         bool writeback = true;
6789         bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6790
6791         vcpu->arch.l1tf_flush_l1d = true;
6792
6793         /*
6794          * Clear write_fault_to_shadow_pgtable here to ensure it is
6795          * never reused.
6796          */
6797         vcpu->arch.write_fault_to_shadow_pgtable = false;
6798         kvm_clear_exception_queue(vcpu);
6799
6800         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6801                 init_emulate_ctxt(vcpu);
6802
6803                 /*
6804                  * We will reenter on the same instruction since
6805                  * we do not set complete_userspace_io.  This does not
6806                  * handle watchpoints yet, those would be handled in
6807                  * the emulate_ops.
6808                  */
6809                 if (!(emulation_type & EMULTYPE_SKIP) &&
6810                     kvm_vcpu_check_breakpoint(vcpu, &r))
6811                         return r;
6812
6813                 ctxt->interruptibility = 0;
6814                 ctxt->have_exception = false;
6815                 ctxt->exception.vector = -1;
6816                 ctxt->perm_ok = false;
6817
6818                 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6819
6820                 r = x86_decode_insn(ctxt, insn, insn_len);
6821
6822                 trace_kvm_emulate_insn_start(vcpu);
6823                 ++vcpu->stat.insn_emulation;
6824                 if (r != EMULATION_OK)  {
6825                         if ((emulation_type & EMULTYPE_TRAP_UD) ||
6826                             (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6827                                 kvm_queue_exception(vcpu, UD_VECTOR);
6828                                 return 1;
6829                         }
6830                         if (reexecute_instruction(vcpu, cr2_or_gpa,
6831                                                   write_fault_to_spt,
6832                                                   emulation_type))
6833                                 return 1;
6834                         if (ctxt->have_exception) {
6835                                 /*
6836                                  * #UD should result in just EMULATION_FAILED, and trap-like
6837                                  * exception should not be encountered during decode.
6838                                  */
6839                                 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6840                                              exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6841                                 inject_emulated_exception(vcpu);
6842                                 return 1;
6843                         }
6844                         return handle_emulation_failure(vcpu, emulation_type);
6845                 }
6846         }
6847
6848         if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6849             !is_vmware_backdoor_opcode(ctxt)) {
6850                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6851                 return 1;
6852         }
6853
6854         /*
6855          * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6856          * for kvm_skip_emulated_instruction().  The caller is responsible for
6857          * updating interruptibility state and injecting single-step #DBs.
6858          */
6859         if (emulation_type & EMULTYPE_SKIP) {
6860                 kvm_rip_write(vcpu, ctxt->_eip);
6861                 if (ctxt->eflags & X86_EFLAGS_RF)
6862                         kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6863                 return 1;
6864         }
6865
6866         if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
6867                 return 1;
6868
6869         /* this is needed for vmware backdoor interface to work since it
6870            changes registers values  during IO operation */
6871         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6872                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6873                 emulator_invalidate_register_cache(ctxt);
6874         }
6875
6876 restart:
6877         if (emulation_type & EMULTYPE_PF) {
6878                 /* Save the faulting GPA (cr2) in the address field */
6879                 ctxt->exception.address = cr2_or_gpa;
6880
6881                 /* With shadow page tables, cr2 contains a GVA or nGPA. */
6882                 if (vcpu->arch.mmu->direct_map) {
6883                         ctxt->gpa_available = true;
6884                         ctxt->gpa_val = cr2_or_gpa;
6885                 }
6886         } else {
6887                 /* Sanitize the address out of an abundance of paranoia. */
6888                 ctxt->exception.address = 0;
6889         }
6890
6891         r = x86_emulate_insn(ctxt);
6892
6893         if (r == EMULATION_INTERCEPTED)
6894                 return 1;
6895
6896         if (r == EMULATION_FAILED) {
6897                 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
6898                                         emulation_type))
6899                         return 1;
6900
6901                 return handle_emulation_failure(vcpu, emulation_type);
6902         }
6903
6904         if (ctxt->have_exception) {
6905                 r = 1;
6906                 if (inject_emulated_exception(vcpu))
6907                         return r;
6908         } else if (vcpu->arch.pio.count) {
6909                 if (!vcpu->arch.pio.in) {
6910                         /* FIXME: return into emulator if single-stepping.  */
6911                         vcpu->arch.pio.count = 0;
6912                 } else {
6913                         writeback = false;
6914                         vcpu->arch.complete_userspace_io = complete_emulated_pio;
6915                 }
6916                 r = 0;
6917         } else if (vcpu->mmio_needed) {
6918                 ++vcpu->stat.mmio_exits;
6919
6920                 if (!vcpu->mmio_is_write)
6921                         writeback = false;
6922                 r = 0;
6923                 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6924         } else if (r == EMULATION_RESTART)
6925                 goto restart;
6926         else
6927                 r = 1;
6928
6929         if (writeback) {
6930                 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
6931                 toggle_interruptibility(vcpu, ctxt->interruptibility);
6932                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6933                 if (!ctxt->have_exception ||
6934                     exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6935                         kvm_rip_write(vcpu, ctxt->eip);
6936                         if (r && ctxt->tf)
6937                                 r = kvm_vcpu_do_singlestep(vcpu);
6938                         if (kvm_x86_ops.update_emulated_instruction)
6939                                 kvm_x86_ops.update_emulated_instruction(vcpu);
6940                         __kvm_set_rflags(vcpu, ctxt->eflags);
6941                 }
6942
6943                 /*
6944                  * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6945                  * do nothing, and it will be requested again as soon as
6946                  * the shadow expires.  But we still need to check here,
6947                  * because POPF has no interrupt shadow.
6948                  */
6949                 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6950                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6951         } else
6952                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6953
6954         return r;
6955 }
6956
6957 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6958 {
6959         return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6960 }
6961 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6962
6963 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6964                                         void *insn, int insn_len)
6965 {
6966         return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6967 }
6968 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6969
6970 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6971 {
6972         vcpu->arch.pio.count = 0;
6973         return 1;
6974 }
6975
6976 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6977 {
6978         vcpu->arch.pio.count = 0;
6979
6980         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6981                 return 1;
6982
6983         return kvm_skip_emulated_instruction(vcpu);
6984 }
6985
6986 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6987                             unsigned short port)
6988 {
6989         unsigned long val = kvm_rax_read(vcpu);
6990         int ret = emulator_pio_out(vcpu, size, port, &val, 1);
6991
6992         if (ret)
6993                 return ret;
6994
6995         /*
6996          * Workaround userspace that relies on old KVM behavior of %rip being
6997          * incremented prior to exiting to userspace to handle "OUT 0x7e".
6998          */
6999         if (port == 0x7e &&
7000             kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
7001                 vcpu->arch.complete_userspace_io =
7002                         complete_fast_pio_out_port_0x7e;
7003                 kvm_skip_emulated_instruction(vcpu);
7004         } else {
7005                 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7006                 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
7007         }
7008         return 0;
7009 }
7010
7011 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
7012 {
7013         unsigned long val;
7014
7015         /* We should only ever be called with arch.pio.count equal to 1 */
7016         BUG_ON(vcpu->arch.pio.count != 1);
7017
7018         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
7019                 vcpu->arch.pio.count = 0;
7020                 return 1;
7021         }
7022
7023         /* For size less than 4 we merge, else we zero extend */
7024         val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7025
7026         /*
7027          * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7028          * the copy and tracing
7029          */
7030         emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7031         kvm_rax_write(vcpu, val);
7032
7033         return kvm_skip_emulated_instruction(vcpu);
7034 }
7035
7036 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7037                            unsigned short port)
7038 {
7039         unsigned long val;
7040         int ret;
7041
7042         /* For size less than 4 we merge, else we zero extend */
7043         val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7044
7045         ret = emulator_pio_in(vcpu, size, port, &val, 1);
7046         if (ret) {
7047                 kvm_rax_write(vcpu, val);
7048                 return ret;
7049         }
7050
7051         vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7052         vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7053
7054         return 0;
7055 }
7056
7057 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7058 {
7059         int ret;
7060
7061         if (in)
7062                 ret = kvm_fast_pio_in(vcpu, size, port);
7063         else
7064                 ret = kvm_fast_pio_out(vcpu, size, port);
7065         return ret && kvm_skip_emulated_instruction(vcpu);
7066 }
7067 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7068
7069 static int kvmclock_cpu_down_prep(unsigned int cpu)
7070 {
7071         __this_cpu_write(cpu_tsc_khz, 0);
7072         return 0;
7073 }
7074
7075 static void tsc_khz_changed(void *data)
7076 {
7077         struct cpufreq_freqs *freq = data;
7078         unsigned long khz = 0;
7079
7080         if (data)
7081                 khz = freq->new;
7082         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7083                 khz = cpufreq_quick_get(raw_smp_processor_id());
7084         if (!khz)
7085                 khz = tsc_khz;
7086         __this_cpu_write(cpu_tsc_khz, khz);
7087 }
7088
7089 #ifdef CONFIG_X86_64
7090 static void kvm_hyperv_tsc_notifier(void)
7091 {
7092         struct kvm *kvm;
7093         struct kvm_vcpu *vcpu;
7094         int cpu;
7095
7096         mutex_lock(&kvm_lock);
7097         list_for_each_entry(kvm, &vm_list, vm_list)
7098                 kvm_make_mclock_inprogress_request(kvm);
7099
7100         hyperv_stop_tsc_emulation();
7101
7102         /* TSC frequency always matches when on Hyper-V */
7103         for_each_present_cpu(cpu)
7104                 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7105         kvm_max_guest_tsc_khz = tsc_khz;
7106
7107         list_for_each_entry(kvm, &vm_list, vm_list) {
7108                 struct kvm_arch *ka = &kvm->arch;
7109
7110                 spin_lock(&ka->pvclock_gtod_sync_lock);
7111
7112                 pvclock_update_vm_gtod_copy(kvm);
7113
7114                 kvm_for_each_vcpu(cpu, vcpu, kvm)
7115                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7116
7117                 kvm_for_each_vcpu(cpu, vcpu, kvm)
7118                         kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7119
7120                 spin_unlock(&ka->pvclock_gtod_sync_lock);
7121         }
7122         mutex_unlock(&kvm_lock);
7123 }
7124 #endif
7125
7126 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7127 {
7128         struct kvm *kvm;
7129         struct kvm_vcpu *vcpu;
7130         int i, send_ipi = 0;
7131
7132         /*
7133          * We allow guests to temporarily run on slowing clocks,
7134          * provided we notify them after, or to run on accelerating
7135          * clocks, provided we notify them before.  Thus time never
7136          * goes backwards.
7137          *
7138          * However, we have a problem.  We can't atomically update
7139          * the frequency of a given CPU from this function; it is
7140          * merely a notifier, which can be called from any CPU.
7141          * Changing the TSC frequency at arbitrary points in time
7142          * requires a recomputation of local variables related to
7143          * the TSC for each VCPU.  We must flag these local variables
7144          * to be updated and be sure the update takes place with the
7145          * new frequency before any guests proceed.
7146          *
7147          * Unfortunately, the combination of hotplug CPU and frequency
7148          * change creates an intractable locking scenario; the order
7149          * of when these callouts happen is undefined with respect to
7150          * CPU hotplug, and they can race with each other.  As such,
7151          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7152          * undefined; you can actually have a CPU frequency change take
7153          * place in between the computation of X and the setting of the
7154          * variable.  To protect against this problem, all updates of
7155          * the per_cpu tsc_khz variable are done in an interrupt
7156          * protected IPI, and all callers wishing to update the value
7157          * must wait for a synchronous IPI to complete (which is trivial
7158          * if the caller is on the CPU already).  This establishes the
7159          * necessary total order on variable updates.
7160          *
7161          * Note that because a guest time update may take place
7162          * anytime after the setting of the VCPU's request bit, the
7163          * correct TSC value must be set before the request.  However,
7164          * to ensure the update actually makes it to any guest which
7165          * starts running in hardware virtualization between the set
7166          * and the acquisition of the spinlock, we must also ping the
7167          * CPU after setting the request bit.
7168          *
7169          */
7170
7171         smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7172
7173         mutex_lock(&kvm_lock);
7174         list_for_each_entry(kvm, &vm_list, vm_list) {
7175                 kvm_for_each_vcpu(i, vcpu, kvm) {
7176                         if (vcpu->cpu != cpu)
7177                                 continue;
7178                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7179                         if (vcpu->cpu != raw_smp_processor_id())
7180                                 send_ipi = 1;
7181                 }
7182         }
7183         mutex_unlock(&kvm_lock);
7184
7185         if (freq->old < freq->new && send_ipi) {
7186                 /*
7187                  * We upscale the frequency.  Must make the guest
7188                  * doesn't see old kvmclock values while running with
7189                  * the new frequency, otherwise we risk the guest sees
7190                  * time go backwards.
7191                  *
7192                  * In case we update the frequency for another cpu
7193                  * (which might be in guest context) send an interrupt
7194                  * to kick the cpu out of guest context.  Next time
7195                  * guest context is entered kvmclock will be updated,
7196                  * so the guest will not see stale values.
7197                  */
7198                 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7199         }
7200 }
7201
7202 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7203                                      void *data)
7204 {
7205         struct cpufreq_freqs *freq = data;
7206         int cpu;
7207
7208         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7209                 return 0;
7210         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7211                 return 0;
7212
7213         for_each_cpu(cpu, freq->policy->cpus)
7214                 __kvmclock_cpufreq_notifier(freq, cpu);
7215
7216         return 0;
7217 }
7218
7219 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7220         .notifier_call  = kvmclock_cpufreq_notifier
7221 };
7222
7223 static int kvmclock_cpu_online(unsigned int cpu)
7224 {
7225         tsc_khz_changed(NULL);
7226         return 0;
7227 }
7228
7229 static void kvm_timer_init(void)
7230 {
7231         max_tsc_khz = tsc_khz;
7232
7233         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7234 #ifdef CONFIG_CPU_FREQ
7235                 struct cpufreq_policy *policy;
7236                 int cpu;
7237
7238                 cpu = get_cpu();
7239                 policy = cpufreq_cpu_get(cpu);
7240                 if (policy) {
7241                         if (policy->cpuinfo.max_freq)
7242                                 max_tsc_khz = policy->cpuinfo.max_freq;
7243                         cpufreq_cpu_put(policy);
7244                 }
7245                 put_cpu();
7246 #endif
7247                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7248                                           CPUFREQ_TRANSITION_NOTIFIER);
7249         }
7250
7251         cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7252                           kvmclock_cpu_online, kvmclock_cpu_down_prep);
7253 }
7254
7255 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7256 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7257
7258 int kvm_is_in_guest(void)
7259 {
7260         return __this_cpu_read(current_vcpu) != NULL;
7261 }
7262
7263 static int kvm_is_user_mode(void)
7264 {
7265         int user_mode = 3;
7266
7267         if (__this_cpu_read(current_vcpu))
7268                 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu));
7269
7270         return user_mode != 0;
7271 }
7272
7273 static unsigned long kvm_get_guest_ip(void)
7274 {
7275         unsigned long ip = 0;
7276
7277         if (__this_cpu_read(current_vcpu))
7278                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7279
7280         return ip;
7281 }
7282
7283 static void kvm_handle_intel_pt_intr(void)
7284 {
7285         struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7286
7287         kvm_make_request(KVM_REQ_PMI, vcpu);
7288         __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7289                         (unsigned long *)&vcpu->arch.pmu.global_status);
7290 }
7291
7292 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7293         .is_in_guest            = kvm_is_in_guest,
7294         .is_user_mode           = kvm_is_user_mode,
7295         .get_guest_ip           = kvm_get_guest_ip,
7296         .handle_intel_pt_intr   = kvm_handle_intel_pt_intr,
7297 };
7298
7299 #ifdef CONFIG_X86_64
7300 static void pvclock_gtod_update_fn(struct work_struct *work)
7301 {
7302         struct kvm *kvm;
7303
7304         struct kvm_vcpu *vcpu;
7305         int i;
7306
7307         mutex_lock(&kvm_lock);
7308         list_for_each_entry(kvm, &vm_list, vm_list)
7309                 kvm_for_each_vcpu(i, vcpu, kvm)
7310                         kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7311         atomic_set(&kvm_guest_has_master_clock, 0);
7312         mutex_unlock(&kvm_lock);
7313 }
7314
7315 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7316
7317 /*
7318  * Notification about pvclock gtod data update.
7319  */
7320 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7321                                void *priv)
7322 {
7323         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7324         struct timekeeper *tk = priv;
7325
7326         update_pvclock_gtod(tk);
7327
7328         /* disable master clock if host does not trust, or does not
7329          * use, TSC based clocksource.
7330          */
7331         if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7332             atomic_read(&kvm_guest_has_master_clock) != 0)
7333                 queue_work(system_long_wq, &pvclock_gtod_work);
7334
7335         return 0;
7336 }
7337
7338 static struct notifier_block pvclock_gtod_notifier = {
7339         .notifier_call = pvclock_gtod_notify,
7340 };
7341 #endif
7342
7343 int kvm_arch_init(void *opaque)
7344 {
7345         struct kvm_x86_init_ops *ops = opaque;
7346         int r;
7347
7348         if (kvm_x86_ops.hardware_enable) {
7349                 printk(KERN_ERR "kvm: already loaded the other module\n");
7350                 r = -EEXIST;
7351                 goto out;
7352         }
7353
7354         if (!ops->cpu_has_kvm_support()) {
7355                 pr_err_ratelimited("kvm: no hardware support\n");
7356                 r = -EOPNOTSUPP;
7357                 goto out;
7358         }
7359         if (ops->disabled_by_bios()) {
7360                 pr_err_ratelimited("kvm: disabled by bios\n");
7361                 r = -EOPNOTSUPP;
7362                 goto out;
7363         }
7364
7365         /*
7366          * KVM explicitly assumes that the guest has an FPU and
7367          * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7368          * vCPU's FPU state as a fxregs_state struct.
7369          */
7370         if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7371                 printk(KERN_ERR "kvm: inadequate fpu\n");
7372                 r = -EOPNOTSUPP;
7373                 goto out;
7374         }
7375
7376         r = -ENOMEM;
7377         x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7378                                           __alignof__(struct fpu), SLAB_ACCOUNT,
7379                                           NULL);
7380         if (!x86_fpu_cache) {
7381                 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7382                 goto out;
7383         }
7384
7385         x86_emulator_cache = kvm_alloc_emulator_cache();
7386         if (!x86_emulator_cache) {
7387                 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7388                 goto out_free_x86_fpu_cache;
7389         }
7390
7391         shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7392         if (!shared_msrs) {
7393                 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7394                 goto out_free_x86_emulator_cache;
7395         }
7396
7397         r = kvm_mmu_module_init();
7398         if (r)
7399                 goto out_free_percpu;
7400
7401         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7402                         PT_DIRTY_MASK, PT64_NX_MASK, 0,
7403                         PT_PRESENT_MASK, 0, sme_me_mask);
7404         kvm_timer_init();
7405
7406         perf_register_guest_info_callbacks(&kvm_guest_cbs);
7407
7408         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7409                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7410                 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7411         }
7412
7413         kvm_lapic_init();
7414         if (pi_inject_timer == -1)
7415                 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7416 #ifdef CONFIG_X86_64
7417         pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7418
7419         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7420                 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7421 #endif
7422
7423         return 0;
7424
7425 out_free_percpu:
7426         free_percpu(shared_msrs);
7427 out_free_x86_emulator_cache:
7428         kmem_cache_destroy(x86_emulator_cache);
7429 out_free_x86_fpu_cache:
7430         kmem_cache_destroy(x86_fpu_cache);
7431 out:
7432         return r;
7433 }
7434
7435 void kvm_arch_exit(void)
7436 {
7437 #ifdef CONFIG_X86_64
7438         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7439                 clear_hv_tscchange_cb();
7440 #endif
7441         kvm_lapic_exit();
7442         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7443
7444         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7445                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7446                                             CPUFREQ_TRANSITION_NOTIFIER);
7447         cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7448 #ifdef CONFIG_X86_64
7449         pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7450 #endif
7451         kvm_x86_ops.hardware_enable = NULL;
7452         kvm_mmu_module_exit();
7453         free_percpu(shared_msrs);
7454         kmem_cache_destroy(x86_fpu_cache);
7455 }
7456
7457 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7458 {
7459         ++vcpu->stat.halt_exits;
7460         if (lapic_in_kernel(vcpu)) {
7461                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7462                 return 1;
7463         } else {
7464                 vcpu->run->exit_reason = KVM_EXIT_HLT;
7465                 return 0;
7466         }
7467 }
7468 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7469
7470 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7471 {
7472         int ret = kvm_skip_emulated_instruction(vcpu);
7473         /*
7474          * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7475          * KVM_EXIT_DEBUG here.
7476          */
7477         return kvm_vcpu_halt(vcpu) && ret;
7478 }
7479 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7480
7481 #ifdef CONFIG_X86_64
7482 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7483                                 unsigned long clock_type)
7484 {
7485         struct kvm_clock_pairing clock_pairing;
7486         struct timespec64 ts;
7487         u64 cycle;
7488         int ret;
7489
7490         if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7491                 return -KVM_EOPNOTSUPP;
7492
7493         if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7494                 return -KVM_EOPNOTSUPP;
7495
7496         clock_pairing.sec = ts.tv_sec;
7497         clock_pairing.nsec = ts.tv_nsec;
7498         clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7499         clock_pairing.flags = 0;
7500         memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7501
7502         ret = 0;
7503         if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7504                             sizeof(struct kvm_clock_pairing)))
7505                 ret = -KVM_EFAULT;
7506
7507         return ret;
7508 }
7509 #endif
7510
7511 /*
7512  * kvm_pv_kick_cpu_op:  Kick a vcpu.
7513  *
7514  * @apicid - apicid of vcpu to be kicked.
7515  */
7516 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7517 {
7518         struct kvm_lapic_irq lapic_irq;
7519
7520         lapic_irq.shorthand = APIC_DEST_NOSHORT;
7521         lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
7522         lapic_irq.level = 0;
7523         lapic_irq.dest_id = apicid;
7524         lapic_irq.msi_redir_hint = false;
7525
7526         lapic_irq.delivery_mode = APIC_DM_REMRD;
7527         kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7528 }
7529
7530 bool kvm_apicv_activated(struct kvm *kvm)
7531 {
7532         return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
7533 }
7534 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
7535
7536 void kvm_apicv_init(struct kvm *kvm, bool enable)
7537 {
7538         if (enable)
7539                 clear_bit(APICV_INHIBIT_REASON_DISABLE,
7540                           &kvm->arch.apicv_inhibit_reasons);
7541         else
7542                 set_bit(APICV_INHIBIT_REASON_DISABLE,
7543                         &kvm->arch.apicv_inhibit_reasons);
7544 }
7545 EXPORT_SYMBOL_GPL(kvm_apicv_init);
7546
7547 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7548 {
7549         struct kvm_vcpu *target = NULL;
7550         struct kvm_apic_map *map;
7551
7552         rcu_read_lock();
7553         map = rcu_dereference(kvm->arch.apic_map);
7554
7555         if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7556                 target = map->phys_map[dest_id]->vcpu;
7557
7558         rcu_read_unlock();
7559
7560         if (target && READ_ONCE(target->ready))
7561                 kvm_vcpu_yield_to(target);
7562 }
7563
7564 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7565 {
7566         unsigned long nr, a0, a1, a2, a3, ret;
7567         int op_64_bit;
7568
7569         if (kvm_hv_hypercall_enabled(vcpu->kvm))
7570                 return kvm_hv_hypercall(vcpu);
7571
7572         nr = kvm_rax_read(vcpu);
7573         a0 = kvm_rbx_read(vcpu);
7574         a1 = kvm_rcx_read(vcpu);
7575         a2 = kvm_rdx_read(vcpu);
7576         a3 = kvm_rsi_read(vcpu);
7577
7578         trace_kvm_hypercall(nr, a0, a1, a2, a3);
7579
7580         op_64_bit = is_64_bit_mode(vcpu);
7581         if (!op_64_bit) {
7582                 nr &= 0xFFFFFFFF;
7583                 a0 &= 0xFFFFFFFF;
7584                 a1 &= 0xFFFFFFFF;
7585                 a2 &= 0xFFFFFFFF;
7586                 a3 &= 0xFFFFFFFF;
7587         }
7588
7589         if (kvm_x86_ops.get_cpl(vcpu) != 0) {
7590                 ret = -KVM_EPERM;
7591                 goto out;
7592         }
7593
7594         switch (nr) {
7595         case KVM_HC_VAPIC_POLL_IRQ:
7596                 ret = 0;
7597                 break;
7598         case KVM_HC_KICK_CPU:
7599                 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7600                 kvm_sched_yield(vcpu->kvm, a1);
7601                 ret = 0;
7602                 break;
7603 #ifdef CONFIG_X86_64
7604         case KVM_HC_CLOCK_PAIRING:
7605                 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7606                 break;
7607 #endif
7608         case KVM_HC_SEND_IPI:
7609                 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7610                 break;
7611         case KVM_HC_SCHED_YIELD:
7612                 kvm_sched_yield(vcpu->kvm, a0);
7613                 ret = 0;
7614                 break;
7615         default:
7616                 ret = -KVM_ENOSYS;
7617                 break;
7618         }
7619 out:
7620         if (!op_64_bit)
7621                 ret = (u32)ret;
7622         kvm_rax_write(vcpu, ret);
7623
7624         ++vcpu->stat.hypercalls;
7625         return kvm_skip_emulated_instruction(vcpu);
7626 }
7627 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7628
7629 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7630 {
7631         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7632         char instruction[3];
7633         unsigned long rip = kvm_rip_read(vcpu);
7634
7635         kvm_x86_ops.patch_hypercall(vcpu, instruction);
7636
7637         return emulator_write_emulated(ctxt, rip, instruction, 3,
7638                 &ctxt->exception);
7639 }
7640
7641 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7642 {
7643         return vcpu->run->request_interrupt_window &&
7644                 likely(!pic_in_kernel(vcpu->kvm));
7645 }
7646
7647 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7648 {
7649         struct kvm_run *kvm_run = vcpu->run;
7650
7651         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7652         kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7653         kvm_run->cr8 = kvm_get_cr8(vcpu);
7654         kvm_run->apic_base = kvm_get_apic_base(vcpu);
7655         kvm_run->ready_for_interrupt_injection =
7656                 pic_in_kernel(vcpu->kvm) ||
7657                 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7658 }
7659
7660 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7661 {
7662         int max_irr, tpr;
7663
7664         if (!kvm_x86_ops.update_cr8_intercept)
7665                 return;
7666
7667         if (!lapic_in_kernel(vcpu))
7668                 return;
7669
7670         if (vcpu->arch.apicv_active)
7671                 return;
7672
7673         if (!vcpu->arch.apic->vapic_addr)
7674                 max_irr = kvm_lapic_find_highest_irr(vcpu);
7675         else
7676                 max_irr = -1;
7677
7678         if (max_irr != -1)
7679                 max_irr >>= 4;
7680
7681         tpr = kvm_lapic_get_cr8(vcpu);
7682
7683         kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr);
7684 }
7685
7686 static int inject_pending_event(struct kvm_vcpu *vcpu)
7687 {
7688         int r;
7689
7690         /* try to reinject previous events if any */
7691
7692         if (vcpu->arch.exception.injected)
7693                 kvm_x86_ops.queue_exception(vcpu);
7694         /*
7695          * Do not inject an NMI or interrupt if there is a pending
7696          * exception.  Exceptions and interrupts are recognized at
7697          * instruction boundaries, i.e. the start of an instruction.
7698          * Trap-like exceptions, e.g. #DB, have higher priority than
7699          * NMIs and interrupts, i.e. traps are recognized before an
7700          * NMI/interrupt that's pending on the same instruction.
7701          * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7702          * priority, but are only generated (pended) during instruction
7703          * execution, i.e. a pending fault-like exception means the
7704          * fault occurred on the *previous* instruction and must be
7705          * serviced prior to recognizing any new events in order to
7706          * fully complete the previous instruction.
7707          */
7708         else if (!vcpu->arch.exception.pending) {
7709                 if (vcpu->arch.nmi_injected)
7710                         kvm_x86_ops.set_nmi(vcpu);
7711                 else if (vcpu->arch.interrupt.injected)
7712                         kvm_x86_ops.set_irq(vcpu);
7713         }
7714
7715         WARN_ON_ONCE(vcpu->arch.exception.injected &&
7716                      vcpu->arch.exception.pending);
7717
7718         /*
7719          * Call check_nested_events() even if we reinjected a previous event
7720          * in order for caller to determine if it should require immediate-exit
7721          * from L2 to L1 due to pending L1 events which require exit
7722          * from L2 to L1.
7723          */
7724         if (is_guest_mode(vcpu)) {
7725                 r = kvm_x86_ops.nested_ops->check_events(vcpu);
7726                 if (r != 0)
7727                         return r;
7728         }
7729
7730         /* try to inject new event if pending */
7731         if (vcpu->arch.exception.pending) {
7732                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7733                                         vcpu->arch.exception.has_error_code,
7734                                         vcpu->arch.exception.error_code);
7735
7736                 vcpu->arch.exception.pending = false;
7737                 vcpu->arch.exception.injected = true;
7738
7739                 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7740                         __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7741                                              X86_EFLAGS_RF);
7742
7743                 if (vcpu->arch.exception.nr == DB_VECTOR) {
7744                         /*
7745                          * This code assumes that nSVM doesn't use
7746                          * check_nested_events(). If it does, the
7747                          * DR6/DR7 changes should happen before L1
7748                          * gets a #VMEXIT for an intercepted #DB in
7749                          * L2.  (Under VMX, on the other hand, the
7750                          * DR6/DR7 changes should not happen in the
7751                          * event of a VM-exit to L1 for an intercepted
7752                          * #DB in L2.)
7753                          */
7754                         kvm_deliver_exception_payload(vcpu);
7755                         if (vcpu->arch.dr7 & DR7_GD) {
7756                                 vcpu->arch.dr7 &= ~DR7_GD;
7757                                 kvm_update_dr7(vcpu);
7758                         }
7759                 }
7760
7761                 kvm_x86_ops.queue_exception(vcpu);
7762         }
7763
7764         /* Don't consider new event if we re-injected an event */
7765         if (kvm_event_needs_reinjection(vcpu))
7766                 return 0;
7767
7768         if (vcpu->arch.smi_pending &&
7769             kvm_x86_ops.smi_allowed(vcpu, true)) {
7770                 vcpu->arch.smi_pending = false;
7771                 ++vcpu->arch.smi_count;
7772                 enter_smm(vcpu);
7773         } else if (vcpu->arch.nmi_pending &&
7774                    kvm_x86_ops.nmi_allowed(vcpu, true)) {
7775                 --vcpu->arch.nmi_pending;
7776                 vcpu->arch.nmi_injected = true;
7777                 kvm_x86_ops.set_nmi(vcpu);
7778         } else if (kvm_cpu_has_injectable_intr(vcpu) &&
7779                    kvm_x86_ops.interrupt_allowed(vcpu, true)) {
7780                 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
7781                 kvm_x86_ops.set_irq(vcpu);
7782         }
7783
7784         return 0;
7785 }
7786
7787 static void process_nmi(struct kvm_vcpu *vcpu)
7788 {
7789         unsigned limit = 2;
7790
7791         /*
7792          * x86 is limited to one NMI running, and one NMI pending after it.
7793          * If an NMI is already in progress, limit further NMIs to just one.
7794          * Otherwise, allow two (and we'll inject the first one immediately).
7795          */
7796         if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7797                 limit = 1;
7798
7799         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7800         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7801         kvm_make_request(KVM_REQ_EVENT, vcpu);
7802 }
7803
7804 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7805 {
7806         u32 flags = 0;
7807         flags |= seg->g       << 23;
7808         flags |= seg->db      << 22;
7809         flags |= seg->l       << 21;
7810         flags |= seg->avl     << 20;
7811         flags |= seg->present << 15;
7812         flags |= seg->dpl     << 13;
7813         flags |= seg->s       << 12;
7814         flags |= seg->type    << 8;
7815         return flags;
7816 }
7817
7818 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7819 {
7820         struct kvm_segment seg;
7821         int offset;
7822
7823         kvm_get_segment(vcpu, &seg, n);
7824         put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7825
7826         if (n < 3)
7827                 offset = 0x7f84 + n * 12;
7828         else
7829                 offset = 0x7f2c + (n - 3) * 12;
7830
7831         put_smstate(u32, buf, offset + 8, seg.base);
7832         put_smstate(u32, buf, offset + 4, seg.limit);
7833         put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7834 }
7835
7836 #ifdef CONFIG_X86_64
7837 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7838 {
7839         struct kvm_segment seg;
7840         int offset;
7841         u16 flags;
7842
7843         kvm_get_segment(vcpu, &seg, n);
7844         offset = 0x7e00 + n * 16;
7845
7846         flags = enter_smm_get_segment_flags(&seg) >> 8;
7847         put_smstate(u16, buf, offset, seg.selector);
7848         put_smstate(u16, buf, offset + 2, flags);
7849         put_smstate(u32, buf, offset + 4, seg.limit);
7850         put_smstate(u64, buf, offset + 8, seg.base);
7851 }
7852 #endif
7853
7854 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7855 {
7856         struct desc_ptr dt;
7857         struct kvm_segment seg;
7858         unsigned long val;
7859         int i;
7860
7861         put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7862         put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7863         put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7864         put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7865
7866         for (i = 0; i < 8; i++)
7867                 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7868
7869         kvm_get_dr(vcpu, 6, &val);
7870         put_smstate(u32, buf, 0x7fcc, (u32)val);
7871         kvm_get_dr(vcpu, 7, &val);
7872         put_smstate(u32, buf, 0x7fc8, (u32)val);
7873
7874         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7875         put_smstate(u32, buf, 0x7fc4, seg.selector);
7876         put_smstate(u32, buf, 0x7f64, seg.base);
7877         put_smstate(u32, buf, 0x7f60, seg.limit);
7878         put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7879
7880         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7881         put_smstate(u32, buf, 0x7fc0, seg.selector);
7882         put_smstate(u32, buf, 0x7f80, seg.base);
7883         put_smstate(u32, buf, 0x7f7c, seg.limit);
7884         put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7885
7886         kvm_x86_ops.get_gdt(vcpu, &dt);
7887         put_smstate(u32, buf, 0x7f74, dt.address);
7888         put_smstate(u32, buf, 0x7f70, dt.size);
7889
7890         kvm_x86_ops.get_idt(vcpu, &dt);
7891         put_smstate(u32, buf, 0x7f58, dt.address);
7892         put_smstate(u32, buf, 0x7f54, dt.size);
7893
7894         for (i = 0; i < 6; i++)
7895                 enter_smm_save_seg_32(vcpu, buf, i);
7896
7897         put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7898
7899         /* revision id */
7900         put_smstate(u32, buf, 0x7efc, 0x00020000);
7901         put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7902 }
7903
7904 #ifdef CONFIG_X86_64
7905 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7906 {
7907         struct desc_ptr dt;
7908         struct kvm_segment seg;
7909         unsigned long val;
7910         int i;
7911
7912         for (i = 0; i < 16; i++)
7913                 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7914
7915         put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7916         put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7917
7918         kvm_get_dr(vcpu, 6, &val);
7919         put_smstate(u64, buf, 0x7f68, val);
7920         kvm_get_dr(vcpu, 7, &val);
7921         put_smstate(u64, buf, 0x7f60, val);
7922
7923         put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7924         put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7925         put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7926
7927         put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7928
7929         /* revision id */
7930         put_smstate(u32, buf, 0x7efc, 0x00020064);
7931
7932         put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7933
7934         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7935         put_smstate(u16, buf, 0x7e90, seg.selector);
7936         put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7937         put_smstate(u32, buf, 0x7e94, seg.limit);
7938         put_smstate(u64, buf, 0x7e98, seg.base);
7939
7940         kvm_x86_ops.get_idt(vcpu, &dt);
7941         put_smstate(u32, buf, 0x7e84, dt.size);
7942         put_smstate(u64, buf, 0x7e88, dt.address);
7943
7944         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7945         put_smstate(u16, buf, 0x7e70, seg.selector);
7946         put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7947         put_smstate(u32, buf, 0x7e74, seg.limit);
7948         put_smstate(u64, buf, 0x7e78, seg.base);
7949
7950         kvm_x86_ops.get_gdt(vcpu, &dt);
7951         put_smstate(u32, buf, 0x7e64, dt.size);
7952         put_smstate(u64, buf, 0x7e68, dt.address);
7953
7954         for (i = 0; i < 6; i++)
7955                 enter_smm_save_seg_64(vcpu, buf, i);
7956 }
7957 #endif
7958
7959 static void enter_smm(struct kvm_vcpu *vcpu)
7960 {
7961         struct kvm_segment cs, ds;
7962         struct desc_ptr dt;
7963         char buf[512];
7964         u32 cr0;
7965
7966         trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7967         memset(buf, 0, 512);
7968 #ifdef CONFIG_X86_64
7969         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7970                 enter_smm_save_state_64(vcpu, buf);
7971         else
7972 #endif
7973                 enter_smm_save_state_32(vcpu, buf);
7974
7975         /*
7976          * Give pre_enter_smm() a chance to make ISA-specific changes to the
7977          * vCPU state (e.g. leave guest mode) after we've saved the state into
7978          * the SMM state-save area.
7979          */
7980         kvm_x86_ops.pre_enter_smm(vcpu, buf);
7981
7982         vcpu->arch.hflags |= HF_SMM_MASK;
7983         kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7984
7985         if (kvm_x86_ops.get_nmi_mask(vcpu))
7986                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7987         else
7988                 kvm_x86_ops.set_nmi_mask(vcpu, true);
7989
7990         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7991         kvm_rip_write(vcpu, 0x8000);
7992
7993         cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7994         kvm_x86_ops.set_cr0(vcpu, cr0);
7995         vcpu->arch.cr0 = cr0;
7996
7997         kvm_x86_ops.set_cr4(vcpu, 0);
7998
7999         /* Undocumented: IDT limit is set to zero on entry to SMM.  */
8000         dt.address = dt.size = 0;
8001         kvm_x86_ops.set_idt(vcpu, &dt);
8002
8003         __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
8004
8005         cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
8006         cs.base = vcpu->arch.smbase;
8007
8008         ds.selector = 0;
8009         ds.base = 0;
8010
8011         cs.limit    = ds.limit = 0xffffffff;
8012         cs.type     = ds.type = 0x3;
8013         cs.dpl      = ds.dpl = 0;
8014         cs.db       = ds.db = 0;
8015         cs.s        = ds.s = 1;
8016         cs.l        = ds.l = 0;
8017         cs.g        = ds.g = 1;
8018         cs.avl      = ds.avl = 0;
8019         cs.present  = ds.present = 1;
8020         cs.unusable = ds.unusable = 0;
8021         cs.padding  = ds.padding = 0;
8022
8023         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8024         kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8025         kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8026         kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8027         kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8028         kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8029
8030 #ifdef CONFIG_X86_64
8031         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8032                 kvm_x86_ops.set_efer(vcpu, 0);
8033 #endif
8034
8035         kvm_update_cpuid(vcpu);
8036         kvm_mmu_reset_context(vcpu);
8037 }
8038
8039 static void process_smi(struct kvm_vcpu *vcpu)
8040 {
8041         vcpu->arch.smi_pending = true;
8042         kvm_make_request(KVM_REQ_EVENT, vcpu);
8043 }
8044
8045 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8046                                        unsigned long *vcpu_bitmap)
8047 {
8048         cpumask_var_t cpus;
8049
8050         zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8051
8052         kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8053                                     NULL, vcpu_bitmap, cpus);
8054
8055         free_cpumask_var(cpus);
8056 }
8057
8058 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8059 {
8060         kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8061 }
8062
8063 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8064 {
8065         if (!lapic_in_kernel(vcpu))
8066                 return;
8067
8068         vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8069         kvm_apic_update_apicv(vcpu);
8070         kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu);
8071 }
8072 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8073
8074 /*
8075  * NOTE: Do not hold any lock prior to calling this.
8076  *
8077  * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8078  * locked, because it calls __x86_set_memory_region() which does
8079  * synchronize_srcu(&kvm->srcu).
8080  */
8081 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8082 {
8083         struct kvm_vcpu *except;
8084         unsigned long old, new, expected;
8085
8086         if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8087             !kvm_x86_ops.check_apicv_inhibit_reasons(bit))
8088                 return;
8089
8090         old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8091         do {
8092                 expected = new = old;
8093                 if (activate)
8094                         __clear_bit(bit, &new);
8095                 else
8096                         __set_bit(bit, &new);
8097                 if (new == old)
8098                         break;
8099                 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8100         } while (old != expected);
8101
8102         if (!!old == !!new)
8103                 return;
8104
8105         trace_kvm_apicv_update_request(activate, bit);
8106         if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8107                 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate);
8108
8109         /*
8110          * Sending request to update APICV for all other vcpus,
8111          * while update the calling vcpu immediately instead of
8112          * waiting for another #VMEXIT to handle the request.
8113          */
8114         except = kvm_get_running_vcpu();
8115         kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE,
8116                                          except);
8117         if (except)
8118                 kvm_vcpu_update_apicv(except);
8119 }
8120 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8121
8122 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8123 {
8124         if (!kvm_apic_present(vcpu))
8125                 return;
8126
8127         bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8128
8129         if (irqchip_split(vcpu->kvm))
8130                 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8131         else {
8132                 if (vcpu->arch.apicv_active)
8133                         kvm_x86_ops.sync_pir_to_irr(vcpu);
8134                 if (ioapic_in_kernel(vcpu->kvm))
8135                         kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8136         }
8137
8138         if (is_guest_mode(vcpu))
8139                 vcpu->arch.load_eoi_exitmap_pending = true;
8140         else
8141                 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8142 }
8143
8144 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8145 {
8146         u64 eoi_exit_bitmap[4];
8147
8148         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8149                 return;
8150
8151         bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8152                   vcpu_to_synic(vcpu)->vec_bitmap, 256);
8153         kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8154 }
8155
8156 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8157                 unsigned long start, unsigned long end,
8158                 bool blockable)
8159 {
8160         unsigned long apic_address;
8161
8162         /*
8163          * The physical address of apic access page is stored in the VMCS.
8164          * Update it when it becomes invalid.
8165          */
8166         apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8167         if (start <= apic_address && apic_address < end)
8168                 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8169
8170         return 0;
8171 }
8172
8173 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8174 {
8175         if (!lapic_in_kernel(vcpu))
8176                 return;
8177
8178         if (!kvm_x86_ops.set_apic_access_page_addr)
8179                 return;
8180
8181         kvm_x86_ops.set_apic_access_page_addr(vcpu);
8182 }
8183
8184 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8185 {
8186         smp_send_reschedule(vcpu->cpu);
8187 }
8188 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8189
8190 /*
8191  * Returns 1 to let vcpu_run() continue the guest execution loop without
8192  * exiting to the userspace.  Otherwise, the value will be returned to the
8193  * userspace.
8194  */
8195 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8196 {
8197         int r;
8198         bool req_int_win =
8199                 dm_request_for_irq_injection(vcpu) &&
8200                 kvm_cpu_accept_dm_intr(vcpu);
8201         enum exit_fastpath_completion exit_fastpath;
8202
8203         bool req_immediate_exit = false;
8204
8205         if (kvm_request_pending(vcpu)) {
8206                 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) {
8207                         if (unlikely(!kvm_x86_ops.nested_ops->get_vmcs12_pages(vcpu))) {
8208                                 r = 0;
8209                                 goto out;
8210                         }
8211                 }
8212                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8213                         kvm_mmu_unload(vcpu);
8214                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8215                         __kvm_migrate_timers(vcpu);
8216                 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8217                         kvm_gen_update_masterclock(vcpu->kvm);
8218                 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8219                         kvm_gen_kvmclock_update(vcpu);
8220                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8221                         r = kvm_guest_time_update(vcpu);
8222                         if (unlikely(r))
8223                                 goto out;
8224                 }
8225                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8226                         kvm_mmu_sync_roots(vcpu);
8227                 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8228                         kvm_mmu_load_pgd(vcpu);
8229                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
8230                         kvm_vcpu_flush_tlb_all(vcpu);
8231
8232                         /* Flushing all ASIDs flushes the current ASID... */
8233                         kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
8234                 }
8235                 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
8236                         kvm_vcpu_flush_tlb_current(vcpu);
8237                 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu))
8238                         kvm_vcpu_flush_tlb_guest(vcpu);
8239
8240                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8241                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8242                         r = 0;
8243                         goto out;
8244                 }
8245                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8246                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8247                         vcpu->mmio_needed = 0;
8248                         r = 0;
8249                         goto out;
8250                 }
8251                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8252                         /* Page is swapped out. Do synthetic halt */
8253                         vcpu->arch.apf.halted = true;
8254                         r = 1;
8255                         goto out;
8256                 }
8257                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8258                         record_steal_time(vcpu);
8259                 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8260                         process_smi(vcpu);
8261                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8262                         process_nmi(vcpu);
8263                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8264                         kvm_pmu_handle_event(vcpu);
8265                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8266                         kvm_pmu_deliver_pmi(vcpu);
8267                 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8268                         BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8269                         if (test_bit(vcpu->arch.pending_ioapic_eoi,
8270                                      vcpu->arch.ioapic_handled_vectors)) {
8271                                 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8272                                 vcpu->run->eoi.vector =
8273                                                 vcpu->arch.pending_ioapic_eoi;
8274                                 r = 0;
8275                                 goto out;
8276                         }
8277                 }
8278                 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8279                         vcpu_scan_ioapic(vcpu);
8280                 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8281                         vcpu_load_eoi_exitmap(vcpu);
8282                 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8283                         kvm_vcpu_reload_apic_access_page(vcpu);
8284                 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8285                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8286                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8287                         r = 0;
8288                         goto out;
8289                 }
8290                 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8291                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8292                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8293                         r = 0;
8294                         goto out;
8295                 }
8296                 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8297                         vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8298                         vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8299                         r = 0;
8300                         goto out;
8301                 }
8302
8303                 /*
8304                  * KVM_REQ_HV_STIMER has to be processed after
8305                  * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8306                  * depend on the guest clock being up-to-date
8307                  */
8308                 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8309                         kvm_hv_process_stimers(vcpu);
8310                 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8311                         kvm_vcpu_update_apicv(vcpu);
8312         }
8313
8314         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8315                 ++vcpu->stat.req_event;
8316                 kvm_apic_accept_events(vcpu);
8317                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8318                         r = 1;
8319                         goto out;
8320                 }
8321
8322                 if (inject_pending_event(vcpu) != 0)
8323                         req_immediate_exit = true;
8324                 else {
8325                         /* Enable SMI/NMI/IRQ window open exits if needed.
8326                          *
8327                          * SMIs have three cases:
8328                          * 1) They can be nested, and then there is nothing to
8329                          *    do here because RSM will cause a vmexit anyway.
8330                          * 2) There is an ISA-specific reason why SMI cannot be
8331                          *    injected, and the moment when this changes can be
8332                          *    intercepted.
8333                          * 3) Or the SMI can be pending because
8334                          *    inject_pending_event has completed the injection
8335                          *    of an IRQ or NMI from the previous vmexit, and
8336                          *    then we request an immediate exit to inject the
8337                          *    SMI.
8338                          */
8339                         if (vcpu->arch.smi_pending && !is_smm(vcpu))
8340                                 if (!kvm_x86_ops.enable_smi_window(vcpu))
8341                                         req_immediate_exit = true;
8342                         if (vcpu->arch.nmi_pending)
8343                                 kvm_x86_ops.enable_nmi_window(vcpu);
8344                         if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8345                                 kvm_x86_ops.enable_irq_window(vcpu);
8346                         if (is_guest_mode(vcpu) &&
8347                             kvm_x86_ops.nested_ops->hv_timer_pending &&
8348                             kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
8349                                 req_immediate_exit = true;
8350                         WARN_ON(vcpu->arch.exception.pending);
8351                 }
8352
8353                 if (kvm_lapic_enabled(vcpu)) {
8354                         update_cr8_intercept(vcpu);
8355                         kvm_lapic_sync_to_vapic(vcpu);
8356                 }
8357         }
8358
8359         r = kvm_mmu_reload(vcpu);
8360         if (unlikely(r)) {
8361                 goto cancel_injection;
8362         }
8363
8364         preempt_disable();
8365
8366         kvm_x86_ops.prepare_guest_switch(vcpu);
8367
8368         /*
8369          * Disable IRQs before setting IN_GUEST_MODE.  Posted interrupt
8370          * IPI are then delayed after guest entry, which ensures that they
8371          * result in virtual interrupt delivery.
8372          */
8373         local_irq_disable();
8374         vcpu->mode = IN_GUEST_MODE;
8375
8376         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8377
8378         /*
8379          * 1) We should set ->mode before checking ->requests.  Please see
8380          * the comment in kvm_vcpu_exiting_guest_mode().
8381          *
8382          * 2) For APICv, we should set ->mode before checking PID.ON. This
8383          * pairs with the memory barrier implicit in pi_test_and_set_on
8384          * (see vmx_deliver_posted_interrupt).
8385          *
8386          * 3) This also orders the write to mode from any reads to the page
8387          * tables done while the VCPU is running.  Please see the comment
8388          * in kvm_flush_remote_tlbs.
8389          */
8390         smp_mb__after_srcu_read_unlock();
8391
8392         /*
8393          * This handles the case where a posted interrupt was
8394          * notified with kvm_vcpu_kick.
8395          */
8396         if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8397                 kvm_x86_ops.sync_pir_to_irr(vcpu);
8398
8399         if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
8400             || need_resched() || signal_pending(current)) {
8401                 vcpu->mode = OUTSIDE_GUEST_MODE;
8402                 smp_wmb();
8403                 local_irq_enable();
8404                 preempt_enable();
8405                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8406                 r = 1;
8407                 goto cancel_injection;
8408         }
8409
8410         if (req_immediate_exit) {
8411                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8412                 kvm_x86_ops.request_immediate_exit(vcpu);
8413         }
8414
8415         trace_kvm_entry(vcpu->vcpu_id);
8416         guest_enter_irqoff();
8417
8418         fpregs_assert_state_consistent();
8419         if (test_thread_flag(TIF_NEED_FPU_LOAD))
8420                 switch_fpu_return();
8421
8422         if (unlikely(vcpu->arch.switch_db_regs)) {
8423                 set_debugreg(0, 7);
8424                 set_debugreg(vcpu->arch.eff_db[0], 0);
8425                 set_debugreg(vcpu->arch.eff_db[1], 1);
8426                 set_debugreg(vcpu->arch.eff_db[2], 2);
8427                 set_debugreg(vcpu->arch.eff_db[3], 3);
8428                 set_debugreg(vcpu->arch.dr6, 6);
8429                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8430         }
8431
8432         exit_fastpath = kvm_x86_ops.run(vcpu);
8433
8434         /*
8435          * Do this here before restoring debug registers on the host.  And
8436          * since we do this before handling the vmexit, a DR access vmexit
8437          * can (a) read the correct value of the debug registers, (b) set
8438          * KVM_DEBUGREG_WONT_EXIT again.
8439          */
8440         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8441                 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8442                 kvm_x86_ops.sync_dirty_debug_regs(vcpu);
8443                 kvm_update_dr0123(vcpu);
8444                 kvm_update_dr7(vcpu);
8445                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8446         }
8447
8448         /*
8449          * If the guest has used debug registers, at least dr7
8450          * will be disabled while returning to the host.
8451          * If we don't have active breakpoints in the host, we don't
8452          * care about the messed up debug address registers. But if
8453          * we have some of them active, restore the old state.
8454          */
8455         if (hw_breakpoint_active())
8456                 hw_breakpoint_restore();
8457
8458         vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8459
8460         vcpu->mode = OUTSIDE_GUEST_MODE;
8461         smp_wmb();
8462
8463         kvm_x86_ops.handle_exit_irqoff(vcpu);
8464
8465         /*
8466          * Consume any pending interrupts, including the possible source of
8467          * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8468          * An instruction is required after local_irq_enable() to fully unblock
8469          * interrupts on processors that implement an interrupt shadow, the
8470          * stat.exits increment will do nicely.
8471          */
8472         kvm_before_interrupt(vcpu);
8473         local_irq_enable();
8474         ++vcpu->stat.exits;
8475         local_irq_disable();
8476         kvm_after_interrupt(vcpu);
8477
8478         guest_exit_irqoff();
8479         if (lapic_in_kernel(vcpu)) {
8480                 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8481                 if (delta != S64_MIN) {
8482                         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8483                         vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8484                 }
8485         }
8486
8487         local_irq_enable();
8488         preempt_enable();
8489
8490         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8491
8492         /*
8493          * Profile KVM exit RIPs:
8494          */
8495         if (unlikely(prof_on == KVM_PROFILING)) {
8496                 unsigned long rip = kvm_rip_read(vcpu);
8497                 profile_hit(KVM_PROFILING, (void *)rip);
8498         }
8499
8500         if (unlikely(vcpu->arch.tsc_always_catchup))
8501                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8502
8503         if (vcpu->arch.apic_attention)
8504                 kvm_lapic_sync_from_vapic(vcpu);
8505
8506         r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath);
8507         return r;
8508
8509 cancel_injection:
8510         if (req_immediate_exit)
8511                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8512         kvm_x86_ops.cancel_injection(vcpu);
8513         if (unlikely(vcpu->arch.apic_attention))
8514                 kvm_lapic_sync_from_vapic(vcpu);
8515 out:
8516         return r;
8517 }
8518
8519 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8520 {
8521         if (!kvm_arch_vcpu_runnable(vcpu) &&
8522             (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) {
8523                 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8524                 kvm_vcpu_block(vcpu);
8525                 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8526
8527                 if (kvm_x86_ops.post_block)
8528                         kvm_x86_ops.post_block(vcpu);
8529
8530                 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8531                         return 1;
8532         }
8533
8534         kvm_apic_accept_events(vcpu);
8535         switch(vcpu->arch.mp_state) {
8536         case KVM_MP_STATE_HALTED:
8537                 vcpu->arch.pv.pv_unhalted = false;
8538                 vcpu->arch.mp_state =
8539                         KVM_MP_STATE_RUNNABLE;
8540                 /* fall through */
8541         case KVM_MP_STATE_RUNNABLE:
8542                 vcpu->arch.apf.halted = false;
8543                 break;
8544         case KVM_MP_STATE_INIT_RECEIVED:
8545                 break;
8546         default:
8547                 return -EINTR;
8548         }
8549         return 1;
8550 }
8551
8552 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8553 {
8554         if (is_guest_mode(vcpu))
8555                 kvm_x86_ops.nested_ops->check_events(vcpu);
8556
8557         return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8558                 !vcpu->arch.apf.halted);
8559 }
8560
8561 static int vcpu_run(struct kvm_vcpu *vcpu)
8562 {
8563         int r;
8564         struct kvm *kvm = vcpu->kvm;
8565
8566         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8567         vcpu->arch.l1tf_flush_l1d = true;
8568
8569         for (;;) {
8570                 if (kvm_vcpu_running(vcpu)) {
8571                         r = vcpu_enter_guest(vcpu);
8572                 } else {
8573                         r = vcpu_block(kvm, vcpu);
8574                 }
8575
8576                 if (r <= 0)
8577                         break;
8578
8579                 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8580                 if (kvm_cpu_has_pending_timer(vcpu))
8581                         kvm_inject_pending_timer_irqs(vcpu);
8582
8583                 if (dm_request_for_irq_injection(vcpu) &&
8584                         kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8585                         r = 0;
8586                         vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8587                         ++vcpu->stat.request_irq_exits;
8588                         break;
8589                 }
8590
8591                 kvm_check_async_pf_completion(vcpu);
8592
8593                 if (signal_pending(current)) {
8594                         r = -EINTR;
8595                         vcpu->run->exit_reason = KVM_EXIT_INTR;
8596                         ++vcpu->stat.signal_exits;
8597                         break;
8598                 }
8599                 if (need_resched()) {
8600                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8601                         cond_resched();
8602                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8603                 }
8604         }
8605
8606         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8607
8608         return r;
8609 }
8610
8611 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8612 {
8613         int r;
8614
8615         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8616         r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8617         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8618         return r;
8619 }
8620
8621 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8622 {
8623         BUG_ON(!vcpu->arch.pio.count);
8624
8625         return complete_emulated_io(vcpu);
8626 }
8627
8628 /*
8629  * Implements the following, as a state machine:
8630  *
8631  * read:
8632  *   for each fragment
8633  *     for each mmio piece in the fragment
8634  *       write gpa, len
8635  *       exit
8636  *       copy data
8637  *   execute insn
8638  *
8639  * write:
8640  *   for each fragment
8641  *     for each mmio piece in the fragment
8642  *       write gpa, len
8643  *       copy data
8644  *       exit
8645  */
8646 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8647 {
8648         struct kvm_run *run = vcpu->run;
8649         struct kvm_mmio_fragment *frag;
8650         unsigned len;
8651
8652         BUG_ON(!vcpu->mmio_needed);
8653
8654         /* Complete previous fragment */
8655         frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8656         len = min(8u, frag->len);
8657         if (!vcpu->mmio_is_write)
8658                 memcpy(frag->data, run->mmio.data, len);
8659
8660         if (frag->len <= 8) {
8661                 /* Switch to the next fragment. */
8662                 frag++;
8663                 vcpu->mmio_cur_fragment++;
8664         } else {
8665                 /* Go forward to the next mmio piece. */
8666                 frag->data += len;
8667                 frag->gpa += len;
8668                 frag->len -= len;
8669         }
8670
8671         if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8672                 vcpu->mmio_needed = 0;
8673
8674                 /* FIXME: return into emulator if single-stepping.  */
8675                 if (vcpu->mmio_is_write)
8676                         return 1;
8677                 vcpu->mmio_read_completed = 1;
8678                 return complete_emulated_io(vcpu);
8679         }
8680
8681         run->exit_reason = KVM_EXIT_MMIO;
8682         run->mmio.phys_addr = frag->gpa;
8683         if (vcpu->mmio_is_write)
8684                 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8685         run->mmio.len = min(8u, frag->len);
8686         run->mmio.is_write = vcpu->mmio_is_write;
8687         vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8688         return 0;
8689 }
8690
8691 static void kvm_save_current_fpu(struct fpu *fpu)
8692 {
8693         /*
8694          * If the target FPU state is not resident in the CPU registers, just
8695          * memcpy() from current, else save CPU state directly to the target.
8696          */
8697         if (test_thread_flag(TIF_NEED_FPU_LOAD))
8698                 memcpy(&fpu->state, &current->thread.fpu.state,
8699                        fpu_kernel_xstate_size);
8700         else
8701                 copy_fpregs_to_fpstate(fpu);
8702 }
8703
8704 /* Swap (qemu) user FPU context for the guest FPU context. */
8705 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8706 {
8707         fpregs_lock();
8708
8709         kvm_save_current_fpu(vcpu->arch.user_fpu);
8710
8711         /* PKRU is separately restored in kvm_x86_ops.run.  */
8712         __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8713                                 ~XFEATURE_MASK_PKRU);
8714
8715         fpregs_mark_activate();
8716         fpregs_unlock();
8717
8718         trace_kvm_fpu(1);
8719 }
8720
8721 /* When vcpu_run ends, restore user space FPU context. */
8722 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8723 {
8724         fpregs_lock();
8725
8726         kvm_save_current_fpu(vcpu->arch.guest_fpu);
8727
8728         copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8729
8730         fpregs_mark_activate();
8731         fpregs_unlock();
8732
8733         ++vcpu->stat.fpu_reload;
8734         trace_kvm_fpu(0);
8735 }
8736
8737 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
8738 {
8739         struct kvm_run *kvm_run = vcpu->run;
8740         int r;
8741
8742         vcpu_load(vcpu);
8743         kvm_sigset_activate(vcpu);
8744         kvm_load_guest_fpu(vcpu);
8745
8746         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8747                 if (kvm_run->immediate_exit) {
8748                         r = -EINTR;
8749                         goto out;
8750                 }
8751                 kvm_vcpu_block(vcpu);
8752                 kvm_apic_accept_events(vcpu);
8753                 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8754                 r = -EAGAIN;
8755                 if (signal_pending(current)) {
8756                         r = -EINTR;
8757                         kvm_run->exit_reason = KVM_EXIT_INTR;
8758                         ++vcpu->stat.signal_exits;
8759                 }
8760                 goto out;
8761         }
8762
8763         if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8764                 r = -EINVAL;
8765                 goto out;
8766         }
8767
8768         if (kvm_run->kvm_dirty_regs) {
8769                 r = sync_regs(vcpu);
8770                 if (r != 0)
8771                         goto out;
8772         }
8773
8774         /* re-sync apic's tpr */
8775         if (!lapic_in_kernel(vcpu)) {
8776                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8777                         r = -EINVAL;
8778                         goto out;
8779                 }
8780         }
8781
8782         if (unlikely(vcpu->arch.complete_userspace_io)) {
8783                 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8784                 vcpu->arch.complete_userspace_io = NULL;
8785                 r = cui(vcpu);
8786                 if (r <= 0)
8787                         goto out;
8788         } else
8789                 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8790
8791         if (kvm_run->immediate_exit)
8792                 r = -EINTR;
8793         else
8794                 r = vcpu_run(vcpu);
8795
8796 out:
8797         kvm_put_guest_fpu(vcpu);
8798         if (kvm_run->kvm_valid_regs)
8799                 store_regs(vcpu);
8800         post_kvm_run_save(vcpu);
8801         kvm_sigset_deactivate(vcpu);
8802
8803         vcpu_put(vcpu);
8804         return r;
8805 }
8806
8807 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8808 {
8809         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8810                 /*
8811                  * We are here if userspace calls get_regs() in the middle of
8812                  * instruction emulation. Registers state needs to be copied
8813                  * back from emulation context to vcpu. Userspace shouldn't do
8814                  * that usually, but some bad designed PV devices (vmware
8815                  * backdoor interface) need this to work
8816                  */
8817                 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
8818                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8819         }
8820         regs->rax = kvm_rax_read(vcpu);
8821         regs->rbx = kvm_rbx_read(vcpu);
8822         regs->rcx = kvm_rcx_read(vcpu);
8823         regs->rdx = kvm_rdx_read(vcpu);
8824         regs->rsi = kvm_rsi_read(vcpu);
8825         regs->rdi = kvm_rdi_read(vcpu);
8826         regs->rsp = kvm_rsp_read(vcpu);
8827         regs->rbp = kvm_rbp_read(vcpu);
8828 #ifdef CONFIG_X86_64
8829         regs->r8 = kvm_r8_read(vcpu);
8830         regs->r9 = kvm_r9_read(vcpu);
8831         regs->r10 = kvm_r10_read(vcpu);
8832         regs->r11 = kvm_r11_read(vcpu);
8833         regs->r12 = kvm_r12_read(vcpu);
8834         regs->r13 = kvm_r13_read(vcpu);
8835         regs->r14 = kvm_r14_read(vcpu);
8836         regs->r15 = kvm_r15_read(vcpu);
8837 #endif
8838
8839         regs->rip = kvm_rip_read(vcpu);
8840         regs->rflags = kvm_get_rflags(vcpu);
8841 }
8842
8843 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8844 {
8845         vcpu_load(vcpu);
8846         __get_regs(vcpu, regs);
8847         vcpu_put(vcpu);
8848         return 0;
8849 }
8850
8851 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8852 {
8853         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8854         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8855
8856         kvm_rax_write(vcpu, regs->rax);
8857         kvm_rbx_write(vcpu, regs->rbx);
8858         kvm_rcx_write(vcpu, regs->rcx);
8859         kvm_rdx_write(vcpu, regs->rdx);
8860         kvm_rsi_write(vcpu, regs->rsi);
8861         kvm_rdi_write(vcpu, regs->rdi);
8862         kvm_rsp_write(vcpu, regs->rsp);
8863         kvm_rbp_write(vcpu, regs->rbp);
8864 #ifdef CONFIG_X86_64
8865         kvm_r8_write(vcpu, regs->r8);
8866         kvm_r9_write(vcpu, regs->r9);
8867         kvm_r10_write(vcpu, regs->r10);
8868         kvm_r11_write(vcpu, regs->r11);
8869         kvm_r12_write(vcpu, regs->r12);
8870         kvm_r13_write(vcpu, regs->r13);
8871         kvm_r14_write(vcpu, regs->r14);
8872         kvm_r15_write(vcpu, regs->r15);
8873 #endif
8874
8875         kvm_rip_write(vcpu, regs->rip);
8876         kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8877
8878         vcpu->arch.exception.pending = false;
8879
8880         kvm_make_request(KVM_REQ_EVENT, vcpu);
8881 }
8882
8883 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8884 {
8885         vcpu_load(vcpu);
8886         __set_regs(vcpu, regs);
8887         vcpu_put(vcpu);
8888         return 0;
8889 }
8890
8891 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8892 {
8893         struct kvm_segment cs;
8894
8895         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8896         *db = cs.db;
8897         *l = cs.l;
8898 }
8899 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8900
8901 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8902 {
8903         struct desc_ptr dt;
8904
8905         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8906         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8907         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8908         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8909         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8910         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8911
8912         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8913         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8914
8915         kvm_x86_ops.get_idt(vcpu, &dt);
8916         sregs->idt.limit = dt.size;
8917         sregs->idt.base = dt.address;
8918         kvm_x86_ops.get_gdt(vcpu, &dt);
8919         sregs->gdt.limit = dt.size;
8920         sregs->gdt.base = dt.address;
8921
8922         sregs->cr0 = kvm_read_cr0(vcpu);
8923         sregs->cr2 = vcpu->arch.cr2;
8924         sregs->cr3 = kvm_read_cr3(vcpu);
8925         sregs->cr4 = kvm_read_cr4(vcpu);
8926         sregs->cr8 = kvm_get_cr8(vcpu);
8927         sregs->efer = vcpu->arch.efer;
8928         sregs->apic_base = kvm_get_apic_base(vcpu);
8929
8930         memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8931
8932         if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8933                 set_bit(vcpu->arch.interrupt.nr,
8934                         (unsigned long *)sregs->interrupt_bitmap);
8935 }
8936
8937 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8938                                   struct kvm_sregs *sregs)
8939 {
8940         vcpu_load(vcpu);
8941         __get_sregs(vcpu, sregs);
8942         vcpu_put(vcpu);
8943         return 0;
8944 }
8945
8946 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8947                                     struct kvm_mp_state *mp_state)
8948 {
8949         vcpu_load(vcpu);
8950         if (kvm_mpx_supported())
8951                 kvm_load_guest_fpu(vcpu);
8952
8953         kvm_apic_accept_events(vcpu);
8954         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8955                                         vcpu->arch.pv.pv_unhalted)
8956                 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8957         else
8958                 mp_state->mp_state = vcpu->arch.mp_state;
8959
8960         if (kvm_mpx_supported())
8961                 kvm_put_guest_fpu(vcpu);
8962         vcpu_put(vcpu);
8963         return 0;
8964 }
8965
8966 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8967                                     struct kvm_mp_state *mp_state)
8968 {
8969         int ret = -EINVAL;
8970
8971         vcpu_load(vcpu);
8972
8973         if (!lapic_in_kernel(vcpu) &&
8974             mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8975                 goto out;
8976
8977         /*
8978          * KVM_MP_STATE_INIT_RECEIVED means the processor is in
8979          * INIT state; latched init should be reported using
8980          * KVM_SET_VCPU_EVENTS, so reject it here.
8981          */
8982         if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
8983             (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8984              mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8985                 goto out;
8986
8987         if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8988                 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8989                 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8990         } else
8991                 vcpu->arch.mp_state = mp_state->mp_state;
8992         kvm_make_request(KVM_REQ_EVENT, vcpu);
8993
8994         ret = 0;
8995 out:
8996         vcpu_put(vcpu);
8997         return ret;
8998 }
8999
9000 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
9001                     int reason, bool has_error_code, u32 error_code)
9002 {
9003         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9004         int ret;
9005
9006         init_emulate_ctxt(vcpu);
9007
9008         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9009                                    has_error_code, error_code);
9010         if (ret) {
9011                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9012                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
9013                 vcpu->run->internal.ndata = 0;
9014                 return 0;
9015         }
9016
9017         kvm_rip_write(vcpu, ctxt->eip);
9018         kvm_set_rflags(vcpu, ctxt->eflags);
9019         return 1;
9020 }
9021 EXPORT_SYMBOL_GPL(kvm_task_switch);
9022
9023 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9024 {
9025         if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
9026                 /*
9027                  * When EFER.LME and CR0.PG are set, the processor is in
9028                  * 64-bit mode (though maybe in a 32-bit code segment).
9029                  * CR4.PAE and EFER.LMA must be set.
9030                  */
9031                 if (!(sregs->cr4 & X86_CR4_PAE)
9032                     || !(sregs->efer & EFER_LMA))
9033                         return -EINVAL;
9034         } else {
9035                 /*
9036                  * Not in 64-bit mode: EFER.LMA is clear and the code
9037                  * segment cannot be 64-bit.
9038                  */
9039                 if (sregs->efer & EFER_LMA || sregs->cs.l)
9040                         return -EINVAL;
9041         }
9042
9043         return kvm_valid_cr4(vcpu, sregs->cr4);
9044 }
9045
9046 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9047 {
9048         struct msr_data apic_base_msr;
9049         int mmu_reset_needed = 0;
9050         int cpuid_update_needed = 0;
9051         int pending_vec, max_bits, idx;
9052         struct desc_ptr dt;
9053         int ret = -EINVAL;
9054
9055         if (kvm_valid_sregs(vcpu, sregs))
9056                 goto out;
9057
9058         apic_base_msr.data = sregs->apic_base;
9059         apic_base_msr.host_initiated = true;
9060         if (kvm_set_apic_base(vcpu, &apic_base_msr))
9061                 goto out;
9062
9063         dt.size = sregs->idt.limit;
9064         dt.address = sregs->idt.base;
9065         kvm_x86_ops.set_idt(vcpu, &dt);
9066         dt.size = sregs->gdt.limit;
9067         dt.address = sregs->gdt.base;
9068         kvm_x86_ops.set_gdt(vcpu, &dt);
9069
9070         vcpu->arch.cr2 = sregs->cr2;
9071         mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9072         vcpu->arch.cr3 = sregs->cr3;
9073         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9074
9075         kvm_set_cr8(vcpu, sregs->cr8);
9076
9077         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9078         kvm_x86_ops.set_efer(vcpu, sregs->efer);
9079
9080         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9081         kvm_x86_ops.set_cr0(vcpu, sregs->cr0);
9082         vcpu->arch.cr0 = sregs->cr0;
9083
9084         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9085         cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
9086                                 (X86_CR4_OSXSAVE | X86_CR4_PKE));
9087         kvm_x86_ops.set_cr4(vcpu, sregs->cr4);
9088         if (cpuid_update_needed)
9089                 kvm_update_cpuid(vcpu);
9090
9091         idx = srcu_read_lock(&vcpu->kvm->srcu);
9092         if (is_pae_paging(vcpu)) {
9093                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9094                 mmu_reset_needed = 1;
9095         }
9096         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9097
9098         if (mmu_reset_needed)
9099                 kvm_mmu_reset_context(vcpu);
9100
9101         max_bits = KVM_NR_INTERRUPTS;
9102         pending_vec = find_first_bit(
9103                 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9104         if (pending_vec < max_bits) {
9105                 kvm_queue_interrupt(vcpu, pending_vec, false);
9106                 pr_debug("Set back pending irq %d\n", pending_vec);
9107         }
9108
9109         kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9110         kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9111         kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9112         kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9113         kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9114         kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9115
9116         kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9117         kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9118
9119         update_cr8_intercept(vcpu);
9120
9121         /* Older userspace won't unhalt the vcpu on reset. */
9122         if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9123             sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9124             !is_protmode(vcpu))
9125                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9126
9127         kvm_make_request(KVM_REQ_EVENT, vcpu);
9128
9129         ret = 0;
9130 out:
9131         return ret;
9132 }
9133
9134 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9135                                   struct kvm_sregs *sregs)
9136 {
9137         int ret;
9138
9139         vcpu_load(vcpu);
9140         ret = __set_sregs(vcpu, sregs);
9141         vcpu_put(vcpu);
9142         return ret;
9143 }
9144
9145 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9146                                         struct kvm_guest_debug *dbg)
9147 {
9148         unsigned long rflags;
9149         int i, r;
9150
9151         vcpu_load(vcpu);
9152
9153         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9154                 r = -EBUSY;
9155                 if (vcpu->arch.exception.pending)
9156                         goto out;
9157                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9158                         kvm_queue_exception(vcpu, DB_VECTOR);
9159                 else
9160                         kvm_queue_exception(vcpu, BP_VECTOR);
9161         }
9162
9163         /*
9164          * Read rflags as long as potentially injected trace flags are still
9165          * filtered out.
9166          */
9167         rflags = kvm_get_rflags(vcpu);
9168
9169         vcpu->guest_debug = dbg->control;
9170         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9171                 vcpu->guest_debug = 0;
9172
9173         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9174                 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9175                         vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9176                 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9177         } else {
9178                 for (i = 0; i < KVM_NR_DB_REGS; i++)
9179                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9180         }
9181         kvm_update_dr7(vcpu);
9182
9183         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9184                 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9185                         get_segment_base(vcpu, VCPU_SREG_CS);
9186
9187         /*
9188          * Trigger an rflags update that will inject or remove the trace
9189          * flags.
9190          */
9191         kvm_set_rflags(vcpu, rflags);
9192
9193         kvm_x86_ops.update_bp_intercept(vcpu);
9194
9195         r = 0;
9196
9197 out:
9198         vcpu_put(vcpu);
9199         return r;
9200 }
9201
9202 /*
9203  * Translate a guest virtual address to a guest physical address.
9204  */
9205 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9206                                     struct kvm_translation *tr)
9207 {
9208         unsigned long vaddr = tr->linear_address;
9209         gpa_t gpa;
9210         int idx;
9211
9212         vcpu_load(vcpu);
9213
9214         idx = srcu_read_lock(&vcpu->kvm->srcu);
9215         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9216         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9217         tr->physical_address = gpa;
9218         tr->valid = gpa != UNMAPPED_GVA;
9219         tr->writeable = 1;
9220         tr->usermode = 0;
9221
9222         vcpu_put(vcpu);
9223         return 0;
9224 }
9225
9226 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9227 {
9228         struct fxregs_state *fxsave;
9229
9230         vcpu_load(vcpu);
9231
9232         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9233         memcpy(fpu->fpr, fxsave->st_space, 128);
9234         fpu->fcw = fxsave->cwd;
9235         fpu->fsw = fxsave->swd;
9236         fpu->ftwx = fxsave->twd;
9237         fpu->last_opcode = fxsave->fop;
9238         fpu->last_ip = fxsave->rip;
9239         fpu->last_dp = fxsave->rdp;
9240         memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9241
9242         vcpu_put(vcpu);
9243         return 0;
9244 }
9245
9246 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9247 {
9248         struct fxregs_state *fxsave;
9249
9250         vcpu_load(vcpu);
9251
9252         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9253
9254         memcpy(fxsave->st_space, fpu->fpr, 128);
9255         fxsave->cwd = fpu->fcw;
9256         fxsave->swd = fpu->fsw;
9257         fxsave->twd = fpu->ftwx;
9258         fxsave->fop = fpu->last_opcode;
9259         fxsave->rip = fpu->last_ip;
9260         fxsave->rdp = fpu->last_dp;
9261         memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9262
9263         vcpu_put(vcpu);
9264         return 0;
9265 }
9266
9267 static void store_regs(struct kvm_vcpu *vcpu)
9268 {
9269         BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9270
9271         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9272                 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9273
9274         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9275                 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9276
9277         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9278                 kvm_vcpu_ioctl_x86_get_vcpu_events(
9279                                 vcpu, &vcpu->run->s.regs.events);
9280 }
9281
9282 static int sync_regs(struct kvm_vcpu *vcpu)
9283 {
9284         if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9285                 return -EINVAL;
9286
9287         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9288                 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9289                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9290         }
9291         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9292                 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9293                         return -EINVAL;
9294                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9295         }
9296         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9297                 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9298                                 vcpu, &vcpu->run->s.regs.events))
9299                         return -EINVAL;
9300                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9301         }
9302
9303         return 0;
9304 }
9305
9306 static void fx_init(struct kvm_vcpu *vcpu)
9307 {
9308         fpstate_init(&vcpu->arch.guest_fpu->state);
9309         if (boot_cpu_has(X86_FEATURE_XSAVES))
9310                 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9311                         host_xcr0 | XSTATE_COMPACTION_ENABLED;
9312
9313         /*
9314          * Ensure guest xcr0 is valid for loading
9315          */
9316         vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9317
9318         vcpu->arch.cr0 |= X86_CR0_ET;
9319 }
9320
9321 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9322 {
9323         if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9324                 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9325                              "guest TSC will not be reliable\n");
9326
9327         return 0;
9328 }
9329
9330 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9331 {
9332         struct page *page;
9333         int r;
9334
9335         if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9336                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9337         else
9338                 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9339
9340         kvm_set_tsc_khz(vcpu, max_tsc_khz);
9341
9342         r = kvm_mmu_create(vcpu);
9343         if (r < 0)
9344                 return r;
9345
9346         if (irqchip_in_kernel(vcpu->kvm)) {
9347                 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9348                 if (r < 0)
9349                         goto fail_mmu_destroy;
9350                 if (kvm_apicv_activated(vcpu->kvm))
9351                         vcpu->arch.apicv_active = true;
9352         } else
9353                 static_key_slow_inc(&kvm_no_apic_vcpu);
9354
9355         r = -ENOMEM;
9356
9357         page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9358         if (!page)
9359                 goto fail_free_lapic;
9360         vcpu->arch.pio_data = page_address(page);
9361
9362         vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9363                                        GFP_KERNEL_ACCOUNT);
9364         if (!vcpu->arch.mce_banks)
9365                 goto fail_free_pio_data;
9366         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9367
9368         if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9369                                 GFP_KERNEL_ACCOUNT))
9370                 goto fail_free_mce_banks;
9371
9372         if (!alloc_emulate_ctxt(vcpu))
9373                 goto free_wbinvd_dirty_mask;
9374
9375         vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9376                                                 GFP_KERNEL_ACCOUNT);
9377         if (!vcpu->arch.user_fpu) {
9378                 pr_err("kvm: failed to allocate userspace's fpu\n");
9379                 goto free_emulate_ctxt;
9380         }
9381
9382         vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9383                                                  GFP_KERNEL_ACCOUNT);
9384         if (!vcpu->arch.guest_fpu) {
9385                 pr_err("kvm: failed to allocate vcpu's fpu\n");
9386                 goto free_user_fpu;
9387         }
9388         fx_init(vcpu);
9389
9390         vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9391
9392         vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9393
9394         kvm_async_pf_hash_reset(vcpu);
9395         kvm_pmu_init(vcpu);
9396
9397         vcpu->arch.pending_external_vector = -1;
9398         vcpu->arch.preempted_in_kernel = false;
9399
9400         kvm_hv_vcpu_init(vcpu);
9401
9402         r = kvm_x86_ops.vcpu_create(vcpu);
9403         if (r)
9404                 goto free_guest_fpu;
9405
9406         vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9407         vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9408         kvm_vcpu_mtrr_init(vcpu);
9409         vcpu_load(vcpu);
9410         kvm_vcpu_reset(vcpu, false);
9411         kvm_init_mmu(vcpu, false);
9412         vcpu_put(vcpu);
9413         return 0;
9414
9415 free_guest_fpu:
9416         kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9417 free_user_fpu:
9418         kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9419 free_emulate_ctxt:
9420         kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9421 free_wbinvd_dirty_mask:
9422         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9423 fail_free_mce_banks:
9424         kfree(vcpu->arch.mce_banks);
9425 fail_free_pio_data:
9426         free_page((unsigned long)vcpu->arch.pio_data);
9427 fail_free_lapic:
9428         kvm_free_lapic(vcpu);
9429 fail_mmu_destroy:
9430         kvm_mmu_destroy(vcpu);
9431         return r;
9432 }
9433
9434 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9435 {
9436         struct msr_data msr;
9437         struct kvm *kvm = vcpu->kvm;
9438
9439         kvm_hv_vcpu_postcreate(vcpu);
9440
9441         if (mutex_lock_killable(&vcpu->mutex))
9442                 return;
9443         vcpu_load(vcpu);
9444         msr.data = 0x0;
9445         msr.index = MSR_IA32_TSC;
9446         msr.host_initiated = true;
9447         kvm_write_tsc(vcpu, &msr);
9448         vcpu_put(vcpu);
9449
9450         /* poll control enabled by default */
9451         vcpu->arch.msr_kvm_poll_control = 1;
9452
9453         mutex_unlock(&vcpu->mutex);
9454
9455         if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
9456                 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9457                                                 KVMCLOCK_SYNC_PERIOD);
9458 }
9459
9460 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9461 {
9462         struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9463         int idx;
9464
9465         kvm_release_pfn(cache->pfn, cache->dirty, cache);
9466
9467         kvmclock_reset(vcpu);
9468
9469         kvm_x86_ops.vcpu_free(vcpu);
9470
9471         kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9472         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9473         kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9474         kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9475
9476         kvm_hv_vcpu_uninit(vcpu);
9477         kvm_pmu_destroy(vcpu);
9478         kfree(vcpu->arch.mce_banks);
9479         kvm_free_lapic(vcpu);
9480         idx = srcu_read_lock(&vcpu->kvm->srcu);
9481         kvm_mmu_destroy(vcpu);
9482         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9483         free_page((unsigned long)vcpu->arch.pio_data);
9484         if (!lapic_in_kernel(vcpu))
9485                 static_key_slow_dec(&kvm_no_apic_vcpu);
9486 }
9487
9488 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9489 {
9490         kvm_lapic_reset(vcpu, init_event);
9491
9492         vcpu->arch.hflags = 0;
9493
9494         vcpu->arch.smi_pending = 0;
9495         vcpu->arch.smi_count = 0;
9496         atomic_set(&vcpu->arch.nmi_queued, 0);
9497         vcpu->arch.nmi_pending = 0;
9498         vcpu->arch.nmi_injected = false;
9499         kvm_clear_interrupt_queue(vcpu);
9500         kvm_clear_exception_queue(vcpu);
9501
9502         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9503         kvm_update_dr0123(vcpu);
9504         vcpu->arch.dr6 = DR6_INIT;
9505         vcpu->arch.dr7 = DR7_FIXED_1;
9506         kvm_update_dr7(vcpu);
9507
9508         vcpu->arch.cr2 = 0;
9509
9510         kvm_make_request(KVM_REQ_EVENT, vcpu);
9511         vcpu->arch.apf.msr_val = 0;
9512         vcpu->arch.st.msr_val = 0;
9513
9514         kvmclock_reset(vcpu);
9515
9516         kvm_clear_async_pf_completion_queue(vcpu);
9517         kvm_async_pf_hash_reset(vcpu);
9518         vcpu->arch.apf.halted = false;
9519
9520         if (kvm_mpx_supported()) {
9521                 void *mpx_state_buffer;
9522
9523                 /*
9524                  * To avoid have the INIT path from kvm_apic_has_events() that be
9525                  * called with loaded FPU and does not let userspace fix the state.
9526                  */
9527                 if (init_event)
9528                         kvm_put_guest_fpu(vcpu);
9529                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9530                                         XFEATURE_BNDREGS);
9531                 if (mpx_state_buffer)
9532                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9533                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9534                                         XFEATURE_BNDCSR);
9535                 if (mpx_state_buffer)
9536                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9537                 if (init_event)
9538                         kvm_load_guest_fpu(vcpu);
9539         }
9540
9541         if (!init_event) {
9542                 kvm_pmu_reset(vcpu);
9543                 vcpu->arch.smbase = 0x30000;
9544
9545                 vcpu->arch.msr_misc_features_enables = 0;
9546
9547                 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9548         }
9549
9550         memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9551         vcpu->arch.regs_avail = ~0;
9552         vcpu->arch.regs_dirty = ~0;
9553
9554         vcpu->arch.ia32_xss = 0;
9555
9556         kvm_x86_ops.vcpu_reset(vcpu, init_event);
9557 }
9558
9559 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9560 {
9561         struct kvm_segment cs;
9562
9563         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9564         cs.selector = vector << 8;
9565         cs.base = vector << 12;
9566         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9567         kvm_rip_write(vcpu, 0);
9568 }
9569
9570 int kvm_arch_hardware_enable(void)
9571 {
9572         struct kvm *kvm;
9573         struct kvm_vcpu *vcpu;
9574         int i;
9575         int ret;
9576         u64 local_tsc;
9577         u64 max_tsc = 0;
9578         bool stable, backwards_tsc = false;
9579
9580         kvm_shared_msr_cpu_online();
9581         ret = kvm_x86_ops.hardware_enable();
9582         if (ret != 0)
9583                 return ret;
9584
9585         local_tsc = rdtsc();
9586         stable = !kvm_check_tsc_unstable();
9587         list_for_each_entry(kvm, &vm_list, vm_list) {
9588                 kvm_for_each_vcpu(i, vcpu, kvm) {
9589                         if (!stable && vcpu->cpu == smp_processor_id())
9590                                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9591                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9592                                 backwards_tsc = true;
9593                                 if (vcpu->arch.last_host_tsc > max_tsc)
9594                                         max_tsc = vcpu->arch.last_host_tsc;
9595                         }
9596                 }
9597         }
9598
9599         /*
9600          * Sometimes, even reliable TSCs go backwards.  This happens on
9601          * platforms that reset TSC during suspend or hibernate actions, but
9602          * maintain synchronization.  We must compensate.  Fortunately, we can
9603          * detect that condition here, which happens early in CPU bringup,
9604          * before any KVM threads can be running.  Unfortunately, we can't
9605          * bring the TSCs fully up to date with real time, as we aren't yet far
9606          * enough into CPU bringup that we know how much real time has actually
9607          * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9608          * variables that haven't been updated yet.
9609          *
9610          * So we simply find the maximum observed TSC above, then record the
9611          * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
9612          * the adjustment will be applied.  Note that we accumulate
9613          * adjustments, in case multiple suspend cycles happen before some VCPU
9614          * gets a chance to run again.  In the event that no KVM threads get a
9615          * chance to run, we will miss the entire elapsed period, as we'll have
9616          * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9617          * loose cycle time.  This isn't too big a deal, since the loss will be
9618          * uniform across all VCPUs (not to mention the scenario is extremely
9619          * unlikely). It is possible that a second hibernate recovery happens
9620          * much faster than a first, causing the observed TSC here to be
9621          * smaller; this would require additional padding adjustment, which is
9622          * why we set last_host_tsc to the local tsc observed here.
9623          *
9624          * N.B. - this code below runs only on platforms with reliable TSC,
9625          * as that is the only way backwards_tsc is set above.  Also note
9626          * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9627          * have the same delta_cyc adjustment applied if backwards_tsc
9628          * is detected.  Note further, this adjustment is only done once,
9629          * as we reset last_host_tsc on all VCPUs to stop this from being
9630          * called multiple times (one for each physical CPU bringup).
9631          *
9632          * Platforms with unreliable TSCs don't have to deal with this, they
9633          * will be compensated by the logic in vcpu_load, which sets the TSC to
9634          * catchup mode.  This will catchup all VCPUs to real time, but cannot
9635          * guarantee that they stay in perfect synchronization.
9636          */
9637         if (backwards_tsc) {
9638                 u64 delta_cyc = max_tsc - local_tsc;
9639                 list_for_each_entry(kvm, &vm_list, vm_list) {
9640                         kvm->arch.backwards_tsc_observed = true;
9641                         kvm_for_each_vcpu(i, vcpu, kvm) {
9642                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9643                                 vcpu->arch.last_host_tsc = local_tsc;
9644                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9645                         }
9646
9647                         /*
9648                          * We have to disable TSC offset matching.. if you were
9649                          * booting a VM while issuing an S4 host suspend....
9650                          * you may have some problem.  Solving this issue is
9651                          * left as an exercise to the reader.
9652                          */
9653                         kvm->arch.last_tsc_nsec = 0;
9654                         kvm->arch.last_tsc_write = 0;
9655                 }
9656
9657         }
9658         return 0;
9659 }
9660
9661 void kvm_arch_hardware_disable(void)
9662 {
9663         kvm_x86_ops.hardware_disable();
9664         drop_user_return_notifiers();
9665 }
9666
9667 int kvm_arch_hardware_setup(void *opaque)
9668 {
9669         struct kvm_x86_init_ops *ops = opaque;
9670         int r;
9671
9672         rdmsrl_safe(MSR_EFER, &host_efer);
9673
9674         if (boot_cpu_has(X86_FEATURE_XSAVES))
9675                 rdmsrl(MSR_IA32_XSS, host_xss);
9676
9677         r = ops->hardware_setup();
9678         if (r != 0)
9679                 return r;
9680
9681         memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
9682
9683         if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
9684                 supported_xss = 0;
9685
9686 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
9687         cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
9688 #undef __kvm_cpu_cap_has
9689
9690         if (kvm_has_tsc_control) {
9691                 /*
9692                  * Make sure the user can only configure tsc_khz values that
9693                  * fit into a signed integer.
9694                  * A min value is not calculated because it will always
9695                  * be 1 on all machines.
9696                  */
9697                 u64 max = min(0x7fffffffULL,
9698                               __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9699                 kvm_max_guest_tsc_khz = max;
9700
9701                 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9702         }
9703
9704         kvm_init_msr_list();
9705         return 0;
9706 }
9707
9708 void kvm_arch_hardware_unsetup(void)
9709 {
9710         kvm_x86_ops.hardware_unsetup();
9711 }
9712
9713 int kvm_arch_check_processor_compat(void *opaque)
9714 {
9715         struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
9716         struct kvm_x86_init_ops *ops = opaque;
9717
9718         WARN_ON(!irqs_disabled());
9719
9720         if (__cr4_reserved_bits(cpu_has, c) !=
9721             __cr4_reserved_bits(cpu_has, &boot_cpu_data))
9722                 return -EIO;
9723
9724         return ops->check_processor_compatibility();
9725 }
9726
9727 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9728 {
9729         return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9730 }
9731 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9732
9733 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9734 {
9735         return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9736 }
9737
9738 struct static_key kvm_no_apic_vcpu __read_mostly;
9739 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9740
9741 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9742 {
9743         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
9744
9745         vcpu->arch.l1tf_flush_l1d = true;
9746         if (pmu->version && unlikely(pmu->event_count)) {
9747                 pmu->need_cleanup = true;
9748                 kvm_make_request(KVM_REQ_PMU, vcpu);
9749         }
9750         kvm_x86_ops.sched_in(vcpu, cpu);
9751 }
9752
9753 void kvm_arch_free_vm(struct kvm *kvm)
9754 {
9755         kfree(kvm->arch.hyperv.hv_pa_pg);
9756         vfree(kvm);
9757 }
9758
9759
9760 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9761 {
9762         if (type)
9763                 return -EINVAL;
9764
9765         INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9766         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9767         INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9768         INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
9769         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9770         atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9771
9772         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9773         set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9774         /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9775         set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9776                 &kvm->arch.irq_sources_bitmap);
9777
9778         raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9779         mutex_init(&kvm->arch.apic_map_lock);
9780         spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9781
9782         kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
9783         pvclock_update_vm_gtod_copy(kvm);
9784
9785         kvm->arch.guest_can_read_msr_platform_info = true;
9786
9787         INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9788         INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9789
9790         kvm_hv_init_vm(kvm);
9791         kvm_page_track_init(kvm);
9792         kvm_mmu_init_vm(kvm);
9793
9794         return kvm_x86_ops.vm_init(kvm);
9795 }
9796
9797 int kvm_arch_post_init_vm(struct kvm *kvm)
9798 {
9799         return kvm_mmu_post_init_vm(kvm);
9800 }
9801
9802 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9803 {
9804         vcpu_load(vcpu);
9805         kvm_mmu_unload(vcpu);
9806         vcpu_put(vcpu);
9807 }
9808
9809 static void kvm_free_vcpus(struct kvm *kvm)
9810 {
9811         unsigned int i;
9812         struct kvm_vcpu *vcpu;
9813
9814         /*
9815          * Unpin any mmu pages first.
9816          */
9817         kvm_for_each_vcpu(i, vcpu, kvm) {
9818                 kvm_clear_async_pf_completion_queue(vcpu);
9819                 kvm_unload_vcpu_mmu(vcpu);
9820         }
9821         kvm_for_each_vcpu(i, vcpu, kvm)
9822                 kvm_vcpu_destroy(vcpu);
9823
9824         mutex_lock(&kvm->lock);
9825         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9826                 kvm->vcpus[i] = NULL;
9827
9828         atomic_set(&kvm->online_vcpus, 0);
9829         mutex_unlock(&kvm->lock);
9830 }
9831
9832 void kvm_arch_sync_events(struct kvm *kvm)
9833 {
9834         cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9835         cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9836         kvm_free_pit(kvm);
9837 }
9838
9839 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9840 {
9841         int i, r;
9842         unsigned long hva, uninitialized_var(old_npages);
9843         struct kvm_memslots *slots = kvm_memslots(kvm);
9844         struct kvm_memory_slot *slot;
9845
9846         /* Called with kvm->slots_lock held.  */
9847         if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9848                 return -EINVAL;
9849
9850         slot = id_to_memslot(slots, id);
9851         if (size) {
9852                 if (slot && slot->npages)
9853                         return -EEXIST;
9854
9855                 /*
9856                  * MAP_SHARED to prevent internal slot pages from being moved
9857                  * by fork()/COW.
9858                  */
9859                 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9860                               MAP_SHARED | MAP_ANONYMOUS, 0);
9861                 if (IS_ERR((void *)hva))
9862                         return PTR_ERR((void *)hva);
9863         } else {
9864                 if (!slot || !slot->npages)
9865                         return 0;
9866
9867                 /*
9868                  * Stuff a non-canonical value to catch use-after-delete.  This
9869                  * ends up being 0 on 32-bit KVM, but there's no better
9870                  * alternative.
9871                  */
9872                 hva = (unsigned long)(0xdeadull << 48);
9873                 old_npages = slot->npages;
9874         }
9875
9876         for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9877                 struct kvm_userspace_memory_region m;
9878
9879                 m.slot = id | (i << 16);
9880                 m.flags = 0;
9881                 m.guest_phys_addr = gpa;
9882                 m.userspace_addr = hva;
9883                 m.memory_size = size;
9884                 r = __kvm_set_memory_region(kvm, &m);
9885                 if (r < 0)
9886                         return r;
9887         }
9888
9889         if (!size)
9890                 vm_munmap(hva, old_npages * PAGE_SIZE);
9891
9892         return 0;
9893 }
9894 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9895
9896 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
9897 {
9898         kvm_mmu_pre_destroy_vm(kvm);
9899 }
9900
9901 void kvm_arch_destroy_vm(struct kvm *kvm)
9902 {
9903         if (current->mm == kvm->mm) {
9904                 /*
9905                  * Free memory regions allocated on behalf of userspace,
9906                  * unless the the memory map has changed due to process exit
9907                  * or fd copying.
9908                  */
9909                 mutex_lock(&kvm->slots_lock);
9910                 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
9911                                         0, 0);
9912                 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
9913                                         0, 0);
9914                 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9915                 mutex_unlock(&kvm->slots_lock);
9916         }
9917         if (kvm_x86_ops.vm_destroy)
9918                 kvm_x86_ops.vm_destroy(kvm);
9919         kvm_pic_destroy(kvm);
9920         kvm_ioapic_destroy(kvm);
9921         kvm_free_vcpus(kvm);
9922         kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9923         kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9924         kvm_mmu_uninit_vm(kvm);
9925         kvm_page_track_cleanup(kvm);
9926         kvm_hv_destroy_vm(kvm);
9927 }
9928
9929 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
9930 {
9931         int i;
9932
9933         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9934                 kvfree(slot->arch.rmap[i]);
9935                 slot->arch.rmap[i] = NULL;
9936
9937                 if (i == 0)
9938                         continue;
9939
9940                 kvfree(slot->arch.lpage_info[i - 1]);
9941                 slot->arch.lpage_info[i - 1] = NULL;
9942         }
9943
9944         kvm_page_track_free_memslot(slot);
9945 }
9946
9947 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
9948                                       unsigned long npages)
9949 {
9950         int i;
9951
9952         /*
9953          * Clear out the previous array pointers for the KVM_MR_MOVE case.  The
9954          * old arrays will be freed by __kvm_set_memory_region() if installing
9955          * the new memslot is successful.
9956          */
9957         memset(&slot->arch, 0, sizeof(slot->arch));
9958
9959         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9960                 struct kvm_lpage_info *linfo;
9961                 unsigned long ugfn;
9962                 int lpages;
9963                 int level = i + 1;
9964
9965                 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9966                                       slot->base_gfn, level) + 1;
9967
9968                 slot->arch.rmap[i] =
9969                         kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9970                                  GFP_KERNEL_ACCOUNT);
9971                 if (!slot->arch.rmap[i])
9972                         goto out_free;
9973                 if (i == 0)
9974                         continue;
9975
9976                 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9977                 if (!linfo)
9978                         goto out_free;
9979
9980                 slot->arch.lpage_info[i - 1] = linfo;
9981
9982                 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9983                         linfo[0].disallow_lpage = 1;
9984                 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9985                         linfo[lpages - 1].disallow_lpage = 1;
9986                 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9987                 /*
9988                  * If the gfn and userspace address are not aligned wrt each
9989                  * other, disable large page support for this slot.
9990                  */
9991                 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
9992                         unsigned long j;
9993
9994                         for (j = 0; j < lpages; ++j)
9995                                 linfo[j].disallow_lpage = 1;
9996                 }
9997         }
9998
9999         if (kvm_page_track_create_memslot(slot, npages))
10000                 goto out_free;
10001
10002         return 0;
10003
10004 out_free:
10005         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10006                 kvfree(slot->arch.rmap[i]);
10007                 slot->arch.rmap[i] = NULL;
10008                 if (i == 0)
10009                         continue;
10010
10011                 kvfree(slot->arch.lpage_info[i - 1]);
10012                 slot->arch.lpage_info[i - 1] = NULL;
10013         }
10014         return -ENOMEM;
10015 }
10016
10017 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
10018 {
10019         struct kvm_vcpu *vcpu;
10020         int i;
10021
10022         /*
10023          * memslots->generation has been incremented.
10024          * mmio generation may have reached its maximum value.
10025          */
10026         kvm_mmu_invalidate_mmio_sptes(kvm, gen);
10027
10028         /* Force re-initialization of steal_time cache */
10029         kvm_for_each_vcpu(i, vcpu, kvm)
10030                 kvm_vcpu_kick(vcpu);
10031 }
10032
10033 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10034                                 struct kvm_memory_slot *memslot,
10035                                 const struct kvm_userspace_memory_region *mem,
10036                                 enum kvm_mr_change change)
10037 {
10038         if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10039                 return kvm_alloc_memslot_metadata(memslot,
10040                                                   mem->memory_size >> PAGE_SHIFT);
10041         return 0;
10042 }
10043
10044 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10045                                      struct kvm_memory_slot *new)
10046 {
10047         /* Still write protect RO slot */
10048         if (new->flags & KVM_MEM_READONLY) {
10049                 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K);
10050                 return;
10051         }
10052
10053         /*
10054          * Call kvm_x86_ops dirty logging hooks when they are valid.
10055          *
10056          * kvm_x86_ops.slot_disable_log_dirty is called when:
10057          *
10058          *  - KVM_MR_CREATE with dirty logging is disabled
10059          *  - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
10060          *
10061          * The reason is, in case of PML, we need to set D-bit for any slots
10062          * with dirty logging disabled in order to eliminate unnecessary GPA
10063          * logging in PML buffer (and potential PML buffer full VMEXIT). This
10064          * guarantees leaving PML enabled during guest's lifetime won't have
10065          * any additional overhead from PML when guest is running with dirty
10066          * logging disabled for memory slots.
10067          *
10068          * kvm_x86_ops.slot_enable_log_dirty is called when switching new slot
10069          * to dirty logging mode.
10070          *
10071          * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
10072          *
10073          * In case of write protect:
10074          *
10075          * Write protect all pages for dirty logging.
10076          *
10077          * All the sptes including the large sptes which point to this
10078          * slot are set to readonly. We can not create any new large
10079          * spte on this slot until the end of the logging.
10080          *
10081          * See the comments in fast_page_fault().
10082          */
10083         if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10084                 if (kvm_x86_ops.slot_enable_log_dirty) {
10085                         kvm_x86_ops.slot_enable_log_dirty(kvm, new);
10086                 } else {
10087                         int level =
10088                                 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10089                                 PG_LEVEL_2M : PG_LEVEL_4K;
10090
10091                         /*
10092                          * If we're with initial-all-set, we don't need
10093                          * to write protect any small page because
10094                          * they're reported as dirty already.  However
10095                          * we still need to write-protect huge pages
10096                          * so that the page split can happen lazily on
10097                          * the first write to the huge page.
10098                          */
10099                         kvm_mmu_slot_remove_write_access(kvm, new, level);
10100                 }
10101         } else {
10102                 if (kvm_x86_ops.slot_disable_log_dirty)
10103                         kvm_x86_ops.slot_disable_log_dirty(kvm, new);
10104         }
10105 }
10106
10107 void kvm_arch_commit_memory_region(struct kvm *kvm,
10108                                 const struct kvm_userspace_memory_region *mem,
10109                                 struct kvm_memory_slot *old,
10110                                 const struct kvm_memory_slot *new,
10111                                 enum kvm_mr_change change)
10112 {
10113         if (!kvm->arch.n_requested_mmu_pages)
10114                 kvm_mmu_change_mmu_pages(kvm,
10115                                 kvm_mmu_calculate_default_mmu_pages(kvm));
10116
10117         /*
10118          * Dirty logging tracks sptes in 4k granularity, meaning that large
10119          * sptes have to be split.  If live migration is successful, the guest
10120          * in the source machine will be destroyed and large sptes will be
10121          * created in the destination. However, if the guest continues to run
10122          * in the source machine (for example if live migration fails), small
10123          * sptes will remain around and cause bad performance.
10124          *
10125          * Scan sptes if dirty logging has been stopped, dropping those
10126          * which can be collapsed into a single large-page spte.  Later
10127          * page faults will create the large-page sptes.
10128          *
10129          * There is no need to do this in any of the following cases:
10130          * CREATE:      No dirty mappings will already exist.
10131          * MOVE/DELETE: The old mappings will already have been cleaned up by
10132          *              kvm_arch_flush_shadow_memslot()
10133          */
10134         if (change == KVM_MR_FLAGS_ONLY &&
10135                 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10136                 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10137                 kvm_mmu_zap_collapsible_sptes(kvm, new);
10138
10139         /*
10140          * Set up write protection and/or dirty logging for the new slot.
10141          *
10142          * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
10143          * been zapped so no dirty logging staff is needed for old slot. For
10144          * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
10145          * new and it's also covered when dealing with the new slot.
10146          *
10147          * FIXME: const-ify all uses of struct kvm_memory_slot.
10148          */
10149         if (change != KVM_MR_DELETE)
10150                 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
10151
10152         /* Free the arrays associated with the old memslot. */
10153         if (change == KVM_MR_MOVE)
10154                 kvm_arch_free_memslot(kvm, old);
10155 }
10156
10157 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10158 {
10159         kvm_mmu_zap_all(kvm);
10160 }
10161
10162 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10163                                    struct kvm_memory_slot *slot)
10164 {
10165         kvm_page_track_flush_slot(kvm, slot);
10166 }
10167
10168 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10169 {
10170         return (is_guest_mode(vcpu) &&
10171                         kvm_x86_ops.guest_apic_has_interrupt &&
10172                         kvm_x86_ops.guest_apic_has_interrupt(vcpu));
10173 }
10174
10175 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10176 {
10177         if (!list_empty_careful(&vcpu->async_pf.done))
10178                 return true;
10179
10180         if (kvm_apic_has_events(vcpu))
10181                 return true;
10182
10183         if (vcpu->arch.pv.pv_unhalted)
10184                 return true;
10185
10186         if (vcpu->arch.exception.pending)
10187                 return true;
10188
10189         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10190             (vcpu->arch.nmi_pending &&
10191              kvm_x86_ops.nmi_allowed(vcpu, false)))
10192                 return true;
10193
10194         if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10195             (vcpu->arch.smi_pending &&
10196              kvm_x86_ops.smi_allowed(vcpu, false)))
10197                 return true;
10198
10199         if (kvm_arch_interrupt_allowed(vcpu) &&
10200             (kvm_cpu_has_interrupt(vcpu) ||
10201             kvm_guest_apic_has_interrupt(vcpu)))
10202                 return true;
10203
10204         if (kvm_hv_has_stimer_pending(vcpu))
10205                 return true;
10206
10207         if (is_guest_mode(vcpu) &&
10208             kvm_x86_ops.nested_ops->hv_timer_pending &&
10209             kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
10210                 return true;
10211
10212         return false;
10213 }
10214
10215 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10216 {
10217         return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10218 }
10219
10220 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10221 {
10222         if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10223                 return true;
10224
10225         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10226                 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10227                  kvm_test_request(KVM_REQ_EVENT, vcpu))
10228                 return true;
10229
10230         if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu))
10231                 return true;
10232
10233         return false;
10234 }
10235
10236 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10237 {
10238         return vcpu->arch.preempted_in_kernel;
10239 }
10240
10241 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10242 {
10243         return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10244 }
10245
10246 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10247 {
10248         return kvm_x86_ops.interrupt_allowed(vcpu, false);
10249 }
10250
10251 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10252 {
10253         if (is_64_bit_mode(vcpu))
10254                 return kvm_rip_read(vcpu);
10255         return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10256                      kvm_rip_read(vcpu));
10257 }
10258 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10259
10260 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10261 {
10262         return kvm_get_linear_rip(vcpu) == linear_rip;
10263 }
10264 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10265
10266 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10267 {
10268         unsigned long rflags;
10269
10270         rflags = kvm_x86_ops.get_rflags(vcpu);
10271         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10272                 rflags &= ~X86_EFLAGS_TF;
10273         return rflags;
10274 }
10275 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10276
10277 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10278 {
10279         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10280             kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10281                 rflags |= X86_EFLAGS_TF;
10282         kvm_x86_ops.set_rflags(vcpu, rflags);
10283 }
10284
10285 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10286 {
10287         __kvm_set_rflags(vcpu, rflags);
10288         kvm_make_request(KVM_REQ_EVENT, vcpu);
10289 }
10290 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10291
10292 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10293 {
10294         int r;
10295
10296         if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10297               work->wakeup_all)
10298                 return;
10299
10300         r = kvm_mmu_reload(vcpu);
10301         if (unlikely(r))
10302                 return;
10303
10304         if (!vcpu->arch.mmu->direct_map &&
10305               work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10306                 return;
10307
10308         kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10309 }
10310
10311 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10312 {
10313         return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10314 }
10315
10316 static inline u32 kvm_async_pf_next_probe(u32 key)
10317 {
10318         return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
10319 }
10320
10321 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10322 {
10323         u32 key = kvm_async_pf_hash_fn(gfn);
10324
10325         while (vcpu->arch.apf.gfns[key] != ~0)
10326                 key = kvm_async_pf_next_probe(key);
10327
10328         vcpu->arch.apf.gfns[key] = gfn;
10329 }
10330
10331 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10332 {
10333         int i;
10334         u32 key = kvm_async_pf_hash_fn(gfn);
10335
10336         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
10337                      (vcpu->arch.apf.gfns[key] != gfn &&
10338                       vcpu->arch.apf.gfns[key] != ~0); i++)
10339                 key = kvm_async_pf_next_probe(key);
10340
10341         return key;
10342 }
10343
10344 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10345 {
10346         return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10347 }
10348
10349 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10350 {
10351         u32 i, j, k;
10352
10353         i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10354         while (true) {
10355                 vcpu->arch.apf.gfns[i] = ~0;
10356                 do {
10357                         j = kvm_async_pf_next_probe(j);
10358                         if (vcpu->arch.apf.gfns[j] == ~0)
10359                                 return;
10360                         k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10361                         /*
10362                          * k lies cyclically in ]i,j]
10363                          * |    i.k.j |
10364                          * |....j i.k.| or  |.k..j i...|
10365                          */
10366                 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10367                 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10368                 i = j;
10369         }
10370 }
10371
10372 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
10373 {
10374
10375         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
10376                                       sizeof(val));
10377 }
10378
10379 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
10380 {
10381
10382         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10383                                       sizeof(u32));
10384 }
10385
10386 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10387 {
10388         if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10389                 return false;
10390
10391         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10392             (vcpu->arch.apf.send_user_only &&
10393              kvm_x86_ops.get_cpl(vcpu) == 0))
10394                 return false;
10395
10396         return true;
10397 }
10398
10399 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10400 {
10401         if (unlikely(!lapic_in_kernel(vcpu) ||
10402                      kvm_event_needs_reinjection(vcpu) ||
10403                      vcpu->arch.exception.pending))
10404                 return false;
10405
10406         if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10407                 return false;
10408
10409         /*
10410          * If interrupts are off we cannot even use an artificial
10411          * halt state.
10412          */
10413         return kvm_arch_interrupt_allowed(vcpu);
10414 }
10415
10416 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10417                                      struct kvm_async_pf *work)
10418 {
10419         struct x86_exception fault;
10420
10421         trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10422         kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10423
10424         if (kvm_can_deliver_async_pf(vcpu) &&
10425             !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
10426                 fault.vector = PF_VECTOR;
10427                 fault.error_code_valid = true;
10428                 fault.error_code = 0;
10429                 fault.nested_page_fault = false;
10430                 fault.address = work->arch.token;
10431                 fault.async_page_fault = true;
10432                 kvm_inject_page_fault(vcpu, &fault);
10433         } else {
10434                 /*
10435                  * It is not possible to deliver a paravirtualized asynchronous
10436                  * page fault, but putting the guest in an artificial halt state
10437                  * can be beneficial nevertheless: if an interrupt arrives, we
10438                  * can deliver it timely and perhaps the guest will schedule
10439                  * another process.  When the instruction that triggered a page
10440                  * fault is retried, hopefully the page will be ready in the host.
10441                  */
10442                 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10443         }
10444 }
10445
10446 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10447                                  struct kvm_async_pf *work)
10448 {
10449         struct x86_exception fault;
10450         u32 val;
10451
10452         if (work->wakeup_all)
10453                 work->arch.token = ~0; /* broadcast wakeup */
10454         else
10455                 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10456         trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
10457
10458         if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10459             !apf_get_user(vcpu, &val)) {
10460                 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10461                     vcpu->arch.exception.pending &&
10462                     vcpu->arch.exception.nr == PF_VECTOR &&
10463                     !apf_put_user(vcpu, 0)) {
10464                         vcpu->arch.exception.injected = false;
10465                         vcpu->arch.exception.pending = false;
10466                         vcpu->arch.exception.nr = 0;
10467                         vcpu->arch.exception.has_error_code = false;
10468                         vcpu->arch.exception.error_code = 0;
10469                         vcpu->arch.exception.has_payload = false;
10470                         vcpu->arch.exception.payload = 0;
10471                 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10472                         fault.vector = PF_VECTOR;
10473                         fault.error_code_valid = true;
10474                         fault.error_code = 0;
10475                         fault.nested_page_fault = false;
10476                         fault.address = work->arch.token;
10477                         fault.async_page_fault = true;
10478                         kvm_inject_page_fault(vcpu, &fault);
10479                 }
10480         }
10481         vcpu->arch.apf.halted = false;
10482         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10483 }
10484
10485 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10486 {
10487         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10488                 return true;
10489         else
10490                 return kvm_can_do_async_pf(vcpu);
10491 }
10492
10493 void kvm_arch_start_assignment(struct kvm *kvm)
10494 {
10495         atomic_inc(&kvm->arch.assigned_device_count);
10496 }
10497 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10498
10499 void kvm_arch_end_assignment(struct kvm *kvm)
10500 {
10501         atomic_dec(&kvm->arch.assigned_device_count);
10502 }
10503 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10504
10505 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10506 {
10507         return atomic_read(&kvm->arch.assigned_device_count);
10508 }
10509 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10510
10511 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10512 {
10513         atomic_inc(&kvm->arch.noncoherent_dma_count);
10514 }
10515 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10516
10517 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10518 {
10519         atomic_dec(&kvm->arch.noncoherent_dma_count);
10520 }
10521 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10522
10523 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10524 {
10525         return atomic_read(&kvm->arch.noncoherent_dma_count);
10526 }
10527 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10528
10529 bool kvm_arch_has_irq_bypass(void)
10530 {
10531         return true;
10532 }
10533
10534 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10535                                       struct irq_bypass_producer *prod)
10536 {
10537         struct kvm_kernel_irqfd *irqfd =
10538                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10539
10540         irqfd->producer = prod;
10541
10542         return kvm_x86_ops.update_pi_irte(irqfd->kvm,
10543                                            prod->irq, irqfd->gsi, 1);
10544 }
10545
10546 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10547                                       struct irq_bypass_producer *prod)
10548 {
10549         int ret;
10550         struct kvm_kernel_irqfd *irqfd =
10551                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10552
10553         WARN_ON(irqfd->producer != prod);
10554         irqfd->producer = NULL;
10555
10556         /*
10557          * When producer of consumer is unregistered, we change back to
10558          * remapped mode, so we can re-use the current implementation
10559          * when the irq is masked/disabled or the consumer side (KVM
10560          * int this case doesn't want to receive the interrupts.
10561         */
10562         ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10563         if (ret)
10564                 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10565                        " fails: %d\n", irqfd->consumer.token, ret);
10566 }
10567
10568 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10569                                    uint32_t guest_irq, bool set)
10570 {
10571         return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set);
10572 }
10573
10574 bool kvm_vector_hashing_enabled(void)
10575 {
10576         return vector_hashing;
10577 }
10578
10579 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10580 {
10581         return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10582 }
10583 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10584
10585 u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu)
10586 {
10587         uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD;
10588
10589         /* The STIBP bit doesn't fault even if it's not advertised */
10590         if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
10591             !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
10592                 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10593         if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
10594             !boot_cpu_has(X86_FEATURE_AMD_IBRS))
10595                 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10596
10597         if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) &&
10598             !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
10599                 bits &= ~SPEC_CTRL_SSBD;
10600         if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
10601             !boot_cpu_has(X86_FEATURE_AMD_SSBD))
10602                 bits &= ~SPEC_CTRL_SSBD;
10603
10604         return bits;
10605 }
10606 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits);
10607
10608 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10609 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10610 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10611 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10612 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10613 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10614 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10615 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10616 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10617 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10618 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10619 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10620 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10621 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10622 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10623 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10624 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10625 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10626 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10627 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
10628 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
10629 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);