1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
38 #include <linux/vmalloc.h>
39 #include <linux/export.h>
40 #include <linux/moduleparam.h>
41 #include <linux/mman.h>
42 #include <linux/highmem.h>
43 #include <linux/iommu.h>
44 #include <linux/intel-iommu.h>
45 #include <linux/cpufreq.h>
46 #include <linux/user-return-notifier.h>
47 #include <linux/srcu.h>
48 #include <linux/slab.h>
49 #include <linux/perf_event.h>
50 #include <linux/uaccess.h>
51 #include <linux/hash.h>
52 #include <linux/pci.h>
53 #include <linux/timekeeper_internal.h>
54 #include <linux/pvclock_gtod.h>
55 #include <linux/kvm_irqfd.h>
56 #include <linux/irqbypass.h>
57 #include <linux/sched/stat.h>
58 #include <linux/sched/isolation.h>
59 #include <linux/mem_encrypt.h>
60 #include <linux/entry-kvm.h>
61 #include <linux/suspend.h>
63 #include <trace/events/kvm.h>
65 #include <asm/debugreg.h>
70 #include <linux/kernel_stat.h>
71 #include <asm/fpu/api.h>
72 #include <asm/fpu/xcr.h>
73 #include <asm/fpu/xstate.h>
74 #include <asm/pvclock.h>
75 #include <asm/div64.h>
76 #include <asm/irq_remapping.h>
77 #include <asm/mshyperv.h>
78 #include <asm/hypervisor.h>
79 #include <asm/tlbflush.h>
80 #include <asm/intel_pt.h>
81 #include <asm/emulate_prefix.h>
83 #include <clocksource/hyperv_timer.h>
85 #define CREATE_TRACE_POINTS
88 #define MAX_IO_MSRS 256
89 #define KVM_MAX_MCE_BANKS 32
90 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
91 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
93 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
95 #define emul_to_vcpu(ctxt) \
96 ((struct kvm_vcpu *)(ctxt)->vcpu)
99 * - enable syscall per default because its emulated by KVM
100 * - enable LME and LMA per default on 64 bit KVM
104 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
106 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
109 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
111 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE)
113 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE
115 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
116 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
118 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
119 static void process_nmi(struct kvm_vcpu *vcpu);
120 static void process_smi(struct kvm_vcpu *vcpu);
121 static void enter_smm(struct kvm_vcpu *vcpu);
122 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
123 static void store_regs(struct kvm_vcpu *vcpu);
124 static int sync_regs(struct kvm_vcpu *vcpu);
125 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu);
127 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
128 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
130 struct kvm_x86_ops kvm_x86_ops __read_mostly;
132 #define KVM_X86_OP(func) \
133 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \
134 *(((struct kvm_x86_ops *)0)->func));
135 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
136 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
137 #include <asm/kvm-x86-ops.h>
138 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
139 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg);
141 static bool __read_mostly ignore_msrs = 0;
142 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
144 bool __read_mostly report_ignored_msrs = true;
145 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
146 EXPORT_SYMBOL_GPL(report_ignored_msrs);
148 unsigned int min_timer_period_us = 200;
149 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
151 static bool __read_mostly kvmclock_periodic_sync = true;
152 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
154 bool __read_mostly kvm_has_tsc_control;
155 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
156 u32 __read_mostly kvm_max_guest_tsc_khz;
157 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
158 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
159 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
160 u64 __read_mostly kvm_max_tsc_scaling_ratio;
161 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
162 u64 __read_mostly kvm_default_tsc_scaling_ratio;
163 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
164 bool __read_mostly kvm_has_bus_lock_exit;
165 EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit);
167 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
168 static u32 __read_mostly tsc_tolerance_ppm = 250;
169 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
172 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
173 * adaptive tuning starting from default advancement of 1000ns. '0' disables
174 * advancement entirely. Any other value is used as-is and disables adaptive
175 * tuning, i.e. allows privileged userspace to set an exact advancement time.
177 static int __read_mostly lapic_timer_advance_ns = -1;
178 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
180 static bool __read_mostly vector_hashing = true;
181 module_param(vector_hashing, bool, S_IRUGO);
183 bool __read_mostly enable_vmware_backdoor = false;
184 module_param(enable_vmware_backdoor, bool, S_IRUGO);
185 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
187 static bool __read_mostly force_emulation_prefix = false;
188 module_param(force_emulation_prefix, bool, S_IRUGO);
190 int __read_mostly pi_inject_timer = -1;
191 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
193 /* Enable/disable PMU virtualization */
194 bool __read_mostly enable_pmu = true;
195 EXPORT_SYMBOL_GPL(enable_pmu);
196 module_param(enable_pmu, bool, 0444);
198 bool __read_mostly eager_page_split = true;
199 module_param(eager_page_split, bool, 0644);
202 * Restoring the host value for MSRs that are only consumed when running in
203 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
204 * returns to userspace, i.e. the kernel can run with the guest's value.
206 #define KVM_MAX_NR_USER_RETURN_MSRS 16
208 struct kvm_user_return_msrs {
209 struct user_return_notifier urn;
211 struct kvm_user_return_msr_values {
214 } values[KVM_MAX_NR_USER_RETURN_MSRS];
217 u32 __read_mostly kvm_nr_uret_msrs;
218 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs);
219 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS];
220 static struct kvm_user_return_msrs __percpu *user_return_msrs;
222 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
223 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
224 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
225 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE)
227 u64 __read_mostly host_efer;
228 EXPORT_SYMBOL_GPL(host_efer);
230 bool __read_mostly allow_smaller_maxphyaddr = 0;
231 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
233 bool __read_mostly enable_apicv = true;
234 EXPORT_SYMBOL_GPL(enable_apicv);
236 u64 __read_mostly host_xss;
237 EXPORT_SYMBOL_GPL(host_xss);
238 u64 __read_mostly supported_xss;
239 EXPORT_SYMBOL_GPL(supported_xss);
241 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
242 KVM_GENERIC_VM_STATS(),
243 STATS_DESC_COUNTER(VM, mmu_shadow_zapped),
244 STATS_DESC_COUNTER(VM, mmu_pte_write),
245 STATS_DESC_COUNTER(VM, mmu_pde_zapped),
246 STATS_DESC_COUNTER(VM, mmu_flooded),
247 STATS_DESC_COUNTER(VM, mmu_recycled),
248 STATS_DESC_COUNTER(VM, mmu_cache_miss),
249 STATS_DESC_ICOUNTER(VM, mmu_unsync),
250 STATS_DESC_ICOUNTER(VM, pages_4k),
251 STATS_DESC_ICOUNTER(VM, pages_2m),
252 STATS_DESC_ICOUNTER(VM, pages_1g),
253 STATS_DESC_ICOUNTER(VM, nx_lpage_splits),
254 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size),
255 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions)
258 const struct kvm_stats_header kvm_vm_stats_header = {
259 .name_size = KVM_STATS_NAME_SIZE,
260 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
261 .id_offset = sizeof(struct kvm_stats_header),
262 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
263 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
264 sizeof(kvm_vm_stats_desc),
267 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
268 KVM_GENERIC_VCPU_STATS(),
269 STATS_DESC_COUNTER(VCPU, pf_fixed),
270 STATS_DESC_COUNTER(VCPU, pf_guest),
271 STATS_DESC_COUNTER(VCPU, tlb_flush),
272 STATS_DESC_COUNTER(VCPU, invlpg),
273 STATS_DESC_COUNTER(VCPU, exits),
274 STATS_DESC_COUNTER(VCPU, io_exits),
275 STATS_DESC_COUNTER(VCPU, mmio_exits),
276 STATS_DESC_COUNTER(VCPU, signal_exits),
277 STATS_DESC_COUNTER(VCPU, irq_window_exits),
278 STATS_DESC_COUNTER(VCPU, nmi_window_exits),
279 STATS_DESC_COUNTER(VCPU, l1d_flush),
280 STATS_DESC_COUNTER(VCPU, halt_exits),
281 STATS_DESC_COUNTER(VCPU, request_irq_exits),
282 STATS_DESC_COUNTER(VCPU, irq_exits),
283 STATS_DESC_COUNTER(VCPU, host_state_reload),
284 STATS_DESC_COUNTER(VCPU, fpu_reload),
285 STATS_DESC_COUNTER(VCPU, insn_emulation),
286 STATS_DESC_COUNTER(VCPU, insn_emulation_fail),
287 STATS_DESC_COUNTER(VCPU, hypercalls),
288 STATS_DESC_COUNTER(VCPU, irq_injections),
289 STATS_DESC_COUNTER(VCPU, nmi_injections),
290 STATS_DESC_COUNTER(VCPU, req_event),
291 STATS_DESC_COUNTER(VCPU, nested_run),
292 STATS_DESC_COUNTER(VCPU, directed_yield_attempted),
293 STATS_DESC_COUNTER(VCPU, directed_yield_successful),
294 STATS_DESC_ICOUNTER(VCPU, guest_mode)
297 const struct kvm_stats_header kvm_vcpu_stats_header = {
298 .name_size = KVM_STATS_NAME_SIZE,
299 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
300 .id_offset = sizeof(struct kvm_stats_header),
301 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
302 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
303 sizeof(kvm_vcpu_stats_desc),
306 u64 __read_mostly host_xcr0;
307 u64 __read_mostly supported_xcr0;
308 EXPORT_SYMBOL_GPL(supported_xcr0);
310 static struct kmem_cache *x86_emulator_cache;
313 * When called, it means the previous get/set msr reached an invalid msr.
314 * Return true if we want to ignore/silent this failed msr access.
316 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write)
318 const char *op = write ? "wrmsr" : "rdmsr";
321 if (report_ignored_msrs)
322 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
327 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
333 static struct kmem_cache *kvm_alloc_emulator_cache(void)
335 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
336 unsigned int size = sizeof(struct x86_emulate_ctxt);
338 return kmem_cache_create_usercopy("x86_emulator", size,
339 __alignof__(struct x86_emulate_ctxt),
340 SLAB_ACCOUNT, useroffset,
341 size - useroffset, NULL);
344 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
346 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
349 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
350 vcpu->arch.apf.gfns[i] = ~0;
353 static void kvm_on_user_return(struct user_return_notifier *urn)
356 struct kvm_user_return_msrs *msrs
357 = container_of(urn, struct kvm_user_return_msrs, urn);
358 struct kvm_user_return_msr_values *values;
362 * Disabling irqs at this point since the following code could be
363 * interrupted and executed through kvm_arch_hardware_disable()
365 local_irq_save(flags);
366 if (msrs->registered) {
367 msrs->registered = false;
368 user_return_notifier_unregister(urn);
370 local_irq_restore(flags);
371 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) {
372 values = &msrs->values[slot];
373 if (values->host != values->curr) {
374 wrmsrl(kvm_uret_msrs_list[slot], values->host);
375 values->curr = values->host;
380 static int kvm_probe_user_return_msr(u32 msr)
386 ret = rdmsrl_safe(msr, &val);
389 ret = wrmsrl_safe(msr, val);
395 int kvm_add_user_return_msr(u32 msr)
397 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS);
399 if (kvm_probe_user_return_msr(msr))
402 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr;
403 return kvm_nr_uret_msrs++;
405 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr);
407 int kvm_find_user_return_msr(u32 msr)
411 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
412 if (kvm_uret_msrs_list[i] == msr)
417 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr);
419 static void kvm_user_return_msr_cpu_online(void)
421 unsigned int cpu = smp_processor_id();
422 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
426 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
427 rdmsrl_safe(kvm_uret_msrs_list[i], &value);
428 msrs->values[i].host = value;
429 msrs->values[i].curr = value;
433 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
435 unsigned int cpu = smp_processor_id();
436 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
439 value = (value & mask) | (msrs->values[slot].host & ~mask);
440 if (value == msrs->values[slot].curr)
442 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value);
446 msrs->values[slot].curr = value;
447 if (!msrs->registered) {
448 msrs->urn.on_user_return = kvm_on_user_return;
449 user_return_notifier_register(&msrs->urn);
450 msrs->registered = true;
454 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
456 static void drop_user_return_notifiers(void)
458 unsigned int cpu = smp_processor_id();
459 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
461 if (msrs->registered)
462 kvm_on_user_return(&msrs->urn);
465 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
467 return vcpu->arch.apic_base;
469 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
471 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
473 return kvm_apic_mode(kvm_get_apic_base(vcpu));
475 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
477 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
479 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
480 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
481 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
482 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
484 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
486 if (!msr_info->host_initiated) {
487 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
489 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
493 kvm_lapic_set_base(vcpu, msr_info->data);
494 kvm_recalculate_apic_map(vcpu->kvm);
497 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
500 * Handle a fault on a hardware virtualization (VMX or SVM) instruction.
502 * Hardware virtualization extension instructions may fault if a reboot turns
503 * off virtualization while processes are running. Usually after catching the
504 * fault we just panic; during reboot instead the instruction is ignored.
506 noinstr void kvm_spurious_fault(void)
508 /* Fault while not rebooting. We want the trace. */
509 BUG_ON(!kvm_rebooting);
511 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
513 #define EXCPT_BENIGN 0
514 #define EXCPT_CONTRIBUTORY 1
517 static int exception_class(int vector)
527 return EXCPT_CONTRIBUTORY;
534 #define EXCPT_FAULT 0
536 #define EXCPT_ABORT 2
537 #define EXCPT_INTERRUPT 3
539 static int exception_type(int vector)
543 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
544 return EXCPT_INTERRUPT;
548 /* #DB is trap, as instruction watchpoints are handled elsewhere */
549 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
552 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
555 /* Reserved exceptions will result in fault */
559 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
561 unsigned nr = vcpu->arch.exception.nr;
562 bool has_payload = vcpu->arch.exception.has_payload;
563 unsigned long payload = vcpu->arch.exception.payload;
571 * "Certain debug exceptions may clear bit 0-3. The
572 * remaining contents of the DR6 register are never
573 * cleared by the processor".
575 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
577 * In order to reflect the #DB exception payload in guest
578 * dr6, three components need to be considered: active low
579 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
581 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
582 * In the target guest dr6:
583 * FIXED_1 bits should always be set.
584 * Active low bits should be cleared if 1-setting in payload.
585 * Active high bits should be set if 1-setting in payload.
587 * Note, the payload is compatible with the pending debug
588 * exceptions/exit qualification under VMX, that active_low bits
589 * are active high in payload.
590 * So they need to be flipped for DR6.
592 vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
593 vcpu->arch.dr6 |= payload;
594 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW;
597 * The #DB payload is defined as compatible with the 'pending
598 * debug exceptions' field under VMX, not DR6. While bit 12 is
599 * defined in the 'pending debug exceptions' field (enabled
600 * breakpoint), it is reserved and must be zero in DR6.
602 vcpu->arch.dr6 &= ~BIT(12);
605 vcpu->arch.cr2 = payload;
609 vcpu->arch.exception.has_payload = false;
610 vcpu->arch.exception.payload = 0;
612 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
614 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
615 unsigned nr, bool has_error, u32 error_code,
616 bool has_payload, unsigned long payload, bool reinject)
621 kvm_make_request(KVM_REQ_EVENT, vcpu);
623 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
627 * On vmentry, vcpu->arch.exception.pending is only
628 * true if an event injection was blocked by
629 * nested_run_pending. In that case, however,
630 * vcpu_enter_guest requests an immediate exit,
631 * and the guest shouldn't proceed far enough to
634 WARN_ON_ONCE(vcpu->arch.exception.pending);
635 vcpu->arch.exception.injected = true;
636 if (WARN_ON_ONCE(has_payload)) {
638 * A reinjected event has already
639 * delivered its payload.
645 vcpu->arch.exception.pending = true;
646 vcpu->arch.exception.injected = false;
648 vcpu->arch.exception.has_error_code = has_error;
649 vcpu->arch.exception.nr = nr;
650 vcpu->arch.exception.error_code = error_code;
651 vcpu->arch.exception.has_payload = has_payload;
652 vcpu->arch.exception.payload = payload;
653 if (!is_guest_mode(vcpu))
654 kvm_deliver_exception_payload(vcpu);
658 /* to check exception */
659 prev_nr = vcpu->arch.exception.nr;
660 if (prev_nr == DF_VECTOR) {
661 /* triple fault -> shutdown */
662 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
665 class1 = exception_class(prev_nr);
666 class2 = exception_class(nr);
667 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
668 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
670 * Generate double fault per SDM Table 5-5. Set
671 * exception.pending = true so that the double fault
672 * can trigger a nested vmexit.
674 vcpu->arch.exception.pending = true;
675 vcpu->arch.exception.injected = false;
676 vcpu->arch.exception.has_error_code = true;
677 vcpu->arch.exception.nr = DF_VECTOR;
678 vcpu->arch.exception.error_code = 0;
679 vcpu->arch.exception.has_payload = false;
680 vcpu->arch.exception.payload = 0;
682 /* replace previous exception with a new one in a hope
683 that instruction re-execution will regenerate lost
688 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
690 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
692 EXPORT_SYMBOL_GPL(kvm_queue_exception);
694 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
696 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
698 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
700 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
701 unsigned long payload)
703 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
705 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
707 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
708 u32 error_code, unsigned long payload)
710 kvm_multiple_exception(vcpu, nr, true, error_code,
711 true, payload, false);
714 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
717 kvm_inject_gp(vcpu, 0);
719 return kvm_skip_emulated_instruction(vcpu);
723 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
725 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err)
728 kvm_inject_gp(vcpu, 0);
732 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
733 EMULTYPE_COMPLETE_USER_EXIT);
736 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
738 ++vcpu->stat.pf_guest;
739 vcpu->arch.exception.nested_apf =
740 is_guest_mode(vcpu) && fault->async_page_fault;
741 if (vcpu->arch.exception.nested_apf) {
742 vcpu->arch.apf.nested_apf_token = fault->address;
743 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
745 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
749 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
751 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
752 struct x86_exception *fault)
754 struct kvm_mmu *fault_mmu;
755 WARN_ON_ONCE(fault->vector != PF_VECTOR);
757 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
761 * Invalidate the TLB entry for the faulting address, if it exists,
762 * else the access will fault indefinitely (and to emulate hardware).
764 if ((fault->error_code & PFERR_PRESENT_MASK) &&
765 !(fault->error_code & PFERR_RSVD_MASK))
766 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
767 fault_mmu->root.hpa);
769 fault_mmu->inject_page_fault(vcpu, fault);
770 return fault->nested_page_fault;
772 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
774 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
776 atomic_inc(&vcpu->arch.nmi_queued);
777 kvm_make_request(KVM_REQ_NMI, vcpu);
779 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
781 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
783 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
785 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
787 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
789 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
791 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
794 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
795 * a #GP and return false.
797 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
799 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl)
801 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
804 EXPORT_SYMBOL_GPL(kvm_require_cpl);
806 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
808 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
811 kvm_queue_exception(vcpu, UD_VECTOR);
814 EXPORT_SYMBOL_GPL(kvm_require_dr);
816 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
818 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2);
822 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
824 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
826 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
827 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
831 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
834 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated
837 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn),
838 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL);
839 if (real_gpa == UNMAPPED_GVA)
842 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */
843 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte,
844 cr3 & GENMASK(11, 5), sizeof(pdpte));
848 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
849 if ((pdpte[i] & PT_PRESENT_MASK) &&
850 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
856 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled.
857 * Shadow page roots need to be reconstructed instead.
859 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)))
860 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT);
862 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
863 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
864 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
865 vcpu->arch.pdptrs_from_userspace = false;
869 EXPORT_SYMBOL_GPL(load_pdptrs);
871 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
873 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
874 kvm_clear_async_pf_completion_queue(vcpu);
875 kvm_async_pf_hash_reset(vcpu);
878 * Clearing CR0.PG is defined to flush the TLB from the guest's
881 if (!(cr0 & X86_CR0_PG))
882 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
885 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS)
886 kvm_mmu_reset_context(vcpu);
888 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
889 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
890 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
891 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
893 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
895 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
897 unsigned long old_cr0 = kvm_read_cr0(vcpu);
902 if (cr0 & 0xffffffff00000000UL)
906 cr0 &= ~CR0_RESERVED_BITS;
908 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
911 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
915 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
916 (cr0 & X86_CR0_PG)) {
921 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
926 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
927 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) &&
928 !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
931 if (!(cr0 & X86_CR0_PG) &&
932 (is_64_bit_mode(vcpu) || kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)))
935 static_call(kvm_x86_set_cr0)(vcpu, cr0);
937 kvm_post_set_cr0(vcpu, old_cr0, cr0);
941 EXPORT_SYMBOL_GPL(kvm_set_cr0);
943 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
945 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
947 EXPORT_SYMBOL_GPL(kvm_lmsw);
949 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
951 if (vcpu->arch.guest_state_protected)
954 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
956 if (vcpu->arch.xcr0 != host_xcr0)
957 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
959 if (vcpu->arch.xsaves_enabled &&
960 vcpu->arch.ia32_xss != host_xss)
961 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
964 if (static_cpu_has(X86_FEATURE_PKU) &&
965 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
966 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
967 vcpu->arch.pkru != vcpu->arch.host_pkru)
968 write_pkru(vcpu->arch.pkru);
970 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
972 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
974 if (vcpu->arch.guest_state_protected)
977 if (static_cpu_has(X86_FEATURE_PKU) &&
978 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
979 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
980 vcpu->arch.pkru = rdpkru();
981 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
982 write_pkru(vcpu->arch.host_pkru);
985 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
987 if (vcpu->arch.xcr0 != host_xcr0)
988 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
990 if (vcpu->arch.xsaves_enabled &&
991 vcpu->arch.ia32_xss != host_xss)
992 wrmsrl(MSR_IA32_XSS, host_xss);
996 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
998 static inline u64 kvm_guest_supported_xcr0(struct kvm_vcpu *vcpu)
1000 return vcpu->arch.guest_fpu.fpstate->user_xfeatures;
1003 #ifdef CONFIG_X86_64
1004 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu)
1006 return kvm_guest_supported_xcr0(vcpu) & XFEATURE_MASK_USER_DYNAMIC;
1010 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
1013 u64 old_xcr0 = vcpu->arch.xcr0;
1016 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
1017 if (index != XCR_XFEATURE_ENABLED_MASK)
1019 if (!(xcr0 & XFEATURE_MASK_FP))
1021 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
1025 * Do not allow the guest to set bits that we do not support
1026 * saving. However, xcr0 bit 0 is always set, even if the
1027 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()).
1029 valid_bits = kvm_guest_supported_xcr0(vcpu) | XFEATURE_MASK_FP;
1030 if (xcr0 & ~valid_bits)
1033 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
1034 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
1037 if (xcr0 & XFEATURE_MASK_AVX512) {
1038 if (!(xcr0 & XFEATURE_MASK_YMM))
1040 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
1044 if ((xcr0 & XFEATURE_MASK_XTILE) &&
1045 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE))
1048 vcpu->arch.xcr0 = xcr0;
1050 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
1051 kvm_update_cpuid_runtime(vcpu);
1055 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu)
1057 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 ||
1058 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) {
1059 kvm_inject_gp(vcpu, 0);
1063 return kvm_skip_emulated_instruction(vcpu);
1065 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv);
1067 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1069 if (cr4 & cr4_reserved_bits)
1072 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
1075 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4);
1077 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4);
1079 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
1081 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
1082 kvm_mmu_reset_context(vcpu);
1085 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB
1086 * according to the SDM; however, stale prev_roots could be reused
1087 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we
1088 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST
1089 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed,
1093 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE))
1094 kvm_mmu_unload(vcpu);
1097 * The TLB has to be flushed for all PCIDs if any of the following
1098 * (architecturally required) changes happen:
1099 * - CR4.PCIDE is changed from 1 to 0
1100 * - CR4.PGE is toggled
1102 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT.
1104 if (((cr4 ^ old_cr4) & X86_CR4_PGE) ||
1105 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1106 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1109 * The TLB has to be flushed for the current PCID if any of the
1110 * following (architecturally required) changes happen:
1111 * - CR4.SMEP is changed from 0 to 1
1112 * - CR4.PAE is toggled
1114 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) ||
1115 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP)))
1116 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1119 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1121 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1123 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1125 if (!kvm_is_valid_cr4(vcpu, cr4))
1128 if (is_long_mode(vcpu)) {
1129 if (!(cr4 & X86_CR4_PAE))
1131 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1133 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1134 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS)
1135 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
1138 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1139 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1142 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1143 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1147 static_call(kvm_x86_set_cr4)(vcpu, cr4);
1149 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1153 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1155 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid)
1157 struct kvm_mmu *mmu = vcpu->arch.mmu;
1158 unsigned long roots_to_free = 0;
1162 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but
1163 * this is reachable when running EPT=1 and unrestricted_guest=0, and
1164 * also via the emulator. KVM's TDP page tables are not in the scope of
1165 * the invalidation, but the guest's TLB entries need to be flushed as
1166 * the CPU may have cached entries in its TLB for the target PCID.
1168 if (unlikely(tdp_enabled)) {
1169 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1174 * If neither the current CR3 nor any of the prev_roots use the given
1175 * PCID, then nothing needs to be done here because a resync will
1176 * happen anyway before switching to any other CR3.
1178 if (kvm_get_active_pcid(vcpu) == pcid) {
1179 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1180 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1184 * If PCID is disabled, there is no need to free prev_roots even if the
1185 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB
1188 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
1191 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
1192 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid)
1193 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
1195 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
1198 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1200 bool skip_tlb_flush = false;
1201 unsigned long pcid = 0;
1202 #ifdef CONFIG_X86_64
1203 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1206 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1207 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1208 pcid = cr3 & X86_CR3_PCID_MASK;
1212 /* PDPTRs are always reloaded for PAE paging. */
1213 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu))
1214 goto handle_tlb_flush;
1217 * Do not condition the GPA check on long mode, this helper is used to
1218 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that
1219 * the current vCPU mode is accurate.
1221 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3))
1224 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3))
1227 if (cr3 != kvm_read_cr3(vcpu))
1228 kvm_mmu_new_pgd(vcpu, cr3);
1230 vcpu->arch.cr3 = cr3;
1231 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
1232 /* Do not call post_set_cr3, we do not get here for confidential guests. */
1236 * A load of CR3 that flushes the TLB flushes only the current PCID,
1237 * even if PCID is disabled, in which case PCID=0 is flushed. It's a
1238 * moot point in the end because _disabling_ PCID will flush all PCIDs,
1239 * and it's impossible to use a non-zero PCID when PCID is disabled,
1240 * i.e. only PCID=0 can be relevant.
1242 if (!skip_tlb_flush)
1243 kvm_invalidate_pcid(vcpu, pcid);
1247 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1249 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1251 if (cr8 & CR8_RESERVED_BITS)
1253 if (lapic_in_kernel(vcpu))
1254 kvm_lapic_set_tpr(vcpu, cr8);
1256 vcpu->arch.cr8 = cr8;
1259 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1261 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1263 if (lapic_in_kernel(vcpu))
1264 return kvm_lapic_get_cr8(vcpu);
1266 return vcpu->arch.cr8;
1268 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1270 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1274 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1275 for (i = 0; i < KVM_NR_DB_REGS; i++)
1276 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1280 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1284 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1285 dr7 = vcpu->arch.guest_debug_dr7;
1287 dr7 = vcpu->arch.dr7;
1288 static_call(kvm_x86_set_dr7)(vcpu, dr7);
1289 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1290 if (dr7 & DR7_BP_EN_MASK)
1291 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1293 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1295 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1297 u64 fixed = DR6_FIXED_1;
1299 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1302 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1303 fixed |= DR6_BUS_LOCK;
1307 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1309 size_t size = ARRAY_SIZE(vcpu->arch.db);
1313 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1314 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1315 vcpu->arch.eff_db[dr] = val;
1319 if (!kvm_dr6_valid(val))
1321 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1325 if (!kvm_dr7_valid(val))
1327 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1328 kvm_update_dr7(vcpu);
1334 EXPORT_SYMBOL_GPL(kvm_set_dr);
1336 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1338 size_t size = ARRAY_SIZE(vcpu->arch.db);
1342 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1346 *val = vcpu->arch.dr6;
1350 *val = vcpu->arch.dr7;
1354 EXPORT_SYMBOL_GPL(kvm_get_dr);
1356 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu)
1358 u32 ecx = kvm_rcx_read(vcpu);
1361 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) {
1362 kvm_inject_gp(vcpu, 0);
1366 kvm_rax_write(vcpu, (u32)data);
1367 kvm_rdx_write(vcpu, data >> 32);
1368 return kvm_skip_emulated_instruction(vcpu);
1370 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc);
1373 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1374 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1376 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1377 * extract the supported MSRs from the related const lists.
1378 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1379 * capabilities of the host cpu. This capabilities test skips MSRs that are
1380 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1381 * may depend on host virtualization features rather than host cpu features.
1384 static const u32 msrs_to_save_all[] = {
1385 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1387 #ifdef CONFIG_X86_64
1388 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1390 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1391 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1393 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1394 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1395 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1396 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1397 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1398 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1399 MSR_IA32_UMWAIT_CONTROL,
1401 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1402 MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
1403 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1404 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1405 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1406 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1407 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1408 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1409 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1410 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1411 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1412 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1413 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1414 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1415 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1416 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1417 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1418 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1419 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1420 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1421 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1422 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1424 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
1425 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
1426 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
1427 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
1428 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
1429 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
1430 MSR_IA32_XFD, MSR_IA32_XFD_ERR,
1433 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1434 static unsigned num_msrs_to_save;
1436 static const u32 emulated_msrs_all[] = {
1437 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1438 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1439 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1440 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1441 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1442 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1443 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1445 HV_X64_MSR_VP_INDEX,
1446 HV_X64_MSR_VP_RUNTIME,
1447 HV_X64_MSR_SCONTROL,
1448 HV_X64_MSR_STIMER0_CONFIG,
1449 HV_X64_MSR_VP_ASSIST_PAGE,
1450 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1451 HV_X64_MSR_TSC_EMULATION_STATUS,
1452 HV_X64_MSR_SYNDBG_OPTIONS,
1453 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1454 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1455 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1457 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1458 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1460 MSR_IA32_TSC_ADJUST,
1461 MSR_IA32_TSC_DEADLINE,
1462 MSR_IA32_ARCH_CAPABILITIES,
1463 MSR_IA32_PERF_CAPABILITIES,
1464 MSR_IA32_MISC_ENABLE,
1465 MSR_IA32_MCG_STATUS,
1467 MSR_IA32_MCG_EXT_CTL,
1471 MSR_MISC_FEATURES_ENABLES,
1472 MSR_AMD64_VIRT_SPEC_CTRL,
1473 MSR_AMD64_TSC_RATIO,
1478 * The following list leaves out MSRs whose values are determined
1479 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1480 * We always support the "true" VMX control MSRs, even if the host
1481 * processor does not, so I am putting these registers here rather
1482 * than in msrs_to_save_all.
1485 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1486 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1487 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1488 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1490 MSR_IA32_VMX_CR0_FIXED0,
1491 MSR_IA32_VMX_CR4_FIXED0,
1492 MSR_IA32_VMX_VMCS_ENUM,
1493 MSR_IA32_VMX_PROCBASED_CTLS2,
1494 MSR_IA32_VMX_EPT_VPID_CAP,
1495 MSR_IA32_VMX_VMFUNC,
1498 MSR_KVM_POLL_CONTROL,
1501 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1502 static unsigned num_emulated_msrs;
1505 * List of msr numbers which are used to expose MSR-based features that
1506 * can be used by a hypervisor to validate requested CPU features.
1508 static const u32 msr_based_features_all[] = {
1510 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1511 MSR_IA32_VMX_PINBASED_CTLS,
1512 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1513 MSR_IA32_VMX_PROCBASED_CTLS,
1514 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1515 MSR_IA32_VMX_EXIT_CTLS,
1516 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1517 MSR_IA32_VMX_ENTRY_CTLS,
1519 MSR_IA32_VMX_CR0_FIXED0,
1520 MSR_IA32_VMX_CR0_FIXED1,
1521 MSR_IA32_VMX_CR4_FIXED0,
1522 MSR_IA32_VMX_CR4_FIXED1,
1523 MSR_IA32_VMX_VMCS_ENUM,
1524 MSR_IA32_VMX_PROCBASED_CTLS2,
1525 MSR_IA32_VMX_EPT_VPID_CAP,
1526 MSR_IA32_VMX_VMFUNC,
1530 MSR_IA32_ARCH_CAPABILITIES,
1531 MSR_IA32_PERF_CAPABILITIES,
1534 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1535 static unsigned int num_msr_based_features;
1537 static u64 kvm_get_arch_capabilities(void)
1541 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1542 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1545 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1546 * the nested hypervisor runs with NX huge pages. If it is not,
1547 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other
1548 * L1 guests, so it need not worry about its own (L2) guests.
1550 data |= ARCH_CAP_PSCHANGE_MC_NO;
1553 * If we're doing cache flushes (either "always" or "cond")
1554 * we will do one whenever the guest does a vmlaunch/vmresume.
1555 * If an outer hypervisor is doing the cache flush for us
1556 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1557 * capability to the guest too, and if EPT is disabled we're not
1558 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1559 * require a nested hypervisor to do a flush of its own.
1561 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1562 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1564 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1565 data |= ARCH_CAP_RDCL_NO;
1566 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1567 data |= ARCH_CAP_SSB_NO;
1568 if (!boot_cpu_has_bug(X86_BUG_MDS))
1569 data |= ARCH_CAP_MDS_NO;
1571 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1573 * If RTM=0 because the kernel has disabled TSX, the host might
1574 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1575 * and therefore knows that there cannot be TAA) but keep
1576 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1577 * and we want to allow migrating those guests to tsx=off hosts.
1579 data &= ~ARCH_CAP_TAA_NO;
1580 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1581 data |= ARCH_CAP_TAA_NO;
1584 * Nothing to do here; we emulate TSX_CTRL if present on the
1585 * host so the guest can choose between disabling TSX or
1586 * using VERW to clear CPU buffers.
1593 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1595 switch (msr->index) {
1596 case MSR_IA32_ARCH_CAPABILITIES:
1597 msr->data = kvm_get_arch_capabilities();
1599 case MSR_IA32_UCODE_REV:
1600 rdmsrl_safe(msr->index, &msr->data);
1603 return static_call(kvm_x86_get_msr_feature)(msr);
1608 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1610 struct kvm_msr_entry msr;
1614 r = kvm_get_msr_feature(&msr);
1616 if (r == KVM_MSR_RET_INVALID) {
1617 /* Unconditionally clear the output for simplicity */
1619 if (kvm_msr_ignored_check(index, 0, false))
1631 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1633 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1636 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1639 if (efer & (EFER_LME | EFER_LMA) &&
1640 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1643 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1649 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1651 if (efer & efer_reserved_bits)
1654 return __kvm_valid_efer(vcpu, efer);
1656 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1658 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1660 u64 old_efer = vcpu->arch.efer;
1661 u64 efer = msr_info->data;
1664 if (efer & efer_reserved_bits)
1667 if (!msr_info->host_initiated) {
1668 if (!__kvm_valid_efer(vcpu, efer))
1671 if (is_paging(vcpu) &&
1672 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1677 efer |= vcpu->arch.efer & EFER_LMA;
1679 r = static_call(kvm_x86_set_efer)(vcpu, efer);
1685 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
1686 kvm_mmu_reset_context(vcpu);
1691 void kvm_enable_efer_bits(u64 mask)
1693 efer_reserved_bits &= ~mask;
1695 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1697 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1699 struct kvm_x86_msr_filter *msr_filter;
1700 struct msr_bitmap_range *ranges;
1701 struct kvm *kvm = vcpu->kvm;
1706 /* x2APIC MSRs do not support filtering. */
1707 if (index >= 0x800 && index <= 0x8ff)
1710 idx = srcu_read_lock(&kvm->srcu);
1712 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu);
1718 allowed = msr_filter->default_allow;
1719 ranges = msr_filter->ranges;
1721 for (i = 0; i < msr_filter->count; i++) {
1722 u32 start = ranges[i].base;
1723 u32 end = start + ranges[i].nmsrs;
1724 u32 flags = ranges[i].flags;
1725 unsigned long *bitmap = ranges[i].bitmap;
1727 if ((index >= start) && (index < end) && (flags & type)) {
1728 allowed = !!test_bit(index - start, bitmap);
1734 srcu_read_unlock(&kvm->srcu, idx);
1738 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1741 * Write @data into the MSR specified by @index. Select MSR specific fault
1742 * checks are bypassed if @host_initiated is %true.
1743 * Returns 0 on success, non-0 otherwise.
1744 * Assumes vcpu_load() was already called.
1746 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1747 bool host_initiated)
1749 struct msr_data msr;
1754 case MSR_KERNEL_GS_BASE:
1757 if (is_noncanonical_address(data, vcpu))
1760 case MSR_IA32_SYSENTER_EIP:
1761 case MSR_IA32_SYSENTER_ESP:
1763 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1764 * non-canonical address is written on Intel but not on
1765 * AMD (which ignores the top 32-bits, because it does
1766 * not implement 64-bit SYSENTER).
1768 * 64-bit code should hence be able to write a non-canonical
1769 * value on AMD. Making the address canonical ensures that
1770 * vmentry does not fail on Intel after writing a non-canonical
1771 * value, and that something deterministic happens if the guest
1772 * invokes 64-bit SYSENTER.
1774 data = __canonical_address(data, vcpu_virt_addr_bits(vcpu));
1777 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1780 if (!host_initiated &&
1781 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1782 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1786 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
1787 * incomplete and conflicting architectural behavior. Current
1788 * AMD CPUs completely ignore bits 63:32, i.e. they aren't
1789 * reserved and always read as zeros. Enforce Intel's reserved
1790 * bits check if and only if the guest CPU is Intel, and clear
1791 * the bits in all other cases. This ensures cross-vendor
1792 * migration will provide consistent behavior for the guest.
1794 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0)
1803 msr.host_initiated = host_initiated;
1805 return static_call(kvm_x86_set_msr)(vcpu, &msr);
1808 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1809 u32 index, u64 data, bool host_initiated)
1811 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1813 if (ret == KVM_MSR_RET_INVALID)
1814 if (kvm_msr_ignored_check(index, data, true))
1821 * Read the MSR specified by @index into @data. Select MSR specific fault
1822 * checks are bypassed if @host_initiated is %true.
1823 * Returns 0 on success, non-0 otherwise.
1824 * Assumes vcpu_load() was already called.
1826 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1827 bool host_initiated)
1829 struct msr_data msr;
1834 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1837 if (!host_initiated &&
1838 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1839 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1845 msr.host_initiated = host_initiated;
1847 ret = static_call(kvm_x86_get_msr)(vcpu, &msr);
1853 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1854 u32 index, u64 *data, bool host_initiated)
1856 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1858 if (ret == KVM_MSR_RET_INVALID) {
1859 /* Unconditionally clear *data for simplicity */
1861 if (kvm_msr_ignored_check(index, 0, false))
1868 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1870 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1871 return KVM_MSR_RET_FILTERED;
1872 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1875 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data)
1877 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1878 return KVM_MSR_RET_FILTERED;
1879 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1882 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1884 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1886 EXPORT_SYMBOL_GPL(kvm_get_msr);
1888 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1890 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1892 EXPORT_SYMBOL_GPL(kvm_set_msr);
1894 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu)
1896 if (!vcpu->run->msr.error) {
1897 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1898 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1902 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu)
1904 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error);
1907 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1909 complete_userspace_rdmsr(vcpu);
1910 return complete_emulated_msr_access(vcpu);
1913 static int complete_fast_msr_access(struct kvm_vcpu *vcpu)
1915 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error);
1918 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu)
1920 complete_userspace_rdmsr(vcpu);
1921 return complete_fast_msr_access(vcpu);
1924 static u64 kvm_msr_reason(int r)
1927 case KVM_MSR_RET_INVALID:
1928 return KVM_MSR_EXIT_REASON_UNKNOWN;
1929 case KVM_MSR_RET_FILTERED:
1930 return KVM_MSR_EXIT_REASON_FILTER;
1932 return KVM_MSR_EXIT_REASON_INVAL;
1936 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1937 u32 exit_reason, u64 data,
1938 int (*completion)(struct kvm_vcpu *vcpu),
1941 u64 msr_reason = kvm_msr_reason(r);
1943 /* Check if the user wanted to know about this MSR fault */
1944 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
1947 vcpu->run->exit_reason = exit_reason;
1948 vcpu->run->msr.error = 0;
1949 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
1950 vcpu->run->msr.reason = msr_reason;
1951 vcpu->run->msr.index = index;
1952 vcpu->run->msr.data = data;
1953 vcpu->arch.complete_userspace_io = completion;
1958 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1960 u32 ecx = kvm_rcx_read(vcpu);
1964 r = kvm_get_msr_with_filter(vcpu, ecx, &data);
1967 trace_kvm_msr_read(ecx, data);
1969 kvm_rax_write(vcpu, data & -1u);
1970 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1972 /* MSR read failed? See if we should ask user space */
1973 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0,
1974 complete_fast_rdmsr, r))
1976 trace_kvm_msr_read_ex(ecx);
1979 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
1981 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1983 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1985 u32 ecx = kvm_rcx_read(vcpu);
1986 u64 data = kvm_read_edx_eax(vcpu);
1989 r = kvm_set_msr_with_filter(vcpu, ecx, data);
1992 trace_kvm_msr_write(ecx, data);
1994 /* MSR write failed? See if we should ask user space */
1995 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data,
1996 complete_fast_msr_access, r))
1998 /* Signal all other negative errors to userspace */
2001 trace_kvm_msr_write_ex(ecx, data);
2004 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2006 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
2008 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu)
2010 return kvm_skip_emulated_instruction(vcpu);
2012 EXPORT_SYMBOL_GPL(kvm_emulate_as_nop);
2014 int kvm_emulate_invd(struct kvm_vcpu *vcpu)
2016 /* Treat an INVD instruction as a NOP and just skip it. */
2017 return kvm_emulate_as_nop(vcpu);
2019 EXPORT_SYMBOL_GPL(kvm_emulate_invd);
2021 int kvm_emulate_mwait(struct kvm_vcpu *vcpu)
2023 pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n");
2024 return kvm_emulate_as_nop(vcpu);
2026 EXPORT_SYMBOL_GPL(kvm_emulate_mwait);
2028 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu)
2030 kvm_queue_exception(vcpu, UD_VECTOR);
2033 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op);
2035 int kvm_emulate_monitor(struct kvm_vcpu *vcpu)
2037 pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n");
2038 return kvm_emulate_as_nop(vcpu);
2040 EXPORT_SYMBOL_GPL(kvm_emulate_monitor);
2042 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
2044 xfer_to_guest_mode_prepare();
2045 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
2046 xfer_to_guest_mode_work_pending();
2050 * The fast path for frequent and performance sensitive wrmsr emulation,
2051 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
2052 * the latency of virtual IPI by avoiding the expensive bits of transitioning
2053 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
2054 * other cases which must be called after interrupts are enabled on the host.
2056 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
2058 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
2061 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
2062 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
2063 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
2064 ((u32)(data >> 32) != X2APIC_BROADCAST))
2065 return kvm_x2apic_icr_write(vcpu->arch.apic, data);
2070 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
2072 if (!kvm_can_use_hv_timer(vcpu))
2075 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2079 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
2081 u32 msr = kvm_rcx_read(vcpu);
2083 fastpath_t ret = EXIT_FASTPATH_NONE;
2086 case APIC_BASE_MSR + (APIC_ICR >> 4):
2087 data = kvm_read_edx_eax(vcpu);
2088 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
2089 kvm_skip_emulated_instruction(vcpu);
2090 ret = EXIT_FASTPATH_EXIT_HANDLED;
2093 case MSR_IA32_TSC_DEADLINE:
2094 data = kvm_read_edx_eax(vcpu);
2095 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
2096 kvm_skip_emulated_instruction(vcpu);
2097 ret = EXIT_FASTPATH_REENTER_GUEST;
2104 if (ret != EXIT_FASTPATH_NONE)
2105 trace_kvm_msr_write(msr, data);
2109 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
2112 * Adapt set_msr() to msr_io()'s calling convention
2114 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2116 return kvm_get_msr_ignored_check(vcpu, index, data, true);
2119 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2121 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
2124 #ifdef CONFIG_X86_64
2125 struct pvclock_clock {
2135 struct pvclock_gtod_data {
2138 struct pvclock_clock clock; /* extract of a clocksource struct */
2139 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
2145 static struct pvclock_gtod_data pvclock_gtod_data;
2147 static void update_pvclock_gtod(struct timekeeper *tk)
2149 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
2151 write_seqcount_begin(&vdata->seq);
2153 /* copy pvclock gtod data */
2154 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
2155 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
2156 vdata->clock.mask = tk->tkr_mono.mask;
2157 vdata->clock.mult = tk->tkr_mono.mult;
2158 vdata->clock.shift = tk->tkr_mono.shift;
2159 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
2160 vdata->clock.offset = tk->tkr_mono.base;
2162 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
2163 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
2164 vdata->raw_clock.mask = tk->tkr_raw.mask;
2165 vdata->raw_clock.mult = tk->tkr_raw.mult;
2166 vdata->raw_clock.shift = tk->tkr_raw.shift;
2167 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
2168 vdata->raw_clock.offset = tk->tkr_raw.base;
2170 vdata->wall_time_sec = tk->xtime_sec;
2172 vdata->offs_boot = tk->offs_boot;
2174 write_seqcount_end(&vdata->seq);
2177 static s64 get_kvmclock_base_ns(void)
2179 /* Count up from boot time, but with the frequency of the raw clock. */
2180 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
2183 static s64 get_kvmclock_base_ns(void)
2185 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
2186 return ktime_get_boottime_ns();
2190 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs)
2194 struct pvclock_wall_clock wc;
2201 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
2206 ++version; /* first time write, random junk */
2210 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
2214 * The guest calculates current wall clock time by adding
2215 * system time (updated by kvm_guest_time_update below) to the
2216 * wall clock specified here. We do the reverse here.
2218 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
2220 wc.nsec = do_div(wall_nsec, 1000000000);
2221 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
2222 wc.version = version;
2224 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
2227 wc_sec_hi = wall_nsec >> 32;
2228 kvm_write_guest(kvm, wall_clock + sec_hi_ofs,
2229 &wc_sec_hi, sizeof(wc_sec_hi));
2233 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
2236 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
2237 bool old_msr, bool host_initiated)
2239 struct kvm_arch *ka = &vcpu->kvm->arch;
2241 if (vcpu->vcpu_id == 0 && !host_initiated) {
2242 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
2243 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2245 ka->boot_vcpu_runs_old_kvmclock = old_msr;
2248 vcpu->arch.time = system_time;
2249 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2251 /* we verify if the enable bit is set... */
2252 vcpu->arch.pv_time_enabled = false;
2253 if (!(system_time & 1))
2256 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2257 &vcpu->arch.pv_time, system_time & ~1ULL,
2258 sizeof(struct pvclock_vcpu_time_info)))
2259 vcpu->arch.pv_time_enabled = true;
2264 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2266 do_shl32_div32(dividend, divisor);
2270 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2271 s8 *pshift, u32 *pmultiplier)
2279 scaled64 = scaled_hz;
2280 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2285 tps32 = (uint32_t)tps64;
2286 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2287 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2295 *pmultiplier = div_frac(scaled64, tps32);
2298 #ifdef CONFIG_X86_64
2299 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2302 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2303 static unsigned long max_tsc_khz;
2305 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2307 u64 v = (u64)khz * (1000000 + ppm);
2312 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier);
2314 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2318 /* Guest TSC same frequency as host TSC? */
2320 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio);
2324 /* TSC scaling supported? */
2325 if (!kvm_has_tsc_control) {
2326 if (user_tsc_khz > tsc_khz) {
2327 vcpu->arch.tsc_catchup = 1;
2328 vcpu->arch.tsc_always_catchup = 1;
2331 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2336 /* TSC scaling required - calculate ratio */
2337 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
2338 user_tsc_khz, tsc_khz);
2340 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
2341 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2346 kvm_vcpu_write_tsc_multiplier(vcpu, ratio);
2350 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2352 u32 thresh_lo, thresh_hi;
2353 int use_scaling = 0;
2355 /* tsc_khz can be zero if TSC calibration fails */
2356 if (user_tsc_khz == 0) {
2357 /* set tsc_scaling_ratio to a safe value */
2358 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio);
2362 /* Compute a scale to convert nanoseconds in TSC cycles */
2363 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2364 &vcpu->arch.virtual_tsc_shift,
2365 &vcpu->arch.virtual_tsc_mult);
2366 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2369 * Compute the variation in TSC rate which is acceptable
2370 * within the range of tolerance and decide if the
2371 * rate being applied is within that bounds of the hardware
2372 * rate. If so, no scaling or compensation need be done.
2374 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2375 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2376 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2377 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2380 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2383 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2385 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2386 vcpu->arch.virtual_tsc_mult,
2387 vcpu->arch.virtual_tsc_shift);
2388 tsc += vcpu->arch.this_tsc_write;
2392 #ifdef CONFIG_X86_64
2393 static inline int gtod_is_based_on_tsc(int mode)
2395 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2399 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2401 #ifdef CONFIG_X86_64
2403 struct kvm_arch *ka = &vcpu->kvm->arch;
2404 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2406 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2407 atomic_read(&vcpu->kvm->online_vcpus));
2410 * Once the masterclock is enabled, always perform request in
2411 * order to update it.
2413 * In order to enable masterclock, the host clocksource must be TSC
2414 * and the vcpus need to have matched TSCs. When that happens,
2415 * perform request to enable masterclock.
2417 if (ka->use_master_clock ||
2418 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2419 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2421 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2422 atomic_read(&vcpu->kvm->online_vcpus),
2423 ka->use_master_clock, gtod->clock.vclock_mode);
2428 * Multiply tsc by a fixed point number represented by ratio.
2430 * The most significant 64-N bits (mult) of ratio represent the
2431 * integral part of the fixed point number; the remaining N bits
2432 * (frac) represent the fractional part, ie. ratio represents a fixed
2433 * point number (mult + frac * 2^(-N)).
2435 * N equals to kvm_tsc_scaling_ratio_frac_bits.
2437 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2439 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
2442 u64 kvm_scale_tsc(u64 tsc, u64 ratio)
2446 if (ratio != kvm_default_tsc_scaling_ratio)
2447 _tsc = __scale_tsc(ratio, tsc);
2451 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2453 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2457 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio);
2459 return target_tsc - tsc;
2462 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2464 return vcpu->arch.l1_tsc_offset +
2465 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio);
2467 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2469 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier)
2473 if (l2_multiplier == kvm_default_tsc_scaling_ratio)
2474 nested_offset = l1_offset;
2476 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier,
2477 kvm_tsc_scaling_ratio_frac_bits);
2479 nested_offset += l2_offset;
2480 return nested_offset;
2482 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset);
2484 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier)
2486 if (l2_multiplier != kvm_default_tsc_scaling_ratio)
2487 return mul_u64_u64_shr(l1_multiplier, l2_multiplier,
2488 kvm_tsc_scaling_ratio_frac_bits);
2490 return l1_multiplier;
2492 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier);
2494 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset)
2496 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2497 vcpu->arch.l1_tsc_offset,
2500 vcpu->arch.l1_tsc_offset = l1_offset;
2503 * If we are here because L1 chose not to trap WRMSR to TSC then
2504 * according to the spec this should set L1's TSC (as opposed to
2505 * setting L1's offset for L2).
2507 if (is_guest_mode(vcpu))
2508 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2510 static_call(kvm_x86_get_l2_tsc_offset)(vcpu),
2511 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2513 vcpu->arch.tsc_offset = l1_offset;
2515 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset);
2518 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier)
2520 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier;
2522 /* Userspace is changing the multiplier while L2 is active */
2523 if (is_guest_mode(vcpu))
2524 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2526 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2528 vcpu->arch.tsc_scaling_ratio = l1_multiplier;
2530 if (kvm_has_tsc_control)
2531 static_call(kvm_x86_write_tsc_multiplier)(
2532 vcpu, vcpu->arch.tsc_scaling_ratio);
2535 static inline bool kvm_check_tsc_unstable(void)
2537 #ifdef CONFIG_X86_64
2539 * TSC is marked unstable when we're running on Hyper-V,
2540 * 'TSC page' clocksource is good.
2542 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2545 return check_tsc_unstable();
2549 * Infers attempts to synchronize the guest's tsc from host writes. Sets the
2550 * offset for the vcpu and tracks the TSC matching generation that the vcpu
2553 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc,
2554 u64 ns, bool matched)
2556 struct kvm *kvm = vcpu->kvm;
2558 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2561 * We also track th most recent recorded KHZ, write and time to
2562 * allow the matching interval to be extended at each write.
2564 kvm->arch.last_tsc_nsec = ns;
2565 kvm->arch.last_tsc_write = tsc;
2566 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2567 kvm->arch.last_tsc_offset = offset;
2569 vcpu->arch.last_guest_tsc = tsc;
2571 kvm_vcpu_write_tsc_offset(vcpu, offset);
2575 * We split periods of matched TSC writes into generations.
2576 * For each generation, we track the original measured
2577 * nanosecond time, offset, and write, so if TSCs are in
2578 * sync, we can match exact offset, and if not, we can match
2579 * exact software computation in compute_guest_tsc()
2581 * These values are tracked in kvm->arch.cur_xxx variables.
2583 kvm->arch.cur_tsc_generation++;
2584 kvm->arch.cur_tsc_nsec = ns;
2585 kvm->arch.cur_tsc_write = tsc;
2586 kvm->arch.cur_tsc_offset = offset;
2587 kvm->arch.nr_vcpus_matched_tsc = 0;
2588 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) {
2589 kvm->arch.nr_vcpus_matched_tsc++;
2592 /* Keep track of which generation this VCPU has synchronized to */
2593 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2594 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2595 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2597 kvm_track_tsc_matching(vcpu);
2600 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2602 struct kvm *kvm = vcpu->kvm;
2603 u64 offset, ns, elapsed;
2604 unsigned long flags;
2605 bool matched = false;
2606 bool synchronizing = false;
2608 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2609 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2610 ns = get_kvmclock_base_ns();
2611 elapsed = ns - kvm->arch.last_tsc_nsec;
2613 if (vcpu->arch.virtual_tsc_khz) {
2616 * detection of vcpu initialization -- need to sync
2617 * with other vCPUs. This particularly helps to keep
2618 * kvm_clock stable after CPU hotplug
2620 synchronizing = true;
2622 u64 tsc_exp = kvm->arch.last_tsc_write +
2623 nsec_to_cycles(vcpu, elapsed);
2624 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2626 * Special case: TSC write with a small delta (1 second)
2627 * of virtual cycle time against real time is
2628 * interpreted as an attempt to synchronize the CPU.
2630 synchronizing = data < tsc_exp + tsc_hz &&
2631 data + tsc_hz > tsc_exp;
2636 * For a reliable TSC, we can match TSC offsets, and for an unstable
2637 * TSC, we add elapsed time in this computation. We could let the
2638 * compensation code attempt to catch up if we fall behind, but
2639 * it's better to try to match offsets from the beginning.
2641 if (synchronizing &&
2642 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2643 if (!kvm_check_tsc_unstable()) {
2644 offset = kvm->arch.cur_tsc_offset;
2646 u64 delta = nsec_to_cycles(vcpu, elapsed);
2648 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2653 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched);
2654 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2657 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2660 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2661 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2664 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2666 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2667 WARN_ON(adjustment < 0);
2668 adjustment = kvm_scale_tsc((u64) adjustment,
2669 vcpu->arch.l1_tsc_scaling_ratio);
2670 adjust_tsc_offset_guest(vcpu, adjustment);
2673 #ifdef CONFIG_X86_64
2675 static u64 read_tsc(void)
2677 u64 ret = (u64)rdtsc_ordered();
2678 u64 last = pvclock_gtod_data.clock.cycle_last;
2680 if (likely(ret >= last))
2684 * GCC likes to generate cmov here, but this branch is extremely
2685 * predictable (it's just a function of time and the likely is
2686 * very likely) and there's a data dependence, so force GCC
2687 * to generate a branch instead. I don't barrier() because
2688 * we don't actually need a barrier, and if this function
2689 * ever gets inlined it will generate worse code.
2695 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2701 switch (clock->vclock_mode) {
2702 case VDSO_CLOCKMODE_HVCLOCK:
2703 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2705 if (tsc_pg_val != U64_MAX) {
2706 /* TSC page valid */
2707 *mode = VDSO_CLOCKMODE_HVCLOCK;
2708 v = (tsc_pg_val - clock->cycle_last) &
2711 /* TSC page invalid */
2712 *mode = VDSO_CLOCKMODE_NONE;
2715 case VDSO_CLOCKMODE_TSC:
2716 *mode = VDSO_CLOCKMODE_TSC;
2717 *tsc_timestamp = read_tsc();
2718 v = (*tsc_timestamp - clock->cycle_last) &
2722 *mode = VDSO_CLOCKMODE_NONE;
2725 if (*mode == VDSO_CLOCKMODE_NONE)
2726 *tsc_timestamp = v = 0;
2728 return v * clock->mult;
2731 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2733 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2739 seq = read_seqcount_begin(>od->seq);
2740 ns = gtod->raw_clock.base_cycles;
2741 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2742 ns >>= gtod->raw_clock.shift;
2743 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2744 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2750 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2752 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2758 seq = read_seqcount_begin(>od->seq);
2759 ts->tv_sec = gtod->wall_time_sec;
2760 ns = gtod->clock.base_cycles;
2761 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2762 ns >>= gtod->clock.shift;
2763 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2765 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2771 /* returns true if host is using TSC based clocksource */
2772 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2774 /* checked again under seqlock below */
2775 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2778 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2782 /* returns true if host is using TSC based clocksource */
2783 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2786 /* checked again under seqlock below */
2787 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2790 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2796 * Assuming a stable TSC across physical CPUS, and a stable TSC
2797 * across virtual CPUs, the following condition is possible.
2798 * Each numbered line represents an event visible to both
2799 * CPUs at the next numbered event.
2801 * "timespecX" represents host monotonic time. "tscX" represents
2804 * VCPU0 on CPU0 | VCPU1 on CPU1
2806 * 1. read timespec0,tsc0
2807 * 2. | timespec1 = timespec0 + N
2809 * 3. transition to guest | transition to guest
2810 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2811 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2812 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2814 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2817 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2819 * - 0 < N - M => M < N
2821 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2822 * always the case (the difference between two distinct xtime instances
2823 * might be smaller then the difference between corresponding TSC reads,
2824 * when updating guest vcpus pvclock areas).
2826 * To avoid that problem, do not allow visibility of distinct
2827 * system_timestamp/tsc_timestamp values simultaneously: use a master
2828 * copy of host monotonic time values. Update that master copy
2831 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2835 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2837 #ifdef CONFIG_X86_64
2838 struct kvm_arch *ka = &kvm->arch;
2840 bool host_tsc_clocksource, vcpus_matched;
2842 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2843 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2844 atomic_read(&kvm->online_vcpus));
2847 * If the host uses TSC clock, then passthrough TSC as stable
2850 host_tsc_clocksource = kvm_get_time_and_clockread(
2851 &ka->master_kernel_ns,
2852 &ka->master_cycle_now);
2854 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2855 && !ka->backwards_tsc_observed
2856 && !ka->boot_vcpu_runs_old_kvmclock;
2858 if (ka->use_master_clock)
2859 atomic_set(&kvm_guest_has_master_clock, 1);
2861 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2862 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2867 static void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2869 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2872 static void __kvm_start_pvclock_update(struct kvm *kvm)
2874 raw_spin_lock_irq(&kvm->arch.tsc_write_lock);
2875 write_seqcount_begin(&kvm->arch.pvclock_sc);
2878 static void kvm_start_pvclock_update(struct kvm *kvm)
2880 kvm_make_mclock_inprogress_request(kvm);
2882 /* no guest entries from this point */
2883 __kvm_start_pvclock_update(kvm);
2886 static void kvm_end_pvclock_update(struct kvm *kvm)
2888 struct kvm_arch *ka = &kvm->arch;
2889 struct kvm_vcpu *vcpu;
2892 write_seqcount_end(&ka->pvclock_sc);
2893 raw_spin_unlock_irq(&ka->tsc_write_lock);
2894 kvm_for_each_vcpu(i, vcpu, kvm)
2895 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2897 /* guest entries allowed */
2898 kvm_for_each_vcpu(i, vcpu, kvm)
2899 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2902 static void kvm_update_masterclock(struct kvm *kvm)
2904 kvm_hv_request_tsc_page_update(kvm);
2905 kvm_start_pvclock_update(kvm);
2906 pvclock_update_vm_gtod_copy(kvm);
2907 kvm_end_pvclock_update(kvm);
2910 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */
2911 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
2913 struct kvm_arch *ka = &kvm->arch;
2914 struct pvclock_vcpu_time_info hv_clock;
2916 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2920 if (ka->use_master_clock && __this_cpu_read(cpu_tsc_khz)) {
2921 #ifdef CONFIG_X86_64
2922 struct timespec64 ts;
2924 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) {
2925 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec;
2926 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC;
2929 data->host_tsc = rdtsc();
2931 data->flags |= KVM_CLOCK_TSC_STABLE;
2932 hv_clock.tsc_timestamp = ka->master_cycle_now;
2933 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2934 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2935 &hv_clock.tsc_shift,
2936 &hv_clock.tsc_to_system_mul);
2937 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc);
2939 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset;
2945 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
2947 struct kvm_arch *ka = &kvm->arch;
2951 seq = read_seqcount_begin(&ka->pvclock_sc);
2952 __get_kvmclock(kvm, data);
2953 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
2956 u64 get_kvmclock_ns(struct kvm *kvm)
2958 struct kvm_clock_data data;
2960 get_kvmclock(kvm, &data);
2964 static void kvm_setup_pvclock_page(struct kvm_vcpu *v,
2965 struct gfn_to_hva_cache *cache,
2966 unsigned int offset)
2968 struct kvm_vcpu_arch *vcpu = &v->arch;
2969 struct pvclock_vcpu_time_info guest_hv_clock;
2971 if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache,
2972 &guest_hv_clock, offset, sizeof(guest_hv_clock))))
2975 /* This VCPU is paused, but it's legal for a guest to read another
2976 * VCPU's kvmclock, so we really have to follow the specification where
2977 * it says that version is odd if data is being modified, and even after
2980 * Version field updates must be kept separate. This is because
2981 * kvm_write_guest_cached might use a "rep movs" instruction, and
2982 * writes within a string instruction are weakly ordered. So there
2983 * are three writes overall.
2985 * As a small optimization, only write the version field in the first
2986 * and third write. The vcpu->pv_time cache is still valid, because the
2987 * version field is the first in the struct.
2989 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2991 if (guest_hv_clock.version & 1)
2992 ++guest_hv_clock.version; /* first time write, random junk */
2994 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2995 kvm_write_guest_offset_cached(v->kvm, cache,
2996 &vcpu->hv_clock, offset,
2997 sizeof(vcpu->hv_clock.version));
3001 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
3002 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
3004 if (vcpu->pvclock_set_guest_stopped_request) {
3005 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
3006 vcpu->pvclock_set_guest_stopped_request = false;
3009 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
3011 kvm_write_guest_offset_cached(v->kvm, cache,
3012 &vcpu->hv_clock, offset,
3013 sizeof(vcpu->hv_clock));
3017 vcpu->hv_clock.version++;
3018 kvm_write_guest_offset_cached(v->kvm, cache,
3019 &vcpu->hv_clock, offset,
3020 sizeof(vcpu->hv_clock.version));
3023 static int kvm_guest_time_update(struct kvm_vcpu *v)
3025 unsigned long flags, tgt_tsc_khz;
3027 struct kvm_vcpu_arch *vcpu = &v->arch;
3028 struct kvm_arch *ka = &v->kvm->arch;
3030 u64 tsc_timestamp, host_tsc;
3032 bool use_master_clock;
3038 * If the host uses TSC clock, then passthrough TSC as stable
3042 seq = read_seqcount_begin(&ka->pvclock_sc);
3043 use_master_clock = ka->use_master_clock;
3044 if (use_master_clock) {
3045 host_tsc = ka->master_cycle_now;
3046 kernel_ns = ka->master_kernel_ns;
3048 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3050 /* Keep irq disabled to prevent changes to the clock */
3051 local_irq_save(flags);
3052 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
3053 if (unlikely(tgt_tsc_khz == 0)) {
3054 local_irq_restore(flags);
3055 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3058 if (!use_master_clock) {
3060 kernel_ns = get_kvmclock_base_ns();
3063 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
3066 * We may have to catch up the TSC to match elapsed wall clock
3067 * time for two reasons, even if kvmclock is used.
3068 * 1) CPU could have been running below the maximum TSC rate
3069 * 2) Broken TSC compensation resets the base at each VCPU
3070 * entry to avoid unknown leaps of TSC even when running
3071 * again on the same CPU. This may cause apparent elapsed
3072 * time to disappear, and the guest to stand still or run
3075 if (vcpu->tsc_catchup) {
3076 u64 tsc = compute_guest_tsc(v, kernel_ns);
3077 if (tsc > tsc_timestamp) {
3078 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
3079 tsc_timestamp = tsc;
3083 local_irq_restore(flags);
3085 /* With all the info we got, fill in the values */
3087 if (kvm_has_tsc_control)
3088 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz,
3089 v->arch.l1_tsc_scaling_ratio);
3091 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3092 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
3093 &vcpu->hv_clock.tsc_shift,
3094 &vcpu->hv_clock.tsc_to_system_mul);
3095 vcpu->hw_tsc_khz = tgt_tsc_khz;
3098 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
3099 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
3100 vcpu->last_guest_tsc = tsc_timestamp;
3102 /* If the host uses TSC clocksource, then it is stable */
3104 if (use_master_clock)
3105 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
3107 vcpu->hv_clock.flags = pvclock_flags;
3109 if (vcpu->pv_time_enabled)
3110 kvm_setup_pvclock_page(v, &vcpu->pv_time, 0);
3111 if (vcpu->xen.vcpu_info_set)
3112 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache,
3113 offsetof(struct compat_vcpu_info, time));
3114 if (vcpu->xen.vcpu_time_info_set)
3115 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0);
3116 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
3121 * kvmclock updates which are isolated to a given vcpu, such as
3122 * vcpu->cpu migration, should not allow system_timestamp from
3123 * the rest of the vcpus to remain static. Otherwise ntp frequency
3124 * correction applies to one vcpu's system_timestamp but not
3127 * So in those cases, request a kvmclock update for all vcpus.
3128 * We need to rate-limit these requests though, as they can
3129 * considerably slow guests that have a large number of vcpus.
3130 * The time for a remote vcpu to update its kvmclock is bound
3131 * by the delay we use to rate-limit the updates.
3134 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
3136 static void kvmclock_update_fn(struct work_struct *work)
3139 struct delayed_work *dwork = to_delayed_work(work);
3140 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3141 kvmclock_update_work);
3142 struct kvm *kvm = container_of(ka, struct kvm, arch);
3143 struct kvm_vcpu *vcpu;
3145 kvm_for_each_vcpu(i, vcpu, kvm) {
3146 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3147 kvm_vcpu_kick(vcpu);
3151 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
3153 struct kvm *kvm = v->kvm;
3155 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3156 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
3157 KVMCLOCK_UPDATE_DELAY);
3160 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
3162 static void kvmclock_sync_fn(struct work_struct *work)
3164 struct delayed_work *dwork = to_delayed_work(work);
3165 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3166 kvmclock_sync_work);
3167 struct kvm *kvm = container_of(ka, struct kvm, arch);
3169 if (!kvmclock_periodic_sync)
3172 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
3173 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
3174 KVMCLOCK_SYNC_PERIOD);
3178 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
3180 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
3182 /* McStatusWrEn enabled? */
3183 if (guest_cpuid_is_amd_or_hygon(vcpu))
3184 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
3189 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3191 u64 mcg_cap = vcpu->arch.mcg_cap;
3192 unsigned bank_num = mcg_cap & 0xff;
3193 u32 msr = msr_info->index;
3194 u64 data = msr_info->data;
3197 case MSR_IA32_MCG_STATUS:
3198 vcpu->arch.mcg_status = data;
3200 case MSR_IA32_MCG_CTL:
3201 if (!(mcg_cap & MCG_CTL_P) &&
3202 (data || !msr_info->host_initiated))
3204 if (data != 0 && data != ~(u64)0)
3206 vcpu->arch.mcg_ctl = data;
3209 if (msr >= MSR_IA32_MC0_CTL &&
3210 msr < MSR_IA32_MCx_CTL(bank_num)) {
3211 u32 offset = array_index_nospec(
3212 msr - MSR_IA32_MC0_CTL,
3213 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3215 /* only 0 or all 1s can be written to IA32_MCi_CTL
3216 * some Linux kernels though clear bit 10 in bank 4 to
3217 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
3218 * this to avoid an uncatched #GP in the guest
3220 if ((offset & 0x3) == 0 &&
3221 data != 0 && (data | (1 << 10)) != ~(u64)0)
3225 if (!msr_info->host_initiated &&
3226 (offset & 0x3) == 1 && data != 0) {
3227 if (!can_set_mci_status(vcpu))
3231 vcpu->arch.mce_banks[offset] = data;
3239 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
3241 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
3243 return (vcpu->arch.apf.msr_en_val & mask) == mask;
3246 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
3248 gpa_t gpa = data & ~0x3f;
3250 /* Bits 4:5 are reserved, Should be zero */
3254 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
3255 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
3258 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
3259 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
3262 if (!lapic_in_kernel(vcpu))
3263 return data ? 1 : 0;
3265 vcpu->arch.apf.msr_en_val = data;
3267 if (!kvm_pv_async_pf_enabled(vcpu)) {
3268 kvm_clear_async_pf_completion_queue(vcpu);
3269 kvm_async_pf_hash_reset(vcpu);
3273 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
3277 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
3278 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
3280 kvm_async_pf_wakeup_all(vcpu);
3285 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
3287 /* Bits 8-63 are reserved */
3291 if (!lapic_in_kernel(vcpu))
3294 vcpu->arch.apf.msr_int_val = data;
3296 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
3301 static void kvmclock_reset(struct kvm_vcpu *vcpu)
3303 vcpu->arch.pv_time_enabled = false;
3304 vcpu->arch.time = 0;
3307 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
3309 ++vcpu->stat.tlb_flush;
3310 static_call(kvm_x86_flush_tlb_all)(vcpu);
3313 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
3315 ++vcpu->stat.tlb_flush;
3319 * A TLB flush on behalf of the guest is equivalent to
3320 * INVPCID(all), toggling CR4.PGE, etc., which requires
3321 * a forced sync of the shadow page tables. Ensure all the
3322 * roots are synced and the guest TLB in hardware is clean.
3324 kvm_mmu_sync_roots(vcpu);
3325 kvm_mmu_sync_prev_roots(vcpu);
3328 static_call(kvm_x86_flush_tlb_guest)(vcpu);
3332 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
3334 ++vcpu->stat.tlb_flush;
3335 static_call(kvm_x86_flush_tlb_current)(vcpu);
3339 * Service "local" TLB flush requests, which are specific to the current MMU
3340 * context. In addition to the generic event handling in vcpu_enter_guest(),
3341 * TLB flushes that are targeted at an MMU context also need to be serviced
3342 * prior before nested VM-Enter/VM-Exit.
3344 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu)
3346 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
3347 kvm_vcpu_flush_tlb_current(vcpu);
3349 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu))
3350 kvm_vcpu_flush_tlb_guest(vcpu);
3352 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests);
3354 static void record_steal_time(struct kvm_vcpu *vcpu)
3356 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
3357 struct kvm_steal_time __user *st;
3358 struct kvm_memslots *slots;
3362 if (kvm_xen_msr_enabled(vcpu->kvm)) {
3363 kvm_xen_runstate_set_running(vcpu);
3367 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3370 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm))
3373 slots = kvm_memslots(vcpu->kvm);
3375 if (unlikely(slots->generation != ghc->generation ||
3376 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) {
3377 gfn_t gfn = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
3379 /* We rely on the fact that it fits in a single page. */
3380 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS);
3382 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gfn, sizeof(*st)) ||
3383 kvm_is_error_hva(ghc->hva) || !ghc->memslot)
3387 st = (struct kvm_steal_time __user *)ghc->hva;
3389 * Doing a TLB flush here, on the guest's behalf, can avoid
3392 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
3393 u8 st_preempted = 0;
3396 if (!user_access_begin(st, sizeof(*st)))
3399 asm volatile("1: xchgb %0, %2\n"
3402 _ASM_EXTABLE_UA(1b, 2b)
3403 : "+q" (st_preempted),
3405 "+m" (st->preempted));
3411 vcpu->arch.st.preempted = 0;
3413 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
3414 st_preempted & KVM_VCPU_FLUSH_TLB);
3415 if (st_preempted & KVM_VCPU_FLUSH_TLB)
3416 kvm_vcpu_flush_tlb_guest(vcpu);
3418 if (!user_access_begin(st, sizeof(*st)))
3421 if (!user_access_begin(st, sizeof(*st)))
3424 unsafe_put_user(0, &st->preempted, out);
3425 vcpu->arch.st.preempted = 0;
3428 unsafe_get_user(version, &st->version, out);
3430 version += 1; /* first time write, random junk */
3433 unsafe_put_user(version, &st->version, out);
3437 unsafe_get_user(steal, &st->steal, out);
3438 steal += current->sched_info.run_delay -
3439 vcpu->arch.st.last_steal;
3440 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3441 unsafe_put_user(steal, &st->steal, out);
3444 unsafe_put_user(version, &st->version, out);
3449 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
3452 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3455 u32 msr = msr_info->index;
3456 u64 data = msr_info->data;
3458 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr)
3459 return kvm_xen_write_hypercall_page(vcpu, data);
3462 case MSR_AMD64_NB_CFG:
3463 case MSR_IA32_UCODE_WRITE:
3464 case MSR_VM_HSAVE_PA:
3465 case MSR_AMD64_PATCH_LOADER:
3466 case MSR_AMD64_BU_CFG2:
3467 case MSR_AMD64_DC_CFG:
3468 case MSR_F15H_EX_CFG:
3471 case MSR_IA32_UCODE_REV:
3472 if (msr_info->host_initiated)
3473 vcpu->arch.microcode_version = data;
3475 case MSR_IA32_ARCH_CAPABILITIES:
3476 if (!msr_info->host_initiated)
3478 vcpu->arch.arch_capabilities = data;
3480 case MSR_IA32_PERF_CAPABILITIES: {
3481 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
3483 if (!msr_info->host_initiated)
3485 if (kvm_get_msr_feature(&msr_ent))
3487 if (data & ~msr_ent.data)
3490 vcpu->arch.perf_capabilities = data;
3495 return set_efer(vcpu, msr_info);
3497 data &= ~(u64)0x40; /* ignore flush filter disable */
3498 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3499 data &= ~(u64)0x8; /* ignore TLB cache disable */
3501 /* Handle McStatusWrEn */
3502 if (data == BIT_ULL(18)) {
3503 vcpu->arch.msr_hwcr = data;
3504 } else if (data != 0) {
3505 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3510 case MSR_FAM10H_MMIO_CONF_BASE:
3512 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3517 case 0x200 ... 0x2ff:
3518 return kvm_mtrr_set_msr(vcpu, msr, data);
3519 case MSR_IA32_APICBASE:
3520 return kvm_set_apic_base(vcpu, msr_info);
3521 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3522 return kvm_x2apic_msr_write(vcpu, msr, data);
3523 case MSR_IA32_TSC_DEADLINE:
3524 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3526 case MSR_IA32_TSC_ADJUST:
3527 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3528 if (!msr_info->host_initiated) {
3529 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3530 adjust_tsc_offset_guest(vcpu, adj);
3531 /* Before back to guest, tsc_timestamp must be adjusted
3532 * as well, otherwise guest's percpu pvclock time could jump.
3534 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3536 vcpu->arch.ia32_tsc_adjust_msr = data;
3539 case MSR_IA32_MISC_ENABLE:
3540 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3541 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3542 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3544 vcpu->arch.ia32_misc_enable_msr = data;
3545 kvm_update_cpuid_runtime(vcpu);
3547 vcpu->arch.ia32_misc_enable_msr = data;
3550 case MSR_IA32_SMBASE:
3551 if (!msr_info->host_initiated)
3553 vcpu->arch.smbase = data;
3555 case MSR_IA32_POWER_CTL:
3556 vcpu->arch.msr_ia32_power_ctl = data;
3559 if (msr_info->host_initiated) {
3560 kvm_synchronize_tsc(vcpu, data);
3562 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3563 adjust_tsc_offset_guest(vcpu, adj);
3564 vcpu->arch.ia32_tsc_adjust_msr += adj;
3568 if (!msr_info->host_initiated &&
3569 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3572 * KVM supports exposing PT to the guest, but does not support
3573 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3574 * XSAVES/XRSTORS to save/restore PT MSRs.
3576 if (data & ~supported_xss)
3578 vcpu->arch.ia32_xss = data;
3579 kvm_update_cpuid_runtime(vcpu);
3582 if (!msr_info->host_initiated)
3584 vcpu->arch.smi_count = data;
3586 case MSR_KVM_WALL_CLOCK_NEW:
3587 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3590 vcpu->kvm->arch.wall_clock = data;
3591 kvm_write_wall_clock(vcpu->kvm, data, 0);
3593 case MSR_KVM_WALL_CLOCK:
3594 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3597 vcpu->kvm->arch.wall_clock = data;
3598 kvm_write_wall_clock(vcpu->kvm, data, 0);
3600 case MSR_KVM_SYSTEM_TIME_NEW:
3601 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3604 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3606 case MSR_KVM_SYSTEM_TIME:
3607 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3610 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3612 case MSR_KVM_ASYNC_PF_EN:
3613 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3616 if (kvm_pv_enable_async_pf(vcpu, data))
3619 case MSR_KVM_ASYNC_PF_INT:
3620 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3623 if (kvm_pv_enable_async_pf_int(vcpu, data))
3626 case MSR_KVM_ASYNC_PF_ACK:
3627 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3630 vcpu->arch.apf.pageready_pending = false;
3631 kvm_check_async_pf_completion(vcpu);
3634 case MSR_KVM_STEAL_TIME:
3635 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3638 if (unlikely(!sched_info_on()))
3641 if (data & KVM_STEAL_RESERVED_MASK)
3644 vcpu->arch.st.msr_val = data;
3646 if (!(data & KVM_MSR_ENABLED))
3649 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3652 case MSR_KVM_PV_EOI_EN:
3653 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3656 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8)))
3660 case MSR_KVM_POLL_CONTROL:
3661 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3664 /* only enable bit supported */
3665 if (data & (-1ULL << 1))
3668 vcpu->arch.msr_kvm_poll_control = data;
3671 case MSR_IA32_MCG_CTL:
3672 case MSR_IA32_MCG_STATUS:
3673 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3674 return set_msr_mce(vcpu, msr_info);
3676 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3677 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3680 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3681 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3682 if (kvm_pmu_is_valid_msr(vcpu, msr))
3683 return kvm_pmu_set_msr(vcpu, msr_info);
3685 if (pr || data != 0)
3686 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3687 "0x%x data 0x%llx\n", msr, data);
3689 case MSR_K7_CLK_CTL:
3691 * Ignore all writes to this no longer documented MSR.
3692 * Writes are only relevant for old K7 processors,
3693 * all pre-dating SVM, but a recommended workaround from
3694 * AMD for these chips. It is possible to specify the
3695 * affected processor models on the command line, hence
3696 * the need to ignore the workaround.
3699 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3700 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3701 case HV_X64_MSR_SYNDBG_OPTIONS:
3702 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3703 case HV_X64_MSR_CRASH_CTL:
3704 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3705 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3706 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3707 case HV_X64_MSR_TSC_EMULATION_STATUS:
3708 return kvm_hv_set_msr_common(vcpu, msr, data,
3709 msr_info->host_initiated);
3710 case MSR_IA32_BBL_CR_CTL3:
3711 /* Drop writes to this legacy MSR -- see rdmsr
3712 * counterpart for further detail.
3714 if (report_ignored_msrs)
3715 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3718 case MSR_AMD64_OSVW_ID_LENGTH:
3719 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3721 vcpu->arch.osvw.length = data;
3723 case MSR_AMD64_OSVW_STATUS:
3724 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3726 vcpu->arch.osvw.status = data;
3728 case MSR_PLATFORM_INFO:
3729 if (!msr_info->host_initiated ||
3730 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3731 cpuid_fault_enabled(vcpu)))
3733 vcpu->arch.msr_platform_info = data;
3735 case MSR_MISC_FEATURES_ENABLES:
3736 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3737 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3738 !supports_cpuid_fault(vcpu)))
3740 vcpu->arch.msr_misc_features_enables = data;
3742 #ifdef CONFIG_X86_64
3744 if (!msr_info->host_initiated &&
3745 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3748 if (data & ~kvm_guest_supported_xfd(vcpu))
3751 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data);
3753 case MSR_IA32_XFD_ERR:
3754 if (!msr_info->host_initiated &&
3755 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3758 if (data & ~kvm_guest_supported_xfd(vcpu))
3761 vcpu->arch.guest_fpu.xfd_err = data;
3765 if (kvm_pmu_is_valid_msr(vcpu, msr))
3766 return kvm_pmu_set_msr(vcpu, msr_info);
3767 return KVM_MSR_RET_INVALID;
3771 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3773 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3776 u64 mcg_cap = vcpu->arch.mcg_cap;
3777 unsigned bank_num = mcg_cap & 0xff;
3780 case MSR_IA32_P5_MC_ADDR:
3781 case MSR_IA32_P5_MC_TYPE:
3784 case MSR_IA32_MCG_CAP:
3785 data = vcpu->arch.mcg_cap;
3787 case MSR_IA32_MCG_CTL:
3788 if (!(mcg_cap & MCG_CTL_P) && !host)
3790 data = vcpu->arch.mcg_ctl;
3792 case MSR_IA32_MCG_STATUS:
3793 data = vcpu->arch.mcg_status;
3796 if (msr >= MSR_IA32_MC0_CTL &&
3797 msr < MSR_IA32_MCx_CTL(bank_num)) {
3798 u32 offset = array_index_nospec(
3799 msr - MSR_IA32_MC0_CTL,
3800 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3802 data = vcpu->arch.mce_banks[offset];
3811 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3813 switch (msr_info->index) {
3814 case MSR_IA32_PLATFORM_ID:
3815 case MSR_IA32_EBL_CR_POWERON:
3816 case MSR_IA32_LASTBRANCHFROMIP:
3817 case MSR_IA32_LASTBRANCHTOIP:
3818 case MSR_IA32_LASTINTFROMIP:
3819 case MSR_IA32_LASTINTTOIP:
3820 case MSR_AMD64_SYSCFG:
3821 case MSR_K8_TSEG_ADDR:
3822 case MSR_K8_TSEG_MASK:
3823 case MSR_VM_HSAVE_PA:
3824 case MSR_K8_INT_PENDING_MSG:
3825 case MSR_AMD64_NB_CFG:
3826 case MSR_FAM10H_MMIO_CONF_BASE:
3827 case MSR_AMD64_BU_CFG2:
3828 case MSR_IA32_PERF_CTL:
3829 case MSR_AMD64_DC_CFG:
3830 case MSR_F15H_EX_CFG:
3832 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3833 * limit) MSRs. Just return 0, as we do not want to expose the host
3834 * data here. Do not conditionalize this on CPUID, as KVM does not do
3835 * so for existing CPU-specific MSRs.
3837 case MSR_RAPL_POWER_UNIT:
3838 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3839 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3840 case MSR_PKG_ENERGY_STATUS: /* Total package */
3841 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3844 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3845 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3846 return kvm_pmu_get_msr(vcpu, msr_info);
3847 if (!msr_info->host_initiated)
3851 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3852 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3853 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3854 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3855 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3856 return kvm_pmu_get_msr(vcpu, msr_info);
3859 case MSR_IA32_UCODE_REV:
3860 msr_info->data = vcpu->arch.microcode_version;
3862 case MSR_IA32_ARCH_CAPABILITIES:
3863 if (!msr_info->host_initiated &&
3864 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3866 msr_info->data = vcpu->arch.arch_capabilities;
3868 case MSR_IA32_PERF_CAPABILITIES:
3869 if (!msr_info->host_initiated &&
3870 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3872 msr_info->data = vcpu->arch.perf_capabilities;
3874 case MSR_IA32_POWER_CTL:
3875 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3877 case MSR_IA32_TSC: {
3879 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
3880 * even when not intercepted. AMD manual doesn't explicitly
3881 * state this but appears to behave the same.
3883 * On userspace reads and writes, however, we unconditionally
3884 * return L1's TSC value to ensure backwards-compatible
3885 * behavior for migration.
3889 if (msr_info->host_initiated) {
3890 offset = vcpu->arch.l1_tsc_offset;
3891 ratio = vcpu->arch.l1_tsc_scaling_ratio;
3893 offset = vcpu->arch.tsc_offset;
3894 ratio = vcpu->arch.tsc_scaling_ratio;
3897 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset;
3901 case 0x200 ... 0x2ff:
3902 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3903 case 0xcd: /* fsb frequency */
3907 * MSR_EBC_FREQUENCY_ID
3908 * Conservative value valid for even the basic CPU models.
3909 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3910 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3911 * and 266MHz for model 3, or 4. Set Core Clock
3912 * Frequency to System Bus Frequency Ratio to 1 (bits
3913 * 31:24) even though these are only valid for CPU
3914 * models > 2, however guests may end up dividing or
3915 * multiplying by zero otherwise.
3917 case MSR_EBC_FREQUENCY_ID:
3918 msr_info->data = 1 << 24;
3920 case MSR_IA32_APICBASE:
3921 msr_info->data = kvm_get_apic_base(vcpu);
3923 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3924 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3925 case MSR_IA32_TSC_DEADLINE:
3926 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3928 case MSR_IA32_TSC_ADJUST:
3929 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3931 case MSR_IA32_MISC_ENABLE:
3932 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3934 case MSR_IA32_SMBASE:
3935 if (!msr_info->host_initiated)
3937 msr_info->data = vcpu->arch.smbase;
3940 msr_info->data = vcpu->arch.smi_count;
3942 case MSR_IA32_PERF_STATUS:
3943 /* TSC increment by tick */
3944 msr_info->data = 1000ULL;
3945 /* CPU multiplier */
3946 msr_info->data |= (((uint64_t)4ULL) << 40);
3949 msr_info->data = vcpu->arch.efer;
3951 case MSR_KVM_WALL_CLOCK:
3952 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3955 msr_info->data = vcpu->kvm->arch.wall_clock;
3957 case MSR_KVM_WALL_CLOCK_NEW:
3958 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3961 msr_info->data = vcpu->kvm->arch.wall_clock;
3963 case MSR_KVM_SYSTEM_TIME:
3964 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3967 msr_info->data = vcpu->arch.time;
3969 case MSR_KVM_SYSTEM_TIME_NEW:
3970 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3973 msr_info->data = vcpu->arch.time;
3975 case MSR_KVM_ASYNC_PF_EN:
3976 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3979 msr_info->data = vcpu->arch.apf.msr_en_val;
3981 case MSR_KVM_ASYNC_PF_INT:
3982 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3985 msr_info->data = vcpu->arch.apf.msr_int_val;
3987 case MSR_KVM_ASYNC_PF_ACK:
3988 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3993 case MSR_KVM_STEAL_TIME:
3994 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3997 msr_info->data = vcpu->arch.st.msr_val;
3999 case MSR_KVM_PV_EOI_EN:
4000 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
4003 msr_info->data = vcpu->arch.pv_eoi.msr_val;
4005 case MSR_KVM_POLL_CONTROL:
4006 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
4009 msr_info->data = vcpu->arch.msr_kvm_poll_control;
4011 case MSR_IA32_P5_MC_ADDR:
4012 case MSR_IA32_P5_MC_TYPE:
4013 case MSR_IA32_MCG_CAP:
4014 case MSR_IA32_MCG_CTL:
4015 case MSR_IA32_MCG_STATUS:
4016 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4017 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
4018 msr_info->host_initiated);
4020 if (!msr_info->host_initiated &&
4021 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
4023 msr_info->data = vcpu->arch.ia32_xss;
4025 case MSR_K7_CLK_CTL:
4027 * Provide expected ramp-up count for K7. All other
4028 * are set to zero, indicating minimum divisors for
4031 * This prevents guest kernels on AMD host with CPU
4032 * type 6, model 8 and higher from exploding due to
4033 * the rdmsr failing.
4035 msr_info->data = 0x20000000;
4037 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4038 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4039 case HV_X64_MSR_SYNDBG_OPTIONS:
4040 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4041 case HV_X64_MSR_CRASH_CTL:
4042 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4043 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4044 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4045 case HV_X64_MSR_TSC_EMULATION_STATUS:
4046 return kvm_hv_get_msr_common(vcpu,
4047 msr_info->index, &msr_info->data,
4048 msr_info->host_initiated);
4049 case MSR_IA32_BBL_CR_CTL3:
4050 /* This legacy MSR exists but isn't fully documented in current
4051 * silicon. It is however accessed by winxp in very narrow
4052 * scenarios where it sets bit #19, itself documented as
4053 * a "reserved" bit. Best effort attempt to source coherent
4054 * read data here should the balance of the register be
4055 * interpreted by the guest:
4057 * L2 cache control register 3: 64GB range, 256KB size,
4058 * enabled, latency 0x1, configured
4060 msr_info->data = 0xbe702111;
4062 case MSR_AMD64_OSVW_ID_LENGTH:
4063 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4065 msr_info->data = vcpu->arch.osvw.length;
4067 case MSR_AMD64_OSVW_STATUS:
4068 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4070 msr_info->data = vcpu->arch.osvw.status;
4072 case MSR_PLATFORM_INFO:
4073 if (!msr_info->host_initiated &&
4074 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
4076 msr_info->data = vcpu->arch.msr_platform_info;
4078 case MSR_MISC_FEATURES_ENABLES:
4079 msr_info->data = vcpu->arch.msr_misc_features_enables;
4082 msr_info->data = vcpu->arch.msr_hwcr;
4084 #ifdef CONFIG_X86_64
4086 if (!msr_info->host_initiated &&
4087 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4090 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd;
4092 case MSR_IA32_XFD_ERR:
4093 if (!msr_info->host_initiated &&
4094 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4097 msr_info->data = vcpu->arch.guest_fpu.xfd_err;
4101 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4102 return kvm_pmu_get_msr(vcpu, msr_info);
4103 return KVM_MSR_RET_INVALID;
4107 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
4110 * Read or write a bunch of msrs. All parameters are kernel addresses.
4112 * @return number of msrs set successfully.
4114 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
4115 struct kvm_msr_entry *entries,
4116 int (*do_msr)(struct kvm_vcpu *vcpu,
4117 unsigned index, u64 *data))
4121 for (i = 0; i < msrs->nmsrs; ++i)
4122 if (do_msr(vcpu, entries[i].index, &entries[i].data))
4129 * Read or write a bunch of msrs. Parameters are user addresses.
4131 * @return number of msrs set successfully.
4133 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
4134 int (*do_msr)(struct kvm_vcpu *vcpu,
4135 unsigned index, u64 *data),
4138 struct kvm_msrs msrs;
4139 struct kvm_msr_entry *entries;
4144 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
4148 if (msrs.nmsrs >= MAX_IO_MSRS)
4151 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
4152 entries = memdup_user(user_msrs->entries, size);
4153 if (IS_ERR(entries)) {
4154 r = PTR_ERR(entries);
4158 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
4163 if (writeback && copy_to_user(user_msrs->entries, entries, size))
4174 static inline bool kvm_can_mwait_in_guest(void)
4176 return boot_cpu_has(X86_FEATURE_MWAIT) &&
4177 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
4178 boot_cpu_has(X86_FEATURE_ARAT);
4181 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
4182 struct kvm_cpuid2 __user *cpuid_arg)
4184 struct kvm_cpuid2 cpuid;
4188 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4191 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4196 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4202 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
4207 case KVM_CAP_IRQCHIP:
4209 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
4210 case KVM_CAP_SET_TSS_ADDR:
4211 case KVM_CAP_EXT_CPUID:
4212 case KVM_CAP_EXT_EMUL_CPUID:
4213 case KVM_CAP_CLOCKSOURCE:
4215 case KVM_CAP_NOP_IO_DELAY:
4216 case KVM_CAP_MP_STATE:
4217 case KVM_CAP_SYNC_MMU:
4218 case KVM_CAP_USER_NMI:
4219 case KVM_CAP_REINJECT_CONTROL:
4220 case KVM_CAP_IRQ_INJECT_STATUS:
4221 case KVM_CAP_IOEVENTFD:
4222 case KVM_CAP_IOEVENTFD_NO_LENGTH:
4224 case KVM_CAP_PIT_STATE2:
4225 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
4226 case KVM_CAP_VCPU_EVENTS:
4227 case KVM_CAP_HYPERV:
4228 case KVM_CAP_HYPERV_VAPIC:
4229 case KVM_CAP_HYPERV_SPIN:
4230 case KVM_CAP_HYPERV_SYNIC:
4231 case KVM_CAP_HYPERV_SYNIC2:
4232 case KVM_CAP_HYPERV_VP_INDEX:
4233 case KVM_CAP_HYPERV_EVENTFD:
4234 case KVM_CAP_HYPERV_TLBFLUSH:
4235 case KVM_CAP_HYPERV_SEND_IPI:
4236 case KVM_CAP_HYPERV_CPUID:
4237 case KVM_CAP_HYPERV_ENFORCE_CPUID:
4238 case KVM_CAP_SYS_HYPERV_CPUID:
4239 case KVM_CAP_PCI_SEGMENT:
4240 case KVM_CAP_DEBUGREGS:
4241 case KVM_CAP_X86_ROBUST_SINGLESTEP:
4243 case KVM_CAP_ASYNC_PF:
4244 case KVM_CAP_ASYNC_PF_INT:
4245 case KVM_CAP_GET_TSC_KHZ:
4246 case KVM_CAP_KVMCLOCK_CTRL:
4247 case KVM_CAP_READONLY_MEM:
4248 case KVM_CAP_HYPERV_TIME:
4249 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
4250 case KVM_CAP_TSC_DEADLINE_TIMER:
4251 case KVM_CAP_DISABLE_QUIRKS:
4252 case KVM_CAP_SET_BOOT_CPU_ID:
4253 case KVM_CAP_SPLIT_IRQCHIP:
4254 case KVM_CAP_IMMEDIATE_EXIT:
4255 case KVM_CAP_PMU_EVENT_FILTER:
4256 case KVM_CAP_GET_MSR_FEATURES:
4257 case KVM_CAP_MSR_PLATFORM_INFO:
4258 case KVM_CAP_EXCEPTION_PAYLOAD:
4259 case KVM_CAP_SET_GUEST_DEBUG:
4260 case KVM_CAP_LAST_CPU:
4261 case KVM_CAP_X86_USER_SPACE_MSR:
4262 case KVM_CAP_X86_MSR_FILTER:
4263 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4264 #ifdef CONFIG_X86_SGX_KVM
4265 case KVM_CAP_SGX_ATTRIBUTE:
4267 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
4268 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
4269 case KVM_CAP_SREGS2:
4270 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
4271 case KVM_CAP_VCPU_ATTRIBUTES:
4272 case KVM_CAP_SYS_ATTRIBUTES:
4274 case KVM_CAP_ENABLE_CAP:
4277 case KVM_CAP_EXIT_HYPERCALL:
4278 r = KVM_EXIT_HYPERCALL_VALID_MASK;
4280 case KVM_CAP_SET_GUEST_DEBUG2:
4281 return KVM_GUESTDBG_VALID_MASK;
4282 #ifdef CONFIG_KVM_XEN
4283 case KVM_CAP_XEN_HVM:
4284 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR |
4285 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL |
4286 KVM_XEN_HVM_CONFIG_SHARED_INFO |
4287 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL;
4288 if (sched_info_on())
4289 r |= KVM_XEN_HVM_CONFIG_RUNSTATE;
4292 case KVM_CAP_SYNC_REGS:
4293 r = KVM_SYNC_X86_VALID_FIELDS;
4295 case KVM_CAP_ADJUST_CLOCK:
4296 r = KVM_CLOCK_VALID_FLAGS;
4298 case KVM_CAP_X86_DISABLE_EXITS:
4299 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
4300 KVM_X86_DISABLE_EXITS_CSTATE;
4301 if(kvm_can_mwait_in_guest())
4302 r |= KVM_X86_DISABLE_EXITS_MWAIT;
4304 case KVM_CAP_X86_SMM:
4305 /* SMBASE is usually relocated above 1M on modern chipsets,
4306 * and SMM handlers might indeed rely on 4G segment limits,
4307 * so do not report SMM to be available if real mode is
4308 * emulated via vm86 mode. Still, do not go to great lengths
4309 * to avoid userspace's usage of the feature, because it is a
4310 * fringe case that is not enabled except via specific settings
4311 * of the module parameters.
4313 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE);
4315 case KVM_CAP_NR_VCPUS:
4316 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
4318 case KVM_CAP_MAX_VCPUS:
4321 case KVM_CAP_MAX_VCPU_ID:
4322 r = KVM_MAX_VCPU_IDS;
4324 case KVM_CAP_PV_MMU: /* obsolete */
4328 r = KVM_MAX_MCE_BANKS;
4331 r = boot_cpu_has(X86_FEATURE_XSAVE);
4333 case KVM_CAP_TSC_CONTROL:
4334 r = kvm_has_tsc_control;
4336 case KVM_CAP_X2APIC_API:
4337 r = KVM_X2APIC_API_VALID_FLAGS;
4339 case KVM_CAP_NESTED_STATE:
4340 r = kvm_x86_ops.nested_ops->get_state ?
4341 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
4343 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4344 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
4346 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4347 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
4349 case KVM_CAP_SMALLER_MAXPHYADDR:
4350 r = (int) allow_smaller_maxphyaddr;
4352 case KVM_CAP_STEAL_TIME:
4353 r = sched_info_on();
4355 case KVM_CAP_X86_BUS_LOCK_EXIT:
4356 if (kvm_has_bus_lock_exit)
4357 r = KVM_BUS_LOCK_DETECTION_OFF |
4358 KVM_BUS_LOCK_DETECTION_EXIT;
4362 case KVM_CAP_XSAVE2: {
4363 u64 guest_perm = xstate_get_guest_group_perm();
4365 r = xstate_required_size(supported_xcr0 & guest_perm, false);
4366 if (r < sizeof(struct kvm_xsave))
4367 r = sizeof(struct kvm_xsave);
4369 case KVM_CAP_PMU_CAPABILITY:
4370 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0;
4373 case KVM_CAP_DISABLE_QUIRKS2:
4374 r = KVM_X86_VALID_QUIRKS;
4382 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr)
4384 void __user *uaddr = (void __user*)(unsigned long)attr->addr;
4386 if ((u64)(unsigned long)uaddr != attr->addr)
4387 return ERR_PTR_USR(-EFAULT);
4391 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr)
4393 u64 __user *uaddr = kvm_get_attr_addr(attr);
4399 return PTR_ERR(uaddr);
4401 switch (attr->attr) {
4402 case KVM_X86_XCOMP_GUEST_SUPP:
4403 if (put_user(supported_xcr0, uaddr))
4412 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr)
4417 switch (attr->attr) {
4418 case KVM_X86_XCOMP_GUEST_SUPP:
4425 long kvm_arch_dev_ioctl(struct file *filp,
4426 unsigned int ioctl, unsigned long arg)
4428 void __user *argp = (void __user *)arg;
4432 case KVM_GET_MSR_INDEX_LIST: {
4433 struct kvm_msr_list __user *user_msr_list = argp;
4434 struct kvm_msr_list msr_list;
4438 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4441 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
4442 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4445 if (n < msr_list.nmsrs)
4448 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
4449 num_msrs_to_save * sizeof(u32)))
4451 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
4453 num_emulated_msrs * sizeof(u32)))
4458 case KVM_GET_SUPPORTED_CPUID:
4459 case KVM_GET_EMULATED_CPUID: {
4460 struct kvm_cpuid2 __user *cpuid_arg = argp;
4461 struct kvm_cpuid2 cpuid;
4464 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4467 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
4473 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4478 case KVM_X86_GET_MCE_CAP_SUPPORTED:
4480 if (copy_to_user(argp, &kvm_mce_cap_supported,
4481 sizeof(kvm_mce_cap_supported)))
4485 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
4486 struct kvm_msr_list __user *user_msr_list = argp;
4487 struct kvm_msr_list msr_list;
4491 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4494 msr_list.nmsrs = num_msr_based_features;
4495 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4498 if (n < msr_list.nmsrs)
4501 if (copy_to_user(user_msr_list->indices, &msr_based_features,
4502 num_msr_based_features * sizeof(u32)))
4508 r = msr_io(NULL, argp, do_get_msr_feature, 1);
4510 case KVM_GET_SUPPORTED_HV_CPUID:
4511 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
4513 case KVM_GET_DEVICE_ATTR: {
4514 struct kvm_device_attr attr;
4516 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4518 r = kvm_x86_dev_get_attr(&attr);
4521 case KVM_HAS_DEVICE_ATTR: {
4522 struct kvm_device_attr attr;
4524 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4526 r = kvm_x86_dev_has_attr(&attr);
4537 static void wbinvd_ipi(void *garbage)
4542 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
4544 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
4547 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
4549 /* Address WBINVD may be executed by guest */
4550 if (need_emulate_wbinvd(vcpu)) {
4551 if (static_call(kvm_x86_has_wbinvd_exit)())
4552 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4553 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
4554 smp_call_function_single(vcpu->cpu,
4555 wbinvd_ipi, NULL, 1);
4558 static_call(kvm_x86_vcpu_load)(vcpu, cpu);
4560 /* Save host pkru register if supported */
4561 vcpu->arch.host_pkru = read_pkru();
4563 /* Apply any externally detected TSC adjustments (due to suspend) */
4564 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
4565 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
4566 vcpu->arch.tsc_offset_adjustment = 0;
4567 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4570 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
4571 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4572 rdtsc() - vcpu->arch.last_host_tsc;
4574 mark_tsc_unstable("KVM discovered backwards TSC");
4576 if (kvm_check_tsc_unstable()) {
4577 u64 offset = kvm_compute_l1_tsc_offset(vcpu,
4578 vcpu->arch.last_guest_tsc);
4579 kvm_vcpu_write_tsc_offset(vcpu, offset);
4580 vcpu->arch.tsc_catchup = 1;
4583 if (kvm_lapic_hv_timer_in_use(vcpu))
4584 kvm_lapic_restart_hv_timer(vcpu);
4587 * On a host with synchronized TSC, there is no need to update
4588 * kvmclock on vcpu->cpu migration
4590 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
4591 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
4592 if (vcpu->cpu != cpu)
4593 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
4597 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4600 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4602 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
4603 struct kvm_steal_time __user *st;
4604 struct kvm_memslots *slots;
4605 static const u8 preempted = KVM_VCPU_PREEMPTED;
4607 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4610 if (vcpu->arch.st.preempted)
4613 /* This happens on process exit */
4614 if (unlikely(current->mm != vcpu->kvm->mm))
4617 slots = kvm_memslots(vcpu->kvm);
4619 if (unlikely(slots->generation != ghc->generation ||
4620 kvm_is_error_hva(ghc->hva) || !ghc->memslot))
4623 st = (struct kvm_steal_time __user *)ghc->hva;
4624 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted));
4626 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted)))
4627 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4629 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
4632 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4636 if (vcpu->preempted && !vcpu->arch.guest_state_protected)
4637 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu);
4640 * Take the srcu lock as memslots will be accessed to check the gfn
4641 * cache generation against the memslots generation.
4643 idx = srcu_read_lock(&vcpu->kvm->srcu);
4644 if (kvm_xen_msr_enabled(vcpu->kvm))
4645 kvm_xen_runstate_set_preempted(vcpu);
4647 kvm_steal_time_set_preempted(vcpu);
4648 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4650 static_call(kvm_x86_vcpu_put)(vcpu);
4651 vcpu->arch.last_host_tsc = rdtsc();
4654 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4655 struct kvm_lapic_state *s)
4657 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
4659 return kvm_apic_get_state(vcpu, s);
4662 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4663 struct kvm_lapic_state *s)
4667 r = kvm_apic_set_state(vcpu, s);
4670 update_cr8_intercept(vcpu);
4675 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4678 * We can accept userspace's request for interrupt injection
4679 * as long as we have a place to store the interrupt number.
4680 * The actual injection will happen when the CPU is able to
4681 * deliver the interrupt.
4683 if (kvm_cpu_has_extint(vcpu))
4686 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
4687 return (!lapic_in_kernel(vcpu) ||
4688 kvm_apic_accept_pic_intr(vcpu));
4691 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4694 * Do not cause an interrupt window exit if an exception
4695 * is pending or an event needs reinjection; userspace
4696 * might want to inject the interrupt manually using KVM_SET_REGS
4697 * or KVM_SET_SREGS. For that to work, we must be at an
4698 * instruction boundary and with no events half-injected.
4700 return (kvm_arch_interrupt_allowed(vcpu) &&
4701 kvm_cpu_accept_dm_intr(vcpu) &&
4702 !kvm_event_needs_reinjection(vcpu) &&
4703 !vcpu->arch.exception.pending);
4706 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4707 struct kvm_interrupt *irq)
4709 if (irq->irq >= KVM_NR_INTERRUPTS)
4712 if (!irqchip_in_kernel(vcpu->kvm)) {
4713 kvm_queue_interrupt(vcpu, irq->irq, false);
4714 kvm_make_request(KVM_REQ_EVENT, vcpu);
4719 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4720 * fail for in-kernel 8259.
4722 if (pic_in_kernel(vcpu->kvm))
4725 if (vcpu->arch.pending_external_vector != -1)
4728 vcpu->arch.pending_external_vector = irq->irq;
4729 kvm_make_request(KVM_REQ_EVENT, vcpu);
4733 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4735 kvm_inject_nmi(vcpu);
4740 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
4742 kvm_make_request(KVM_REQ_SMI, vcpu);
4747 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4748 struct kvm_tpr_access_ctl *tac)
4752 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4756 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4760 unsigned bank_num = mcg_cap & 0xff, bank;
4763 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4765 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
4768 vcpu->arch.mcg_cap = mcg_cap;
4769 /* Init IA32_MCG_CTL to all 1s */
4770 if (mcg_cap & MCG_CTL_P)
4771 vcpu->arch.mcg_ctl = ~(u64)0;
4772 /* Init IA32_MCi_CTL to all 1s */
4773 for (bank = 0; bank < bank_num; bank++)
4774 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4776 static_call(kvm_x86_setup_mce)(vcpu);
4781 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4782 struct kvm_x86_mce *mce)
4784 u64 mcg_cap = vcpu->arch.mcg_cap;
4785 unsigned bank_num = mcg_cap & 0xff;
4786 u64 *banks = vcpu->arch.mce_banks;
4788 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
4791 * if IA32_MCG_CTL is not all 1s, the uncorrected error
4792 * reporting is disabled
4794 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
4795 vcpu->arch.mcg_ctl != ~(u64)0)
4797 banks += 4 * mce->bank;
4799 * if IA32_MCi_CTL is not all 1s, the uncorrected error
4800 * reporting is disabled for the bank
4802 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
4804 if (mce->status & MCI_STATUS_UC) {
4805 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
4806 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
4807 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4810 if (banks[1] & MCI_STATUS_VAL)
4811 mce->status |= MCI_STATUS_OVER;
4812 banks[2] = mce->addr;
4813 banks[3] = mce->misc;
4814 vcpu->arch.mcg_status = mce->mcg_status;
4815 banks[1] = mce->status;
4816 kvm_queue_exception(vcpu, MC_VECTOR);
4817 } else if (!(banks[1] & MCI_STATUS_VAL)
4818 || !(banks[1] & MCI_STATUS_UC)) {
4819 if (banks[1] & MCI_STATUS_VAL)
4820 mce->status |= MCI_STATUS_OVER;
4821 banks[2] = mce->addr;
4822 banks[3] = mce->misc;
4823 banks[1] = mce->status;
4825 banks[1] |= MCI_STATUS_OVER;
4829 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
4830 struct kvm_vcpu_events *events)
4834 if (kvm_check_request(KVM_REQ_SMI, vcpu))
4838 * In guest mode, payload delivery should be deferred,
4839 * so that the L1 hypervisor can intercept #PF before
4840 * CR2 is modified (or intercept #DB before DR6 is
4841 * modified under nVMX). Unless the per-VM capability,
4842 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
4843 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
4844 * opportunistically defer the exception payload, deliver it if the
4845 * capability hasn't been requested before processing a
4846 * KVM_GET_VCPU_EVENTS.
4848 if (!vcpu->kvm->arch.exception_payload_enabled &&
4849 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
4850 kvm_deliver_exception_payload(vcpu);
4853 * The API doesn't provide the instruction length for software
4854 * exceptions, so don't report them. As long as the guest RIP
4855 * isn't advanced, we should expect to encounter the exception
4858 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
4859 events->exception.injected = 0;
4860 events->exception.pending = 0;
4862 events->exception.injected = vcpu->arch.exception.injected;
4863 events->exception.pending = vcpu->arch.exception.pending;
4865 * For ABI compatibility, deliberately conflate
4866 * pending and injected exceptions when
4867 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
4869 if (!vcpu->kvm->arch.exception_payload_enabled)
4870 events->exception.injected |=
4871 vcpu->arch.exception.pending;
4873 events->exception.nr = vcpu->arch.exception.nr;
4874 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
4875 events->exception.error_code = vcpu->arch.exception.error_code;
4876 events->exception_has_payload = vcpu->arch.exception.has_payload;
4877 events->exception_payload = vcpu->arch.exception.payload;
4879 events->interrupt.injected =
4880 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
4881 events->interrupt.nr = vcpu->arch.interrupt.nr;
4882 events->interrupt.soft = 0;
4883 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
4885 events->nmi.injected = vcpu->arch.nmi_injected;
4886 events->nmi.pending = vcpu->arch.nmi_pending != 0;
4887 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu);
4888 events->nmi.pad = 0;
4890 events->sipi_vector = 0; /* never valid when reporting to user space */
4892 events->smi.smm = is_smm(vcpu);
4893 events->smi.pending = vcpu->arch.smi_pending;
4894 events->smi.smm_inside_nmi =
4895 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
4896 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
4898 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
4899 | KVM_VCPUEVENT_VALID_SHADOW
4900 | KVM_VCPUEVENT_VALID_SMM);
4901 if (vcpu->kvm->arch.exception_payload_enabled)
4902 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4904 memset(&events->reserved, 0, sizeof(events->reserved));
4907 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm);
4909 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4910 struct kvm_vcpu_events *events)
4912 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4913 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4914 | KVM_VCPUEVENT_VALID_SHADOW
4915 | KVM_VCPUEVENT_VALID_SMM
4916 | KVM_VCPUEVENT_VALID_PAYLOAD))
4919 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4920 if (!vcpu->kvm->arch.exception_payload_enabled)
4922 if (events->exception.pending)
4923 events->exception.injected = 0;
4925 events->exception_has_payload = 0;
4927 events->exception.pending = 0;
4928 events->exception_has_payload = 0;
4931 if ((events->exception.injected || events->exception.pending) &&
4932 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4935 /* INITs are latched while in SMM */
4936 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4937 (events->smi.smm || events->smi.pending) &&
4938 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4942 vcpu->arch.exception.injected = events->exception.injected;
4943 vcpu->arch.exception.pending = events->exception.pending;
4944 vcpu->arch.exception.nr = events->exception.nr;
4945 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4946 vcpu->arch.exception.error_code = events->exception.error_code;
4947 vcpu->arch.exception.has_payload = events->exception_has_payload;
4948 vcpu->arch.exception.payload = events->exception_payload;
4950 vcpu->arch.interrupt.injected = events->interrupt.injected;
4951 vcpu->arch.interrupt.nr = events->interrupt.nr;
4952 vcpu->arch.interrupt.soft = events->interrupt.soft;
4953 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4954 static_call(kvm_x86_set_interrupt_shadow)(vcpu,
4955 events->interrupt.shadow);
4957 vcpu->arch.nmi_injected = events->nmi.injected;
4958 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4959 vcpu->arch.nmi_pending = events->nmi.pending;
4960 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked);
4962 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4963 lapic_in_kernel(vcpu))
4964 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4966 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4967 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4968 kvm_x86_ops.nested_ops->leave_nested(vcpu);
4969 kvm_smm_changed(vcpu, events->smi.smm);
4972 vcpu->arch.smi_pending = events->smi.pending;
4974 if (events->smi.smm) {
4975 if (events->smi.smm_inside_nmi)
4976 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4978 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4981 if (lapic_in_kernel(vcpu)) {
4982 if (events->smi.latched_init)
4983 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4985 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4989 kvm_make_request(KVM_REQ_EVENT, vcpu);
4994 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4995 struct kvm_debugregs *dbgregs)
4999 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
5000 kvm_get_dr(vcpu, 6, &val);
5002 dbgregs->dr7 = vcpu->arch.dr7;
5004 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
5007 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
5008 struct kvm_debugregs *dbgregs)
5013 if (!kvm_dr6_valid(dbgregs->dr6))
5015 if (!kvm_dr7_valid(dbgregs->dr7))
5018 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
5019 kvm_update_dr0123(vcpu);
5020 vcpu->arch.dr6 = dbgregs->dr6;
5021 vcpu->arch.dr7 = dbgregs->dr7;
5022 kvm_update_dr7(vcpu);
5027 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
5028 struct kvm_xsave *guest_xsave)
5030 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5033 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5034 guest_xsave->region,
5035 sizeof(guest_xsave->region),
5039 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu,
5040 u8 *state, unsigned int size)
5042 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5045 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5046 state, size, vcpu->arch.pkru);
5049 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
5050 struct kvm_xsave *guest_xsave)
5052 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5055 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu,
5056 guest_xsave->region,
5057 supported_xcr0, &vcpu->arch.pkru);
5060 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
5061 struct kvm_xcrs *guest_xcrs)
5063 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
5064 guest_xcrs->nr_xcrs = 0;
5068 guest_xcrs->nr_xcrs = 1;
5069 guest_xcrs->flags = 0;
5070 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
5071 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
5074 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
5075 struct kvm_xcrs *guest_xcrs)
5079 if (!boot_cpu_has(X86_FEATURE_XSAVE))
5082 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
5085 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
5086 /* Only support XCR0 currently */
5087 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
5088 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
5089 guest_xcrs->xcrs[i].value);
5098 * kvm_set_guest_paused() indicates to the guest kernel that it has been
5099 * stopped by the hypervisor. This function will be called from the host only.
5100 * EINVAL is returned when the host attempts to set the flag for a guest that
5101 * does not support pv clocks.
5103 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
5105 if (!vcpu->arch.pv_time_enabled)
5107 vcpu->arch.pvclock_set_guest_stopped_request = true;
5108 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5112 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu,
5113 struct kvm_device_attr *attr)
5117 switch (attr->attr) {
5118 case KVM_VCPU_TSC_OFFSET:
5128 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu,
5129 struct kvm_device_attr *attr)
5131 u64 __user *uaddr = kvm_get_attr_addr(attr);
5135 return PTR_ERR(uaddr);
5137 switch (attr->attr) {
5138 case KVM_VCPU_TSC_OFFSET:
5140 if (put_user(vcpu->arch.l1_tsc_offset, uaddr))
5151 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu,
5152 struct kvm_device_attr *attr)
5154 u64 __user *uaddr = kvm_get_attr_addr(attr);
5155 struct kvm *kvm = vcpu->kvm;
5159 return PTR_ERR(uaddr);
5161 switch (attr->attr) {
5162 case KVM_VCPU_TSC_OFFSET: {
5163 u64 offset, tsc, ns;
5164 unsigned long flags;
5168 if (get_user(offset, uaddr))
5171 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
5173 matched = (vcpu->arch.virtual_tsc_khz &&
5174 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz &&
5175 kvm->arch.last_tsc_offset == offset);
5177 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset;
5178 ns = get_kvmclock_base_ns();
5180 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched);
5181 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
5193 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu,
5197 struct kvm_device_attr attr;
5200 if (copy_from_user(&attr, argp, sizeof(attr)))
5203 if (attr.group != KVM_VCPU_TSC_CTRL)
5207 case KVM_HAS_DEVICE_ATTR:
5208 r = kvm_arch_tsc_has_attr(vcpu, &attr);
5210 case KVM_GET_DEVICE_ATTR:
5211 r = kvm_arch_tsc_get_attr(vcpu, &attr);
5213 case KVM_SET_DEVICE_ATTR:
5214 r = kvm_arch_tsc_set_attr(vcpu, &attr);
5221 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
5222 struct kvm_enable_cap *cap)
5225 uint16_t vmcs_version;
5226 void __user *user_ptr;
5232 case KVM_CAP_HYPERV_SYNIC2:
5237 case KVM_CAP_HYPERV_SYNIC:
5238 if (!irqchip_in_kernel(vcpu->kvm))
5240 return kvm_hv_activate_synic(vcpu, cap->cap ==
5241 KVM_CAP_HYPERV_SYNIC2);
5242 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5243 if (!kvm_x86_ops.nested_ops->enable_evmcs)
5245 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
5247 user_ptr = (void __user *)(uintptr_t)cap->args[0];
5248 if (copy_to_user(user_ptr, &vmcs_version,
5249 sizeof(vmcs_version)))
5253 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5254 if (!kvm_x86_ops.enable_direct_tlbflush)
5257 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu);
5259 case KVM_CAP_HYPERV_ENFORCE_CPUID:
5260 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]);
5262 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
5263 vcpu->arch.pv_cpuid.enforce = cap->args[0];
5264 if (vcpu->arch.pv_cpuid.enforce)
5265 kvm_update_pv_runtime(vcpu);
5273 long kvm_arch_vcpu_ioctl(struct file *filp,
5274 unsigned int ioctl, unsigned long arg)
5276 struct kvm_vcpu *vcpu = filp->private_data;
5277 void __user *argp = (void __user *)arg;
5280 struct kvm_sregs2 *sregs2;
5281 struct kvm_lapic_state *lapic;
5282 struct kvm_xsave *xsave;
5283 struct kvm_xcrs *xcrs;
5291 case KVM_GET_LAPIC: {
5293 if (!lapic_in_kernel(vcpu))
5295 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
5296 GFP_KERNEL_ACCOUNT);
5301 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
5305 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
5310 case KVM_SET_LAPIC: {
5312 if (!lapic_in_kernel(vcpu))
5314 u.lapic = memdup_user(argp, sizeof(*u.lapic));
5315 if (IS_ERR(u.lapic)) {
5316 r = PTR_ERR(u.lapic);
5320 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
5323 case KVM_INTERRUPT: {
5324 struct kvm_interrupt irq;
5327 if (copy_from_user(&irq, argp, sizeof(irq)))
5329 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
5333 r = kvm_vcpu_ioctl_nmi(vcpu);
5337 r = kvm_vcpu_ioctl_smi(vcpu);
5340 case KVM_SET_CPUID: {
5341 struct kvm_cpuid __user *cpuid_arg = argp;
5342 struct kvm_cpuid cpuid;
5345 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5347 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
5350 case KVM_SET_CPUID2: {
5351 struct kvm_cpuid2 __user *cpuid_arg = argp;
5352 struct kvm_cpuid2 cpuid;
5355 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5357 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
5358 cpuid_arg->entries);
5361 case KVM_GET_CPUID2: {
5362 struct kvm_cpuid2 __user *cpuid_arg = argp;
5363 struct kvm_cpuid2 cpuid;
5366 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5368 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
5369 cpuid_arg->entries);
5373 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
5378 case KVM_GET_MSRS: {
5379 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5380 r = msr_io(vcpu, argp, do_get_msr, 1);
5381 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5384 case KVM_SET_MSRS: {
5385 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5386 r = msr_io(vcpu, argp, do_set_msr, 0);
5387 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5390 case KVM_TPR_ACCESS_REPORTING: {
5391 struct kvm_tpr_access_ctl tac;
5394 if (copy_from_user(&tac, argp, sizeof(tac)))
5396 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
5400 if (copy_to_user(argp, &tac, sizeof(tac)))
5405 case KVM_SET_VAPIC_ADDR: {
5406 struct kvm_vapic_addr va;
5410 if (!lapic_in_kernel(vcpu))
5413 if (copy_from_user(&va, argp, sizeof(va)))
5415 idx = srcu_read_lock(&vcpu->kvm->srcu);
5416 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
5417 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5420 case KVM_X86_SETUP_MCE: {
5424 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
5426 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
5429 case KVM_X86_SET_MCE: {
5430 struct kvm_x86_mce mce;
5433 if (copy_from_user(&mce, argp, sizeof(mce)))
5435 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
5438 case KVM_GET_VCPU_EVENTS: {
5439 struct kvm_vcpu_events events;
5441 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
5444 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
5449 case KVM_SET_VCPU_EVENTS: {
5450 struct kvm_vcpu_events events;
5453 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
5456 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
5459 case KVM_GET_DEBUGREGS: {
5460 struct kvm_debugregs dbgregs;
5462 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
5465 if (copy_to_user(argp, &dbgregs,
5466 sizeof(struct kvm_debugregs)))
5471 case KVM_SET_DEBUGREGS: {
5472 struct kvm_debugregs dbgregs;
5475 if (copy_from_user(&dbgregs, argp,
5476 sizeof(struct kvm_debugregs)))
5479 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
5482 case KVM_GET_XSAVE: {
5484 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave))
5487 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
5492 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
5495 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
5500 case KVM_SET_XSAVE: {
5501 int size = vcpu->arch.guest_fpu.uabi_size;
5503 u.xsave = memdup_user(argp, size);
5504 if (IS_ERR(u.xsave)) {
5505 r = PTR_ERR(u.xsave);
5509 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
5513 case KVM_GET_XSAVE2: {
5514 int size = vcpu->arch.guest_fpu.uabi_size;
5516 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT);
5521 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size);
5524 if (copy_to_user(argp, u.xsave, size))
5531 case KVM_GET_XCRS: {
5532 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
5537 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
5540 if (copy_to_user(argp, u.xcrs,
5541 sizeof(struct kvm_xcrs)))
5546 case KVM_SET_XCRS: {
5547 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
5548 if (IS_ERR(u.xcrs)) {
5549 r = PTR_ERR(u.xcrs);
5553 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
5556 case KVM_SET_TSC_KHZ: {
5560 user_tsc_khz = (u32)arg;
5562 if (kvm_has_tsc_control &&
5563 user_tsc_khz >= kvm_max_guest_tsc_khz)
5566 if (user_tsc_khz == 0)
5567 user_tsc_khz = tsc_khz;
5569 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
5574 case KVM_GET_TSC_KHZ: {
5575 r = vcpu->arch.virtual_tsc_khz;
5578 case KVM_KVMCLOCK_CTRL: {
5579 r = kvm_set_guest_paused(vcpu);
5582 case KVM_ENABLE_CAP: {
5583 struct kvm_enable_cap cap;
5586 if (copy_from_user(&cap, argp, sizeof(cap)))
5588 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
5591 case KVM_GET_NESTED_STATE: {
5592 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5596 if (!kvm_x86_ops.nested_ops->get_state)
5599 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
5601 if (get_user(user_data_size, &user_kvm_nested_state->size))
5604 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
5609 if (r > user_data_size) {
5610 if (put_user(r, &user_kvm_nested_state->size))
5620 case KVM_SET_NESTED_STATE: {
5621 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5622 struct kvm_nested_state kvm_state;
5626 if (!kvm_x86_ops.nested_ops->set_state)
5630 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
5634 if (kvm_state.size < sizeof(kvm_state))
5637 if (kvm_state.flags &
5638 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
5639 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
5640 | KVM_STATE_NESTED_GIF_SET))
5643 /* nested_run_pending implies guest_mode. */
5644 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
5645 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
5648 idx = srcu_read_lock(&vcpu->kvm->srcu);
5649 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
5650 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5653 case KVM_GET_SUPPORTED_HV_CPUID:
5654 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5656 #ifdef CONFIG_KVM_XEN
5657 case KVM_XEN_VCPU_GET_ATTR: {
5658 struct kvm_xen_vcpu_attr xva;
5661 if (copy_from_user(&xva, argp, sizeof(xva)))
5663 r = kvm_xen_vcpu_get_attr(vcpu, &xva);
5664 if (!r && copy_to_user(argp, &xva, sizeof(xva)))
5668 case KVM_XEN_VCPU_SET_ATTR: {
5669 struct kvm_xen_vcpu_attr xva;
5672 if (copy_from_user(&xva, argp, sizeof(xva)))
5674 r = kvm_xen_vcpu_set_attr(vcpu, &xva);
5678 case KVM_GET_SREGS2: {
5679 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL);
5683 __get_sregs2(vcpu, u.sregs2);
5685 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2)))
5690 case KVM_SET_SREGS2: {
5691 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2));
5692 if (IS_ERR(u.sregs2)) {
5693 r = PTR_ERR(u.sregs2);
5697 r = __set_sregs2(vcpu, u.sregs2);
5700 case KVM_HAS_DEVICE_ATTR:
5701 case KVM_GET_DEVICE_ATTR:
5702 case KVM_SET_DEVICE_ATTR:
5703 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp);
5715 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5717 return VM_FAULT_SIGBUS;
5720 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
5724 if (addr > (unsigned int)(-3 * PAGE_SIZE))
5726 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr);
5730 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
5733 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr);
5736 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
5737 unsigned long kvm_nr_mmu_pages)
5739 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
5742 mutex_lock(&kvm->slots_lock);
5744 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
5745 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
5747 mutex_unlock(&kvm->slots_lock);
5751 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
5753 return kvm->arch.n_max_mmu_pages;
5756 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5758 struct kvm_pic *pic = kvm->arch.vpic;
5762 switch (chip->chip_id) {
5763 case KVM_IRQCHIP_PIC_MASTER:
5764 memcpy(&chip->chip.pic, &pic->pics[0],
5765 sizeof(struct kvm_pic_state));
5767 case KVM_IRQCHIP_PIC_SLAVE:
5768 memcpy(&chip->chip.pic, &pic->pics[1],
5769 sizeof(struct kvm_pic_state));
5771 case KVM_IRQCHIP_IOAPIC:
5772 kvm_get_ioapic(kvm, &chip->chip.ioapic);
5781 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5783 struct kvm_pic *pic = kvm->arch.vpic;
5787 switch (chip->chip_id) {
5788 case KVM_IRQCHIP_PIC_MASTER:
5789 spin_lock(&pic->lock);
5790 memcpy(&pic->pics[0], &chip->chip.pic,
5791 sizeof(struct kvm_pic_state));
5792 spin_unlock(&pic->lock);
5794 case KVM_IRQCHIP_PIC_SLAVE:
5795 spin_lock(&pic->lock);
5796 memcpy(&pic->pics[1], &chip->chip.pic,
5797 sizeof(struct kvm_pic_state));
5798 spin_unlock(&pic->lock);
5800 case KVM_IRQCHIP_IOAPIC:
5801 kvm_set_ioapic(kvm, &chip->chip.ioapic);
5807 kvm_pic_update_irq(pic);
5811 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5813 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
5815 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
5817 mutex_lock(&kps->lock);
5818 memcpy(ps, &kps->channels, sizeof(*ps));
5819 mutex_unlock(&kps->lock);
5823 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5826 struct kvm_pit *pit = kvm->arch.vpit;
5828 mutex_lock(&pit->pit_state.lock);
5829 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
5830 for (i = 0; i < 3; i++)
5831 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
5832 mutex_unlock(&pit->pit_state.lock);
5836 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5838 mutex_lock(&kvm->arch.vpit->pit_state.lock);
5839 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
5840 sizeof(ps->channels));
5841 ps->flags = kvm->arch.vpit->pit_state.flags;
5842 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
5843 memset(&ps->reserved, 0, sizeof(ps->reserved));
5847 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5851 u32 prev_legacy, cur_legacy;
5852 struct kvm_pit *pit = kvm->arch.vpit;
5854 mutex_lock(&pit->pit_state.lock);
5855 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
5856 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
5857 if (!prev_legacy && cur_legacy)
5859 memcpy(&pit->pit_state.channels, &ps->channels,
5860 sizeof(pit->pit_state.channels));
5861 pit->pit_state.flags = ps->flags;
5862 for (i = 0; i < 3; i++)
5863 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
5865 mutex_unlock(&pit->pit_state.lock);
5869 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
5870 struct kvm_reinject_control *control)
5872 struct kvm_pit *pit = kvm->arch.vpit;
5874 /* pit->pit_state.lock was overloaded to prevent userspace from getting
5875 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
5876 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
5878 mutex_lock(&pit->pit_state.lock);
5879 kvm_pit_set_reinject(pit, control->pit_reinject);
5880 mutex_unlock(&pit->pit_state.lock);
5885 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
5889 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called
5890 * before reporting dirty_bitmap to userspace. KVM flushes the buffers
5891 * on all VM-Exits, thus we only need to kick running vCPUs to force a
5894 struct kvm_vcpu *vcpu;
5897 kvm_for_each_vcpu(i, vcpu, kvm)
5898 kvm_vcpu_kick(vcpu);
5901 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
5904 if (!irqchip_in_kernel(kvm))
5907 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
5908 irq_event->irq, irq_event->level,
5913 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
5914 struct kvm_enable_cap *cap)
5922 case KVM_CAP_DISABLE_QUIRKS2:
5924 if (cap->args[0] & ~KVM_X86_VALID_QUIRKS)
5927 case KVM_CAP_DISABLE_QUIRKS:
5928 kvm->arch.disabled_quirks = cap->args[0];
5931 case KVM_CAP_SPLIT_IRQCHIP: {
5932 mutex_lock(&kvm->lock);
5934 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
5935 goto split_irqchip_unlock;
5937 if (irqchip_in_kernel(kvm))
5938 goto split_irqchip_unlock;
5939 if (kvm->created_vcpus)
5940 goto split_irqchip_unlock;
5941 r = kvm_setup_empty_irq_routing(kvm);
5943 goto split_irqchip_unlock;
5944 /* Pairs with irqchip_in_kernel. */
5946 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
5947 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
5948 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
5950 split_irqchip_unlock:
5951 mutex_unlock(&kvm->lock);
5954 case KVM_CAP_X2APIC_API:
5956 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
5959 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
5960 kvm->arch.x2apic_format = true;
5961 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
5962 kvm->arch.x2apic_broadcast_quirk_disabled = true;
5966 case KVM_CAP_X86_DISABLE_EXITS:
5968 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
5971 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
5972 kvm_can_mwait_in_guest())
5973 kvm->arch.mwait_in_guest = true;
5974 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
5975 kvm->arch.hlt_in_guest = true;
5976 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
5977 kvm->arch.pause_in_guest = true;
5978 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
5979 kvm->arch.cstate_in_guest = true;
5982 case KVM_CAP_MSR_PLATFORM_INFO:
5983 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
5986 case KVM_CAP_EXCEPTION_PAYLOAD:
5987 kvm->arch.exception_payload_enabled = cap->args[0];
5990 case KVM_CAP_X86_USER_SPACE_MSR:
5991 kvm->arch.user_space_msr_mask = cap->args[0];
5994 case KVM_CAP_X86_BUS_LOCK_EXIT:
5996 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE)
5999 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) &&
6000 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
6003 if (kvm_has_bus_lock_exit &&
6004 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
6005 kvm->arch.bus_lock_detection_enabled = true;
6008 #ifdef CONFIG_X86_SGX_KVM
6009 case KVM_CAP_SGX_ATTRIBUTE: {
6010 unsigned long allowed_attributes = 0;
6012 r = sgx_set_attribute(&allowed_attributes, cap->args[0]);
6016 /* KVM only supports the PROVISIONKEY privileged attribute. */
6017 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) &&
6018 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY))
6019 kvm->arch.sgx_provisioning_allowed = true;
6025 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
6027 if (!kvm_x86_ops.vm_copy_enc_context_from)
6030 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]);
6032 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
6034 if (!kvm_x86_ops.vm_move_enc_context_from)
6037 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]);
6039 case KVM_CAP_EXIT_HYPERCALL:
6040 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) {
6044 kvm->arch.hypercall_exit_enabled = cap->args[0];
6047 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
6049 if (cap->args[0] & ~1)
6051 kvm->arch.exit_on_emulation_error = cap->args[0];
6054 case KVM_CAP_PMU_CAPABILITY:
6056 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK))
6059 mutex_lock(&kvm->lock);
6060 if (!kvm->created_vcpus) {
6061 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE);
6064 mutex_unlock(&kvm->lock);
6073 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow)
6075 struct kvm_x86_msr_filter *msr_filter;
6077 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT);
6081 msr_filter->default_allow = default_allow;
6085 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter)
6092 for (i = 0; i < msr_filter->count; i++)
6093 kfree(msr_filter->ranges[i].bitmap);
6098 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter,
6099 struct kvm_msr_filter_range *user_range)
6101 unsigned long *bitmap = NULL;
6104 if (!user_range->nmsrs)
6107 if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE))
6110 if (!user_range->flags)
6113 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
6114 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
6117 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
6119 return PTR_ERR(bitmap);
6121 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) {
6122 .flags = user_range->flags,
6123 .base = user_range->base,
6124 .nmsrs = user_range->nmsrs,
6128 msr_filter->count++;
6132 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp)
6134 struct kvm_msr_filter __user *user_msr_filter = argp;
6135 struct kvm_x86_msr_filter *new_filter, *old_filter;
6136 struct kvm_msr_filter filter;
6142 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
6145 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++)
6146 empty &= !filter.ranges[i].nmsrs;
6148 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY);
6149 if (empty && !default_allow)
6152 new_filter = kvm_alloc_msr_filter(default_allow);
6156 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
6157 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]);
6159 kvm_free_msr_filter(new_filter);
6164 mutex_lock(&kvm->lock);
6166 /* The per-VM filter is protected by kvm->lock... */
6167 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1);
6169 rcu_assign_pointer(kvm->arch.msr_filter, new_filter);
6170 synchronize_srcu(&kvm->srcu);
6172 kvm_free_msr_filter(old_filter);
6174 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
6175 mutex_unlock(&kvm->lock);
6180 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER
6181 static int kvm_arch_suspend_notifier(struct kvm *kvm)
6183 struct kvm_vcpu *vcpu;
6187 mutex_lock(&kvm->lock);
6188 kvm_for_each_vcpu(i, vcpu, kvm) {
6189 if (!vcpu->arch.pv_time_enabled)
6192 ret = kvm_set_guest_paused(vcpu);
6194 kvm_err("Failed to pause guest VCPU%d: %d\n",
6195 vcpu->vcpu_id, ret);
6199 mutex_unlock(&kvm->lock);
6201 return ret ? NOTIFY_BAD : NOTIFY_DONE;
6204 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state)
6207 case PM_HIBERNATION_PREPARE:
6208 case PM_SUSPEND_PREPARE:
6209 return kvm_arch_suspend_notifier(kvm);
6214 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */
6216 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp)
6218 struct kvm_clock_data data = { 0 };
6220 get_kvmclock(kvm, &data);
6221 if (copy_to_user(argp, &data, sizeof(data)))
6227 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp)
6229 struct kvm_arch *ka = &kvm->arch;
6230 struct kvm_clock_data data;
6233 if (copy_from_user(&data, argp, sizeof(data)))
6237 * Only KVM_CLOCK_REALTIME is used, but allow passing the
6238 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK.
6240 if (data.flags & ~KVM_CLOCK_VALID_FLAGS)
6243 kvm_hv_request_tsc_page_update(kvm);
6244 kvm_start_pvclock_update(kvm);
6245 pvclock_update_vm_gtod_copy(kvm);
6248 * This pairs with kvm_guest_time_update(): when masterclock is
6249 * in use, we use master_kernel_ns + kvmclock_offset to set
6250 * unsigned 'system_time' so if we use get_kvmclock_ns() (which
6251 * is slightly ahead) here we risk going negative on unsigned
6252 * 'system_time' when 'data.clock' is very small.
6254 if (data.flags & KVM_CLOCK_REALTIME) {
6255 u64 now_real_ns = ktime_get_real_ns();
6258 * Avoid stepping the kvmclock backwards.
6260 if (now_real_ns > data.realtime)
6261 data.clock += now_real_ns - data.realtime;
6264 if (ka->use_master_clock)
6265 now_raw_ns = ka->master_kernel_ns;
6267 now_raw_ns = get_kvmclock_base_ns();
6268 ka->kvmclock_offset = data.clock - now_raw_ns;
6269 kvm_end_pvclock_update(kvm);
6273 long kvm_arch_vm_ioctl(struct file *filp,
6274 unsigned int ioctl, unsigned long arg)
6276 struct kvm *kvm = filp->private_data;
6277 void __user *argp = (void __user *)arg;
6280 * This union makes it completely explicit to gcc-3.x
6281 * that these two variables' stack usage should be
6282 * combined, not added together.
6285 struct kvm_pit_state ps;
6286 struct kvm_pit_state2 ps2;
6287 struct kvm_pit_config pit_config;
6291 case KVM_SET_TSS_ADDR:
6292 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
6294 case KVM_SET_IDENTITY_MAP_ADDR: {
6297 mutex_lock(&kvm->lock);
6299 if (kvm->created_vcpus)
6300 goto set_identity_unlock;
6302 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
6303 goto set_identity_unlock;
6304 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
6305 set_identity_unlock:
6306 mutex_unlock(&kvm->lock);
6309 case KVM_SET_NR_MMU_PAGES:
6310 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
6312 case KVM_GET_NR_MMU_PAGES:
6313 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
6315 case KVM_CREATE_IRQCHIP: {
6316 mutex_lock(&kvm->lock);
6319 if (irqchip_in_kernel(kvm))
6320 goto create_irqchip_unlock;
6323 if (kvm->created_vcpus)
6324 goto create_irqchip_unlock;
6326 r = kvm_pic_init(kvm);
6328 goto create_irqchip_unlock;
6330 r = kvm_ioapic_init(kvm);
6332 kvm_pic_destroy(kvm);
6333 goto create_irqchip_unlock;
6336 r = kvm_setup_default_irq_routing(kvm);
6338 kvm_ioapic_destroy(kvm);
6339 kvm_pic_destroy(kvm);
6340 goto create_irqchip_unlock;
6342 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
6344 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
6345 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6346 create_irqchip_unlock:
6347 mutex_unlock(&kvm->lock);
6350 case KVM_CREATE_PIT:
6351 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
6353 case KVM_CREATE_PIT2:
6355 if (copy_from_user(&u.pit_config, argp,
6356 sizeof(struct kvm_pit_config)))
6359 mutex_lock(&kvm->lock);
6362 goto create_pit_unlock;
6364 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
6368 mutex_unlock(&kvm->lock);
6370 case KVM_GET_IRQCHIP: {
6371 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6372 struct kvm_irqchip *chip;
6374 chip = memdup_user(argp, sizeof(*chip));
6381 if (!irqchip_kernel(kvm))
6382 goto get_irqchip_out;
6383 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
6385 goto get_irqchip_out;
6387 if (copy_to_user(argp, chip, sizeof(*chip)))
6388 goto get_irqchip_out;
6394 case KVM_SET_IRQCHIP: {
6395 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6396 struct kvm_irqchip *chip;
6398 chip = memdup_user(argp, sizeof(*chip));
6405 if (!irqchip_kernel(kvm))
6406 goto set_irqchip_out;
6407 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
6414 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
6417 if (!kvm->arch.vpit)
6419 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
6423 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
6430 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
6432 mutex_lock(&kvm->lock);
6434 if (!kvm->arch.vpit)
6436 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
6438 mutex_unlock(&kvm->lock);
6441 case KVM_GET_PIT2: {
6443 if (!kvm->arch.vpit)
6445 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
6449 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
6454 case KVM_SET_PIT2: {
6456 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
6458 mutex_lock(&kvm->lock);
6460 if (!kvm->arch.vpit)
6462 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
6464 mutex_unlock(&kvm->lock);
6467 case KVM_REINJECT_CONTROL: {
6468 struct kvm_reinject_control control;
6470 if (copy_from_user(&control, argp, sizeof(control)))
6473 if (!kvm->arch.vpit)
6475 r = kvm_vm_ioctl_reinject(kvm, &control);
6478 case KVM_SET_BOOT_CPU_ID:
6480 mutex_lock(&kvm->lock);
6481 if (kvm->created_vcpus)
6484 kvm->arch.bsp_vcpu_id = arg;
6485 mutex_unlock(&kvm->lock);
6487 #ifdef CONFIG_KVM_XEN
6488 case KVM_XEN_HVM_CONFIG: {
6489 struct kvm_xen_hvm_config xhc;
6491 if (copy_from_user(&xhc, argp, sizeof(xhc)))
6493 r = kvm_xen_hvm_config(kvm, &xhc);
6496 case KVM_XEN_HVM_GET_ATTR: {
6497 struct kvm_xen_hvm_attr xha;
6500 if (copy_from_user(&xha, argp, sizeof(xha)))
6502 r = kvm_xen_hvm_get_attr(kvm, &xha);
6503 if (!r && copy_to_user(argp, &xha, sizeof(xha)))
6507 case KVM_XEN_HVM_SET_ATTR: {
6508 struct kvm_xen_hvm_attr xha;
6511 if (copy_from_user(&xha, argp, sizeof(xha)))
6513 r = kvm_xen_hvm_set_attr(kvm, &xha);
6518 r = kvm_vm_ioctl_set_clock(kvm, argp);
6521 r = kvm_vm_ioctl_get_clock(kvm, argp);
6523 case KVM_MEMORY_ENCRYPT_OP: {
6525 if (!kvm_x86_ops.mem_enc_ioctl)
6528 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp);
6531 case KVM_MEMORY_ENCRYPT_REG_REGION: {
6532 struct kvm_enc_region region;
6535 if (copy_from_user(®ion, argp, sizeof(region)))
6539 if (!kvm_x86_ops.mem_enc_register_region)
6542 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion);
6545 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
6546 struct kvm_enc_region region;
6549 if (copy_from_user(®ion, argp, sizeof(region)))
6553 if (!kvm_x86_ops.mem_enc_unregister_region)
6556 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion);
6559 case KVM_HYPERV_EVENTFD: {
6560 struct kvm_hyperv_eventfd hvevfd;
6563 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
6565 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
6568 case KVM_SET_PMU_EVENT_FILTER:
6569 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
6571 case KVM_X86_SET_MSR_FILTER:
6572 r = kvm_vm_ioctl_set_msr_filter(kvm, argp);
6581 static void kvm_init_msr_list(void)
6583 struct x86_pmu_capability x86_pmu;
6587 BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
6588 "Please update the fixed PMCs in msrs_to_saved_all[]");
6590 perf_get_x86_pmu_capability(&x86_pmu);
6592 num_msrs_to_save = 0;
6593 num_emulated_msrs = 0;
6594 num_msr_based_features = 0;
6596 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
6597 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
6601 * Even MSRs that are valid in the host may not be exposed
6602 * to the guests in some cases.
6604 switch (msrs_to_save_all[i]) {
6605 case MSR_IA32_BNDCFGS:
6606 if (!kvm_mpx_supported())
6610 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) &&
6611 !kvm_cpu_cap_has(X86_FEATURE_RDPID))
6614 case MSR_IA32_UMWAIT_CONTROL:
6615 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
6618 case MSR_IA32_RTIT_CTL:
6619 case MSR_IA32_RTIT_STATUS:
6620 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
6623 case MSR_IA32_RTIT_CR3_MATCH:
6624 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
6625 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
6628 case MSR_IA32_RTIT_OUTPUT_BASE:
6629 case MSR_IA32_RTIT_OUTPUT_MASK:
6630 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
6631 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
6632 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
6635 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
6636 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
6637 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
6638 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
6641 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
6642 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
6643 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
6646 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
6647 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
6648 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
6652 case MSR_IA32_XFD_ERR:
6653 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
6660 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
6663 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
6664 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i]))
6667 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
6670 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
6671 struct kvm_msr_entry msr;
6673 msr.index = msr_based_features_all[i];
6674 if (kvm_get_msr_feature(&msr))
6677 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
6681 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
6689 if (!(lapic_in_kernel(vcpu) &&
6690 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
6691 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
6702 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
6709 if (!(lapic_in_kernel(vcpu) &&
6710 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
6712 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
6714 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
6724 static void kvm_set_segment(struct kvm_vcpu *vcpu,
6725 struct kvm_segment *var, int seg)
6727 static_call(kvm_x86_set_segment)(vcpu, var, seg);
6730 void kvm_get_segment(struct kvm_vcpu *vcpu,
6731 struct kvm_segment *var, int seg)
6733 static_call(kvm_x86_get_segment)(vcpu, var, seg);
6736 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
6737 struct x86_exception *exception)
6739 struct kvm_mmu *mmu = vcpu->arch.mmu;
6742 BUG_ON(!mmu_is_nested(vcpu));
6744 /* NPT walks are always user-walks */
6745 access |= PFERR_USER_MASK;
6746 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception);
6751 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
6752 struct x86_exception *exception)
6754 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6756 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6757 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
6759 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read);
6761 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
6762 struct x86_exception *exception)
6764 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6766 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6767 access |= PFERR_FETCH_MASK;
6768 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
6771 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
6772 struct x86_exception *exception)
6774 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6776 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6777 access |= PFERR_WRITE_MASK;
6778 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
6780 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write);
6782 /* uses this to access any guest's mapped memory without checking CPL */
6783 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
6784 struct x86_exception *exception)
6786 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6788 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception);
6791 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
6792 struct kvm_vcpu *vcpu, u64 access,
6793 struct x86_exception *exception)
6795 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6797 int r = X86EMUL_CONTINUE;
6800 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
6801 unsigned offset = addr & (PAGE_SIZE-1);
6802 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
6805 if (gpa == UNMAPPED_GVA)
6806 return X86EMUL_PROPAGATE_FAULT;
6807 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
6810 r = X86EMUL_IO_NEEDED;
6822 /* used for instruction fetching */
6823 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
6824 gva_t addr, void *val, unsigned int bytes,
6825 struct x86_exception *exception)
6827 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6828 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6829 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6833 /* Inline kvm_read_guest_virt_helper for speed. */
6834 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK,
6836 if (unlikely(gpa == UNMAPPED_GVA))
6837 return X86EMUL_PROPAGATE_FAULT;
6839 offset = addr & (PAGE_SIZE-1);
6840 if (WARN_ON(offset + bytes > PAGE_SIZE))
6841 bytes = (unsigned)PAGE_SIZE - offset;
6842 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
6844 if (unlikely(ret < 0))
6845 return X86EMUL_IO_NEEDED;
6847 return X86EMUL_CONTINUE;
6850 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
6851 gva_t addr, void *val, unsigned int bytes,
6852 struct x86_exception *exception)
6854 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6857 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
6858 * is returned, but our callers are not ready for that and they blindly
6859 * call kvm_inject_page_fault. Ensure that they at least do not leak
6860 * uninitialized kernel stack memory into cr2 and error code.
6862 memset(exception, 0, sizeof(*exception));
6863 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
6866 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
6868 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
6869 gva_t addr, void *val, unsigned int bytes,
6870 struct x86_exception *exception, bool system)
6872 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6876 access |= PFERR_IMPLICIT_ACCESS;
6877 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
6878 access |= PFERR_USER_MASK;
6880 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
6883 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
6884 unsigned long addr, void *val, unsigned int bytes)
6886 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6887 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
6889 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
6892 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
6893 struct kvm_vcpu *vcpu, u64 access,
6894 struct x86_exception *exception)
6896 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6898 int r = X86EMUL_CONTINUE;
6901 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
6902 unsigned offset = addr & (PAGE_SIZE-1);
6903 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
6906 if (gpa == UNMAPPED_GVA)
6907 return X86EMUL_PROPAGATE_FAULT;
6908 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
6910 r = X86EMUL_IO_NEEDED;
6922 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
6923 unsigned int bytes, struct x86_exception *exception,
6926 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6927 u64 access = PFERR_WRITE_MASK;
6930 access |= PFERR_IMPLICIT_ACCESS;
6931 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
6932 access |= PFERR_USER_MASK;
6934 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6938 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
6939 unsigned int bytes, struct x86_exception *exception)
6941 /* kvm_write_guest_virt_system can pull in tons of pages. */
6942 vcpu->arch.l1tf_flush_l1d = true;
6944 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6945 PFERR_WRITE_MASK, exception);
6947 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
6949 static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type,
6950 void *insn, int insn_len)
6952 return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type,
6956 int handle_ud(struct kvm_vcpu *vcpu)
6958 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
6959 int emul_type = EMULTYPE_TRAP_UD;
6960 char sig[5]; /* ud2; .ascii "kvm" */
6961 struct x86_exception e;
6963 if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0)))
6966 if (force_emulation_prefix &&
6967 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
6968 sig, sizeof(sig), &e) == 0 &&
6969 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
6970 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
6971 emul_type = EMULTYPE_TRAP_UD_FORCED;
6974 return kvm_emulate_instruction(vcpu, emul_type);
6976 EXPORT_SYMBOL_GPL(handle_ud);
6978 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6979 gpa_t gpa, bool write)
6981 /* For APIC access vmexit */
6982 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6985 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
6986 trace_vcpu_match_mmio(gva, gpa, write, true);
6993 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6994 gpa_t *gpa, struct x86_exception *exception,
6997 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6998 u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0)
6999 | (write ? PFERR_WRITE_MASK : 0);
7002 * currently PKRU is only applied to ept enabled guest so
7003 * there is no pkey in EPT page table for L1 guest or EPT
7004 * shadow page table for L2 guest.
7006 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) ||
7007 !permission_fault(vcpu, vcpu->arch.walk_mmu,
7008 vcpu->arch.mmio_access, 0, access))) {
7009 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
7010 (gva & (PAGE_SIZE - 1));
7011 trace_vcpu_match_mmio(gva, *gpa, write, false);
7015 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7017 if (*gpa == UNMAPPED_GVA)
7020 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
7023 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
7024 const void *val, int bytes)
7028 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
7031 kvm_page_track_write(vcpu, gpa, val, bytes);
7035 struct read_write_emulator_ops {
7036 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
7038 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
7039 void *val, int bytes);
7040 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7041 int bytes, void *val);
7042 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7043 void *val, int bytes);
7047 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
7049 if (vcpu->mmio_read_completed) {
7050 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
7051 vcpu->mmio_fragments[0].gpa, val);
7052 vcpu->mmio_read_completed = 0;
7059 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7060 void *val, int bytes)
7062 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
7065 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7066 void *val, int bytes)
7068 return emulator_write_phys(vcpu, gpa, val, bytes);
7071 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
7073 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
7074 return vcpu_mmio_write(vcpu, gpa, bytes, val);
7077 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7078 void *val, int bytes)
7080 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
7081 return X86EMUL_IO_NEEDED;
7084 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7085 void *val, int bytes)
7087 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
7089 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
7090 return X86EMUL_CONTINUE;
7093 static const struct read_write_emulator_ops read_emultor = {
7094 .read_write_prepare = read_prepare,
7095 .read_write_emulate = read_emulate,
7096 .read_write_mmio = vcpu_mmio_read,
7097 .read_write_exit_mmio = read_exit_mmio,
7100 static const struct read_write_emulator_ops write_emultor = {
7101 .read_write_emulate = write_emulate,
7102 .read_write_mmio = write_mmio,
7103 .read_write_exit_mmio = write_exit_mmio,
7107 static int emulator_read_write_onepage(unsigned long addr, void *val,
7109 struct x86_exception *exception,
7110 struct kvm_vcpu *vcpu,
7111 const struct read_write_emulator_ops *ops)
7115 bool write = ops->write;
7116 struct kvm_mmio_fragment *frag;
7117 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7120 * If the exit was due to a NPF we may already have a GPA.
7121 * If the GPA is present, use it to avoid the GVA to GPA table walk.
7122 * Note, this cannot be used on string operations since string
7123 * operation using rep will only have the initial GPA from the NPF
7126 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
7127 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
7128 gpa = ctxt->gpa_val;
7129 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
7131 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
7133 return X86EMUL_PROPAGATE_FAULT;
7136 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
7137 return X86EMUL_CONTINUE;
7140 * Is this MMIO handled locally?
7142 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
7143 if (handled == bytes)
7144 return X86EMUL_CONTINUE;
7150 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
7151 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
7155 return X86EMUL_CONTINUE;
7158 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
7160 void *val, unsigned int bytes,
7161 struct x86_exception *exception,
7162 const struct read_write_emulator_ops *ops)
7164 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7168 if (ops->read_write_prepare &&
7169 ops->read_write_prepare(vcpu, val, bytes))
7170 return X86EMUL_CONTINUE;
7172 vcpu->mmio_nr_fragments = 0;
7174 /* Crossing a page boundary? */
7175 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
7178 now = -addr & ~PAGE_MASK;
7179 rc = emulator_read_write_onepage(addr, val, now, exception,
7182 if (rc != X86EMUL_CONTINUE)
7185 if (ctxt->mode != X86EMUL_MODE_PROT64)
7191 rc = emulator_read_write_onepage(addr, val, bytes, exception,
7193 if (rc != X86EMUL_CONTINUE)
7196 if (!vcpu->mmio_nr_fragments)
7199 gpa = vcpu->mmio_fragments[0].gpa;
7201 vcpu->mmio_needed = 1;
7202 vcpu->mmio_cur_fragment = 0;
7204 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
7205 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
7206 vcpu->run->exit_reason = KVM_EXIT_MMIO;
7207 vcpu->run->mmio.phys_addr = gpa;
7209 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
7212 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
7216 struct x86_exception *exception)
7218 return emulator_read_write(ctxt, addr, val, bytes,
7219 exception, &read_emultor);
7222 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
7226 struct x86_exception *exception)
7228 return emulator_read_write(ctxt, addr, (void *)val, bytes,
7229 exception, &write_emultor);
7232 #define CMPXCHG_TYPE(t, ptr, old, new) \
7233 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
7235 #ifdef CONFIG_X86_64
7236 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
7238 # define CMPXCHG64(ptr, old, new) \
7239 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
7242 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
7247 struct x86_exception *exception)
7249 struct kvm_host_map map;
7250 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7256 /* guests cmpxchg8b have to be emulated atomically */
7257 if (bytes > 8 || (bytes & (bytes - 1)))
7260 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
7262 if (gpa == UNMAPPED_GVA ||
7263 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7267 * Emulate the atomic as a straight write to avoid #AC if SLD is
7268 * enabled in the host and the access splits a cache line.
7270 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
7271 page_line_mask = ~(cache_line_size() - 1);
7273 page_line_mask = PAGE_MASK;
7275 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
7278 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
7281 kaddr = map.hva + offset_in_page(gpa);
7285 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
7288 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
7291 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
7294 exchanged = CMPXCHG64(kaddr, old, new);
7300 kvm_vcpu_unmap(vcpu, &map, true);
7303 return X86EMUL_CMPXCHG_FAILED;
7305 kvm_page_track_write(vcpu, gpa, new, bytes);
7307 return X86EMUL_CONTINUE;
7310 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
7312 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
7315 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
7319 for (i = 0; i < vcpu->arch.pio.count; i++) {
7320 if (vcpu->arch.pio.in)
7321 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
7322 vcpu->arch.pio.size, pd);
7324 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
7325 vcpu->arch.pio.port, vcpu->arch.pio.size,
7329 pd += vcpu->arch.pio.size;
7334 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
7335 unsigned short port,
7336 unsigned int count, bool in)
7338 vcpu->arch.pio.port = port;
7339 vcpu->arch.pio.in = in;
7340 vcpu->arch.pio.count = count;
7341 vcpu->arch.pio.size = size;
7343 if (!kernel_pio(vcpu, vcpu->arch.pio_data))
7346 vcpu->run->exit_reason = KVM_EXIT_IO;
7347 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
7348 vcpu->run->io.size = size;
7349 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
7350 vcpu->run->io.count = count;
7351 vcpu->run->io.port = port;
7356 static int __emulator_pio_in(struct kvm_vcpu *vcpu, int size,
7357 unsigned short port, unsigned int count)
7359 WARN_ON(vcpu->arch.pio.count);
7360 memset(vcpu->arch.pio_data, 0, size * count);
7361 return emulator_pio_in_out(vcpu, size, port, count, true);
7364 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val)
7366 int size = vcpu->arch.pio.size;
7367 unsigned count = vcpu->arch.pio.count;
7368 memcpy(val, vcpu->arch.pio_data, size * count);
7369 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data);
7370 vcpu->arch.pio.count = 0;
7373 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
7374 unsigned short port, void *val, unsigned int count)
7376 if (vcpu->arch.pio.count) {
7378 * Complete a previous iteration that required userspace I/O.
7379 * Note, @count isn't guaranteed to match pio.count as userspace
7380 * can modify ECX before rerunning the vCPU. Ignore any such
7381 * shenanigans as KVM doesn't support modifying the rep count,
7382 * and the emulator ensures @count doesn't overflow the buffer.
7385 int r = __emulator_pio_in(vcpu, size, port, count);
7389 /* Results already available, fall through. */
7392 complete_emulator_pio_in(vcpu, val);
7396 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
7397 int size, unsigned short port, void *val,
7400 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
7404 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
7405 unsigned short port, const void *val,
7410 memcpy(vcpu->arch.pio_data, val, size * count);
7411 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
7412 ret = emulator_pio_in_out(vcpu, size, port, count, false);
7414 vcpu->arch.pio.count = 0;
7419 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
7420 int size, unsigned short port,
7421 const void *val, unsigned int count)
7423 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
7426 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
7428 return static_call(kvm_x86_get_segment_base)(vcpu, seg);
7431 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
7433 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
7436 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
7438 if (!need_emulate_wbinvd(vcpu))
7439 return X86EMUL_CONTINUE;
7441 if (static_call(kvm_x86_has_wbinvd_exit)()) {
7442 int cpu = get_cpu();
7444 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
7445 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask,
7446 wbinvd_ipi, NULL, 1);
7448 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
7451 return X86EMUL_CONTINUE;
7454 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
7456 kvm_emulate_wbinvd_noskip(vcpu);
7457 return kvm_skip_emulated_instruction(vcpu);
7459 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
7463 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
7465 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
7468 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
7469 unsigned long *dest)
7471 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
7474 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
7475 unsigned long value)
7478 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
7481 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
7483 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
7486 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
7488 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7489 unsigned long value;
7493 value = kvm_read_cr0(vcpu);
7496 value = vcpu->arch.cr2;
7499 value = kvm_read_cr3(vcpu);
7502 value = kvm_read_cr4(vcpu);
7505 value = kvm_get_cr8(vcpu);
7508 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7515 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
7517 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7522 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
7525 vcpu->arch.cr2 = val;
7528 res = kvm_set_cr3(vcpu, val);
7531 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
7534 res = kvm_set_cr8(vcpu, val);
7537 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7544 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
7546 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt));
7549 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7551 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt);
7554 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7556 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt);
7559 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7561 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt);
7564 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7566 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt);
7569 static unsigned long emulator_get_cached_segment_base(
7570 struct x86_emulate_ctxt *ctxt, int seg)
7572 return get_segment_base(emul_to_vcpu(ctxt), seg);
7575 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
7576 struct desc_struct *desc, u32 *base3,
7579 struct kvm_segment var;
7581 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
7582 *selector = var.selector;
7585 memset(desc, 0, sizeof(*desc));
7593 set_desc_limit(desc, var.limit);
7594 set_desc_base(desc, (unsigned long)var.base);
7595 #ifdef CONFIG_X86_64
7597 *base3 = var.base >> 32;
7599 desc->type = var.type;
7601 desc->dpl = var.dpl;
7602 desc->p = var.present;
7603 desc->avl = var.avl;
7611 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
7612 struct desc_struct *desc, u32 base3,
7615 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7616 struct kvm_segment var;
7618 var.selector = selector;
7619 var.base = get_desc_base(desc);
7620 #ifdef CONFIG_X86_64
7621 var.base |= ((u64)base3) << 32;
7623 var.limit = get_desc_limit(desc);
7625 var.limit = (var.limit << 12) | 0xfff;
7626 var.type = desc->type;
7627 var.dpl = desc->dpl;
7632 var.avl = desc->avl;
7633 var.present = desc->p;
7634 var.unusable = !var.present;
7637 kvm_set_segment(vcpu, &var, seg);
7641 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt,
7642 u32 msr_index, u64 *pdata)
7644 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7647 r = kvm_get_msr_with_filter(vcpu, msr_index, pdata);
7649 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0,
7650 complete_emulated_rdmsr, r)) {
7651 /* Bounce to user space */
7652 return X86EMUL_IO_NEEDED;
7658 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt,
7659 u32 msr_index, u64 data)
7661 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7664 r = kvm_set_msr_with_filter(vcpu, msr_index, data);
7666 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data,
7667 complete_emulated_msr_access, r)) {
7668 /* Bounce to user space */
7669 return X86EMUL_IO_NEEDED;
7675 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
7676 u32 msr_index, u64 *pdata)
7678 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
7681 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
7682 u32 msr_index, u64 data)
7684 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
7687 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
7689 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7691 return vcpu->arch.smbase;
7694 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
7696 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7698 vcpu->arch.smbase = smbase;
7701 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
7704 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc))
7709 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
7710 u32 pmc, u64 *pdata)
7712 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
7715 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
7717 emul_to_vcpu(ctxt)->arch.halt_request = 1;
7720 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
7721 struct x86_instruction_info *info,
7722 enum x86_intercept_stage stage)
7724 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage,
7728 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
7729 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
7732 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
7735 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
7737 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
7740 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
7742 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
7745 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
7747 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
7750 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt)
7752 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID);
7755 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
7757 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg);
7760 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
7762 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val);
7765 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
7767 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked);
7770 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
7772 return emul_to_vcpu(ctxt)->arch.hflags;
7775 static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt)
7777 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7779 kvm_smm_changed(vcpu, false);
7782 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt,
7783 const char *smstate)
7785 return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate);
7788 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt)
7790 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt));
7793 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
7795 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
7798 static const struct x86_emulate_ops emulate_ops = {
7799 .read_gpr = emulator_read_gpr,
7800 .write_gpr = emulator_write_gpr,
7801 .read_std = emulator_read_std,
7802 .write_std = emulator_write_std,
7803 .read_phys = kvm_read_guest_phys_system,
7804 .fetch = kvm_fetch_guest_virt,
7805 .read_emulated = emulator_read_emulated,
7806 .write_emulated = emulator_write_emulated,
7807 .cmpxchg_emulated = emulator_cmpxchg_emulated,
7808 .invlpg = emulator_invlpg,
7809 .pio_in_emulated = emulator_pio_in_emulated,
7810 .pio_out_emulated = emulator_pio_out_emulated,
7811 .get_segment = emulator_get_segment,
7812 .set_segment = emulator_set_segment,
7813 .get_cached_segment_base = emulator_get_cached_segment_base,
7814 .get_gdt = emulator_get_gdt,
7815 .get_idt = emulator_get_idt,
7816 .set_gdt = emulator_set_gdt,
7817 .set_idt = emulator_set_idt,
7818 .get_cr = emulator_get_cr,
7819 .set_cr = emulator_set_cr,
7820 .cpl = emulator_get_cpl,
7821 .get_dr = emulator_get_dr,
7822 .set_dr = emulator_set_dr,
7823 .get_smbase = emulator_get_smbase,
7824 .set_smbase = emulator_set_smbase,
7825 .set_msr_with_filter = emulator_set_msr_with_filter,
7826 .get_msr_with_filter = emulator_get_msr_with_filter,
7827 .set_msr = emulator_set_msr,
7828 .get_msr = emulator_get_msr,
7829 .check_pmc = emulator_check_pmc,
7830 .read_pmc = emulator_read_pmc,
7831 .halt = emulator_halt,
7832 .wbinvd = emulator_wbinvd,
7833 .fix_hypercall = emulator_fix_hypercall,
7834 .intercept = emulator_intercept,
7835 .get_cpuid = emulator_get_cpuid,
7836 .guest_has_long_mode = emulator_guest_has_long_mode,
7837 .guest_has_movbe = emulator_guest_has_movbe,
7838 .guest_has_fxsr = emulator_guest_has_fxsr,
7839 .guest_has_rdpid = emulator_guest_has_rdpid,
7840 .set_nmi_mask = emulator_set_nmi_mask,
7841 .get_hflags = emulator_get_hflags,
7842 .exiting_smm = emulator_exiting_smm,
7843 .leave_smm = emulator_leave_smm,
7844 .triple_fault = emulator_triple_fault,
7845 .set_xcr = emulator_set_xcr,
7848 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
7850 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
7852 * an sti; sti; sequence only disable interrupts for the first
7853 * instruction. So, if the last instruction, be it emulated or
7854 * not, left the system with the INT_STI flag enabled, it
7855 * means that the last instruction is an sti. We should not
7856 * leave the flag on in this case. The same goes for mov ss
7858 if (int_shadow & mask)
7860 if (unlikely(int_shadow || mask)) {
7861 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask);
7863 kvm_make_request(KVM_REQ_EVENT, vcpu);
7867 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
7869 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7870 if (ctxt->exception.vector == PF_VECTOR)
7871 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
7873 if (ctxt->exception.error_code_valid)
7874 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
7875 ctxt->exception.error_code);
7877 kvm_queue_exception(vcpu, ctxt->exception.vector);
7881 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
7883 struct x86_emulate_ctxt *ctxt;
7885 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
7887 pr_err("kvm: failed to allocate vcpu's emulator\n");
7892 ctxt->ops = &emulate_ops;
7893 vcpu->arch.emulate_ctxt = ctxt;
7898 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
7900 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7903 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
7905 ctxt->gpa_available = false;
7906 ctxt->eflags = kvm_get_rflags(vcpu);
7907 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
7909 ctxt->eip = kvm_rip_read(vcpu);
7910 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
7911 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
7912 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
7913 cs_db ? X86EMUL_MODE_PROT32 :
7914 X86EMUL_MODE_PROT16;
7915 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
7916 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
7917 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
7919 ctxt->interruptibility = 0;
7920 ctxt->have_exception = false;
7921 ctxt->exception.vector = -1;
7922 ctxt->perm_ok = false;
7924 init_decode_cache(ctxt);
7925 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7928 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
7930 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7933 init_emulate_ctxt(vcpu);
7937 ctxt->_eip = ctxt->eip + inc_eip;
7938 ret = emulate_int_real(ctxt, irq);
7940 if (ret != X86EMUL_CONTINUE) {
7941 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7943 ctxt->eip = ctxt->_eip;
7944 kvm_rip_write(vcpu, ctxt->eip);
7945 kvm_set_rflags(vcpu, ctxt->eflags);
7948 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
7950 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
7951 u8 ndata, u8 *insn_bytes, u8 insn_size)
7953 struct kvm_run *run = vcpu->run;
7958 * Zero the whole array used to retrieve the exit info, as casting to
7959 * u32 for select entries will leave some chunks uninitialized.
7961 memset(&info, 0, sizeof(info));
7963 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1],
7964 &info[2], (u32 *)&info[3],
7967 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7968 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION;
7971 * There's currently space for 13 entries, but 5 are used for the exit
7972 * reason and info. Restrict to 4 to reduce the maintenance burden
7973 * when expanding kvm_run.emulation_failure in the future.
7975 if (WARN_ON_ONCE(ndata > 4))
7978 /* Always include the flags as a 'data' entry. */
7980 run->emulation_failure.flags = 0;
7983 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) +
7984 sizeof(run->emulation_failure.insn_bytes) != 16));
7986 run->emulation_failure.flags |=
7987 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES;
7988 run->emulation_failure.insn_size = insn_size;
7989 memset(run->emulation_failure.insn_bytes, 0x90,
7990 sizeof(run->emulation_failure.insn_bytes));
7991 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size);
7994 memcpy(&run->internal.data[info_start], info, sizeof(info));
7995 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data,
7996 ndata * sizeof(data[0]));
7998 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata;
8001 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu)
8003 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8005 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data,
8006 ctxt->fetch.end - ctxt->fetch.data);
8009 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8012 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0);
8014 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit);
8016 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu)
8018 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0);
8020 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit);
8022 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
8024 struct kvm *kvm = vcpu->kvm;
8026 ++vcpu->stat.insn_emulation_fail;
8027 trace_kvm_emulate_insn_failed(vcpu);
8029 if (emulation_type & EMULTYPE_VMWARE_GP) {
8030 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8034 if (kvm->arch.exit_on_emulation_error ||
8035 (emulation_type & EMULTYPE_SKIP)) {
8036 prepare_emulation_ctxt_failure_exit(vcpu);
8040 kvm_queue_exception(vcpu, UD_VECTOR);
8042 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) {
8043 prepare_emulation_ctxt_failure_exit(vcpu);
8050 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8051 bool write_fault_to_shadow_pgtable,
8054 gpa_t gpa = cr2_or_gpa;
8057 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8060 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8061 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8064 if (!vcpu->arch.mmu->direct_map) {
8066 * Write permission should be allowed since only
8067 * write access need to be emulated.
8069 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8072 * If the mapping is invalid in guest, let cpu retry
8073 * it to generate fault.
8075 if (gpa == UNMAPPED_GVA)
8080 * Do not retry the unhandleable instruction if it faults on the
8081 * readonly host memory, otherwise it will goto a infinite loop:
8082 * retry instruction -> write #PF -> emulation fail -> retry
8083 * instruction -> ...
8085 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
8088 * If the instruction failed on the error pfn, it can not be fixed,
8089 * report the error to userspace.
8091 if (is_error_noslot_pfn(pfn))
8094 kvm_release_pfn_clean(pfn);
8096 /* The instructions are well-emulated on direct mmu. */
8097 if (vcpu->arch.mmu->direct_map) {
8098 unsigned int indirect_shadow_pages;
8100 write_lock(&vcpu->kvm->mmu_lock);
8101 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
8102 write_unlock(&vcpu->kvm->mmu_lock);
8104 if (indirect_shadow_pages)
8105 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8111 * if emulation was due to access to shadowed page table
8112 * and it failed try to unshadow page and re-enter the
8113 * guest to let CPU execute the instruction.
8115 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8118 * If the access faults on its page table, it can not
8119 * be fixed by unprotecting shadow page and it should
8120 * be reported to userspace.
8122 return !write_fault_to_shadow_pgtable;
8125 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
8126 gpa_t cr2_or_gpa, int emulation_type)
8128 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8129 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
8131 last_retry_eip = vcpu->arch.last_retry_eip;
8132 last_retry_addr = vcpu->arch.last_retry_addr;
8135 * If the emulation is caused by #PF and it is non-page_table
8136 * writing instruction, it means the VM-EXIT is caused by shadow
8137 * page protected, we can zap the shadow page and retry this
8138 * instruction directly.
8140 * Note: if the guest uses a non-page-table modifying instruction
8141 * on the PDE that points to the instruction, then we will unmap
8142 * the instruction and go to an infinite loop. So, we cache the
8143 * last retried eip and the last fault address, if we meet the eip
8144 * and the address again, we can break out of the potential infinite
8147 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
8149 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8152 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8153 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8156 if (x86_page_table_writing_insn(ctxt))
8159 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
8162 vcpu->arch.last_retry_eip = ctxt->eip;
8163 vcpu->arch.last_retry_addr = cr2_or_gpa;
8165 if (!vcpu->arch.mmu->direct_map)
8166 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8168 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8173 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
8174 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
8176 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm)
8178 trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm);
8181 vcpu->arch.hflags |= HF_SMM_MASK;
8183 vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK);
8185 /* Process a latched INIT or SMI, if any. */
8186 kvm_make_request(KVM_REQ_EVENT, vcpu);
8189 * Even if KVM_SET_SREGS2 loaded PDPTRs out of band,
8190 * on SMM exit we still need to reload them from
8193 vcpu->arch.pdptrs_from_userspace = false;
8196 kvm_mmu_reset_context(vcpu);
8199 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
8208 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
8209 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
8214 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
8216 struct kvm_run *kvm_run = vcpu->run;
8218 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
8219 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW;
8220 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
8221 kvm_run->debug.arch.exception = DB_VECTOR;
8222 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8225 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
8229 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
8231 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8234 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu);
8238 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8241 * rflags is the old, "raw" value of the flags. The new value has
8242 * not been saved yet.
8244 * This is correct even for TF set by the guest, because "the
8245 * processor will not generate this exception after the instruction
8246 * that sets the TF flag".
8248 if (unlikely(rflags & X86_EFLAGS_TF))
8249 r = kvm_vcpu_do_singlestep(vcpu);
8252 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
8254 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
8256 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
8257 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
8258 struct kvm_run *kvm_run = vcpu->run;
8259 unsigned long eip = kvm_get_linear_rip(vcpu);
8260 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8261 vcpu->arch.guest_debug_dr7,
8265 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
8266 kvm_run->debug.arch.pc = eip;
8267 kvm_run->debug.arch.exception = DB_VECTOR;
8268 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8274 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
8275 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
8276 unsigned long eip = kvm_get_linear_rip(vcpu);
8277 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8282 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
8291 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
8293 switch (ctxt->opcode_len) {
8300 case 0xe6: /* OUT */
8304 case 0x6c: /* INS */
8306 case 0x6e: /* OUTS */
8313 case 0x33: /* RDPMC */
8323 * Decode to be emulated instruction. Return EMULATION_OK if success.
8325 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
8326 void *insn, int insn_len)
8328 int r = EMULATION_OK;
8329 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8331 init_emulate_ctxt(vcpu);
8334 * We will reenter on the same instruction since we do not set
8335 * complete_userspace_io. This does not handle watchpoints yet,
8336 * those would be handled in the emulate_ops.
8338 if (!(emulation_type & EMULTYPE_SKIP) &&
8339 kvm_vcpu_check_breakpoint(vcpu, &r))
8342 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type);
8344 trace_kvm_emulate_insn_start(vcpu);
8345 ++vcpu->stat.insn_emulation;
8349 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction);
8351 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8352 int emulation_type, void *insn, int insn_len)
8355 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8356 bool writeback = true;
8357 bool write_fault_to_spt;
8359 if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len)))
8362 vcpu->arch.l1tf_flush_l1d = true;
8365 * Clear write_fault_to_shadow_pgtable here to ensure it is
8368 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
8369 vcpu->arch.write_fault_to_shadow_pgtable = false;
8371 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8372 kvm_clear_exception_queue(vcpu);
8374 r = x86_decode_emulated_instruction(vcpu, emulation_type,
8376 if (r != EMULATION_OK) {
8377 if ((emulation_type & EMULTYPE_TRAP_UD) ||
8378 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
8379 kvm_queue_exception(vcpu, UD_VECTOR);
8382 if (reexecute_instruction(vcpu, cr2_or_gpa,
8386 if (ctxt->have_exception) {
8388 * #UD should result in just EMULATION_FAILED, and trap-like
8389 * exception should not be encountered during decode.
8391 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
8392 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8393 inject_emulated_exception(vcpu);
8396 return handle_emulation_failure(vcpu, emulation_type);
8400 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
8401 !is_vmware_backdoor_opcode(ctxt)) {
8402 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8407 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for
8408 * use *only* by vendor callbacks for kvm_skip_emulated_instruction().
8409 * The caller is responsible for updating interruptibility state and
8410 * injecting single-step #DBs.
8412 if (emulation_type & EMULTYPE_SKIP) {
8413 if (ctxt->mode != X86EMUL_MODE_PROT64)
8414 ctxt->eip = (u32)ctxt->_eip;
8416 ctxt->eip = ctxt->_eip;
8418 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) {
8423 kvm_rip_write(vcpu, ctxt->eip);
8424 if (ctxt->eflags & X86_EFLAGS_RF)
8425 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
8429 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
8432 /* this is needed for vmware backdoor interface to work since it
8433 changes registers values during IO operation */
8434 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
8435 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8436 emulator_invalidate_register_cache(ctxt);
8440 if (emulation_type & EMULTYPE_PF) {
8441 /* Save the faulting GPA (cr2) in the address field */
8442 ctxt->exception.address = cr2_or_gpa;
8444 /* With shadow page tables, cr2 contains a GVA or nGPA. */
8445 if (vcpu->arch.mmu->direct_map) {
8446 ctxt->gpa_available = true;
8447 ctxt->gpa_val = cr2_or_gpa;
8450 /* Sanitize the address out of an abundance of paranoia. */
8451 ctxt->exception.address = 0;
8454 r = x86_emulate_insn(ctxt);
8456 if (r == EMULATION_INTERCEPTED)
8459 if (r == EMULATION_FAILED) {
8460 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
8464 return handle_emulation_failure(vcpu, emulation_type);
8467 if (ctxt->have_exception) {
8469 if (inject_emulated_exception(vcpu))
8471 } else if (vcpu->arch.pio.count) {
8472 if (!vcpu->arch.pio.in) {
8473 /* FIXME: return into emulator if single-stepping. */
8474 vcpu->arch.pio.count = 0;
8477 vcpu->arch.complete_userspace_io = complete_emulated_pio;
8480 } else if (vcpu->mmio_needed) {
8481 ++vcpu->stat.mmio_exits;
8483 if (!vcpu->mmio_is_write)
8486 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8487 } else if (vcpu->arch.complete_userspace_io) {
8490 } else if (r == EMULATION_RESTART)
8497 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8498 toggle_interruptibility(vcpu, ctxt->interruptibility);
8499 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8500 if (!ctxt->have_exception ||
8501 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
8502 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8503 if (ctxt->is_branch)
8504 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
8505 kvm_rip_write(vcpu, ctxt->eip);
8506 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
8507 r = kvm_vcpu_do_singlestep(vcpu);
8508 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu);
8509 __kvm_set_rflags(vcpu, ctxt->eflags);
8513 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
8514 * do nothing, and it will be requested again as soon as
8515 * the shadow expires. But we still need to check here,
8516 * because POPF has no interrupt shadow.
8518 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
8519 kvm_make_request(KVM_REQ_EVENT, vcpu);
8521 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
8526 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
8528 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
8530 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
8532 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
8533 void *insn, int insn_len)
8535 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
8537 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
8539 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
8541 vcpu->arch.pio.count = 0;
8545 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
8547 vcpu->arch.pio.count = 0;
8549 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
8552 return kvm_skip_emulated_instruction(vcpu);
8555 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
8556 unsigned short port)
8558 unsigned long val = kvm_rax_read(vcpu);
8559 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
8565 * Workaround userspace that relies on old KVM behavior of %rip being
8566 * incremented prior to exiting to userspace to handle "OUT 0x7e".
8569 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
8570 vcpu->arch.complete_userspace_io =
8571 complete_fast_pio_out_port_0x7e;
8572 kvm_skip_emulated_instruction(vcpu);
8574 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8575 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
8580 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
8584 /* We should only ever be called with arch.pio.count equal to 1 */
8585 BUG_ON(vcpu->arch.pio.count != 1);
8587 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
8588 vcpu->arch.pio.count = 0;
8592 /* For size less than 4 we merge, else we zero extend */
8593 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
8596 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
8597 * the copy and tracing
8599 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
8600 kvm_rax_write(vcpu, val);
8602 return kvm_skip_emulated_instruction(vcpu);
8605 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
8606 unsigned short port)
8611 /* For size less than 4 we merge, else we zero extend */
8612 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
8614 ret = emulator_pio_in(vcpu, size, port, &val, 1);
8616 kvm_rax_write(vcpu, val);
8620 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8621 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
8626 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
8631 ret = kvm_fast_pio_in(vcpu, size, port);
8633 ret = kvm_fast_pio_out(vcpu, size, port);
8634 return ret && kvm_skip_emulated_instruction(vcpu);
8636 EXPORT_SYMBOL_GPL(kvm_fast_pio);
8638 static int kvmclock_cpu_down_prep(unsigned int cpu)
8640 __this_cpu_write(cpu_tsc_khz, 0);
8644 static void tsc_khz_changed(void *data)
8646 struct cpufreq_freqs *freq = data;
8647 unsigned long khz = 0;
8651 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
8652 khz = cpufreq_quick_get(raw_smp_processor_id());
8655 __this_cpu_write(cpu_tsc_khz, khz);
8658 #ifdef CONFIG_X86_64
8659 static void kvm_hyperv_tsc_notifier(void)
8664 mutex_lock(&kvm_lock);
8665 list_for_each_entry(kvm, &vm_list, vm_list)
8666 kvm_make_mclock_inprogress_request(kvm);
8668 /* no guest entries from this point */
8669 hyperv_stop_tsc_emulation();
8671 /* TSC frequency always matches when on Hyper-V */
8672 for_each_present_cpu(cpu)
8673 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
8674 kvm_max_guest_tsc_khz = tsc_khz;
8676 list_for_each_entry(kvm, &vm_list, vm_list) {
8677 __kvm_start_pvclock_update(kvm);
8678 pvclock_update_vm_gtod_copy(kvm);
8679 kvm_end_pvclock_update(kvm);
8682 mutex_unlock(&kvm_lock);
8686 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
8689 struct kvm_vcpu *vcpu;
8694 * We allow guests to temporarily run on slowing clocks,
8695 * provided we notify them after, or to run on accelerating
8696 * clocks, provided we notify them before. Thus time never
8699 * However, we have a problem. We can't atomically update
8700 * the frequency of a given CPU from this function; it is
8701 * merely a notifier, which can be called from any CPU.
8702 * Changing the TSC frequency at arbitrary points in time
8703 * requires a recomputation of local variables related to
8704 * the TSC for each VCPU. We must flag these local variables
8705 * to be updated and be sure the update takes place with the
8706 * new frequency before any guests proceed.
8708 * Unfortunately, the combination of hotplug CPU and frequency
8709 * change creates an intractable locking scenario; the order
8710 * of when these callouts happen is undefined with respect to
8711 * CPU hotplug, and they can race with each other. As such,
8712 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
8713 * undefined; you can actually have a CPU frequency change take
8714 * place in between the computation of X and the setting of the
8715 * variable. To protect against this problem, all updates of
8716 * the per_cpu tsc_khz variable are done in an interrupt
8717 * protected IPI, and all callers wishing to update the value
8718 * must wait for a synchronous IPI to complete (which is trivial
8719 * if the caller is on the CPU already). This establishes the
8720 * necessary total order on variable updates.
8722 * Note that because a guest time update may take place
8723 * anytime after the setting of the VCPU's request bit, the
8724 * correct TSC value must be set before the request. However,
8725 * to ensure the update actually makes it to any guest which
8726 * starts running in hardware virtualization between the set
8727 * and the acquisition of the spinlock, we must also ping the
8728 * CPU after setting the request bit.
8732 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
8734 mutex_lock(&kvm_lock);
8735 list_for_each_entry(kvm, &vm_list, vm_list) {
8736 kvm_for_each_vcpu(i, vcpu, kvm) {
8737 if (vcpu->cpu != cpu)
8739 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8740 if (vcpu->cpu != raw_smp_processor_id())
8744 mutex_unlock(&kvm_lock);
8746 if (freq->old < freq->new && send_ipi) {
8748 * We upscale the frequency. Must make the guest
8749 * doesn't see old kvmclock values while running with
8750 * the new frequency, otherwise we risk the guest sees
8751 * time go backwards.
8753 * In case we update the frequency for another cpu
8754 * (which might be in guest context) send an interrupt
8755 * to kick the cpu out of guest context. Next time
8756 * guest context is entered kvmclock will be updated,
8757 * so the guest will not see stale values.
8759 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
8763 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
8766 struct cpufreq_freqs *freq = data;
8769 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
8771 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
8774 for_each_cpu(cpu, freq->policy->cpus)
8775 __kvmclock_cpufreq_notifier(freq, cpu);
8780 static struct notifier_block kvmclock_cpufreq_notifier_block = {
8781 .notifier_call = kvmclock_cpufreq_notifier
8784 static int kvmclock_cpu_online(unsigned int cpu)
8786 tsc_khz_changed(NULL);
8790 static void kvm_timer_init(void)
8792 max_tsc_khz = tsc_khz;
8794 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
8795 #ifdef CONFIG_CPU_FREQ
8796 struct cpufreq_policy *policy;
8800 policy = cpufreq_cpu_get(cpu);
8802 if (policy->cpuinfo.max_freq)
8803 max_tsc_khz = policy->cpuinfo.max_freq;
8804 cpufreq_cpu_put(policy);
8808 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
8809 CPUFREQ_TRANSITION_NOTIFIER);
8812 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
8813 kvmclock_cpu_online, kvmclock_cpu_down_prep);
8816 #ifdef CONFIG_X86_64
8817 static void pvclock_gtod_update_fn(struct work_struct *work)
8820 struct kvm_vcpu *vcpu;
8823 mutex_lock(&kvm_lock);
8824 list_for_each_entry(kvm, &vm_list, vm_list)
8825 kvm_for_each_vcpu(i, vcpu, kvm)
8826 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
8827 atomic_set(&kvm_guest_has_master_clock, 0);
8828 mutex_unlock(&kvm_lock);
8831 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
8834 * Indirection to move queue_work() out of the tk_core.seq write held
8835 * region to prevent possible deadlocks against time accessors which
8836 * are invoked with work related locks held.
8838 static void pvclock_irq_work_fn(struct irq_work *w)
8840 queue_work(system_long_wq, &pvclock_gtod_work);
8843 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn);
8846 * Notification about pvclock gtod data update.
8848 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
8851 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
8852 struct timekeeper *tk = priv;
8854 update_pvclock_gtod(tk);
8857 * Disable master clock if host does not trust, or does not use,
8858 * TSC based clocksource. Delegate queue_work() to irq_work as
8859 * this is invoked with tk_core.seq write held.
8861 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
8862 atomic_read(&kvm_guest_has_master_clock) != 0)
8863 irq_work_queue(&pvclock_irq_work);
8867 static struct notifier_block pvclock_gtod_notifier = {
8868 .notifier_call = pvclock_gtod_notify,
8872 int kvm_arch_init(void *opaque)
8874 struct kvm_x86_init_ops *ops = opaque;
8877 if (kvm_x86_ops.hardware_enable) {
8878 pr_err("kvm: already loaded vendor module '%s'\n", kvm_x86_ops.name);
8883 if (!ops->cpu_has_kvm_support()) {
8884 pr_err_ratelimited("kvm: no hardware support for '%s'\n",
8885 ops->runtime_ops->name);
8889 if (ops->disabled_by_bios()) {
8890 pr_err_ratelimited("kvm: support for '%s' disabled by bios\n",
8891 ops->runtime_ops->name);
8897 * KVM explicitly assumes that the guest has an FPU and
8898 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
8899 * vCPU's FPU state as a fxregs_state struct.
8901 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
8902 printk(KERN_ERR "kvm: inadequate fpu\n");
8907 if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
8908 pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n");
8915 x86_emulator_cache = kvm_alloc_emulator_cache();
8916 if (!x86_emulator_cache) {
8917 pr_err("kvm: failed to allocate cache for x86 emulator\n");
8921 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
8922 if (!user_return_msrs) {
8923 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
8924 goto out_free_x86_emulator_cache;
8926 kvm_nr_uret_msrs = 0;
8928 r = kvm_mmu_vendor_module_init();
8930 goto out_free_percpu;
8934 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
8935 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
8936 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
8939 if (pi_inject_timer == -1)
8940 pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER);
8941 #ifdef CONFIG_X86_64
8942 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
8944 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
8945 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
8951 free_percpu(user_return_msrs);
8952 out_free_x86_emulator_cache:
8953 kmem_cache_destroy(x86_emulator_cache);
8958 void kvm_arch_exit(void)
8960 #ifdef CONFIG_X86_64
8961 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
8962 clear_hv_tscchange_cb();
8966 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
8967 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
8968 CPUFREQ_TRANSITION_NOTIFIER);
8969 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
8970 #ifdef CONFIG_X86_64
8971 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
8972 irq_work_sync(&pvclock_irq_work);
8973 cancel_work_sync(&pvclock_gtod_work);
8975 kvm_x86_ops.hardware_enable = NULL;
8976 kvm_mmu_vendor_module_exit();
8977 free_percpu(user_return_msrs);
8978 kmem_cache_destroy(x86_emulator_cache);
8979 #ifdef CONFIG_KVM_XEN
8980 static_key_deferred_flush(&kvm_xen_enabled);
8981 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key));
8985 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason)
8988 * The vCPU has halted, e.g. executed HLT. Update the run state if the
8989 * local APIC is in-kernel, the run loop will detect the non-runnable
8990 * state and halt the vCPU. Exit to userspace if the local APIC is
8991 * managed by userspace, in which case userspace is responsible for
8992 * handling wake events.
8994 ++vcpu->stat.halt_exits;
8995 if (lapic_in_kernel(vcpu)) {
8996 vcpu->arch.mp_state = state;
8999 vcpu->run->exit_reason = reason;
9004 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu)
9006 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
9008 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip);
9010 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
9012 int ret = kvm_skip_emulated_instruction(vcpu);
9014 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
9015 * KVM_EXIT_DEBUG here.
9017 return kvm_emulate_halt_noskip(vcpu) && ret;
9019 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
9021 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
9023 int ret = kvm_skip_emulated_instruction(vcpu);
9025 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD,
9026 KVM_EXIT_AP_RESET_HOLD) && ret;
9028 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
9030 #ifdef CONFIG_X86_64
9031 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
9032 unsigned long clock_type)
9034 struct kvm_clock_pairing clock_pairing;
9035 struct timespec64 ts;
9039 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
9040 return -KVM_EOPNOTSUPP;
9043 * When tsc is in permanent catchup mode guests won't be able to use
9044 * pvclock_read_retry loop to get consistent view of pvclock
9046 if (vcpu->arch.tsc_always_catchup)
9047 return -KVM_EOPNOTSUPP;
9049 if (!kvm_get_walltime_and_clockread(&ts, &cycle))
9050 return -KVM_EOPNOTSUPP;
9052 clock_pairing.sec = ts.tv_sec;
9053 clock_pairing.nsec = ts.tv_nsec;
9054 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
9055 clock_pairing.flags = 0;
9056 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
9059 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
9060 sizeof(struct kvm_clock_pairing)))
9068 * kvm_pv_kick_cpu_op: Kick a vcpu.
9070 * @apicid - apicid of vcpu to be kicked.
9072 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid)
9074 struct kvm_lapic_irq lapic_irq;
9076 lapic_irq.shorthand = APIC_DEST_NOSHORT;
9077 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
9078 lapic_irq.level = 0;
9079 lapic_irq.dest_id = apicid;
9080 lapic_irq.msi_redir_hint = false;
9082 lapic_irq.delivery_mode = APIC_DM_REMRD;
9083 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
9086 bool kvm_apicv_activated(struct kvm *kvm)
9088 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
9090 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
9093 static void set_or_clear_apicv_inhibit(unsigned long *inhibits,
9094 enum kvm_apicv_inhibit reason, bool set)
9097 __set_bit(reason, inhibits);
9099 __clear_bit(reason, inhibits);
9101 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits);
9104 static void kvm_apicv_init(struct kvm *kvm)
9106 unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons;
9108 init_rwsem(&kvm->arch.apicv_update_lock);
9110 set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true);
9113 set_or_clear_apicv_inhibit(inhibits,
9114 APICV_INHIBIT_REASON_ABSENT, true);
9117 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id)
9119 struct kvm_vcpu *target = NULL;
9120 struct kvm_apic_map *map;
9122 vcpu->stat.directed_yield_attempted++;
9124 if (single_task_running())
9128 map = rcu_dereference(vcpu->kvm->arch.apic_map);
9130 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
9131 target = map->phys_map[dest_id]->vcpu;
9135 if (!target || !READ_ONCE(target->ready))
9138 /* Ignore requests to yield to self */
9142 if (kvm_vcpu_yield_to(target) <= 0)
9145 vcpu->stat.directed_yield_successful++;
9151 static int complete_hypercall_exit(struct kvm_vcpu *vcpu)
9153 u64 ret = vcpu->run->hypercall.ret;
9155 if (!is_64_bit_mode(vcpu))
9157 kvm_rax_write(vcpu, ret);
9158 ++vcpu->stat.hypercalls;
9159 return kvm_skip_emulated_instruction(vcpu);
9162 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
9164 unsigned long nr, a0, a1, a2, a3, ret;
9167 if (kvm_xen_hypercall_enabled(vcpu->kvm))
9168 return kvm_xen_hypercall(vcpu);
9170 if (kvm_hv_hypercall_enabled(vcpu))
9171 return kvm_hv_hypercall(vcpu);
9173 nr = kvm_rax_read(vcpu);
9174 a0 = kvm_rbx_read(vcpu);
9175 a1 = kvm_rcx_read(vcpu);
9176 a2 = kvm_rdx_read(vcpu);
9177 a3 = kvm_rsi_read(vcpu);
9179 trace_kvm_hypercall(nr, a0, a1, a2, a3);
9181 op_64_bit = is_64_bit_hypercall(vcpu);
9190 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) {
9198 case KVM_HC_VAPIC_POLL_IRQ:
9201 case KVM_HC_KICK_CPU:
9202 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
9205 kvm_pv_kick_cpu_op(vcpu->kvm, a1);
9206 kvm_sched_yield(vcpu, a1);
9209 #ifdef CONFIG_X86_64
9210 case KVM_HC_CLOCK_PAIRING:
9211 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
9214 case KVM_HC_SEND_IPI:
9215 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
9218 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
9220 case KVM_HC_SCHED_YIELD:
9221 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
9224 kvm_sched_yield(vcpu, a0);
9227 case KVM_HC_MAP_GPA_RANGE: {
9228 u64 gpa = a0, npages = a1, attrs = a2;
9231 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE)))
9234 if (!PAGE_ALIGNED(gpa) || !npages ||
9235 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) {
9240 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL;
9241 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE;
9242 vcpu->run->hypercall.args[0] = gpa;
9243 vcpu->run->hypercall.args[1] = npages;
9244 vcpu->run->hypercall.args[2] = attrs;
9245 vcpu->run->hypercall.longmode = op_64_bit;
9246 vcpu->arch.complete_userspace_io = complete_hypercall_exit;
9256 kvm_rax_write(vcpu, ret);
9258 ++vcpu->stat.hypercalls;
9259 return kvm_skip_emulated_instruction(vcpu);
9261 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
9263 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
9265 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
9266 char instruction[3];
9267 unsigned long rip = kvm_rip_read(vcpu);
9269 static_call(kvm_x86_patch_hypercall)(vcpu, instruction);
9271 return emulator_write_emulated(ctxt, rip, instruction, 3,
9275 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
9277 return vcpu->run->request_interrupt_window &&
9278 likely(!pic_in_kernel(vcpu->kvm));
9281 /* Called within kvm->srcu read side. */
9282 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
9284 struct kvm_run *kvm_run = vcpu->run;
9286 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu);
9287 kvm_run->cr8 = kvm_get_cr8(vcpu);
9288 kvm_run->apic_base = kvm_get_apic_base(vcpu);
9290 kvm_run->ready_for_interrupt_injection =
9291 pic_in_kernel(vcpu->kvm) ||
9292 kvm_vcpu_ready_for_interrupt_injection(vcpu);
9295 kvm_run->flags |= KVM_RUN_X86_SMM;
9298 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
9302 if (!kvm_x86_ops.update_cr8_intercept)
9305 if (!lapic_in_kernel(vcpu))
9308 if (vcpu->arch.apicv_active)
9311 if (!vcpu->arch.apic->vapic_addr)
9312 max_irr = kvm_lapic_find_highest_irr(vcpu);
9319 tpr = kvm_lapic_get_cr8(vcpu);
9321 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr);
9325 int kvm_check_nested_events(struct kvm_vcpu *vcpu)
9327 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
9328 kvm_x86_ops.nested_ops->triple_fault(vcpu);
9332 return kvm_x86_ops.nested_ops->check_events(vcpu);
9335 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
9337 if (vcpu->arch.exception.error_code && !is_protmode(vcpu))
9338 vcpu->arch.exception.error_code = false;
9339 static_call(kvm_x86_queue_exception)(vcpu);
9342 static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
9345 bool can_inject = true;
9347 /* try to reinject previous events if any */
9349 if (vcpu->arch.exception.injected) {
9350 kvm_inject_exception(vcpu);
9354 * Do not inject an NMI or interrupt if there is a pending
9355 * exception. Exceptions and interrupts are recognized at
9356 * instruction boundaries, i.e. the start of an instruction.
9357 * Trap-like exceptions, e.g. #DB, have higher priority than
9358 * NMIs and interrupts, i.e. traps are recognized before an
9359 * NMI/interrupt that's pending on the same instruction.
9360 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
9361 * priority, but are only generated (pended) during instruction
9362 * execution, i.e. a pending fault-like exception means the
9363 * fault occurred on the *previous* instruction and must be
9364 * serviced prior to recognizing any new events in order to
9365 * fully complete the previous instruction.
9367 else if (!vcpu->arch.exception.pending) {
9368 if (vcpu->arch.nmi_injected) {
9369 static_call(kvm_x86_inject_nmi)(vcpu);
9371 } else if (vcpu->arch.interrupt.injected) {
9372 static_call(kvm_x86_inject_irq)(vcpu);
9377 WARN_ON_ONCE(vcpu->arch.exception.injected &&
9378 vcpu->arch.exception.pending);
9381 * Call check_nested_events() even if we reinjected a previous event
9382 * in order for caller to determine if it should require immediate-exit
9383 * from L2 to L1 due to pending L1 events which require exit
9386 if (is_guest_mode(vcpu)) {
9387 r = kvm_check_nested_events(vcpu);
9392 /* try to inject new event if pending */
9393 if (vcpu->arch.exception.pending) {
9394 trace_kvm_inj_exception(vcpu->arch.exception.nr,
9395 vcpu->arch.exception.has_error_code,
9396 vcpu->arch.exception.error_code);
9398 vcpu->arch.exception.pending = false;
9399 vcpu->arch.exception.injected = true;
9401 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
9402 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
9405 if (vcpu->arch.exception.nr == DB_VECTOR) {
9406 kvm_deliver_exception_payload(vcpu);
9407 if (vcpu->arch.dr7 & DR7_GD) {
9408 vcpu->arch.dr7 &= ~DR7_GD;
9409 kvm_update_dr7(vcpu);
9413 kvm_inject_exception(vcpu);
9417 /* Don't inject interrupts if the user asked to avoid doing so */
9418 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ)
9422 * Finally, inject interrupt events. If an event cannot be injected
9423 * due to architectural conditions (e.g. IF=0) a window-open exit
9424 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
9425 * and can architecturally be injected, but we cannot do it right now:
9426 * an interrupt could have arrived just now and we have to inject it
9427 * as a vmexit, or there could already an event in the queue, which is
9428 * indicated by can_inject. In that case we request an immediate exit
9429 * in order to make progress and get back here for another iteration.
9430 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
9432 if (vcpu->arch.smi_pending) {
9433 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY;
9437 vcpu->arch.smi_pending = false;
9438 ++vcpu->arch.smi_count;
9442 static_call(kvm_x86_enable_smi_window)(vcpu);
9445 if (vcpu->arch.nmi_pending) {
9446 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY;
9450 --vcpu->arch.nmi_pending;
9451 vcpu->arch.nmi_injected = true;
9452 static_call(kvm_x86_inject_nmi)(vcpu);
9454 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0);
9456 if (vcpu->arch.nmi_pending)
9457 static_call(kvm_x86_enable_nmi_window)(vcpu);
9460 if (kvm_cpu_has_injectable_intr(vcpu)) {
9461 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY;
9465 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
9466 static_call(kvm_x86_inject_irq)(vcpu);
9467 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
9469 if (kvm_cpu_has_injectable_intr(vcpu))
9470 static_call(kvm_x86_enable_irq_window)(vcpu);
9473 if (is_guest_mode(vcpu) &&
9474 kvm_x86_ops.nested_ops->hv_timer_pending &&
9475 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
9476 *req_immediate_exit = true;
9478 WARN_ON(vcpu->arch.exception.pending);
9483 *req_immediate_exit = true;
9489 static void process_nmi(struct kvm_vcpu *vcpu)
9494 * x86 is limited to one NMI running, and one NMI pending after it.
9495 * If an NMI is already in progress, limit further NMIs to just one.
9496 * Otherwise, allow two (and we'll inject the first one immediately).
9498 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected)
9501 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
9502 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
9503 kvm_make_request(KVM_REQ_EVENT, vcpu);
9506 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
9509 flags |= seg->g << 23;
9510 flags |= seg->db << 22;
9511 flags |= seg->l << 21;
9512 flags |= seg->avl << 20;
9513 flags |= seg->present << 15;
9514 flags |= seg->dpl << 13;
9515 flags |= seg->s << 12;
9516 flags |= seg->type << 8;
9520 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
9522 struct kvm_segment seg;
9525 kvm_get_segment(vcpu, &seg, n);
9526 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
9529 offset = 0x7f84 + n * 12;
9531 offset = 0x7f2c + (n - 3) * 12;
9533 put_smstate(u32, buf, offset + 8, seg.base);
9534 put_smstate(u32, buf, offset + 4, seg.limit);
9535 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
9538 #ifdef CONFIG_X86_64
9539 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
9541 struct kvm_segment seg;
9545 kvm_get_segment(vcpu, &seg, n);
9546 offset = 0x7e00 + n * 16;
9548 flags = enter_smm_get_segment_flags(&seg) >> 8;
9549 put_smstate(u16, buf, offset, seg.selector);
9550 put_smstate(u16, buf, offset + 2, flags);
9551 put_smstate(u32, buf, offset + 4, seg.limit);
9552 put_smstate(u64, buf, offset + 8, seg.base);
9556 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
9559 struct kvm_segment seg;
9563 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
9564 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
9565 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
9566 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
9568 for (i = 0; i < 8; i++)
9569 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i));
9571 kvm_get_dr(vcpu, 6, &val);
9572 put_smstate(u32, buf, 0x7fcc, (u32)val);
9573 kvm_get_dr(vcpu, 7, &val);
9574 put_smstate(u32, buf, 0x7fc8, (u32)val);
9576 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
9577 put_smstate(u32, buf, 0x7fc4, seg.selector);
9578 put_smstate(u32, buf, 0x7f64, seg.base);
9579 put_smstate(u32, buf, 0x7f60, seg.limit);
9580 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
9582 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
9583 put_smstate(u32, buf, 0x7fc0, seg.selector);
9584 put_smstate(u32, buf, 0x7f80, seg.base);
9585 put_smstate(u32, buf, 0x7f7c, seg.limit);
9586 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
9588 static_call(kvm_x86_get_gdt)(vcpu, &dt);
9589 put_smstate(u32, buf, 0x7f74, dt.address);
9590 put_smstate(u32, buf, 0x7f70, dt.size);
9592 static_call(kvm_x86_get_idt)(vcpu, &dt);
9593 put_smstate(u32, buf, 0x7f58, dt.address);
9594 put_smstate(u32, buf, 0x7f54, dt.size);
9596 for (i = 0; i < 6; i++)
9597 enter_smm_save_seg_32(vcpu, buf, i);
9599 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
9602 put_smstate(u32, buf, 0x7efc, 0x00020000);
9603 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
9606 #ifdef CONFIG_X86_64
9607 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
9610 struct kvm_segment seg;
9614 for (i = 0; i < 16; i++)
9615 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i));
9617 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
9618 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
9620 kvm_get_dr(vcpu, 6, &val);
9621 put_smstate(u64, buf, 0x7f68, val);
9622 kvm_get_dr(vcpu, 7, &val);
9623 put_smstate(u64, buf, 0x7f60, val);
9625 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
9626 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
9627 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
9629 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
9632 put_smstate(u32, buf, 0x7efc, 0x00020064);
9634 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
9636 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
9637 put_smstate(u16, buf, 0x7e90, seg.selector);
9638 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
9639 put_smstate(u32, buf, 0x7e94, seg.limit);
9640 put_smstate(u64, buf, 0x7e98, seg.base);
9642 static_call(kvm_x86_get_idt)(vcpu, &dt);
9643 put_smstate(u32, buf, 0x7e84, dt.size);
9644 put_smstate(u64, buf, 0x7e88, dt.address);
9646 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
9647 put_smstate(u16, buf, 0x7e70, seg.selector);
9648 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
9649 put_smstate(u32, buf, 0x7e74, seg.limit);
9650 put_smstate(u64, buf, 0x7e78, seg.base);
9652 static_call(kvm_x86_get_gdt)(vcpu, &dt);
9653 put_smstate(u32, buf, 0x7e64, dt.size);
9654 put_smstate(u64, buf, 0x7e68, dt.address);
9656 for (i = 0; i < 6; i++)
9657 enter_smm_save_seg_64(vcpu, buf, i);
9661 static void enter_smm(struct kvm_vcpu *vcpu)
9663 struct kvm_segment cs, ds;
9668 memset(buf, 0, 512);
9669 #ifdef CONFIG_X86_64
9670 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
9671 enter_smm_save_state_64(vcpu, buf);
9674 enter_smm_save_state_32(vcpu, buf);
9677 * Give enter_smm() a chance to make ISA-specific changes to the vCPU
9678 * state (e.g. leave guest mode) after we've saved the state into the
9679 * SMM state-save area.
9681 static_call(kvm_x86_enter_smm)(vcpu, buf);
9683 kvm_smm_changed(vcpu, true);
9684 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
9686 if (static_call(kvm_x86_get_nmi_mask)(vcpu))
9687 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
9689 static_call(kvm_x86_set_nmi_mask)(vcpu, true);
9691 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
9692 kvm_rip_write(vcpu, 0x8000);
9694 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
9695 static_call(kvm_x86_set_cr0)(vcpu, cr0);
9696 vcpu->arch.cr0 = cr0;
9698 static_call(kvm_x86_set_cr4)(vcpu, 0);
9700 /* Undocumented: IDT limit is set to zero on entry to SMM. */
9701 dt.address = dt.size = 0;
9702 static_call(kvm_x86_set_idt)(vcpu, &dt);
9704 kvm_set_dr(vcpu, 7, DR7_FIXED_1);
9706 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
9707 cs.base = vcpu->arch.smbase;
9712 cs.limit = ds.limit = 0xffffffff;
9713 cs.type = ds.type = 0x3;
9714 cs.dpl = ds.dpl = 0;
9719 cs.avl = ds.avl = 0;
9720 cs.present = ds.present = 1;
9721 cs.unusable = ds.unusable = 0;
9722 cs.padding = ds.padding = 0;
9724 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9725 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
9726 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
9727 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
9728 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
9729 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
9731 #ifdef CONFIG_X86_64
9732 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
9733 static_call(kvm_x86_set_efer)(vcpu, 0);
9736 kvm_update_cpuid_runtime(vcpu);
9737 kvm_mmu_reset_context(vcpu);
9740 static void process_smi(struct kvm_vcpu *vcpu)
9742 vcpu->arch.smi_pending = true;
9743 kvm_make_request(KVM_REQ_EVENT, vcpu);
9746 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
9747 unsigned long *vcpu_bitmap)
9749 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap);
9752 void kvm_make_scan_ioapic_request(struct kvm *kvm)
9754 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
9757 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
9761 if (!lapic_in_kernel(vcpu))
9764 down_read(&vcpu->kvm->arch.apicv_update_lock);
9766 activate = kvm_apicv_activated(vcpu->kvm);
9767 if (vcpu->arch.apicv_active == activate)
9770 vcpu->arch.apicv_active = activate;
9771 kvm_apic_update_apicv(vcpu);
9772 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
9775 * When APICv gets disabled, we may still have injected interrupts
9776 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was
9777 * still active when the interrupt got accepted. Make sure
9778 * inject_pending_event() is called to check for that.
9780 if (!vcpu->arch.apicv_active)
9781 kvm_make_request(KVM_REQ_EVENT, vcpu);
9784 up_read(&vcpu->kvm->arch.apicv_update_lock);
9786 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
9788 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
9789 enum kvm_apicv_inhibit reason, bool set)
9791 unsigned long old, new;
9793 lockdep_assert_held_write(&kvm->arch.apicv_update_lock);
9795 if (!static_call(kvm_x86_check_apicv_inhibit_reasons)(reason))
9798 old = new = kvm->arch.apicv_inhibit_reasons;
9800 set_or_clear_apicv_inhibit(&new, reason, set);
9802 if (!!old != !!new) {
9804 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid
9805 * false positives in the sanity check WARN in svm_vcpu_run().
9806 * This task will wait for all vCPUs to ack the kick IRQ before
9807 * updating apicv_inhibit_reasons, and all other vCPUs will
9808 * block on acquiring apicv_update_lock so that vCPUs can't
9809 * redo svm_vcpu_run() without seeing the new inhibit state.
9811 * Note, holding apicv_update_lock and taking it in the read
9812 * side (handling the request) also prevents other vCPUs from
9813 * servicing the request with a stale apicv_inhibit_reasons.
9815 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
9816 kvm->arch.apicv_inhibit_reasons = new;
9818 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE);
9819 kvm_zap_gfn_range(kvm, gfn, gfn+1);
9822 kvm->arch.apicv_inhibit_reasons = new;
9826 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
9827 enum kvm_apicv_inhibit reason, bool set)
9832 down_write(&kvm->arch.apicv_update_lock);
9833 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set);
9834 up_write(&kvm->arch.apicv_update_lock);
9836 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit);
9838 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
9840 if (!kvm_apic_present(vcpu))
9843 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
9845 if (irqchip_split(vcpu->kvm))
9846 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
9848 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
9849 if (ioapic_in_kernel(vcpu->kvm))
9850 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
9853 if (is_guest_mode(vcpu))
9854 vcpu->arch.load_eoi_exitmap_pending = true;
9856 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
9859 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
9861 u64 eoi_exit_bitmap[4];
9863 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
9866 if (to_hv_vcpu(vcpu)) {
9867 bitmap_or((ulong *)eoi_exit_bitmap,
9868 vcpu->arch.ioapic_handled_vectors,
9869 to_hv_synic(vcpu)->vec_bitmap, 256);
9870 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap);
9874 static_call_cond(kvm_x86_load_eoi_exitmap)(
9875 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors);
9878 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
9879 unsigned long start, unsigned long end)
9881 unsigned long apic_address;
9884 * The physical address of apic access page is stored in the VMCS.
9885 * Update it when it becomes invalid.
9887 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
9888 if (start <= apic_address && apic_address < end)
9889 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
9892 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
9894 if (!lapic_in_kernel(vcpu))
9897 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu);
9900 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
9902 smp_send_reschedule(vcpu->cpu);
9904 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
9907 * Called within kvm->srcu read side.
9908 * Returns 1 to let vcpu_run() continue the guest execution loop without
9909 * exiting to the userspace. Otherwise, the value will be returned to the
9912 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
9916 dm_request_for_irq_injection(vcpu) &&
9917 kvm_cpu_accept_dm_intr(vcpu);
9918 fastpath_t exit_fastpath;
9920 bool req_immediate_exit = false;
9922 /* Forbid vmenter if vcpu dirty ring is soft-full */
9923 if (unlikely(vcpu->kvm->dirty_ring_size &&
9924 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) {
9925 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL;
9926 trace_kvm_dirty_ring_exit(vcpu);
9931 if (kvm_request_pending(vcpu)) {
9932 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) {
9936 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
9937 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
9942 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu))
9943 kvm_mmu_free_obsolete_roots(vcpu);
9944 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
9945 __kvm_migrate_timers(vcpu);
9946 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
9947 kvm_update_masterclock(vcpu->kvm);
9948 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
9949 kvm_gen_kvmclock_update(vcpu);
9950 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
9951 r = kvm_guest_time_update(vcpu);
9955 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
9956 kvm_mmu_sync_roots(vcpu);
9957 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
9958 kvm_mmu_load_pgd(vcpu);
9959 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
9960 kvm_vcpu_flush_tlb_all(vcpu);
9962 /* Flushing all ASIDs flushes the current ASID... */
9963 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
9965 kvm_service_local_tlb_flush_requests(vcpu);
9967 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
9968 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
9972 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
9973 if (is_guest_mode(vcpu)) {
9974 kvm_x86_ops.nested_ops->triple_fault(vcpu);
9976 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
9977 vcpu->mmio_needed = 0;
9982 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
9983 /* Page is swapped out. Do synthetic halt */
9984 vcpu->arch.apf.halted = true;
9988 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
9989 record_steal_time(vcpu);
9990 if (kvm_check_request(KVM_REQ_SMI, vcpu))
9992 if (kvm_check_request(KVM_REQ_NMI, vcpu))
9994 if (kvm_check_request(KVM_REQ_PMU, vcpu))
9995 kvm_pmu_handle_event(vcpu);
9996 if (kvm_check_request(KVM_REQ_PMI, vcpu))
9997 kvm_pmu_deliver_pmi(vcpu);
9998 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
9999 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
10000 if (test_bit(vcpu->arch.pending_ioapic_eoi,
10001 vcpu->arch.ioapic_handled_vectors)) {
10002 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
10003 vcpu->run->eoi.vector =
10004 vcpu->arch.pending_ioapic_eoi;
10009 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
10010 vcpu_scan_ioapic(vcpu);
10011 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
10012 vcpu_load_eoi_exitmap(vcpu);
10013 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
10014 kvm_vcpu_reload_apic_access_page(vcpu);
10015 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
10016 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10017 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
10021 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
10022 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10023 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
10027 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
10028 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
10030 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
10031 vcpu->run->hyperv = hv_vcpu->exit;
10037 * KVM_REQ_HV_STIMER has to be processed after
10038 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
10039 * depend on the guest clock being up-to-date
10041 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
10042 kvm_hv_process_stimers(vcpu);
10043 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
10044 kvm_vcpu_update_apicv(vcpu);
10045 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
10046 kvm_check_async_pf_completion(vcpu);
10047 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
10048 static_call(kvm_x86_msr_filter_changed)(vcpu);
10050 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
10051 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu);
10054 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win ||
10055 kvm_xen_has_interrupt(vcpu)) {
10056 ++vcpu->stat.req_event;
10057 r = kvm_apic_accept_events(vcpu);
10062 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
10067 r = inject_pending_event(vcpu, &req_immediate_exit);
10073 static_call(kvm_x86_enable_irq_window)(vcpu);
10075 if (kvm_lapic_enabled(vcpu)) {
10076 update_cr8_intercept(vcpu);
10077 kvm_lapic_sync_to_vapic(vcpu);
10081 r = kvm_mmu_reload(vcpu);
10083 goto cancel_injection;
10088 static_call(kvm_x86_prepare_switch_to_guest)(vcpu);
10091 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
10092 * IPI are then delayed after guest entry, which ensures that they
10093 * result in virtual interrupt delivery.
10095 local_irq_disable();
10097 /* Store vcpu->apicv_active before vcpu->mode. */
10098 smp_store_release(&vcpu->mode, IN_GUEST_MODE);
10100 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
10103 * 1) We should set ->mode before checking ->requests. Please see
10104 * the comment in kvm_vcpu_exiting_guest_mode().
10106 * 2) For APICv, we should set ->mode before checking PID.ON. This
10107 * pairs with the memory barrier implicit in pi_test_and_set_on
10108 * (see vmx_deliver_posted_interrupt).
10110 * 3) This also orders the write to mode from any reads to the page
10111 * tables done while the VCPU is running. Please see the comment
10112 * in kvm_flush_remote_tlbs.
10114 smp_mb__after_srcu_read_unlock();
10117 * Process pending posted interrupts to handle the case where the
10118 * notification IRQ arrived in the host, or was never sent (because the
10119 * target vCPU wasn't running). Do this regardless of the vCPU's APICv
10120 * status, KVM doesn't update assigned devices when APICv is inhibited,
10121 * i.e. they can post interrupts even if APICv is temporarily disabled.
10123 if (kvm_lapic_enabled(vcpu))
10124 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10126 if (kvm_vcpu_exit_request(vcpu)) {
10127 vcpu->mode = OUTSIDE_GUEST_MODE;
10129 local_irq_enable();
10131 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
10133 goto cancel_injection;
10136 if (req_immediate_exit) {
10137 kvm_make_request(KVM_REQ_EVENT, vcpu);
10138 static_call(kvm_x86_request_immediate_exit)(vcpu);
10141 fpregs_assert_state_consistent();
10142 if (test_thread_flag(TIF_NEED_FPU_LOAD))
10143 switch_fpu_return();
10145 if (vcpu->arch.guest_fpu.xfd_err)
10146 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);
10148 if (unlikely(vcpu->arch.switch_db_regs)) {
10149 set_debugreg(0, 7);
10150 set_debugreg(vcpu->arch.eff_db[0], 0);
10151 set_debugreg(vcpu->arch.eff_db[1], 1);
10152 set_debugreg(vcpu->arch.eff_db[2], 2);
10153 set_debugreg(vcpu->arch.eff_db[3], 3);
10154 } else if (unlikely(hw_breakpoint_active())) {
10155 set_debugreg(0, 7);
10158 guest_timing_enter_irqoff();
10162 * Assert that vCPU vs. VM APICv state is consistent. An APICv
10163 * update must kick and wait for all vCPUs before toggling the
10164 * per-VM state, and responsing vCPUs must wait for the update
10165 * to complete before servicing KVM_REQ_APICV_UPDATE.
10167 WARN_ON_ONCE(kvm_apicv_activated(vcpu->kvm) != kvm_vcpu_apicv_active(vcpu));
10169 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu);
10170 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST))
10173 if (kvm_lapic_enabled(vcpu))
10174 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10176 if (unlikely(kvm_vcpu_exit_request(vcpu))) {
10177 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
10183 * Do this here before restoring debug registers on the host. And
10184 * since we do this before handling the vmexit, a DR access vmexit
10185 * can (a) read the correct value of the debug registers, (b) set
10186 * KVM_DEBUGREG_WONT_EXIT again.
10188 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
10189 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
10190 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu);
10191 kvm_update_dr0123(vcpu);
10192 kvm_update_dr7(vcpu);
10196 * If the guest has used debug registers, at least dr7
10197 * will be disabled while returning to the host.
10198 * If we don't have active breakpoints in the host, we don't
10199 * care about the messed up debug address registers. But if
10200 * we have some of them active, restore the old state.
10202 if (hw_breakpoint_active())
10203 hw_breakpoint_restore();
10205 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
10206 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
10208 vcpu->mode = OUTSIDE_GUEST_MODE;
10212 * Sync xfd before calling handle_exit_irqoff() which may
10213 * rely on the fact that guest_fpu::xfd is up-to-date (e.g.
10214 * in #NM irqoff handler).
10216 if (vcpu->arch.xfd_no_write_intercept)
10217 fpu_sync_guest_vmexit_xfd_state();
10219 static_call(kvm_x86_handle_exit_irqoff)(vcpu);
10221 if (vcpu->arch.guest_fpu.xfd_err)
10222 wrmsrl(MSR_IA32_XFD_ERR, 0);
10225 * Consume any pending interrupts, including the possible source of
10226 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
10227 * An instruction is required after local_irq_enable() to fully unblock
10228 * interrupts on processors that implement an interrupt shadow, the
10229 * stat.exits increment will do nicely.
10231 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ);
10232 local_irq_enable();
10233 ++vcpu->stat.exits;
10234 local_irq_disable();
10235 kvm_after_interrupt(vcpu);
10238 * Wait until after servicing IRQs to account guest time so that any
10239 * ticks that occurred while running the guest are properly accounted
10240 * to the guest. Waiting until IRQs are enabled degrades the accuracy
10241 * of accounting via context tracking, but the loss of accuracy is
10242 * acceptable for all known use cases.
10244 guest_timing_exit_irqoff();
10246 if (lapic_in_kernel(vcpu)) {
10247 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
10248 if (delta != S64_MIN) {
10249 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
10250 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
10254 local_irq_enable();
10257 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
10260 * Profile KVM exit RIPs:
10262 if (unlikely(prof_on == KVM_PROFILING)) {
10263 unsigned long rip = kvm_rip_read(vcpu);
10264 profile_hit(KVM_PROFILING, (void *)rip);
10267 if (unlikely(vcpu->arch.tsc_always_catchup))
10268 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10270 if (vcpu->arch.apic_attention)
10271 kvm_lapic_sync_from_vapic(vcpu);
10273 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath);
10277 if (req_immediate_exit)
10278 kvm_make_request(KVM_REQ_EVENT, vcpu);
10279 static_call(kvm_x86_cancel_injection)(vcpu);
10280 if (unlikely(vcpu->arch.apic_attention))
10281 kvm_lapic_sync_from_vapic(vcpu);
10286 /* Called within kvm->srcu read side. */
10287 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
10291 if (!kvm_arch_vcpu_runnable(vcpu)) {
10293 * Switch to the software timer before halt-polling/blocking as
10294 * the guest's timer may be a break event for the vCPU, and the
10295 * hypervisor timer runs only when the CPU is in guest mode.
10296 * Switch before halt-polling so that KVM recognizes an expired
10297 * timer before blocking.
10299 hv_timer = kvm_lapic_hv_timer_in_use(vcpu);
10301 kvm_lapic_switch_to_sw_timer(vcpu);
10303 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
10304 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10305 kvm_vcpu_halt(vcpu);
10307 kvm_vcpu_block(vcpu);
10308 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
10311 kvm_lapic_switch_to_hv_timer(vcpu);
10313 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
10317 if (kvm_apic_accept_events(vcpu) < 0)
10319 switch(vcpu->arch.mp_state) {
10320 case KVM_MP_STATE_HALTED:
10321 case KVM_MP_STATE_AP_RESET_HOLD:
10322 vcpu->arch.pv.pv_unhalted = false;
10323 vcpu->arch.mp_state =
10324 KVM_MP_STATE_RUNNABLE;
10326 case KVM_MP_STATE_RUNNABLE:
10327 vcpu->arch.apf.halted = false;
10329 case KVM_MP_STATE_INIT_RECEIVED:
10337 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
10339 if (is_guest_mode(vcpu))
10340 kvm_check_nested_events(vcpu);
10342 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
10343 !vcpu->arch.apf.halted);
10346 /* Called within kvm->srcu read side. */
10347 static int vcpu_run(struct kvm_vcpu *vcpu)
10350 struct kvm *kvm = vcpu->kvm;
10352 vcpu->arch.l1tf_flush_l1d = true;
10355 if (kvm_vcpu_running(vcpu)) {
10356 r = vcpu_enter_guest(vcpu);
10358 r = vcpu_block(kvm, vcpu);
10364 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu);
10365 if (kvm_cpu_has_pending_timer(vcpu))
10366 kvm_inject_pending_timer_irqs(vcpu);
10368 if (dm_request_for_irq_injection(vcpu) &&
10369 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
10371 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
10372 ++vcpu->stat.request_irq_exits;
10376 if (__xfer_to_guest_mode_work_pending()) {
10377 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
10378 r = xfer_to_guest_mode_handle_work(vcpu);
10379 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
10388 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
10392 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
10393 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
10394 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
10398 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
10400 BUG_ON(!vcpu->arch.pio.count);
10402 return complete_emulated_io(vcpu);
10406 * Implements the following, as a state machine:
10409 * for each fragment
10410 * for each mmio piece in the fragment
10417 * for each fragment
10418 * for each mmio piece in the fragment
10423 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
10425 struct kvm_run *run = vcpu->run;
10426 struct kvm_mmio_fragment *frag;
10429 BUG_ON(!vcpu->mmio_needed);
10431 /* Complete previous fragment */
10432 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
10433 len = min(8u, frag->len);
10434 if (!vcpu->mmio_is_write)
10435 memcpy(frag->data, run->mmio.data, len);
10437 if (frag->len <= 8) {
10438 /* Switch to the next fragment. */
10440 vcpu->mmio_cur_fragment++;
10442 /* Go forward to the next mmio piece. */
10448 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
10449 vcpu->mmio_needed = 0;
10451 /* FIXME: return into emulator if single-stepping. */
10452 if (vcpu->mmio_is_write)
10454 vcpu->mmio_read_completed = 1;
10455 return complete_emulated_io(vcpu);
10458 run->exit_reason = KVM_EXIT_MMIO;
10459 run->mmio.phys_addr = frag->gpa;
10460 if (vcpu->mmio_is_write)
10461 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
10462 run->mmio.len = min(8u, frag->len);
10463 run->mmio.is_write = vcpu->mmio_is_write;
10464 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
10468 /* Swap (qemu) user FPU context for the guest FPU context. */
10469 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
10471 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */
10472 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true);
10476 /* When vcpu_run ends, restore user space FPU context. */
10477 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
10479 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false);
10480 ++vcpu->stat.fpu_reload;
10484 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
10486 struct kvm_run *kvm_run = vcpu->run;
10487 struct kvm *kvm = vcpu->kvm;
10491 kvm_sigset_activate(vcpu);
10492 kvm_run->flags = 0;
10493 kvm_load_guest_fpu(vcpu);
10495 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
10496 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
10497 if (kvm_run->immediate_exit) {
10502 * It should be impossible for the hypervisor timer to be in
10503 * use before KVM has ever run the vCPU.
10505 WARN_ON_ONCE(kvm_lapic_hv_timer_in_use(vcpu));
10507 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
10508 kvm_vcpu_block(vcpu);
10509 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
10511 if (kvm_apic_accept_events(vcpu) < 0) {
10515 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
10517 if (signal_pending(current)) {
10519 kvm_run->exit_reason = KVM_EXIT_INTR;
10520 ++vcpu->stat.signal_exits;
10525 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) ||
10526 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) {
10531 if (kvm_run->kvm_dirty_regs) {
10532 r = sync_regs(vcpu);
10537 /* re-sync apic's tpr */
10538 if (!lapic_in_kernel(vcpu)) {
10539 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
10545 if (unlikely(vcpu->arch.complete_userspace_io)) {
10546 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
10547 vcpu->arch.complete_userspace_io = NULL;
10552 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
10554 if (kvm_run->immediate_exit) {
10559 r = static_call(kvm_x86_vcpu_pre_run)(vcpu);
10563 r = vcpu_run(vcpu);
10566 kvm_put_guest_fpu(vcpu);
10567 if (kvm_run->kvm_valid_regs)
10569 post_kvm_run_save(vcpu);
10570 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
10572 kvm_sigset_deactivate(vcpu);
10577 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10579 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
10581 * We are here if userspace calls get_regs() in the middle of
10582 * instruction emulation. Registers state needs to be copied
10583 * back from emulation context to vcpu. Userspace shouldn't do
10584 * that usually, but some bad designed PV devices (vmware
10585 * backdoor interface) need this to work
10587 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
10588 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
10590 regs->rax = kvm_rax_read(vcpu);
10591 regs->rbx = kvm_rbx_read(vcpu);
10592 regs->rcx = kvm_rcx_read(vcpu);
10593 regs->rdx = kvm_rdx_read(vcpu);
10594 regs->rsi = kvm_rsi_read(vcpu);
10595 regs->rdi = kvm_rdi_read(vcpu);
10596 regs->rsp = kvm_rsp_read(vcpu);
10597 regs->rbp = kvm_rbp_read(vcpu);
10598 #ifdef CONFIG_X86_64
10599 regs->r8 = kvm_r8_read(vcpu);
10600 regs->r9 = kvm_r9_read(vcpu);
10601 regs->r10 = kvm_r10_read(vcpu);
10602 regs->r11 = kvm_r11_read(vcpu);
10603 regs->r12 = kvm_r12_read(vcpu);
10604 regs->r13 = kvm_r13_read(vcpu);
10605 regs->r14 = kvm_r14_read(vcpu);
10606 regs->r15 = kvm_r15_read(vcpu);
10609 regs->rip = kvm_rip_read(vcpu);
10610 regs->rflags = kvm_get_rflags(vcpu);
10613 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10616 __get_regs(vcpu, regs);
10621 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10623 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
10624 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
10626 kvm_rax_write(vcpu, regs->rax);
10627 kvm_rbx_write(vcpu, regs->rbx);
10628 kvm_rcx_write(vcpu, regs->rcx);
10629 kvm_rdx_write(vcpu, regs->rdx);
10630 kvm_rsi_write(vcpu, regs->rsi);
10631 kvm_rdi_write(vcpu, regs->rdi);
10632 kvm_rsp_write(vcpu, regs->rsp);
10633 kvm_rbp_write(vcpu, regs->rbp);
10634 #ifdef CONFIG_X86_64
10635 kvm_r8_write(vcpu, regs->r8);
10636 kvm_r9_write(vcpu, regs->r9);
10637 kvm_r10_write(vcpu, regs->r10);
10638 kvm_r11_write(vcpu, regs->r11);
10639 kvm_r12_write(vcpu, regs->r12);
10640 kvm_r13_write(vcpu, regs->r13);
10641 kvm_r14_write(vcpu, regs->r14);
10642 kvm_r15_write(vcpu, regs->r15);
10645 kvm_rip_write(vcpu, regs->rip);
10646 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
10648 vcpu->arch.exception.pending = false;
10650 kvm_make_request(KVM_REQ_EVENT, vcpu);
10653 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10656 __set_regs(vcpu, regs);
10661 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
10663 struct desc_ptr dt;
10665 if (vcpu->arch.guest_state_protected)
10666 goto skip_protected_regs;
10668 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
10669 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
10670 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
10671 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
10672 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
10673 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
10675 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
10676 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
10678 static_call(kvm_x86_get_idt)(vcpu, &dt);
10679 sregs->idt.limit = dt.size;
10680 sregs->idt.base = dt.address;
10681 static_call(kvm_x86_get_gdt)(vcpu, &dt);
10682 sregs->gdt.limit = dt.size;
10683 sregs->gdt.base = dt.address;
10685 sregs->cr2 = vcpu->arch.cr2;
10686 sregs->cr3 = kvm_read_cr3(vcpu);
10688 skip_protected_regs:
10689 sregs->cr0 = kvm_read_cr0(vcpu);
10690 sregs->cr4 = kvm_read_cr4(vcpu);
10691 sregs->cr8 = kvm_get_cr8(vcpu);
10692 sregs->efer = vcpu->arch.efer;
10693 sregs->apic_base = kvm_get_apic_base(vcpu);
10696 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
10698 __get_sregs_common(vcpu, sregs);
10700 if (vcpu->arch.guest_state_protected)
10703 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
10704 set_bit(vcpu->arch.interrupt.nr,
10705 (unsigned long *)sregs->interrupt_bitmap);
10708 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
10712 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2);
10714 if (vcpu->arch.guest_state_protected)
10717 if (is_pae_paging(vcpu)) {
10718 for (i = 0 ; i < 4 ; i++)
10719 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i);
10720 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
10724 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
10725 struct kvm_sregs *sregs)
10728 __get_sregs(vcpu, sregs);
10733 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
10734 struct kvm_mp_state *mp_state)
10739 if (kvm_mpx_supported())
10740 kvm_load_guest_fpu(vcpu);
10742 r = kvm_apic_accept_events(vcpu);
10747 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
10748 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
10749 vcpu->arch.pv.pv_unhalted)
10750 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
10752 mp_state->mp_state = vcpu->arch.mp_state;
10755 if (kvm_mpx_supported())
10756 kvm_put_guest_fpu(vcpu);
10761 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
10762 struct kvm_mp_state *mp_state)
10768 if (!lapic_in_kernel(vcpu) &&
10769 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
10773 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
10774 * INIT state; latched init should be reported using
10775 * KVM_SET_VCPU_EVENTS, so reject it here.
10777 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
10778 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
10779 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
10782 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
10783 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
10784 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
10786 vcpu->arch.mp_state = mp_state->mp_state;
10787 kvm_make_request(KVM_REQ_EVENT, vcpu);
10795 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
10796 int reason, bool has_error_code, u32 error_code)
10798 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
10801 init_emulate_ctxt(vcpu);
10803 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
10804 has_error_code, error_code);
10806 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
10807 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
10808 vcpu->run->internal.ndata = 0;
10812 kvm_rip_write(vcpu, ctxt->eip);
10813 kvm_set_rflags(vcpu, ctxt->eflags);
10816 EXPORT_SYMBOL_GPL(kvm_task_switch);
10818 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
10820 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
10822 * When EFER.LME and CR0.PG are set, the processor is in
10823 * 64-bit mode (though maybe in a 32-bit code segment).
10824 * CR4.PAE and EFER.LMA must be set.
10826 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
10828 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3))
10832 * Not in 64-bit mode: EFER.LMA is clear and the code
10833 * segment cannot be 64-bit.
10835 if (sregs->efer & EFER_LMA || sregs->cs.l)
10839 return kvm_is_valid_cr4(vcpu, sregs->cr4);
10842 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs,
10843 int *mmu_reset_needed, bool update_pdptrs)
10845 struct msr_data apic_base_msr;
10847 struct desc_ptr dt;
10849 if (!kvm_is_valid_sregs(vcpu, sregs))
10852 apic_base_msr.data = sregs->apic_base;
10853 apic_base_msr.host_initiated = true;
10854 if (kvm_set_apic_base(vcpu, &apic_base_msr))
10857 if (vcpu->arch.guest_state_protected)
10860 dt.size = sregs->idt.limit;
10861 dt.address = sregs->idt.base;
10862 static_call(kvm_x86_set_idt)(vcpu, &dt);
10863 dt.size = sregs->gdt.limit;
10864 dt.address = sregs->gdt.base;
10865 static_call(kvm_x86_set_gdt)(vcpu, &dt);
10867 vcpu->arch.cr2 = sregs->cr2;
10868 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
10869 vcpu->arch.cr3 = sregs->cr3;
10870 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
10871 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3);
10873 kvm_set_cr8(vcpu, sregs->cr8);
10875 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
10876 static_call(kvm_x86_set_efer)(vcpu, sregs->efer);
10878 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
10879 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0);
10880 vcpu->arch.cr0 = sregs->cr0;
10882 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
10883 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4);
10885 if (update_pdptrs) {
10886 idx = srcu_read_lock(&vcpu->kvm->srcu);
10887 if (is_pae_paging(vcpu)) {
10888 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
10889 *mmu_reset_needed = 1;
10891 srcu_read_unlock(&vcpu->kvm->srcu, idx);
10894 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
10895 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
10896 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
10897 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
10898 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
10899 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
10901 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
10902 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
10904 update_cr8_intercept(vcpu);
10906 /* Older userspace won't unhalt the vcpu on reset. */
10907 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
10908 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
10909 !is_protmode(vcpu))
10910 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10915 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
10917 int pending_vec, max_bits;
10918 int mmu_reset_needed = 0;
10919 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true);
10924 if (mmu_reset_needed)
10925 kvm_mmu_reset_context(vcpu);
10927 max_bits = KVM_NR_INTERRUPTS;
10928 pending_vec = find_first_bit(
10929 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
10931 if (pending_vec < max_bits) {
10932 kvm_queue_interrupt(vcpu, pending_vec, false);
10933 pr_debug("Set back pending irq %d\n", pending_vec);
10934 kvm_make_request(KVM_REQ_EVENT, vcpu);
10939 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
10941 int mmu_reset_needed = 0;
10942 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
10943 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) &&
10944 !(sregs2->efer & EFER_LMA);
10947 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID)
10950 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected))
10953 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2,
10954 &mmu_reset_needed, !valid_pdptrs);
10958 if (valid_pdptrs) {
10959 for (i = 0; i < 4 ; i++)
10960 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]);
10962 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
10963 mmu_reset_needed = 1;
10964 vcpu->arch.pdptrs_from_userspace = true;
10966 if (mmu_reset_needed)
10967 kvm_mmu_reset_context(vcpu);
10971 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
10972 struct kvm_sregs *sregs)
10977 ret = __set_sregs(vcpu, sregs);
10982 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm)
10985 struct kvm_vcpu *vcpu;
10988 down_write(&kvm->arch.apicv_update_lock);
10990 kvm_for_each_vcpu(i, vcpu, kvm) {
10991 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) {
10996 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set);
10997 up_write(&kvm->arch.apicv_update_lock);
11000 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
11001 struct kvm_guest_debug *dbg)
11003 unsigned long rflags;
11006 if (vcpu->arch.guest_state_protected)
11011 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
11013 if (vcpu->arch.exception.pending)
11015 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
11016 kvm_queue_exception(vcpu, DB_VECTOR);
11018 kvm_queue_exception(vcpu, BP_VECTOR);
11022 * Read rflags as long as potentially injected trace flags are still
11025 rflags = kvm_get_rflags(vcpu);
11027 vcpu->guest_debug = dbg->control;
11028 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
11029 vcpu->guest_debug = 0;
11031 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
11032 for (i = 0; i < KVM_NR_DB_REGS; ++i)
11033 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
11034 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
11036 for (i = 0; i < KVM_NR_DB_REGS; i++)
11037 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
11039 kvm_update_dr7(vcpu);
11041 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
11042 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu);
11045 * Trigger an rflags update that will inject or remove the trace
11048 kvm_set_rflags(vcpu, rflags);
11050 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11052 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm);
11062 * Translate a guest virtual address to a guest physical address.
11064 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
11065 struct kvm_translation *tr)
11067 unsigned long vaddr = tr->linear_address;
11073 idx = srcu_read_lock(&vcpu->kvm->srcu);
11074 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
11075 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11076 tr->physical_address = gpa;
11077 tr->valid = gpa != UNMAPPED_GVA;
11085 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11087 struct fxregs_state *fxsave;
11089 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11094 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11095 memcpy(fpu->fpr, fxsave->st_space, 128);
11096 fpu->fcw = fxsave->cwd;
11097 fpu->fsw = fxsave->swd;
11098 fpu->ftwx = fxsave->twd;
11099 fpu->last_opcode = fxsave->fop;
11100 fpu->last_ip = fxsave->rip;
11101 fpu->last_dp = fxsave->rdp;
11102 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
11108 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11110 struct fxregs_state *fxsave;
11112 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11117 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11119 memcpy(fxsave->st_space, fpu->fpr, 128);
11120 fxsave->cwd = fpu->fcw;
11121 fxsave->swd = fpu->fsw;
11122 fxsave->twd = fpu->ftwx;
11123 fxsave->fop = fpu->last_opcode;
11124 fxsave->rip = fpu->last_ip;
11125 fxsave->rdp = fpu->last_dp;
11126 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
11132 static void store_regs(struct kvm_vcpu *vcpu)
11134 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
11136 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
11137 __get_regs(vcpu, &vcpu->run->s.regs.regs);
11139 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
11140 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
11142 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
11143 kvm_vcpu_ioctl_x86_get_vcpu_events(
11144 vcpu, &vcpu->run->s.regs.events);
11147 static int sync_regs(struct kvm_vcpu *vcpu)
11149 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
11150 __set_regs(vcpu, &vcpu->run->s.regs.regs);
11151 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
11153 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
11154 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
11156 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
11158 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
11159 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
11160 vcpu, &vcpu->run->s.regs.events))
11162 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
11168 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
11170 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
11171 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
11172 "guest TSC will not be reliable\n");
11177 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
11182 vcpu->arch.last_vmentry_cpu = -1;
11183 vcpu->arch.regs_avail = ~0;
11184 vcpu->arch.regs_dirty = ~0;
11186 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
11187 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11189 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
11191 r = kvm_mmu_create(vcpu);
11195 if (irqchip_in_kernel(vcpu->kvm)) {
11196 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
11198 goto fail_mmu_destroy;
11199 if (kvm_apicv_activated(vcpu->kvm))
11200 vcpu->arch.apicv_active = true;
11202 static_branch_inc(&kvm_has_noapic_vcpu);
11206 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
11208 goto fail_free_lapic;
11209 vcpu->arch.pio_data = page_address(page);
11211 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
11212 GFP_KERNEL_ACCOUNT);
11213 if (!vcpu->arch.mce_banks)
11214 goto fail_free_pio_data;
11215 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
11217 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
11218 GFP_KERNEL_ACCOUNT))
11219 goto fail_free_mce_banks;
11221 if (!alloc_emulate_ctxt(vcpu))
11222 goto free_wbinvd_dirty_mask;
11224 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) {
11225 pr_err("kvm: failed to allocate vcpu's fpu\n");
11226 goto free_emulate_ctxt;
11229 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
11230 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
11232 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
11234 kvm_async_pf_hash_reset(vcpu);
11235 kvm_pmu_init(vcpu);
11237 vcpu->arch.pending_external_vector = -1;
11238 vcpu->arch.preempted_in_kernel = false;
11240 #if IS_ENABLED(CONFIG_HYPERV)
11241 vcpu->arch.hv_root_tdp = INVALID_PAGE;
11244 r = static_call(kvm_x86_vcpu_create)(vcpu);
11246 goto free_guest_fpu;
11248 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
11249 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
11250 kvm_vcpu_mtrr_init(vcpu);
11252 kvm_set_tsc_khz(vcpu, max_tsc_khz);
11253 kvm_vcpu_reset(vcpu, false);
11254 kvm_init_mmu(vcpu);
11259 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11261 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11262 free_wbinvd_dirty_mask:
11263 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11264 fail_free_mce_banks:
11265 kfree(vcpu->arch.mce_banks);
11266 fail_free_pio_data:
11267 free_page((unsigned long)vcpu->arch.pio_data);
11269 kvm_free_lapic(vcpu);
11271 kvm_mmu_destroy(vcpu);
11275 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
11277 struct kvm *kvm = vcpu->kvm;
11279 if (mutex_lock_killable(&vcpu->mutex))
11282 kvm_synchronize_tsc(vcpu, 0);
11285 /* poll control enabled by default */
11286 vcpu->arch.msr_kvm_poll_control = 1;
11288 mutex_unlock(&vcpu->mutex);
11290 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
11291 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
11292 KVMCLOCK_SYNC_PERIOD);
11295 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
11299 kvmclock_reset(vcpu);
11301 static_call(kvm_x86_vcpu_free)(vcpu);
11303 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11304 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11305 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11307 kvm_hv_vcpu_uninit(vcpu);
11308 kvm_pmu_destroy(vcpu);
11309 kfree(vcpu->arch.mce_banks);
11310 kvm_free_lapic(vcpu);
11311 idx = srcu_read_lock(&vcpu->kvm->srcu);
11312 kvm_mmu_destroy(vcpu);
11313 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11314 free_page((unsigned long)vcpu->arch.pio_data);
11315 kvfree(vcpu->arch.cpuid_entries);
11316 if (!lapic_in_kernel(vcpu))
11317 static_branch_dec(&kvm_has_noapic_vcpu);
11320 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
11322 struct kvm_cpuid_entry2 *cpuid_0x1;
11323 unsigned long old_cr0 = kvm_read_cr0(vcpu);
11324 unsigned long new_cr0;
11327 * Several of the "set" flows, e.g. ->set_cr0(), read other registers
11328 * to handle side effects. RESET emulation hits those flows and relies
11329 * on emulated/virtualized registers, including those that are loaded
11330 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel
11331 * to detect improper or missing initialization.
11333 WARN_ON_ONCE(!init_event &&
11334 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu)));
11336 kvm_lapic_reset(vcpu, init_event);
11338 vcpu->arch.hflags = 0;
11340 vcpu->arch.smi_pending = 0;
11341 vcpu->arch.smi_count = 0;
11342 atomic_set(&vcpu->arch.nmi_queued, 0);
11343 vcpu->arch.nmi_pending = 0;
11344 vcpu->arch.nmi_injected = false;
11345 kvm_clear_interrupt_queue(vcpu);
11346 kvm_clear_exception_queue(vcpu);
11348 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
11349 kvm_update_dr0123(vcpu);
11350 vcpu->arch.dr6 = DR6_ACTIVE_LOW;
11351 vcpu->arch.dr7 = DR7_FIXED_1;
11352 kvm_update_dr7(vcpu);
11354 vcpu->arch.cr2 = 0;
11356 kvm_make_request(KVM_REQ_EVENT, vcpu);
11357 vcpu->arch.apf.msr_en_val = 0;
11358 vcpu->arch.apf.msr_int_val = 0;
11359 vcpu->arch.st.msr_val = 0;
11361 kvmclock_reset(vcpu);
11363 kvm_clear_async_pf_completion_queue(vcpu);
11364 kvm_async_pf_hash_reset(vcpu);
11365 vcpu->arch.apf.halted = false;
11367 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) {
11368 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate;
11371 * To avoid have the INIT path from kvm_apic_has_events() that be
11372 * called with loaded FPU and does not let userspace fix the state.
11375 kvm_put_guest_fpu(vcpu);
11377 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS);
11378 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR);
11381 kvm_load_guest_fpu(vcpu);
11385 kvm_pmu_reset(vcpu);
11386 vcpu->arch.smbase = 0x30000;
11388 vcpu->arch.msr_misc_features_enables = 0;
11390 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP);
11391 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true);
11394 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */
11395 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
11396 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP);
11399 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon)
11400 * if no CPUID match is found. Note, it's impossible to get a match at
11401 * RESET since KVM emulates RESET before exposing the vCPU to userspace,
11402 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry
11403 * on RESET. But, go through the motions in case that's ever remedied.
11405 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1, 0);
11406 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600);
11408 static_call(kvm_x86_vcpu_reset)(vcpu, init_event);
11410 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
11411 kvm_rip_write(vcpu, 0xfff0);
11413 vcpu->arch.cr3 = 0;
11414 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11417 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions
11418 * of Intel's SDM list CD/NW as being set on INIT, but they contradict
11419 * (or qualify) that with a footnote stating that CD/NW are preserved.
11421 new_cr0 = X86_CR0_ET;
11423 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD));
11425 new_cr0 |= X86_CR0_NW | X86_CR0_CD;
11427 static_call(kvm_x86_set_cr0)(vcpu, new_cr0);
11428 static_call(kvm_x86_set_cr4)(vcpu, 0);
11429 static_call(kvm_x86_set_efer)(vcpu, 0);
11430 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11433 * On the standard CR0/CR4/EFER modification paths, there are several
11434 * complex conditions determining whether the MMU has to be reset and/or
11435 * which PCIDs have to be flushed. However, CR0.WP and the paging-related
11436 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush
11437 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as
11438 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here.
11440 if (old_cr0 & X86_CR0_PG) {
11441 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11442 kvm_mmu_reset_context(vcpu);
11446 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's
11447 * APM states the TLBs are untouched by INIT, but it also states that
11448 * the TLBs are flushed on "External initialization of the processor."
11449 * Flush the guest TLB regardless of vendor, there is no meaningful
11450 * benefit in relying on the guest to flush the TLB immediately after
11451 * INIT. A spurious TLB flush is benign and likely negligible from a
11452 * performance perspective.
11455 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11457 EXPORT_SYMBOL_GPL(kvm_vcpu_reset);
11459 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
11461 struct kvm_segment cs;
11463 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
11464 cs.selector = vector << 8;
11465 cs.base = vector << 12;
11466 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
11467 kvm_rip_write(vcpu, 0);
11469 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
11471 int kvm_arch_hardware_enable(void)
11474 struct kvm_vcpu *vcpu;
11479 bool stable, backwards_tsc = false;
11481 kvm_user_return_msr_cpu_online();
11482 ret = static_call(kvm_x86_hardware_enable)();
11486 local_tsc = rdtsc();
11487 stable = !kvm_check_tsc_unstable();
11488 list_for_each_entry(kvm, &vm_list, vm_list) {
11489 kvm_for_each_vcpu(i, vcpu, kvm) {
11490 if (!stable && vcpu->cpu == smp_processor_id())
11491 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
11492 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
11493 backwards_tsc = true;
11494 if (vcpu->arch.last_host_tsc > max_tsc)
11495 max_tsc = vcpu->arch.last_host_tsc;
11501 * Sometimes, even reliable TSCs go backwards. This happens on
11502 * platforms that reset TSC during suspend or hibernate actions, but
11503 * maintain synchronization. We must compensate. Fortunately, we can
11504 * detect that condition here, which happens early in CPU bringup,
11505 * before any KVM threads can be running. Unfortunately, we can't
11506 * bring the TSCs fully up to date with real time, as we aren't yet far
11507 * enough into CPU bringup that we know how much real time has actually
11508 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
11509 * variables that haven't been updated yet.
11511 * So we simply find the maximum observed TSC above, then record the
11512 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
11513 * the adjustment will be applied. Note that we accumulate
11514 * adjustments, in case multiple suspend cycles happen before some VCPU
11515 * gets a chance to run again. In the event that no KVM threads get a
11516 * chance to run, we will miss the entire elapsed period, as we'll have
11517 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
11518 * loose cycle time. This isn't too big a deal, since the loss will be
11519 * uniform across all VCPUs (not to mention the scenario is extremely
11520 * unlikely). It is possible that a second hibernate recovery happens
11521 * much faster than a first, causing the observed TSC here to be
11522 * smaller; this would require additional padding adjustment, which is
11523 * why we set last_host_tsc to the local tsc observed here.
11525 * N.B. - this code below runs only on platforms with reliable TSC,
11526 * as that is the only way backwards_tsc is set above. Also note
11527 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
11528 * have the same delta_cyc adjustment applied if backwards_tsc
11529 * is detected. Note further, this adjustment is only done once,
11530 * as we reset last_host_tsc on all VCPUs to stop this from being
11531 * called multiple times (one for each physical CPU bringup).
11533 * Platforms with unreliable TSCs don't have to deal with this, they
11534 * will be compensated by the logic in vcpu_load, which sets the TSC to
11535 * catchup mode. This will catchup all VCPUs to real time, but cannot
11536 * guarantee that they stay in perfect synchronization.
11538 if (backwards_tsc) {
11539 u64 delta_cyc = max_tsc - local_tsc;
11540 list_for_each_entry(kvm, &vm_list, vm_list) {
11541 kvm->arch.backwards_tsc_observed = true;
11542 kvm_for_each_vcpu(i, vcpu, kvm) {
11543 vcpu->arch.tsc_offset_adjustment += delta_cyc;
11544 vcpu->arch.last_host_tsc = local_tsc;
11545 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
11549 * We have to disable TSC offset matching.. if you were
11550 * booting a VM while issuing an S4 host suspend....
11551 * you may have some problem. Solving this issue is
11552 * left as an exercise to the reader.
11554 kvm->arch.last_tsc_nsec = 0;
11555 kvm->arch.last_tsc_write = 0;
11562 void kvm_arch_hardware_disable(void)
11564 static_call(kvm_x86_hardware_disable)();
11565 drop_user_return_notifiers();
11568 int kvm_arch_hardware_setup(void *opaque)
11570 struct kvm_x86_init_ops *ops = opaque;
11573 rdmsrl_safe(MSR_EFER, &host_efer);
11575 if (boot_cpu_has(X86_FEATURE_XSAVES))
11576 rdmsrl(MSR_IA32_XSS, host_xss);
11578 r = ops->hardware_setup();
11582 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
11583 kvm_ops_static_call_update();
11585 kvm_register_perf_callbacks(ops->handle_intel_pt_intr);
11587 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
11590 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
11591 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
11592 #undef __kvm_cpu_cap_has
11594 if (kvm_has_tsc_control) {
11596 * Make sure the user can only configure tsc_khz values that
11597 * fit into a signed integer.
11598 * A min value is not calculated because it will always
11599 * be 1 on all machines.
11601 u64 max = min(0x7fffffffULL,
11602 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
11603 kvm_max_guest_tsc_khz = max;
11605 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
11606 kvm_init_msr_list();
11610 void kvm_arch_hardware_unsetup(void)
11612 kvm_unregister_perf_callbacks();
11614 static_call(kvm_x86_hardware_unsetup)();
11617 int kvm_arch_check_processor_compat(void *opaque)
11619 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
11620 struct kvm_x86_init_ops *ops = opaque;
11622 WARN_ON(!irqs_disabled());
11624 if (__cr4_reserved_bits(cpu_has, c) !=
11625 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
11628 return ops->check_processor_compatibility();
11631 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
11633 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
11635 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
11637 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
11639 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
11642 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
11643 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu);
11645 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
11647 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
11649 vcpu->arch.l1tf_flush_l1d = true;
11650 if (pmu->version && unlikely(pmu->event_count)) {
11651 pmu->need_cleanup = true;
11652 kvm_make_request(KVM_REQ_PMU, vcpu);
11654 static_call(kvm_x86_sched_in)(vcpu, cpu);
11657 void kvm_arch_free_vm(struct kvm *kvm)
11659 kfree(to_kvm_hv(kvm)->hv_pa_pg);
11660 __kvm_arch_free_vm(kvm);
11664 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
11667 unsigned long flags;
11672 ret = kvm_page_track_init(kvm);
11676 ret = kvm_mmu_init_vm(kvm);
11678 goto out_page_track;
11680 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
11681 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
11682 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
11684 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
11685 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
11686 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
11687 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
11688 &kvm->arch.irq_sources_bitmap);
11690 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
11691 mutex_init(&kvm->arch.apic_map_lock);
11692 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock);
11693 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
11695 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
11696 pvclock_update_vm_gtod_copy(kvm);
11697 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
11699 kvm->arch.guest_can_read_msr_platform_info = true;
11700 kvm->arch.enable_pmu = enable_pmu;
11702 #if IS_ENABLED(CONFIG_HYPERV)
11703 spin_lock_init(&kvm->arch.hv_root_tdp_lock);
11704 kvm->arch.hv_root_tdp = INVALID_PAGE;
11707 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
11708 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
11710 kvm_apicv_init(kvm);
11711 kvm_hv_init_vm(kvm);
11712 kvm_xen_init_vm(kvm);
11714 return static_call(kvm_x86_vm_init)(kvm);
11717 kvm_page_track_cleanup(kvm);
11722 int kvm_arch_post_init_vm(struct kvm *kvm)
11724 return kvm_mmu_post_init_vm(kvm);
11727 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
11730 kvm_mmu_unload(vcpu);
11734 static void kvm_free_vcpus(struct kvm *kvm)
11737 struct kvm_vcpu *vcpu;
11740 * Unpin any mmu pages first.
11742 kvm_for_each_vcpu(i, vcpu, kvm) {
11743 kvm_clear_async_pf_completion_queue(vcpu);
11744 kvm_unload_vcpu_mmu(vcpu);
11747 kvm_destroy_vcpus(kvm);
11750 void kvm_arch_sync_events(struct kvm *kvm)
11752 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
11753 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
11758 * __x86_set_memory_region: Setup KVM internal memory slot
11760 * @kvm: the kvm pointer to the VM.
11761 * @id: the slot ID to setup.
11762 * @gpa: the GPA to install the slot (unused when @size == 0).
11763 * @size: the size of the slot. Set to zero to uninstall a slot.
11765 * This function helps to setup a KVM internal memory slot. Specify
11766 * @size > 0 to install a new slot, while @size == 0 to uninstall a
11767 * slot. The return code can be one of the following:
11769 * HVA: on success (uninstall will return a bogus HVA)
11772 * The caller should always use IS_ERR() to check the return value
11773 * before use. Note, the KVM internal memory slots are guaranteed to
11774 * remain valid and unchanged until the VM is destroyed, i.e., the
11775 * GPA->HVA translation will not change. However, the HVA is a user
11776 * address, i.e. its accessibility is not guaranteed, and must be
11777 * accessed via __copy_{to,from}_user().
11779 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
11783 unsigned long hva, old_npages;
11784 struct kvm_memslots *slots = kvm_memslots(kvm);
11785 struct kvm_memory_slot *slot;
11787 /* Called with kvm->slots_lock held. */
11788 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
11789 return ERR_PTR_USR(-EINVAL);
11791 slot = id_to_memslot(slots, id);
11793 if (slot && slot->npages)
11794 return ERR_PTR_USR(-EEXIST);
11797 * MAP_SHARED to prevent internal slot pages from being moved
11800 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
11801 MAP_SHARED | MAP_ANONYMOUS, 0);
11802 if (IS_ERR((void *)hva))
11803 return (void __user *)hva;
11805 if (!slot || !slot->npages)
11808 old_npages = slot->npages;
11809 hva = slot->userspace_addr;
11812 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
11813 struct kvm_userspace_memory_region m;
11815 m.slot = id | (i << 16);
11817 m.guest_phys_addr = gpa;
11818 m.userspace_addr = hva;
11819 m.memory_size = size;
11820 r = __kvm_set_memory_region(kvm, &m);
11822 return ERR_PTR_USR(r);
11826 vm_munmap(hva, old_npages * PAGE_SIZE);
11828 return (void __user *)hva;
11830 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
11832 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
11834 kvm_mmu_pre_destroy_vm(kvm);
11837 void kvm_arch_destroy_vm(struct kvm *kvm)
11839 if (current->mm == kvm->mm) {
11841 * Free memory regions allocated on behalf of userspace,
11842 * unless the the memory map has changed due to process exit
11845 mutex_lock(&kvm->slots_lock);
11846 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
11848 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
11850 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
11851 mutex_unlock(&kvm->slots_lock);
11853 static_call_cond(kvm_x86_vm_destroy)(kvm);
11854 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1));
11855 kvm_pic_destroy(kvm);
11856 kvm_ioapic_destroy(kvm);
11857 kvm_free_vcpus(kvm);
11858 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
11859 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
11860 kvm_mmu_uninit_vm(kvm);
11861 kvm_page_track_cleanup(kvm);
11862 kvm_xen_destroy_vm(kvm);
11863 kvm_hv_destroy_vm(kvm);
11866 static void memslot_rmap_free(struct kvm_memory_slot *slot)
11870 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
11871 kvfree(slot->arch.rmap[i]);
11872 slot->arch.rmap[i] = NULL;
11876 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
11880 memslot_rmap_free(slot);
11882 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
11883 kvfree(slot->arch.lpage_info[i - 1]);
11884 slot->arch.lpage_info[i - 1] = NULL;
11887 kvm_page_track_free_memslot(slot);
11890 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages)
11892 const int sz = sizeof(*slot->arch.rmap[0]);
11895 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
11897 int lpages = __kvm_mmu_slot_lpages(slot, npages, level);
11899 if (slot->arch.rmap[i])
11902 slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT);
11903 if (!slot->arch.rmap[i]) {
11904 memslot_rmap_free(slot);
11912 static int kvm_alloc_memslot_metadata(struct kvm *kvm,
11913 struct kvm_memory_slot *slot)
11915 unsigned long npages = slot->npages;
11919 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
11920 * old arrays will be freed by __kvm_set_memory_region() if installing
11921 * the new memslot is successful.
11923 memset(&slot->arch, 0, sizeof(slot->arch));
11925 if (kvm_memslots_have_rmaps(kvm)) {
11926 r = memslot_rmap_alloc(slot, npages);
11931 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
11932 struct kvm_lpage_info *linfo;
11933 unsigned long ugfn;
11937 lpages = __kvm_mmu_slot_lpages(slot, npages, level);
11939 linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
11943 slot->arch.lpage_info[i - 1] = linfo;
11945 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
11946 linfo[0].disallow_lpage = 1;
11947 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
11948 linfo[lpages - 1].disallow_lpage = 1;
11949 ugfn = slot->userspace_addr >> PAGE_SHIFT;
11951 * If the gfn and userspace address are not aligned wrt each
11952 * other, disable large page support for this slot.
11954 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
11957 for (j = 0; j < lpages; ++j)
11958 linfo[j].disallow_lpage = 1;
11962 if (kvm_page_track_create_memslot(kvm, slot, npages))
11968 memslot_rmap_free(slot);
11970 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
11971 kvfree(slot->arch.lpage_info[i - 1]);
11972 slot->arch.lpage_info[i - 1] = NULL;
11977 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
11979 struct kvm_vcpu *vcpu;
11983 * memslots->generation has been incremented.
11984 * mmio generation may have reached its maximum value.
11986 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
11988 /* Force re-initialization of steal_time cache */
11989 kvm_for_each_vcpu(i, vcpu, kvm)
11990 kvm_vcpu_kick(vcpu);
11993 int kvm_arch_prepare_memory_region(struct kvm *kvm,
11994 const struct kvm_memory_slot *old,
11995 struct kvm_memory_slot *new,
11996 enum kvm_mr_change change)
11998 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
11999 return kvm_alloc_memslot_metadata(kvm, new);
12001 if (change == KVM_MR_FLAGS_ONLY)
12002 memcpy(&new->arch, &old->arch, sizeof(old->arch));
12003 else if (WARN_ON_ONCE(change != KVM_MR_DELETE))
12010 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable)
12012 struct kvm_arch *ka = &kvm->arch;
12014 if (!kvm_x86_ops.cpu_dirty_log_size)
12017 if ((enable && ++ka->cpu_dirty_logging_count == 1) ||
12018 (!enable && --ka->cpu_dirty_logging_count == 0))
12019 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING);
12021 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0);
12024 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
12025 struct kvm_memory_slot *old,
12026 const struct kvm_memory_slot *new,
12027 enum kvm_mr_change change)
12029 u32 old_flags = old ? old->flags : 0;
12030 u32 new_flags = new ? new->flags : 0;
12031 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES;
12034 * Update CPU dirty logging if dirty logging is being toggled. This
12035 * applies to all operations.
12037 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)
12038 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages);
12041 * Nothing more to do for RO slots (which can't be dirtied and can't be
12042 * made writable) or CREATE/MOVE/DELETE of a slot.
12044 * For a memslot with dirty logging disabled:
12045 * CREATE: No dirty mappings will already exist.
12046 * MOVE/DELETE: The old mappings will already have been cleaned up by
12047 * kvm_arch_flush_shadow_memslot()
12049 * For a memslot with dirty logging enabled:
12050 * CREATE: No shadow pages exist, thus nothing to write-protect
12051 * and no dirty bits to clear.
12052 * MOVE/DELETE: The old mappings will already have been cleaned up by
12053 * kvm_arch_flush_shadow_memslot().
12055 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY))
12059 * READONLY and non-flags changes were filtered out above, and the only
12060 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty
12061 * logging isn't being toggled on or off.
12063 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)))
12066 if (!log_dirty_pages) {
12068 * Dirty logging tracks sptes in 4k granularity, meaning that
12069 * large sptes have to be split. If live migration succeeds,
12070 * the guest in the source machine will be destroyed and large
12071 * sptes will be created in the destination. However, if the
12072 * guest continues to run in the source machine (for example if
12073 * live migration fails), small sptes will remain around and
12074 * cause bad performance.
12076 * Scan sptes if dirty logging has been stopped, dropping those
12077 * which can be collapsed into a single large-page spte. Later
12078 * page faults will create the large-page sptes.
12080 kvm_mmu_zap_collapsible_sptes(kvm, new);
12083 * Initially-all-set does not require write protecting any page,
12084 * because they're all assumed to be dirty.
12086 if (kvm_dirty_log_manual_protect_and_init_set(kvm))
12089 if (READ_ONCE(eager_page_split))
12090 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K);
12092 if (kvm_x86_ops.cpu_dirty_log_size) {
12093 kvm_mmu_slot_leaf_clear_dirty(kvm, new);
12094 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M);
12096 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K);
12101 void kvm_arch_commit_memory_region(struct kvm *kvm,
12102 struct kvm_memory_slot *old,
12103 const struct kvm_memory_slot *new,
12104 enum kvm_mr_change change)
12106 if (!kvm->arch.n_requested_mmu_pages &&
12107 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) {
12108 unsigned long nr_mmu_pages;
12110 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO;
12111 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
12112 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
12115 kvm_mmu_slot_apply_flags(kvm, old, new, change);
12117 /* Free the arrays associated with the old memslot. */
12118 if (change == KVM_MR_MOVE)
12119 kvm_arch_free_memslot(kvm, old);
12122 void kvm_arch_flush_shadow_all(struct kvm *kvm)
12124 kvm_mmu_zap_all(kvm);
12127 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
12128 struct kvm_memory_slot *slot)
12130 kvm_page_track_flush_slot(kvm, slot);
12133 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
12135 return (is_guest_mode(vcpu) &&
12136 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu));
12139 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
12141 if (!list_empty_careful(&vcpu->async_pf.done))
12144 if (kvm_apic_has_events(vcpu))
12147 if (vcpu->arch.pv.pv_unhalted)
12150 if (vcpu->arch.exception.pending)
12153 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12154 (vcpu->arch.nmi_pending &&
12155 static_call(kvm_x86_nmi_allowed)(vcpu, false)))
12158 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
12159 (vcpu->arch.smi_pending &&
12160 static_call(kvm_x86_smi_allowed)(vcpu, false)))
12163 if (kvm_arch_interrupt_allowed(vcpu) &&
12164 (kvm_cpu_has_interrupt(vcpu) ||
12165 kvm_guest_apic_has_interrupt(vcpu)))
12168 if (kvm_hv_has_stimer_pending(vcpu))
12171 if (is_guest_mode(vcpu) &&
12172 kvm_x86_ops.nested_ops->hv_timer_pending &&
12173 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
12179 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
12181 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
12184 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu)
12186 if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
12192 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
12194 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
12197 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12198 kvm_test_request(KVM_REQ_SMI, vcpu) ||
12199 kvm_test_request(KVM_REQ_EVENT, vcpu))
12202 return kvm_arch_dy_has_pending_interrupt(vcpu);
12205 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
12207 if (vcpu->arch.guest_state_protected)
12210 return vcpu->arch.preempted_in_kernel;
12213 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu)
12215 return kvm_rip_read(vcpu);
12218 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
12220 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
12223 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
12225 return static_call(kvm_x86_interrupt_allowed)(vcpu, false);
12228 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
12230 /* Can't read the RIP when guest state is protected, just return 0 */
12231 if (vcpu->arch.guest_state_protected)
12234 if (is_64_bit_mode(vcpu))
12235 return kvm_rip_read(vcpu);
12236 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
12237 kvm_rip_read(vcpu));
12239 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
12241 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
12243 return kvm_get_linear_rip(vcpu) == linear_rip;
12245 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
12247 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
12249 unsigned long rflags;
12251 rflags = static_call(kvm_x86_get_rflags)(vcpu);
12252 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
12253 rflags &= ~X86_EFLAGS_TF;
12256 EXPORT_SYMBOL_GPL(kvm_get_rflags);
12258 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12260 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
12261 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
12262 rflags |= X86_EFLAGS_TF;
12263 static_call(kvm_x86_set_rflags)(vcpu, rflags);
12266 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12268 __kvm_set_rflags(vcpu, rflags);
12269 kvm_make_request(KVM_REQ_EVENT, vcpu);
12271 EXPORT_SYMBOL_GPL(kvm_set_rflags);
12273 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
12277 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
12281 r = kvm_mmu_reload(vcpu);
12285 if (!vcpu->arch.mmu->direct_map &&
12286 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
12289 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
12292 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
12294 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
12296 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
12299 static inline u32 kvm_async_pf_next_probe(u32 key)
12301 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
12304 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12306 u32 key = kvm_async_pf_hash_fn(gfn);
12308 while (vcpu->arch.apf.gfns[key] != ~0)
12309 key = kvm_async_pf_next_probe(key);
12311 vcpu->arch.apf.gfns[key] = gfn;
12314 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
12317 u32 key = kvm_async_pf_hash_fn(gfn);
12319 for (i = 0; i < ASYNC_PF_PER_VCPU &&
12320 (vcpu->arch.apf.gfns[key] != gfn &&
12321 vcpu->arch.apf.gfns[key] != ~0); i++)
12322 key = kvm_async_pf_next_probe(key);
12327 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12329 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
12332 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12336 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
12338 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
12342 vcpu->arch.apf.gfns[i] = ~0;
12344 j = kvm_async_pf_next_probe(j);
12345 if (vcpu->arch.apf.gfns[j] == ~0)
12347 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
12349 * k lies cyclically in ]i,j]
12351 * |....j i.k.| or |.k..j i...|
12353 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
12354 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
12359 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
12361 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
12363 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
12367 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
12369 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
12371 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
12372 &token, offset, sizeof(token));
12375 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
12377 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
12380 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
12381 &val, offset, sizeof(val)))
12387 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
12390 if (!kvm_pv_async_pf_enabled(vcpu))
12393 if (vcpu->arch.apf.send_user_only &&
12394 static_call(kvm_x86_get_cpl)(vcpu) == 0)
12397 if (is_guest_mode(vcpu)) {
12399 * L1 needs to opt into the special #PF vmexits that are
12400 * used to deliver async page faults.
12402 return vcpu->arch.apf.delivery_as_pf_vmexit;
12405 * Play it safe in case the guest temporarily disables paging.
12406 * The real mode IDT in particular is unlikely to have a #PF
12409 return is_paging(vcpu);
12413 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
12415 if (unlikely(!lapic_in_kernel(vcpu) ||
12416 kvm_event_needs_reinjection(vcpu) ||
12417 vcpu->arch.exception.pending))
12420 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
12424 * If interrupts are off we cannot even use an artificial
12427 return kvm_arch_interrupt_allowed(vcpu);
12430 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
12431 struct kvm_async_pf *work)
12433 struct x86_exception fault;
12435 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
12436 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
12438 if (kvm_can_deliver_async_pf(vcpu) &&
12439 !apf_put_user_notpresent(vcpu)) {
12440 fault.vector = PF_VECTOR;
12441 fault.error_code_valid = true;
12442 fault.error_code = 0;
12443 fault.nested_page_fault = false;
12444 fault.address = work->arch.token;
12445 fault.async_page_fault = true;
12446 kvm_inject_page_fault(vcpu, &fault);
12450 * It is not possible to deliver a paravirtualized asynchronous
12451 * page fault, but putting the guest in an artificial halt state
12452 * can be beneficial nevertheless: if an interrupt arrives, we
12453 * can deliver it timely and perhaps the guest will schedule
12454 * another process. When the instruction that triggered a page
12455 * fault is retried, hopefully the page will be ready in the host.
12457 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
12462 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
12463 struct kvm_async_pf *work)
12465 struct kvm_lapic_irq irq = {
12466 .delivery_mode = APIC_DM_FIXED,
12467 .vector = vcpu->arch.apf.vec
12470 if (work->wakeup_all)
12471 work->arch.token = ~0; /* broadcast wakeup */
12473 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
12474 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
12476 if ((work->wakeup_all || work->notpresent_injected) &&
12477 kvm_pv_async_pf_enabled(vcpu) &&
12478 !apf_put_user_ready(vcpu, work->arch.token)) {
12479 vcpu->arch.apf.pageready_pending = true;
12480 kvm_apic_set_irq(vcpu, &irq, NULL);
12483 vcpu->arch.apf.halted = false;
12484 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
12487 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
12489 kvm_make_request(KVM_REQ_APF_READY, vcpu);
12490 if (!vcpu->arch.apf.pageready_pending)
12491 kvm_vcpu_kick(vcpu);
12494 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
12496 if (!kvm_pv_async_pf_enabled(vcpu))
12499 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu);
12502 void kvm_arch_start_assignment(struct kvm *kvm)
12504 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1)
12505 static_call_cond(kvm_x86_pi_start_assignment)(kvm);
12507 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
12509 void kvm_arch_end_assignment(struct kvm *kvm)
12511 atomic_dec(&kvm->arch.assigned_device_count);
12513 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
12515 bool kvm_arch_has_assigned_device(struct kvm *kvm)
12517 return atomic_read(&kvm->arch.assigned_device_count);
12519 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
12521 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
12523 atomic_inc(&kvm->arch.noncoherent_dma_count);
12525 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
12527 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
12529 atomic_dec(&kvm->arch.noncoherent_dma_count);
12531 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
12533 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
12535 return atomic_read(&kvm->arch.noncoherent_dma_count);
12537 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
12539 bool kvm_arch_has_irq_bypass(void)
12544 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
12545 struct irq_bypass_producer *prod)
12547 struct kvm_kernel_irqfd *irqfd =
12548 container_of(cons, struct kvm_kernel_irqfd, consumer);
12551 irqfd->producer = prod;
12552 kvm_arch_start_assignment(irqfd->kvm);
12553 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm,
12554 prod->irq, irqfd->gsi, 1);
12557 kvm_arch_end_assignment(irqfd->kvm);
12562 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
12563 struct irq_bypass_producer *prod)
12566 struct kvm_kernel_irqfd *irqfd =
12567 container_of(cons, struct kvm_kernel_irqfd, consumer);
12569 WARN_ON(irqfd->producer != prod);
12570 irqfd->producer = NULL;
12573 * When producer of consumer is unregistered, we change back to
12574 * remapped mode, so we can re-use the current implementation
12575 * when the irq is masked/disabled or the consumer side (KVM
12576 * int this case doesn't want to receive the interrupts.
12578 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0);
12580 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
12581 " fails: %d\n", irqfd->consumer.token, ret);
12583 kvm_arch_end_assignment(irqfd->kvm);
12586 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
12587 uint32_t guest_irq, bool set)
12589 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set);
12592 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old,
12593 struct kvm_kernel_irq_routing_entry *new)
12595 if (new->type != KVM_IRQ_ROUTING_MSI)
12598 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi));
12601 bool kvm_vector_hashing_enabled(void)
12603 return vector_hashing;
12606 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
12608 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
12610 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
12613 int kvm_spec_ctrl_test_value(u64 value)
12616 * test that setting IA32_SPEC_CTRL to given value
12617 * is allowed by the host processor
12621 unsigned long flags;
12624 local_irq_save(flags);
12626 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
12628 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
12631 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
12633 local_irq_restore(flags);
12637 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
12639 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
12641 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
12642 struct x86_exception fault;
12643 u64 access = error_code &
12644 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
12646 if (!(error_code & PFERR_PRESENT_MASK) ||
12647 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != UNMAPPED_GVA) {
12649 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
12650 * tables probably do not match the TLB. Just proceed
12651 * with the error code that the processor gave.
12653 fault.vector = PF_VECTOR;
12654 fault.error_code_valid = true;
12655 fault.error_code = error_code;
12656 fault.nested_page_fault = false;
12657 fault.address = gva;
12659 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
12661 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
12664 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
12665 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
12666 * indicates whether exit to userspace is needed.
12668 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
12669 struct x86_exception *e)
12671 if (r == X86EMUL_PROPAGATE_FAULT) {
12672 kvm_inject_emulated_page_fault(vcpu, e);
12677 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
12678 * while handling a VMX instruction KVM could've handled the request
12679 * correctly by exiting to userspace and performing I/O but there
12680 * doesn't seem to be a real use-case behind such requests, just return
12681 * KVM_EXIT_INTERNAL_ERROR for now.
12683 kvm_prepare_emulation_failure_exit(vcpu);
12687 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
12689 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
12692 struct x86_exception e;
12699 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
12700 if (r != X86EMUL_CONTINUE)
12701 return kvm_handle_memory_failure(vcpu, r, &e);
12703 if (operand.pcid >> 12 != 0) {
12704 kvm_inject_gp(vcpu, 0);
12708 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
12711 case INVPCID_TYPE_INDIV_ADDR:
12712 if ((!pcid_enabled && (operand.pcid != 0)) ||
12713 is_noncanonical_address(operand.gla, vcpu)) {
12714 kvm_inject_gp(vcpu, 0);
12717 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
12718 return kvm_skip_emulated_instruction(vcpu);
12720 case INVPCID_TYPE_SINGLE_CTXT:
12721 if (!pcid_enabled && (operand.pcid != 0)) {
12722 kvm_inject_gp(vcpu, 0);
12726 kvm_invalidate_pcid(vcpu, operand.pcid);
12727 return kvm_skip_emulated_instruction(vcpu);
12729 case INVPCID_TYPE_ALL_NON_GLOBAL:
12731 * Currently, KVM doesn't mark global entries in the shadow
12732 * page tables, so a non-global flush just degenerates to a
12733 * global flush. If needed, we could optimize this later by
12734 * keeping track of global entries in shadow page tables.
12738 case INVPCID_TYPE_ALL_INCL_GLOBAL:
12739 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12740 return kvm_skip_emulated_instruction(vcpu);
12743 kvm_inject_gp(vcpu, 0);
12747 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
12749 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
12751 struct kvm_run *run = vcpu->run;
12752 struct kvm_mmio_fragment *frag;
12755 BUG_ON(!vcpu->mmio_needed);
12757 /* Complete previous fragment */
12758 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
12759 len = min(8u, frag->len);
12760 if (!vcpu->mmio_is_write)
12761 memcpy(frag->data, run->mmio.data, len);
12763 if (frag->len <= 8) {
12764 /* Switch to the next fragment. */
12766 vcpu->mmio_cur_fragment++;
12768 /* Go forward to the next mmio piece. */
12774 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
12775 vcpu->mmio_needed = 0;
12777 // VMG change, at this point, we're always done
12778 // RIP has already been advanced
12782 // More MMIO is needed
12783 run->mmio.phys_addr = frag->gpa;
12784 run->mmio.len = min(8u, frag->len);
12785 run->mmio.is_write = vcpu->mmio_is_write;
12786 if (run->mmio.is_write)
12787 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
12788 run->exit_reason = KVM_EXIT_MMIO;
12790 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
12795 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
12799 struct kvm_mmio_fragment *frag;
12804 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
12805 if (handled == bytes)
12812 /*TODO: Check if need to increment number of frags */
12813 frag = vcpu->mmio_fragments;
12814 vcpu->mmio_nr_fragments = 1;
12819 vcpu->mmio_needed = 1;
12820 vcpu->mmio_cur_fragment = 0;
12822 vcpu->run->mmio.phys_addr = gpa;
12823 vcpu->run->mmio.len = min(8u, frag->len);
12824 vcpu->run->mmio.is_write = 1;
12825 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
12826 vcpu->run->exit_reason = KVM_EXIT_MMIO;
12828 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
12832 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
12834 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
12838 struct kvm_mmio_fragment *frag;
12843 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
12844 if (handled == bytes)
12851 /*TODO: Check if need to increment number of frags */
12852 frag = vcpu->mmio_fragments;
12853 vcpu->mmio_nr_fragments = 1;
12858 vcpu->mmio_needed = 1;
12859 vcpu->mmio_cur_fragment = 0;
12861 vcpu->run->mmio.phys_addr = gpa;
12862 vcpu->run->mmio.len = min(8u, frag->len);
12863 vcpu->run->mmio.is_write = 0;
12864 vcpu->run->exit_reason = KVM_EXIT_MMIO;
12866 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
12870 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
12872 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
12873 unsigned int port);
12875 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu)
12877 int size = vcpu->arch.pio.size;
12878 int port = vcpu->arch.pio.port;
12880 vcpu->arch.pio.count = 0;
12881 if (vcpu->arch.sev_pio_count)
12882 return kvm_sev_es_outs(vcpu, size, port);
12886 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
12890 unsigned int count =
12891 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
12892 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count);
12894 /* memcpy done already by emulator_pio_out. */
12895 vcpu->arch.sev_pio_count -= count;
12896 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size;
12900 /* Emulation done by the kernel. */
12901 if (!vcpu->arch.sev_pio_count)
12905 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs;
12909 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
12910 unsigned int port);
12912 static void advance_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
12914 unsigned count = vcpu->arch.pio.count;
12915 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data);
12916 vcpu->arch.sev_pio_count -= count;
12917 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size;
12920 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
12922 int size = vcpu->arch.pio.size;
12923 int port = vcpu->arch.pio.port;
12925 advance_sev_es_emulated_ins(vcpu);
12926 if (vcpu->arch.sev_pio_count)
12927 return kvm_sev_es_ins(vcpu, size, port);
12931 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
12935 unsigned int count =
12936 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
12937 if (!__emulator_pio_in(vcpu, size, port, count))
12940 /* Emulation done by the kernel. */
12941 advance_sev_es_emulated_ins(vcpu);
12942 if (!vcpu->arch.sev_pio_count)
12946 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
12950 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
12951 unsigned int port, void *data, unsigned int count,
12954 vcpu->arch.sev_pio_data = data;
12955 vcpu->arch.sev_pio_count = count;
12956 return in ? kvm_sev_es_ins(vcpu, size, port)
12957 : kvm_sev_es_outs(vcpu, size, port);
12959 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
12961 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
12962 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
12963 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
12964 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
12965 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
12966 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
12967 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
12968 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
12969 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
12970 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
12971 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
12972 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
12973 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
12974 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
12975 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
12976 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
12977 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
12978 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
12979 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
12980 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
12981 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
12982 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
12983 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq);
12984 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
12985 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
12986 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
12987 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
12989 static int __init kvm_x86_init(void)
12991 kvm_mmu_x86_module_init();
12994 module_init(kvm_x86_init);
12996 static void __exit kvm_x86_exit(void)
12999 * If module_init() is implemented, module_exit() must also be
13000 * implemented to allow module unload.
13003 module_exit(kvm_x86_exit);