2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/mem_encrypt.h>
59 #include <trace/events/kvm.h>
61 #include <asm/debugreg.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70 #include <asm/mshyperv.h>
71 #include <asm/hypervisor.h>
73 #define CREATE_TRACE_POINTS
76 #define MAX_IO_MSRS 256
77 #define KVM_MAX_MCE_BANKS 32
78 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
81 #define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
90 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
92 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
95 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
98 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
101 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
102 static void process_nmi(struct kvm_vcpu *vcpu);
103 static void enter_smm(struct kvm_vcpu *vcpu);
104 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
105 static void store_regs(struct kvm_vcpu *vcpu);
106 static int sync_regs(struct kvm_vcpu *vcpu);
108 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
109 EXPORT_SYMBOL_GPL(kvm_x86_ops);
111 static bool __read_mostly ignore_msrs = 0;
112 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
114 static bool __read_mostly report_ignored_msrs = true;
115 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
117 unsigned int min_timer_period_us = 200;
118 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
120 static bool __read_mostly kvmclock_periodic_sync = true;
121 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
123 bool __read_mostly kvm_has_tsc_control;
124 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
125 u32 __read_mostly kvm_max_guest_tsc_khz;
126 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
127 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129 u64 __read_mostly kvm_max_tsc_scaling_ratio;
130 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
131 u64 __read_mostly kvm_default_tsc_scaling_ratio;
132 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
134 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
135 static u32 __read_mostly tsc_tolerance_ppm = 250;
136 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
138 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
139 unsigned int __read_mostly lapic_timer_advance_ns = 0;
140 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
141 EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
143 static bool __read_mostly vector_hashing = true;
144 module_param(vector_hashing, bool, S_IRUGO);
146 bool __read_mostly enable_vmware_backdoor = false;
147 module_param(enable_vmware_backdoor, bool, S_IRUGO);
148 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
150 static bool __read_mostly force_emulation_prefix = false;
151 module_param(force_emulation_prefix, bool, S_IRUGO);
153 #define KVM_NR_SHARED_MSRS 16
155 struct kvm_shared_msrs_global {
157 u32 msrs[KVM_NR_SHARED_MSRS];
160 struct kvm_shared_msrs {
161 struct user_return_notifier urn;
163 struct kvm_shared_msr_values {
166 } values[KVM_NR_SHARED_MSRS];
169 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
170 static struct kvm_shared_msrs __percpu *shared_msrs;
172 struct kvm_stats_debugfs_item debugfs_entries[] = {
173 { "pf_fixed", VCPU_STAT(pf_fixed) },
174 { "pf_guest", VCPU_STAT(pf_guest) },
175 { "tlb_flush", VCPU_STAT(tlb_flush) },
176 { "invlpg", VCPU_STAT(invlpg) },
177 { "exits", VCPU_STAT(exits) },
178 { "io_exits", VCPU_STAT(io_exits) },
179 { "mmio_exits", VCPU_STAT(mmio_exits) },
180 { "signal_exits", VCPU_STAT(signal_exits) },
181 { "irq_window", VCPU_STAT(irq_window_exits) },
182 { "nmi_window", VCPU_STAT(nmi_window_exits) },
183 { "halt_exits", VCPU_STAT(halt_exits) },
184 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
185 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
186 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
187 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
188 { "hypercalls", VCPU_STAT(hypercalls) },
189 { "request_irq", VCPU_STAT(request_irq_exits) },
190 { "irq_exits", VCPU_STAT(irq_exits) },
191 { "host_state_reload", VCPU_STAT(host_state_reload) },
192 { "fpu_reload", VCPU_STAT(fpu_reload) },
193 { "insn_emulation", VCPU_STAT(insn_emulation) },
194 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
195 { "irq_injections", VCPU_STAT(irq_injections) },
196 { "nmi_injections", VCPU_STAT(nmi_injections) },
197 { "req_event", VCPU_STAT(req_event) },
198 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
199 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
200 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
201 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
202 { "mmu_flooded", VM_STAT(mmu_flooded) },
203 { "mmu_recycled", VM_STAT(mmu_recycled) },
204 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
205 { "mmu_unsync", VM_STAT(mmu_unsync) },
206 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
207 { "largepages", VM_STAT(lpages) },
208 { "max_mmu_page_hash_collisions",
209 VM_STAT(max_mmu_page_hash_collisions) },
213 u64 __read_mostly host_xcr0;
215 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
217 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
220 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
221 vcpu->arch.apf.gfns[i] = ~0;
224 static void kvm_on_user_return(struct user_return_notifier *urn)
227 struct kvm_shared_msrs *locals
228 = container_of(urn, struct kvm_shared_msrs, urn);
229 struct kvm_shared_msr_values *values;
233 * Disabling irqs at this point since the following code could be
234 * interrupted and executed through kvm_arch_hardware_disable()
236 local_irq_save(flags);
237 if (locals->registered) {
238 locals->registered = false;
239 user_return_notifier_unregister(urn);
241 local_irq_restore(flags);
242 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
243 values = &locals->values[slot];
244 if (values->host != values->curr) {
245 wrmsrl(shared_msrs_global.msrs[slot], values->host);
246 values->curr = values->host;
251 static void shared_msr_update(unsigned slot, u32 msr)
254 unsigned int cpu = smp_processor_id();
255 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
257 /* only read, and nobody should modify it at this time,
258 * so don't need lock */
259 if (slot >= shared_msrs_global.nr) {
260 printk(KERN_ERR "kvm: invalid MSR slot!");
263 rdmsrl_safe(msr, &value);
264 smsr->values[slot].host = value;
265 smsr->values[slot].curr = value;
268 void kvm_define_shared_msr(unsigned slot, u32 msr)
270 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
271 shared_msrs_global.msrs[slot] = msr;
272 if (slot >= shared_msrs_global.nr)
273 shared_msrs_global.nr = slot + 1;
275 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
277 static void kvm_shared_msr_cpu_online(void)
281 for (i = 0; i < shared_msrs_global.nr; ++i)
282 shared_msr_update(i, shared_msrs_global.msrs[i]);
285 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
287 unsigned int cpu = smp_processor_id();
288 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
291 if (((value ^ smsr->values[slot].curr) & mask) == 0)
293 smsr->values[slot].curr = value;
294 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
298 if (!smsr->registered) {
299 smsr->urn.on_user_return = kvm_on_user_return;
300 user_return_notifier_register(&smsr->urn);
301 smsr->registered = true;
305 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
307 static void drop_user_return_notifiers(void)
309 unsigned int cpu = smp_processor_id();
310 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
312 if (smsr->registered)
313 kvm_on_user_return(&smsr->urn);
316 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
318 return vcpu->arch.apic_base;
320 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
322 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
324 return kvm_apic_mode(kvm_get_apic_base(vcpu));
326 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
328 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
330 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
331 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
332 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
333 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
335 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
337 if (!msr_info->host_initiated) {
338 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
340 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
344 kvm_lapic_set_base(vcpu, msr_info->data);
347 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
349 asmlinkage __visible void kvm_spurious_fault(void)
351 /* Fault while not rebooting. We want the trace. */
354 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
356 #define EXCPT_BENIGN 0
357 #define EXCPT_CONTRIBUTORY 1
360 static int exception_class(int vector)
370 return EXCPT_CONTRIBUTORY;
377 #define EXCPT_FAULT 0
379 #define EXCPT_ABORT 2
380 #define EXCPT_INTERRUPT 3
382 static int exception_type(int vector)
386 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
387 return EXCPT_INTERRUPT;
391 /* #DB is trap, as instruction watchpoints are handled elsewhere */
392 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
395 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
398 /* Reserved exceptions will result in fault */
402 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
403 unsigned nr, bool has_error, u32 error_code,
409 kvm_make_request(KVM_REQ_EVENT, vcpu);
411 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
413 if (has_error && !is_protmode(vcpu))
417 * On vmentry, vcpu->arch.exception.pending is only
418 * true if an event injection was blocked by
419 * nested_run_pending. In that case, however,
420 * vcpu_enter_guest requests an immediate exit,
421 * and the guest shouldn't proceed far enough to
424 WARN_ON_ONCE(vcpu->arch.exception.pending);
425 vcpu->arch.exception.injected = true;
427 vcpu->arch.exception.pending = true;
428 vcpu->arch.exception.injected = false;
430 vcpu->arch.exception.has_error_code = has_error;
431 vcpu->arch.exception.nr = nr;
432 vcpu->arch.exception.error_code = error_code;
436 /* to check exception */
437 prev_nr = vcpu->arch.exception.nr;
438 if (prev_nr == DF_VECTOR) {
439 /* triple fault -> shutdown */
440 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
443 class1 = exception_class(prev_nr);
444 class2 = exception_class(nr);
445 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
446 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
448 * Generate double fault per SDM Table 5-5. Set
449 * exception.pending = true so that the double fault
450 * can trigger a nested vmexit.
452 vcpu->arch.exception.pending = true;
453 vcpu->arch.exception.injected = false;
454 vcpu->arch.exception.has_error_code = true;
455 vcpu->arch.exception.nr = DF_VECTOR;
456 vcpu->arch.exception.error_code = 0;
458 /* replace previous exception with a new one in a hope
459 that instruction re-execution will regenerate lost
464 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
466 kvm_multiple_exception(vcpu, nr, false, 0, false);
468 EXPORT_SYMBOL_GPL(kvm_queue_exception);
470 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
472 kvm_multiple_exception(vcpu, nr, false, 0, true);
474 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
476 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
479 kvm_inject_gp(vcpu, 0);
481 return kvm_skip_emulated_instruction(vcpu);
485 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
487 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
489 ++vcpu->stat.pf_guest;
490 vcpu->arch.exception.nested_apf =
491 is_guest_mode(vcpu) && fault->async_page_fault;
492 if (vcpu->arch.exception.nested_apf)
493 vcpu->arch.apf.nested_apf_token = fault->address;
495 vcpu->arch.cr2 = fault->address;
496 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
498 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
500 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
502 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
503 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
505 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
507 return fault->nested_page_fault;
510 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
512 atomic_inc(&vcpu->arch.nmi_queued);
513 kvm_make_request(KVM_REQ_NMI, vcpu);
515 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
517 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
519 kvm_multiple_exception(vcpu, nr, true, error_code, false);
521 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
523 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
525 kvm_multiple_exception(vcpu, nr, true, error_code, true);
527 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
530 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
531 * a #GP and return false.
533 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
535 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
537 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
540 EXPORT_SYMBOL_GPL(kvm_require_cpl);
542 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
544 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
547 kvm_queue_exception(vcpu, UD_VECTOR);
550 EXPORT_SYMBOL_GPL(kvm_require_dr);
553 * This function will be used to read from the physical memory of the currently
554 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
555 * can read from guest physical or from the guest's guest physical memory.
557 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
558 gfn_t ngfn, void *data, int offset, int len,
561 struct x86_exception exception;
565 ngpa = gfn_to_gpa(ngfn);
566 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
567 if (real_gfn == UNMAPPED_GVA)
570 real_gfn = gpa_to_gfn(real_gfn);
572 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
574 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
576 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
577 void *data, int offset, int len, u32 access)
579 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
580 data, offset, len, access);
584 * Load the pae pdptrs. Return true is they are all valid.
586 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
588 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
589 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
592 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
594 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
595 offset * sizeof(u64), sizeof(pdpte),
596 PFERR_USER_MASK|PFERR_WRITE_MASK);
601 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
602 if ((pdpte[i] & PT_PRESENT_MASK) &&
604 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
611 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
612 __set_bit(VCPU_EXREG_PDPTR,
613 (unsigned long *)&vcpu->arch.regs_avail);
614 __set_bit(VCPU_EXREG_PDPTR,
615 (unsigned long *)&vcpu->arch.regs_dirty);
620 EXPORT_SYMBOL_GPL(load_pdptrs);
622 bool pdptrs_changed(struct kvm_vcpu *vcpu)
624 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
630 if (is_long_mode(vcpu) || !is_pae(vcpu))
633 if (!test_bit(VCPU_EXREG_PDPTR,
634 (unsigned long *)&vcpu->arch.regs_avail))
637 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
638 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
639 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
640 PFERR_USER_MASK | PFERR_WRITE_MASK);
643 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
648 EXPORT_SYMBOL_GPL(pdptrs_changed);
650 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
652 unsigned long old_cr0 = kvm_read_cr0(vcpu);
653 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
658 if (cr0 & 0xffffffff00000000UL)
662 cr0 &= ~CR0_RESERVED_BITS;
664 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
667 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
670 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
672 if ((vcpu->arch.efer & EFER_LME)) {
677 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
682 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
687 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
690 kvm_x86_ops->set_cr0(vcpu, cr0);
692 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
693 kvm_clear_async_pf_completion_queue(vcpu);
694 kvm_async_pf_hash_reset(vcpu);
697 if ((cr0 ^ old_cr0) & update_bits)
698 kvm_mmu_reset_context(vcpu);
700 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
701 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
702 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
703 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
707 EXPORT_SYMBOL_GPL(kvm_set_cr0);
709 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
711 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
713 EXPORT_SYMBOL_GPL(kvm_lmsw);
715 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
717 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
718 !vcpu->guest_xcr0_loaded) {
719 /* kvm_set_xcr() also depends on this */
720 if (vcpu->arch.xcr0 != host_xcr0)
721 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
722 vcpu->guest_xcr0_loaded = 1;
726 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
728 if (vcpu->guest_xcr0_loaded) {
729 if (vcpu->arch.xcr0 != host_xcr0)
730 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
731 vcpu->guest_xcr0_loaded = 0;
735 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
738 u64 old_xcr0 = vcpu->arch.xcr0;
741 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
742 if (index != XCR_XFEATURE_ENABLED_MASK)
744 if (!(xcr0 & XFEATURE_MASK_FP))
746 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
750 * Do not allow the guest to set bits that we do not support
751 * saving. However, xcr0 bit 0 is always set, even if the
752 * emulated CPU does not support XSAVE (see fx_init).
754 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
755 if (xcr0 & ~valid_bits)
758 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
759 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
762 if (xcr0 & XFEATURE_MASK_AVX512) {
763 if (!(xcr0 & XFEATURE_MASK_YMM))
765 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
768 vcpu->arch.xcr0 = xcr0;
770 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
771 kvm_update_cpuid(vcpu);
775 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
777 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
778 __kvm_set_xcr(vcpu, index, xcr)) {
779 kvm_inject_gp(vcpu, 0);
784 EXPORT_SYMBOL_GPL(kvm_set_xcr);
786 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
788 unsigned long old_cr4 = kvm_read_cr4(vcpu);
789 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
790 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
792 if (cr4 & CR4_RESERVED_BITS)
795 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
798 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
801 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
804 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
807 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
810 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
813 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
816 if (is_long_mode(vcpu)) {
817 if (!(cr4 & X86_CR4_PAE))
819 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
820 && ((cr4 ^ old_cr4) & pdptr_bits)
821 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
825 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
826 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
829 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
830 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
834 if (kvm_x86_ops->set_cr4(vcpu, cr4))
837 if (((cr4 ^ old_cr4) & pdptr_bits) ||
838 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
839 kvm_mmu_reset_context(vcpu);
841 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
842 kvm_update_cpuid(vcpu);
846 EXPORT_SYMBOL_GPL(kvm_set_cr4);
848 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
851 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
854 cr3 &= ~CR3_PCID_INVD;
857 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
858 kvm_mmu_sync_roots(vcpu);
859 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
863 if (is_long_mode(vcpu) &&
864 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
866 else if (is_pae(vcpu) && is_paging(vcpu) &&
867 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
870 vcpu->arch.cr3 = cr3;
871 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
872 kvm_mmu_new_cr3(vcpu);
875 EXPORT_SYMBOL_GPL(kvm_set_cr3);
877 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
879 if (cr8 & CR8_RESERVED_BITS)
881 if (lapic_in_kernel(vcpu))
882 kvm_lapic_set_tpr(vcpu, cr8);
884 vcpu->arch.cr8 = cr8;
887 EXPORT_SYMBOL_GPL(kvm_set_cr8);
889 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
891 if (lapic_in_kernel(vcpu))
892 return kvm_lapic_get_cr8(vcpu);
894 return vcpu->arch.cr8;
896 EXPORT_SYMBOL_GPL(kvm_get_cr8);
898 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
902 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
903 for (i = 0; i < KVM_NR_DB_REGS; i++)
904 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
905 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
909 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
911 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
912 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
915 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
919 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
920 dr7 = vcpu->arch.guest_debug_dr7;
922 dr7 = vcpu->arch.dr7;
923 kvm_x86_ops->set_dr7(vcpu, dr7);
924 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
925 if (dr7 & DR7_BP_EN_MASK)
926 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
929 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
931 u64 fixed = DR6_FIXED_1;
933 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
938 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
942 vcpu->arch.db[dr] = val;
943 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
944 vcpu->arch.eff_db[dr] = val;
949 if (val & 0xffffffff00000000ULL)
951 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
952 kvm_update_dr6(vcpu);
957 if (val & 0xffffffff00000000ULL)
959 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
960 kvm_update_dr7(vcpu);
967 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
969 if (__kvm_set_dr(vcpu, dr, val)) {
970 kvm_inject_gp(vcpu, 0);
975 EXPORT_SYMBOL_GPL(kvm_set_dr);
977 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
981 *val = vcpu->arch.db[dr];
986 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
987 *val = vcpu->arch.dr6;
989 *val = kvm_x86_ops->get_dr6(vcpu);
994 *val = vcpu->arch.dr7;
999 EXPORT_SYMBOL_GPL(kvm_get_dr);
1001 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1003 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1007 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1010 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1011 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1014 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1017 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1018 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1020 * This list is modified at module load time to reflect the
1021 * capabilities of the host cpu. This capabilities test skips MSRs that are
1022 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1023 * may depend on host virtualization features rather than host cpu features.
1026 static u32 msrs_to_save[] = {
1027 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1029 #ifdef CONFIG_X86_64
1030 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1032 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1033 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1034 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
1037 static unsigned num_msrs_to_save;
1039 static u32 emulated_msrs[] = {
1040 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1041 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1042 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1043 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1044 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1045 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1046 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1048 HV_X64_MSR_VP_INDEX,
1049 HV_X64_MSR_VP_RUNTIME,
1050 HV_X64_MSR_SCONTROL,
1051 HV_X64_MSR_STIMER0_CONFIG,
1052 HV_X64_MSR_VP_ASSIST_PAGE,
1053 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1054 HV_X64_MSR_TSC_EMULATION_STATUS,
1056 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1059 MSR_IA32_TSC_ADJUST,
1060 MSR_IA32_TSCDEADLINE,
1061 MSR_IA32_MISC_ENABLE,
1062 MSR_IA32_MCG_STATUS,
1064 MSR_IA32_MCG_EXT_CTL,
1068 MSR_MISC_FEATURES_ENABLES,
1069 MSR_AMD64_VIRT_SPEC_CTRL,
1072 static unsigned num_emulated_msrs;
1075 * List of msr numbers which are used to expose MSR-based features that
1076 * can be used by a hypervisor to validate requested CPU features.
1078 static u32 msr_based_features[] = {
1080 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1081 MSR_IA32_VMX_PINBASED_CTLS,
1082 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1083 MSR_IA32_VMX_PROCBASED_CTLS,
1084 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1085 MSR_IA32_VMX_EXIT_CTLS,
1086 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1087 MSR_IA32_VMX_ENTRY_CTLS,
1089 MSR_IA32_VMX_CR0_FIXED0,
1090 MSR_IA32_VMX_CR0_FIXED1,
1091 MSR_IA32_VMX_CR4_FIXED0,
1092 MSR_IA32_VMX_CR4_FIXED1,
1093 MSR_IA32_VMX_VMCS_ENUM,
1094 MSR_IA32_VMX_PROCBASED_CTLS2,
1095 MSR_IA32_VMX_EPT_VPID_CAP,
1096 MSR_IA32_VMX_VMFUNC,
1100 MSR_IA32_ARCH_CAPABILITIES,
1103 static unsigned int num_msr_based_features;
1105 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1107 switch (msr->index) {
1108 case MSR_IA32_UCODE_REV:
1109 case MSR_IA32_ARCH_CAPABILITIES:
1110 rdmsrl_safe(msr->index, &msr->data);
1113 if (kvm_x86_ops->get_msr_feature(msr))
1119 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1121 struct kvm_msr_entry msr;
1125 r = kvm_get_msr_feature(&msr);
1134 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1136 if (efer & efer_reserved_bits)
1139 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1142 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1147 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1149 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1151 u64 old_efer = vcpu->arch.efer;
1153 if (!kvm_valid_efer(vcpu, efer))
1157 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1161 efer |= vcpu->arch.efer & EFER_LMA;
1163 kvm_x86_ops->set_efer(vcpu, efer);
1165 /* Update reserved bits */
1166 if ((efer ^ old_efer) & EFER_NX)
1167 kvm_mmu_reset_context(vcpu);
1172 void kvm_enable_efer_bits(u64 mask)
1174 efer_reserved_bits &= ~mask;
1176 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1179 * Writes msr value into into the appropriate "register".
1180 * Returns 0 on success, non-0 otherwise.
1181 * Assumes vcpu_load() was already called.
1183 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1185 switch (msr->index) {
1188 case MSR_KERNEL_GS_BASE:
1191 if (is_noncanonical_address(msr->data, vcpu))
1194 case MSR_IA32_SYSENTER_EIP:
1195 case MSR_IA32_SYSENTER_ESP:
1197 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1198 * non-canonical address is written on Intel but not on
1199 * AMD (which ignores the top 32-bits, because it does
1200 * not implement 64-bit SYSENTER).
1202 * 64-bit code should hence be able to write a non-canonical
1203 * value on AMD. Making the address canonical ensures that
1204 * vmentry does not fail on Intel after writing a non-canonical
1205 * value, and that something deterministic happens if the guest
1206 * invokes 64-bit SYSENTER.
1208 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
1210 return kvm_x86_ops->set_msr(vcpu, msr);
1212 EXPORT_SYMBOL_GPL(kvm_set_msr);
1215 * Adapt set_msr() to msr_io()'s calling convention
1217 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1219 struct msr_data msr;
1223 msr.host_initiated = true;
1224 r = kvm_get_msr(vcpu, &msr);
1232 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1234 struct msr_data msr;
1238 msr.host_initiated = true;
1239 return kvm_set_msr(vcpu, &msr);
1242 #ifdef CONFIG_X86_64
1243 struct pvclock_gtod_data {
1246 struct { /* extract of a clocksource struct */
1259 static struct pvclock_gtod_data pvclock_gtod_data;
1261 static void update_pvclock_gtod(struct timekeeper *tk)
1263 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1266 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1268 write_seqcount_begin(&vdata->seq);
1270 /* copy pvclock gtod data */
1271 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1272 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1273 vdata->clock.mask = tk->tkr_mono.mask;
1274 vdata->clock.mult = tk->tkr_mono.mult;
1275 vdata->clock.shift = tk->tkr_mono.shift;
1277 vdata->boot_ns = boot_ns;
1278 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1280 vdata->wall_time_sec = tk->xtime_sec;
1282 write_seqcount_end(&vdata->seq);
1286 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1289 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1290 * vcpu_enter_guest. This function is only called from
1291 * the physical CPU that is running vcpu.
1293 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1296 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1300 struct pvclock_wall_clock wc;
1301 struct timespec64 boot;
1306 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1311 ++version; /* first time write, random junk */
1315 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1319 * The guest calculates current wall clock time by adding
1320 * system time (updated by kvm_guest_time_update below) to the
1321 * wall clock specified here. guest system time equals host
1322 * system time for us, thus we must fill in host boot time here.
1324 getboottime64(&boot);
1326 if (kvm->arch.kvmclock_offset) {
1327 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1328 boot = timespec64_sub(boot, ts);
1330 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1331 wc.nsec = boot.tv_nsec;
1332 wc.version = version;
1334 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1337 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1340 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1342 do_shl32_div32(dividend, divisor);
1346 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1347 s8 *pshift, u32 *pmultiplier)
1355 scaled64 = scaled_hz;
1356 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1361 tps32 = (uint32_t)tps64;
1362 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1363 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1371 *pmultiplier = div_frac(scaled64, tps32);
1373 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1374 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1377 #ifdef CONFIG_X86_64
1378 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1381 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1382 static unsigned long max_tsc_khz;
1384 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1386 u64 v = (u64)khz * (1000000 + ppm);
1391 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1395 /* Guest TSC same frequency as host TSC? */
1397 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1401 /* TSC scaling supported? */
1402 if (!kvm_has_tsc_control) {
1403 if (user_tsc_khz > tsc_khz) {
1404 vcpu->arch.tsc_catchup = 1;
1405 vcpu->arch.tsc_always_catchup = 1;
1408 WARN(1, "user requested TSC rate below hardware speed\n");
1413 /* TSC scaling required - calculate ratio */
1414 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1415 user_tsc_khz, tsc_khz);
1417 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1418 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1423 vcpu->arch.tsc_scaling_ratio = ratio;
1427 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1429 u32 thresh_lo, thresh_hi;
1430 int use_scaling = 0;
1432 /* tsc_khz can be zero if TSC calibration fails */
1433 if (user_tsc_khz == 0) {
1434 /* set tsc_scaling_ratio to a safe value */
1435 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1439 /* Compute a scale to convert nanoseconds in TSC cycles */
1440 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1441 &vcpu->arch.virtual_tsc_shift,
1442 &vcpu->arch.virtual_tsc_mult);
1443 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1446 * Compute the variation in TSC rate which is acceptable
1447 * within the range of tolerance and decide if the
1448 * rate being applied is within that bounds of the hardware
1449 * rate. If so, no scaling or compensation need be done.
1451 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1452 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1453 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1454 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1457 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1460 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1462 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1463 vcpu->arch.virtual_tsc_mult,
1464 vcpu->arch.virtual_tsc_shift);
1465 tsc += vcpu->arch.this_tsc_write;
1469 static inline int gtod_is_based_on_tsc(int mode)
1471 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1474 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1476 #ifdef CONFIG_X86_64
1478 struct kvm_arch *ka = &vcpu->kvm->arch;
1479 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1481 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1482 atomic_read(&vcpu->kvm->online_vcpus));
1485 * Once the masterclock is enabled, always perform request in
1486 * order to update it.
1488 * In order to enable masterclock, the host clocksource must be TSC
1489 * and the vcpus need to have matched TSCs. When that happens,
1490 * perform request to enable masterclock.
1492 if (ka->use_master_clock ||
1493 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1494 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1496 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1497 atomic_read(&vcpu->kvm->online_vcpus),
1498 ka->use_master_clock, gtod->clock.vclock_mode);
1502 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1504 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1505 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1509 * Multiply tsc by a fixed point number represented by ratio.
1511 * The most significant 64-N bits (mult) of ratio represent the
1512 * integral part of the fixed point number; the remaining N bits
1513 * (frac) represent the fractional part, ie. ratio represents a fixed
1514 * point number (mult + frac * 2^(-N)).
1516 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1518 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1520 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1523 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1526 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1528 if (ratio != kvm_default_tsc_scaling_ratio)
1529 _tsc = __scale_tsc(ratio, tsc);
1533 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1535 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1539 tsc = kvm_scale_tsc(vcpu, rdtsc());
1541 return target_tsc - tsc;
1544 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1546 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1548 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1550 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1552 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1554 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1555 vcpu->arch.tsc_offset = offset;
1558 static inline bool kvm_check_tsc_unstable(void)
1560 #ifdef CONFIG_X86_64
1562 * TSC is marked unstable when we're running on Hyper-V,
1563 * 'TSC page' clocksource is good.
1565 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1568 return check_tsc_unstable();
1571 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1573 struct kvm *kvm = vcpu->kvm;
1574 u64 offset, ns, elapsed;
1575 unsigned long flags;
1577 bool already_matched;
1578 u64 data = msr->data;
1579 bool synchronizing = false;
1581 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1582 offset = kvm_compute_tsc_offset(vcpu, data);
1583 ns = ktime_get_boot_ns();
1584 elapsed = ns - kvm->arch.last_tsc_nsec;
1586 if (vcpu->arch.virtual_tsc_khz) {
1587 if (data == 0 && msr->host_initiated) {
1589 * detection of vcpu initialization -- need to sync
1590 * with other vCPUs. This particularly helps to keep
1591 * kvm_clock stable after CPU hotplug
1593 synchronizing = true;
1595 u64 tsc_exp = kvm->arch.last_tsc_write +
1596 nsec_to_cycles(vcpu, elapsed);
1597 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1599 * Special case: TSC write with a small delta (1 second)
1600 * of virtual cycle time against real time is
1601 * interpreted as an attempt to synchronize the CPU.
1603 synchronizing = data < tsc_exp + tsc_hz &&
1604 data + tsc_hz > tsc_exp;
1609 * For a reliable TSC, we can match TSC offsets, and for an unstable
1610 * TSC, we add elapsed time in this computation. We could let the
1611 * compensation code attempt to catch up if we fall behind, but
1612 * it's better to try to match offsets from the beginning.
1614 if (synchronizing &&
1615 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1616 if (!kvm_check_tsc_unstable()) {
1617 offset = kvm->arch.cur_tsc_offset;
1618 pr_debug("kvm: matched tsc offset for %llu\n", data);
1620 u64 delta = nsec_to_cycles(vcpu, elapsed);
1622 offset = kvm_compute_tsc_offset(vcpu, data);
1623 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1626 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1629 * We split periods of matched TSC writes into generations.
1630 * For each generation, we track the original measured
1631 * nanosecond time, offset, and write, so if TSCs are in
1632 * sync, we can match exact offset, and if not, we can match
1633 * exact software computation in compute_guest_tsc()
1635 * These values are tracked in kvm->arch.cur_xxx variables.
1637 kvm->arch.cur_tsc_generation++;
1638 kvm->arch.cur_tsc_nsec = ns;
1639 kvm->arch.cur_tsc_write = data;
1640 kvm->arch.cur_tsc_offset = offset;
1642 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1643 kvm->arch.cur_tsc_generation, data);
1647 * We also track th most recent recorded KHZ, write and time to
1648 * allow the matching interval to be extended at each write.
1650 kvm->arch.last_tsc_nsec = ns;
1651 kvm->arch.last_tsc_write = data;
1652 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1654 vcpu->arch.last_guest_tsc = data;
1656 /* Keep track of which generation this VCPU has synchronized to */
1657 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1658 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1659 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1661 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1662 update_ia32_tsc_adjust_msr(vcpu, offset);
1664 kvm_vcpu_write_tsc_offset(vcpu, offset);
1665 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1667 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1669 kvm->arch.nr_vcpus_matched_tsc = 0;
1670 } else if (!already_matched) {
1671 kvm->arch.nr_vcpus_matched_tsc++;
1674 kvm_track_tsc_matching(vcpu);
1675 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1678 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1680 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1683 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
1686 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1688 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1689 WARN_ON(adjustment < 0);
1690 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1691 adjust_tsc_offset_guest(vcpu, adjustment);
1694 #ifdef CONFIG_X86_64
1696 static u64 read_tsc(void)
1698 u64 ret = (u64)rdtsc_ordered();
1699 u64 last = pvclock_gtod_data.clock.cycle_last;
1701 if (likely(ret >= last))
1705 * GCC likes to generate cmov here, but this branch is extremely
1706 * predictable (it's just a function of time and the likely is
1707 * very likely) and there's a data dependence, so force GCC
1708 * to generate a branch instead. I don't barrier() because
1709 * we don't actually need a barrier, and if this function
1710 * ever gets inlined it will generate worse code.
1716 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
1719 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1722 switch (gtod->clock.vclock_mode) {
1723 case VCLOCK_HVCLOCK:
1724 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1726 if (tsc_pg_val != U64_MAX) {
1727 /* TSC page valid */
1728 *mode = VCLOCK_HVCLOCK;
1729 v = (tsc_pg_val - gtod->clock.cycle_last) &
1732 /* TSC page invalid */
1733 *mode = VCLOCK_NONE;
1738 *tsc_timestamp = read_tsc();
1739 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1743 *mode = VCLOCK_NONE;
1746 if (*mode == VCLOCK_NONE)
1747 *tsc_timestamp = v = 0;
1749 return v * gtod->clock.mult;
1752 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
1754 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1760 seq = read_seqcount_begin(>od->seq);
1761 ns = gtod->nsec_base;
1762 ns += vgettsc(tsc_timestamp, &mode);
1763 ns >>= gtod->clock.shift;
1764 ns += gtod->boot_ns;
1765 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1771 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
1773 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1779 seq = read_seqcount_begin(>od->seq);
1780 ts->tv_sec = gtod->wall_time_sec;
1781 ns = gtod->nsec_base;
1782 ns += vgettsc(tsc_timestamp, &mode);
1783 ns >>= gtod->clock.shift;
1784 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1786 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1792 /* returns true if host is using TSC based clocksource */
1793 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
1795 /* checked again under seqlock below */
1796 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1799 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1803 /* returns true if host is using TSC based clocksource */
1804 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
1807 /* checked again under seqlock below */
1808 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1811 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
1817 * Assuming a stable TSC across physical CPUS, and a stable TSC
1818 * across virtual CPUs, the following condition is possible.
1819 * Each numbered line represents an event visible to both
1820 * CPUs at the next numbered event.
1822 * "timespecX" represents host monotonic time. "tscX" represents
1825 * VCPU0 on CPU0 | VCPU1 on CPU1
1827 * 1. read timespec0,tsc0
1828 * 2. | timespec1 = timespec0 + N
1830 * 3. transition to guest | transition to guest
1831 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1832 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1833 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1835 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1838 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1840 * - 0 < N - M => M < N
1842 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1843 * always the case (the difference between two distinct xtime instances
1844 * might be smaller then the difference between corresponding TSC reads,
1845 * when updating guest vcpus pvclock areas).
1847 * To avoid that problem, do not allow visibility of distinct
1848 * system_timestamp/tsc_timestamp values simultaneously: use a master
1849 * copy of host monotonic time values. Update that master copy
1852 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1856 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1858 #ifdef CONFIG_X86_64
1859 struct kvm_arch *ka = &kvm->arch;
1861 bool host_tsc_clocksource, vcpus_matched;
1863 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1864 atomic_read(&kvm->online_vcpus));
1867 * If the host uses TSC clock, then passthrough TSC as stable
1870 host_tsc_clocksource = kvm_get_time_and_clockread(
1871 &ka->master_kernel_ns,
1872 &ka->master_cycle_now);
1874 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1875 && !ka->backwards_tsc_observed
1876 && !ka->boot_vcpu_runs_old_kvmclock;
1878 if (ka->use_master_clock)
1879 atomic_set(&kvm_guest_has_master_clock, 1);
1881 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1882 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1887 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1889 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1892 static void kvm_gen_update_masterclock(struct kvm *kvm)
1894 #ifdef CONFIG_X86_64
1896 struct kvm_vcpu *vcpu;
1897 struct kvm_arch *ka = &kvm->arch;
1899 spin_lock(&ka->pvclock_gtod_sync_lock);
1900 kvm_make_mclock_inprogress_request(kvm);
1901 /* no guest entries from this point */
1902 pvclock_update_vm_gtod_copy(kvm);
1904 kvm_for_each_vcpu(i, vcpu, kvm)
1905 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1907 /* guest entries allowed */
1908 kvm_for_each_vcpu(i, vcpu, kvm)
1909 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
1911 spin_unlock(&ka->pvclock_gtod_sync_lock);
1915 u64 get_kvmclock_ns(struct kvm *kvm)
1917 struct kvm_arch *ka = &kvm->arch;
1918 struct pvclock_vcpu_time_info hv_clock;
1921 spin_lock(&ka->pvclock_gtod_sync_lock);
1922 if (!ka->use_master_clock) {
1923 spin_unlock(&ka->pvclock_gtod_sync_lock);
1924 return ktime_get_boot_ns() + ka->kvmclock_offset;
1927 hv_clock.tsc_timestamp = ka->master_cycle_now;
1928 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1929 spin_unlock(&ka->pvclock_gtod_sync_lock);
1931 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1934 if (__this_cpu_read(cpu_tsc_khz)) {
1935 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1936 &hv_clock.tsc_shift,
1937 &hv_clock.tsc_to_system_mul);
1938 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1940 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
1947 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1949 struct kvm_vcpu_arch *vcpu = &v->arch;
1950 struct pvclock_vcpu_time_info guest_hv_clock;
1952 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1953 &guest_hv_clock, sizeof(guest_hv_clock))))
1956 /* This VCPU is paused, but it's legal for a guest to read another
1957 * VCPU's kvmclock, so we really have to follow the specification where
1958 * it says that version is odd if data is being modified, and even after
1961 * Version field updates must be kept separate. This is because
1962 * kvm_write_guest_cached might use a "rep movs" instruction, and
1963 * writes within a string instruction are weakly ordered. So there
1964 * are three writes overall.
1966 * As a small optimization, only write the version field in the first
1967 * and third write. The vcpu->pv_time cache is still valid, because the
1968 * version field is the first in the struct.
1970 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1972 if (guest_hv_clock.version & 1)
1973 ++guest_hv_clock.version; /* first time write, random junk */
1975 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1976 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1978 sizeof(vcpu->hv_clock.version));
1982 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1983 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1985 if (vcpu->pvclock_set_guest_stopped_request) {
1986 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1987 vcpu->pvclock_set_guest_stopped_request = false;
1990 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1992 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1994 sizeof(vcpu->hv_clock));
1998 vcpu->hv_clock.version++;
1999 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2001 sizeof(vcpu->hv_clock.version));
2004 static int kvm_guest_time_update(struct kvm_vcpu *v)
2006 unsigned long flags, tgt_tsc_khz;
2007 struct kvm_vcpu_arch *vcpu = &v->arch;
2008 struct kvm_arch *ka = &v->kvm->arch;
2010 u64 tsc_timestamp, host_tsc;
2012 bool use_master_clock;
2018 * If the host uses TSC clock, then passthrough TSC as stable
2021 spin_lock(&ka->pvclock_gtod_sync_lock);
2022 use_master_clock = ka->use_master_clock;
2023 if (use_master_clock) {
2024 host_tsc = ka->master_cycle_now;
2025 kernel_ns = ka->master_kernel_ns;
2027 spin_unlock(&ka->pvclock_gtod_sync_lock);
2029 /* Keep irq disabled to prevent changes to the clock */
2030 local_irq_save(flags);
2031 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2032 if (unlikely(tgt_tsc_khz == 0)) {
2033 local_irq_restore(flags);
2034 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2037 if (!use_master_clock) {
2039 kernel_ns = ktime_get_boot_ns();
2042 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2045 * We may have to catch up the TSC to match elapsed wall clock
2046 * time for two reasons, even if kvmclock is used.
2047 * 1) CPU could have been running below the maximum TSC rate
2048 * 2) Broken TSC compensation resets the base at each VCPU
2049 * entry to avoid unknown leaps of TSC even when running
2050 * again on the same CPU. This may cause apparent elapsed
2051 * time to disappear, and the guest to stand still or run
2054 if (vcpu->tsc_catchup) {
2055 u64 tsc = compute_guest_tsc(v, kernel_ns);
2056 if (tsc > tsc_timestamp) {
2057 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2058 tsc_timestamp = tsc;
2062 local_irq_restore(flags);
2064 /* With all the info we got, fill in the values */
2066 if (kvm_has_tsc_control)
2067 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2069 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2070 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2071 &vcpu->hv_clock.tsc_shift,
2072 &vcpu->hv_clock.tsc_to_system_mul);
2073 vcpu->hw_tsc_khz = tgt_tsc_khz;
2076 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2077 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2078 vcpu->last_guest_tsc = tsc_timestamp;
2080 /* If the host uses TSC clocksource, then it is stable */
2082 if (use_master_clock)
2083 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2085 vcpu->hv_clock.flags = pvclock_flags;
2087 if (vcpu->pv_time_enabled)
2088 kvm_setup_pvclock_page(v);
2089 if (v == kvm_get_vcpu(v->kvm, 0))
2090 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2095 * kvmclock updates which are isolated to a given vcpu, such as
2096 * vcpu->cpu migration, should not allow system_timestamp from
2097 * the rest of the vcpus to remain static. Otherwise ntp frequency
2098 * correction applies to one vcpu's system_timestamp but not
2101 * So in those cases, request a kvmclock update for all vcpus.
2102 * We need to rate-limit these requests though, as they can
2103 * considerably slow guests that have a large number of vcpus.
2104 * The time for a remote vcpu to update its kvmclock is bound
2105 * by the delay we use to rate-limit the updates.
2108 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2110 static void kvmclock_update_fn(struct work_struct *work)
2113 struct delayed_work *dwork = to_delayed_work(work);
2114 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2115 kvmclock_update_work);
2116 struct kvm *kvm = container_of(ka, struct kvm, arch);
2117 struct kvm_vcpu *vcpu;
2119 kvm_for_each_vcpu(i, vcpu, kvm) {
2120 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2121 kvm_vcpu_kick(vcpu);
2125 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2127 struct kvm *kvm = v->kvm;
2129 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2130 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2131 KVMCLOCK_UPDATE_DELAY);
2134 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2136 static void kvmclock_sync_fn(struct work_struct *work)
2138 struct delayed_work *dwork = to_delayed_work(work);
2139 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2140 kvmclock_sync_work);
2141 struct kvm *kvm = container_of(ka, struct kvm, arch);
2143 if (!kvmclock_periodic_sync)
2146 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2147 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2148 KVMCLOCK_SYNC_PERIOD);
2151 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2153 u64 mcg_cap = vcpu->arch.mcg_cap;
2154 unsigned bank_num = mcg_cap & 0xff;
2155 u32 msr = msr_info->index;
2156 u64 data = msr_info->data;
2159 case MSR_IA32_MCG_STATUS:
2160 vcpu->arch.mcg_status = data;
2162 case MSR_IA32_MCG_CTL:
2163 if (!(mcg_cap & MCG_CTL_P) &&
2164 (data || !msr_info->host_initiated))
2166 if (data != 0 && data != ~(u64)0)
2168 vcpu->arch.mcg_ctl = data;
2171 if (msr >= MSR_IA32_MC0_CTL &&
2172 msr < MSR_IA32_MCx_CTL(bank_num)) {
2173 u32 offset = msr - MSR_IA32_MC0_CTL;
2174 /* only 0 or all 1s can be written to IA32_MCi_CTL
2175 * some Linux kernels though clear bit 10 in bank 4 to
2176 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2177 * this to avoid an uncatched #GP in the guest
2179 if ((offset & 0x3) == 0 &&
2180 data != 0 && (data | (1 << 10)) != ~(u64)0)
2182 if (!msr_info->host_initiated &&
2183 (offset & 0x3) == 1 && data != 0)
2185 vcpu->arch.mce_banks[offset] = data;
2193 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2195 struct kvm *kvm = vcpu->kvm;
2196 int lm = is_long_mode(vcpu);
2197 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2198 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2199 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2200 : kvm->arch.xen_hvm_config.blob_size_32;
2201 u32 page_num = data & ~PAGE_MASK;
2202 u64 page_addr = data & PAGE_MASK;
2207 if (page_num >= blob_size)
2210 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2215 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2224 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2226 gpa_t gpa = data & ~0x3f;
2228 /* Bits 3:5 are reserved, Should be zero */
2232 vcpu->arch.apf.msr_val = data;
2234 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2235 kvm_clear_async_pf_completion_queue(vcpu);
2236 kvm_async_pf_hash_reset(vcpu);
2240 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2244 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2245 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2246 kvm_async_pf_wakeup_all(vcpu);
2250 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2252 vcpu->arch.pv_time_enabled = false;
2255 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2257 ++vcpu->stat.tlb_flush;
2258 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2261 static void record_steal_time(struct kvm_vcpu *vcpu)
2263 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2266 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2267 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2271 * Doing a TLB flush here, on the guest's behalf, can avoid
2274 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2275 kvm_vcpu_flush_tlb(vcpu, false);
2277 if (vcpu->arch.st.steal.version & 1)
2278 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2280 vcpu->arch.st.steal.version += 1;
2282 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2283 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2287 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2288 vcpu->arch.st.last_steal;
2289 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2291 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2292 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2296 vcpu->arch.st.steal.version += 1;
2298 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2299 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2302 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2305 u32 msr = msr_info->index;
2306 u64 data = msr_info->data;
2309 case MSR_AMD64_NB_CFG:
2310 case MSR_IA32_UCODE_WRITE:
2311 case MSR_VM_HSAVE_PA:
2312 case MSR_AMD64_PATCH_LOADER:
2313 case MSR_AMD64_BU_CFG2:
2314 case MSR_AMD64_DC_CFG:
2317 case MSR_IA32_UCODE_REV:
2318 if (msr_info->host_initiated)
2319 vcpu->arch.microcode_version = data;
2322 return set_efer(vcpu, data);
2324 data &= ~(u64)0x40; /* ignore flush filter disable */
2325 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2326 data &= ~(u64)0x8; /* ignore TLB cache disable */
2327 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2329 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2334 case MSR_FAM10H_MMIO_CONF_BASE:
2336 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2341 case MSR_IA32_DEBUGCTLMSR:
2343 /* We support the non-activated case already */
2345 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2346 /* Values other than LBR and BTF are vendor-specific,
2347 thus reserved and should throw a #GP */
2350 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2353 case 0x200 ... 0x2ff:
2354 return kvm_mtrr_set_msr(vcpu, msr, data);
2355 case MSR_IA32_APICBASE:
2356 return kvm_set_apic_base(vcpu, msr_info);
2357 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2358 return kvm_x2apic_msr_write(vcpu, msr, data);
2359 case MSR_IA32_TSCDEADLINE:
2360 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2362 case MSR_IA32_TSC_ADJUST:
2363 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2364 if (!msr_info->host_initiated) {
2365 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2366 adjust_tsc_offset_guest(vcpu, adj);
2368 vcpu->arch.ia32_tsc_adjust_msr = data;
2371 case MSR_IA32_MISC_ENABLE:
2372 vcpu->arch.ia32_misc_enable_msr = data;
2374 case MSR_IA32_SMBASE:
2375 if (!msr_info->host_initiated)
2377 vcpu->arch.smbase = data;
2380 kvm_write_tsc(vcpu, msr_info);
2383 if (!msr_info->host_initiated)
2385 vcpu->arch.smi_count = data;
2387 case MSR_KVM_WALL_CLOCK_NEW:
2388 case MSR_KVM_WALL_CLOCK:
2389 vcpu->kvm->arch.wall_clock = data;
2390 kvm_write_wall_clock(vcpu->kvm, data);
2392 case MSR_KVM_SYSTEM_TIME_NEW:
2393 case MSR_KVM_SYSTEM_TIME: {
2394 struct kvm_arch *ka = &vcpu->kvm->arch;
2396 kvmclock_reset(vcpu);
2398 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2399 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2401 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2402 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2404 ka->boot_vcpu_runs_old_kvmclock = tmp;
2407 vcpu->arch.time = data;
2408 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2410 /* we verify if the enable bit is set... */
2414 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2415 &vcpu->arch.pv_time, data & ~1ULL,
2416 sizeof(struct pvclock_vcpu_time_info)))
2417 vcpu->arch.pv_time_enabled = false;
2419 vcpu->arch.pv_time_enabled = true;
2423 case MSR_KVM_ASYNC_PF_EN:
2424 if (kvm_pv_enable_async_pf(vcpu, data))
2427 case MSR_KVM_STEAL_TIME:
2429 if (unlikely(!sched_info_on()))
2432 if (data & KVM_STEAL_RESERVED_MASK)
2435 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2436 data & KVM_STEAL_VALID_BITS,
2437 sizeof(struct kvm_steal_time)))
2440 vcpu->arch.st.msr_val = data;
2442 if (!(data & KVM_MSR_ENABLED))
2445 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2448 case MSR_KVM_PV_EOI_EN:
2449 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2453 case MSR_IA32_MCG_CTL:
2454 case MSR_IA32_MCG_STATUS:
2455 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2456 return set_msr_mce(vcpu, msr_info);
2458 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2459 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2460 pr = true; /* fall through */
2461 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2462 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2463 if (kvm_pmu_is_valid_msr(vcpu, msr))
2464 return kvm_pmu_set_msr(vcpu, msr_info);
2466 if (pr || data != 0)
2467 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2468 "0x%x data 0x%llx\n", msr, data);
2470 case MSR_K7_CLK_CTL:
2472 * Ignore all writes to this no longer documented MSR.
2473 * Writes are only relevant for old K7 processors,
2474 * all pre-dating SVM, but a recommended workaround from
2475 * AMD for these chips. It is possible to specify the
2476 * affected processor models on the command line, hence
2477 * the need to ignore the workaround.
2480 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2481 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2482 case HV_X64_MSR_CRASH_CTL:
2483 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2484 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2485 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2486 case HV_X64_MSR_TSC_EMULATION_STATUS:
2487 return kvm_hv_set_msr_common(vcpu, msr, data,
2488 msr_info->host_initiated);
2489 case MSR_IA32_BBL_CR_CTL3:
2490 /* Drop writes to this legacy MSR -- see rdmsr
2491 * counterpart for further detail.
2493 if (report_ignored_msrs)
2494 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2497 case MSR_AMD64_OSVW_ID_LENGTH:
2498 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2500 vcpu->arch.osvw.length = data;
2502 case MSR_AMD64_OSVW_STATUS:
2503 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2505 vcpu->arch.osvw.status = data;
2507 case MSR_PLATFORM_INFO:
2508 if (!msr_info->host_initiated ||
2509 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2510 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2511 cpuid_fault_enabled(vcpu)))
2513 vcpu->arch.msr_platform_info = data;
2515 case MSR_MISC_FEATURES_ENABLES:
2516 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2517 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2518 !supports_cpuid_fault(vcpu)))
2520 vcpu->arch.msr_misc_features_enables = data;
2523 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2524 return xen_hvm_config(vcpu, data);
2525 if (kvm_pmu_is_valid_msr(vcpu, msr))
2526 return kvm_pmu_set_msr(vcpu, msr_info);
2528 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2532 if (report_ignored_msrs)
2534 "ignored wrmsr: 0x%x data 0x%llx\n",
2541 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2545 * Reads an msr value (of 'msr_index') into 'pdata'.
2546 * Returns 0 on success, non-0 otherwise.
2547 * Assumes vcpu_load() was already called.
2549 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2551 return kvm_x86_ops->get_msr(vcpu, msr);
2553 EXPORT_SYMBOL_GPL(kvm_get_msr);
2555 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2558 u64 mcg_cap = vcpu->arch.mcg_cap;
2559 unsigned bank_num = mcg_cap & 0xff;
2562 case MSR_IA32_P5_MC_ADDR:
2563 case MSR_IA32_P5_MC_TYPE:
2566 case MSR_IA32_MCG_CAP:
2567 data = vcpu->arch.mcg_cap;
2569 case MSR_IA32_MCG_CTL:
2570 if (!(mcg_cap & MCG_CTL_P) && !host)
2572 data = vcpu->arch.mcg_ctl;
2574 case MSR_IA32_MCG_STATUS:
2575 data = vcpu->arch.mcg_status;
2578 if (msr >= MSR_IA32_MC0_CTL &&
2579 msr < MSR_IA32_MCx_CTL(bank_num)) {
2580 u32 offset = msr - MSR_IA32_MC0_CTL;
2581 data = vcpu->arch.mce_banks[offset];
2590 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2592 switch (msr_info->index) {
2593 case MSR_IA32_PLATFORM_ID:
2594 case MSR_IA32_EBL_CR_POWERON:
2595 case MSR_IA32_DEBUGCTLMSR:
2596 case MSR_IA32_LASTBRANCHFROMIP:
2597 case MSR_IA32_LASTBRANCHTOIP:
2598 case MSR_IA32_LASTINTFROMIP:
2599 case MSR_IA32_LASTINTTOIP:
2601 case MSR_K8_TSEG_ADDR:
2602 case MSR_K8_TSEG_MASK:
2604 case MSR_VM_HSAVE_PA:
2605 case MSR_K8_INT_PENDING_MSG:
2606 case MSR_AMD64_NB_CFG:
2607 case MSR_FAM10H_MMIO_CONF_BASE:
2608 case MSR_AMD64_BU_CFG2:
2609 case MSR_IA32_PERF_CTL:
2610 case MSR_AMD64_DC_CFG:
2613 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
2614 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2615 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2616 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2617 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2618 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2619 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2622 case MSR_IA32_UCODE_REV:
2623 msr_info->data = vcpu->arch.microcode_version;
2626 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2629 case 0x200 ... 0x2ff:
2630 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2631 case 0xcd: /* fsb frequency */
2635 * MSR_EBC_FREQUENCY_ID
2636 * Conservative value valid for even the basic CPU models.
2637 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2638 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2639 * and 266MHz for model 3, or 4. Set Core Clock
2640 * Frequency to System Bus Frequency Ratio to 1 (bits
2641 * 31:24) even though these are only valid for CPU
2642 * models > 2, however guests may end up dividing or
2643 * multiplying by zero otherwise.
2645 case MSR_EBC_FREQUENCY_ID:
2646 msr_info->data = 1 << 24;
2648 case MSR_IA32_APICBASE:
2649 msr_info->data = kvm_get_apic_base(vcpu);
2651 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2652 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2654 case MSR_IA32_TSCDEADLINE:
2655 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2657 case MSR_IA32_TSC_ADJUST:
2658 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2660 case MSR_IA32_MISC_ENABLE:
2661 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2663 case MSR_IA32_SMBASE:
2664 if (!msr_info->host_initiated)
2666 msr_info->data = vcpu->arch.smbase;
2669 msr_info->data = vcpu->arch.smi_count;
2671 case MSR_IA32_PERF_STATUS:
2672 /* TSC increment by tick */
2673 msr_info->data = 1000ULL;
2674 /* CPU multiplier */
2675 msr_info->data |= (((uint64_t)4ULL) << 40);
2678 msr_info->data = vcpu->arch.efer;
2680 case MSR_KVM_WALL_CLOCK:
2681 case MSR_KVM_WALL_CLOCK_NEW:
2682 msr_info->data = vcpu->kvm->arch.wall_clock;
2684 case MSR_KVM_SYSTEM_TIME:
2685 case MSR_KVM_SYSTEM_TIME_NEW:
2686 msr_info->data = vcpu->arch.time;
2688 case MSR_KVM_ASYNC_PF_EN:
2689 msr_info->data = vcpu->arch.apf.msr_val;
2691 case MSR_KVM_STEAL_TIME:
2692 msr_info->data = vcpu->arch.st.msr_val;
2694 case MSR_KVM_PV_EOI_EN:
2695 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2697 case MSR_IA32_P5_MC_ADDR:
2698 case MSR_IA32_P5_MC_TYPE:
2699 case MSR_IA32_MCG_CAP:
2700 case MSR_IA32_MCG_CTL:
2701 case MSR_IA32_MCG_STATUS:
2702 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2703 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2704 msr_info->host_initiated);
2705 case MSR_K7_CLK_CTL:
2707 * Provide expected ramp-up count for K7. All other
2708 * are set to zero, indicating minimum divisors for
2711 * This prevents guest kernels on AMD host with CPU
2712 * type 6, model 8 and higher from exploding due to
2713 * the rdmsr failing.
2715 msr_info->data = 0x20000000;
2717 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2718 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2719 case HV_X64_MSR_CRASH_CTL:
2720 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2721 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2722 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2723 case HV_X64_MSR_TSC_EMULATION_STATUS:
2724 return kvm_hv_get_msr_common(vcpu,
2725 msr_info->index, &msr_info->data,
2726 msr_info->host_initiated);
2728 case MSR_IA32_BBL_CR_CTL3:
2729 /* This legacy MSR exists but isn't fully documented in current
2730 * silicon. It is however accessed by winxp in very narrow
2731 * scenarios where it sets bit #19, itself documented as
2732 * a "reserved" bit. Best effort attempt to source coherent
2733 * read data here should the balance of the register be
2734 * interpreted by the guest:
2736 * L2 cache control register 3: 64GB range, 256KB size,
2737 * enabled, latency 0x1, configured
2739 msr_info->data = 0xbe702111;
2741 case MSR_AMD64_OSVW_ID_LENGTH:
2742 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2744 msr_info->data = vcpu->arch.osvw.length;
2746 case MSR_AMD64_OSVW_STATUS:
2747 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2749 msr_info->data = vcpu->arch.osvw.status;
2751 case MSR_PLATFORM_INFO:
2752 msr_info->data = vcpu->arch.msr_platform_info;
2754 case MSR_MISC_FEATURES_ENABLES:
2755 msr_info->data = vcpu->arch.msr_misc_features_enables;
2758 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2759 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2761 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2765 if (report_ignored_msrs)
2766 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2774 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2777 * Read or write a bunch of msrs. All parameters are kernel addresses.
2779 * @return number of msrs set successfully.
2781 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2782 struct kvm_msr_entry *entries,
2783 int (*do_msr)(struct kvm_vcpu *vcpu,
2784 unsigned index, u64 *data))
2788 for (i = 0; i < msrs->nmsrs; ++i)
2789 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2796 * Read or write a bunch of msrs. Parameters are user addresses.
2798 * @return number of msrs set successfully.
2800 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2801 int (*do_msr)(struct kvm_vcpu *vcpu,
2802 unsigned index, u64 *data),
2805 struct kvm_msrs msrs;
2806 struct kvm_msr_entry *entries;
2811 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2815 if (msrs.nmsrs >= MAX_IO_MSRS)
2818 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2819 entries = memdup_user(user_msrs->entries, size);
2820 if (IS_ERR(entries)) {
2821 r = PTR_ERR(entries);
2825 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2830 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2841 static inline bool kvm_can_mwait_in_guest(void)
2843 return boot_cpu_has(X86_FEATURE_MWAIT) &&
2844 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2845 boot_cpu_has(X86_FEATURE_ARAT);
2848 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2853 case KVM_CAP_IRQCHIP:
2855 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2856 case KVM_CAP_SET_TSS_ADDR:
2857 case KVM_CAP_EXT_CPUID:
2858 case KVM_CAP_EXT_EMUL_CPUID:
2859 case KVM_CAP_CLOCKSOURCE:
2861 case KVM_CAP_NOP_IO_DELAY:
2862 case KVM_CAP_MP_STATE:
2863 case KVM_CAP_SYNC_MMU:
2864 case KVM_CAP_USER_NMI:
2865 case KVM_CAP_REINJECT_CONTROL:
2866 case KVM_CAP_IRQ_INJECT_STATUS:
2867 case KVM_CAP_IOEVENTFD:
2868 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2870 case KVM_CAP_PIT_STATE2:
2871 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2872 case KVM_CAP_XEN_HVM:
2873 case KVM_CAP_VCPU_EVENTS:
2874 case KVM_CAP_HYPERV:
2875 case KVM_CAP_HYPERV_VAPIC:
2876 case KVM_CAP_HYPERV_SPIN:
2877 case KVM_CAP_HYPERV_SYNIC:
2878 case KVM_CAP_HYPERV_SYNIC2:
2879 case KVM_CAP_HYPERV_VP_INDEX:
2880 case KVM_CAP_HYPERV_EVENTFD:
2881 case KVM_CAP_HYPERV_TLBFLUSH:
2882 case KVM_CAP_PCI_SEGMENT:
2883 case KVM_CAP_DEBUGREGS:
2884 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2886 case KVM_CAP_ASYNC_PF:
2887 case KVM_CAP_GET_TSC_KHZ:
2888 case KVM_CAP_KVMCLOCK_CTRL:
2889 case KVM_CAP_READONLY_MEM:
2890 case KVM_CAP_HYPERV_TIME:
2891 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2892 case KVM_CAP_TSC_DEADLINE_TIMER:
2893 case KVM_CAP_ENABLE_CAP_VM:
2894 case KVM_CAP_DISABLE_QUIRKS:
2895 case KVM_CAP_SET_BOOT_CPU_ID:
2896 case KVM_CAP_SPLIT_IRQCHIP:
2897 case KVM_CAP_IMMEDIATE_EXIT:
2898 case KVM_CAP_GET_MSR_FEATURES:
2901 case KVM_CAP_SYNC_REGS:
2902 r = KVM_SYNC_X86_VALID_FIELDS;
2904 case KVM_CAP_ADJUST_CLOCK:
2905 r = KVM_CLOCK_TSC_STABLE;
2907 case KVM_CAP_X86_DISABLE_EXITS:
2908 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
2909 if(kvm_can_mwait_in_guest())
2910 r |= KVM_X86_DISABLE_EXITS_MWAIT;
2912 case KVM_CAP_X86_SMM:
2913 /* SMBASE is usually relocated above 1M on modern chipsets,
2914 * and SMM handlers might indeed rely on 4G segment limits,
2915 * so do not report SMM to be available if real mode is
2916 * emulated via vm86 mode. Still, do not go to great lengths
2917 * to avoid userspace's usage of the feature, because it is a
2918 * fringe case that is not enabled except via specific settings
2919 * of the module parameters.
2921 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
2924 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2926 case KVM_CAP_NR_VCPUS:
2927 r = KVM_SOFT_MAX_VCPUS;
2929 case KVM_CAP_MAX_VCPUS:
2932 case KVM_CAP_NR_MEMSLOTS:
2933 r = KVM_USER_MEM_SLOTS;
2935 case KVM_CAP_PV_MMU: /* obsolete */
2939 r = KVM_MAX_MCE_BANKS;
2942 r = boot_cpu_has(X86_FEATURE_XSAVE);
2944 case KVM_CAP_TSC_CONTROL:
2945 r = kvm_has_tsc_control;
2947 case KVM_CAP_X2APIC_API:
2948 r = KVM_X2APIC_API_VALID_FLAGS;
2957 long kvm_arch_dev_ioctl(struct file *filp,
2958 unsigned int ioctl, unsigned long arg)
2960 void __user *argp = (void __user *)arg;
2964 case KVM_GET_MSR_INDEX_LIST: {
2965 struct kvm_msr_list __user *user_msr_list = argp;
2966 struct kvm_msr_list msr_list;
2970 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2973 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2974 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2977 if (n < msr_list.nmsrs)
2980 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2981 num_msrs_to_save * sizeof(u32)))
2983 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2985 num_emulated_msrs * sizeof(u32)))
2990 case KVM_GET_SUPPORTED_CPUID:
2991 case KVM_GET_EMULATED_CPUID: {
2992 struct kvm_cpuid2 __user *cpuid_arg = argp;
2993 struct kvm_cpuid2 cpuid;
2996 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2999 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3005 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3010 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3012 if (copy_to_user(argp, &kvm_mce_cap_supported,
3013 sizeof(kvm_mce_cap_supported)))
3017 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3018 struct kvm_msr_list __user *user_msr_list = argp;
3019 struct kvm_msr_list msr_list;
3023 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3026 msr_list.nmsrs = num_msr_based_features;
3027 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3030 if (n < msr_list.nmsrs)
3033 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3034 num_msr_based_features * sizeof(u32)))
3040 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3050 static void wbinvd_ipi(void *garbage)
3055 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3057 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3060 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3062 /* Address WBINVD may be executed by guest */
3063 if (need_emulate_wbinvd(vcpu)) {
3064 if (kvm_x86_ops->has_wbinvd_exit())
3065 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3066 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3067 smp_call_function_single(vcpu->cpu,
3068 wbinvd_ipi, NULL, 1);
3071 kvm_x86_ops->vcpu_load(vcpu, cpu);
3073 /* Apply any externally detected TSC adjustments (due to suspend) */
3074 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3075 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3076 vcpu->arch.tsc_offset_adjustment = 0;
3077 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3080 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3081 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3082 rdtsc() - vcpu->arch.last_host_tsc;
3084 mark_tsc_unstable("KVM discovered backwards TSC");
3086 if (kvm_check_tsc_unstable()) {
3087 u64 offset = kvm_compute_tsc_offset(vcpu,
3088 vcpu->arch.last_guest_tsc);
3089 kvm_vcpu_write_tsc_offset(vcpu, offset);
3090 vcpu->arch.tsc_catchup = 1;
3093 if (kvm_lapic_hv_timer_in_use(vcpu))
3094 kvm_lapic_restart_hv_timer(vcpu);
3097 * On a host with synchronized TSC, there is no need to update
3098 * kvmclock on vcpu->cpu migration
3100 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3101 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3102 if (vcpu->cpu != cpu)
3103 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3107 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3110 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3112 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3115 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
3117 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3118 &vcpu->arch.st.steal.preempted,
3119 offsetof(struct kvm_steal_time, preempted),
3120 sizeof(vcpu->arch.st.steal.preempted));
3123 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3127 if (vcpu->preempted)
3128 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3131 * Disable page faults because we're in atomic context here.
3132 * kvm_write_guest_offset_cached() would call might_fault()
3133 * that relies on pagefault_disable() to tell if there's a
3134 * bug. NOTE: the write to guest memory may not go through if
3135 * during postcopy live migration or if there's heavy guest
3138 pagefault_disable();
3140 * kvm_memslots() will be called by
3141 * kvm_write_guest_offset_cached() so take the srcu lock.
3143 idx = srcu_read_lock(&vcpu->kvm->srcu);
3144 kvm_steal_time_set_preempted(vcpu);
3145 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3147 kvm_x86_ops->vcpu_put(vcpu);
3148 vcpu->arch.last_host_tsc = rdtsc();
3150 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3151 * on every vmexit, but if not, we might have a stale dr6 from the
3152 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3157 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3158 struct kvm_lapic_state *s)
3160 if (vcpu->arch.apicv_active)
3161 kvm_x86_ops->sync_pir_to_irr(vcpu);
3163 return kvm_apic_get_state(vcpu, s);
3166 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3167 struct kvm_lapic_state *s)
3171 r = kvm_apic_set_state(vcpu, s);
3174 update_cr8_intercept(vcpu);
3179 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3181 return (!lapic_in_kernel(vcpu) ||
3182 kvm_apic_accept_pic_intr(vcpu));
3186 * if userspace requested an interrupt window, check that the
3187 * interrupt window is open.
3189 * No need to exit to userspace if we already have an interrupt queued.
3191 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3193 return kvm_arch_interrupt_allowed(vcpu) &&
3194 !kvm_cpu_has_interrupt(vcpu) &&
3195 !kvm_event_needs_reinjection(vcpu) &&
3196 kvm_cpu_accept_dm_intr(vcpu);
3199 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3200 struct kvm_interrupt *irq)
3202 if (irq->irq >= KVM_NR_INTERRUPTS)
3205 if (!irqchip_in_kernel(vcpu->kvm)) {
3206 kvm_queue_interrupt(vcpu, irq->irq, false);
3207 kvm_make_request(KVM_REQ_EVENT, vcpu);
3212 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3213 * fail for in-kernel 8259.
3215 if (pic_in_kernel(vcpu->kvm))
3218 if (vcpu->arch.pending_external_vector != -1)
3221 vcpu->arch.pending_external_vector = irq->irq;
3222 kvm_make_request(KVM_REQ_EVENT, vcpu);
3226 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3228 kvm_inject_nmi(vcpu);
3233 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3235 kvm_make_request(KVM_REQ_SMI, vcpu);
3240 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3241 struct kvm_tpr_access_ctl *tac)
3245 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3249 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3253 unsigned bank_num = mcg_cap & 0xff, bank;
3256 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3258 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3261 vcpu->arch.mcg_cap = mcg_cap;
3262 /* Init IA32_MCG_CTL to all 1s */
3263 if (mcg_cap & MCG_CTL_P)
3264 vcpu->arch.mcg_ctl = ~(u64)0;
3265 /* Init IA32_MCi_CTL to all 1s */
3266 for (bank = 0; bank < bank_num; bank++)
3267 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3269 if (kvm_x86_ops->setup_mce)
3270 kvm_x86_ops->setup_mce(vcpu);
3275 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3276 struct kvm_x86_mce *mce)
3278 u64 mcg_cap = vcpu->arch.mcg_cap;
3279 unsigned bank_num = mcg_cap & 0xff;
3280 u64 *banks = vcpu->arch.mce_banks;
3282 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3285 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3286 * reporting is disabled
3288 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3289 vcpu->arch.mcg_ctl != ~(u64)0)
3291 banks += 4 * mce->bank;
3293 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3294 * reporting is disabled for the bank
3296 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3298 if (mce->status & MCI_STATUS_UC) {
3299 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3300 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3301 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3304 if (banks[1] & MCI_STATUS_VAL)
3305 mce->status |= MCI_STATUS_OVER;
3306 banks[2] = mce->addr;
3307 banks[3] = mce->misc;
3308 vcpu->arch.mcg_status = mce->mcg_status;
3309 banks[1] = mce->status;
3310 kvm_queue_exception(vcpu, MC_VECTOR);
3311 } else if (!(banks[1] & MCI_STATUS_VAL)
3312 || !(banks[1] & MCI_STATUS_UC)) {
3313 if (banks[1] & MCI_STATUS_VAL)
3314 mce->status |= MCI_STATUS_OVER;
3315 banks[2] = mce->addr;
3316 banks[3] = mce->misc;
3317 banks[1] = mce->status;
3319 banks[1] |= MCI_STATUS_OVER;
3323 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3324 struct kvm_vcpu_events *events)
3328 * FIXME: pass injected and pending separately. This is only
3329 * needed for nested virtualization, whose state cannot be
3330 * migrated yet. For now we can combine them.
3332 events->exception.injected =
3333 (vcpu->arch.exception.pending ||
3334 vcpu->arch.exception.injected) &&
3335 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3336 events->exception.nr = vcpu->arch.exception.nr;
3337 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3338 events->exception.pad = 0;
3339 events->exception.error_code = vcpu->arch.exception.error_code;
3341 events->interrupt.injected =
3342 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3343 events->interrupt.nr = vcpu->arch.interrupt.nr;
3344 events->interrupt.soft = 0;
3345 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3347 events->nmi.injected = vcpu->arch.nmi_injected;
3348 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3349 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3350 events->nmi.pad = 0;
3352 events->sipi_vector = 0; /* never valid when reporting to user space */
3354 events->smi.smm = is_smm(vcpu);
3355 events->smi.pending = vcpu->arch.smi_pending;
3356 events->smi.smm_inside_nmi =
3357 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3358 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3360 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3361 | KVM_VCPUEVENT_VALID_SHADOW
3362 | KVM_VCPUEVENT_VALID_SMM);
3363 memset(&events->reserved, 0, sizeof(events->reserved));
3366 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3368 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3369 struct kvm_vcpu_events *events)
3371 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3372 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3373 | KVM_VCPUEVENT_VALID_SHADOW
3374 | KVM_VCPUEVENT_VALID_SMM))
3377 if (events->exception.injected &&
3378 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3379 is_guest_mode(vcpu)))
3382 /* INITs are latched while in SMM */
3383 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3384 (events->smi.smm || events->smi.pending) &&
3385 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3389 vcpu->arch.exception.injected = false;
3390 vcpu->arch.exception.pending = events->exception.injected;
3391 vcpu->arch.exception.nr = events->exception.nr;
3392 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3393 vcpu->arch.exception.error_code = events->exception.error_code;
3395 vcpu->arch.interrupt.injected = events->interrupt.injected;
3396 vcpu->arch.interrupt.nr = events->interrupt.nr;
3397 vcpu->arch.interrupt.soft = events->interrupt.soft;
3398 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3399 kvm_x86_ops->set_interrupt_shadow(vcpu,
3400 events->interrupt.shadow);
3402 vcpu->arch.nmi_injected = events->nmi.injected;
3403 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3404 vcpu->arch.nmi_pending = events->nmi.pending;
3405 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3407 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3408 lapic_in_kernel(vcpu))
3409 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3411 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3412 u32 hflags = vcpu->arch.hflags;
3413 if (events->smi.smm)
3414 hflags |= HF_SMM_MASK;
3416 hflags &= ~HF_SMM_MASK;
3417 kvm_set_hflags(vcpu, hflags);
3419 vcpu->arch.smi_pending = events->smi.pending;
3421 if (events->smi.smm) {
3422 if (events->smi.smm_inside_nmi)
3423 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3425 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3426 if (lapic_in_kernel(vcpu)) {
3427 if (events->smi.latched_init)
3428 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3430 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3435 kvm_make_request(KVM_REQ_EVENT, vcpu);
3440 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3441 struct kvm_debugregs *dbgregs)
3445 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3446 kvm_get_dr(vcpu, 6, &val);
3448 dbgregs->dr7 = vcpu->arch.dr7;
3450 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3453 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3454 struct kvm_debugregs *dbgregs)
3459 if (dbgregs->dr6 & ~0xffffffffull)
3461 if (dbgregs->dr7 & ~0xffffffffull)
3464 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3465 kvm_update_dr0123(vcpu);
3466 vcpu->arch.dr6 = dbgregs->dr6;
3467 kvm_update_dr6(vcpu);
3468 vcpu->arch.dr7 = dbgregs->dr7;
3469 kvm_update_dr7(vcpu);
3474 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3476 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3478 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3479 u64 xstate_bv = xsave->header.xfeatures;
3483 * Copy legacy XSAVE area, to avoid complications with CPUID
3484 * leaves 0 and 1 in the loop below.
3486 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3489 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3490 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3493 * Copy each region from the possibly compacted offset to the
3494 * non-compacted offset.
3496 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3498 u64 feature = valid & -valid;
3499 int index = fls64(feature) - 1;
3500 void *src = get_xsave_addr(xsave, feature);
3503 u32 size, offset, ecx, edx;
3504 cpuid_count(XSTATE_CPUID, index,
3505 &size, &offset, &ecx, &edx);
3506 if (feature == XFEATURE_MASK_PKRU)
3507 memcpy(dest + offset, &vcpu->arch.pkru,
3508 sizeof(vcpu->arch.pkru));
3510 memcpy(dest + offset, src, size);
3518 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3520 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3521 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3525 * Copy legacy XSAVE area, to avoid complications with CPUID
3526 * leaves 0 and 1 in the loop below.
3528 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3530 /* Set XSTATE_BV and possibly XCOMP_BV. */
3531 xsave->header.xfeatures = xstate_bv;
3532 if (boot_cpu_has(X86_FEATURE_XSAVES))
3533 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3536 * Copy each region from the non-compacted offset to the
3537 * possibly compacted offset.
3539 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3541 u64 feature = valid & -valid;
3542 int index = fls64(feature) - 1;
3543 void *dest = get_xsave_addr(xsave, feature);
3546 u32 size, offset, ecx, edx;
3547 cpuid_count(XSTATE_CPUID, index,
3548 &size, &offset, &ecx, &edx);
3549 if (feature == XFEATURE_MASK_PKRU)
3550 memcpy(&vcpu->arch.pkru, src + offset,
3551 sizeof(vcpu->arch.pkru));
3553 memcpy(dest, src + offset, size);
3560 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3561 struct kvm_xsave *guest_xsave)
3563 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3564 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3565 fill_xsave((u8 *) guest_xsave->region, vcpu);
3567 memcpy(guest_xsave->region,
3568 &vcpu->arch.guest_fpu.state.fxsave,
3569 sizeof(struct fxregs_state));
3570 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3571 XFEATURE_MASK_FPSSE;
3575 #define XSAVE_MXCSR_OFFSET 24
3577 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3578 struct kvm_xsave *guest_xsave)
3581 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3582 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3584 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3586 * Here we allow setting states that are not present in
3587 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3588 * with old userspace.
3590 if (xstate_bv & ~kvm_supported_xcr0() ||
3591 mxcsr & ~mxcsr_feature_mask)
3593 load_xsave(vcpu, (u8 *)guest_xsave->region);
3595 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3596 mxcsr & ~mxcsr_feature_mask)
3598 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3599 guest_xsave->region, sizeof(struct fxregs_state));
3604 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3605 struct kvm_xcrs *guest_xcrs)
3607 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3608 guest_xcrs->nr_xcrs = 0;
3612 guest_xcrs->nr_xcrs = 1;
3613 guest_xcrs->flags = 0;
3614 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3615 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3618 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3619 struct kvm_xcrs *guest_xcrs)
3623 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3626 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3629 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3630 /* Only support XCR0 currently */
3631 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3632 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3633 guest_xcrs->xcrs[i].value);
3642 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3643 * stopped by the hypervisor. This function will be called from the host only.
3644 * EINVAL is returned when the host attempts to set the flag for a guest that
3645 * does not support pv clocks.
3647 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3649 if (!vcpu->arch.pv_time_enabled)
3651 vcpu->arch.pvclock_set_guest_stopped_request = true;
3652 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3656 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3657 struct kvm_enable_cap *cap)
3663 case KVM_CAP_HYPERV_SYNIC2:
3666 case KVM_CAP_HYPERV_SYNIC:
3667 if (!irqchip_in_kernel(vcpu->kvm))
3669 return kvm_hv_activate_synic(vcpu, cap->cap ==
3670 KVM_CAP_HYPERV_SYNIC2);
3676 long kvm_arch_vcpu_ioctl(struct file *filp,
3677 unsigned int ioctl, unsigned long arg)
3679 struct kvm_vcpu *vcpu = filp->private_data;
3680 void __user *argp = (void __user *)arg;
3683 struct kvm_lapic_state *lapic;
3684 struct kvm_xsave *xsave;
3685 struct kvm_xcrs *xcrs;
3693 case KVM_GET_LAPIC: {
3695 if (!lapic_in_kernel(vcpu))
3697 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3702 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3706 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3711 case KVM_SET_LAPIC: {
3713 if (!lapic_in_kernel(vcpu))
3715 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3716 if (IS_ERR(u.lapic)) {
3717 r = PTR_ERR(u.lapic);
3721 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3724 case KVM_INTERRUPT: {
3725 struct kvm_interrupt irq;
3728 if (copy_from_user(&irq, argp, sizeof irq))
3730 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3734 r = kvm_vcpu_ioctl_nmi(vcpu);
3738 r = kvm_vcpu_ioctl_smi(vcpu);
3741 case KVM_SET_CPUID: {
3742 struct kvm_cpuid __user *cpuid_arg = argp;
3743 struct kvm_cpuid cpuid;
3746 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3748 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3751 case KVM_SET_CPUID2: {
3752 struct kvm_cpuid2 __user *cpuid_arg = argp;
3753 struct kvm_cpuid2 cpuid;
3756 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3758 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3759 cpuid_arg->entries);
3762 case KVM_GET_CPUID2: {
3763 struct kvm_cpuid2 __user *cpuid_arg = argp;
3764 struct kvm_cpuid2 cpuid;
3767 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3769 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3770 cpuid_arg->entries);
3774 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3779 case KVM_GET_MSRS: {
3780 int idx = srcu_read_lock(&vcpu->kvm->srcu);
3781 r = msr_io(vcpu, argp, do_get_msr, 1);
3782 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3785 case KVM_SET_MSRS: {
3786 int idx = srcu_read_lock(&vcpu->kvm->srcu);
3787 r = msr_io(vcpu, argp, do_set_msr, 0);
3788 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3791 case KVM_TPR_ACCESS_REPORTING: {
3792 struct kvm_tpr_access_ctl tac;
3795 if (copy_from_user(&tac, argp, sizeof tac))
3797 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3801 if (copy_to_user(argp, &tac, sizeof tac))
3806 case KVM_SET_VAPIC_ADDR: {
3807 struct kvm_vapic_addr va;
3811 if (!lapic_in_kernel(vcpu))
3814 if (copy_from_user(&va, argp, sizeof va))
3816 idx = srcu_read_lock(&vcpu->kvm->srcu);
3817 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3818 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3821 case KVM_X86_SETUP_MCE: {
3825 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3827 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3830 case KVM_X86_SET_MCE: {
3831 struct kvm_x86_mce mce;
3834 if (copy_from_user(&mce, argp, sizeof mce))
3836 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3839 case KVM_GET_VCPU_EVENTS: {
3840 struct kvm_vcpu_events events;
3842 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3845 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3850 case KVM_SET_VCPU_EVENTS: {
3851 struct kvm_vcpu_events events;
3854 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3857 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3860 case KVM_GET_DEBUGREGS: {
3861 struct kvm_debugregs dbgregs;
3863 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3866 if (copy_to_user(argp, &dbgregs,
3867 sizeof(struct kvm_debugregs)))
3872 case KVM_SET_DEBUGREGS: {
3873 struct kvm_debugregs dbgregs;
3876 if (copy_from_user(&dbgregs, argp,
3877 sizeof(struct kvm_debugregs)))
3880 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3883 case KVM_GET_XSAVE: {
3884 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3889 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3892 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3897 case KVM_SET_XSAVE: {
3898 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3899 if (IS_ERR(u.xsave)) {
3900 r = PTR_ERR(u.xsave);
3904 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3907 case KVM_GET_XCRS: {
3908 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3913 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3916 if (copy_to_user(argp, u.xcrs,
3917 sizeof(struct kvm_xcrs)))
3922 case KVM_SET_XCRS: {
3923 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3924 if (IS_ERR(u.xcrs)) {
3925 r = PTR_ERR(u.xcrs);
3929 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3932 case KVM_SET_TSC_KHZ: {
3936 user_tsc_khz = (u32)arg;
3938 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3941 if (user_tsc_khz == 0)
3942 user_tsc_khz = tsc_khz;
3944 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3949 case KVM_GET_TSC_KHZ: {
3950 r = vcpu->arch.virtual_tsc_khz;
3953 case KVM_KVMCLOCK_CTRL: {
3954 r = kvm_set_guest_paused(vcpu);
3957 case KVM_ENABLE_CAP: {
3958 struct kvm_enable_cap cap;
3961 if (copy_from_user(&cap, argp, sizeof(cap)))
3963 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3976 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3978 return VM_FAULT_SIGBUS;
3981 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3985 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3987 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3991 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3994 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
3997 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3998 u32 kvm_nr_mmu_pages)
4000 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4003 mutex_lock(&kvm->slots_lock);
4005 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4006 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4008 mutex_unlock(&kvm->slots_lock);
4012 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4014 return kvm->arch.n_max_mmu_pages;
4017 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4019 struct kvm_pic *pic = kvm->arch.vpic;
4023 switch (chip->chip_id) {
4024 case KVM_IRQCHIP_PIC_MASTER:
4025 memcpy(&chip->chip.pic, &pic->pics[0],
4026 sizeof(struct kvm_pic_state));
4028 case KVM_IRQCHIP_PIC_SLAVE:
4029 memcpy(&chip->chip.pic, &pic->pics[1],
4030 sizeof(struct kvm_pic_state));
4032 case KVM_IRQCHIP_IOAPIC:
4033 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4042 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4044 struct kvm_pic *pic = kvm->arch.vpic;
4048 switch (chip->chip_id) {
4049 case KVM_IRQCHIP_PIC_MASTER:
4050 spin_lock(&pic->lock);
4051 memcpy(&pic->pics[0], &chip->chip.pic,
4052 sizeof(struct kvm_pic_state));
4053 spin_unlock(&pic->lock);
4055 case KVM_IRQCHIP_PIC_SLAVE:
4056 spin_lock(&pic->lock);
4057 memcpy(&pic->pics[1], &chip->chip.pic,
4058 sizeof(struct kvm_pic_state));
4059 spin_unlock(&pic->lock);
4061 case KVM_IRQCHIP_IOAPIC:
4062 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4068 kvm_pic_update_irq(pic);
4072 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4074 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4076 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4078 mutex_lock(&kps->lock);
4079 memcpy(ps, &kps->channels, sizeof(*ps));
4080 mutex_unlock(&kps->lock);
4084 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4087 struct kvm_pit *pit = kvm->arch.vpit;
4089 mutex_lock(&pit->pit_state.lock);
4090 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4091 for (i = 0; i < 3; i++)
4092 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4093 mutex_unlock(&pit->pit_state.lock);
4097 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4099 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4100 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4101 sizeof(ps->channels));
4102 ps->flags = kvm->arch.vpit->pit_state.flags;
4103 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4104 memset(&ps->reserved, 0, sizeof(ps->reserved));
4108 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4112 u32 prev_legacy, cur_legacy;
4113 struct kvm_pit *pit = kvm->arch.vpit;
4115 mutex_lock(&pit->pit_state.lock);
4116 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4117 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4118 if (!prev_legacy && cur_legacy)
4120 memcpy(&pit->pit_state.channels, &ps->channels,
4121 sizeof(pit->pit_state.channels));
4122 pit->pit_state.flags = ps->flags;
4123 for (i = 0; i < 3; i++)
4124 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4126 mutex_unlock(&pit->pit_state.lock);
4130 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4131 struct kvm_reinject_control *control)
4133 struct kvm_pit *pit = kvm->arch.vpit;
4138 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4139 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4140 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4142 mutex_lock(&pit->pit_state.lock);
4143 kvm_pit_set_reinject(pit, control->pit_reinject);
4144 mutex_unlock(&pit->pit_state.lock);
4150 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4151 * @kvm: kvm instance
4152 * @log: slot id and address to which we copy the log
4154 * Steps 1-4 below provide general overview of dirty page logging. See
4155 * kvm_get_dirty_log_protect() function description for additional details.
4157 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4158 * always flush the TLB (step 4) even if previous step failed and the dirty
4159 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4160 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4161 * writes will be marked dirty for next log read.
4163 * 1. Take a snapshot of the bit and clear it if needed.
4164 * 2. Write protect the corresponding page.
4165 * 3. Copy the snapshot to the userspace.
4166 * 4. Flush TLB's if needed.
4168 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4170 bool is_dirty = false;
4173 mutex_lock(&kvm->slots_lock);
4176 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4178 if (kvm_x86_ops->flush_log_dirty)
4179 kvm_x86_ops->flush_log_dirty(kvm);
4181 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
4184 * All the TLBs can be flushed out of mmu lock, see the comments in
4185 * kvm_mmu_slot_remove_write_access().
4187 lockdep_assert_held(&kvm->slots_lock);
4189 kvm_flush_remote_tlbs(kvm);
4191 mutex_unlock(&kvm->slots_lock);
4195 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4198 if (!irqchip_in_kernel(kvm))
4201 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4202 irq_event->irq, irq_event->level,
4207 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4208 struct kvm_enable_cap *cap)
4216 case KVM_CAP_DISABLE_QUIRKS:
4217 kvm->arch.disabled_quirks = cap->args[0];
4220 case KVM_CAP_SPLIT_IRQCHIP: {
4221 mutex_lock(&kvm->lock);
4223 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4224 goto split_irqchip_unlock;
4226 if (irqchip_in_kernel(kvm))
4227 goto split_irqchip_unlock;
4228 if (kvm->created_vcpus)
4229 goto split_irqchip_unlock;
4230 r = kvm_setup_empty_irq_routing(kvm);
4232 goto split_irqchip_unlock;
4233 /* Pairs with irqchip_in_kernel. */
4235 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4236 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4238 split_irqchip_unlock:
4239 mutex_unlock(&kvm->lock);
4242 case KVM_CAP_X2APIC_API:
4244 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4247 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4248 kvm->arch.x2apic_format = true;
4249 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4250 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4254 case KVM_CAP_X86_DISABLE_EXITS:
4256 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4259 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4260 kvm_can_mwait_in_guest())
4261 kvm->arch.mwait_in_guest = true;
4262 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4263 kvm->arch.hlt_in_guest = true;
4264 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4265 kvm->arch.pause_in_guest = true;
4275 long kvm_arch_vm_ioctl(struct file *filp,
4276 unsigned int ioctl, unsigned long arg)
4278 struct kvm *kvm = filp->private_data;
4279 void __user *argp = (void __user *)arg;
4282 * This union makes it completely explicit to gcc-3.x
4283 * that these two variables' stack usage should be
4284 * combined, not added together.
4287 struct kvm_pit_state ps;
4288 struct kvm_pit_state2 ps2;
4289 struct kvm_pit_config pit_config;
4293 case KVM_SET_TSS_ADDR:
4294 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4296 case KVM_SET_IDENTITY_MAP_ADDR: {
4299 mutex_lock(&kvm->lock);
4301 if (kvm->created_vcpus)
4302 goto set_identity_unlock;
4304 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4305 goto set_identity_unlock;
4306 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4307 set_identity_unlock:
4308 mutex_unlock(&kvm->lock);
4311 case KVM_SET_NR_MMU_PAGES:
4312 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4314 case KVM_GET_NR_MMU_PAGES:
4315 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4317 case KVM_CREATE_IRQCHIP: {
4318 mutex_lock(&kvm->lock);
4321 if (irqchip_in_kernel(kvm))
4322 goto create_irqchip_unlock;
4325 if (kvm->created_vcpus)
4326 goto create_irqchip_unlock;
4328 r = kvm_pic_init(kvm);
4330 goto create_irqchip_unlock;
4332 r = kvm_ioapic_init(kvm);
4334 kvm_pic_destroy(kvm);
4335 goto create_irqchip_unlock;
4338 r = kvm_setup_default_irq_routing(kvm);
4340 kvm_ioapic_destroy(kvm);
4341 kvm_pic_destroy(kvm);
4342 goto create_irqchip_unlock;
4344 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4346 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4347 create_irqchip_unlock:
4348 mutex_unlock(&kvm->lock);
4351 case KVM_CREATE_PIT:
4352 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4354 case KVM_CREATE_PIT2:
4356 if (copy_from_user(&u.pit_config, argp,
4357 sizeof(struct kvm_pit_config)))
4360 mutex_lock(&kvm->lock);
4363 goto create_pit_unlock;
4365 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4369 mutex_unlock(&kvm->lock);
4371 case KVM_GET_IRQCHIP: {
4372 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4373 struct kvm_irqchip *chip;
4375 chip = memdup_user(argp, sizeof(*chip));
4382 if (!irqchip_kernel(kvm))
4383 goto get_irqchip_out;
4384 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4386 goto get_irqchip_out;
4388 if (copy_to_user(argp, chip, sizeof *chip))
4389 goto get_irqchip_out;
4395 case KVM_SET_IRQCHIP: {
4396 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4397 struct kvm_irqchip *chip;
4399 chip = memdup_user(argp, sizeof(*chip));
4406 if (!irqchip_kernel(kvm))
4407 goto set_irqchip_out;
4408 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4410 goto set_irqchip_out;
4418 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4421 if (!kvm->arch.vpit)
4423 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4427 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4434 if (copy_from_user(&u.ps, argp, sizeof u.ps))
4437 if (!kvm->arch.vpit)
4439 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4442 case KVM_GET_PIT2: {
4444 if (!kvm->arch.vpit)
4446 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4450 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4455 case KVM_SET_PIT2: {
4457 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4460 if (!kvm->arch.vpit)
4462 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4465 case KVM_REINJECT_CONTROL: {
4466 struct kvm_reinject_control control;
4468 if (copy_from_user(&control, argp, sizeof(control)))
4470 r = kvm_vm_ioctl_reinject(kvm, &control);
4473 case KVM_SET_BOOT_CPU_ID:
4475 mutex_lock(&kvm->lock);
4476 if (kvm->created_vcpus)
4479 kvm->arch.bsp_vcpu_id = arg;
4480 mutex_unlock(&kvm->lock);
4482 case KVM_XEN_HVM_CONFIG: {
4483 struct kvm_xen_hvm_config xhc;
4485 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4490 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4494 case KVM_SET_CLOCK: {
4495 struct kvm_clock_data user_ns;
4499 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4508 * TODO: userspace has to take care of races with VCPU_RUN, so
4509 * kvm_gen_update_masterclock() can be cut down to locked
4510 * pvclock_update_vm_gtod_copy().
4512 kvm_gen_update_masterclock(kvm);
4513 now_ns = get_kvmclock_ns(kvm);
4514 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4515 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4518 case KVM_GET_CLOCK: {
4519 struct kvm_clock_data user_ns;
4522 now_ns = get_kvmclock_ns(kvm);
4523 user_ns.clock = now_ns;
4524 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4525 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4528 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4533 case KVM_ENABLE_CAP: {
4534 struct kvm_enable_cap cap;
4537 if (copy_from_user(&cap, argp, sizeof(cap)))
4539 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4542 case KVM_MEMORY_ENCRYPT_OP: {
4544 if (kvm_x86_ops->mem_enc_op)
4545 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4548 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4549 struct kvm_enc_region region;
4552 if (copy_from_user(®ion, argp, sizeof(region)))
4556 if (kvm_x86_ops->mem_enc_reg_region)
4557 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion);
4560 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4561 struct kvm_enc_region region;
4564 if (copy_from_user(®ion, argp, sizeof(region)))
4568 if (kvm_x86_ops->mem_enc_unreg_region)
4569 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion);
4572 case KVM_HYPERV_EVENTFD: {
4573 struct kvm_hyperv_eventfd hvevfd;
4576 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4578 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4588 static void kvm_init_msr_list(void)
4593 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4594 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4598 * Even MSRs that are valid in the host may not be exposed
4599 * to the guests in some cases.
4601 switch (msrs_to_save[i]) {
4602 case MSR_IA32_BNDCFGS:
4603 if (!kvm_x86_ops->mpx_supported())
4607 if (!kvm_x86_ops->rdtscp_supported())
4615 msrs_to_save[j] = msrs_to_save[i];
4618 num_msrs_to_save = j;
4620 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4621 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4625 emulated_msrs[j] = emulated_msrs[i];
4628 num_emulated_msrs = j;
4630 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4631 struct kvm_msr_entry msr;
4633 msr.index = msr_based_features[i];
4634 if (kvm_get_msr_feature(&msr))
4638 msr_based_features[j] = msr_based_features[i];
4641 num_msr_based_features = j;
4644 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4652 if (!(lapic_in_kernel(vcpu) &&
4653 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4654 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4665 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4672 if (!(lapic_in_kernel(vcpu) &&
4673 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4675 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4677 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
4687 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4688 struct kvm_segment *var, int seg)
4690 kvm_x86_ops->set_segment(vcpu, var, seg);
4693 void kvm_get_segment(struct kvm_vcpu *vcpu,
4694 struct kvm_segment *var, int seg)
4696 kvm_x86_ops->get_segment(vcpu, var, seg);
4699 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4700 struct x86_exception *exception)
4704 BUG_ON(!mmu_is_nested(vcpu));
4706 /* NPT walks are always user-walks */
4707 access |= PFERR_USER_MASK;
4708 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4713 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4714 struct x86_exception *exception)
4716 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4717 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4720 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4721 struct x86_exception *exception)
4723 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4724 access |= PFERR_FETCH_MASK;
4725 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4728 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4729 struct x86_exception *exception)
4731 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4732 access |= PFERR_WRITE_MASK;
4733 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4736 /* uses this to access any guest's mapped memory without checking CPL */
4737 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4738 struct x86_exception *exception)
4740 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4743 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4744 struct kvm_vcpu *vcpu, u32 access,
4745 struct x86_exception *exception)
4748 int r = X86EMUL_CONTINUE;
4751 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4753 unsigned offset = addr & (PAGE_SIZE-1);
4754 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4757 if (gpa == UNMAPPED_GVA)
4758 return X86EMUL_PROPAGATE_FAULT;
4759 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4762 r = X86EMUL_IO_NEEDED;
4774 /* used for instruction fetching */
4775 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4776 gva_t addr, void *val, unsigned int bytes,
4777 struct x86_exception *exception)
4779 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4780 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4784 /* Inline kvm_read_guest_virt_helper for speed. */
4785 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4787 if (unlikely(gpa == UNMAPPED_GVA))
4788 return X86EMUL_PROPAGATE_FAULT;
4790 offset = addr & (PAGE_SIZE-1);
4791 if (WARN_ON(offset + bytes > PAGE_SIZE))
4792 bytes = (unsigned)PAGE_SIZE - offset;
4793 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4795 if (unlikely(ret < 0))
4796 return X86EMUL_IO_NEEDED;
4798 return X86EMUL_CONTINUE;
4801 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
4802 gva_t addr, void *val, unsigned int bytes,
4803 struct x86_exception *exception)
4805 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4807 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4810 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4812 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
4813 gva_t addr, void *val, unsigned int bytes,
4814 struct x86_exception *exception, bool system)
4816 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4819 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4820 access |= PFERR_USER_MASK;
4822 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
4825 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4826 unsigned long addr, void *val, unsigned int bytes)
4828 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4829 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4831 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4834 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4835 struct kvm_vcpu *vcpu, u32 access,
4836 struct x86_exception *exception)
4839 int r = X86EMUL_CONTINUE;
4842 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4845 unsigned offset = addr & (PAGE_SIZE-1);
4846 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4849 if (gpa == UNMAPPED_GVA)
4850 return X86EMUL_PROPAGATE_FAULT;
4851 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4853 r = X86EMUL_IO_NEEDED;
4865 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
4866 unsigned int bytes, struct x86_exception *exception,
4869 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4870 u32 access = PFERR_WRITE_MASK;
4872 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4873 access |= PFERR_USER_MASK;
4875 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
4879 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
4880 unsigned int bytes, struct x86_exception *exception)
4882 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
4883 PFERR_WRITE_MASK, exception);
4885 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4887 int handle_ud(struct kvm_vcpu *vcpu)
4889 int emul_type = EMULTYPE_TRAP_UD;
4890 enum emulation_result er;
4891 char sig[5]; /* ud2; .ascii "kvm" */
4892 struct x86_exception e;
4894 if (force_emulation_prefix &&
4895 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
4896 sig, sizeof(sig), &e) == 0 &&
4897 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
4898 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
4902 er = emulate_instruction(vcpu, emul_type);
4903 if (er == EMULATE_USER_EXIT)
4905 if (er != EMULATE_DONE)
4906 kvm_queue_exception(vcpu, UD_VECTOR);
4909 EXPORT_SYMBOL_GPL(handle_ud);
4911 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4912 gpa_t gpa, bool write)
4914 /* For APIC access vmexit */
4915 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4918 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4919 trace_vcpu_match_mmio(gva, gpa, write, true);
4926 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4927 gpa_t *gpa, struct x86_exception *exception,
4930 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4931 | (write ? PFERR_WRITE_MASK : 0);
4934 * currently PKRU is only applied to ept enabled guest so
4935 * there is no pkey in EPT page table for L1 guest or EPT
4936 * shadow page table for L2 guest.
4938 if (vcpu_match_mmio_gva(vcpu, gva)
4939 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4940 vcpu->arch.access, 0, access)) {
4941 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4942 (gva & (PAGE_SIZE - 1));
4943 trace_vcpu_match_mmio(gva, *gpa, write, false);
4947 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4949 if (*gpa == UNMAPPED_GVA)
4952 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
4955 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4956 const void *val, int bytes)
4960 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4963 kvm_page_track_write(vcpu, gpa, val, bytes);
4967 struct read_write_emulator_ops {
4968 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4970 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4971 void *val, int bytes);
4972 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4973 int bytes, void *val);
4974 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4975 void *val, int bytes);
4979 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4981 if (vcpu->mmio_read_completed) {
4982 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4983 vcpu->mmio_fragments[0].gpa, val);
4984 vcpu->mmio_read_completed = 0;
4991 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4992 void *val, int bytes)
4994 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4997 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4998 void *val, int bytes)
5000 return emulator_write_phys(vcpu, gpa, val, bytes);
5003 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5005 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5006 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5009 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5010 void *val, int bytes)
5012 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5013 return X86EMUL_IO_NEEDED;
5016 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5017 void *val, int bytes)
5019 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5021 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5022 return X86EMUL_CONTINUE;
5025 static const struct read_write_emulator_ops read_emultor = {
5026 .read_write_prepare = read_prepare,
5027 .read_write_emulate = read_emulate,
5028 .read_write_mmio = vcpu_mmio_read,
5029 .read_write_exit_mmio = read_exit_mmio,
5032 static const struct read_write_emulator_ops write_emultor = {
5033 .read_write_emulate = write_emulate,
5034 .read_write_mmio = write_mmio,
5035 .read_write_exit_mmio = write_exit_mmio,
5039 static int emulator_read_write_onepage(unsigned long addr, void *val,
5041 struct x86_exception *exception,
5042 struct kvm_vcpu *vcpu,
5043 const struct read_write_emulator_ops *ops)
5047 bool write = ops->write;
5048 struct kvm_mmio_fragment *frag;
5049 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5052 * If the exit was due to a NPF we may already have a GPA.
5053 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5054 * Note, this cannot be used on string operations since string
5055 * operation using rep will only have the initial GPA from the NPF
5058 if (vcpu->arch.gpa_available &&
5059 emulator_can_use_gpa(ctxt) &&
5060 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5061 gpa = vcpu->arch.gpa_val;
5062 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5064 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5066 return X86EMUL_PROPAGATE_FAULT;
5069 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5070 return X86EMUL_CONTINUE;
5073 * Is this MMIO handled locally?
5075 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5076 if (handled == bytes)
5077 return X86EMUL_CONTINUE;
5083 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5084 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5088 return X86EMUL_CONTINUE;
5091 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5093 void *val, unsigned int bytes,
5094 struct x86_exception *exception,
5095 const struct read_write_emulator_ops *ops)
5097 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5101 if (ops->read_write_prepare &&
5102 ops->read_write_prepare(vcpu, val, bytes))
5103 return X86EMUL_CONTINUE;
5105 vcpu->mmio_nr_fragments = 0;
5107 /* Crossing a page boundary? */
5108 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5111 now = -addr & ~PAGE_MASK;
5112 rc = emulator_read_write_onepage(addr, val, now, exception,
5115 if (rc != X86EMUL_CONTINUE)
5118 if (ctxt->mode != X86EMUL_MODE_PROT64)
5124 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5126 if (rc != X86EMUL_CONTINUE)
5129 if (!vcpu->mmio_nr_fragments)
5132 gpa = vcpu->mmio_fragments[0].gpa;
5134 vcpu->mmio_needed = 1;
5135 vcpu->mmio_cur_fragment = 0;
5137 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5138 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5139 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5140 vcpu->run->mmio.phys_addr = gpa;
5142 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5145 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5149 struct x86_exception *exception)
5151 return emulator_read_write(ctxt, addr, val, bytes,
5152 exception, &read_emultor);
5155 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5159 struct x86_exception *exception)
5161 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5162 exception, &write_emultor);
5165 #define CMPXCHG_TYPE(t, ptr, old, new) \
5166 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5168 #ifdef CONFIG_X86_64
5169 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5171 # define CMPXCHG64(ptr, old, new) \
5172 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5175 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5180 struct x86_exception *exception)
5182 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5188 /* guests cmpxchg8b have to be emulated atomically */
5189 if (bytes > 8 || (bytes & (bytes - 1)))
5192 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5194 if (gpa == UNMAPPED_GVA ||
5195 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5198 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5201 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
5202 if (is_error_page(page))
5205 kaddr = kmap_atomic(page);
5206 kaddr += offset_in_page(gpa);
5209 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5212 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5215 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5218 exchanged = CMPXCHG64(kaddr, old, new);
5223 kunmap_atomic(kaddr);
5224 kvm_release_page_dirty(page);
5227 return X86EMUL_CMPXCHG_FAILED;
5229 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5230 kvm_page_track_write(vcpu, gpa, new, bytes);
5232 return X86EMUL_CONTINUE;
5235 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5237 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5240 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5244 for (i = 0; i < vcpu->arch.pio.count; i++) {
5245 if (vcpu->arch.pio.in)
5246 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5247 vcpu->arch.pio.size, pd);
5249 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5250 vcpu->arch.pio.port, vcpu->arch.pio.size,
5254 pd += vcpu->arch.pio.size;
5259 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5260 unsigned short port, void *val,
5261 unsigned int count, bool in)
5263 vcpu->arch.pio.port = port;
5264 vcpu->arch.pio.in = in;
5265 vcpu->arch.pio.count = count;
5266 vcpu->arch.pio.size = size;
5268 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5269 vcpu->arch.pio.count = 0;
5273 vcpu->run->exit_reason = KVM_EXIT_IO;
5274 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5275 vcpu->run->io.size = size;
5276 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5277 vcpu->run->io.count = count;
5278 vcpu->run->io.port = port;
5283 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5284 int size, unsigned short port, void *val,
5287 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5290 if (vcpu->arch.pio.count)
5293 memset(vcpu->arch.pio_data, 0, size * count);
5295 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5298 memcpy(val, vcpu->arch.pio_data, size * count);
5299 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5300 vcpu->arch.pio.count = 0;
5307 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5308 int size, unsigned short port,
5309 const void *val, unsigned int count)
5311 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5313 memcpy(vcpu->arch.pio_data, val, size * count);
5314 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5315 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5318 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5320 return kvm_x86_ops->get_segment_base(vcpu, seg);
5323 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5325 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5328 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5330 if (!need_emulate_wbinvd(vcpu))
5331 return X86EMUL_CONTINUE;
5333 if (kvm_x86_ops->has_wbinvd_exit()) {
5334 int cpu = get_cpu();
5336 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5337 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5338 wbinvd_ipi, NULL, 1);
5340 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5343 return X86EMUL_CONTINUE;
5346 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5348 kvm_emulate_wbinvd_noskip(vcpu);
5349 return kvm_skip_emulated_instruction(vcpu);
5351 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5355 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5357 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5360 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5361 unsigned long *dest)
5363 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5366 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5367 unsigned long value)
5370 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5373 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5375 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5378 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5380 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5381 unsigned long value;
5385 value = kvm_read_cr0(vcpu);
5388 value = vcpu->arch.cr2;
5391 value = kvm_read_cr3(vcpu);
5394 value = kvm_read_cr4(vcpu);
5397 value = kvm_get_cr8(vcpu);
5400 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5407 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5409 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5414 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5417 vcpu->arch.cr2 = val;
5420 res = kvm_set_cr3(vcpu, val);
5423 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5426 res = kvm_set_cr8(vcpu, val);
5429 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5436 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5438 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5441 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5443 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5446 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5448 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5451 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5453 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5456 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5458 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5461 static unsigned long emulator_get_cached_segment_base(
5462 struct x86_emulate_ctxt *ctxt, int seg)
5464 return get_segment_base(emul_to_vcpu(ctxt), seg);
5467 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5468 struct desc_struct *desc, u32 *base3,
5471 struct kvm_segment var;
5473 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5474 *selector = var.selector;
5477 memset(desc, 0, sizeof(*desc));
5485 set_desc_limit(desc, var.limit);
5486 set_desc_base(desc, (unsigned long)var.base);
5487 #ifdef CONFIG_X86_64
5489 *base3 = var.base >> 32;
5491 desc->type = var.type;
5493 desc->dpl = var.dpl;
5494 desc->p = var.present;
5495 desc->avl = var.avl;
5503 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5504 struct desc_struct *desc, u32 base3,
5507 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5508 struct kvm_segment var;
5510 var.selector = selector;
5511 var.base = get_desc_base(desc);
5512 #ifdef CONFIG_X86_64
5513 var.base |= ((u64)base3) << 32;
5515 var.limit = get_desc_limit(desc);
5517 var.limit = (var.limit << 12) | 0xfff;
5518 var.type = desc->type;
5519 var.dpl = desc->dpl;
5524 var.avl = desc->avl;
5525 var.present = desc->p;
5526 var.unusable = !var.present;
5529 kvm_set_segment(vcpu, &var, seg);
5533 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5534 u32 msr_index, u64 *pdata)
5536 struct msr_data msr;
5539 msr.index = msr_index;
5540 msr.host_initiated = false;
5541 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5549 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5550 u32 msr_index, u64 data)
5552 struct msr_data msr;
5555 msr.index = msr_index;
5556 msr.host_initiated = false;
5557 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5560 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5562 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5564 return vcpu->arch.smbase;
5567 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5569 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5571 vcpu->arch.smbase = smbase;
5574 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5577 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5580 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5581 u32 pmc, u64 *pdata)
5583 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5586 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5588 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5591 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5592 struct x86_instruction_info *info,
5593 enum x86_intercept_stage stage)
5595 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5598 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5599 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
5601 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
5604 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5606 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5609 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5611 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5614 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5616 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5619 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5621 return emul_to_vcpu(ctxt)->arch.hflags;
5624 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5626 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5629 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5631 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5634 static const struct x86_emulate_ops emulate_ops = {
5635 .read_gpr = emulator_read_gpr,
5636 .write_gpr = emulator_write_gpr,
5637 .read_std = emulator_read_std,
5638 .write_std = emulator_write_std,
5639 .read_phys = kvm_read_guest_phys_system,
5640 .fetch = kvm_fetch_guest_virt,
5641 .read_emulated = emulator_read_emulated,
5642 .write_emulated = emulator_write_emulated,
5643 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5644 .invlpg = emulator_invlpg,
5645 .pio_in_emulated = emulator_pio_in_emulated,
5646 .pio_out_emulated = emulator_pio_out_emulated,
5647 .get_segment = emulator_get_segment,
5648 .set_segment = emulator_set_segment,
5649 .get_cached_segment_base = emulator_get_cached_segment_base,
5650 .get_gdt = emulator_get_gdt,
5651 .get_idt = emulator_get_idt,
5652 .set_gdt = emulator_set_gdt,
5653 .set_idt = emulator_set_idt,
5654 .get_cr = emulator_get_cr,
5655 .set_cr = emulator_set_cr,
5656 .cpl = emulator_get_cpl,
5657 .get_dr = emulator_get_dr,
5658 .set_dr = emulator_set_dr,
5659 .get_smbase = emulator_get_smbase,
5660 .set_smbase = emulator_set_smbase,
5661 .set_msr = emulator_set_msr,
5662 .get_msr = emulator_get_msr,
5663 .check_pmc = emulator_check_pmc,
5664 .read_pmc = emulator_read_pmc,
5665 .halt = emulator_halt,
5666 .wbinvd = emulator_wbinvd,
5667 .fix_hypercall = emulator_fix_hypercall,
5668 .intercept = emulator_intercept,
5669 .get_cpuid = emulator_get_cpuid,
5670 .set_nmi_mask = emulator_set_nmi_mask,
5671 .get_hflags = emulator_get_hflags,
5672 .set_hflags = emulator_set_hflags,
5673 .pre_leave_smm = emulator_pre_leave_smm,
5676 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5678 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5680 * an sti; sti; sequence only disable interrupts for the first
5681 * instruction. So, if the last instruction, be it emulated or
5682 * not, left the system with the INT_STI flag enabled, it
5683 * means that the last instruction is an sti. We should not
5684 * leave the flag on in this case. The same goes for mov ss
5686 if (int_shadow & mask)
5688 if (unlikely(int_shadow || mask)) {
5689 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5691 kvm_make_request(KVM_REQ_EVENT, vcpu);
5695 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5697 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5698 if (ctxt->exception.vector == PF_VECTOR)
5699 return kvm_propagate_fault(vcpu, &ctxt->exception);
5701 if (ctxt->exception.error_code_valid)
5702 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5703 ctxt->exception.error_code);
5705 kvm_queue_exception(vcpu, ctxt->exception.vector);
5709 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5711 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5714 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5716 ctxt->eflags = kvm_get_rflags(vcpu);
5717 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5719 ctxt->eip = kvm_rip_read(vcpu);
5720 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5721 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5722 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5723 cs_db ? X86EMUL_MODE_PROT32 :
5724 X86EMUL_MODE_PROT16;
5725 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5726 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5727 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5729 init_decode_cache(ctxt);
5730 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5733 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5735 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5738 init_emulate_ctxt(vcpu);
5742 ctxt->_eip = ctxt->eip + inc_eip;
5743 ret = emulate_int_real(ctxt, irq);
5745 if (ret != X86EMUL_CONTINUE)
5746 return EMULATE_FAIL;
5748 ctxt->eip = ctxt->_eip;
5749 kvm_rip_write(vcpu, ctxt->eip);
5750 kvm_set_rflags(vcpu, ctxt->eflags);
5752 return EMULATE_DONE;
5754 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5756 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
5758 int r = EMULATE_DONE;
5760 ++vcpu->stat.insn_emulation_fail;
5761 trace_kvm_emulate_insn_failed(vcpu);
5763 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5764 return EMULATE_FAIL;
5766 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5767 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5768 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5769 vcpu->run->internal.ndata = 0;
5770 r = EMULATE_USER_EXIT;
5773 kvm_queue_exception(vcpu, UD_VECTOR);
5778 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5779 bool write_fault_to_shadow_pgtable,
5785 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5788 if (!vcpu->arch.mmu.direct_map) {
5790 * Write permission should be allowed since only
5791 * write access need to be emulated.
5793 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5796 * If the mapping is invalid in guest, let cpu retry
5797 * it to generate fault.
5799 if (gpa == UNMAPPED_GVA)
5804 * Do not retry the unhandleable instruction if it faults on the
5805 * readonly host memory, otherwise it will goto a infinite loop:
5806 * retry instruction -> write #PF -> emulation fail -> retry
5807 * instruction -> ...
5809 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5812 * If the instruction failed on the error pfn, it can not be fixed,
5813 * report the error to userspace.
5815 if (is_error_noslot_pfn(pfn))
5818 kvm_release_pfn_clean(pfn);
5820 /* The instructions are well-emulated on direct mmu. */
5821 if (vcpu->arch.mmu.direct_map) {
5822 unsigned int indirect_shadow_pages;
5824 spin_lock(&vcpu->kvm->mmu_lock);
5825 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5826 spin_unlock(&vcpu->kvm->mmu_lock);
5828 if (indirect_shadow_pages)
5829 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5835 * if emulation was due to access to shadowed page table
5836 * and it failed try to unshadow page and re-enter the
5837 * guest to let CPU execute the instruction.
5839 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5842 * If the access faults on its page table, it can not
5843 * be fixed by unprotecting shadow page and it should
5844 * be reported to userspace.
5846 return !write_fault_to_shadow_pgtable;
5849 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5850 unsigned long cr2, int emulation_type)
5852 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5853 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5855 last_retry_eip = vcpu->arch.last_retry_eip;
5856 last_retry_addr = vcpu->arch.last_retry_addr;
5859 * If the emulation is caused by #PF and it is non-page_table
5860 * writing instruction, it means the VM-EXIT is caused by shadow
5861 * page protected, we can zap the shadow page and retry this
5862 * instruction directly.
5864 * Note: if the guest uses a non-page-table modifying instruction
5865 * on the PDE that points to the instruction, then we will unmap
5866 * the instruction and go to an infinite loop. So, we cache the
5867 * last retried eip and the last fault address, if we meet the eip
5868 * and the address again, we can break out of the potential infinite
5871 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5873 if (!(emulation_type & EMULTYPE_RETRY))
5876 if (x86_page_table_writing_insn(ctxt))
5879 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5882 vcpu->arch.last_retry_eip = ctxt->eip;
5883 vcpu->arch.last_retry_addr = cr2;
5885 if (!vcpu->arch.mmu.direct_map)
5886 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5888 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5893 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5894 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5896 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5898 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5899 /* This is a good place to trace that we are exiting SMM. */
5900 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5902 /* Process a latched INIT or SMI, if any. */
5903 kvm_make_request(KVM_REQ_EVENT, vcpu);
5906 kvm_mmu_reset_context(vcpu);
5909 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5911 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5913 vcpu->arch.hflags = emul_flags;
5915 if (changed & HF_SMM_MASK)
5916 kvm_smm_changed(vcpu);
5919 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5928 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5929 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5934 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
5936 struct kvm_run *kvm_run = vcpu->run;
5938 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5939 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5940 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5941 kvm_run->debug.arch.exception = DB_VECTOR;
5942 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5943 *r = EMULATE_USER_EXIT;
5946 * "Certain debug exceptions may clear bit 0-3. The
5947 * remaining contents of the DR6 register are never
5948 * cleared by the processor".
5950 vcpu->arch.dr6 &= ~15;
5951 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5952 kvm_queue_exception(vcpu, DB_VECTOR);
5956 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5958 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5959 int r = EMULATE_DONE;
5961 kvm_x86_ops->skip_emulated_instruction(vcpu);
5964 * rflags is the old, "raw" value of the flags. The new value has
5965 * not been saved yet.
5967 * This is correct even for TF set by the guest, because "the
5968 * processor will not generate this exception after the instruction
5969 * that sets the TF flag".
5971 if (unlikely(rflags & X86_EFLAGS_TF))
5972 kvm_vcpu_do_singlestep(vcpu, &r);
5973 return r == EMULATE_DONE;
5975 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5977 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5979 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5980 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5981 struct kvm_run *kvm_run = vcpu->run;
5982 unsigned long eip = kvm_get_linear_rip(vcpu);
5983 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5984 vcpu->arch.guest_debug_dr7,
5988 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5989 kvm_run->debug.arch.pc = eip;
5990 kvm_run->debug.arch.exception = DB_VECTOR;
5991 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5992 *r = EMULATE_USER_EXIT;
5997 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5998 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5999 unsigned long eip = kvm_get_linear_rip(vcpu);
6000 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6005 vcpu->arch.dr6 &= ~15;
6006 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6007 kvm_queue_exception(vcpu, DB_VECTOR);
6016 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6018 switch (ctxt->opcode_len) {
6025 case 0xe6: /* OUT */
6029 case 0x6c: /* INS */
6031 case 0x6e: /* OUTS */
6038 case 0x33: /* RDPMC */
6047 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6054 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6055 bool writeback = true;
6056 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6059 * Clear write_fault_to_shadow_pgtable here to ensure it is
6062 vcpu->arch.write_fault_to_shadow_pgtable = false;
6063 kvm_clear_exception_queue(vcpu);
6065 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6066 init_emulate_ctxt(vcpu);
6069 * We will reenter on the same instruction since
6070 * we do not set complete_userspace_io. This does not
6071 * handle watchpoints yet, those would be handled in
6074 if (!(emulation_type & EMULTYPE_SKIP) &&
6075 kvm_vcpu_check_breakpoint(vcpu, &r))
6078 ctxt->interruptibility = 0;
6079 ctxt->have_exception = false;
6080 ctxt->exception.vector = -1;
6081 ctxt->perm_ok = false;
6083 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6085 r = x86_decode_insn(ctxt, insn, insn_len);
6087 trace_kvm_emulate_insn_start(vcpu);
6088 ++vcpu->stat.insn_emulation;
6089 if (r != EMULATION_OK) {
6090 if (emulation_type & EMULTYPE_TRAP_UD)
6091 return EMULATE_FAIL;
6092 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6094 return EMULATE_DONE;
6095 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6096 return EMULATE_DONE;
6097 if (emulation_type & EMULTYPE_SKIP)
6098 return EMULATE_FAIL;
6099 return handle_emulation_failure(vcpu, emulation_type);
6103 if ((emulation_type & EMULTYPE_VMWARE) &&
6104 !is_vmware_backdoor_opcode(ctxt))
6105 return EMULATE_FAIL;
6107 if (emulation_type & EMULTYPE_SKIP) {
6108 kvm_rip_write(vcpu, ctxt->_eip);
6109 if (ctxt->eflags & X86_EFLAGS_RF)
6110 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6111 return EMULATE_DONE;
6114 if (retry_instruction(ctxt, cr2, emulation_type))
6115 return EMULATE_DONE;
6117 /* this is needed for vmware backdoor interface to work since it
6118 changes registers values during IO operation */
6119 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6120 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6121 emulator_invalidate_register_cache(ctxt);
6125 /* Save the faulting GPA (cr2) in the address field */
6126 ctxt->exception.address = cr2;
6128 r = x86_emulate_insn(ctxt);
6130 if (r == EMULATION_INTERCEPTED)
6131 return EMULATE_DONE;
6133 if (r == EMULATION_FAILED) {
6134 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6136 return EMULATE_DONE;
6138 return handle_emulation_failure(vcpu, emulation_type);
6141 if (ctxt->have_exception) {
6143 if (inject_emulated_exception(vcpu))
6145 } else if (vcpu->arch.pio.count) {
6146 if (!vcpu->arch.pio.in) {
6147 /* FIXME: return into emulator if single-stepping. */
6148 vcpu->arch.pio.count = 0;
6151 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6153 r = EMULATE_USER_EXIT;
6154 } else if (vcpu->mmio_needed) {
6155 if (!vcpu->mmio_is_write)
6157 r = EMULATE_USER_EXIT;
6158 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6159 } else if (r == EMULATION_RESTART)
6165 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6166 toggle_interruptibility(vcpu, ctxt->interruptibility);
6167 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6168 kvm_rip_write(vcpu, ctxt->eip);
6169 if (r == EMULATE_DONE &&
6170 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6171 kvm_vcpu_do_singlestep(vcpu, &r);
6172 if (!ctxt->have_exception ||
6173 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6174 __kvm_set_rflags(vcpu, ctxt->eflags);
6177 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6178 * do nothing, and it will be requested again as soon as
6179 * the shadow expires. But we still need to check here,
6180 * because POPF has no interrupt shadow.
6182 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6183 kvm_make_request(KVM_REQ_EVENT, vcpu);
6185 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6189 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
6191 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6192 unsigned short port)
6194 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
6195 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6196 size, port, &val, 1);
6197 /* do not return to emulator after return from userspace */
6198 vcpu->arch.pio.count = 0;
6202 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6206 /* We should only ever be called with arch.pio.count equal to 1 */
6207 BUG_ON(vcpu->arch.pio.count != 1);
6209 /* For size less than 4 we merge, else we zero extend */
6210 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6214 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6215 * the copy and tracing
6217 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6218 vcpu->arch.pio.port, &val, 1);
6219 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6224 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6225 unsigned short port)
6230 /* For size less than 4 we merge, else we zero extend */
6231 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6233 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6236 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6240 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6245 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6247 int ret = kvm_skip_emulated_instruction(vcpu);
6250 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6251 * KVM_EXIT_DEBUG here.
6254 return kvm_fast_pio_in(vcpu, size, port) && ret;
6256 return kvm_fast_pio_out(vcpu, size, port) && ret;
6258 EXPORT_SYMBOL_GPL(kvm_fast_pio);
6260 static int kvmclock_cpu_down_prep(unsigned int cpu)
6262 __this_cpu_write(cpu_tsc_khz, 0);
6266 static void tsc_khz_changed(void *data)
6268 struct cpufreq_freqs *freq = data;
6269 unsigned long khz = 0;
6273 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6274 khz = cpufreq_quick_get(raw_smp_processor_id());
6277 __this_cpu_write(cpu_tsc_khz, khz);
6280 #ifdef CONFIG_X86_64
6281 static void kvm_hyperv_tsc_notifier(void)
6284 struct kvm_vcpu *vcpu;
6287 spin_lock(&kvm_lock);
6288 list_for_each_entry(kvm, &vm_list, vm_list)
6289 kvm_make_mclock_inprogress_request(kvm);
6291 hyperv_stop_tsc_emulation();
6293 /* TSC frequency always matches when on Hyper-V */
6294 for_each_present_cpu(cpu)
6295 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6296 kvm_max_guest_tsc_khz = tsc_khz;
6298 list_for_each_entry(kvm, &vm_list, vm_list) {
6299 struct kvm_arch *ka = &kvm->arch;
6301 spin_lock(&ka->pvclock_gtod_sync_lock);
6303 pvclock_update_vm_gtod_copy(kvm);
6305 kvm_for_each_vcpu(cpu, vcpu, kvm)
6306 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6308 kvm_for_each_vcpu(cpu, vcpu, kvm)
6309 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6311 spin_unlock(&ka->pvclock_gtod_sync_lock);
6313 spin_unlock(&kvm_lock);
6317 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6320 struct cpufreq_freqs *freq = data;
6322 struct kvm_vcpu *vcpu;
6323 int i, send_ipi = 0;
6326 * We allow guests to temporarily run on slowing clocks,
6327 * provided we notify them after, or to run on accelerating
6328 * clocks, provided we notify them before. Thus time never
6331 * However, we have a problem. We can't atomically update
6332 * the frequency of a given CPU from this function; it is
6333 * merely a notifier, which can be called from any CPU.
6334 * Changing the TSC frequency at arbitrary points in time
6335 * requires a recomputation of local variables related to
6336 * the TSC for each VCPU. We must flag these local variables
6337 * to be updated and be sure the update takes place with the
6338 * new frequency before any guests proceed.
6340 * Unfortunately, the combination of hotplug CPU and frequency
6341 * change creates an intractable locking scenario; the order
6342 * of when these callouts happen is undefined with respect to
6343 * CPU hotplug, and they can race with each other. As such,
6344 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6345 * undefined; you can actually have a CPU frequency change take
6346 * place in between the computation of X and the setting of the
6347 * variable. To protect against this problem, all updates of
6348 * the per_cpu tsc_khz variable are done in an interrupt
6349 * protected IPI, and all callers wishing to update the value
6350 * must wait for a synchronous IPI to complete (which is trivial
6351 * if the caller is on the CPU already). This establishes the
6352 * necessary total order on variable updates.
6354 * Note that because a guest time update may take place
6355 * anytime after the setting of the VCPU's request bit, the
6356 * correct TSC value must be set before the request. However,
6357 * to ensure the update actually makes it to any guest which
6358 * starts running in hardware virtualization between the set
6359 * and the acquisition of the spinlock, we must also ping the
6360 * CPU after setting the request bit.
6364 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6366 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6369 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6371 spin_lock(&kvm_lock);
6372 list_for_each_entry(kvm, &vm_list, vm_list) {
6373 kvm_for_each_vcpu(i, vcpu, kvm) {
6374 if (vcpu->cpu != freq->cpu)
6376 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6377 if (vcpu->cpu != smp_processor_id())
6381 spin_unlock(&kvm_lock);
6383 if (freq->old < freq->new && send_ipi) {
6385 * We upscale the frequency. Must make the guest
6386 * doesn't see old kvmclock values while running with
6387 * the new frequency, otherwise we risk the guest sees
6388 * time go backwards.
6390 * In case we update the frequency for another cpu
6391 * (which might be in guest context) send an interrupt
6392 * to kick the cpu out of guest context. Next time
6393 * guest context is entered kvmclock will be updated,
6394 * so the guest will not see stale values.
6396 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6401 static struct notifier_block kvmclock_cpufreq_notifier_block = {
6402 .notifier_call = kvmclock_cpufreq_notifier
6405 static int kvmclock_cpu_online(unsigned int cpu)
6407 tsc_khz_changed(NULL);
6411 static void kvm_timer_init(void)
6413 max_tsc_khz = tsc_khz;
6415 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
6416 #ifdef CONFIG_CPU_FREQ
6417 struct cpufreq_policy policy;
6420 memset(&policy, 0, sizeof(policy));
6422 cpufreq_get_policy(&policy, cpu);
6423 if (policy.cpuinfo.max_freq)
6424 max_tsc_khz = policy.cpuinfo.max_freq;
6427 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6428 CPUFREQ_TRANSITION_NOTIFIER);
6430 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
6432 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6433 kvmclock_cpu_online, kvmclock_cpu_down_prep);
6436 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6437 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
6439 int kvm_is_in_guest(void)
6441 return __this_cpu_read(current_vcpu) != NULL;
6444 static int kvm_is_user_mode(void)
6448 if (__this_cpu_read(current_vcpu))
6449 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6451 return user_mode != 0;
6454 static unsigned long kvm_get_guest_ip(void)
6456 unsigned long ip = 0;
6458 if (__this_cpu_read(current_vcpu))
6459 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6464 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6465 .is_in_guest = kvm_is_in_guest,
6466 .is_user_mode = kvm_is_user_mode,
6467 .get_guest_ip = kvm_get_guest_ip,
6470 static void kvm_set_mmio_spte_mask(void)
6473 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6476 * Set the reserved bits and the present bit of an paging-structure
6477 * entry to generate page fault with PFER.RSV = 1.
6479 /* Mask the reserved physical address bits. */
6480 mask = rsvd_bits(maxphyaddr, 51);
6482 /* Set the present bit. */
6485 #ifdef CONFIG_X86_64
6487 * If reserved bit is not supported, clear the present bit to disable
6490 if (maxphyaddr == 52)
6494 kvm_mmu_set_mmio_spte_mask(mask, mask);
6497 #ifdef CONFIG_X86_64
6498 static void pvclock_gtod_update_fn(struct work_struct *work)
6502 struct kvm_vcpu *vcpu;
6505 spin_lock(&kvm_lock);
6506 list_for_each_entry(kvm, &vm_list, vm_list)
6507 kvm_for_each_vcpu(i, vcpu, kvm)
6508 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6509 atomic_set(&kvm_guest_has_master_clock, 0);
6510 spin_unlock(&kvm_lock);
6513 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6516 * Notification about pvclock gtod data update.
6518 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6521 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6522 struct timekeeper *tk = priv;
6524 update_pvclock_gtod(tk);
6526 /* disable master clock if host does not trust, or does not
6527 * use, TSC based clocksource.
6529 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
6530 atomic_read(&kvm_guest_has_master_clock) != 0)
6531 queue_work(system_long_wq, &pvclock_gtod_work);
6536 static struct notifier_block pvclock_gtod_notifier = {
6537 .notifier_call = pvclock_gtod_notify,
6541 int kvm_arch_init(void *opaque)
6544 struct kvm_x86_ops *ops = opaque;
6547 printk(KERN_ERR "kvm: already loaded the other module\n");
6552 if (!ops->cpu_has_kvm_support()) {
6553 printk(KERN_ERR "kvm: no hardware support\n");
6557 if (ops->disabled_by_bios()) {
6558 printk(KERN_ERR "kvm: disabled by bios\n");
6564 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6566 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6570 r = kvm_mmu_module_init();
6572 goto out_free_percpu;
6574 kvm_set_mmio_spte_mask();
6578 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
6579 PT_DIRTY_MASK, PT64_NX_MASK, 0,
6580 PT_PRESENT_MASK, 0, sme_me_mask);
6583 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6585 if (boot_cpu_has(X86_FEATURE_XSAVE))
6586 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6589 #ifdef CONFIG_X86_64
6590 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6592 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
6593 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
6599 free_percpu(shared_msrs);
6604 void kvm_arch_exit(void)
6606 #ifdef CONFIG_X86_64
6607 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
6608 clear_hv_tscchange_cb();
6611 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6613 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6614 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6615 CPUFREQ_TRANSITION_NOTIFIER);
6616 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
6617 #ifdef CONFIG_X86_64
6618 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6621 kvm_mmu_module_exit();
6622 free_percpu(shared_msrs);
6625 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
6627 ++vcpu->stat.halt_exits;
6628 if (lapic_in_kernel(vcpu)) {
6629 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
6632 vcpu->run->exit_reason = KVM_EXIT_HLT;
6636 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6638 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6640 int ret = kvm_skip_emulated_instruction(vcpu);
6642 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6643 * KVM_EXIT_DEBUG here.
6645 return kvm_vcpu_halt(vcpu) && ret;
6647 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6649 #ifdef CONFIG_X86_64
6650 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6651 unsigned long clock_type)
6653 struct kvm_clock_pairing clock_pairing;
6654 struct timespec64 ts;
6658 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6659 return -KVM_EOPNOTSUPP;
6661 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6662 return -KVM_EOPNOTSUPP;
6664 clock_pairing.sec = ts.tv_sec;
6665 clock_pairing.nsec = ts.tv_nsec;
6666 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6667 clock_pairing.flags = 0;
6670 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6671 sizeof(struct kvm_clock_pairing)))
6679 * kvm_pv_kick_cpu_op: Kick a vcpu.
6681 * @apicid - apicid of vcpu to be kicked.
6683 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6685 struct kvm_lapic_irq lapic_irq;
6687 lapic_irq.shorthand = 0;
6688 lapic_irq.dest_mode = 0;
6689 lapic_irq.level = 0;
6690 lapic_irq.dest_id = apicid;
6691 lapic_irq.msi_redir_hint = false;
6693 lapic_irq.delivery_mode = APIC_DM_REMRD;
6694 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6697 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6699 vcpu->arch.apicv_active = false;
6700 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6703 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6705 unsigned long nr, a0, a1, a2, a3, ret;
6708 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6709 return kvm_hv_hypercall(vcpu);
6711 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6712 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6713 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6714 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6715 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
6717 trace_kvm_hypercall(nr, a0, a1, a2, a3);
6719 op_64_bit = is_64_bit_mode(vcpu);
6728 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6734 case KVM_HC_VAPIC_POLL_IRQ:
6737 case KVM_HC_KICK_CPU:
6738 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6741 #ifdef CONFIG_X86_64
6742 case KVM_HC_CLOCK_PAIRING:
6743 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6753 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6755 ++vcpu->stat.hypercalls;
6756 return kvm_skip_emulated_instruction(vcpu);
6758 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6760 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6762 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6763 char instruction[3];
6764 unsigned long rip = kvm_rip_read(vcpu);
6766 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6768 return emulator_write_emulated(ctxt, rip, instruction, 3,
6772 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6774 return vcpu->run->request_interrupt_window &&
6775 likely(!pic_in_kernel(vcpu->kvm));
6778 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6780 struct kvm_run *kvm_run = vcpu->run;
6782 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6783 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6784 kvm_run->cr8 = kvm_get_cr8(vcpu);
6785 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6786 kvm_run->ready_for_interrupt_injection =
6787 pic_in_kernel(vcpu->kvm) ||
6788 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6791 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6795 if (!kvm_x86_ops->update_cr8_intercept)
6798 if (!lapic_in_kernel(vcpu))
6801 if (vcpu->arch.apicv_active)
6804 if (!vcpu->arch.apic->vapic_addr)
6805 max_irr = kvm_lapic_find_highest_irr(vcpu);
6812 tpr = kvm_lapic_get_cr8(vcpu);
6814 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6817 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6821 /* try to reinject previous events if any */
6823 if (vcpu->arch.exception.injected)
6824 kvm_x86_ops->queue_exception(vcpu);
6826 * Do not inject an NMI or interrupt if there is a pending
6827 * exception. Exceptions and interrupts are recognized at
6828 * instruction boundaries, i.e. the start of an instruction.
6829 * Trap-like exceptions, e.g. #DB, have higher priority than
6830 * NMIs and interrupts, i.e. traps are recognized before an
6831 * NMI/interrupt that's pending on the same instruction.
6832 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
6833 * priority, but are only generated (pended) during instruction
6834 * execution, i.e. a pending fault-like exception means the
6835 * fault occurred on the *previous* instruction and must be
6836 * serviced prior to recognizing any new events in order to
6837 * fully complete the previous instruction.
6839 else if (!vcpu->arch.exception.pending) {
6840 if (vcpu->arch.nmi_injected)
6841 kvm_x86_ops->set_nmi(vcpu);
6842 else if (vcpu->arch.interrupt.injected)
6843 kvm_x86_ops->set_irq(vcpu);
6847 * Call check_nested_events() even if we reinjected a previous event
6848 * in order for caller to determine if it should require immediate-exit
6849 * from L2 to L1 due to pending L1 events which require exit
6852 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6853 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6858 /* try to inject new event if pending */
6859 if (vcpu->arch.exception.pending) {
6860 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6861 vcpu->arch.exception.has_error_code,
6862 vcpu->arch.exception.error_code);
6864 WARN_ON_ONCE(vcpu->arch.exception.injected);
6865 vcpu->arch.exception.pending = false;
6866 vcpu->arch.exception.injected = true;
6868 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6869 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6872 if (vcpu->arch.exception.nr == DB_VECTOR &&
6873 (vcpu->arch.dr7 & DR7_GD)) {
6874 vcpu->arch.dr7 &= ~DR7_GD;
6875 kvm_update_dr7(vcpu);
6878 kvm_x86_ops->queue_exception(vcpu);
6881 /* Don't consider new event if we re-injected an event */
6882 if (kvm_event_needs_reinjection(vcpu))
6885 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
6886 kvm_x86_ops->smi_allowed(vcpu)) {
6887 vcpu->arch.smi_pending = false;
6888 ++vcpu->arch.smi_count;
6890 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6891 --vcpu->arch.nmi_pending;
6892 vcpu->arch.nmi_injected = true;
6893 kvm_x86_ops->set_nmi(vcpu);
6894 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6896 * Because interrupts can be injected asynchronously, we are
6897 * calling check_nested_events again here to avoid a race condition.
6898 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6899 * proposal and current concerns. Perhaps we should be setting
6900 * KVM_REQ_EVENT only on certain events and not unconditionally?
6902 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6903 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6907 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6908 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6910 kvm_x86_ops->set_irq(vcpu);
6917 static void process_nmi(struct kvm_vcpu *vcpu)
6922 * x86 is limited to one NMI running, and one NMI pending after it.
6923 * If an NMI is already in progress, limit further NMIs to just one.
6924 * Otherwise, allow two (and we'll inject the first one immediately).
6926 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6929 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6930 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6931 kvm_make_request(KVM_REQ_EVENT, vcpu);
6934 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
6937 flags |= seg->g << 23;
6938 flags |= seg->db << 22;
6939 flags |= seg->l << 21;
6940 flags |= seg->avl << 20;
6941 flags |= seg->present << 15;
6942 flags |= seg->dpl << 13;
6943 flags |= seg->s << 12;
6944 flags |= seg->type << 8;
6948 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6950 struct kvm_segment seg;
6953 kvm_get_segment(vcpu, &seg, n);
6954 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6957 offset = 0x7f84 + n * 12;
6959 offset = 0x7f2c + (n - 3) * 12;
6961 put_smstate(u32, buf, offset + 8, seg.base);
6962 put_smstate(u32, buf, offset + 4, seg.limit);
6963 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
6966 #ifdef CONFIG_X86_64
6967 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6969 struct kvm_segment seg;
6973 kvm_get_segment(vcpu, &seg, n);
6974 offset = 0x7e00 + n * 16;
6976 flags = enter_smm_get_segment_flags(&seg) >> 8;
6977 put_smstate(u16, buf, offset, seg.selector);
6978 put_smstate(u16, buf, offset + 2, flags);
6979 put_smstate(u32, buf, offset + 4, seg.limit);
6980 put_smstate(u64, buf, offset + 8, seg.base);
6984 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6987 struct kvm_segment seg;
6991 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6992 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6993 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6994 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6996 for (i = 0; i < 8; i++)
6997 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6999 kvm_get_dr(vcpu, 6, &val);
7000 put_smstate(u32, buf, 0x7fcc, (u32)val);
7001 kvm_get_dr(vcpu, 7, &val);
7002 put_smstate(u32, buf, 0x7fc8, (u32)val);
7004 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7005 put_smstate(u32, buf, 0x7fc4, seg.selector);
7006 put_smstate(u32, buf, 0x7f64, seg.base);
7007 put_smstate(u32, buf, 0x7f60, seg.limit);
7008 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7010 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7011 put_smstate(u32, buf, 0x7fc0, seg.selector);
7012 put_smstate(u32, buf, 0x7f80, seg.base);
7013 put_smstate(u32, buf, 0x7f7c, seg.limit);
7014 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7016 kvm_x86_ops->get_gdt(vcpu, &dt);
7017 put_smstate(u32, buf, 0x7f74, dt.address);
7018 put_smstate(u32, buf, 0x7f70, dt.size);
7020 kvm_x86_ops->get_idt(vcpu, &dt);
7021 put_smstate(u32, buf, 0x7f58, dt.address);
7022 put_smstate(u32, buf, 0x7f54, dt.size);
7024 for (i = 0; i < 6; i++)
7025 enter_smm_save_seg_32(vcpu, buf, i);
7027 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7030 put_smstate(u32, buf, 0x7efc, 0x00020000);
7031 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7034 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7036 #ifdef CONFIG_X86_64
7038 struct kvm_segment seg;
7042 for (i = 0; i < 16; i++)
7043 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7045 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7046 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7048 kvm_get_dr(vcpu, 6, &val);
7049 put_smstate(u64, buf, 0x7f68, val);
7050 kvm_get_dr(vcpu, 7, &val);
7051 put_smstate(u64, buf, 0x7f60, val);
7053 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7054 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7055 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7057 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7060 put_smstate(u32, buf, 0x7efc, 0x00020064);
7062 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7064 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7065 put_smstate(u16, buf, 0x7e90, seg.selector);
7066 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7067 put_smstate(u32, buf, 0x7e94, seg.limit);
7068 put_smstate(u64, buf, 0x7e98, seg.base);
7070 kvm_x86_ops->get_idt(vcpu, &dt);
7071 put_smstate(u32, buf, 0x7e84, dt.size);
7072 put_smstate(u64, buf, 0x7e88, dt.address);
7074 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7075 put_smstate(u16, buf, 0x7e70, seg.selector);
7076 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7077 put_smstate(u32, buf, 0x7e74, seg.limit);
7078 put_smstate(u64, buf, 0x7e78, seg.base);
7080 kvm_x86_ops->get_gdt(vcpu, &dt);
7081 put_smstate(u32, buf, 0x7e64, dt.size);
7082 put_smstate(u64, buf, 0x7e68, dt.address);
7084 for (i = 0; i < 6; i++)
7085 enter_smm_save_seg_64(vcpu, buf, i);
7091 static void enter_smm(struct kvm_vcpu *vcpu)
7093 struct kvm_segment cs, ds;
7098 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7099 memset(buf, 0, 512);
7100 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7101 enter_smm_save_state_64(vcpu, buf);
7103 enter_smm_save_state_32(vcpu, buf);
7106 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7107 * vCPU state (e.g. leave guest mode) after we've saved the state into
7108 * the SMM state-save area.
7110 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7112 vcpu->arch.hflags |= HF_SMM_MASK;
7113 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7115 if (kvm_x86_ops->get_nmi_mask(vcpu))
7116 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7118 kvm_x86_ops->set_nmi_mask(vcpu, true);
7120 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7121 kvm_rip_write(vcpu, 0x8000);
7123 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7124 kvm_x86_ops->set_cr0(vcpu, cr0);
7125 vcpu->arch.cr0 = cr0;
7127 kvm_x86_ops->set_cr4(vcpu, 0);
7129 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7130 dt.address = dt.size = 0;
7131 kvm_x86_ops->set_idt(vcpu, &dt);
7133 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7135 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7136 cs.base = vcpu->arch.smbase;
7141 cs.limit = ds.limit = 0xffffffff;
7142 cs.type = ds.type = 0x3;
7143 cs.dpl = ds.dpl = 0;
7148 cs.avl = ds.avl = 0;
7149 cs.present = ds.present = 1;
7150 cs.unusable = ds.unusable = 0;
7151 cs.padding = ds.padding = 0;
7153 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7154 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7155 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7156 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7157 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7158 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7160 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7161 kvm_x86_ops->set_efer(vcpu, 0);
7163 kvm_update_cpuid(vcpu);
7164 kvm_mmu_reset_context(vcpu);
7167 static void process_smi(struct kvm_vcpu *vcpu)
7169 vcpu->arch.smi_pending = true;
7170 kvm_make_request(KVM_REQ_EVENT, vcpu);
7173 void kvm_make_scan_ioapic_request(struct kvm *kvm)
7175 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7178 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
7180 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7183 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
7185 if (irqchip_split(vcpu->kvm))
7186 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
7188 if (vcpu->arch.apicv_active)
7189 kvm_x86_ops->sync_pir_to_irr(vcpu);
7190 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
7193 if (is_guest_mode(vcpu))
7194 vcpu->arch.load_eoi_exitmap_pending = true;
7196 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7199 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7201 u64 eoi_exit_bitmap[4];
7203 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7206 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7207 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7208 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
7211 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7212 unsigned long start, unsigned long end)
7214 unsigned long apic_address;
7217 * The physical address of apic access page is stored in the VMCS.
7218 * Update it when it becomes invalid.
7220 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7221 if (start <= apic_address && apic_address < end)
7222 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7225 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7227 struct page *page = NULL;
7229 if (!lapic_in_kernel(vcpu))
7232 if (!kvm_x86_ops->set_apic_access_page_addr)
7235 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7236 if (is_error_page(page))
7238 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7241 * Do not pin apic access page in memory, the MMU notifier
7242 * will call us again if it is migrated or swapped out.
7246 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7249 * Returns 1 to let vcpu_run() continue the guest execution loop without
7250 * exiting to the userspace. Otherwise, the value will be returned to the
7253 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
7257 dm_request_for_irq_injection(vcpu) &&
7258 kvm_cpu_accept_dm_intr(vcpu);
7260 bool req_immediate_exit = false;
7262 if (kvm_request_pending(vcpu)) {
7263 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7264 kvm_x86_ops->get_vmcs12_pages(vcpu);
7265 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
7266 kvm_mmu_unload(vcpu);
7267 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
7268 __kvm_migrate_timers(vcpu);
7269 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7270 kvm_gen_update_masterclock(vcpu->kvm);
7271 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7272 kvm_gen_kvmclock_update(vcpu);
7273 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7274 r = kvm_guest_time_update(vcpu);
7278 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
7279 kvm_mmu_sync_roots(vcpu);
7280 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
7281 kvm_vcpu_flush_tlb(vcpu, true);
7282 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
7283 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
7287 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
7288 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7289 vcpu->mmio_needed = 0;
7293 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7294 /* Page is swapped out. Do synthetic halt */
7295 vcpu->arch.apf.halted = true;
7299 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7300 record_steal_time(vcpu);
7301 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7303 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7305 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7306 kvm_pmu_handle_event(vcpu);
7307 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7308 kvm_pmu_deliver_pmi(vcpu);
7309 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7310 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7311 if (test_bit(vcpu->arch.pending_ioapic_eoi,
7312 vcpu->arch.ioapic_handled_vectors)) {
7313 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7314 vcpu->run->eoi.vector =
7315 vcpu->arch.pending_ioapic_eoi;
7320 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7321 vcpu_scan_ioapic(vcpu);
7322 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7323 vcpu_load_eoi_exitmap(vcpu);
7324 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7325 kvm_vcpu_reload_apic_access_page(vcpu);
7326 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7327 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7328 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7332 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7333 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7334 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7338 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7339 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7340 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7346 * KVM_REQ_HV_STIMER has to be processed after
7347 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7348 * depend on the guest clock being up-to-date
7350 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7351 kvm_hv_process_stimers(vcpu);
7354 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
7355 ++vcpu->stat.req_event;
7356 kvm_apic_accept_events(vcpu);
7357 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7362 if (inject_pending_event(vcpu, req_int_win) != 0)
7363 req_immediate_exit = true;
7365 /* Enable SMI/NMI/IRQ window open exits if needed.
7367 * SMIs have three cases:
7368 * 1) They can be nested, and then there is nothing to
7369 * do here because RSM will cause a vmexit anyway.
7370 * 2) There is an ISA-specific reason why SMI cannot be
7371 * injected, and the moment when this changes can be
7373 * 3) Or the SMI can be pending because
7374 * inject_pending_event has completed the injection
7375 * of an IRQ or NMI from the previous vmexit, and
7376 * then we request an immediate exit to inject the
7379 if (vcpu->arch.smi_pending && !is_smm(vcpu))
7380 if (!kvm_x86_ops->enable_smi_window(vcpu))
7381 req_immediate_exit = true;
7382 if (vcpu->arch.nmi_pending)
7383 kvm_x86_ops->enable_nmi_window(vcpu);
7384 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7385 kvm_x86_ops->enable_irq_window(vcpu);
7386 WARN_ON(vcpu->arch.exception.pending);
7389 if (kvm_lapic_enabled(vcpu)) {
7390 update_cr8_intercept(vcpu);
7391 kvm_lapic_sync_to_vapic(vcpu);
7395 r = kvm_mmu_reload(vcpu);
7397 goto cancel_injection;
7402 kvm_x86_ops->prepare_guest_switch(vcpu);
7405 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7406 * IPI are then delayed after guest entry, which ensures that they
7407 * result in virtual interrupt delivery.
7409 local_irq_disable();
7410 vcpu->mode = IN_GUEST_MODE;
7412 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7415 * 1) We should set ->mode before checking ->requests. Please see
7416 * the comment in kvm_vcpu_exiting_guest_mode().
7418 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7419 * pairs with the memory barrier implicit in pi_test_and_set_on
7420 * (see vmx_deliver_posted_interrupt).
7422 * 3) This also orders the write to mode from any reads to the page
7423 * tables done while the VCPU is running. Please see the comment
7424 * in kvm_flush_remote_tlbs.
7426 smp_mb__after_srcu_read_unlock();
7429 * This handles the case where a posted interrupt was
7430 * notified with kvm_vcpu_kick.
7432 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7433 kvm_x86_ops->sync_pir_to_irr(vcpu);
7435 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
7436 || need_resched() || signal_pending(current)) {
7437 vcpu->mode = OUTSIDE_GUEST_MODE;
7441 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7443 goto cancel_injection;
7446 kvm_load_guest_xcr0(vcpu);
7448 if (req_immediate_exit) {
7449 kvm_make_request(KVM_REQ_EVENT, vcpu);
7450 smp_send_reschedule(vcpu->cpu);
7453 trace_kvm_entry(vcpu->vcpu_id);
7454 if (lapic_timer_advance_ns)
7455 wait_lapic_expire(vcpu);
7456 guest_enter_irqoff();
7458 if (unlikely(vcpu->arch.switch_db_regs)) {
7460 set_debugreg(vcpu->arch.eff_db[0], 0);
7461 set_debugreg(vcpu->arch.eff_db[1], 1);
7462 set_debugreg(vcpu->arch.eff_db[2], 2);
7463 set_debugreg(vcpu->arch.eff_db[3], 3);
7464 set_debugreg(vcpu->arch.dr6, 6);
7465 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7468 kvm_x86_ops->run(vcpu);
7471 * Do this here before restoring debug registers on the host. And
7472 * since we do this before handling the vmexit, a DR access vmexit
7473 * can (a) read the correct value of the debug registers, (b) set
7474 * KVM_DEBUGREG_WONT_EXIT again.
7476 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
7477 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7478 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
7479 kvm_update_dr0123(vcpu);
7480 kvm_update_dr6(vcpu);
7481 kvm_update_dr7(vcpu);
7482 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7486 * If the guest has used debug registers, at least dr7
7487 * will be disabled while returning to the host.
7488 * If we don't have active breakpoints in the host, we don't
7489 * care about the messed up debug address registers. But if
7490 * we have some of them active, restore the old state.
7492 if (hw_breakpoint_active())
7493 hw_breakpoint_restore();
7495 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
7497 vcpu->mode = OUTSIDE_GUEST_MODE;
7500 kvm_put_guest_xcr0(vcpu);
7502 kvm_before_interrupt(vcpu);
7503 kvm_x86_ops->handle_external_intr(vcpu);
7504 kvm_after_interrupt(vcpu);
7508 guest_exit_irqoff();
7513 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7516 * Profile KVM exit RIPs:
7518 if (unlikely(prof_on == KVM_PROFILING)) {
7519 unsigned long rip = kvm_rip_read(vcpu);
7520 profile_hit(KVM_PROFILING, (void *)rip);
7523 if (unlikely(vcpu->arch.tsc_always_catchup))
7524 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7526 if (vcpu->arch.apic_attention)
7527 kvm_lapic_sync_from_vapic(vcpu);
7529 vcpu->arch.gpa_available = false;
7530 r = kvm_x86_ops->handle_exit(vcpu);
7534 kvm_x86_ops->cancel_injection(vcpu);
7535 if (unlikely(vcpu->arch.apic_attention))
7536 kvm_lapic_sync_from_vapic(vcpu);
7541 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7543 if (!kvm_arch_vcpu_runnable(vcpu) &&
7544 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
7545 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7546 kvm_vcpu_block(vcpu);
7547 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7549 if (kvm_x86_ops->post_block)
7550 kvm_x86_ops->post_block(vcpu);
7552 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7556 kvm_apic_accept_events(vcpu);
7557 switch(vcpu->arch.mp_state) {
7558 case KVM_MP_STATE_HALTED:
7559 vcpu->arch.pv.pv_unhalted = false;
7560 vcpu->arch.mp_state =
7561 KVM_MP_STATE_RUNNABLE;
7562 case KVM_MP_STATE_RUNNABLE:
7563 vcpu->arch.apf.halted = false;
7565 case KVM_MP_STATE_INIT_RECEIVED:
7574 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7576 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7577 kvm_x86_ops->check_nested_events(vcpu, false);
7579 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7580 !vcpu->arch.apf.halted);
7583 static int vcpu_run(struct kvm_vcpu *vcpu)
7586 struct kvm *kvm = vcpu->kvm;
7588 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7591 if (kvm_vcpu_running(vcpu)) {
7592 r = vcpu_enter_guest(vcpu);
7594 r = vcpu_block(kvm, vcpu);
7600 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
7601 if (kvm_cpu_has_pending_timer(vcpu))
7602 kvm_inject_pending_timer_irqs(vcpu);
7604 if (dm_request_for_irq_injection(vcpu) &&
7605 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
7607 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
7608 ++vcpu->stat.request_irq_exits;
7612 kvm_check_async_pf_completion(vcpu);
7614 if (signal_pending(current)) {
7616 vcpu->run->exit_reason = KVM_EXIT_INTR;
7617 ++vcpu->stat.signal_exits;
7620 if (need_resched()) {
7621 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7623 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7627 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7632 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7635 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7636 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7637 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7638 if (r != EMULATE_DONE)
7643 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7645 BUG_ON(!vcpu->arch.pio.count);
7647 return complete_emulated_io(vcpu);
7651 * Implements the following, as a state machine:
7655 * for each mmio piece in the fragment
7663 * for each mmio piece in the fragment
7668 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
7670 struct kvm_run *run = vcpu->run;
7671 struct kvm_mmio_fragment *frag;
7674 BUG_ON(!vcpu->mmio_needed);
7676 /* Complete previous fragment */
7677 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7678 len = min(8u, frag->len);
7679 if (!vcpu->mmio_is_write)
7680 memcpy(frag->data, run->mmio.data, len);
7682 if (frag->len <= 8) {
7683 /* Switch to the next fragment. */
7685 vcpu->mmio_cur_fragment++;
7687 /* Go forward to the next mmio piece. */
7693 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
7694 vcpu->mmio_needed = 0;
7696 /* FIXME: return into emulator if single-stepping. */
7697 if (vcpu->mmio_is_write)
7699 vcpu->mmio_read_completed = 1;
7700 return complete_emulated_io(vcpu);
7703 run->exit_reason = KVM_EXIT_MMIO;
7704 run->mmio.phys_addr = frag->gpa;
7705 if (vcpu->mmio_is_write)
7706 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7707 run->mmio.len = min(8u, frag->len);
7708 run->mmio.is_write = vcpu->mmio_is_write;
7709 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7713 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7718 kvm_sigset_activate(vcpu);
7719 kvm_load_guest_fpu(vcpu);
7721 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
7722 if (kvm_run->immediate_exit) {
7726 kvm_vcpu_block(vcpu);
7727 kvm_apic_accept_events(vcpu);
7728 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
7730 if (signal_pending(current)) {
7732 vcpu->run->exit_reason = KVM_EXIT_INTR;
7733 ++vcpu->stat.signal_exits;
7738 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7743 if (vcpu->run->kvm_dirty_regs) {
7744 r = sync_regs(vcpu);
7749 /* re-sync apic's tpr */
7750 if (!lapic_in_kernel(vcpu)) {
7751 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7757 if (unlikely(vcpu->arch.complete_userspace_io)) {
7758 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7759 vcpu->arch.complete_userspace_io = NULL;
7764 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
7766 if (kvm_run->immediate_exit)
7772 kvm_put_guest_fpu(vcpu);
7773 if (vcpu->run->kvm_valid_regs)
7775 post_kvm_run_save(vcpu);
7776 kvm_sigset_deactivate(vcpu);
7782 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7784 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7786 * We are here if userspace calls get_regs() in the middle of
7787 * instruction emulation. Registers state needs to be copied
7788 * back from emulation context to vcpu. Userspace shouldn't do
7789 * that usually, but some bad designed PV devices (vmware
7790 * backdoor interface) need this to work
7792 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7793 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7795 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7796 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7797 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7798 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7799 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7800 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7801 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7802 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
7803 #ifdef CONFIG_X86_64
7804 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7805 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7806 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7807 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7808 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7809 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7810 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7811 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
7814 regs->rip = kvm_rip_read(vcpu);
7815 regs->rflags = kvm_get_rflags(vcpu);
7818 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7821 __get_regs(vcpu, regs);
7826 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7828 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7829 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7831 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7832 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7833 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7834 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7835 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7836 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7837 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7838 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
7839 #ifdef CONFIG_X86_64
7840 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7841 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7842 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7843 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7844 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7845 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7846 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7847 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
7850 kvm_rip_write(vcpu, regs->rip);
7851 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
7853 vcpu->arch.exception.pending = false;
7855 kvm_make_request(KVM_REQ_EVENT, vcpu);
7858 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7861 __set_regs(vcpu, regs);
7866 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7868 struct kvm_segment cs;
7870 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7874 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7876 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7880 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7881 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7882 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7883 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7884 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7885 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7887 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7888 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7890 kvm_x86_ops->get_idt(vcpu, &dt);
7891 sregs->idt.limit = dt.size;
7892 sregs->idt.base = dt.address;
7893 kvm_x86_ops->get_gdt(vcpu, &dt);
7894 sregs->gdt.limit = dt.size;
7895 sregs->gdt.base = dt.address;
7897 sregs->cr0 = kvm_read_cr0(vcpu);
7898 sregs->cr2 = vcpu->arch.cr2;
7899 sregs->cr3 = kvm_read_cr3(vcpu);
7900 sregs->cr4 = kvm_read_cr4(vcpu);
7901 sregs->cr8 = kvm_get_cr8(vcpu);
7902 sregs->efer = vcpu->arch.efer;
7903 sregs->apic_base = kvm_get_apic_base(vcpu);
7905 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7907 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
7908 set_bit(vcpu->arch.interrupt.nr,
7909 (unsigned long *)sregs->interrupt_bitmap);
7912 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7913 struct kvm_sregs *sregs)
7916 __get_sregs(vcpu, sregs);
7921 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7922 struct kvm_mp_state *mp_state)
7926 kvm_apic_accept_events(vcpu);
7927 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7928 vcpu->arch.pv.pv_unhalted)
7929 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7931 mp_state->mp_state = vcpu->arch.mp_state;
7937 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7938 struct kvm_mp_state *mp_state)
7944 if (!lapic_in_kernel(vcpu) &&
7945 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7948 /* INITs are latched while in SMM */
7949 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7950 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7951 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7954 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7955 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7956 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7958 vcpu->arch.mp_state = mp_state->mp_state;
7959 kvm_make_request(KVM_REQ_EVENT, vcpu);
7967 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7968 int reason, bool has_error_code, u32 error_code)
7970 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7973 init_emulate_ctxt(vcpu);
7975 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7976 has_error_code, error_code);
7979 return EMULATE_FAIL;
7981 kvm_rip_write(vcpu, ctxt->eip);
7982 kvm_set_rflags(vcpu, ctxt->eflags);
7983 kvm_make_request(KVM_REQ_EVENT, vcpu);
7984 return EMULATE_DONE;
7986 EXPORT_SYMBOL_GPL(kvm_task_switch);
7988 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7990 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
7992 * When EFER.LME and CR0.PG are set, the processor is in
7993 * 64-bit mode (though maybe in a 32-bit code segment).
7994 * CR4.PAE and EFER.LMA must be set.
7996 if (!(sregs->cr4 & X86_CR4_PAE)
7997 || !(sregs->efer & EFER_LMA))
8001 * Not in 64-bit mode: EFER.LMA is clear and the code
8002 * segment cannot be 64-bit.
8004 if (sregs->efer & EFER_LMA || sregs->cs.l)
8011 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8013 struct msr_data apic_base_msr;
8014 int mmu_reset_needed = 0;
8015 int cpuid_update_needed = 0;
8016 int pending_vec, max_bits, idx;
8020 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8021 (sregs->cr4 & X86_CR4_OSXSAVE))
8024 if (kvm_valid_sregs(vcpu, sregs))
8027 apic_base_msr.data = sregs->apic_base;
8028 apic_base_msr.host_initiated = true;
8029 if (kvm_set_apic_base(vcpu, &apic_base_msr))
8032 dt.size = sregs->idt.limit;
8033 dt.address = sregs->idt.base;
8034 kvm_x86_ops->set_idt(vcpu, &dt);
8035 dt.size = sregs->gdt.limit;
8036 dt.address = sregs->gdt.base;
8037 kvm_x86_ops->set_gdt(vcpu, &dt);
8039 vcpu->arch.cr2 = sregs->cr2;
8040 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
8041 vcpu->arch.cr3 = sregs->cr3;
8042 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
8044 kvm_set_cr8(vcpu, sregs->cr8);
8046 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
8047 kvm_x86_ops->set_efer(vcpu, sregs->efer);
8049 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
8050 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
8051 vcpu->arch.cr0 = sregs->cr0;
8053 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
8054 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8055 (X86_CR4_OSXSAVE | X86_CR4_PKE));
8056 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
8057 if (cpuid_update_needed)
8058 kvm_update_cpuid(vcpu);
8060 idx = srcu_read_lock(&vcpu->kvm->srcu);
8061 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
8062 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
8063 mmu_reset_needed = 1;
8065 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8067 if (mmu_reset_needed)
8068 kvm_mmu_reset_context(vcpu);
8070 max_bits = KVM_NR_INTERRUPTS;
8071 pending_vec = find_first_bit(
8072 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8073 if (pending_vec < max_bits) {
8074 kvm_queue_interrupt(vcpu, pending_vec, false);
8075 pr_debug("Set back pending irq %d\n", pending_vec);
8078 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8079 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8080 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8081 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8082 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8083 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8085 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8086 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8088 update_cr8_intercept(vcpu);
8090 /* Older userspace won't unhalt the vcpu on reset. */
8091 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
8092 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
8094 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8096 kvm_make_request(KVM_REQ_EVENT, vcpu);
8103 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8104 struct kvm_sregs *sregs)
8109 ret = __set_sregs(vcpu, sregs);
8114 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8115 struct kvm_guest_debug *dbg)
8117 unsigned long rflags;
8122 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8124 if (vcpu->arch.exception.pending)
8126 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8127 kvm_queue_exception(vcpu, DB_VECTOR);
8129 kvm_queue_exception(vcpu, BP_VECTOR);
8133 * Read rflags as long as potentially injected trace flags are still
8136 rflags = kvm_get_rflags(vcpu);
8138 vcpu->guest_debug = dbg->control;
8139 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8140 vcpu->guest_debug = 0;
8142 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
8143 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8144 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
8145 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
8147 for (i = 0; i < KVM_NR_DB_REGS; i++)
8148 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
8150 kvm_update_dr7(vcpu);
8152 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8153 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8154 get_segment_base(vcpu, VCPU_SREG_CS);
8157 * Trigger an rflags update that will inject or remove the trace
8160 kvm_set_rflags(vcpu, rflags);
8162 kvm_x86_ops->update_bp_intercept(vcpu);
8172 * Translate a guest virtual address to a guest physical address.
8174 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8175 struct kvm_translation *tr)
8177 unsigned long vaddr = tr->linear_address;
8183 idx = srcu_read_lock(&vcpu->kvm->srcu);
8184 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
8185 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8186 tr->physical_address = gpa;
8187 tr->valid = gpa != UNMAPPED_GVA;
8195 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8197 struct fxregs_state *fxsave;
8201 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
8202 memcpy(fpu->fpr, fxsave->st_space, 128);
8203 fpu->fcw = fxsave->cwd;
8204 fpu->fsw = fxsave->swd;
8205 fpu->ftwx = fxsave->twd;
8206 fpu->last_opcode = fxsave->fop;
8207 fpu->last_ip = fxsave->rip;
8208 fpu->last_dp = fxsave->rdp;
8209 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8215 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8217 struct fxregs_state *fxsave;
8221 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
8223 memcpy(fxsave->st_space, fpu->fpr, 128);
8224 fxsave->cwd = fpu->fcw;
8225 fxsave->swd = fpu->fsw;
8226 fxsave->twd = fpu->ftwx;
8227 fxsave->fop = fpu->last_opcode;
8228 fxsave->rip = fpu->last_ip;
8229 fxsave->rdp = fpu->last_dp;
8230 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8236 static void store_regs(struct kvm_vcpu *vcpu)
8238 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8240 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8241 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8243 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8244 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8246 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8247 kvm_vcpu_ioctl_x86_get_vcpu_events(
8248 vcpu, &vcpu->run->s.regs.events);
8251 static int sync_regs(struct kvm_vcpu *vcpu)
8253 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8256 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8257 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8258 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8260 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8261 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8263 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8265 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8266 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8267 vcpu, &vcpu->run->s.regs.events))
8269 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8275 static void fx_init(struct kvm_vcpu *vcpu)
8277 fpstate_init(&vcpu->arch.guest_fpu.state);
8278 if (boot_cpu_has(X86_FEATURE_XSAVES))
8279 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
8280 host_xcr0 | XSTATE_COMPACTION_ENABLED;
8283 * Ensure guest xcr0 is valid for loading
8285 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8287 vcpu->arch.cr0 |= X86_CR0_ET;
8290 /* Swap (qemu) user FPU context for the guest FPU context. */
8291 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8294 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
8295 /* PKRU is separately restored in kvm_x86_ops->run. */
8296 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8297 ~XFEATURE_MASK_PKRU);
8302 /* When vcpu_run ends, restore user space FPU context. */
8303 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8306 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
8307 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8309 ++vcpu->stat.fpu_reload;
8313 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8315 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8317 kvmclock_reset(vcpu);
8319 kvm_x86_ops->vcpu_free(vcpu);
8320 free_cpumask_var(wbinvd_dirty_mask);
8323 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8326 struct kvm_vcpu *vcpu;
8328 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
8329 printk_once(KERN_WARNING
8330 "kvm: SMP vm created on host with unstable TSC; "
8331 "guest TSC will not be reliable\n");
8333 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8338 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8340 kvm_vcpu_mtrr_init(vcpu);
8342 kvm_vcpu_reset(vcpu, false);
8343 kvm_mmu_setup(vcpu);
8348 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
8350 struct msr_data msr;
8351 struct kvm *kvm = vcpu->kvm;
8353 kvm_hv_vcpu_postcreate(vcpu);
8355 if (mutex_lock_killable(&vcpu->mutex))
8359 msr.index = MSR_IA32_TSC;
8360 msr.host_initiated = true;
8361 kvm_write_tsc(vcpu, &msr);
8363 mutex_unlock(&vcpu->mutex);
8365 if (!kvmclock_periodic_sync)
8368 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8369 KVMCLOCK_SYNC_PERIOD);
8372 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
8374 vcpu->arch.apf.msr_val = 0;
8377 kvm_mmu_unload(vcpu);
8380 kvm_x86_ops->vcpu_free(vcpu);
8383 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
8385 kvm_lapic_reset(vcpu, init_event);
8387 vcpu->arch.hflags = 0;
8389 vcpu->arch.smi_pending = 0;
8390 vcpu->arch.smi_count = 0;
8391 atomic_set(&vcpu->arch.nmi_queued, 0);
8392 vcpu->arch.nmi_pending = 0;
8393 vcpu->arch.nmi_injected = false;
8394 kvm_clear_interrupt_queue(vcpu);
8395 kvm_clear_exception_queue(vcpu);
8396 vcpu->arch.exception.pending = false;
8398 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
8399 kvm_update_dr0123(vcpu);
8400 vcpu->arch.dr6 = DR6_INIT;
8401 kvm_update_dr6(vcpu);
8402 vcpu->arch.dr7 = DR7_FIXED_1;
8403 kvm_update_dr7(vcpu);
8407 kvm_make_request(KVM_REQ_EVENT, vcpu);
8408 vcpu->arch.apf.msr_val = 0;
8409 vcpu->arch.st.msr_val = 0;
8411 kvmclock_reset(vcpu);
8413 kvm_clear_async_pf_completion_queue(vcpu);
8414 kvm_async_pf_hash_reset(vcpu);
8415 vcpu->arch.apf.halted = false;
8417 if (kvm_mpx_supported()) {
8418 void *mpx_state_buffer;
8421 * To avoid have the INIT path from kvm_apic_has_events() that be
8422 * called with loaded FPU and does not let userspace fix the state.
8425 kvm_put_guest_fpu(vcpu);
8426 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8427 XFEATURE_MASK_BNDREGS);
8428 if (mpx_state_buffer)
8429 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8430 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8431 XFEATURE_MASK_BNDCSR);
8432 if (mpx_state_buffer)
8433 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
8435 kvm_load_guest_fpu(vcpu);
8439 kvm_pmu_reset(vcpu);
8440 vcpu->arch.smbase = 0x30000;
8442 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8443 vcpu->arch.msr_misc_features_enables = 0;
8445 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8448 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8449 vcpu->arch.regs_avail = ~0;
8450 vcpu->arch.regs_dirty = ~0;
8452 vcpu->arch.ia32_xss = 0;
8454 kvm_x86_ops->vcpu_reset(vcpu, init_event);
8457 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
8459 struct kvm_segment cs;
8461 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8462 cs.selector = vector << 8;
8463 cs.base = vector << 12;
8464 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8465 kvm_rip_write(vcpu, 0);
8468 int kvm_arch_hardware_enable(void)
8471 struct kvm_vcpu *vcpu;
8476 bool stable, backwards_tsc = false;
8478 kvm_shared_msr_cpu_online();
8479 ret = kvm_x86_ops->hardware_enable();
8483 local_tsc = rdtsc();
8484 stable = !kvm_check_tsc_unstable();
8485 list_for_each_entry(kvm, &vm_list, vm_list) {
8486 kvm_for_each_vcpu(i, vcpu, kvm) {
8487 if (!stable && vcpu->cpu == smp_processor_id())
8488 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8489 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8490 backwards_tsc = true;
8491 if (vcpu->arch.last_host_tsc > max_tsc)
8492 max_tsc = vcpu->arch.last_host_tsc;
8498 * Sometimes, even reliable TSCs go backwards. This happens on
8499 * platforms that reset TSC during suspend or hibernate actions, but
8500 * maintain synchronization. We must compensate. Fortunately, we can
8501 * detect that condition here, which happens early in CPU bringup,
8502 * before any KVM threads can be running. Unfortunately, we can't
8503 * bring the TSCs fully up to date with real time, as we aren't yet far
8504 * enough into CPU bringup that we know how much real time has actually
8505 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
8506 * variables that haven't been updated yet.
8508 * So we simply find the maximum observed TSC above, then record the
8509 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8510 * the adjustment will be applied. Note that we accumulate
8511 * adjustments, in case multiple suspend cycles happen before some VCPU
8512 * gets a chance to run again. In the event that no KVM threads get a
8513 * chance to run, we will miss the entire elapsed period, as we'll have
8514 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8515 * loose cycle time. This isn't too big a deal, since the loss will be
8516 * uniform across all VCPUs (not to mention the scenario is extremely
8517 * unlikely). It is possible that a second hibernate recovery happens
8518 * much faster than a first, causing the observed TSC here to be
8519 * smaller; this would require additional padding adjustment, which is
8520 * why we set last_host_tsc to the local tsc observed here.
8522 * N.B. - this code below runs only on platforms with reliable TSC,
8523 * as that is the only way backwards_tsc is set above. Also note
8524 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8525 * have the same delta_cyc adjustment applied if backwards_tsc
8526 * is detected. Note further, this adjustment is only done once,
8527 * as we reset last_host_tsc on all VCPUs to stop this from being
8528 * called multiple times (one for each physical CPU bringup).
8530 * Platforms with unreliable TSCs don't have to deal with this, they
8531 * will be compensated by the logic in vcpu_load, which sets the TSC to
8532 * catchup mode. This will catchup all VCPUs to real time, but cannot
8533 * guarantee that they stay in perfect synchronization.
8535 if (backwards_tsc) {
8536 u64 delta_cyc = max_tsc - local_tsc;
8537 list_for_each_entry(kvm, &vm_list, vm_list) {
8538 kvm->arch.backwards_tsc_observed = true;
8539 kvm_for_each_vcpu(i, vcpu, kvm) {
8540 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8541 vcpu->arch.last_host_tsc = local_tsc;
8542 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
8546 * We have to disable TSC offset matching.. if you were
8547 * booting a VM while issuing an S4 host suspend....
8548 * you may have some problem. Solving this issue is
8549 * left as an exercise to the reader.
8551 kvm->arch.last_tsc_nsec = 0;
8552 kvm->arch.last_tsc_write = 0;
8559 void kvm_arch_hardware_disable(void)
8561 kvm_x86_ops->hardware_disable();
8562 drop_user_return_notifiers();
8565 int kvm_arch_hardware_setup(void)
8569 r = kvm_x86_ops->hardware_setup();
8573 if (kvm_has_tsc_control) {
8575 * Make sure the user can only configure tsc_khz values that
8576 * fit into a signed integer.
8577 * A min value is not calculated because it will always
8578 * be 1 on all machines.
8580 u64 max = min(0x7fffffffULL,
8581 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8582 kvm_max_guest_tsc_khz = max;
8584 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
8587 kvm_init_msr_list();
8591 void kvm_arch_hardware_unsetup(void)
8593 kvm_x86_ops->hardware_unsetup();
8596 void kvm_arch_check_processor_compat(void *rtn)
8598 kvm_x86_ops->check_processor_compatibility(rtn);
8601 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8603 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8605 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8607 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8609 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
8612 struct static_key kvm_no_apic_vcpu __read_mostly;
8613 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
8615 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8620 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
8621 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
8622 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
8623 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8625 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
8627 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8632 vcpu->arch.pio_data = page_address(page);
8634 kvm_set_tsc_khz(vcpu, max_tsc_khz);
8636 r = kvm_mmu_create(vcpu);
8638 goto fail_free_pio_data;
8640 if (irqchip_in_kernel(vcpu->kvm)) {
8641 r = kvm_create_lapic(vcpu);
8643 goto fail_mmu_destroy;
8645 static_key_slow_inc(&kvm_no_apic_vcpu);
8647 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8649 if (!vcpu->arch.mce_banks) {
8651 goto fail_free_lapic;
8653 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8655 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8657 goto fail_free_mce_banks;
8662 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
8664 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8666 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8668 kvm_async_pf_hash_reset(vcpu);
8671 vcpu->arch.pending_external_vector = -1;
8672 vcpu->arch.preempted_in_kernel = false;
8674 kvm_hv_vcpu_init(vcpu);
8678 fail_free_mce_banks:
8679 kfree(vcpu->arch.mce_banks);
8681 kvm_free_lapic(vcpu);
8683 kvm_mmu_destroy(vcpu);
8685 free_page((unsigned long)vcpu->arch.pio_data);
8690 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8694 kvm_hv_vcpu_uninit(vcpu);
8695 kvm_pmu_destroy(vcpu);
8696 kfree(vcpu->arch.mce_banks);
8697 kvm_free_lapic(vcpu);
8698 idx = srcu_read_lock(&vcpu->kvm->srcu);
8699 kvm_mmu_destroy(vcpu);
8700 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8701 free_page((unsigned long)vcpu->arch.pio_data);
8702 if (!lapic_in_kernel(vcpu))
8703 static_key_slow_dec(&kvm_no_apic_vcpu);
8706 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8708 kvm_x86_ops->sched_in(vcpu, cpu);
8711 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
8716 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
8717 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
8718 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
8719 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
8720 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
8722 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8723 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
8724 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8725 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8726 &kvm->arch.irq_sources_bitmap);
8728 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
8729 mutex_init(&kvm->arch.apic_map_lock);
8730 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8732 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
8733 pvclock_update_vm_gtod_copy(kvm);
8735 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
8736 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
8738 kvm_hv_init_vm(kvm);
8739 kvm_page_track_init(kvm);
8740 kvm_mmu_init_vm(kvm);
8742 if (kvm_x86_ops->vm_init)
8743 return kvm_x86_ops->vm_init(kvm);
8748 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8751 kvm_mmu_unload(vcpu);
8755 static void kvm_free_vcpus(struct kvm *kvm)
8758 struct kvm_vcpu *vcpu;
8761 * Unpin any mmu pages first.
8763 kvm_for_each_vcpu(i, vcpu, kvm) {
8764 kvm_clear_async_pf_completion_queue(vcpu);
8765 kvm_unload_vcpu_mmu(vcpu);
8767 kvm_for_each_vcpu(i, vcpu, kvm)
8768 kvm_arch_vcpu_free(vcpu);
8770 mutex_lock(&kvm->lock);
8771 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8772 kvm->vcpus[i] = NULL;
8774 atomic_set(&kvm->online_vcpus, 0);
8775 mutex_unlock(&kvm->lock);
8778 void kvm_arch_sync_events(struct kvm *kvm)
8780 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
8781 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
8785 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8789 struct kvm_memslots *slots = kvm_memslots(kvm);
8790 struct kvm_memory_slot *slot, old;
8792 /* Called with kvm->slots_lock held. */
8793 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8796 slot = id_to_memslot(slots, id);
8802 * MAP_SHARED to prevent internal slot pages from being moved
8805 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8806 MAP_SHARED | MAP_ANONYMOUS, 0);
8807 if (IS_ERR((void *)hva))
8808 return PTR_ERR((void *)hva);
8817 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
8818 struct kvm_userspace_memory_region m;
8820 m.slot = id | (i << 16);
8822 m.guest_phys_addr = gpa;
8823 m.userspace_addr = hva;
8824 m.memory_size = size;
8825 r = __kvm_set_memory_region(kvm, &m);
8831 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8835 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8837 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8841 mutex_lock(&kvm->slots_lock);
8842 r = __x86_set_memory_region(kvm, id, gpa, size);
8843 mutex_unlock(&kvm->slots_lock);
8847 EXPORT_SYMBOL_GPL(x86_set_memory_region);
8849 void kvm_arch_destroy_vm(struct kvm *kvm)
8851 if (current->mm == kvm->mm) {
8853 * Free memory regions allocated on behalf of userspace,
8854 * unless the the memory map has changed due to process exit
8857 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8858 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8859 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
8861 if (kvm_x86_ops->vm_destroy)
8862 kvm_x86_ops->vm_destroy(kvm);
8863 kvm_pic_destroy(kvm);
8864 kvm_ioapic_destroy(kvm);
8865 kvm_free_vcpus(kvm);
8866 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
8867 kvm_mmu_uninit_vm(kvm);
8868 kvm_page_track_cleanup(kvm);
8869 kvm_hv_destroy_vm(kvm);
8872 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
8873 struct kvm_memory_slot *dont)
8877 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8878 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
8879 kvfree(free->arch.rmap[i]);
8880 free->arch.rmap[i] = NULL;
8885 if (!dont || free->arch.lpage_info[i - 1] !=
8886 dont->arch.lpage_info[i - 1]) {
8887 kvfree(free->arch.lpage_info[i - 1]);
8888 free->arch.lpage_info[i - 1] = NULL;
8892 kvm_page_track_free_memslot(free, dont);
8895 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8896 unsigned long npages)
8900 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8901 struct kvm_lpage_info *linfo;
8906 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8907 slot->base_gfn, level) + 1;
8909 slot->arch.rmap[i] =
8910 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
8912 if (!slot->arch.rmap[i])
8917 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL);
8921 slot->arch.lpage_info[i - 1] = linfo;
8923 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
8924 linfo[0].disallow_lpage = 1;
8925 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
8926 linfo[lpages - 1].disallow_lpage = 1;
8927 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8929 * If the gfn and userspace address are not aligned wrt each
8930 * other, or if explicitly asked to, disable large page
8931 * support for this slot
8933 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8934 !kvm_largepages_enabled()) {
8937 for (j = 0; j < lpages; ++j)
8938 linfo[j].disallow_lpage = 1;
8942 if (kvm_page_track_create_memslot(slot, npages))
8948 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8949 kvfree(slot->arch.rmap[i]);
8950 slot->arch.rmap[i] = NULL;
8954 kvfree(slot->arch.lpage_info[i - 1]);
8955 slot->arch.lpage_info[i - 1] = NULL;
8960 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
8963 * memslots->generation has been incremented.
8964 * mmio generation may have reached its maximum value.
8966 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
8969 int kvm_arch_prepare_memory_region(struct kvm *kvm,
8970 struct kvm_memory_slot *memslot,
8971 const struct kvm_userspace_memory_region *mem,
8972 enum kvm_mr_change change)
8977 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8978 struct kvm_memory_slot *new)
8980 /* Still write protect RO slot */
8981 if (new->flags & KVM_MEM_READONLY) {
8982 kvm_mmu_slot_remove_write_access(kvm, new);
8987 * Call kvm_x86_ops dirty logging hooks when they are valid.
8989 * kvm_x86_ops->slot_disable_log_dirty is called when:
8991 * - KVM_MR_CREATE with dirty logging is disabled
8992 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8994 * The reason is, in case of PML, we need to set D-bit for any slots
8995 * with dirty logging disabled in order to eliminate unnecessary GPA
8996 * logging in PML buffer (and potential PML buffer full VMEXT). This
8997 * guarantees leaving PML enabled during guest's lifetime won't have
8998 * any additonal overhead from PML when guest is running with dirty
8999 * logging disabled for memory slots.
9001 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9002 * to dirty logging mode.
9004 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9006 * In case of write protect:
9008 * Write protect all pages for dirty logging.
9010 * All the sptes including the large sptes which point to this
9011 * slot are set to readonly. We can not create any new large
9012 * spte on this slot until the end of the logging.
9014 * See the comments in fast_page_fault().
9016 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9017 if (kvm_x86_ops->slot_enable_log_dirty)
9018 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9020 kvm_mmu_slot_remove_write_access(kvm, new);
9022 if (kvm_x86_ops->slot_disable_log_dirty)
9023 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9027 void kvm_arch_commit_memory_region(struct kvm *kvm,
9028 const struct kvm_userspace_memory_region *mem,
9029 const struct kvm_memory_slot *old,
9030 const struct kvm_memory_slot *new,
9031 enum kvm_mr_change change)
9033 int nr_mmu_pages = 0;
9035 if (!kvm->arch.n_requested_mmu_pages)
9036 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9039 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
9042 * Dirty logging tracks sptes in 4k granularity, meaning that large
9043 * sptes have to be split. If live migration is successful, the guest
9044 * in the source machine will be destroyed and large sptes will be
9045 * created in the destination. However, if the guest continues to run
9046 * in the source machine (for example if live migration fails), small
9047 * sptes will remain around and cause bad performance.
9049 * Scan sptes if dirty logging has been stopped, dropping those
9050 * which can be collapsed into a single large-page spte. Later
9051 * page faults will create the large-page sptes.
9053 if ((change != KVM_MR_DELETE) &&
9054 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9055 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9056 kvm_mmu_zap_collapsible_sptes(kvm, new);
9059 * Set up write protection and/or dirty logging for the new slot.
9061 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9062 * been zapped so no dirty logging staff is needed for old slot. For
9063 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9064 * new and it's also covered when dealing with the new slot.
9066 * FIXME: const-ify all uses of struct kvm_memory_slot.
9068 if (change != KVM_MR_DELETE)
9069 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
9072 void kvm_arch_flush_shadow_all(struct kvm *kvm)
9074 kvm_mmu_invalidate_zap_all_pages(kvm);
9077 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9078 struct kvm_memory_slot *slot)
9080 kvm_page_track_flush_slot(kvm, slot);
9083 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9085 if (!list_empty_careful(&vcpu->async_pf.done))
9088 if (kvm_apic_has_events(vcpu))
9091 if (vcpu->arch.pv.pv_unhalted)
9094 if (vcpu->arch.exception.pending)
9097 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9098 (vcpu->arch.nmi_pending &&
9099 kvm_x86_ops->nmi_allowed(vcpu)))
9102 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9103 (vcpu->arch.smi_pending && !is_smm(vcpu)))
9106 if (kvm_arch_interrupt_allowed(vcpu) &&
9107 kvm_cpu_has_interrupt(vcpu))
9110 if (kvm_hv_has_stimer_pending(vcpu))
9116 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9118 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
9121 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9123 return vcpu->arch.preempted_in_kernel;
9126 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
9128 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
9131 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9133 return kvm_x86_ops->interrupt_allowed(vcpu);
9136 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
9138 if (is_64_bit_mode(vcpu))
9139 return kvm_rip_read(vcpu);
9140 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9141 kvm_rip_read(vcpu));
9143 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
9145 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9147 return kvm_get_linear_rip(vcpu) == linear_rip;
9149 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9151 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9153 unsigned long rflags;
9155 rflags = kvm_x86_ops->get_rflags(vcpu);
9156 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9157 rflags &= ~X86_EFLAGS_TF;
9160 EXPORT_SYMBOL_GPL(kvm_get_rflags);
9162 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9164 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
9165 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
9166 rflags |= X86_EFLAGS_TF;
9167 kvm_x86_ops->set_rflags(vcpu, rflags);
9170 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9172 __kvm_set_rflags(vcpu, rflags);
9173 kvm_make_request(KVM_REQ_EVENT, vcpu);
9175 EXPORT_SYMBOL_GPL(kvm_set_rflags);
9177 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9181 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
9185 r = kvm_mmu_reload(vcpu);
9189 if (!vcpu->arch.mmu.direct_map &&
9190 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
9193 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
9196 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9198 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9201 static inline u32 kvm_async_pf_next_probe(u32 key)
9203 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9206 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9208 u32 key = kvm_async_pf_hash_fn(gfn);
9210 while (vcpu->arch.apf.gfns[key] != ~0)
9211 key = kvm_async_pf_next_probe(key);
9213 vcpu->arch.apf.gfns[key] = gfn;
9216 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9219 u32 key = kvm_async_pf_hash_fn(gfn);
9221 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
9222 (vcpu->arch.apf.gfns[key] != gfn &&
9223 vcpu->arch.apf.gfns[key] != ~0); i++)
9224 key = kvm_async_pf_next_probe(key);
9229 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9231 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9234 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9238 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9240 vcpu->arch.apf.gfns[i] = ~0;
9242 j = kvm_async_pf_next_probe(j);
9243 if (vcpu->arch.apf.gfns[j] == ~0)
9245 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9247 * k lies cyclically in ]i,j]
9249 * |....j i.k.| or |.k..j i...|
9251 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9252 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9257 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9260 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9264 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9267 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9271 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9272 struct kvm_async_pf *work)
9274 struct x86_exception fault;
9276 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
9277 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
9279 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
9280 (vcpu->arch.apf.send_user_only &&
9281 kvm_x86_ops->get_cpl(vcpu) == 0))
9282 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9283 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
9284 fault.vector = PF_VECTOR;
9285 fault.error_code_valid = true;
9286 fault.error_code = 0;
9287 fault.nested_page_fault = false;
9288 fault.address = work->arch.token;
9289 fault.async_page_fault = true;
9290 kvm_inject_page_fault(vcpu, &fault);
9294 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9295 struct kvm_async_pf *work)
9297 struct x86_exception fault;
9300 if (work->wakeup_all)
9301 work->arch.token = ~0; /* broadcast wakeup */
9303 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
9304 trace_kvm_async_pf_ready(work->arch.token, work->gva);
9306 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9307 !apf_get_user(vcpu, &val)) {
9308 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9309 vcpu->arch.exception.pending &&
9310 vcpu->arch.exception.nr == PF_VECTOR &&
9311 !apf_put_user(vcpu, 0)) {
9312 vcpu->arch.exception.injected = false;
9313 vcpu->arch.exception.pending = false;
9314 vcpu->arch.exception.nr = 0;
9315 vcpu->arch.exception.has_error_code = false;
9316 vcpu->arch.exception.error_code = 0;
9317 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9318 fault.vector = PF_VECTOR;
9319 fault.error_code_valid = true;
9320 fault.error_code = 0;
9321 fault.nested_page_fault = false;
9322 fault.address = work->arch.token;
9323 fault.async_page_fault = true;
9324 kvm_inject_page_fault(vcpu, &fault);
9327 vcpu->arch.apf.halted = false;
9328 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9331 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9333 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9336 return kvm_can_do_async_pf(vcpu);
9339 void kvm_arch_start_assignment(struct kvm *kvm)
9341 atomic_inc(&kvm->arch.assigned_device_count);
9343 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9345 void kvm_arch_end_assignment(struct kvm *kvm)
9347 atomic_dec(&kvm->arch.assigned_device_count);
9349 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9351 bool kvm_arch_has_assigned_device(struct kvm *kvm)
9353 return atomic_read(&kvm->arch.assigned_device_count);
9355 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9357 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9359 atomic_inc(&kvm->arch.noncoherent_dma_count);
9361 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9363 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9365 atomic_dec(&kvm->arch.noncoherent_dma_count);
9367 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9369 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9371 return atomic_read(&kvm->arch.noncoherent_dma_count);
9373 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9375 bool kvm_arch_has_irq_bypass(void)
9377 return kvm_x86_ops->update_pi_irte != NULL;
9380 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9381 struct irq_bypass_producer *prod)
9383 struct kvm_kernel_irqfd *irqfd =
9384 container_of(cons, struct kvm_kernel_irqfd, consumer);
9386 irqfd->producer = prod;
9388 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9389 prod->irq, irqfd->gsi, 1);
9392 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9393 struct irq_bypass_producer *prod)
9396 struct kvm_kernel_irqfd *irqfd =
9397 container_of(cons, struct kvm_kernel_irqfd, consumer);
9399 WARN_ON(irqfd->producer != prod);
9400 irqfd->producer = NULL;
9403 * When producer of consumer is unregistered, we change back to
9404 * remapped mode, so we can re-use the current implementation
9405 * when the irq is masked/disabled or the consumer side (KVM
9406 * int this case doesn't want to receive the interrupts.
9408 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9410 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9411 " fails: %d\n", irqfd->consumer.token, ret);
9414 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9415 uint32_t guest_irq, bool set)
9417 if (!kvm_x86_ops->update_pi_irte)
9420 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9423 bool kvm_vector_hashing_enabled(void)
9425 return vector_hashing;
9427 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9429 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
9430 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
9431 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9432 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9433 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9434 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
9435 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
9436 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
9437 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
9438 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
9439 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
9440 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
9441 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
9442 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
9443 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
9444 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
9445 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
9446 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9447 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);