arch/x86/kvm/x86.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * derived from drivers/kvm/kvm_main.c
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright (C) 2008 Qumranet, Inc.
   9  * Copyright IBM Corporation, 2008
  10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  11  *
  12  * Authors:
  13  *   Avi Kivity   <avi@qumranet.com>
  14  *   Yaniv Kamay  <yaniv@qumranet.com>
  15  *   Amit Shah    <amit.shah@qumranet.com>
  16  *   Ben-Ami Yassour <benami@il.ibm.com>
  17  */
  18
  19 #include <linux/kvm_host.h>
  20 #include "irq.h"
  21 #include "ioapic.h"
  22 #include "mmu.h"
  23 #include "i8254.h"
  24 #include "tss.h"
  25 #include "kvm_cache_regs.h"
  26 #include "kvm_emulate.h"
  27 #include "x86.h"
  28 #include "cpuid.h"
  29 #include "pmu.h"
  30 #include "hyperv.h"
  31 #include "lapic.h"
  32
  33 #include <linux/clocksource.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/kvm.h>
  36 #include <linux/fs.h>
  37 #include <linux/vmalloc.h>
  38 #include <linux/export.h>
  39 #include <linux/moduleparam.h>
  40 #include <linux/mman.h>
  41 #include <linux/highmem.h>
  42 #include <linux/iommu.h>
  43 #include <linux/intel-iommu.h>
  44 #include <linux/cpufreq.h>
  45 #include <linux/user-return-notifier.h>
  46 #include <linux/srcu.h>
  47 #include <linux/slab.h>
  48 #include <linux/perf_event.h>
  49 #include <linux/uaccess.h>
  50 #include <linux/hash.h>
  51 #include <linux/pci.h>
  52 #include <linux/timekeeper_internal.h>
  53 #include <linux/pvclock_gtod.h>
  54 #include <linux/kvm_irqfd.h>
  55 #include <linux/irqbypass.h>
  56 #include <linux/sched/stat.h>
  57 #include <linux/sched/isolation.h>
  58 #include <linux/mem_encrypt.h>
  59 #include <linux/entry-kvm.h>
  60
  61 #include <trace/events/kvm.h>
  62
  63 #include <asm/debugreg.h>
  64 #include <asm/msr.h>
  65 #include <asm/desc.h>
  66 #include <asm/mce.h>
  67 #include <linux/kernel_stat.h>
  68 #include <asm/fpu/internal.h> /* Ugh! */
  69 #include <asm/pvclock.h>
  70 #include <asm/div64.h>
  71 #include <asm/irq_remapping.h>
  72 #include <asm/mshyperv.h>
  73 #include <asm/hypervisor.h>
  74 #include <asm/tlbflush.h>
  75 #include <asm/intel_pt.h>
  76 #include <asm/emulate_prefix.h>
  77 #include <clocksource/hyperv_timer.h>
  78
  79 #define CREATE_TRACE_POINTS
  80 #include "trace.h"
  81
  82 #define MAX_IO_MSRS 256
  83 #define KVM_MAX_MCE_BANKS 32
  84 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
  85 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
  86
  87 #define emul_to_vcpu(ctxt) \
  88         ((struct kvm_vcpu *)(ctxt)->vcpu)
  89
  90 /* EFER defaults:
  91  * - enable syscall per default because its emulated by KVM
  92  * - enable LME and LMA per default on 64 bit KVM
  93  */
  94 #ifdef CONFIG_X86_64
  95 static
  96 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
  97 #else
  98 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
  99 #endif
 100
 101 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
 102
 103 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
 104                                     KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
 105
 106 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
 107 static void process_nmi(struct kvm_vcpu *vcpu);
 108 static void enter_smm(struct kvm_vcpu *vcpu);
 109 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
 110 static void store_regs(struct kvm_vcpu *vcpu);
 111 static int sync_regs(struct kvm_vcpu *vcpu);
 112
 113 struct kvm_x86_ops kvm_x86_ops __read_mostly;
 114 EXPORT_SYMBOL_GPL(kvm_x86_ops);
 115
 116 static bool __read_mostly ignore_msrs = 0;
 117 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
 118
 119 static bool __read_mostly report_ignored_msrs = true;
 120 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
 121
 122 unsigned int min_timer_period_us = 200;
 123 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
 124
 125 static bool __read_mostly kvmclock_periodic_sync = true;
 126 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
 127
 128 bool __read_mostly kvm_has_tsc_control;
 129 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
 130 u32  __read_mostly kvm_max_guest_tsc_khz;
 131 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
 132 u8   __read_mostly kvm_tsc_scaling_ratio_frac_bits;
 133 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
 134 u64  __read_mostly kvm_max_tsc_scaling_ratio;
 135 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
 136 u64 __read_mostly kvm_default_tsc_scaling_ratio;
 137 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
 138
 139 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
 140 static u32 __read_mostly tsc_tolerance_ppm = 250;
 141 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
 142
 143 /*
 144  * lapic timer advance (tscdeadline mode only) in nanoseconds.  '-1' enables
 145  * adaptive tuning starting from default advancment of 1000ns.  '0' disables
 146  * advancement entirely.  Any other value is used as-is and disables adaptive
 147  * tuning, i.e. allows priveleged userspace to set an exact advancement time.
 148  */
 149 static int __read_mostly lapic_timer_advance_ns = -1;
 150 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
 151
 152 static bool __read_mostly vector_hashing = true;
 153 module_param(vector_hashing, bool, S_IRUGO);
 154
 155 bool __read_mostly enable_vmware_backdoor = false;
 156 module_param(enable_vmware_backdoor, bool, S_IRUGO);
 157 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
 158
 159 static bool __read_mostly force_emulation_prefix = false;
 160 module_param(force_emulation_prefix, bool, S_IRUGO);
 161
 162 int __read_mostly pi_inject_timer = -1;
 163 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
 164
 165 /*
 166  * Restoring the host value for MSRs that are only consumed when running in
 167  * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
 168  * returns to userspace, i.e. the kernel can run with the guest's value.
 169  */
 170 #define KVM_MAX_NR_USER_RETURN_MSRS 16
 171
 172 struct kvm_user_return_msrs_global {
 173         int nr;
 174         u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS];
 175 };
 176
 177 struct kvm_user_return_msrs {
 178         struct user_return_notifier urn;
 179         bool registered;
 180         struct kvm_user_return_msr_values {
 181                 u64 host;
 182                 u64 curr;
 183         } values[KVM_MAX_NR_USER_RETURN_MSRS];
 184 };
 185
 186 static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global;
 187 static struct kvm_user_return_msrs __percpu *user_return_msrs;
 188
 189 #define KVM_SUPPORTED_XCR0     (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
 190                                 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
 191                                 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
 192                                 | XFEATURE_MASK_PKRU)
 193
 194 u64 __read_mostly host_efer;
 195 EXPORT_SYMBOL_GPL(host_efer);
 196
 197 bool __read_mostly allow_smaller_maxphyaddr;
 198 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
 199
 200 static u64 __read_mostly host_xss;
 201 u64 __read_mostly supported_xss;
 202 EXPORT_SYMBOL_GPL(supported_xss);
 203
 204 struct kvm_stats_debugfs_item debugfs_entries[] = {
 205         VCPU_STAT("pf_fixed", pf_fixed),
 206         VCPU_STAT("pf_guest", pf_guest),
 207         VCPU_STAT("tlb_flush", tlb_flush),
 208         VCPU_STAT("invlpg", invlpg),
 209         VCPU_STAT("exits", exits),
 210         VCPU_STAT("io_exits", io_exits),
 211         VCPU_STAT("mmio_exits", mmio_exits),
 212         VCPU_STAT("signal_exits", signal_exits),
 213         VCPU_STAT("irq_window", irq_window_exits),
 214         VCPU_STAT("nmi_window", nmi_window_exits),
 215         VCPU_STAT("halt_exits", halt_exits),
 216         VCPU_STAT("halt_successful_poll", halt_successful_poll),
 217         VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
 218         VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
 219         VCPU_STAT("halt_wakeup", halt_wakeup),
 220         VCPU_STAT("hypercalls", hypercalls),
 221         VCPU_STAT("request_irq", request_irq_exits),
 222         VCPU_STAT("irq_exits", irq_exits),
 223         VCPU_STAT("host_state_reload", host_state_reload),
 224         VCPU_STAT("fpu_reload", fpu_reload),
 225         VCPU_STAT("insn_emulation", insn_emulation),
 226         VCPU_STAT("insn_emulation_fail", insn_emulation_fail),
 227         VCPU_STAT("irq_injections", irq_injections),
 228         VCPU_STAT("nmi_injections", nmi_injections),
 229         VCPU_STAT("req_event", req_event),
 230         VCPU_STAT("l1d_flush", l1d_flush),
 231         VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
 232         VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
 233         VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped),
 234         VM_STAT("mmu_pte_write", mmu_pte_write),
 235         VM_STAT("mmu_pte_updated", mmu_pte_updated),
 236         VM_STAT("mmu_pde_zapped", mmu_pde_zapped),
 237         VM_STAT("mmu_flooded", mmu_flooded),
 238         VM_STAT("mmu_recycled", mmu_recycled),
 239         VM_STAT("mmu_cache_miss", mmu_cache_miss),
 240         VM_STAT("mmu_unsync", mmu_unsync),
 241         VM_STAT("remote_tlb_flush", remote_tlb_flush),
 242         VM_STAT("largepages", lpages, .mode = 0444),
 243         VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444),
 244         VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions),
 245         { NULL }
 246 };
 247
 248 u64 __read_mostly host_xcr0;
 249 u64 __read_mostly supported_xcr0;
 250 EXPORT_SYMBOL_GPL(supported_xcr0);
 251
 252 static struct kmem_cache *x86_fpu_cache;
 253
 254 static struct kmem_cache *x86_emulator_cache;
 255
 256 /*
 257  * When called, it means the previous get/set msr reached an invalid msr.
 258  * Return 0 if we want to ignore/silent this failed msr access, or 1 if we want
 259  * to fail the caller.
 260  */
 261 static int kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr,
 262                                  u64 data, bool write)
 263 {
 264         const char *op = write ? "wrmsr" : "rdmsr";
 265
 266         if (ignore_msrs) {
 267                 if (report_ignored_msrs)
 268                         vcpu_unimpl(vcpu, "ignored %s: 0x%x data 0x%llx\n",
 269                                     op, msr, data);
 270                 /* Mask the error */
 271                 return 0;
 272         } else {
 273                 vcpu_debug_ratelimited(vcpu, "unhandled %s: 0x%x data 0x%llx\n",
 274                                        op, msr, data);
 275                 return -ENOENT;
 276         }
 277 }
 278
 279 static struct kmem_cache *kvm_alloc_emulator_cache(void)
 280 {
 281         unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
 282         unsigned int size = sizeof(struct x86_emulate_ctxt);
 283
 284         return kmem_cache_create_usercopy("x86_emulator", size,
 285                                           __alignof__(struct x86_emulate_ctxt),
 286                                           SLAB_ACCOUNT, useroffset,
 287                                           size - useroffset, NULL);
 288 }
 289
 290 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
 291
 292 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
 293 {
 294         int i;
 295         for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
 296                 vcpu->arch.apf.gfns[i] = ~0;
 297 }
 298
 299 static void kvm_on_user_return(struct user_return_notifier *urn)
 300 {
 301         unsigned slot;
 302         struct kvm_user_return_msrs *msrs
 303                 = container_of(urn, struct kvm_user_return_msrs, urn);
 304         struct kvm_user_return_msr_values *values;
 305         unsigned long flags;
 306
 307         /*
 308          * Disabling irqs at this point since the following code could be
 309          * interrupted and executed through kvm_arch_hardware_disable()
 310          */
 311         local_irq_save(flags);
 312         if (msrs->registered) {
 313                 msrs->registered = false;
 314                 user_return_notifier_unregister(urn);
 315         }
 316         local_irq_restore(flags);
 317         for (slot = 0; slot < user_return_msrs_global.nr; ++slot) {
 318                 values = &msrs->values[slot];
 319                 if (values->host != values->curr) {
 320                         wrmsrl(user_return_msrs_global.msrs[slot], values->host);
 321                         values->curr = values->host;
 322                 }
 323         }
 324 }
 325
 326 void kvm_define_user_return_msr(unsigned slot, u32 msr)
 327 {
 328         BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS);
 329         user_return_msrs_global.msrs[slot] = msr;
 330         if (slot >= user_return_msrs_global.nr)
 331                 user_return_msrs_global.nr = slot + 1;
 332 }
 333 EXPORT_SYMBOL_GPL(kvm_define_user_return_msr);
 334
 335 static void kvm_user_return_msr_cpu_online(void)
 336 {
 337         unsigned int cpu = smp_processor_id();
 338         struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
 339         u64 value;
 340         int i;
 341
 342         for (i = 0; i < user_return_msrs_global.nr; ++i) {
 343                 rdmsrl_safe(user_return_msrs_global.msrs[i], &value);
 344                 msrs->values[i].host = value;
 345                 msrs->values[i].curr = value;
 346         }
 347 }
 348
 349 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
 350 {
 351         unsigned int cpu = smp_processor_id();
 352         struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
 353         int err;
 354
 355         value = (value & mask) | (msrs->values[slot].host & ~mask);
 356         if (value == msrs->values[slot].curr)
 357                 return 0;
 358         err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value);
 359         if (err)
 360                 return 1;
 361
 362         msrs->values[slot].curr = value;
 363         if (!msrs->registered) {
 364                 msrs->urn.on_user_return = kvm_on_user_return;
 365                 user_return_notifier_register(&msrs->urn);
 366                 msrs->registered = true;
 367         }
 368         return 0;
 369 }
 370 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
 371
 372 static void drop_user_return_notifiers(void)
 373 {
 374         unsigned int cpu = smp_processor_id();
 375         struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
 376
 377         if (msrs->registered)
 378                 kvm_on_user_return(&msrs->urn);
 379 }
 380
 381 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
 382 {
 383         return vcpu->arch.apic_base;
 384 }
 385 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
 386
 387 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
 388 {
 389         return kvm_apic_mode(kvm_get_apic_base(vcpu));
 390 }
 391 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
 392
 393 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 394 {
 395         enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
 396         enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
 397         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
 398                 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
 399
 400         if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
 401                 return 1;
 402         if (!msr_info->host_initiated) {
 403                 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
 404                         return 1;
 405                 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
 406                         return 1;
 407         }
 408
 409         kvm_lapic_set_base(vcpu, msr_info->data);
 410         kvm_recalculate_apic_map(vcpu->kvm);
 411         return 0;
 412 }
 413 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
 414
 415 asmlinkage __visible noinstr void kvm_spurious_fault(void)
 416 {
 417         /* Fault while not rebooting.  We want the trace. */
 418         BUG_ON(!kvm_rebooting);
 419 }
 420 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
 421
 422 #define EXCPT_BENIGN            0
 423 #define EXCPT_CONTRIBUTORY      1
 424 #define EXCPT_PF                2
 425
 426 static int exception_class(int vector)
 427 {
 428         switch (vector) {
 429         case PF_VECTOR:
 430                 return EXCPT_PF;
 431         case DE_VECTOR:
 432         case TS_VECTOR:
 433         case NP_VECTOR:
 434         case SS_VECTOR:
 435         case GP_VECTOR:
 436                 return EXCPT_CONTRIBUTORY;
 437         default:
 438                 break;
 439         }
 440         return EXCPT_BENIGN;
 441 }
 442
 443 #define EXCPT_FAULT             0
 444 #define EXCPT_TRAP              1
 445 #define EXCPT_ABORT             2
 446 #define EXCPT_INTERRUPT         3
 447
 448 static int exception_type(int vector)
 449 {
 450         unsigned int mask;
 451
 452         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
 453                 return EXCPT_INTERRUPT;
 454
 455         mask = 1 << vector;
 456
 457         /* #DB is trap, as instruction watchpoints are handled elsewhere */
 458         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
 459                 return EXCPT_TRAP;
 460
 461         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
 462                 return EXCPT_ABORT;
 463
 464         /* Reserved exceptions will result in fault */
 465         return EXCPT_FAULT;
 466 }
 467
 468 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
 469 {
 470         unsigned nr = vcpu->arch.exception.nr;
 471         bool has_payload = vcpu->arch.exception.has_payload;
 472         unsigned long payload = vcpu->arch.exception.payload;
 473
 474         if (!has_payload)
 475                 return;
 476
 477         switch (nr) {
 478         case DB_VECTOR:
 479                 /*
 480                  * "Certain debug exceptions may clear bit 0-3.  The
 481                  * remaining contents of the DR6 register are never
 482                  * cleared by the processor".
 483                  */
 484                 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
 485                 /*
 486                  * DR6.RTM is set by all #DB exceptions that don't clear it.
 487                  */
 488                 vcpu->arch.dr6 |= DR6_RTM;
 489                 vcpu->arch.dr6 |= payload;
 490                 /*
 491                  * Bit 16 should be set in the payload whenever the #DB
 492                  * exception should clear DR6.RTM. This makes the payload
 493                  * compatible with the pending debug exceptions under VMX.
 494                  * Though not currently documented in the SDM, this also
 495                  * makes the payload compatible with the exit qualification
 496                  * for #DB exceptions under VMX.
 497                  */
 498                 vcpu->arch.dr6 ^= payload & DR6_RTM;
 499
 500                 /*
 501                  * The #DB payload is defined as compatible with the 'pending
 502                  * debug exceptions' field under VMX, not DR6. While bit 12 is
 503                  * defined in the 'pending debug exceptions' field (enabled
 504                  * breakpoint), it is reserved and must be zero in DR6.
 505                  */
 506                 vcpu->arch.dr6 &= ~BIT(12);
 507                 break;
 508         case PF_VECTOR:
 509                 vcpu->arch.cr2 = payload;
 510                 break;
 511         }
 512
 513         vcpu->arch.exception.has_payload = false;
 514         vcpu->arch.exception.payload = 0;
 515 }
 516 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
 517
 518 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
 519                 unsigned nr, bool has_error, u32 error_code,
 520                 bool has_payload, unsigned long payload, bool reinject)
 521 {
 522         u32 prev_nr;
 523         int class1, class2;
 524
 525         kvm_make_request(KVM_REQ_EVENT, vcpu);
 526
 527         if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
 528         queue:
 529                 if (has_error && !is_protmode(vcpu))
 530                         has_error = false;
 531                 if (reinject) {
 532                         /*
 533                          * On vmentry, vcpu->arch.exception.pending is only
 534                          * true if an event injection was blocked by
 535                          * nested_run_pending.  In that case, however,
 536                          * vcpu_enter_guest requests an immediate exit,
 537                          * and the guest shouldn't proceed far enough to
 538                          * need reinjection.
 539                          */
 540                         WARN_ON_ONCE(vcpu->arch.exception.pending);
 541                         vcpu->arch.exception.injected = true;
 542                         if (WARN_ON_ONCE(has_payload)) {
 543                                 /*
 544                                  * A reinjected event has already
 545                                  * delivered its payload.
 546                                  */
 547                                 has_payload = false;
 548                                 payload = 0;
 549                         }
 550                 } else {
 551                         vcpu->arch.exception.pending = true;
 552                         vcpu->arch.exception.injected = false;
 553                 }
 554                 vcpu->arch.exception.has_error_code = has_error;
 555                 vcpu->arch.exception.nr = nr;
 556                 vcpu->arch.exception.error_code = error_code;
 557                 vcpu->arch.exception.has_payload = has_payload;
 558                 vcpu->arch.exception.payload = payload;
 559                 if (!is_guest_mode(vcpu))
 560                         kvm_deliver_exception_payload(vcpu);
 561                 return;
 562         }
 563
 564         /* to check exception */
 565         prev_nr = vcpu->arch.exception.nr;
 566         if (prev_nr == DF_VECTOR) {
 567                 /* triple fault -> shutdown */
 568                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
 569                 return;
 570         }
 571         class1 = exception_class(prev_nr);
 572         class2 = exception_class(nr);
 573         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
 574                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
 575                 /*
 576                  * Generate double fault per SDM Table 5-5.  Set
 577                  * exception.pending = true so that the double fault
 578                  * can trigger a nested vmexit.
 579                  */
 580                 vcpu->arch.exception.pending = true;
 581                 vcpu->arch.exception.injected = false;
 582                 vcpu->arch.exception.has_error_code = true;
 583                 vcpu->arch.exception.nr = DF_VECTOR;
 584                 vcpu->arch.exception.error_code = 0;
 585                 vcpu->arch.exception.has_payload = false;
 586                 vcpu->arch.exception.payload = 0;
 587         } else
 588                 /* replace previous exception with a new one in a hope
 589                    that instruction re-execution will regenerate lost
 590                    exception */
 591                 goto queue;
 592 }
 593
 594 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 595 {
 596         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
 597 }
 598 EXPORT_SYMBOL_GPL(kvm_queue_exception);
 599
 600 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 601 {
 602         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
 603 }
 604 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
 605
 606 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
 607                            unsigned long payload)
 608 {
 609         kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
 610 }
 611 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
 612
 613 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
 614                                     u32 error_code, unsigned long payload)
 615 {
 616         kvm_multiple_exception(vcpu, nr, true, error_code,
 617                                true, payload, false);
 618 }
 619
 620 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
 621 {
 622         if (err)
 623                 kvm_inject_gp(vcpu, 0);
 624         else
 625                 return kvm_skip_emulated_instruction(vcpu);
 626
 627         return 1;
 628 }
 629 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
 630
 631 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 632 {
 633         ++vcpu->stat.pf_guest;
 634         vcpu->arch.exception.nested_apf =
 635                 is_guest_mode(vcpu) && fault->async_page_fault;
 636         if (vcpu->arch.exception.nested_apf) {
 637                 vcpu->arch.apf.nested_apf_token = fault->address;
 638                 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
 639         } else {
 640                 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
 641                                         fault->address);
 642         }
 643 }
 644 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
 645
 646 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
 647                                     struct x86_exception *fault)
 648 {
 649         struct kvm_mmu *fault_mmu;
 650         WARN_ON_ONCE(fault->vector != PF_VECTOR);
 651
 652         fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
 653                                                vcpu->arch.walk_mmu;
 654
 655         /*
 656          * Invalidate the TLB entry for the faulting address, if it exists,
 657          * else the access will fault indefinitely (and to emulate hardware).
 658          */
 659         if ((fault->error_code & PFERR_PRESENT_MASK) &&
 660             !(fault->error_code & PFERR_RSVD_MASK))
 661                 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
 662                                        fault_mmu->root_hpa);
 663
 664         fault_mmu->inject_page_fault(vcpu, fault);
 665         return fault->nested_page_fault;
 666 }
 667 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
 668
 669 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
 670 {
 671         atomic_inc(&vcpu->arch.nmi_queued);
 672         kvm_make_request(KVM_REQ_NMI, vcpu);
 673 }
 674 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
 675
 676 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 677 {
 678         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
 679 }
 680 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
 681
 682 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 683 {
 684         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
 685 }
 686 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
 687
 688 /*
 689  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
 690  * a #GP and return false.
 691  */
 692 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
 693 {
 694         if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl)
 695                 return true;
 696         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
 697         return false;
 698 }
 699 EXPORT_SYMBOL_GPL(kvm_require_cpl);
 700
 701 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
 702 {
 703         if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 704                 return true;
 705
 706         kvm_queue_exception(vcpu, UD_VECTOR);
 707         return false;
 708 }
 709 EXPORT_SYMBOL_GPL(kvm_require_dr);
 710
 711 /*
 712  * This function will be used to read from the physical memory of the currently
 713  * running guest. The difference to kvm_vcpu_read_guest_page is that this function
 714  * can read from guest physical or from the guest's guest physical memory.
 715  */
 716 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 717                             gfn_t ngfn, void *data, int offset, int len,
 718                             u32 access)
 719 {
 720         struct x86_exception exception;
 721         gfn_t real_gfn;
 722         gpa_t ngpa;
 723
 724         ngpa     = gfn_to_gpa(ngfn);
 725         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
 726         if (real_gfn == UNMAPPED_GVA)
 727                 return -EFAULT;
 728
 729         real_gfn = gpa_to_gfn(real_gfn);
 730
 731         return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
 732 }
 733 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
 734
 735 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
 736                                void *data, int offset, int len, u32 access)
 737 {
 738         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
 739                                        data, offset, len, access);
 740 }
 741
 742 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
 743 {
 744         return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
 745                rsvd_bits(1, 2);
 746 }
 747
 748 /*
 749  * Load the pae pdptrs.  Return 1 if they are all valid, 0 otherwise.
 750  */
 751 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
 752 {
 753         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
 754         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
 755         int i;
 756         int ret;
 757         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
 758
 759         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
 760                                       offset * sizeof(u64), sizeof(pdpte),
 761                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
 762         if (ret < 0) {
 763                 ret = 0;
 764                 goto out;
 765         }
 766         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
 767                 if ((pdpte[i] & PT_PRESENT_MASK) &&
 768                     (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
 769                         ret = 0;
 770                         goto out;
 771                 }
 772         }
 773         ret = 1;
 774
 775         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
 776         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
 777
 778 out:
 779
 780         return ret;
 781 }
 782 EXPORT_SYMBOL_GPL(load_pdptrs);
 783
 784 bool pdptrs_changed(struct kvm_vcpu *vcpu)
 785 {
 786         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
 787         int offset;
 788         gfn_t gfn;
 789         int r;
 790
 791         if (!is_pae_paging(vcpu))
 792                 return false;
 793
 794         if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
 795                 return true;
 796
 797         gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
 798         offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
 799         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
 800                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
 801         if (r < 0)
 802                 return true;
 803
 804         return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
 805 }
 806 EXPORT_SYMBOL_GPL(pdptrs_changed);
 807
 808 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 809 {
 810         unsigned long old_cr0 = kvm_read_cr0(vcpu);
 811         unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG;
 812         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
 813
 814         cr0 |= X86_CR0_ET;
 815
 816 #ifdef CONFIG_X86_64
 817         if (cr0 & 0xffffffff00000000UL)
 818                 return 1;
 819 #endif
 820
 821         cr0 &= ~CR0_RESERVED_BITS;
 822
 823         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
 824                 return 1;
 825
 826         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
 827                 return 1;
 828
 829 #ifdef CONFIG_X86_64
 830         if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
 831             (cr0 & X86_CR0_PG)) {
 832                 int cs_db, cs_l;
 833
 834                 if (!is_pae(vcpu))
 835                         return 1;
 836                 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
 837                 if (cs_l)
 838                         return 1;
 839         }
 840 #endif
 841         if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
 842             is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) &&
 843             !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)))
 844                 return 1;
 845
 846         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
 847                 return 1;
 848
 849         kvm_x86_ops.set_cr0(vcpu, cr0);
 850
 851         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
 852                 kvm_clear_async_pf_completion_queue(vcpu);
 853                 kvm_async_pf_hash_reset(vcpu);
 854         }
 855
 856         if ((cr0 ^ old_cr0) & update_bits)
 857                 kvm_mmu_reset_context(vcpu);
 858
 859         if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
 860             kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
 861             !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
 862                 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
 863
 864         return 0;
 865 }
 866 EXPORT_SYMBOL_GPL(kvm_set_cr0);
 867
 868 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 869 {
 870         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
 871 }
 872 EXPORT_SYMBOL_GPL(kvm_lmsw);
 873
 874 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
 875 {
 876         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
 877
 878                 if (vcpu->arch.xcr0 != host_xcr0)
 879                         xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
 880
 881                 if (vcpu->arch.xsaves_enabled &&
 882                     vcpu->arch.ia32_xss != host_xss)
 883                         wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
 884         }
 885
 886         if (static_cpu_has(X86_FEATURE_PKU) &&
 887             (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
 888              (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
 889             vcpu->arch.pkru != vcpu->arch.host_pkru)
 890                 __write_pkru(vcpu->arch.pkru);
 891 }
 892 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
 893
 894 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
 895 {
 896         if (static_cpu_has(X86_FEATURE_PKU) &&
 897             (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
 898              (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
 899                 vcpu->arch.pkru = rdpkru();
 900                 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
 901                         __write_pkru(vcpu->arch.host_pkru);
 902         }
 903
 904         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
 905
 906                 if (vcpu->arch.xcr0 != host_xcr0)
 907                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
 908
 909                 if (vcpu->arch.xsaves_enabled &&
 910                     vcpu->arch.ia32_xss != host_xss)
 911                         wrmsrl(MSR_IA32_XSS, host_xss);
 912         }
 913
 914 }
 915 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
 916
 917 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 918 {
 919         u64 xcr0 = xcr;
 920         u64 old_xcr0 = vcpu->arch.xcr0;
 921         u64 valid_bits;
 922
 923         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
 924         if (index != XCR_XFEATURE_ENABLED_MASK)
 925                 return 1;
 926         if (!(xcr0 & XFEATURE_MASK_FP))
 927                 return 1;
 928         if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
 929                 return 1;
 930
 931         /*
 932          * Do not allow the guest to set bits that we do not support
 933          * saving.  However, xcr0 bit 0 is always set, even if the
 934          * emulated CPU does not support XSAVE (see fx_init).
 935          */
 936         valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
 937         if (xcr0 & ~valid_bits)
 938                 return 1;
 939
 940         if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
 941             (!(xcr0 & XFEATURE_MASK_BNDCSR)))
 942                 return 1;
 943
 944         if (xcr0 & XFEATURE_MASK_AVX512) {
 945                 if (!(xcr0 & XFEATURE_MASK_YMM))
 946                         return 1;
 947                 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
 948                         return 1;
 949         }
 950         vcpu->arch.xcr0 = xcr0;
 951
 952         if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
 953                 kvm_update_cpuid_runtime(vcpu);
 954         return 0;
 955 }
 956
 957 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 958 {
 959         if (kvm_x86_ops.get_cpl(vcpu) != 0 ||
 960             __kvm_set_xcr(vcpu, index, xcr)) {
 961                 kvm_inject_gp(vcpu, 0);
 962                 return 1;
 963         }
 964         return 0;
 965 }
 966 EXPORT_SYMBOL_GPL(kvm_set_xcr);
 967
 968 int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 969 {
 970         if (cr4 & cr4_reserved_bits)
 971                 return -EINVAL;
 972
 973         if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
 974                 return -EINVAL;
 975
 976         return 0;
 977 }
 978 EXPORT_SYMBOL_GPL(kvm_valid_cr4);
 979
 980 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 981 {
 982         unsigned long old_cr4 = kvm_read_cr4(vcpu);
 983         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
 984                                    X86_CR4_SMEP;
 985
 986         if (kvm_valid_cr4(vcpu, cr4))
 987                 return 1;
 988
 989         if (is_long_mode(vcpu)) {
 990                 if (!(cr4 & X86_CR4_PAE))
 991                         return 1;
 992                 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
 993                         return 1;
 994         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
 995                    && ((cr4 ^ old_cr4) & pdptr_bits)
 996                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 997                                    kvm_read_cr3(vcpu)))
 998                 return 1;
 999
1000         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1001                 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1002                         return 1;
1003
1004                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1005                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1006                         return 1;
1007         }
1008
1009         if (kvm_x86_ops.set_cr4(vcpu, cr4))
1010                 return 1;
1011
1012         if (((cr4 ^ old_cr4) & pdptr_bits) ||
1013             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1014                 kvm_mmu_reset_context(vcpu);
1015
1016         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1017                 kvm_update_cpuid_runtime(vcpu);
1018
1019         return 0;
1020 }
1021 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1022
1023 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1024 {
1025         bool skip_tlb_flush = false;
1026 #ifdef CONFIG_X86_64
1027         bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1028
1029         if (pcid_enabled) {
1030                 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1031                 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1032         }
1033 #endif
1034
1035         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1036                 if (!skip_tlb_flush) {
1037                         kvm_mmu_sync_roots(vcpu);
1038                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1039                 }
1040                 return 0;
1041         }
1042
1043         if (is_long_mode(vcpu) &&
1044             (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
1045                 return 1;
1046         else if (is_pae_paging(vcpu) &&
1047                  !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1048                 return 1;
1049
1050         kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush);
1051         vcpu->arch.cr3 = cr3;
1052         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1053
1054         return 0;
1055 }
1056 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1057
1058 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1059 {
1060         if (cr8 & CR8_RESERVED_BITS)
1061                 return 1;
1062         if (lapic_in_kernel(vcpu))
1063                 kvm_lapic_set_tpr(vcpu, cr8);
1064         else
1065                 vcpu->arch.cr8 = cr8;
1066         return 0;
1067 }
1068 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1069
1070 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1071 {
1072         if (lapic_in_kernel(vcpu))
1073                 return kvm_lapic_get_cr8(vcpu);
1074         else
1075                 return vcpu->arch.cr8;
1076 }
1077 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1078
1079 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1080 {
1081         int i;
1082
1083         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1084                 for (i = 0; i < KVM_NR_DB_REGS; i++)
1085                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1086                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1087         }
1088 }
1089
1090 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1091 {
1092         unsigned long dr7;
1093
1094         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1095                 dr7 = vcpu->arch.guest_debug_dr7;
1096         else
1097                 dr7 = vcpu->arch.dr7;
1098         kvm_x86_ops.set_dr7(vcpu, dr7);
1099         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1100         if (dr7 & DR7_BP_EN_MASK)
1101                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1102 }
1103 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1104
1105 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1106 {
1107         u64 fixed = DR6_FIXED_1;
1108
1109         if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1110                 fixed |= DR6_RTM;
1111         return fixed;
1112 }
1113
1114 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1115 {
1116         size_t size = ARRAY_SIZE(vcpu->arch.db);
1117
1118         switch (dr) {
1119         case 0 ... 3:
1120                 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1121                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1122                         vcpu->arch.eff_db[dr] = val;
1123                 break;
1124         case 4:
1125         case 6:
1126                 if (!kvm_dr6_valid(val))
1127                         return -1; /* #GP */
1128                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1129                 break;
1130         case 5:
1131         default: /* 7 */
1132                 if (!kvm_dr7_valid(val))
1133                         return -1; /* #GP */
1134                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1135                 kvm_update_dr7(vcpu);
1136                 break;
1137         }
1138
1139         return 0;
1140 }
1141
1142 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1143 {
1144         if (__kvm_set_dr(vcpu, dr, val)) {
1145                 kvm_inject_gp(vcpu, 0);
1146                 return 1;
1147         }
1148         return 0;
1149 }
1150 EXPORT_SYMBOL_GPL(kvm_set_dr);
1151
1152 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1153 {
1154         size_t size = ARRAY_SIZE(vcpu->arch.db);
1155
1156         switch (dr) {
1157         case 0 ... 3:
1158                 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1159                 break;
1160         case 4:
1161         case 6:
1162                 *val = vcpu->arch.dr6;
1163                 break;
1164         case 5:
1165         default: /* 7 */
1166                 *val = vcpu->arch.dr7;
1167                 break;
1168         }
1169         return 0;
1170 }
1171 EXPORT_SYMBOL_GPL(kvm_get_dr);
1172
1173 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1174 {
1175         u32 ecx = kvm_rcx_read(vcpu);
1176         u64 data;
1177         int err;
1178
1179         err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1180         if (err)
1181                 return err;
1182         kvm_rax_write(vcpu, (u32)data);
1183         kvm_rdx_write(vcpu, data >> 32);
1184         return err;
1185 }
1186 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1187
1188 /*
1189  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1190  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1191  *
1192  * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1193  * extract the supported MSRs from the related const lists.
1194  * msrs_to_save is selected from the msrs_to_save_all to reflect the
1195  * capabilities of the host cpu. This capabilities test skips MSRs that are
1196  * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1197  * may depend on host virtualization features rather than host cpu features.
1198  */
1199
1200 static const u32 msrs_to_save_all[] = {
1201         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1202         MSR_STAR,
1203 #ifdef CONFIG_X86_64
1204         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1205 #endif
1206         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1207         MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1208         MSR_IA32_SPEC_CTRL,
1209         MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1210         MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1211         MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1212         MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1213         MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1214         MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1215         MSR_IA32_UMWAIT_CONTROL,
1216
1217         MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1218         MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1219         MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1220         MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1221         MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1222         MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1223         MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1224         MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1225         MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1226         MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1227         MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1228         MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1229         MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1230         MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1231         MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1232         MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1233         MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1234         MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1235         MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1236         MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1237         MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1238         MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1239 };
1240
1241 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1242 static unsigned num_msrs_to_save;
1243
1244 static const u32 emulated_msrs_all[] = {
1245         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1246         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1247         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1248         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1249         HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1250         HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1251         HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1252         HV_X64_MSR_RESET,
1253         HV_X64_MSR_VP_INDEX,
1254         HV_X64_MSR_VP_RUNTIME,
1255         HV_X64_MSR_SCONTROL,
1256         HV_X64_MSR_STIMER0_CONFIG,
1257         HV_X64_MSR_VP_ASSIST_PAGE,
1258         HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1259         HV_X64_MSR_TSC_EMULATION_STATUS,
1260         HV_X64_MSR_SYNDBG_OPTIONS,
1261         HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1262         HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1263         HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1264
1265         MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1266         MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1267
1268         MSR_IA32_TSC_ADJUST,
1269         MSR_IA32_TSCDEADLINE,
1270         MSR_IA32_ARCH_CAPABILITIES,
1271         MSR_IA32_PERF_CAPABILITIES,
1272         MSR_IA32_MISC_ENABLE,
1273         MSR_IA32_MCG_STATUS,
1274         MSR_IA32_MCG_CTL,
1275         MSR_IA32_MCG_EXT_CTL,
1276         MSR_IA32_SMBASE,
1277         MSR_SMI_COUNT,
1278         MSR_PLATFORM_INFO,
1279         MSR_MISC_FEATURES_ENABLES,
1280         MSR_AMD64_VIRT_SPEC_CTRL,
1281         MSR_IA32_POWER_CTL,
1282         MSR_IA32_UCODE_REV,
1283
1284         /*
1285          * The following list leaves out MSRs whose values are determined
1286          * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1287          * We always support the "true" VMX control MSRs, even if the host
1288          * processor does not, so I am putting these registers here rather
1289          * than in msrs_to_save_all.
1290          */
1291         MSR_IA32_VMX_BASIC,
1292         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1293         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1294         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1295         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1296         MSR_IA32_VMX_MISC,
1297         MSR_IA32_VMX_CR0_FIXED0,
1298         MSR_IA32_VMX_CR4_FIXED0,
1299         MSR_IA32_VMX_VMCS_ENUM,
1300         MSR_IA32_VMX_PROCBASED_CTLS2,
1301         MSR_IA32_VMX_EPT_VPID_CAP,
1302         MSR_IA32_VMX_VMFUNC,
1303
1304         MSR_K7_HWCR,
1305         MSR_KVM_POLL_CONTROL,
1306 };
1307
1308 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1309 static unsigned num_emulated_msrs;
1310
1311 /*
1312  * List of msr numbers which are used to expose MSR-based features that
1313  * can be used by a hypervisor to validate requested CPU features.
1314  */
1315 static const u32 msr_based_features_all[] = {
1316         MSR_IA32_VMX_BASIC,
1317         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1318         MSR_IA32_VMX_PINBASED_CTLS,
1319         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1320         MSR_IA32_VMX_PROCBASED_CTLS,
1321         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1322         MSR_IA32_VMX_EXIT_CTLS,
1323         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1324         MSR_IA32_VMX_ENTRY_CTLS,
1325         MSR_IA32_VMX_MISC,
1326         MSR_IA32_VMX_CR0_FIXED0,
1327         MSR_IA32_VMX_CR0_FIXED1,
1328         MSR_IA32_VMX_CR4_FIXED0,
1329         MSR_IA32_VMX_CR4_FIXED1,
1330         MSR_IA32_VMX_VMCS_ENUM,
1331         MSR_IA32_VMX_PROCBASED_CTLS2,
1332         MSR_IA32_VMX_EPT_VPID_CAP,
1333         MSR_IA32_VMX_VMFUNC,
1334
1335         MSR_F10H_DECFG,
1336         MSR_IA32_UCODE_REV,
1337         MSR_IA32_ARCH_CAPABILITIES,
1338         MSR_IA32_PERF_CAPABILITIES,
1339 };
1340
1341 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1342 static unsigned int num_msr_based_features;
1343
1344 static u64 kvm_get_arch_capabilities(void)
1345 {
1346         u64 data = 0;
1347
1348         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1349                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1350
1351         /*
1352          * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1353          * the nested hypervisor runs with NX huge pages.  If it is not,
1354          * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1355          * L1 guests, so it need not worry about its own (L2) guests.
1356          */
1357         data |= ARCH_CAP_PSCHANGE_MC_NO;
1358
1359         /*
1360          * If we're doing cache flushes (either "always" or "cond")
1361          * we will do one whenever the guest does a vmlaunch/vmresume.
1362          * If an outer hypervisor is doing the cache flush for us
1363          * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1364          * capability to the guest too, and if EPT is disabled we're not
1365          * vulnerable.  Overall, only VMENTER_L1D_FLUSH_NEVER will
1366          * require a nested hypervisor to do a flush of its own.
1367          */
1368         if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1369                 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1370
1371         if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1372                 data |= ARCH_CAP_RDCL_NO;
1373         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1374                 data |= ARCH_CAP_SSB_NO;
1375         if (!boot_cpu_has_bug(X86_BUG_MDS))
1376                 data |= ARCH_CAP_MDS_NO;
1377
1378         /*
1379          * On TAA affected systems:
1380          *      - nothing to do if TSX is disabled on the host.
1381          *      - we emulate TSX_CTRL if present on the host.
1382          *        This lets the guest use VERW to clear CPU buffers.
1383          */
1384         if (!boot_cpu_has(X86_FEATURE_RTM))
1385                 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1386         else if (!boot_cpu_has_bug(X86_BUG_TAA))
1387                 data |= ARCH_CAP_TAA_NO;
1388
1389         return data;
1390 }
1391
1392 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1393 {
1394         switch (msr->index) {
1395         case MSR_IA32_ARCH_CAPABILITIES:
1396                 msr->data = kvm_get_arch_capabilities();
1397                 break;
1398         case MSR_IA32_UCODE_REV:
1399                 rdmsrl_safe(msr->index, &msr->data);
1400                 break;
1401         default:
1402                 return kvm_x86_ops.get_msr_feature(msr);
1403         }
1404         return 0;
1405 }
1406
1407 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1408 {
1409         struct kvm_msr_entry msr;
1410         int r;
1411
1412         msr.index = index;
1413         r = kvm_get_msr_feature(&msr);
1414
1415         if (r == KVM_MSR_RET_INVALID) {
1416                 /* Unconditionally clear the output for simplicity */
1417                 *data = 0;
1418                 r = kvm_msr_ignored_check(vcpu, index, 0, false);
1419         }
1420
1421         if (r)
1422                 return r;
1423
1424         *data = msr.data;
1425
1426         return 0;
1427 }
1428
1429 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1430 {
1431         if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1432                 return false;
1433
1434         if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1435                 return false;
1436
1437         if (efer & (EFER_LME | EFER_LMA) &&
1438             !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1439                 return false;
1440
1441         if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1442                 return false;
1443
1444         return true;
1445
1446 }
1447 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1448 {
1449         if (efer & efer_reserved_bits)
1450                 return false;
1451
1452         return __kvm_valid_efer(vcpu, efer);
1453 }
1454 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1455
1456 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1457 {
1458         u64 old_efer = vcpu->arch.efer;
1459         u64 efer = msr_info->data;
1460
1461         if (efer & efer_reserved_bits)
1462                 return 1;
1463
1464         if (!msr_info->host_initiated) {
1465                 if (!__kvm_valid_efer(vcpu, efer))
1466                         return 1;
1467
1468                 if (is_paging(vcpu) &&
1469                     (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1470                         return 1;
1471         }
1472
1473         efer &= ~EFER_LMA;
1474         efer |= vcpu->arch.efer & EFER_LMA;
1475
1476         kvm_x86_ops.set_efer(vcpu, efer);
1477
1478         /* Update reserved bits */
1479         if ((efer ^ old_efer) & EFER_NX)
1480                 kvm_mmu_reset_context(vcpu);
1481
1482         return 0;
1483 }
1484
1485 void kvm_enable_efer_bits(u64 mask)
1486 {
1487        efer_reserved_bits &= ~mask;
1488 }
1489 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1490
1491 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1492 {
1493         struct kvm *kvm = vcpu->kvm;
1494         struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
1495         u32 count = kvm->arch.msr_filter.count;
1496         u32 i;
1497         bool r = kvm->arch.msr_filter.default_allow;
1498         int idx;
1499
1500         /* MSR filtering not set up or x2APIC enabled, allow everything */
1501         if (!count || (index >= 0x800 && index <= 0x8ff))
1502                 return true;
1503
1504         /* Prevent collision with set_msr_filter */
1505         idx = srcu_read_lock(&kvm->srcu);
1506
1507         for (i = 0; i < count; i++) {
1508                 u32 start = ranges[i].base;
1509                 u32 end = start + ranges[i].nmsrs;
1510                 u32 flags = ranges[i].flags;
1511                 unsigned long *bitmap = ranges[i].bitmap;
1512
1513                 if ((index >= start) && (index < end) && (flags & type)) {
1514                         r = !!test_bit(index - start, bitmap);
1515                         break;
1516                 }
1517         }
1518
1519         srcu_read_unlock(&kvm->srcu, idx);
1520
1521         return r;
1522 }
1523 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1524
1525 /*
1526  * Write @data into the MSR specified by @index.  Select MSR specific fault
1527  * checks are bypassed if @host_initiated is %true.
1528  * Returns 0 on success, non-0 otherwise.
1529  * Assumes vcpu_load() was already called.
1530  */
1531 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1532                          bool host_initiated)
1533 {
1534         struct msr_data msr;
1535
1536         if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1537                 return -EPERM;
1538
1539         switch (index) {
1540         case MSR_FS_BASE:
1541         case MSR_GS_BASE:
1542         case MSR_KERNEL_GS_BASE:
1543         case MSR_CSTAR:
1544         case MSR_LSTAR:
1545                 if (is_noncanonical_address(data, vcpu))
1546                         return 1;
1547                 break;
1548         case MSR_IA32_SYSENTER_EIP:
1549         case MSR_IA32_SYSENTER_ESP:
1550                 /*
1551                  * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1552                  * non-canonical address is written on Intel but not on
1553                  * AMD (which ignores the top 32-bits, because it does
1554                  * not implement 64-bit SYSENTER).
1555                  *
1556                  * 64-bit code should hence be able to write a non-canonical
1557                  * value on AMD.  Making the address canonical ensures that
1558                  * vmentry does not fail on Intel after writing a non-canonical
1559                  * value, and that something deterministic happens if the guest
1560                  * invokes 64-bit SYSENTER.
1561                  */
1562                 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1563         }
1564
1565         msr.data = data;
1566         msr.index = index;
1567         msr.host_initiated = host_initiated;
1568
1569         return kvm_x86_ops.set_msr(vcpu, &msr);
1570 }
1571
1572 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1573                                      u32 index, u64 data, bool host_initiated)
1574 {
1575         int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1576
1577         if (ret == KVM_MSR_RET_INVALID)
1578                 ret = kvm_msr_ignored_check(vcpu, index, data, true);
1579
1580         return ret;
1581 }
1582
1583 /*
1584  * Read the MSR specified by @index into @data.  Select MSR specific fault
1585  * checks are bypassed if @host_initiated is %true.
1586  * Returns 0 on success, non-0 otherwise.
1587  * Assumes vcpu_load() was already called.
1588  */
1589 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1590                   bool host_initiated)
1591 {
1592         struct msr_data msr;
1593         int ret;
1594
1595         if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1596                 return -EPERM;
1597
1598         msr.index = index;
1599         msr.host_initiated = host_initiated;
1600
1601         ret = kvm_x86_ops.get_msr(vcpu, &msr);
1602         if (!ret)
1603                 *data = msr.data;
1604         return ret;
1605 }
1606
1607 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1608                                      u32 index, u64 *data, bool host_initiated)
1609 {
1610         int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1611
1612         if (ret == KVM_MSR_RET_INVALID) {
1613                 /* Unconditionally clear *data for simplicity */
1614                 *data = 0;
1615                 ret = kvm_msr_ignored_check(vcpu, index, 0, false);
1616         }
1617
1618         return ret;
1619 }
1620
1621 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1622 {
1623         return kvm_get_msr_ignored_check(vcpu, index, data, false);
1624 }
1625 EXPORT_SYMBOL_GPL(kvm_get_msr);
1626
1627 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1628 {
1629         return kvm_set_msr_ignored_check(vcpu, index, data, false);
1630 }
1631 EXPORT_SYMBOL_GPL(kvm_set_msr);
1632
1633 static int complete_emulated_msr(struct kvm_vcpu *vcpu, bool is_read)
1634 {
1635         if (vcpu->run->msr.error) {
1636                 kvm_inject_gp(vcpu, 0);
1637                 return 1;
1638         } else if (is_read) {
1639                 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1640                 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1641         }
1642
1643         return kvm_skip_emulated_instruction(vcpu);
1644 }
1645
1646 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1647 {
1648         return complete_emulated_msr(vcpu, true);
1649 }
1650
1651 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu)
1652 {
1653         return complete_emulated_msr(vcpu, false);
1654 }
1655
1656 static u64 kvm_msr_reason(int r)
1657 {
1658         switch (r) {
1659         case -ENOENT:
1660                 return KVM_MSR_EXIT_REASON_UNKNOWN;
1661         case -EPERM:
1662                 return KVM_MSR_EXIT_REASON_FILTER;
1663         default:
1664                 return KVM_MSR_EXIT_REASON_INVAL;
1665         }
1666 }
1667
1668 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1669                               u32 exit_reason, u64 data,
1670                               int (*completion)(struct kvm_vcpu *vcpu),
1671                               int r)
1672 {
1673         u64 msr_reason = kvm_msr_reason(r);
1674
1675         /* Check if the user wanted to know about this MSR fault */
1676         if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
1677                 return 0;
1678
1679         vcpu->run->exit_reason = exit_reason;
1680         vcpu->run->msr.error = 0;
1681         memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
1682         vcpu->run->msr.reason = msr_reason;
1683         vcpu->run->msr.index = index;
1684         vcpu->run->msr.data = data;
1685         vcpu->arch.complete_userspace_io = completion;
1686
1687         return 1;
1688 }
1689
1690 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r)
1691 {
1692         return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0,
1693                                    complete_emulated_rdmsr, r);
1694 }
1695
1696 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r)
1697 {
1698         return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data,
1699                                    complete_emulated_wrmsr, r);
1700 }
1701
1702 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1703 {
1704         u32 ecx = kvm_rcx_read(vcpu);
1705         u64 data;
1706         int r;
1707
1708         r = kvm_get_msr(vcpu, ecx, &data);
1709
1710         /* MSR read failed? See if we should ask user space */
1711         if (r && kvm_get_msr_user_space(vcpu, ecx, r)) {
1712                 /* Bounce to user space */
1713                 return 0;
1714         }
1715
1716         /* MSR read failed? Inject a #GP */
1717         if (r) {
1718                 trace_kvm_msr_read_ex(ecx);
1719                 kvm_inject_gp(vcpu, 0);
1720                 return 1;
1721         }
1722
1723         trace_kvm_msr_read(ecx, data);
1724
1725         kvm_rax_write(vcpu, data & -1u);
1726         kvm_rdx_write(vcpu, (data >> 32) & -1u);
1727         return kvm_skip_emulated_instruction(vcpu);
1728 }
1729 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1730
1731 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1732 {
1733         u32 ecx = kvm_rcx_read(vcpu);
1734         u64 data = kvm_read_edx_eax(vcpu);
1735         int r;
1736
1737         r = kvm_set_msr(vcpu, ecx, data);
1738
1739         /* MSR write failed? See if we should ask user space */
1740         if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) {
1741                 /* Bounce to user space */
1742                 return 0;
1743         }
1744
1745         /* MSR write failed? Inject a #GP */
1746         if (r) {
1747                 trace_kvm_msr_write_ex(ecx, data);
1748                 kvm_inject_gp(vcpu, 0);
1749                 return 1;
1750         }
1751
1752         trace_kvm_msr_write(ecx, data);
1753         return kvm_skip_emulated_instruction(vcpu);
1754 }
1755 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1756
1757 bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
1758 {
1759         return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
1760                 xfer_to_guest_mode_work_pending();
1761 }
1762 EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request);
1763
1764 /*
1765  * The fast path for frequent and performance sensitive wrmsr emulation,
1766  * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1767  * the latency of virtual IPI by avoiding the expensive bits of transitioning
1768  * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1769  * other cases which must be called after interrupts are enabled on the host.
1770  */
1771 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1772 {
1773         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1774                 return 1;
1775
1776         if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1777                 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1778                 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1779                 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1780
1781                 data &= ~(1 << 12);
1782                 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1783                 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1784                 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1785                 trace_kvm_apic_write(APIC_ICR, (u32)data);
1786                 return 0;
1787         }
1788
1789         return 1;
1790 }
1791
1792 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
1793 {
1794         if (!kvm_can_use_hv_timer(vcpu))
1795                 return 1;
1796
1797         kvm_set_lapic_tscdeadline_msr(vcpu, data);
1798         return 0;
1799 }
1800
1801 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1802 {
1803         u32 msr = kvm_rcx_read(vcpu);
1804         u64 data;
1805         fastpath_t ret = EXIT_FASTPATH_NONE;
1806
1807         switch (msr) {
1808         case APIC_BASE_MSR + (APIC_ICR >> 4):
1809                 data = kvm_read_edx_eax(vcpu);
1810                 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
1811                         kvm_skip_emulated_instruction(vcpu);
1812                         ret = EXIT_FASTPATH_EXIT_HANDLED;
1813                 }
1814                 break;
1815         case MSR_IA32_TSCDEADLINE:
1816                 data = kvm_read_edx_eax(vcpu);
1817                 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
1818                         kvm_skip_emulated_instruction(vcpu);
1819                         ret = EXIT_FASTPATH_REENTER_GUEST;
1820                 }
1821                 break;
1822         default:
1823                 break;
1824         }
1825
1826         if (ret != EXIT_FASTPATH_NONE)
1827                 trace_kvm_msr_write(msr, data);
1828
1829         return ret;
1830 }
1831 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1832
1833 /*
1834  * Adapt set_msr() to msr_io()'s calling convention
1835  */
1836 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1837 {
1838         return kvm_get_msr_ignored_check(vcpu, index, data, true);
1839 }
1840
1841 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1842 {
1843         return kvm_set_msr_ignored_check(vcpu, index, *data, true);
1844 }
1845
1846 #ifdef CONFIG_X86_64
1847 struct pvclock_clock {
1848         int vclock_mode;
1849         u64 cycle_last;
1850         u64 mask;
1851         u32 mult;
1852         u32 shift;
1853         u64 base_cycles;
1854         u64 offset;
1855 };
1856
1857 struct pvclock_gtod_data {
1858         seqcount_t      seq;
1859
1860         struct pvclock_clock clock; /* extract of a clocksource struct */
1861         struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1862
1863         ktime_t         offs_boot;
1864         u64             wall_time_sec;
1865 };
1866
1867 static struct pvclock_gtod_data pvclock_gtod_data;
1868
1869 static void update_pvclock_gtod(struct timekeeper *tk)
1870 {
1871         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1872
1873         write_seqcount_begin(&vdata->seq);
1874
1875         /* copy pvclock gtod data */
1876         vdata->clock.vclock_mode        = tk->tkr_mono.clock->vdso_clock_mode;
1877         vdata->clock.cycle_last         = tk->tkr_mono.cycle_last;
1878         vdata->clock.mask               = tk->tkr_mono.mask;
1879         vdata->clock.mult               = tk->tkr_mono.mult;
1880         vdata->clock.shift              = tk->tkr_mono.shift;
1881         vdata->clock.base_cycles        = tk->tkr_mono.xtime_nsec;
1882         vdata->clock.offset             = tk->tkr_mono.base;
1883
1884         vdata->raw_clock.vclock_mode    = tk->tkr_raw.clock->vdso_clock_mode;
1885         vdata->raw_clock.cycle_last     = tk->tkr_raw.cycle_last;
1886         vdata->raw_clock.mask           = tk->tkr_raw.mask;
1887         vdata->raw_clock.mult           = tk->tkr_raw.mult;
1888         vdata->raw_clock.shift          = tk->tkr_raw.shift;
1889         vdata->raw_clock.base_cycles    = tk->tkr_raw.xtime_nsec;
1890         vdata->raw_clock.offset         = tk->tkr_raw.base;
1891
1892         vdata->wall_time_sec            = tk->xtime_sec;
1893
1894         vdata->offs_boot                = tk->offs_boot;
1895
1896         write_seqcount_end(&vdata->seq);
1897 }
1898
1899 static s64 get_kvmclock_base_ns(void)
1900 {
1901         /* Count up from boot time, but with the frequency of the raw clock.  */
1902         return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1903 }
1904 #else
1905 static s64 get_kvmclock_base_ns(void)
1906 {
1907         /* Master clock not used, so we can just use CLOCK_BOOTTIME.  */
1908         return ktime_get_boottime_ns();
1909 }
1910 #endif
1911
1912 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1913 {
1914         int version;
1915         int r;
1916         struct pvclock_wall_clock wc;
1917         u64 wall_nsec;
1918
1919         kvm->arch.wall_clock = wall_clock;
1920
1921         if (!wall_clock)
1922                 return;
1923
1924         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1925         if (r)
1926                 return;
1927
1928         if (version & 1)
1929                 ++version;  /* first time write, random junk */
1930
1931         ++version;
1932
1933         if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1934                 return;
1935
1936         /*
1937          * The guest calculates current wall clock time by adding
1938          * system time (updated by kvm_guest_time_update below) to the
1939          * wall clock specified here.  We do the reverse here.
1940          */
1941         wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1942
1943         wc.nsec = do_div(wall_nsec, 1000000000);
1944         wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1945         wc.version = version;
1946
1947         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1948
1949         version++;
1950         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1951 }
1952
1953 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
1954                                   bool old_msr, bool host_initiated)
1955 {
1956         struct kvm_arch *ka = &vcpu->kvm->arch;
1957
1958         if (vcpu->vcpu_id == 0 && !host_initiated) {
1959                 if (ka->boot_vcpu_runs_old_kvmclock && old_msr)
1960                         kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1961
1962                 ka->boot_vcpu_runs_old_kvmclock = old_msr;
1963         }
1964
1965         vcpu->arch.time = system_time;
1966         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
1967
1968         /* we verify if the enable bit is set... */
1969         vcpu->arch.pv_time_enabled = false;
1970         if (!(system_time & 1))
1971                 return;
1972
1973         if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
1974                                        &vcpu->arch.pv_time, system_time & ~1ULL,
1975                                        sizeof(struct pvclock_vcpu_time_info)))
1976                 vcpu->arch.pv_time_enabled = true;
1977
1978         return;
1979 }
1980
1981 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1982 {
1983         do_shl32_div32(dividend, divisor);
1984         return dividend;
1985 }
1986
1987 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1988                                s8 *pshift, u32 *pmultiplier)
1989 {
1990         uint64_t scaled64;
1991         int32_t  shift = 0;
1992         uint64_t tps64;
1993         uint32_t tps32;
1994
1995         tps64 = base_hz;
1996         scaled64 = scaled_hz;
1997         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1998                 tps64 >>= 1;
1999                 shift--;
2000         }
2001
2002         tps32 = (uint32_t)tps64;
2003         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2004                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2005                         scaled64 >>= 1;
2006                 else
2007                         tps32 <<= 1;
2008                 shift++;
2009         }
2010
2011         *pshift = shift;
2012         *pmultiplier = div_frac(scaled64, tps32);
2013 }
2014
2015 #ifdef CONFIG_X86_64
2016 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2017 #endif
2018
2019 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2020 static unsigned long max_tsc_khz;
2021
2022 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2023 {
2024         u64 v = (u64)khz * (1000000 + ppm);
2025         do_div(v, 1000000);
2026         return v;
2027 }
2028
2029 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2030 {
2031         u64 ratio;
2032
2033         /* Guest TSC same frequency as host TSC? */
2034         if (!scale) {
2035                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2036                 return 0;
2037         }
2038
2039         /* TSC scaling supported? */
2040         if (!kvm_has_tsc_control) {
2041                 if (user_tsc_khz > tsc_khz) {
2042                         vcpu->arch.tsc_catchup = 1;
2043                         vcpu->arch.tsc_always_catchup = 1;
2044                         return 0;
2045                 } else {
2046                         pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2047                         return -1;
2048                 }
2049         }
2050
2051         /* TSC scaling required  - calculate ratio */
2052         ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
2053                                 user_tsc_khz, tsc_khz);
2054
2055         if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
2056                 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2057                                     user_tsc_khz);
2058                 return -1;
2059         }
2060
2061         vcpu->arch.tsc_scaling_ratio = ratio;
2062         return 0;
2063 }
2064
2065 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2066 {
2067         u32 thresh_lo, thresh_hi;
2068         int use_scaling = 0;
2069
2070         /* tsc_khz can be zero if TSC calibration fails */
2071         if (user_tsc_khz == 0) {
2072                 /* set tsc_scaling_ratio to a safe value */
2073                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2074                 return -1;
2075         }
2076
2077         /* Compute a scale to convert nanoseconds in TSC cycles */
2078         kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2079                            &vcpu->arch.virtual_tsc_shift,
2080                            &vcpu->arch.virtual_tsc_mult);
2081         vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2082
2083         /*
2084          * Compute the variation in TSC rate which is acceptable
2085          * within the range of tolerance and decide if the
2086          * rate being applied is within that bounds of the hardware
2087          * rate.  If so, no scaling or compensation need be done.
2088          */
2089         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2090         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2091         if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2092                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2093                 use_scaling = 1;
2094         }
2095         return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2096 }
2097
2098 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2099 {
2100         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2101                                       vcpu->arch.virtual_tsc_mult,
2102                                       vcpu->arch.virtual_tsc_shift);
2103         tsc += vcpu->arch.this_tsc_write;
2104         return tsc;
2105 }
2106
2107 static inline int gtod_is_based_on_tsc(int mode)
2108 {
2109         return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2110 }
2111
2112 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2113 {
2114 #ifdef CONFIG_X86_64
2115         bool vcpus_matched;
2116         struct kvm_arch *ka = &vcpu->kvm->arch;
2117         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2118
2119         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2120                          atomic_read(&vcpu->kvm->online_vcpus));
2121
2122         /*
2123          * Once the masterclock is enabled, always perform request in
2124          * order to update it.
2125          *
2126          * In order to enable masterclock, the host clocksource must be TSC
2127          * and the vcpus need to have matched TSCs.  When that happens,
2128          * perform request to enable masterclock.
2129          */
2130         if (ka->use_master_clock ||
2131             (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2132                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2133
2134         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2135                             atomic_read(&vcpu->kvm->online_vcpus),
2136                             ka->use_master_clock, gtod->clock.vclock_mode);
2137 #endif
2138 }
2139
2140 /*
2141  * Multiply tsc by a fixed point number represented by ratio.
2142  *
2143  * The most significant 64-N bits (mult) of ratio represent the
2144  * integral part of the fixed point number; the remaining N bits
2145  * (frac) represent the fractional part, ie. ratio represents a fixed
2146  * point number (mult + frac * 2^(-N)).
2147  *
2148  * N equals to kvm_tsc_scaling_ratio_frac_bits.
2149  */
2150 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2151 {
2152         return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
2153 }
2154
2155 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
2156 {
2157         u64 _tsc = tsc;
2158         u64 ratio = vcpu->arch.tsc_scaling_ratio;
2159
2160         if (ratio != kvm_default_tsc_scaling_ratio)
2161                 _tsc = __scale_tsc(ratio, tsc);
2162
2163         return _tsc;
2164 }
2165 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2166
2167 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2168 {
2169         u64 tsc;
2170
2171         tsc = kvm_scale_tsc(vcpu, rdtsc());
2172
2173         return target_tsc - tsc;
2174 }
2175
2176 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2177 {
2178         return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
2179 }
2180 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2181
2182 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2183 {
2184         vcpu->arch.l1_tsc_offset = offset;
2185         vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset);
2186 }
2187
2188 static inline bool kvm_check_tsc_unstable(void)
2189 {
2190 #ifdef CONFIG_X86_64
2191         /*
2192          * TSC is marked unstable when we're running on Hyper-V,
2193          * 'TSC page' clocksource is good.
2194          */
2195         if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2196                 return false;
2197 #endif
2198         return check_tsc_unstable();
2199 }
2200
2201 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2202 {
2203         struct kvm *kvm = vcpu->kvm;
2204         u64 offset, ns, elapsed;
2205         unsigned long flags;
2206         bool matched;
2207         bool already_matched;
2208         bool synchronizing = false;
2209
2210         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2211         offset = kvm_compute_tsc_offset(vcpu, data);
2212         ns = get_kvmclock_base_ns();
2213         elapsed = ns - kvm->arch.last_tsc_nsec;
2214
2215         if (vcpu->arch.virtual_tsc_khz) {
2216                 if (data == 0) {
2217                         /*
2218                          * detection of vcpu initialization -- need to sync
2219                          * with other vCPUs. This particularly helps to keep
2220                          * kvm_clock stable after CPU hotplug
2221                          */
2222                         synchronizing = true;
2223                 } else {
2224                         u64 tsc_exp = kvm->arch.last_tsc_write +
2225                                                 nsec_to_cycles(vcpu, elapsed);
2226                         u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2227                         /*
2228                          * Special case: TSC write with a small delta (1 second)
2229                          * of virtual cycle time against real time is
2230                          * interpreted as an attempt to synchronize the CPU.
2231                          */
2232                         synchronizing = data < tsc_exp + tsc_hz &&
2233                                         data + tsc_hz > tsc_exp;
2234                 }
2235         }
2236
2237         /*
2238          * For a reliable TSC, we can match TSC offsets, and for an unstable
2239          * TSC, we add elapsed time in this computation.  We could let the
2240          * compensation code attempt to catch up if we fall behind, but
2241          * it's better to try to match offsets from the beginning.
2242          */
2243         if (synchronizing &&
2244             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2245                 if (!kvm_check_tsc_unstable()) {
2246                         offset = kvm->arch.cur_tsc_offset;
2247                 } else {
2248                         u64 delta = nsec_to_cycles(vcpu, elapsed);
2249                         data += delta;
2250                         offset = kvm_compute_tsc_offset(vcpu, data);
2251                 }
2252                 matched = true;
2253                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2254         } else {
2255                 /*
2256                  * We split periods of matched TSC writes into generations.
2257                  * For each generation, we track the original measured
2258                  * nanosecond time, offset, and write, so if TSCs are in
2259                  * sync, we can match exact offset, and if not, we can match
2260                  * exact software computation in compute_guest_tsc()
2261                  *
2262                  * These values are tracked in kvm->arch.cur_xxx variables.
2263                  */
2264                 kvm->arch.cur_tsc_generation++;
2265                 kvm->arch.cur_tsc_nsec = ns;
2266                 kvm->arch.cur_tsc_write = data;
2267                 kvm->arch.cur_tsc_offset = offset;
2268                 matched = false;
2269         }
2270
2271         /*
2272          * We also track th most recent recorded KHZ, write and time to
2273          * allow the matching interval to be extended at each write.
2274          */
2275         kvm->arch.last_tsc_nsec = ns;
2276         kvm->arch.last_tsc_write = data;
2277         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2278
2279         vcpu->arch.last_guest_tsc = data;
2280
2281         /* Keep track of which generation this VCPU has synchronized to */
2282         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2283         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2284         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2285
2286         kvm_vcpu_write_tsc_offset(vcpu, offset);
2287         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2288
2289         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2290         if (!matched) {
2291                 kvm->arch.nr_vcpus_matched_tsc = 0;
2292         } else if (!already_matched) {
2293                 kvm->arch.nr_vcpus_matched_tsc++;
2294         }
2295
2296         kvm_track_tsc_matching(vcpu);
2297         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2298 }
2299
2300 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2301                                            s64 adjustment)
2302 {
2303         u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2304         kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2305 }
2306
2307 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2308 {
2309         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2310                 WARN_ON(adjustment < 0);
2311         adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2312         adjust_tsc_offset_guest(vcpu, adjustment);
2313 }
2314
2315 #ifdef CONFIG_X86_64
2316
2317 static u64 read_tsc(void)
2318 {
2319         u64 ret = (u64)rdtsc_ordered();
2320         u64 last = pvclock_gtod_data.clock.cycle_last;
2321
2322         if (likely(ret >= last))
2323                 return ret;
2324
2325         /*
2326          * GCC likes to generate cmov here, but this branch is extremely
2327          * predictable (it's just a function of time and the likely is
2328          * very likely) and there's a data dependence, so force GCC
2329          * to generate a branch instead.  I don't barrier() because
2330          * we don't actually need a barrier, and if this function
2331          * ever gets inlined it will generate worse code.
2332          */
2333         asm volatile ("");
2334         return last;
2335 }
2336
2337 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2338                           int *mode)
2339 {
2340         long v;
2341         u64 tsc_pg_val;
2342
2343         switch (clock->vclock_mode) {
2344         case VDSO_CLOCKMODE_HVCLOCK:
2345                 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2346                                                   tsc_timestamp);
2347                 if (tsc_pg_val != U64_MAX) {
2348                         /* TSC page valid */
2349                         *mode = VDSO_CLOCKMODE_HVCLOCK;
2350                         v = (tsc_pg_val - clock->cycle_last) &
2351                                 clock->mask;
2352                 } else {
2353                         /* TSC page invalid */
2354                         *mode = VDSO_CLOCKMODE_NONE;
2355                 }
2356                 break;
2357         case VDSO_CLOCKMODE_TSC:
2358                 *mode = VDSO_CLOCKMODE_TSC;
2359                 *tsc_timestamp = read_tsc();
2360                 v = (*tsc_timestamp - clock->cycle_last) &
2361                         clock->mask;
2362                 break;
2363         default:
2364                 *mode = VDSO_CLOCKMODE_NONE;
2365         }
2366
2367         if (*mode == VDSO_CLOCKMODE_NONE)
2368                 *tsc_timestamp = v = 0;
2369
2370         return v * clock->mult;
2371 }
2372
2373 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2374 {
2375         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2376         unsigned long seq;
2377         int mode;
2378         u64 ns;
2379
2380         do {
2381                 seq = read_seqcount_begin(&gtod->seq);
2382                 ns = gtod->raw_clock.base_cycles;
2383                 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2384                 ns >>= gtod->raw_clock.shift;
2385                 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2386         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2387         *t = ns;
2388
2389         return mode;
2390 }
2391
2392 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2393 {
2394         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2395         unsigned long seq;
2396         int mode;
2397         u64 ns;
2398
2399         do {
2400                 seq = read_seqcount_begin(&gtod->seq);
2401                 ts->tv_sec = gtod->wall_time_sec;
2402                 ns = gtod->clock.base_cycles;
2403                 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2404                 ns >>= gtod->clock.shift;
2405         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2406
2407         ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2408         ts->tv_nsec = ns;
2409
2410         return mode;
2411 }
2412
2413 /* returns true if host is using TSC based clocksource */
2414 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2415 {
2416         /* checked again under seqlock below */
2417         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2418                 return false;
2419
2420         return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2421                                                       tsc_timestamp));
2422 }
2423
2424 /* returns true if host is using TSC based clocksource */
2425 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2426                                            u64 *tsc_timestamp)
2427 {
2428         /* checked again under seqlock below */
2429         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2430                 return false;
2431
2432         return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2433 }
2434 #endif
2435
2436 /*
2437  *
2438  * Assuming a stable TSC across physical CPUS, and a stable TSC
2439  * across virtual CPUs, the following condition is possible.
2440  * Each numbered line represents an event visible to both
2441  * CPUs at the next numbered event.
2442  *
2443  * "timespecX" represents host monotonic time. "tscX" represents
2444  * RDTSC value.
2445  *
2446  *              VCPU0 on CPU0           |       VCPU1 on CPU1
2447  *
2448  * 1.  read timespec0,tsc0
2449  * 2.                                   | timespec1 = timespec0 + N
2450  *                                      | tsc1 = tsc0 + M
2451  * 3. transition to guest               | transition to guest
2452  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2453  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
2454  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2455  *
2456  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2457  *
2458  *      - ret0 < ret1
2459  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2460  *              ...
2461  *      - 0 < N - M => M < N
2462  *
2463  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2464  * always the case (the difference between two distinct xtime instances
2465  * might be smaller then the difference between corresponding TSC reads,
2466  * when updating guest vcpus pvclock areas).
2467  *
2468  * To avoid that problem, do not allow visibility of distinct
2469  * system_timestamp/tsc_timestamp values simultaneously: use a master
2470  * copy of host monotonic time values. Update that master copy
2471  * in lockstep.
2472  *
2473  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2474  *
2475  */
2476
2477 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2478 {
2479 #ifdef CONFIG_X86_64
2480         struct kvm_arch *ka = &kvm->arch;
2481         int vclock_mode;
2482         bool host_tsc_clocksource, vcpus_matched;
2483
2484         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2485                         atomic_read(&kvm->online_vcpus));
2486
2487         /*
2488          * If the host uses TSC clock, then passthrough TSC as stable
2489          * to the guest.
2490          */
2491         host_tsc_clocksource = kvm_get_time_and_clockread(
2492                                         &ka->master_kernel_ns,
2493                                         &ka->master_cycle_now);
2494
2495         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2496                                 && !ka->backwards_tsc_observed
2497                                 && !ka->boot_vcpu_runs_old_kvmclock;
2498
2499         if (ka->use_master_clock)
2500                 atomic_set(&kvm_guest_has_master_clock, 1);
2501
2502         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2503         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2504                                         vcpus_matched);
2505 #endif
2506 }
2507
2508 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2509 {
2510         kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2511 }
2512
2513 static void kvm_gen_update_masterclock(struct kvm *kvm)
2514 {
2515 #ifdef CONFIG_X86_64
2516         int i;
2517         struct kvm_vcpu *vcpu;
2518         struct kvm_arch *ka = &kvm->arch;
2519
2520         spin_lock(&ka->pvclock_gtod_sync_lock);
2521         kvm_make_mclock_inprogress_request(kvm);
2522         /* no guest entries from this point */
2523         pvclock_update_vm_gtod_copy(kvm);
2524
2525         kvm_for_each_vcpu(i, vcpu, kvm)
2526                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2527
2528         /* guest entries allowed */
2529         kvm_for_each_vcpu(i, vcpu, kvm)
2530                 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2531
2532         spin_unlock(&ka->pvclock_gtod_sync_lock);
2533 #endif
2534 }
2535
2536 u64 get_kvmclock_ns(struct kvm *kvm)
2537 {
2538         struct kvm_arch *ka = &kvm->arch;
2539         struct pvclock_vcpu_time_info hv_clock;
2540         u64 ret;
2541
2542         spin_lock(&ka->pvclock_gtod_sync_lock);
2543         if (!ka->use_master_clock) {
2544                 spin_unlock(&ka->pvclock_gtod_sync_lock);
2545                 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2546         }
2547
2548         hv_clock.tsc_timestamp = ka->master_cycle_now;
2549         hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2550         spin_unlock(&ka->pvclock_gtod_sync_lock);
2551
2552         /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2553         get_cpu();
2554
2555         if (__this_cpu_read(cpu_tsc_khz)) {
2556                 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2557                                    &hv_clock.tsc_shift,
2558                                    &hv_clock.tsc_to_system_mul);
2559                 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2560         } else
2561                 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2562
2563         put_cpu();
2564
2565         return ret;
2566 }
2567
2568 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2569 {
2570         struct kvm_vcpu_arch *vcpu = &v->arch;
2571         struct pvclock_vcpu_time_info guest_hv_clock;
2572
2573         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2574                 &guest_hv_clock, sizeof(guest_hv_clock))))
2575                 return;
2576
2577         /* This VCPU is paused, but it's legal for a guest to read another
2578          * VCPU's kvmclock, so we really have to follow the specification where
2579          * it says that version is odd if data is being modified, and even after
2580          * it is consistent.
2581          *
2582          * Version field updates must be kept separate.  This is because
2583          * kvm_write_guest_cached might use a "rep movs" instruction, and
2584          * writes within a string instruction are weakly ordered.  So there
2585          * are three writes overall.
2586          *
2587          * As a small optimization, only write the version field in the first
2588          * and third write.  The vcpu->pv_time cache is still valid, because the
2589          * version field is the first in the struct.
2590          */
2591         BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2592
2593         if (guest_hv_clock.version & 1)
2594                 ++guest_hv_clock.version;  /* first time write, random junk */
2595
2596         vcpu->hv_clock.version = guest_hv_clock.version + 1;
2597         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2598                                 &vcpu->hv_clock,
2599                                 sizeof(vcpu->hv_clock.version));
2600
2601         smp_wmb();
2602
2603         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2604         vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2605
2606         if (vcpu->pvclock_set_guest_stopped_request) {
2607                 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2608                 vcpu->pvclock_set_guest_stopped_request = false;
2609         }
2610
2611         trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2612
2613         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2614                                 &vcpu->hv_clock,
2615                                 sizeof(vcpu->hv_clock));
2616
2617         smp_wmb();
2618
2619         vcpu->hv_clock.version++;
2620         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2621                                 &vcpu->hv_clock,
2622                                 sizeof(vcpu->hv_clock.version));
2623 }
2624
2625 static int kvm_guest_time_update(struct kvm_vcpu *v)
2626 {
2627         unsigned long flags, tgt_tsc_khz;
2628         struct kvm_vcpu_arch *vcpu = &v->arch;
2629         struct kvm_arch *ka = &v->kvm->arch;
2630         s64 kernel_ns;
2631         u64 tsc_timestamp, host_tsc;
2632         u8 pvclock_flags;
2633         bool use_master_clock;
2634
2635         kernel_ns = 0;
2636         host_tsc = 0;
2637
2638         /*
2639          * If the host uses TSC clock, then passthrough TSC as stable
2640          * to the guest.
2641          */
2642         spin_lock(&ka->pvclock_gtod_sync_lock);
2643         use_master_clock = ka->use_master_clock;
2644         if (use_master_clock) {
2645                 host_tsc = ka->master_cycle_now;
2646                 kernel_ns = ka->master_kernel_ns;
2647         }
2648         spin_unlock(&ka->pvclock_gtod_sync_lock);
2649
2650         /* Keep irq disabled to prevent changes to the clock */
2651         local_irq_save(flags);
2652         tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2653         if (unlikely(tgt_tsc_khz == 0)) {
2654                 local_irq_restore(flags);
2655                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2656                 return 1;
2657         }
2658         if (!use_master_clock) {
2659                 host_tsc = rdtsc();
2660                 kernel_ns = get_kvmclock_base_ns();
2661         }
2662
2663         tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2664
2665         /*
2666          * We may have to catch up the TSC to match elapsed wall clock
2667          * time for two reasons, even if kvmclock is used.
2668          *   1) CPU could have been running below the maximum TSC rate
2669          *   2) Broken TSC compensation resets the base at each VCPU
2670          *      entry to avoid unknown leaps of TSC even when running
2671          *      again on the same CPU.  This may cause apparent elapsed
2672          *      time to disappear, and the guest to stand still or run
2673          *      very slowly.
2674          */
2675         if (vcpu->tsc_catchup) {
2676                 u64 tsc = compute_guest_tsc(v, kernel_ns);
2677                 if (tsc > tsc_timestamp) {
2678                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2679                         tsc_timestamp = tsc;
2680                 }
2681         }
2682
2683         local_irq_restore(flags);
2684
2685         /* With all the info we got, fill in the values */
2686
2687         if (kvm_has_tsc_control)
2688                 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2689
2690         if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2691                 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2692                                    &vcpu->hv_clock.tsc_shift,
2693                                    &vcpu->hv_clock.tsc_to_system_mul);
2694                 vcpu->hw_tsc_khz = tgt_tsc_khz;
2695         }
2696
2697         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2698         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2699         vcpu->last_guest_tsc = tsc_timestamp;
2700
2701         /* If the host uses TSC clocksource, then it is stable */
2702         pvclock_flags = 0;
2703         if (use_master_clock)
2704                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2705
2706         vcpu->hv_clock.flags = pvclock_flags;
2707
2708         if (vcpu->pv_time_enabled)
2709                 kvm_setup_pvclock_page(v);
2710         if (v == kvm_get_vcpu(v->kvm, 0))
2711                 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2712         return 0;
2713 }
2714
2715 /*
2716  * kvmclock updates which are isolated to a given vcpu, such as
2717  * vcpu->cpu migration, should not allow system_timestamp from
2718  * the rest of the vcpus to remain static. Otherwise ntp frequency
2719  * correction applies to one vcpu's system_timestamp but not
2720  * the others.
2721  *
2722  * So in those cases, request a kvmclock update for all vcpus.
2723  * We need to rate-limit these requests though, as they can
2724  * considerably slow guests that have a large number of vcpus.
2725  * The time for a remote vcpu to update its kvmclock is bound
2726  * by the delay we use to rate-limit the updates.
2727  */
2728
2729 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2730
2731 static void kvmclock_update_fn(struct work_struct *work)
2732 {
2733         int i;
2734         struct delayed_work *dwork = to_delayed_work(work);
2735         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2736                                            kvmclock_update_work);
2737         struct kvm *kvm = container_of(ka, struct kvm, arch);
2738         struct kvm_vcpu *vcpu;
2739
2740         kvm_for_each_vcpu(i, vcpu, kvm) {
2741                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2742                 kvm_vcpu_kick(vcpu);
2743         }
2744 }
2745
2746 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2747 {
2748         struct kvm *kvm = v->kvm;
2749
2750         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2751         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2752                                         KVMCLOCK_UPDATE_DELAY);
2753 }
2754
2755 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2756
2757 static void kvmclock_sync_fn(struct work_struct *work)
2758 {
2759         struct delayed_work *dwork = to_delayed_work(work);
2760         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2761                                            kvmclock_sync_work);
2762         struct kvm *kvm = container_of(ka, struct kvm, arch);
2763
2764         if (!kvmclock_periodic_sync)
2765                 return;
2766
2767         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2768         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2769                                         KVMCLOCK_SYNC_PERIOD);
2770 }
2771
2772 /*
2773  * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2774  */
2775 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2776 {
2777         /* McStatusWrEn enabled? */
2778         if (guest_cpuid_is_amd_or_hygon(vcpu))
2779                 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2780
2781         return false;
2782 }
2783
2784 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2785 {
2786         u64 mcg_cap = vcpu->arch.mcg_cap;
2787         unsigned bank_num = mcg_cap & 0xff;
2788         u32 msr = msr_info->index;
2789         u64 data = msr_info->data;
2790
2791         switch (msr) {
2792         case MSR_IA32_MCG_STATUS:
2793                 vcpu->arch.mcg_status = data;
2794                 break;
2795         case MSR_IA32_MCG_CTL:
2796                 if (!(mcg_cap & MCG_CTL_P) &&
2797                     (data || !msr_info->host_initiated))
2798                         return 1;
2799                 if (data != 0 && data != ~(u64)0)
2800                         return 1;
2801                 vcpu->arch.mcg_ctl = data;
2802                 break;
2803         default:
2804                 if (msr >= MSR_IA32_MC0_CTL &&
2805                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2806                         u32 offset = array_index_nospec(
2807                                 msr - MSR_IA32_MC0_CTL,
2808                                 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2809
2810                         /* only 0 or all 1s can be written to IA32_MCi_CTL
2811                          * some Linux kernels though clear bit 10 in bank 4 to
2812                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2813                          * this to avoid an uncatched #GP in the guest
2814                          */
2815                         if ((offset & 0x3) == 0 &&
2816                             data != 0 && (data | (1 << 10)) != ~(u64)0)
2817                                 return -1;
2818
2819                         /* MCi_STATUS */
2820                         if (!msr_info->host_initiated &&
2821                             (offset & 0x3) == 1 && data != 0) {
2822                                 if (!can_set_mci_status(vcpu))
2823                                         return -1;
2824                         }
2825
2826                         vcpu->arch.mce_banks[offset] = data;
2827                         break;
2828                 }
2829                 return 1;
2830         }
2831         return 0;
2832 }
2833
2834 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2835 {
2836         struct kvm *kvm = vcpu->kvm;
2837         int lm = is_long_mode(vcpu);
2838         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2839                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2840         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2841                 : kvm->arch.xen_hvm_config.blob_size_32;
2842         u32 page_num = data & ~PAGE_MASK;
2843         u64 page_addr = data & PAGE_MASK;
2844         u8 *page;
2845         int r;
2846
2847         r = -E2BIG;
2848         if (page_num >= blob_size)
2849                 goto out;
2850         r = -ENOMEM;
2851         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2852         if (IS_ERR(page)) {
2853                 r = PTR_ERR(page);
2854                 goto out;
2855         }
2856         if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2857                 goto out_free;
2858         r = 0;
2859 out_free:
2860         kfree(page);
2861 out:
2862         return r;
2863 }
2864
2865 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
2866 {
2867         u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
2868
2869         return (vcpu->arch.apf.msr_en_val & mask) == mask;
2870 }
2871
2872 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2873 {
2874         gpa_t gpa = data & ~0x3f;
2875
2876         /* Bits 4:5 are reserved, Should be zero */
2877         if (data & 0x30)
2878                 return 1;
2879
2880         if (!lapic_in_kernel(vcpu))
2881                 return data ? 1 : 0;
2882
2883         vcpu->arch.apf.msr_en_val = data;
2884
2885         if (!kvm_pv_async_pf_enabled(vcpu)) {
2886                 kvm_clear_async_pf_completion_queue(vcpu);
2887                 kvm_async_pf_hash_reset(vcpu);
2888                 return 0;
2889         }
2890
2891         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2892                                         sizeof(u64)))
2893                 return 1;
2894
2895         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2896         vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2897
2898         kvm_async_pf_wakeup_all(vcpu);
2899
2900         return 0;
2901 }
2902
2903 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
2904 {
2905         /* Bits 8-63 are reserved */
2906         if (data >> 8)
2907                 return 1;
2908
2909         if (!lapic_in_kernel(vcpu))
2910                 return 1;
2911
2912         vcpu->arch.apf.msr_int_val = data;
2913
2914         vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
2915
2916         return 0;
2917 }
2918
2919 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2920 {
2921         vcpu->arch.pv_time_enabled = false;
2922         vcpu->arch.time = 0;
2923 }
2924
2925 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
2926 {
2927         ++vcpu->stat.tlb_flush;
2928         kvm_x86_ops.tlb_flush_all(vcpu);
2929 }
2930
2931 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
2932 {
2933         ++vcpu->stat.tlb_flush;
2934         kvm_x86_ops.tlb_flush_guest(vcpu);
2935 }
2936
2937 static void record_steal_time(struct kvm_vcpu *vcpu)
2938 {
2939         struct kvm_host_map map;
2940         struct kvm_steal_time *st;
2941
2942         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2943                 return;
2944
2945         /* -EAGAIN is returned in atomic context so we can just return. */
2946         if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2947                         &map, &vcpu->arch.st.cache, false))
2948                 return;
2949
2950         st = map.hva +
2951                 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2952
2953         /*
2954          * Doing a TLB flush here, on the guest's behalf, can avoid
2955          * expensive IPIs.
2956          */
2957         trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2958                 st->preempted & KVM_VCPU_FLUSH_TLB);
2959         if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2960                 kvm_vcpu_flush_tlb_guest(vcpu);
2961
2962         vcpu->arch.st.preempted = 0;
2963
2964         if (st->version & 1)
2965                 st->version += 1;  /* first time write, random junk */
2966
2967         st->version += 1;
2968
2969         smp_wmb();
2970
2971         st->steal += current->sched_info.run_delay -
2972                 vcpu->arch.st.last_steal;
2973         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2974
2975         smp_wmb();
2976
2977         st->version += 1;
2978
2979         kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2980 }
2981
2982 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2983 {
2984         bool pr = false;
2985         u32 msr = msr_info->index;
2986         u64 data = msr_info->data;
2987
2988         switch (msr) {
2989         case MSR_AMD64_NB_CFG:
2990         case MSR_IA32_UCODE_WRITE:
2991         case MSR_VM_HSAVE_PA:
2992         case MSR_AMD64_PATCH_LOADER:
2993         case MSR_AMD64_BU_CFG2:
2994         case MSR_AMD64_DC_CFG:
2995         case MSR_F15H_EX_CFG:
2996                 break;
2997
2998         case MSR_IA32_UCODE_REV:
2999                 if (msr_info->host_initiated)
3000                         vcpu->arch.microcode_version = data;
3001                 break;
3002         case MSR_IA32_ARCH_CAPABILITIES:
3003                 if (!msr_info->host_initiated)
3004                         return 1;
3005                 vcpu->arch.arch_capabilities = data;
3006                 break;
3007         case MSR_IA32_PERF_CAPABILITIES: {
3008                 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
3009
3010                 if (!msr_info->host_initiated)
3011                         return 1;
3012                 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent))
3013                         return 1;
3014                 if (data & ~msr_ent.data)
3015                         return 1;
3016
3017                 vcpu->arch.perf_capabilities = data;
3018
3019                 return 0;
3020                 }
3021         case MSR_EFER:
3022                 return set_efer(vcpu, msr_info);
3023         case MSR_K7_HWCR:
3024                 data &= ~(u64)0x40;     /* ignore flush filter disable */
3025                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
3026                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
3027
3028                 /* Handle McStatusWrEn */
3029                 if (data == BIT_ULL(18)) {
3030                         vcpu->arch.msr_hwcr = data;
3031                 } else if (data != 0) {
3032                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3033                                     data);
3034                         return 1;
3035                 }
3036                 break;
3037         case MSR_FAM10H_MMIO_CONF_BASE:
3038                 if (data != 0) {
3039                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3040                                     "0x%llx\n", data);
3041                         return 1;
3042                 }
3043                 break;
3044         case MSR_IA32_DEBUGCTLMSR:
3045                 if (!data) {
3046                         /* We support the non-activated case already */
3047                         break;
3048                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
3049                         /* Values other than LBR and BTF are vendor-specific,
3050                            thus reserved and should throw a #GP */
3051                         return 1;
3052                 }
3053                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
3054                             __func__, data);
3055                 break;
3056         case 0x200 ... 0x2ff:
3057                 return kvm_mtrr_set_msr(vcpu, msr, data);
3058         case MSR_IA32_APICBASE:
3059                 return kvm_set_apic_base(vcpu, msr_info);
3060         case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3061                 return kvm_x2apic_msr_write(vcpu, msr, data);
3062         case MSR_IA32_TSCDEADLINE:
3063                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3064                 break;
3065         case MSR_IA32_TSC_ADJUST:
3066                 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3067                         if (!msr_info->host_initiated) {
3068                                 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3069                                 adjust_tsc_offset_guest(vcpu, adj);
3070                         }
3071                         vcpu->arch.ia32_tsc_adjust_msr = data;
3072                 }
3073                 break;
3074         case MSR_IA32_MISC_ENABLE:
3075                 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3076                     ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3077                         if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3078                                 return 1;
3079                         vcpu->arch.ia32_misc_enable_msr = data;
3080                         kvm_update_cpuid_runtime(vcpu);
3081                 } else {
3082                         vcpu->arch.ia32_misc_enable_msr = data;
3083                 }
3084                 break;
3085         case MSR_IA32_SMBASE:
3086                 if (!msr_info->host_initiated)
3087                         return 1;
3088                 vcpu->arch.smbase = data;
3089                 break;
3090         case MSR_IA32_POWER_CTL:
3091                 vcpu->arch.msr_ia32_power_ctl = data;
3092                 break;
3093         case MSR_IA32_TSC:
3094                 if (msr_info->host_initiated) {
3095                         kvm_synchronize_tsc(vcpu, data);
3096                 } else {
3097                         u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3098                         adjust_tsc_offset_guest(vcpu, adj);
3099                         vcpu->arch.ia32_tsc_adjust_msr += adj;
3100                 }
3101                 break;
3102         case MSR_IA32_XSS:
3103                 if (!msr_info->host_initiated &&
3104                     !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3105                         return 1;
3106                 /*
3107                  * KVM supports exposing PT to the guest, but does not support
3108                  * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3109                  * XSAVES/XRSTORS to save/restore PT MSRs.
3110                  */
3111                 if (data & ~supported_xss)
3112                         return 1;
3113                 vcpu->arch.ia32_xss = data;
3114                 break;
3115         case MSR_SMI_COUNT:
3116                 if (!msr_info->host_initiated)
3117                         return 1;
3118                 vcpu->arch.smi_count = data;
3119                 break;
3120         case MSR_KVM_WALL_CLOCK_NEW:
3121         case MSR_KVM_WALL_CLOCK:
3122                 kvm_write_wall_clock(vcpu->kvm, data);
3123                 break;
3124         case MSR_KVM_SYSTEM_TIME_NEW:
3125                 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3126                 break;
3127         case MSR_KVM_SYSTEM_TIME:
3128                 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3129                 break;
3130         case MSR_KVM_ASYNC_PF_EN:
3131                 if (kvm_pv_enable_async_pf(vcpu, data))
3132                         return 1;
3133                 break;
3134         case MSR_KVM_ASYNC_PF_INT:
3135                 if (kvm_pv_enable_async_pf_int(vcpu, data))
3136                         return 1;
3137                 break;
3138         case MSR_KVM_ASYNC_PF_ACK:
3139                 if (data & 0x1) {
3140                         vcpu->arch.apf.pageready_pending = false;
3141                         kvm_check_async_pf_completion(vcpu);
3142                 }
3143                 break;
3144         case MSR_KVM_STEAL_TIME:
3145
3146                 if (unlikely(!sched_info_on()))
3147                         return 1;
3148
3149                 if (data & KVM_STEAL_RESERVED_MASK)
3150                         return 1;
3151
3152                 vcpu->arch.st.msr_val = data;
3153
3154                 if (!(data & KVM_MSR_ENABLED))
3155                         break;
3156
3157                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3158
3159                 break;
3160         case MSR_KVM_PV_EOI_EN:
3161                 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
3162                         return 1;
3163                 break;
3164
3165         case MSR_KVM_POLL_CONTROL:
3166                 /* only enable bit supported */
3167                 if (data & (-1ULL << 1))
3168                         return 1;
3169
3170                 vcpu->arch.msr_kvm_poll_control = data;
3171                 break;
3172
3173         case MSR_IA32_MCG_CTL:
3174         case MSR_IA32_MCG_STATUS:
3175         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3176                 return set_msr_mce(vcpu, msr_info);
3177
3178         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3179         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3180                 pr = true;
3181                 fallthrough;
3182         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3183         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3184                 if (kvm_pmu_is_valid_msr(vcpu, msr))
3185                         return kvm_pmu_set_msr(vcpu, msr_info);
3186
3187                 if (pr || data != 0)
3188                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3189                                     "0x%x data 0x%llx\n", msr, data);
3190                 break;
3191         case MSR_K7_CLK_CTL:
3192                 /*
3193                  * Ignore all writes to this no longer documented MSR.
3194                  * Writes are only relevant for old K7 processors,
3195                  * all pre-dating SVM, but a recommended workaround from
3196                  * AMD for these chips. It is possible to specify the
3197                  * affected processor models on the command line, hence
3198                  * the need to ignore the workaround.
3199                  */
3200                 break;
3201         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3202         case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3203         case HV_X64_MSR_SYNDBG_OPTIONS:
3204         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3205         case HV_X64_MSR_CRASH_CTL:
3206         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3207         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3208         case HV_X64_MSR_TSC_EMULATION_CONTROL:
3209         case HV_X64_MSR_TSC_EMULATION_STATUS:
3210                 return kvm_hv_set_msr_common(vcpu, msr, data,
3211                                              msr_info->host_initiated);
3212         case MSR_IA32_BBL_CR_CTL3:
3213                 /* Drop writes to this legacy MSR -- see rdmsr
3214                  * counterpart for further detail.
3215                  */
3216                 if (report_ignored_msrs)
3217                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3218                                 msr, data);
3219                 break;
3220         case MSR_AMD64_OSVW_ID_LENGTH:
3221                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3222                         return 1;
3223                 vcpu->arch.osvw.length = data;
3224                 break;
3225         case MSR_AMD64_OSVW_STATUS:
3226                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3227                         return 1;
3228                 vcpu->arch.osvw.status = data;
3229                 break;
3230         case MSR_PLATFORM_INFO:
3231                 if (!msr_info->host_initiated ||
3232                     (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3233                      cpuid_fault_enabled(vcpu)))
3234                         return 1;
3235                 vcpu->arch.msr_platform_info = data;
3236                 break;
3237         case MSR_MISC_FEATURES_ENABLES:
3238                 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3239                     (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3240                      !supports_cpuid_fault(vcpu)))
3241                         return 1;
3242                 vcpu->arch.msr_misc_features_enables = data;
3243                 break;
3244         default:
3245                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
3246                         return xen_hvm_config(vcpu, data);
3247                 if (kvm_pmu_is_valid_msr(vcpu, msr))
3248                         return kvm_pmu_set_msr(vcpu, msr_info);
3249                 return KVM_MSR_RET_INVALID;
3250         }
3251         return 0;
3252 }
3253 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3254
3255 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3256 {
3257         u64 data;
3258         u64 mcg_cap = vcpu->arch.mcg_cap;
3259         unsigned bank_num = mcg_cap & 0xff;
3260
3261         switch (msr) {
3262         case MSR_IA32_P5_MC_ADDR:
3263         case MSR_IA32_P5_MC_TYPE:
3264                 data = 0;
3265                 break;
3266         case MSR_IA32_MCG_CAP:
3267                 data = vcpu->arch.mcg_cap;
3268                 break;
3269         case MSR_IA32_MCG_CTL:
3270                 if (!(mcg_cap & MCG_CTL_P) && !host)
3271                         return 1;
3272                 data = vcpu->arch.mcg_ctl;
3273                 break;
3274         case MSR_IA32_MCG_STATUS:
3275                 data = vcpu->arch.mcg_status;
3276                 break;
3277         default:
3278                 if (msr >= MSR_IA32_MC0_CTL &&
3279                     msr < MSR_IA32_MCx_CTL(bank_num)) {
3280                         u32 offset = array_index_nospec(
3281                                 msr - MSR_IA32_MC0_CTL,
3282                                 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3283
3284                         data = vcpu->arch.mce_banks[offset];
3285                         break;
3286                 }
3287                 return 1;
3288         }
3289         *pdata = data;
3290         return 0;
3291 }
3292
3293 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3294 {
3295         switch (msr_info->index) {
3296         case MSR_IA32_PLATFORM_ID:
3297         case MSR_IA32_EBL_CR_POWERON:
3298         case MSR_IA32_DEBUGCTLMSR:
3299         case MSR_IA32_LASTBRANCHFROMIP:
3300         case MSR_IA32_LASTBRANCHTOIP:
3301         case MSR_IA32_LASTINTFROMIP:
3302         case MSR_IA32_LASTINTTOIP:
3303         case MSR_K8_SYSCFG:
3304         case MSR_K8_TSEG_ADDR:
3305         case MSR_K8_TSEG_MASK:
3306         case MSR_VM_HSAVE_PA:
3307         case MSR_K8_INT_PENDING_MSG:
3308         case MSR_AMD64_NB_CFG:
3309         case MSR_FAM10H_MMIO_CONF_BASE:
3310         case MSR_AMD64_BU_CFG2:
3311         case MSR_IA32_PERF_CTL:
3312         case MSR_AMD64_DC_CFG:
3313         case MSR_F15H_EX_CFG:
3314         /*
3315          * Intel Sandy Bridge CPUs must support the RAPL (running average power
3316          * limit) MSRs. Just return 0, as we do not want to expose the host
3317          * data here. Do not conditionalize this on CPUID, as KVM does not do
3318          * so for existing CPU-specific MSRs.
3319          */
3320         case MSR_RAPL_POWER_UNIT:
3321         case MSR_PP0_ENERGY_STATUS:     /* Power plane 0 (core) */
3322         case MSR_PP1_ENERGY_STATUS:     /* Power plane 1 (graphics uncore) */
3323         case MSR_PKG_ENERGY_STATUS:     /* Total package */
3324         case MSR_DRAM_ENERGY_STATUS:    /* DRAM controller */
3325                 msr_info->data = 0;
3326                 break;
3327         case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3328         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3329         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3330         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3331         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3332                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3333                         return kvm_pmu_get_msr(vcpu, msr_info);
3334                 msr_info->data = 0;
3335                 break;
3336         case MSR_IA32_UCODE_REV:
3337                 msr_info->data = vcpu->arch.microcode_version;
3338                 break;
3339         case MSR_IA32_ARCH_CAPABILITIES:
3340                 if (!msr_info->host_initiated &&
3341                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3342                         return 1;
3343                 msr_info->data = vcpu->arch.arch_capabilities;
3344                 break;
3345         case MSR_IA32_PERF_CAPABILITIES:
3346                 if (!msr_info->host_initiated &&
3347                     !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3348                         return 1;
3349                 msr_info->data = vcpu->arch.perf_capabilities;
3350                 break;
3351         case MSR_IA32_POWER_CTL:
3352                 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3353                 break;
3354         case MSR_IA32_TSC: {
3355                 /*
3356                  * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
3357                  * even when not intercepted. AMD manual doesn't explicitly
3358                  * state this but appears to behave the same.
3359                  *
3360                  * Unconditionally return L1's TSC offset on userspace reads
3361                  * so that userspace reads and writes always operate on L1's
3362                  * offset, e.g. to ensure deterministic behavior for migration.
3363                  */
3364                 u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset :
3365                                                             vcpu->arch.tsc_offset;
3366
3367                 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset;
3368                 break;
3369         }
3370         case MSR_MTRRcap:
3371         case 0x200 ... 0x2ff:
3372                 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3373         case 0xcd: /* fsb frequency */
3374                 msr_info->data = 3;
3375                 break;
3376                 /*
3377                  * MSR_EBC_FREQUENCY_ID
3378                  * Conservative value valid for even the basic CPU models.
3379                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3380                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3381                  * and 266MHz for model 3, or 4. Set Core Clock
3382                  * Frequency to System Bus Frequency Ratio to 1 (bits
3383                  * 31:24) even though these are only valid for CPU
3384                  * models > 2, however guests may end up dividing or
3385                  * multiplying by zero otherwise.
3386                  */
3387         case MSR_EBC_FREQUENCY_ID:
3388                 msr_info->data = 1 << 24;
3389                 break;
3390         case MSR_IA32_APICBASE:
3391                 msr_info->data = kvm_get_apic_base(vcpu);
3392                 break;
3393         case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3394                 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3395         case MSR_IA32_TSCDEADLINE:
3396                 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3397                 break;
3398         case MSR_IA32_TSC_ADJUST:
3399                 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3400                 break;
3401         case MSR_IA32_MISC_ENABLE:
3402                 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3403                 break;
3404         case MSR_IA32_SMBASE:
3405                 if (!msr_info->host_initiated)
3406                         return 1;
3407                 msr_info->data = vcpu->arch.smbase;
3408                 break;
3409         case MSR_SMI_COUNT:
3410                 msr_info->data = vcpu->arch.smi_count;
3411                 break;
3412         case MSR_IA32_PERF_STATUS:
3413                 /* TSC increment by tick */
3414                 msr_info->data = 1000ULL;
3415                 /* CPU multiplier */
3416                 msr_info->data |= (((uint64_t)4ULL) << 40);
3417                 break;
3418         case MSR_EFER:
3419                 msr_info->data = vcpu->arch.efer;
3420                 break;
3421         case MSR_KVM_WALL_CLOCK:
3422         case MSR_KVM_WALL_CLOCK_NEW:
3423                 msr_info->data = vcpu->kvm->arch.wall_clock;
3424                 break;
3425         case MSR_KVM_SYSTEM_TIME:
3426         case MSR_KVM_SYSTEM_TIME_NEW:
3427                 msr_info->data = vcpu->arch.time;
3428                 break;
3429         case MSR_KVM_ASYNC_PF_EN:
3430                 msr_info->data = vcpu->arch.apf.msr_en_val;
3431                 break;
3432         case MSR_KVM_ASYNC_PF_INT:
3433                 msr_info->data = vcpu->arch.apf.msr_int_val;
3434                 break;
3435         case MSR_KVM_ASYNC_PF_ACK:
3436                 msr_info->data = 0;
3437                 break;
3438         case MSR_KVM_STEAL_TIME:
3439                 msr_info->data = vcpu->arch.st.msr_val;
3440                 break;
3441         case MSR_KVM_PV_EOI_EN:
3442                 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3443                 break;
3444         case MSR_KVM_POLL_CONTROL:
3445                 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3446                 break;
3447         case MSR_IA32_P5_MC_ADDR:
3448         case MSR_IA32_P5_MC_TYPE:
3449         case MSR_IA32_MCG_CAP:
3450         case MSR_IA32_MCG_CTL:
3451         case MSR_IA32_MCG_STATUS:
3452         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3453                 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3454                                    msr_info->host_initiated);
3455         case MSR_IA32_XSS:
3456                 if (!msr_info->host_initiated &&
3457                     !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3458                         return 1;
3459                 msr_info->data = vcpu->arch.ia32_xss;
3460                 break;
3461         case MSR_K7_CLK_CTL:
3462                 /*
3463                  * Provide expected ramp-up count for K7. All other
3464                  * are set to zero, indicating minimum divisors for
3465                  * every field.
3466                  *
3467                  * This prevents guest kernels on AMD host with CPU
3468                  * type 6, model 8 and higher from exploding due to
3469                  * the rdmsr failing.
3470                  */
3471                 msr_info->data = 0x20000000;
3472                 break;
3473         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3474         case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3475         case HV_X64_MSR_SYNDBG_OPTIONS:
3476         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3477         case HV_X64_MSR_CRASH_CTL:
3478         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3479         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3480         case HV_X64_MSR_TSC_EMULATION_CONTROL:
3481         case HV_X64_MSR_TSC_EMULATION_STATUS:
3482                 return kvm_hv_get_msr_common(vcpu,
3483                                              msr_info->index, &msr_info->data,
3484                                              msr_info->host_initiated);
3485         case MSR_IA32_BBL_CR_CTL3:
3486                 /* This legacy MSR exists but isn't fully documented in current
3487                  * silicon.  It is however accessed by winxp in very narrow
3488                  * scenarios where it sets bit #19, itself documented as
3489                  * a "reserved" bit.  Best effort attempt to source coherent
3490                  * read data here should the balance of the register be
3491                  * interpreted by the guest:
3492                  *
3493                  * L2 cache control register 3: 64GB range, 256KB size,
3494                  * enabled, latency 0x1, configured
3495                  */
3496                 msr_info->data = 0xbe702111;
3497                 break;
3498         case MSR_AMD64_OSVW_ID_LENGTH:
3499                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3500                         return 1;
3501                 msr_info->data = vcpu->arch.osvw.length;
3502                 break;
3503         case MSR_AMD64_OSVW_STATUS:
3504                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3505                         return 1;
3506                 msr_info->data = vcpu->arch.osvw.status;
3507                 break;
3508         case MSR_PLATFORM_INFO:
3509                 if (!msr_info->host_initiated &&
3510                     !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3511                         return 1;
3512                 msr_info->data = vcpu->arch.msr_platform_info;
3513                 break;
3514         case MSR_MISC_FEATURES_ENABLES:
3515                 msr_info->data = vcpu->arch.msr_misc_features_enables;
3516                 break;
3517         case MSR_K7_HWCR:
3518                 msr_info->data = vcpu->arch.msr_hwcr;
3519                 break;
3520         default:
3521                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3522                         return kvm_pmu_get_msr(vcpu, msr_info);
3523                 return KVM_MSR_RET_INVALID;
3524         }
3525         return 0;
3526 }
3527 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3528
3529 /*
3530  * Read or write a bunch of msrs. All parameters are kernel addresses.
3531  *
3532  * @return number of msrs set successfully.
3533  */
3534 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3535                     struct kvm_msr_entry *entries,
3536                     int (*do_msr)(struct kvm_vcpu *vcpu,
3537                                   unsigned index, u64 *data))
3538 {
3539         int i;
3540
3541         for (i = 0; i < msrs->nmsrs; ++i)
3542                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3543                         break;
3544
3545         return i;
3546 }
3547
3548 /*
3549  * Read or write a bunch of msrs. Parameters are user addresses.
3550  *
3551  * @return number of msrs set successfully.
3552  */
3553 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3554                   int (*do_msr)(struct kvm_vcpu *vcpu,
3555                                 unsigned index, u64 *data),
3556                   int writeback)
3557 {
3558         struct kvm_msrs msrs;
3559         struct kvm_msr_entry *entries;
3560         int r, n;
3561         unsigned size;
3562
3563         r = -EFAULT;
3564         if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3565                 goto out;
3566
3567         r = -E2BIG;
3568         if (msrs.nmsrs >= MAX_IO_MSRS)
3569                 goto out;
3570
3571         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3572         entries = memdup_user(user_msrs->entries, size);
3573         if (IS_ERR(entries)) {
3574                 r = PTR_ERR(entries);
3575                 goto out;
3576         }
3577
3578         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3579         if (r < 0)
3580                 goto out_free;
3581
3582         r = -EFAULT;
3583         if (writeback && copy_to_user(user_msrs->entries, entries, size))
3584                 goto out_free;
3585
3586         r = n;
3587
3588 out_free:
3589         kfree(entries);
3590 out:
3591         return r;
3592 }
3593
3594 static inline bool kvm_can_mwait_in_guest(void)
3595 {
3596         return boot_cpu_has(X86_FEATURE_MWAIT) &&
3597                 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3598                 boot_cpu_has(X86_FEATURE_ARAT);
3599 }
3600
3601 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3602 {
3603         int r = 0;
3604
3605         switch (ext) {
3606         case KVM_CAP_IRQCHIP:
3607         case KVM_CAP_HLT:
3608         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3609         case KVM_CAP_SET_TSS_ADDR:
3610         case KVM_CAP_EXT_CPUID:
3611         case KVM_CAP_EXT_EMUL_CPUID:
3612         case KVM_CAP_CLOCKSOURCE:
3613         case KVM_CAP_PIT:
3614         case KVM_CAP_NOP_IO_DELAY:
3615         case KVM_CAP_MP_STATE:
3616         case KVM_CAP_SYNC_MMU:
3617         case KVM_CAP_USER_NMI:
3618         case KVM_CAP_REINJECT_CONTROL:
3619         case KVM_CAP_IRQ_INJECT_STATUS:
3620         case KVM_CAP_IOEVENTFD:
3621         case KVM_CAP_IOEVENTFD_NO_LENGTH:
3622         case KVM_CAP_PIT2:
3623         case KVM_CAP_PIT_STATE2:
3624         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3625         case KVM_CAP_XEN_HVM:
3626         case KVM_CAP_VCPU_EVENTS:
3627         case KVM_CAP_HYPERV:
3628         case KVM_CAP_HYPERV_VAPIC:
3629         case KVM_CAP_HYPERV_SPIN:
3630         case KVM_CAP_HYPERV_SYNIC:
3631         case KVM_CAP_HYPERV_SYNIC2:
3632         case KVM_CAP_HYPERV_VP_INDEX:
3633         case KVM_CAP_HYPERV_EVENTFD:
3634         case KVM_CAP_HYPERV_TLBFLUSH:
3635         case KVM_CAP_HYPERV_SEND_IPI:
3636         case KVM_CAP_HYPERV_CPUID:
3637         case KVM_CAP_PCI_SEGMENT:
3638         case KVM_CAP_DEBUGREGS:
3639         case KVM_CAP_X86_ROBUST_SINGLESTEP:
3640         case KVM_CAP_XSAVE:
3641         case KVM_CAP_ASYNC_PF:
3642         case KVM_CAP_ASYNC_PF_INT:
3643         case KVM_CAP_GET_TSC_KHZ:
3644         case KVM_CAP_KVMCLOCK_CTRL:
3645         case KVM_CAP_READONLY_MEM:
3646         case KVM_CAP_HYPERV_TIME:
3647         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3648         case KVM_CAP_TSC_DEADLINE_TIMER:
3649         case KVM_CAP_DISABLE_QUIRKS:
3650         case KVM_CAP_SET_BOOT_CPU_ID:
3651         case KVM_CAP_SPLIT_IRQCHIP:
3652         case KVM_CAP_IMMEDIATE_EXIT:
3653         case KVM_CAP_PMU_EVENT_FILTER:
3654         case KVM_CAP_GET_MSR_FEATURES:
3655         case KVM_CAP_MSR_PLATFORM_INFO:
3656         case KVM_CAP_EXCEPTION_PAYLOAD:
3657         case KVM_CAP_SET_GUEST_DEBUG:
3658         case KVM_CAP_LAST_CPU:
3659         case KVM_CAP_X86_USER_SPACE_MSR:
3660         case KVM_CAP_X86_MSR_FILTER:
3661                 r = 1;
3662                 break;
3663         case KVM_CAP_SYNC_REGS:
3664                 r = KVM_SYNC_X86_VALID_FIELDS;
3665                 break;
3666         case KVM_CAP_ADJUST_CLOCK:
3667                 r = KVM_CLOCK_TSC_STABLE;
3668                 break;
3669         case KVM_CAP_X86_DISABLE_EXITS:
3670                 r |=  KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3671                       KVM_X86_DISABLE_EXITS_CSTATE;
3672                 if(kvm_can_mwait_in_guest())
3673                         r |= KVM_X86_DISABLE_EXITS_MWAIT;
3674                 break;
3675         case KVM_CAP_X86_SMM:
3676                 /* SMBASE is usually relocated above 1M on modern chipsets,
3677                  * and SMM handlers might indeed rely on 4G segment limits,
3678                  * so do not report SMM to be available if real mode is
3679                  * emulated via vm86 mode.  Still, do not go to great lengths
3680                  * to avoid userspace's usage of the feature, because it is a
3681                  * fringe case that is not enabled except via specific settings
3682                  * of the module parameters.
3683                  */
3684                 r = kvm_x86_ops.has_emulated_msr(MSR_IA32_SMBASE);
3685                 break;
3686         case KVM_CAP_VAPIC:
3687                 r = !kvm_x86_ops.cpu_has_accelerated_tpr();
3688                 break;
3689         case KVM_CAP_NR_VCPUS:
3690                 r = KVM_SOFT_MAX_VCPUS;
3691                 break;
3692         case KVM_CAP_MAX_VCPUS:
3693                 r = KVM_MAX_VCPUS;
3694                 break;
3695         case KVM_CAP_MAX_VCPU_ID:
3696                 r = KVM_MAX_VCPU_ID;
3697                 break;
3698         case KVM_CAP_PV_MMU:    /* obsolete */
3699                 r = 0;
3700                 break;
3701         case KVM_CAP_MCE:
3702                 r = KVM_MAX_MCE_BANKS;
3703                 break;
3704         case KVM_CAP_XCRS:
3705                 r = boot_cpu_has(X86_FEATURE_XSAVE);
3706                 break;
3707         case KVM_CAP_TSC_CONTROL:
3708                 r = kvm_has_tsc_control;
3709                 break;
3710         case KVM_CAP_X2APIC_API:
3711                 r = KVM_X2APIC_API_VALID_FLAGS;
3712                 break;
3713         case KVM_CAP_NESTED_STATE:
3714                 r = kvm_x86_ops.nested_ops->get_state ?
3715                         kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
3716                 break;
3717         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3718                 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3719                 break;
3720         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3721                 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
3722                 break;
3723         case KVM_CAP_SMALLER_MAXPHYADDR:
3724                 r = (int) allow_smaller_maxphyaddr;
3725                 break;
3726         case KVM_CAP_STEAL_TIME:
3727                 r = sched_info_on();
3728                 break;
3729         default:
3730                 break;
3731         }
3732         return r;
3733
3734 }
3735
3736 long kvm_arch_dev_ioctl(struct file *filp,
3737                         unsigned int ioctl, unsigned long arg)
3738 {
3739         void __user *argp = (void __user *)arg;
3740         long r;
3741
3742         switch (ioctl) {
3743         case KVM_GET_MSR_INDEX_LIST: {
3744                 struct kvm_msr_list __user *user_msr_list = argp;
3745                 struct kvm_msr_list msr_list;
3746                 unsigned n;
3747
3748                 r = -EFAULT;
3749                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3750                         goto out;
3751                 n = msr_list.nmsrs;
3752                 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3753                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3754                         goto out;
3755                 r = -E2BIG;
3756                 if (n < msr_list.nmsrs)
3757                         goto out;
3758                 r = -EFAULT;
3759                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3760                                  num_msrs_to_save * sizeof(u32)))
3761                         goto out;
3762                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3763                                  &emulated_msrs,
3764                                  num_emulated_msrs * sizeof(u32)))
3765                         goto out;
3766                 r = 0;
3767                 break;
3768         }
3769         case KVM_GET_SUPPORTED_CPUID:
3770         case KVM_GET_EMULATED_CPUID: {
3771                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3772                 struct kvm_cpuid2 cpuid;
3773
3774                 r = -EFAULT;
3775                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3776                         goto out;
3777
3778                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3779                                             ioctl);
3780                 if (r)
3781                         goto out;
3782
3783                 r = -EFAULT;
3784                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3785                         goto out;
3786                 r = 0;
3787                 break;
3788         }
3789         case KVM_X86_GET_MCE_CAP_SUPPORTED:
3790                 r = -EFAULT;
3791                 if (copy_to_user(argp, &kvm_mce_cap_supported,
3792                                  sizeof(kvm_mce_cap_supported)))
3793                         goto out;
3794                 r = 0;
3795                 break;
3796         case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3797                 struct kvm_msr_list __user *user_msr_list = argp;
3798                 struct kvm_msr_list msr_list;
3799                 unsigned int n;
3800
3801                 r = -EFAULT;
3802                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3803                         goto out;
3804                 n = msr_list.nmsrs;
3805                 msr_list.nmsrs = num_msr_based_features;
3806                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3807                         goto out;
3808                 r = -E2BIG;
3809                 if (n < msr_list.nmsrs)
3810                         goto out;
3811                 r = -EFAULT;
3812                 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3813                                  num_msr_based_features * sizeof(u32)))
3814                         goto out;
3815                 r = 0;
3816                 break;
3817         }
3818         case KVM_GET_MSRS:
3819                 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3820                 break;
3821         default:
3822                 r = -EINVAL;
3823                 break;
3824         }
3825 out:
3826         return r;
3827 }
3828
3829 static void wbinvd_ipi(void *garbage)
3830 {
3831         wbinvd();
3832 }
3833
3834 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3835 {
3836         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3837 }
3838
3839 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3840 {
3841         /* Address WBINVD may be executed by guest */
3842         if (need_emulate_wbinvd(vcpu)) {
3843                 if (kvm_x86_ops.has_wbinvd_exit())
3844                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3845                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3846                         smp_call_function_single(vcpu->cpu,
3847                                         wbinvd_ipi, NULL, 1);
3848         }
3849
3850         kvm_x86_ops.vcpu_load(vcpu, cpu);
3851
3852         /* Save host pkru register if supported */
3853         vcpu->arch.host_pkru = read_pkru();
3854
3855         /* Apply any externally detected TSC adjustments (due to suspend) */
3856         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3857                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3858                 vcpu->arch.tsc_offset_adjustment = 0;
3859                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3860         }
3861
3862         if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3863                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3864                                 rdtsc() - vcpu->arch.last_host_tsc;
3865                 if (tsc_delta < 0)
3866                         mark_tsc_unstable("KVM discovered backwards TSC");
3867
3868                 if (kvm_check_tsc_unstable()) {
3869                         u64 offset = kvm_compute_tsc_offset(vcpu,
3870                                                 vcpu->arch.last_guest_tsc);
3871                         kvm_vcpu_write_tsc_offset(vcpu, offset);
3872                         vcpu->arch.tsc_catchup = 1;
3873                 }
3874
3875                 if (kvm_lapic_hv_timer_in_use(vcpu))
3876                         kvm_lapic_restart_hv_timer(vcpu);
3877
3878                 /*
3879                  * On a host with synchronized TSC, there is no need to update
3880                  * kvmclock on vcpu->cpu migration
3881                  */
3882                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3883                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3884                 if (vcpu->cpu != cpu)
3885                         kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3886                 vcpu->cpu = cpu;
3887         }
3888
3889         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3890 }
3891
3892 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3893 {
3894         struct kvm_host_map map;
3895         struct kvm_steal_time *st;
3896
3897         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3898                 return;
3899
3900         if (vcpu->arch.st.preempted)
3901                 return;
3902
3903         if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3904                         &vcpu->arch.st.cache, true))
3905                 return;
3906
3907         st = map.hva +
3908                 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
3909
3910         st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
3911
3912         kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
3913 }
3914
3915 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3916 {
3917         int idx;
3918
3919         if (vcpu->preempted)
3920                 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu);
3921
3922         /*
3923          * Disable page faults because we're in atomic context here.
3924          * kvm_write_guest_offset_cached() would call might_fault()
3925          * that relies on pagefault_disable() to tell if there's a
3926          * bug. NOTE: the write to guest memory may not go through if
3927          * during postcopy live migration or if there's heavy guest
3928          * paging.
3929          */
3930         pagefault_disable();
3931         /*
3932          * kvm_memslots() will be called by
3933          * kvm_write_guest_offset_cached() so take the srcu lock.
3934          */
3935         idx = srcu_read_lock(&vcpu->kvm->srcu);
3936         kvm_steal_time_set_preempted(vcpu);
3937         srcu_read_unlock(&vcpu->kvm->srcu, idx);
3938         pagefault_enable();
3939         kvm_x86_ops.vcpu_put(vcpu);
3940         vcpu->arch.last_host_tsc = rdtsc();
3941         /*
3942          * If userspace has set any breakpoints or watchpoints, dr6 is restored
3943          * on every vmexit, but if not, we might have a stale dr6 from the
3944          * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3945          */
3946         set_debugreg(0, 6);
3947 }
3948
3949 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3950                                     struct kvm_lapic_state *s)
3951 {
3952         if (vcpu->arch.apicv_active)
3953                 kvm_x86_ops.sync_pir_to_irr(vcpu);
3954
3955         return kvm_apic_get_state(vcpu, s);
3956 }
3957
3958 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3959                                     struct kvm_lapic_state *s)
3960 {
3961         int r;
3962
3963         r = kvm_apic_set_state(vcpu, s);
3964         if (r)
3965                 return r;
3966         update_cr8_intercept(vcpu);
3967
3968         return 0;
3969 }
3970
3971 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3972 {
3973         return (!lapic_in_kernel(vcpu) ||
3974                 kvm_apic_accept_pic_intr(vcpu));
3975 }
3976
3977 /*
3978  * if userspace requested an interrupt window, check that the
3979  * interrupt window is open.
3980  *
3981  * No need to exit to userspace if we already have an interrupt queued.
3982  */
3983 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3984 {
3985         return kvm_arch_interrupt_allowed(vcpu) &&
3986                 !kvm_cpu_has_interrupt(vcpu) &&
3987                 !kvm_event_needs_reinjection(vcpu) &&
3988                 kvm_cpu_accept_dm_intr(vcpu);
3989 }
3990
3991 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3992                                     struct kvm_interrupt *irq)
3993 {
3994         if (irq->irq >= KVM_NR_INTERRUPTS)
3995                 return -EINVAL;
3996
3997         if (!irqchip_in_kernel(vcpu->kvm)) {
3998                 kvm_queue_interrupt(vcpu, irq->irq, false);
3999                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4000                 return 0;
4001         }
4002
4003         /*
4004          * With in-kernel LAPIC, we only use this to inject EXTINT, so
4005          * fail for in-kernel 8259.
4006          */
4007         if (pic_in_kernel(vcpu->kvm))
4008                 return -ENXIO;
4009
4010         if (vcpu->arch.pending_external_vector != -1)
4011                 return -EEXIST;
4012
4013         vcpu->arch.pending_external_vector = irq->irq;
4014         kvm_make_request(KVM_REQ_EVENT, vcpu);
4015         return 0;
4016 }
4017
4018 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4019 {
4020         kvm_inject_nmi(vcpu);
4021
4022         return 0;
4023 }
4024
4025 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
4026 {
4027         kvm_make_request(KVM_REQ_SMI, vcpu);
4028
4029         return 0;
4030 }
4031
4032 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4033                                            struct kvm_tpr_access_ctl *tac)
4034 {
4035         if (tac->flags)
4036                 return -EINVAL;
4037         vcpu->arch.tpr_access_reporting = !!tac->enabled;
4038         return 0;
4039 }
4040
4041 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4042                                         u64 mcg_cap)
4043 {
4044         int r;
4045         unsigned bank_num = mcg_cap & 0xff, bank;
4046
4047         r = -EINVAL;
4048         if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4049                 goto out;
4050         if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
4051                 goto out;
4052         r = 0;
4053         vcpu->arch.mcg_cap = mcg_cap;
4054         /* Init IA32_MCG_CTL to all 1s */
4055         if (mcg_cap & MCG_CTL_P)
4056                 vcpu->arch.mcg_ctl = ~(u64)0;
4057         /* Init IA32_MCi_CTL to all 1s */
4058         for (bank = 0; bank < bank_num; bank++)
4059                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4060
4061         kvm_x86_ops.setup_mce(vcpu);
4062 out:
4063         return r;
4064 }
4065
4066 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4067                                       struct kvm_x86_mce *mce)
4068 {
4069         u64 mcg_cap = vcpu->arch.mcg_cap;
4070         unsigned bank_num = mcg_cap & 0xff;
4071         u64 *banks = vcpu->arch.mce_banks;
4072
4073         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
4074                 return -EINVAL;
4075         /*
4076          * if IA32_MCG_CTL is not all 1s, the uncorrected error
4077          * reporting is disabled
4078          */
4079         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
4080             vcpu->arch.mcg_ctl != ~(u64)0)
4081                 return 0;
4082         banks += 4 * mce->bank;
4083         /*
4084          * if IA32_MCi_CTL is not all 1s, the uncorrected error
4085          * reporting is disabled for the bank
4086          */
4087         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
4088                 return 0;
4089         if (mce->status & MCI_STATUS_UC) {
4090                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
4091                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
4092                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4093                         return 0;
4094                 }
4095                 if (banks[1] & MCI_STATUS_VAL)
4096                         mce->status |= MCI_STATUS_OVER;
4097                 banks[2] = mce->addr;
4098                 banks[3] = mce->misc;
4099                 vcpu->arch.mcg_status = mce->mcg_status;
4100                 banks[1] = mce->status;
4101                 kvm_queue_exception(vcpu, MC_VECTOR);
4102         } else if (!(banks[1] & MCI_STATUS_VAL)
4103                    || !(banks[1] & MCI_STATUS_UC)) {
4104                 if (banks[1] & MCI_STATUS_VAL)
4105                         mce->status |= MCI_STATUS_OVER;
4106                 banks[2] = mce->addr;
4107                 banks[3] = mce->misc;
4108                 banks[1] = mce->status;
4109         } else
4110                 banks[1] |= MCI_STATUS_OVER;
4111         return 0;
4112 }
4113
4114 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
4115                                                struct kvm_vcpu_events *events)
4116 {
4117         process_nmi(vcpu);
4118
4119         /*
4120          * In guest mode, payload delivery should be deferred,
4121          * so that the L1 hypervisor can intercept #PF before
4122          * CR2 is modified (or intercept #DB before DR6 is
4123          * modified under nVMX). Unless the per-VM capability,
4124          * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
4125          * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
4126          * opportunistically defer the exception payload, deliver it if the
4127          * capability hasn't been requested before processing a
4128          * KVM_GET_VCPU_EVENTS.
4129          */
4130         if (!vcpu->kvm->arch.exception_payload_enabled &&
4131             vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
4132                 kvm_deliver_exception_payload(vcpu);
4133
4134         /*
4135          * The API doesn't provide the instruction length for software
4136          * exceptions, so don't report them. As long as the guest RIP
4137          * isn't advanced, we should expect to encounter the exception
4138          * again.
4139          */
4140         if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
4141                 events->exception.injected = 0;
4142                 events->exception.pending = 0;
4143         } else {
4144                 events->exception.injected = vcpu->arch.exception.injected;
4145                 events->exception.pending = vcpu->arch.exception.pending;
4146                 /*
4147                  * For ABI compatibility, deliberately conflate
4148                  * pending and injected exceptions when
4149                  * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
4150                  */
4151                 if (!vcpu->kvm->arch.exception_payload_enabled)
4152                         events->exception.injected |=
4153                                 vcpu->arch.exception.pending;
4154         }
4155         events->exception.nr = vcpu->arch.exception.nr;
4156         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
4157         events->exception.error_code = vcpu->arch.exception.error_code;
4158         events->exception_has_payload = vcpu->arch.exception.has_payload;
4159         events->exception_payload = vcpu->arch.exception.payload;
4160
4161         events->interrupt.injected =
4162                 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
4163         events->interrupt.nr = vcpu->arch.interrupt.nr;
4164         events->interrupt.soft = 0;
4165         events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
4166
4167         events->nmi.injected = vcpu->arch.nmi_injected;
4168         events->nmi.pending = vcpu->arch.nmi_pending != 0;
4169         events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu);
4170         events->nmi.pad = 0;
4171
4172         events->sipi_vector = 0; /* never valid when reporting to user space */
4173
4174         events->smi.smm = is_smm(vcpu);
4175         events->smi.pending = vcpu->arch.smi_pending;
4176         events->smi.smm_inside_nmi =
4177                 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
4178         events->smi.latched_init = kvm_lapic_latched_init(vcpu);
4179
4180         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
4181                          | KVM_VCPUEVENT_VALID_SHADOW
4182                          | KVM_VCPUEVENT_VALID_SMM);
4183         if (vcpu->kvm->arch.exception_payload_enabled)
4184                 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4185
4186         memset(&events->reserved, 0, sizeof(events->reserved));
4187 }
4188
4189 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
4190
4191 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4192                                               struct kvm_vcpu_events *events)
4193 {
4194         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4195                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4196                               | KVM_VCPUEVENT_VALID_SHADOW
4197                               | KVM_VCPUEVENT_VALID_SMM
4198                               | KVM_VCPUEVENT_VALID_PAYLOAD))
4199                 return -EINVAL;
4200
4201         if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4202                 if (!vcpu->kvm->arch.exception_payload_enabled)
4203                         return -EINVAL;
4204                 if (events->exception.pending)
4205                         events->exception.injected = 0;
4206                 else
4207                         events->exception_has_payload = 0;
4208         } else {
4209                 events->exception.pending = 0;
4210                 events->exception_has_payload = 0;
4211         }
4212
4213         if ((events->exception.injected || events->exception.pending) &&
4214             (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4215                 return -EINVAL;
4216
4217         /* INITs are latched while in SMM */
4218         if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4219             (events->smi.smm || events->smi.pending) &&
4220             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4221                 return -EINVAL;
4222
4223         process_nmi(vcpu);
4224         vcpu->arch.exception.injected = events->exception.injected;
4225         vcpu->arch.exception.pending = events->exception.pending;
4226         vcpu->arch.exception.nr = events->exception.nr;
4227         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4228         vcpu->arch.exception.error_code = events->exception.error_code;
4229         vcpu->arch.exception.has_payload = events->exception_has_payload;
4230         vcpu->arch.exception.payload = events->exception_payload;
4231
4232         vcpu->arch.interrupt.injected = events->interrupt.injected;
4233         vcpu->arch.interrupt.nr = events->interrupt.nr;
4234         vcpu->arch.interrupt.soft = events->interrupt.soft;
4235         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4236                 kvm_x86_ops.set_interrupt_shadow(vcpu,
4237                                                   events->interrupt.shadow);
4238
4239         vcpu->arch.nmi_injected = events->nmi.injected;
4240         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4241                 vcpu->arch.nmi_pending = events->nmi.pending;
4242         kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked);
4243
4244         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4245             lapic_in_kernel(vcpu))
4246                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4247
4248         if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4249                 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4250                         if (events->smi.smm)
4251                                 vcpu->arch.hflags |= HF_SMM_MASK;
4252                         else
4253                                 vcpu->arch.hflags &= ~HF_SMM_MASK;
4254                         kvm_smm_changed(vcpu);
4255                 }
4256
4257                 vcpu->arch.smi_pending = events->smi.pending;
4258
4259                 if (events->smi.smm) {
4260                         if (events->smi.smm_inside_nmi)
4261                                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4262                         else
4263                                 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4264                 }
4265
4266                 if (lapic_in_kernel(vcpu)) {
4267                         if (events->smi.latched_init)
4268                                 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4269                         else
4270                                 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4271                 }
4272         }
4273
4274         kvm_make_request(KVM_REQ_EVENT, vcpu);
4275
4276         return 0;
4277 }
4278
4279 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4280                                              struct kvm_debugregs *dbgregs)
4281 {
4282         unsigned long val;
4283
4284         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4285         kvm_get_dr(vcpu, 6, &val);
4286         dbgregs->dr6 = val;
4287         dbgregs->dr7 = vcpu->arch.dr7;
4288         dbgregs->flags = 0;
4289         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4290 }
4291
4292 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4293                                             struct kvm_debugregs *dbgregs)
4294 {
4295         if (dbgregs->flags)
4296                 return -EINVAL;
4297
4298         if (dbgregs->dr6 & ~0xffffffffull)
4299                 return -EINVAL;
4300         if (dbgregs->dr7 & ~0xffffffffull)
4301                 return -EINVAL;
4302
4303         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4304         kvm_update_dr0123(vcpu);
4305         vcpu->arch.dr6 = dbgregs->dr6;
4306         vcpu->arch.dr7 = dbgregs->dr7;
4307         kvm_update_dr7(vcpu);
4308
4309         return 0;
4310 }
4311
4312 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4313
4314 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4315 {
4316         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4317         u64 xstate_bv = xsave->header.xfeatures;
4318         u64 valid;
4319
4320         /*
4321          * Copy legacy XSAVE area, to avoid complications with CPUID
4322          * leaves 0 and 1 in the loop below.
4323          */
4324         memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4325
4326         /* Set XSTATE_BV */
4327         xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4328         *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4329
4330         /*
4331          * Copy each region from the possibly compacted offset to the
4332          * non-compacted offset.
4333          */
4334         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4335         while (valid) {
4336                 u64 xfeature_mask = valid & -valid;
4337                 int xfeature_nr = fls64(xfeature_mask) - 1;
4338                 void *src = get_xsave_addr(xsave, xfeature_nr);
4339
4340                 if (src) {
4341                         u32 size, offset, ecx, edx;
4342                         cpuid_count(XSTATE_CPUID, xfeature_nr,
4343                                     &size, &offset, &ecx, &edx);
4344                         if (xfeature_nr == XFEATURE_PKRU)
4345                                 memcpy(dest + offset, &vcpu->arch.pkru,
4346                                        sizeof(vcpu->arch.pkru));
4347                         else
4348                                 memcpy(dest + offset, src, size);
4349
4350                 }
4351
4352                 valid -= xfeature_mask;
4353         }
4354 }
4355
4356 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4357 {
4358         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4359         u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4360         u64 valid;
4361
4362         /*
4363          * Copy legacy XSAVE area, to avoid complications with CPUID
4364          * leaves 0 and 1 in the loop below.
4365          */
4366         memcpy(xsave, src, XSAVE_HDR_OFFSET);
4367
4368         /* Set XSTATE_BV and possibly XCOMP_BV.  */
4369         xsave->header.xfeatures = xstate_bv;
4370         if (boot_cpu_has(X86_FEATURE_XSAVES))
4371                 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4372
4373         /*
4374          * Copy each region from the non-compacted offset to the
4375          * possibly compacted offset.
4376          */
4377         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4378         while (valid) {
4379                 u64 xfeature_mask = valid & -valid;
4380                 int xfeature_nr = fls64(xfeature_mask) - 1;
4381                 void *dest = get_xsave_addr(xsave, xfeature_nr);
4382
4383                 if (dest) {
4384                         u32 size, offset, ecx, edx;
4385                         cpuid_count(XSTATE_CPUID, xfeature_nr,
4386                                     &size, &offset, &ecx, &edx);
4387                         if (xfeature_nr == XFEATURE_PKRU)
4388                                 memcpy(&vcpu->arch.pkru, src + offset,
4389                                        sizeof(vcpu->arch.pkru));
4390                         else
4391                                 memcpy(dest, src + offset, size);
4392                 }
4393
4394                 valid -= xfeature_mask;
4395         }
4396 }
4397
4398 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4399                                          struct kvm_xsave *guest_xsave)
4400 {
4401         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4402                 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4403                 fill_xsave((u8 *) guest_xsave->region, vcpu);
4404         } else {
4405                 memcpy(guest_xsave->region,
4406                         &vcpu->arch.guest_fpu->state.fxsave,
4407                         sizeof(struct fxregs_state));
4408                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4409                         XFEATURE_MASK_FPSSE;
4410         }
4411 }
4412
4413 #define XSAVE_MXCSR_OFFSET 24
4414
4415 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4416                                         struct kvm_xsave *guest_xsave)
4417 {
4418         u64 xstate_bv =
4419                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4420         u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4421
4422         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4423                 /*
4424                  * Here we allow setting states that are not present in
4425                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
4426                  * with old userspace.
4427                  */
4428                 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4429                         return -EINVAL;
4430                 load_xsave(vcpu, (u8 *)guest_xsave->region);
4431         } else {
4432                 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4433                         mxcsr & ~mxcsr_feature_mask)
4434                         return -EINVAL;
4435                 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4436                         guest_xsave->region, sizeof(struct fxregs_state));
4437         }
4438         return 0;
4439 }
4440
4441 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4442                                         struct kvm_xcrs *guest_xcrs)
4443 {
4444         if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4445                 guest_xcrs->nr_xcrs = 0;
4446                 return;
4447         }
4448
4449         guest_xcrs->nr_xcrs = 1;
4450         guest_xcrs->flags = 0;
4451         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4452         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4453 }
4454
4455 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4456                                        struct kvm_xcrs *guest_xcrs)
4457 {
4458         int i, r = 0;
4459
4460         if (!boot_cpu_has(X86_FEATURE_XSAVE))
4461                 return -EINVAL;
4462
4463         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4464                 return -EINVAL;
4465
4466         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4467                 /* Only support XCR0 currently */
4468                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4469                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4470                                 guest_xcrs->xcrs[i].value);
4471                         break;
4472                 }
4473         if (r)
4474                 r = -EINVAL;
4475         return r;
4476 }
4477
4478 /*
4479  * kvm_set_guest_paused() indicates to the guest kernel that it has been
4480  * stopped by the hypervisor.  This function will be called from the host only.
4481  * EINVAL is returned when the host attempts to set the flag for a guest that
4482  * does not support pv clocks.
4483  */
4484 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4485 {
4486         if (!vcpu->arch.pv_time_enabled)
4487                 return -EINVAL;
4488         vcpu->arch.pvclock_set_guest_stopped_request = true;
4489         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4490         return 0;
4491 }
4492
4493 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4494                                      struct kvm_enable_cap *cap)
4495 {
4496         int r;
4497         uint16_t vmcs_version;
4498         void __user *user_ptr;
4499
4500         if (cap->flags)
4501                 return -EINVAL;
4502
4503         switch (cap->cap) {
4504         case KVM_CAP_HYPERV_SYNIC2:
4505                 if (cap->args[0])
4506                         return -EINVAL;
4507                 fallthrough;
4508
4509         case KVM_CAP_HYPERV_SYNIC:
4510                 if (!irqchip_in_kernel(vcpu->kvm))
4511                         return -EINVAL;
4512                 return kvm_hv_activate_synic(vcpu, cap->cap ==
4513                                              KVM_CAP_HYPERV_SYNIC2);
4514         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4515                 if (!kvm_x86_ops.nested_ops->enable_evmcs)
4516                         return -ENOTTY;
4517                 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
4518                 if (!r) {
4519                         user_ptr = (void __user *)(uintptr_t)cap->args[0];
4520                         if (copy_to_user(user_ptr, &vmcs_version,
4521                                          sizeof(vmcs_version)))
4522                                 r = -EFAULT;
4523                 }
4524                 return r;
4525         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4526                 if (!kvm_x86_ops.enable_direct_tlbflush)
4527                         return -ENOTTY;
4528
4529                 return kvm_x86_ops.enable_direct_tlbflush(vcpu);
4530
4531         default:
4532                 return -EINVAL;
4533         }
4534 }
4535
4536 long kvm_arch_vcpu_ioctl(struct file *filp,
4537                          unsigned int ioctl, unsigned long arg)
4538 {
4539         struct kvm_vcpu *vcpu = filp->private_data;
4540         void __user *argp = (void __user *)arg;
4541         int r;
4542         union {
4543                 struct kvm_lapic_state *lapic;
4544                 struct kvm_xsave *xsave;
4545                 struct kvm_xcrs *xcrs;
4546                 void *buffer;
4547         } u;
4548
4549         vcpu_load(vcpu);
4550
4551         u.buffer = NULL;
4552         switch (ioctl) {
4553         case KVM_GET_LAPIC: {
4554                 r = -EINVAL;
4555                 if (!lapic_in_kernel(vcpu))
4556                         goto out;
4557                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4558                                 GFP_KERNEL_ACCOUNT);
4559
4560                 r = -ENOMEM;
4561                 if (!u.lapic)
4562                         goto out;
4563                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4564                 if (r)
4565                         goto out;
4566                 r = -EFAULT;
4567                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4568                         goto out;
4569                 r = 0;
4570                 break;
4571         }
4572         case KVM_SET_LAPIC: {
4573                 r = -EINVAL;
4574                 if (!lapic_in_kernel(vcpu))
4575                         goto out;
4576                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4577                 if (IS_ERR(u.lapic)) {
4578                         r = PTR_ERR(u.lapic);
4579                         goto out_nofree;
4580                 }
4581
4582                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4583                 break;
4584         }
4585         case KVM_INTERRUPT: {
4586                 struct kvm_interrupt irq;
4587
4588                 r = -EFAULT;
4589                 if (copy_from_user(&irq, argp, sizeof(irq)))
4590                         goto out;
4591                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4592                 break;
4593         }
4594         case KVM_NMI: {
4595                 r = kvm_vcpu_ioctl_nmi(vcpu);
4596                 break;
4597         }
4598         case KVM_SMI: {
4599                 r = kvm_vcpu_ioctl_smi(vcpu);
4600                 break;
4601         }
4602         case KVM_SET_CPUID: {
4603                 struct kvm_cpuid __user *cpuid_arg = argp;
4604                 struct kvm_cpuid cpuid;
4605
4606                 r = -EFAULT;
4607                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4608                         goto out;
4609                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4610                 break;
4611         }
4612         case KVM_SET_CPUID2: {
4613                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4614                 struct kvm_cpuid2 cpuid;
4615
4616                 r = -EFAULT;
4617                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4618                         goto out;
4619                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4620                                               cpuid_arg->entries);
4621                 break;
4622         }
4623         case KVM_GET_CPUID2: {
4624                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4625                 struct kvm_cpuid2 cpuid;
4626
4627                 r = -EFAULT;
4628                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4629                         goto out;
4630                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4631                                               cpuid_arg->entries);
4632                 if (r)
4633                         goto out;
4634                 r = -EFAULT;
4635                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4636                         goto out;
4637                 r = 0;
4638                 break;
4639         }
4640         case KVM_GET_MSRS: {
4641                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4642                 r = msr_io(vcpu, argp, do_get_msr, 1);
4643                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4644                 break;
4645         }
4646         case KVM_SET_MSRS: {
4647                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4648                 r = msr_io(vcpu, argp, do_set_msr, 0);
4649                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4650                 break;
4651         }
4652         case KVM_TPR_ACCESS_REPORTING: {
4653                 struct kvm_tpr_access_ctl tac;
4654
4655                 r = -EFAULT;
4656                 if (copy_from_user(&tac, argp, sizeof(tac)))
4657                         goto out;
4658                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4659                 if (r)
4660                         goto out;
4661                 r = -EFAULT;
4662                 if (copy_to_user(argp, &tac, sizeof(tac)))
4663                         goto out;
4664                 r = 0;
4665                 break;
4666         };
4667         case KVM_SET_VAPIC_ADDR: {
4668                 struct kvm_vapic_addr va;
4669                 int idx;
4670
4671                 r = -EINVAL;
4672                 if (!lapic_in_kernel(vcpu))
4673                         goto out;
4674                 r = -EFAULT;
4675                 if (copy_from_user(&va, argp, sizeof(va)))
4676                         goto out;
4677                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4678                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4679                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4680                 break;
4681         }
4682         case KVM_X86_SETUP_MCE: {
4683                 u64 mcg_cap;
4684
4685                 r = -EFAULT;
4686                 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4687                         goto out;
4688                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4689                 break;
4690         }
4691         case KVM_X86_SET_MCE: {
4692                 struct kvm_x86_mce mce;
4693
4694                 r = -EFAULT;
4695                 if (copy_from_user(&mce, argp, sizeof(mce)))
4696                         goto out;
4697                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4698                 break;
4699         }
4700         case KVM_GET_VCPU_EVENTS: {
4701                 struct kvm_vcpu_events events;
4702
4703                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4704
4705                 r = -EFAULT;
4706                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4707                         break;
4708                 r = 0;
4709                 break;
4710         }
4711         case KVM_SET_VCPU_EVENTS: {
4712                 struct kvm_vcpu_events events;
4713
4714                 r = -EFAULT;
4715                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4716                         break;
4717
4718                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4719                 break;
4720         }
4721         case KVM_GET_DEBUGREGS: {
4722                 struct kvm_debugregs dbgregs;
4723
4724                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4725
4726                 r = -EFAULT;
4727                 if (copy_to_user(argp, &dbgregs,
4728                                  sizeof(struct kvm_debugregs)))
4729                         break;
4730                 r = 0;
4731                 break;
4732         }
4733         case KVM_SET_DEBUGREGS: {
4734                 struct kvm_debugregs dbgregs;
4735
4736                 r = -EFAULT;
4737                 if (copy_from_user(&dbgregs, argp,
4738                                    sizeof(struct kvm_debugregs)))
4739                         break;
4740
4741                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4742                 break;
4743         }
4744         case KVM_GET_XSAVE: {
4745                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4746                 r = -ENOMEM;
4747                 if (!u.xsave)
4748                         break;
4749
4750                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4751
4752                 r = -EFAULT;
4753                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4754                         break;
4755                 r = 0;
4756                 break;
4757         }
4758         case KVM_SET_XSAVE: {
4759                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4760                 if (IS_ERR(u.xsave)) {
4761                         r = PTR_ERR(u.xsave);
4762                         goto out_nofree;
4763                 }
4764
4765                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4766                 break;
4767         }
4768         case KVM_GET_XCRS: {
4769                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4770                 r = -ENOMEM;
4771                 if (!u.xcrs)
4772                         break;
4773
4774                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4775
4776                 r = -EFAULT;
4777                 if (copy_to_user(argp, u.xcrs,
4778                                  sizeof(struct kvm_xcrs)))
4779                         break;
4780                 r = 0;
4781                 break;
4782         }
4783         case KVM_SET_XCRS: {
4784                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4785                 if (IS_ERR(u.xcrs)) {
4786                         r = PTR_ERR(u.xcrs);
4787                         goto out_nofree;
4788                 }
4789
4790                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4791                 break;
4792         }
4793         case KVM_SET_TSC_KHZ: {
4794                 u32 user_tsc_khz;
4795
4796                 r = -EINVAL;
4797                 user_tsc_khz = (u32)arg;
4798
4799                 if (kvm_has_tsc_control &&
4800                     user_tsc_khz >= kvm_max_guest_tsc_khz)
4801                         goto out;
4802
4803                 if (user_tsc_khz == 0)
4804                         user_tsc_khz = tsc_khz;
4805
4806                 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4807                         r = 0;
4808
4809                 goto out;
4810         }
4811         case KVM_GET_TSC_KHZ: {
4812                 r = vcpu->arch.virtual_tsc_khz;
4813                 goto out;
4814         }
4815         case KVM_KVMCLOCK_CTRL: {
4816                 r = kvm_set_guest_paused(vcpu);
4817                 goto out;
4818         }
4819         case KVM_ENABLE_CAP: {
4820                 struct kvm_enable_cap cap;
4821
4822                 r = -EFAULT;
4823                 if (copy_from_user(&cap, argp, sizeof(cap)))
4824                         goto out;
4825                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4826                 break;
4827         }
4828         case KVM_GET_NESTED_STATE: {
4829                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4830                 u32 user_data_size;
4831
4832                 r = -EINVAL;
4833                 if (!kvm_x86_ops.nested_ops->get_state)
4834                         break;
4835
4836                 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4837                 r = -EFAULT;
4838                 if (get_user(user_data_size, &user_kvm_nested_state->size))
4839                         break;
4840
4841                 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
4842                                                      user_data_size);
4843                 if (r < 0)
4844                         break;
4845
4846                 if (r > user_data_size) {
4847                         if (put_user(r, &user_kvm_nested_state->size))
4848                                 r = -EFAULT;
4849                         else
4850                                 r = -E2BIG;
4851                         break;
4852                 }
4853
4854                 r = 0;
4855                 break;
4856         }
4857         case KVM_SET_NESTED_STATE: {
4858                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4859                 struct kvm_nested_state kvm_state;
4860                 int idx;
4861
4862                 r = -EINVAL;
4863                 if (!kvm_x86_ops.nested_ops->set_state)
4864                         break;
4865
4866                 r = -EFAULT;
4867                 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4868                         break;
4869
4870                 r = -EINVAL;
4871                 if (kvm_state.size < sizeof(kvm_state))
4872                         break;
4873
4874                 if (kvm_state.flags &
4875                     ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4876                       | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
4877                       | KVM_STATE_NESTED_GIF_SET))
4878                         break;
4879
4880                 /* nested_run_pending implies guest_mode.  */
4881                 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4882                     && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4883                         break;
4884
4885                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4886                 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
4887                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4888                 break;
4889         }
4890         case KVM_GET_SUPPORTED_HV_CPUID: {
4891                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4892                 struct kvm_cpuid2 cpuid;
4893
4894                 r = -EFAULT;
4895                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4896                         goto out;
4897
4898                 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4899                                                 cpuid_arg->entries);
4900                 if (r)
4901                         goto out;
4902
4903                 r = -EFAULT;
4904                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4905                         goto out;
4906                 r = 0;
4907                 break;
4908         }
4909         default:
4910                 r = -EINVAL;
4911         }
4912 out:
4913         kfree(u.buffer);
4914 out_nofree:
4915         vcpu_put(vcpu);
4916         return r;
4917 }
4918
4919 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4920 {
4921         return VM_FAULT_SIGBUS;
4922 }
4923
4924 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4925 {
4926         int ret;
4927
4928         if (addr > (unsigned int)(-3 * PAGE_SIZE))
4929                 return -EINVAL;
4930         ret = kvm_x86_ops.set_tss_addr(kvm, addr);
4931         return ret;
4932 }
4933
4934 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4935                                               u64 ident_addr)
4936 {
4937         return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr);
4938 }
4939
4940 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4941                                          unsigned long kvm_nr_mmu_pages)
4942 {
4943         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4944                 return -EINVAL;
4945
4946         mutex_lock(&kvm->slots_lock);
4947
4948         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4949         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4950
4951         mutex_unlock(&kvm->slots_lock);
4952         return 0;
4953 }
4954
4955 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4956 {
4957         return kvm->arch.n_max_mmu_pages;
4958 }
4959
4960 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4961 {
4962         struct kvm_pic *pic = kvm->arch.vpic;
4963         int r;
4964
4965         r = 0;
4966         switch (chip->chip_id) {
4967         case KVM_IRQCHIP_PIC_MASTER:
4968                 memcpy(&chip->chip.pic, &pic->pics[0],
4969                         sizeof(struct kvm_pic_state));
4970                 break;
4971         case KVM_IRQCHIP_PIC_SLAVE:
4972                 memcpy(&chip->chip.pic, &pic->pics[1],
4973                         sizeof(struct kvm_pic_state));
4974                 break;
4975         case KVM_IRQCHIP_IOAPIC:
4976                 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4977                 break;
4978         default:
4979                 r = -EINVAL;
4980                 break;
4981         }
4982         return r;
4983 }
4984
4985 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4986 {
4987         struct kvm_pic *pic = kvm->arch.vpic;
4988         int r;
4989
4990         r = 0;
4991         switch (chip->chip_id) {
4992         case KVM_IRQCHIP_PIC_MASTER:
4993                 spin_lock(&pic->lock);
4994                 memcpy(&pic->pics[0], &chip->chip.pic,
4995                         sizeof(struct kvm_pic_state));
4996                 spin_unlock(&pic->lock);
4997                 break;
4998         case KVM_IRQCHIP_PIC_SLAVE:
4999                 spin_lock(&pic->lock);
5000                 memcpy(&pic->pics[1], &chip->chip.pic,
5001                         sizeof(struct kvm_pic_state));
5002                 spin_unlock(&pic->lock);
5003                 break;
5004         case KVM_IRQCHIP_IOAPIC:
5005                 kvm_set_ioapic(kvm, &chip->chip.ioapic);
5006                 break;
5007         default:
5008                 r = -EINVAL;
5009                 break;
5010         }
5011         kvm_pic_update_irq(pic);
5012         return r;
5013 }
5014
5015 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5016 {
5017         struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
5018
5019         BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
5020
5021         mutex_lock(&kps->lock);
5022         memcpy(ps, &kps->channels, sizeof(*ps));
5023         mutex_unlock(&kps->lock);
5024         return 0;
5025 }
5026
5027 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5028 {
5029         int i;
5030         struct kvm_pit *pit = kvm->arch.vpit;
5031
5032         mutex_lock(&pit->pit_state.lock);
5033         memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
5034         for (i = 0; i < 3; i++)
5035                 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
5036         mutex_unlock(&pit->pit_state.lock);
5037         return 0;
5038 }
5039
5040 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5041 {
5042         mutex_lock(&kvm->arch.vpit->pit_state.lock);
5043         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
5044                 sizeof(ps->channels));
5045         ps->flags = kvm->arch.vpit->pit_state.flags;
5046         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
5047         memset(&ps->reserved, 0, sizeof(ps->reserved));
5048         return 0;
5049 }
5050
5051 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5052 {
5053         int start = 0;
5054         int i;
5055         u32 prev_legacy, cur_legacy;
5056         struct kvm_pit *pit = kvm->arch.vpit;
5057
5058         mutex_lock(&pit->pit_state.lock);
5059         prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
5060         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
5061         if (!prev_legacy && cur_legacy)
5062                 start = 1;
5063         memcpy(&pit->pit_state.channels, &ps->channels,
5064                sizeof(pit->pit_state.channels));
5065         pit->pit_state.flags = ps->flags;
5066         for (i = 0; i < 3; i++)
5067                 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
5068                                    start && i == 0);
5069         mutex_unlock(&pit->pit_state.lock);
5070         return 0;
5071 }
5072
5073 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
5074                                  struct kvm_reinject_control *control)
5075 {
5076         struct kvm_pit *pit = kvm->arch.vpit;
5077
5078         /* pit->pit_state.lock was overloaded to prevent userspace from getting
5079          * an inconsistent state after running multiple KVM_REINJECT_CONTROL
5080          * ioctls in parallel.  Use a separate lock if that ioctl isn't rare.
5081          */
5082         mutex_lock(&pit->pit_state.lock);
5083         kvm_pit_set_reinject(pit, control->pit_reinject);
5084         mutex_unlock(&pit->pit_state.lock);
5085
5086         return 0;
5087 }
5088
5089 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
5090 {
5091         /*
5092          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
5093          */
5094         if (kvm_x86_ops.flush_log_dirty)
5095                 kvm_x86_ops.flush_log_dirty(kvm);
5096 }
5097
5098 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
5099                         bool line_status)
5100 {
5101         if (!irqchip_in_kernel(kvm))
5102                 return -ENXIO;
5103
5104         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
5105                                         irq_event->irq, irq_event->level,
5106                                         line_status);
5107         return 0;
5108 }
5109
5110 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
5111                             struct kvm_enable_cap *cap)
5112 {
5113         int r;
5114
5115         if (cap->flags)
5116                 return -EINVAL;
5117
5118         switch (cap->cap) {
5119         case KVM_CAP_DISABLE_QUIRKS:
5120                 kvm->arch.disabled_quirks = cap->args[0];
5121                 r = 0;
5122                 break;
5123         case KVM_CAP_SPLIT_IRQCHIP: {
5124                 mutex_lock(&kvm->lock);
5125                 r = -EINVAL;
5126                 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
5127                         goto split_irqchip_unlock;
5128                 r = -EEXIST;
5129                 if (irqchip_in_kernel(kvm))
5130                         goto split_irqchip_unlock;
5131                 if (kvm->created_vcpus)
5132                         goto split_irqchip_unlock;
5133                 r = kvm_setup_empty_irq_routing(kvm);
5134                 if (r)
5135                         goto split_irqchip_unlock;
5136                 /* Pairs with irqchip_in_kernel. */
5137                 smp_wmb();
5138                 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
5139                 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
5140                 r = 0;
5141 split_irqchip_unlock:
5142                 mutex_unlock(&kvm->lock);
5143                 break;
5144         }
5145         case KVM_CAP_X2APIC_API:
5146                 r = -EINVAL;
5147                 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
5148                         break;
5149
5150                 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
5151                         kvm->arch.x2apic_format = true;
5152                 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
5153                         kvm->arch.x2apic_broadcast_quirk_disabled = true;
5154
5155                 r = 0;
5156                 break;
5157         case KVM_CAP_X86_DISABLE_EXITS:
5158                 r = -EINVAL;
5159                 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
5160                         break;
5161
5162                 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
5163                         kvm_can_mwait_in_guest())
5164                         kvm->arch.mwait_in_guest = true;
5165                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
5166                         kvm->arch.hlt_in_guest = true;
5167                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
5168                         kvm->arch.pause_in_guest = true;
5169                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
5170                         kvm->arch.cstate_in_guest = true;
5171                 r = 0;
5172                 break;
5173         case KVM_CAP_MSR_PLATFORM_INFO:
5174                 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
5175                 r = 0;
5176                 break;
5177         case KVM_CAP_EXCEPTION_PAYLOAD:
5178                 kvm->arch.exception_payload_enabled = cap->args[0];
5179                 r = 0;
5180                 break;
5181         case KVM_CAP_X86_USER_SPACE_MSR:
5182                 kvm->arch.user_space_msr_mask = cap->args[0];
5183                 r = 0;
5184                 break;
5185         default:
5186                 r = -EINVAL;
5187                 break;
5188         }
5189         return r;
5190 }
5191
5192 static void kvm_clear_msr_filter(struct kvm *kvm)
5193 {
5194         u32 i;
5195         u32 count = kvm->arch.msr_filter.count;
5196         struct msr_bitmap_range ranges[16];
5197
5198         mutex_lock(&kvm->lock);
5199         kvm->arch.msr_filter.count = 0;
5200         memcpy(ranges, kvm->arch.msr_filter.ranges, count * sizeof(ranges[0]));
5201         mutex_unlock(&kvm->lock);
5202         synchronize_srcu(&kvm->srcu);
5203
5204         for (i = 0; i < count; i++)
5205                 kfree(ranges[i].bitmap);
5206 }
5207
5208 static int kvm_add_msr_filter(struct kvm *kvm, struct kvm_msr_filter_range *user_range)
5209 {
5210         struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
5211         struct msr_bitmap_range range;
5212         unsigned long *bitmap = NULL;
5213         size_t bitmap_size;
5214         int r;
5215
5216         if (!user_range->nmsrs)
5217                 return 0;
5218
5219         bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
5220         if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
5221                 return -EINVAL;
5222
5223         bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
5224         if (IS_ERR(bitmap))
5225                 return PTR_ERR(bitmap);
5226
5227         range = (struct msr_bitmap_range) {
5228                 .flags = user_range->flags,
5229                 .base = user_range->base,
5230                 .nmsrs = user_range->nmsrs,
5231                 .bitmap = bitmap,
5232         };
5233
5234         if (range.flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) {
5235                 r = -EINVAL;
5236                 goto err;
5237         }
5238
5239         if (!range.flags) {
5240                 r = -EINVAL;
5241                 goto err;
5242         }
5243
5244         /* Everything ok, add this range identifier to our global pool */
5245         ranges[kvm->arch.msr_filter.count] = range;
5246         /* Make sure we filled the array before we tell anyone to walk it */
5247         smp_wmb();
5248         kvm->arch.msr_filter.count++;
5249
5250         return 0;
5251 err:
5252         kfree(bitmap);
5253         return r;
5254 }
5255
5256 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp)
5257 {
5258         struct kvm_msr_filter __user *user_msr_filter = argp;
5259         struct kvm_msr_filter filter;
5260         bool default_allow;
5261         int r = 0;
5262         bool empty = true;
5263         u32 i;
5264
5265         if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
5266                 return -EFAULT;
5267
5268         for (i = 0; i < ARRAY_SIZE(filter.ranges); i++)
5269                 empty &= !filter.ranges[i].nmsrs;
5270
5271         default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY);
5272         if (empty && !default_allow)
5273                 return -EINVAL;
5274
5275         kvm_clear_msr_filter(kvm);
5276
5277         kvm->arch.msr_filter.default_allow = default_allow;
5278
5279         /*
5280          * Protect from concurrent calls to this function that could trigger
5281          * a TOCTOU violation on kvm->arch.msr_filter.count.
5282          */
5283         mutex_lock(&kvm->lock);
5284         for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
5285                 r = kvm_add_msr_filter(kvm, &filter.ranges[i]);
5286                 if (r)
5287                         break;
5288         }
5289
5290         kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
5291         mutex_unlock(&kvm->lock);
5292
5293         return r;
5294 }
5295
5296 long kvm_arch_vm_ioctl(struct file *filp,
5297                        unsigned int ioctl, unsigned long arg)
5298 {
5299         struct kvm *kvm = filp->private_data;
5300         void __user *argp = (void __user *)arg;
5301         int r = -ENOTTY;
5302         /*
5303          * This union makes it completely explicit to gcc-3.x
5304          * that these two variables' stack usage should be
5305          * combined, not added together.
5306          */
5307         union {
5308                 struct kvm_pit_state ps;
5309                 struct kvm_pit_state2 ps2;
5310                 struct kvm_pit_config pit_config;
5311         } u;
5312
5313         switch (ioctl) {
5314         case KVM_SET_TSS_ADDR:
5315                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
5316                 break;
5317         case KVM_SET_IDENTITY_MAP_ADDR: {
5318                 u64 ident_addr;
5319
5320                 mutex_lock(&kvm->lock);
5321                 r = -EINVAL;
5322                 if (kvm->created_vcpus)
5323                         goto set_identity_unlock;
5324                 r = -EFAULT;
5325                 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
5326                         goto set_identity_unlock;
5327                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
5328 set_identity_unlock:
5329                 mutex_unlock(&kvm->lock);
5330                 break;
5331         }
5332         case KVM_SET_NR_MMU_PAGES:
5333                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
5334                 break;
5335         case KVM_GET_NR_MMU_PAGES:
5336                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
5337                 break;
5338         case KVM_CREATE_IRQCHIP: {
5339                 mutex_lock(&kvm->lock);
5340
5341                 r = -EEXIST;
5342                 if (irqchip_in_kernel(kvm))
5343                         goto create_irqchip_unlock;
5344
5345                 r = -EINVAL;
5346                 if (kvm->created_vcpus)
5347                         goto create_irqchip_unlock;
5348
5349                 r = kvm_pic_init(kvm);
5350                 if (r)
5351                         goto create_irqchip_unlock;
5352
5353                 r = kvm_ioapic_init(kvm);
5354                 if (r) {
5355                         kvm_pic_destroy(kvm);
5356                         goto create_irqchip_unlock;
5357                 }
5358
5359                 r = kvm_setup_default_irq_routing(kvm);
5360                 if (r) {
5361                         kvm_ioapic_destroy(kvm);
5362                         kvm_pic_destroy(kvm);
5363                         goto create_irqchip_unlock;
5364                 }
5365                 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
5366                 smp_wmb();
5367                 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
5368         create_irqchip_unlock:
5369                 mutex_unlock(&kvm->lock);
5370                 break;
5371         }
5372         case KVM_CREATE_PIT:
5373                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
5374                 goto create_pit;
5375         case KVM_CREATE_PIT2:
5376                 r = -EFAULT;
5377                 if (copy_from_user(&u.pit_config, argp,
5378                                    sizeof(struct kvm_pit_config)))
5379                         goto out;
5380         create_pit:
5381                 mutex_lock(&kvm->lock);
5382                 r = -EEXIST;
5383                 if (kvm->arch.vpit)
5384                         goto create_pit_unlock;
5385                 r = -ENOMEM;
5386                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5387                 if (kvm->arch.vpit)
5388                         r = 0;
5389         create_pit_unlock:
5390                 mutex_unlock(&kvm->lock);
5391                 break;
5392         case KVM_GET_IRQCHIP: {
5393                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5394                 struct kvm_irqchip *chip;
5395
5396                 chip = memdup_user(argp, sizeof(*chip));
5397                 if (IS_ERR(chip)) {
5398                         r = PTR_ERR(chip);
5399                         goto out;
5400                 }
5401
5402                 r = -ENXIO;
5403                 if (!irqchip_kernel(kvm))
5404                         goto get_irqchip_out;
5405                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5406                 if (r)
5407                         goto get_irqchip_out;
5408                 r = -EFAULT;
5409                 if (copy_to_user(argp, chip, sizeof(*chip)))
5410                         goto get_irqchip_out;
5411                 r = 0;
5412         get_irqchip_out:
5413                 kfree(chip);
5414                 break;
5415         }
5416         case KVM_SET_IRQCHIP: {
5417                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5418                 struct kvm_irqchip *chip;
5419
5420                 chip = memdup_user(argp, sizeof(*chip));
5421                 if (IS_ERR(chip)) {
5422                         r = PTR_ERR(chip);
5423                         goto out;
5424                 }
5425
5426                 r = -ENXIO;
5427                 if (!irqchip_kernel(kvm))
5428                         goto set_irqchip_out;
5429                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5430         set_irqchip_out:
5431                 kfree(chip);
5432                 break;
5433         }
5434         case KVM_GET_PIT: {
5435                 r = -EFAULT;
5436                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5437                         goto out;
5438                 r = -ENXIO;
5439                 if (!kvm->arch.vpit)
5440                         goto out;
5441                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5442                 if (r)
5443                         goto out;
5444                 r = -EFAULT;
5445                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5446                         goto out;
5447                 r = 0;
5448                 break;
5449         }
5450         case KVM_SET_PIT: {
5451                 r = -EFAULT;
5452                 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5453                         goto out;
5454                 mutex_lock(&kvm->lock);
5455                 r = -ENXIO;
5456                 if (!kvm->arch.vpit)
5457                         goto set_pit_out;
5458                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5459 set_pit_out:
5460                 mutex_unlock(&kvm->lock);
5461                 break;
5462         }
5463         case KVM_GET_PIT2: {
5464                 r = -ENXIO;
5465                 if (!kvm->arch.vpit)
5466                         goto out;
5467                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5468                 if (r)
5469                         goto out;
5470                 r = -EFAULT;
5471                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5472                         goto out;
5473                 r = 0;
5474                 break;
5475         }
5476         case KVM_SET_PIT2: {
5477                 r = -EFAULT;
5478                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5479                         goto out;
5480                 mutex_lock(&kvm->lock);
5481                 r = -ENXIO;
5482                 if (!kvm->arch.vpit)
5483                         goto set_pit2_out;
5484                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5485 set_pit2_out:
5486                 mutex_unlock(&kvm->lock);
5487                 break;
5488         }
5489         case KVM_REINJECT_CONTROL: {
5490                 struct kvm_reinject_control control;
5491                 r =  -EFAULT;
5492                 if (copy_from_user(&control, argp, sizeof(control)))
5493                         goto out;
5494                 r = -ENXIO;
5495                 if (!kvm->arch.vpit)
5496                         goto out;
5497                 r = kvm_vm_ioctl_reinject(kvm, &control);
5498                 break;
5499         }
5500         case KVM_SET_BOOT_CPU_ID:
5501                 r = 0;
5502                 mutex_lock(&kvm->lock);
5503                 if (kvm->created_vcpus)
5504                         r = -EBUSY;
5505                 else
5506                         kvm->arch.bsp_vcpu_id = arg;
5507                 mutex_unlock(&kvm->lock);
5508                 break;
5509         case KVM_XEN_HVM_CONFIG: {
5510                 struct kvm_xen_hvm_config xhc;
5511                 r = -EFAULT;
5512                 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5513                         goto out;
5514                 r = -EINVAL;
5515                 if (xhc.flags)
5516                         goto out;
5517                 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5518                 r = 0;
5519                 break;
5520         }
5521         case KVM_SET_CLOCK: {
5522                 struct kvm_clock_data user_ns;
5523                 u64 now_ns;
5524
5525                 r = -EFAULT;
5526                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5527                         goto out;
5528
5529                 r = -EINVAL;
5530                 if (user_ns.flags)
5531                         goto out;
5532
5533                 r = 0;
5534                 /*
5535                  * TODO: userspace has to take care of races with VCPU_RUN, so
5536                  * kvm_gen_update_masterclock() can be cut down to locked
5537                  * pvclock_update_vm_gtod_copy().
5538                  */
5539                 kvm_gen_update_masterclock(kvm);
5540                 now_ns = get_kvmclock_ns(kvm);
5541                 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5542                 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5543                 break;
5544         }
5545         case KVM_GET_CLOCK: {
5546                 struct kvm_clock_data user_ns;
5547                 u64 now_ns;
5548
5549                 now_ns = get_kvmclock_ns(kvm);
5550                 user_ns.clock = now_ns;
5551                 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5552                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5553
5554                 r = -EFAULT;
5555                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5556                         goto out;
5557                 r = 0;
5558                 break;
5559         }
5560         case KVM_MEMORY_ENCRYPT_OP: {
5561                 r = -ENOTTY;
5562                 if (kvm_x86_ops.mem_enc_op)
5563                         r = kvm_x86_ops.mem_enc_op(kvm, argp);
5564                 break;
5565         }
5566         case KVM_MEMORY_ENCRYPT_REG_REGION: {
5567                 struct kvm_enc_region region;
5568
5569                 r = -EFAULT;
5570                 if (copy_from_user(&region, argp, sizeof(region)))
5571                         goto out;
5572
5573                 r = -ENOTTY;
5574                 if (kvm_x86_ops.mem_enc_reg_region)
5575                         r = kvm_x86_ops.mem_enc_reg_region(kvm, &region);
5576                 break;
5577         }
5578         case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5579                 struct kvm_enc_region region;
5580
5581                 r = -EFAULT;
5582                 if (copy_from_user(&region, argp, sizeof(region)))
5583                         goto out;
5584
5585                 r = -ENOTTY;
5586                 if (kvm_x86_ops.mem_enc_unreg_region)
5587                         r = kvm_x86_ops.mem_enc_unreg_region(kvm, &region);
5588                 break;
5589         }
5590         case KVM_HYPERV_EVENTFD: {
5591                 struct kvm_hyperv_eventfd hvevfd;
5592
5593                 r = -EFAULT;
5594                 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5595                         goto out;
5596                 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5597                 break;
5598         }
5599         case KVM_SET_PMU_EVENT_FILTER:
5600                 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5601                 break;
5602         case KVM_X86_SET_MSR_FILTER:
5603                 r = kvm_vm_ioctl_set_msr_filter(kvm, argp);
5604                 break;
5605         default:
5606                 r = -ENOTTY;
5607         }
5608 out:
5609         return r;
5610 }
5611
5612 static void kvm_init_msr_list(void)
5613 {
5614         struct x86_pmu_capability x86_pmu;
5615         u32 dummy[2];
5616         unsigned i;
5617
5618         BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5619                          "Please update the fixed PMCs in msrs_to_saved_all[]");
5620
5621         perf_get_x86_pmu_capability(&x86_pmu);
5622
5623         num_msrs_to_save = 0;
5624         num_emulated_msrs = 0;
5625         num_msr_based_features = 0;
5626
5627         for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5628                 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5629                         continue;
5630
5631                 /*
5632                  * Even MSRs that are valid in the host may not be exposed
5633                  * to the guests in some cases.
5634                  */
5635                 switch (msrs_to_save_all[i]) {
5636                 case MSR_IA32_BNDCFGS:
5637                         if (!kvm_mpx_supported())
5638                                 continue;
5639                         break;
5640                 case MSR_TSC_AUX:
5641                         if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5642                                 continue;
5643                         break;
5644                 case MSR_IA32_UMWAIT_CONTROL:
5645                         if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
5646                                 continue;
5647                         break;
5648                 case MSR_IA32_RTIT_CTL:
5649                 case MSR_IA32_RTIT_STATUS:
5650                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5651                                 continue;
5652                         break;
5653                 case MSR_IA32_RTIT_CR3_MATCH:
5654                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5655                             !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5656                                 continue;
5657                         break;
5658                 case MSR_IA32_RTIT_OUTPUT_BASE:
5659                 case MSR_IA32_RTIT_OUTPUT_MASK:
5660                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5661                                 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5662                                  !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5663                                 continue;
5664                         break;
5665                 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
5666                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5667                                 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5668                                 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5669                                 continue;
5670                         break;
5671                 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5672                         if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5673                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5674                                 continue;
5675                         break;
5676                 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5677                         if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5678                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5679                                 continue;
5680                         break;
5681                 default:
5682                         break;
5683                 }
5684
5685                 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5686         }
5687
5688         for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5689                 if (!kvm_x86_ops.has_emulated_msr(emulated_msrs_all[i]))
5690                         continue;
5691
5692                 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5693         }
5694
5695         for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5696                 struct kvm_msr_entry msr;
5697
5698                 msr.index = msr_based_features_all[i];
5699                 if (kvm_get_msr_feature(&msr))
5700                         continue;
5701
5702                 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5703         }
5704 }
5705
5706 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5707                            const void *v)
5708 {
5709         int handled = 0;
5710         int n;
5711
5712         do {
5713                 n = min(len, 8);
5714                 if (!(lapic_in_kernel(vcpu) &&
5715                       !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5716                     && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5717                         break;
5718                 handled += n;
5719                 addr += n;
5720                 len -= n;
5721                 v += n;
5722         } while (len);
5723
5724         return handled;
5725 }
5726
5727 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5728 {
5729         int handled = 0;
5730         int n;
5731
5732         do {
5733                 n = min(len, 8);
5734                 if (!(lapic_in_kernel(vcpu) &&
5735                       !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5736                                          addr, n, v))
5737                     && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5738                         break;
5739                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5740                 handled += n;
5741                 addr += n;
5742                 len -= n;
5743                 v += n;
5744         } while (len);
5745
5746         return handled;
5747 }
5748
5749 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5750                         struct kvm_segment *var, int seg)
5751 {
5752         kvm_x86_ops.set_segment(vcpu, var, seg);
5753 }
5754
5755 void kvm_get_segment(struct kvm_vcpu *vcpu,
5756                      struct kvm_segment *var, int seg)
5757 {
5758         kvm_x86_ops.get_segment(vcpu, var, seg);
5759 }
5760
5761 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5762                            struct x86_exception *exception)
5763 {
5764         gpa_t t_gpa;
5765
5766         BUG_ON(!mmu_is_nested(vcpu));
5767
5768         /* NPT walks are always user-walks */
5769         access |= PFERR_USER_MASK;
5770         t_gpa  = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5771
5772         return t_gpa;
5773 }
5774
5775 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5776                               struct x86_exception *exception)
5777 {
5778         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5779         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5780 }
5781
5782  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5783                                 struct x86_exception *exception)
5784 {
5785         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5786         access |= PFERR_FETCH_MASK;
5787         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5788 }
5789
5790 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5791                                struct x86_exception *exception)
5792 {
5793         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5794         access |= PFERR_WRITE_MASK;
5795         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5796 }
5797
5798 /* uses this to access any guest's mapped memory without checking CPL */
5799 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5800                                 struct x86_exception *exception)
5801 {
5802         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5803 }
5804
5805 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5806                                       struct kvm_vcpu *vcpu, u32 access,
5807                                       struct x86_exception *exception)
5808 {
5809         void *data = val;
5810         int r = X86EMUL_CONTINUE;
5811
5812         while (bytes) {
5813                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5814                                                             exception);
5815                 unsigned offset = addr & (PAGE_SIZE-1);
5816                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5817                 int ret;
5818
5819                 if (gpa == UNMAPPED_GVA)
5820                         return X86EMUL_PROPAGATE_FAULT;
5821                 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5822                                                offset, toread);
5823                 if (ret < 0) {
5824                         r = X86EMUL_IO_NEEDED;
5825                         goto out;
5826                 }
5827
5828                 bytes -= toread;
5829                 data += toread;
5830                 addr += toread;
5831         }
5832 out:
5833         return r;
5834 }
5835
5836 /* used for instruction fetching */
5837 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5838                                 gva_t addr, void *val, unsigned int bytes,
5839                                 struct x86_exception *exception)
5840 {
5841         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5842         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5843         unsigned offset;
5844         int ret;
5845
5846         /* Inline kvm_read_guest_virt_helper for speed.  */
5847         gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5848                                                     exception);
5849         if (unlikely(gpa == UNMAPPED_GVA))
5850                 return X86EMUL_PROPAGATE_FAULT;
5851
5852         offset = addr & (PAGE_SIZE-1);
5853         if (WARN_ON(offset + bytes > PAGE_SIZE))
5854                 bytes = (unsigned)PAGE_SIZE - offset;
5855         ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5856                                        offset, bytes);
5857         if (unlikely(ret < 0))
5858                 return X86EMUL_IO_NEEDED;
5859
5860         return X86EMUL_CONTINUE;
5861 }
5862
5863 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5864                                gva_t addr, void *val, unsigned int bytes,
5865                                struct x86_exception *exception)
5866 {
5867         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5868
5869         /*
5870          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5871          * is returned, but our callers are not ready for that and they blindly
5872          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5873          * uninitialized kernel stack memory into cr2 and error code.
5874          */
5875         memset(exception, 0, sizeof(*exception));
5876         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5877                                           exception);
5878 }
5879 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5880
5881 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5882                              gva_t addr, void *val, unsigned int bytes,
5883                              struct x86_exception *exception, bool system)
5884 {
5885         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5886         u32 access = 0;
5887
5888         if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5889                 access |= PFERR_USER_MASK;
5890
5891         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5892 }
5893
5894 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5895                 unsigned long addr, void *val, unsigned int bytes)
5896 {
5897         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5898         int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5899
5900         return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5901 }
5902
5903 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5904                                       struct kvm_vcpu *vcpu, u32 access,
5905                                       struct x86_exception *exception)
5906 {
5907         void *data = val;
5908         int r = X86EMUL_CONTINUE;
5909
5910         while (bytes) {
5911                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5912                                                              access,
5913                                                              exception);
5914                 unsigned offset = addr & (PAGE_SIZE-1);
5915                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5916                 int ret;
5917
5918                 if (gpa == UNMAPPED_GVA)
5919                         return X86EMUL_PROPAGATE_FAULT;
5920                 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5921                 if (ret < 0) {
5922                         r = X86EMUL_IO_NEEDED;
5923                         goto out;
5924                 }
5925
5926                 bytes -= towrite;
5927                 data += towrite;
5928                 addr += towrite;
5929         }
5930 out:
5931         return r;
5932 }
5933
5934 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5935                               unsigned int bytes, struct x86_exception *exception,
5936                               bool system)
5937 {
5938         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5939         u32 access = PFERR_WRITE_MASK;
5940
5941         if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5942                 access |= PFERR_USER_MASK;
5943
5944         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5945                                            access, exception);
5946 }
5947
5948 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5949                                 unsigned int bytes, struct x86_exception *exception)
5950 {
5951         /* kvm_write_guest_virt_system can pull in tons of pages. */
5952         vcpu->arch.l1tf_flush_l1d = true;
5953
5954         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5955                                            PFERR_WRITE_MASK, exception);
5956 }
5957 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5958
5959 int handle_ud(struct kvm_vcpu *vcpu)
5960 {
5961         static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
5962         int emul_type = EMULTYPE_TRAP_UD;
5963         char sig[5]; /* ud2; .ascii "kvm" */
5964         struct x86_exception e;
5965
5966         if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, NULL, 0)))
5967                 return 1;
5968
5969         if (force_emulation_prefix &&
5970             kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5971                                 sig, sizeof(sig), &e) == 0 &&
5972             memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
5973                 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5974                 emul_type = EMULTYPE_TRAP_UD_FORCED;
5975         }
5976
5977         return kvm_emulate_instruction(vcpu, emul_type);
5978 }
5979 EXPORT_SYMBOL_GPL(handle_ud);
5980
5981 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5982                             gpa_t gpa, bool write)
5983 {
5984         /* For APIC access vmexit */
5985         if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5986                 return 1;
5987
5988         if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5989                 trace_vcpu_match_mmio(gva, gpa, write, true);
5990                 return 1;
5991         }
5992
5993         return 0;
5994 }
5995
5996 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5997                                 gpa_t *gpa, struct x86_exception *exception,
5998                                 bool write)
5999 {
6000         u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
6001                 | (write ? PFERR_WRITE_MASK : 0);
6002
6003         /*
6004          * currently PKRU is only applied to ept enabled guest so
6005          * there is no pkey in EPT page table for L1 guest or EPT
6006          * shadow page table for L2 guest.
6007          */
6008         if (vcpu_match_mmio_gva(vcpu, gva)
6009             && !permission_fault(vcpu, vcpu->arch.walk_mmu,
6010                                  vcpu->arch.mmio_access, 0, access)) {
6011                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
6012                                         (gva & (PAGE_SIZE - 1));
6013                 trace_vcpu_match_mmio(gva, *gpa, write, false);
6014                 return 1;
6015         }
6016
6017         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
6018
6019         if (*gpa == UNMAPPED_GVA)
6020                 return -1;
6021
6022         return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
6023 }
6024
6025 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
6026                         const void *val, int bytes)
6027 {
6028         int ret;
6029
6030         ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
6031         if (ret < 0)
6032                 return 0;
6033         kvm_page_track_write(vcpu, gpa, val, bytes);
6034         return 1;
6035 }
6036
6037 struct read_write_emulator_ops {
6038         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
6039                                   int bytes);
6040         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
6041                                   void *val, int bytes);
6042         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6043                                int bytes, void *val);
6044         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6045                                     void *val, int bytes);
6046         bool write;
6047 };
6048
6049 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
6050 {
6051         if (vcpu->mmio_read_completed) {
6052                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
6053                                vcpu->mmio_fragments[0].gpa, val);
6054                 vcpu->mmio_read_completed = 0;
6055                 return 1;
6056         }
6057
6058         return 0;
6059 }
6060
6061 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6062                         void *val, int bytes)
6063 {
6064         return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
6065 }
6066
6067 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6068                          void *val, int bytes)
6069 {
6070         return emulator_write_phys(vcpu, gpa, val, bytes);
6071 }
6072
6073 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
6074 {
6075         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
6076         return vcpu_mmio_write(vcpu, gpa, bytes, val);
6077 }
6078
6079 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6080                           void *val, int bytes)
6081 {
6082         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
6083         return X86EMUL_IO_NEEDED;
6084 }
6085
6086 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6087                            void *val, int bytes)
6088 {
6089         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
6090
6091         memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
6092         return X86EMUL_CONTINUE;
6093 }
6094
6095 static const struct read_write_emulator_ops read_emultor = {
6096         .read_write_prepare = read_prepare,
6097         .read_write_emulate = read_emulate,
6098         .read_write_mmio = vcpu_mmio_read,
6099         .read_write_exit_mmio = read_exit_mmio,
6100 };
6101
6102 static const struct read_write_emulator_ops write_emultor = {
6103         .read_write_emulate = write_emulate,
6104         .read_write_mmio = write_mmio,
6105         .read_write_exit_mmio = write_exit_mmio,
6106         .write = true,
6107 };
6108
6109 static int emulator_read_write_onepage(unsigned long addr, void *val,
6110                                        unsigned int bytes,
6111                                        struct x86_exception *exception,
6112                                        struct kvm_vcpu *vcpu,
6113                                        const struct read_write_emulator_ops *ops)
6114 {
6115         gpa_t gpa;
6116         int handled, ret;
6117         bool write = ops->write;
6118         struct kvm_mmio_fragment *frag;
6119         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6120
6121         /*
6122          * If the exit was due to a NPF we may already have a GPA.
6123          * If the GPA is present, use it to avoid the GVA to GPA table walk.
6124          * Note, this cannot be used on string operations since string
6125          * operation using rep will only have the initial GPA from the NPF
6126          * occurred.
6127          */
6128         if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
6129             (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
6130                 gpa = ctxt->gpa_val;
6131                 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
6132         } else {
6133                 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
6134                 if (ret < 0)
6135                         return X86EMUL_PROPAGATE_FAULT;
6136         }
6137
6138         if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
6139                 return X86EMUL_CONTINUE;
6140
6141         /*
6142          * Is this MMIO handled locally?
6143          */
6144         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
6145         if (handled == bytes)
6146                 return X86EMUL_CONTINUE;
6147
6148         gpa += handled;
6149         bytes -= handled;
6150         val += handled;
6151
6152         WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
6153         frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
6154         frag->gpa = gpa;
6155         frag->data = val;
6156         frag->len = bytes;
6157         return X86EMUL_CONTINUE;
6158 }
6159
6160 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
6161                         unsigned long addr,
6162                         void *val, unsigned int bytes,
6163                         struct x86_exception *exception,
6164                         const struct read_write_emulator_ops *ops)
6165 {
6166         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6167         gpa_t gpa;
6168         int rc;
6169
6170         if (ops->read_write_prepare &&
6171                   ops->read_write_prepare(vcpu, val, bytes))
6172                 return X86EMUL_CONTINUE;
6173
6174         vcpu->mmio_nr_fragments = 0;
6175
6176         /* Crossing a page boundary? */
6177         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
6178                 int now;
6179
6180                 now = -addr & ~PAGE_MASK;
6181                 rc = emulator_read_write_onepage(addr, val, now, exception,
6182                                                  vcpu, ops);
6183
6184                 if (rc != X86EMUL_CONTINUE)
6185                         return rc;
6186                 addr += now;
6187                 if (ctxt->mode != X86EMUL_MODE_PROT64)
6188                         addr = (u32)addr;
6189                 val += now;
6190                 bytes -= now;
6191         }
6192
6193         rc = emulator_read_write_onepage(addr, val, bytes, exception,
6194                                          vcpu, ops);
6195         if (rc != X86EMUL_CONTINUE)
6196                 return rc;
6197
6198         if (!vcpu->mmio_nr_fragments)
6199                 return rc;
6200
6201         gpa = vcpu->mmio_fragments[0].gpa;
6202
6203         vcpu->mmio_needed = 1;
6204         vcpu->mmio_cur_fragment = 0;
6205
6206         vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
6207         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
6208         vcpu->run->exit_reason = KVM_EXIT_MMIO;
6209         vcpu->run->mmio.phys_addr = gpa;
6210
6211         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
6212 }
6213
6214 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
6215                                   unsigned long addr,
6216                                   void *val,
6217                                   unsigned int bytes,
6218                                   struct x86_exception *exception)
6219 {
6220         return emulator_read_write(ctxt, addr, val, bytes,
6221                                    exception, &read_emultor);
6222 }
6223
6224 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
6225                             unsigned long addr,
6226                             const void *val,
6227                             unsigned int bytes,
6228                             struct x86_exception *exception)
6229 {
6230         return emulator_read_write(ctxt, addr, (void *)val, bytes,
6231                                    exception, &write_emultor);
6232 }
6233
6234 #define CMPXCHG_TYPE(t, ptr, old, new) \
6235         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
6236
6237 #ifdef CONFIG_X86_64
6238 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
6239 #else
6240 #  define CMPXCHG64(ptr, old, new) \
6241         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
6242 #endif
6243
6244 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
6245                                      unsigned long addr,
6246                                      const void *old,
6247                                      const void *new,
6248                                      unsigned int bytes,
6249                                      struct x86_exception *exception)
6250 {
6251         struct kvm_host_map map;
6252         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6253         u64 page_line_mask;
6254         gpa_t gpa;
6255         char *kaddr;
6256         bool exchanged;
6257
6258         /* guests cmpxchg8b have to be emulated atomically */
6259         if (bytes > 8 || (bytes & (bytes - 1)))
6260                 goto emul_write;
6261
6262         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
6263
6264         if (gpa == UNMAPPED_GVA ||
6265             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6266                 goto emul_write;
6267
6268         /*
6269          * Emulate the atomic as a straight write to avoid #AC if SLD is
6270          * enabled in the host and the access splits a cache line.
6271          */
6272         if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
6273                 page_line_mask = ~(cache_line_size() - 1);
6274         else
6275                 page_line_mask = PAGE_MASK;
6276
6277         if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
6278                 goto emul_write;
6279
6280         if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
6281                 goto emul_write;
6282
6283         kaddr = map.hva + offset_in_page(gpa);
6284
6285         switch (bytes) {
6286         case 1:
6287                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
6288                 break;
6289         case 2:
6290                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
6291                 break;
6292         case 4:
6293                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
6294                 break;
6295         case 8:
6296                 exchanged = CMPXCHG64(kaddr, old, new);
6297                 break;
6298         default:
6299                 BUG();
6300         }
6301
6302         kvm_vcpu_unmap(vcpu, &map, true);
6303
6304         if (!exchanged)
6305                 return X86EMUL_CMPXCHG_FAILED;
6306
6307         kvm_page_track_write(vcpu, gpa, new, bytes);
6308
6309         return X86EMUL_CONTINUE;
6310
6311 emul_write:
6312         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
6313
6314         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
6315 }
6316
6317 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
6318 {
6319         int r = 0, i;
6320
6321         for (i = 0; i < vcpu->arch.pio.count; i++) {
6322                 if (vcpu->arch.pio.in)
6323                         r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
6324                                             vcpu->arch.pio.size, pd);
6325                 else
6326                         r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
6327                                              vcpu->arch.pio.port, vcpu->arch.pio.size,
6328                                              pd);
6329                 if (r)
6330                         break;
6331                 pd += vcpu->arch.pio.size;
6332         }
6333         return r;
6334 }
6335
6336 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
6337                                unsigned short port, void *val,
6338                                unsigned int count, bool in)
6339 {
6340         vcpu->arch.pio.port = port;
6341         vcpu->arch.pio.in = in;
6342         vcpu->arch.pio.count  = count;
6343         vcpu->arch.pio.size = size;
6344
6345         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
6346                 vcpu->arch.pio.count = 0;
6347                 return 1;
6348         }
6349
6350         vcpu->run->exit_reason = KVM_EXIT_IO;
6351         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
6352         vcpu->run->io.size = size;
6353         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
6354         vcpu->run->io.count = count;
6355         vcpu->run->io.port = port;
6356
6357         return 0;
6358 }
6359
6360 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
6361                            unsigned short port, void *val, unsigned int count)
6362 {
6363         int ret;
6364
6365         if (vcpu->arch.pio.count)
6366                 goto data_avail;
6367
6368         memset(vcpu->arch.pio_data, 0, size * count);
6369
6370         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
6371         if (ret) {
6372 data_avail:
6373                 memcpy(val, vcpu->arch.pio_data, size * count);
6374                 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
6375                 vcpu->arch.pio.count = 0;
6376                 return 1;
6377         }
6378
6379         return 0;
6380 }
6381
6382 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
6383                                     int size, unsigned short port, void *val,
6384                                     unsigned int count)
6385 {
6386         return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
6387
6388 }
6389
6390 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
6391                             unsigned short port, const void *val,
6392                             unsigned int count)
6393 {
6394         memcpy(vcpu->arch.pio_data, val, size * count);
6395         trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6396         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6397 }
6398
6399 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
6400                                      int size, unsigned short port,
6401                                      const void *val, unsigned int count)
6402 {
6403         return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
6404 }
6405
6406 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6407 {
6408         return kvm_x86_ops.get_segment_base(vcpu, seg);
6409 }
6410
6411 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6412 {
6413         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6414 }
6415
6416 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6417 {
6418         if (!need_emulate_wbinvd(vcpu))
6419                 return X86EMUL_CONTINUE;
6420
6421         if (kvm_x86_ops.has_wbinvd_exit()) {
6422                 int cpu = get_cpu();
6423
6424                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6425                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6426                                 wbinvd_ipi, NULL, 1);
6427                 put_cpu();
6428                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6429         } else
6430                 wbinvd();
6431         return X86EMUL_CONTINUE;
6432 }
6433
6434 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6435 {
6436         kvm_emulate_wbinvd_noskip(vcpu);
6437         return kvm_skip_emulated_instruction(vcpu);
6438 }
6439 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6440
6441
6442
6443 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6444 {
6445         kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6446 }
6447
6448 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6449                            unsigned long *dest)
6450 {
6451         return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6452 }
6453
6454 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6455                            unsigned long value)
6456 {
6457
6458         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6459 }
6460
6461 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6462 {
6463         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6464 }
6465
6466 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6467 {
6468         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6469         unsigned long value;
6470
6471         switch (cr) {
6472         case 0:
6473                 value = kvm_read_cr0(vcpu);
6474                 break;
6475         case 2:
6476                 value = vcpu->arch.cr2;
6477                 break;
6478         case 3:
6479                 value = kvm_read_cr3(vcpu);
6480                 break;
6481         case 4:
6482                 value = kvm_read_cr4(vcpu);
6483                 break;
6484         case 8:
6485                 value = kvm_get_cr8(vcpu);
6486                 break;
6487         default:
6488                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6489                 return 0;
6490         }
6491
6492         return value;
6493 }
6494
6495 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6496 {
6497         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6498         int res = 0;
6499
6500         switch (cr) {
6501         case 0:
6502                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6503                 break;
6504         case 2:
6505                 vcpu->arch.cr2 = val;
6506                 break;
6507         case 3:
6508                 res = kvm_set_cr3(vcpu, val);
6509                 break;
6510         case 4:
6511                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6512                 break;
6513         case 8:
6514                 res = kvm_set_cr8(vcpu, val);
6515                 break;
6516         default:
6517                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6518                 res = -1;
6519         }
6520
6521         return res;
6522 }
6523
6524 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6525 {
6526         return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt));
6527 }
6528
6529 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6530 {
6531         kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt);
6532 }
6533
6534 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6535 {
6536         kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt);
6537 }
6538
6539 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6540 {
6541         kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt);
6542 }
6543
6544 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6545 {
6546         kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt);
6547 }
6548
6549 static unsigned long emulator_get_cached_segment_base(
6550         struct x86_emulate_ctxt *ctxt, int seg)
6551 {
6552         return get_segment_base(emul_to_vcpu(ctxt), seg);
6553 }
6554
6555 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6556                                  struct desc_struct *desc, u32 *base3,
6557                                  int seg)
6558 {
6559         struct kvm_segment var;
6560
6561         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6562         *selector = var.selector;
6563
6564         if (var.unusable) {
6565                 memset(desc, 0, sizeof(*desc));
6566                 if (base3)
6567                         *base3 = 0;
6568                 return false;
6569         }
6570
6571         if (var.g)
6572                 var.limit >>= 12;
6573         set_desc_limit(desc, var.limit);
6574         set_desc_base(desc, (unsigned long)var.base);
6575 #ifdef CONFIG_X86_64
6576         if (base3)
6577                 *base3 = var.base >> 32;
6578 #endif
6579         desc->type = var.type;
6580         desc->s = var.s;
6581         desc->dpl = var.dpl;
6582         desc->p = var.present;
6583         desc->avl = var.avl;
6584         desc->l = var.l;
6585         desc->d = var.db;
6586         desc->g = var.g;
6587
6588         return true;
6589 }
6590
6591 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6592                                  struct desc_struct *desc, u32 base3,
6593                                  int seg)
6594 {
6595         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6596         struct kvm_segment var;
6597
6598         var.selector = selector;
6599         var.base = get_desc_base(desc);
6600 #ifdef CONFIG_X86_64
6601         var.base |= ((u64)base3) << 32;
6602 #endif
6603         var.limit = get_desc_limit(desc);
6604         if (desc->g)
6605                 var.limit = (var.limit << 12) | 0xfff;
6606         var.type = desc->type;
6607         var.dpl = desc->dpl;
6608         var.db = desc->d;
6609         var.s = desc->s;
6610         var.l = desc->l;
6611         var.g = desc->g;
6612         var.avl = desc->avl;
6613         var.present = desc->p;
6614         var.unusable = !var.present;
6615         var.padding = 0;
6616
6617         kvm_set_segment(vcpu, &var, seg);
6618         return;
6619 }
6620
6621 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6622                             u32 msr_index, u64 *pdata)
6623 {
6624         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6625         int r;
6626
6627         r = kvm_get_msr(vcpu, msr_index, pdata);
6628
6629         if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) {
6630                 /* Bounce to user space */
6631                 return X86EMUL_IO_NEEDED;
6632         }
6633
6634         return r;
6635 }
6636
6637 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6638                             u32 msr_index, u64 data)
6639 {
6640         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6641         int r;
6642
6643         r = kvm_set_msr(vcpu, msr_index, data);
6644
6645         if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) {
6646                 /* Bounce to user space */
6647                 return X86EMUL_IO_NEEDED;
6648         }
6649
6650         return r;
6651 }
6652
6653 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6654 {
6655         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6656
6657         return vcpu->arch.smbase;
6658 }
6659
6660 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6661 {
6662         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6663
6664         vcpu->arch.smbase = smbase;
6665 }
6666
6667 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6668                               u32 pmc)
6669 {
6670         return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6671 }
6672
6673 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6674                              u32 pmc, u64 *pdata)
6675 {
6676         return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6677 }
6678
6679 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6680 {
6681         emul_to_vcpu(ctxt)->arch.halt_request = 1;
6682 }
6683
6684 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6685                               struct x86_instruction_info *info,
6686                               enum x86_intercept_stage stage)
6687 {
6688         return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage,
6689                                             &ctxt->exception);
6690 }
6691
6692 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6693                               u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6694                               bool exact_only)
6695 {
6696         return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6697 }
6698
6699 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6700 {
6701         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6702 }
6703
6704 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6705 {
6706         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6707 }
6708
6709 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6710 {
6711         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6712 }
6713
6714 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6715 {
6716         return kvm_register_read(emul_to_vcpu(ctxt), reg);
6717 }
6718
6719 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6720 {
6721         kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6722 }
6723
6724 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6725 {
6726         kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked);
6727 }
6728
6729 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6730 {
6731         return emul_to_vcpu(ctxt)->arch.hflags;
6732 }
6733
6734 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6735 {
6736         emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6737 }
6738
6739 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6740                                   const char *smstate)
6741 {
6742         return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6743 }
6744
6745 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6746 {
6747         kvm_smm_changed(emul_to_vcpu(ctxt));
6748 }
6749
6750 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6751 {
6752         return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6753 }
6754
6755 static const struct x86_emulate_ops emulate_ops = {
6756         .read_gpr            = emulator_read_gpr,
6757         .write_gpr           = emulator_write_gpr,
6758         .read_std            = emulator_read_std,
6759         .write_std           = emulator_write_std,
6760         .read_phys           = kvm_read_guest_phys_system,
6761         .fetch               = kvm_fetch_guest_virt,
6762         .read_emulated       = emulator_read_emulated,
6763         .write_emulated      = emulator_write_emulated,
6764         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
6765         .invlpg              = emulator_invlpg,
6766         .pio_in_emulated     = emulator_pio_in_emulated,
6767         .pio_out_emulated    = emulator_pio_out_emulated,
6768         .get_segment         = emulator_get_segment,
6769         .set_segment         = emulator_set_segment,
6770         .get_cached_segment_base = emulator_get_cached_segment_base,
6771         .get_gdt             = emulator_get_gdt,
6772         .get_idt             = emulator_get_idt,
6773         .set_gdt             = emulator_set_gdt,
6774         .set_idt             = emulator_set_idt,
6775         .get_cr              = emulator_get_cr,
6776         .set_cr              = emulator_set_cr,
6777         .cpl                 = emulator_get_cpl,
6778         .get_dr              = emulator_get_dr,
6779         .set_dr              = emulator_set_dr,
6780         .get_smbase          = emulator_get_smbase,
6781         .set_smbase          = emulator_set_smbase,
6782         .set_msr             = emulator_set_msr,
6783         .get_msr             = emulator_get_msr,
6784         .check_pmc           = emulator_check_pmc,
6785         .read_pmc            = emulator_read_pmc,
6786         .halt                = emulator_halt,
6787         .wbinvd              = emulator_wbinvd,
6788         .fix_hypercall       = emulator_fix_hypercall,
6789         .intercept           = emulator_intercept,
6790         .get_cpuid           = emulator_get_cpuid,
6791         .guest_has_long_mode = emulator_guest_has_long_mode,
6792         .guest_has_movbe     = emulator_guest_has_movbe,
6793         .guest_has_fxsr      = emulator_guest_has_fxsr,
6794         .set_nmi_mask        = emulator_set_nmi_mask,
6795         .get_hflags          = emulator_get_hflags,
6796         .set_hflags          = emulator_set_hflags,
6797         .pre_leave_smm       = emulator_pre_leave_smm,
6798         .post_leave_smm      = emulator_post_leave_smm,
6799         .set_xcr             = emulator_set_xcr,
6800 };
6801
6802 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6803 {
6804         u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
6805         /*
6806          * an sti; sti; sequence only disable interrupts for the first
6807          * instruction. So, if the last instruction, be it emulated or
6808          * not, left the system with the INT_STI flag enabled, it
6809          * means that the last instruction is an sti. We should not
6810          * leave the flag on in this case. The same goes for mov ss
6811          */
6812         if (int_shadow & mask)
6813                 mask = 0;
6814         if (unlikely(int_shadow || mask)) {
6815                 kvm_x86_ops.set_interrupt_shadow(vcpu, mask);
6816                 if (!mask)
6817                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6818         }
6819 }
6820
6821 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6822 {
6823         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6824         if (ctxt->exception.vector == PF_VECTOR)
6825                 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
6826
6827         if (ctxt->exception.error_code_valid)
6828                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6829                                       ctxt->exception.error_code);
6830         else
6831                 kvm_queue_exception(vcpu, ctxt->exception.vector);
6832         return false;
6833 }
6834
6835 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6836 {
6837         struct x86_emulate_ctxt *ctxt;
6838
6839         ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6840         if (!ctxt) {
6841                 pr_err("kvm: failed to allocate vcpu's emulator\n");
6842                 return NULL;
6843         }
6844
6845         ctxt->vcpu = vcpu;
6846         ctxt->ops = &emulate_ops;
6847         vcpu->arch.emulate_ctxt = ctxt;
6848
6849         return ctxt;
6850 }
6851
6852 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6853 {
6854         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6855         int cs_db, cs_l;
6856
6857         kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6858
6859         ctxt->gpa_available = false;
6860         ctxt->eflags = kvm_get_rflags(vcpu);
6861         ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6862
6863         ctxt->eip = kvm_rip_read(vcpu);
6864         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
6865                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
6866                      (cs_l && is_long_mode(vcpu))       ? X86EMUL_MODE_PROT64 :
6867                      cs_db                              ? X86EMUL_MODE_PROT32 :
6868                                                           X86EMUL_MODE_PROT16;
6869         BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6870         BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6871         BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6872
6873         init_decode_cache(ctxt);
6874         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6875 }
6876
6877 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6878 {
6879         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6880         int ret;
6881
6882         init_emulate_ctxt(vcpu);
6883
6884         ctxt->op_bytes = 2;
6885         ctxt->ad_bytes = 2;
6886         ctxt->_eip = ctxt->eip + inc_eip;
6887         ret = emulate_int_real(ctxt, irq);
6888
6889         if (ret != X86EMUL_CONTINUE) {
6890                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6891         } else {
6892                 ctxt->eip = ctxt->_eip;
6893                 kvm_rip_write(vcpu, ctxt->eip);
6894                 kvm_set_rflags(vcpu, ctxt->eflags);
6895         }
6896 }
6897 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6898
6899 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6900 {
6901         ++vcpu->stat.insn_emulation_fail;
6902         trace_kvm_emulate_insn_failed(vcpu);
6903
6904         if (emulation_type & EMULTYPE_VMWARE_GP) {
6905                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6906                 return 1;
6907         }
6908
6909         if (emulation_type & EMULTYPE_SKIP) {
6910                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6911                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6912                 vcpu->run->internal.ndata = 0;
6913                 return 0;
6914         }
6915
6916         kvm_queue_exception(vcpu, UD_VECTOR);
6917
6918         if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) {
6919                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6920                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6921                 vcpu->run->internal.ndata = 0;
6922                 return 0;
6923         }
6924
6925         return 1;
6926 }
6927
6928 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6929                                   bool write_fault_to_shadow_pgtable,
6930                                   int emulation_type)
6931 {
6932         gpa_t gpa = cr2_or_gpa;
6933         kvm_pfn_t pfn;
6934
6935         if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6936                 return false;
6937
6938         if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6939             WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6940                 return false;
6941
6942         if (!vcpu->arch.mmu->direct_map) {
6943                 /*
6944                  * Write permission should be allowed since only
6945                  * write access need to be emulated.
6946                  */
6947                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6948
6949                 /*
6950                  * If the mapping is invalid in guest, let cpu retry
6951                  * it to generate fault.
6952                  */
6953                 if (gpa == UNMAPPED_GVA)
6954                         return true;
6955         }
6956
6957         /*
6958          * Do not retry the unhandleable instruction if it faults on the
6959          * readonly host memory, otherwise it will goto a infinite loop:
6960          * retry instruction -> write #PF -> emulation fail -> retry
6961          * instruction -> ...
6962          */
6963         pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6964
6965         /*
6966          * If the instruction failed on the error pfn, it can not be fixed,
6967          * report the error to userspace.
6968          */
6969         if (is_error_noslot_pfn(pfn))
6970                 return false;
6971
6972         kvm_release_pfn_clean(pfn);
6973
6974         /* The instructions are well-emulated on direct mmu. */
6975         if (vcpu->arch.mmu->direct_map) {
6976                 unsigned int indirect_shadow_pages;
6977
6978                 spin_lock(&vcpu->kvm->mmu_lock);
6979                 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6980                 spin_unlock(&vcpu->kvm->mmu_lock);
6981
6982                 if (indirect_shadow_pages)
6983                         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6984
6985                 return true;
6986         }
6987
6988         /*
6989          * if emulation was due to access to shadowed page table
6990          * and it failed try to unshadow page and re-enter the
6991          * guest to let CPU execute the instruction.
6992          */
6993         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6994
6995         /*
6996          * If the access faults on its page table, it can not
6997          * be fixed by unprotecting shadow page and it should
6998          * be reported to userspace.
6999          */
7000         return !write_fault_to_shadow_pgtable;
7001 }
7002
7003 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
7004                               gpa_t cr2_or_gpa,  int emulation_type)
7005 {
7006         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7007         unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
7008
7009         last_retry_eip = vcpu->arch.last_retry_eip;
7010         last_retry_addr = vcpu->arch.last_retry_addr;
7011
7012         /*
7013          * If the emulation is caused by #PF and it is non-page_table
7014          * writing instruction, it means the VM-EXIT is caused by shadow
7015          * page protected, we can zap the shadow page and retry this
7016          * instruction directly.
7017          *
7018          * Note: if the guest uses a non-page-table modifying instruction
7019          * on the PDE that points to the instruction, then we will unmap
7020          * the instruction and go to an infinite loop. So, we cache the
7021          * last retried eip and the last fault address, if we meet the eip
7022          * and the address again, we can break out of the potential infinite
7023          * loop.
7024          */
7025         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
7026
7027         if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7028                 return false;
7029
7030         if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7031             WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7032                 return false;
7033
7034         if (x86_page_table_writing_insn(ctxt))
7035                 return false;
7036
7037         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
7038                 return false;
7039
7040         vcpu->arch.last_retry_eip = ctxt->eip;
7041         vcpu->arch.last_retry_addr = cr2_or_gpa;
7042
7043         if (!vcpu->arch.mmu->direct_map)
7044                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7045
7046         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7047
7048         return true;
7049 }
7050
7051 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
7052 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
7053
7054 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
7055 {
7056         if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
7057                 /* This is a good place to trace that we are exiting SMM.  */
7058                 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
7059
7060                 /* Process a latched INIT or SMI, if any.  */
7061                 kvm_make_request(KVM_REQ_EVENT, vcpu);
7062         }
7063
7064         kvm_mmu_reset_context(vcpu);
7065 }
7066
7067 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
7068                                 unsigned long *db)
7069 {
7070         u32 dr6 = 0;
7071         int i;
7072         u32 enable, rwlen;
7073
7074         enable = dr7;
7075         rwlen = dr7 >> 16;
7076         for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
7077                 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
7078                         dr6 |= (1 << i);
7079         return dr6;
7080 }
7081
7082 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
7083 {
7084         struct kvm_run *kvm_run = vcpu->run;
7085
7086         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
7087                 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
7088                 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
7089                 kvm_run->debug.arch.exception = DB_VECTOR;
7090                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7091                 return 0;
7092         }
7093         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
7094         return 1;
7095 }
7096
7097 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
7098 {
7099         unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7100         int r;
7101
7102         r = kvm_x86_ops.skip_emulated_instruction(vcpu);
7103         if (unlikely(!r))
7104                 return 0;
7105
7106         /*
7107          * rflags is the old, "raw" value of the flags.  The new value has
7108          * not been saved yet.
7109          *
7110          * This is correct even for TF set by the guest, because "the
7111          * processor will not generate this exception after the instruction
7112          * that sets the TF flag".
7113          */
7114         if (unlikely(rflags & X86_EFLAGS_TF))
7115                 r = kvm_vcpu_do_singlestep(vcpu);
7116         return r;
7117 }
7118 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
7119
7120 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
7121 {
7122         if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
7123             (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
7124                 struct kvm_run *kvm_run = vcpu->run;
7125                 unsigned long eip = kvm_get_linear_rip(vcpu);
7126                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7127                                            vcpu->arch.guest_debug_dr7,
7128                                            vcpu->arch.eff_db);
7129
7130                 if (dr6 != 0) {
7131                         kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
7132                         kvm_run->debug.arch.pc = eip;
7133                         kvm_run->debug.arch.exception = DB_VECTOR;
7134                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
7135                         *r = 0;
7136                         return true;
7137                 }
7138         }
7139
7140         if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
7141             !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
7142                 unsigned long eip = kvm_get_linear_rip(vcpu);
7143                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7144                                            vcpu->arch.dr7,
7145                                            vcpu->arch.db);
7146
7147                 if (dr6 != 0) {
7148                         kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
7149                         *r = 1;
7150                         return true;
7151                 }
7152         }
7153
7154         return false;
7155 }
7156
7157 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
7158 {
7159         switch (ctxt->opcode_len) {
7160         case 1:
7161                 switch (ctxt->b) {
7162                 case 0xe4:      /* IN */
7163                 case 0xe5:
7164                 case 0xec:
7165                 case 0xed:
7166                 case 0xe6:      /* OUT */
7167                 case 0xe7:
7168                 case 0xee:
7169                 case 0xef:
7170                 case 0x6c:      /* INS */
7171                 case 0x6d:
7172                 case 0x6e:      /* OUTS */
7173                 case 0x6f:
7174                         return true;
7175                 }
7176                 break;
7177         case 2:
7178                 switch (ctxt->b) {
7179                 case 0x33:      /* RDPMC */
7180                         return true;
7181                 }
7182                 break;
7183         }
7184
7185         return false;
7186 }
7187
7188 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7189                             int emulation_type, void *insn, int insn_len)
7190 {
7191         int r;
7192         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7193         bool writeback = true;
7194         bool write_fault_to_spt;
7195
7196         if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, insn, insn_len)))
7197                 return 1;
7198
7199         vcpu->arch.l1tf_flush_l1d = true;
7200
7201         /*
7202          * Clear write_fault_to_shadow_pgtable here to ensure it is
7203          * never reused.
7204          */
7205         write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
7206         vcpu->arch.write_fault_to_shadow_pgtable = false;
7207         kvm_clear_exception_queue(vcpu);
7208
7209         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
7210                 init_emulate_ctxt(vcpu);
7211
7212                 /*
7213                  * We will reenter on the same instruction since
7214                  * we do not set complete_userspace_io.  This does not
7215                  * handle watchpoints yet, those would be handled in
7216                  * the emulate_ops.
7217                  */
7218                 if (!(emulation_type & EMULTYPE_SKIP) &&
7219                     kvm_vcpu_check_breakpoint(vcpu, &r))
7220                         return r;
7221
7222                 ctxt->interruptibility = 0;
7223                 ctxt->have_exception = false;
7224                 ctxt->exception.vector = -1;
7225                 ctxt->perm_ok = false;
7226
7227                 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
7228
7229                 r = x86_decode_insn(ctxt, insn, insn_len);
7230
7231                 trace_kvm_emulate_insn_start(vcpu);
7232                 ++vcpu->stat.insn_emulation;
7233                 if (r != EMULATION_OK)  {
7234                         if ((emulation_type & EMULTYPE_TRAP_UD) ||
7235                             (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
7236                                 kvm_queue_exception(vcpu, UD_VECTOR);
7237                                 return 1;
7238                         }
7239                         if (reexecute_instruction(vcpu, cr2_or_gpa,
7240                                                   write_fault_to_spt,
7241                                                   emulation_type))
7242                                 return 1;
7243                         if (ctxt->have_exception) {
7244                                 /*
7245                                  * #UD should result in just EMULATION_FAILED, and trap-like
7246                                  * exception should not be encountered during decode.
7247                                  */
7248                                 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
7249                                              exception_type(ctxt->exception.vector) == EXCPT_TRAP);
7250                                 inject_emulated_exception(vcpu);
7251                                 return 1;
7252                         }
7253                         return handle_emulation_failure(vcpu, emulation_type);
7254                 }
7255         }
7256
7257         if ((emulation_type & EMULTYPE_VMWARE_GP) &&
7258             !is_vmware_backdoor_opcode(ctxt)) {
7259                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7260                 return 1;
7261         }
7262
7263         /*
7264          * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
7265          * for kvm_skip_emulated_instruction().  The caller is responsible for
7266          * updating interruptibility state and injecting single-step #DBs.
7267          */
7268         if (emulation_type & EMULTYPE_SKIP) {
7269                 kvm_rip_write(vcpu, ctxt->_eip);
7270                 if (ctxt->eflags & X86_EFLAGS_RF)
7271                         kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
7272                 return 1;
7273         }
7274
7275         if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
7276                 return 1;
7277
7278         /* this is needed for vmware backdoor interface to work since it
7279            changes registers values  during IO operation */
7280         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
7281                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7282                 emulator_invalidate_register_cache(ctxt);
7283         }
7284
7285 restart:
7286         if (emulation_type & EMULTYPE_PF) {
7287                 /* Save the faulting GPA (cr2) in the address field */
7288                 ctxt->exception.address = cr2_or_gpa;
7289
7290                 /* With shadow page tables, cr2 contains a GVA or nGPA. */
7291                 if (vcpu->arch.mmu->direct_map) {
7292                         ctxt->gpa_available = true;
7293                         ctxt->gpa_val = cr2_or_gpa;
7294                 }
7295         } else {
7296                 /* Sanitize the address out of an abundance of paranoia. */
7297                 ctxt->exception.address = 0;
7298         }
7299
7300         r = x86_emulate_insn(ctxt);
7301
7302         if (r == EMULATION_INTERCEPTED)
7303                 return 1;
7304
7305         if (r == EMULATION_FAILED) {
7306                 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
7307                                         emulation_type))
7308                         return 1;
7309
7310                 return handle_emulation_failure(vcpu, emulation_type);
7311         }
7312
7313         if (ctxt->have_exception) {
7314                 r = 1;
7315                 if (inject_emulated_exception(vcpu))
7316                         return r;
7317         } else if (vcpu->arch.pio.count) {
7318                 if (!vcpu->arch.pio.in) {
7319                         /* FIXME: return into emulator if single-stepping.  */
7320                         vcpu->arch.pio.count = 0;
7321                 } else {
7322                         writeback = false;
7323                         vcpu->arch.complete_userspace_io = complete_emulated_pio;
7324                 }
7325                 r = 0;
7326         } else if (vcpu->mmio_needed) {
7327                 ++vcpu->stat.mmio_exits;
7328
7329                 if (!vcpu->mmio_is_write)
7330                         writeback = false;
7331                 r = 0;
7332                 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7333         } else if (r == EMULATION_RESTART)
7334                 goto restart;
7335         else
7336                 r = 1;
7337
7338         if (writeback) {
7339                 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7340                 toggle_interruptibility(vcpu, ctxt->interruptibility);
7341                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7342                 if (!ctxt->have_exception ||
7343                     exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
7344                         kvm_rip_write(vcpu, ctxt->eip);
7345                         if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
7346                                 r = kvm_vcpu_do_singlestep(vcpu);
7347                         if (kvm_x86_ops.update_emulated_instruction)
7348                                 kvm_x86_ops.update_emulated_instruction(vcpu);
7349                         __kvm_set_rflags(vcpu, ctxt->eflags);
7350                 }
7351
7352                 /*
7353                  * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
7354                  * do nothing, and it will be requested again as soon as
7355                  * the shadow expires.  But we still need to check here,
7356                  * because POPF has no interrupt shadow.
7357                  */
7358                 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
7359                         kvm_make_request(KVM_REQ_EVENT, vcpu);
7360         } else
7361                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
7362
7363         return r;
7364 }
7365
7366 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
7367 {
7368         return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
7369 }
7370 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
7371
7372 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
7373                                         void *insn, int insn_len)
7374 {
7375         return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
7376 }
7377 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
7378
7379 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
7380 {
7381         vcpu->arch.pio.count = 0;
7382         return 1;
7383 }
7384
7385 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
7386 {
7387         vcpu->arch.pio.count = 0;
7388
7389         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
7390                 return 1;
7391
7392         return kvm_skip_emulated_instruction(vcpu);
7393 }
7394
7395 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
7396                             unsigned short port)
7397 {
7398         unsigned long val = kvm_rax_read(vcpu);
7399         int ret = emulator_pio_out(vcpu, size, port, &val, 1);
7400
7401         if (ret)
7402                 return ret;
7403
7404         /*
7405          * Workaround userspace that relies on old KVM behavior of %rip being
7406          * incremented prior to exiting to userspace to handle "OUT 0x7e".
7407          */
7408         if (port == 0x7e &&
7409             kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
7410                 vcpu->arch.complete_userspace_io =
7411                         complete_fast_pio_out_port_0x7e;
7412                 kvm_skip_emulated_instruction(vcpu);
7413         } else {
7414                 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7415                 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
7416         }
7417         return 0;
7418 }
7419
7420 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
7421 {
7422         unsigned long val;
7423
7424         /* We should only ever be called with arch.pio.count equal to 1 */
7425         BUG_ON(vcpu->arch.pio.count != 1);
7426
7427         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
7428                 vcpu->arch.pio.count = 0;
7429                 return 1;
7430         }
7431
7432         /* For size less than 4 we merge, else we zero extend */
7433         val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7434
7435         /*
7436          * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7437          * the copy and tracing
7438          */
7439         emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7440         kvm_rax_write(vcpu, val);
7441
7442         return kvm_skip_emulated_instruction(vcpu);
7443 }
7444
7445 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7446                            unsigned short port)
7447 {
7448         unsigned long val;
7449         int ret;
7450
7451         /* For size less than 4 we merge, else we zero extend */
7452         val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7453
7454         ret = emulator_pio_in(vcpu, size, port, &val, 1);
7455         if (ret) {
7456                 kvm_rax_write(vcpu, val);
7457                 return ret;
7458         }
7459
7460         vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7461         vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7462
7463         return 0;
7464 }
7465
7466 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7467 {
7468         int ret;
7469
7470         if (in)
7471                 ret = kvm_fast_pio_in(vcpu, size, port);
7472         else
7473                 ret = kvm_fast_pio_out(vcpu, size, port);
7474         return ret && kvm_skip_emulated_instruction(vcpu);
7475 }
7476 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7477
7478 static int kvmclock_cpu_down_prep(unsigned int cpu)
7479 {
7480         __this_cpu_write(cpu_tsc_khz, 0);
7481         return 0;
7482 }
7483
7484 static void tsc_khz_changed(void *data)
7485 {
7486         struct cpufreq_freqs *freq = data;
7487         unsigned long khz = 0;
7488
7489         if (data)
7490                 khz = freq->new;
7491         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7492                 khz = cpufreq_quick_get(raw_smp_processor_id());
7493         if (!khz)
7494                 khz = tsc_khz;
7495         __this_cpu_write(cpu_tsc_khz, khz);
7496 }
7497
7498 #ifdef CONFIG_X86_64
7499 static void kvm_hyperv_tsc_notifier(void)
7500 {
7501         struct kvm *kvm;
7502         struct kvm_vcpu *vcpu;
7503         int cpu;
7504
7505         mutex_lock(&kvm_lock);
7506         list_for_each_entry(kvm, &vm_list, vm_list)
7507                 kvm_make_mclock_inprogress_request(kvm);
7508
7509         hyperv_stop_tsc_emulation();
7510
7511         /* TSC frequency always matches when on Hyper-V */
7512         for_each_present_cpu(cpu)
7513                 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7514         kvm_max_guest_tsc_khz = tsc_khz;
7515
7516         list_for_each_entry(kvm, &vm_list, vm_list) {
7517                 struct kvm_arch *ka = &kvm->arch;
7518
7519                 spin_lock(&ka->pvclock_gtod_sync_lock);
7520
7521                 pvclock_update_vm_gtod_copy(kvm);
7522
7523                 kvm_for_each_vcpu(cpu, vcpu, kvm)
7524                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7525
7526                 kvm_for_each_vcpu(cpu, vcpu, kvm)
7527                         kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7528
7529                 spin_unlock(&ka->pvclock_gtod_sync_lock);
7530         }
7531         mutex_unlock(&kvm_lock);
7532 }
7533 #endif
7534
7535 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7536 {
7537         struct kvm *kvm;
7538         struct kvm_vcpu *vcpu;
7539         int i, send_ipi = 0;
7540
7541         /*
7542          * We allow guests to temporarily run on slowing clocks,
7543          * provided we notify them after, or to run on accelerating
7544          * clocks, provided we notify them before.  Thus time never
7545          * goes backwards.
7546          *
7547          * However, we have a problem.  We can't atomically update
7548          * the frequency of a given CPU from this function; it is
7549          * merely a notifier, which can be called from any CPU.
7550          * Changing the TSC frequency at arbitrary points in time
7551          * requires a recomputation of local variables related to
7552          * the TSC for each VCPU.  We must flag these local variables
7553          * to be updated and be sure the update takes place with the
7554          * new frequency before any guests proceed.
7555          *
7556          * Unfortunately, the combination of hotplug CPU and frequency
7557          * change creates an intractable locking scenario; the order
7558          * of when these callouts happen is undefined with respect to
7559          * CPU hotplug, and they can race with each other.  As such,
7560          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7561          * undefined; you can actually have a CPU frequency change take
7562          * place in between the computation of X and the setting of the
7563          * variable.  To protect against this problem, all updates of
7564          * the per_cpu tsc_khz variable are done in an interrupt
7565          * protected IPI, and all callers wishing to update the value
7566          * must wait for a synchronous IPI to complete (which is trivial
7567          * if the caller is on the CPU already).  This establishes the
7568          * necessary total order on variable updates.
7569          *
7570          * Note that because a guest time update may take place
7571          * anytime after the setting of the VCPU's request bit, the
7572          * correct TSC value must be set before the request.  However,
7573          * to ensure the update actually makes it to any guest which
7574          * starts running in hardware virtualization between the set
7575          * and the acquisition of the spinlock, we must also ping the
7576          * CPU after setting the request bit.
7577          *
7578          */
7579
7580         smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7581
7582         mutex_lock(&kvm_lock);
7583         list_for_each_entry(kvm, &vm_list, vm_list) {
7584                 kvm_for_each_vcpu(i, vcpu, kvm) {
7585                         if (vcpu->cpu != cpu)
7586                                 continue;
7587                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7588                         if (vcpu->cpu != raw_smp_processor_id())
7589                                 send_ipi = 1;
7590                 }
7591         }
7592         mutex_unlock(&kvm_lock);
7593
7594         if (freq->old < freq->new && send_ipi) {
7595                 /*
7596                  * We upscale the frequency.  Must make the guest
7597                  * doesn't see old kvmclock values while running with
7598                  * the new frequency, otherwise we risk the guest sees
7599                  * time go backwards.
7600                  *
7601                  * In case we update the frequency for another cpu
7602                  * (which might be in guest context) send an interrupt
7603                  * to kick the cpu out of guest context.  Next time
7604                  * guest context is entered kvmclock will be updated,
7605                  * so the guest will not see stale values.
7606                  */
7607                 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7608         }
7609 }
7610
7611 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7612                                      void *data)
7613 {
7614         struct cpufreq_freqs *freq = data;
7615         int cpu;
7616
7617         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7618                 return 0;
7619         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7620                 return 0;
7621
7622         for_each_cpu(cpu, freq->policy->cpus)
7623                 __kvmclock_cpufreq_notifier(freq, cpu);
7624
7625         return 0;
7626 }
7627
7628 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7629         .notifier_call  = kvmclock_cpufreq_notifier
7630 };
7631
7632 static int kvmclock_cpu_online(unsigned int cpu)
7633 {
7634         tsc_khz_changed(NULL);
7635         return 0;
7636 }
7637
7638 static void kvm_timer_init(void)
7639 {
7640         max_tsc_khz = tsc_khz;
7641
7642         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7643 #ifdef CONFIG_CPU_FREQ
7644                 struct cpufreq_policy *policy;
7645                 int cpu;
7646
7647                 cpu = get_cpu();
7648                 policy = cpufreq_cpu_get(cpu);
7649                 if (policy) {
7650                         if (policy->cpuinfo.max_freq)
7651                                 max_tsc_khz = policy->cpuinfo.max_freq;
7652                         cpufreq_cpu_put(policy);
7653                 }
7654                 put_cpu();
7655 #endif
7656                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7657                                           CPUFREQ_TRANSITION_NOTIFIER);
7658         }
7659
7660         cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7661                           kvmclock_cpu_online, kvmclock_cpu_down_prep);
7662 }
7663
7664 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7665 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7666
7667 int kvm_is_in_guest(void)
7668 {
7669         return __this_cpu_read(current_vcpu) != NULL;
7670 }
7671
7672 static int kvm_is_user_mode(void)
7673 {
7674         int user_mode = 3;
7675
7676         if (__this_cpu_read(current_vcpu))
7677                 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu));
7678
7679         return user_mode != 0;
7680 }
7681
7682 static unsigned long kvm_get_guest_ip(void)
7683 {
7684         unsigned long ip = 0;
7685
7686         if (__this_cpu_read(current_vcpu))
7687                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7688
7689         return ip;
7690 }
7691
7692 static void kvm_handle_intel_pt_intr(void)
7693 {
7694         struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7695
7696         kvm_make_request(KVM_REQ_PMI, vcpu);
7697         __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7698                         (unsigned long *)&vcpu->arch.pmu.global_status);
7699 }
7700
7701 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7702         .is_in_guest            = kvm_is_in_guest,
7703         .is_user_mode           = kvm_is_user_mode,
7704         .get_guest_ip           = kvm_get_guest_ip,
7705         .handle_intel_pt_intr   = kvm_handle_intel_pt_intr,
7706 };
7707
7708 #ifdef CONFIG_X86_64
7709 static void pvclock_gtod_update_fn(struct work_struct *work)
7710 {
7711         struct kvm *kvm;
7712
7713         struct kvm_vcpu *vcpu;
7714         int i;
7715
7716         mutex_lock(&kvm_lock);
7717         list_for_each_entry(kvm, &vm_list, vm_list)
7718                 kvm_for_each_vcpu(i, vcpu, kvm)
7719                         kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7720         atomic_set(&kvm_guest_has_master_clock, 0);
7721         mutex_unlock(&kvm_lock);
7722 }
7723
7724 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7725
7726 /*
7727  * Notification about pvclock gtod data update.
7728  */
7729 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7730                                void *priv)
7731 {
7732         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7733         struct timekeeper *tk = priv;
7734
7735         update_pvclock_gtod(tk);
7736
7737         /* disable master clock if host does not trust, or does not
7738          * use, TSC based clocksource.
7739          */
7740         if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7741             atomic_read(&kvm_guest_has_master_clock) != 0)
7742                 queue_work(system_long_wq, &pvclock_gtod_work);
7743
7744         return 0;
7745 }
7746
7747 static struct notifier_block pvclock_gtod_notifier = {
7748         .notifier_call = pvclock_gtod_notify,
7749 };
7750 #endif
7751
7752 int kvm_arch_init(void *opaque)
7753 {
7754         struct kvm_x86_init_ops *ops = opaque;
7755         int r;
7756
7757         if (kvm_x86_ops.hardware_enable) {
7758                 printk(KERN_ERR "kvm: already loaded the other module\n");
7759                 r = -EEXIST;
7760                 goto out;
7761         }
7762
7763         if (!ops->cpu_has_kvm_support()) {
7764                 pr_err_ratelimited("kvm: no hardware support\n");
7765                 r = -EOPNOTSUPP;
7766                 goto out;
7767         }
7768         if (ops->disabled_by_bios()) {
7769                 pr_err_ratelimited("kvm: disabled by bios\n");
7770                 r = -EOPNOTSUPP;
7771                 goto out;
7772         }
7773
7774         /*
7775          * KVM explicitly assumes that the guest has an FPU and
7776          * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7777          * vCPU's FPU state as a fxregs_state struct.
7778          */
7779         if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7780                 printk(KERN_ERR "kvm: inadequate fpu\n");
7781                 r = -EOPNOTSUPP;
7782                 goto out;
7783         }
7784
7785         r = -ENOMEM;
7786         x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7787                                           __alignof__(struct fpu), SLAB_ACCOUNT,
7788                                           NULL);
7789         if (!x86_fpu_cache) {
7790                 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7791                 goto out;
7792         }
7793
7794         x86_emulator_cache = kvm_alloc_emulator_cache();
7795         if (!x86_emulator_cache) {
7796                 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7797                 goto out_free_x86_fpu_cache;
7798         }
7799
7800         user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
7801         if (!user_return_msrs) {
7802                 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
7803                 goto out_free_x86_emulator_cache;
7804         }
7805
7806         r = kvm_mmu_module_init();
7807         if (r)
7808                 goto out_free_percpu;
7809
7810         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7811                         PT_DIRTY_MASK, PT64_NX_MASK, 0,
7812                         PT_PRESENT_MASK, 0, sme_me_mask);
7813         kvm_timer_init();
7814
7815         perf_register_guest_info_callbacks(&kvm_guest_cbs);
7816
7817         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7818                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7819                 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7820         }
7821
7822         kvm_lapic_init();
7823         if (pi_inject_timer == -1)
7824                 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7825 #ifdef CONFIG_X86_64
7826         pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7827
7828         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7829                 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7830 #endif
7831
7832         return 0;
7833
7834 out_free_percpu:
7835         free_percpu(user_return_msrs);
7836 out_free_x86_emulator_cache:
7837         kmem_cache_destroy(x86_emulator_cache);
7838 out_free_x86_fpu_cache:
7839         kmem_cache_destroy(x86_fpu_cache);
7840 out:
7841         return r;
7842 }
7843
7844 void kvm_arch_exit(void)
7845 {
7846 #ifdef CONFIG_X86_64
7847         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7848                 clear_hv_tscchange_cb();
7849 #endif
7850         kvm_lapic_exit();
7851         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7852
7853         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7854                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7855                                             CPUFREQ_TRANSITION_NOTIFIER);
7856         cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7857 #ifdef CONFIG_X86_64
7858         pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7859 #endif
7860         kvm_x86_ops.hardware_enable = NULL;
7861         kvm_mmu_module_exit();
7862         free_percpu(user_return_msrs);
7863         kmem_cache_destroy(x86_fpu_cache);
7864 }
7865
7866 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7867 {
7868         ++vcpu->stat.halt_exits;
7869         if (lapic_in_kernel(vcpu)) {
7870                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7871                 return 1;
7872         } else {
7873                 vcpu->run->exit_reason = KVM_EXIT_HLT;
7874                 return 0;
7875         }
7876 }
7877 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7878
7879 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7880 {
7881         int ret = kvm_skip_emulated_instruction(vcpu);
7882         /*
7883          * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7884          * KVM_EXIT_DEBUG here.
7885          */
7886         return kvm_vcpu_halt(vcpu) && ret;
7887 }
7888 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7889
7890 #ifdef CONFIG_X86_64
7891 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7892                                 unsigned long clock_type)
7893 {
7894         struct kvm_clock_pairing clock_pairing;
7895         struct timespec64 ts;
7896         u64 cycle;
7897         int ret;
7898
7899         if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7900                 return -KVM_EOPNOTSUPP;
7901
7902         if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7903                 return -KVM_EOPNOTSUPP;
7904
7905         clock_pairing.sec = ts.tv_sec;
7906         clock_pairing.nsec = ts.tv_nsec;
7907         clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7908         clock_pairing.flags = 0;
7909         memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7910
7911         ret = 0;
7912         if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7913                             sizeof(struct kvm_clock_pairing)))
7914                 ret = -KVM_EFAULT;
7915
7916         return ret;
7917 }
7918 #endif
7919
7920 /*
7921  * kvm_pv_kick_cpu_op:  Kick a vcpu.
7922  *
7923  * @apicid - apicid of vcpu to be kicked.
7924  */
7925 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7926 {
7927         struct kvm_lapic_irq lapic_irq;
7928
7929         lapic_irq.shorthand = APIC_DEST_NOSHORT;
7930         lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
7931         lapic_irq.level = 0;
7932         lapic_irq.dest_id = apicid;
7933         lapic_irq.msi_redir_hint = false;
7934
7935         lapic_irq.delivery_mode = APIC_DM_REMRD;
7936         kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7937 }
7938
7939 bool kvm_apicv_activated(struct kvm *kvm)
7940 {
7941         return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
7942 }
7943 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
7944
7945 void kvm_apicv_init(struct kvm *kvm, bool enable)
7946 {
7947         if (enable)
7948                 clear_bit(APICV_INHIBIT_REASON_DISABLE,
7949                           &kvm->arch.apicv_inhibit_reasons);
7950         else
7951                 set_bit(APICV_INHIBIT_REASON_DISABLE,
7952                         &kvm->arch.apicv_inhibit_reasons);
7953 }
7954 EXPORT_SYMBOL_GPL(kvm_apicv_init);
7955
7956 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7957 {
7958         struct kvm_vcpu *target = NULL;
7959         struct kvm_apic_map *map;
7960
7961         rcu_read_lock();
7962         map = rcu_dereference(kvm->arch.apic_map);
7963
7964         if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7965                 target = map->phys_map[dest_id]->vcpu;
7966
7967         rcu_read_unlock();
7968
7969         if (target && READ_ONCE(target->ready))
7970                 kvm_vcpu_yield_to(target);
7971 }
7972
7973 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7974 {
7975         unsigned long nr, a0, a1, a2, a3, ret;
7976         int op_64_bit;
7977
7978         if (kvm_hv_hypercall_enabled(vcpu->kvm))
7979                 return kvm_hv_hypercall(vcpu);
7980
7981         nr = kvm_rax_read(vcpu);
7982         a0 = kvm_rbx_read(vcpu);
7983         a1 = kvm_rcx_read(vcpu);
7984         a2 = kvm_rdx_read(vcpu);
7985         a3 = kvm_rsi_read(vcpu);
7986
7987         trace_kvm_hypercall(nr, a0, a1, a2, a3);
7988
7989         op_64_bit = is_64_bit_mode(vcpu);
7990         if (!op_64_bit) {
7991                 nr &= 0xFFFFFFFF;
7992                 a0 &= 0xFFFFFFFF;
7993                 a1 &= 0xFFFFFFFF;
7994                 a2 &= 0xFFFFFFFF;
7995                 a3 &= 0xFFFFFFFF;
7996         }
7997
7998         if (kvm_x86_ops.get_cpl(vcpu) != 0) {
7999                 ret = -KVM_EPERM;
8000                 goto out;
8001         }
8002
8003         switch (nr) {
8004         case KVM_HC_VAPIC_POLL_IRQ:
8005                 ret = 0;
8006                 break;
8007         case KVM_HC_KICK_CPU:
8008                 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
8009                 kvm_sched_yield(vcpu->kvm, a1);
8010                 ret = 0;
8011                 break;
8012 #ifdef CONFIG_X86_64
8013         case KVM_HC_CLOCK_PAIRING:
8014                 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
8015                 break;
8016 #endif
8017         case KVM_HC_SEND_IPI:
8018                 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
8019                 break;
8020         case KVM_HC_SCHED_YIELD:
8021                 kvm_sched_yield(vcpu->kvm, a0);
8022                 ret = 0;
8023                 break;
8024         default:
8025                 ret = -KVM_ENOSYS;
8026                 break;
8027         }
8028 out:
8029         if (!op_64_bit)
8030                 ret = (u32)ret;
8031         kvm_rax_write(vcpu, ret);
8032
8033         ++vcpu->stat.hypercalls;
8034         return kvm_skip_emulated_instruction(vcpu);
8035 }
8036 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
8037
8038 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8039 {
8040         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8041         char instruction[3];
8042         unsigned long rip = kvm_rip_read(vcpu);
8043
8044         kvm_x86_ops.patch_hypercall(vcpu, instruction);
8045
8046         return emulator_write_emulated(ctxt, rip, instruction, 3,
8047                 &ctxt->exception);
8048 }
8049
8050 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
8051 {
8052         return vcpu->run->request_interrupt_window &&
8053                 likely(!pic_in_kernel(vcpu->kvm));
8054 }
8055
8056 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
8057 {
8058         struct kvm_run *kvm_run = vcpu->run;
8059
8060         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
8061         kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
8062         kvm_run->cr8 = kvm_get_cr8(vcpu);
8063         kvm_run->apic_base = kvm_get_apic_base(vcpu);
8064         kvm_run->ready_for_interrupt_injection =
8065                 pic_in_kernel(vcpu->kvm) ||
8066                 kvm_vcpu_ready_for_interrupt_injection(vcpu);
8067 }
8068
8069 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
8070 {
8071         int max_irr, tpr;
8072
8073         if (!kvm_x86_ops.update_cr8_intercept)
8074                 return;
8075
8076         if (!lapic_in_kernel(vcpu))
8077                 return;
8078
8079         if (vcpu->arch.apicv_active)
8080                 return;
8081
8082         if (!vcpu->arch.apic->vapic_addr)
8083                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8084         else
8085                 max_irr = -1;
8086
8087         if (max_irr != -1)
8088                 max_irr >>= 4;
8089
8090         tpr = kvm_lapic_get_cr8(vcpu);
8091
8092         kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr);
8093 }
8094
8095 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
8096 {
8097         int r;
8098         bool can_inject = true;
8099
8100         /* try to reinject previous events if any */
8101
8102         if (vcpu->arch.exception.injected) {
8103                 kvm_x86_ops.queue_exception(vcpu);
8104                 can_inject = false;
8105         }
8106         /*
8107          * Do not inject an NMI or interrupt if there is a pending
8108          * exception.  Exceptions and interrupts are recognized at
8109          * instruction boundaries, i.e. the start of an instruction.
8110          * Trap-like exceptions, e.g. #DB, have higher priority than
8111          * NMIs and interrupts, i.e. traps are recognized before an
8112          * NMI/interrupt that's pending on the same instruction.
8113          * Fault-like exceptions, e.g. #GP and #PF, are the lowest
8114          * priority, but are only generated (pended) during instruction
8115          * execution, i.e. a pending fault-like exception means the
8116          * fault occurred on the *previous* instruction and must be
8117          * serviced prior to recognizing any new events in order to
8118          * fully complete the previous instruction.
8119          */
8120         else if (!vcpu->arch.exception.pending) {
8121                 if (vcpu->arch.nmi_injected) {
8122                         kvm_x86_ops.set_nmi(vcpu);
8123                         can_inject = false;
8124                 } else if (vcpu->arch.interrupt.injected) {
8125                         kvm_x86_ops.set_irq(vcpu);
8126                         can_inject = false;
8127                 }
8128         }
8129
8130         WARN_ON_ONCE(vcpu->arch.exception.injected &&
8131                      vcpu->arch.exception.pending);
8132
8133         /*
8134          * Call check_nested_events() even if we reinjected a previous event
8135          * in order for caller to determine if it should require immediate-exit
8136          * from L2 to L1 due to pending L1 events which require exit
8137          * from L2 to L1.
8138          */
8139         if (is_guest_mode(vcpu)) {
8140                 r = kvm_x86_ops.nested_ops->check_events(vcpu);
8141                 if (r < 0)
8142                         goto busy;
8143         }
8144
8145         /* try to inject new event if pending */
8146         if (vcpu->arch.exception.pending) {
8147                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
8148                                         vcpu->arch.exception.has_error_code,
8149                                         vcpu->arch.exception.error_code);
8150
8151                 vcpu->arch.exception.pending = false;
8152                 vcpu->arch.exception.injected = true;
8153
8154                 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
8155                         __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
8156                                              X86_EFLAGS_RF);
8157
8158                 if (vcpu->arch.exception.nr == DB_VECTOR) {
8159                         kvm_deliver_exception_payload(vcpu);
8160                         if (vcpu->arch.dr7 & DR7_GD) {
8161                                 vcpu->arch.dr7 &= ~DR7_GD;
8162                                 kvm_update_dr7(vcpu);
8163                         }
8164                 }
8165
8166                 kvm_x86_ops.queue_exception(vcpu);
8167                 can_inject = false;
8168         }
8169
8170         /*
8171          * Finally, inject interrupt events.  If an event cannot be injected
8172          * due to architectural conditions (e.g. IF=0) a window-open exit
8173          * will re-request KVM_REQ_EVENT.  Sometimes however an event is pending
8174          * and can architecturally be injected, but we cannot do it right now:
8175          * an interrupt could have arrived just now and we have to inject it
8176          * as a vmexit, or there could already an event in the queue, which is
8177          * indicated by can_inject.  In that case we request an immediate exit
8178          * in order to make progress and get back here for another iteration.
8179          * The kvm_x86_ops hooks communicate this by returning -EBUSY.
8180          */
8181         if (vcpu->arch.smi_pending) {
8182                 r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY;
8183                 if (r < 0)
8184                         goto busy;
8185                 if (r) {
8186                         vcpu->arch.smi_pending = false;
8187                         ++vcpu->arch.smi_count;
8188                         enter_smm(vcpu);
8189                         can_inject = false;
8190                 } else
8191                         kvm_x86_ops.enable_smi_window(vcpu);
8192         }
8193
8194         if (vcpu->arch.nmi_pending) {
8195                 r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY;
8196                 if (r < 0)
8197                         goto busy;
8198                 if (r) {
8199                         --vcpu->arch.nmi_pending;
8200                         vcpu->arch.nmi_injected = true;
8201                         kvm_x86_ops.set_nmi(vcpu);
8202                         can_inject = false;
8203                         WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0);
8204                 }
8205                 if (vcpu->arch.nmi_pending)
8206                         kvm_x86_ops.enable_nmi_window(vcpu);
8207         }
8208
8209         if (kvm_cpu_has_injectable_intr(vcpu)) {
8210                 r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY;
8211                 if (r < 0)
8212                         goto busy;
8213                 if (r) {
8214                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
8215                         kvm_x86_ops.set_irq(vcpu);
8216                         WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0);
8217                 }
8218                 if (kvm_cpu_has_injectable_intr(vcpu))
8219                         kvm_x86_ops.enable_irq_window(vcpu);
8220         }
8221
8222         if (is_guest_mode(vcpu) &&
8223             kvm_x86_ops.nested_ops->hv_timer_pending &&
8224             kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
8225                 *req_immediate_exit = true;
8226
8227         WARN_ON(vcpu->arch.exception.pending);
8228         return;
8229
8230 busy:
8231         *req_immediate_exit = true;
8232         return;
8233 }
8234
8235 static void process_nmi(struct kvm_vcpu *vcpu)
8236 {
8237         unsigned limit = 2;
8238
8239         /*
8240          * x86 is limited to one NMI running, and one NMI pending after it.
8241          * If an NMI is already in progress, limit further NMIs to just one.
8242          * Otherwise, allow two (and we'll inject the first one immediately).
8243          */
8244         if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
8245                 limit = 1;
8246
8247         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
8248         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
8249         kvm_make_request(KVM_REQ_EVENT, vcpu);
8250 }
8251
8252 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
8253 {
8254         u32 flags = 0;
8255         flags |= seg->g       << 23;
8256         flags |= seg->db      << 22;
8257         flags |= seg->l       << 21;
8258         flags |= seg->avl     << 20;
8259         flags |= seg->present << 15;
8260         flags |= seg->dpl     << 13;
8261         flags |= seg->s       << 12;
8262         flags |= seg->type    << 8;
8263         return flags;
8264 }
8265
8266 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
8267 {
8268         struct kvm_segment seg;
8269         int offset;
8270
8271         kvm_get_segment(vcpu, &seg, n);
8272         put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
8273
8274         if (n < 3)
8275                 offset = 0x7f84 + n * 12;
8276         else
8277                 offset = 0x7f2c + (n - 3) * 12;
8278
8279         put_smstate(u32, buf, offset + 8, seg.base);
8280         put_smstate(u32, buf, offset + 4, seg.limit);
8281         put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
8282 }
8283
8284 #ifdef CONFIG_X86_64
8285 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
8286 {
8287         struct kvm_segment seg;
8288         int offset;
8289         u16 flags;
8290
8291         kvm_get_segment(vcpu, &seg, n);
8292         offset = 0x7e00 + n * 16;
8293
8294         flags = enter_smm_get_segment_flags(&seg) >> 8;
8295         put_smstate(u16, buf, offset, seg.selector);
8296         put_smstate(u16, buf, offset + 2, flags);
8297         put_smstate(u32, buf, offset + 4, seg.limit);
8298         put_smstate(u64, buf, offset + 8, seg.base);
8299 }
8300 #endif
8301
8302 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
8303 {
8304         struct desc_ptr dt;
8305         struct kvm_segment seg;
8306         unsigned long val;
8307         int i;
8308
8309         put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
8310         put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
8311         put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
8312         put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
8313
8314         for (i = 0; i < 8; i++)
8315                 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
8316
8317         kvm_get_dr(vcpu, 6, &val);
8318         put_smstate(u32, buf, 0x7fcc, (u32)val);
8319         kvm_get_dr(vcpu, 7, &val);
8320         put_smstate(u32, buf, 0x7fc8, (u32)val);
8321
8322         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8323         put_smstate(u32, buf, 0x7fc4, seg.selector);
8324         put_smstate(u32, buf, 0x7f64, seg.base);
8325         put_smstate(u32, buf, 0x7f60, seg.limit);
8326         put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
8327
8328         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8329         put_smstate(u32, buf, 0x7fc0, seg.selector);
8330         put_smstate(u32, buf, 0x7f80, seg.base);
8331         put_smstate(u32, buf, 0x7f7c, seg.limit);
8332         put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
8333
8334         kvm_x86_ops.get_gdt(vcpu, &dt);
8335         put_smstate(u32, buf, 0x7f74, dt.address);
8336         put_smstate(u32, buf, 0x7f70, dt.size);
8337
8338         kvm_x86_ops.get_idt(vcpu, &dt);
8339         put_smstate(u32, buf, 0x7f58, dt.address);
8340         put_smstate(u32, buf, 0x7f54, dt.size);
8341
8342         for (i = 0; i < 6; i++)
8343                 enter_smm_save_seg_32(vcpu, buf, i);
8344
8345         put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
8346
8347         /* revision id */
8348         put_smstate(u32, buf, 0x7efc, 0x00020000);
8349         put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
8350 }
8351
8352 #ifdef CONFIG_X86_64
8353 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
8354 {
8355         struct desc_ptr dt;
8356         struct kvm_segment seg;
8357         unsigned long val;
8358         int i;
8359
8360         for (i = 0; i < 16; i++)
8361                 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
8362
8363         put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
8364         put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
8365
8366         kvm_get_dr(vcpu, 6, &val);
8367         put_smstate(u64, buf, 0x7f68, val);
8368         kvm_get_dr(vcpu, 7, &val);
8369         put_smstate(u64, buf, 0x7f60, val);
8370
8371         put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
8372         put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
8373         put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
8374
8375         put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
8376
8377         /* revision id */
8378         put_smstate(u32, buf, 0x7efc, 0x00020064);
8379
8380         put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
8381
8382         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8383         put_smstate(u16, buf, 0x7e90, seg.selector);
8384         put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
8385         put_smstate(u32, buf, 0x7e94, seg.limit);
8386         put_smstate(u64, buf, 0x7e98, seg.base);
8387
8388         kvm_x86_ops.get_idt(vcpu, &dt);
8389         put_smstate(u32, buf, 0x7e84, dt.size);
8390         put_smstate(u64, buf, 0x7e88, dt.address);
8391
8392         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8393         put_smstate(u16, buf, 0x7e70, seg.selector);
8394         put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
8395         put_smstate(u32, buf, 0x7e74, seg.limit);
8396         put_smstate(u64, buf, 0x7e78, seg.base);
8397
8398         kvm_x86_ops.get_gdt(vcpu, &dt);
8399         put_smstate(u32, buf, 0x7e64, dt.size);
8400         put_smstate(u64, buf, 0x7e68, dt.address);
8401
8402         for (i = 0; i < 6; i++)
8403                 enter_smm_save_seg_64(vcpu, buf, i);
8404 }
8405 #endif
8406
8407 static void enter_smm(struct kvm_vcpu *vcpu)
8408 {
8409         struct kvm_segment cs, ds;
8410         struct desc_ptr dt;
8411         char buf[512];
8412         u32 cr0;
8413
8414         trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
8415         memset(buf, 0, 512);
8416 #ifdef CONFIG_X86_64
8417         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8418                 enter_smm_save_state_64(vcpu, buf);
8419         else
8420 #endif
8421                 enter_smm_save_state_32(vcpu, buf);
8422
8423         /*
8424          * Give pre_enter_smm() a chance to make ISA-specific changes to the
8425          * vCPU state (e.g. leave guest mode) after we've saved the state into
8426          * the SMM state-save area.
8427          */
8428         kvm_x86_ops.pre_enter_smm(vcpu, buf);
8429
8430         vcpu->arch.hflags |= HF_SMM_MASK;
8431         kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
8432
8433         if (kvm_x86_ops.get_nmi_mask(vcpu))
8434                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
8435         else
8436                 kvm_x86_ops.set_nmi_mask(vcpu, true);
8437
8438         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
8439         kvm_rip_write(vcpu, 0x8000);
8440
8441         cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
8442         kvm_x86_ops.set_cr0(vcpu, cr0);
8443         vcpu->arch.cr0 = cr0;
8444
8445         kvm_x86_ops.set_cr4(vcpu, 0);
8446
8447         /* Undocumented: IDT limit is set to zero on entry to SMM.  */
8448         dt.address = dt.size = 0;
8449         kvm_x86_ops.set_idt(vcpu, &dt);
8450
8451         __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
8452
8453         cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
8454         cs.base = vcpu->arch.smbase;
8455
8456         ds.selector = 0;
8457         ds.base = 0;
8458
8459         cs.limit    = ds.limit = 0xffffffff;
8460         cs.type     = ds.type = 0x3;
8461         cs.dpl      = ds.dpl = 0;
8462         cs.db       = ds.db = 0;
8463         cs.s        = ds.s = 1;
8464         cs.l        = ds.l = 0;
8465         cs.g        = ds.g = 1;
8466         cs.avl      = ds.avl = 0;
8467         cs.present  = ds.present = 1;
8468         cs.unusable = ds.unusable = 0;
8469         cs.padding  = ds.padding = 0;
8470
8471         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8472         kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8473         kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8474         kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8475         kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8476         kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8477
8478 #ifdef CONFIG_X86_64
8479         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8480                 kvm_x86_ops.set_efer(vcpu, 0);
8481 #endif
8482
8483         kvm_update_cpuid_runtime(vcpu);
8484         kvm_mmu_reset_context(vcpu);
8485 }
8486
8487 static void process_smi(struct kvm_vcpu *vcpu)
8488 {
8489         vcpu->arch.smi_pending = true;
8490         kvm_make_request(KVM_REQ_EVENT, vcpu);
8491 }
8492
8493 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8494                                        unsigned long *vcpu_bitmap)
8495 {
8496         cpumask_var_t cpus;
8497
8498         zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8499
8500         kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8501                                     NULL, vcpu_bitmap, cpus);
8502
8503         free_cpumask_var(cpus);
8504 }
8505
8506 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8507 {
8508         kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8509 }
8510
8511 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8512 {
8513         if (!lapic_in_kernel(vcpu))
8514                 return;
8515
8516         vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8517         kvm_apic_update_apicv(vcpu);
8518         kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu);
8519 }
8520 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8521
8522 /*
8523  * NOTE: Do not hold any lock prior to calling this.
8524  *
8525  * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8526  * locked, because it calls __x86_set_memory_region() which does
8527  * synchronize_srcu(&kvm->srcu).
8528  */
8529 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8530 {
8531         struct kvm_vcpu *except;
8532         unsigned long old, new, expected;
8533
8534         if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8535             !kvm_x86_ops.check_apicv_inhibit_reasons(bit))
8536                 return;
8537
8538         old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8539         do {
8540                 expected = new = old;
8541                 if (activate)
8542                         __clear_bit(bit, &new);
8543                 else
8544                         __set_bit(bit, &new);
8545                 if (new == old)
8546                         break;
8547                 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8548         } while (old != expected);
8549
8550         if (!!old == !!new)
8551                 return;
8552
8553         trace_kvm_apicv_update_request(activate, bit);
8554         if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8555                 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate);
8556
8557         /*
8558          * Sending request to update APICV for all other vcpus,
8559          * while update the calling vcpu immediately instead of
8560          * waiting for another #VMEXIT to handle the request.
8561          */
8562         except = kvm_get_running_vcpu();
8563         kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE,
8564                                          except);
8565         if (except)
8566                 kvm_vcpu_update_apicv(except);
8567 }
8568 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8569
8570 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8571 {
8572         if (!kvm_apic_present(vcpu))
8573                 return;
8574
8575         bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8576
8577         if (irqchip_split(vcpu->kvm))
8578                 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8579         else {
8580                 if (vcpu->arch.apicv_active)
8581                         kvm_x86_ops.sync_pir_to_irr(vcpu);
8582                 if (ioapic_in_kernel(vcpu->kvm))
8583                         kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8584         }
8585
8586         if (is_guest_mode(vcpu))
8587                 vcpu->arch.load_eoi_exitmap_pending = true;
8588         else
8589                 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8590 }
8591
8592 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8593 {
8594         u64 eoi_exit_bitmap[4];
8595
8596         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8597                 return;
8598
8599         bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8600                   vcpu_to_synic(vcpu)->vec_bitmap, 256);
8601         kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8602 }
8603
8604 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8605                                             unsigned long start, unsigned long end)
8606 {
8607         unsigned long apic_address;
8608
8609         /*
8610          * The physical address of apic access page is stored in the VMCS.
8611          * Update it when it becomes invalid.
8612          */
8613         apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8614         if (start <= apic_address && apic_address < end)
8615                 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8616 }
8617
8618 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8619 {
8620         if (!lapic_in_kernel(vcpu))
8621                 return;
8622
8623         if (!kvm_x86_ops.set_apic_access_page_addr)
8624                 return;
8625
8626         kvm_x86_ops.set_apic_access_page_addr(vcpu);
8627 }
8628
8629 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8630 {
8631         smp_send_reschedule(vcpu->cpu);
8632 }
8633 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8634
8635 /*
8636  * Returns 1 to let vcpu_run() continue the guest execution loop without
8637  * exiting to the userspace.  Otherwise, the value will be returned to the
8638  * userspace.
8639  */
8640 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8641 {
8642         int r;
8643         bool req_int_win =
8644                 dm_request_for_irq_injection(vcpu) &&
8645                 kvm_cpu_accept_dm_intr(vcpu);
8646         fastpath_t exit_fastpath;
8647
8648         bool req_immediate_exit = false;
8649
8650         if (kvm_request_pending(vcpu)) {
8651                 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
8652                         if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
8653                                 r = 0;
8654                                 goto out;
8655                         }
8656                 }
8657                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8658                         kvm_mmu_unload(vcpu);
8659                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8660                         __kvm_migrate_timers(vcpu);
8661                 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8662                         kvm_gen_update_masterclock(vcpu->kvm);
8663                 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8664                         kvm_gen_kvmclock_update(vcpu);
8665                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8666                         r = kvm_guest_time_update(vcpu);
8667                         if (unlikely(r))
8668                                 goto out;
8669                 }
8670                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8671                         kvm_mmu_sync_roots(vcpu);
8672                 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8673                         kvm_mmu_load_pgd(vcpu);
8674                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
8675                         kvm_vcpu_flush_tlb_all(vcpu);
8676
8677                         /* Flushing all ASIDs flushes the current ASID... */
8678                         kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
8679                 }
8680                 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
8681                         kvm_vcpu_flush_tlb_current(vcpu);
8682                 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu))
8683                         kvm_vcpu_flush_tlb_guest(vcpu);
8684
8685                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8686                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8687                         r = 0;
8688                         goto out;
8689                 }
8690                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8691                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8692                         vcpu->mmio_needed = 0;
8693                         r = 0;
8694                         goto out;
8695                 }
8696                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8697                         /* Page is swapped out. Do synthetic halt */
8698                         vcpu->arch.apf.halted = true;
8699                         r = 1;
8700                         goto out;
8701                 }
8702                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8703                         record_steal_time(vcpu);
8704                 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8705                         process_smi(vcpu);
8706                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8707                         process_nmi(vcpu);
8708                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8709                         kvm_pmu_handle_event(vcpu);
8710                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8711                         kvm_pmu_deliver_pmi(vcpu);
8712                 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8713                         BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8714                         if (test_bit(vcpu->arch.pending_ioapic_eoi,
8715                                      vcpu->arch.ioapic_handled_vectors)) {
8716                                 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8717                                 vcpu->run->eoi.vector =
8718                                                 vcpu->arch.pending_ioapic_eoi;
8719                                 r = 0;
8720                                 goto out;
8721                         }
8722                 }
8723                 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8724                         vcpu_scan_ioapic(vcpu);
8725                 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8726                         vcpu_load_eoi_exitmap(vcpu);
8727                 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8728                         kvm_vcpu_reload_apic_access_page(vcpu);
8729                 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8730                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8731                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8732                         r = 0;
8733                         goto out;
8734                 }
8735                 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8736                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8737                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8738                         r = 0;
8739                         goto out;
8740                 }
8741                 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8742                         vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8743                         vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8744                         r = 0;
8745                         goto out;
8746                 }
8747
8748                 /*
8749                  * KVM_REQ_HV_STIMER has to be processed after
8750                  * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8751                  * depend on the guest clock being up-to-date
8752                  */
8753                 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8754                         kvm_hv_process_stimers(vcpu);
8755                 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8756                         kvm_vcpu_update_apicv(vcpu);
8757                 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
8758                         kvm_check_async_pf_completion(vcpu);
8759                 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
8760                         kvm_x86_ops.msr_filter_changed(vcpu);
8761         }
8762
8763         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8764                 ++vcpu->stat.req_event;
8765                 kvm_apic_accept_events(vcpu);
8766                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8767                         r = 1;
8768                         goto out;
8769                 }
8770
8771                 inject_pending_event(vcpu, &req_immediate_exit);
8772                 if (req_int_win)
8773                         kvm_x86_ops.enable_irq_window(vcpu);
8774
8775                 if (kvm_lapic_enabled(vcpu)) {
8776                         update_cr8_intercept(vcpu);
8777                         kvm_lapic_sync_to_vapic(vcpu);
8778                 }
8779         }
8780
8781         r = kvm_mmu_reload(vcpu);
8782         if (unlikely(r)) {
8783                 goto cancel_injection;
8784         }
8785
8786         preempt_disable();
8787
8788         kvm_x86_ops.prepare_guest_switch(vcpu);
8789
8790         /*
8791          * Disable IRQs before setting IN_GUEST_MODE.  Posted interrupt
8792          * IPI are then delayed after guest entry, which ensures that they
8793          * result in virtual interrupt delivery.
8794          */
8795         local_irq_disable();
8796         vcpu->mode = IN_GUEST_MODE;
8797
8798         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8799
8800         /*
8801          * 1) We should set ->mode before checking ->requests.  Please see
8802          * the comment in kvm_vcpu_exiting_guest_mode().
8803          *
8804          * 2) For APICv, we should set ->mode before checking PID.ON. This
8805          * pairs with the memory barrier implicit in pi_test_and_set_on
8806          * (see vmx_deliver_posted_interrupt).
8807          *
8808          * 3) This also orders the write to mode from any reads to the page
8809          * tables done while the VCPU is running.  Please see the comment
8810          * in kvm_flush_remote_tlbs.
8811          */
8812         smp_mb__after_srcu_read_unlock();
8813
8814         /*
8815          * This handles the case where a posted interrupt was
8816          * notified with kvm_vcpu_kick.
8817          */
8818         if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8819                 kvm_x86_ops.sync_pir_to_irr(vcpu);
8820
8821         if (kvm_vcpu_exit_request(vcpu)) {
8822                 vcpu->mode = OUTSIDE_GUEST_MODE;
8823                 smp_wmb();
8824                 local_irq_enable();
8825                 preempt_enable();
8826                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8827                 r = 1;
8828                 goto cancel_injection;
8829         }
8830
8831         if (req_immediate_exit) {
8832                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8833                 kvm_x86_ops.request_immediate_exit(vcpu);
8834         }
8835
8836         trace_kvm_entry(vcpu);
8837
8838         fpregs_assert_state_consistent();
8839         if (test_thread_flag(TIF_NEED_FPU_LOAD))
8840                 switch_fpu_return();
8841
8842         if (unlikely(vcpu->arch.switch_db_regs)) {
8843                 set_debugreg(0, 7);
8844                 set_debugreg(vcpu->arch.eff_db[0], 0);
8845                 set_debugreg(vcpu->arch.eff_db[1], 1);
8846                 set_debugreg(vcpu->arch.eff_db[2], 2);
8847                 set_debugreg(vcpu->arch.eff_db[3], 3);
8848                 set_debugreg(vcpu->arch.dr6, 6);
8849                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8850         }
8851
8852         exit_fastpath = kvm_x86_ops.run(vcpu);
8853
8854         /*
8855          * Do this here before restoring debug registers on the host.  And
8856          * since we do this before handling the vmexit, a DR access vmexit
8857          * can (a) read the correct value of the debug registers, (b) set
8858          * KVM_DEBUGREG_WONT_EXIT again.
8859          */
8860         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8861                 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8862                 kvm_x86_ops.sync_dirty_debug_regs(vcpu);
8863                 kvm_update_dr0123(vcpu);
8864                 kvm_update_dr7(vcpu);
8865                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8866         }
8867
8868         /*
8869          * If the guest has used debug registers, at least dr7
8870          * will be disabled while returning to the host.
8871          * If we don't have active breakpoints in the host, we don't
8872          * care about the messed up debug address registers. But if
8873          * we have some of them active, restore the old state.
8874          */
8875         if (hw_breakpoint_active())
8876                 hw_breakpoint_restore();
8877
8878         vcpu->arch.last_vmentry_cpu = vcpu->cpu;
8879         vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8880
8881         vcpu->mode = OUTSIDE_GUEST_MODE;
8882         smp_wmb();
8883
8884         kvm_x86_ops.handle_exit_irqoff(vcpu);
8885
8886         /*
8887          * Consume any pending interrupts, including the possible source of
8888          * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8889          * An instruction is required after local_irq_enable() to fully unblock
8890          * interrupts on processors that implement an interrupt shadow, the
8891          * stat.exits increment will do nicely.
8892          */
8893         kvm_before_interrupt(vcpu);
8894         local_irq_enable();
8895         ++vcpu->stat.exits;
8896         local_irq_disable();
8897         kvm_after_interrupt(vcpu);
8898
8899         if (lapic_in_kernel(vcpu)) {
8900                 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8901                 if (delta != S64_MIN) {
8902                         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8903                         vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8904                 }
8905         }
8906
8907         local_irq_enable();
8908         preempt_enable();
8909
8910         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8911
8912         /*
8913          * Profile KVM exit RIPs:
8914          */
8915         if (unlikely(prof_on == KVM_PROFILING)) {
8916                 unsigned long rip = kvm_rip_read(vcpu);
8917                 profile_hit(KVM_PROFILING, (void *)rip);
8918         }
8919
8920         if (unlikely(vcpu->arch.tsc_always_catchup))
8921                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8922
8923         if (vcpu->arch.apic_attention)
8924                 kvm_lapic_sync_from_vapic(vcpu);
8925
8926         r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath);
8927         return r;
8928
8929 cancel_injection:
8930         if (req_immediate_exit)
8931                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8932         kvm_x86_ops.cancel_injection(vcpu);
8933         if (unlikely(vcpu->arch.apic_attention))
8934                 kvm_lapic_sync_from_vapic(vcpu);
8935 out:
8936         return r;
8937 }
8938
8939 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8940 {
8941         if (!kvm_arch_vcpu_runnable(vcpu) &&
8942             (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) {
8943                 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8944                 kvm_vcpu_block(vcpu);
8945                 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8946
8947                 if (kvm_x86_ops.post_block)
8948                         kvm_x86_ops.post_block(vcpu);
8949
8950                 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8951                         return 1;
8952         }
8953
8954         kvm_apic_accept_events(vcpu);
8955         switch(vcpu->arch.mp_state) {
8956         case KVM_MP_STATE_HALTED:
8957                 vcpu->arch.pv.pv_unhalted = false;
8958                 vcpu->arch.mp_state =
8959                         KVM_MP_STATE_RUNNABLE;
8960                 fallthrough;
8961         case KVM_MP_STATE_RUNNABLE:
8962                 vcpu->arch.apf.halted = false;
8963                 break;
8964         case KVM_MP_STATE_INIT_RECEIVED:
8965                 break;
8966         default:
8967                 return -EINTR;
8968         }
8969         return 1;
8970 }
8971
8972 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8973 {
8974         if (is_guest_mode(vcpu))
8975                 kvm_x86_ops.nested_ops->check_events(vcpu);
8976
8977         return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8978                 !vcpu->arch.apf.halted);
8979 }
8980
8981 static int vcpu_run(struct kvm_vcpu *vcpu)
8982 {
8983         int r;
8984         struct kvm *kvm = vcpu->kvm;
8985
8986         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8987         vcpu->arch.l1tf_flush_l1d = true;
8988
8989         for (;;) {
8990                 if (kvm_vcpu_running(vcpu)) {
8991                         r = vcpu_enter_guest(vcpu);
8992                 } else {
8993                         r = vcpu_block(kvm, vcpu);
8994                 }
8995
8996                 if (r <= 0)
8997                         break;
8998
8999                 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
9000                 if (kvm_cpu_has_pending_timer(vcpu))
9001                         kvm_inject_pending_timer_irqs(vcpu);
9002
9003                 if (dm_request_for_irq_injection(vcpu) &&
9004                         kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
9005                         r = 0;
9006                         vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
9007                         ++vcpu->stat.request_irq_exits;
9008                         break;
9009                 }
9010
9011                 if (__xfer_to_guest_mode_work_pending()) {
9012                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9013                         r = xfer_to_guest_mode_handle_work(vcpu);
9014                         if (r)
9015                                 return r;
9016                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9017                 }
9018         }
9019
9020         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9021
9022         return r;
9023 }
9024
9025 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
9026 {
9027         int r;
9028
9029         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9030         r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
9031         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
9032         return r;
9033 }
9034
9035 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
9036 {
9037         BUG_ON(!vcpu->arch.pio.count);
9038
9039         return complete_emulated_io(vcpu);
9040 }
9041
9042 /*
9043  * Implements the following, as a state machine:
9044  *
9045  * read:
9046  *   for each fragment
9047  *     for each mmio piece in the fragment
9048  *       write gpa, len
9049  *       exit
9050  *       copy data
9051  *   execute insn
9052  *
9053  * write:
9054  *   for each fragment
9055  *     for each mmio piece in the fragment
9056  *       write gpa, len
9057  *       copy data
9058  *       exit
9059  */
9060 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
9061 {
9062         struct kvm_run *run = vcpu->run;
9063         struct kvm_mmio_fragment *frag;
9064         unsigned len;
9065
9066         BUG_ON(!vcpu->mmio_needed);
9067
9068         /* Complete previous fragment */
9069         frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
9070         len = min(8u, frag->len);
9071         if (!vcpu->mmio_is_write)
9072                 memcpy(frag->data, run->mmio.data, len);
9073
9074         if (frag->len <= 8) {
9075                 /* Switch to the next fragment. */
9076                 frag++;
9077                 vcpu->mmio_cur_fragment++;
9078         } else {
9079                 /* Go forward to the next mmio piece. */
9080                 frag->data += len;
9081                 frag->gpa += len;
9082                 frag->len -= len;
9083         }
9084
9085         if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
9086                 vcpu->mmio_needed = 0;
9087
9088                 /* FIXME: return into emulator if single-stepping.  */
9089                 if (vcpu->mmio_is_write)
9090                         return 1;
9091                 vcpu->mmio_read_completed = 1;
9092                 return complete_emulated_io(vcpu);
9093         }
9094
9095         run->exit_reason = KVM_EXIT_MMIO;
9096         run->mmio.phys_addr = frag->gpa;
9097         if (vcpu->mmio_is_write)
9098                 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
9099         run->mmio.len = min(8u, frag->len);
9100         run->mmio.is_write = vcpu->mmio_is_write;
9101         vcpu->arch.complete_userspace_io = complete_emulated_mmio;
9102         return 0;
9103 }
9104
9105 static void kvm_save_current_fpu(struct fpu *fpu)
9106 {
9107         /*
9108          * If the target FPU state is not resident in the CPU registers, just
9109          * memcpy() from current, else save CPU state directly to the target.
9110          */
9111         if (test_thread_flag(TIF_NEED_FPU_LOAD))
9112                 memcpy(&fpu->state, &current->thread.fpu.state,
9113                        fpu_kernel_xstate_size);
9114         else
9115                 copy_fpregs_to_fpstate(fpu);
9116 }
9117
9118 /* Swap (qemu) user FPU context for the guest FPU context. */
9119 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
9120 {
9121         fpregs_lock();
9122
9123         kvm_save_current_fpu(vcpu->arch.user_fpu);
9124
9125         /* PKRU is separately restored in kvm_x86_ops.run.  */
9126         __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
9127                                 ~XFEATURE_MASK_PKRU);
9128
9129         fpregs_mark_activate();
9130         fpregs_unlock();
9131
9132         trace_kvm_fpu(1);
9133 }
9134
9135 /* When vcpu_run ends, restore user space FPU context. */
9136 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
9137 {
9138         fpregs_lock();
9139
9140         kvm_save_current_fpu(vcpu->arch.guest_fpu);
9141
9142         copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
9143
9144         fpregs_mark_activate();
9145         fpregs_unlock();
9146
9147         ++vcpu->stat.fpu_reload;
9148         trace_kvm_fpu(0);
9149 }
9150
9151 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
9152 {
9153         struct kvm_run *kvm_run = vcpu->run;
9154         int r;
9155
9156         vcpu_load(vcpu);
9157         kvm_sigset_activate(vcpu);
9158         kvm_load_guest_fpu(vcpu);
9159
9160         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
9161                 if (kvm_run->immediate_exit) {
9162                         r = -EINTR;
9163                         goto out;
9164                 }
9165                 kvm_vcpu_block(vcpu);
9166                 kvm_apic_accept_events(vcpu);
9167                 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
9168                 r = -EAGAIN;
9169                 if (signal_pending(current)) {
9170                         r = -EINTR;
9171                         kvm_run->exit_reason = KVM_EXIT_INTR;
9172                         ++vcpu->stat.signal_exits;
9173                 }
9174                 goto out;
9175         }
9176
9177         if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
9178                 r = -EINVAL;
9179                 goto out;
9180         }
9181
9182         if (kvm_run->kvm_dirty_regs) {
9183                 r = sync_regs(vcpu);
9184                 if (r != 0)
9185                         goto out;
9186         }
9187
9188         /* re-sync apic's tpr */
9189         if (!lapic_in_kernel(vcpu)) {
9190                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
9191                         r = -EINVAL;
9192                         goto out;
9193                 }
9194         }
9195
9196         if (unlikely(vcpu->arch.complete_userspace_io)) {
9197                 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
9198                 vcpu->arch.complete_userspace_io = NULL;
9199                 r = cui(vcpu);
9200                 if (r <= 0)
9201                         goto out;
9202         } else
9203                 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
9204
9205         if (kvm_run->immediate_exit)
9206                 r = -EINTR;
9207         else
9208                 r = vcpu_run(vcpu);
9209
9210 out:
9211         kvm_put_guest_fpu(vcpu);
9212         if (kvm_run->kvm_valid_regs)
9213                 store_regs(vcpu);
9214         post_kvm_run_save(vcpu);
9215         kvm_sigset_deactivate(vcpu);
9216
9217         vcpu_put(vcpu);
9218         return r;
9219 }
9220
9221 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9222 {
9223         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
9224                 /*
9225                  * We are here if userspace calls get_regs() in the middle of
9226                  * instruction emulation. Registers state needs to be copied
9227                  * back from emulation context to vcpu. Userspace shouldn't do
9228                  * that usually, but some bad designed PV devices (vmware
9229                  * backdoor interface) need this to work
9230                  */
9231                 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
9232                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9233         }
9234         regs->rax = kvm_rax_read(vcpu);
9235         regs->rbx = kvm_rbx_read(vcpu);
9236         regs->rcx = kvm_rcx_read(vcpu);
9237         regs->rdx = kvm_rdx_read(vcpu);
9238         regs->rsi = kvm_rsi_read(vcpu);
9239         regs->rdi = kvm_rdi_read(vcpu);
9240         regs->rsp = kvm_rsp_read(vcpu);
9241         regs->rbp = kvm_rbp_read(vcpu);
9242 #ifdef CONFIG_X86_64
9243         regs->r8 = kvm_r8_read(vcpu);
9244         regs->r9 = kvm_r9_read(vcpu);
9245         regs->r10 = kvm_r10_read(vcpu);
9246         regs->r11 = kvm_r11_read(vcpu);
9247         regs->r12 = kvm_r12_read(vcpu);
9248         regs->r13 = kvm_r13_read(vcpu);
9249         regs->r14 = kvm_r14_read(vcpu);
9250         regs->r15 = kvm_r15_read(vcpu);
9251 #endif
9252
9253         regs->rip = kvm_rip_read(vcpu);
9254         regs->rflags = kvm_get_rflags(vcpu);
9255 }
9256
9257 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9258 {
9259         vcpu_load(vcpu);
9260         __get_regs(vcpu, regs);
9261         vcpu_put(vcpu);
9262         return 0;
9263 }
9264
9265 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9266 {
9267         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
9268         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9269
9270         kvm_rax_write(vcpu, regs->rax);
9271         kvm_rbx_write(vcpu, regs->rbx);
9272         kvm_rcx_write(vcpu, regs->rcx);
9273         kvm_rdx_write(vcpu, regs->rdx);
9274         kvm_rsi_write(vcpu, regs->rsi);
9275         kvm_rdi_write(vcpu, regs->rdi);
9276         kvm_rsp_write(vcpu, regs->rsp);
9277         kvm_rbp_write(vcpu, regs->rbp);
9278 #ifdef CONFIG_X86_64
9279         kvm_r8_write(vcpu, regs->r8);
9280         kvm_r9_write(vcpu, regs->r9);
9281         kvm_r10_write(vcpu, regs->r10);
9282         kvm_r11_write(vcpu, regs->r11);
9283         kvm_r12_write(vcpu, regs->r12);
9284         kvm_r13_write(vcpu, regs->r13);
9285         kvm_r14_write(vcpu, regs->r14);
9286         kvm_r15_write(vcpu, regs->r15);
9287 #endif
9288
9289         kvm_rip_write(vcpu, regs->rip);
9290         kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
9291
9292         vcpu->arch.exception.pending = false;
9293
9294         kvm_make_request(KVM_REQ_EVENT, vcpu);
9295 }
9296
9297 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9298 {
9299         vcpu_load(vcpu);
9300         __set_regs(vcpu, regs);
9301         vcpu_put(vcpu);
9302         return 0;
9303 }
9304
9305 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
9306 {
9307         struct kvm_segment cs;
9308
9309         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9310         *db = cs.db;
9311         *l = cs.l;
9312 }
9313 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
9314
9315 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9316 {
9317         struct desc_ptr dt;
9318
9319         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9320         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9321         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9322         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9323         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9324         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9325
9326         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9327         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9328
9329         kvm_x86_ops.get_idt(vcpu, &dt);
9330         sregs->idt.limit = dt.size;
9331         sregs->idt.base = dt.address;
9332         kvm_x86_ops.get_gdt(vcpu, &dt);
9333         sregs->gdt.limit = dt.size;
9334         sregs->gdt.base = dt.address;
9335
9336         sregs->cr0 = kvm_read_cr0(vcpu);
9337         sregs->cr2 = vcpu->arch.cr2;
9338         sregs->cr3 = kvm_read_cr3(vcpu);
9339         sregs->cr4 = kvm_read_cr4(vcpu);
9340         sregs->cr8 = kvm_get_cr8(vcpu);
9341         sregs->efer = vcpu->arch.efer;
9342         sregs->apic_base = kvm_get_apic_base(vcpu);
9343
9344         memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
9345
9346         if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
9347                 set_bit(vcpu->arch.interrupt.nr,
9348                         (unsigned long *)sregs->interrupt_bitmap);
9349 }
9350
9351 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
9352                                   struct kvm_sregs *sregs)
9353 {
9354         vcpu_load(vcpu);
9355         __get_sregs(vcpu, sregs);
9356         vcpu_put(vcpu);
9357         return 0;
9358 }
9359
9360 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
9361                                     struct kvm_mp_state *mp_state)
9362 {
9363         vcpu_load(vcpu);
9364         if (kvm_mpx_supported())
9365                 kvm_load_guest_fpu(vcpu);
9366
9367         kvm_apic_accept_events(vcpu);
9368         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
9369                                         vcpu->arch.pv.pv_unhalted)
9370                 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
9371         else
9372                 mp_state->mp_state = vcpu->arch.mp_state;
9373
9374         if (kvm_mpx_supported())
9375                 kvm_put_guest_fpu(vcpu);
9376         vcpu_put(vcpu);
9377         return 0;
9378 }
9379
9380 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
9381                                     struct kvm_mp_state *mp_state)
9382 {
9383         int ret = -EINVAL;
9384
9385         vcpu_load(vcpu);
9386
9387         if (!lapic_in_kernel(vcpu) &&
9388             mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
9389                 goto out;
9390
9391         /*
9392          * KVM_MP_STATE_INIT_RECEIVED means the processor is in
9393          * INIT state; latched init should be reported using
9394          * KVM_SET_VCPU_EVENTS, so reject it here.
9395          */
9396         if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
9397             (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
9398              mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
9399                 goto out;
9400
9401         if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
9402                 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
9403                 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
9404         } else
9405                 vcpu->arch.mp_state = mp_state->mp_state;
9406         kvm_make_request(KVM_REQ_EVENT, vcpu);
9407
9408         ret = 0;
9409 out:
9410         vcpu_put(vcpu);
9411         return ret;
9412 }
9413
9414 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
9415                     int reason, bool has_error_code, u32 error_code)
9416 {
9417         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9418         int ret;
9419
9420         init_emulate_ctxt(vcpu);
9421
9422         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9423                                    has_error_code, error_code);
9424         if (ret) {
9425                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9426                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
9427                 vcpu->run->internal.ndata = 0;
9428                 return 0;
9429         }
9430
9431         kvm_rip_write(vcpu, ctxt->eip);
9432         kvm_set_rflags(vcpu, ctxt->eflags);
9433         return 1;
9434 }
9435 EXPORT_SYMBOL_GPL(kvm_task_switch);
9436
9437 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9438 {
9439         if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
9440                 /*
9441                  * When EFER.LME and CR0.PG are set, the processor is in
9442                  * 64-bit mode (though maybe in a 32-bit code segment).
9443                  * CR4.PAE and EFER.LMA must be set.
9444                  */
9445                 if (!(sregs->cr4 & X86_CR4_PAE)
9446                     || !(sregs->efer & EFER_LMA))
9447                         return -EINVAL;
9448         } else {
9449                 /*
9450                  * Not in 64-bit mode: EFER.LMA is clear and the code
9451                  * segment cannot be 64-bit.
9452                  */
9453                 if (sregs->efer & EFER_LMA || sregs->cs.l)
9454                         return -EINVAL;
9455         }
9456
9457         return kvm_valid_cr4(vcpu, sregs->cr4);
9458 }
9459
9460 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9461 {
9462         struct msr_data apic_base_msr;
9463         int mmu_reset_needed = 0;
9464         int cpuid_update_needed = 0;
9465         int pending_vec, max_bits, idx;
9466         struct desc_ptr dt;
9467         int ret = -EINVAL;
9468
9469         if (kvm_valid_sregs(vcpu, sregs))
9470                 goto out;
9471
9472         apic_base_msr.data = sregs->apic_base;
9473         apic_base_msr.host_initiated = true;
9474         if (kvm_set_apic_base(vcpu, &apic_base_msr))
9475                 goto out;
9476
9477         dt.size = sregs->idt.limit;
9478         dt.address = sregs->idt.base;
9479         kvm_x86_ops.set_idt(vcpu, &dt);
9480         dt.size = sregs->gdt.limit;
9481         dt.address = sregs->gdt.base;
9482         kvm_x86_ops.set_gdt(vcpu, &dt);
9483
9484         vcpu->arch.cr2 = sregs->cr2;
9485         mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9486         vcpu->arch.cr3 = sregs->cr3;
9487         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9488
9489         kvm_set_cr8(vcpu, sregs->cr8);
9490
9491         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9492         kvm_x86_ops.set_efer(vcpu, sregs->efer);
9493
9494         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9495         kvm_x86_ops.set_cr0(vcpu, sregs->cr0);
9496         vcpu->arch.cr0 = sregs->cr0;
9497
9498         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9499         cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
9500                                 (X86_CR4_OSXSAVE | X86_CR4_PKE));
9501         kvm_x86_ops.set_cr4(vcpu, sregs->cr4);
9502         if (cpuid_update_needed)
9503                 kvm_update_cpuid_runtime(vcpu);
9504
9505         idx = srcu_read_lock(&vcpu->kvm->srcu);
9506         if (is_pae_paging(vcpu)) {
9507                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9508                 mmu_reset_needed = 1;
9509         }
9510         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9511
9512         if (mmu_reset_needed)
9513                 kvm_mmu_reset_context(vcpu);
9514
9515         max_bits = KVM_NR_INTERRUPTS;
9516         pending_vec = find_first_bit(
9517                 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9518         if (pending_vec < max_bits) {
9519                 kvm_queue_interrupt(vcpu, pending_vec, false);
9520                 pr_debug("Set back pending irq %d\n", pending_vec);
9521         }
9522
9523         kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9524         kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9525         kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9526         kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9527         kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9528         kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9529
9530         kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9531         kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9532
9533         update_cr8_intercept(vcpu);
9534
9535         /* Older userspace won't unhalt the vcpu on reset. */
9536         if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9537             sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9538             !is_protmode(vcpu))
9539                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9540
9541         kvm_make_request(KVM_REQ_EVENT, vcpu);
9542
9543         ret = 0;
9544 out:
9545         return ret;
9546 }
9547
9548 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9549                                   struct kvm_sregs *sregs)
9550 {
9551         int ret;
9552
9553         vcpu_load(vcpu);
9554         ret = __set_sregs(vcpu, sregs);
9555         vcpu_put(vcpu);
9556         return ret;
9557 }
9558
9559 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9560                                         struct kvm_guest_debug *dbg)
9561 {
9562         unsigned long rflags;
9563         int i, r;
9564
9565         vcpu_load(vcpu);
9566
9567         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9568                 r = -EBUSY;
9569                 if (vcpu->arch.exception.pending)
9570                         goto out;
9571                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9572                         kvm_queue_exception(vcpu, DB_VECTOR);
9573                 else
9574                         kvm_queue_exception(vcpu, BP_VECTOR);
9575         }
9576
9577         /*
9578          * Read rflags as long as potentially injected trace flags are still
9579          * filtered out.
9580          */
9581         rflags = kvm_get_rflags(vcpu);
9582
9583         vcpu->guest_debug = dbg->control;
9584         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9585                 vcpu->guest_debug = 0;
9586
9587         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9588                 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9589                         vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9590                 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9591         } else {
9592                 for (i = 0; i < KVM_NR_DB_REGS; i++)
9593                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9594         }
9595         kvm_update_dr7(vcpu);
9596
9597         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9598                 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9599                         get_segment_base(vcpu, VCPU_SREG_CS);
9600
9601         /*
9602          * Trigger an rflags update that will inject or remove the trace
9603          * flags.
9604          */
9605         kvm_set_rflags(vcpu, rflags);
9606
9607         kvm_x86_ops.update_exception_bitmap(vcpu);
9608
9609         r = 0;
9610
9611 out:
9612         vcpu_put(vcpu);
9613         return r;
9614 }
9615
9616 /*
9617  * Translate a guest virtual address to a guest physical address.
9618  */
9619 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9620                                     struct kvm_translation *tr)
9621 {
9622         unsigned long vaddr = tr->linear_address;
9623         gpa_t gpa;
9624         int idx;
9625
9626         vcpu_load(vcpu);
9627
9628         idx = srcu_read_lock(&vcpu->kvm->srcu);
9629         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9630         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9631         tr->physical_address = gpa;
9632         tr->valid = gpa != UNMAPPED_GVA;
9633         tr->writeable = 1;
9634         tr->usermode = 0;
9635
9636         vcpu_put(vcpu);
9637         return 0;
9638 }
9639
9640 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9641 {
9642         struct fxregs_state *fxsave;
9643
9644         vcpu_load(vcpu);
9645
9646         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9647         memcpy(fpu->fpr, fxsave->st_space, 128);
9648         fpu->fcw = fxsave->cwd;
9649         fpu->fsw = fxsave->swd;
9650         fpu->ftwx = fxsave->twd;
9651         fpu->last_opcode = fxsave->fop;
9652         fpu->last_ip = fxsave->rip;
9653         fpu->last_dp = fxsave->rdp;
9654         memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9655
9656         vcpu_put(vcpu);
9657         return 0;
9658 }
9659
9660 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9661 {
9662         struct fxregs_state *fxsave;
9663
9664         vcpu_load(vcpu);
9665
9666         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9667
9668         memcpy(fxsave->st_space, fpu->fpr, 128);
9669         fxsave->cwd = fpu->fcw;
9670         fxsave->swd = fpu->fsw;
9671         fxsave->twd = fpu->ftwx;
9672         fxsave->fop = fpu->last_opcode;
9673         fxsave->rip = fpu->last_ip;
9674         fxsave->rdp = fpu->last_dp;
9675         memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9676
9677         vcpu_put(vcpu);
9678         return 0;
9679 }
9680
9681 static void store_regs(struct kvm_vcpu *vcpu)
9682 {
9683         BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9684
9685         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9686                 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9687
9688         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9689                 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9690
9691         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9692                 kvm_vcpu_ioctl_x86_get_vcpu_events(
9693                                 vcpu, &vcpu->run->s.regs.events);
9694 }
9695
9696 static int sync_regs(struct kvm_vcpu *vcpu)
9697 {
9698         if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9699                 return -EINVAL;
9700
9701         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9702                 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9703                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9704         }
9705         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9706                 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9707                         return -EINVAL;
9708                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9709         }
9710         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9711                 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9712                                 vcpu, &vcpu->run->s.regs.events))
9713                         return -EINVAL;
9714                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9715         }
9716
9717         return 0;
9718 }
9719
9720 static void fx_init(struct kvm_vcpu *vcpu)
9721 {
9722         fpstate_init(&vcpu->arch.guest_fpu->state);
9723         if (boot_cpu_has(X86_FEATURE_XSAVES))
9724                 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9725                         host_xcr0 | XSTATE_COMPACTION_ENABLED;
9726
9727         /*
9728          * Ensure guest xcr0 is valid for loading
9729          */
9730         vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9731
9732         vcpu->arch.cr0 |= X86_CR0_ET;
9733 }
9734
9735 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9736 {
9737         if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9738                 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9739                              "guest TSC will not be reliable\n");
9740
9741         return 0;
9742 }
9743
9744 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9745 {
9746         struct page *page;
9747         int r;
9748
9749         if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9750                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9751         else
9752                 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9753
9754         kvm_set_tsc_khz(vcpu, max_tsc_khz);
9755
9756         r = kvm_mmu_create(vcpu);
9757         if (r < 0)
9758                 return r;
9759
9760         if (irqchip_in_kernel(vcpu->kvm)) {
9761                 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9762                 if (r < 0)
9763                         goto fail_mmu_destroy;
9764                 if (kvm_apicv_activated(vcpu->kvm))
9765                         vcpu->arch.apicv_active = true;
9766         } else
9767                 static_key_slow_inc(&kvm_no_apic_vcpu);
9768
9769         r = -ENOMEM;
9770
9771         page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9772         if (!page)
9773                 goto fail_free_lapic;
9774         vcpu->arch.pio_data = page_address(page);
9775
9776         vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9777                                        GFP_KERNEL_ACCOUNT);
9778         if (!vcpu->arch.mce_banks)
9779                 goto fail_free_pio_data;
9780         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9781
9782         if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9783                                 GFP_KERNEL_ACCOUNT))
9784                 goto fail_free_mce_banks;
9785
9786         if (!alloc_emulate_ctxt(vcpu))
9787                 goto free_wbinvd_dirty_mask;
9788
9789         vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9790                                                 GFP_KERNEL_ACCOUNT);
9791         if (!vcpu->arch.user_fpu) {
9792                 pr_err("kvm: failed to allocate userspace's fpu\n");
9793                 goto free_emulate_ctxt;
9794         }
9795
9796         vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9797                                                  GFP_KERNEL_ACCOUNT);
9798         if (!vcpu->arch.guest_fpu) {
9799                 pr_err("kvm: failed to allocate vcpu's fpu\n");
9800                 goto free_user_fpu;
9801         }
9802         fx_init(vcpu);
9803
9804         vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9805
9806         vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9807
9808         kvm_async_pf_hash_reset(vcpu);
9809         kvm_pmu_init(vcpu);
9810
9811         vcpu->arch.pending_external_vector = -1;
9812         vcpu->arch.preempted_in_kernel = false;
9813
9814         kvm_hv_vcpu_init(vcpu);
9815
9816         r = kvm_x86_ops.vcpu_create(vcpu);
9817         if (r)
9818                 goto free_guest_fpu;
9819
9820         vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9821         vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9822         kvm_vcpu_mtrr_init(vcpu);
9823         vcpu_load(vcpu);
9824         kvm_vcpu_reset(vcpu, false);
9825         kvm_init_mmu(vcpu, false);
9826         vcpu_put(vcpu);
9827         return 0;
9828
9829 free_guest_fpu:
9830         kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9831 free_user_fpu:
9832         kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9833 free_emulate_ctxt:
9834         kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9835 free_wbinvd_dirty_mask:
9836         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9837 fail_free_mce_banks:
9838         kfree(vcpu->arch.mce_banks);
9839 fail_free_pio_data:
9840         free_page((unsigned long)vcpu->arch.pio_data);
9841 fail_free_lapic:
9842         kvm_free_lapic(vcpu);
9843 fail_mmu_destroy:
9844         kvm_mmu_destroy(vcpu);
9845         return r;
9846 }
9847
9848 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9849 {
9850         struct kvm *kvm = vcpu->kvm;
9851
9852         kvm_hv_vcpu_postcreate(vcpu);
9853
9854         if (mutex_lock_killable(&vcpu->mutex))
9855                 return;
9856         vcpu_load(vcpu);
9857         kvm_synchronize_tsc(vcpu, 0);
9858         vcpu_put(vcpu);
9859
9860         /* poll control enabled by default */
9861         vcpu->arch.msr_kvm_poll_control = 1;
9862
9863         mutex_unlock(&vcpu->mutex);
9864
9865         if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
9866                 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9867                                                 KVMCLOCK_SYNC_PERIOD);
9868 }
9869
9870 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9871 {
9872         struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9873         int idx;
9874
9875         kvm_release_pfn(cache->pfn, cache->dirty, cache);
9876
9877         kvmclock_reset(vcpu);
9878
9879         kvm_x86_ops.vcpu_free(vcpu);
9880
9881         kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9882         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9883         kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9884         kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9885
9886         kvm_hv_vcpu_uninit(vcpu);
9887         kvm_pmu_destroy(vcpu);
9888         kfree(vcpu->arch.mce_banks);
9889         kvm_free_lapic(vcpu);
9890         idx = srcu_read_lock(&vcpu->kvm->srcu);
9891         kvm_mmu_destroy(vcpu);
9892         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9893         free_page((unsigned long)vcpu->arch.pio_data);
9894         if (!lapic_in_kernel(vcpu))
9895                 static_key_slow_dec(&kvm_no_apic_vcpu);
9896 }
9897
9898 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9899 {
9900         kvm_lapic_reset(vcpu, init_event);
9901
9902         vcpu->arch.hflags = 0;
9903
9904         vcpu->arch.smi_pending = 0;
9905         vcpu->arch.smi_count = 0;
9906         atomic_set(&vcpu->arch.nmi_queued, 0);
9907         vcpu->arch.nmi_pending = 0;
9908         vcpu->arch.nmi_injected = false;
9909         kvm_clear_interrupt_queue(vcpu);
9910         kvm_clear_exception_queue(vcpu);
9911
9912         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9913         kvm_update_dr0123(vcpu);
9914         vcpu->arch.dr6 = DR6_INIT;
9915         vcpu->arch.dr7 = DR7_FIXED_1;
9916         kvm_update_dr7(vcpu);
9917
9918         vcpu->arch.cr2 = 0;
9919
9920         kvm_make_request(KVM_REQ_EVENT, vcpu);
9921         vcpu->arch.apf.msr_en_val = 0;
9922         vcpu->arch.apf.msr_int_val = 0;
9923         vcpu->arch.st.msr_val = 0;
9924
9925         kvmclock_reset(vcpu);
9926
9927         kvm_clear_async_pf_completion_queue(vcpu);
9928         kvm_async_pf_hash_reset(vcpu);
9929         vcpu->arch.apf.halted = false;
9930
9931         if (kvm_mpx_supported()) {
9932                 void *mpx_state_buffer;
9933
9934                 /*
9935                  * To avoid have the INIT path from kvm_apic_has_events() that be
9936                  * called with loaded FPU and does not let userspace fix the state.
9937                  */
9938                 if (init_event)
9939                         kvm_put_guest_fpu(vcpu);
9940                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9941                                         XFEATURE_BNDREGS);
9942                 if (mpx_state_buffer)
9943                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9944                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9945                                         XFEATURE_BNDCSR);
9946                 if (mpx_state_buffer)
9947                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9948                 if (init_event)
9949                         kvm_load_guest_fpu(vcpu);
9950         }
9951
9952         if (!init_event) {
9953                 kvm_pmu_reset(vcpu);
9954                 vcpu->arch.smbase = 0x30000;
9955
9956                 vcpu->arch.msr_misc_features_enables = 0;
9957
9958                 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9959         }
9960
9961         memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9962         vcpu->arch.regs_avail = ~0;
9963         vcpu->arch.regs_dirty = ~0;
9964
9965         vcpu->arch.ia32_xss = 0;
9966
9967         kvm_x86_ops.vcpu_reset(vcpu, init_event);
9968 }
9969
9970 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9971 {
9972         struct kvm_segment cs;
9973
9974         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9975         cs.selector = vector << 8;
9976         cs.base = vector << 12;
9977         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9978         kvm_rip_write(vcpu, 0);
9979 }
9980
9981 int kvm_arch_hardware_enable(void)
9982 {
9983         struct kvm *kvm;
9984         struct kvm_vcpu *vcpu;
9985         int i;
9986         int ret;
9987         u64 local_tsc;
9988         u64 max_tsc = 0;
9989         bool stable, backwards_tsc = false;
9990
9991         kvm_user_return_msr_cpu_online();
9992         ret = kvm_x86_ops.hardware_enable();
9993         if (ret != 0)
9994                 return ret;
9995
9996         local_tsc = rdtsc();
9997         stable = !kvm_check_tsc_unstable();
9998         list_for_each_entry(kvm, &vm_list, vm_list) {
9999                 kvm_for_each_vcpu(i, vcpu, kvm) {
10000                         if (!stable && vcpu->cpu == smp_processor_id())
10001                                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10002                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
10003                                 backwards_tsc = true;
10004                                 if (vcpu->arch.last_host_tsc > max_tsc)
10005                                         max_tsc = vcpu->arch.last_host_tsc;
10006                         }
10007                 }
10008         }
10009
10010         /*
10011          * Sometimes, even reliable TSCs go backwards.  This happens on
10012          * platforms that reset TSC during suspend or hibernate actions, but
10013          * maintain synchronization.  We must compensate.  Fortunately, we can
10014          * detect that condition here, which happens early in CPU bringup,
10015          * before any KVM threads can be running.  Unfortunately, we can't
10016          * bring the TSCs fully up to date with real time, as we aren't yet far
10017          * enough into CPU bringup that we know how much real time has actually
10018          * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
10019          * variables that haven't been updated yet.
10020          *
10021          * So we simply find the maximum observed TSC above, then record the
10022          * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
10023          * the adjustment will be applied.  Note that we accumulate
10024          * adjustments, in case multiple suspend cycles happen before some VCPU
10025          * gets a chance to run again.  In the event that no KVM threads get a
10026          * chance to run, we will miss the entire elapsed period, as we'll have
10027          * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
10028          * loose cycle time.  This isn't too big a deal, since the loss will be
10029          * uniform across all VCPUs (not to mention the scenario is extremely
10030          * unlikely). It is possible that a second hibernate recovery happens
10031          * much faster than a first, causing the observed TSC here to be
10032          * smaller; this would require additional padding adjustment, which is
10033          * why we set last_host_tsc to the local tsc observed here.
10034          *
10035          * N.B. - this code below runs only on platforms with reliable TSC,
10036          * as that is the only way backwards_tsc is set above.  Also note
10037          * that this runs for ALL vcpus, which is not a bug; all VCPUs should
10038          * have the same delta_cyc adjustment applied if backwards_tsc
10039          * is detected.  Note further, this adjustment is only done once,
10040          * as we reset last_host_tsc on all VCPUs to stop this from being
10041          * called multiple times (one for each physical CPU bringup).
10042          *
10043          * Platforms with unreliable TSCs don't have to deal with this, they
10044          * will be compensated by the logic in vcpu_load, which sets the TSC to
10045          * catchup mode.  This will catchup all VCPUs to real time, but cannot
10046          * guarantee that they stay in perfect synchronization.
10047          */
10048         if (backwards_tsc) {
10049                 u64 delta_cyc = max_tsc - local_tsc;
10050                 list_for_each_entry(kvm, &vm_list, vm_list) {
10051                         kvm->arch.backwards_tsc_observed = true;
10052                         kvm_for_each_vcpu(i, vcpu, kvm) {
10053                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
10054                                 vcpu->arch.last_host_tsc = local_tsc;
10055                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
10056                         }
10057
10058                         /*
10059                          * We have to disable TSC offset matching.. if you were
10060                          * booting a VM while issuing an S4 host suspend....
10061                          * you may have some problem.  Solving this issue is
10062                          * left as an exercise to the reader.
10063                          */
10064                         kvm->arch.last_tsc_nsec = 0;
10065                         kvm->arch.last_tsc_write = 0;
10066                 }
10067
10068         }
10069         return 0;
10070 }
10071
10072 void kvm_arch_hardware_disable(void)
10073 {
10074         kvm_x86_ops.hardware_disable();
10075         drop_user_return_notifiers();
10076 }
10077
10078 int kvm_arch_hardware_setup(void *opaque)
10079 {
10080         struct kvm_x86_init_ops *ops = opaque;
10081         int r;
10082
10083         rdmsrl_safe(MSR_EFER, &host_efer);
10084
10085         if (boot_cpu_has(X86_FEATURE_XSAVES))
10086                 rdmsrl(MSR_IA32_XSS, host_xss);
10087
10088         r = ops->hardware_setup();
10089         if (r != 0)
10090                 return r;
10091
10092         memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
10093
10094         if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
10095                 supported_xss = 0;
10096
10097 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
10098         cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
10099 #undef __kvm_cpu_cap_has
10100
10101         if (kvm_has_tsc_control) {
10102                 /*
10103                  * Make sure the user can only configure tsc_khz values that
10104                  * fit into a signed integer.
10105                  * A min value is not calculated because it will always
10106                  * be 1 on all machines.
10107                  */
10108                 u64 max = min(0x7fffffffULL,
10109                               __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
10110                 kvm_max_guest_tsc_khz = max;
10111
10112                 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
10113         }
10114
10115         kvm_init_msr_list();
10116         return 0;
10117 }
10118
10119 void kvm_arch_hardware_unsetup(void)
10120 {
10121         kvm_x86_ops.hardware_unsetup();
10122 }
10123
10124 int kvm_arch_check_processor_compat(void *opaque)
10125 {
10126         struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
10127         struct kvm_x86_init_ops *ops = opaque;
10128
10129         WARN_ON(!irqs_disabled());
10130
10131         if (__cr4_reserved_bits(cpu_has, c) !=
10132             __cr4_reserved_bits(cpu_has, &boot_cpu_data))
10133                 return -EIO;
10134
10135         return ops->check_processor_compatibility();
10136 }
10137
10138 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
10139 {
10140         return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
10141 }
10142 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
10143
10144 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
10145 {
10146         return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
10147 }
10148
10149 struct static_key kvm_no_apic_vcpu __read_mostly;
10150 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
10151
10152 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
10153 {
10154         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
10155
10156         vcpu->arch.l1tf_flush_l1d = true;
10157         if (pmu->version && unlikely(pmu->event_count)) {
10158                 pmu->need_cleanup = true;
10159                 kvm_make_request(KVM_REQ_PMU, vcpu);
10160         }
10161         kvm_x86_ops.sched_in(vcpu, cpu);
10162 }
10163
10164 void kvm_arch_free_vm(struct kvm *kvm)
10165 {
10166         kfree(kvm->arch.hyperv.hv_pa_pg);
10167         vfree(kvm);
10168 }
10169
10170
10171 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
10172 {
10173         if (type)
10174                 return -EINVAL;
10175
10176         INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
10177         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
10178         INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
10179         INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
10180         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
10181         atomic_set(&kvm->arch.noncoherent_dma_count, 0);
10182
10183         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
10184         set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
10185         /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
10186         set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
10187                 &kvm->arch.irq_sources_bitmap);
10188
10189         raw_spin_lock_init(&kvm->arch.tsc_write_lock);
10190         mutex_init(&kvm->arch.apic_map_lock);
10191         spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
10192
10193         kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
10194         pvclock_update_vm_gtod_copy(kvm);
10195
10196         kvm->arch.guest_can_read_msr_platform_info = true;
10197
10198         INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
10199         INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
10200
10201         kvm_hv_init_vm(kvm);
10202         kvm_page_track_init(kvm);
10203         kvm_mmu_init_vm(kvm);
10204
10205         return kvm_x86_ops.vm_init(kvm);
10206 }
10207
10208 int kvm_arch_post_init_vm(struct kvm *kvm)
10209 {
10210         return kvm_mmu_post_init_vm(kvm);
10211 }
10212
10213 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
10214 {
10215         vcpu_load(vcpu);
10216         kvm_mmu_unload(vcpu);
10217         vcpu_put(vcpu);
10218 }
10219
10220 static void kvm_free_vcpus(struct kvm *kvm)
10221 {
10222         unsigned int i;
10223         struct kvm_vcpu *vcpu;
10224
10225         /*
10226          * Unpin any mmu pages first.
10227          */
10228         kvm_for_each_vcpu(i, vcpu, kvm) {
10229                 kvm_clear_async_pf_completion_queue(vcpu);
10230                 kvm_unload_vcpu_mmu(vcpu);
10231         }
10232         kvm_for_each_vcpu(i, vcpu, kvm)
10233                 kvm_vcpu_destroy(vcpu);
10234
10235         mutex_lock(&kvm->lock);
10236         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
10237                 kvm->vcpus[i] = NULL;
10238
10239         atomic_set(&kvm->online_vcpus, 0);
10240         mutex_unlock(&kvm->lock);
10241 }
10242
10243 void kvm_arch_sync_events(struct kvm *kvm)
10244 {
10245         cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
10246         cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
10247         kvm_free_pit(kvm);
10248 }
10249
10250 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
10251 {
10252         int i, r;
10253         unsigned long hva, old_npages;
10254         struct kvm_memslots *slots = kvm_memslots(kvm);
10255         struct kvm_memory_slot *slot;
10256
10257         /* Called with kvm->slots_lock held.  */
10258         if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
10259                 return -EINVAL;
10260
10261         slot = id_to_memslot(slots, id);
10262         if (size) {
10263                 if (slot && slot->npages)
10264                         return -EEXIST;
10265
10266                 /*
10267                  * MAP_SHARED to prevent internal slot pages from being moved
10268                  * by fork()/COW.
10269                  */
10270                 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
10271                               MAP_SHARED | MAP_ANONYMOUS, 0);
10272                 if (IS_ERR((void *)hva))
10273                         return PTR_ERR((void *)hva);
10274         } else {
10275                 if (!slot || !slot->npages)
10276                         return 0;
10277
10278                 old_npages = slot->npages;
10279                 hva = 0;
10280         }
10281
10282         for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
10283                 struct kvm_userspace_memory_region m;
10284
10285                 m.slot = id | (i << 16);
10286                 m.flags = 0;
10287                 m.guest_phys_addr = gpa;
10288                 m.userspace_addr = hva;
10289                 m.memory_size = size;
10290                 r = __kvm_set_memory_region(kvm, &m);
10291                 if (r < 0)
10292                         return r;
10293         }
10294
10295         if (!size)
10296                 vm_munmap(hva, old_npages * PAGE_SIZE);
10297
10298         return 0;
10299 }
10300 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
10301
10302 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
10303 {
10304         kvm_mmu_pre_destroy_vm(kvm);
10305 }
10306
10307 void kvm_arch_destroy_vm(struct kvm *kvm)
10308 {
10309         u32 i;
10310
10311         if (current->mm == kvm->mm) {
10312                 /*
10313                  * Free memory regions allocated on behalf of userspace,
10314                  * unless the the memory map has changed due to process exit
10315                  * or fd copying.
10316                  */
10317                 mutex_lock(&kvm->slots_lock);
10318                 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
10319                                         0, 0);
10320                 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
10321                                         0, 0);
10322                 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
10323                 mutex_unlock(&kvm->slots_lock);
10324         }
10325         if (kvm_x86_ops.vm_destroy)
10326                 kvm_x86_ops.vm_destroy(kvm);
10327         for (i = 0; i < kvm->arch.msr_filter.count; i++)
10328                 kfree(kvm->arch.msr_filter.ranges[i].bitmap);
10329         kvm_pic_destroy(kvm);
10330         kvm_ioapic_destroy(kvm);
10331         kvm_free_vcpus(kvm);
10332         kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
10333         kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
10334         kvm_mmu_uninit_vm(kvm);
10335         kvm_page_track_cleanup(kvm);
10336         kvm_hv_destroy_vm(kvm);
10337 }
10338
10339 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
10340 {
10341         int i;
10342
10343         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10344                 kvfree(slot->arch.rmap[i]);
10345                 slot->arch.rmap[i] = NULL;
10346
10347                 if (i == 0)
10348                         continue;
10349
10350                 kvfree(slot->arch.lpage_info[i - 1]);
10351                 slot->arch.lpage_info[i - 1] = NULL;
10352         }
10353
10354         kvm_page_track_free_memslot(slot);
10355 }
10356
10357 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
10358                                       unsigned long npages)
10359 {
10360         int i;
10361
10362         /*
10363          * Clear out the previous array pointers for the KVM_MR_MOVE case.  The
10364          * old arrays will be freed by __kvm_set_memory_region() if installing
10365          * the new memslot is successful.
10366          */
10367         memset(&slot->arch, 0, sizeof(slot->arch));
10368
10369         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10370                 struct kvm_lpage_info *linfo;
10371                 unsigned long ugfn;
10372                 int lpages;
10373                 int level = i + 1;
10374
10375                 lpages = gfn_to_index(slot->base_gfn + npages - 1,
10376                                       slot->base_gfn, level) + 1;
10377
10378                 slot->arch.rmap[i] =
10379                         kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
10380                                  GFP_KERNEL_ACCOUNT);
10381                 if (!slot->arch.rmap[i])
10382                         goto out_free;
10383                 if (i == 0)
10384                         continue;
10385
10386                 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
10387                 if (!linfo)
10388                         goto out_free;
10389
10390                 slot->arch.lpage_info[i - 1] = linfo;
10391
10392                 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
10393                         linfo[0].disallow_lpage = 1;
10394                 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
10395                         linfo[lpages - 1].disallow_lpage = 1;
10396                 ugfn = slot->userspace_addr >> PAGE_SHIFT;
10397                 /*
10398                  * If the gfn and userspace address are not aligned wrt each
10399                  * other, disable large page support for this slot.
10400                  */
10401                 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
10402                         unsigned long j;
10403
10404                         for (j = 0; j < lpages; ++j)
10405                                 linfo[j].disallow_lpage = 1;
10406                 }
10407         }
10408
10409         if (kvm_page_track_create_memslot(slot, npages))
10410                 goto out_free;
10411
10412         return 0;
10413
10414 out_free:
10415         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10416                 kvfree(slot->arch.rmap[i]);
10417                 slot->arch.rmap[i] = NULL;
10418                 if (i == 0)
10419                         continue;
10420
10421                 kvfree(slot->arch.lpage_info[i - 1]);
10422                 slot->arch.lpage_info[i - 1] = NULL;
10423         }
10424         return -ENOMEM;
10425 }
10426
10427 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
10428 {
10429         struct kvm_vcpu *vcpu;
10430         int i;
10431
10432         /*
10433          * memslots->generation has been incremented.
10434          * mmio generation may have reached its maximum value.
10435          */
10436         kvm_mmu_invalidate_mmio_sptes(kvm, gen);
10437
10438         /* Force re-initialization of steal_time cache */
10439         kvm_for_each_vcpu(i, vcpu, kvm)
10440                 kvm_vcpu_kick(vcpu);
10441 }
10442
10443 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10444                                 struct kvm_memory_slot *memslot,
10445                                 const struct kvm_userspace_memory_region *mem,
10446                                 enum kvm_mr_change change)
10447 {
10448         if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10449                 return kvm_alloc_memslot_metadata(memslot,
10450                                                   mem->memory_size >> PAGE_SHIFT);
10451         return 0;
10452 }
10453
10454 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10455                                      struct kvm_memory_slot *old,
10456                                      struct kvm_memory_slot *new,
10457                                      enum kvm_mr_change change)
10458 {
10459         /*
10460          * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot.
10461          * See comments below.
10462          */
10463         if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY))
10464                 return;
10465
10466         /*
10467          * Dirty logging tracks sptes in 4k granularity, meaning that large
10468          * sptes have to be split.  If live migration is successful, the guest
10469          * in the source machine will be destroyed and large sptes will be
10470          * created in the destination. However, if the guest continues to run
10471          * in the source machine (for example if live migration fails), small
10472          * sptes will remain around and cause bad performance.
10473          *
10474          * Scan sptes if dirty logging has been stopped, dropping those
10475          * which can be collapsed into a single large-page spte.  Later
10476          * page faults will create the large-page sptes.
10477          *
10478          * There is no need to do this in any of the following cases:
10479          * CREATE:      No dirty mappings will already exist.
10480          * MOVE/DELETE: The old mappings will already have been cleaned up by
10481          *              kvm_arch_flush_shadow_memslot()
10482          */
10483         if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10484             !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10485                 kvm_mmu_zap_collapsible_sptes(kvm, new);
10486
10487         /*
10488          * Enable or disable dirty logging for the slot.
10489          *
10490          * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old
10491          * slot have been zapped so no dirty logging updates are needed for
10492          * the old slot.
10493          * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible
10494          * any mappings that might be created in it will consume the
10495          * properties of the new slot and do not need to be updated here.
10496          *
10497          * When PML is enabled, the kvm_x86_ops dirty logging hooks are
10498          * called to enable/disable dirty logging.
10499          *
10500          * When disabling dirty logging with PML enabled, the D-bit is set
10501          * for sptes in the slot in order to prevent unnecessary GPA
10502          * logging in the PML buffer (and potential PML buffer full VMEXIT).
10503          * This guarantees leaving PML enabled for the guest's lifetime
10504          * won't have any additional overhead from PML when the guest is
10505          * running with dirty logging disabled.
10506          *
10507          * When enabling dirty logging, large sptes are write-protected
10508          * so they can be split on first write.  New large sptes cannot
10509          * be created for this slot until the end of the logging.
10510          * See the comments in fast_page_fault().
10511          * For small sptes, nothing is done if the dirty log is in the
10512          * initial-all-set state.  Otherwise, depending on whether pml
10513          * is enabled the D-bit or the W-bit will be cleared.
10514          */
10515         if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10516                 if (kvm_x86_ops.slot_enable_log_dirty) {
10517                         kvm_x86_ops.slot_enable_log_dirty(kvm, new);
10518                 } else {
10519                         int level =
10520                                 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10521                                 PG_LEVEL_2M : PG_LEVEL_4K;
10522
10523                         /*
10524                          * If we're with initial-all-set, we don't need
10525                          * to write protect any small page because
10526                          * they're reported as dirty already.  However
10527                          * we still need to write-protect huge pages
10528                          * so that the page split can happen lazily on
10529                          * the first write to the huge page.
10530                          */
10531                         kvm_mmu_slot_remove_write_access(kvm, new, level);
10532                 }
10533         } else {
10534                 if (kvm_x86_ops.slot_disable_log_dirty)
10535                         kvm_x86_ops.slot_disable_log_dirty(kvm, new);
10536         }
10537 }
10538
10539 void kvm_arch_commit_memory_region(struct kvm *kvm,
10540                                 const struct kvm_userspace_memory_region *mem,
10541                                 struct kvm_memory_slot *old,
10542                                 const struct kvm_memory_slot *new,
10543                                 enum kvm_mr_change change)
10544 {
10545         if (!kvm->arch.n_requested_mmu_pages)
10546                 kvm_mmu_change_mmu_pages(kvm,
10547                                 kvm_mmu_calculate_default_mmu_pages(kvm));
10548
10549         /*
10550          * FIXME: const-ify all uses of struct kvm_memory_slot.
10551          */
10552         kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change);
10553
10554         /* Free the arrays associated with the old memslot. */
10555         if (change == KVM_MR_MOVE)
10556                 kvm_arch_free_memslot(kvm, old);
10557 }
10558
10559 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10560 {
10561         kvm_mmu_zap_all(kvm);
10562 }
10563
10564 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10565                                    struct kvm_memory_slot *slot)
10566 {
10567         kvm_page_track_flush_slot(kvm, slot);
10568 }
10569
10570 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10571 {
10572         return (is_guest_mode(vcpu) &&
10573                         kvm_x86_ops.guest_apic_has_interrupt &&
10574                         kvm_x86_ops.guest_apic_has_interrupt(vcpu));
10575 }
10576
10577 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10578 {
10579         if (!list_empty_careful(&vcpu->async_pf.done))
10580                 return true;
10581
10582         if (kvm_apic_has_events(vcpu))
10583                 return true;
10584
10585         if (vcpu->arch.pv.pv_unhalted)
10586                 return true;
10587
10588         if (vcpu->arch.exception.pending)
10589                 return true;
10590
10591         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10592             (vcpu->arch.nmi_pending &&
10593              kvm_x86_ops.nmi_allowed(vcpu, false)))
10594                 return true;
10595
10596         if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10597             (vcpu->arch.smi_pending &&
10598              kvm_x86_ops.smi_allowed(vcpu, false)))
10599                 return true;
10600
10601         if (kvm_arch_interrupt_allowed(vcpu) &&
10602             (kvm_cpu_has_interrupt(vcpu) ||
10603             kvm_guest_apic_has_interrupt(vcpu)))
10604                 return true;
10605
10606         if (kvm_hv_has_stimer_pending(vcpu))
10607                 return true;
10608
10609         if (is_guest_mode(vcpu) &&
10610             kvm_x86_ops.nested_ops->hv_timer_pending &&
10611             kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
10612                 return true;
10613
10614         return false;
10615 }
10616
10617 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10618 {
10619         return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10620 }
10621
10622 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10623 {
10624         if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10625                 return true;
10626
10627         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10628                 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10629                  kvm_test_request(KVM_REQ_EVENT, vcpu))
10630                 return true;
10631
10632         if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu))
10633                 return true;
10634
10635         return false;
10636 }
10637
10638 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10639 {
10640         return vcpu->arch.preempted_in_kernel;
10641 }
10642
10643 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10644 {
10645         return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10646 }
10647
10648 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10649 {
10650         return kvm_x86_ops.interrupt_allowed(vcpu, false);
10651 }
10652
10653 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10654 {
10655         if (is_64_bit_mode(vcpu))
10656                 return kvm_rip_read(vcpu);
10657         return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10658                      kvm_rip_read(vcpu));
10659 }
10660 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10661
10662 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10663 {
10664         return kvm_get_linear_rip(vcpu) == linear_rip;
10665 }
10666 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10667
10668 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10669 {
10670         unsigned long rflags;
10671
10672         rflags = kvm_x86_ops.get_rflags(vcpu);
10673         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10674                 rflags &= ~X86_EFLAGS_TF;
10675         return rflags;
10676 }
10677 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10678
10679 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10680 {
10681         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10682             kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10683                 rflags |= X86_EFLAGS_TF;
10684         kvm_x86_ops.set_rflags(vcpu, rflags);
10685 }
10686
10687 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10688 {
10689         __kvm_set_rflags(vcpu, rflags);
10690         kvm_make_request(KVM_REQ_EVENT, vcpu);
10691 }
10692 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10693
10694 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10695 {
10696         int r;
10697
10698         if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10699               work->wakeup_all)
10700                 return;
10701
10702         r = kvm_mmu_reload(vcpu);
10703         if (unlikely(r))
10704                 return;
10705
10706         if (!vcpu->arch.mmu->direct_map &&
10707               work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10708                 return;
10709
10710         kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10711 }
10712
10713 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10714 {
10715         BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
10716
10717         return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10718 }
10719
10720 static inline u32 kvm_async_pf_next_probe(u32 key)
10721 {
10722         return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
10723 }
10724
10725 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10726 {
10727         u32 key = kvm_async_pf_hash_fn(gfn);
10728
10729         while (vcpu->arch.apf.gfns[key] != ~0)
10730                 key = kvm_async_pf_next_probe(key);
10731
10732         vcpu->arch.apf.gfns[key] = gfn;
10733 }
10734
10735 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10736 {
10737         int i;
10738         u32 key = kvm_async_pf_hash_fn(gfn);
10739
10740         for (i = 0; i < ASYNC_PF_PER_VCPU &&
10741                      (vcpu->arch.apf.gfns[key] != gfn &&
10742                       vcpu->arch.apf.gfns[key] != ~0); i++)
10743                 key = kvm_async_pf_next_probe(key);
10744
10745         return key;
10746 }
10747
10748 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10749 {
10750         return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10751 }
10752
10753 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10754 {
10755         u32 i, j, k;
10756
10757         i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10758
10759         if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
10760                 return;
10761
10762         while (true) {
10763                 vcpu->arch.apf.gfns[i] = ~0;
10764                 do {
10765                         j = kvm_async_pf_next_probe(j);
10766                         if (vcpu->arch.apf.gfns[j] == ~0)
10767                                 return;
10768                         k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10769                         /*
10770                          * k lies cyclically in ]i,j]
10771                          * |    i.k.j |
10772                          * |....j i.k.| or  |.k..j i...|
10773                          */
10774                 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10775                 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10776                 i = j;
10777         }
10778 }
10779
10780 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
10781 {
10782         u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
10783
10784         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
10785                                       sizeof(reason));
10786 }
10787
10788 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
10789 {
10790         unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
10791
10792         return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
10793                                              &token, offset, sizeof(token));
10794 }
10795
10796 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
10797 {
10798         unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
10799         u32 val;
10800
10801         if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
10802                                          &val, offset, sizeof(val)))
10803                 return false;
10804
10805         return !val;
10806 }
10807
10808 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10809 {
10810         if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10811                 return false;
10812
10813         if (!kvm_pv_async_pf_enabled(vcpu) ||
10814             (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0))
10815                 return false;
10816
10817         return true;
10818 }
10819
10820 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10821 {
10822         if (unlikely(!lapic_in_kernel(vcpu) ||
10823                      kvm_event_needs_reinjection(vcpu) ||
10824                      vcpu->arch.exception.pending))
10825                 return false;
10826
10827         if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10828                 return false;
10829
10830         /*
10831          * If interrupts are off we cannot even use an artificial
10832          * halt state.
10833          */
10834         return kvm_arch_interrupt_allowed(vcpu);
10835 }
10836
10837 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10838                                      struct kvm_async_pf *work)
10839 {
10840         struct x86_exception fault;
10841
10842         trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10843         kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10844
10845         if (kvm_can_deliver_async_pf(vcpu) &&
10846             !apf_put_user_notpresent(vcpu)) {
10847                 fault.vector = PF_VECTOR;
10848                 fault.error_code_valid = true;
10849                 fault.error_code = 0;
10850                 fault.nested_page_fault = false;
10851                 fault.address = work->arch.token;
10852                 fault.async_page_fault = true;
10853                 kvm_inject_page_fault(vcpu, &fault);
10854                 return true;
10855         } else {
10856                 /*
10857                  * It is not possible to deliver a paravirtualized asynchronous
10858                  * page fault, but putting the guest in an artificial halt state
10859                  * can be beneficial nevertheless: if an interrupt arrives, we
10860                  * can deliver it timely and perhaps the guest will schedule
10861                  * another process.  When the instruction that triggered a page
10862                  * fault is retried, hopefully the page will be ready in the host.
10863                  */
10864                 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10865                 return false;
10866         }
10867 }
10868
10869 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10870                                  struct kvm_async_pf *work)
10871 {
10872         struct kvm_lapic_irq irq = {
10873                 .delivery_mode = APIC_DM_FIXED,
10874                 .vector = vcpu->arch.apf.vec
10875         };
10876
10877         if (work->wakeup_all)
10878                 work->arch.token = ~0; /* broadcast wakeup */
10879         else
10880                 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10881         trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
10882
10883         if ((work->wakeup_all || work->notpresent_injected) &&
10884             kvm_pv_async_pf_enabled(vcpu) &&
10885             !apf_put_user_ready(vcpu, work->arch.token)) {
10886                 vcpu->arch.apf.pageready_pending = true;
10887                 kvm_apic_set_irq(vcpu, &irq, NULL);
10888         }
10889
10890         vcpu->arch.apf.halted = false;
10891         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10892 }
10893
10894 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
10895 {
10896         kvm_make_request(KVM_REQ_APF_READY, vcpu);
10897         if (!vcpu->arch.apf.pageready_pending)
10898                 kvm_vcpu_kick(vcpu);
10899 }
10900
10901 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
10902 {
10903         if (!kvm_pv_async_pf_enabled(vcpu))
10904                 return true;
10905         else
10906                 return apf_pageready_slot_free(vcpu);
10907 }
10908
10909 void kvm_arch_start_assignment(struct kvm *kvm)
10910 {
10911         atomic_inc(&kvm->arch.assigned_device_count);
10912 }
10913 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10914
10915 void kvm_arch_end_assignment(struct kvm *kvm)
10916 {
10917         atomic_dec(&kvm->arch.assigned_device_count);
10918 }
10919 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10920
10921 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10922 {
10923         return atomic_read(&kvm->arch.assigned_device_count);
10924 }
10925 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10926
10927 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10928 {
10929         atomic_inc(&kvm->arch.noncoherent_dma_count);
10930 }
10931 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10932
10933 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10934 {
10935         atomic_dec(&kvm->arch.noncoherent_dma_count);
10936 }
10937 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10938
10939 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10940 {
10941         return atomic_read(&kvm->arch.noncoherent_dma_count);
10942 }
10943 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10944
10945 bool kvm_arch_has_irq_bypass(void)
10946 {
10947         return true;
10948 }
10949
10950 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10951                                       struct irq_bypass_producer *prod)
10952 {
10953         struct kvm_kernel_irqfd *irqfd =
10954                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10955         int ret;
10956
10957         irqfd->producer = prod;
10958         kvm_arch_start_assignment(irqfd->kvm);
10959         ret = kvm_x86_ops.update_pi_irte(irqfd->kvm,
10960                                          prod->irq, irqfd->gsi, 1);
10961
10962         if (ret)
10963                 kvm_arch_end_assignment(irqfd->kvm);
10964
10965         return ret;
10966 }
10967
10968 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10969                                       struct irq_bypass_producer *prod)
10970 {
10971         int ret;
10972         struct kvm_kernel_irqfd *irqfd =
10973                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10974
10975         WARN_ON(irqfd->producer != prod);
10976         irqfd->producer = NULL;
10977
10978         /*
10979          * When producer of consumer is unregistered, we change back to
10980          * remapped mode, so we can re-use the current implementation
10981          * when the irq is masked/disabled or the consumer side (KVM
10982          * int this case doesn't want to receive the interrupts.
10983         */
10984         ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10985         if (ret)
10986                 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10987                        " fails: %d\n", irqfd->consumer.token, ret);
10988
10989         kvm_arch_end_assignment(irqfd->kvm);
10990 }
10991
10992 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10993                                    uint32_t guest_irq, bool set)
10994 {
10995         return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set);
10996 }
10997
10998 bool kvm_vector_hashing_enabled(void)
10999 {
11000         return vector_hashing;
11001 }
11002
11003 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
11004 {
11005         return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
11006 }
11007 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
11008
11009
11010 int kvm_spec_ctrl_test_value(u64 value)
11011 {
11012         /*
11013          * test that setting IA32_SPEC_CTRL to given value
11014          * is allowed by the host processor
11015          */
11016
11017         u64 saved_value;
11018         unsigned long flags;
11019         int ret = 0;
11020
11021         local_irq_save(flags);
11022
11023         if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
11024                 ret = 1;
11025         else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
11026                 ret = 1;
11027         else
11028                 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
11029
11030         local_irq_restore(flags);
11031
11032         return ret;
11033 }
11034 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
11035
11036 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
11037 {
11038         struct x86_exception fault;
11039         u32 access = error_code &
11040                 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
11041
11042         if (!(error_code & PFERR_PRESENT_MASK) ||
11043             vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) {
11044                 /*
11045                  * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
11046                  * tables probably do not match the TLB.  Just proceed
11047                  * with the error code that the processor gave.
11048                  */
11049                 fault.vector = PF_VECTOR;
11050                 fault.error_code_valid = true;
11051                 fault.error_code = error_code;
11052                 fault.nested_page_fault = false;
11053                 fault.address = gva;
11054         }
11055         vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
11056 }
11057 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
11058
11059 /*
11060  * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
11061  * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
11062  * indicates whether exit to userspace is needed.
11063  */
11064 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
11065                               struct x86_exception *e)
11066 {
11067         if (r == X86EMUL_PROPAGATE_FAULT) {
11068                 kvm_inject_emulated_page_fault(vcpu, e);
11069                 return 1;
11070         }
11071
11072         /*
11073          * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
11074          * while handling a VMX instruction KVM could've handled the request
11075          * correctly by exiting to userspace and performing I/O but there
11076          * doesn't seem to be a real use-case behind such requests, just return
11077          * KVM_EXIT_INTERNAL_ERROR for now.
11078          */
11079         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11080         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11081         vcpu->run->internal.ndata = 0;
11082
11083         return 0;
11084 }
11085 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
11086
11087 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
11088 {
11089         bool pcid_enabled;
11090         struct x86_exception e;
11091         unsigned i;
11092         unsigned long roots_to_free = 0;
11093         struct {
11094                 u64 pcid;
11095                 u64 gla;
11096         } operand;
11097         int r;
11098
11099         r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
11100         if (r != X86EMUL_CONTINUE)
11101                 return kvm_handle_memory_failure(vcpu, r, &e);
11102
11103         if (operand.pcid >> 12 != 0) {
11104                 kvm_inject_gp(vcpu, 0);
11105                 return 1;
11106         }
11107
11108         pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
11109
11110         switch (type) {
11111         case INVPCID_TYPE_INDIV_ADDR:
11112                 if ((!pcid_enabled && (operand.pcid != 0)) ||
11113                     is_noncanonical_address(operand.gla, vcpu)) {
11114                         kvm_inject_gp(vcpu, 0);
11115                         return 1;
11116                 }
11117                 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
11118                 return kvm_skip_emulated_instruction(vcpu);
11119
11120         case INVPCID_TYPE_SINGLE_CTXT:
11121                 if (!pcid_enabled && (operand.pcid != 0)) {
11122                         kvm_inject_gp(vcpu, 0);
11123                         return 1;
11124                 }
11125
11126                 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
11127                         kvm_mmu_sync_roots(vcpu);
11128                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
11129                 }
11130
11131                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
11132                         if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd)
11133                             == operand.pcid)
11134                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
11135
11136                 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
11137                 /*
11138                  * If neither the current cr3 nor any of the prev_roots use the
11139                  * given PCID, then nothing needs to be done here because a
11140                  * resync will happen anyway before switching to any other CR3.
11141                  */
11142
11143                 return kvm_skip_emulated_instruction(vcpu);
11144
11145         case INVPCID_TYPE_ALL_NON_GLOBAL:
11146                 /*
11147                  * Currently, KVM doesn't mark global entries in the shadow
11148                  * page tables, so a non-global flush just degenerates to a
11149                  * global flush. If needed, we could optimize this later by
11150                  * keeping track of global entries in shadow page tables.
11151                  */
11152
11153                 fallthrough;
11154         case INVPCID_TYPE_ALL_INCL_GLOBAL:
11155                 kvm_mmu_unload(vcpu);
11156                 return kvm_skip_emulated_instruction(vcpu);
11157
11158         default:
11159                 BUG(); /* We have already checked above that type <= 3 */
11160         }
11161 }
11162 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
11163
11164 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
11165 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
11166 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
11167 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
11168 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
11169 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
11170 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
11171 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
11172 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
11173 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
11174 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
11175 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
11176 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
11177 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
11178 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
11179 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
11180 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
11181 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
11182 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
11183 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
11184 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
11185 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);