1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/sched/isolation.h>
58 #include <linux/mem_encrypt.h>
59 #include <linux/entry-kvm.h>
61 #include <trace/events/kvm.h>
63 #include <asm/debugreg.h>
67 #include <linux/kernel_stat.h>
68 #include <asm/fpu/internal.h> /* Ugh! */
69 #include <asm/pvclock.h>
70 #include <asm/div64.h>
71 #include <asm/irq_remapping.h>
72 #include <asm/mshyperv.h>
73 #include <asm/hypervisor.h>
74 #include <asm/tlbflush.h>
75 #include <asm/intel_pt.h>
76 #include <asm/emulate_prefix.h>
77 #include <clocksource/hyperv_timer.h>
79 #define CREATE_TRACE_POINTS
82 #define MAX_IO_MSRS 256
83 #define KVM_MAX_MCE_BANKS 32
84 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
85 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
87 #define emul_to_vcpu(ctxt) \
88 ((struct kvm_vcpu *)(ctxt)->vcpu)
91 * - enable syscall per default because its emulated by KVM
92 * - enable LME and LMA per default on 64 bit KVM
96 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
98 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
101 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
103 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
104 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
106 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
107 static void process_nmi(struct kvm_vcpu *vcpu);
108 static void enter_smm(struct kvm_vcpu *vcpu);
109 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
110 static void store_regs(struct kvm_vcpu *vcpu);
111 static int sync_regs(struct kvm_vcpu *vcpu);
113 struct kvm_x86_ops kvm_x86_ops __read_mostly;
114 EXPORT_SYMBOL_GPL(kvm_x86_ops);
116 static bool __read_mostly ignore_msrs = 0;
117 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
119 static bool __read_mostly report_ignored_msrs = true;
120 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
122 unsigned int min_timer_period_us = 200;
123 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
125 static bool __read_mostly kvmclock_periodic_sync = true;
126 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
128 bool __read_mostly kvm_has_tsc_control;
129 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
130 u32 __read_mostly kvm_max_guest_tsc_khz;
131 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
132 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
133 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
134 u64 __read_mostly kvm_max_tsc_scaling_ratio;
135 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
136 u64 __read_mostly kvm_default_tsc_scaling_ratio;
137 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
139 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
140 static u32 __read_mostly tsc_tolerance_ppm = 250;
141 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
144 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
145 * adaptive tuning starting from default advancment of 1000ns. '0' disables
146 * advancement entirely. Any other value is used as-is and disables adaptive
147 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
149 static int __read_mostly lapic_timer_advance_ns = -1;
150 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
152 static bool __read_mostly vector_hashing = true;
153 module_param(vector_hashing, bool, S_IRUGO);
155 bool __read_mostly enable_vmware_backdoor = false;
156 module_param(enable_vmware_backdoor, bool, S_IRUGO);
157 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
159 static bool __read_mostly force_emulation_prefix = false;
160 module_param(force_emulation_prefix, bool, S_IRUGO);
162 int __read_mostly pi_inject_timer = -1;
163 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
166 * Restoring the host value for MSRs that are only consumed when running in
167 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
168 * returns to userspace, i.e. the kernel can run with the guest's value.
170 #define KVM_MAX_NR_USER_RETURN_MSRS 16
172 struct kvm_user_return_msrs_global {
174 u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS];
177 struct kvm_user_return_msrs {
178 struct user_return_notifier urn;
180 struct kvm_user_return_msr_values {
183 } values[KVM_MAX_NR_USER_RETURN_MSRS];
186 static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global;
187 static struct kvm_user_return_msrs __percpu *user_return_msrs;
189 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
190 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
191 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
192 | XFEATURE_MASK_PKRU)
194 u64 __read_mostly host_efer;
195 EXPORT_SYMBOL_GPL(host_efer);
197 bool __read_mostly allow_smaller_maxphyaddr = 0;
198 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
200 static u64 __read_mostly host_xss;
201 u64 __read_mostly supported_xss;
202 EXPORT_SYMBOL_GPL(supported_xss);
204 struct kvm_stats_debugfs_item debugfs_entries[] = {
205 VCPU_STAT("pf_fixed", pf_fixed),
206 VCPU_STAT("pf_guest", pf_guest),
207 VCPU_STAT("tlb_flush", tlb_flush),
208 VCPU_STAT("invlpg", invlpg),
209 VCPU_STAT("exits", exits),
210 VCPU_STAT("io_exits", io_exits),
211 VCPU_STAT("mmio_exits", mmio_exits),
212 VCPU_STAT("signal_exits", signal_exits),
213 VCPU_STAT("irq_window", irq_window_exits),
214 VCPU_STAT("nmi_window", nmi_window_exits),
215 VCPU_STAT("halt_exits", halt_exits),
216 VCPU_STAT("halt_successful_poll", halt_successful_poll),
217 VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
218 VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
219 VCPU_STAT("halt_wakeup", halt_wakeup),
220 VCPU_STAT("hypercalls", hypercalls),
221 VCPU_STAT("request_irq", request_irq_exits),
222 VCPU_STAT("irq_exits", irq_exits),
223 VCPU_STAT("host_state_reload", host_state_reload),
224 VCPU_STAT("fpu_reload", fpu_reload),
225 VCPU_STAT("insn_emulation", insn_emulation),
226 VCPU_STAT("insn_emulation_fail", insn_emulation_fail),
227 VCPU_STAT("irq_injections", irq_injections),
228 VCPU_STAT("nmi_injections", nmi_injections),
229 VCPU_STAT("req_event", req_event),
230 VCPU_STAT("l1d_flush", l1d_flush),
231 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
232 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
233 VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped),
234 VM_STAT("mmu_pte_write", mmu_pte_write),
235 VM_STAT("mmu_pte_updated", mmu_pte_updated),
236 VM_STAT("mmu_pde_zapped", mmu_pde_zapped),
237 VM_STAT("mmu_flooded", mmu_flooded),
238 VM_STAT("mmu_recycled", mmu_recycled),
239 VM_STAT("mmu_cache_miss", mmu_cache_miss),
240 VM_STAT("mmu_unsync", mmu_unsync),
241 VM_STAT("remote_tlb_flush", remote_tlb_flush),
242 VM_STAT("largepages", lpages, .mode = 0444),
243 VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444),
244 VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions),
248 u64 __read_mostly host_xcr0;
249 u64 __read_mostly supported_xcr0;
250 EXPORT_SYMBOL_GPL(supported_xcr0);
252 static struct kmem_cache *x86_fpu_cache;
254 static struct kmem_cache *x86_emulator_cache;
257 * When called, it means the previous get/set msr reached an invalid msr.
258 * Return true if we want to ignore/silent this failed msr access.
260 static bool kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr,
261 u64 data, bool write)
263 const char *op = write ? "wrmsr" : "rdmsr";
266 if (report_ignored_msrs)
267 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
272 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
278 static struct kmem_cache *kvm_alloc_emulator_cache(void)
280 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
281 unsigned int size = sizeof(struct x86_emulate_ctxt);
283 return kmem_cache_create_usercopy("x86_emulator", size,
284 __alignof__(struct x86_emulate_ctxt),
285 SLAB_ACCOUNT, useroffset,
286 size - useroffset, NULL);
289 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
291 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
294 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
295 vcpu->arch.apf.gfns[i] = ~0;
298 static void kvm_on_user_return(struct user_return_notifier *urn)
301 struct kvm_user_return_msrs *msrs
302 = container_of(urn, struct kvm_user_return_msrs, urn);
303 struct kvm_user_return_msr_values *values;
307 * Disabling irqs at this point since the following code could be
308 * interrupted and executed through kvm_arch_hardware_disable()
310 local_irq_save(flags);
311 if (msrs->registered) {
312 msrs->registered = false;
313 user_return_notifier_unregister(urn);
315 local_irq_restore(flags);
316 for (slot = 0; slot < user_return_msrs_global.nr; ++slot) {
317 values = &msrs->values[slot];
318 if (values->host != values->curr) {
319 wrmsrl(user_return_msrs_global.msrs[slot], values->host);
320 values->curr = values->host;
325 void kvm_define_user_return_msr(unsigned slot, u32 msr)
327 BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS);
328 user_return_msrs_global.msrs[slot] = msr;
329 if (slot >= user_return_msrs_global.nr)
330 user_return_msrs_global.nr = slot + 1;
332 EXPORT_SYMBOL_GPL(kvm_define_user_return_msr);
334 static void kvm_user_return_msr_cpu_online(void)
336 unsigned int cpu = smp_processor_id();
337 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
341 for (i = 0; i < user_return_msrs_global.nr; ++i) {
342 rdmsrl_safe(user_return_msrs_global.msrs[i], &value);
343 msrs->values[i].host = value;
344 msrs->values[i].curr = value;
348 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
350 unsigned int cpu = smp_processor_id();
351 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
354 value = (value & mask) | (msrs->values[slot].host & ~mask);
355 if (value == msrs->values[slot].curr)
357 err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value);
361 msrs->values[slot].curr = value;
362 if (!msrs->registered) {
363 msrs->urn.on_user_return = kvm_on_user_return;
364 user_return_notifier_register(&msrs->urn);
365 msrs->registered = true;
369 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
371 static void drop_user_return_notifiers(void)
373 unsigned int cpu = smp_processor_id();
374 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
376 if (msrs->registered)
377 kvm_on_user_return(&msrs->urn);
380 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
382 return vcpu->arch.apic_base;
384 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
386 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
388 return kvm_apic_mode(kvm_get_apic_base(vcpu));
390 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
392 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
394 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
395 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
396 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
397 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
399 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
401 if (!msr_info->host_initiated) {
402 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
404 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
408 kvm_lapic_set_base(vcpu, msr_info->data);
409 kvm_recalculate_apic_map(vcpu->kvm);
412 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
414 asmlinkage __visible noinstr void kvm_spurious_fault(void)
416 /* Fault while not rebooting. We want the trace. */
417 BUG_ON(!kvm_rebooting);
419 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
421 #define EXCPT_BENIGN 0
422 #define EXCPT_CONTRIBUTORY 1
425 static int exception_class(int vector)
435 return EXCPT_CONTRIBUTORY;
442 #define EXCPT_FAULT 0
444 #define EXCPT_ABORT 2
445 #define EXCPT_INTERRUPT 3
447 static int exception_type(int vector)
451 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
452 return EXCPT_INTERRUPT;
456 /* #DB is trap, as instruction watchpoints are handled elsewhere */
457 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
460 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
463 /* Reserved exceptions will result in fault */
467 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
469 unsigned nr = vcpu->arch.exception.nr;
470 bool has_payload = vcpu->arch.exception.has_payload;
471 unsigned long payload = vcpu->arch.exception.payload;
479 * "Certain debug exceptions may clear bit 0-3. The
480 * remaining contents of the DR6 register are never
481 * cleared by the processor".
483 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
485 * DR6.RTM is set by all #DB exceptions that don't clear it.
487 vcpu->arch.dr6 |= DR6_RTM;
488 vcpu->arch.dr6 |= payload;
490 * Bit 16 should be set in the payload whenever the #DB
491 * exception should clear DR6.RTM. This makes the payload
492 * compatible with the pending debug exceptions under VMX.
493 * Though not currently documented in the SDM, this also
494 * makes the payload compatible with the exit qualification
495 * for #DB exceptions under VMX.
497 vcpu->arch.dr6 ^= payload & DR6_RTM;
500 * The #DB payload is defined as compatible with the 'pending
501 * debug exceptions' field under VMX, not DR6. While bit 12 is
502 * defined in the 'pending debug exceptions' field (enabled
503 * breakpoint), it is reserved and must be zero in DR6.
505 vcpu->arch.dr6 &= ~BIT(12);
508 vcpu->arch.cr2 = payload;
512 vcpu->arch.exception.has_payload = false;
513 vcpu->arch.exception.payload = 0;
515 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
517 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
518 unsigned nr, bool has_error, u32 error_code,
519 bool has_payload, unsigned long payload, bool reinject)
524 kvm_make_request(KVM_REQ_EVENT, vcpu);
526 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
528 if (has_error && !is_protmode(vcpu))
532 * On vmentry, vcpu->arch.exception.pending is only
533 * true if an event injection was blocked by
534 * nested_run_pending. In that case, however,
535 * vcpu_enter_guest requests an immediate exit,
536 * and the guest shouldn't proceed far enough to
539 WARN_ON_ONCE(vcpu->arch.exception.pending);
540 vcpu->arch.exception.injected = true;
541 if (WARN_ON_ONCE(has_payload)) {
543 * A reinjected event has already
544 * delivered its payload.
550 vcpu->arch.exception.pending = true;
551 vcpu->arch.exception.injected = false;
553 vcpu->arch.exception.has_error_code = has_error;
554 vcpu->arch.exception.nr = nr;
555 vcpu->arch.exception.error_code = error_code;
556 vcpu->arch.exception.has_payload = has_payload;
557 vcpu->arch.exception.payload = payload;
558 if (!is_guest_mode(vcpu))
559 kvm_deliver_exception_payload(vcpu);
563 /* to check exception */
564 prev_nr = vcpu->arch.exception.nr;
565 if (prev_nr == DF_VECTOR) {
566 /* triple fault -> shutdown */
567 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
570 class1 = exception_class(prev_nr);
571 class2 = exception_class(nr);
572 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
573 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
575 * Generate double fault per SDM Table 5-5. Set
576 * exception.pending = true so that the double fault
577 * can trigger a nested vmexit.
579 vcpu->arch.exception.pending = true;
580 vcpu->arch.exception.injected = false;
581 vcpu->arch.exception.has_error_code = true;
582 vcpu->arch.exception.nr = DF_VECTOR;
583 vcpu->arch.exception.error_code = 0;
584 vcpu->arch.exception.has_payload = false;
585 vcpu->arch.exception.payload = 0;
587 /* replace previous exception with a new one in a hope
588 that instruction re-execution will regenerate lost
593 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
595 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
597 EXPORT_SYMBOL_GPL(kvm_queue_exception);
599 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
601 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
603 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
605 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
606 unsigned long payload)
608 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
610 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
612 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
613 u32 error_code, unsigned long payload)
615 kvm_multiple_exception(vcpu, nr, true, error_code,
616 true, payload, false);
619 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
622 kvm_inject_gp(vcpu, 0);
624 return kvm_skip_emulated_instruction(vcpu);
628 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
630 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
632 ++vcpu->stat.pf_guest;
633 vcpu->arch.exception.nested_apf =
634 is_guest_mode(vcpu) && fault->async_page_fault;
635 if (vcpu->arch.exception.nested_apf) {
636 vcpu->arch.apf.nested_apf_token = fault->address;
637 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
639 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
643 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
645 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
646 struct x86_exception *fault)
648 struct kvm_mmu *fault_mmu;
649 WARN_ON_ONCE(fault->vector != PF_VECTOR);
651 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
655 * Invalidate the TLB entry for the faulting address, if it exists,
656 * else the access will fault indefinitely (and to emulate hardware).
658 if ((fault->error_code & PFERR_PRESENT_MASK) &&
659 !(fault->error_code & PFERR_RSVD_MASK))
660 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
661 fault_mmu->root_hpa);
663 fault_mmu->inject_page_fault(vcpu, fault);
664 return fault->nested_page_fault;
666 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
668 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
670 atomic_inc(&vcpu->arch.nmi_queued);
671 kvm_make_request(KVM_REQ_NMI, vcpu);
673 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
675 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
677 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
679 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
681 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
683 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
685 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
688 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
689 * a #GP and return false.
691 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
693 if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl)
695 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
698 EXPORT_SYMBOL_GPL(kvm_require_cpl);
700 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
702 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705 kvm_queue_exception(vcpu, UD_VECTOR);
708 EXPORT_SYMBOL_GPL(kvm_require_dr);
711 * This function will be used to read from the physical memory of the currently
712 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
713 * can read from guest physical or from the guest's guest physical memory.
715 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
716 gfn_t ngfn, void *data, int offset, int len,
719 struct x86_exception exception;
723 ngpa = gfn_to_gpa(ngfn);
724 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
725 if (real_gfn == UNMAPPED_GVA)
728 real_gfn = gpa_to_gfn(real_gfn);
730 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
732 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
734 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
735 void *data, int offset, int len, u32 access)
737 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
738 data, offset, len, access);
741 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
743 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
748 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
750 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
752 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
753 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
756 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
758 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
759 offset * sizeof(u64), sizeof(pdpte),
760 PFERR_USER_MASK|PFERR_WRITE_MASK);
765 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
766 if ((pdpte[i] & PT_PRESENT_MASK) &&
767 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
774 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
775 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
781 EXPORT_SYMBOL_GPL(load_pdptrs);
783 bool pdptrs_changed(struct kvm_vcpu *vcpu)
785 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
790 if (!is_pae_paging(vcpu))
793 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
796 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
797 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
798 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
799 PFERR_USER_MASK | PFERR_WRITE_MASK);
803 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
805 EXPORT_SYMBOL_GPL(pdptrs_changed);
807 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
809 unsigned long old_cr0 = kvm_read_cr0(vcpu);
810 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG;
811 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
816 if (cr0 & 0xffffffff00000000UL)
820 cr0 &= ~CR0_RESERVED_BITS;
822 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
825 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
829 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
830 (cr0 & X86_CR0_PG)) {
835 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
840 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
841 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) &&
842 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)))
845 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
848 kvm_x86_ops.set_cr0(vcpu, cr0);
850 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
851 kvm_clear_async_pf_completion_queue(vcpu);
852 kvm_async_pf_hash_reset(vcpu);
855 if ((cr0 ^ old_cr0) & update_bits)
856 kvm_mmu_reset_context(vcpu);
858 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
859 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
860 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
861 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
865 EXPORT_SYMBOL_GPL(kvm_set_cr0);
867 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
869 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
871 EXPORT_SYMBOL_GPL(kvm_lmsw);
873 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
875 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
877 if (vcpu->arch.xcr0 != host_xcr0)
878 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
880 if (vcpu->arch.xsaves_enabled &&
881 vcpu->arch.ia32_xss != host_xss)
882 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
885 if (static_cpu_has(X86_FEATURE_PKU) &&
886 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
887 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
888 vcpu->arch.pkru != vcpu->arch.host_pkru)
889 __write_pkru(vcpu->arch.pkru);
891 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
893 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
895 if (static_cpu_has(X86_FEATURE_PKU) &&
896 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
897 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
898 vcpu->arch.pkru = rdpkru();
899 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
900 __write_pkru(vcpu->arch.host_pkru);
903 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
905 if (vcpu->arch.xcr0 != host_xcr0)
906 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
908 if (vcpu->arch.xsaves_enabled &&
909 vcpu->arch.ia32_xss != host_xss)
910 wrmsrl(MSR_IA32_XSS, host_xss);
914 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
916 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
919 u64 old_xcr0 = vcpu->arch.xcr0;
922 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
923 if (index != XCR_XFEATURE_ENABLED_MASK)
925 if (!(xcr0 & XFEATURE_MASK_FP))
927 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
931 * Do not allow the guest to set bits that we do not support
932 * saving. However, xcr0 bit 0 is always set, even if the
933 * emulated CPU does not support XSAVE (see fx_init).
935 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
936 if (xcr0 & ~valid_bits)
939 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
940 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
943 if (xcr0 & XFEATURE_MASK_AVX512) {
944 if (!(xcr0 & XFEATURE_MASK_YMM))
946 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
949 vcpu->arch.xcr0 = xcr0;
951 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
952 kvm_update_cpuid_runtime(vcpu);
956 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
958 if (kvm_x86_ops.get_cpl(vcpu) != 0 ||
959 __kvm_set_xcr(vcpu, index, xcr)) {
960 kvm_inject_gp(vcpu, 0);
965 EXPORT_SYMBOL_GPL(kvm_set_xcr);
967 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
969 if (cr4 & cr4_reserved_bits)
972 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
975 return kvm_x86_ops.is_valid_cr4(vcpu, cr4);
977 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4);
979 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
981 unsigned long old_cr4 = kvm_read_cr4(vcpu);
982 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
984 unsigned long mmu_role_bits = pdptr_bits | X86_CR4_SMAP | X86_CR4_PKE;
986 if (!kvm_is_valid_cr4(vcpu, cr4))
989 if (is_long_mode(vcpu)) {
990 if (!(cr4 & X86_CR4_PAE))
992 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
994 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
995 && ((cr4 ^ old_cr4) & pdptr_bits)
996 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
1000 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1001 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1004 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1005 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1009 kvm_x86_ops.set_cr4(vcpu, cr4);
1011 if (((cr4 ^ old_cr4) & mmu_role_bits) ||
1012 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1013 kvm_mmu_reset_context(vcpu);
1015 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1016 kvm_update_cpuid_runtime(vcpu);
1020 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1022 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1024 bool skip_tlb_flush = false;
1025 #ifdef CONFIG_X86_64
1026 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1029 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1030 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1034 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1035 if (!skip_tlb_flush) {
1036 kvm_mmu_sync_roots(vcpu);
1037 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1042 if (is_long_mode(vcpu) &&
1043 (cr3 & vcpu->arch.cr3_lm_rsvd_bits))
1045 else if (is_pae_paging(vcpu) &&
1046 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1049 kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush);
1050 vcpu->arch.cr3 = cr3;
1051 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1055 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1057 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1059 if (cr8 & CR8_RESERVED_BITS)
1061 if (lapic_in_kernel(vcpu))
1062 kvm_lapic_set_tpr(vcpu, cr8);
1064 vcpu->arch.cr8 = cr8;
1067 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1069 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1071 if (lapic_in_kernel(vcpu))
1072 return kvm_lapic_get_cr8(vcpu);
1074 return vcpu->arch.cr8;
1076 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1078 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1082 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1083 for (i = 0; i < KVM_NR_DB_REGS; i++)
1084 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1085 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1089 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1093 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1094 dr7 = vcpu->arch.guest_debug_dr7;
1096 dr7 = vcpu->arch.dr7;
1097 kvm_x86_ops.set_dr7(vcpu, dr7);
1098 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1099 if (dr7 & DR7_BP_EN_MASK)
1100 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1102 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1104 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1106 u64 fixed = DR6_FIXED_1;
1108 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1113 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1115 size_t size = ARRAY_SIZE(vcpu->arch.db);
1119 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1120 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1121 vcpu->arch.eff_db[dr] = val;
1125 if (!kvm_dr6_valid(val))
1126 return -1; /* #GP */
1127 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1131 if (!kvm_dr7_valid(val))
1132 return -1; /* #GP */
1133 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1134 kvm_update_dr7(vcpu);
1141 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1143 if (__kvm_set_dr(vcpu, dr, val)) {
1144 kvm_inject_gp(vcpu, 0);
1149 EXPORT_SYMBOL_GPL(kvm_set_dr);
1151 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1153 size_t size = ARRAY_SIZE(vcpu->arch.db);
1157 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1161 *val = vcpu->arch.dr6;
1165 *val = vcpu->arch.dr7;
1170 EXPORT_SYMBOL_GPL(kvm_get_dr);
1172 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1174 u32 ecx = kvm_rcx_read(vcpu);
1178 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1181 kvm_rax_write(vcpu, (u32)data);
1182 kvm_rdx_write(vcpu, data >> 32);
1185 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1188 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1189 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1191 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1192 * extract the supported MSRs from the related const lists.
1193 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1194 * capabilities of the host cpu. This capabilities test skips MSRs that are
1195 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1196 * may depend on host virtualization features rather than host cpu features.
1199 static const u32 msrs_to_save_all[] = {
1200 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1202 #ifdef CONFIG_X86_64
1203 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1205 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1206 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1208 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1209 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1210 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1211 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1212 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1213 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1214 MSR_IA32_UMWAIT_CONTROL,
1216 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1217 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1218 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1219 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1220 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1221 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1222 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1223 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1224 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1225 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1226 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1227 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1228 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1229 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1230 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1231 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1232 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1233 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1234 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1235 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1236 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1237 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1240 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1241 static unsigned num_msrs_to_save;
1243 static const u32 emulated_msrs_all[] = {
1244 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1245 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1246 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1247 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1248 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1249 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1250 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1252 HV_X64_MSR_VP_INDEX,
1253 HV_X64_MSR_VP_RUNTIME,
1254 HV_X64_MSR_SCONTROL,
1255 HV_X64_MSR_STIMER0_CONFIG,
1256 HV_X64_MSR_VP_ASSIST_PAGE,
1257 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1258 HV_X64_MSR_TSC_EMULATION_STATUS,
1259 HV_X64_MSR_SYNDBG_OPTIONS,
1260 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1261 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1262 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1264 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1265 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1267 MSR_IA32_TSC_ADJUST,
1268 MSR_IA32_TSCDEADLINE,
1269 MSR_IA32_ARCH_CAPABILITIES,
1270 MSR_IA32_PERF_CAPABILITIES,
1271 MSR_IA32_MISC_ENABLE,
1272 MSR_IA32_MCG_STATUS,
1274 MSR_IA32_MCG_EXT_CTL,
1278 MSR_MISC_FEATURES_ENABLES,
1279 MSR_AMD64_VIRT_SPEC_CTRL,
1284 * The following list leaves out MSRs whose values are determined
1285 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1286 * We always support the "true" VMX control MSRs, even if the host
1287 * processor does not, so I am putting these registers here rather
1288 * than in msrs_to_save_all.
1291 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1292 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1293 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1294 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1296 MSR_IA32_VMX_CR0_FIXED0,
1297 MSR_IA32_VMX_CR4_FIXED0,
1298 MSR_IA32_VMX_VMCS_ENUM,
1299 MSR_IA32_VMX_PROCBASED_CTLS2,
1300 MSR_IA32_VMX_EPT_VPID_CAP,
1301 MSR_IA32_VMX_VMFUNC,
1304 MSR_KVM_POLL_CONTROL,
1307 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1308 static unsigned num_emulated_msrs;
1311 * List of msr numbers which are used to expose MSR-based features that
1312 * can be used by a hypervisor to validate requested CPU features.
1314 static const u32 msr_based_features_all[] = {
1316 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1317 MSR_IA32_VMX_PINBASED_CTLS,
1318 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1319 MSR_IA32_VMX_PROCBASED_CTLS,
1320 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1321 MSR_IA32_VMX_EXIT_CTLS,
1322 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1323 MSR_IA32_VMX_ENTRY_CTLS,
1325 MSR_IA32_VMX_CR0_FIXED0,
1326 MSR_IA32_VMX_CR0_FIXED1,
1327 MSR_IA32_VMX_CR4_FIXED0,
1328 MSR_IA32_VMX_CR4_FIXED1,
1329 MSR_IA32_VMX_VMCS_ENUM,
1330 MSR_IA32_VMX_PROCBASED_CTLS2,
1331 MSR_IA32_VMX_EPT_VPID_CAP,
1332 MSR_IA32_VMX_VMFUNC,
1336 MSR_IA32_ARCH_CAPABILITIES,
1337 MSR_IA32_PERF_CAPABILITIES,
1340 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1341 static unsigned int num_msr_based_features;
1343 static u64 kvm_get_arch_capabilities(void)
1347 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1348 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1351 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1352 * the nested hypervisor runs with NX huge pages. If it is not,
1353 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1354 * L1 guests, so it need not worry about its own (L2) guests.
1356 data |= ARCH_CAP_PSCHANGE_MC_NO;
1359 * If we're doing cache flushes (either "always" or "cond")
1360 * we will do one whenever the guest does a vmlaunch/vmresume.
1361 * If an outer hypervisor is doing the cache flush for us
1362 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1363 * capability to the guest too, and if EPT is disabled we're not
1364 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1365 * require a nested hypervisor to do a flush of its own.
1367 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1368 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1370 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1371 data |= ARCH_CAP_RDCL_NO;
1372 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1373 data |= ARCH_CAP_SSB_NO;
1374 if (!boot_cpu_has_bug(X86_BUG_MDS))
1375 data |= ARCH_CAP_MDS_NO;
1378 * On TAA affected systems:
1379 * - nothing to do if TSX is disabled on the host.
1380 * - we emulate TSX_CTRL if present on the host.
1381 * This lets the guest use VERW to clear CPU buffers.
1383 if (!boot_cpu_has(X86_FEATURE_RTM))
1384 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1385 else if (!boot_cpu_has_bug(X86_BUG_TAA))
1386 data |= ARCH_CAP_TAA_NO;
1391 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1393 switch (msr->index) {
1394 case MSR_IA32_ARCH_CAPABILITIES:
1395 msr->data = kvm_get_arch_capabilities();
1397 case MSR_IA32_UCODE_REV:
1398 rdmsrl_safe(msr->index, &msr->data);
1401 return kvm_x86_ops.get_msr_feature(msr);
1406 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1408 struct kvm_msr_entry msr;
1412 r = kvm_get_msr_feature(&msr);
1414 if (r == KVM_MSR_RET_INVALID) {
1415 /* Unconditionally clear the output for simplicity */
1417 if (kvm_msr_ignored_check(vcpu, index, 0, false))
1429 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1431 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1434 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1437 if (efer & (EFER_LME | EFER_LMA) &&
1438 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1441 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1447 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1449 if (efer & efer_reserved_bits)
1452 return __kvm_valid_efer(vcpu, efer);
1454 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1456 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1458 u64 old_efer = vcpu->arch.efer;
1459 u64 efer = msr_info->data;
1462 if (efer & efer_reserved_bits)
1465 if (!msr_info->host_initiated) {
1466 if (!__kvm_valid_efer(vcpu, efer))
1469 if (is_paging(vcpu) &&
1470 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1475 efer |= vcpu->arch.efer & EFER_LMA;
1477 r = kvm_x86_ops.set_efer(vcpu, efer);
1483 /* Update reserved bits */
1484 if ((efer ^ old_efer) & EFER_NX)
1485 kvm_mmu_reset_context(vcpu);
1490 void kvm_enable_efer_bits(u64 mask)
1492 efer_reserved_bits &= ~mask;
1494 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1496 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1498 struct kvm *kvm = vcpu->kvm;
1499 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
1500 u32 count = kvm->arch.msr_filter.count;
1502 bool r = kvm->arch.msr_filter.default_allow;
1505 /* MSR filtering not set up or x2APIC enabled, allow everything */
1506 if (!count || (index >= 0x800 && index <= 0x8ff))
1509 /* Prevent collision with set_msr_filter */
1510 idx = srcu_read_lock(&kvm->srcu);
1512 for (i = 0; i < count; i++) {
1513 u32 start = ranges[i].base;
1514 u32 end = start + ranges[i].nmsrs;
1515 u32 flags = ranges[i].flags;
1516 unsigned long *bitmap = ranges[i].bitmap;
1518 if ((index >= start) && (index < end) && (flags & type)) {
1519 r = !!test_bit(index - start, bitmap);
1524 srcu_read_unlock(&kvm->srcu, idx);
1528 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1531 * Write @data into the MSR specified by @index. Select MSR specific fault
1532 * checks are bypassed if @host_initiated is %true.
1533 * Returns 0 on success, non-0 otherwise.
1534 * Assumes vcpu_load() was already called.
1536 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1537 bool host_initiated)
1539 struct msr_data msr;
1541 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1542 return KVM_MSR_RET_FILTERED;
1547 case MSR_KERNEL_GS_BASE:
1550 if (is_noncanonical_address(data, vcpu))
1553 case MSR_IA32_SYSENTER_EIP:
1554 case MSR_IA32_SYSENTER_ESP:
1556 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1557 * non-canonical address is written on Intel but not on
1558 * AMD (which ignores the top 32-bits, because it does
1559 * not implement 64-bit SYSENTER).
1561 * 64-bit code should hence be able to write a non-canonical
1562 * value on AMD. Making the address canonical ensures that
1563 * vmentry does not fail on Intel after writing a non-canonical
1564 * value, and that something deterministic happens if the guest
1565 * invokes 64-bit SYSENTER.
1567 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1572 msr.host_initiated = host_initiated;
1574 return kvm_x86_ops.set_msr(vcpu, &msr);
1577 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1578 u32 index, u64 data, bool host_initiated)
1580 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1582 if (ret == KVM_MSR_RET_INVALID)
1583 if (kvm_msr_ignored_check(vcpu, index, data, true))
1590 * Read the MSR specified by @index into @data. Select MSR specific fault
1591 * checks are bypassed if @host_initiated is %true.
1592 * Returns 0 on success, non-0 otherwise.
1593 * Assumes vcpu_load() was already called.
1595 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1596 bool host_initiated)
1598 struct msr_data msr;
1601 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1602 return KVM_MSR_RET_FILTERED;
1605 msr.host_initiated = host_initiated;
1607 ret = kvm_x86_ops.get_msr(vcpu, &msr);
1613 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1614 u32 index, u64 *data, bool host_initiated)
1616 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1618 if (ret == KVM_MSR_RET_INVALID) {
1619 /* Unconditionally clear *data for simplicity */
1621 if (kvm_msr_ignored_check(vcpu, index, 0, false))
1628 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1630 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1632 EXPORT_SYMBOL_GPL(kvm_get_msr);
1634 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1636 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1638 EXPORT_SYMBOL_GPL(kvm_set_msr);
1640 static int complete_emulated_msr(struct kvm_vcpu *vcpu, bool is_read)
1642 if (vcpu->run->msr.error) {
1643 kvm_inject_gp(vcpu, 0);
1645 } else if (is_read) {
1646 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1647 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1650 return kvm_skip_emulated_instruction(vcpu);
1653 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1655 return complete_emulated_msr(vcpu, true);
1658 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu)
1660 return complete_emulated_msr(vcpu, false);
1663 static u64 kvm_msr_reason(int r)
1666 case KVM_MSR_RET_INVALID:
1667 return KVM_MSR_EXIT_REASON_UNKNOWN;
1668 case KVM_MSR_RET_FILTERED:
1669 return KVM_MSR_EXIT_REASON_FILTER;
1671 return KVM_MSR_EXIT_REASON_INVAL;
1675 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1676 u32 exit_reason, u64 data,
1677 int (*completion)(struct kvm_vcpu *vcpu),
1680 u64 msr_reason = kvm_msr_reason(r);
1682 /* Check if the user wanted to know about this MSR fault */
1683 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
1686 vcpu->run->exit_reason = exit_reason;
1687 vcpu->run->msr.error = 0;
1688 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
1689 vcpu->run->msr.reason = msr_reason;
1690 vcpu->run->msr.index = index;
1691 vcpu->run->msr.data = data;
1692 vcpu->arch.complete_userspace_io = completion;
1697 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r)
1699 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0,
1700 complete_emulated_rdmsr, r);
1703 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r)
1705 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data,
1706 complete_emulated_wrmsr, r);
1709 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1711 u32 ecx = kvm_rcx_read(vcpu);
1715 r = kvm_get_msr(vcpu, ecx, &data);
1717 /* MSR read failed? See if we should ask user space */
1718 if (r && kvm_get_msr_user_space(vcpu, ecx, r)) {
1719 /* Bounce to user space */
1723 /* MSR read failed? Inject a #GP */
1725 trace_kvm_msr_read_ex(ecx);
1726 kvm_inject_gp(vcpu, 0);
1730 trace_kvm_msr_read(ecx, data);
1732 kvm_rax_write(vcpu, data & -1u);
1733 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1734 return kvm_skip_emulated_instruction(vcpu);
1736 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1738 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1740 u32 ecx = kvm_rcx_read(vcpu);
1741 u64 data = kvm_read_edx_eax(vcpu);
1744 r = kvm_set_msr(vcpu, ecx, data);
1746 /* MSR write failed? See if we should ask user space */
1747 if (r && kvm_set_msr_user_space(vcpu, ecx, data, r))
1748 /* Bounce to user space */
1751 /* Signal all other negative errors to userspace */
1755 /* MSR write failed? Inject a #GP */
1757 trace_kvm_msr_write_ex(ecx, data);
1758 kvm_inject_gp(vcpu, 0);
1762 trace_kvm_msr_write(ecx, data);
1763 return kvm_skip_emulated_instruction(vcpu);
1765 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1767 bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
1769 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
1770 xfer_to_guest_mode_work_pending();
1772 EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request);
1775 * The fast path for frequent and performance sensitive wrmsr emulation,
1776 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1777 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1778 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1779 * other cases which must be called after interrupts are enabled on the host.
1781 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1783 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1786 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1787 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1788 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1789 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1792 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1793 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1794 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1795 trace_kvm_apic_write(APIC_ICR, (u32)data);
1802 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
1804 if (!kvm_can_use_hv_timer(vcpu))
1807 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1811 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1813 u32 msr = kvm_rcx_read(vcpu);
1815 fastpath_t ret = EXIT_FASTPATH_NONE;
1818 case APIC_BASE_MSR + (APIC_ICR >> 4):
1819 data = kvm_read_edx_eax(vcpu);
1820 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
1821 kvm_skip_emulated_instruction(vcpu);
1822 ret = EXIT_FASTPATH_EXIT_HANDLED;
1825 case MSR_IA32_TSCDEADLINE:
1826 data = kvm_read_edx_eax(vcpu);
1827 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
1828 kvm_skip_emulated_instruction(vcpu);
1829 ret = EXIT_FASTPATH_REENTER_GUEST;
1836 if (ret != EXIT_FASTPATH_NONE)
1837 trace_kvm_msr_write(msr, data);
1841 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1844 * Adapt set_msr() to msr_io()'s calling convention
1846 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1848 return kvm_get_msr_ignored_check(vcpu, index, data, true);
1851 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1853 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
1856 #ifdef CONFIG_X86_64
1857 struct pvclock_clock {
1867 struct pvclock_gtod_data {
1870 struct pvclock_clock clock; /* extract of a clocksource struct */
1871 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1877 static struct pvclock_gtod_data pvclock_gtod_data;
1879 static void update_pvclock_gtod(struct timekeeper *tk)
1881 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1883 write_seqcount_begin(&vdata->seq);
1885 /* copy pvclock gtod data */
1886 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
1887 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1888 vdata->clock.mask = tk->tkr_mono.mask;
1889 vdata->clock.mult = tk->tkr_mono.mult;
1890 vdata->clock.shift = tk->tkr_mono.shift;
1891 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
1892 vdata->clock.offset = tk->tkr_mono.base;
1894 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
1895 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1896 vdata->raw_clock.mask = tk->tkr_raw.mask;
1897 vdata->raw_clock.mult = tk->tkr_raw.mult;
1898 vdata->raw_clock.shift = tk->tkr_raw.shift;
1899 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
1900 vdata->raw_clock.offset = tk->tkr_raw.base;
1902 vdata->wall_time_sec = tk->xtime_sec;
1904 vdata->offs_boot = tk->offs_boot;
1906 write_seqcount_end(&vdata->seq);
1909 static s64 get_kvmclock_base_ns(void)
1911 /* Count up from boot time, but with the frequency of the raw clock. */
1912 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1915 static s64 get_kvmclock_base_ns(void)
1917 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
1918 return ktime_get_boottime_ns();
1922 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1926 struct pvclock_wall_clock wc;
1929 kvm->arch.wall_clock = wall_clock;
1934 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1939 ++version; /* first time write, random junk */
1943 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1947 * The guest calculates current wall clock time by adding
1948 * system time (updated by kvm_guest_time_update below) to the
1949 * wall clock specified here. We do the reverse here.
1951 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1953 wc.nsec = do_div(wall_nsec, 1000000000);
1954 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1955 wc.version = version;
1957 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1960 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1963 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
1964 bool old_msr, bool host_initiated)
1966 struct kvm_arch *ka = &vcpu->kvm->arch;
1968 if (vcpu->vcpu_id == 0 && !host_initiated) {
1969 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
1970 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1972 ka->boot_vcpu_runs_old_kvmclock = old_msr;
1975 vcpu->arch.time = system_time;
1976 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
1978 /* we verify if the enable bit is set... */
1979 vcpu->arch.pv_time_enabled = false;
1980 if (!(system_time & 1))
1983 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
1984 &vcpu->arch.pv_time, system_time & ~1ULL,
1985 sizeof(struct pvclock_vcpu_time_info)))
1986 vcpu->arch.pv_time_enabled = true;
1991 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1993 do_shl32_div32(dividend, divisor);
1997 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1998 s8 *pshift, u32 *pmultiplier)
2006 scaled64 = scaled_hz;
2007 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2012 tps32 = (uint32_t)tps64;
2013 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2014 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2022 *pmultiplier = div_frac(scaled64, tps32);
2025 #ifdef CONFIG_X86_64
2026 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2029 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2030 static unsigned long max_tsc_khz;
2032 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2034 u64 v = (u64)khz * (1000000 + ppm);
2039 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2043 /* Guest TSC same frequency as host TSC? */
2045 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2049 /* TSC scaling supported? */
2050 if (!kvm_has_tsc_control) {
2051 if (user_tsc_khz > tsc_khz) {
2052 vcpu->arch.tsc_catchup = 1;
2053 vcpu->arch.tsc_always_catchup = 1;
2056 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2061 /* TSC scaling required - calculate ratio */
2062 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
2063 user_tsc_khz, tsc_khz);
2065 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
2066 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2071 vcpu->arch.tsc_scaling_ratio = ratio;
2075 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2077 u32 thresh_lo, thresh_hi;
2078 int use_scaling = 0;
2080 /* tsc_khz can be zero if TSC calibration fails */
2081 if (user_tsc_khz == 0) {
2082 /* set tsc_scaling_ratio to a safe value */
2083 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2087 /* Compute a scale to convert nanoseconds in TSC cycles */
2088 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2089 &vcpu->arch.virtual_tsc_shift,
2090 &vcpu->arch.virtual_tsc_mult);
2091 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2094 * Compute the variation in TSC rate which is acceptable
2095 * within the range of tolerance and decide if the
2096 * rate being applied is within that bounds of the hardware
2097 * rate. If so, no scaling or compensation need be done.
2099 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2100 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2101 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2102 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2105 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2108 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2110 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2111 vcpu->arch.virtual_tsc_mult,
2112 vcpu->arch.virtual_tsc_shift);
2113 tsc += vcpu->arch.this_tsc_write;
2117 static inline int gtod_is_based_on_tsc(int mode)
2119 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2122 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2124 #ifdef CONFIG_X86_64
2126 struct kvm_arch *ka = &vcpu->kvm->arch;
2127 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2129 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2130 atomic_read(&vcpu->kvm->online_vcpus));
2133 * Once the masterclock is enabled, always perform request in
2134 * order to update it.
2136 * In order to enable masterclock, the host clocksource must be TSC
2137 * and the vcpus need to have matched TSCs. When that happens,
2138 * perform request to enable masterclock.
2140 if (ka->use_master_clock ||
2141 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2142 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2144 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2145 atomic_read(&vcpu->kvm->online_vcpus),
2146 ka->use_master_clock, gtod->clock.vclock_mode);
2151 * Multiply tsc by a fixed point number represented by ratio.
2153 * The most significant 64-N bits (mult) of ratio represent the
2154 * integral part of the fixed point number; the remaining N bits
2155 * (frac) represent the fractional part, ie. ratio represents a fixed
2156 * point number (mult + frac * 2^(-N)).
2158 * N equals to kvm_tsc_scaling_ratio_frac_bits.
2160 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2162 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
2165 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
2168 u64 ratio = vcpu->arch.tsc_scaling_ratio;
2170 if (ratio != kvm_default_tsc_scaling_ratio)
2171 _tsc = __scale_tsc(ratio, tsc);
2175 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2177 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2181 tsc = kvm_scale_tsc(vcpu, rdtsc());
2183 return target_tsc - tsc;
2186 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2188 return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
2190 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2192 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2194 vcpu->arch.l1_tsc_offset = offset;
2195 vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset);
2198 static inline bool kvm_check_tsc_unstable(void)
2200 #ifdef CONFIG_X86_64
2202 * TSC is marked unstable when we're running on Hyper-V,
2203 * 'TSC page' clocksource is good.
2205 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2208 return check_tsc_unstable();
2211 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2213 struct kvm *kvm = vcpu->kvm;
2214 u64 offset, ns, elapsed;
2215 unsigned long flags;
2217 bool already_matched;
2218 bool synchronizing = false;
2220 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2221 offset = kvm_compute_tsc_offset(vcpu, data);
2222 ns = get_kvmclock_base_ns();
2223 elapsed = ns - kvm->arch.last_tsc_nsec;
2225 if (vcpu->arch.virtual_tsc_khz) {
2228 * detection of vcpu initialization -- need to sync
2229 * with other vCPUs. This particularly helps to keep
2230 * kvm_clock stable after CPU hotplug
2232 synchronizing = true;
2234 u64 tsc_exp = kvm->arch.last_tsc_write +
2235 nsec_to_cycles(vcpu, elapsed);
2236 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2238 * Special case: TSC write with a small delta (1 second)
2239 * of virtual cycle time against real time is
2240 * interpreted as an attempt to synchronize the CPU.
2242 synchronizing = data < tsc_exp + tsc_hz &&
2243 data + tsc_hz > tsc_exp;
2248 * For a reliable TSC, we can match TSC offsets, and for an unstable
2249 * TSC, we add elapsed time in this computation. We could let the
2250 * compensation code attempt to catch up if we fall behind, but
2251 * it's better to try to match offsets from the beginning.
2253 if (synchronizing &&
2254 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2255 if (!kvm_check_tsc_unstable()) {
2256 offset = kvm->arch.cur_tsc_offset;
2258 u64 delta = nsec_to_cycles(vcpu, elapsed);
2260 offset = kvm_compute_tsc_offset(vcpu, data);
2263 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2266 * We split periods of matched TSC writes into generations.
2267 * For each generation, we track the original measured
2268 * nanosecond time, offset, and write, so if TSCs are in
2269 * sync, we can match exact offset, and if not, we can match
2270 * exact software computation in compute_guest_tsc()
2272 * These values are tracked in kvm->arch.cur_xxx variables.
2274 kvm->arch.cur_tsc_generation++;
2275 kvm->arch.cur_tsc_nsec = ns;
2276 kvm->arch.cur_tsc_write = data;
2277 kvm->arch.cur_tsc_offset = offset;
2282 * We also track th most recent recorded KHZ, write and time to
2283 * allow the matching interval to be extended at each write.
2285 kvm->arch.last_tsc_nsec = ns;
2286 kvm->arch.last_tsc_write = data;
2287 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2289 vcpu->arch.last_guest_tsc = data;
2291 /* Keep track of which generation this VCPU has synchronized to */
2292 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2293 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2294 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2296 kvm_vcpu_write_tsc_offset(vcpu, offset);
2297 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2299 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2301 kvm->arch.nr_vcpus_matched_tsc = 0;
2302 } else if (!already_matched) {
2303 kvm->arch.nr_vcpus_matched_tsc++;
2306 kvm_track_tsc_matching(vcpu);
2307 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2310 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2313 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2314 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2317 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2319 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2320 WARN_ON(adjustment < 0);
2321 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2322 adjust_tsc_offset_guest(vcpu, adjustment);
2325 #ifdef CONFIG_X86_64
2327 static u64 read_tsc(void)
2329 u64 ret = (u64)rdtsc_ordered();
2330 u64 last = pvclock_gtod_data.clock.cycle_last;
2332 if (likely(ret >= last))
2336 * GCC likes to generate cmov here, but this branch is extremely
2337 * predictable (it's just a function of time and the likely is
2338 * very likely) and there's a data dependence, so force GCC
2339 * to generate a branch instead. I don't barrier() because
2340 * we don't actually need a barrier, and if this function
2341 * ever gets inlined it will generate worse code.
2347 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2353 switch (clock->vclock_mode) {
2354 case VDSO_CLOCKMODE_HVCLOCK:
2355 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2357 if (tsc_pg_val != U64_MAX) {
2358 /* TSC page valid */
2359 *mode = VDSO_CLOCKMODE_HVCLOCK;
2360 v = (tsc_pg_val - clock->cycle_last) &
2363 /* TSC page invalid */
2364 *mode = VDSO_CLOCKMODE_NONE;
2367 case VDSO_CLOCKMODE_TSC:
2368 *mode = VDSO_CLOCKMODE_TSC;
2369 *tsc_timestamp = read_tsc();
2370 v = (*tsc_timestamp - clock->cycle_last) &
2374 *mode = VDSO_CLOCKMODE_NONE;
2377 if (*mode == VDSO_CLOCKMODE_NONE)
2378 *tsc_timestamp = v = 0;
2380 return v * clock->mult;
2383 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2385 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2391 seq = read_seqcount_begin(>od->seq);
2392 ns = gtod->raw_clock.base_cycles;
2393 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2394 ns >>= gtod->raw_clock.shift;
2395 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2396 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2402 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2404 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2410 seq = read_seqcount_begin(>od->seq);
2411 ts->tv_sec = gtod->wall_time_sec;
2412 ns = gtod->clock.base_cycles;
2413 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2414 ns >>= gtod->clock.shift;
2415 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2417 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2423 /* returns true if host is using TSC based clocksource */
2424 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2426 /* checked again under seqlock below */
2427 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2430 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2434 /* returns true if host is using TSC based clocksource */
2435 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2438 /* checked again under seqlock below */
2439 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2442 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2448 * Assuming a stable TSC across physical CPUS, and a stable TSC
2449 * across virtual CPUs, the following condition is possible.
2450 * Each numbered line represents an event visible to both
2451 * CPUs at the next numbered event.
2453 * "timespecX" represents host monotonic time. "tscX" represents
2456 * VCPU0 on CPU0 | VCPU1 on CPU1
2458 * 1. read timespec0,tsc0
2459 * 2. | timespec1 = timespec0 + N
2461 * 3. transition to guest | transition to guest
2462 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2463 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2464 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2466 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2469 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2471 * - 0 < N - M => M < N
2473 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2474 * always the case (the difference between two distinct xtime instances
2475 * might be smaller then the difference between corresponding TSC reads,
2476 * when updating guest vcpus pvclock areas).
2478 * To avoid that problem, do not allow visibility of distinct
2479 * system_timestamp/tsc_timestamp values simultaneously: use a master
2480 * copy of host monotonic time values. Update that master copy
2483 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2487 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2489 #ifdef CONFIG_X86_64
2490 struct kvm_arch *ka = &kvm->arch;
2492 bool host_tsc_clocksource, vcpus_matched;
2494 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2495 atomic_read(&kvm->online_vcpus));
2498 * If the host uses TSC clock, then passthrough TSC as stable
2501 host_tsc_clocksource = kvm_get_time_and_clockread(
2502 &ka->master_kernel_ns,
2503 &ka->master_cycle_now);
2505 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2506 && !ka->backwards_tsc_observed
2507 && !ka->boot_vcpu_runs_old_kvmclock;
2509 if (ka->use_master_clock)
2510 atomic_set(&kvm_guest_has_master_clock, 1);
2512 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2513 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2518 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2520 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2523 static void kvm_gen_update_masterclock(struct kvm *kvm)
2525 #ifdef CONFIG_X86_64
2527 struct kvm_vcpu *vcpu;
2528 struct kvm_arch *ka = &kvm->arch;
2530 spin_lock(&ka->pvclock_gtod_sync_lock);
2531 kvm_make_mclock_inprogress_request(kvm);
2532 /* no guest entries from this point */
2533 pvclock_update_vm_gtod_copy(kvm);
2535 kvm_for_each_vcpu(i, vcpu, kvm)
2536 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2538 /* guest entries allowed */
2539 kvm_for_each_vcpu(i, vcpu, kvm)
2540 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2542 spin_unlock(&ka->pvclock_gtod_sync_lock);
2546 u64 get_kvmclock_ns(struct kvm *kvm)
2548 struct kvm_arch *ka = &kvm->arch;
2549 struct pvclock_vcpu_time_info hv_clock;
2552 spin_lock(&ka->pvclock_gtod_sync_lock);
2553 if (!ka->use_master_clock) {
2554 spin_unlock(&ka->pvclock_gtod_sync_lock);
2555 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2558 hv_clock.tsc_timestamp = ka->master_cycle_now;
2559 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2560 spin_unlock(&ka->pvclock_gtod_sync_lock);
2562 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2565 if (__this_cpu_read(cpu_tsc_khz)) {
2566 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2567 &hv_clock.tsc_shift,
2568 &hv_clock.tsc_to_system_mul);
2569 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2571 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2578 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2580 struct kvm_vcpu_arch *vcpu = &v->arch;
2581 struct pvclock_vcpu_time_info guest_hv_clock;
2583 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2584 &guest_hv_clock, sizeof(guest_hv_clock))))
2587 /* This VCPU is paused, but it's legal for a guest to read another
2588 * VCPU's kvmclock, so we really have to follow the specification where
2589 * it says that version is odd if data is being modified, and even after
2592 * Version field updates must be kept separate. This is because
2593 * kvm_write_guest_cached might use a "rep movs" instruction, and
2594 * writes within a string instruction are weakly ordered. So there
2595 * are three writes overall.
2597 * As a small optimization, only write the version field in the first
2598 * and third write. The vcpu->pv_time cache is still valid, because the
2599 * version field is the first in the struct.
2601 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2603 if (guest_hv_clock.version & 1)
2604 ++guest_hv_clock.version; /* first time write, random junk */
2606 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2607 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2609 sizeof(vcpu->hv_clock.version));
2613 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2614 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2616 if (vcpu->pvclock_set_guest_stopped_request) {
2617 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2618 vcpu->pvclock_set_guest_stopped_request = false;
2621 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2623 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2625 sizeof(vcpu->hv_clock));
2629 vcpu->hv_clock.version++;
2630 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2632 sizeof(vcpu->hv_clock.version));
2635 static int kvm_guest_time_update(struct kvm_vcpu *v)
2637 unsigned long flags, tgt_tsc_khz;
2638 struct kvm_vcpu_arch *vcpu = &v->arch;
2639 struct kvm_arch *ka = &v->kvm->arch;
2641 u64 tsc_timestamp, host_tsc;
2643 bool use_master_clock;
2649 * If the host uses TSC clock, then passthrough TSC as stable
2652 spin_lock(&ka->pvclock_gtod_sync_lock);
2653 use_master_clock = ka->use_master_clock;
2654 if (use_master_clock) {
2655 host_tsc = ka->master_cycle_now;
2656 kernel_ns = ka->master_kernel_ns;
2658 spin_unlock(&ka->pvclock_gtod_sync_lock);
2660 /* Keep irq disabled to prevent changes to the clock */
2661 local_irq_save(flags);
2662 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2663 if (unlikely(tgt_tsc_khz == 0)) {
2664 local_irq_restore(flags);
2665 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2668 if (!use_master_clock) {
2670 kernel_ns = get_kvmclock_base_ns();
2673 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2676 * We may have to catch up the TSC to match elapsed wall clock
2677 * time for two reasons, even if kvmclock is used.
2678 * 1) CPU could have been running below the maximum TSC rate
2679 * 2) Broken TSC compensation resets the base at each VCPU
2680 * entry to avoid unknown leaps of TSC even when running
2681 * again on the same CPU. This may cause apparent elapsed
2682 * time to disappear, and the guest to stand still or run
2685 if (vcpu->tsc_catchup) {
2686 u64 tsc = compute_guest_tsc(v, kernel_ns);
2687 if (tsc > tsc_timestamp) {
2688 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2689 tsc_timestamp = tsc;
2693 local_irq_restore(flags);
2695 /* With all the info we got, fill in the values */
2697 if (kvm_has_tsc_control)
2698 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2700 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2701 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2702 &vcpu->hv_clock.tsc_shift,
2703 &vcpu->hv_clock.tsc_to_system_mul);
2704 vcpu->hw_tsc_khz = tgt_tsc_khz;
2707 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2708 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2709 vcpu->last_guest_tsc = tsc_timestamp;
2711 /* If the host uses TSC clocksource, then it is stable */
2713 if (use_master_clock)
2714 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2716 vcpu->hv_clock.flags = pvclock_flags;
2718 if (vcpu->pv_time_enabled)
2719 kvm_setup_pvclock_page(v);
2720 if (v == kvm_get_vcpu(v->kvm, 0))
2721 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2726 * kvmclock updates which are isolated to a given vcpu, such as
2727 * vcpu->cpu migration, should not allow system_timestamp from
2728 * the rest of the vcpus to remain static. Otherwise ntp frequency
2729 * correction applies to one vcpu's system_timestamp but not
2732 * So in those cases, request a kvmclock update for all vcpus.
2733 * We need to rate-limit these requests though, as they can
2734 * considerably slow guests that have a large number of vcpus.
2735 * The time for a remote vcpu to update its kvmclock is bound
2736 * by the delay we use to rate-limit the updates.
2739 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2741 static void kvmclock_update_fn(struct work_struct *work)
2744 struct delayed_work *dwork = to_delayed_work(work);
2745 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2746 kvmclock_update_work);
2747 struct kvm *kvm = container_of(ka, struct kvm, arch);
2748 struct kvm_vcpu *vcpu;
2750 kvm_for_each_vcpu(i, vcpu, kvm) {
2751 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2752 kvm_vcpu_kick(vcpu);
2756 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2758 struct kvm *kvm = v->kvm;
2760 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2761 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2762 KVMCLOCK_UPDATE_DELAY);
2765 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2767 static void kvmclock_sync_fn(struct work_struct *work)
2769 struct delayed_work *dwork = to_delayed_work(work);
2770 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2771 kvmclock_sync_work);
2772 struct kvm *kvm = container_of(ka, struct kvm, arch);
2774 if (!kvmclock_periodic_sync)
2777 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2778 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2779 KVMCLOCK_SYNC_PERIOD);
2783 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2785 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2787 /* McStatusWrEn enabled? */
2788 if (guest_cpuid_is_amd_or_hygon(vcpu))
2789 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2794 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2796 u64 mcg_cap = vcpu->arch.mcg_cap;
2797 unsigned bank_num = mcg_cap & 0xff;
2798 u32 msr = msr_info->index;
2799 u64 data = msr_info->data;
2802 case MSR_IA32_MCG_STATUS:
2803 vcpu->arch.mcg_status = data;
2805 case MSR_IA32_MCG_CTL:
2806 if (!(mcg_cap & MCG_CTL_P) &&
2807 (data || !msr_info->host_initiated))
2809 if (data != 0 && data != ~(u64)0)
2811 vcpu->arch.mcg_ctl = data;
2814 if (msr >= MSR_IA32_MC0_CTL &&
2815 msr < MSR_IA32_MCx_CTL(bank_num)) {
2816 u32 offset = array_index_nospec(
2817 msr - MSR_IA32_MC0_CTL,
2818 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2820 /* only 0 or all 1s can be written to IA32_MCi_CTL
2821 * some Linux kernels though clear bit 10 in bank 4 to
2822 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2823 * this to avoid an uncatched #GP in the guest
2825 if ((offset & 0x3) == 0 &&
2826 data != 0 && (data | (1 << 10)) != ~(u64)0)
2830 if (!msr_info->host_initiated &&
2831 (offset & 0x3) == 1 && data != 0) {
2832 if (!can_set_mci_status(vcpu))
2836 vcpu->arch.mce_banks[offset] = data;
2844 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2846 struct kvm *kvm = vcpu->kvm;
2847 int lm = is_long_mode(vcpu);
2848 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2849 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2850 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2851 : kvm->arch.xen_hvm_config.blob_size_32;
2852 u32 page_num = data & ~PAGE_MASK;
2853 u64 page_addr = data & PAGE_MASK;
2856 if (page_num >= blob_size)
2859 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2861 return PTR_ERR(page);
2863 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) {
2870 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
2872 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
2874 return (vcpu->arch.apf.msr_en_val & mask) == mask;
2877 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2879 gpa_t gpa = data & ~0x3f;
2881 /* Bits 4:5 are reserved, Should be zero */
2885 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
2886 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
2889 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
2890 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
2893 if (!lapic_in_kernel(vcpu))
2894 return data ? 1 : 0;
2896 vcpu->arch.apf.msr_en_val = data;
2898 if (!kvm_pv_async_pf_enabled(vcpu)) {
2899 kvm_clear_async_pf_completion_queue(vcpu);
2900 kvm_async_pf_hash_reset(vcpu);
2904 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2908 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2909 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2911 kvm_async_pf_wakeup_all(vcpu);
2916 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
2918 /* Bits 8-63 are reserved */
2922 if (!lapic_in_kernel(vcpu))
2925 vcpu->arch.apf.msr_int_val = data;
2927 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
2932 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2934 vcpu->arch.pv_time_enabled = false;
2935 vcpu->arch.time = 0;
2938 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
2940 ++vcpu->stat.tlb_flush;
2941 kvm_x86_ops.tlb_flush_all(vcpu);
2944 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
2946 ++vcpu->stat.tlb_flush;
2947 kvm_x86_ops.tlb_flush_guest(vcpu);
2950 static void record_steal_time(struct kvm_vcpu *vcpu)
2952 struct kvm_host_map map;
2953 struct kvm_steal_time *st;
2955 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2958 /* -EAGAIN is returned in atomic context so we can just return. */
2959 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2960 &map, &vcpu->arch.st.cache, false))
2964 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2967 * Doing a TLB flush here, on the guest's behalf, can avoid
2970 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
2971 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2972 st->preempted & KVM_VCPU_FLUSH_TLB);
2973 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2974 kvm_vcpu_flush_tlb_guest(vcpu);
2977 vcpu->arch.st.preempted = 0;
2979 if (st->version & 1)
2980 st->version += 1; /* first time write, random junk */
2986 st->steal += current->sched_info.run_delay -
2987 vcpu->arch.st.last_steal;
2988 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2994 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2997 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3000 u32 msr = msr_info->index;
3001 u64 data = msr_info->data;
3004 case MSR_AMD64_NB_CFG:
3005 case MSR_IA32_UCODE_WRITE:
3006 case MSR_VM_HSAVE_PA:
3007 case MSR_AMD64_PATCH_LOADER:
3008 case MSR_AMD64_BU_CFG2:
3009 case MSR_AMD64_DC_CFG:
3010 case MSR_F15H_EX_CFG:
3013 case MSR_IA32_UCODE_REV:
3014 if (msr_info->host_initiated)
3015 vcpu->arch.microcode_version = data;
3017 case MSR_IA32_ARCH_CAPABILITIES:
3018 if (!msr_info->host_initiated)
3020 vcpu->arch.arch_capabilities = data;
3022 case MSR_IA32_PERF_CAPABILITIES: {
3023 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
3025 if (!msr_info->host_initiated)
3027 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent))
3029 if (data & ~msr_ent.data)
3032 vcpu->arch.perf_capabilities = data;
3037 return set_efer(vcpu, msr_info);
3039 data &= ~(u64)0x40; /* ignore flush filter disable */
3040 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3041 data &= ~(u64)0x8; /* ignore TLB cache disable */
3043 /* Handle McStatusWrEn */
3044 if (data == BIT_ULL(18)) {
3045 vcpu->arch.msr_hwcr = data;
3046 } else if (data != 0) {
3047 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3052 case MSR_FAM10H_MMIO_CONF_BASE:
3054 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3059 case MSR_IA32_DEBUGCTLMSR:
3061 /* We support the non-activated case already */
3063 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
3064 /* Values other than LBR and BTF are vendor-specific,
3065 thus reserved and should throw a #GP */
3067 } else if (report_ignored_msrs)
3068 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
3071 case 0x200 ... 0x2ff:
3072 return kvm_mtrr_set_msr(vcpu, msr, data);
3073 case MSR_IA32_APICBASE:
3074 return kvm_set_apic_base(vcpu, msr_info);
3075 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3076 return kvm_x2apic_msr_write(vcpu, msr, data);
3077 case MSR_IA32_TSCDEADLINE:
3078 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3080 case MSR_IA32_TSC_ADJUST:
3081 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3082 if (!msr_info->host_initiated) {
3083 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3084 adjust_tsc_offset_guest(vcpu, adj);
3086 vcpu->arch.ia32_tsc_adjust_msr = data;
3089 case MSR_IA32_MISC_ENABLE:
3090 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3091 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3092 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3094 vcpu->arch.ia32_misc_enable_msr = data;
3095 kvm_update_cpuid_runtime(vcpu);
3097 vcpu->arch.ia32_misc_enable_msr = data;
3100 case MSR_IA32_SMBASE:
3101 if (!msr_info->host_initiated)
3103 vcpu->arch.smbase = data;
3105 case MSR_IA32_POWER_CTL:
3106 vcpu->arch.msr_ia32_power_ctl = data;
3109 if (msr_info->host_initiated) {
3110 kvm_synchronize_tsc(vcpu, data);
3112 u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3113 adjust_tsc_offset_guest(vcpu, adj);
3114 vcpu->arch.ia32_tsc_adjust_msr += adj;
3118 if (!msr_info->host_initiated &&
3119 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3122 * KVM supports exposing PT to the guest, but does not support
3123 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3124 * XSAVES/XRSTORS to save/restore PT MSRs.
3126 if (data & ~supported_xss)
3128 vcpu->arch.ia32_xss = data;
3131 if (!msr_info->host_initiated)
3133 vcpu->arch.smi_count = data;
3135 case MSR_KVM_WALL_CLOCK_NEW:
3136 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3139 kvm_write_wall_clock(vcpu->kvm, data);
3141 case MSR_KVM_WALL_CLOCK:
3142 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3145 kvm_write_wall_clock(vcpu->kvm, data);
3147 case MSR_KVM_SYSTEM_TIME_NEW:
3148 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3151 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3153 case MSR_KVM_SYSTEM_TIME:
3154 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3157 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3159 case MSR_KVM_ASYNC_PF_EN:
3160 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3163 if (kvm_pv_enable_async_pf(vcpu, data))
3166 case MSR_KVM_ASYNC_PF_INT:
3167 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3170 if (kvm_pv_enable_async_pf_int(vcpu, data))
3173 case MSR_KVM_ASYNC_PF_ACK:
3174 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3177 vcpu->arch.apf.pageready_pending = false;
3178 kvm_check_async_pf_completion(vcpu);
3181 case MSR_KVM_STEAL_TIME:
3182 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3185 if (unlikely(!sched_info_on()))
3188 if (data & KVM_STEAL_RESERVED_MASK)
3191 vcpu->arch.st.msr_val = data;
3193 if (!(data & KVM_MSR_ENABLED))
3196 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3199 case MSR_KVM_PV_EOI_EN:
3200 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3203 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
3207 case MSR_KVM_POLL_CONTROL:
3208 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3211 /* only enable bit supported */
3212 if (data & (-1ULL << 1))
3215 vcpu->arch.msr_kvm_poll_control = data;
3218 case MSR_IA32_MCG_CTL:
3219 case MSR_IA32_MCG_STATUS:
3220 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3221 return set_msr_mce(vcpu, msr_info);
3223 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3224 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3227 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3228 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3229 if (kvm_pmu_is_valid_msr(vcpu, msr))
3230 return kvm_pmu_set_msr(vcpu, msr_info);
3232 if (pr || data != 0)
3233 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3234 "0x%x data 0x%llx\n", msr, data);
3236 case MSR_K7_CLK_CTL:
3238 * Ignore all writes to this no longer documented MSR.
3239 * Writes are only relevant for old K7 processors,
3240 * all pre-dating SVM, but a recommended workaround from
3241 * AMD for these chips. It is possible to specify the
3242 * affected processor models on the command line, hence
3243 * the need to ignore the workaround.
3246 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3247 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3248 case HV_X64_MSR_SYNDBG_OPTIONS:
3249 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3250 case HV_X64_MSR_CRASH_CTL:
3251 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3252 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3253 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3254 case HV_X64_MSR_TSC_EMULATION_STATUS:
3255 return kvm_hv_set_msr_common(vcpu, msr, data,
3256 msr_info->host_initiated);
3257 case MSR_IA32_BBL_CR_CTL3:
3258 /* Drop writes to this legacy MSR -- see rdmsr
3259 * counterpart for further detail.
3261 if (report_ignored_msrs)
3262 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3265 case MSR_AMD64_OSVW_ID_LENGTH:
3266 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3268 vcpu->arch.osvw.length = data;
3270 case MSR_AMD64_OSVW_STATUS:
3271 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3273 vcpu->arch.osvw.status = data;
3275 case MSR_PLATFORM_INFO:
3276 if (!msr_info->host_initiated ||
3277 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3278 cpuid_fault_enabled(vcpu)))
3280 vcpu->arch.msr_platform_info = data;
3282 case MSR_MISC_FEATURES_ENABLES:
3283 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3284 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3285 !supports_cpuid_fault(vcpu)))
3287 vcpu->arch.msr_misc_features_enables = data;
3290 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
3291 return xen_hvm_config(vcpu, data);
3292 if (kvm_pmu_is_valid_msr(vcpu, msr))
3293 return kvm_pmu_set_msr(vcpu, msr_info);
3294 return KVM_MSR_RET_INVALID;
3298 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3300 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3303 u64 mcg_cap = vcpu->arch.mcg_cap;
3304 unsigned bank_num = mcg_cap & 0xff;
3307 case MSR_IA32_P5_MC_ADDR:
3308 case MSR_IA32_P5_MC_TYPE:
3311 case MSR_IA32_MCG_CAP:
3312 data = vcpu->arch.mcg_cap;
3314 case MSR_IA32_MCG_CTL:
3315 if (!(mcg_cap & MCG_CTL_P) && !host)
3317 data = vcpu->arch.mcg_ctl;
3319 case MSR_IA32_MCG_STATUS:
3320 data = vcpu->arch.mcg_status;
3323 if (msr >= MSR_IA32_MC0_CTL &&
3324 msr < MSR_IA32_MCx_CTL(bank_num)) {
3325 u32 offset = array_index_nospec(
3326 msr - MSR_IA32_MC0_CTL,
3327 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3329 data = vcpu->arch.mce_banks[offset];
3338 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3340 switch (msr_info->index) {
3341 case MSR_IA32_PLATFORM_ID:
3342 case MSR_IA32_EBL_CR_POWERON:
3343 case MSR_IA32_DEBUGCTLMSR:
3344 case MSR_IA32_LASTBRANCHFROMIP:
3345 case MSR_IA32_LASTBRANCHTOIP:
3346 case MSR_IA32_LASTINTFROMIP:
3347 case MSR_IA32_LASTINTTOIP:
3349 case MSR_K8_TSEG_ADDR:
3350 case MSR_K8_TSEG_MASK:
3351 case MSR_VM_HSAVE_PA:
3352 case MSR_K8_INT_PENDING_MSG:
3353 case MSR_AMD64_NB_CFG:
3354 case MSR_FAM10H_MMIO_CONF_BASE:
3355 case MSR_AMD64_BU_CFG2:
3356 case MSR_IA32_PERF_CTL:
3357 case MSR_AMD64_DC_CFG:
3358 case MSR_F15H_EX_CFG:
3360 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3361 * limit) MSRs. Just return 0, as we do not want to expose the host
3362 * data here. Do not conditionalize this on CPUID, as KVM does not do
3363 * so for existing CPU-specific MSRs.
3365 case MSR_RAPL_POWER_UNIT:
3366 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3367 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3368 case MSR_PKG_ENERGY_STATUS: /* Total package */
3369 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3372 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3373 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3374 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3375 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3376 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3377 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3378 return kvm_pmu_get_msr(vcpu, msr_info);
3381 case MSR_IA32_UCODE_REV:
3382 msr_info->data = vcpu->arch.microcode_version;
3384 case MSR_IA32_ARCH_CAPABILITIES:
3385 if (!msr_info->host_initiated &&
3386 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3388 msr_info->data = vcpu->arch.arch_capabilities;
3390 case MSR_IA32_PERF_CAPABILITIES:
3391 if (!msr_info->host_initiated &&
3392 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3394 msr_info->data = vcpu->arch.perf_capabilities;
3396 case MSR_IA32_POWER_CTL:
3397 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3399 case MSR_IA32_TSC: {
3401 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
3402 * even when not intercepted. AMD manual doesn't explicitly
3403 * state this but appears to behave the same.
3405 * On userspace reads and writes, however, we unconditionally
3406 * return L1's TSC value to ensure backwards-compatible
3407 * behavior for migration.
3409 u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset :
3410 vcpu->arch.tsc_offset;
3412 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset;
3416 case 0x200 ... 0x2ff:
3417 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3418 case 0xcd: /* fsb frequency */
3422 * MSR_EBC_FREQUENCY_ID
3423 * Conservative value valid for even the basic CPU models.
3424 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3425 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3426 * and 266MHz for model 3, or 4. Set Core Clock
3427 * Frequency to System Bus Frequency Ratio to 1 (bits
3428 * 31:24) even though these are only valid for CPU
3429 * models > 2, however guests may end up dividing or
3430 * multiplying by zero otherwise.
3432 case MSR_EBC_FREQUENCY_ID:
3433 msr_info->data = 1 << 24;
3435 case MSR_IA32_APICBASE:
3436 msr_info->data = kvm_get_apic_base(vcpu);
3438 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3439 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3440 case MSR_IA32_TSCDEADLINE:
3441 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3443 case MSR_IA32_TSC_ADJUST:
3444 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3446 case MSR_IA32_MISC_ENABLE:
3447 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3449 case MSR_IA32_SMBASE:
3450 if (!msr_info->host_initiated)
3452 msr_info->data = vcpu->arch.smbase;
3455 msr_info->data = vcpu->arch.smi_count;
3457 case MSR_IA32_PERF_STATUS:
3458 /* TSC increment by tick */
3459 msr_info->data = 1000ULL;
3460 /* CPU multiplier */
3461 msr_info->data |= (((uint64_t)4ULL) << 40);
3464 msr_info->data = vcpu->arch.efer;
3466 case MSR_KVM_WALL_CLOCK:
3467 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3470 msr_info->data = vcpu->kvm->arch.wall_clock;
3472 case MSR_KVM_WALL_CLOCK_NEW:
3473 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3476 msr_info->data = vcpu->kvm->arch.wall_clock;
3478 case MSR_KVM_SYSTEM_TIME:
3479 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3482 msr_info->data = vcpu->arch.time;
3484 case MSR_KVM_SYSTEM_TIME_NEW:
3485 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3488 msr_info->data = vcpu->arch.time;
3490 case MSR_KVM_ASYNC_PF_EN:
3491 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3494 msr_info->data = vcpu->arch.apf.msr_en_val;
3496 case MSR_KVM_ASYNC_PF_INT:
3497 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3500 msr_info->data = vcpu->arch.apf.msr_int_val;
3502 case MSR_KVM_ASYNC_PF_ACK:
3503 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3508 case MSR_KVM_STEAL_TIME:
3509 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3512 msr_info->data = vcpu->arch.st.msr_val;
3514 case MSR_KVM_PV_EOI_EN:
3515 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3518 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3520 case MSR_KVM_POLL_CONTROL:
3521 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3524 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3526 case MSR_IA32_P5_MC_ADDR:
3527 case MSR_IA32_P5_MC_TYPE:
3528 case MSR_IA32_MCG_CAP:
3529 case MSR_IA32_MCG_CTL:
3530 case MSR_IA32_MCG_STATUS:
3531 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3532 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3533 msr_info->host_initiated);
3535 if (!msr_info->host_initiated &&
3536 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3538 msr_info->data = vcpu->arch.ia32_xss;
3540 case MSR_K7_CLK_CTL:
3542 * Provide expected ramp-up count for K7. All other
3543 * are set to zero, indicating minimum divisors for
3546 * This prevents guest kernels on AMD host with CPU
3547 * type 6, model 8 and higher from exploding due to
3548 * the rdmsr failing.
3550 msr_info->data = 0x20000000;
3552 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3553 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3554 case HV_X64_MSR_SYNDBG_OPTIONS:
3555 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3556 case HV_X64_MSR_CRASH_CTL:
3557 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3558 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3559 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3560 case HV_X64_MSR_TSC_EMULATION_STATUS:
3561 return kvm_hv_get_msr_common(vcpu,
3562 msr_info->index, &msr_info->data,
3563 msr_info->host_initiated);
3564 case MSR_IA32_BBL_CR_CTL3:
3565 /* This legacy MSR exists but isn't fully documented in current
3566 * silicon. It is however accessed by winxp in very narrow
3567 * scenarios where it sets bit #19, itself documented as
3568 * a "reserved" bit. Best effort attempt to source coherent
3569 * read data here should the balance of the register be
3570 * interpreted by the guest:
3572 * L2 cache control register 3: 64GB range, 256KB size,
3573 * enabled, latency 0x1, configured
3575 msr_info->data = 0xbe702111;
3577 case MSR_AMD64_OSVW_ID_LENGTH:
3578 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3580 msr_info->data = vcpu->arch.osvw.length;
3582 case MSR_AMD64_OSVW_STATUS:
3583 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3585 msr_info->data = vcpu->arch.osvw.status;
3587 case MSR_PLATFORM_INFO:
3588 if (!msr_info->host_initiated &&
3589 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3591 msr_info->data = vcpu->arch.msr_platform_info;
3593 case MSR_MISC_FEATURES_ENABLES:
3594 msr_info->data = vcpu->arch.msr_misc_features_enables;
3597 msr_info->data = vcpu->arch.msr_hwcr;
3600 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3601 return kvm_pmu_get_msr(vcpu, msr_info);
3602 return KVM_MSR_RET_INVALID;
3606 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3609 * Read or write a bunch of msrs. All parameters are kernel addresses.
3611 * @return number of msrs set successfully.
3613 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3614 struct kvm_msr_entry *entries,
3615 int (*do_msr)(struct kvm_vcpu *vcpu,
3616 unsigned index, u64 *data))
3620 for (i = 0; i < msrs->nmsrs; ++i)
3621 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3628 * Read or write a bunch of msrs. Parameters are user addresses.
3630 * @return number of msrs set successfully.
3632 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3633 int (*do_msr)(struct kvm_vcpu *vcpu,
3634 unsigned index, u64 *data),
3637 struct kvm_msrs msrs;
3638 struct kvm_msr_entry *entries;
3643 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3647 if (msrs.nmsrs >= MAX_IO_MSRS)
3650 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3651 entries = memdup_user(user_msrs->entries, size);
3652 if (IS_ERR(entries)) {
3653 r = PTR_ERR(entries);
3657 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3662 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3673 static inline bool kvm_can_mwait_in_guest(void)
3675 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3676 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3677 boot_cpu_has(X86_FEATURE_ARAT);
3680 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
3681 struct kvm_cpuid2 __user *cpuid_arg)
3683 struct kvm_cpuid2 cpuid;
3687 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3690 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3695 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3701 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3706 case KVM_CAP_IRQCHIP:
3708 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3709 case KVM_CAP_SET_TSS_ADDR:
3710 case KVM_CAP_EXT_CPUID:
3711 case KVM_CAP_EXT_EMUL_CPUID:
3712 case KVM_CAP_CLOCKSOURCE:
3714 case KVM_CAP_NOP_IO_DELAY:
3715 case KVM_CAP_MP_STATE:
3716 case KVM_CAP_SYNC_MMU:
3717 case KVM_CAP_USER_NMI:
3718 case KVM_CAP_REINJECT_CONTROL:
3719 case KVM_CAP_IRQ_INJECT_STATUS:
3720 case KVM_CAP_IOEVENTFD:
3721 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3723 case KVM_CAP_PIT_STATE2:
3724 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3725 case KVM_CAP_XEN_HVM:
3726 case KVM_CAP_VCPU_EVENTS:
3727 case KVM_CAP_HYPERV:
3728 case KVM_CAP_HYPERV_VAPIC:
3729 case KVM_CAP_HYPERV_SPIN:
3730 case KVM_CAP_HYPERV_SYNIC:
3731 case KVM_CAP_HYPERV_SYNIC2:
3732 case KVM_CAP_HYPERV_VP_INDEX:
3733 case KVM_CAP_HYPERV_EVENTFD:
3734 case KVM_CAP_HYPERV_TLBFLUSH:
3735 case KVM_CAP_HYPERV_SEND_IPI:
3736 case KVM_CAP_HYPERV_CPUID:
3737 case KVM_CAP_SYS_HYPERV_CPUID:
3738 case KVM_CAP_PCI_SEGMENT:
3739 case KVM_CAP_DEBUGREGS:
3740 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3742 case KVM_CAP_ASYNC_PF:
3743 case KVM_CAP_ASYNC_PF_INT:
3744 case KVM_CAP_GET_TSC_KHZ:
3745 case KVM_CAP_KVMCLOCK_CTRL:
3746 case KVM_CAP_READONLY_MEM:
3747 case KVM_CAP_HYPERV_TIME:
3748 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3749 case KVM_CAP_TSC_DEADLINE_TIMER:
3750 case KVM_CAP_DISABLE_QUIRKS:
3751 case KVM_CAP_SET_BOOT_CPU_ID:
3752 case KVM_CAP_SPLIT_IRQCHIP:
3753 case KVM_CAP_IMMEDIATE_EXIT:
3754 case KVM_CAP_PMU_EVENT_FILTER:
3755 case KVM_CAP_GET_MSR_FEATURES:
3756 case KVM_CAP_MSR_PLATFORM_INFO:
3757 case KVM_CAP_EXCEPTION_PAYLOAD:
3758 case KVM_CAP_SET_GUEST_DEBUG:
3759 case KVM_CAP_LAST_CPU:
3760 case KVM_CAP_X86_USER_SPACE_MSR:
3761 case KVM_CAP_X86_MSR_FILTER:
3762 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
3765 case KVM_CAP_SYNC_REGS:
3766 r = KVM_SYNC_X86_VALID_FIELDS;
3768 case KVM_CAP_ADJUST_CLOCK:
3769 r = KVM_CLOCK_TSC_STABLE;
3771 case KVM_CAP_X86_DISABLE_EXITS:
3772 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3773 KVM_X86_DISABLE_EXITS_CSTATE;
3774 if(kvm_can_mwait_in_guest())
3775 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3777 case KVM_CAP_X86_SMM:
3778 /* SMBASE is usually relocated above 1M on modern chipsets,
3779 * and SMM handlers might indeed rely on 4G segment limits,
3780 * so do not report SMM to be available if real mode is
3781 * emulated via vm86 mode. Still, do not go to great lengths
3782 * to avoid userspace's usage of the feature, because it is a
3783 * fringe case that is not enabled except via specific settings
3784 * of the module parameters.
3786 r = kvm_x86_ops.has_emulated_msr(MSR_IA32_SMBASE);
3789 r = !kvm_x86_ops.cpu_has_accelerated_tpr();
3791 case KVM_CAP_NR_VCPUS:
3792 r = KVM_SOFT_MAX_VCPUS;
3794 case KVM_CAP_MAX_VCPUS:
3797 case KVM_CAP_MAX_VCPU_ID:
3798 r = KVM_MAX_VCPU_ID;
3800 case KVM_CAP_PV_MMU: /* obsolete */
3804 r = KVM_MAX_MCE_BANKS;
3807 r = boot_cpu_has(X86_FEATURE_XSAVE);
3809 case KVM_CAP_TSC_CONTROL:
3810 r = kvm_has_tsc_control;
3812 case KVM_CAP_X2APIC_API:
3813 r = KVM_X2APIC_API_VALID_FLAGS;
3815 case KVM_CAP_NESTED_STATE:
3816 r = kvm_x86_ops.nested_ops->get_state ?
3817 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
3819 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3820 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3822 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3823 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
3825 case KVM_CAP_SMALLER_MAXPHYADDR:
3826 r = (int) allow_smaller_maxphyaddr;
3828 case KVM_CAP_STEAL_TIME:
3829 r = sched_info_on();
3838 long kvm_arch_dev_ioctl(struct file *filp,
3839 unsigned int ioctl, unsigned long arg)
3841 void __user *argp = (void __user *)arg;
3845 case KVM_GET_MSR_INDEX_LIST: {
3846 struct kvm_msr_list __user *user_msr_list = argp;
3847 struct kvm_msr_list msr_list;
3851 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3854 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3855 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3858 if (n < msr_list.nmsrs)
3861 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3862 num_msrs_to_save * sizeof(u32)))
3864 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3866 num_emulated_msrs * sizeof(u32)))
3871 case KVM_GET_SUPPORTED_CPUID:
3872 case KVM_GET_EMULATED_CPUID: {
3873 struct kvm_cpuid2 __user *cpuid_arg = argp;
3874 struct kvm_cpuid2 cpuid;
3877 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3880 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3886 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3891 case KVM_X86_GET_MCE_CAP_SUPPORTED:
3893 if (copy_to_user(argp, &kvm_mce_cap_supported,
3894 sizeof(kvm_mce_cap_supported)))
3898 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3899 struct kvm_msr_list __user *user_msr_list = argp;
3900 struct kvm_msr_list msr_list;
3904 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3907 msr_list.nmsrs = num_msr_based_features;
3908 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3911 if (n < msr_list.nmsrs)
3914 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3915 num_msr_based_features * sizeof(u32)))
3921 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3923 case KVM_GET_SUPPORTED_HV_CPUID:
3924 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
3934 static void wbinvd_ipi(void *garbage)
3939 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3941 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3944 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3946 /* Address WBINVD may be executed by guest */
3947 if (need_emulate_wbinvd(vcpu)) {
3948 if (kvm_x86_ops.has_wbinvd_exit())
3949 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3950 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3951 smp_call_function_single(vcpu->cpu,
3952 wbinvd_ipi, NULL, 1);
3955 kvm_x86_ops.vcpu_load(vcpu, cpu);
3957 /* Save host pkru register if supported */
3958 vcpu->arch.host_pkru = read_pkru();
3960 /* Apply any externally detected TSC adjustments (due to suspend) */
3961 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3962 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3963 vcpu->arch.tsc_offset_adjustment = 0;
3964 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3967 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3968 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3969 rdtsc() - vcpu->arch.last_host_tsc;
3971 mark_tsc_unstable("KVM discovered backwards TSC");
3973 if (kvm_check_tsc_unstable()) {
3974 u64 offset = kvm_compute_tsc_offset(vcpu,
3975 vcpu->arch.last_guest_tsc);
3976 kvm_vcpu_write_tsc_offset(vcpu, offset);
3977 vcpu->arch.tsc_catchup = 1;
3980 if (kvm_lapic_hv_timer_in_use(vcpu))
3981 kvm_lapic_restart_hv_timer(vcpu);
3984 * On a host with synchronized TSC, there is no need to update
3985 * kvmclock on vcpu->cpu migration
3987 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3988 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3989 if (vcpu->cpu != cpu)
3990 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3994 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3997 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3999 struct kvm_host_map map;
4000 struct kvm_steal_time *st;
4002 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4005 if (vcpu->arch.st.preempted)
4008 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
4009 &vcpu->arch.st.cache, true))
4013 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
4015 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4017 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
4020 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4024 if (vcpu->preempted)
4025 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu);
4028 * Disable page faults because we're in atomic context here.
4029 * kvm_write_guest_offset_cached() would call might_fault()
4030 * that relies on pagefault_disable() to tell if there's a
4031 * bug. NOTE: the write to guest memory may not go through if
4032 * during postcopy live migration or if there's heavy guest
4035 pagefault_disable();
4037 * kvm_memslots() will be called by
4038 * kvm_write_guest_offset_cached() so take the srcu lock.
4040 idx = srcu_read_lock(&vcpu->kvm->srcu);
4041 kvm_steal_time_set_preempted(vcpu);
4042 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4044 kvm_x86_ops.vcpu_put(vcpu);
4045 vcpu->arch.last_host_tsc = rdtsc();
4047 * If userspace has set any breakpoints or watchpoints, dr6 is restored
4048 * on every vmexit, but if not, we might have a stale dr6 from the
4049 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
4054 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4055 struct kvm_lapic_state *s)
4057 if (vcpu->arch.apicv_active)
4058 kvm_x86_ops.sync_pir_to_irr(vcpu);
4060 return kvm_apic_get_state(vcpu, s);
4063 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4064 struct kvm_lapic_state *s)
4068 r = kvm_apic_set_state(vcpu, s);
4071 update_cr8_intercept(vcpu);
4076 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4078 return (!lapic_in_kernel(vcpu) ||
4079 kvm_apic_accept_pic_intr(vcpu));
4083 * if userspace requested an interrupt window, check that the
4084 * interrupt window is open.
4086 * No need to exit to userspace if we already have an interrupt queued.
4088 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4090 return kvm_arch_interrupt_allowed(vcpu) &&
4091 !kvm_cpu_has_interrupt(vcpu) &&
4092 !kvm_event_needs_reinjection(vcpu) &&
4093 kvm_cpu_accept_dm_intr(vcpu);
4096 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4097 struct kvm_interrupt *irq)
4099 if (irq->irq >= KVM_NR_INTERRUPTS)
4102 if (!irqchip_in_kernel(vcpu->kvm)) {
4103 kvm_queue_interrupt(vcpu, irq->irq, false);
4104 kvm_make_request(KVM_REQ_EVENT, vcpu);
4109 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4110 * fail for in-kernel 8259.
4112 if (pic_in_kernel(vcpu->kvm))
4115 if (vcpu->arch.pending_external_vector != -1)
4118 vcpu->arch.pending_external_vector = irq->irq;
4119 kvm_make_request(KVM_REQ_EVENT, vcpu);
4123 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4125 kvm_inject_nmi(vcpu);
4130 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
4132 kvm_make_request(KVM_REQ_SMI, vcpu);
4137 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4138 struct kvm_tpr_access_ctl *tac)
4142 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4146 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4150 unsigned bank_num = mcg_cap & 0xff, bank;
4153 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4155 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
4158 vcpu->arch.mcg_cap = mcg_cap;
4159 /* Init IA32_MCG_CTL to all 1s */
4160 if (mcg_cap & MCG_CTL_P)
4161 vcpu->arch.mcg_ctl = ~(u64)0;
4162 /* Init IA32_MCi_CTL to all 1s */
4163 for (bank = 0; bank < bank_num; bank++)
4164 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4166 kvm_x86_ops.setup_mce(vcpu);
4171 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4172 struct kvm_x86_mce *mce)
4174 u64 mcg_cap = vcpu->arch.mcg_cap;
4175 unsigned bank_num = mcg_cap & 0xff;
4176 u64 *banks = vcpu->arch.mce_banks;
4178 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
4181 * if IA32_MCG_CTL is not all 1s, the uncorrected error
4182 * reporting is disabled
4184 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
4185 vcpu->arch.mcg_ctl != ~(u64)0)
4187 banks += 4 * mce->bank;
4189 * if IA32_MCi_CTL is not all 1s, the uncorrected error
4190 * reporting is disabled for the bank
4192 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
4194 if (mce->status & MCI_STATUS_UC) {
4195 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
4196 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
4197 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4200 if (banks[1] & MCI_STATUS_VAL)
4201 mce->status |= MCI_STATUS_OVER;
4202 banks[2] = mce->addr;
4203 banks[3] = mce->misc;
4204 vcpu->arch.mcg_status = mce->mcg_status;
4205 banks[1] = mce->status;
4206 kvm_queue_exception(vcpu, MC_VECTOR);
4207 } else if (!(banks[1] & MCI_STATUS_VAL)
4208 || !(banks[1] & MCI_STATUS_UC)) {
4209 if (banks[1] & MCI_STATUS_VAL)
4210 mce->status |= MCI_STATUS_OVER;
4211 banks[2] = mce->addr;
4212 banks[3] = mce->misc;
4213 banks[1] = mce->status;
4215 banks[1] |= MCI_STATUS_OVER;
4219 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
4220 struct kvm_vcpu_events *events)
4225 * In guest mode, payload delivery should be deferred,
4226 * so that the L1 hypervisor can intercept #PF before
4227 * CR2 is modified (or intercept #DB before DR6 is
4228 * modified under nVMX). Unless the per-VM capability,
4229 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
4230 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
4231 * opportunistically defer the exception payload, deliver it if the
4232 * capability hasn't been requested before processing a
4233 * KVM_GET_VCPU_EVENTS.
4235 if (!vcpu->kvm->arch.exception_payload_enabled &&
4236 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
4237 kvm_deliver_exception_payload(vcpu);
4240 * The API doesn't provide the instruction length for software
4241 * exceptions, so don't report them. As long as the guest RIP
4242 * isn't advanced, we should expect to encounter the exception
4245 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
4246 events->exception.injected = 0;
4247 events->exception.pending = 0;
4249 events->exception.injected = vcpu->arch.exception.injected;
4250 events->exception.pending = vcpu->arch.exception.pending;
4252 * For ABI compatibility, deliberately conflate
4253 * pending and injected exceptions when
4254 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
4256 if (!vcpu->kvm->arch.exception_payload_enabled)
4257 events->exception.injected |=
4258 vcpu->arch.exception.pending;
4260 events->exception.nr = vcpu->arch.exception.nr;
4261 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
4262 events->exception.error_code = vcpu->arch.exception.error_code;
4263 events->exception_has_payload = vcpu->arch.exception.has_payload;
4264 events->exception_payload = vcpu->arch.exception.payload;
4266 events->interrupt.injected =
4267 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
4268 events->interrupt.nr = vcpu->arch.interrupt.nr;
4269 events->interrupt.soft = 0;
4270 events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
4272 events->nmi.injected = vcpu->arch.nmi_injected;
4273 events->nmi.pending = vcpu->arch.nmi_pending != 0;
4274 events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu);
4275 events->nmi.pad = 0;
4277 events->sipi_vector = 0; /* never valid when reporting to user space */
4279 events->smi.smm = is_smm(vcpu);
4280 events->smi.pending = vcpu->arch.smi_pending;
4281 events->smi.smm_inside_nmi =
4282 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
4283 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
4285 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
4286 | KVM_VCPUEVENT_VALID_SHADOW
4287 | KVM_VCPUEVENT_VALID_SMM);
4288 if (vcpu->kvm->arch.exception_payload_enabled)
4289 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4291 memset(&events->reserved, 0, sizeof(events->reserved));
4294 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
4296 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4297 struct kvm_vcpu_events *events)
4299 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4300 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4301 | KVM_VCPUEVENT_VALID_SHADOW
4302 | KVM_VCPUEVENT_VALID_SMM
4303 | KVM_VCPUEVENT_VALID_PAYLOAD))
4306 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4307 if (!vcpu->kvm->arch.exception_payload_enabled)
4309 if (events->exception.pending)
4310 events->exception.injected = 0;
4312 events->exception_has_payload = 0;
4314 events->exception.pending = 0;
4315 events->exception_has_payload = 0;
4318 if ((events->exception.injected || events->exception.pending) &&
4319 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4322 /* INITs are latched while in SMM */
4323 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4324 (events->smi.smm || events->smi.pending) &&
4325 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4329 vcpu->arch.exception.injected = events->exception.injected;
4330 vcpu->arch.exception.pending = events->exception.pending;
4331 vcpu->arch.exception.nr = events->exception.nr;
4332 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4333 vcpu->arch.exception.error_code = events->exception.error_code;
4334 vcpu->arch.exception.has_payload = events->exception_has_payload;
4335 vcpu->arch.exception.payload = events->exception_payload;
4337 vcpu->arch.interrupt.injected = events->interrupt.injected;
4338 vcpu->arch.interrupt.nr = events->interrupt.nr;
4339 vcpu->arch.interrupt.soft = events->interrupt.soft;
4340 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4341 kvm_x86_ops.set_interrupt_shadow(vcpu,
4342 events->interrupt.shadow);
4344 vcpu->arch.nmi_injected = events->nmi.injected;
4345 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4346 vcpu->arch.nmi_pending = events->nmi.pending;
4347 kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked);
4349 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4350 lapic_in_kernel(vcpu))
4351 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4353 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4354 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4355 if (events->smi.smm)
4356 vcpu->arch.hflags |= HF_SMM_MASK;
4358 vcpu->arch.hflags &= ~HF_SMM_MASK;
4359 kvm_smm_changed(vcpu);
4362 vcpu->arch.smi_pending = events->smi.pending;
4364 if (events->smi.smm) {
4365 if (events->smi.smm_inside_nmi)
4366 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4368 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4371 if (lapic_in_kernel(vcpu)) {
4372 if (events->smi.latched_init)
4373 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4375 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4379 kvm_make_request(KVM_REQ_EVENT, vcpu);
4384 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4385 struct kvm_debugregs *dbgregs)
4389 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4390 kvm_get_dr(vcpu, 6, &val);
4392 dbgregs->dr7 = vcpu->arch.dr7;
4394 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4397 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4398 struct kvm_debugregs *dbgregs)
4403 if (dbgregs->dr6 & ~0xffffffffull)
4405 if (dbgregs->dr7 & ~0xffffffffull)
4408 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4409 kvm_update_dr0123(vcpu);
4410 vcpu->arch.dr6 = dbgregs->dr6;
4411 vcpu->arch.dr7 = dbgregs->dr7;
4412 kvm_update_dr7(vcpu);
4417 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4419 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4421 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4422 u64 xstate_bv = xsave->header.xfeatures;
4426 * Copy legacy XSAVE area, to avoid complications with CPUID
4427 * leaves 0 and 1 in the loop below.
4429 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4432 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4433 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4436 * Copy each region from the possibly compacted offset to the
4437 * non-compacted offset.
4439 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4441 u64 xfeature_mask = valid & -valid;
4442 int xfeature_nr = fls64(xfeature_mask) - 1;
4443 void *src = get_xsave_addr(xsave, xfeature_nr);
4446 u32 size, offset, ecx, edx;
4447 cpuid_count(XSTATE_CPUID, xfeature_nr,
4448 &size, &offset, &ecx, &edx);
4449 if (xfeature_nr == XFEATURE_PKRU)
4450 memcpy(dest + offset, &vcpu->arch.pkru,
4451 sizeof(vcpu->arch.pkru));
4453 memcpy(dest + offset, src, size);
4457 valid -= xfeature_mask;
4461 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4463 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4464 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4468 * Copy legacy XSAVE area, to avoid complications with CPUID
4469 * leaves 0 and 1 in the loop below.
4471 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4473 /* Set XSTATE_BV and possibly XCOMP_BV. */
4474 xsave->header.xfeatures = xstate_bv;
4475 if (boot_cpu_has(X86_FEATURE_XSAVES))
4476 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4479 * Copy each region from the non-compacted offset to the
4480 * possibly compacted offset.
4482 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4484 u64 xfeature_mask = valid & -valid;
4485 int xfeature_nr = fls64(xfeature_mask) - 1;
4486 void *dest = get_xsave_addr(xsave, xfeature_nr);
4489 u32 size, offset, ecx, edx;
4490 cpuid_count(XSTATE_CPUID, xfeature_nr,
4491 &size, &offset, &ecx, &edx);
4492 if (xfeature_nr == XFEATURE_PKRU)
4493 memcpy(&vcpu->arch.pkru, src + offset,
4494 sizeof(vcpu->arch.pkru));
4496 memcpy(dest, src + offset, size);
4499 valid -= xfeature_mask;
4503 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4504 struct kvm_xsave *guest_xsave)
4506 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4507 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4508 fill_xsave((u8 *) guest_xsave->region, vcpu);
4510 memcpy(guest_xsave->region,
4511 &vcpu->arch.guest_fpu->state.fxsave,
4512 sizeof(struct fxregs_state));
4513 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4514 XFEATURE_MASK_FPSSE;
4518 #define XSAVE_MXCSR_OFFSET 24
4520 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4521 struct kvm_xsave *guest_xsave)
4524 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4525 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4527 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4529 * Here we allow setting states that are not present in
4530 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4531 * with old userspace.
4533 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4535 load_xsave(vcpu, (u8 *)guest_xsave->region);
4537 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4538 mxcsr & ~mxcsr_feature_mask)
4540 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4541 guest_xsave->region, sizeof(struct fxregs_state));
4546 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4547 struct kvm_xcrs *guest_xcrs)
4549 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4550 guest_xcrs->nr_xcrs = 0;
4554 guest_xcrs->nr_xcrs = 1;
4555 guest_xcrs->flags = 0;
4556 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4557 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4560 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4561 struct kvm_xcrs *guest_xcrs)
4565 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4568 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4571 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4572 /* Only support XCR0 currently */
4573 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4574 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4575 guest_xcrs->xcrs[i].value);
4584 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4585 * stopped by the hypervisor. This function will be called from the host only.
4586 * EINVAL is returned when the host attempts to set the flag for a guest that
4587 * does not support pv clocks.
4589 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4591 if (!vcpu->arch.pv_time_enabled)
4593 vcpu->arch.pvclock_set_guest_stopped_request = true;
4594 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4598 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4599 struct kvm_enable_cap *cap)
4602 uint16_t vmcs_version;
4603 void __user *user_ptr;
4609 case KVM_CAP_HYPERV_SYNIC2:
4614 case KVM_CAP_HYPERV_SYNIC:
4615 if (!irqchip_in_kernel(vcpu->kvm))
4617 return kvm_hv_activate_synic(vcpu, cap->cap ==
4618 KVM_CAP_HYPERV_SYNIC2);
4619 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4620 if (!kvm_x86_ops.nested_ops->enable_evmcs)
4622 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
4624 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4625 if (copy_to_user(user_ptr, &vmcs_version,
4626 sizeof(vmcs_version)))
4630 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4631 if (!kvm_x86_ops.enable_direct_tlbflush)
4634 return kvm_x86_ops.enable_direct_tlbflush(vcpu);
4636 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4637 vcpu->arch.pv_cpuid.enforce = cap->args[0];
4638 if (vcpu->arch.pv_cpuid.enforce)
4639 kvm_update_pv_runtime(vcpu);
4648 long kvm_arch_vcpu_ioctl(struct file *filp,
4649 unsigned int ioctl, unsigned long arg)
4651 struct kvm_vcpu *vcpu = filp->private_data;
4652 void __user *argp = (void __user *)arg;
4655 struct kvm_lapic_state *lapic;
4656 struct kvm_xsave *xsave;
4657 struct kvm_xcrs *xcrs;
4665 case KVM_GET_LAPIC: {
4667 if (!lapic_in_kernel(vcpu))
4669 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4670 GFP_KERNEL_ACCOUNT);
4675 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4679 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4684 case KVM_SET_LAPIC: {
4686 if (!lapic_in_kernel(vcpu))
4688 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4689 if (IS_ERR(u.lapic)) {
4690 r = PTR_ERR(u.lapic);
4694 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4697 case KVM_INTERRUPT: {
4698 struct kvm_interrupt irq;
4701 if (copy_from_user(&irq, argp, sizeof(irq)))
4703 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4707 r = kvm_vcpu_ioctl_nmi(vcpu);
4711 r = kvm_vcpu_ioctl_smi(vcpu);
4714 case KVM_SET_CPUID: {
4715 struct kvm_cpuid __user *cpuid_arg = argp;
4716 struct kvm_cpuid cpuid;
4719 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4721 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4724 case KVM_SET_CPUID2: {
4725 struct kvm_cpuid2 __user *cpuid_arg = argp;
4726 struct kvm_cpuid2 cpuid;
4729 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4731 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4732 cpuid_arg->entries);
4735 case KVM_GET_CPUID2: {
4736 struct kvm_cpuid2 __user *cpuid_arg = argp;
4737 struct kvm_cpuid2 cpuid;
4740 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4742 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4743 cpuid_arg->entries);
4747 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4752 case KVM_GET_MSRS: {
4753 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4754 r = msr_io(vcpu, argp, do_get_msr, 1);
4755 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4758 case KVM_SET_MSRS: {
4759 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4760 r = msr_io(vcpu, argp, do_set_msr, 0);
4761 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4764 case KVM_TPR_ACCESS_REPORTING: {
4765 struct kvm_tpr_access_ctl tac;
4768 if (copy_from_user(&tac, argp, sizeof(tac)))
4770 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4774 if (copy_to_user(argp, &tac, sizeof(tac)))
4779 case KVM_SET_VAPIC_ADDR: {
4780 struct kvm_vapic_addr va;
4784 if (!lapic_in_kernel(vcpu))
4787 if (copy_from_user(&va, argp, sizeof(va)))
4789 idx = srcu_read_lock(&vcpu->kvm->srcu);
4790 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4791 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4794 case KVM_X86_SETUP_MCE: {
4798 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4800 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4803 case KVM_X86_SET_MCE: {
4804 struct kvm_x86_mce mce;
4807 if (copy_from_user(&mce, argp, sizeof(mce)))
4809 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4812 case KVM_GET_VCPU_EVENTS: {
4813 struct kvm_vcpu_events events;
4815 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4818 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4823 case KVM_SET_VCPU_EVENTS: {
4824 struct kvm_vcpu_events events;
4827 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4830 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4833 case KVM_GET_DEBUGREGS: {
4834 struct kvm_debugregs dbgregs;
4836 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4839 if (copy_to_user(argp, &dbgregs,
4840 sizeof(struct kvm_debugregs)))
4845 case KVM_SET_DEBUGREGS: {
4846 struct kvm_debugregs dbgregs;
4849 if (copy_from_user(&dbgregs, argp,
4850 sizeof(struct kvm_debugregs)))
4853 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4856 case KVM_GET_XSAVE: {
4857 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4862 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4865 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4870 case KVM_SET_XSAVE: {
4871 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4872 if (IS_ERR(u.xsave)) {
4873 r = PTR_ERR(u.xsave);
4877 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4880 case KVM_GET_XCRS: {
4881 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4886 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4889 if (copy_to_user(argp, u.xcrs,
4890 sizeof(struct kvm_xcrs)))
4895 case KVM_SET_XCRS: {
4896 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4897 if (IS_ERR(u.xcrs)) {
4898 r = PTR_ERR(u.xcrs);
4902 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4905 case KVM_SET_TSC_KHZ: {
4909 user_tsc_khz = (u32)arg;
4911 if (kvm_has_tsc_control &&
4912 user_tsc_khz >= kvm_max_guest_tsc_khz)
4915 if (user_tsc_khz == 0)
4916 user_tsc_khz = tsc_khz;
4918 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4923 case KVM_GET_TSC_KHZ: {
4924 r = vcpu->arch.virtual_tsc_khz;
4927 case KVM_KVMCLOCK_CTRL: {
4928 r = kvm_set_guest_paused(vcpu);
4931 case KVM_ENABLE_CAP: {
4932 struct kvm_enable_cap cap;
4935 if (copy_from_user(&cap, argp, sizeof(cap)))
4937 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4940 case KVM_GET_NESTED_STATE: {
4941 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4945 if (!kvm_x86_ops.nested_ops->get_state)
4948 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4950 if (get_user(user_data_size, &user_kvm_nested_state->size))
4953 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
4958 if (r > user_data_size) {
4959 if (put_user(r, &user_kvm_nested_state->size))
4969 case KVM_SET_NESTED_STATE: {
4970 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4971 struct kvm_nested_state kvm_state;
4975 if (!kvm_x86_ops.nested_ops->set_state)
4979 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4983 if (kvm_state.size < sizeof(kvm_state))
4986 if (kvm_state.flags &
4987 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4988 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
4989 | KVM_STATE_NESTED_GIF_SET))
4992 /* nested_run_pending implies guest_mode. */
4993 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4994 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4997 idx = srcu_read_lock(&vcpu->kvm->srcu);
4998 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
4999 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5002 case KVM_GET_SUPPORTED_HV_CPUID:
5003 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5015 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5017 return VM_FAULT_SIGBUS;
5020 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
5024 if (addr > (unsigned int)(-3 * PAGE_SIZE))
5026 ret = kvm_x86_ops.set_tss_addr(kvm, addr);
5030 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
5033 return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr);
5036 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
5037 unsigned long kvm_nr_mmu_pages)
5039 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
5042 mutex_lock(&kvm->slots_lock);
5044 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
5045 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
5047 mutex_unlock(&kvm->slots_lock);
5051 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
5053 return kvm->arch.n_max_mmu_pages;
5056 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5058 struct kvm_pic *pic = kvm->arch.vpic;
5062 switch (chip->chip_id) {
5063 case KVM_IRQCHIP_PIC_MASTER:
5064 memcpy(&chip->chip.pic, &pic->pics[0],
5065 sizeof(struct kvm_pic_state));
5067 case KVM_IRQCHIP_PIC_SLAVE:
5068 memcpy(&chip->chip.pic, &pic->pics[1],
5069 sizeof(struct kvm_pic_state));
5071 case KVM_IRQCHIP_IOAPIC:
5072 kvm_get_ioapic(kvm, &chip->chip.ioapic);
5081 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5083 struct kvm_pic *pic = kvm->arch.vpic;
5087 switch (chip->chip_id) {
5088 case KVM_IRQCHIP_PIC_MASTER:
5089 spin_lock(&pic->lock);
5090 memcpy(&pic->pics[0], &chip->chip.pic,
5091 sizeof(struct kvm_pic_state));
5092 spin_unlock(&pic->lock);
5094 case KVM_IRQCHIP_PIC_SLAVE:
5095 spin_lock(&pic->lock);
5096 memcpy(&pic->pics[1], &chip->chip.pic,
5097 sizeof(struct kvm_pic_state));
5098 spin_unlock(&pic->lock);
5100 case KVM_IRQCHIP_IOAPIC:
5101 kvm_set_ioapic(kvm, &chip->chip.ioapic);
5107 kvm_pic_update_irq(pic);
5111 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5113 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
5115 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
5117 mutex_lock(&kps->lock);
5118 memcpy(ps, &kps->channels, sizeof(*ps));
5119 mutex_unlock(&kps->lock);
5123 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5126 struct kvm_pit *pit = kvm->arch.vpit;
5128 mutex_lock(&pit->pit_state.lock);
5129 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
5130 for (i = 0; i < 3; i++)
5131 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
5132 mutex_unlock(&pit->pit_state.lock);
5136 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5138 mutex_lock(&kvm->arch.vpit->pit_state.lock);
5139 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
5140 sizeof(ps->channels));
5141 ps->flags = kvm->arch.vpit->pit_state.flags;
5142 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
5143 memset(&ps->reserved, 0, sizeof(ps->reserved));
5147 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5151 u32 prev_legacy, cur_legacy;
5152 struct kvm_pit *pit = kvm->arch.vpit;
5154 mutex_lock(&pit->pit_state.lock);
5155 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
5156 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
5157 if (!prev_legacy && cur_legacy)
5159 memcpy(&pit->pit_state.channels, &ps->channels,
5160 sizeof(pit->pit_state.channels));
5161 pit->pit_state.flags = ps->flags;
5162 for (i = 0; i < 3; i++)
5163 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
5165 mutex_unlock(&pit->pit_state.lock);
5169 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
5170 struct kvm_reinject_control *control)
5172 struct kvm_pit *pit = kvm->arch.vpit;
5174 /* pit->pit_state.lock was overloaded to prevent userspace from getting
5175 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
5176 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
5178 mutex_lock(&pit->pit_state.lock);
5179 kvm_pit_set_reinject(pit, control->pit_reinject);
5180 mutex_unlock(&pit->pit_state.lock);
5185 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
5188 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
5190 if (kvm_x86_ops.flush_log_dirty)
5191 kvm_x86_ops.flush_log_dirty(kvm);
5194 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
5197 if (!irqchip_in_kernel(kvm))
5200 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
5201 irq_event->irq, irq_event->level,
5206 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
5207 struct kvm_enable_cap *cap)
5215 case KVM_CAP_DISABLE_QUIRKS:
5216 kvm->arch.disabled_quirks = cap->args[0];
5219 case KVM_CAP_SPLIT_IRQCHIP: {
5220 mutex_lock(&kvm->lock);
5222 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
5223 goto split_irqchip_unlock;
5225 if (irqchip_in_kernel(kvm))
5226 goto split_irqchip_unlock;
5227 if (kvm->created_vcpus)
5228 goto split_irqchip_unlock;
5229 r = kvm_setup_empty_irq_routing(kvm);
5231 goto split_irqchip_unlock;
5232 /* Pairs with irqchip_in_kernel. */
5234 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
5235 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
5237 split_irqchip_unlock:
5238 mutex_unlock(&kvm->lock);
5241 case KVM_CAP_X2APIC_API:
5243 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
5246 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
5247 kvm->arch.x2apic_format = true;
5248 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
5249 kvm->arch.x2apic_broadcast_quirk_disabled = true;
5253 case KVM_CAP_X86_DISABLE_EXITS:
5255 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
5258 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
5259 kvm_can_mwait_in_guest())
5260 kvm->arch.mwait_in_guest = true;
5261 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
5262 kvm->arch.hlt_in_guest = true;
5263 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
5264 kvm->arch.pause_in_guest = true;
5265 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
5266 kvm->arch.cstate_in_guest = true;
5269 case KVM_CAP_MSR_PLATFORM_INFO:
5270 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
5273 case KVM_CAP_EXCEPTION_PAYLOAD:
5274 kvm->arch.exception_payload_enabled = cap->args[0];
5277 case KVM_CAP_X86_USER_SPACE_MSR:
5278 kvm->arch.user_space_msr_mask = cap->args[0];
5288 static void kvm_clear_msr_filter(struct kvm *kvm)
5291 u32 count = kvm->arch.msr_filter.count;
5292 struct msr_bitmap_range ranges[16];
5294 mutex_lock(&kvm->lock);
5295 kvm->arch.msr_filter.count = 0;
5296 memcpy(ranges, kvm->arch.msr_filter.ranges, count * sizeof(ranges[0]));
5297 mutex_unlock(&kvm->lock);
5298 synchronize_srcu(&kvm->srcu);
5300 for (i = 0; i < count; i++)
5301 kfree(ranges[i].bitmap);
5304 static int kvm_add_msr_filter(struct kvm *kvm, struct kvm_msr_filter_range *user_range)
5306 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
5307 struct msr_bitmap_range range;
5308 unsigned long *bitmap = NULL;
5312 if (!user_range->nmsrs)
5315 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
5316 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
5319 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
5321 return PTR_ERR(bitmap);
5323 range = (struct msr_bitmap_range) {
5324 .flags = user_range->flags,
5325 .base = user_range->base,
5326 .nmsrs = user_range->nmsrs,
5330 if (range.flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) {
5340 /* Everything ok, add this range identifier to our global pool */
5341 ranges[kvm->arch.msr_filter.count] = range;
5342 /* Make sure we filled the array before we tell anyone to walk it */
5344 kvm->arch.msr_filter.count++;
5352 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp)
5354 struct kvm_msr_filter __user *user_msr_filter = argp;
5355 struct kvm_msr_filter filter;
5361 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
5364 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++)
5365 empty &= !filter.ranges[i].nmsrs;
5367 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY);
5368 if (empty && !default_allow)
5371 kvm_clear_msr_filter(kvm);
5373 kvm->arch.msr_filter.default_allow = default_allow;
5376 * Protect from concurrent calls to this function that could trigger
5377 * a TOCTOU violation on kvm->arch.msr_filter.count.
5379 mutex_lock(&kvm->lock);
5380 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
5381 r = kvm_add_msr_filter(kvm, &filter.ranges[i]);
5386 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
5387 mutex_unlock(&kvm->lock);
5392 long kvm_arch_vm_ioctl(struct file *filp,
5393 unsigned int ioctl, unsigned long arg)
5395 struct kvm *kvm = filp->private_data;
5396 void __user *argp = (void __user *)arg;
5399 * This union makes it completely explicit to gcc-3.x
5400 * that these two variables' stack usage should be
5401 * combined, not added together.
5404 struct kvm_pit_state ps;
5405 struct kvm_pit_state2 ps2;
5406 struct kvm_pit_config pit_config;
5410 case KVM_SET_TSS_ADDR:
5411 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
5413 case KVM_SET_IDENTITY_MAP_ADDR: {
5416 mutex_lock(&kvm->lock);
5418 if (kvm->created_vcpus)
5419 goto set_identity_unlock;
5421 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
5422 goto set_identity_unlock;
5423 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
5424 set_identity_unlock:
5425 mutex_unlock(&kvm->lock);
5428 case KVM_SET_NR_MMU_PAGES:
5429 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
5431 case KVM_GET_NR_MMU_PAGES:
5432 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
5434 case KVM_CREATE_IRQCHIP: {
5435 mutex_lock(&kvm->lock);
5438 if (irqchip_in_kernel(kvm))
5439 goto create_irqchip_unlock;
5442 if (kvm->created_vcpus)
5443 goto create_irqchip_unlock;
5445 r = kvm_pic_init(kvm);
5447 goto create_irqchip_unlock;
5449 r = kvm_ioapic_init(kvm);
5451 kvm_pic_destroy(kvm);
5452 goto create_irqchip_unlock;
5455 r = kvm_setup_default_irq_routing(kvm);
5457 kvm_ioapic_destroy(kvm);
5458 kvm_pic_destroy(kvm);
5459 goto create_irqchip_unlock;
5461 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
5463 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
5464 create_irqchip_unlock:
5465 mutex_unlock(&kvm->lock);
5468 case KVM_CREATE_PIT:
5469 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
5471 case KVM_CREATE_PIT2:
5473 if (copy_from_user(&u.pit_config, argp,
5474 sizeof(struct kvm_pit_config)))
5477 mutex_lock(&kvm->lock);
5480 goto create_pit_unlock;
5482 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5486 mutex_unlock(&kvm->lock);
5488 case KVM_GET_IRQCHIP: {
5489 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5490 struct kvm_irqchip *chip;
5492 chip = memdup_user(argp, sizeof(*chip));
5499 if (!irqchip_kernel(kvm))
5500 goto get_irqchip_out;
5501 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5503 goto get_irqchip_out;
5505 if (copy_to_user(argp, chip, sizeof(*chip)))
5506 goto get_irqchip_out;
5512 case KVM_SET_IRQCHIP: {
5513 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5514 struct kvm_irqchip *chip;
5516 chip = memdup_user(argp, sizeof(*chip));
5523 if (!irqchip_kernel(kvm))
5524 goto set_irqchip_out;
5525 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5532 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5535 if (!kvm->arch.vpit)
5537 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5541 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5548 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5550 mutex_lock(&kvm->lock);
5552 if (!kvm->arch.vpit)
5554 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5556 mutex_unlock(&kvm->lock);
5559 case KVM_GET_PIT2: {
5561 if (!kvm->arch.vpit)
5563 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5567 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5572 case KVM_SET_PIT2: {
5574 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5576 mutex_lock(&kvm->lock);
5578 if (!kvm->arch.vpit)
5580 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5582 mutex_unlock(&kvm->lock);
5585 case KVM_REINJECT_CONTROL: {
5586 struct kvm_reinject_control control;
5588 if (copy_from_user(&control, argp, sizeof(control)))
5591 if (!kvm->arch.vpit)
5593 r = kvm_vm_ioctl_reinject(kvm, &control);
5596 case KVM_SET_BOOT_CPU_ID:
5598 mutex_lock(&kvm->lock);
5599 if (kvm->created_vcpus)
5602 kvm->arch.bsp_vcpu_id = arg;
5603 mutex_unlock(&kvm->lock);
5605 case KVM_XEN_HVM_CONFIG: {
5606 struct kvm_xen_hvm_config xhc;
5608 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5613 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5617 case KVM_SET_CLOCK: {
5618 struct kvm_clock_data user_ns;
5622 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5631 * TODO: userspace has to take care of races with VCPU_RUN, so
5632 * kvm_gen_update_masterclock() can be cut down to locked
5633 * pvclock_update_vm_gtod_copy().
5635 kvm_gen_update_masterclock(kvm);
5636 now_ns = get_kvmclock_ns(kvm);
5637 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5638 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5641 case KVM_GET_CLOCK: {
5642 struct kvm_clock_data user_ns;
5645 now_ns = get_kvmclock_ns(kvm);
5646 user_ns.clock = now_ns;
5647 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5648 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5651 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5656 case KVM_MEMORY_ENCRYPT_OP: {
5658 if (kvm_x86_ops.mem_enc_op)
5659 r = kvm_x86_ops.mem_enc_op(kvm, argp);
5662 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5663 struct kvm_enc_region region;
5666 if (copy_from_user(®ion, argp, sizeof(region)))
5670 if (kvm_x86_ops.mem_enc_reg_region)
5671 r = kvm_x86_ops.mem_enc_reg_region(kvm, ®ion);
5674 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5675 struct kvm_enc_region region;
5678 if (copy_from_user(®ion, argp, sizeof(region)))
5682 if (kvm_x86_ops.mem_enc_unreg_region)
5683 r = kvm_x86_ops.mem_enc_unreg_region(kvm, ®ion);
5686 case KVM_HYPERV_EVENTFD: {
5687 struct kvm_hyperv_eventfd hvevfd;
5690 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5692 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5695 case KVM_SET_PMU_EVENT_FILTER:
5696 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5698 case KVM_X86_SET_MSR_FILTER:
5699 r = kvm_vm_ioctl_set_msr_filter(kvm, argp);
5708 static void kvm_init_msr_list(void)
5710 struct x86_pmu_capability x86_pmu;
5714 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5715 "Please update the fixed PMCs in msrs_to_saved_all[]");
5717 perf_get_x86_pmu_capability(&x86_pmu);
5719 num_msrs_to_save = 0;
5720 num_emulated_msrs = 0;
5721 num_msr_based_features = 0;
5723 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5724 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5728 * Even MSRs that are valid in the host may not be exposed
5729 * to the guests in some cases.
5731 switch (msrs_to_save_all[i]) {
5732 case MSR_IA32_BNDCFGS:
5733 if (!kvm_mpx_supported())
5737 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5740 case MSR_IA32_UMWAIT_CONTROL:
5741 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
5744 case MSR_IA32_RTIT_CTL:
5745 case MSR_IA32_RTIT_STATUS:
5746 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5749 case MSR_IA32_RTIT_CR3_MATCH:
5750 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5751 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5754 case MSR_IA32_RTIT_OUTPUT_BASE:
5755 case MSR_IA32_RTIT_OUTPUT_MASK:
5756 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5757 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5758 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5761 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
5762 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5763 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5764 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5767 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5768 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5769 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5772 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5773 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5774 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5781 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5784 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5785 if (!kvm_x86_ops.has_emulated_msr(emulated_msrs_all[i]))
5788 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5791 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5792 struct kvm_msr_entry msr;
5794 msr.index = msr_based_features_all[i];
5795 if (kvm_get_msr_feature(&msr))
5798 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5802 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5810 if (!(lapic_in_kernel(vcpu) &&
5811 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5812 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5823 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5830 if (!(lapic_in_kernel(vcpu) &&
5831 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5833 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5835 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5845 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5846 struct kvm_segment *var, int seg)
5848 kvm_x86_ops.set_segment(vcpu, var, seg);
5851 void kvm_get_segment(struct kvm_vcpu *vcpu,
5852 struct kvm_segment *var, int seg)
5854 kvm_x86_ops.get_segment(vcpu, var, seg);
5857 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5858 struct x86_exception *exception)
5862 BUG_ON(!mmu_is_nested(vcpu));
5864 /* NPT walks are always user-walks */
5865 access |= PFERR_USER_MASK;
5866 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5871 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5872 struct x86_exception *exception)
5874 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5875 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5878 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5879 struct x86_exception *exception)
5881 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5882 access |= PFERR_FETCH_MASK;
5883 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5886 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5887 struct x86_exception *exception)
5889 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5890 access |= PFERR_WRITE_MASK;
5891 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5894 /* uses this to access any guest's mapped memory without checking CPL */
5895 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5896 struct x86_exception *exception)
5898 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5901 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5902 struct kvm_vcpu *vcpu, u32 access,
5903 struct x86_exception *exception)
5906 int r = X86EMUL_CONTINUE;
5909 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5911 unsigned offset = addr & (PAGE_SIZE-1);
5912 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5915 if (gpa == UNMAPPED_GVA)
5916 return X86EMUL_PROPAGATE_FAULT;
5917 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5920 r = X86EMUL_IO_NEEDED;
5932 /* used for instruction fetching */
5933 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5934 gva_t addr, void *val, unsigned int bytes,
5935 struct x86_exception *exception)
5937 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5938 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5942 /* Inline kvm_read_guest_virt_helper for speed. */
5943 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5945 if (unlikely(gpa == UNMAPPED_GVA))
5946 return X86EMUL_PROPAGATE_FAULT;
5948 offset = addr & (PAGE_SIZE-1);
5949 if (WARN_ON(offset + bytes > PAGE_SIZE))
5950 bytes = (unsigned)PAGE_SIZE - offset;
5951 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5953 if (unlikely(ret < 0))
5954 return X86EMUL_IO_NEEDED;
5956 return X86EMUL_CONTINUE;
5959 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5960 gva_t addr, void *val, unsigned int bytes,
5961 struct x86_exception *exception)
5963 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5966 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5967 * is returned, but our callers are not ready for that and they blindly
5968 * call kvm_inject_page_fault. Ensure that they at least do not leak
5969 * uninitialized kernel stack memory into cr2 and error code.
5971 memset(exception, 0, sizeof(*exception));
5972 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5975 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5977 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5978 gva_t addr, void *val, unsigned int bytes,
5979 struct x86_exception *exception, bool system)
5981 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5984 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5985 access |= PFERR_USER_MASK;
5987 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5990 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5991 unsigned long addr, void *val, unsigned int bytes)
5993 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5994 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5996 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5999 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
6000 struct kvm_vcpu *vcpu, u32 access,
6001 struct x86_exception *exception)
6004 int r = X86EMUL_CONTINUE;
6007 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
6010 unsigned offset = addr & (PAGE_SIZE-1);
6011 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
6014 if (gpa == UNMAPPED_GVA)
6015 return X86EMUL_PROPAGATE_FAULT;
6016 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
6018 r = X86EMUL_IO_NEEDED;
6030 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
6031 unsigned int bytes, struct x86_exception *exception,
6034 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6035 u32 access = PFERR_WRITE_MASK;
6037 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
6038 access |= PFERR_USER_MASK;
6040 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6044 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
6045 unsigned int bytes, struct x86_exception *exception)
6047 /* kvm_write_guest_virt_system can pull in tons of pages. */
6048 vcpu->arch.l1tf_flush_l1d = true;
6050 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6051 PFERR_WRITE_MASK, exception);
6053 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
6055 int handle_ud(struct kvm_vcpu *vcpu)
6057 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
6058 int emul_type = EMULTYPE_TRAP_UD;
6059 char sig[5]; /* ud2; .ascii "kvm" */
6060 struct x86_exception e;
6062 if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, NULL, 0)))
6065 if (force_emulation_prefix &&
6066 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
6067 sig, sizeof(sig), &e) == 0 &&
6068 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
6069 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
6070 emul_type = EMULTYPE_TRAP_UD_FORCED;
6073 return kvm_emulate_instruction(vcpu, emul_type);
6075 EXPORT_SYMBOL_GPL(handle_ud);
6077 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6078 gpa_t gpa, bool write)
6080 /* For APIC access vmexit */
6081 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6084 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
6085 trace_vcpu_match_mmio(gva, gpa, write, true);
6092 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6093 gpa_t *gpa, struct x86_exception *exception,
6096 u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
6097 | (write ? PFERR_WRITE_MASK : 0);
6100 * currently PKRU is only applied to ept enabled guest so
6101 * there is no pkey in EPT page table for L1 guest or EPT
6102 * shadow page table for L2 guest.
6104 if (vcpu_match_mmio_gva(vcpu, gva)
6105 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
6106 vcpu->arch.mmio_access, 0, access)) {
6107 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
6108 (gva & (PAGE_SIZE - 1));
6109 trace_vcpu_match_mmio(gva, *gpa, write, false);
6113 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
6115 if (*gpa == UNMAPPED_GVA)
6118 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
6121 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
6122 const void *val, int bytes)
6126 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
6129 kvm_page_track_write(vcpu, gpa, val, bytes);
6133 struct read_write_emulator_ops {
6134 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
6136 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
6137 void *val, int bytes);
6138 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6139 int bytes, void *val);
6140 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6141 void *val, int bytes);
6145 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
6147 if (vcpu->mmio_read_completed) {
6148 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
6149 vcpu->mmio_fragments[0].gpa, val);
6150 vcpu->mmio_read_completed = 0;
6157 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6158 void *val, int bytes)
6160 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
6163 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6164 void *val, int bytes)
6166 return emulator_write_phys(vcpu, gpa, val, bytes);
6169 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
6171 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
6172 return vcpu_mmio_write(vcpu, gpa, bytes, val);
6175 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6176 void *val, int bytes)
6178 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
6179 return X86EMUL_IO_NEEDED;
6182 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6183 void *val, int bytes)
6185 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
6187 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
6188 return X86EMUL_CONTINUE;
6191 static const struct read_write_emulator_ops read_emultor = {
6192 .read_write_prepare = read_prepare,
6193 .read_write_emulate = read_emulate,
6194 .read_write_mmio = vcpu_mmio_read,
6195 .read_write_exit_mmio = read_exit_mmio,
6198 static const struct read_write_emulator_ops write_emultor = {
6199 .read_write_emulate = write_emulate,
6200 .read_write_mmio = write_mmio,
6201 .read_write_exit_mmio = write_exit_mmio,
6205 static int emulator_read_write_onepage(unsigned long addr, void *val,
6207 struct x86_exception *exception,
6208 struct kvm_vcpu *vcpu,
6209 const struct read_write_emulator_ops *ops)
6213 bool write = ops->write;
6214 struct kvm_mmio_fragment *frag;
6215 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6218 * If the exit was due to a NPF we may already have a GPA.
6219 * If the GPA is present, use it to avoid the GVA to GPA table walk.
6220 * Note, this cannot be used on string operations since string
6221 * operation using rep will only have the initial GPA from the NPF
6224 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
6225 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
6226 gpa = ctxt->gpa_val;
6227 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
6229 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
6231 return X86EMUL_PROPAGATE_FAULT;
6234 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
6235 return X86EMUL_CONTINUE;
6238 * Is this MMIO handled locally?
6240 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
6241 if (handled == bytes)
6242 return X86EMUL_CONTINUE;
6248 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
6249 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
6253 return X86EMUL_CONTINUE;
6256 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
6258 void *val, unsigned int bytes,
6259 struct x86_exception *exception,
6260 const struct read_write_emulator_ops *ops)
6262 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6266 if (ops->read_write_prepare &&
6267 ops->read_write_prepare(vcpu, val, bytes))
6268 return X86EMUL_CONTINUE;
6270 vcpu->mmio_nr_fragments = 0;
6272 /* Crossing a page boundary? */
6273 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
6276 now = -addr & ~PAGE_MASK;
6277 rc = emulator_read_write_onepage(addr, val, now, exception,
6280 if (rc != X86EMUL_CONTINUE)
6283 if (ctxt->mode != X86EMUL_MODE_PROT64)
6289 rc = emulator_read_write_onepage(addr, val, bytes, exception,
6291 if (rc != X86EMUL_CONTINUE)
6294 if (!vcpu->mmio_nr_fragments)
6297 gpa = vcpu->mmio_fragments[0].gpa;
6299 vcpu->mmio_needed = 1;
6300 vcpu->mmio_cur_fragment = 0;
6302 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
6303 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
6304 vcpu->run->exit_reason = KVM_EXIT_MMIO;
6305 vcpu->run->mmio.phys_addr = gpa;
6307 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
6310 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
6314 struct x86_exception *exception)
6316 return emulator_read_write(ctxt, addr, val, bytes,
6317 exception, &read_emultor);
6320 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
6324 struct x86_exception *exception)
6326 return emulator_read_write(ctxt, addr, (void *)val, bytes,
6327 exception, &write_emultor);
6330 #define CMPXCHG_TYPE(t, ptr, old, new) \
6331 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
6333 #ifdef CONFIG_X86_64
6334 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
6336 # define CMPXCHG64(ptr, old, new) \
6337 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
6340 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
6345 struct x86_exception *exception)
6347 struct kvm_host_map map;
6348 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6354 /* guests cmpxchg8b have to be emulated atomically */
6355 if (bytes > 8 || (bytes & (bytes - 1)))
6358 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
6360 if (gpa == UNMAPPED_GVA ||
6361 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6365 * Emulate the atomic as a straight write to avoid #AC if SLD is
6366 * enabled in the host and the access splits a cache line.
6368 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
6369 page_line_mask = ~(cache_line_size() - 1);
6371 page_line_mask = PAGE_MASK;
6373 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
6376 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
6379 kaddr = map.hva + offset_in_page(gpa);
6383 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
6386 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
6389 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
6392 exchanged = CMPXCHG64(kaddr, old, new);
6398 kvm_vcpu_unmap(vcpu, &map, true);
6401 return X86EMUL_CMPXCHG_FAILED;
6403 kvm_page_track_write(vcpu, gpa, new, bytes);
6405 return X86EMUL_CONTINUE;
6408 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
6410 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
6413 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
6417 for (i = 0; i < vcpu->arch.pio.count; i++) {
6418 if (vcpu->arch.pio.in)
6419 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
6420 vcpu->arch.pio.size, pd);
6422 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
6423 vcpu->arch.pio.port, vcpu->arch.pio.size,
6427 pd += vcpu->arch.pio.size;
6432 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
6433 unsigned short port, void *val,
6434 unsigned int count, bool in)
6436 vcpu->arch.pio.port = port;
6437 vcpu->arch.pio.in = in;
6438 vcpu->arch.pio.count = count;
6439 vcpu->arch.pio.size = size;
6441 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
6442 vcpu->arch.pio.count = 0;
6446 vcpu->run->exit_reason = KVM_EXIT_IO;
6447 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
6448 vcpu->run->io.size = size;
6449 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
6450 vcpu->run->io.count = count;
6451 vcpu->run->io.port = port;
6456 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
6457 unsigned short port, void *val, unsigned int count)
6461 if (vcpu->arch.pio.count)
6464 memset(vcpu->arch.pio_data, 0, size * count);
6466 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
6469 memcpy(val, vcpu->arch.pio_data, size * count);
6470 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
6471 vcpu->arch.pio.count = 0;
6478 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
6479 int size, unsigned short port, void *val,
6482 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
6486 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
6487 unsigned short port, const void *val,
6490 memcpy(vcpu->arch.pio_data, val, size * count);
6491 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6492 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6495 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
6496 int size, unsigned short port,
6497 const void *val, unsigned int count)
6499 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
6502 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6504 return kvm_x86_ops.get_segment_base(vcpu, seg);
6507 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6509 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6512 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6514 if (!need_emulate_wbinvd(vcpu))
6515 return X86EMUL_CONTINUE;
6517 if (kvm_x86_ops.has_wbinvd_exit()) {
6518 int cpu = get_cpu();
6520 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6521 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6522 wbinvd_ipi, NULL, 1);
6524 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6527 return X86EMUL_CONTINUE;
6530 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6532 kvm_emulate_wbinvd_noskip(vcpu);
6533 return kvm_skip_emulated_instruction(vcpu);
6535 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6539 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6541 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6544 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6545 unsigned long *dest)
6547 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6550 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6551 unsigned long value)
6554 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6557 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6559 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6562 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6564 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6565 unsigned long value;
6569 value = kvm_read_cr0(vcpu);
6572 value = vcpu->arch.cr2;
6575 value = kvm_read_cr3(vcpu);
6578 value = kvm_read_cr4(vcpu);
6581 value = kvm_get_cr8(vcpu);
6584 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6591 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6593 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6598 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6601 vcpu->arch.cr2 = val;
6604 res = kvm_set_cr3(vcpu, val);
6607 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6610 res = kvm_set_cr8(vcpu, val);
6613 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6620 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6622 return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt));
6625 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6627 kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt);
6630 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6632 kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt);
6635 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6637 kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt);
6640 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6642 kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt);
6645 static unsigned long emulator_get_cached_segment_base(
6646 struct x86_emulate_ctxt *ctxt, int seg)
6648 return get_segment_base(emul_to_vcpu(ctxt), seg);
6651 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6652 struct desc_struct *desc, u32 *base3,
6655 struct kvm_segment var;
6657 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6658 *selector = var.selector;
6661 memset(desc, 0, sizeof(*desc));
6669 set_desc_limit(desc, var.limit);
6670 set_desc_base(desc, (unsigned long)var.base);
6671 #ifdef CONFIG_X86_64
6673 *base3 = var.base >> 32;
6675 desc->type = var.type;
6677 desc->dpl = var.dpl;
6678 desc->p = var.present;
6679 desc->avl = var.avl;
6687 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6688 struct desc_struct *desc, u32 base3,
6691 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6692 struct kvm_segment var;
6694 var.selector = selector;
6695 var.base = get_desc_base(desc);
6696 #ifdef CONFIG_X86_64
6697 var.base |= ((u64)base3) << 32;
6699 var.limit = get_desc_limit(desc);
6701 var.limit = (var.limit << 12) | 0xfff;
6702 var.type = desc->type;
6703 var.dpl = desc->dpl;
6708 var.avl = desc->avl;
6709 var.present = desc->p;
6710 var.unusable = !var.present;
6713 kvm_set_segment(vcpu, &var, seg);
6717 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6718 u32 msr_index, u64 *pdata)
6720 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6723 r = kvm_get_msr(vcpu, msr_index, pdata);
6725 if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) {
6726 /* Bounce to user space */
6727 return X86EMUL_IO_NEEDED;
6733 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6734 u32 msr_index, u64 data)
6736 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6739 r = kvm_set_msr(vcpu, msr_index, data);
6741 if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) {
6742 /* Bounce to user space */
6743 return X86EMUL_IO_NEEDED;
6749 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6751 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6753 return vcpu->arch.smbase;
6756 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6758 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6760 vcpu->arch.smbase = smbase;
6763 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6766 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6769 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6770 u32 pmc, u64 *pdata)
6772 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6775 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6777 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6780 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6781 struct x86_instruction_info *info,
6782 enum x86_intercept_stage stage)
6784 return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage,
6788 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6789 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6792 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6795 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6797 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6800 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6802 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6805 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6807 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6810 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6812 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6815 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6817 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6820 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6822 kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked);
6825 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6827 return emul_to_vcpu(ctxt)->arch.hflags;
6830 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6832 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6835 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6836 const char *smstate)
6838 return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6841 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6843 kvm_smm_changed(emul_to_vcpu(ctxt));
6846 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6848 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6851 static const struct x86_emulate_ops emulate_ops = {
6852 .read_gpr = emulator_read_gpr,
6853 .write_gpr = emulator_write_gpr,
6854 .read_std = emulator_read_std,
6855 .write_std = emulator_write_std,
6856 .read_phys = kvm_read_guest_phys_system,
6857 .fetch = kvm_fetch_guest_virt,
6858 .read_emulated = emulator_read_emulated,
6859 .write_emulated = emulator_write_emulated,
6860 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6861 .invlpg = emulator_invlpg,
6862 .pio_in_emulated = emulator_pio_in_emulated,
6863 .pio_out_emulated = emulator_pio_out_emulated,
6864 .get_segment = emulator_get_segment,
6865 .set_segment = emulator_set_segment,
6866 .get_cached_segment_base = emulator_get_cached_segment_base,
6867 .get_gdt = emulator_get_gdt,
6868 .get_idt = emulator_get_idt,
6869 .set_gdt = emulator_set_gdt,
6870 .set_idt = emulator_set_idt,
6871 .get_cr = emulator_get_cr,
6872 .set_cr = emulator_set_cr,
6873 .cpl = emulator_get_cpl,
6874 .get_dr = emulator_get_dr,
6875 .set_dr = emulator_set_dr,
6876 .get_smbase = emulator_get_smbase,
6877 .set_smbase = emulator_set_smbase,
6878 .set_msr = emulator_set_msr,
6879 .get_msr = emulator_get_msr,
6880 .check_pmc = emulator_check_pmc,
6881 .read_pmc = emulator_read_pmc,
6882 .halt = emulator_halt,
6883 .wbinvd = emulator_wbinvd,
6884 .fix_hypercall = emulator_fix_hypercall,
6885 .intercept = emulator_intercept,
6886 .get_cpuid = emulator_get_cpuid,
6887 .guest_has_long_mode = emulator_guest_has_long_mode,
6888 .guest_has_movbe = emulator_guest_has_movbe,
6889 .guest_has_fxsr = emulator_guest_has_fxsr,
6890 .set_nmi_mask = emulator_set_nmi_mask,
6891 .get_hflags = emulator_get_hflags,
6892 .set_hflags = emulator_set_hflags,
6893 .pre_leave_smm = emulator_pre_leave_smm,
6894 .post_leave_smm = emulator_post_leave_smm,
6895 .set_xcr = emulator_set_xcr,
6898 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6900 u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
6902 * an sti; sti; sequence only disable interrupts for the first
6903 * instruction. So, if the last instruction, be it emulated or
6904 * not, left the system with the INT_STI flag enabled, it
6905 * means that the last instruction is an sti. We should not
6906 * leave the flag on in this case. The same goes for mov ss
6908 if (int_shadow & mask)
6910 if (unlikely(int_shadow || mask)) {
6911 kvm_x86_ops.set_interrupt_shadow(vcpu, mask);
6913 kvm_make_request(KVM_REQ_EVENT, vcpu);
6917 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6919 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6920 if (ctxt->exception.vector == PF_VECTOR)
6921 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
6923 if (ctxt->exception.error_code_valid)
6924 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6925 ctxt->exception.error_code);
6927 kvm_queue_exception(vcpu, ctxt->exception.vector);
6931 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6933 struct x86_emulate_ctxt *ctxt;
6935 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6937 pr_err("kvm: failed to allocate vcpu's emulator\n");
6942 ctxt->ops = &emulate_ops;
6943 vcpu->arch.emulate_ctxt = ctxt;
6948 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6950 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6953 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6955 ctxt->gpa_available = false;
6956 ctxt->eflags = kvm_get_rflags(vcpu);
6957 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6959 ctxt->eip = kvm_rip_read(vcpu);
6960 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6961 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6962 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6963 cs_db ? X86EMUL_MODE_PROT32 :
6964 X86EMUL_MODE_PROT16;
6965 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6966 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6967 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6969 init_decode_cache(ctxt);
6970 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6973 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6975 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6978 init_emulate_ctxt(vcpu);
6982 ctxt->_eip = ctxt->eip + inc_eip;
6983 ret = emulate_int_real(ctxt, irq);
6985 if (ret != X86EMUL_CONTINUE) {
6986 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6988 ctxt->eip = ctxt->_eip;
6989 kvm_rip_write(vcpu, ctxt->eip);
6990 kvm_set_rflags(vcpu, ctxt->eflags);
6993 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6995 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6997 ++vcpu->stat.insn_emulation_fail;
6998 trace_kvm_emulate_insn_failed(vcpu);
7000 if (emulation_type & EMULTYPE_VMWARE_GP) {
7001 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7005 if (emulation_type & EMULTYPE_SKIP) {
7006 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7007 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7008 vcpu->run->internal.ndata = 0;
7012 kvm_queue_exception(vcpu, UD_VECTOR);
7014 if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) {
7015 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7016 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7017 vcpu->run->internal.ndata = 0;
7024 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7025 bool write_fault_to_shadow_pgtable,
7028 gpa_t gpa = cr2_or_gpa;
7031 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7034 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7035 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7038 if (!vcpu->arch.mmu->direct_map) {
7040 * Write permission should be allowed since only
7041 * write access need to be emulated.
7043 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7046 * If the mapping is invalid in guest, let cpu retry
7047 * it to generate fault.
7049 if (gpa == UNMAPPED_GVA)
7054 * Do not retry the unhandleable instruction if it faults on the
7055 * readonly host memory, otherwise it will goto a infinite loop:
7056 * retry instruction -> write #PF -> emulation fail -> retry
7057 * instruction -> ...
7059 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
7062 * If the instruction failed on the error pfn, it can not be fixed,
7063 * report the error to userspace.
7065 if (is_error_noslot_pfn(pfn))
7068 kvm_release_pfn_clean(pfn);
7070 /* The instructions are well-emulated on direct mmu. */
7071 if (vcpu->arch.mmu->direct_map) {
7072 unsigned int indirect_shadow_pages;
7074 spin_lock(&vcpu->kvm->mmu_lock);
7075 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
7076 spin_unlock(&vcpu->kvm->mmu_lock);
7078 if (indirect_shadow_pages)
7079 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7085 * if emulation was due to access to shadowed page table
7086 * and it failed try to unshadow page and re-enter the
7087 * guest to let CPU execute the instruction.
7089 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7092 * If the access faults on its page table, it can not
7093 * be fixed by unprotecting shadow page and it should
7094 * be reported to userspace.
7096 return !write_fault_to_shadow_pgtable;
7099 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
7100 gpa_t cr2_or_gpa, int emulation_type)
7102 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7103 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
7105 last_retry_eip = vcpu->arch.last_retry_eip;
7106 last_retry_addr = vcpu->arch.last_retry_addr;
7109 * If the emulation is caused by #PF and it is non-page_table
7110 * writing instruction, it means the VM-EXIT is caused by shadow
7111 * page protected, we can zap the shadow page and retry this
7112 * instruction directly.
7114 * Note: if the guest uses a non-page-table modifying instruction
7115 * on the PDE that points to the instruction, then we will unmap
7116 * the instruction and go to an infinite loop. So, we cache the
7117 * last retried eip and the last fault address, if we meet the eip
7118 * and the address again, we can break out of the potential infinite
7121 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
7123 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7126 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7127 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7130 if (x86_page_table_writing_insn(ctxt))
7133 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
7136 vcpu->arch.last_retry_eip = ctxt->eip;
7137 vcpu->arch.last_retry_addr = cr2_or_gpa;
7139 if (!vcpu->arch.mmu->direct_map)
7140 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7142 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7147 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
7148 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
7150 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
7152 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
7153 /* This is a good place to trace that we are exiting SMM. */
7154 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
7156 /* Process a latched INIT or SMI, if any. */
7157 kvm_make_request(KVM_REQ_EVENT, vcpu);
7160 kvm_mmu_reset_context(vcpu);
7163 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
7172 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
7173 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
7178 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
7180 struct kvm_run *kvm_run = vcpu->run;
7182 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
7183 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
7184 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
7185 kvm_run->debug.arch.exception = DB_VECTOR;
7186 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7189 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
7193 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
7195 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7198 r = kvm_x86_ops.skip_emulated_instruction(vcpu);
7203 * rflags is the old, "raw" value of the flags. The new value has
7204 * not been saved yet.
7206 * This is correct even for TF set by the guest, because "the
7207 * processor will not generate this exception after the instruction
7208 * that sets the TF flag".
7210 if (unlikely(rflags & X86_EFLAGS_TF))
7211 r = kvm_vcpu_do_singlestep(vcpu);
7214 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
7216 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
7218 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
7219 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
7220 struct kvm_run *kvm_run = vcpu->run;
7221 unsigned long eip = kvm_get_linear_rip(vcpu);
7222 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7223 vcpu->arch.guest_debug_dr7,
7227 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
7228 kvm_run->debug.arch.pc = eip;
7229 kvm_run->debug.arch.exception = DB_VECTOR;
7230 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7236 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
7237 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
7238 unsigned long eip = kvm_get_linear_rip(vcpu);
7239 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7244 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
7253 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
7255 switch (ctxt->opcode_len) {
7262 case 0xe6: /* OUT */
7266 case 0x6c: /* INS */
7268 case 0x6e: /* OUTS */
7275 case 0x33: /* RDPMC */
7284 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7285 int emulation_type, void *insn, int insn_len)
7288 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7289 bool writeback = true;
7290 bool write_fault_to_spt;
7292 if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, insn, insn_len)))
7295 vcpu->arch.l1tf_flush_l1d = true;
7298 * Clear write_fault_to_shadow_pgtable here to ensure it is
7301 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
7302 vcpu->arch.write_fault_to_shadow_pgtable = false;
7303 kvm_clear_exception_queue(vcpu);
7305 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
7306 init_emulate_ctxt(vcpu);
7309 * We will reenter on the same instruction since
7310 * we do not set complete_userspace_io. This does not
7311 * handle watchpoints yet, those would be handled in
7314 if (!(emulation_type & EMULTYPE_SKIP) &&
7315 kvm_vcpu_check_breakpoint(vcpu, &r))
7318 ctxt->interruptibility = 0;
7319 ctxt->have_exception = false;
7320 ctxt->exception.vector = -1;
7321 ctxt->perm_ok = false;
7323 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
7325 r = x86_decode_insn(ctxt, insn, insn_len);
7327 trace_kvm_emulate_insn_start(vcpu);
7328 ++vcpu->stat.insn_emulation;
7329 if (r != EMULATION_OK) {
7330 if ((emulation_type & EMULTYPE_TRAP_UD) ||
7331 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
7332 kvm_queue_exception(vcpu, UD_VECTOR);
7335 if (reexecute_instruction(vcpu, cr2_or_gpa,
7339 if (ctxt->have_exception) {
7341 * #UD should result in just EMULATION_FAILED, and trap-like
7342 * exception should not be encountered during decode.
7344 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
7345 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
7346 inject_emulated_exception(vcpu);
7349 return handle_emulation_failure(vcpu, emulation_type);
7353 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
7354 !is_vmware_backdoor_opcode(ctxt)) {
7355 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7360 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
7361 * for kvm_skip_emulated_instruction(). The caller is responsible for
7362 * updating interruptibility state and injecting single-step #DBs.
7364 if (emulation_type & EMULTYPE_SKIP) {
7365 kvm_rip_write(vcpu, ctxt->_eip);
7366 if (ctxt->eflags & X86_EFLAGS_RF)
7367 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
7371 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
7374 /* this is needed for vmware backdoor interface to work since it
7375 changes registers values during IO operation */
7376 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
7377 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7378 emulator_invalidate_register_cache(ctxt);
7382 if (emulation_type & EMULTYPE_PF) {
7383 /* Save the faulting GPA (cr2) in the address field */
7384 ctxt->exception.address = cr2_or_gpa;
7386 /* With shadow page tables, cr2 contains a GVA or nGPA. */
7387 if (vcpu->arch.mmu->direct_map) {
7388 ctxt->gpa_available = true;
7389 ctxt->gpa_val = cr2_or_gpa;
7392 /* Sanitize the address out of an abundance of paranoia. */
7393 ctxt->exception.address = 0;
7396 r = x86_emulate_insn(ctxt);
7398 if (r == EMULATION_INTERCEPTED)
7401 if (r == EMULATION_FAILED) {
7402 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
7406 return handle_emulation_failure(vcpu, emulation_type);
7409 if (ctxt->have_exception) {
7411 if (inject_emulated_exception(vcpu))
7413 } else if (vcpu->arch.pio.count) {
7414 if (!vcpu->arch.pio.in) {
7415 /* FIXME: return into emulator if single-stepping. */
7416 vcpu->arch.pio.count = 0;
7419 vcpu->arch.complete_userspace_io = complete_emulated_pio;
7422 } else if (vcpu->mmio_needed) {
7423 ++vcpu->stat.mmio_exits;
7425 if (!vcpu->mmio_is_write)
7428 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7429 } else if (r == EMULATION_RESTART)
7435 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7436 toggle_interruptibility(vcpu, ctxt->interruptibility);
7437 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7438 if (!ctxt->have_exception ||
7439 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
7440 kvm_rip_write(vcpu, ctxt->eip);
7441 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
7442 r = kvm_vcpu_do_singlestep(vcpu);
7443 if (kvm_x86_ops.update_emulated_instruction)
7444 kvm_x86_ops.update_emulated_instruction(vcpu);
7445 __kvm_set_rflags(vcpu, ctxt->eflags);
7449 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
7450 * do nothing, and it will be requested again as soon as
7451 * the shadow expires. But we still need to check here,
7452 * because POPF has no interrupt shadow.
7454 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
7455 kvm_make_request(KVM_REQ_EVENT, vcpu);
7457 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
7462 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
7464 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
7466 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
7468 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
7469 void *insn, int insn_len)
7471 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
7473 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
7475 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
7477 vcpu->arch.pio.count = 0;
7481 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
7483 vcpu->arch.pio.count = 0;
7485 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
7488 return kvm_skip_emulated_instruction(vcpu);
7491 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
7492 unsigned short port)
7494 unsigned long val = kvm_rax_read(vcpu);
7495 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
7501 * Workaround userspace that relies on old KVM behavior of %rip being
7502 * incremented prior to exiting to userspace to handle "OUT 0x7e".
7505 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
7506 vcpu->arch.complete_userspace_io =
7507 complete_fast_pio_out_port_0x7e;
7508 kvm_skip_emulated_instruction(vcpu);
7510 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7511 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
7516 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
7520 /* We should only ever be called with arch.pio.count equal to 1 */
7521 BUG_ON(vcpu->arch.pio.count != 1);
7523 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
7524 vcpu->arch.pio.count = 0;
7528 /* For size less than 4 we merge, else we zero extend */
7529 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7532 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7533 * the copy and tracing
7535 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7536 kvm_rax_write(vcpu, val);
7538 return kvm_skip_emulated_instruction(vcpu);
7541 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7542 unsigned short port)
7547 /* For size less than 4 we merge, else we zero extend */
7548 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7550 ret = emulator_pio_in(vcpu, size, port, &val, 1);
7552 kvm_rax_write(vcpu, val);
7556 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7557 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7562 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7567 ret = kvm_fast_pio_in(vcpu, size, port);
7569 ret = kvm_fast_pio_out(vcpu, size, port);
7570 return ret && kvm_skip_emulated_instruction(vcpu);
7572 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7574 static int kvmclock_cpu_down_prep(unsigned int cpu)
7576 __this_cpu_write(cpu_tsc_khz, 0);
7580 static void tsc_khz_changed(void *data)
7582 struct cpufreq_freqs *freq = data;
7583 unsigned long khz = 0;
7587 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7588 khz = cpufreq_quick_get(raw_smp_processor_id());
7591 __this_cpu_write(cpu_tsc_khz, khz);
7594 #ifdef CONFIG_X86_64
7595 static void kvm_hyperv_tsc_notifier(void)
7598 struct kvm_vcpu *vcpu;
7601 mutex_lock(&kvm_lock);
7602 list_for_each_entry(kvm, &vm_list, vm_list)
7603 kvm_make_mclock_inprogress_request(kvm);
7605 hyperv_stop_tsc_emulation();
7607 /* TSC frequency always matches when on Hyper-V */
7608 for_each_present_cpu(cpu)
7609 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7610 kvm_max_guest_tsc_khz = tsc_khz;
7612 list_for_each_entry(kvm, &vm_list, vm_list) {
7613 struct kvm_arch *ka = &kvm->arch;
7615 spin_lock(&ka->pvclock_gtod_sync_lock);
7617 pvclock_update_vm_gtod_copy(kvm);
7619 kvm_for_each_vcpu(cpu, vcpu, kvm)
7620 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7622 kvm_for_each_vcpu(cpu, vcpu, kvm)
7623 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7625 spin_unlock(&ka->pvclock_gtod_sync_lock);
7627 mutex_unlock(&kvm_lock);
7631 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7634 struct kvm_vcpu *vcpu;
7635 int i, send_ipi = 0;
7638 * We allow guests to temporarily run on slowing clocks,
7639 * provided we notify them after, or to run on accelerating
7640 * clocks, provided we notify them before. Thus time never
7643 * However, we have a problem. We can't atomically update
7644 * the frequency of a given CPU from this function; it is
7645 * merely a notifier, which can be called from any CPU.
7646 * Changing the TSC frequency at arbitrary points in time
7647 * requires a recomputation of local variables related to
7648 * the TSC for each VCPU. We must flag these local variables
7649 * to be updated and be sure the update takes place with the
7650 * new frequency before any guests proceed.
7652 * Unfortunately, the combination of hotplug CPU and frequency
7653 * change creates an intractable locking scenario; the order
7654 * of when these callouts happen is undefined with respect to
7655 * CPU hotplug, and they can race with each other. As such,
7656 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7657 * undefined; you can actually have a CPU frequency change take
7658 * place in between the computation of X and the setting of the
7659 * variable. To protect against this problem, all updates of
7660 * the per_cpu tsc_khz variable are done in an interrupt
7661 * protected IPI, and all callers wishing to update the value
7662 * must wait for a synchronous IPI to complete (which is trivial
7663 * if the caller is on the CPU already). This establishes the
7664 * necessary total order on variable updates.
7666 * Note that because a guest time update may take place
7667 * anytime after the setting of the VCPU's request bit, the
7668 * correct TSC value must be set before the request. However,
7669 * to ensure the update actually makes it to any guest which
7670 * starts running in hardware virtualization between the set
7671 * and the acquisition of the spinlock, we must also ping the
7672 * CPU after setting the request bit.
7676 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7678 mutex_lock(&kvm_lock);
7679 list_for_each_entry(kvm, &vm_list, vm_list) {
7680 kvm_for_each_vcpu(i, vcpu, kvm) {
7681 if (vcpu->cpu != cpu)
7683 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7684 if (vcpu->cpu != raw_smp_processor_id())
7688 mutex_unlock(&kvm_lock);
7690 if (freq->old < freq->new && send_ipi) {
7692 * We upscale the frequency. Must make the guest
7693 * doesn't see old kvmclock values while running with
7694 * the new frequency, otherwise we risk the guest sees
7695 * time go backwards.
7697 * In case we update the frequency for another cpu
7698 * (which might be in guest context) send an interrupt
7699 * to kick the cpu out of guest context. Next time
7700 * guest context is entered kvmclock will be updated,
7701 * so the guest will not see stale values.
7703 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7707 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7710 struct cpufreq_freqs *freq = data;
7713 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7715 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7718 for_each_cpu(cpu, freq->policy->cpus)
7719 __kvmclock_cpufreq_notifier(freq, cpu);
7724 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7725 .notifier_call = kvmclock_cpufreq_notifier
7728 static int kvmclock_cpu_online(unsigned int cpu)
7730 tsc_khz_changed(NULL);
7734 static void kvm_timer_init(void)
7736 max_tsc_khz = tsc_khz;
7738 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7739 #ifdef CONFIG_CPU_FREQ
7740 struct cpufreq_policy *policy;
7744 policy = cpufreq_cpu_get(cpu);
7746 if (policy->cpuinfo.max_freq)
7747 max_tsc_khz = policy->cpuinfo.max_freq;
7748 cpufreq_cpu_put(policy);
7752 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7753 CPUFREQ_TRANSITION_NOTIFIER);
7756 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7757 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7760 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7761 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7763 int kvm_is_in_guest(void)
7765 return __this_cpu_read(current_vcpu) != NULL;
7768 static int kvm_is_user_mode(void)
7772 if (__this_cpu_read(current_vcpu))
7773 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu));
7775 return user_mode != 0;
7778 static unsigned long kvm_get_guest_ip(void)
7780 unsigned long ip = 0;
7782 if (__this_cpu_read(current_vcpu))
7783 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7788 static void kvm_handle_intel_pt_intr(void)
7790 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7792 kvm_make_request(KVM_REQ_PMI, vcpu);
7793 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7794 (unsigned long *)&vcpu->arch.pmu.global_status);
7797 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7798 .is_in_guest = kvm_is_in_guest,
7799 .is_user_mode = kvm_is_user_mode,
7800 .get_guest_ip = kvm_get_guest_ip,
7801 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7804 #ifdef CONFIG_X86_64
7805 static void pvclock_gtod_update_fn(struct work_struct *work)
7809 struct kvm_vcpu *vcpu;
7812 mutex_lock(&kvm_lock);
7813 list_for_each_entry(kvm, &vm_list, vm_list)
7814 kvm_for_each_vcpu(i, vcpu, kvm)
7815 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7816 atomic_set(&kvm_guest_has_master_clock, 0);
7817 mutex_unlock(&kvm_lock);
7820 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7823 * Notification about pvclock gtod data update.
7825 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7828 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7829 struct timekeeper *tk = priv;
7831 update_pvclock_gtod(tk);
7833 /* disable master clock if host does not trust, or does not
7834 * use, TSC based clocksource.
7836 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7837 atomic_read(&kvm_guest_has_master_clock) != 0)
7838 queue_work(system_long_wq, &pvclock_gtod_work);
7843 static struct notifier_block pvclock_gtod_notifier = {
7844 .notifier_call = pvclock_gtod_notify,
7848 int kvm_arch_init(void *opaque)
7850 struct kvm_x86_init_ops *ops = opaque;
7853 if (kvm_x86_ops.hardware_enable) {
7854 printk(KERN_ERR "kvm: already loaded the other module\n");
7859 if (!ops->cpu_has_kvm_support()) {
7860 pr_err_ratelimited("kvm: no hardware support\n");
7864 if (ops->disabled_by_bios()) {
7865 pr_err_ratelimited("kvm: disabled by bios\n");
7871 * KVM explicitly assumes that the guest has an FPU and
7872 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7873 * vCPU's FPU state as a fxregs_state struct.
7875 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7876 printk(KERN_ERR "kvm: inadequate fpu\n");
7882 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7883 __alignof__(struct fpu), SLAB_ACCOUNT,
7885 if (!x86_fpu_cache) {
7886 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7890 x86_emulator_cache = kvm_alloc_emulator_cache();
7891 if (!x86_emulator_cache) {
7892 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7893 goto out_free_x86_fpu_cache;
7896 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
7897 if (!user_return_msrs) {
7898 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
7899 goto out_free_x86_emulator_cache;
7902 r = kvm_mmu_module_init();
7904 goto out_free_percpu;
7906 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7907 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7908 PT_PRESENT_MASK, 0, sme_me_mask);
7911 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7913 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7914 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7915 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7919 if (pi_inject_timer == -1)
7920 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7921 #ifdef CONFIG_X86_64
7922 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7924 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7925 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7931 free_percpu(user_return_msrs);
7932 out_free_x86_emulator_cache:
7933 kmem_cache_destroy(x86_emulator_cache);
7934 out_free_x86_fpu_cache:
7935 kmem_cache_destroy(x86_fpu_cache);
7940 void kvm_arch_exit(void)
7942 #ifdef CONFIG_X86_64
7943 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7944 clear_hv_tscchange_cb();
7947 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7949 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7950 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7951 CPUFREQ_TRANSITION_NOTIFIER);
7952 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7953 #ifdef CONFIG_X86_64
7954 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7956 kvm_x86_ops.hardware_enable = NULL;
7957 kvm_mmu_module_exit();
7958 free_percpu(user_return_msrs);
7959 kmem_cache_destroy(x86_fpu_cache);
7962 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7964 ++vcpu->stat.halt_exits;
7965 if (lapic_in_kernel(vcpu)) {
7966 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7969 vcpu->run->exit_reason = KVM_EXIT_HLT;
7973 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7975 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7977 int ret = kvm_skip_emulated_instruction(vcpu);
7979 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7980 * KVM_EXIT_DEBUG here.
7982 return kvm_vcpu_halt(vcpu) && ret;
7984 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7986 #ifdef CONFIG_X86_64
7987 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7988 unsigned long clock_type)
7990 struct kvm_clock_pairing clock_pairing;
7991 struct timespec64 ts;
7995 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7996 return -KVM_EOPNOTSUPP;
7998 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7999 return -KVM_EOPNOTSUPP;
8001 clock_pairing.sec = ts.tv_sec;
8002 clock_pairing.nsec = ts.tv_nsec;
8003 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
8004 clock_pairing.flags = 0;
8005 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
8008 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
8009 sizeof(struct kvm_clock_pairing)))
8017 * kvm_pv_kick_cpu_op: Kick a vcpu.
8019 * @apicid - apicid of vcpu to be kicked.
8021 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
8023 struct kvm_lapic_irq lapic_irq;
8025 lapic_irq.shorthand = APIC_DEST_NOSHORT;
8026 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
8027 lapic_irq.level = 0;
8028 lapic_irq.dest_id = apicid;
8029 lapic_irq.msi_redir_hint = false;
8031 lapic_irq.delivery_mode = APIC_DM_REMRD;
8032 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
8035 bool kvm_apicv_activated(struct kvm *kvm)
8037 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
8039 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
8041 void kvm_apicv_init(struct kvm *kvm, bool enable)
8044 clear_bit(APICV_INHIBIT_REASON_DISABLE,
8045 &kvm->arch.apicv_inhibit_reasons);
8047 set_bit(APICV_INHIBIT_REASON_DISABLE,
8048 &kvm->arch.apicv_inhibit_reasons);
8050 EXPORT_SYMBOL_GPL(kvm_apicv_init);
8052 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
8054 struct kvm_vcpu *target = NULL;
8055 struct kvm_apic_map *map;
8058 map = rcu_dereference(kvm->arch.apic_map);
8060 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
8061 target = map->phys_map[dest_id]->vcpu;
8065 if (target && READ_ONCE(target->ready))
8066 kvm_vcpu_yield_to(target);
8069 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
8071 unsigned long nr, a0, a1, a2, a3, ret;
8074 if (kvm_hv_hypercall_enabled(vcpu->kvm))
8075 return kvm_hv_hypercall(vcpu);
8077 nr = kvm_rax_read(vcpu);
8078 a0 = kvm_rbx_read(vcpu);
8079 a1 = kvm_rcx_read(vcpu);
8080 a2 = kvm_rdx_read(vcpu);
8081 a3 = kvm_rsi_read(vcpu);
8083 trace_kvm_hypercall(nr, a0, a1, a2, a3);
8085 op_64_bit = is_64_bit_mode(vcpu);
8094 if (kvm_x86_ops.get_cpl(vcpu) != 0) {
8102 case KVM_HC_VAPIC_POLL_IRQ:
8105 case KVM_HC_KICK_CPU:
8106 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
8109 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
8110 kvm_sched_yield(vcpu->kvm, a1);
8113 #ifdef CONFIG_X86_64
8114 case KVM_HC_CLOCK_PAIRING:
8115 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
8118 case KVM_HC_SEND_IPI:
8119 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
8122 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
8124 case KVM_HC_SCHED_YIELD:
8125 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
8128 kvm_sched_yield(vcpu->kvm, a0);
8138 kvm_rax_write(vcpu, ret);
8140 ++vcpu->stat.hypercalls;
8141 return kvm_skip_emulated_instruction(vcpu);
8143 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
8145 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8147 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8148 char instruction[3];
8149 unsigned long rip = kvm_rip_read(vcpu);
8151 kvm_x86_ops.patch_hypercall(vcpu, instruction);
8153 return emulator_write_emulated(ctxt, rip, instruction, 3,
8157 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
8159 return vcpu->run->request_interrupt_window &&
8160 likely(!pic_in_kernel(vcpu->kvm));
8163 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
8165 struct kvm_run *kvm_run = vcpu->run;
8167 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
8168 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
8169 kvm_run->cr8 = kvm_get_cr8(vcpu);
8170 kvm_run->apic_base = kvm_get_apic_base(vcpu);
8171 kvm_run->ready_for_interrupt_injection =
8172 pic_in_kernel(vcpu->kvm) ||
8173 kvm_vcpu_ready_for_interrupt_injection(vcpu);
8176 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
8180 if (!kvm_x86_ops.update_cr8_intercept)
8183 if (!lapic_in_kernel(vcpu))
8186 if (vcpu->arch.apicv_active)
8189 if (!vcpu->arch.apic->vapic_addr)
8190 max_irr = kvm_lapic_find_highest_irr(vcpu);
8197 tpr = kvm_lapic_get_cr8(vcpu);
8199 kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr);
8202 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
8205 bool can_inject = true;
8207 /* try to reinject previous events if any */
8209 if (vcpu->arch.exception.injected) {
8210 kvm_x86_ops.queue_exception(vcpu);
8214 * Do not inject an NMI or interrupt if there is a pending
8215 * exception. Exceptions and interrupts are recognized at
8216 * instruction boundaries, i.e. the start of an instruction.
8217 * Trap-like exceptions, e.g. #DB, have higher priority than
8218 * NMIs and interrupts, i.e. traps are recognized before an
8219 * NMI/interrupt that's pending on the same instruction.
8220 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
8221 * priority, but are only generated (pended) during instruction
8222 * execution, i.e. a pending fault-like exception means the
8223 * fault occurred on the *previous* instruction and must be
8224 * serviced prior to recognizing any new events in order to
8225 * fully complete the previous instruction.
8227 else if (!vcpu->arch.exception.pending) {
8228 if (vcpu->arch.nmi_injected) {
8229 kvm_x86_ops.set_nmi(vcpu);
8231 } else if (vcpu->arch.interrupt.injected) {
8232 kvm_x86_ops.set_irq(vcpu);
8237 WARN_ON_ONCE(vcpu->arch.exception.injected &&
8238 vcpu->arch.exception.pending);
8241 * Call check_nested_events() even if we reinjected a previous event
8242 * in order for caller to determine if it should require immediate-exit
8243 * from L2 to L1 due to pending L1 events which require exit
8246 if (is_guest_mode(vcpu)) {
8247 r = kvm_x86_ops.nested_ops->check_events(vcpu);
8252 /* try to inject new event if pending */
8253 if (vcpu->arch.exception.pending) {
8254 trace_kvm_inj_exception(vcpu->arch.exception.nr,
8255 vcpu->arch.exception.has_error_code,
8256 vcpu->arch.exception.error_code);
8258 vcpu->arch.exception.pending = false;
8259 vcpu->arch.exception.injected = true;
8261 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
8262 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
8265 if (vcpu->arch.exception.nr == DB_VECTOR) {
8266 kvm_deliver_exception_payload(vcpu);
8267 if (vcpu->arch.dr7 & DR7_GD) {
8268 vcpu->arch.dr7 &= ~DR7_GD;
8269 kvm_update_dr7(vcpu);
8273 kvm_x86_ops.queue_exception(vcpu);
8278 * Finally, inject interrupt events. If an event cannot be injected
8279 * due to architectural conditions (e.g. IF=0) a window-open exit
8280 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
8281 * and can architecturally be injected, but we cannot do it right now:
8282 * an interrupt could have arrived just now and we have to inject it
8283 * as a vmexit, or there could already an event in the queue, which is
8284 * indicated by can_inject. In that case we request an immediate exit
8285 * in order to make progress and get back here for another iteration.
8286 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
8288 if (vcpu->arch.smi_pending) {
8289 r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY;
8293 vcpu->arch.smi_pending = false;
8294 ++vcpu->arch.smi_count;
8298 kvm_x86_ops.enable_smi_window(vcpu);
8301 if (vcpu->arch.nmi_pending) {
8302 r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY;
8306 --vcpu->arch.nmi_pending;
8307 vcpu->arch.nmi_injected = true;
8308 kvm_x86_ops.set_nmi(vcpu);
8310 WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0);
8312 if (vcpu->arch.nmi_pending)
8313 kvm_x86_ops.enable_nmi_window(vcpu);
8316 if (kvm_cpu_has_injectable_intr(vcpu)) {
8317 r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY;
8321 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
8322 kvm_x86_ops.set_irq(vcpu);
8323 WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0);
8325 if (kvm_cpu_has_injectable_intr(vcpu))
8326 kvm_x86_ops.enable_irq_window(vcpu);
8329 if (is_guest_mode(vcpu) &&
8330 kvm_x86_ops.nested_ops->hv_timer_pending &&
8331 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
8332 *req_immediate_exit = true;
8334 WARN_ON(vcpu->arch.exception.pending);
8338 *req_immediate_exit = true;
8342 static void process_nmi(struct kvm_vcpu *vcpu)
8347 * x86 is limited to one NMI running, and one NMI pending after it.
8348 * If an NMI is already in progress, limit further NMIs to just one.
8349 * Otherwise, allow two (and we'll inject the first one immediately).
8351 if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
8354 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
8355 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
8356 kvm_make_request(KVM_REQ_EVENT, vcpu);
8359 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
8362 flags |= seg->g << 23;
8363 flags |= seg->db << 22;
8364 flags |= seg->l << 21;
8365 flags |= seg->avl << 20;
8366 flags |= seg->present << 15;
8367 flags |= seg->dpl << 13;
8368 flags |= seg->s << 12;
8369 flags |= seg->type << 8;
8373 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
8375 struct kvm_segment seg;
8378 kvm_get_segment(vcpu, &seg, n);
8379 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
8382 offset = 0x7f84 + n * 12;
8384 offset = 0x7f2c + (n - 3) * 12;
8386 put_smstate(u32, buf, offset + 8, seg.base);
8387 put_smstate(u32, buf, offset + 4, seg.limit);
8388 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
8391 #ifdef CONFIG_X86_64
8392 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
8394 struct kvm_segment seg;
8398 kvm_get_segment(vcpu, &seg, n);
8399 offset = 0x7e00 + n * 16;
8401 flags = enter_smm_get_segment_flags(&seg) >> 8;
8402 put_smstate(u16, buf, offset, seg.selector);
8403 put_smstate(u16, buf, offset + 2, flags);
8404 put_smstate(u32, buf, offset + 4, seg.limit);
8405 put_smstate(u64, buf, offset + 8, seg.base);
8409 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
8412 struct kvm_segment seg;
8416 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
8417 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
8418 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
8419 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
8421 for (i = 0; i < 8; i++)
8422 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
8424 kvm_get_dr(vcpu, 6, &val);
8425 put_smstate(u32, buf, 0x7fcc, (u32)val);
8426 kvm_get_dr(vcpu, 7, &val);
8427 put_smstate(u32, buf, 0x7fc8, (u32)val);
8429 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8430 put_smstate(u32, buf, 0x7fc4, seg.selector);
8431 put_smstate(u32, buf, 0x7f64, seg.base);
8432 put_smstate(u32, buf, 0x7f60, seg.limit);
8433 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
8435 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8436 put_smstate(u32, buf, 0x7fc0, seg.selector);
8437 put_smstate(u32, buf, 0x7f80, seg.base);
8438 put_smstate(u32, buf, 0x7f7c, seg.limit);
8439 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
8441 kvm_x86_ops.get_gdt(vcpu, &dt);
8442 put_smstate(u32, buf, 0x7f74, dt.address);
8443 put_smstate(u32, buf, 0x7f70, dt.size);
8445 kvm_x86_ops.get_idt(vcpu, &dt);
8446 put_smstate(u32, buf, 0x7f58, dt.address);
8447 put_smstate(u32, buf, 0x7f54, dt.size);
8449 for (i = 0; i < 6; i++)
8450 enter_smm_save_seg_32(vcpu, buf, i);
8452 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
8455 put_smstate(u32, buf, 0x7efc, 0x00020000);
8456 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
8459 #ifdef CONFIG_X86_64
8460 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
8463 struct kvm_segment seg;
8467 for (i = 0; i < 16; i++)
8468 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
8470 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
8471 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
8473 kvm_get_dr(vcpu, 6, &val);
8474 put_smstate(u64, buf, 0x7f68, val);
8475 kvm_get_dr(vcpu, 7, &val);
8476 put_smstate(u64, buf, 0x7f60, val);
8478 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
8479 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
8480 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
8482 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
8485 put_smstate(u32, buf, 0x7efc, 0x00020064);
8487 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
8489 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8490 put_smstate(u16, buf, 0x7e90, seg.selector);
8491 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
8492 put_smstate(u32, buf, 0x7e94, seg.limit);
8493 put_smstate(u64, buf, 0x7e98, seg.base);
8495 kvm_x86_ops.get_idt(vcpu, &dt);
8496 put_smstate(u32, buf, 0x7e84, dt.size);
8497 put_smstate(u64, buf, 0x7e88, dt.address);
8499 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8500 put_smstate(u16, buf, 0x7e70, seg.selector);
8501 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
8502 put_smstate(u32, buf, 0x7e74, seg.limit);
8503 put_smstate(u64, buf, 0x7e78, seg.base);
8505 kvm_x86_ops.get_gdt(vcpu, &dt);
8506 put_smstate(u32, buf, 0x7e64, dt.size);
8507 put_smstate(u64, buf, 0x7e68, dt.address);
8509 for (i = 0; i < 6; i++)
8510 enter_smm_save_seg_64(vcpu, buf, i);
8514 static void enter_smm(struct kvm_vcpu *vcpu)
8516 struct kvm_segment cs, ds;
8521 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
8522 memset(buf, 0, 512);
8523 #ifdef CONFIG_X86_64
8524 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8525 enter_smm_save_state_64(vcpu, buf);
8528 enter_smm_save_state_32(vcpu, buf);
8531 * Give pre_enter_smm() a chance to make ISA-specific changes to the
8532 * vCPU state (e.g. leave guest mode) after we've saved the state into
8533 * the SMM state-save area.
8535 kvm_x86_ops.pre_enter_smm(vcpu, buf);
8537 vcpu->arch.hflags |= HF_SMM_MASK;
8538 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
8540 if (kvm_x86_ops.get_nmi_mask(vcpu))
8541 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
8543 kvm_x86_ops.set_nmi_mask(vcpu, true);
8545 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
8546 kvm_rip_write(vcpu, 0x8000);
8548 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
8549 kvm_x86_ops.set_cr0(vcpu, cr0);
8550 vcpu->arch.cr0 = cr0;
8552 kvm_x86_ops.set_cr4(vcpu, 0);
8554 /* Undocumented: IDT limit is set to zero on entry to SMM. */
8555 dt.address = dt.size = 0;
8556 kvm_x86_ops.set_idt(vcpu, &dt);
8558 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
8560 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
8561 cs.base = vcpu->arch.smbase;
8566 cs.limit = ds.limit = 0xffffffff;
8567 cs.type = ds.type = 0x3;
8568 cs.dpl = ds.dpl = 0;
8573 cs.avl = ds.avl = 0;
8574 cs.present = ds.present = 1;
8575 cs.unusable = ds.unusable = 0;
8576 cs.padding = ds.padding = 0;
8578 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8579 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8580 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8581 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8582 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8583 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8585 #ifdef CONFIG_X86_64
8586 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8587 kvm_x86_ops.set_efer(vcpu, 0);
8590 kvm_update_cpuid_runtime(vcpu);
8591 kvm_mmu_reset_context(vcpu);
8594 static void process_smi(struct kvm_vcpu *vcpu)
8596 vcpu->arch.smi_pending = true;
8597 kvm_make_request(KVM_REQ_EVENT, vcpu);
8600 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8601 unsigned long *vcpu_bitmap)
8605 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8607 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8608 NULL, vcpu_bitmap, cpus);
8610 free_cpumask_var(cpus);
8613 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8615 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8618 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8620 if (!lapic_in_kernel(vcpu))
8623 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8624 kvm_apic_update_apicv(vcpu);
8625 kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu);
8627 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8630 * NOTE: Do not hold any lock prior to calling this.
8632 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8633 * locked, because it calls __x86_set_memory_region() which does
8634 * synchronize_srcu(&kvm->srcu).
8636 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8638 struct kvm_vcpu *except;
8639 unsigned long old, new, expected;
8641 if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8642 !kvm_x86_ops.check_apicv_inhibit_reasons(bit))
8645 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8647 expected = new = old;
8649 __clear_bit(bit, &new);
8651 __set_bit(bit, &new);
8654 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8655 } while (old != expected);
8660 trace_kvm_apicv_update_request(activate, bit);
8661 if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8662 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate);
8665 * Sending request to update APICV for all other vcpus,
8666 * while update the calling vcpu immediately instead of
8667 * waiting for another #VMEXIT to handle the request.
8669 except = kvm_get_running_vcpu();
8670 kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE,
8673 kvm_vcpu_update_apicv(except);
8675 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8677 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8679 if (!kvm_apic_present(vcpu))
8682 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8684 if (irqchip_split(vcpu->kvm))
8685 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8687 if (vcpu->arch.apicv_active)
8688 kvm_x86_ops.sync_pir_to_irr(vcpu);
8689 if (ioapic_in_kernel(vcpu->kvm))
8690 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8693 if (is_guest_mode(vcpu))
8694 vcpu->arch.load_eoi_exitmap_pending = true;
8696 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8699 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8701 u64 eoi_exit_bitmap[4];
8703 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8706 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8707 vcpu_to_synic(vcpu)->vec_bitmap, 256);
8708 kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8711 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8712 unsigned long start, unsigned long end)
8714 unsigned long apic_address;
8717 * The physical address of apic access page is stored in the VMCS.
8718 * Update it when it becomes invalid.
8720 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8721 if (start <= apic_address && apic_address < end)
8722 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8725 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8727 if (!lapic_in_kernel(vcpu))
8730 if (!kvm_x86_ops.set_apic_access_page_addr)
8733 kvm_x86_ops.set_apic_access_page_addr(vcpu);
8736 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8738 smp_send_reschedule(vcpu->cpu);
8740 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8743 * Returns 1 to let vcpu_run() continue the guest execution loop without
8744 * exiting to the userspace. Otherwise, the value will be returned to the
8747 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8751 dm_request_for_irq_injection(vcpu) &&
8752 kvm_cpu_accept_dm_intr(vcpu);
8753 fastpath_t exit_fastpath;
8755 bool req_immediate_exit = false;
8757 if (kvm_request_pending(vcpu)) {
8758 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
8759 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
8764 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8765 kvm_mmu_unload(vcpu);
8766 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8767 __kvm_migrate_timers(vcpu);
8768 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8769 kvm_gen_update_masterclock(vcpu->kvm);
8770 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8771 kvm_gen_kvmclock_update(vcpu);
8772 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8773 r = kvm_guest_time_update(vcpu);
8777 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8778 kvm_mmu_sync_roots(vcpu);
8779 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8780 kvm_mmu_load_pgd(vcpu);
8781 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
8782 kvm_vcpu_flush_tlb_all(vcpu);
8784 /* Flushing all ASIDs flushes the current ASID... */
8785 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
8787 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
8788 kvm_vcpu_flush_tlb_current(vcpu);
8789 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu))
8790 kvm_vcpu_flush_tlb_guest(vcpu);
8792 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8793 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8797 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8798 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8799 vcpu->mmio_needed = 0;
8803 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8804 /* Page is swapped out. Do synthetic halt */
8805 vcpu->arch.apf.halted = true;
8809 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8810 record_steal_time(vcpu);
8811 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8813 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8815 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8816 kvm_pmu_handle_event(vcpu);
8817 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8818 kvm_pmu_deliver_pmi(vcpu);
8819 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8820 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8821 if (test_bit(vcpu->arch.pending_ioapic_eoi,
8822 vcpu->arch.ioapic_handled_vectors)) {
8823 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8824 vcpu->run->eoi.vector =
8825 vcpu->arch.pending_ioapic_eoi;
8830 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8831 vcpu_scan_ioapic(vcpu);
8832 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8833 vcpu_load_eoi_exitmap(vcpu);
8834 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8835 kvm_vcpu_reload_apic_access_page(vcpu);
8836 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8837 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8838 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8842 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8843 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8844 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8848 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8849 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8850 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8856 * KVM_REQ_HV_STIMER has to be processed after
8857 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8858 * depend on the guest clock being up-to-date
8860 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8861 kvm_hv_process_stimers(vcpu);
8862 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8863 kvm_vcpu_update_apicv(vcpu);
8864 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
8865 kvm_check_async_pf_completion(vcpu);
8866 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
8867 kvm_x86_ops.msr_filter_changed(vcpu);
8870 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8871 ++vcpu->stat.req_event;
8872 kvm_apic_accept_events(vcpu);
8873 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8878 inject_pending_event(vcpu, &req_immediate_exit);
8880 kvm_x86_ops.enable_irq_window(vcpu);
8882 if (kvm_lapic_enabled(vcpu)) {
8883 update_cr8_intercept(vcpu);
8884 kvm_lapic_sync_to_vapic(vcpu);
8888 r = kvm_mmu_reload(vcpu);
8890 goto cancel_injection;
8895 kvm_x86_ops.prepare_guest_switch(vcpu);
8898 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8899 * IPI are then delayed after guest entry, which ensures that they
8900 * result in virtual interrupt delivery.
8902 local_irq_disable();
8903 vcpu->mode = IN_GUEST_MODE;
8905 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8908 * 1) We should set ->mode before checking ->requests. Please see
8909 * the comment in kvm_vcpu_exiting_guest_mode().
8911 * 2) For APICv, we should set ->mode before checking PID.ON. This
8912 * pairs with the memory barrier implicit in pi_test_and_set_on
8913 * (see vmx_deliver_posted_interrupt).
8915 * 3) This also orders the write to mode from any reads to the page
8916 * tables done while the VCPU is running. Please see the comment
8917 * in kvm_flush_remote_tlbs.
8919 smp_mb__after_srcu_read_unlock();
8922 * This handles the case where a posted interrupt was
8923 * notified with kvm_vcpu_kick.
8925 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8926 kvm_x86_ops.sync_pir_to_irr(vcpu);
8928 if (kvm_vcpu_exit_request(vcpu)) {
8929 vcpu->mode = OUTSIDE_GUEST_MODE;
8933 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8935 goto cancel_injection;
8938 if (req_immediate_exit) {
8939 kvm_make_request(KVM_REQ_EVENT, vcpu);
8940 kvm_x86_ops.request_immediate_exit(vcpu);
8943 trace_kvm_entry(vcpu);
8945 fpregs_assert_state_consistent();
8946 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8947 switch_fpu_return();
8949 if (unlikely(vcpu->arch.switch_db_regs)) {
8951 set_debugreg(vcpu->arch.eff_db[0], 0);
8952 set_debugreg(vcpu->arch.eff_db[1], 1);
8953 set_debugreg(vcpu->arch.eff_db[2], 2);
8954 set_debugreg(vcpu->arch.eff_db[3], 3);
8955 set_debugreg(vcpu->arch.dr6, 6);
8956 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8959 exit_fastpath = kvm_x86_ops.run(vcpu);
8962 * Do this here before restoring debug registers on the host. And
8963 * since we do this before handling the vmexit, a DR access vmexit
8964 * can (a) read the correct value of the debug registers, (b) set
8965 * KVM_DEBUGREG_WONT_EXIT again.
8967 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8968 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8969 kvm_x86_ops.sync_dirty_debug_regs(vcpu);
8970 kvm_update_dr0123(vcpu);
8971 kvm_update_dr7(vcpu);
8972 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8976 * If the guest has used debug registers, at least dr7
8977 * will be disabled while returning to the host.
8978 * If we don't have active breakpoints in the host, we don't
8979 * care about the messed up debug address registers. But if
8980 * we have some of them active, restore the old state.
8982 if (hw_breakpoint_active())
8983 hw_breakpoint_restore();
8985 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
8986 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8988 vcpu->mode = OUTSIDE_GUEST_MODE;
8991 kvm_x86_ops.handle_exit_irqoff(vcpu);
8994 * Consume any pending interrupts, including the possible source of
8995 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8996 * An instruction is required after local_irq_enable() to fully unblock
8997 * interrupts on processors that implement an interrupt shadow, the
8998 * stat.exits increment will do nicely.
9000 kvm_before_interrupt(vcpu);
9003 local_irq_disable();
9004 kvm_after_interrupt(vcpu);
9006 if (lapic_in_kernel(vcpu)) {
9007 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
9008 if (delta != S64_MIN) {
9009 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
9010 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
9017 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9020 * Profile KVM exit RIPs:
9022 if (unlikely(prof_on == KVM_PROFILING)) {
9023 unsigned long rip = kvm_rip_read(vcpu);
9024 profile_hit(KVM_PROFILING, (void *)rip);
9027 if (unlikely(vcpu->arch.tsc_always_catchup))
9028 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9030 if (vcpu->arch.apic_attention)
9031 kvm_lapic_sync_from_vapic(vcpu);
9033 r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath);
9037 if (req_immediate_exit)
9038 kvm_make_request(KVM_REQ_EVENT, vcpu);
9039 kvm_x86_ops.cancel_injection(vcpu);
9040 if (unlikely(vcpu->arch.apic_attention))
9041 kvm_lapic_sync_from_vapic(vcpu);
9046 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
9048 if (!kvm_arch_vcpu_runnable(vcpu) &&
9049 (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) {
9050 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9051 kvm_vcpu_block(vcpu);
9052 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9054 if (kvm_x86_ops.post_block)
9055 kvm_x86_ops.post_block(vcpu);
9057 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
9061 kvm_apic_accept_events(vcpu);
9062 switch(vcpu->arch.mp_state) {
9063 case KVM_MP_STATE_HALTED:
9064 vcpu->arch.pv.pv_unhalted = false;
9065 vcpu->arch.mp_state =
9066 KVM_MP_STATE_RUNNABLE;
9068 case KVM_MP_STATE_RUNNABLE:
9069 vcpu->arch.apf.halted = false;
9071 case KVM_MP_STATE_INIT_RECEIVED:
9079 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
9081 if (is_guest_mode(vcpu))
9082 kvm_x86_ops.nested_ops->check_events(vcpu);
9084 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
9085 !vcpu->arch.apf.halted);
9088 static int vcpu_run(struct kvm_vcpu *vcpu)
9091 struct kvm *kvm = vcpu->kvm;
9093 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9094 vcpu->arch.l1tf_flush_l1d = true;
9097 if (kvm_vcpu_running(vcpu)) {
9098 r = vcpu_enter_guest(vcpu);
9100 r = vcpu_block(kvm, vcpu);
9106 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
9107 if (kvm_cpu_has_pending_timer(vcpu))
9108 kvm_inject_pending_timer_irqs(vcpu);
9110 if (dm_request_for_irq_injection(vcpu) &&
9111 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
9113 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
9114 ++vcpu->stat.request_irq_exits;
9118 if (__xfer_to_guest_mode_work_pending()) {
9119 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9120 r = xfer_to_guest_mode_handle_work(vcpu);
9123 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9127 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9132 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
9136 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9137 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
9138 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
9142 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
9144 BUG_ON(!vcpu->arch.pio.count);
9146 return complete_emulated_io(vcpu);
9150 * Implements the following, as a state machine:
9154 * for each mmio piece in the fragment
9162 * for each mmio piece in the fragment
9167 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
9169 struct kvm_run *run = vcpu->run;
9170 struct kvm_mmio_fragment *frag;
9173 BUG_ON(!vcpu->mmio_needed);
9175 /* Complete previous fragment */
9176 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
9177 len = min(8u, frag->len);
9178 if (!vcpu->mmio_is_write)
9179 memcpy(frag->data, run->mmio.data, len);
9181 if (frag->len <= 8) {
9182 /* Switch to the next fragment. */
9184 vcpu->mmio_cur_fragment++;
9186 /* Go forward to the next mmio piece. */
9192 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
9193 vcpu->mmio_needed = 0;
9195 /* FIXME: return into emulator if single-stepping. */
9196 if (vcpu->mmio_is_write)
9198 vcpu->mmio_read_completed = 1;
9199 return complete_emulated_io(vcpu);
9202 run->exit_reason = KVM_EXIT_MMIO;
9203 run->mmio.phys_addr = frag->gpa;
9204 if (vcpu->mmio_is_write)
9205 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
9206 run->mmio.len = min(8u, frag->len);
9207 run->mmio.is_write = vcpu->mmio_is_write;
9208 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
9212 static void kvm_save_current_fpu(struct fpu *fpu)
9215 * If the target FPU state is not resident in the CPU registers, just
9216 * memcpy() from current, else save CPU state directly to the target.
9218 if (test_thread_flag(TIF_NEED_FPU_LOAD))
9219 memcpy(&fpu->state, ¤t->thread.fpu.state,
9220 fpu_kernel_xstate_size);
9222 copy_fpregs_to_fpstate(fpu);
9225 /* Swap (qemu) user FPU context for the guest FPU context. */
9226 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
9230 kvm_save_current_fpu(vcpu->arch.user_fpu);
9232 /* PKRU is separately restored in kvm_x86_ops.run. */
9233 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
9234 ~XFEATURE_MASK_PKRU);
9236 fpregs_mark_activate();
9242 /* When vcpu_run ends, restore user space FPU context. */
9243 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
9247 kvm_save_current_fpu(vcpu->arch.guest_fpu);
9249 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
9251 fpregs_mark_activate();
9254 ++vcpu->stat.fpu_reload;
9258 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
9260 struct kvm_run *kvm_run = vcpu->run;
9264 kvm_sigset_activate(vcpu);
9265 kvm_load_guest_fpu(vcpu);
9267 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
9268 if (kvm_run->immediate_exit) {
9272 kvm_vcpu_block(vcpu);
9273 kvm_apic_accept_events(vcpu);
9274 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
9276 if (signal_pending(current)) {
9278 kvm_run->exit_reason = KVM_EXIT_INTR;
9279 ++vcpu->stat.signal_exits;
9284 if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
9289 if (kvm_run->kvm_dirty_regs) {
9290 r = sync_regs(vcpu);
9295 /* re-sync apic's tpr */
9296 if (!lapic_in_kernel(vcpu)) {
9297 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
9303 if (unlikely(vcpu->arch.complete_userspace_io)) {
9304 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
9305 vcpu->arch.complete_userspace_io = NULL;
9310 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
9312 if (kvm_run->immediate_exit)
9318 kvm_put_guest_fpu(vcpu);
9319 if (kvm_run->kvm_valid_regs)
9321 post_kvm_run_save(vcpu);
9322 kvm_sigset_deactivate(vcpu);
9328 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9330 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
9332 * We are here if userspace calls get_regs() in the middle of
9333 * instruction emulation. Registers state needs to be copied
9334 * back from emulation context to vcpu. Userspace shouldn't do
9335 * that usually, but some bad designed PV devices (vmware
9336 * backdoor interface) need this to work
9338 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
9339 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9341 regs->rax = kvm_rax_read(vcpu);
9342 regs->rbx = kvm_rbx_read(vcpu);
9343 regs->rcx = kvm_rcx_read(vcpu);
9344 regs->rdx = kvm_rdx_read(vcpu);
9345 regs->rsi = kvm_rsi_read(vcpu);
9346 regs->rdi = kvm_rdi_read(vcpu);
9347 regs->rsp = kvm_rsp_read(vcpu);
9348 regs->rbp = kvm_rbp_read(vcpu);
9349 #ifdef CONFIG_X86_64
9350 regs->r8 = kvm_r8_read(vcpu);
9351 regs->r9 = kvm_r9_read(vcpu);
9352 regs->r10 = kvm_r10_read(vcpu);
9353 regs->r11 = kvm_r11_read(vcpu);
9354 regs->r12 = kvm_r12_read(vcpu);
9355 regs->r13 = kvm_r13_read(vcpu);
9356 regs->r14 = kvm_r14_read(vcpu);
9357 regs->r15 = kvm_r15_read(vcpu);
9360 regs->rip = kvm_rip_read(vcpu);
9361 regs->rflags = kvm_get_rflags(vcpu);
9364 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9367 __get_regs(vcpu, regs);
9372 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9374 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
9375 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9377 kvm_rax_write(vcpu, regs->rax);
9378 kvm_rbx_write(vcpu, regs->rbx);
9379 kvm_rcx_write(vcpu, regs->rcx);
9380 kvm_rdx_write(vcpu, regs->rdx);
9381 kvm_rsi_write(vcpu, regs->rsi);
9382 kvm_rdi_write(vcpu, regs->rdi);
9383 kvm_rsp_write(vcpu, regs->rsp);
9384 kvm_rbp_write(vcpu, regs->rbp);
9385 #ifdef CONFIG_X86_64
9386 kvm_r8_write(vcpu, regs->r8);
9387 kvm_r9_write(vcpu, regs->r9);
9388 kvm_r10_write(vcpu, regs->r10);
9389 kvm_r11_write(vcpu, regs->r11);
9390 kvm_r12_write(vcpu, regs->r12);
9391 kvm_r13_write(vcpu, regs->r13);
9392 kvm_r14_write(vcpu, regs->r14);
9393 kvm_r15_write(vcpu, regs->r15);
9396 kvm_rip_write(vcpu, regs->rip);
9397 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
9399 vcpu->arch.exception.pending = false;
9401 kvm_make_request(KVM_REQ_EVENT, vcpu);
9404 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9407 __set_regs(vcpu, regs);
9412 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
9414 struct kvm_segment cs;
9416 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9420 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
9422 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9426 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9427 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9428 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9429 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9430 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9431 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9433 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9434 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9436 kvm_x86_ops.get_idt(vcpu, &dt);
9437 sregs->idt.limit = dt.size;
9438 sregs->idt.base = dt.address;
9439 kvm_x86_ops.get_gdt(vcpu, &dt);
9440 sregs->gdt.limit = dt.size;
9441 sregs->gdt.base = dt.address;
9443 sregs->cr0 = kvm_read_cr0(vcpu);
9444 sregs->cr2 = vcpu->arch.cr2;
9445 sregs->cr3 = kvm_read_cr3(vcpu);
9446 sregs->cr4 = kvm_read_cr4(vcpu);
9447 sregs->cr8 = kvm_get_cr8(vcpu);
9448 sregs->efer = vcpu->arch.efer;
9449 sregs->apic_base = kvm_get_apic_base(vcpu);
9451 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
9453 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
9454 set_bit(vcpu->arch.interrupt.nr,
9455 (unsigned long *)sregs->interrupt_bitmap);
9458 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
9459 struct kvm_sregs *sregs)
9462 __get_sregs(vcpu, sregs);
9467 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
9468 struct kvm_mp_state *mp_state)
9471 if (kvm_mpx_supported())
9472 kvm_load_guest_fpu(vcpu);
9474 kvm_apic_accept_events(vcpu);
9475 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
9476 vcpu->arch.pv.pv_unhalted)
9477 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
9479 mp_state->mp_state = vcpu->arch.mp_state;
9481 if (kvm_mpx_supported())
9482 kvm_put_guest_fpu(vcpu);
9487 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
9488 struct kvm_mp_state *mp_state)
9494 if (!lapic_in_kernel(vcpu) &&
9495 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
9499 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
9500 * INIT state; latched init should be reported using
9501 * KVM_SET_VCPU_EVENTS, so reject it here.
9503 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
9504 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
9505 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
9508 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
9509 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
9510 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
9512 vcpu->arch.mp_state = mp_state->mp_state;
9513 kvm_make_request(KVM_REQ_EVENT, vcpu);
9521 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
9522 int reason, bool has_error_code, u32 error_code)
9524 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9527 init_emulate_ctxt(vcpu);
9529 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9530 has_error_code, error_code);
9532 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9533 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
9534 vcpu->run->internal.ndata = 0;
9538 kvm_rip_write(vcpu, ctxt->eip);
9539 kvm_set_rflags(vcpu, ctxt->eflags);
9542 EXPORT_SYMBOL_GPL(kvm_task_switch);
9544 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9546 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
9548 * When EFER.LME and CR0.PG are set, the processor is in
9549 * 64-bit mode (though maybe in a 32-bit code segment).
9550 * CR4.PAE and EFER.LMA must be set.
9552 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
9556 * Not in 64-bit mode: EFER.LMA is clear and the code
9557 * segment cannot be 64-bit.
9559 if (sregs->efer & EFER_LMA || sregs->cs.l)
9563 return kvm_is_valid_cr4(vcpu, sregs->cr4);
9566 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9568 struct msr_data apic_base_msr;
9569 int mmu_reset_needed = 0;
9570 int cpuid_update_needed = 0;
9571 int pending_vec, max_bits, idx;
9575 if (!kvm_is_valid_sregs(vcpu, sregs))
9578 apic_base_msr.data = sregs->apic_base;
9579 apic_base_msr.host_initiated = true;
9580 if (kvm_set_apic_base(vcpu, &apic_base_msr))
9583 dt.size = sregs->idt.limit;
9584 dt.address = sregs->idt.base;
9585 kvm_x86_ops.set_idt(vcpu, &dt);
9586 dt.size = sregs->gdt.limit;
9587 dt.address = sregs->gdt.base;
9588 kvm_x86_ops.set_gdt(vcpu, &dt);
9590 vcpu->arch.cr2 = sregs->cr2;
9591 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9592 vcpu->arch.cr3 = sregs->cr3;
9593 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9595 kvm_set_cr8(vcpu, sregs->cr8);
9597 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9598 kvm_x86_ops.set_efer(vcpu, sregs->efer);
9600 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9601 kvm_x86_ops.set_cr0(vcpu, sregs->cr0);
9602 vcpu->arch.cr0 = sregs->cr0;
9604 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9605 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
9606 (X86_CR4_OSXSAVE | X86_CR4_PKE));
9607 kvm_x86_ops.set_cr4(vcpu, sregs->cr4);
9608 if (cpuid_update_needed)
9609 kvm_update_cpuid_runtime(vcpu);
9611 idx = srcu_read_lock(&vcpu->kvm->srcu);
9612 if (is_pae_paging(vcpu)) {
9613 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9614 mmu_reset_needed = 1;
9616 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9618 if (mmu_reset_needed)
9619 kvm_mmu_reset_context(vcpu);
9621 max_bits = KVM_NR_INTERRUPTS;
9622 pending_vec = find_first_bit(
9623 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9624 if (pending_vec < max_bits) {
9625 kvm_queue_interrupt(vcpu, pending_vec, false);
9626 pr_debug("Set back pending irq %d\n", pending_vec);
9629 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9630 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9631 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9632 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9633 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9634 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9636 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9637 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9639 update_cr8_intercept(vcpu);
9641 /* Older userspace won't unhalt the vcpu on reset. */
9642 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9643 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9645 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9647 kvm_make_request(KVM_REQ_EVENT, vcpu);
9654 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9655 struct kvm_sregs *sregs)
9660 ret = __set_sregs(vcpu, sregs);
9665 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9666 struct kvm_guest_debug *dbg)
9668 unsigned long rflags;
9673 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9675 if (vcpu->arch.exception.pending)
9677 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9678 kvm_queue_exception(vcpu, DB_VECTOR);
9680 kvm_queue_exception(vcpu, BP_VECTOR);
9684 * Read rflags as long as potentially injected trace flags are still
9687 rflags = kvm_get_rflags(vcpu);
9689 vcpu->guest_debug = dbg->control;
9690 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9691 vcpu->guest_debug = 0;
9693 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9694 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9695 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9696 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9698 for (i = 0; i < KVM_NR_DB_REGS; i++)
9699 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9701 kvm_update_dr7(vcpu);
9703 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9704 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9705 get_segment_base(vcpu, VCPU_SREG_CS);
9708 * Trigger an rflags update that will inject or remove the trace
9711 kvm_set_rflags(vcpu, rflags);
9713 kvm_x86_ops.update_exception_bitmap(vcpu);
9723 * Translate a guest virtual address to a guest physical address.
9725 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9726 struct kvm_translation *tr)
9728 unsigned long vaddr = tr->linear_address;
9734 idx = srcu_read_lock(&vcpu->kvm->srcu);
9735 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9736 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9737 tr->physical_address = gpa;
9738 tr->valid = gpa != UNMAPPED_GVA;
9746 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9748 struct fxregs_state *fxsave;
9752 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9753 memcpy(fpu->fpr, fxsave->st_space, 128);
9754 fpu->fcw = fxsave->cwd;
9755 fpu->fsw = fxsave->swd;
9756 fpu->ftwx = fxsave->twd;
9757 fpu->last_opcode = fxsave->fop;
9758 fpu->last_ip = fxsave->rip;
9759 fpu->last_dp = fxsave->rdp;
9760 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9766 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9768 struct fxregs_state *fxsave;
9772 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9774 memcpy(fxsave->st_space, fpu->fpr, 128);
9775 fxsave->cwd = fpu->fcw;
9776 fxsave->swd = fpu->fsw;
9777 fxsave->twd = fpu->ftwx;
9778 fxsave->fop = fpu->last_opcode;
9779 fxsave->rip = fpu->last_ip;
9780 fxsave->rdp = fpu->last_dp;
9781 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9787 static void store_regs(struct kvm_vcpu *vcpu)
9789 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9791 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9792 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9794 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9795 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9797 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9798 kvm_vcpu_ioctl_x86_get_vcpu_events(
9799 vcpu, &vcpu->run->s.regs.events);
9802 static int sync_regs(struct kvm_vcpu *vcpu)
9804 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9807 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9808 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9809 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9811 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9812 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9814 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9816 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9817 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9818 vcpu, &vcpu->run->s.regs.events))
9820 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9826 static void fx_init(struct kvm_vcpu *vcpu)
9828 fpstate_init(&vcpu->arch.guest_fpu->state);
9829 if (boot_cpu_has(X86_FEATURE_XSAVES))
9830 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9831 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9834 * Ensure guest xcr0 is valid for loading
9836 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9838 vcpu->arch.cr0 |= X86_CR0_ET;
9841 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9843 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9844 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9845 "guest TSC will not be reliable\n");
9850 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9855 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9856 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9858 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9860 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9862 r = kvm_mmu_create(vcpu);
9866 if (irqchip_in_kernel(vcpu->kvm)) {
9867 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9869 goto fail_mmu_destroy;
9870 if (kvm_apicv_activated(vcpu->kvm))
9871 vcpu->arch.apicv_active = true;
9873 static_key_slow_inc(&kvm_no_apic_vcpu);
9877 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9879 goto fail_free_lapic;
9880 vcpu->arch.pio_data = page_address(page);
9882 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9883 GFP_KERNEL_ACCOUNT);
9884 if (!vcpu->arch.mce_banks)
9885 goto fail_free_pio_data;
9886 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9888 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9889 GFP_KERNEL_ACCOUNT))
9890 goto fail_free_mce_banks;
9892 if (!alloc_emulate_ctxt(vcpu))
9893 goto free_wbinvd_dirty_mask;
9895 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9896 GFP_KERNEL_ACCOUNT);
9897 if (!vcpu->arch.user_fpu) {
9898 pr_err("kvm: failed to allocate userspace's fpu\n");
9899 goto free_emulate_ctxt;
9902 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9903 GFP_KERNEL_ACCOUNT);
9904 if (!vcpu->arch.guest_fpu) {
9905 pr_err("kvm: failed to allocate vcpu's fpu\n");
9910 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9912 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9914 kvm_async_pf_hash_reset(vcpu);
9917 vcpu->arch.pending_external_vector = -1;
9918 vcpu->arch.preempted_in_kernel = false;
9920 kvm_hv_vcpu_init(vcpu);
9922 r = kvm_x86_ops.vcpu_create(vcpu);
9924 goto free_guest_fpu;
9926 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9927 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9928 kvm_vcpu_mtrr_init(vcpu);
9930 kvm_vcpu_reset(vcpu, false);
9931 kvm_init_mmu(vcpu, false);
9936 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9938 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9940 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9941 free_wbinvd_dirty_mask:
9942 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9943 fail_free_mce_banks:
9944 kfree(vcpu->arch.mce_banks);
9946 free_page((unsigned long)vcpu->arch.pio_data);
9948 kvm_free_lapic(vcpu);
9950 kvm_mmu_destroy(vcpu);
9954 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9956 struct kvm *kvm = vcpu->kvm;
9958 kvm_hv_vcpu_postcreate(vcpu);
9960 if (mutex_lock_killable(&vcpu->mutex))
9963 kvm_synchronize_tsc(vcpu, 0);
9966 /* poll control enabled by default */
9967 vcpu->arch.msr_kvm_poll_control = 1;
9969 mutex_unlock(&vcpu->mutex);
9971 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
9972 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9973 KVMCLOCK_SYNC_PERIOD);
9976 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9978 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9981 kvm_release_pfn(cache->pfn, cache->dirty, cache);
9983 kvmclock_reset(vcpu);
9985 kvm_x86_ops.vcpu_free(vcpu);
9987 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9988 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9989 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9990 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9992 kvm_hv_vcpu_uninit(vcpu);
9993 kvm_pmu_destroy(vcpu);
9994 kfree(vcpu->arch.mce_banks);
9995 kvm_free_lapic(vcpu);
9996 idx = srcu_read_lock(&vcpu->kvm->srcu);
9997 kvm_mmu_destroy(vcpu);
9998 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9999 free_page((unsigned long)vcpu->arch.pio_data);
10000 kvfree(vcpu->arch.cpuid_entries);
10001 if (!lapic_in_kernel(vcpu))
10002 static_key_slow_dec(&kvm_no_apic_vcpu);
10005 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
10007 kvm_lapic_reset(vcpu, init_event);
10009 vcpu->arch.hflags = 0;
10011 vcpu->arch.smi_pending = 0;
10012 vcpu->arch.smi_count = 0;
10013 atomic_set(&vcpu->arch.nmi_queued, 0);
10014 vcpu->arch.nmi_pending = 0;
10015 vcpu->arch.nmi_injected = false;
10016 kvm_clear_interrupt_queue(vcpu);
10017 kvm_clear_exception_queue(vcpu);
10019 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
10020 kvm_update_dr0123(vcpu);
10021 vcpu->arch.dr6 = DR6_INIT;
10022 vcpu->arch.dr7 = DR7_FIXED_1;
10023 kvm_update_dr7(vcpu);
10025 vcpu->arch.cr2 = 0;
10027 kvm_make_request(KVM_REQ_EVENT, vcpu);
10028 vcpu->arch.apf.msr_en_val = 0;
10029 vcpu->arch.apf.msr_int_val = 0;
10030 vcpu->arch.st.msr_val = 0;
10032 kvmclock_reset(vcpu);
10034 kvm_clear_async_pf_completion_queue(vcpu);
10035 kvm_async_pf_hash_reset(vcpu);
10036 vcpu->arch.apf.halted = false;
10038 if (kvm_mpx_supported()) {
10039 void *mpx_state_buffer;
10042 * To avoid have the INIT path from kvm_apic_has_events() that be
10043 * called with loaded FPU and does not let userspace fix the state.
10046 kvm_put_guest_fpu(vcpu);
10047 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
10049 if (mpx_state_buffer)
10050 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
10051 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
10053 if (mpx_state_buffer)
10054 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
10056 kvm_load_guest_fpu(vcpu);
10060 kvm_pmu_reset(vcpu);
10061 vcpu->arch.smbase = 0x30000;
10063 vcpu->arch.msr_misc_features_enables = 0;
10065 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
10068 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
10069 vcpu->arch.regs_avail = ~0;
10070 vcpu->arch.regs_dirty = ~0;
10072 vcpu->arch.ia32_xss = 0;
10074 kvm_x86_ops.vcpu_reset(vcpu, init_event);
10077 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
10079 struct kvm_segment cs;
10081 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
10082 cs.selector = vector << 8;
10083 cs.base = vector << 12;
10084 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
10085 kvm_rip_write(vcpu, 0);
10088 int kvm_arch_hardware_enable(void)
10091 struct kvm_vcpu *vcpu;
10096 bool stable, backwards_tsc = false;
10098 kvm_user_return_msr_cpu_online();
10099 ret = kvm_x86_ops.hardware_enable();
10103 local_tsc = rdtsc();
10104 stable = !kvm_check_tsc_unstable();
10105 list_for_each_entry(kvm, &vm_list, vm_list) {
10106 kvm_for_each_vcpu(i, vcpu, kvm) {
10107 if (!stable && vcpu->cpu == smp_processor_id())
10108 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10109 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
10110 backwards_tsc = true;
10111 if (vcpu->arch.last_host_tsc > max_tsc)
10112 max_tsc = vcpu->arch.last_host_tsc;
10118 * Sometimes, even reliable TSCs go backwards. This happens on
10119 * platforms that reset TSC during suspend or hibernate actions, but
10120 * maintain synchronization. We must compensate. Fortunately, we can
10121 * detect that condition here, which happens early in CPU bringup,
10122 * before any KVM threads can be running. Unfortunately, we can't
10123 * bring the TSCs fully up to date with real time, as we aren't yet far
10124 * enough into CPU bringup that we know how much real time has actually
10125 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
10126 * variables that haven't been updated yet.
10128 * So we simply find the maximum observed TSC above, then record the
10129 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
10130 * the adjustment will be applied. Note that we accumulate
10131 * adjustments, in case multiple suspend cycles happen before some VCPU
10132 * gets a chance to run again. In the event that no KVM threads get a
10133 * chance to run, we will miss the entire elapsed period, as we'll have
10134 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
10135 * loose cycle time. This isn't too big a deal, since the loss will be
10136 * uniform across all VCPUs (not to mention the scenario is extremely
10137 * unlikely). It is possible that a second hibernate recovery happens
10138 * much faster than a first, causing the observed TSC here to be
10139 * smaller; this would require additional padding adjustment, which is
10140 * why we set last_host_tsc to the local tsc observed here.
10142 * N.B. - this code below runs only on platforms with reliable TSC,
10143 * as that is the only way backwards_tsc is set above. Also note
10144 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
10145 * have the same delta_cyc adjustment applied if backwards_tsc
10146 * is detected. Note further, this adjustment is only done once,
10147 * as we reset last_host_tsc on all VCPUs to stop this from being
10148 * called multiple times (one for each physical CPU bringup).
10150 * Platforms with unreliable TSCs don't have to deal with this, they
10151 * will be compensated by the logic in vcpu_load, which sets the TSC to
10152 * catchup mode. This will catchup all VCPUs to real time, but cannot
10153 * guarantee that they stay in perfect synchronization.
10155 if (backwards_tsc) {
10156 u64 delta_cyc = max_tsc - local_tsc;
10157 list_for_each_entry(kvm, &vm_list, vm_list) {
10158 kvm->arch.backwards_tsc_observed = true;
10159 kvm_for_each_vcpu(i, vcpu, kvm) {
10160 vcpu->arch.tsc_offset_adjustment += delta_cyc;
10161 vcpu->arch.last_host_tsc = local_tsc;
10162 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
10166 * We have to disable TSC offset matching.. if you were
10167 * booting a VM while issuing an S4 host suspend....
10168 * you may have some problem. Solving this issue is
10169 * left as an exercise to the reader.
10171 kvm->arch.last_tsc_nsec = 0;
10172 kvm->arch.last_tsc_write = 0;
10179 void kvm_arch_hardware_disable(void)
10181 kvm_x86_ops.hardware_disable();
10182 drop_user_return_notifiers();
10185 int kvm_arch_hardware_setup(void *opaque)
10187 struct kvm_x86_init_ops *ops = opaque;
10190 rdmsrl_safe(MSR_EFER, &host_efer);
10192 if (boot_cpu_has(X86_FEATURE_XSAVES))
10193 rdmsrl(MSR_IA32_XSS, host_xss);
10195 r = ops->hardware_setup();
10199 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
10201 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
10204 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
10205 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
10206 #undef __kvm_cpu_cap_has
10208 if (kvm_has_tsc_control) {
10210 * Make sure the user can only configure tsc_khz values that
10211 * fit into a signed integer.
10212 * A min value is not calculated because it will always
10213 * be 1 on all machines.
10215 u64 max = min(0x7fffffffULL,
10216 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
10217 kvm_max_guest_tsc_khz = max;
10219 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
10222 kvm_init_msr_list();
10226 void kvm_arch_hardware_unsetup(void)
10228 kvm_x86_ops.hardware_unsetup();
10231 int kvm_arch_check_processor_compat(void *opaque)
10233 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
10234 struct kvm_x86_init_ops *ops = opaque;
10236 WARN_ON(!irqs_disabled());
10238 if (__cr4_reserved_bits(cpu_has, c) !=
10239 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
10242 return ops->check_processor_compatibility();
10245 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
10247 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
10249 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
10251 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
10253 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
10256 struct static_key kvm_no_apic_vcpu __read_mostly;
10257 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
10259 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
10261 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
10263 vcpu->arch.l1tf_flush_l1d = true;
10264 if (pmu->version && unlikely(pmu->event_count)) {
10265 pmu->need_cleanup = true;
10266 kvm_make_request(KVM_REQ_PMU, vcpu);
10268 kvm_x86_ops.sched_in(vcpu, cpu);
10271 void kvm_arch_free_vm(struct kvm *kvm)
10273 kfree(kvm->arch.hyperv.hv_pa_pg);
10278 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
10283 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
10284 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
10285 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
10286 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
10287 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
10288 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
10290 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
10291 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
10292 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
10293 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
10294 &kvm->arch.irq_sources_bitmap);
10296 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
10297 mutex_init(&kvm->arch.apic_map_lock);
10298 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
10300 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
10301 pvclock_update_vm_gtod_copy(kvm);
10303 kvm->arch.guest_can_read_msr_platform_info = true;
10305 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
10306 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
10308 kvm_hv_init_vm(kvm);
10309 kvm_page_track_init(kvm);
10310 kvm_mmu_init_vm(kvm);
10312 return kvm_x86_ops.vm_init(kvm);
10315 int kvm_arch_post_init_vm(struct kvm *kvm)
10317 return kvm_mmu_post_init_vm(kvm);
10320 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
10323 kvm_mmu_unload(vcpu);
10327 static void kvm_free_vcpus(struct kvm *kvm)
10330 struct kvm_vcpu *vcpu;
10333 * Unpin any mmu pages first.
10335 kvm_for_each_vcpu(i, vcpu, kvm) {
10336 kvm_clear_async_pf_completion_queue(vcpu);
10337 kvm_unload_vcpu_mmu(vcpu);
10339 kvm_for_each_vcpu(i, vcpu, kvm)
10340 kvm_vcpu_destroy(vcpu);
10342 mutex_lock(&kvm->lock);
10343 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
10344 kvm->vcpus[i] = NULL;
10346 atomic_set(&kvm->online_vcpus, 0);
10347 mutex_unlock(&kvm->lock);
10350 void kvm_arch_sync_events(struct kvm *kvm)
10352 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
10353 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
10357 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
10360 * __x86_set_memory_region: Setup KVM internal memory slot
10362 * @kvm: the kvm pointer to the VM.
10363 * @id: the slot ID to setup.
10364 * @gpa: the GPA to install the slot (unused when @size == 0).
10365 * @size: the size of the slot. Set to zero to uninstall a slot.
10367 * This function helps to setup a KVM internal memory slot. Specify
10368 * @size > 0 to install a new slot, while @size == 0 to uninstall a
10369 * slot. The return code can be one of the following:
10371 * HVA: on success (uninstall will return a bogus HVA)
10374 * The caller should always use IS_ERR() to check the return value
10375 * before use. Note, the KVM internal memory slots are guaranteed to
10376 * remain valid and unchanged until the VM is destroyed, i.e., the
10377 * GPA->HVA translation will not change. However, the HVA is a user
10378 * address, i.e. its accessibility is not guaranteed, and must be
10379 * accessed via __copy_{to,from}_user().
10381 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
10385 unsigned long hva, old_npages;
10386 struct kvm_memslots *slots = kvm_memslots(kvm);
10387 struct kvm_memory_slot *slot;
10389 /* Called with kvm->slots_lock held. */
10390 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
10391 return ERR_PTR_USR(-EINVAL);
10393 slot = id_to_memslot(slots, id);
10395 if (slot && slot->npages)
10396 return ERR_PTR_USR(-EEXIST);
10399 * MAP_SHARED to prevent internal slot pages from being moved
10402 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
10403 MAP_SHARED | MAP_ANONYMOUS, 0);
10404 if (IS_ERR((void *)hva))
10405 return (void __user *)hva;
10407 if (!slot || !slot->npages)
10410 old_npages = slot->npages;
10414 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
10415 struct kvm_userspace_memory_region m;
10417 m.slot = id | (i << 16);
10419 m.guest_phys_addr = gpa;
10420 m.userspace_addr = hva;
10421 m.memory_size = size;
10422 r = __kvm_set_memory_region(kvm, &m);
10424 return ERR_PTR_USR(r);
10428 vm_munmap(hva, old_npages * PAGE_SIZE);
10430 return (void __user *)hva;
10432 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
10434 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
10436 kvm_mmu_pre_destroy_vm(kvm);
10439 void kvm_arch_destroy_vm(struct kvm *kvm)
10443 if (current->mm == kvm->mm) {
10445 * Free memory regions allocated on behalf of userspace,
10446 * unless the the memory map has changed due to process exit
10449 mutex_lock(&kvm->slots_lock);
10450 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
10452 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
10454 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
10455 mutex_unlock(&kvm->slots_lock);
10457 if (kvm_x86_ops.vm_destroy)
10458 kvm_x86_ops.vm_destroy(kvm);
10459 for (i = 0; i < kvm->arch.msr_filter.count; i++)
10460 kfree(kvm->arch.msr_filter.ranges[i].bitmap);
10461 kvm_pic_destroy(kvm);
10462 kvm_ioapic_destroy(kvm);
10463 kvm_free_vcpus(kvm);
10464 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
10465 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
10466 kvm_mmu_uninit_vm(kvm);
10467 kvm_page_track_cleanup(kvm);
10468 kvm_hv_destroy_vm(kvm);
10471 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
10475 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10476 kvfree(slot->arch.rmap[i]);
10477 slot->arch.rmap[i] = NULL;
10482 kvfree(slot->arch.lpage_info[i - 1]);
10483 slot->arch.lpage_info[i - 1] = NULL;
10486 kvm_page_track_free_memslot(slot);
10489 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
10490 unsigned long npages)
10495 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
10496 * old arrays will be freed by __kvm_set_memory_region() if installing
10497 * the new memslot is successful.
10499 memset(&slot->arch, 0, sizeof(slot->arch));
10501 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10502 struct kvm_lpage_info *linfo;
10503 unsigned long ugfn;
10507 lpages = gfn_to_index(slot->base_gfn + npages - 1,
10508 slot->base_gfn, level) + 1;
10510 slot->arch.rmap[i] =
10511 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
10512 GFP_KERNEL_ACCOUNT);
10513 if (!slot->arch.rmap[i])
10518 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
10522 slot->arch.lpage_info[i - 1] = linfo;
10524 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
10525 linfo[0].disallow_lpage = 1;
10526 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
10527 linfo[lpages - 1].disallow_lpage = 1;
10528 ugfn = slot->userspace_addr >> PAGE_SHIFT;
10530 * If the gfn and userspace address are not aligned wrt each
10531 * other, disable large page support for this slot.
10533 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
10536 for (j = 0; j < lpages; ++j)
10537 linfo[j].disallow_lpage = 1;
10541 if (kvm_page_track_create_memslot(slot, npages))
10547 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10548 kvfree(slot->arch.rmap[i]);
10549 slot->arch.rmap[i] = NULL;
10553 kvfree(slot->arch.lpage_info[i - 1]);
10554 slot->arch.lpage_info[i - 1] = NULL;
10559 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
10561 struct kvm_vcpu *vcpu;
10565 * memslots->generation has been incremented.
10566 * mmio generation may have reached its maximum value.
10568 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
10570 /* Force re-initialization of steal_time cache */
10571 kvm_for_each_vcpu(i, vcpu, kvm)
10572 kvm_vcpu_kick(vcpu);
10575 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10576 struct kvm_memory_slot *memslot,
10577 const struct kvm_userspace_memory_region *mem,
10578 enum kvm_mr_change change)
10580 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10581 return kvm_alloc_memslot_metadata(memslot,
10582 mem->memory_size >> PAGE_SHIFT);
10586 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10587 struct kvm_memory_slot *old,
10588 struct kvm_memory_slot *new,
10589 enum kvm_mr_change change)
10592 * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot.
10593 * See comments below.
10595 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY))
10599 * Dirty logging tracks sptes in 4k granularity, meaning that large
10600 * sptes have to be split. If live migration is successful, the guest
10601 * in the source machine will be destroyed and large sptes will be
10602 * created in the destination. However, if the guest continues to run
10603 * in the source machine (for example if live migration fails), small
10604 * sptes will remain around and cause bad performance.
10606 * Scan sptes if dirty logging has been stopped, dropping those
10607 * which can be collapsed into a single large-page spte. Later
10608 * page faults will create the large-page sptes.
10610 * There is no need to do this in any of the following cases:
10611 * CREATE: No dirty mappings will already exist.
10612 * MOVE/DELETE: The old mappings will already have been cleaned up by
10613 * kvm_arch_flush_shadow_memslot()
10615 if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10616 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10617 kvm_mmu_zap_collapsible_sptes(kvm, new);
10620 * Enable or disable dirty logging for the slot.
10622 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old
10623 * slot have been zapped so no dirty logging updates are needed for
10625 * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible
10626 * any mappings that might be created in it will consume the
10627 * properties of the new slot and do not need to be updated here.
10629 * When PML is enabled, the kvm_x86_ops dirty logging hooks are
10630 * called to enable/disable dirty logging.
10632 * When disabling dirty logging with PML enabled, the D-bit is set
10633 * for sptes in the slot in order to prevent unnecessary GPA
10634 * logging in the PML buffer (and potential PML buffer full VMEXIT).
10635 * This guarantees leaving PML enabled for the guest's lifetime
10636 * won't have any additional overhead from PML when the guest is
10637 * running with dirty logging disabled.
10639 * When enabling dirty logging, large sptes are write-protected
10640 * so they can be split on first write. New large sptes cannot
10641 * be created for this slot until the end of the logging.
10642 * See the comments in fast_page_fault().
10643 * For small sptes, nothing is done if the dirty log is in the
10644 * initial-all-set state. Otherwise, depending on whether pml
10645 * is enabled the D-bit or the W-bit will be cleared.
10647 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10648 if (kvm_x86_ops.slot_enable_log_dirty) {
10649 kvm_x86_ops.slot_enable_log_dirty(kvm, new);
10652 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10653 PG_LEVEL_2M : PG_LEVEL_4K;
10656 * If we're with initial-all-set, we don't need
10657 * to write protect any small page because
10658 * they're reported as dirty already. However
10659 * we still need to write-protect huge pages
10660 * so that the page split can happen lazily on
10661 * the first write to the huge page.
10663 kvm_mmu_slot_remove_write_access(kvm, new, level);
10666 if (kvm_x86_ops.slot_disable_log_dirty)
10667 kvm_x86_ops.slot_disable_log_dirty(kvm, new);
10671 void kvm_arch_commit_memory_region(struct kvm *kvm,
10672 const struct kvm_userspace_memory_region *mem,
10673 struct kvm_memory_slot *old,
10674 const struct kvm_memory_slot *new,
10675 enum kvm_mr_change change)
10677 if (!kvm->arch.n_requested_mmu_pages)
10678 kvm_mmu_change_mmu_pages(kvm,
10679 kvm_mmu_calculate_default_mmu_pages(kvm));
10682 * FIXME: const-ify all uses of struct kvm_memory_slot.
10684 kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change);
10686 /* Free the arrays associated with the old memslot. */
10687 if (change == KVM_MR_MOVE)
10688 kvm_arch_free_memslot(kvm, old);
10691 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10693 kvm_mmu_zap_all(kvm);
10696 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10697 struct kvm_memory_slot *slot)
10699 kvm_page_track_flush_slot(kvm, slot);
10702 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10704 return (is_guest_mode(vcpu) &&
10705 kvm_x86_ops.guest_apic_has_interrupt &&
10706 kvm_x86_ops.guest_apic_has_interrupt(vcpu));
10709 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10711 if (!list_empty_careful(&vcpu->async_pf.done))
10714 if (kvm_apic_has_events(vcpu))
10717 if (vcpu->arch.pv.pv_unhalted)
10720 if (vcpu->arch.exception.pending)
10723 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10724 (vcpu->arch.nmi_pending &&
10725 kvm_x86_ops.nmi_allowed(vcpu, false)))
10728 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10729 (vcpu->arch.smi_pending &&
10730 kvm_x86_ops.smi_allowed(vcpu, false)))
10733 if (kvm_arch_interrupt_allowed(vcpu) &&
10734 (kvm_cpu_has_interrupt(vcpu) ||
10735 kvm_guest_apic_has_interrupt(vcpu)))
10738 if (kvm_hv_has_stimer_pending(vcpu))
10741 if (is_guest_mode(vcpu) &&
10742 kvm_x86_ops.nested_ops->hv_timer_pending &&
10743 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
10749 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10751 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10754 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10756 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10759 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10760 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10761 kvm_test_request(KVM_REQ_EVENT, vcpu))
10764 if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu))
10770 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10772 return vcpu->arch.preempted_in_kernel;
10775 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10777 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10780 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10782 return kvm_x86_ops.interrupt_allowed(vcpu, false);
10785 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10787 if (is_64_bit_mode(vcpu))
10788 return kvm_rip_read(vcpu);
10789 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10790 kvm_rip_read(vcpu));
10792 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10794 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10796 return kvm_get_linear_rip(vcpu) == linear_rip;
10798 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10800 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10802 unsigned long rflags;
10804 rflags = kvm_x86_ops.get_rflags(vcpu);
10805 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10806 rflags &= ~X86_EFLAGS_TF;
10809 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10811 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10813 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10814 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10815 rflags |= X86_EFLAGS_TF;
10816 kvm_x86_ops.set_rflags(vcpu, rflags);
10819 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10821 __kvm_set_rflags(vcpu, rflags);
10822 kvm_make_request(KVM_REQ_EVENT, vcpu);
10824 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10826 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10830 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10834 r = kvm_mmu_reload(vcpu);
10838 if (!vcpu->arch.mmu->direct_map &&
10839 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10842 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10845 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10847 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
10849 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10852 static inline u32 kvm_async_pf_next_probe(u32 key)
10854 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
10857 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10859 u32 key = kvm_async_pf_hash_fn(gfn);
10861 while (vcpu->arch.apf.gfns[key] != ~0)
10862 key = kvm_async_pf_next_probe(key);
10864 vcpu->arch.apf.gfns[key] = gfn;
10867 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10870 u32 key = kvm_async_pf_hash_fn(gfn);
10872 for (i = 0; i < ASYNC_PF_PER_VCPU &&
10873 (vcpu->arch.apf.gfns[key] != gfn &&
10874 vcpu->arch.apf.gfns[key] != ~0); i++)
10875 key = kvm_async_pf_next_probe(key);
10880 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10882 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10885 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10889 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10891 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
10895 vcpu->arch.apf.gfns[i] = ~0;
10897 j = kvm_async_pf_next_probe(j);
10898 if (vcpu->arch.apf.gfns[j] == ~0)
10900 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10902 * k lies cyclically in ]i,j]
10904 * |....j i.k.| or |.k..j i...|
10906 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10907 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10912 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
10914 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
10916 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
10920 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
10922 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
10924 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
10925 &token, offset, sizeof(token));
10928 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
10930 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
10933 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
10934 &val, offset, sizeof(val)))
10940 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10942 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10945 if (!kvm_pv_async_pf_enabled(vcpu) ||
10946 (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0))
10952 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10954 if (unlikely(!lapic_in_kernel(vcpu) ||
10955 kvm_event_needs_reinjection(vcpu) ||
10956 vcpu->arch.exception.pending))
10959 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10963 * If interrupts are off we cannot even use an artificial
10966 return kvm_arch_interrupt_allowed(vcpu);
10969 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10970 struct kvm_async_pf *work)
10972 struct x86_exception fault;
10974 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10975 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10977 if (kvm_can_deliver_async_pf(vcpu) &&
10978 !apf_put_user_notpresent(vcpu)) {
10979 fault.vector = PF_VECTOR;
10980 fault.error_code_valid = true;
10981 fault.error_code = 0;
10982 fault.nested_page_fault = false;
10983 fault.address = work->arch.token;
10984 fault.async_page_fault = true;
10985 kvm_inject_page_fault(vcpu, &fault);
10989 * It is not possible to deliver a paravirtualized asynchronous
10990 * page fault, but putting the guest in an artificial halt state
10991 * can be beneficial nevertheless: if an interrupt arrives, we
10992 * can deliver it timely and perhaps the guest will schedule
10993 * another process. When the instruction that triggered a page
10994 * fault is retried, hopefully the page will be ready in the host.
10996 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
11001 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
11002 struct kvm_async_pf *work)
11004 struct kvm_lapic_irq irq = {
11005 .delivery_mode = APIC_DM_FIXED,
11006 .vector = vcpu->arch.apf.vec
11009 if (work->wakeup_all)
11010 work->arch.token = ~0; /* broadcast wakeup */
11012 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
11013 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
11015 if ((work->wakeup_all || work->notpresent_injected) &&
11016 kvm_pv_async_pf_enabled(vcpu) &&
11017 !apf_put_user_ready(vcpu, work->arch.token)) {
11018 vcpu->arch.apf.pageready_pending = true;
11019 kvm_apic_set_irq(vcpu, &irq, NULL);
11022 vcpu->arch.apf.halted = false;
11023 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11026 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
11028 kvm_make_request(KVM_REQ_APF_READY, vcpu);
11029 if (!vcpu->arch.apf.pageready_pending)
11030 kvm_vcpu_kick(vcpu);
11033 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
11035 if (!kvm_pv_async_pf_enabled(vcpu))
11038 return apf_pageready_slot_free(vcpu);
11041 void kvm_arch_start_assignment(struct kvm *kvm)
11043 atomic_inc(&kvm->arch.assigned_device_count);
11045 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
11047 void kvm_arch_end_assignment(struct kvm *kvm)
11049 atomic_dec(&kvm->arch.assigned_device_count);
11051 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
11053 bool kvm_arch_has_assigned_device(struct kvm *kvm)
11055 return atomic_read(&kvm->arch.assigned_device_count);
11057 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
11059 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
11061 atomic_inc(&kvm->arch.noncoherent_dma_count);
11063 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
11065 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
11067 atomic_dec(&kvm->arch.noncoherent_dma_count);
11069 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
11071 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
11073 return atomic_read(&kvm->arch.noncoherent_dma_count);
11075 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
11077 bool kvm_arch_has_irq_bypass(void)
11082 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
11083 struct irq_bypass_producer *prod)
11085 struct kvm_kernel_irqfd *irqfd =
11086 container_of(cons, struct kvm_kernel_irqfd, consumer);
11089 irqfd->producer = prod;
11090 kvm_arch_start_assignment(irqfd->kvm);
11091 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm,
11092 prod->irq, irqfd->gsi, 1);
11095 kvm_arch_end_assignment(irqfd->kvm);
11100 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
11101 struct irq_bypass_producer *prod)
11104 struct kvm_kernel_irqfd *irqfd =
11105 container_of(cons, struct kvm_kernel_irqfd, consumer);
11107 WARN_ON(irqfd->producer != prod);
11108 irqfd->producer = NULL;
11111 * When producer of consumer is unregistered, we change back to
11112 * remapped mode, so we can re-use the current implementation
11113 * when the irq is masked/disabled or the consumer side (KVM
11114 * int this case doesn't want to receive the interrupts.
11116 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
11118 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
11119 " fails: %d\n", irqfd->consumer.token, ret);
11121 kvm_arch_end_assignment(irqfd->kvm);
11124 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
11125 uint32_t guest_irq, bool set)
11127 return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set);
11130 bool kvm_vector_hashing_enabled(void)
11132 return vector_hashing;
11135 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
11137 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
11139 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
11142 int kvm_spec_ctrl_test_value(u64 value)
11145 * test that setting IA32_SPEC_CTRL to given value
11146 * is allowed by the host processor
11150 unsigned long flags;
11153 local_irq_save(flags);
11155 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
11157 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
11160 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
11162 local_irq_restore(flags);
11166 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
11168 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
11170 struct x86_exception fault;
11171 u32 access = error_code &
11172 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
11174 if (!(error_code & PFERR_PRESENT_MASK) ||
11175 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) {
11177 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
11178 * tables probably do not match the TLB. Just proceed
11179 * with the error code that the processor gave.
11181 fault.vector = PF_VECTOR;
11182 fault.error_code_valid = true;
11183 fault.error_code = error_code;
11184 fault.nested_page_fault = false;
11185 fault.address = gva;
11187 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
11189 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
11192 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
11193 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
11194 * indicates whether exit to userspace is needed.
11196 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
11197 struct x86_exception *e)
11199 if (r == X86EMUL_PROPAGATE_FAULT) {
11200 kvm_inject_emulated_page_fault(vcpu, e);
11205 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
11206 * while handling a VMX instruction KVM could've handled the request
11207 * correctly by exiting to userspace and performing I/O but there
11208 * doesn't seem to be a real use-case behind such requests, just return
11209 * KVM_EXIT_INTERNAL_ERROR for now.
11211 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11212 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11213 vcpu->run->internal.ndata = 0;
11217 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
11219 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
11222 struct x86_exception e;
11224 unsigned long roots_to_free = 0;
11231 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
11232 if (r != X86EMUL_CONTINUE)
11233 return kvm_handle_memory_failure(vcpu, r, &e);
11235 if (operand.pcid >> 12 != 0) {
11236 kvm_inject_gp(vcpu, 0);
11240 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
11243 case INVPCID_TYPE_INDIV_ADDR:
11244 if ((!pcid_enabled && (operand.pcid != 0)) ||
11245 is_noncanonical_address(operand.gla, vcpu)) {
11246 kvm_inject_gp(vcpu, 0);
11249 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
11250 return kvm_skip_emulated_instruction(vcpu);
11252 case INVPCID_TYPE_SINGLE_CTXT:
11253 if (!pcid_enabled && (operand.pcid != 0)) {
11254 kvm_inject_gp(vcpu, 0);
11258 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
11259 kvm_mmu_sync_roots(vcpu);
11260 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
11263 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
11264 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd)
11266 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
11268 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
11270 * If neither the current cr3 nor any of the prev_roots use the
11271 * given PCID, then nothing needs to be done here because a
11272 * resync will happen anyway before switching to any other CR3.
11275 return kvm_skip_emulated_instruction(vcpu);
11277 case INVPCID_TYPE_ALL_NON_GLOBAL:
11279 * Currently, KVM doesn't mark global entries in the shadow
11280 * page tables, so a non-global flush just degenerates to a
11281 * global flush. If needed, we could optimize this later by
11282 * keeping track of global entries in shadow page tables.
11286 case INVPCID_TYPE_ALL_INCL_GLOBAL:
11287 kvm_mmu_unload(vcpu);
11288 return kvm_skip_emulated_instruction(vcpu);
11291 BUG(); /* We have already checked above that type <= 3 */
11294 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
11296 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
11297 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
11298 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
11299 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
11300 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
11301 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
11302 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
11303 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
11304 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
11305 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
11306 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
11307 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
11308 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
11309 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
11310 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
11311 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
11312 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
11313 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
11314 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
11315 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
11316 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
11317 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);