arch/x86/kvm/x86.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * derived from drivers/kvm/kvm_main.c
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright (C) 2008 Qumranet, Inc.
   9  * Copyright IBM Corporation, 2008
  10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  11  *
  12  * Authors:
  13  *   Avi Kivity   <avi@qumranet.com>
  14  *   Yaniv Kamay  <yaniv@qumranet.com>
  15  *   Amit Shah    <amit.shah@qumranet.com>
  16  *   Ben-Ami Yassour <benami@il.ibm.com>
  17  */
  18
  19 #include <linux/kvm_host.h>
  20 #include "irq.h"
  21 #include "ioapic.h"
  22 #include "mmu.h"
  23 #include "i8254.h"
  24 #include "tss.h"
  25 #include "kvm_cache_regs.h"
  26 #include "kvm_emulate.h"
  27 #include "x86.h"
  28 #include "cpuid.h"
  29 #include "pmu.h"
  30 #include "hyperv.h"
  31 #include "lapic.h"
  32
  33 #include <linux/clocksource.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/kvm.h>
  36 #include <linux/fs.h>
  37 #include <linux/vmalloc.h>
  38 #include <linux/export.h>
  39 #include <linux/moduleparam.h>
  40 #include <linux/mman.h>
  41 #include <linux/highmem.h>
  42 #include <linux/iommu.h>
  43 #include <linux/intel-iommu.h>
  44 #include <linux/cpufreq.h>
  45 #include <linux/user-return-notifier.h>
  46 #include <linux/srcu.h>
  47 #include <linux/slab.h>
  48 #include <linux/perf_event.h>
  49 #include <linux/uaccess.h>
  50 #include <linux/hash.h>
  51 #include <linux/pci.h>
  52 #include <linux/timekeeper_internal.h>
  53 #include <linux/pvclock_gtod.h>
  54 #include <linux/kvm_irqfd.h>
  55 #include <linux/irqbypass.h>
  56 #include <linux/sched/stat.h>
  57 #include <linux/sched/isolation.h>
  58 #include <linux/mem_encrypt.h>
  59
  60 #include <trace/events/kvm.h>
  61
  62 #include <asm/debugreg.h>
  63 #include <asm/msr.h>
  64 #include <asm/desc.h>
  65 #include <asm/mce.h>
  66 #include <linux/kernel_stat.h>
  67 #include <asm/fpu/internal.h> /* Ugh! */
  68 #include <asm/pvclock.h>
  69 #include <asm/div64.h>
  70 #include <asm/irq_remapping.h>
  71 #include <asm/mshyperv.h>
  72 #include <asm/hypervisor.h>
  73 #include <asm/intel_pt.h>
  74 #include <asm/emulate_prefix.h>
  75 #include <clocksource/hyperv_timer.h>
  76
  77 #define CREATE_TRACE_POINTS
  78 #include "trace.h"
  79
  80 #define MAX_IO_MSRS 256
  81 #define KVM_MAX_MCE_BANKS 32
  82 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
  83 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
  84
  85 #define emul_to_vcpu(ctxt) \
  86         ((struct kvm_vcpu *)(ctxt)->vcpu)
  87
  88 /* EFER defaults:
  89  * - enable syscall per default because its emulated by KVM
  90  * - enable LME and LMA per default on 64 bit KVM
  91  */
  92 #ifdef CONFIG_X86_64
  93 static
  94 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
  95 #else
  96 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
  97 #endif
  98
  99 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
 100
 101 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
 102                                     KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
 103
 104 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
 105 static void process_nmi(struct kvm_vcpu *vcpu);
 106 static void enter_smm(struct kvm_vcpu *vcpu);
 107 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
 108 static void store_regs(struct kvm_vcpu *vcpu);
 109 static int sync_regs(struct kvm_vcpu *vcpu);
 110
 111 struct kvm_x86_ops kvm_x86_ops __read_mostly;
 112 EXPORT_SYMBOL_GPL(kvm_x86_ops);
 113
 114 static bool __read_mostly ignore_msrs = 0;
 115 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
 116
 117 static bool __read_mostly report_ignored_msrs = true;
 118 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
 119
 120 unsigned int min_timer_period_us = 200;
 121 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
 122
 123 static bool __read_mostly kvmclock_periodic_sync = true;
 124 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
 125
 126 bool __read_mostly kvm_has_tsc_control;
 127 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
 128 u32  __read_mostly kvm_max_guest_tsc_khz;
 129 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
 130 u8   __read_mostly kvm_tsc_scaling_ratio_frac_bits;
 131 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
 132 u64  __read_mostly kvm_max_tsc_scaling_ratio;
 133 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
 134 u64 __read_mostly kvm_default_tsc_scaling_ratio;
 135 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
 136
 137 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
 138 static u32 __read_mostly tsc_tolerance_ppm = 250;
 139 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
 140
 141 /*
 142  * lapic timer advance (tscdeadline mode only) in nanoseconds.  '-1' enables
 143  * adaptive tuning starting from default advancment of 1000ns.  '0' disables
 144  * advancement entirely.  Any other value is used as-is and disables adaptive
 145  * tuning, i.e. allows priveleged userspace to set an exact advancement time.
 146  */
 147 static int __read_mostly lapic_timer_advance_ns = -1;
 148 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
 149
 150 static bool __read_mostly vector_hashing = true;
 151 module_param(vector_hashing, bool, S_IRUGO);
 152
 153 bool __read_mostly enable_vmware_backdoor = false;
 154 module_param(enable_vmware_backdoor, bool, S_IRUGO);
 155 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
 156
 157 static bool __read_mostly force_emulation_prefix = false;
 158 module_param(force_emulation_prefix, bool, S_IRUGO);
 159
 160 int __read_mostly pi_inject_timer = -1;
 161 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
 162
 163 #define KVM_NR_SHARED_MSRS 16
 164
 165 struct kvm_shared_msrs_global {
 166         int nr;
 167         u32 msrs[KVM_NR_SHARED_MSRS];
 168 };
 169
 170 struct kvm_shared_msrs {
 171         struct user_return_notifier urn;
 172         bool registered;
 173         struct kvm_shared_msr_values {
 174                 u64 host;
 175                 u64 curr;
 176         } values[KVM_NR_SHARED_MSRS];
 177 };
 178
 179 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
 180 static struct kvm_shared_msrs __percpu *shared_msrs;
 181
 182 #define KVM_SUPPORTED_XCR0     (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
 183                                 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
 184                                 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
 185                                 | XFEATURE_MASK_PKRU)
 186
 187 u64 __read_mostly host_efer;
 188 EXPORT_SYMBOL_GPL(host_efer);
 189
 190 static u64 __read_mostly host_xss;
 191 u64 __read_mostly supported_xss;
 192 EXPORT_SYMBOL_GPL(supported_xss);
 193
 194 struct kvm_stats_debugfs_item debugfs_entries[] = {
 195         VCPU_STAT("pf_fixed", pf_fixed),
 196         VCPU_STAT("pf_guest", pf_guest),
 197         VCPU_STAT("tlb_flush", tlb_flush),
 198         VCPU_STAT("invlpg", invlpg),
 199         VCPU_STAT("exits", exits),
 200         VCPU_STAT("io_exits", io_exits),
 201         VCPU_STAT("mmio_exits", mmio_exits),
 202         VCPU_STAT("signal_exits", signal_exits),
 203         VCPU_STAT("irq_window", irq_window_exits),
 204         VCPU_STAT("nmi_window", nmi_window_exits),
 205         VCPU_STAT("halt_exits", halt_exits),
 206         VCPU_STAT("halt_successful_poll", halt_successful_poll),
 207         VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
 208         VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
 209         VCPU_STAT("halt_wakeup", halt_wakeup),
 210         VCPU_STAT("hypercalls", hypercalls),
 211         VCPU_STAT("request_irq", request_irq_exits),
 212         VCPU_STAT("irq_exits", irq_exits),
 213         VCPU_STAT("host_state_reload", host_state_reload),
 214         VCPU_STAT("fpu_reload", fpu_reload),
 215         VCPU_STAT("insn_emulation", insn_emulation),
 216         VCPU_STAT("insn_emulation_fail", insn_emulation_fail),
 217         VCPU_STAT("irq_injections", irq_injections),
 218         VCPU_STAT("nmi_injections", nmi_injections),
 219         VCPU_STAT("req_event", req_event),
 220         VCPU_STAT("l1d_flush", l1d_flush),
 221         VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
 222         VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
 223         VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped),
 224         VM_STAT("mmu_pte_write", mmu_pte_write),
 225         VM_STAT("mmu_pte_updated", mmu_pte_updated),
 226         VM_STAT("mmu_pde_zapped", mmu_pde_zapped),
 227         VM_STAT("mmu_flooded", mmu_flooded),
 228         VM_STAT("mmu_recycled", mmu_recycled),
 229         VM_STAT("mmu_cache_miss", mmu_cache_miss),
 230         VM_STAT("mmu_unsync", mmu_unsync),
 231         VM_STAT("remote_tlb_flush", remote_tlb_flush),
 232         VM_STAT("largepages", lpages, .mode = 0444),
 233         VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444),
 234         VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions),
 235         { NULL }
 236 };
 237
 238 u64 __read_mostly host_xcr0;
 239 u64 __read_mostly supported_xcr0;
 240 EXPORT_SYMBOL_GPL(supported_xcr0);
 241
 242 static struct kmem_cache *x86_fpu_cache;
 243
 244 static struct kmem_cache *x86_emulator_cache;
 245
 246 static struct kmem_cache *kvm_alloc_emulator_cache(void)
 247 {
 248         unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
 249         unsigned int size = sizeof(struct x86_emulate_ctxt);
 250
 251         return kmem_cache_create_usercopy("x86_emulator", size,
 252                                           __alignof__(struct x86_emulate_ctxt),
 253                                           SLAB_ACCOUNT, useroffset,
 254                                           size - useroffset, NULL);
 255 }
 256
 257 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
 258
 259 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
 260 {
 261         int i;
 262         for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
 263                 vcpu->arch.apf.gfns[i] = ~0;
 264 }
 265
 266 static void kvm_on_user_return(struct user_return_notifier *urn)
 267 {
 268         unsigned slot;
 269         struct kvm_shared_msrs *locals
 270                 = container_of(urn, struct kvm_shared_msrs, urn);
 271         struct kvm_shared_msr_values *values;
 272         unsigned long flags;
 273
 274         /*
 275          * Disabling irqs at this point since the following code could be
 276          * interrupted and executed through kvm_arch_hardware_disable()
 277          */
 278         local_irq_save(flags);
 279         if (locals->registered) {
 280                 locals->registered = false;
 281                 user_return_notifier_unregister(urn);
 282         }
 283         local_irq_restore(flags);
 284         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
 285                 values = &locals->values[slot];
 286                 if (values->host != values->curr) {
 287                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
 288                         values->curr = values->host;
 289                 }
 290         }
 291 }
 292
 293 void kvm_define_shared_msr(unsigned slot, u32 msr)
 294 {
 295         BUG_ON(slot >= KVM_NR_SHARED_MSRS);
 296         shared_msrs_global.msrs[slot] = msr;
 297         if (slot >= shared_msrs_global.nr)
 298                 shared_msrs_global.nr = slot + 1;
 299 }
 300 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
 301
 302 static void kvm_shared_msr_cpu_online(void)
 303 {
 304         unsigned int cpu = smp_processor_id();
 305         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 306         u64 value;
 307         int i;
 308
 309         for (i = 0; i < shared_msrs_global.nr; ++i) {
 310                 rdmsrl_safe(shared_msrs_global.msrs[i], &value);
 311                 smsr->values[i].host = value;
 312                 smsr->values[i].curr = value;
 313         }
 314 }
 315
 316 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
 317 {
 318         unsigned int cpu = smp_processor_id();
 319         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 320         int err;
 321
 322         value = (value & mask) | (smsr->values[slot].host & ~mask);
 323         if (value == smsr->values[slot].curr)
 324                 return 0;
 325         err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
 326         if (err)
 327                 return 1;
 328
 329         smsr->values[slot].curr = value;
 330         if (!smsr->registered) {
 331                 smsr->urn.on_user_return = kvm_on_user_return;
 332                 user_return_notifier_register(&smsr->urn);
 333                 smsr->registered = true;
 334         }
 335         return 0;
 336 }
 337 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
 338
 339 static void drop_user_return_notifiers(void)
 340 {
 341         unsigned int cpu = smp_processor_id();
 342         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 343
 344         if (smsr->registered)
 345                 kvm_on_user_return(&smsr->urn);
 346 }
 347
 348 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
 349 {
 350         return vcpu->arch.apic_base;
 351 }
 352 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
 353
 354 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
 355 {
 356         return kvm_apic_mode(kvm_get_apic_base(vcpu));
 357 }
 358 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
 359
 360 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 361 {
 362         enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
 363         enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
 364         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
 365                 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
 366
 367         if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
 368                 return 1;
 369         if (!msr_info->host_initiated) {
 370                 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
 371                         return 1;
 372                 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
 373                         return 1;
 374         }
 375
 376         kvm_lapic_set_base(vcpu, msr_info->data);
 377         kvm_recalculate_apic_map(vcpu->kvm);
 378         return 0;
 379 }
 380 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
 381
 382 asmlinkage __visible void kvm_spurious_fault(void)
 383 {
 384         /* Fault while not rebooting.  We want the trace. */
 385         BUG_ON(!kvm_rebooting);
 386 }
 387 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
 388
 389 #define EXCPT_BENIGN            0
 390 #define EXCPT_CONTRIBUTORY      1
 391 #define EXCPT_PF                2
 392
 393 static int exception_class(int vector)
 394 {
 395         switch (vector) {
 396         case PF_VECTOR:
 397                 return EXCPT_PF;
 398         case DE_VECTOR:
 399         case TS_VECTOR:
 400         case NP_VECTOR:
 401         case SS_VECTOR:
 402         case GP_VECTOR:
 403                 return EXCPT_CONTRIBUTORY;
 404         default:
 405                 break;
 406         }
 407         return EXCPT_BENIGN;
 408 }
 409
 410 #define EXCPT_FAULT             0
 411 #define EXCPT_TRAP              1
 412 #define EXCPT_ABORT             2
 413 #define EXCPT_INTERRUPT         3
 414
 415 static int exception_type(int vector)
 416 {
 417         unsigned int mask;
 418
 419         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
 420                 return EXCPT_INTERRUPT;
 421
 422         mask = 1 << vector;
 423
 424         /* #DB is trap, as instruction watchpoints are handled elsewhere */
 425         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
 426                 return EXCPT_TRAP;
 427
 428         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
 429                 return EXCPT_ABORT;
 430
 431         /* Reserved exceptions will result in fault */
 432         return EXCPT_FAULT;
 433 }
 434
 435 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
 436 {
 437         unsigned nr = vcpu->arch.exception.nr;
 438         bool has_payload = vcpu->arch.exception.has_payload;
 439         unsigned long payload = vcpu->arch.exception.payload;
 440
 441         if (!has_payload)
 442                 return;
 443
 444         switch (nr) {
 445         case DB_VECTOR:
 446                 /*
 447                  * "Certain debug exceptions may clear bit 0-3.  The
 448                  * remaining contents of the DR6 register are never
 449                  * cleared by the processor".
 450                  */
 451                 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
 452                 /*
 453                  * DR6.RTM is set by all #DB exceptions that don't clear it.
 454                  */
 455                 vcpu->arch.dr6 |= DR6_RTM;
 456                 vcpu->arch.dr6 |= payload;
 457                 /*
 458                  * Bit 16 should be set in the payload whenever the #DB
 459                  * exception should clear DR6.RTM. This makes the payload
 460                  * compatible with the pending debug exceptions under VMX.
 461                  * Though not currently documented in the SDM, this also
 462                  * makes the payload compatible with the exit qualification
 463                  * for #DB exceptions under VMX.
 464                  */
 465                 vcpu->arch.dr6 ^= payload & DR6_RTM;
 466
 467                 /*
 468                  * The #DB payload is defined as compatible with the 'pending
 469                  * debug exceptions' field under VMX, not DR6. While bit 12 is
 470                  * defined in the 'pending debug exceptions' field (enabled
 471                  * breakpoint), it is reserved and must be zero in DR6.
 472                  */
 473                 vcpu->arch.dr6 &= ~BIT(12);
 474                 break;
 475         case PF_VECTOR:
 476                 vcpu->arch.cr2 = payload;
 477                 break;
 478         }
 479
 480         vcpu->arch.exception.has_payload = false;
 481         vcpu->arch.exception.payload = 0;
 482 }
 483 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
 484
 485 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
 486                 unsigned nr, bool has_error, u32 error_code,
 487                 bool has_payload, unsigned long payload, bool reinject)
 488 {
 489         u32 prev_nr;
 490         int class1, class2;
 491
 492         kvm_make_request(KVM_REQ_EVENT, vcpu);
 493
 494         if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
 495         queue:
 496                 if (has_error && !is_protmode(vcpu))
 497                         has_error = false;
 498                 if (reinject) {
 499                         /*
 500                          * On vmentry, vcpu->arch.exception.pending is only
 501                          * true if an event injection was blocked by
 502                          * nested_run_pending.  In that case, however,
 503                          * vcpu_enter_guest requests an immediate exit,
 504                          * and the guest shouldn't proceed far enough to
 505                          * need reinjection.
 506                          */
 507                         WARN_ON_ONCE(vcpu->arch.exception.pending);
 508                         vcpu->arch.exception.injected = true;
 509                         if (WARN_ON_ONCE(has_payload)) {
 510                                 /*
 511                                  * A reinjected event has already
 512                                  * delivered its payload.
 513                                  */
 514                                 has_payload = false;
 515                                 payload = 0;
 516                         }
 517                 } else {
 518                         vcpu->arch.exception.pending = true;
 519                         vcpu->arch.exception.injected = false;
 520                 }
 521                 vcpu->arch.exception.has_error_code = has_error;
 522                 vcpu->arch.exception.nr = nr;
 523                 vcpu->arch.exception.error_code = error_code;
 524                 vcpu->arch.exception.has_payload = has_payload;
 525                 vcpu->arch.exception.payload = payload;
 526                 if (!is_guest_mode(vcpu))
 527                         kvm_deliver_exception_payload(vcpu);
 528                 return;
 529         }
 530
 531         /* to check exception */
 532         prev_nr = vcpu->arch.exception.nr;
 533         if (prev_nr == DF_VECTOR) {
 534                 /* triple fault -> shutdown */
 535                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
 536                 return;
 537         }
 538         class1 = exception_class(prev_nr);
 539         class2 = exception_class(nr);
 540         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
 541                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
 542                 /*
 543                  * Generate double fault per SDM Table 5-5.  Set
 544                  * exception.pending = true so that the double fault
 545                  * can trigger a nested vmexit.
 546                  */
 547                 vcpu->arch.exception.pending = true;
 548                 vcpu->arch.exception.injected = false;
 549                 vcpu->arch.exception.has_error_code = true;
 550                 vcpu->arch.exception.nr = DF_VECTOR;
 551                 vcpu->arch.exception.error_code = 0;
 552                 vcpu->arch.exception.has_payload = false;
 553                 vcpu->arch.exception.payload = 0;
 554         } else
 555                 /* replace previous exception with a new one in a hope
 556                    that instruction re-execution will regenerate lost
 557                    exception */
 558                 goto queue;
 559 }
 560
 561 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 562 {
 563         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
 564 }
 565 EXPORT_SYMBOL_GPL(kvm_queue_exception);
 566
 567 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 568 {
 569         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
 570 }
 571 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
 572
 573 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
 574                            unsigned long payload)
 575 {
 576         kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
 577 }
 578 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
 579
 580 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
 581                                     u32 error_code, unsigned long payload)
 582 {
 583         kvm_multiple_exception(vcpu, nr, true, error_code,
 584                                true, payload, false);
 585 }
 586
 587 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
 588 {
 589         if (err)
 590                 kvm_inject_gp(vcpu, 0);
 591         else
 592                 return kvm_skip_emulated_instruction(vcpu);
 593
 594         return 1;
 595 }
 596 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
 597
 598 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 599 {
 600         ++vcpu->stat.pf_guest;
 601         vcpu->arch.exception.nested_apf =
 602                 is_guest_mode(vcpu) && fault->async_page_fault;
 603         if (vcpu->arch.exception.nested_apf) {
 604                 vcpu->arch.apf.nested_apf_token = fault->address;
 605                 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
 606         } else {
 607                 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
 608                                         fault->address);
 609         }
 610 }
 611 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
 612
 613 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
 614                                     struct x86_exception *fault)
 615 {
 616         struct kvm_mmu *fault_mmu;
 617         WARN_ON_ONCE(fault->vector != PF_VECTOR);
 618
 619         fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
 620                                                vcpu->arch.walk_mmu;
 621
 622         /*
 623          * Invalidate the TLB entry for the faulting address, if it exists,
 624          * else the access will fault indefinitely (and to emulate hardware).
 625          */
 626         if ((fault->error_code & PFERR_PRESENT_MASK) &&
 627             !(fault->error_code & PFERR_RSVD_MASK))
 628                 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
 629                                        fault_mmu->root_hpa);
 630
 631         fault_mmu->inject_page_fault(vcpu, fault);
 632         return fault->nested_page_fault;
 633 }
 634 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
 635
 636 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
 637 {
 638         atomic_inc(&vcpu->arch.nmi_queued);
 639         kvm_make_request(KVM_REQ_NMI, vcpu);
 640 }
 641 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
 642
 643 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 644 {
 645         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
 646 }
 647 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
 648
 649 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 650 {
 651         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
 652 }
 653 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
 654
 655 /*
 656  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
 657  * a #GP and return false.
 658  */
 659 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
 660 {
 661         if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl)
 662                 return true;
 663         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
 664         return false;
 665 }
 666 EXPORT_SYMBOL_GPL(kvm_require_cpl);
 667
 668 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
 669 {
 670         if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 671                 return true;
 672
 673         kvm_queue_exception(vcpu, UD_VECTOR);
 674         return false;
 675 }
 676 EXPORT_SYMBOL_GPL(kvm_require_dr);
 677
 678 /*
 679  * This function will be used to read from the physical memory of the currently
 680  * running guest. The difference to kvm_vcpu_read_guest_page is that this function
 681  * can read from guest physical or from the guest's guest physical memory.
 682  */
 683 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 684                             gfn_t ngfn, void *data, int offset, int len,
 685                             u32 access)
 686 {
 687         struct x86_exception exception;
 688         gfn_t real_gfn;
 689         gpa_t ngpa;
 690
 691         ngpa     = gfn_to_gpa(ngfn);
 692         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
 693         if (real_gfn == UNMAPPED_GVA)
 694                 return -EFAULT;
 695
 696         real_gfn = gpa_to_gfn(real_gfn);
 697
 698         return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
 699 }
 700 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
 701
 702 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
 703                                void *data, int offset, int len, u32 access)
 704 {
 705         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
 706                                        data, offset, len, access);
 707 }
 708
 709 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
 710 {
 711         return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
 712                rsvd_bits(1, 2);
 713 }
 714
 715 /*
 716  * Load the pae pdptrs.  Return 1 if they are all valid, 0 otherwise.
 717  */
 718 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
 719 {
 720         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
 721         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
 722         int i;
 723         int ret;
 724         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
 725
 726         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
 727                                       offset * sizeof(u64), sizeof(pdpte),
 728                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
 729         if (ret < 0) {
 730                 ret = 0;
 731                 goto out;
 732         }
 733         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
 734                 if ((pdpte[i] & PT_PRESENT_MASK) &&
 735                     (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
 736                         ret = 0;
 737                         goto out;
 738                 }
 739         }
 740         ret = 1;
 741
 742         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
 743         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
 744
 745 out:
 746
 747         return ret;
 748 }
 749 EXPORT_SYMBOL_GPL(load_pdptrs);
 750
 751 bool pdptrs_changed(struct kvm_vcpu *vcpu)
 752 {
 753         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
 754         int offset;
 755         gfn_t gfn;
 756         int r;
 757
 758         if (!is_pae_paging(vcpu))
 759                 return false;
 760
 761         if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
 762                 return true;
 763
 764         gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
 765         offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
 766         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
 767                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
 768         if (r < 0)
 769                 return true;
 770
 771         return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
 772 }
 773 EXPORT_SYMBOL_GPL(pdptrs_changed);
 774
 775 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 776 {
 777         unsigned long old_cr0 = kvm_read_cr0(vcpu);
 778         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
 779
 780         cr0 |= X86_CR0_ET;
 781
 782 #ifdef CONFIG_X86_64
 783         if (cr0 & 0xffffffff00000000UL)
 784                 return 1;
 785 #endif
 786
 787         cr0 &= ~CR0_RESERVED_BITS;
 788
 789         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
 790                 return 1;
 791
 792         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
 793                 return 1;
 794
 795         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 796 #ifdef CONFIG_X86_64
 797                 if ((vcpu->arch.efer & EFER_LME)) {
 798                         int cs_db, cs_l;
 799
 800                         if (!is_pae(vcpu))
 801                                 return 1;
 802                         kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
 803                         if (cs_l)
 804                                 return 1;
 805                 } else
 806 #endif
 807                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 808                                                  kvm_read_cr3(vcpu)))
 809                         return 1;
 810         }
 811
 812         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
 813                 return 1;
 814
 815         kvm_x86_ops.set_cr0(vcpu, cr0);
 816
 817         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
 818                 kvm_clear_async_pf_completion_queue(vcpu);
 819                 kvm_async_pf_hash_reset(vcpu);
 820         }
 821
 822         if ((cr0 ^ old_cr0) & update_bits)
 823                 kvm_mmu_reset_context(vcpu);
 824
 825         if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
 826             kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
 827             !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
 828                 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
 829
 830         return 0;
 831 }
 832 EXPORT_SYMBOL_GPL(kvm_set_cr0);
 833
 834 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 835 {
 836         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
 837 }
 838 EXPORT_SYMBOL_GPL(kvm_lmsw);
 839
 840 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
 841 {
 842         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
 843
 844                 if (vcpu->arch.xcr0 != host_xcr0)
 845                         xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
 846
 847                 if (vcpu->arch.xsaves_enabled &&
 848                     vcpu->arch.ia32_xss != host_xss)
 849                         wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
 850         }
 851
 852         if (static_cpu_has(X86_FEATURE_PKU) &&
 853             (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
 854              (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
 855             vcpu->arch.pkru != vcpu->arch.host_pkru)
 856                 __write_pkru(vcpu->arch.pkru);
 857 }
 858 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
 859
 860 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
 861 {
 862         if (static_cpu_has(X86_FEATURE_PKU) &&
 863             (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
 864              (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
 865                 vcpu->arch.pkru = rdpkru();
 866                 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
 867                         __write_pkru(vcpu->arch.host_pkru);
 868         }
 869
 870         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
 871
 872                 if (vcpu->arch.xcr0 != host_xcr0)
 873                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
 874
 875                 if (vcpu->arch.xsaves_enabled &&
 876                     vcpu->arch.ia32_xss != host_xss)
 877                         wrmsrl(MSR_IA32_XSS, host_xss);
 878         }
 879
 880 }
 881 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
 882
 883 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 884 {
 885         u64 xcr0 = xcr;
 886         u64 old_xcr0 = vcpu->arch.xcr0;
 887         u64 valid_bits;
 888
 889         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
 890         if (index != XCR_XFEATURE_ENABLED_MASK)
 891                 return 1;
 892         if (!(xcr0 & XFEATURE_MASK_FP))
 893                 return 1;
 894         if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
 895                 return 1;
 896
 897         /*
 898          * Do not allow the guest to set bits that we do not support
 899          * saving.  However, xcr0 bit 0 is always set, even if the
 900          * emulated CPU does not support XSAVE (see fx_init).
 901          */
 902         valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
 903         if (xcr0 & ~valid_bits)
 904                 return 1;
 905
 906         if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
 907             (!(xcr0 & XFEATURE_MASK_BNDCSR)))
 908                 return 1;
 909
 910         if (xcr0 & XFEATURE_MASK_AVX512) {
 911                 if (!(xcr0 & XFEATURE_MASK_YMM))
 912                         return 1;
 913                 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
 914                         return 1;
 915         }
 916         vcpu->arch.xcr0 = xcr0;
 917
 918         if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
 919                 kvm_update_cpuid(vcpu);
 920         return 0;
 921 }
 922
 923 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 924 {
 925         if (kvm_x86_ops.get_cpl(vcpu) != 0 ||
 926             __kvm_set_xcr(vcpu, index, xcr)) {
 927                 kvm_inject_gp(vcpu, 0);
 928                 return 1;
 929         }
 930         return 0;
 931 }
 932 EXPORT_SYMBOL_GPL(kvm_set_xcr);
 933
 934 #define __cr4_reserved_bits(__cpu_has, __c)             \
 935 ({                                                      \
 936         u64 __reserved_bits = CR4_RESERVED_BITS;        \
 937                                                         \
 938         if (!__cpu_has(__c, X86_FEATURE_XSAVE))         \
 939                 __reserved_bits |= X86_CR4_OSXSAVE;     \
 940         if (!__cpu_has(__c, X86_FEATURE_SMEP))          \
 941                 __reserved_bits |= X86_CR4_SMEP;        \
 942         if (!__cpu_has(__c, X86_FEATURE_SMAP))          \
 943                 __reserved_bits |= X86_CR4_SMAP;        \
 944         if (!__cpu_has(__c, X86_FEATURE_FSGSBASE))      \
 945                 __reserved_bits |= X86_CR4_FSGSBASE;    \
 946         if (!__cpu_has(__c, X86_FEATURE_PKU))           \
 947                 __reserved_bits |= X86_CR4_PKE;         \
 948         if (!__cpu_has(__c, X86_FEATURE_LA57))          \
 949                 __reserved_bits |= X86_CR4_LA57;        \
 950         if (!__cpu_has(__c, X86_FEATURE_UMIP))          \
 951                 __reserved_bits |= X86_CR4_UMIP;        \
 952         __reserved_bits;                                \
 953 })
 954
 955 static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 956 {
 957         if (cr4 & cr4_reserved_bits)
 958                 return -EINVAL;
 959
 960         if (cr4 & __cr4_reserved_bits(guest_cpuid_has, vcpu))
 961                 return -EINVAL;
 962
 963         return 0;
 964 }
 965
 966 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 967 {
 968         unsigned long old_cr4 = kvm_read_cr4(vcpu);
 969         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
 970                                    X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
 971
 972         if (kvm_valid_cr4(vcpu, cr4))
 973                 return 1;
 974
 975         if (is_long_mode(vcpu)) {
 976                 if (!(cr4 & X86_CR4_PAE))
 977                         return 1;
 978                 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
 979                         return 1;
 980         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
 981                    && ((cr4 ^ old_cr4) & pdptr_bits)
 982                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 983                                    kvm_read_cr3(vcpu)))
 984                 return 1;
 985
 986         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
 987                 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
 988                         return 1;
 989
 990                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
 991                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
 992                         return 1;
 993         }
 994
 995         if (kvm_x86_ops.set_cr4(vcpu, cr4))
 996                 return 1;
 997
 998         if (((cr4 ^ old_cr4) & pdptr_bits) ||
 999             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1000                 kvm_mmu_reset_context(vcpu);
1001
1002         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1003                 kvm_update_cpuid(vcpu);
1004
1005         return 0;
1006 }
1007 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1008
1009 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1010 {
1011         bool skip_tlb_flush = false;
1012 #ifdef CONFIG_X86_64
1013         bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1014
1015         if (pcid_enabled) {
1016                 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1017                 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1018         }
1019 #endif
1020
1021         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1022                 if (!skip_tlb_flush) {
1023                         kvm_mmu_sync_roots(vcpu);
1024                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1025                 }
1026                 return 0;
1027         }
1028
1029         if (is_long_mode(vcpu) &&
1030             (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
1031                 return 1;
1032         else if (is_pae_paging(vcpu) &&
1033                  !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1034                 return 1;
1035
1036         kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush);
1037         vcpu->arch.cr3 = cr3;
1038         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1039
1040         return 0;
1041 }
1042 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1043
1044 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1045 {
1046         if (cr8 & CR8_RESERVED_BITS)
1047                 return 1;
1048         if (lapic_in_kernel(vcpu))
1049                 kvm_lapic_set_tpr(vcpu, cr8);
1050         else
1051                 vcpu->arch.cr8 = cr8;
1052         return 0;
1053 }
1054 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1055
1056 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1057 {
1058         if (lapic_in_kernel(vcpu))
1059                 return kvm_lapic_get_cr8(vcpu);
1060         else
1061                 return vcpu->arch.cr8;
1062 }
1063 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1064
1065 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1066 {
1067         int i;
1068
1069         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1070                 for (i = 0; i < KVM_NR_DB_REGS; i++)
1071                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1072                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1073         }
1074 }
1075
1076 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1077 {
1078         unsigned long dr7;
1079
1080         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1081                 dr7 = vcpu->arch.guest_debug_dr7;
1082         else
1083                 dr7 = vcpu->arch.dr7;
1084         kvm_x86_ops.set_dr7(vcpu, dr7);
1085         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1086         if (dr7 & DR7_BP_EN_MASK)
1087                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1088 }
1089 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1090
1091 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1092 {
1093         u64 fixed = DR6_FIXED_1;
1094
1095         if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1096                 fixed |= DR6_RTM;
1097         return fixed;
1098 }
1099
1100 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1101 {
1102         size_t size = ARRAY_SIZE(vcpu->arch.db);
1103
1104         switch (dr) {
1105         case 0 ... 3:
1106                 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1107                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1108                         vcpu->arch.eff_db[dr] = val;
1109                 break;
1110         case 4:
1111                 /* fall through */
1112         case 6:
1113                 if (val & 0xffffffff00000000ULL)
1114                         return -1; /* #GP */
1115                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1116                 break;
1117         case 5:
1118                 /* fall through */
1119         default: /* 7 */
1120                 if (!kvm_dr7_valid(val))
1121                         return -1; /* #GP */
1122                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1123                 kvm_update_dr7(vcpu);
1124                 break;
1125         }
1126
1127         return 0;
1128 }
1129
1130 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1131 {
1132         if (__kvm_set_dr(vcpu, dr, val)) {
1133                 kvm_inject_gp(vcpu, 0);
1134                 return 1;
1135         }
1136         return 0;
1137 }
1138 EXPORT_SYMBOL_GPL(kvm_set_dr);
1139
1140 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1141 {
1142         size_t size = ARRAY_SIZE(vcpu->arch.db);
1143
1144         switch (dr) {
1145         case 0 ... 3:
1146                 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1147                 break;
1148         case 4:
1149                 /* fall through */
1150         case 6:
1151                 *val = vcpu->arch.dr6;
1152                 break;
1153         case 5:
1154                 /* fall through */
1155         default: /* 7 */
1156                 *val = vcpu->arch.dr7;
1157                 break;
1158         }
1159         return 0;
1160 }
1161 EXPORT_SYMBOL_GPL(kvm_get_dr);
1162
1163 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1164 {
1165         u32 ecx = kvm_rcx_read(vcpu);
1166         u64 data;
1167         int err;
1168
1169         err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1170         if (err)
1171                 return err;
1172         kvm_rax_write(vcpu, (u32)data);
1173         kvm_rdx_write(vcpu, data >> 32);
1174         return err;
1175 }
1176 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1177
1178 /*
1179  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1180  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1181  *
1182  * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1183  * extract the supported MSRs from the related const lists.
1184  * msrs_to_save is selected from the msrs_to_save_all to reflect the
1185  * capabilities of the host cpu. This capabilities test skips MSRs that are
1186  * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1187  * may depend on host virtualization features rather than host cpu features.
1188  */
1189
1190 static const u32 msrs_to_save_all[] = {
1191         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1192         MSR_STAR,
1193 #ifdef CONFIG_X86_64
1194         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1195 #endif
1196         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1197         MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1198         MSR_IA32_SPEC_CTRL,
1199         MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1200         MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1201         MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1202         MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1203         MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1204         MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1205         MSR_IA32_UMWAIT_CONTROL,
1206
1207         MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1208         MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1209         MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1210         MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1211         MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1212         MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1213         MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1214         MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1215         MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1216         MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1217         MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1218         MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1219         MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1220         MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1221         MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1222         MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1223         MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1224         MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1225         MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1226         MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1227         MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1228         MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1229 };
1230
1231 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1232 static unsigned num_msrs_to_save;
1233
1234 static const u32 emulated_msrs_all[] = {
1235         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1236         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1237         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1238         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1239         HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1240         HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1241         HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1242         HV_X64_MSR_RESET,
1243         HV_X64_MSR_VP_INDEX,
1244         HV_X64_MSR_VP_RUNTIME,
1245         HV_X64_MSR_SCONTROL,
1246         HV_X64_MSR_STIMER0_CONFIG,
1247         HV_X64_MSR_VP_ASSIST_PAGE,
1248         HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1249         HV_X64_MSR_TSC_EMULATION_STATUS,
1250         HV_X64_MSR_SYNDBG_OPTIONS,
1251         HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1252         HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1253         HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1254
1255         MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1256         MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1257
1258         MSR_IA32_TSC_ADJUST,
1259         MSR_IA32_TSCDEADLINE,
1260         MSR_IA32_ARCH_CAPABILITIES,
1261         MSR_IA32_PERF_CAPABILITIES,
1262         MSR_IA32_MISC_ENABLE,
1263         MSR_IA32_MCG_STATUS,
1264         MSR_IA32_MCG_CTL,
1265         MSR_IA32_MCG_EXT_CTL,
1266         MSR_IA32_SMBASE,
1267         MSR_SMI_COUNT,
1268         MSR_PLATFORM_INFO,
1269         MSR_MISC_FEATURES_ENABLES,
1270         MSR_AMD64_VIRT_SPEC_CTRL,
1271         MSR_IA32_POWER_CTL,
1272         MSR_IA32_UCODE_REV,
1273
1274         /*
1275          * The following list leaves out MSRs whose values are determined
1276          * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1277          * We always support the "true" VMX control MSRs, even if the host
1278          * processor does not, so I am putting these registers here rather
1279          * than in msrs_to_save_all.
1280          */
1281         MSR_IA32_VMX_BASIC,
1282         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1283         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1284         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1285         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1286         MSR_IA32_VMX_MISC,
1287         MSR_IA32_VMX_CR0_FIXED0,
1288         MSR_IA32_VMX_CR4_FIXED0,
1289         MSR_IA32_VMX_VMCS_ENUM,
1290         MSR_IA32_VMX_PROCBASED_CTLS2,
1291         MSR_IA32_VMX_EPT_VPID_CAP,
1292         MSR_IA32_VMX_VMFUNC,
1293
1294         MSR_K7_HWCR,
1295         MSR_KVM_POLL_CONTROL,
1296 };
1297
1298 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1299 static unsigned num_emulated_msrs;
1300
1301 /*
1302  * List of msr numbers which are used to expose MSR-based features that
1303  * can be used by a hypervisor to validate requested CPU features.
1304  */
1305 static const u32 msr_based_features_all[] = {
1306         MSR_IA32_VMX_BASIC,
1307         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1308         MSR_IA32_VMX_PINBASED_CTLS,
1309         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1310         MSR_IA32_VMX_PROCBASED_CTLS,
1311         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1312         MSR_IA32_VMX_EXIT_CTLS,
1313         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1314         MSR_IA32_VMX_ENTRY_CTLS,
1315         MSR_IA32_VMX_MISC,
1316         MSR_IA32_VMX_CR0_FIXED0,
1317         MSR_IA32_VMX_CR0_FIXED1,
1318         MSR_IA32_VMX_CR4_FIXED0,
1319         MSR_IA32_VMX_CR4_FIXED1,
1320         MSR_IA32_VMX_VMCS_ENUM,
1321         MSR_IA32_VMX_PROCBASED_CTLS2,
1322         MSR_IA32_VMX_EPT_VPID_CAP,
1323         MSR_IA32_VMX_VMFUNC,
1324
1325         MSR_F10H_DECFG,
1326         MSR_IA32_UCODE_REV,
1327         MSR_IA32_ARCH_CAPABILITIES,
1328         MSR_IA32_PERF_CAPABILITIES,
1329 };
1330
1331 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1332 static unsigned int num_msr_based_features;
1333
1334 static u64 kvm_get_arch_capabilities(void)
1335 {
1336         u64 data = 0;
1337
1338         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1339                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1340
1341         /*
1342          * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1343          * the nested hypervisor runs with NX huge pages.  If it is not,
1344          * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1345          * L1 guests, so it need not worry about its own (L2) guests.
1346          */
1347         data |= ARCH_CAP_PSCHANGE_MC_NO;
1348
1349         /*
1350          * If we're doing cache flushes (either "always" or "cond")
1351          * we will do one whenever the guest does a vmlaunch/vmresume.
1352          * If an outer hypervisor is doing the cache flush for us
1353          * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1354          * capability to the guest too, and if EPT is disabled we're not
1355          * vulnerable.  Overall, only VMENTER_L1D_FLUSH_NEVER will
1356          * require a nested hypervisor to do a flush of its own.
1357          */
1358         if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1359                 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1360
1361         if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1362                 data |= ARCH_CAP_RDCL_NO;
1363         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1364                 data |= ARCH_CAP_SSB_NO;
1365         if (!boot_cpu_has_bug(X86_BUG_MDS))
1366                 data |= ARCH_CAP_MDS_NO;
1367
1368         /*
1369          * On TAA affected systems:
1370          *      - nothing to do if TSX is disabled on the host.
1371          *      - we emulate TSX_CTRL if present on the host.
1372          *        This lets the guest use VERW to clear CPU buffers.
1373          */
1374         if (!boot_cpu_has(X86_FEATURE_RTM))
1375                 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1376         else if (!boot_cpu_has_bug(X86_BUG_TAA))
1377                 data |= ARCH_CAP_TAA_NO;
1378
1379         return data;
1380 }
1381
1382 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1383 {
1384         switch (msr->index) {
1385         case MSR_IA32_ARCH_CAPABILITIES:
1386                 msr->data = kvm_get_arch_capabilities();
1387                 break;
1388         case MSR_IA32_UCODE_REV:
1389                 rdmsrl_safe(msr->index, &msr->data);
1390                 break;
1391         default:
1392                 if (kvm_x86_ops.get_msr_feature(msr))
1393                         return 1;
1394         }
1395         return 0;
1396 }
1397
1398 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1399 {
1400         struct kvm_msr_entry msr;
1401         int r;
1402
1403         msr.index = index;
1404         r = kvm_get_msr_feature(&msr);
1405         if (r)
1406                 return r;
1407
1408         *data = msr.data;
1409
1410         return 0;
1411 }
1412
1413 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1414 {
1415         if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1416                 return false;
1417
1418         if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1419                 return false;
1420
1421         if (efer & (EFER_LME | EFER_LMA) &&
1422             !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1423                 return false;
1424
1425         if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1426                 return false;
1427
1428         return true;
1429
1430 }
1431 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1432 {
1433         if (efer & efer_reserved_bits)
1434                 return false;
1435
1436         return __kvm_valid_efer(vcpu, efer);
1437 }
1438 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1439
1440 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1441 {
1442         u64 old_efer = vcpu->arch.efer;
1443         u64 efer = msr_info->data;
1444
1445         if (efer & efer_reserved_bits)
1446                 return 1;
1447
1448         if (!msr_info->host_initiated) {
1449                 if (!__kvm_valid_efer(vcpu, efer))
1450                         return 1;
1451
1452                 if (is_paging(vcpu) &&
1453                     (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1454                         return 1;
1455         }
1456
1457         efer &= ~EFER_LMA;
1458         efer |= vcpu->arch.efer & EFER_LMA;
1459
1460         kvm_x86_ops.set_efer(vcpu, efer);
1461
1462         /* Update reserved bits */
1463         if ((efer ^ old_efer) & EFER_NX)
1464                 kvm_mmu_reset_context(vcpu);
1465
1466         return 0;
1467 }
1468
1469 void kvm_enable_efer_bits(u64 mask)
1470 {
1471        efer_reserved_bits &= ~mask;
1472 }
1473 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1474
1475 /*
1476  * Write @data into the MSR specified by @index.  Select MSR specific fault
1477  * checks are bypassed if @host_initiated is %true.
1478  * Returns 0 on success, non-0 otherwise.
1479  * Assumes vcpu_load() was already called.
1480  */
1481 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1482                          bool host_initiated)
1483 {
1484         struct msr_data msr;
1485
1486         switch (index) {
1487         case MSR_FS_BASE:
1488         case MSR_GS_BASE:
1489         case MSR_KERNEL_GS_BASE:
1490         case MSR_CSTAR:
1491         case MSR_LSTAR:
1492                 if (is_noncanonical_address(data, vcpu))
1493                         return 1;
1494                 break;
1495         case MSR_IA32_SYSENTER_EIP:
1496         case MSR_IA32_SYSENTER_ESP:
1497                 /*
1498                  * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1499                  * non-canonical address is written on Intel but not on
1500                  * AMD (which ignores the top 32-bits, because it does
1501                  * not implement 64-bit SYSENTER).
1502                  *
1503                  * 64-bit code should hence be able to write a non-canonical
1504                  * value on AMD.  Making the address canonical ensures that
1505                  * vmentry does not fail on Intel after writing a non-canonical
1506                  * value, and that something deterministic happens if the guest
1507                  * invokes 64-bit SYSENTER.
1508                  */
1509                 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1510         }
1511
1512         msr.data = data;
1513         msr.index = index;
1514         msr.host_initiated = host_initiated;
1515
1516         return kvm_x86_ops.set_msr(vcpu, &msr);
1517 }
1518
1519 /*
1520  * Read the MSR specified by @index into @data.  Select MSR specific fault
1521  * checks are bypassed if @host_initiated is %true.
1522  * Returns 0 on success, non-0 otherwise.
1523  * Assumes vcpu_load() was already called.
1524  */
1525 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1526                   bool host_initiated)
1527 {
1528         struct msr_data msr;
1529         int ret;
1530
1531         msr.index = index;
1532         msr.host_initiated = host_initiated;
1533
1534         ret = kvm_x86_ops.get_msr(vcpu, &msr);
1535         if (!ret)
1536                 *data = msr.data;
1537         return ret;
1538 }
1539
1540 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1541 {
1542         return __kvm_get_msr(vcpu, index, data, false);
1543 }
1544 EXPORT_SYMBOL_GPL(kvm_get_msr);
1545
1546 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1547 {
1548         return __kvm_set_msr(vcpu, index, data, false);
1549 }
1550 EXPORT_SYMBOL_GPL(kvm_set_msr);
1551
1552 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1553 {
1554         u32 ecx = kvm_rcx_read(vcpu);
1555         u64 data;
1556
1557         if (kvm_get_msr(vcpu, ecx, &data)) {
1558                 trace_kvm_msr_read_ex(ecx);
1559                 kvm_inject_gp(vcpu, 0);
1560                 return 1;
1561         }
1562
1563         trace_kvm_msr_read(ecx, data);
1564
1565         kvm_rax_write(vcpu, data & -1u);
1566         kvm_rdx_write(vcpu, (data >> 32) & -1u);
1567         return kvm_skip_emulated_instruction(vcpu);
1568 }
1569 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1570
1571 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1572 {
1573         u32 ecx = kvm_rcx_read(vcpu);
1574         u64 data = kvm_read_edx_eax(vcpu);
1575
1576         if (kvm_set_msr(vcpu, ecx, data)) {
1577                 trace_kvm_msr_write_ex(ecx, data);
1578                 kvm_inject_gp(vcpu, 0);
1579                 return 1;
1580         }
1581
1582         trace_kvm_msr_write(ecx, data);
1583         return kvm_skip_emulated_instruction(vcpu);
1584 }
1585 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1586
1587 bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
1588 {
1589         return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
1590                 need_resched() || signal_pending(current);
1591 }
1592 EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request);
1593
1594 /*
1595  * The fast path for frequent and performance sensitive wrmsr emulation,
1596  * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1597  * the latency of virtual IPI by avoiding the expensive bits of transitioning
1598  * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1599  * other cases which must be called after interrupts are enabled on the host.
1600  */
1601 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1602 {
1603         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1604                 return 1;
1605
1606         if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1607                 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1608                 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1609                 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1610
1611                 data &= ~(1 << 12);
1612                 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1613                 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1614                 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1615                 trace_kvm_apic_write(APIC_ICR, (u32)data);
1616                 return 0;
1617         }
1618
1619         return 1;
1620 }
1621
1622 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
1623 {
1624         if (!kvm_can_use_hv_timer(vcpu))
1625                 return 1;
1626
1627         kvm_set_lapic_tscdeadline_msr(vcpu, data);
1628         return 0;
1629 }
1630
1631 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1632 {
1633         u32 msr = kvm_rcx_read(vcpu);
1634         u64 data;
1635         fastpath_t ret = EXIT_FASTPATH_NONE;
1636
1637         switch (msr) {
1638         case APIC_BASE_MSR + (APIC_ICR >> 4):
1639                 data = kvm_read_edx_eax(vcpu);
1640                 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
1641                         kvm_skip_emulated_instruction(vcpu);
1642                         ret = EXIT_FASTPATH_EXIT_HANDLED;
1643                 }
1644                 break;
1645         case MSR_IA32_TSCDEADLINE:
1646                 data = kvm_read_edx_eax(vcpu);
1647                 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
1648                         kvm_skip_emulated_instruction(vcpu);
1649                         ret = EXIT_FASTPATH_REENTER_GUEST;
1650                 }
1651                 break;
1652         default:
1653                 break;
1654         }
1655
1656         if (ret != EXIT_FASTPATH_NONE)
1657                 trace_kvm_msr_write(msr, data);
1658
1659         return ret;
1660 }
1661 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1662
1663 /*
1664  * Adapt set_msr() to msr_io()'s calling convention
1665  */
1666 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1667 {
1668         return __kvm_get_msr(vcpu, index, data, true);
1669 }
1670
1671 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1672 {
1673         return __kvm_set_msr(vcpu, index, *data, true);
1674 }
1675
1676 #ifdef CONFIG_X86_64
1677 struct pvclock_clock {
1678         int vclock_mode;
1679         u64 cycle_last;
1680         u64 mask;
1681         u32 mult;
1682         u32 shift;
1683         u64 base_cycles;
1684         u64 offset;
1685 };
1686
1687 struct pvclock_gtod_data {
1688         seqcount_t      seq;
1689
1690         struct pvclock_clock clock; /* extract of a clocksource struct */
1691         struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1692
1693         ktime_t         offs_boot;
1694         u64             wall_time_sec;
1695 };
1696
1697 static struct pvclock_gtod_data pvclock_gtod_data;
1698
1699 static void update_pvclock_gtod(struct timekeeper *tk)
1700 {
1701         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1702
1703         write_seqcount_begin(&vdata->seq);
1704
1705         /* copy pvclock gtod data */
1706         vdata->clock.vclock_mode        = tk->tkr_mono.clock->vdso_clock_mode;
1707         vdata->clock.cycle_last         = tk->tkr_mono.cycle_last;
1708         vdata->clock.mask               = tk->tkr_mono.mask;
1709         vdata->clock.mult               = tk->tkr_mono.mult;
1710         vdata->clock.shift              = tk->tkr_mono.shift;
1711         vdata->clock.base_cycles        = tk->tkr_mono.xtime_nsec;
1712         vdata->clock.offset             = tk->tkr_mono.base;
1713
1714         vdata->raw_clock.vclock_mode    = tk->tkr_raw.clock->vdso_clock_mode;
1715         vdata->raw_clock.cycle_last     = tk->tkr_raw.cycle_last;
1716         vdata->raw_clock.mask           = tk->tkr_raw.mask;
1717         vdata->raw_clock.mult           = tk->tkr_raw.mult;
1718         vdata->raw_clock.shift          = tk->tkr_raw.shift;
1719         vdata->raw_clock.base_cycles    = tk->tkr_raw.xtime_nsec;
1720         vdata->raw_clock.offset         = tk->tkr_raw.base;
1721
1722         vdata->wall_time_sec            = tk->xtime_sec;
1723
1724         vdata->offs_boot                = tk->offs_boot;
1725
1726         write_seqcount_end(&vdata->seq);
1727 }
1728
1729 static s64 get_kvmclock_base_ns(void)
1730 {
1731         /* Count up from boot time, but with the frequency of the raw clock.  */
1732         return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1733 }
1734 #else
1735 static s64 get_kvmclock_base_ns(void)
1736 {
1737         /* Master clock not used, so we can just use CLOCK_BOOTTIME.  */
1738         return ktime_get_boottime_ns();
1739 }
1740 #endif
1741
1742 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1743 {
1744         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1745         kvm_vcpu_kick(vcpu);
1746 }
1747
1748 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1749 {
1750         int version;
1751         int r;
1752         struct pvclock_wall_clock wc;
1753         u64 wall_nsec;
1754
1755         if (!wall_clock)
1756                 return;
1757
1758         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1759         if (r)
1760                 return;
1761
1762         if (version & 1)
1763                 ++version;  /* first time write, random junk */
1764
1765         ++version;
1766
1767         if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1768                 return;
1769
1770         /*
1771          * The guest calculates current wall clock time by adding
1772          * system time (updated by kvm_guest_time_update below) to the
1773          * wall clock specified here.  We do the reverse here.
1774          */
1775         wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1776
1777         wc.nsec = do_div(wall_nsec, 1000000000);
1778         wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1779         wc.version = version;
1780
1781         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1782
1783         version++;
1784         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1785 }
1786
1787 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1788 {
1789         do_shl32_div32(dividend, divisor);
1790         return dividend;
1791 }
1792
1793 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1794                                s8 *pshift, u32 *pmultiplier)
1795 {
1796         uint64_t scaled64;
1797         int32_t  shift = 0;
1798         uint64_t tps64;
1799         uint32_t tps32;
1800
1801         tps64 = base_hz;
1802         scaled64 = scaled_hz;
1803         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1804                 tps64 >>= 1;
1805                 shift--;
1806         }
1807
1808         tps32 = (uint32_t)tps64;
1809         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1810                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1811                         scaled64 >>= 1;
1812                 else
1813                         tps32 <<= 1;
1814                 shift++;
1815         }
1816
1817         *pshift = shift;
1818         *pmultiplier = div_frac(scaled64, tps32);
1819 }
1820
1821 #ifdef CONFIG_X86_64
1822 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1823 #endif
1824
1825 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1826 static unsigned long max_tsc_khz;
1827
1828 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1829 {
1830         u64 v = (u64)khz * (1000000 + ppm);
1831         do_div(v, 1000000);
1832         return v;
1833 }
1834
1835 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1836 {
1837         u64 ratio;
1838
1839         /* Guest TSC same frequency as host TSC? */
1840         if (!scale) {
1841                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1842                 return 0;
1843         }
1844
1845         /* TSC scaling supported? */
1846         if (!kvm_has_tsc_control) {
1847                 if (user_tsc_khz > tsc_khz) {
1848                         vcpu->arch.tsc_catchup = 1;
1849                         vcpu->arch.tsc_always_catchup = 1;
1850                         return 0;
1851                 } else {
1852                         pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1853                         return -1;
1854                 }
1855         }
1856
1857         /* TSC scaling required  - calculate ratio */
1858         ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1859                                 user_tsc_khz, tsc_khz);
1860
1861         if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1862                 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1863                                     user_tsc_khz);
1864                 return -1;
1865         }
1866
1867         vcpu->arch.tsc_scaling_ratio = ratio;
1868         return 0;
1869 }
1870
1871 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1872 {
1873         u32 thresh_lo, thresh_hi;
1874         int use_scaling = 0;
1875
1876         /* tsc_khz can be zero if TSC calibration fails */
1877         if (user_tsc_khz == 0) {
1878                 /* set tsc_scaling_ratio to a safe value */
1879                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1880                 return -1;
1881         }
1882
1883         /* Compute a scale to convert nanoseconds in TSC cycles */
1884         kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1885                            &vcpu->arch.virtual_tsc_shift,
1886                            &vcpu->arch.virtual_tsc_mult);
1887         vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1888
1889         /*
1890          * Compute the variation in TSC rate which is acceptable
1891          * within the range of tolerance and decide if the
1892          * rate being applied is within that bounds of the hardware
1893          * rate.  If so, no scaling or compensation need be done.
1894          */
1895         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1896         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1897         if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1898                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1899                 use_scaling = 1;
1900         }
1901         return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1902 }
1903
1904 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1905 {
1906         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1907                                       vcpu->arch.virtual_tsc_mult,
1908                                       vcpu->arch.virtual_tsc_shift);
1909         tsc += vcpu->arch.this_tsc_write;
1910         return tsc;
1911 }
1912
1913 static inline int gtod_is_based_on_tsc(int mode)
1914 {
1915         return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
1916 }
1917
1918 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1919 {
1920 #ifdef CONFIG_X86_64
1921         bool vcpus_matched;
1922         struct kvm_arch *ka = &vcpu->kvm->arch;
1923         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1924
1925         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1926                          atomic_read(&vcpu->kvm->online_vcpus));
1927
1928         /*
1929          * Once the masterclock is enabled, always perform request in
1930          * order to update it.
1931          *
1932          * In order to enable masterclock, the host clocksource must be TSC
1933          * and the vcpus need to have matched TSCs.  When that happens,
1934          * perform request to enable masterclock.
1935          */
1936         if (ka->use_master_clock ||
1937             (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1938                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1939
1940         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1941                             atomic_read(&vcpu->kvm->online_vcpus),
1942                             ka->use_master_clock, gtod->clock.vclock_mode);
1943 #endif
1944 }
1945
1946 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1947 {
1948         u64 curr_offset = vcpu->arch.l1_tsc_offset;
1949         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1950 }
1951
1952 /*
1953  * Multiply tsc by a fixed point number represented by ratio.
1954  *
1955  * The most significant 64-N bits (mult) of ratio represent the
1956  * integral part of the fixed point number; the remaining N bits
1957  * (frac) represent the fractional part, ie. ratio represents a fixed
1958  * point number (mult + frac * 2^(-N)).
1959  *
1960  * N equals to kvm_tsc_scaling_ratio_frac_bits.
1961  */
1962 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1963 {
1964         return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1965 }
1966
1967 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1968 {
1969         u64 _tsc = tsc;
1970         u64 ratio = vcpu->arch.tsc_scaling_ratio;
1971
1972         if (ratio != kvm_default_tsc_scaling_ratio)
1973                 _tsc = __scale_tsc(ratio, tsc);
1974
1975         return _tsc;
1976 }
1977 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1978
1979 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1980 {
1981         u64 tsc;
1982
1983         tsc = kvm_scale_tsc(vcpu, rdtsc());
1984
1985         return target_tsc - tsc;
1986 }
1987
1988 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1989 {
1990         return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1991 }
1992 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1993
1994 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1995 {
1996         vcpu->arch.l1_tsc_offset = offset;
1997         vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset);
1998 }
1999
2000 static inline bool kvm_check_tsc_unstable(void)
2001 {
2002 #ifdef CONFIG_X86_64
2003         /*
2004          * TSC is marked unstable when we're running on Hyper-V,
2005          * 'TSC page' clocksource is good.
2006          */
2007         if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2008                 return false;
2009 #endif
2010         return check_tsc_unstable();
2011 }
2012
2013 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
2014 {
2015         struct kvm *kvm = vcpu->kvm;
2016         u64 offset, ns, elapsed;
2017         unsigned long flags;
2018         bool matched;
2019         bool already_matched;
2020         u64 data = msr->data;
2021         bool synchronizing = false;
2022
2023         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2024         offset = kvm_compute_tsc_offset(vcpu, data);
2025         ns = get_kvmclock_base_ns();
2026         elapsed = ns - kvm->arch.last_tsc_nsec;
2027
2028         if (vcpu->arch.virtual_tsc_khz) {
2029                 if (data == 0 && msr->host_initiated) {
2030                         /*
2031                          * detection of vcpu initialization -- need to sync
2032                          * with other vCPUs. This particularly helps to keep
2033                          * kvm_clock stable after CPU hotplug
2034                          */
2035                         synchronizing = true;
2036                 } else {
2037                         u64 tsc_exp = kvm->arch.last_tsc_write +
2038                                                 nsec_to_cycles(vcpu, elapsed);
2039                         u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2040                         /*
2041                          * Special case: TSC write with a small delta (1 second)
2042                          * of virtual cycle time against real time is
2043                          * interpreted as an attempt to synchronize the CPU.
2044                          */
2045                         synchronizing = data < tsc_exp + tsc_hz &&
2046                                         data + tsc_hz > tsc_exp;
2047                 }
2048         }
2049
2050         /*
2051          * For a reliable TSC, we can match TSC offsets, and for an unstable
2052          * TSC, we add elapsed time in this computation.  We could let the
2053          * compensation code attempt to catch up if we fall behind, but
2054          * it's better to try to match offsets from the beginning.
2055          */
2056         if (synchronizing &&
2057             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2058                 if (!kvm_check_tsc_unstable()) {
2059                         offset = kvm->arch.cur_tsc_offset;
2060                 } else {
2061                         u64 delta = nsec_to_cycles(vcpu, elapsed);
2062                         data += delta;
2063                         offset = kvm_compute_tsc_offset(vcpu, data);
2064                 }
2065                 matched = true;
2066                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2067         } else {
2068                 /*
2069                  * We split periods of matched TSC writes into generations.
2070                  * For each generation, we track the original measured
2071                  * nanosecond time, offset, and write, so if TSCs are in
2072                  * sync, we can match exact offset, and if not, we can match
2073                  * exact software computation in compute_guest_tsc()
2074                  *
2075                  * These values are tracked in kvm->arch.cur_xxx variables.
2076                  */
2077                 kvm->arch.cur_tsc_generation++;
2078                 kvm->arch.cur_tsc_nsec = ns;
2079                 kvm->arch.cur_tsc_write = data;
2080                 kvm->arch.cur_tsc_offset = offset;
2081                 matched = false;
2082         }
2083
2084         /*
2085          * We also track th most recent recorded KHZ, write and time to
2086          * allow the matching interval to be extended at each write.
2087          */
2088         kvm->arch.last_tsc_nsec = ns;
2089         kvm->arch.last_tsc_write = data;
2090         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2091
2092         vcpu->arch.last_guest_tsc = data;
2093
2094         /* Keep track of which generation this VCPU has synchronized to */
2095         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2096         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2097         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2098
2099         if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
2100                 update_ia32_tsc_adjust_msr(vcpu, offset);
2101
2102         kvm_vcpu_write_tsc_offset(vcpu, offset);
2103         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2104
2105         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2106         if (!matched) {
2107                 kvm->arch.nr_vcpus_matched_tsc = 0;
2108         } else if (!already_matched) {
2109                 kvm->arch.nr_vcpus_matched_tsc++;
2110         }
2111
2112         kvm_track_tsc_matching(vcpu);
2113         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2114 }
2115
2116 EXPORT_SYMBOL_GPL(kvm_write_tsc);
2117
2118 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2119                                            s64 adjustment)
2120 {
2121         u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2122         kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2123 }
2124
2125 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2126 {
2127         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2128                 WARN_ON(adjustment < 0);
2129         adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2130         adjust_tsc_offset_guest(vcpu, adjustment);
2131 }
2132
2133 #ifdef CONFIG_X86_64
2134
2135 static u64 read_tsc(void)
2136 {
2137         u64 ret = (u64)rdtsc_ordered();
2138         u64 last = pvclock_gtod_data.clock.cycle_last;
2139
2140         if (likely(ret >= last))
2141                 return ret;
2142
2143         /*
2144          * GCC likes to generate cmov here, but this branch is extremely
2145          * predictable (it's just a function of time and the likely is
2146          * very likely) and there's a data dependence, so force GCC
2147          * to generate a branch instead.  I don't barrier() because
2148          * we don't actually need a barrier, and if this function
2149          * ever gets inlined it will generate worse code.
2150          */
2151         asm volatile ("");
2152         return last;
2153 }
2154
2155 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2156                           int *mode)
2157 {
2158         long v;
2159         u64 tsc_pg_val;
2160
2161         switch (clock->vclock_mode) {
2162         case VDSO_CLOCKMODE_HVCLOCK:
2163                 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2164                                                   tsc_timestamp);
2165                 if (tsc_pg_val != U64_MAX) {
2166                         /* TSC page valid */
2167                         *mode = VDSO_CLOCKMODE_HVCLOCK;
2168                         v = (tsc_pg_val - clock->cycle_last) &
2169                                 clock->mask;
2170                 } else {
2171                         /* TSC page invalid */
2172                         *mode = VDSO_CLOCKMODE_NONE;
2173                 }
2174                 break;
2175         case VDSO_CLOCKMODE_TSC:
2176                 *mode = VDSO_CLOCKMODE_TSC;
2177                 *tsc_timestamp = read_tsc();
2178                 v = (*tsc_timestamp - clock->cycle_last) &
2179                         clock->mask;
2180                 break;
2181         default:
2182                 *mode = VDSO_CLOCKMODE_NONE;
2183         }
2184
2185         if (*mode == VDSO_CLOCKMODE_NONE)
2186                 *tsc_timestamp = v = 0;
2187
2188         return v * clock->mult;
2189 }
2190
2191 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2192 {
2193         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2194         unsigned long seq;
2195         int mode;
2196         u64 ns;
2197
2198         do {
2199                 seq = read_seqcount_begin(&gtod->seq);
2200                 ns = gtod->raw_clock.base_cycles;
2201                 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2202                 ns >>= gtod->raw_clock.shift;
2203                 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2204         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2205         *t = ns;
2206
2207         return mode;
2208 }
2209
2210 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2211 {
2212         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2213         unsigned long seq;
2214         int mode;
2215         u64 ns;
2216
2217         do {
2218                 seq = read_seqcount_begin(&gtod->seq);
2219                 ts->tv_sec = gtod->wall_time_sec;
2220                 ns = gtod->clock.base_cycles;
2221                 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2222                 ns >>= gtod->clock.shift;
2223         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2224
2225         ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2226         ts->tv_nsec = ns;
2227
2228         return mode;
2229 }
2230
2231 /* returns true if host is using TSC based clocksource */
2232 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2233 {
2234         /* checked again under seqlock below */
2235         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2236                 return false;
2237
2238         return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2239                                                       tsc_timestamp));
2240 }
2241
2242 /* returns true if host is using TSC based clocksource */
2243 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2244                                            u64 *tsc_timestamp)
2245 {
2246         /* checked again under seqlock below */
2247         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2248                 return false;
2249
2250         return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2251 }
2252 #endif
2253
2254 /*
2255  *
2256  * Assuming a stable TSC across physical CPUS, and a stable TSC
2257  * across virtual CPUs, the following condition is possible.
2258  * Each numbered line represents an event visible to both
2259  * CPUs at the next numbered event.
2260  *
2261  * "timespecX" represents host monotonic time. "tscX" represents
2262  * RDTSC value.
2263  *
2264  *              VCPU0 on CPU0           |       VCPU1 on CPU1
2265  *
2266  * 1.  read timespec0,tsc0
2267  * 2.                                   | timespec1 = timespec0 + N
2268  *                                      | tsc1 = tsc0 + M
2269  * 3. transition to guest               | transition to guest
2270  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2271  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
2272  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2273  *
2274  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2275  *
2276  *      - ret0 < ret1
2277  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2278  *              ...
2279  *      - 0 < N - M => M < N
2280  *
2281  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2282  * always the case (the difference between two distinct xtime instances
2283  * might be smaller then the difference between corresponding TSC reads,
2284  * when updating guest vcpus pvclock areas).
2285  *
2286  * To avoid that problem, do not allow visibility of distinct
2287  * system_timestamp/tsc_timestamp values simultaneously: use a master
2288  * copy of host monotonic time values. Update that master copy
2289  * in lockstep.
2290  *
2291  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2292  *
2293  */
2294
2295 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2296 {
2297 #ifdef CONFIG_X86_64
2298         struct kvm_arch *ka = &kvm->arch;
2299         int vclock_mode;
2300         bool host_tsc_clocksource, vcpus_matched;
2301
2302         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2303                         atomic_read(&kvm->online_vcpus));
2304
2305         /*
2306          * If the host uses TSC clock, then passthrough TSC as stable
2307          * to the guest.
2308          */
2309         host_tsc_clocksource = kvm_get_time_and_clockread(
2310                                         &ka->master_kernel_ns,
2311                                         &ka->master_cycle_now);
2312
2313         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2314                                 && !ka->backwards_tsc_observed
2315                                 && !ka->boot_vcpu_runs_old_kvmclock;
2316
2317         if (ka->use_master_clock)
2318                 atomic_set(&kvm_guest_has_master_clock, 1);
2319
2320         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2321         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2322                                         vcpus_matched);
2323 #endif
2324 }
2325
2326 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2327 {
2328         kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2329 }
2330
2331 static void kvm_gen_update_masterclock(struct kvm *kvm)
2332 {
2333 #ifdef CONFIG_X86_64
2334         int i;
2335         struct kvm_vcpu *vcpu;
2336         struct kvm_arch *ka = &kvm->arch;
2337
2338         spin_lock(&ka->pvclock_gtod_sync_lock);
2339         kvm_make_mclock_inprogress_request(kvm);
2340         /* no guest entries from this point */
2341         pvclock_update_vm_gtod_copy(kvm);
2342
2343         kvm_for_each_vcpu(i, vcpu, kvm)
2344                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2345
2346         /* guest entries allowed */
2347         kvm_for_each_vcpu(i, vcpu, kvm)
2348                 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2349
2350         spin_unlock(&ka->pvclock_gtod_sync_lock);
2351 #endif
2352 }
2353
2354 u64 get_kvmclock_ns(struct kvm *kvm)
2355 {
2356         struct kvm_arch *ka = &kvm->arch;
2357         struct pvclock_vcpu_time_info hv_clock;
2358         u64 ret;
2359
2360         spin_lock(&ka->pvclock_gtod_sync_lock);
2361         if (!ka->use_master_clock) {
2362                 spin_unlock(&ka->pvclock_gtod_sync_lock);
2363                 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2364         }
2365
2366         hv_clock.tsc_timestamp = ka->master_cycle_now;
2367         hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2368         spin_unlock(&ka->pvclock_gtod_sync_lock);
2369
2370         /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2371         get_cpu();
2372
2373         if (__this_cpu_read(cpu_tsc_khz)) {
2374                 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2375                                    &hv_clock.tsc_shift,
2376                                    &hv_clock.tsc_to_system_mul);
2377                 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2378         } else
2379                 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2380
2381         put_cpu();
2382
2383         return ret;
2384 }
2385
2386 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2387 {
2388         struct kvm_vcpu_arch *vcpu = &v->arch;
2389         struct pvclock_vcpu_time_info guest_hv_clock;
2390
2391         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2392                 &guest_hv_clock, sizeof(guest_hv_clock))))
2393                 return;
2394
2395         /* This VCPU is paused, but it's legal for a guest to read another
2396          * VCPU's kvmclock, so we really have to follow the specification where
2397          * it says that version is odd if data is being modified, and even after
2398          * it is consistent.
2399          *
2400          * Version field updates must be kept separate.  This is because
2401          * kvm_write_guest_cached might use a "rep movs" instruction, and
2402          * writes within a string instruction are weakly ordered.  So there
2403          * are three writes overall.
2404          *
2405          * As a small optimization, only write the version field in the first
2406          * and third write.  The vcpu->pv_time cache is still valid, because the
2407          * version field is the first in the struct.
2408          */
2409         BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2410
2411         if (guest_hv_clock.version & 1)
2412                 ++guest_hv_clock.version;  /* first time write, random junk */
2413
2414         vcpu->hv_clock.version = guest_hv_clock.version + 1;
2415         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2416                                 &vcpu->hv_clock,
2417                                 sizeof(vcpu->hv_clock.version));
2418
2419         smp_wmb();
2420
2421         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2422         vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2423
2424         if (vcpu->pvclock_set_guest_stopped_request) {
2425                 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2426                 vcpu->pvclock_set_guest_stopped_request = false;
2427         }
2428
2429         trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2430
2431         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2432                                 &vcpu->hv_clock,
2433                                 sizeof(vcpu->hv_clock));
2434
2435         smp_wmb();
2436
2437         vcpu->hv_clock.version++;
2438         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2439                                 &vcpu->hv_clock,
2440                                 sizeof(vcpu->hv_clock.version));
2441 }
2442
2443 static int kvm_guest_time_update(struct kvm_vcpu *v)
2444 {
2445         unsigned long flags, tgt_tsc_khz;
2446         struct kvm_vcpu_arch *vcpu = &v->arch;
2447         struct kvm_arch *ka = &v->kvm->arch;
2448         s64 kernel_ns;
2449         u64 tsc_timestamp, host_tsc;
2450         u8 pvclock_flags;
2451         bool use_master_clock;
2452
2453         kernel_ns = 0;
2454         host_tsc = 0;
2455
2456         /*
2457          * If the host uses TSC clock, then passthrough TSC as stable
2458          * to the guest.
2459          */
2460         spin_lock(&ka->pvclock_gtod_sync_lock);
2461         use_master_clock = ka->use_master_clock;
2462         if (use_master_clock) {
2463                 host_tsc = ka->master_cycle_now;
2464                 kernel_ns = ka->master_kernel_ns;
2465         }
2466         spin_unlock(&ka->pvclock_gtod_sync_lock);
2467
2468         /* Keep irq disabled to prevent changes to the clock */
2469         local_irq_save(flags);
2470         tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2471         if (unlikely(tgt_tsc_khz == 0)) {
2472                 local_irq_restore(flags);
2473                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2474                 return 1;
2475         }
2476         if (!use_master_clock) {
2477                 host_tsc = rdtsc();
2478                 kernel_ns = get_kvmclock_base_ns();
2479         }
2480
2481         tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2482
2483         /*
2484          * We may have to catch up the TSC to match elapsed wall clock
2485          * time for two reasons, even if kvmclock is used.
2486          *   1) CPU could have been running below the maximum TSC rate
2487          *   2) Broken TSC compensation resets the base at each VCPU
2488          *      entry to avoid unknown leaps of TSC even when running
2489          *      again on the same CPU.  This may cause apparent elapsed
2490          *      time to disappear, and the guest to stand still or run
2491          *      very slowly.
2492          */
2493         if (vcpu->tsc_catchup) {
2494                 u64 tsc = compute_guest_tsc(v, kernel_ns);
2495                 if (tsc > tsc_timestamp) {
2496                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2497                         tsc_timestamp = tsc;
2498                 }
2499         }
2500
2501         local_irq_restore(flags);
2502
2503         /* With all the info we got, fill in the values */
2504
2505         if (kvm_has_tsc_control)
2506                 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2507
2508         if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2509                 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2510                                    &vcpu->hv_clock.tsc_shift,
2511                                    &vcpu->hv_clock.tsc_to_system_mul);
2512                 vcpu->hw_tsc_khz = tgt_tsc_khz;
2513         }
2514
2515         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2516         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2517         vcpu->last_guest_tsc = tsc_timestamp;
2518
2519         /* If the host uses TSC clocksource, then it is stable */
2520         pvclock_flags = 0;
2521         if (use_master_clock)
2522                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2523
2524         vcpu->hv_clock.flags = pvclock_flags;
2525
2526         if (vcpu->pv_time_enabled)
2527                 kvm_setup_pvclock_page(v);
2528         if (v == kvm_get_vcpu(v->kvm, 0))
2529                 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2530         return 0;
2531 }
2532
2533 /*
2534  * kvmclock updates which are isolated to a given vcpu, such as
2535  * vcpu->cpu migration, should not allow system_timestamp from
2536  * the rest of the vcpus to remain static. Otherwise ntp frequency
2537  * correction applies to one vcpu's system_timestamp but not
2538  * the others.
2539  *
2540  * So in those cases, request a kvmclock update for all vcpus.
2541  * We need to rate-limit these requests though, as they can
2542  * considerably slow guests that have a large number of vcpus.
2543  * The time for a remote vcpu to update its kvmclock is bound
2544  * by the delay we use to rate-limit the updates.
2545  */
2546
2547 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2548
2549 static void kvmclock_update_fn(struct work_struct *work)
2550 {
2551         int i;
2552         struct delayed_work *dwork = to_delayed_work(work);
2553         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2554                                            kvmclock_update_work);
2555         struct kvm *kvm = container_of(ka, struct kvm, arch);
2556         struct kvm_vcpu *vcpu;
2557
2558         kvm_for_each_vcpu(i, vcpu, kvm) {
2559                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2560                 kvm_vcpu_kick(vcpu);
2561         }
2562 }
2563
2564 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2565 {
2566         struct kvm *kvm = v->kvm;
2567
2568         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2569         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2570                                         KVMCLOCK_UPDATE_DELAY);
2571 }
2572
2573 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2574
2575 static void kvmclock_sync_fn(struct work_struct *work)
2576 {
2577         struct delayed_work *dwork = to_delayed_work(work);
2578         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2579                                            kvmclock_sync_work);
2580         struct kvm *kvm = container_of(ka, struct kvm, arch);
2581
2582         if (!kvmclock_periodic_sync)
2583                 return;
2584
2585         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2586         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2587                                         KVMCLOCK_SYNC_PERIOD);
2588 }
2589
2590 /*
2591  * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2592  */
2593 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2594 {
2595         /* McStatusWrEn enabled? */
2596         if (guest_cpuid_is_amd_or_hygon(vcpu))
2597                 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2598
2599         return false;
2600 }
2601
2602 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2603 {
2604         u64 mcg_cap = vcpu->arch.mcg_cap;
2605         unsigned bank_num = mcg_cap & 0xff;
2606         u32 msr = msr_info->index;
2607         u64 data = msr_info->data;
2608
2609         switch (msr) {
2610         case MSR_IA32_MCG_STATUS:
2611                 vcpu->arch.mcg_status = data;
2612                 break;
2613         case MSR_IA32_MCG_CTL:
2614                 if (!(mcg_cap & MCG_CTL_P) &&
2615                     (data || !msr_info->host_initiated))
2616                         return 1;
2617                 if (data != 0 && data != ~(u64)0)
2618                         return 1;
2619                 vcpu->arch.mcg_ctl = data;
2620                 break;
2621         default:
2622                 if (msr >= MSR_IA32_MC0_CTL &&
2623                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2624                         u32 offset = array_index_nospec(
2625                                 msr - MSR_IA32_MC0_CTL,
2626                                 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2627
2628                         /* only 0 or all 1s can be written to IA32_MCi_CTL
2629                          * some Linux kernels though clear bit 10 in bank 4 to
2630                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2631                          * this to avoid an uncatched #GP in the guest
2632                          */
2633                         if ((offset & 0x3) == 0 &&
2634                             data != 0 && (data | (1 << 10)) != ~(u64)0)
2635                                 return -1;
2636
2637                         /* MCi_STATUS */
2638                         if (!msr_info->host_initiated &&
2639                             (offset & 0x3) == 1 && data != 0) {
2640                                 if (!can_set_mci_status(vcpu))
2641                                         return -1;
2642                         }
2643
2644                         vcpu->arch.mce_banks[offset] = data;
2645                         break;
2646                 }
2647                 return 1;
2648         }
2649         return 0;
2650 }
2651
2652 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2653 {
2654         struct kvm *kvm = vcpu->kvm;
2655         int lm = is_long_mode(vcpu);
2656         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2657                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2658         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2659                 : kvm->arch.xen_hvm_config.blob_size_32;
2660         u32 page_num = data & ~PAGE_MASK;
2661         u64 page_addr = data & PAGE_MASK;
2662         u8 *page;
2663         int r;
2664
2665         r = -E2BIG;
2666         if (page_num >= blob_size)
2667                 goto out;
2668         r = -ENOMEM;
2669         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2670         if (IS_ERR(page)) {
2671                 r = PTR_ERR(page);
2672                 goto out;
2673         }
2674         if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2675                 goto out_free;
2676         r = 0;
2677 out_free:
2678         kfree(page);
2679 out:
2680         return r;
2681 }
2682
2683 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
2684 {
2685         u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
2686
2687         return (vcpu->arch.apf.msr_en_val & mask) == mask;
2688 }
2689
2690 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2691 {
2692         gpa_t gpa = data & ~0x3f;
2693
2694         /* Bits 4:5 are reserved, Should be zero */
2695         if (data & 0x30)
2696                 return 1;
2697
2698         if (!lapic_in_kernel(vcpu))
2699                 return 1;
2700
2701         vcpu->arch.apf.msr_en_val = data;
2702
2703         if (!kvm_pv_async_pf_enabled(vcpu)) {
2704                 kvm_clear_async_pf_completion_queue(vcpu);
2705                 kvm_async_pf_hash_reset(vcpu);
2706                 return 0;
2707         }
2708
2709         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2710                                         sizeof(u64)))
2711                 return 1;
2712
2713         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2714         vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2715
2716         kvm_async_pf_wakeup_all(vcpu);
2717
2718         return 0;
2719 }
2720
2721 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
2722 {
2723         /* Bits 8-63 are reserved */
2724         if (data >> 8)
2725                 return 1;
2726
2727         if (!lapic_in_kernel(vcpu))
2728                 return 1;
2729
2730         vcpu->arch.apf.msr_int_val = data;
2731
2732         vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
2733
2734         return 0;
2735 }
2736
2737 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2738 {
2739         vcpu->arch.pv_time_enabled = false;
2740         vcpu->arch.time = 0;
2741 }
2742
2743 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
2744 {
2745         ++vcpu->stat.tlb_flush;
2746         kvm_x86_ops.tlb_flush_all(vcpu);
2747 }
2748
2749 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
2750 {
2751         ++vcpu->stat.tlb_flush;
2752         kvm_x86_ops.tlb_flush_guest(vcpu);
2753 }
2754
2755 static void record_steal_time(struct kvm_vcpu *vcpu)
2756 {
2757         struct kvm_host_map map;
2758         struct kvm_steal_time *st;
2759
2760         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2761                 return;
2762
2763         /* -EAGAIN is returned in atomic context so we can just return. */
2764         if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2765                         &map, &vcpu->arch.st.cache, false))
2766                 return;
2767
2768         st = map.hva +
2769                 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2770
2771         /*
2772          * Doing a TLB flush here, on the guest's behalf, can avoid
2773          * expensive IPIs.
2774          */
2775         trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2776                 st->preempted & KVM_VCPU_FLUSH_TLB);
2777         if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2778                 kvm_vcpu_flush_tlb_guest(vcpu);
2779
2780         vcpu->arch.st.preempted = 0;
2781
2782         if (st->version & 1)
2783                 st->version += 1;  /* first time write, random junk */
2784
2785         st->version += 1;
2786
2787         smp_wmb();
2788
2789         st->steal += current->sched_info.run_delay -
2790                 vcpu->arch.st.last_steal;
2791         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2792
2793         smp_wmb();
2794
2795         st->version += 1;
2796
2797         kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2798 }
2799
2800 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2801 {
2802         bool pr = false;
2803         u32 msr = msr_info->index;
2804         u64 data = msr_info->data;
2805
2806         switch (msr) {
2807         case MSR_AMD64_NB_CFG:
2808         case MSR_IA32_UCODE_WRITE:
2809         case MSR_VM_HSAVE_PA:
2810         case MSR_AMD64_PATCH_LOADER:
2811         case MSR_AMD64_BU_CFG2:
2812         case MSR_AMD64_DC_CFG:
2813         case MSR_F15H_EX_CFG:
2814                 break;
2815
2816         case MSR_IA32_UCODE_REV:
2817                 if (msr_info->host_initiated)
2818                         vcpu->arch.microcode_version = data;
2819                 break;
2820         case MSR_IA32_ARCH_CAPABILITIES:
2821                 if (!msr_info->host_initiated)
2822                         return 1;
2823                 vcpu->arch.arch_capabilities = data;
2824                 break;
2825         case MSR_EFER:
2826                 return set_efer(vcpu, msr_info);
2827         case MSR_K7_HWCR:
2828                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2829                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2830                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2831
2832                 /* Handle McStatusWrEn */
2833                 if (data == BIT_ULL(18)) {
2834                         vcpu->arch.msr_hwcr = data;
2835                 } else if (data != 0) {
2836                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2837                                     data);
2838                         return 1;
2839                 }
2840                 break;
2841         case MSR_FAM10H_MMIO_CONF_BASE:
2842                 if (data != 0) {
2843                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2844                                     "0x%llx\n", data);
2845                         return 1;
2846                 }
2847                 break;
2848         case MSR_IA32_DEBUGCTLMSR:
2849                 if (!data) {
2850                         /* We support the non-activated case already */
2851                         break;
2852                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2853                         /* Values other than LBR and BTF are vendor-specific,
2854                            thus reserved and should throw a #GP */
2855                         return 1;
2856                 }
2857                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2858                             __func__, data);
2859                 break;
2860         case 0x200 ... 0x2ff:
2861                 return kvm_mtrr_set_msr(vcpu, msr, data);
2862         case MSR_IA32_APICBASE:
2863                 return kvm_set_apic_base(vcpu, msr_info);
2864         case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
2865                 return kvm_x2apic_msr_write(vcpu, msr, data);
2866         case MSR_IA32_TSCDEADLINE:
2867                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2868                 break;
2869         case MSR_IA32_TSC_ADJUST:
2870                 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2871                         if (!msr_info->host_initiated) {
2872                                 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2873                                 adjust_tsc_offset_guest(vcpu, adj);
2874                         }
2875                         vcpu->arch.ia32_tsc_adjust_msr = data;
2876                 }
2877                 break;
2878         case MSR_IA32_MISC_ENABLE:
2879                 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2880                     ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2881                         if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2882                                 return 1;
2883                         vcpu->arch.ia32_misc_enable_msr = data;
2884                         kvm_update_cpuid(vcpu);
2885                 } else {
2886                         vcpu->arch.ia32_misc_enable_msr = data;
2887                 }
2888                 break;
2889         case MSR_IA32_SMBASE:
2890                 if (!msr_info->host_initiated)
2891                         return 1;
2892                 vcpu->arch.smbase = data;
2893                 break;
2894         case MSR_IA32_POWER_CTL:
2895                 vcpu->arch.msr_ia32_power_ctl = data;
2896                 break;
2897         case MSR_IA32_TSC:
2898                 kvm_write_tsc(vcpu, msr_info);
2899                 break;
2900         case MSR_IA32_XSS:
2901                 if (!msr_info->host_initiated &&
2902                     !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
2903                         return 1;
2904                 /*
2905                  * KVM supports exposing PT to the guest, but does not support
2906                  * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
2907                  * XSAVES/XRSTORS to save/restore PT MSRs.
2908                  */
2909                 if (data & ~supported_xss)
2910                         return 1;
2911                 vcpu->arch.ia32_xss = data;
2912                 break;
2913         case MSR_SMI_COUNT:
2914                 if (!msr_info->host_initiated)
2915                         return 1;
2916                 vcpu->arch.smi_count = data;
2917                 break;
2918         case MSR_KVM_WALL_CLOCK_NEW:
2919         case MSR_KVM_WALL_CLOCK:
2920                 vcpu->kvm->arch.wall_clock = data;
2921                 kvm_write_wall_clock(vcpu->kvm, data);
2922                 break;
2923         case MSR_KVM_SYSTEM_TIME_NEW:
2924         case MSR_KVM_SYSTEM_TIME: {
2925                 struct kvm_arch *ka = &vcpu->kvm->arch;
2926
2927                 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2928                         bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2929
2930                         if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2931                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2932
2933                         ka->boot_vcpu_runs_old_kvmclock = tmp;
2934                 }
2935
2936                 vcpu->arch.time = data;
2937                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2938
2939                 /* we verify if the enable bit is set... */
2940                 vcpu->arch.pv_time_enabled = false;
2941                 if (!(data & 1))
2942                         break;
2943
2944                 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2945                      &vcpu->arch.pv_time, data & ~1ULL,
2946                      sizeof(struct pvclock_vcpu_time_info)))
2947                         vcpu->arch.pv_time_enabled = true;
2948
2949                 break;
2950         }
2951         case MSR_KVM_ASYNC_PF_EN:
2952                 if (kvm_pv_enable_async_pf(vcpu, data))
2953                         return 1;
2954                 break;
2955         case MSR_KVM_ASYNC_PF_INT:
2956                 if (kvm_pv_enable_async_pf_int(vcpu, data))
2957                         return 1;
2958                 break;
2959         case MSR_KVM_ASYNC_PF_ACK:
2960                 if (data & 0x1) {
2961                         vcpu->arch.apf.pageready_pending = false;
2962                         kvm_check_async_pf_completion(vcpu);
2963                 }
2964                 break;
2965         case MSR_KVM_STEAL_TIME:
2966
2967                 if (unlikely(!sched_info_on()))
2968                         return 1;
2969
2970                 if (data & KVM_STEAL_RESERVED_MASK)
2971                         return 1;
2972
2973                 vcpu->arch.st.msr_val = data;
2974
2975                 if (!(data & KVM_MSR_ENABLED))
2976                         break;
2977
2978                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2979
2980                 break;
2981         case MSR_KVM_PV_EOI_EN:
2982                 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2983                         return 1;
2984                 break;
2985
2986         case MSR_KVM_POLL_CONTROL:
2987                 /* only enable bit supported */
2988                 if (data & (-1ULL << 1))
2989                         return 1;
2990
2991                 vcpu->arch.msr_kvm_poll_control = data;
2992                 break;
2993
2994         case MSR_IA32_MCG_CTL:
2995         case MSR_IA32_MCG_STATUS:
2996         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2997                 return set_msr_mce(vcpu, msr_info);
2998
2999         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3000         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3001                 pr = true; /* fall through */
3002         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3003         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3004                 if (kvm_pmu_is_valid_msr(vcpu, msr))
3005                         return kvm_pmu_set_msr(vcpu, msr_info);
3006
3007                 if (pr || data != 0)
3008                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3009                                     "0x%x data 0x%llx\n", msr, data);
3010                 break;
3011         case MSR_K7_CLK_CTL:
3012                 /*
3013                  * Ignore all writes to this no longer documented MSR.
3014                  * Writes are only relevant for old K7 processors,
3015                  * all pre-dating SVM, but a recommended workaround from
3016                  * AMD for these chips. It is possible to specify the
3017                  * affected processor models on the command line, hence
3018                  * the need to ignore the workaround.
3019                  */
3020                 break;
3021         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3022         case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3023         case HV_X64_MSR_SYNDBG_OPTIONS:
3024         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3025         case HV_X64_MSR_CRASH_CTL:
3026         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3027         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3028         case HV_X64_MSR_TSC_EMULATION_CONTROL:
3029         case HV_X64_MSR_TSC_EMULATION_STATUS:
3030                 return kvm_hv_set_msr_common(vcpu, msr, data,
3031                                              msr_info->host_initiated);
3032         case MSR_IA32_BBL_CR_CTL3:
3033                 /* Drop writes to this legacy MSR -- see rdmsr
3034                  * counterpart for further detail.
3035                  */
3036                 if (report_ignored_msrs)
3037                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3038                                 msr, data);
3039                 break;
3040         case MSR_AMD64_OSVW_ID_LENGTH:
3041                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3042                         return 1;
3043                 vcpu->arch.osvw.length = data;
3044                 break;
3045         case MSR_AMD64_OSVW_STATUS:
3046                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3047                         return 1;
3048                 vcpu->arch.osvw.status = data;
3049                 break;
3050         case MSR_PLATFORM_INFO:
3051                 if (!msr_info->host_initiated ||
3052                     (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3053                      cpuid_fault_enabled(vcpu)))
3054                         return 1;
3055                 vcpu->arch.msr_platform_info = data;
3056                 break;
3057         case MSR_MISC_FEATURES_ENABLES:
3058                 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3059                     (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3060                      !supports_cpuid_fault(vcpu)))
3061                         return 1;
3062                 vcpu->arch.msr_misc_features_enables = data;
3063                 break;
3064         default:
3065                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
3066                         return xen_hvm_config(vcpu, data);
3067                 if (kvm_pmu_is_valid_msr(vcpu, msr))
3068                         return kvm_pmu_set_msr(vcpu, msr_info);
3069                 if (!ignore_msrs) {
3070                         vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
3071                                     msr, data);
3072                         return 1;
3073                 } else {
3074                         if (report_ignored_msrs)
3075                                 vcpu_unimpl(vcpu,
3076                                         "ignored wrmsr: 0x%x data 0x%llx\n",
3077                                         msr, data);
3078                         break;
3079                 }
3080         }
3081         return 0;
3082 }
3083 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3084
3085 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3086 {
3087         u64 data;
3088         u64 mcg_cap = vcpu->arch.mcg_cap;
3089         unsigned bank_num = mcg_cap & 0xff;
3090
3091         switch (msr) {
3092         case MSR_IA32_P5_MC_ADDR:
3093         case MSR_IA32_P5_MC_TYPE:
3094                 data = 0;
3095                 break;
3096         case MSR_IA32_MCG_CAP:
3097                 data = vcpu->arch.mcg_cap;
3098                 break;
3099         case MSR_IA32_MCG_CTL:
3100                 if (!(mcg_cap & MCG_CTL_P) && !host)
3101                         return 1;
3102                 data = vcpu->arch.mcg_ctl;
3103                 break;
3104         case MSR_IA32_MCG_STATUS:
3105                 data = vcpu->arch.mcg_status;
3106                 break;
3107         default:
3108                 if (msr >= MSR_IA32_MC0_CTL &&
3109                     msr < MSR_IA32_MCx_CTL(bank_num)) {
3110                         u32 offset = array_index_nospec(
3111                                 msr - MSR_IA32_MC0_CTL,
3112                                 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3113
3114                         data = vcpu->arch.mce_banks[offset];
3115                         break;
3116                 }
3117                 return 1;
3118         }
3119         *pdata = data;
3120         return 0;
3121 }
3122
3123 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3124 {
3125         switch (msr_info->index) {
3126         case MSR_IA32_PLATFORM_ID:
3127         case MSR_IA32_EBL_CR_POWERON:
3128         case MSR_IA32_DEBUGCTLMSR:
3129         case MSR_IA32_LASTBRANCHFROMIP:
3130         case MSR_IA32_LASTBRANCHTOIP:
3131         case MSR_IA32_LASTINTFROMIP:
3132         case MSR_IA32_LASTINTTOIP:
3133         case MSR_K8_SYSCFG:
3134         case MSR_K8_TSEG_ADDR:
3135         case MSR_K8_TSEG_MASK:
3136         case MSR_VM_HSAVE_PA:
3137         case MSR_K8_INT_PENDING_MSG:
3138         case MSR_AMD64_NB_CFG:
3139         case MSR_FAM10H_MMIO_CONF_BASE:
3140         case MSR_AMD64_BU_CFG2:
3141         case MSR_IA32_PERF_CTL:
3142         case MSR_AMD64_DC_CFG:
3143         case MSR_F15H_EX_CFG:
3144         /*
3145          * Intel Sandy Bridge CPUs must support the RAPL (running average power
3146          * limit) MSRs. Just return 0, as we do not want to expose the host
3147          * data here. Do not conditionalize this on CPUID, as KVM does not do
3148          * so for existing CPU-specific MSRs.
3149          */
3150         case MSR_RAPL_POWER_UNIT:
3151         case MSR_PP0_ENERGY_STATUS:     /* Power plane 0 (core) */
3152         case MSR_PP1_ENERGY_STATUS:     /* Power plane 1 (graphics uncore) */
3153         case MSR_PKG_ENERGY_STATUS:     /* Total package */
3154         case MSR_DRAM_ENERGY_STATUS:    /* DRAM controller */
3155                 msr_info->data = 0;
3156                 break;
3157         case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3158         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3159         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3160         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3161         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3162                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3163                         return kvm_pmu_get_msr(vcpu, msr_info);
3164                 msr_info->data = 0;
3165                 break;
3166         case MSR_IA32_UCODE_REV:
3167                 msr_info->data = vcpu->arch.microcode_version;
3168                 break;
3169         case MSR_IA32_ARCH_CAPABILITIES:
3170                 if (!msr_info->host_initiated &&
3171                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3172                         return 1;
3173                 msr_info->data = vcpu->arch.arch_capabilities;
3174                 break;
3175         case MSR_IA32_POWER_CTL:
3176                 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3177                 break;
3178         case MSR_IA32_TSC:
3179                 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
3180                 break;
3181         case MSR_MTRRcap:
3182         case 0x200 ... 0x2ff:
3183                 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3184         case 0xcd: /* fsb frequency */
3185                 msr_info->data = 3;
3186                 break;
3187                 /*
3188                  * MSR_EBC_FREQUENCY_ID
3189                  * Conservative value valid for even the basic CPU models.
3190                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3191                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3192                  * and 266MHz for model 3, or 4. Set Core Clock
3193                  * Frequency to System Bus Frequency Ratio to 1 (bits
3194                  * 31:24) even though these are only valid for CPU
3195                  * models > 2, however guests may end up dividing or
3196                  * multiplying by zero otherwise.
3197                  */
3198         case MSR_EBC_FREQUENCY_ID:
3199                 msr_info->data = 1 << 24;
3200                 break;
3201         case MSR_IA32_APICBASE:
3202                 msr_info->data = kvm_get_apic_base(vcpu);
3203                 break;
3204         case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3205                 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3206         case MSR_IA32_TSCDEADLINE:
3207                 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3208                 break;
3209         case MSR_IA32_TSC_ADJUST:
3210                 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3211                 break;
3212         case MSR_IA32_MISC_ENABLE:
3213                 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3214                 break;
3215         case MSR_IA32_SMBASE:
3216                 if (!msr_info->host_initiated)
3217                         return 1;
3218                 msr_info->data = vcpu->arch.smbase;
3219                 break;
3220         case MSR_SMI_COUNT:
3221                 msr_info->data = vcpu->arch.smi_count;
3222                 break;
3223         case MSR_IA32_PERF_STATUS:
3224                 /* TSC increment by tick */
3225                 msr_info->data = 1000ULL;
3226                 /* CPU multiplier */
3227                 msr_info->data |= (((uint64_t)4ULL) << 40);
3228                 break;
3229         case MSR_EFER:
3230                 msr_info->data = vcpu->arch.efer;
3231                 break;
3232         case MSR_KVM_WALL_CLOCK:
3233         case MSR_KVM_WALL_CLOCK_NEW:
3234                 msr_info->data = vcpu->kvm->arch.wall_clock;
3235                 break;
3236         case MSR_KVM_SYSTEM_TIME:
3237         case MSR_KVM_SYSTEM_TIME_NEW:
3238                 msr_info->data = vcpu->arch.time;
3239                 break;
3240         case MSR_KVM_ASYNC_PF_EN:
3241                 msr_info->data = vcpu->arch.apf.msr_en_val;
3242                 break;
3243         case MSR_KVM_ASYNC_PF_INT:
3244                 msr_info->data = vcpu->arch.apf.msr_int_val;
3245                 break;
3246         case MSR_KVM_ASYNC_PF_ACK:
3247                 msr_info->data = 0;
3248                 break;
3249         case MSR_KVM_STEAL_TIME:
3250                 msr_info->data = vcpu->arch.st.msr_val;
3251                 break;
3252         case MSR_KVM_PV_EOI_EN:
3253                 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3254                 break;
3255         case MSR_KVM_POLL_CONTROL:
3256                 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3257                 break;
3258         case MSR_IA32_P5_MC_ADDR:
3259         case MSR_IA32_P5_MC_TYPE:
3260         case MSR_IA32_MCG_CAP:
3261         case MSR_IA32_MCG_CTL:
3262         case MSR_IA32_MCG_STATUS:
3263         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3264                 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3265                                    msr_info->host_initiated);
3266         case MSR_IA32_XSS:
3267                 if (!msr_info->host_initiated &&
3268                     !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3269                         return 1;
3270                 msr_info->data = vcpu->arch.ia32_xss;
3271                 break;
3272         case MSR_K7_CLK_CTL:
3273                 /*
3274                  * Provide expected ramp-up count for K7. All other
3275                  * are set to zero, indicating minimum divisors for
3276                  * every field.
3277                  *
3278                  * This prevents guest kernels on AMD host with CPU
3279                  * type 6, model 8 and higher from exploding due to
3280                  * the rdmsr failing.
3281                  */
3282                 msr_info->data = 0x20000000;
3283                 break;
3284         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3285         case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3286         case HV_X64_MSR_SYNDBG_OPTIONS:
3287         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3288         case HV_X64_MSR_CRASH_CTL:
3289         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3290         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3291         case HV_X64_MSR_TSC_EMULATION_CONTROL:
3292         case HV_X64_MSR_TSC_EMULATION_STATUS:
3293                 return kvm_hv_get_msr_common(vcpu,
3294                                              msr_info->index, &msr_info->data,
3295                                              msr_info->host_initiated);
3296         case MSR_IA32_BBL_CR_CTL3:
3297                 /* This legacy MSR exists but isn't fully documented in current
3298                  * silicon.  It is however accessed by winxp in very narrow
3299                  * scenarios where it sets bit #19, itself documented as
3300                  * a "reserved" bit.  Best effort attempt to source coherent
3301                  * read data here should the balance of the register be
3302                  * interpreted by the guest:
3303                  *
3304                  * L2 cache control register 3: 64GB range, 256KB size,
3305                  * enabled, latency 0x1, configured
3306                  */
3307                 msr_info->data = 0xbe702111;
3308                 break;
3309         case MSR_AMD64_OSVW_ID_LENGTH:
3310                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3311                         return 1;
3312                 msr_info->data = vcpu->arch.osvw.length;
3313                 break;
3314         case MSR_AMD64_OSVW_STATUS:
3315                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3316                         return 1;
3317                 msr_info->data = vcpu->arch.osvw.status;
3318                 break;
3319         case MSR_PLATFORM_INFO:
3320                 if (!msr_info->host_initiated &&
3321                     !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3322                         return 1;
3323                 msr_info->data = vcpu->arch.msr_platform_info;
3324                 break;
3325         case MSR_MISC_FEATURES_ENABLES:
3326                 msr_info->data = vcpu->arch.msr_misc_features_enables;
3327                 break;
3328         case MSR_K7_HWCR:
3329                 msr_info->data = vcpu->arch.msr_hwcr;
3330                 break;
3331         default:
3332                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3333                         return kvm_pmu_get_msr(vcpu, msr_info);
3334                 if (!ignore_msrs) {
3335                         vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3336                                                msr_info->index);
3337                         return 1;
3338                 } else {
3339                         if (report_ignored_msrs)
3340                                 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3341                                         msr_info->index);
3342                         msr_info->data = 0;
3343                 }
3344                 break;
3345         }
3346         return 0;
3347 }
3348 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3349
3350 /*
3351  * Read or write a bunch of msrs. All parameters are kernel addresses.
3352  *
3353  * @return number of msrs set successfully.
3354  */
3355 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3356                     struct kvm_msr_entry *entries,
3357                     int (*do_msr)(struct kvm_vcpu *vcpu,
3358                                   unsigned index, u64 *data))
3359 {
3360         int i;
3361
3362         for (i = 0; i < msrs->nmsrs; ++i)
3363                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3364                         break;
3365
3366         return i;
3367 }
3368
3369 /*
3370  * Read or write a bunch of msrs. Parameters are user addresses.
3371  *
3372  * @return number of msrs set successfully.
3373  */
3374 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3375                   int (*do_msr)(struct kvm_vcpu *vcpu,
3376                                 unsigned index, u64 *data),
3377                   int writeback)
3378 {
3379         struct kvm_msrs msrs;
3380         struct kvm_msr_entry *entries;
3381         int r, n;
3382         unsigned size;
3383
3384         r = -EFAULT;
3385         if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3386                 goto out;
3387
3388         r = -E2BIG;
3389         if (msrs.nmsrs >= MAX_IO_MSRS)
3390                 goto out;
3391
3392         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3393         entries = memdup_user(user_msrs->entries, size);
3394         if (IS_ERR(entries)) {
3395                 r = PTR_ERR(entries);
3396                 goto out;
3397         }
3398
3399         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3400         if (r < 0)
3401                 goto out_free;
3402
3403         r = -EFAULT;
3404         if (writeback && copy_to_user(user_msrs->entries, entries, size))
3405                 goto out_free;
3406
3407         r = n;
3408
3409 out_free:
3410         kfree(entries);
3411 out:
3412         return r;
3413 }
3414
3415 static inline bool kvm_can_mwait_in_guest(void)
3416 {
3417         return boot_cpu_has(X86_FEATURE_MWAIT) &&
3418                 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3419                 boot_cpu_has(X86_FEATURE_ARAT);
3420 }
3421
3422 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3423 {
3424         int r = 0;
3425
3426         switch (ext) {
3427         case KVM_CAP_IRQCHIP:
3428         case KVM_CAP_HLT:
3429         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3430         case KVM_CAP_SET_TSS_ADDR:
3431         case KVM_CAP_EXT_CPUID:
3432         case KVM_CAP_EXT_EMUL_CPUID:
3433         case KVM_CAP_CLOCKSOURCE:
3434         case KVM_CAP_PIT:
3435         case KVM_CAP_NOP_IO_DELAY:
3436         case KVM_CAP_MP_STATE:
3437         case KVM_CAP_SYNC_MMU:
3438         case KVM_CAP_USER_NMI:
3439         case KVM_CAP_REINJECT_CONTROL:
3440         case KVM_CAP_IRQ_INJECT_STATUS:
3441         case KVM_CAP_IOEVENTFD:
3442         case KVM_CAP_IOEVENTFD_NO_LENGTH:
3443         case KVM_CAP_PIT2:
3444         case KVM_CAP_PIT_STATE2:
3445         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3446         case KVM_CAP_XEN_HVM:
3447         case KVM_CAP_VCPU_EVENTS:
3448         case KVM_CAP_HYPERV:
3449         case KVM_CAP_HYPERV_VAPIC:
3450         case KVM_CAP_HYPERV_SPIN:
3451         case KVM_CAP_HYPERV_SYNIC:
3452         case KVM_CAP_HYPERV_SYNIC2:
3453         case KVM_CAP_HYPERV_VP_INDEX:
3454         case KVM_CAP_HYPERV_EVENTFD:
3455         case KVM_CAP_HYPERV_TLBFLUSH:
3456         case KVM_CAP_HYPERV_SEND_IPI:
3457         case KVM_CAP_HYPERV_CPUID:
3458         case KVM_CAP_PCI_SEGMENT:
3459         case KVM_CAP_DEBUGREGS:
3460         case KVM_CAP_X86_ROBUST_SINGLESTEP:
3461         case KVM_CAP_XSAVE:
3462         case KVM_CAP_ASYNC_PF:
3463         case KVM_CAP_ASYNC_PF_INT:
3464         case KVM_CAP_GET_TSC_KHZ:
3465         case KVM_CAP_KVMCLOCK_CTRL:
3466         case KVM_CAP_READONLY_MEM:
3467         case KVM_CAP_HYPERV_TIME:
3468         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3469         case KVM_CAP_TSC_DEADLINE_TIMER:
3470         case KVM_CAP_DISABLE_QUIRKS:
3471         case KVM_CAP_SET_BOOT_CPU_ID:
3472         case KVM_CAP_SPLIT_IRQCHIP:
3473         case KVM_CAP_IMMEDIATE_EXIT:
3474         case KVM_CAP_PMU_EVENT_FILTER:
3475         case KVM_CAP_GET_MSR_FEATURES:
3476         case KVM_CAP_MSR_PLATFORM_INFO:
3477         case KVM_CAP_EXCEPTION_PAYLOAD:
3478         case KVM_CAP_SET_GUEST_DEBUG:
3479                 r = 1;
3480                 break;
3481         case KVM_CAP_SYNC_REGS:
3482                 r = KVM_SYNC_X86_VALID_FIELDS;
3483                 break;
3484         case KVM_CAP_ADJUST_CLOCK:
3485                 r = KVM_CLOCK_TSC_STABLE;
3486                 break;
3487         case KVM_CAP_X86_DISABLE_EXITS:
3488                 r |=  KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3489                       KVM_X86_DISABLE_EXITS_CSTATE;
3490                 if(kvm_can_mwait_in_guest())
3491                         r |= KVM_X86_DISABLE_EXITS_MWAIT;
3492                 break;
3493         case KVM_CAP_X86_SMM:
3494                 /* SMBASE is usually relocated above 1M on modern chipsets,
3495                  * and SMM handlers might indeed rely on 4G segment limits,
3496                  * so do not report SMM to be available if real mode is
3497                  * emulated via vm86 mode.  Still, do not go to great lengths
3498                  * to avoid userspace's usage of the feature, because it is a
3499                  * fringe case that is not enabled except via specific settings
3500                  * of the module parameters.
3501                  */
3502                 r = kvm_x86_ops.has_emulated_msr(MSR_IA32_SMBASE);
3503                 break;
3504         case KVM_CAP_VAPIC:
3505                 r = !kvm_x86_ops.cpu_has_accelerated_tpr();
3506                 break;
3507         case KVM_CAP_NR_VCPUS:
3508                 r = KVM_SOFT_MAX_VCPUS;
3509                 break;
3510         case KVM_CAP_MAX_VCPUS:
3511                 r = KVM_MAX_VCPUS;
3512                 break;
3513         case KVM_CAP_MAX_VCPU_ID:
3514                 r = KVM_MAX_VCPU_ID;
3515                 break;
3516         case KVM_CAP_PV_MMU:    /* obsolete */
3517                 r = 0;
3518                 break;
3519         case KVM_CAP_MCE:
3520                 r = KVM_MAX_MCE_BANKS;
3521                 break;
3522         case KVM_CAP_XCRS:
3523                 r = boot_cpu_has(X86_FEATURE_XSAVE);
3524                 break;
3525         case KVM_CAP_TSC_CONTROL:
3526                 r = kvm_has_tsc_control;
3527                 break;
3528         case KVM_CAP_X2APIC_API:
3529                 r = KVM_X2APIC_API_VALID_FLAGS;
3530                 break;
3531         case KVM_CAP_NESTED_STATE:
3532                 r = kvm_x86_ops.nested_ops->get_state ?
3533                         kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
3534                 break;
3535         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3536                 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3537                 break;
3538         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3539                 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
3540                 break;
3541         default:
3542                 break;
3543         }
3544         return r;
3545
3546 }
3547
3548 long kvm_arch_dev_ioctl(struct file *filp,
3549                         unsigned int ioctl, unsigned long arg)
3550 {
3551         void __user *argp = (void __user *)arg;
3552         long r;
3553
3554         switch (ioctl) {
3555         case KVM_GET_MSR_INDEX_LIST: {
3556                 struct kvm_msr_list __user *user_msr_list = argp;
3557                 struct kvm_msr_list msr_list;
3558                 unsigned n;
3559
3560                 r = -EFAULT;
3561                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3562                         goto out;
3563                 n = msr_list.nmsrs;
3564                 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3565                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3566                         goto out;
3567                 r = -E2BIG;
3568                 if (n < msr_list.nmsrs)
3569                         goto out;
3570                 r = -EFAULT;
3571                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3572                                  num_msrs_to_save * sizeof(u32)))
3573                         goto out;
3574                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3575                                  &emulated_msrs,
3576                                  num_emulated_msrs * sizeof(u32)))
3577                         goto out;
3578                 r = 0;
3579                 break;
3580         }
3581         case KVM_GET_SUPPORTED_CPUID:
3582         case KVM_GET_EMULATED_CPUID: {
3583                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3584                 struct kvm_cpuid2 cpuid;
3585
3586                 r = -EFAULT;
3587                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3588                         goto out;
3589
3590                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3591                                             ioctl);
3592                 if (r)
3593                         goto out;
3594
3595                 r = -EFAULT;
3596                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3597                         goto out;
3598                 r = 0;
3599                 break;
3600         }
3601         case KVM_X86_GET_MCE_CAP_SUPPORTED:
3602                 r = -EFAULT;
3603                 if (copy_to_user(argp, &kvm_mce_cap_supported,
3604                                  sizeof(kvm_mce_cap_supported)))
3605                         goto out;
3606                 r = 0;
3607                 break;
3608         case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3609                 struct kvm_msr_list __user *user_msr_list = argp;
3610                 struct kvm_msr_list msr_list;
3611                 unsigned int n;
3612
3613                 r = -EFAULT;
3614                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3615                         goto out;
3616                 n = msr_list.nmsrs;
3617                 msr_list.nmsrs = num_msr_based_features;
3618                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3619                         goto out;
3620                 r = -E2BIG;
3621                 if (n < msr_list.nmsrs)
3622                         goto out;
3623                 r = -EFAULT;
3624                 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3625                                  num_msr_based_features * sizeof(u32)))
3626                         goto out;
3627                 r = 0;
3628                 break;
3629         }
3630         case KVM_GET_MSRS:
3631                 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3632                 break;
3633         default:
3634                 r = -EINVAL;
3635                 break;
3636         }
3637 out:
3638         return r;
3639 }
3640
3641 static void wbinvd_ipi(void *garbage)
3642 {
3643         wbinvd();
3644 }
3645
3646 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3647 {
3648         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3649 }
3650
3651 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3652 {
3653         /* Address WBINVD may be executed by guest */
3654         if (need_emulate_wbinvd(vcpu)) {
3655                 if (kvm_x86_ops.has_wbinvd_exit())
3656                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3657                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3658                         smp_call_function_single(vcpu->cpu,
3659                                         wbinvd_ipi, NULL, 1);
3660         }
3661
3662         kvm_x86_ops.vcpu_load(vcpu, cpu);
3663
3664         /* Save host pkru register if supported */
3665         vcpu->arch.host_pkru = read_pkru();
3666
3667         /* Apply any externally detected TSC adjustments (due to suspend) */
3668         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3669                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3670                 vcpu->arch.tsc_offset_adjustment = 0;
3671                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3672         }
3673
3674         if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3675                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3676                                 rdtsc() - vcpu->arch.last_host_tsc;
3677                 if (tsc_delta < 0)
3678                         mark_tsc_unstable("KVM discovered backwards TSC");
3679
3680                 if (kvm_check_tsc_unstable()) {
3681                         u64 offset = kvm_compute_tsc_offset(vcpu,
3682                                                 vcpu->arch.last_guest_tsc);
3683                         kvm_vcpu_write_tsc_offset(vcpu, offset);
3684                         vcpu->arch.tsc_catchup = 1;
3685                 }
3686
3687                 if (kvm_lapic_hv_timer_in_use(vcpu))
3688                         kvm_lapic_restart_hv_timer(vcpu);
3689
3690                 /*
3691                  * On a host with synchronized TSC, there is no need to update
3692                  * kvmclock on vcpu->cpu migration
3693                  */
3694                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3695                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3696                 if (vcpu->cpu != cpu)
3697                         kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3698                 vcpu->cpu = cpu;
3699         }
3700
3701         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3702 }
3703
3704 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3705 {
3706         struct kvm_host_map map;
3707         struct kvm_steal_time *st;
3708
3709         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3710                 return;
3711
3712         if (vcpu->arch.st.preempted)
3713                 return;
3714
3715         if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3716                         &vcpu->arch.st.cache, true))
3717                 return;
3718
3719         st = map.hva +
3720                 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
3721
3722         st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
3723
3724         kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
3725 }
3726
3727 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3728 {
3729         int idx;
3730
3731         if (vcpu->preempted)
3732                 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu);
3733
3734         /*
3735          * Disable page faults because we're in atomic context here.
3736          * kvm_write_guest_offset_cached() would call might_fault()
3737          * that relies on pagefault_disable() to tell if there's a
3738          * bug. NOTE: the write to guest memory may not go through if
3739          * during postcopy live migration or if there's heavy guest
3740          * paging.
3741          */
3742         pagefault_disable();
3743         /*
3744          * kvm_memslots() will be called by
3745          * kvm_write_guest_offset_cached() so take the srcu lock.
3746          */
3747         idx = srcu_read_lock(&vcpu->kvm->srcu);
3748         kvm_steal_time_set_preempted(vcpu);
3749         srcu_read_unlock(&vcpu->kvm->srcu, idx);
3750         pagefault_enable();
3751         kvm_x86_ops.vcpu_put(vcpu);
3752         vcpu->arch.last_host_tsc = rdtsc();
3753         /*
3754          * If userspace has set any breakpoints or watchpoints, dr6 is restored
3755          * on every vmexit, but if not, we might have a stale dr6 from the
3756          * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3757          */
3758         set_debugreg(0, 6);
3759 }
3760
3761 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3762                                     struct kvm_lapic_state *s)
3763 {
3764         if (vcpu->arch.apicv_active)
3765                 kvm_x86_ops.sync_pir_to_irr(vcpu);
3766
3767         return kvm_apic_get_state(vcpu, s);
3768 }
3769
3770 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3771                                     struct kvm_lapic_state *s)
3772 {
3773         int r;
3774
3775         r = kvm_apic_set_state(vcpu, s);
3776         if (r)
3777                 return r;
3778         update_cr8_intercept(vcpu);
3779
3780         return 0;
3781 }
3782
3783 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3784 {
3785         return (!lapic_in_kernel(vcpu) ||
3786                 kvm_apic_accept_pic_intr(vcpu));
3787 }
3788
3789 /*
3790  * if userspace requested an interrupt window, check that the
3791  * interrupt window is open.
3792  *
3793  * No need to exit to userspace if we already have an interrupt queued.
3794  */
3795 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3796 {
3797         return kvm_arch_interrupt_allowed(vcpu) &&
3798                 !kvm_cpu_has_interrupt(vcpu) &&
3799                 !kvm_event_needs_reinjection(vcpu) &&
3800                 kvm_cpu_accept_dm_intr(vcpu);
3801 }
3802
3803 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3804                                     struct kvm_interrupt *irq)
3805 {
3806         if (irq->irq >= KVM_NR_INTERRUPTS)
3807                 return -EINVAL;
3808
3809         if (!irqchip_in_kernel(vcpu->kvm)) {
3810                 kvm_queue_interrupt(vcpu, irq->irq, false);
3811                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3812                 return 0;
3813         }
3814
3815         /*
3816          * With in-kernel LAPIC, we only use this to inject EXTINT, so
3817          * fail for in-kernel 8259.
3818          */
3819         if (pic_in_kernel(vcpu->kvm))
3820                 return -ENXIO;
3821
3822         if (vcpu->arch.pending_external_vector != -1)
3823                 return -EEXIST;
3824
3825         vcpu->arch.pending_external_vector = irq->irq;
3826         kvm_make_request(KVM_REQ_EVENT, vcpu);
3827         return 0;
3828 }
3829
3830 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3831 {
3832         kvm_inject_nmi(vcpu);
3833
3834         return 0;
3835 }
3836
3837 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3838 {
3839         kvm_make_request(KVM_REQ_SMI, vcpu);
3840
3841         return 0;
3842 }
3843
3844 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3845                                            struct kvm_tpr_access_ctl *tac)
3846 {
3847         if (tac->flags)
3848                 return -EINVAL;
3849         vcpu->arch.tpr_access_reporting = !!tac->enabled;
3850         return 0;
3851 }
3852
3853 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3854                                         u64 mcg_cap)
3855 {
3856         int r;
3857         unsigned bank_num = mcg_cap & 0xff, bank;
3858
3859         r = -EINVAL;
3860         if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
3861                 goto out;
3862         if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3863                 goto out;
3864         r = 0;
3865         vcpu->arch.mcg_cap = mcg_cap;
3866         /* Init IA32_MCG_CTL to all 1s */
3867         if (mcg_cap & MCG_CTL_P)
3868                 vcpu->arch.mcg_ctl = ~(u64)0;
3869         /* Init IA32_MCi_CTL to all 1s */
3870         for (bank = 0; bank < bank_num; bank++)
3871                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3872
3873         kvm_x86_ops.setup_mce(vcpu);
3874 out:
3875         return r;
3876 }
3877
3878 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3879                                       struct kvm_x86_mce *mce)
3880 {
3881         u64 mcg_cap = vcpu->arch.mcg_cap;
3882         unsigned bank_num = mcg_cap & 0xff;
3883         u64 *banks = vcpu->arch.mce_banks;
3884
3885         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3886                 return -EINVAL;
3887         /*
3888          * if IA32_MCG_CTL is not all 1s, the uncorrected error
3889          * reporting is disabled
3890          */
3891         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3892             vcpu->arch.mcg_ctl != ~(u64)0)
3893                 return 0;
3894         banks += 4 * mce->bank;
3895         /*
3896          * if IA32_MCi_CTL is not all 1s, the uncorrected error
3897          * reporting is disabled for the bank
3898          */
3899         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3900                 return 0;
3901         if (mce->status & MCI_STATUS_UC) {
3902                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3903                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3904                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3905                         return 0;
3906                 }
3907                 if (banks[1] & MCI_STATUS_VAL)
3908                         mce->status |= MCI_STATUS_OVER;
3909                 banks[2] = mce->addr;
3910                 banks[3] = mce->misc;
3911                 vcpu->arch.mcg_status = mce->mcg_status;
3912                 banks[1] = mce->status;
3913                 kvm_queue_exception(vcpu, MC_VECTOR);
3914         } else if (!(banks[1] & MCI_STATUS_VAL)
3915                    || !(banks[1] & MCI_STATUS_UC)) {
3916                 if (banks[1] & MCI_STATUS_VAL)
3917                         mce->status |= MCI_STATUS_OVER;
3918                 banks[2] = mce->addr;
3919                 banks[3] = mce->misc;
3920                 banks[1] = mce->status;
3921         } else
3922                 banks[1] |= MCI_STATUS_OVER;
3923         return 0;
3924 }
3925
3926 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3927                                                struct kvm_vcpu_events *events)
3928 {
3929         process_nmi(vcpu);
3930
3931         /*
3932          * In guest mode, payload delivery should be deferred,
3933          * so that the L1 hypervisor can intercept #PF before
3934          * CR2 is modified (or intercept #DB before DR6 is
3935          * modified under nVMX). Unless the per-VM capability,
3936          * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
3937          * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
3938          * opportunistically defer the exception payload, deliver it if the
3939          * capability hasn't been requested before processing a
3940          * KVM_GET_VCPU_EVENTS.
3941          */
3942         if (!vcpu->kvm->arch.exception_payload_enabled &&
3943             vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
3944                 kvm_deliver_exception_payload(vcpu);
3945
3946         /*
3947          * The API doesn't provide the instruction length for software
3948          * exceptions, so don't report them. As long as the guest RIP
3949          * isn't advanced, we should expect to encounter the exception
3950          * again.
3951          */
3952         if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3953                 events->exception.injected = 0;
3954                 events->exception.pending = 0;
3955         } else {
3956                 events->exception.injected = vcpu->arch.exception.injected;
3957                 events->exception.pending = vcpu->arch.exception.pending;
3958                 /*
3959                  * For ABI compatibility, deliberately conflate
3960                  * pending and injected exceptions when
3961                  * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3962                  */
3963                 if (!vcpu->kvm->arch.exception_payload_enabled)
3964                         events->exception.injected |=
3965                                 vcpu->arch.exception.pending;
3966         }
3967         events->exception.nr = vcpu->arch.exception.nr;
3968         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3969         events->exception.error_code = vcpu->arch.exception.error_code;
3970         events->exception_has_payload = vcpu->arch.exception.has_payload;
3971         events->exception_payload = vcpu->arch.exception.payload;
3972
3973         events->interrupt.injected =
3974                 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3975         events->interrupt.nr = vcpu->arch.interrupt.nr;
3976         events->interrupt.soft = 0;
3977         events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
3978
3979         events->nmi.injected = vcpu->arch.nmi_injected;
3980         events->nmi.pending = vcpu->arch.nmi_pending != 0;
3981         events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu);
3982         events->nmi.pad = 0;
3983
3984         events->sipi_vector = 0; /* never valid when reporting to user space */
3985
3986         events->smi.smm = is_smm(vcpu);
3987         events->smi.pending = vcpu->arch.smi_pending;
3988         events->smi.smm_inside_nmi =
3989                 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3990         events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3991
3992         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3993                          | KVM_VCPUEVENT_VALID_SHADOW
3994                          | KVM_VCPUEVENT_VALID_SMM);
3995         if (vcpu->kvm->arch.exception_payload_enabled)
3996                 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3997
3998         memset(&events->reserved, 0, sizeof(events->reserved));
3999 }
4000
4001 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
4002
4003 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4004                                               struct kvm_vcpu_events *events)
4005 {
4006         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4007                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4008                               | KVM_VCPUEVENT_VALID_SHADOW
4009                               | KVM_VCPUEVENT_VALID_SMM
4010                               | KVM_VCPUEVENT_VALID_PAYLOAD))
4011                 return -EINVAL;
4012
4013         if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4014                 if (!vcpu->kvm->arch.exception_payload_enabled)
4015                         return -EINVAL;
4016                 if (events->exception.pending)
4017                         events->exception.injected = 0;
4018                 else
4019                         events->exception_has_payload = 0;
4020         } else {
4021                 events->exception.pending = 0;
4022                 events->exception_has_payload = 0;
4023         }
4024
4025         if ((events->exception.injected || events->exception.pending) &&
4026             (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4027                 return -EINVAL;
4028
4029         /* INITs are latched while in SMM */
4030         if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4031             (events->smi.smm || events->smi.pending) &&
4032             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4033                 return -EINVAL;
4034
4035         process_nmi(vcpu);
4036         vcpu->arch.exception.injected = events->exception.injected;
4037         vcpu->arch.exception.pending = events->exception.pending;
4038         vcpu->arch.exception.nr = events->exception.nr;
4039         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4040         vcpu->arch.exception.error_code = events->exception.error_code;
4041         vcpu->arch.exception.has_payload = events->exception_has_payload;
4042         vcpu->arch.exception.payload = events->exception_payload;
4043
4044         vcpu->arch.interrupt.injected = events->interrupt.injected;
4045         vcpu->arch.interrupt.nr = events->interrupt.nr;
4046         vcpu->arch.interrupt.soft = events->interrupt.soft;
4047         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4048                 kvm_x86_ops.set_interrupt_shadow(vcpu,
4049                                                   events->interrupt.shadow);
4050
4051         vcpu->arch.nmi_injected = events->nmi.injected;
4052         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4053                 vcpu->arch.nmi_pending = events->nmi.pending;
4054         kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked);
4055
4056         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4057             lapic_in_kernel(vcpu))
4058                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4059
4060         if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4061                 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4062                         if (events->smi.smm)
4063                                 vcpu->arch.hflags |= HF_SMM_MASK;
4064                         else
4065                                 vcpu->arch.hflags &= ~HF_SMM_MASK;
4066                         kvm_smm_changed(vcpu);
4067                 }
4068
4069                 vcpu->arch.smi_pending = events->smi.pending;
4070
4071                 if (events->smi.smm) {
4072                         if (events->smi.smm_inside_nmi)
4073                                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4074                         else
4075                                 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4076                 }
4077
4078                 if (lapic_in_kernel(vcpu)) {
4079                         if (events->smi.latched_init)
4080                                 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4081                         else
4082                                 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4083                 }
4084         }
4085
4086         kvm_make_request(KVM_REQ_EVENT, vcpu);
4087
4088         return 0;
4089 }
4090
4091 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4092                                              struct kvm_debugregs *dbgregs)
4093 {
4094         unsigned long val;
4095
4096         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4097         kvm_get_dr(vcpu, 6, &val);
4098         dbgregs->dr6 = val;
4099         dbgregs->dr7 = vcpu->arch.dr7;
4100         dbgregs->flags = 0;
4101         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4102 }
4103
4104 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4105                                             struct kvm_debugregs *dbgregs)
4106 {
4107         if (dbgregs->flags)
4108                 return -EINVAL;
4109
4110         if (dbgregs->dr6 & ~0xffffffffull)
4111                 return -EINVAL;
4112         if (dbgregs->dr7 & ~0xffffffffull)
4113                 return -EINVAL;
4114
4115         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4116         kvm_update_dr0123(vcpu);
4117         vcpu->arch.dr6 = dbgregs->dr6;
4118         vcpu->arch.dr7 = dbgregs->dr7;
4119         kvm_update_dr7(vcpu);
4120
4121         return 0;
4122 }
4123
4124 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4125
4126 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4127 {
4128         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4129         u64 xstate_bv = xsave->header.xfeatures;
4130         u64 valid;
4131
4132         /*
4133          * Copy legacy XSAVE area, to avoid complications with CPUID
4134          * leaves 0 and 1 in the loop below.
4135          */
4136         memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4137
4138         /* Set XSTATE_BV */
4139         xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4140         *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4141
4142         /*
4143          * Copy each region from the possibly compacted offset to the
4144          * non-compacted offset.
4145          */
4146         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4147         while (valid) {
4148                 u64 xfeature_mask = valid & -valid;
4149                 int xfeature_nr = fls64(xfeature_mask) - 1;
4150                 void *src = get_xsave_addr(xsave, xfeature_nr);
4151
4152                 if (src) {
4153                         u32 size, offset, ecx, edx;
4154                         cpuid_count(XSTATE_CPUID, xfeature_nr,
4155                                     &size, &offset, &ecx, &edx);
4156                         if (xfeature_nr == XFEATURE_PKRU)
4157                                 memcpy(dest + offset, &vcpu->arch.pkru,
4158                                        sizeof(vcpu->arch.pkru));
4159                         else
4160                                 memcpy(dest + offset, src, size);
4161
4162                 }
4163
4164                 valid -= xfeature_mask;
4165         }
4166 }
4167
4168 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4169 {
4170         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4171         u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4172         u64 valid;
4173
4174         /*
4175          * Copy legacy XSAVE area, to avoid complications with CPUID
4176          * leaves 0 and 1 in the loop below.
4177          */
4178         memcpy(xsave, src, XSAVE_HDR_OFFSET);
4179
4180         /* Set XSTATE_BV and possibly XCOMP_BV.  */
4181         xsave->header.xfeatures = xstate_bv;
4182         if (boot_cpu_has(X86_FEATURE_XSAVES))
4183                 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4184
4185         /*
4186          * Copy each region from the non-compacted offset to the
4187          * possibly compacted offset.
4188          */
4189         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4190         while (valid) {
4191                 u64 xfeature_mask = valid & -valid;
4192                 int xfeature_nr = fls64(xfeature_mask) - 1;
4193                 void *dest = get_xsave_addr(xsave, xfeature_nr);
4194
4195                 if (dest) {
4196                         u32 size, offset, ecx, edx;
4197                         cpuid_count(XSTATE_CPUID, xfeature_nr,
4198                                     &size, &offset, &ecx, &edx);
4199                         if (xfeature_nr == XFEATURE_PKRU)
4200                                 memcpy(&vcpu->arch.pkru, src + offset,
4201                                        sizeof(vcpu->arch.pkru));
4202                         else
4203                                 memcpy(dest, src + offset, size);
4204                 }
4205
4206                 valid -= xfeature_mask;
4207         }
4208 }
4209
4210 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4211                                          struct kvm_xsave *guest_xsave)
4212 {
4213         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4214                 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4215                 fill_xsave((u8 *) guest_xsave->region, vcpu);
4216         } else {
4217                 memcpy(guest_xsave->region,
4218                         &vcpu->arch.guest_fpu->state.fxsave,
4219                         sizeof(struct fxregs_state));
4220                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4221                         XFEATURE_MASK_FPSSE;
4222         }
4223 }
4224
4225 #define XSAVE_MXCSR_OFFSET 24
4226
4227 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4228                                         struct kvm_xsave *guest_xsave)
4229 {
4230         u64 xstate_bv =
4231                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4232         u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4233
4234         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4235                 /*
4236                  * Here we allow setting states that are not present in
4237                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
4238                  * with old userspace.
4239                  */
4240                 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4241                         return -EINVAL;
4242                 load_xsave(vcpu, (u8 *)guest_xsave->region);
4243         } else {
4244                 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4245                         mxcsr & ~mxcsr_feature_mask)
4246                         return -EINVAL;
4247                 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4248                         guest_xsave->region, sizeof(struct fxregs_state));
4249         }
4250         return 0;
4251 }
4252
4253 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4254                                         struct kvm_xcrs *guest_xcrs)
4255 {
4256         if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4257                 guest_xcrs->nr_xcrs = 0;
4258                 return;
4259         }
4260
4261         guest_xcrs->nr_xcrs = 1;
4262         guest_xcrs->flags = 0;
4263         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4264         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4265 }
4266
4267 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4268                                        struct kvm_xcrs *guest_xcrs)
4269 {
4270         int i, r = 0;
4271
4272         if (!boot_cpu_has(X86_FEATURE_XSAVE))
4273                 return -EINVAL;
4274
4275         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4276                 return -EINVAL;
4277
4278         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4279                 /* Only support XCR0 currently */
4280                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4281                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4282                                 guest_xcrs->xcrs[i].value);
4283                         break;
4284                 }
4285         if (r)
4286                 r = -EINVAL;
4287         return r;
4288 }
4289
4290 /*
4291  * kvm_set_guest_paused() indicates to the guest kernel that it has been
4292  * stopped by the hypervisor.  This function will be called from the host only.
4293  * EINVAL is returned when the host attempts to set the flag for a guest that
4294  * does not support pv clocks.
4295  */
4296 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4297 {
4298         if (!vcpu->arch.pv_time_enabled)
4299                 return -EINVAL;
4300         vcpu->arch.pvclock_set_guest_stopped_request = true;
4301         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4302         return 0;
4303 }
4304
4305 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4306                                      struct kvm_enable_cap *cap)
4307 {
4308         int r;
4309         uint16_t vmcs_version;
4310         void __user *user_ptr;
4311
4312         if (cap->flags)
4313                 return -EINVAL;
4314
4315         switch (cap->cap) {
4316         case KVM_CAP_HYPERV_SYNIC2:
4317                 if (cap->args[0])
4318                         return -EINVAL;
4319                 /* fall through */
4320
4321         case KVM_CAP_HYPERV_SYNIC:
4322                 if (!irqchip_in_kernel(vcpu->kvm))
4323                         return -EINVAL;
4324                 return kvm_hv_activate_synic(vcpu, cap->cap ==
4325                                              KVM_CAP_HYPERV_SYNIC2);
4326         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4327                 if (!kvm_x86_ops.nested_ops->enable_evmcs)
4328                         return -ENOTTY;
4329                 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
4330                 if (!r) {
4331                         user_ptr = (void __user *)(uintptr_t)cap->args[0];
4332                         if (copy_to_user(user_ptr, &vmcs_version,
4333                                          sizeof(vmcs_version)))
4334                                 r = -EFAULT;
4335                 }
4336                 return r;
4337         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4338                 if (!kvm_x86_ops.enable_direct_tlbflush)
4339                         return -ENOTTY;
4340
4341                 return kvm_x86_ops.enable_direct_tlbflush(vcpu);
4342
4343         default:
4344                 return -EINVAL;
4345         }
4346 }
4347
4348 long kvm_arch_vcpu_ioctl(struct file *filp,
4349                          unsigned int ioctl, unsigned long arg)
4350 {
4351         struct kvm_vcpu *vcpu = filp->private_data;
4352         void __user *argp = (void __user *)arg;
4353         int r;
4354         union {
4355                 struct kvm_lapic_state *lapic;
4356                 struct kvm_xsave *xsave;
4357                 struct kvm_xcrs *xcrs;
4358                 void *buffer;
4359         } u;
4360
4361         vcpu_load(vcpu);
4362
4363         u.buffer = NULL;
4364         switch (ioctl) {
4365         case KVM_GET_LAPIC: {
4366                 r = -EINVAL;
4367                 if (!lapic_in_kernel(vcpu))
4368                         goto out;
4369                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4370                                 GFP_KERNEL_ACCOUNT);
4371
4372                 r = -ENOMEM;
4373                 if (!u.lapic)
4374                         goto out;
4375                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4376                 if (r)
4377                         goto out;
4378                 r = -EFAULT;
4379                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4380                         goto out;
4381                 r = 0;
4382                 break;
4383         }
4384         case KVM_SET_LAPIC: {
4385                 r = -EINVAL;
4386                 if (!lapic_in_kernel(vcpu))
4387                         goto out;
4388                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4389                 if (IS_ERR(u.lapic)) {
4390                         r = PTR_ERR(u.lapic);
4391                         goto out_nofree;
4392                 }
4393
4394                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4395                 break;
4396         }
4397         case KVM_INTERRUPT: {
4398                 struct kvm_interrupt irq;
4399
4400                 r = -EFAULT;
4401                 if (copy_from_user(&irq, argp, sizeof(irq)))
4402                         goto out;
4403                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4404                 break;
4405         }
4406         case KVM_NMI: {
4407                 r = kvm_vcpu_ioctl_nmi(vcpu);
4408                 break;
4409         }
4410         case KVM_SMI: {
4411                 r = kvm_vcpu_ioctl_smi(vcpu);
4412                 break;
4413         }
4414         case KVM_SET_CPUID: {
4415                 struct kvm_cpuid __user *cpuid_arg = argp;
4416                 struct kvm_cpuid cpuid;
4417
4418                 r = -EFAULT;
4419                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4420                         goto out;
4421                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4422                 break;
4423         }
4424         case KVM_SET_CPUID2: {
4425                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4426                 struct kvm_cpuid2 cpuid;
4427
4428                 r = -EFAULT;
4429                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4430                         goto out;
4431                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4432                                               cpuid_arg->entries);
4433                 break;
4434         }
4435         case KVM_GET_CPUID2: {
4436                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4437                 struct kvm_cpuid2 cpuid;
4438
4439                 r = -EFAULT;
4440                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4441                         goto out;
4442                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4443                                               cpuid_arg->entries);
4444                 if (r)
4445                         goto out;
4446                 r = -EFAULT;
4447                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4448                         goto out;
4449                 r = 0;
4450                 break;
4451         }
4452         case KVM_GET_MSRS: {
4453                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4454                 r = msr_io(vcpu, argp, do_get_msr, 1);
4455                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4456                 break;
4457         }
4458         case KVM_SET_MSRS: {
4459                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4460                 r = msr_io(vcpu, argp, do_set_msr, 0);
4461                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4462                 break;
4463         }
4464         case KVM_TPR_ACCESS_REPORTING: {
4465                 struct kvm_tpr_access_ctl tac;
4466
4467                 r = -EFAULT;
4468                 if (copy_from_user(&tac, argp, sizeof(tac)))
4469                         goto out;
4470                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4471                 if (r)
4472                         goto out;
4473                 r = -EFAULT;
4474                 if (copy_to_user(argp, &tac, sizeof(tac)))
4475                         goto out;
4476                 r = 0;
4477                 break;
4478         };
4479         case KVM_SET_VAPIC_ADDR: {
4480                 struct kvm_vapic_addr va;
4481                 int idx;
4482
4483                 r = -EINVAL;
4484                 if (!lapic_in_kernel(vcpu))
4485                         goto out;
4486                 r = -EFAULT;
4487                 if (copy_from_user(&va, argp, sizeof(va)))
4488                         goto out;
4489                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4490                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4491                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4492                 break;
4493         }
4494         case KVM_X86_SETUP_MCE: {
4495                 u64 mcg_cap;
4496
4497                 r = -EFAULT;
4498                 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4499                         goto out;
4500                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4501                 break;
4502         }
4503         case KVM_X86_SET_MCE: {
4504                 struct kvm_x86_mce mce;
4505
4506                 r = -EFAULT;
4507                 if (copy_from_user(&mce, argp, sizeof(mce)))
4508                         goto out;
4509                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4510                 break;
4511         }
4512         case KVM_GET_VCPU_EVENTS: {
4513                 struct kvm_vcpu_events events;
4514
4515                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4516
4517                 r = -EFAULT;
4518                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4519                         break;
4520                 r = 0;
4521                 break;
4522         }
4523         case KVM_SET_VCPU_EVENTS: {
4524                 struct kvm_vcpu_events events;
4525
4526                 r = -EFAULT;
4527                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4528                         break;
4529
4530                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4531                 break;
4532         }
4533         case KVM_GET_DEBUGREGS: {
4534                 struct kvm_debugregs dbgregs;
4535
4536                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4537
4538                 r = -EFAULT;
4539                 if (copy_to_user(argp, &dbgregs,
4540                                  sizeof(struct kvm_debugregs)))
4541                         break;
4542                 r = 0;
4543                 break;
4544         }
4545         case KVM_SET_DEBUGREGS: {
4546                 struct kvm_debugregs dbgregs;
4547
4548                 r = -EFAULT;
4549                 if (copy_from_user(&dbgregs, argp,
4550                                    sizeof(struct kvm_debugregs)))
4551                         break;
4552
4553                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4554                 break;
4555         }
4556         case KVM_GET_XSAVE: {
4557                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4558                 r = -ENOMEM;
4559                 if (!u.xsave)
4560                         break;
4561
4562                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4563
4564                 r = -EFAULT;
4565                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4566                         break;
4567                 r = 0;
4568                 break;
4569         }
4570         case KVM_SET_XSAVE: {
4571                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4572                 if (IS_ERR(u.xsave)) {
4573                         r = PTR_ERR(u.xsave);
4574                         goto out_nofree;
4575                 }
4576
4577                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4578                 break;
4579         }
4580         case KVM_GET_XCRS: {
4581                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4582                 r = -ENOMEM;
4583                 if (!u.xcrs)
4584                         break;
4585
4586                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4587
4588                 r = -EFAULT;
4589                 if (copy_to_user(argp, u.xcrs,
4590                                  sizeof(struct kvm_xcrs)))
4591                         break;
4592                 r = 0;
4593                 break;
4594         }
4595         case KVM_SET_XCRS: {
4596                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4597                 if (IS_ERR(u.xcrs)) {
4598                         r = PTR_ERR(u.xcrs);
4599                         goto out_nofree;
4600                 }
4601
4602                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4603                 break;
4604         }
4605         case KVM_SET_TSC_KHZ: {
4606                 u32 user_tsc_khz;
4607
4608                 r = -EINVAL;
4609                 user_tsc_khz = (u32)arg;
4610
4611                 if (kvm_has_tsc_control &&
4612                     user_tsc_khz >= kvm_max_guest_tsc_khz)
4613                         goto out;
4614
4615                 if (user_tsc_khz == 0)
4616                         user_tsc_khz = tsc_khz;
4617
4618                 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4619                         r = 0;
4620
4621                 goto out;
4622         }
4623         case KVM_GET_TSC_KHZ: {
4624                 r = vcpu->arch.virtual_tsc_khz;
4625                 goto out;
4626         }
4627         case KVM_KVMCLOCK_CTRL: {
4628                 r = kvm_set_guest_paused(vcpu);
4629                 goto out;
4630         }
4631         case KVM_ENABLE_CAP: {
4632                 struct kvm_enable_cap cap;
4633
4634                 r = -EFAULT;
4635                 if (copy_from_user(&cap, argp, sizeof(cap)))
4636                         goto out;
4637                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4638                 break;
4639         }
4640         case KVM_GET_NESTED_STATE: {
4641                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4642                 u32 user_data_size;
4643
4644                 r = -EINVAL;
4645                 if (!kvm_x86_ops.nested_ops->get_state)
4646                         break;
4647
4648                 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4649                 r = -EFAULT;
4650                 if (get_user(user_data_size, &user_kvm_nested_state->size))
4651                         break;
4652
4653                 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
4654                                                      user_data_size);
4655                 if (r < 0)
4656                         break;
4657
4658                 if (r > user_data_size) {
4659                         if (put_user(r, &user_kvm_nested_state->size))
4660                                 r = -EFAULT;
4661                         else
4662                                 r = -E2BIG;
4663                         break;
4664                 }
4665
4666                 r = 0;
4667                 break;
4668         }
4669         case KVM_SET_NESTED_STATE: {
4670                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4671                 struct kvm_nested_state kvm_state;
4672                 int idx;
4673
4674                 r = -EINVAL;
4675                 if (!kvm_x86_ops.nested_ops->set_state)
4676                         break;
4677
4678                 r = -EFAULT;
4679                 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4680                         break;
4681
4682                 r = -EINVAL;
4683                 if (kvm_state.size < sizeof(kvm_state))
4684                         break;
4685
4686                 if (kvm_state.flags &
4687                     ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4688                       | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
4689                       | KVM_STATE_NESTED_GIF_SET))
4690                         break;
4691
4692                 /* nested_run_pending implies guest_mode.  */
4693                 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4694                     && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4695                         break;
4696
4697                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4698                 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
4699                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4700                 break;
4701         }
4702         case KVM_GET_SUPPORTED_HV_CPUID: {
4703                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4704                 struct kvm_cpuid2 cpuid;
4705
4706                 r = -EFAULT;
4707                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4708                         goto out;
4709
4710                 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4711                                                 cpuid_arg->entries);
4712                 if (r)
4713                         goto out;
4714
4715                 r = -EFAULT;
4716                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4717                         goto out;
4718                 r = 0;
4719                 break;
4720         }
4721         default:
4722                 r = -EINVAL;
4723         }
4724 out:
4725         kfree(u.buffer);
4726 out_nofree:
4727         vcpu_put(vcpu);
4728         return r;
4729 }
4730
4731 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4732 {
4733         return VM_FAULT_SIGBUS;
4734 }
4735
4736 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4737 {
4738         int ret;
4739
4740         if (addr > (unsigned int)(-3 * PAGE_SIZE))
4741                 return -EINVAL;
4742         ret = kvm_x86_ops.set_tss_addr(kvm, addr);
4743         return ret;
4744 }
4745
4746 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4747                                               u64 ident_addr)
4748 {
4749         return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr);
4750 }
4751
4752 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4753                                          unsigned long kvm_nr_mmu_pages)
4754 {
4755         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4756                 return -EINVAL;
4757
4758         mutex_lock(&kvm->slots_lock);
4759
4760         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4761         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4762
4763         mutex_unlock(&kvm->slots_lock);
4764         return 0;
4765 }
4766
4767 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4768 {
4769         return kvm->arch.n_max_mmu_pages;
4770 }
4771
4772 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4773 {
4774         struct kvm_pic *pic = kvm->arch.vpic;
4775         int r;
4776
4777         r = 0;
4778         switch (chip->chip_id) {
4779         case KVM_IRQCHIP_PIC_MASTER:
4780                 memcpy(&chip->chip.pic, &pic->pics[0],
4781                         sizeof(struct kvm_pic_state));
4782                 break;
4783         case KVM_IRQCHIP_PIC_SLAVE:
4784                 memcpy(&chip->chip.pic, &pic->pics[1],
4785                         sizeof(struct kvm_pic_state));
4786                 break;
4787         case KVM_IRQCHIP_IOAPIC:
4788                 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4789                 break;
4790         default:
4791                 r = -EINVAL;
4792                 break;
4793         }
4794         return r;
4795 }
4796
4797 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4798 {
4799         struct kvm_pic *pic = kvm->arch.vpic;
4800         int r;
4801
4802         r = 0;
4803         switch (chip->chip_id) {
4804         case KVM_IRQCHIP_PIC_MASTER:
4805                 spin_lock(&pic->lock);
4806                 memcpy(&pic->pics[0], &chip->chip.pic,
4807                         sizeof(struct kvm_pic_state));
4808                 spin_unlock(&pic->lock);
4809                 break;
4810         case KVM_IRQCHIP_PIC_SLAVE:
4811                 spin_lock(&pic->lock);
4812                 memcpy(&pic->pics[1], &chip->chip.pic,
4813                         sizeof(struct kvm_pic_state));
4814                 spin_unlock(&pic->lock);
4815                 break;
4816         case KVM_IRQCHIP_IOAPIC:
4817                 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4818                 break;
4819         default:
4820                 r = -EINVAL;
4821                 break;
4822         }
4823         kvm_pic_update_irq(pic);
4824         return r;
4825 }
4826
4827 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4828 {
4829         struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4830
4831         BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4832
4833         mutex_lock(&kps->lock);
4834         memcpy(ps, &kps->channels, sizeof(*ps));
4835         mutex_unlock(&kps->lock);
4836         return 0;
4837 }
4838
4839 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4840 {
4841         int i;
4842         struct kvm_pit *pit = kvm->arch.vpit;
4843
4844         mutex_lock(&pit->pit_state.lock);
4845         memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4846         for (i = 0; i < 3; i++)
4847                 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4848         mutex_unlock(&pit->pit_state.lock);
4849         return 0;
4850 }
4851
4852 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4853 {
4854         mutex_lock(&kvm->arch.vpit->pit_state.lock);
4855         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4856                 sizeof(ps->channels));
4857         ps->flags = kvm->arch.vpit->pit_state.flags;
4858         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4859         memset(&ps->reserved, 0, sizeof(ps->reserved));
4860         return 0;
4861 }
4862
4863 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4864 {
4865         int start = 0;
4866         int i;
4867         u32 prev_legacy, cur_legacy;
4868         struct kvm_pit *pit = kvm->arch.vpit;
4869
4870         mutex_lock(&pit->pit_state.lock);
4871         prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4872         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4873         if (!prev_legacy && cur_legacy)
4874                 start = 1;
4875         memcpy(&pit->pit_state.channels, &ps->channels,
4876                sizeof(pit->pit_state.channels));
4877         pit->pit_state.flags = ps->flags;
4878         for (i = 0; i < 3; i++)
4879                 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4880                                    start && i == 0);
4881         mutex_unlock(&pit->pit_state.lock);
4882         return 0;
4883 }
4884
4885 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4886                                  struct kvm_reinject_control *control)
4887 {
4888         struct kvm_pit *pit = kvm->arch.vpit;
4889
4890         /* pit->pit_state.lock was overloaded to prevent userspace from getting
4891          * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4892          * ioctls in parallel.  Use a separate lock if that ioctl isn't rare.
4893          */
4894         mutex_lock(&pit->pit_state.lock);
4895         kvm_pit_set_reinject(pit, control->pit_reinject);
4896         mutex_unlock(&pit->pit_state.lock);
4897
4898         return 0;
4899 }
4900
4901 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
4902 {
4903         /*
4904          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4905          */
4906         if (kvm_x86_ops.flush_log_dirty)
4907                 kvm_x86_ops.flush_log_dirty(kvm);
4908 }
4909
4910 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4911                         bool line_status)
4912 {
4913         if (!irqchip_in_kernel(kvm))
4914                 return -ENXIO;
4915
4916         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4917                                         irq_event->irq, irq_event->level,
4918                                         line_status);
4919         return 0;
4920 }
4921
4922 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4923                             struct kvm_enable_cap *cap)
4924 {
4925         int r;
4926
4927         if (cap->flags)
4928                 return -EINVAL;
4929
4930         switch (cap->cap) {
4931         case KVM_CAP_DISABLE_QUIRKS:
4932                 kvm->arch.disabled_quirks = cap->args[0];
4933                 r = 0;
4934                 break;
4935         case KVM_CAP_SPLIT_IRQCHIP: {
4936                 mutex_lock(&kvm->lock);
4937                 r = -EINVAL;
4938                 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4939                         goto split_irqchip_unlock;
4940                 r = -EEXIST;
4941                 if (irqchip_in_kernel(kvm))
4942                         goto split_irqchip_unlock;
4943                 if (kvm->created_vcpus)
4944                         goto split_irqchip_unlock;
4945                 r = kvm_setup_empty_irq_routing(kvm);
4946                 if (r)
4947                         goto split_irqchip_unlock;
4948                 /* Pairs with irqchip_in_kernel. */
4949                 smp_wmb();
4950                 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4951                 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4952                 r = 0;
4953 split_irqchip_unlock:
4954                 mutex_unlock(&kvm->lock);
4955                 break;
4956         }
4957         case KVM_CAP_X2APIC_API:
4958                 r = -EINVAL;
4959                 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4960                         break;
4961
4962                 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4963                         kvm->arch.x2apic_format = true;
4964                 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4965                         kvm->arch.x2apic_broadcast_quirk_disabled = true;
4966
4967                 r = 0;
4968                 break;
4969         case KVM_CAP_X86_DISABLE_EXITS:
4970                 r = -EINVAL;
4971                 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4972                         break;
4973
4974                 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4975                         kvm_can_mwait_in_guest())
4976                         kvm->arch.mwait_in_guest = true;
4977                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4978                         kvm->arch.hlt_in_guest = true;
4979                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4980                         kvm->arch.pause_in_guest = true;
4981                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4982                         kvm->arch.cstate_in_guest = true;
4983                 r = 0;
4984                 break;
4985         case KVM_CAP_MSR_PLATFORM_INFO:
4986                 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4987                 r = 0;
4988                 break;
4989         case KVM_CAP_EXCEPTION_PAYLOAD:
4990                 kvm->arch.exception_payload_enabled = cap->args[0];
4991                 r = 0;
4992                 break;
4993         default:
4994                 r = -EINVAL;
4995                 break;
4996         }
4997         return r;
4998 }
4999
5000 long kvm_arch_vm_ioctl(struct file *filp,
5001                        unsigned int ioctl, unsigned long arg)
5002 {
5003         struct kvm *kvm = filp->private_data;
5004         void __user *argp = (void __user *)arg;
5005         int r = -ENOTTY;
5006         /*
5007          * This union makes it completely explicit to gcc-3.x
5008          * that these two variables' stack usage should be
5009          * combined, not added together.
5010          */
5011         union {
5012                 struct kvm_pit_state ps;
5013                 struct kvm_pit_state2 ps2;
5014                 struct kvm_pit_config pit_config;
5015         } u;
5016
5017         switch (ioctl) {
5018         case KVM_SET_TSS_ADDR:
5019                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
5020                 break;
5021         case KVM_SET_IDENTITY_MAP_ADDR: {
5022                 u64 ident_addr;
5023
5024                 mutex_lock(&kvm->lock);
5025                 r = -EINVAL;
5026                 if (kvm->created_vcpus)
5027                         goto set_identity_unlock;
5028                 r = -EFAULT;
5029                 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
5030                         goto set_identity_unlock;
5031                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
5032 set_identity_unlock:
5033                 mutex_unlock(&kvm->lock);
5034                 break;
5035         }
5036         case KVM_SET_NR_MMU_PAGES:
5037                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
5038                 break;
5039         case KVM_GET_NR_MMU_PAGES:
5040                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
5041                 break;
5042         case KVM_CREATE_IRQCHIP: {
5043                 mutex_lock(&kvm->lock);
5044
5045                 r = -EEXIST;
5046                 if (irqchip_in_kernel(kvm))
5047                         goto create_irqchip_unlock;
5048
5049                 r = -EINVAL;
5050                 if (kvm->created_vcpus)
5051                         goto create_irqchip_unlock;
5052
5053                 r = kvm_pic_init(kvm);
5054                 if (r)
5055                         goto create_irqchip_unlock;
5056
5057                 r = kvm_ioapic_init(kvm);
5058                 if (r) {
5059                         kvm_pic_destroy(kvm);
5060                         goto create_irqchip_unlock;
5061                 }
5062
5063                 r = kvm_setup_default_irq_routing(kvm);
5064                 if (r) {
5065                         kvm_ioapic_destroy(kvm);
5066                         kvm_pic_destroy(kvm);
5067                         goto create_irqchip_unlock;
5068                 }
5069                 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
5070                 smp_wmb();
5071                 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
5072         create_irqchip_unlock:
5073                 mutex_unlock(&kvm->lock);
5074                 break;
5075         }
5076         case KVM_CREATE_PIT:
5077                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
5078                 goto create_pit;
5079         case KVM_CREATE_PIT2:
5080                 r = -EFAULT;
5081                 if (copy_from_user(&u.pit_config, argp,
5082                                    sizeof(struct kvm_pit_config)))
5083                         goto out;
5084         create_pit:
5085                 mutex_lock(&kvm->lock);
5086                 r = -EEXIST;
5087                 if (kvm->arch.vpit)
5088                         goto create_pit_unlock;
5089                 r = -ENOMEM;
5090                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5091                 if (kvm->arch.vpit)
5092                         r = 0;
5093         create_pit_unlock:
5094                 mutex_unlock(&kvm->lock);
5095                 break;
5096         case KVM_GET_IRQCHIP: {
5097                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5098                 struct kvm_irqchip *chip;
5099
5100                 chip = memdup_user(argp, sizeof(*chip));
5101                 if (IS_ERR(chip)) {
5102                         r = PTR_ERR(chip);
5103                         goto out;
5104                 }
5105
5106                 r = -ENXIO;
5107                 if (!irqchip_kernel(kvm))
5108                         goto get_irqchip_out;
5109                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5110                 if (r)
5111                         goto get_irqchip_out;
5112                 r = -EFAULT;
5113                 if (copy_to_user(argp, chip, sizeof(*chip)))
5114                         goto get_irqchip_out;
5115                 r = 0;
5116         get_irqchip_out:
5117                 kfree(chip);
5118                 break;
5119         }
5120         case KVM_SET_IRQCHIP: {
5121                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5122                 struct kvm_irqchip *chip;
5123
5124                 chip = memdup_user(argp, sizeof(*chip));
5125                 if (IS_ERR(chip)) {
5126                         r = PTR_ERR(chip);
5127                         goto out;
5128                 }
5129
5130                 r = -ENXIO;
5131                 if (!irqchip_kernel(kvm))
5132                         goto set_irqchip_out;
5133                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5134         set_irqchip_out:
5135                 kfree(chip);
5136                 break;
5137         }
5138         case KVM_GET_PIT: {
5139                 r = -EFAULT;
5140                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5141                         goto out;
5142                 r = -ENXIO;
5143                 if (!kvm->arch.vpit)
5144                         goto out;
5145                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5146                 if (r)
5147                         goto out;
5148                 r = -EFAULT;
5149                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5150                         goto out;
5151                 r = 0;
5152                 break;
5153         }
5154         case KVM_SET_PIT: {
5155                 r = -EFAULT;
5156                 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5157                         goto out;
5158                 mutex_lock(&kvm->lock);
5159                 r = -ENXIO;
5160                 if (!kvm->arch.vpit)
5161                         goto set_pit_out;
5162                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5163 set_pit_out:
5164                 mutex_unlock(&kvm->lock);
5165                 break;
5166         }
5167         case KVM_GET_PIT2: {
5168                 r = -ENXIO;
5169                 if (!kvm->arch.vpit)
5170                         goto out;
5171                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5172                 if (r)
5173                         goto out;
5174                 r = -EFAULT;
5175                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5176                         goto out;
5177                 r = 0;
5178                 break;
5179         }
5180         case KVM_SET_PIT2: {
5181                 r = -EFAULT;
5182                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5183                         goto out;
5184                 mutex_lock(&kvm->lock);
5185                 r = -ENXIO;
5186                 if (!kvm->arch.vpit)
5187                         goto set_pit2_out;
5188                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5189 set_pit2_out:
5190                 mutex_unlock(&kvm->lock);
5191                 break;
5192         }
5193         case KVM_REINJECT_CONTROL: {
5194                 struct kvm_reinject_control control;
5195                 r =  -EFAULT;
5196                 if (copy_from_user(&control, argp, sizeof(control)))
5197                         goto out;
5198                 r = -ENXIO;
5199                 if (!kvm->arch.vpit)
5200                         goto out;
5201                 r = kvm_vm_ioctl_reinject(kvm, &control);
5202                 break;
5203         }
5204         case KVM_SET_BOOT_CPU_ID:
5205                 r = 0;
5206                 mutex_lock(&kvm->lock);
5207                 if (kvm->created_vcpus)
5208                         r = -EBUSY;
5209                 else
5210                         kvm->arch.bsp_vcpu_id = arg;
5211                 mutex_unlock(&kvm->lock);
5212                 break;
5213         case KVM_XEN_HVM_CONFIG: {
5214                 struct kvm_xen_hvm_config xhc;
5215                 r = -EFAULT;
5216                 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5217                         goto out;
5218                 r = -EINVAL;
5219                 if (xhc.flags)
5220                         goto out;
5221                 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5222                 r = 0;
5223                 break;
5224         }
5225         case KVM_SET_CLOCK: {
5226                 struct kvm_clock_data user_ns;
5227                 u64 now_ns;
5228
5229                 r = -EFAULT;
5230                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5231                         goto out;
5232
5233                 r = -EINVAL;
5234                 if (user_ns.flags)
5235                         goto out;
5236
5237                 r = 0;
5238                 /*
5239                  * TODO: userspace has to take care of races with VCPU_RUN, so
5240                  * kvm_gen_update_masterclock() can be cut down to locked
5241                  * pvclock_update_vm_gtod_copy().
5242                  */
5243                 kvm_gen_update_masterclock(kvm);
5244                 now_ns = get_kvmclock_ns(kvm);
5245                 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5246                 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5247                 break;
5248         }
5249         case KVM_GET_CLOCK: {
5250                 struct kvm_clock_data user_ns;
5251                 u64 now_ns;
5252
5253                 now_ns = get_kvmclock_ns(kvm);
5254                 user_ns.clock = now_ns;
5255                 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5256                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5257
5258                 r = -EFAULT;
5259                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5260                         goto out;
5261                 r = 0;
5262                 break;
5263         }
5264         case KVM_MEMORY_ENCRYPT_OP: {
5265                 r = -ENOTTY;
5266                 if (kvm_x86_ops.mem_enc_op)
5267                         r = kvm_x86_ops.mem_enc_op(kvm, argp);
5268                 break;
5269         }
5270         case KVM_MEMORY_ENCRYPT_REG_REGION: {
5271                 struct kvm_enc_region region;
5272
5273                 r = -EFAULT;
5274                 if (copy_from_user(&region, argp, sizeof(region)))
5275                         goto out;
5276
5277                 r = -ENOTTY;
5278                 if (kvm_x86_ops.mem_enc_reg_region)
5279                         r = kvm_x86_ops.mem_enc_reg_region(kvm, &region);
5280                 break;
5281         }
5282         case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5283                 struct kvm_enc_region region;
5284
5285                 r = -EFAULT;
5286                 if (copy_from_user(&region, argp, sizeof(region)))
5287                         goto out;
5288
5289                 r = -ENOTTY;
5290                 if (kvm_x86_ops.mem_enc_unreg_region)
5291                         r = kvm_x86_ops.mem_enc_unreg_region(kvm, &region);
5292                 break;
5293         }
5294         case KVM_HYPERV_EVENTFD: {
5295                 struct kvm_hyperv_eventfd hvevfd;
5296
5297                 r = -EFAULT;
5298                 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5299                         goto out;
5300                 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5301                 break;
5302         }
5303         case KVM_SET_PMU_EVENT_FILTER:
5304                 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5305                 break;
5306         default:
5307                 r = -ENOTTY;
5308         }
5309 out:
5310         return r;
5311 }
5312
5313 static void kvm_init_msr_list(void)
5314 {
5315         struct x86_pmu_capability x86_pmu;
5316         u32 dummy[2];
5317         unsigned i;
5318
5319         BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5320                          "Please update the fixed PMCs in msrs_to_saved_all[]");
5321
5322         perf_get_x86_pmu_capability(&x86_pmu);
5323
5324         num_msrs_to_save = 0;
5325         num_emulated_msrs = 0;
5326         num_msr_based_features = 0;
5327
5328         for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5329                 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5330                         continue;
5331
5332                 /*
5333                  * Even MSRs that are valid in the host may not be exposed
5334                  * to the guests in some cases.
5335                  */
5336                 switch (msrs_to_save_all[i]) {
5337                 case MSR_IA32_BNDCFGS:
5338                         if (!kvm_mpx_supported())
5339                                 continue;
5340                         break;
5341                 case MSR_TSC_AUX:
5342                         if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5343                                 continue;
5344                         break;
5345                 case MSR_IA32_UMWAIT_CONTROL:
5346                         if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
5347                                 continue;
5348                         break;
5349                 case MSR_IA32_RTIT_CTL:
5350                 case MSR_IA32_RTIT_STATUS:
5351                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5352                                 continue;
5353                         break;
5354                 case MSR_IA32_RTIT_CR3_MATCH:
5355                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5356                             !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5357                                 continue;
5358                         break;
5359                 case MSR_IA32_RTIT_OUTPUT_BASE:
5360                 case MSR_IA32_RTIT_OUTPUT_MASK:
5361                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5362                                 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5363                                  !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5364                                 continue;
5365                         break;
5366                 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
5367                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5368                                 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5369                                 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5370                                 continue;
5371                         break;
5372                 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5373                         if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5374                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5375                                 continue;
5376                         break;
5377                 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5378                         if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5379                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5380                                 continue;
5381                         break;
5382                 default:
5383                         break;
5384                 }
5385
5386                 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5387         }
5388
5389         for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5390                 if (!kvm_x86_ops.has_emulated_msr(emulated_msrs_all[i]))
5391                         continue;
5392
5393                 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5394         }
5395
5396         for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5397                 struct kvm_msr_entry msr;
5398
5399                 msr.index = msr_based_features_all[i];
5400                 if (kvm_get_msr_feature(&msr))
5401                         continue;
5402
5403                 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5404         }
5405 }
5406
5407 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5408                            const void *v)
5409 {
5410         int handled = 0;
5411         int n;
5412
5413         do {
5414                 n = min(len, 8);
5415                 if (!(lapic_in_kernel(vcpu) &&
5416                       !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5417                     && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5418                         break;
5419                 handled += n;
5420                 addr += n;
5421                 len -= n;
5422                 v += n;
5423         } while (len);
5424
5425         return handled;
5426 }
5427
5428 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5429 {
5430         int handled = 0;
5431         int n;
5432
5433         do {
5434                 n = min(len, 8);
5435                 if (!(lapic_in_kernel(vcpu) &&
5436                       !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5437                                          addr, n, v))
5438                     && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5439                         break;
5440                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5441                 handled += n;
5442                 addr += n;
5443                 len -= n;
5444                 v += n;
5445         } while (len);
5446
5447         return handled;
5448 }
5449
5450 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5451                         struct kvm_segment *var, int seg)
5452 {
5453         kvm_x86_ops.set_segment(vcpu, var, seg);
5454 }
5455
5456 void kvm_get_segment(struct kvm_vcpu *vcpu,
5457                      struct kvm_segment *var, int seg)
5458 {
5459         kvm_x86_ops.get_segment(vcpu, var, seg);
5460 }
5461
5462 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5463                            struct x86_exception *exception)
5464 {
5465         gpa_t t_gpa;
5466
5467         BUG_ON(!mmu_is_nested(vcpu));
5468
5469         /* NPT walks are always user-walks */
5470         access |= PFERR_USER_MASK;
5471         t_gpa  = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5472
5473         return t_gpa;
5474 }
5475
5476 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5477                               struct x86_exception *exception)
5478 {
5479         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5480         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5481 }
5482
5483  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5484                                 struct x86_exception *exception)
5485 {
5486         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5487         access |= PFERR_FETCH_MASK;
5488         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5489 }
5490
5491 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5492                                struct x86_exception *exception)
5493 {
5494         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5495         access |= PFERR_WRITE_MASK;
5496         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5497 }
5498
5499 /* uses this to access any guest's mapped memory without checking CPL */
5500 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5501                                 struct x86_exception *exception)
5502 {
5503         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5504 }
5505
5506 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5507                                       struct kvm_vcpu *vcpu, u32 access,
5508                                       struct x86_exception *exception)
5509 {
5510         void *data = val;
5511         int r = X86EMUL_CONTINUE;
5512
5513         while (bytes) {
5514                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5515                                                             exception);
5516                 unsigned offset = addr & (PAGE_SIZE-1);
5517                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5518                 int ret;
5519
5520                 if (gpa == UNMAPPED_GVA)
5521                         return X86EMUL_PROPAGATE_FAULT;
5522                 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5523                                                offset, toread);
5524                 if (ret < 0) {
5525                         r = X86EMUL_IO_NEEDED;
5526                         goto out;
5527                 }
5528
5529                 bytes -= toread;
5530                 data += toread;
5531                 addr += toread;
5532         }
5533 out:
5534         return r;
5535 }
5536
5537 /* used for instruction fetching */
5538 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5539                                 gva_t addr, void *val, unsigned int bytes,
5540                                 struct x86_exception *exception)
5541 {
5542         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5543         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5544         unsigned offset;
5545         int ret;
5546
5547         /* Inline kvm_read_guest_virt_helper for speed.  */
5548         gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5549                                                     exception);
5550         if (unlikely(gpa == UNMAPPED_GVA))
5551                 return X86EMUL_PROPAGATE_FAULT;
5552
5553         offset = addr & (PAGE_SIZE-1);
5554         if (WARN_ON(offset + bytes > PAGE_SIZE))
5555                 bytes = (unsigned)PAGE_SIZE - offset;
5556         ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5557                                        offset, bytes);
5558         if (unlikely(ret < 0))
5559                 return X86EMUL_IO_NEEDED;
5560
5561         return X86EMUL_CONTINUE;
5562 }
5563
5564 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5565                                gva_t addr, void *val, unsigned int bytes,
5566                                struct x86_exception *exception)
5567 {
5568         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5569
5570         /*
5571          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5572          * is returned, but our callers are not ready for that and they blindly
5573          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5574          * uninitialized kernel stack memory into cr2 and error code.
5575          */
5576         memset(exception, 0, sizeof(*exception));
5577         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5578                                           exception);
5579 }
5580 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5581
5582 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5583                              gva_t addr, void *val, unsigned int bytes,
5584                              struct x86_exception *exception, bool system)
5585 {
5586         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5587         u32 access = 0;
5588
5589         if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5590                 access |= PFERR_USER_MASK;
5591
5592         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5593 }
5594
5595 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5596                 unsigned long addr, void *val, unsigned int bytes)
5597 {
5598         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5599         int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5600
5601         return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5602 }
5603
5604 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5605                                       struct kvm_vcpu *vcpu, u32 access,
5606                                       struct x86_exception *exception)
5607 {
5608         void *data = val;
5609         int r = X86EMUL_CONTINUE;
5610
5611         while (bytes) {
5612                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5613                                                              access,
5614                                                              exception);
5615                 unsigned offset = addr & (PAGE_SIZE-1);
5616                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5617                 int ret;
5618
5619                 if (gpa == UNMAPPED_GVA)
5620                         return X86EMUL_PROPAGATE_FAULT;
5621                 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5622                 if (ret < 0) {
5623                         r = X86EMUL_IO_NEEDED;
5624                         goto out;
5625                 }
5626
5627                 bytes -= towrite;
5628                 data += towrite;
5629                 addr += towrite;
5630         }
5631 out:
5632         return r;
5633 }
5634
5635 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5636                               unsigned int bytes, struct x86_exception *exception,
5637                               bool system)
5638 {
5639         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5640         u32 access = PFERR_WRITE_MASK;
5641
5642         if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5643                 access |= PFERR_USER_MASK;
5644
5645         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5646                                            access, exception);
5647 }
5648
5649 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5650                                 unsigned int bytes, struct x86_exception *exception)
5651 {
5652         /* kvm_write_guest_virt_system can pull in tons of pages. */
5653         vcpu->arch.l1tf_flush_l1d = true;
5654
5655         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5656                                            PFERR_WRITE_MASK, exception);
5657 }
5658 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5659
5660 int handle_ud(struct kvm_vcpu *vcpu)
5661 {
5662         static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
5663         int emul_type = EMULTYPE_TRAP_UD;
5664         char sig[5]; /* ud2; .ascii "kvm" */
5665         struct x86_exception e;
5666
5667         if (force_emulation_prefix &&
5668             kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5669                                 sig, sizeof(sig), &e) == 0 &&
5670             memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
5671                 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5672                 emul_type = EMULTYPE_TRAP_UD_FORCED;
5673         }
5674
5675         return kvm_emulate_instruction(vcpu, emul_type);
5676 }
5677 EXPORT_SYMBOL_GPL(handle_ud);
5678
5679 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5680                             gpa_t gpa, bool write)
5681 {
5682         /* For APIC access vmexit */
5683         if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5684                 return 1;
5685
5686         if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5687                 trace_vcpu_match_mmio(gva, gpa, write, true);
5688                 return 1;
5689         }
5690
5691         return 0;
5692 }
5693
5694 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5695                                 gpa_t *gpa, struct x86_exception *exception,
5696                                 bool write)
5697 {
5698         u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5699                 | (write ? PFERR_WRITE_MASK : 0);
5700
5701         /*
5702          * currently PKRU is only applied to ept enabled guest so
5703          * there is no pkey in EPT page table for L1 guest or EPT
5704          * shadow page table for L2 guest.
5705          */
5706         if (vcpu_match_mmio_gva(vcpu, gva)
5707             && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5708                                  vcpu->arch.mmio_access, 0, access)) {
5709                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5710                                         (gva & (PAGE_SIZE - 1));
5711                 trace_vcpu_match_mmio(gva, *gpa, write, false);
5712                 return 1;
5713         }
5714
5715         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5716
5717         if (*gpa == UNMAPPED_GVA)
5718                 return -1;
5719
5720         return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5721 }
5722
5723 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5724                         const void *val, int bytes)
5725 {
5726         int ret;
5727
5728         ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5729         if (ret < 0)
5730                 return 0;
5731         kvm_page_track_write(vcpu, gpa, val, bytes);
5732         return 1;
5733 }
5734
5735 struct read_write_emulator_ops {
5736         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5737                                   int bytes);
5738         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5739                                   void *val, int bytes);
5740         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5741                                int bytes, void *val);
5742         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5743                                     void *val, int bytes);
5744         bool write;
5745 };
5746
5747 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5748 {
5749         if (vcpu->mmio_read_completed) {
5750                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5751                                vcpu->mmio_fragments[0].gpa, val);
5752                 vcpu->mmio_read_completed = 0;
5753                 return 1;
5754         }
5755
5756         return 0;
5757 }
5758
5759 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5760                         void *val, int bytes)
5761 {
5762         return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5763 }
5764
5765 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5766                          void *val, int bytes)
5767 {
5768         return emulator_write_phys(vcpu, gpa, val, bytes);
5769 }
5770
5771 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5772 {
5773         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5774         return vcpu_mmio_write(vcpu, gpa, bytes, val);
5775 }
5776
5777 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5778                           void *val, int bytes)
5779 {
5780         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5781         return X86EMUL_IO_NEEDED;
5782 }
5783
5784 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5785                            void *val, int bytes)
5786 {
5787         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5788
5789         memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5790         return X86EMUL_CONTINUE;
5791 }
5792
5793 static const struct read_write_emulator_ops read_emultor = {
5794         .read_write_prepare = read_prepare,
5795         .read_write_emulate = read_emulate,
5796         .read_write_mmio = vcpu_mmio_read,
5797         .read_write_exit_mmio = read_exit_mmio,
5798 };
5799
5800 static const struct read_write_emulator_ops write_emultor = {
5801         .read_write_emulate = write_emulate,
5802         .read_write_mmio = write_mmio,
5803         .read_write_exit_mmio = write_exit_mmio,
5804         .write = true,
5805 };
5806
5807 static int emulator_read_write_onepage(unsigned long addr, void *val,
5808                                        unsigned int bytes,
5809                                        struct x86_exception *exception,
5810                                        struct kvm_vcpu *vcpu,
5811                                        const struct read_write_emulator_ops *ops)
5812 {
5813         gpa_t gpa;
5814         int handled, ret;
5815         bool write = ops->write;
5816         struct kvm_mmio_fragment *frag;
5817         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
5818
5819         /*
5820          * If the exit was due to a NPF we may already have a GPA.
5821          * If the GPA is present, use it to avoid the GVA to GPA table walk.
5822          * Note, this cannot be used on string operations since string
5823          * operation using rep will only have the initial GPA from the NPF
5824          * occurred.
5825          */
5826         if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
5827             (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
5828                 gpa = ctxt->gpa_val;
5829                 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5830         } else {
5831                 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5832                 if (ret < 0)
5833                         return X86EMUL_PROPAGATE_FAULT;
5834         }
5835
5836         if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5837                 return X86EMUL_CONTINUE;
5838
5839         /*
5840          * Is this MMIO handled locally?
5841          */
5842         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5843         if (handled == bytes)
5844                 return X86EMUL_CONTINUE;
5845
5846         gpa += handled;
5847         bytes -= handled;
5848         val += handled;
5849
5850         WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5851         frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5852         frag->gpa = gpa;
5853         frag->data = val;
5854         frag->len = bytes;
5855         return X86EMUL_CONTINUE;
5856 }
5857
5858 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5859                         unsigned long addr,
5860                         void *val, unsigned int bytes,
5861                         struct x86_exception *exception,
5862                         const struct read_write_emulator_ops *ops)
5863 {
5864         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5865         gpa_t gpa;
5866         int rc;
5867
5868         if (ops->read_write_prepare &&
5869                   ops->read_write_prepare(vcpu, val, bytes))
5870                 return X86EMUL_CONTINUE;
5871
5872         vcpu->mmio_nr_fragments = 0;
5873
5874         /* Crossing a page boundary? */
5875         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5876                 int now;
5877
5878                 now = -addr & ~PAGE_MASK;
5879                 rc = emulator_read_write_onepage(addr, val, now, exception,
5880                                                  vcpu, ops);
5881
5882                 if (rc != X86EMUL_CONTINUE)
5883                         return rc;
5884                 addr += now;
5885                 if (ctxt->mode != X86EMUL_MODE_PROT64)
5886                         addr = (u32)addr;
5887                 val += now;
5888                 bytes -= now;
5889         }
5890
5891         rc = emulator_read_write_onepage(addr, val, bytes, exception,
5892                                          vcpu, ops);
5893         if (rc != X86EMUL_CONTINUE)
5894                 return rc;
5895
5896         if (!vcpu->mmio_nr_fragments)
5897                 return rc;
5898
5899         gpa = vcpu->mmio_fragments[0].gpa;
5900
5901         vcpu->mmio_needed = 1;
5902         vcpu->mmio_cur_fragment = 0;
5903
5904         vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5905         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5906         vcpu->run->exit_reason = KVM_EXIT_MMIO;
5907         vcpu->run->mmio.phys_addr = gpa;
5908
5909         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5910 }
5911
5912 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5913                                   unsigned long addr,
5914                                   void *val,
5915                                   unsigned int bytes,
5916                                   struct x86_exception *exception)
5917 {
5918         return emulator_read_write(ctxt, addr, val, bytes,
5919                                    exception, &read_emultor);
5920 }
5921
5922 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5923                             unsigned long addr,
5924                             const void *val,
5925                             unsigned int bytes,
5926                             struct x86_exception *exception)
5927 {
5928         return emulator_read_write(ctxt, addr, (void *)val, bytes,
5929                                    exception, &write_emultor);
5930 }
5931
5932 #define CMPXCHG_TYPE(t, ptr, old, new) \
5933         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5934
5935 #ifdef CONFIG_X86_64
5936 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5937 #else
5938 #  define CMPXCHG64(ptr, old, new) \
5939         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5940 #endif
5941
5942 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5943                                      unsigned long addr,
5944                                      const void *old,
5945                                      const void *new,
5946                                      unsigned int bytes,
5947                                      struct x86_exception *exception)
5948 {
5949         struct kvm_host_map map;
5950         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5951         u64 page_line_mask;
5952         gpa_t gpa;
5953         char *kaddr;
5954         bool exchanged;
5955
5956         /* guests cmpxchg8b have to be emulated atomically */
5957         if (bytes > 8 || (bytes & (bytes - 1)))
5958                 goto emul_write;
5959
5960         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5961
5962         if (gpa == UNMAPPED_GVA ||
5963             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5964                 goto emul_write;
5965
5966         /*
5967          * Emulate the atomic as a straight write to avoid #AC if SLD is
5968          * enabled in the host and the access splits a cache line.
5969          */
5970         if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
5971                 page_line_mask = ~(cache_line_size() - 1);
5972         else
5973                 page_line_mask = PAGE_MASK;
5974
5975         if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
5976                 goto emul_write;
5977
5978         if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5979                 goto emul_write;
5980
5981         kaddr = map.hva + offset_in_page(gpa);
5982
5983         switch (bytes) {
5984         case 1:
5985                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5986                 break;
5987         case 2:
5988                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5989                 break;
5990         case 4:
5991                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5992                 break;
5993         case 8:
5994                 exchanged = CMPXCHG64(kaddr, old, new);
5995                 break;
5996         default:
5997                 BUG();
5998         }
5999
6000         kvm_vcpu_unmap(vcpu, &map, true);
6001
6002         if (!exchanged)
6003                 return X86EMUL_CMPXCHG_FAILED;
6004
6005         kvm_page_track_write(vcpu, gpa, new, bytes);
6006
6007         return X86EMUL_CONTINUE;
6008
6009 emul_write:
6010         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
6011
6012         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
6013 }
6014
6015 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
6016 {
6017         int r = 0, i;
6018
6019         for (i = 0; i < vcpu->arch.pio.count; i++) {
6020                 if (vcpu->arch.pio.in)
6021                         r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
6022                                             vcpu->arch.pio.size, pd);
6023                 else
6024                         r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
6025                                              vcpu->arch.pio.port, vcpu->arch.pio.size,
6026                                              pd);
6027                 if (r)
6028                         break;
6029                 pd += vcpu->arch.pio.size;
6030         }
6031         return r;
6032 }
6033
6034 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
6035                                unsigned short port, void *val,
6036                                unsigned int count, bool in)
6037 {
6038         vcpu->arch.pio.port = port;
6039         vcpu->arch.pio.in = in;
6040         vcpu->arch.pio.count  = count;
6041         vcpu->arch.pio.size = size;
6042
6043         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
6044                 vcpu->arch.pio.count = 0;
6045                 return 1;
6046         }
6047
6048         vcpu->run->exit_reason = KVM_EXIT_IO;
6049         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
6050         vcpu->run->io.size = size;
6051         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
6052         vcpu->run->io.count = count;
6053         vcpu->run->io.port = port;
6054
6055         return 0;
6056 }
6057
6058 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
6059                            unsigned short port, void *val, unsigned int count)
6060 {
6061         int ret;
6062
6063         if (vcpu->arch.pio.count)
6064                 goto data_avail;
6065
6066         memset(vcpu->arch.pio_data, 0, size * count);
6067
6068         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
6069         if (ret) {
6070 data_avail:
6071                 memcpy(val, vcpu->arch.pio_data, size * count);
6072                 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
6073                 vcpu->arch.pio.count = 0;
6074                 return 1;
6075         }
6076
6077         return 0;
6078 }
6079
6080 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
6081                                     int size, unsigned short port, void *val,
6082                                     unsigned int count)
6083 {
6084         return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
6085
6086 }
6087
6088 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
6089                             unsigned short port, const void *val,
6090                             unsigned int count)
6091 {
6092         memcpy(vcpu->arch.pio_data, val, size * count);
6093         trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6094         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6095 }
6096
6097 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
6098                                      int size, unsigned short port,
6099                                      const void *val, unsigned int count)
6100 {
6101         return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
6102 }
6103
6104 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6105 {
6106         return kvm_x86_ops.get_segment_base(vcpu, seg);
6107 }
6108
6109 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6110 {
6111         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6112 }
6113
6114 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6115 {
6116         if (!need_emulate_wbinvd(vcpu))
6117                 return X86EMUL_CONTINUE;
6118
6119         if (kvm_x86_ops.has_wbinvd_exit()) {
6120                 int cpu = get_cpu();
6121
6122                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6123                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6124                                 wbinvd_ipi, NULL, 1);
6125                 put_cpu();
6126                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6127         } else
6128                 wbinvd();
6129         return X86EMUL_CONTINUE;
6130 }
6131
6132 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6133 {
6134         kvm_emulate_wbinvd_noskip(vcpu);
6135         return kvm_skip_emulated_instruction(vcpu);
6136 }
6137 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6138
6139
6140
6141 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6142 {
6143         kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6144 }
6145
6146 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6147                            unsigned long *dest)
6148 {
6149         return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6150 }
6151
6152 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6153                            unsigned long value)
6154 {
6155
6156         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6157 }
6158
6159 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6160 {
6161         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6162 }
6163
6164 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6165 {
6166         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6167         unsigned long value;
6168
6169         switch (cr) {
6170         case 0:
6171                 value = kvm_read_cr0(vcpu);
6172                 break;
6173         case 2:
6174                 value = vcpu->arch.cr2;
6175                 break;
6176         case 3:
6177                 value = kvm_read_cr3(vcpu);
6178                 break;
6179         case 4:
6180                 value = kvm_read_cr4(vcpu);
6181                 break;
6182         case 8:
6183                 value = kvm_get_cr8(vcpu);
6184                 break;
6185         default:
6186                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6187                 return 0;
6188         }
6189
6190         return value;
6191 }
6192
6193 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6194 {
6195         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6196         int res = 0;
6197
6198         switch (cr) {
6199         case 0:
6200                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6201                 break;
6202         case 2:
6203                 vcpu->arch.cr2 = val;
6204                 break;
6205         case 3:
6206                 res = kvm_set_cr3(vcpu, val);
6207                 break;
6208         case 4:
6209                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6210                 break;
6211         case 8:
6212                 res = kvm_set_cr8(vcpu, val);
6213                 break;
6214         default:
6215                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6216                 res = -1;
6217         }
6218
6219         return res;
6220 }
6221
6222 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6223 {
6224         return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt));
6225 }
6226
6227 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6228 {
6229         kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt);
6230 }
6231
6232 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6233 {
6234         kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt);
6235 }
6236
6237 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6238 {
6239         kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt);
6240 }
6241
6242 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6243 {
6244         kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt);
6245 }
6246
6247 static unsigned long emulator_get_cached_segment_base(
6248         struct x86_emulate_ctxt *ctxt, int seg)
6249 {
6250         return get_segment_base(emul_to_vcpu(ctxt), seg);
6251 }
6252
6253 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6254                                  struct desc_struct *desc, u32 *base3,
6255                                  int seg)
6256 {
6257         struct kvm_segment var;
6258
6259         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6260         *selector = var.selector;
6261
6262         if (var.unusable) {
6263                 memset(desc, 0, sizeof(*desc));
6264                 if (base3)
6265                         *base3 = 0;
6266                 return false;
6267         }
6268
6269         if (var.g)
6270                 var.limit >>= 12;
6271         set_desc_limit(desc, var.limit);
6272         set_desc_base(desc, (unsigned long)var.base);
6273 #ifdef CONFIG_X86_64
6274         if (base3)
6275                 *base3 = var.base >> 32;
6276 #endif
6277         desc->type = var.type;
6278         desc->s = var.s;
6279         desc->dpl = var.dpl;
6280         desc->p = var.present;
6281         desc->avl = var.avl;
6282         desc->l = var.l;
6283         desc->d = var.db;
6284         desc->g = var.g;
6285
6286         return true;
6287 }
6288
6289 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6290                                  struct desc_struct *desc, u32 base3,
6291                                  int seg)
6292 {
6293         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6294         struct kvm_segment var;
6295
6296         var.selector = selector;
6297         var.base = get_desc_base(desc);
6298 #ifdef CONFIG_X86_64
6299         var.base |= ((u64)base3) << 32;
6300 #endif
6301         var.limit = get_desc_limit(desc);
6302         if (desc->g)
6303                 var.limit = (var.limit << 12) | 0xfff;
6304         var.type = desc->type;
6305         var.dpl = desc->dpl;
6306         var.db = desc->d;
6307         var.s = desc->s;
6308         var.l = desc->l;
6309         var.g = desc->g;
6310         var.avl = desc->avl;
6311         var.present = desc->p;
6312         var.unusable = !var.present;
6313         var.padding = 0;
6314
6315         kvm_set_segment(vcpu, &var, seg);
6316         return;
6317 }
6318
6319 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6320                             u32 msr_index, u64 *pdata)
6321 {
6322         return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6323 }
6324
6325 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6326                             u32 msr_index, u64 data)
6327 {
6328         return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6329 }
6330
6331 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6332 {
6333         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6334
6335         return vcpu->arch.smbase;
6336 }
6337
6338 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6339 {
6340         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6341
6342         vcpu->arch.smbase = smbase;
6343 }
6344
6345 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6346                               u32 pmc)
6347 {
6348         return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6349 }
6350
6351 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6352                              u32 pmc, u64 *pdata)
6353 {
6354         return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6355 }
6356
6357 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6358 {
6359         emul_to_vcpu(ctxt)->arch.halt_request = 1;
6360 }
6361
6362 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6363                               struct x86_instruction_info *info,
6364                               enum x86_intercept_stage stage)
6365 {
6366         return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage,
6367                                             &ctxt->exception);
6368 }
6369
6370 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6371                               u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6372                               bool exact_only)
6373 {
6374         return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6375 }
6376
6377 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6378 {
6379         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6380 }
6381
6382 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6383 {
6384         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6385 }
6386
6387 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6388 {
6389         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6390 }
6391
6392 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6393 {
6394         return kvm_register_read(emul_to_vcpu(ctxt), reg);
6395 }
6396
6397 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6398 {
6399         kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6400 }
6401
6402 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6403 {
6404         kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked);
6405 }
6406
6407 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6408 {
6409         return emul_to_vcpu(ctxt)->arch.hflags;
6410 }
6411
6412 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6413 {
6414         emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6415 }
6416
6417 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6418                                   const char *smstate)
6419 {
6420         return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6421 }
6422
6423 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6424 {
6425         kvm_smm_changed(emul_to_vcpu(ctxt));
6426 }
6427
6428 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6429 {
6430         return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6431 }
6432
6433 static const struct x86_emulate_ops emulate_ops = {
6434         .read_gpr            = emulator_read_gpr,
6435         .write_gpr           = emulator_write_gpr,
6436         .read_std            = emulator_read_std,
6437         .write_std           = emulator_write_std,
6438         .read_phys           = kvm_read_guest_phys_system,
6439         .fetch               = kvm_fetch_guest_virt,
6440         .read_emulated       = emulator_read_emulated,
6441         .write_emulated      = emulator_write_emulated,
6442         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
6443         .invlpg              = emulator_invlpg,
6444         .pio_in_emulated     = emulator_pio_in_emulated,
6445         .pio_out_emulated    = emulator_pio_out_emulated,
6446         .get_segment         = emulator_get_segment,
6447         .set_segment         = emulator_set_segment,
6448         .get_cached_segment_base = emulator_get_cached_segment_base,
6449         .get_gdt             = emulator_get_gdt,
6450         .get_idt             = emulator_get_idt,
6451         .set_gdt             = emulator_set_gdt,
6452         .set_idt             = emulator_set_idt,
6453         .get_cr              = emulator_get_cr,
6454         .set_cr              = emulator_set_cr,
6455         .cpl                 = emulator_get_cpl,
6456         .get_dr              = emulator_get_dr,
6457         .set_dr              = emulator_set_dr,
6458         .get_smbase          = emulator_get_smbase,
6459         .set_smbase          = emulator_set_smbase,
6460         .set_msr             = emulator_set_msr,
6461         .get_msr             = emulator_get_msr,
6462         .check_pmc           = emulator_check_pmc,
6463         .read_pmc            = emulator_read_pmc,
6464         .halt                = emulator_halt,
6465         .wbinvd              = emulator_wbinvd,
6466         .fix_hypercall       = emulator_fix_hypercall,
6467         .intercept           = emulator_intercept,
6468         .get_cpuid           = emulator_get_cpuid,
6469         .guest_has_long_mode = emulator_guest_has_long_mode,
6470         .guest_has_movbe     = emulator_guest_has_movbe,
6471         .guest_has_fxsr      = emulator_guest_has_fxsr,
6472         .set_nmi_mask        = emulator_set_nmi_mask,
6473         .get_hflags          = emulator_get_hflags,
6474         .set_hflags          = emulator_set_hflags,
6475         .pre_leave_smm       = emulator_pre_leave_smm,
6476         .post_leave_smm      = emulator_post_leave_smm,
6477         .set_xcr             = emulator_set_xcr,
6478 };
6479
6480 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6481 {
6482         u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
6483         /*
6484          * an sti; sti; sequence only disable interrupts for the first
6485          * instruction. So, if the last instruction, be it emulated or
6486          * not, left the system with the INT_STI flag enabled, it
6487          * means that the last instruction is an sti. We should not
6488          * leave the flag on in this case. The same goes for mov ss
6489          */
6490         if (int_shadow & mask)
6491                 mask = 0;
6492         if (unlikely(int_shadow || mask)) {
6493                 kvm_x86_ops.set_interrupt_shadow(vcpu, mask);
6494                 if (!mask)
6495                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6496         }
6497 }
6498
6499 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6500 {
6501         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6502         if (ctxt->exception.vector == PF_VECTOR)
6503                 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
6504
6505         if (ctxt->exception.error_code_valid)
6506                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6507                                       ctxt->exception.error_code);
6508         else
6509                 kvm_queue_exception(vcpu, ctxt->exception.vector);
6510         return false;
6511 }
6512
6513 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6514 {
6515         struct x86_emulate_ctxt *ctxt;
6516
6517         ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6518         if (!ctxt) {
6519                 pr_err("kvm: failed to allocate vcpu's emulator\n");
6520                 return NULL;
6521         }
6522
6523         ctxt->vcpu = vcpu;
6524         ctxt->ops = &emulate_ops;
6525         vcpu->arch.emulate_ctxt = ctxt;
6526
6527         return ctxt;
6528 }
6529
6530 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6531 {
6532         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6533         int cs_db, cs_l;
6534
6535         kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6536
6537         ctxt->gpa_available = false;
6538         ctxt->eflags = kvm_get_rflags(vcpu);
6539         ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6540
6541         ctxt->eip = kvm_rip_read(vcpu);
6542         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
6543                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
6544                      (cs_l && is_long_mode(vcpu))       ? X86EMUL_MODE_PROT64 :
6545                      cs_db                              ? X86EMUL_MODE_PROT32 :
6546                                                           X86EMUL_MODE_PROT16;
6547         BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6548         BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6549         BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6550
6551         init_decode_cache(ctxt);
6552         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6553 }
6554
6555 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6556 {
6557         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6558         int ret;
6559
6560         init_emulate_ctxt(vcpu);
6561
6562         ctxt->op_bytes = 2;
6563         ctxt->ad_bytes = 2;
6564         ctxt->_eip = ctxt->eip + inc_eip;
6565         ret = emulate_int_real(ctxt, irq);
6566
6567         if (ret != X86EMUL_CONTINUE) {
6568                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6569         } else {
6570                 ctxt->eip = ctxt->_eip;
6571                 kvm_rip_write(vcpu, ctxt->eip);
6572                 kvm_set_rflags(vcpu, ctxt->eflags);
6573         }
6574 }
6575 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6576
6577 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6578 {
6579         ++vcpu->stat.insn_emulation_fail;
6580         trace_kvm_emulate_insn_failed(vcpu);
6581
6582         if (emulation_type & EMULTYPE_VMWARE_GP) {
6583                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6584                 return 1;
6585         }
6586
6587         if (emulation_type & EMULTYPE_SKIP) {
6588                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6589                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6590                 vcpu->run->internal.ndata = 0;
6591                 return 0;
6592         }
6593
6594         kvm_queue_exception(vcpu, UD_VECTOR);
6595
6596         if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) {
6597                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6598                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6599                 vcpu->run->internal.ndata = 0;
6600                 return 0;
6601         }
6602
6603         return 1;
6604 }
6605
6606 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6607                                   bool write_fault_to_shadow_pgtable,
6608                                   int emulation_type)
6609 {
6610         gpa_t gpa = cr2_or_gpa;
6611         kvm_pfn_t pfn;
6612
6613         if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6614                 return false;
6615
6616         if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6617             WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6618                 return false;
6619
6620         if (!vcpu->arch.mmu->direct_map) {
6621                 /*
6622                  * Write permission should be allowed since only
6623                  * write access need to be emulated.
6624                  */
6625                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6626
6627                 /*
6628                  * If the mapping is invalid in guest, let cpu retry
6629                  * it to generate fault.
6630                  */
6631                 if (gpa == UNMAPPED_GVA)
6632                         return true;
6633         }
6634
6635         /*
6636          * Do not retry the unhandleable instruction if it faults on the
6637          * readonly host memory, otherwise it will goto a infinite loop:
6638          * retry instruction -> write #PF -> emulation fail -> retry
6639          * instruction -> ...
6640          */
6641         pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6642
6643         /*
6644          * If the instruction failed on the error pfn, it can not be fixed,
6645          * report the error to userspace.
6646          */
6647         if (is_error_noslot_pfn(pfn))
6648                 return false;
6649
6650         kvm_release_pfn_clean(pfn);
6651
6652         /* The instructions are well-emulated on direct mmu. */
6653         if (vcpu->arch.mmu->direct_map) {
6654                 unsigned int indirect_shadow_pages;
6655
6656                 spin_lock(&vcpu->kvm->mmu_lock);
6657                 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6658                 spin_unlock(&vcpu->kvm->mmu_lock);
6659
6660                 if (indirect_shadow_pages)
6661                         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6662
6663                 return true;
6664         }
6665
6666         /*
6667          * if emulation was due to access to shadowed page table
6668          * and it failed try to unshadow page and re-enter the
6669          * guest to let CPU execute the instruction.
6670          */
6671         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6672
6673         /*
6674          * If the access faults on its page table, it can not
6675          * be fixed by unprotecting shadow page and it should
6676          * be reported to userspace.
6677          */
6678         return !write_fault_to_shadow_pgtable;
6679 }
6680
6681 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6682                               gpa_t cr2_or_gpa,  int emulation_type)
6683 {
6684         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6685         unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
6686
6687         last_retry_eip = vcpu->arch.last_retry_eip;
6688         last_retry_addr = vcpu->arch.last_retry_addr;
6689
6690         /*
6691          * If the emulation is caused by #PF and it is non-page_table
6692          * writing instruction, it means the VM-EXIT is caused by shadow
6693          * page protected, we can zap the shadow page and retry this
6694          * instruction directly.
6695          *
6696          * Note: if the guest uses a non-page-table modifying instruction
6697          * on the PDE that points to the instruction, then we will unmap
6698          * the instruction and go to an infinite loop. So, we cache the
6699          * last retried eip and the last fault address, if we meet the eip
6700          * and the address again, we can break out of the potential infinite
6701          * loop.
6702          */
6703         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6704
6705         if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6706                 return false;
6707
6708         if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6709             WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6710                 return false;
6711
6712         if (x86_page_table_writing_insn(ctxt))
6713                 return false;
6714
6715         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
6716                 return false;
6717
6718         vcpu->arch.last_retry_eip = ctxt->eip;
6719         vcpu->arch.last_retry_addr = cr2_or_gpa;
6720
6721         if (!vcpu->arch.mmu->direct_map)
6722                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6723
6724         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6725
6726         return true;
6727 }
6728
6729 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6730 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6731
6732 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6733 {
6734         if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6735                 /* This is a good place to trace that we are exiting SMM.  */
6736                 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6737
6738                 /* Process a latched INIT or SMI, if any.  */
6739                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6740         }
6741
6742         kvm_mmu_reset_context(vcpu);
6743 }
6744
6745 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6746                                 unsigned long *db)
6747 {
6748         u32 dr6 = 0;
6749         int i;
6750         u32 enable, rwlen;
6751
6752         enable = dr7;
6753         rwlen = dr7 >> 16;
6754         for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6755                 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6756                         dr6 |= (1 << i);
6757         return dr6;
6758 }
6759
6760 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6761 {
6762         struct kvm_run *kvm_run = vcpu->run;
6763
6764         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6765                 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6766                 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6767                 kvm_run->debug.arch.exception = DB_VECTOR;
6768                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6769                 return 0;
6770         }
6771         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6772         return 1;
6773 }
6774
6775 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6776 {
6777         unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
6778         int r;
6779
6780         r = kvm_x86_ops.skip_emulated_instruction(vcpu);
6781         if (unlikely(!r))
6782                 return 0;
6783
6784         /*
6785          * rflags is the old, "raw" value of the flags.  The new value has
6786          * not been saved yet.
6787          *
6788          * This is correct even for TF set by the guest, because "the
6789          * processor will not generate this exception after the instruction
6790          * that sets the TF flag".
6791          */
6792         if (unlikely(rflags & X86_EFLAGS_TF))
6793                 r = kvm_vcpu_do_singlestep(vcpu);
6794         return r;
6795 }
6796 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6797
6798 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6799 {
6800         if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6801             (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6802                 struct kvm_run *kvm_run = vcpu->run;
6803                 unsigned long eip = kvm_get_linear_rip(vcpu);
6804                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6805                                            vcpu->arch.guest_debug_dr7,
6806                                            vcpu->arch.eff_db);
6807
6808                 if (dr6 != 0) {
6809                         kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6810                         kvm_run->debug.arch.pc = eip;
6811                         kvm_run->debug.arch.exception = DB_VECTOR;
6812                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
6813                         *r = 0;
6814                         return true;
6815                 }
6816         }
6817
6818         if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6819             !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6820                 unsigned long eip = kvm_get_linear_rip(vcpu);
6821                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6822                                            vcpu->arch.dr7,
6823                                            vcpu->arch.db);
6824
6825                 if (dr6 != 0) {
6826                         kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
6827                         *r = 1;
6828                         return true;
6829                 }
6830         }
6831
6832         return false;
6833 }
6834
6835 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6836 {
6837         switch (ctxt->opcode_len) {
6838         case 1:
6839                 switch (ctxt->b) {
6840                 case 0xe4:      /* IN */
6841                 case 0xe5:
6842                 case 0xec:
6843                 case 0xed:
6844                 case 0xe6:      /* OUT */
6845                 case 0xe7:
6846                 case 0xee:
6847                 case 0xef:
6848                 case 0x6c:      /* INS */
6849                 case 0x6d:
6850                 case 0x6e:      /* OUTS */
6851                 case 0x6f:
6852                         return true;
6853                 }
6854                 break;
6855         case 2:
6856                 switch (ctxt->b) {
6857                 case 0x33:      /* RDPMC */
6858                         return true;
6859                 }
6860                 break;
6861         }
6862
6863         return false;
6864 }
6865
6866 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6867                             int emulation_type, void *insn, int insn_len)
6868 {
6869         int r;
6870         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6871         bool writeback = true;
6872         bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6873
6874         vcpu->arch.l1tf_flush_l1d = true;
6875
6876         /*
6877          * Clear write_fault_to_shadow_pgtable here to ensure it is
6878          * never reused.
6879          */
6880         vcpu->arch.write_fault_to_shadow_pgtable = false;
6881         kvm_clear_exception_queue(vcpu);
6882
6883         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6884                 init_emulate_ctxt(vcpu);
6885
6886                 /*
6887                  * We will reenter on the same instruction since
6888                  * we do not set complete_userspace_io.  This does not
6889                  * handle watchpoints yet, those would be handled in
6890                  * the emulate_ops.
6891                  */
6892                 if (!(emulation_type & EMULTYPE_SKIP) &&
6893                     kvm_vcpu_check_breakpoint(vcpu, &r))
6894                         return r;
6895
6896                 ctxt->interruptibility = 0;
6897                 ctxt->have_exception = false;
6898                 ctxt->exception.vector = -1;
6899                 ctxt->perm_ok = false;
6900
6901                 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6902
6903                 r = x86_decode_insn(ctxt, insn, insn_len);
6904
6905                 trace_kvm_emulate_insn_start(vcpu);
6906                 ++vcpu->stat.insn_emulation;
6907                 if (r != EMULATION_OK)  {
6908                         if ((emulation_type & EMULTYPE_TRAP_UD) ||
6909                             (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6910                                 kvm_queue_exception(vcpu, UD_VECTOR);
6911                                 return 1;
6912                         }
6913                         if (reexecute_instruction(vcpu, cr2_or_gpa,
6914                                                   write_fault_to_spt,
6915                                                   emulation_type))
6916                                 return 1;
6917                         if (ctxt->have_exception) {
6918                                 /*
6919                                  * #UD should result in just EMULATION_FAILED, and trap-like
6920                                  * exception should not be encountered during decode.
6921                                  */
6922                                 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6923                                              exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6924                                 inject_emulated_exception(vcpu);
6925                                 return 1;
6926                         }
6927                         return handle_emulation_failure(vcpu, emulation_type);
6928                 }
6929         }
6930
6931         if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6932             !is_vmware_backdoor_opcode(ctxt)) {
6933                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6934                 return 1;
6935         }
6936
6937         /*
6938          * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6939          * for kvm_skip_emulated_instruction().  The caller is responsible for
6940          * updating interruptibility state and injecting single-step #DBs.
6941          */
6942         if (emulation_type & EMULTYPE_SKIP) {
6943                 kvm_rip_write(vcpu, ctxt->_eip);
6944                 if (ctxt->eflags & X86_EFLAGS_RF)
6945                         kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6946                 return 1;
6947         }
6948
6949         if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
6950                 return 1;
6951
6952         /* this is needed for vmware backdoor interface to work since it
6953            changes registers values  during IO operation */
6954         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6955                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6956                 emulator_invalidate_register_cache(ctxt);
6957         }
6958
6959 restart:
6960         if (emulation_type & EMULTYPE_PF) {
6961                 /* Save the faulting GPA (cr2) in the address field */
6962                 ctxt->exception.address = cr2_or_gpa;
6963
6964                 /* With shadow page tables, cr2 contains a GVA or nGPA. */
6965                 if (vcpu->arch.mmu->direct_map) {
6966                         ctxt->gpa_available = true;
6967                         ctxt->gpa_val = cr2_or_gpa;
6968                 }
6969         } else {
6970                 /* Sanitize the address out of an abundance of paranoia. */
6971                 ctxt->exception.address = 0;
6972         }
6973
6974         r = x86_emulate_insn(ctxt);
6975
6976         if (r == EMULATION_INTERCEPTED)
6977                 return 1;
6978
6979         if (r == EMULATION_FAILED) {
6980                 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
6981                                         emulation_type))
6982                         return 1;
6983
6984                 return handle_emulation_failure(vcpu, emulation_type);
6985         }
6986
6987         if (ctxt->have_exception) {
6988                 r = 1;
6989                 if (inject_emulated_exception(vcpu))
6990                         return r;
6991         } else if (vcpu->arch.pio.count) {
6992                 if (!vcpu->arch.pio.in) {
6993                         /* FIXME: return into emulator if single-stepping.  */
6994                         vcpu->arch.pio.count = 0;
6995                 } else {
6996                         writeback = false;
6997                         vcpu->arch.complete_userspace_io = complete_emulated_pio;
6998                 }
6999                 r = 0;
7000         } else if (vcpu->mmio_needed) {
7001                 ++vcpu->stat.mmio_exits;
7002
7003                 if (!vcpu->mmio_is_write)
7004                         writeback = false;
7005                 r = 0;
7006                 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7007         } else if (r == EMULATION_RESTART)
7008                 goto restart;
7009         else
7010                 r = 1;
7011
7012         if (writeback) {
7013                 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7014                 toggle_interruptibility(vcpu, ctxt->interruptibility);
7015                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7016                 if (!ctxt->have_exception ||
7017                     exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
7018                         kvm_rip_write(vcpu, ctxt->eip);
7019                         if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
7020                                 r = kvm_vcpu_do_singlestep(vcpu);
7021                         if (kvm_x86_ops.update_emulated_instruction)
7022                                 kvm_x86_ops.update_emulated_instruction(vcpu);
7023                         __kvm_set_rflags(vcpu, ctxt->eflags);
7024                 }
7025
7026                 /*
7027                  * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
7028                  * do nothing, and it will be requested again as soon as
7029                  * the shadow expires.  But we still need to check here,
7030                  * because POPF has no interrupt shadow.
7031                  */
7032                 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
7033                         kvm_make_request(KVM_REQ_EVENT, vcpu);
7034         } else
7035                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
7036
7037         return r;
7038 }
7039
7040 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
7041 {
7042         return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
7043 }
7044 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
7045
7046 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
7047                                         void *insn, int insn_len)
7048 {
7049         return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
7050 }
7051 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
7052
7053 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
7054 {
7055         vcpu->arch.pio.count = 0;
7056         return 1;
7057 }
7058
7059 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
7060 {
7061         vcpu->arch.pio.count = 0;
7062
7063         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
7064                 return 1;
7065
7066         return kvm_skip_emulated_instruction(vcpu);
7067 }
7068
7069 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
7070                             unsigned short port)
7071 {
7072         unsigned long val = kvm_rax_read(vcpu);
7073         int ret = emulator_pio_out(vcpu, size, port, &val, 1);
7074
7075         if (ret)
7076                 return ret;
7077
7078         /*
7079          * Workaround userspace that relies on old KVM behavior of %rip being
7080          * incremented prior to exiting to userspace to handle "OUT 0x7e".
7081          */
7082         if (port == 0x7e &&
7083             kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
7084                 vcpu->arch.complete_userspace_io =
7085                         complete_fast_pio_out_port_0x7e;
7086                 kvm_skip_emulated_instruction(vcpu);
7087         } else {
7088                 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7089                 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
7090         }
7091         return 0;
7092 }
7093
7094 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
7095 {
7096         unsigned long val;
7097
7098         /* We should only ever be called with arch.pio.count equal to 1 */
7099         BUG_ON(vcpu->arch.pio.count != 1);
7100
7101         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
7102                 vcpu->arch.pio.count = 0;
7103                 return 1;
7104         }
7105
7106         /* For size less than 4 we merge, else we zero extend */
7107         val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7108
7109         /*
7110          * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7111          * the copy and tracing
7112          */
7113         emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7114         kvm_rax_write(vcpu, val);
7115
7116         return kvm_skip_emulated_instruction(vcpu);
7117 }
7118
7119 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7120                            unsigned short port)
7121 {
7122         unsigned long val;
7123         int ret;
7124
7125         /* For size less than 4 we merge, else we zero extend */
7126         val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7127
7128         ret = emulator_pio_in(vcpu, size, port, &val, 1);
7129         if (ret) {
7130                 kvm_rax_write(vcpu, val);
7131                 return ret;
7132         }
7133
7134         vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7135         vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7136
7137         return 0;
7138 }
7139
7140 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7141 {
7142         int ret;
7143
7144         if (in)
7145                 ret = kvm_fast_pio_in(vcpu, size, port);
7146         else
7147                 ret = kvm_fast_pio_out(vcpu, size, port);
7148         return ret && kvm_skip_emulated_instruction(vcpu);
7149 }
7150 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7151
7152 static int kvmclock_cpu_down_prep(unsigned int cpu)
7153 {
7154         __this_cpu_write(cpu_tsc_khz, 0);
7155         return 0;
7156 }
7157
7158 static void tsc_khz_changed(void *data)
7159 {
7160         struct cpufreq_freqs *freq = data;
7161         unsigned long khz = 0;
7162
7163         if (data)
7164                 khz = freq->new;
7165         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7166                 khz = cpufreq_quick_get(raw_smp_processor_id());
7167         if (!khz)
7168                 khz = tsc_khz;
7169         __this_cpu_write(cpu_tsc_khz, khz);
7170 }
7171
7172 #ifdef CONFIG_X86_64
7173 static void kvm_hyperv_tsc_notifier(void)
7174 {
7175         struct kvm *kvm;
7176         struct kvm_vcpu *vcpu;
7177         int cpu;
7178
7179         mutex_lock(&kvm_lock);
7180         list_for_each_entry(kvm, &vm_list, vm_list)
7181                 kvm_make_mclock_inprogress_request(kvm);
7182
7183         hyperv_stop_tsc_emulation();
7184
7185         /* TSC frequency always matches when on Hyper-V */
7186         for_each_present_cpu(cpu)
7187                 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7188         kvm_max_guest_tsc_khz = tsc_khz;
7189
7190         list_for_each_entry(kvm, &vm_list, vm_list) {
7191                 struct kvm_arch *ka = &kvm->arch;
7192
7193                 spin_lock(&ka->pvclock_gtod_sync_lock);
7194
7195                 pvclock_update_vm_gtod_copy(kvm);
7196
7197                 kvm_for_each_vcpu(cpu, vcpu, kvm)
7198                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7199
7200                 kvm_for_each_vcpu(cpu, vcpu, kvm)
7201                         kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7202
7203                 spin_unlock(&ka->pvclock_gtod_sync_lock);
7204         }
7205         mutex_unlock(&kvm_lock);
7206 }
7207 #endif
7208
7209 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7210 {
7211         struct kvm *kvm;
7212         struct kvm_vcpu *vcpu;
7213         int i, send_ipi = 0;
7214
7215         /*
7216          * We allow guests to temporarily run on slowing clocks,
7217          * provided we notify them after, or to run on accelerating
7218          * clocks, provided we notify them before.  Thus time never
7219          * goes backwards.
7220          *
7221          * However, we have a problem.  We can't atomically update
7222          * the frequency of a given CPU from this function; it is
7223          * merely a notifier, which can be called from any CPU.
7224          * Changing the TSC frequency at arbitrary points in time
7225          * requires a recomputation of local variables related to
7226          * the TSC for each VCPU.  We must flag these local variables
7227          * to be updated and be sure the update takes place with the
7228          * new frequency before any guests proceed.
7229          *
7230          * Unfortunately, the combination of hotplug CPU and frequency
7231          * change creates an intractable locking scenario; the order
7232          * of when these callouts happen is undefined with respect to
7233          * CPU hotplug, and they can race with each other.  As such,
7234          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7235          * undefined; you can actually have a CPU frequency change take
7236          * place in between the computation of X and the setting of the
7237          * variable.  To protect against this problem, all updates of
7238          * the per_cpu tsc_khz variable are done in an interrupt
7239          * protected IPI, and all callers wishing to update the value
7240          * must wait for a synchronous IPI to complete (which is trivial
7241          * if the caller is on the CPU already).  This establishes the
7242          * necessary total order on variable updates.
7243          *
7244          * Note that because a guest time update may take place
7245          * anytime after the setting of the VCPU's request bit, the
7246          * correct TSC value must be set before the request.  However,
7247          * to ensure the update actually makes it to any guest which
7248          * starts running in hardware virtualization between the set
7249          * and the acquisition of the spinlock, we must also ping the
7250          * CPU after setting the request bit.
7251          *
7252          */
7253
7254         smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7255
7256         mutex_lock(&kvm_lock);
7257         list_for_each_entry(kvm, &vm_list, vm_list) {
7258                 kvm_for_each_vcpu(i, vcpu, kvm) {
7259                         if (vcpu->cpu != cpu)
7260                                 continue;
7261                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7262                         if (vcpu->cpu != raw_smp_processor_id())
7263                                 send_ipi = 1;
7264                 }
7265         }
7266         mutex_unlock(&kvm_lock);
7267
7268         if (freq->old < freq->new && send_ipi) {
7269                 /*
7270                  * We upscale the frequency.  Must make the guest
7271                  * doesn't see old kvmclock values while running with
7272                  * the new frequency, otherwise we risk the guest sees
7273                  * time go backwards.
7274                  *
7275                  * In case we update the frequency for another cpu
7276                  * (which might be in guest context) send an interrupt
7277                  * to kick the cpu out of guest context.  Next time
7278                  * guest context is entered kvmclock will be updated,
7279                  * so the guest will not see stale values.
7280                  */
7281                 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7282         }
7283 }
7284
7285 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7286                                      void *data)
7287 {
7288         struct cpufreq_freqs *freq = data;
7289         int cpu;
7290
7291         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7292                 return 0;
7293         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7294                 return 0;
7295
7296         for_each_cpu(cpu, freq->policy->cpus)
7297                 __kvmclock_cpufreq_notifier(freq, cpu);
7298
7299         return 0;
7300 }
7301
7302 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7303         .notifier_call  = kvmclock_cpufreq_notifier
7304 };
7305
7306 static int kvmclock_cpu_online(unsigned int cpu)
7307 {
7308         tsc_khz_changed(NULL);
7309         return 0;
7310 }
7311
7312 static void kvm_timer_init(void)
7313 {
7314         max_tsc_khz = tsc_khz;
7315
7316         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7317 #ifdef CONFIG_CPU_FREQ
7318                 struct cpufreq_policy *policy;
7319                 int cpu;
7320
7321                 cpu = get_cpu();
7322                 policy = cpufreq_cpu_get(cpu);
7323                 if (policy) {
7324                         if (policy->cpuinfo.max_freq)
7325                                 max_tsc_khz = policy->cpuinfo.max_freq;
7326                         cpufreq_cpu_put(policy);
7327                 }
7328                 put_cpu();
7329 #endif
7330                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7331                                           CPUFREQ_TRANSITION_NOTIFIER);
7332         }
7333
7334         cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7335                           kvmclock_cpu_online, kvmclock_cpu_down_prep);
7336 }
7337
7338 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7339 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7340
7341 int kvm_is_in_guest(void)
7342 {
7343         return __this_cpu_read(current_vcpu) != NULL;
7344 }
7345
7346 static int kvm_is_user_mode(void)
7347 {
7348         int user_mode = 3;
7349
7350         if (__this_cpu_read(current_vcpu))
7351                 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu));
7352
7353         return user_mode != 0;
7354 }
7355
7356 static unsigned long kvm_get_guest_ip(void)
7357 {
7358         unsigned long ip = 0;
7359
7360         if (__this_cpu_read(current_vcpu))
7361                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7362
7363         return ip;
7364 }
7365
7366 static void kvm_handle_intel_pt_intr(void)
7367 {
7368         struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7369
7370         kvm_make_request(KVM_REQ_PMI, vcpu);
7371         __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7372                         (unsigned long *)&vcpu->arch.pmu.global_status);
7373 }
7374
7375 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7376         .is_in_guest            = kvm_is_in_guest,
7377         .is_user_mode           = kvm_is_user_mode,
7378         .get_guest_ip           = kvm_get_guest_ip,
7379         .handle_intel_pt_intr   = kvm_handle_intel_pt_intr,
7380 };
7381
7382 #ifdef CONFIG_X86_64
7383 static void pvclock_gtod_update_fn(struct work_struct *work)
7384 {
7385         struct kvm *kvm;
7386
7387         struct kvm_vcpu *vcpu;
7388         int i;
7389
7390         mutex_lock(&kvm_lock);
7391         list_for_each_entry(kvm, &vm_list, vm_list)
7392                 kvm_for_each_vcpu(i, vcpu, kvm)
7393                         kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7394         atomic_set(&kvm_guest_has_master_clock, 0);
7395         mutex_unlock(&kvm_lock);
7396 }
7397
7398 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7399
7400 /*
7401  * Notification about pvclock gtod data update.
7402  */
7403 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7404                                void *priv)
7405 {
7406         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7407         struct timekeeper *tk = priv;
7408
7409         update_pvclock_gtod(tk);
7410
7411         /* disable master clock if host does not trust, or does not
7412          * use, TSC based clocksource.
7413          */
7414         if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7415             atomic_read(&kvm_guest_has_master_clock) != 0)
7416                 queue_work(system_long_wq, &pvclock_gtod_work);
7417
7418         return 0;
7419 }
7420
7421 static struct notifier_block pvclock_gtod_notifier = {
7422         .notifier_call = pvclock_gtod_notify,
7423 };
7424 #endif
7425
7426 int kvm_arch_init(void *opaque)
7427 {
7428         struct kvm_x86_init_ops *ops = opaque;
7429         int r;
7430
7431         if (kvm_x86_ops.hardware_enable) {
7432                 printk(KERN_ERR "kvm: already loaded the other module\n");
7433                 r = -EEXIST;
7434                 goto out;
7435         }
7436
7437         if (!ops->cpu_has_kvm_support()) {
7438                 pr_err_ratelimited("kvm: no hardware support\n");
7439                 r = -EOPNOTSUPP;
7440                 goto out;
7441         }
7442         if (ops->disabled_by_bios()) {
7443                 pr_err_ratelimited("kvm: disabled by bios\n");
7444                 r = -EOPNOTSUPP;
7445                 goto out;
7446         }
7447
7448         /*
7449          * KVM explicitly assumes that the guest has an FPU and
7450          * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7451          * vCPU's FPU state as a fxregs_state struct.
7452          */
7453         if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7454                 printk(KERN_ERR "kvm: inadequate fpu\n");
7455                 r = -EOPNOTSUPP;
7456                 goto out;
7457         }
7458
7459         r = -ENOMEM;
7460         x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7461                                           __alignof__(struct fpu), SLAB_ACCOUNT,
7462                                           NULL);
7463         if (!x86_fpu_cache) {
7464                 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7465                 goto out;
7466         }
7467
7468         x86_emulator_cache = kvm_alloc_emulator_cache();
7469         if (!x86_emulator_cache) {
7470                 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7471                 goto out_free_x86_fpu_cache;
7472         }
7473
7474         shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7475         if (!shared_msrs) {
7476                 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7477                 goto out_free_x86_emulator_cache;
7478         }
7479
7480         r = kvm_mmu_module_init();
7481         if (r)
7482                 goto out_free_percpu;
7483
7484         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7485                         PT_DIRTY_MASK, PT64_NX_MASK, 0,
7486                         PT_PRESENT_MASK, 0, sme_me_mask);
7487         kvm_timer_init();
7488
7489         perf_register_guest_info_callbacks(&kvm_guest_cbs);
7490
7491         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7492                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7493                 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7494         }
7495
7496         kvm_lapic_init();
7497         if (pi_inject_timer == -1)
7498                 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7499 #ifdef CONFIG_X86_64
7500         pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7501
7502         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7503                 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7504 #endif
7505
7506         return 0;
7507
7508 out_free_percpu:
7509         free_percpu(shared_msrs);
7510 out_free_x86_emulator_cache:
7511         kmem_cache_destroy(x86_emulator_cache);
7512 out_free_x86_fpu_cache:
7513         kmem_cache_destroy(x86_fpu_cache);
7514 out:
7515         return r;
7516 }
7517
7518 void kvm_arch_exit(void)
7519 {
7520 #ifdef CONFIG_X86_64
7521         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7522                 clear_hv_tscchange_cb();
7523 #endif
7524         kvm_lapic_exit();
7525         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7526
7527         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7528                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7529                                             CPUFREQ_TRANSITION_NOTIFIER);
7530         cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7531 #ifdef CONFIG_X86_64
7532         pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7533 #endif
7534         kvm_x86_ops.hardware_enable = NULL;
7535         kvm_mmu_module_exit();
7536         free_percpu(shared_msrs);
7537         kmem_cache_destroy(x86_fpu_cache);
7538 }
7539
7540 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7541 {
7542         ++vcpu->stat.halt_exits;
7543         if (lapic_in_kernel(vcpu)) {
7544                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7545                 return 1;
7546         } else {
7547                 vcpu->run->exit_reason = KVM_EXIT_HLT;
7548                 return 0;
7549         }
7550 }
7551 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7552
7553 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7554 {
7555         int ret = kvm_skip_emulated_instruction(vcpu);
7556         /*
7557          * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7558          * KVM_EXIT_DEBUG here.
7559          */
7560         return kvm_vcpu_halt(vcpu) && ret;
7561 }
7562 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7563
7564 #ifdef CONFIG_X86_64
7565 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7566                                 unsigned long clock_type)
7567 {
7568         struct kvm_clock_pairing clock_pairing;
7569         struct timespec64 ts;
7570         u64 cycle;
7571         int ret;
7572
7573         if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7574                 return -KVM_EOPNOTSUPP;
7575
7576         if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7577                 return -KVM_EOPNOTSUPP;
7578
7579         clock_pairing.sec = ts.tv_sec;
7580         clock_pairing.nsec = ts.tv_nsec;
7581         clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7582         clock_pairing.flags = 0;
7583         memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7584
7585         ret = 0;
7586         if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7587                             sizeof(struct kvm_clock_pairing)))
7588                 ret = -KVM_EFAULT;
7589
7590         return ret;
7591 }
7592 #endif
7593
7594 /*
7595  * kvm_pv_kick_cpu_op:  Kick a vcpu.
7596  *
7597  * @apicid - apicid of vcpu to be kicked.
7598  */
7599 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7600 {
7601         struct kvm_lapic_irq lapic_irq;
7602
7603         lapic_irq.shorthand = APIC_DEST_NOSHORT;
7604         lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
7605         lapic_irq.level = 0;
7606         lapic_irq.dest_id = apicid;
7607         lapic_irq.msi_redir_hint = false;
7608
7609         lapic_irq.delivery_mode = APIC_DM_REMRD;
7610         kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7611 }
7612
7613 bool kvm_apicv_activated(struct kvm *kvm)
7614 {
7615         return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
7616 }
7617 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
7618
7619 void kvm_apicv_init(struct kvm *kvm, bool enable)
7620 {
7621         if (enable)
7622                 clear_bit(APICV_INHIBIT_REASON_DISABLE,
7623                           &kvm->arch.apicv_inhibit_reasons);
7624         else
7625                 set_bit(APICV_INHIBIT_REASON_DISABLE,
7626                         &kvm->arch.apicv_inhibit_reasons);
7627 }
7628 EXPORT_SYMBOL_GPL(kvm_apicv_init);
7629
7630 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7631 {
7632         struct kvm_vcpu *target = NULL;
7633         struct kvm_apic_map *map;
7634
7635         rcu_read_lock();
7636         map = rcu_dereference(kvm->arch.apic_map);
7637
7638         if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7639                 target = map->phys_map[dest_id]->vcpu;
7640
7641         rcu_read_unlock();
7642
7643         if (target && READ_ONCE(target->ready))
7644                 kvm_vcpu_yield_to(target);
7645 }
7646
7647 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7648 {
7649         unsigned long nr, a0, a1, a2, a3, ret;
7650         int op_64_bit;
7651
7652         if (kvm_hv_hypercall_enabled(vcpu->kvm))
7653                 return kvm_hv_hypercall(vcpu);
7654
7655         nr = kvm_rax_read(vcpu);
7656         a0 = kvm_rbx_read(vcpu);
7657         a1 = kvm_rcx_read(vcpu);
7658         a2 = kvm_rdx_read(vcpu);
7659         a3 = kvm_rsi_read(vcpu);
7660
7661         trace_kvm_hypercall(nr, a0, a1, a2, a3);
7662
7663         op_64_bit = is_64_bit_mode(vcpu);
7664         if (!op_64_bit) {
7665                 nr &= 0xFFFFFFFF;
7666                 a0 &= 0xFFFFFFFF;
7667                 a1 &= 0xFFFFFFFF;
7668                 a2 &= 0xFFFFFFFF;
7669                 a3 &= 0xFFFFFFFF;
7670         }
7671
7672         if (kvm_x86_ops.get_cpl(vcpu) != 0) {
7673                 ret = -KVM_EPERM;
7674                 goto out;
7675         }
7676
7677         switch (nr) {
7678         case KVM_HC_VAPIC_POLL_IRQ:
7679                 ret = 0;
7680                 break;
7681         case KVM_HC_KICK_CPU:
7682                 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7683                 kvm_sched_yield(vcpu->kvm, a1);
7684                 ret = 0;
7685                 break;
7686 #ifdef CONFIG_X86_64
7687         case KVM_HC_CLOCK_PAIRING:
7688                 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7689                 break;
7690 #endif
7691         case KVM_HC_SEND_IPI:
7692                 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7693                 break;
7694         case KVM_HC_SCHED_YIELD:
7695                 kvm_sched_yield(vcpu->kvm, a0);
7696                 ret = 0;
7697                 break;
7698         default:
7699                 ret = -KVM_ENOSYS;
7700                 break;
7701         }
7702 out:
7703         if (!op_64_bit)
7704                 ret = (u32)ret;
7705         kvm_rax_write(vcpu, ret);
7706
7707         ++vcpu->stat.hypercalls;
7708         return kvm_skip_emulated_instruction(vcpu);
7709 }
7710 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7711
7712 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7713 {
7714         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7715         char instruction[3];
7716         unsigned long rip = kvm_rip_read(vcpu);
7717
7718         kvm_x86_ops.patch_hypercall(vcpu, instruction);
7719
7720         return emulator_write_emulated(ctxt, rip, instruction, 3,
7721                 &ctxt->exception);
7722 }
7723
7724 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7725 {
7726         return vcpu->run->request_interrupt_window &&
7727                 likely(!pic_in_kernel(vcpu->kvm));
7728 }
7729
7730 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7731 {
7732         struct kvm_run *kvm_run = vcpu->run;
7733
7734         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7735         kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7736         kvm_run->cr8 = kvm_get_cr8(vcpu);
7737         kvm_run->apic_base = kvm_get_apic_base(vcpu);
7738         kvm_run->ready_for_interrupt_injection =
7739                 pic_in_kernel(vcpu->kvm) ||
7740                 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7741 }
7742
7743 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7744 {
7745         int max_irr, tpr;
7746
7747         if (!kvm_x86_ops.update_cr8_intercept)
7748                 return;
7749
7750         if (!lapic_in_kernel(vcpu))
7751                 return;
7752
7753         if (vcpu->arch.apicv_active)
7754                 return;
7755
7756         if (!vcpu->arch.apic->vapic_addr)
7757                 max_irr = kvm_lapic_find_highest_irr(vcpu);
7758         else
7759                 max_irr = -1;
7760
7761         if (max_irr != -1)
7762                 max_irr >>= 4;
7763
7764         tpr = kvm_lapic_get_cr8(vcpu);
7765
7766         kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr);
7767 }
7768
7769 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
7770 {
7771         int r;
7772         bool can_inject = true;
7773
7774         /* try to reinject previous events if any */
7775
7776         if (vcpu->arch.exception.injected) {
7777                 kvm_x86_ops.queue_exception(vcpu);
7778                 can_inject = false;
7779         }
7780         /*
7781          * Do not inject an NMI or interrupt if there is a pending
7782          * exception.  Exceptions and interrupts are recognized at
7783          * instruction boundaries, i.e. the start of an instruction.
7784          * Trap-like exceptions, e.g. #DB, have higher priority than
7785          * NMIs and interrupts, i.e. traps are recognized before an
7786          * NMI/interrupt that's pending on the same instruction.
7787          * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7788          * priority, but are only generated (pended) during instruction
7789          * execution, i.e. a pending fault-like exception means the
7790          * fault occurred on the *previous* instruction and must be
7791          * serviced prior to recognizing any new events in order to
7792          * fully complete the previous instruction.
7793          */
7794         else if (!vcpu->arch.exception.pending) {
7795                 if (vcpu->arch.nmi_injected) {
7796                         kvm_x86_ops.set_nmi(vcpu);
7797                         can_inject = false;
7798                 } else if (vcpu->arch.interrupt.injected) {
7799                         kvm_x86_ops.set_irq(vcpu);
7800                         can_inject = false;
7801                 }
7802         }
7803
7804         WARN_ON_ONCE(vcpu->arch.exception.injected &&
7805                      vcpu->arch.exception.pending);
7806
7807         /*
7808          * Call check_nested_events() even if we reinjected a previous event
7809          * in order for caller to determine if it should require immediate-exit
7810          * from L2 to L1 due to pending L1 events which require exit
7811          * from L2 to L1.
7812          */
7813         if (is_guest_mode(vcpu)) {
7814                 r = kvm_x86_ops.nested_ops->check_events(vcpu);
7815                 if (r < 0)
7816                         goto busy;
7817         }
7818
7819         /* try to inject new event if pending */
7820         if (vcpu->arch.exception.pending) {
7821                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7822                                         vcpu->arch.exception.has_error_code,
7823                                         vcpu->arch.exception.error_code);
7824
7825                 vcpu->arch.exception.pending = false;
7826                 vcpu->arch.exception.injected = true;
7827
7828                 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7829                         __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7830                                              X86_EFLAGS_RF);
7831
7832                 if (vcpu->arch.exception.nr == DB_VECTOR) {
7833                         kvm_deliver_exception_payload(vcpu);
7834                         if (vcpu->arch.dr7 & DR7_GD) {
7835                                 vcpu->arch.dr7 &= ~DR7_GD;
7836                                 kvm_update_dr7(vcpu);
7837                         }
7838                 }
7839
7840                 kvm_x86_ops.queue_exception(vcpu);
7841                 can_inject = false;
7842         }
7843
7844         /*
7845          * Finally, inject interrupt events.  If an event cannot be injected
7846          * due to architectural conditions (e.g. IF=0) a window-open exit
7847          * will re-request KVM_REQ_EVENT.  Sometimes however an event is pending
7848          * and can architecturally be injected, but we cannot do it right now:
7849          * an interrupt could have arrived just now and we have to inject it
7850          * as a vmexit, or there could already an event in the queue, which is
7851          * indicated by can_inject.  In that case we request an immediate exit
7852          * in order to make progress and get back here for another iteration.
7853          * The kvm_x86_ops hooks communicate this by returning -EBUSY.
7854          */
7855         if (vcpu->arch.smi_pending) {
7856                 r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY;
7857                 if (r < 0)
7858                         goto busy;
7859                 if (r) {
7860                         vcpu->arch.smi_pending = false;
7861                         ++vcpu->arch.smi_count;
7862                         enter_smm(vcpu);
7863                         can_inject = false;
7864                 } else
7865                         kvm_x86_ops.enable_smi_window(vcpu);
7866         }
7867
7868         if (vcpu->arch.nmi_pending) {
7869                 r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY;
7870                 if (r < 0)
7871                         goto busy;
7872                 if (r) {
7873                         --vcpu->arch.nmi_pending;
7874                         vcpu->arch.nmi_injected = true;
7875                         kvm_x86_ops.set_nmi(vcpu);
7876                         can_inject = false;
7877                         WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0);
7878                 }
7879                 if (vcpu->arch.nmi_pending)
7880                         kvm_x86_ops.enable_nmi_window(vcpu);
7881         }
7882
7883         if (kvm_cpu_has_injectable_intr(vcpu)) {
7884                 r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY;
7885                 if (r < 0)
7886                         goto busy;
7887                 if (r) {
7888                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
7889                         kvm_x86_ops.set_irq(vcpu);
7890                         WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0);
7891                 }
7892                 if (kvm_cpu_has_injectable_intr(vcpu))
7893                         kvm_x86_ops.enable_irq_window(vcpu);
7894         }
7895
7896         if (is_guest_mode(vcpu) &&
7897             kvm_x86_ops.nested_ops->hv_timer_pending &&
7898             kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
7899                 *req_immediate_exit = true;
7900
7901         WARN_ON(vcpu->arch.exception.pending);
7902         return;
7903
7904 busy:
7905         *req_immediate_exit = true;
7906         return;
7907 }
7908
7909 static void process_nmi(struct kvm_vcpu *vcpu)
7910 {
7911         unsigned limit = 2;
7912
7913         /*
7914          * x86 is limited to one NMI running, and one NMI pending after it.
7915          * If an NMI is already in progress, limit further NMIs to just one.
7916          * Otherwise, allow two (and we'll inject the first one immediately).
7917          */
7918         if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7919                 limit = 1;
7920
7921         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7922         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7923         kvm_make_request(KVM_REQ_EVENT, vcpu);
7924 }
7925
7926 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7927 {
7928         u32 flags = 0;
7929         flags |= seg->g       << 23;
7930         flags |= seg->db      << 22;
7931         flags |= seg->l       << 21;
7932         flags |= seg->avl     << 20;
7933         flags |= seg->present << 15;
7934         flags |= seg->dpl     << 13;
7935         flags |= seg->s       << 12;
7936         flags |= seg->type    << 8;
7937         return flags;
7938 }
7939
7940 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7941 {
7942         struct kvm_segment seg;
7943         int offset;
7944
7945         kvm_get_segment(vcpu, &seg, n);
7946         put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7947
7948         if (n < 3)
7949                 offset = 0x7f84 + n * 12;
7950         else
7951                 offset = 0x7f2c + (n - 3) * 12;
7952
7953         put_smstate(u32, buf, offset + 8, seg.base);
7954         put_smstate(u32, buf, offset + 4, seg.limit);
7955         put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7956 }
7957
7958 #ifdef CONFIG_X86_64
7959 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7960 {
7961         struct kvm_segment seg;
7962         int offset;
7963         u16 flags;
7964
7965         kvm_get_segment(vcpu, &seg, n);
7966         offset = 0x7e00 + n * 16;
7967
7968         flags = enter_smm_get_segment_flags(&seg) >> 8;
7969         put_smstate(u16, buf, offset, seg.selector);
7970         put_smstate(u16, buf, offset + 2, flags);
7971         put_smstate(u32, buf, offset + 4, seg.limit);
7972         put_smstate(u64, buf, offset + 8, seg.base);
7973 }
7974 #endif
7975
7976 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7977 {
7978         struct desc_ptr dt;
7979         struct kvm_segment seg;
7980         unsigned long val;
7981         int i;
7982
7983         put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7984         put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7985         put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7986         put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7987
7988         for (i = 0; i < 8; i++)
7989                 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7990
7991         kvm_get_dr(vcpu, 6, &val);
7992         put_smstate(u32, buf, 0x7fcc, (u32)val);
7993         kvm_get_dr(vcpu, 7, &val);
7994         put_smstate(u32, buf, 0x7fc8, (u32)val);
7995
7996         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7997         put_smstate(u32, buf, 0x7fc4, seg.selector);
7998         put_smstate(u32, buf, 0x7f64, seg.base);
7999         put_smstate(u32, buf, 0x7f60, seg.limit);
8000         put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
8001
8002         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8003         put_smstate(u32, buf, 0x7fc0, seg.selector);
8004         put_smstate(u32, buf, 0x7f80, seg.base);
8005         put_smstate(u32, buf, 0x7f7c, seg.limit);
8006         put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
8007
8008         kvm_x86_ops.get_gdt(vcpu, &dt);
8009         put_smstate(u32, buf, 0x7f74, dt.address);
8010         put_smstate(u32, buf, 0x7f70, dt.size);
8011
8012         kvm_x86_ops.get_idt(vcpu, &dt);
8013         put_smstate(u32, buf, 0x7f58, dt.address);
8014         put_smstate(u32, buf, 0x7f54, dt.size);
8015
8016         for (i = 0; i < 6; i++)
8017                 enter_smm_save_seg_32(vcpu, buf, i);
8018
8019         put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
8020
8021         /* revision id */
8022         put_smstate(u32, buf, 0x7efc, 0x00020000);
8023         put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
8024 }
8025
8026 #ifdef CONFIG_X86_64
8027 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
8028 {
8029         struct desc_ptr dt;
8030         struct kvm_segment seg;
8031         unsigned long val;
8032         int i;
8033
8034         for (i = 0; i < 16; i++)
8035                 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
8036
8037         put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
8038         put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
8039
8040         kvm_get_dr(vcpu, 6, &val);
8041         put_smstate(u64, buf, 0x7f68, val);
8042         kvm_get_dr(vcpu, 7, &val);
8043         put_smstate(u64, buf, 0x7f60, val);
8044
8045         put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
8046         put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
8047         put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
8048
8049         put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
8050
8051         /* revision id */
8052         put_smstate(u32, buf, 0x7efc, 0x00020064);
8053
8054         put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
8055
8056         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8057         put_smstate(u16, buf, 0x7e90, seg.selector);
8058         put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
8059         put_smstate(u32, buf, 0x7e94, seg.limit);
8060         put_smstate(u64, buf, 0x7e98, seg.base);
8061
8062         kvm_x86_ops.get_idt(vcpu, &dt);
8063         put_smstate(u32, buf, 0x7e84, dt.size);
8064         put_smstate(u64, buf, 0x7e88, dt.address);
8065
8066         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8067         put_smstate(u16, buf, 0x7e70, seg.selector);
8068         put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
8069         put_smstate(u32, buf, 0x7e74, seg.limit);
8070         put_smstate(u64, buf, 0x7e78, seg.base);
8071
8072         kvm_x86_ops.get_gdt(vcpu, &dt);
8073         put_smstate(u32, buf, 0x7e64, dt.size);
8074         put_smstate(u64, buf, 0x7e68, dt.address);
8075
8076         for (i = 0; i < 6; i++)
8077                 enter_smm_save_seg_64(vcpu, buf, i);
8078 }
8079 #endif
8080
8081 static void enter_smm(struct kvm_vcpu *vcpu)
8082 {
8083         struct kvm_segment cs, ds;
8084         struct desc_ptr dt;
8085         char buf[512];
8086         u32 cr0;
8087
8088         trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
8089         memset(buf, 0, 512);
8090 #ifdef CONFIG_X86_64
8091         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8092                 enter_smm_save_state_64(vcpu, buf);
8093         else
8094 #endif
8095                 enter_smm_save_state_32(vcpu, buf);
8096
8097         /*
8098          * Give pre_enter_smm() a chance to make ISA-specific changes to the
8099          * vCPU state (e.g. leave guest mode) after we've saved the state into
8100          * the SMM state-save area.
8101          */
8102         kvm_x86_ops.pre_enter_smm(vcpu, buf);
8103
8104         vcpu->arch.hflags |= HF_SMM_MASK;
8105         kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
8106
8107         if (kvm_x86_ops.get_nmi_mask(vcpu))
8108                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
8109         else
8110                 kvm_x86_ops.set_nmi_mask(vcpu, true);
8111
8112         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
8113         kvm_rip_write(vcpu, 0x8000);
8114
8115         cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
8116         kvm_x86_ops.set_cr0(vcpu, cr0);
8117         vcpu->arch.cr0 = cr0;
8118
8119         kvm_x86_ops.set_cr4(vcpu, 0);
8120
8121         /* Undocumented: IDT limit is set to zero on entry to SMM.  */
8122         dt.address = dt.size = 0;
8123         kvm_x86_ops.set_idt(vcpu, &dt);
8124
8125         __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
8126
8127         cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
8128         cs.base = vcpu->arch.smbase;
8129
8130         ds.selector = 0;
8131         ds.base = 0;
8132
8133         cs.limit    = ds.limit = 0xffffffff;
8134         cs.type     = ds.type = 0x3;
8135         cs.dpl      = ds.dpl = 0;
8136         cs.db       = ds.db = 0;
8137         cs.s        = ds.s = 1;
8138         cs.l        = ds.l = 0;
8139         cs.g        = ds.g = 1;
8140         cs.avl      = ds.avl = 0;
8141         cs.present  = ds.present = 1;
8142         cs.unusable = ds.unusable = 0;
8143         cs.padding  = ds.padding = 0;
8144
8145         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8146         kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8147         kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8148         kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8149         kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8150         kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8151
8152 #ifdef CONFIG_X86_64
8153         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8154                 kvm_x86_ops.set_efer(vcpu, 0);
8155 #endif
8156
8157         kvm_update_cpuid(vcpu);
8158         kvm_mmu_reset_context(vcpu);
8159 }
8160
8161 static void process_smi(struct kvm_vcpu *vcpu)
8162 {
8163         vcpu->arch.smi_pending = true;
8164         kvm_make_request(KVM_REQ_EVENT, vcpu);
8165 }
8166
8167 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8168                                        unsigned long *vcpu_bitmap)
8169 {
8170         cpumask_var_t cpus;
8171
8172         zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8173
8174         kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8175                                     NULL, vcpu_bitmap, cpus);
8176
8177         free_cpumask_var(cpus);
8178 }
8179
8180 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8181 {
8182         kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8183 }
8184
8185 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8186 {
8187         if (!lapic_in_kernel(vcpu))
8188                 return;
8189
8190         vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8191         kvm_apic_update_apicv(vcpu);
8192         kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu);
8193 }
8194 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8195
8196 /*
8197  * NOTE: Do not hold any lock prior to calling this.
8198  *
8199  * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8200  * locked, because it calls __x86_set_memory_region() which does
8201  * synchronize_srcu(&kvm->srcu).
8202  */
8203 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8204 {
8205         struct kvm_vcpu *except;
8206         unsigned long old, new, expected;
8207
8208         if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8209             !kvm_x86_ops.check_apicv_inhibit_reasons(bit))
8210                 return;
8211
8212         old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8213         do {
8214                 expected = new = old;
8215                 if (activate)
8216                         __clear_bit(bit, &new);
8217                 else
8218                         __set_bit(bit, &new);
8219                 if (new == old)
8220                         break;
8221                 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8222         } while (old != expected);
8223
8224         if (!!old == !!new)
8225                 return;
8226
8227         trace_kvm_apicv_update_request(activate, bit);
8228         if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8229                 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate);
8230
8231         /*
8232          * Sending request to update APICV for all other vcpus,
8233          * while update the calling vcpu immediately instead of
8234          * waiting for another #VMEXIT to handle the request.
8235          */
8236         except = kvm_get_running_vcpu();
8237         kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE,
8238                                          except);
8239         if (except)
8240                 kvm_vcpu_update_apicv(except);
8241 }
8242 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8243
8244 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8245 {
8246         if (!kvm_apic_present(vcpu))
8247                 return;
8248
8249         bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8250
8251         if (irqchip_split(vcpu->kvm))
8252                 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8253         else {
8254                 if (vcpu->arch.apicv_active)
8255                         kvm_x86_ops.sync_pir_to_irr(vcpu);
8256                 if (ioapic_in_kernel(vcpu->kvm))
8257                         kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8258         }
8259
8260         if (is_guest_mode(vcpu))
8261                 vcpu->arch.load_eoi_exitmap_pending = true;
8262         else
8263                 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8264 }
8265
8266 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8267 {
8268         u64 eoi_exit_bitmap[4];
8269
8270         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8271                 return;
8272
8273         bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8274                   vcpu_to_synic(vcpu)->vec_bitmap, 256);
8275         kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8276 }
8277
8278 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8279                                             unsigned long start, unsigned long end)
8280 {
8281         unsigned long apic_address;
8282
8283         /*
8284          * The physical address of apic access page is stored in the VMCS.
8285          * Update it when it becomes invalid.
8286          */
8287         apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8288         if (start <= apic_address && apic_address < end)
8289                 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8290 }
8291
8292 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8293 {
8294         if (!lapic_in_kernel(vcpu))
8295                 return;
8296
8297         if (!kvm_x86_ops.set_apic_access_page_addr)
8298                 return;
8299
8300         kvm_x86_ops.set_apic_access_page_addr(vcpu);
8301 }
8302
8303 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8304 {
8305         smp_send_reschedule(vcpu->cpu);
8306 }
8307 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8308
8309 /*
8310  * Returns 1 to let vcpu_run() continue the guest execution loop without
8311  * exiting to the userspace.  Otherwise, the value will be returned to the
8312  * userspace.
8313  */
8314 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8315 {
8316         int r;
8317         bool req_int_win =
8318                 dm_request_for_irq_injection(vcpu) &&
8319                 kvm_cpu_accept_dm_intr(vcpu);
8320         fastpath_t exit_fastpath;
8321
8322         bool req_immediate_exit = false;
8323
8324         if (kvm_request_pending(vcpu)) {
8325                 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) {
8326                         if (unlikely(!kvm_x86_ops.nested_ops->get_vmcs12_pages(vcpu))) {
8327                                 r = 0;
8328                                 goto out;
8329                         }
8330                 }
8331                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8332                         kvm_mmu_unload(vcpu);
8333                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8334                         __kvm_migrate_timers(vcpu);
8335                 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8336                         kvm_gen_update_masterclock(vcpu->kvm);
8337                 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8338                         kvm_gen_kvmclock_update(vcpu);
8339                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8340                         r = kvm_guest_time_update(vcpu);
8341                         if (unlikely(r))
8342                                 goto out;
8343                 }
8344                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8345                         kvm_mmu_sync_roots(vcpu);
8346                 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8347                         kvm_mmu_load_pgd(vcpu);
8348                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
8349                         kvm_vcpu_flush_tlb_all(vcpu);
8350
8351                         /* Flushing all ASIDs flushes the current ASID... */
8352                         kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
8353                 }
8354                 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
8355                         kvm_vcpu_flush_tlb_current(vcpu);
8356                 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu))
8357                         kvm_vcpu_flush_tlb_guest(vcpu);
8358
8359                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8360                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8361                         r = 0;
8362                         goto out;
8363                 }
8364                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8365                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8366                         vcpu->mmio_needed = 0;
8367                         r = 0;
8368                         goto out;
8369                 }
8370                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8371                         /* Page is swapped out. Do synthetic halt */
8372                         vcpu->arch.apf.halted = true;
8373                         r = 1;
8374                         goto out;
8375                 }
8376                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8377                         record_steal_time(vcpu);
8378                 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8379                         process_smi(vcpu);
8380                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8381                         process_nmi(vcpu);
8382                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8383                         kvm_pmu_handle_event(vcpu);
8384                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8385                         kvm_pmu_deliver_pmi(vcpu);
8386                 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8387                         BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8388                         if (test_bit(vcpu->arch.pending_ioapic_eoi,
8389                                      vcpu->arch.ioapic_handled_vectors)) {
8390                                 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8391                                 vcpu->run->eoi.vector =
8392                                                 vcpu->arch.pending_ioapic_eoi;
8393                                 r = 0;
8394                                 goto out;
8395                         }
8396                 }
8397                 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8398                         vcpu_scan_ioapic(vcpu);
8399                 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8400                         vcpu_load_eoi_exitmap(vcpu);
8401                 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8402                         kvm_vcpu_reload_apic_access_page(vcpu);
8403                 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8404                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8405                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8406                         r = 0;
8407                         goto out;
8408                 }
8409                 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8410                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8411                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8412                         r = 0;
8413                         goto out;
8414                 }
8415                 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8416                         vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8417                         vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8418                         r = 0;
8419                         goto out;
8420                 }
8421
8422                 /*
8423                  * KVM_REQ_HV_STIMER has to be processed after
8424                  * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8425                  * depend on the guest clock being up-to-date
8426                  */
8427                 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8428                         kvm_hv_process_stimers(vcpu);
8429                 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8430                         kvm_vcpu_update_apicv(vcpu);
8431                 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
8432                         kvm_check_async_pf_completion(vcpu);
8433         }
8434
8435         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8436                 ++vcpu->stat.req_event;
8437                 kvm_apic_accept_events(vcpu);
8438                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8439                         r = 1;
8440                         goto out;
8441                 }
8442
8443                 inject_pending_event(vcpu, &req_immediate_exit);
8444                 if (req_int_win)
8445                         kvm_x86_ops.enable_irq_window(vcpu);
8446
8447                 if (kvm_lapic_enabled(vcpu)) {
8448                         update_cr8_intercept(vcpu);
8449                         kvm_lapic_sync_to_vapic(vcpu);
8450                 }
8451         }
8452
8453         r = kvm_mmu_reload(vcpu);
8454         if (unlikely(r)) {
8455                 goto cancel_injection;
8456         }
8457
8458         preempt_disable();
8459
8460         kvm_x86_ops.prepare_guest_switch(vcpu);
8461
8462         /*
8463          * Disable IRQs before setting IN_GUEST_MODE.  Posted interrupt
8464          * IPI are then delayed after guest entry, which ensures that they
8465          * result in virtual interrupt delivery.
8466          */
8467         local_irq_disable();
8468         vcpu->mode = IN_GUEST_MODE;
8469
8470         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8471
8472         /*
8473          * 1) We should set ->mode before checking ->requests.  Please see
8474          * the comment in kvm_vcpu_exiting_guest_mode().
8475          *
8476          * 2) For APICv, we should set ->mode before checking PID.ON. This
8477          * pairs with the memory barrier implicit in pi_test_and_set_on
8478          * (see vmx_deliver_posted_interrupt).
8479          *
8480          * 3) This also orders the write to mode from any reads to the page
8481          * tables done while the VCPU is running.  Please see the comment
8482          * in kvm_flush_remote_tlbs.
8483          */
8484         smp_mb__after_srcu_read_unlock();
8485
8486         /*
8487          * This handles the case where a posted interrupt was
8488          * notified with kvm_vcpu_kick.
8489          */
8490         if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8491                 kvm_x86_ops.sync_pir_to_irr(vcpu);
8492
8493         if (kvm_vcpu_exit_request(vcpu)) {
8494                 vcpu->mode = OUTSIDE_GUEST_MODE;
8495                 smp_wmb();
8496                 local_irq_enable();
8497                 preempt_enable();
8498                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8499                 r = 1;
8500                 goto cancel_injection;
8501         }
8502
8503         if (req_immediate_exit) {
8504                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8505                 kvm_x86_ops.request_immediate_exit(vcpu);
8506         }
8507
8508         trace_kvm_entry(vcpu->vcpu_id);
8509         guest_enter_irqoff();
8510
8511         fpregs_assert_state_consistent();
8512         if (test_thread_flag(TIF_NEED_FPU_LOAD))
8513                 switch_fpu_return();
8514
8515         if (unlikely(vcpu->arch.switch_db_regs)) {
8516                 set_debugreg(0, 7);
8517                 set_debugreg(vcpu->arch.eff_db[0], 0);
8518                 set_debugreg(vcpu->arch.eff_db[1], 1);
8519                 set_debugreg(vcpu->arch.eff_db[2], 2);
8520                 set_debugreg(vcpu->arch.eff_db[3], 3);
8521                 set_debugreg(vcpu->arch.dr6, 6);
8522                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8523         }
8524
8525         exit_fastpath = kvm_x86_ops.run(vcpu);
8526
8527         /*
8528          * Do this here before restoring debug registers on the host.  And
8529          * since we do this before handling the vmexit, a DR access vmexit
8530          * can (a) read the correct value of the debug registers, (b) set
8531          * KVM_DEBUGREG_WONT_EXIT again.
8532          */
8533         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8534                 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8535                 kvm_x86_ops.sync_dirty_debug_regs(vcpu);
8536                 kvm_update_dr0123(vcpu);
8537                 kvm_update_dr7(vcpu);
8538                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8539         }
8540
8541         /*
8542          * If the guest has used debug registers, at least dr7
8543          * will be disabled while returning to the host.
8544          * If we don't have active breakpoints in the host, we don't
8545          * care about the messed up debug address registers. But if
8546          * we have some of them active, restore the old state.
8547          */
8548         if (hw_breakpoint_active())
8549                 hw_breakpoint_restore();
8550
8551         vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8552
8553         vcpu->mode = OUTSIDE_GUEST_MODE;
8554         smp_wmb();
8555
8556         kvm_x86_ops.handle_exit_irqoff(vcpu);
8557
8558         /*
8559          * Consume any pending interrupts, including the possible source of
8560          * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8561          * An instruction is required after local_irq_enable() to fully unblock
8562          * interrupts on processors that implement an interrupt shadow, the
8563          * stat.exits increment will do nicely.
8564          */
8565         kvm_before_interrupt(vcpu);
8566         local_irq_enable();
8567         ++vcpu->stat.exits;
8568         local_irq_disable();
8569         kvm_after_interrupt(vcpu);
8570
8571         guest_exit_irqoff();
8572         if (lapic_in_kernel(vcpu)) {
8573                 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8574                 if (delta != S64_MIN) {
8575                         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8576                         vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8577                 }
8578         }
8579
8580         local_irq_enable();
8581         preempt_enable();
8582
8583         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8584
8585         /*
8586          * Profile KVM exit RIPs:
8587          */
8588         if (unlikely(prof_on == KVM_PROFILING)) {
8589                 unsigned long rip = kvm_rip_read(vcpu);
8590                 profile_hit(KVM_PROFILING, (void *)rip);
8591         }
8592
8593         if (unlikely(vcpu->arch.tsc_always_catchup))
8594                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8595
8596         if (vcpu->arch.apic_attention)
8597                 kvm_lapic_sync_from_vapic(vcpu);
8598
8599         r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath);
8600         return r;
8601
8602 cancel_injection:
8603         if (req_immediate_exit)
8604                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8605         kvm_x86_ops.cancel_injection(vcpu);
8606         if (unlikely(vcpu->arch.apic_attention))
8607                 kvm_lapic_sync_from_vapic(vcpu);
8608 out:
8609         return r;
8610 }
8611
8612 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8613 {
8614         if (!kvm_arch_vcpu_runnable(vcpu) &&
8615             (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) {
8616                 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8617                 kvm_vcpu_block(vcpu);
8618                 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8619
8620                 if (kvm_x86_ops.post_block)
8621                         kvm_x86_ops.post_block(vcpu);
8622
8623                 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8624                         return 1;
8625         }
8626
8627         kvm_apic_accept_events(vcpu);
8628         switch(vcpu->arch.mp_state) {
8629         case KVM_MP_STATE_HALTED:
8630                 vcpu->arch.pv.pv_unhalted = false;
8631                 vcpu->arch.mp_state =
8632                         KVM_MP_STATE_RUNNABLE;
8633                 /* fall through */
8634         case KVM_MP_STATE_RUNNABLE:
8635                 vcpu->arch.apf.halted = false;
8636                 break;
8637         case KVM_MP_STATE_INIT_RECEIVED:
8638                 break;
8639         default:
8640                 return -EINTR;
8641         }
8642         return 1;
8643 }
8644
8645 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8646 {
8647         if (is_guest_mode(vcpu))
8648                 kvm_x86_ops.nested_ops->check_events(vcpu);
8649
8650         return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8651                 !vcpu->arch.apf.halted);
8652 }
8653
8654 static int vcpu_run(struct kvm_vcpu *vcpu)
8655 {
8656         int r;
8657         struct kvm *kvm = vcpu->kvm;
8658
8659         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8660         vcpu->arch.l1tf_flush_l1d = true;
8661
8662         for (;;) {
8663                 if (kvm_vcpu_running(vcpu)) {
8664                         r = vcpu_enter_guest(vcpu);
8665                 } else {
8666                         r = vcpu_block(kvm, vcpu);
8667                 }
8668
8669                 if (r <= 0)
8670                         break;
8671
8672                 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8673                 if (kvm_cpu_has_pending_timer(vcpu))
8674                         kvm_inject_pending_timer_irqs(vcpu);
8675
8676                 if (dm_request_for_irq_injection(vcpu) &&
8677                         kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8678                         r = 0;
8679                         vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8680                         ++vcpu->stat.request_irq_exits;
8681                         break;
8682                 }
8683
8684                 if (signal_pending(current)) {
8685                         r = -EINTR;
8686                         vcpu->run->exit_reason = KVM_EXIT_INTR;
8687                         ++vcpu->stat.signal_exits;
8688                         break;
8689                 }
8690                 if (need_resched()) {
8691                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8692                         cond_resched();
8693                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8694                 }
8695         }
8696
8697         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8698
8699         return r;
8700 }
8701
8702 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8703 {
8704         int r;
8705
8706         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8707         r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8708         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8709         return r;
8710 }
8711
8712 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8713 {
8714         BUG_ON(!vcpu->arch.pio.count);
8715
8716         return complete_emulated_io(vcpu);
8717 }
8718
8719 /*
8720  * Implements the following, as a state machine:
8721  *
8722  * read:
8723  *   for each fragment
8724  *     for each mmio piece in the fragment
8725  *       write gpa, len
8726  *       exit
8727  *       copy data
8728  *   execute insn
8729  *
8730  * write:
8731  *   for each fragment
8732  *     for each mmio piece in the fragment
8733  *       write gpa, len
8734  *       copy data
8735  *       exit
8736  */
8737 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8738 {
8739         struct kvm_run *run = vcpu->run;
8740         struct kvm_mmio_fragment *frag;
8741         unsigned len;
8742
8743         BUG_ON(!vcpu->mmio_needed);
8744
8745         /* Complete previous fragment */
8746         frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8747         len = min(8u, frag->len);
8748         if (!vcpu->mmio_is_write)
8749                 memcpy(frag->data, run->mmio.data, len);
8750
8751         if (frag->len <= 8) {
8752                 /* Switch to the next fragment. */
8753                 frag++;
8754                 vcpu->mmio_cur_fragment++;
8755         } else {
8756                 /* Go forward to the next mmio piece. */
8757                 frag->data += len;
8758                 frag->gpa += len;
8759                 frag->len -= len;
8760         }
8761
8762         if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8763                 vcpu->mmio_needed = 0;
8764
8765                 /* FIXME: return into emulator if single-stepping.  */
8766                 if (vcpu->mmio_is_write)
8767                         return 1;
8768                 vcpu->mmio_read_completed = 1;
8769                 return complete_emulated_io(vcpu);
8770         }
8771
8772         run->exit_reason = KVM_EXIT_MMIO;
8773         run->mmio.phys_addr = frag->gpa;
8774         if (vcpu->mmio_is_write)
8775                 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8776         run->mmio.len = min(8u, frag->len);
8777         run->mmio.is_write = vcpu->mmio_is_write;
8778         vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8779         return 0;
8780 }
8781
8782 static void kvm_save_current_fpu(struct fpu *fpu)
8783 {
8784         /*
8785          * If the target FPU state is not resident in the CPU registers, just
8786          * memcpy() from current, else save CPU state directly to the target.
8787          */
8788         if (test_thread_flag(TIF_NEED_FPU_LOAD))
8789                 memcpy(&fpu->state, &current->thread.fpu.state,
8790                        fpu_kernel_xstate_size);
8791         else
8792                 copy_fpregs_to_fpstate(fpu);
8793 }
8794
8795 /* Swap (qemu) user FPU context for the guest FPU context. */
8796 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8797 {
8798         fpregs_lock();
8799
8800         kvm_save_current_fpu(vcpu->arch.user_fpu);
8801
8802         /* PKRU is separately restored in kvm_x86_ops.run.  */
8803         __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8804                                 ~XFEATURE_MASK_PKRU);
8805
8806         fpregs_mark_activate();
8807         fpregs_unlock();
8808
8809         trace_kvm_fpu(1);
8810 }
8811
8812 /* When vcpu_run ends, restore user space FPU context. */
8813 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8814 {
8815         fpregs_lock();
8816
8817         kvm_save_current_fpu(vcpu->arch.guest_fpu);
8818
8819         copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8820
8821         fpregs_mark_activate();
8822         fpregs_unlock();
8823
8824         ++vcpu->stat.fpu_reload;
8825         trace_kvm_fpu(0);
8826 }
8827
8828 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
8829 {
8830         struct kvm_run *kvm_run = vcpu->run;
8831         int r;
8832
8833         vcpu_load(vcpu);
8834         kvm_sigset_activate(vcpu);
8835         kvm_load_guest_fpu(vcpu);
8836
8837         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8838                 if (kvm_run->immediate_exit) {
8839                         r = -EINTR;
8840                         goto out;
8841                 }
8842                 kvm_vcpu_block(vcpu);
8843                 kvm_apic_accept_events(vcpu);
8844                 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8845                 r = -EAGAIN;
8846                 if (signal_pending(current)) {
8847                         r = -EINTR;
8848                         kvm_run->exit_reason = KVM_EXIT_INTR;
8849                         ++vcpu->stat.signal_exits;
8850                 }
8851                 goto out;
8852         }
8853
8854         if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8855                 r = -EINVAL;
8856                 goto out;
8857         }
8858
8859         if (kvm_run->kvm_dirty_regs) {
8860                 r = sync_regs(vcpu);
8861                 if (r != 0)
8862                         goto out;
8863         }
8864
8865         /* re-sync apic's tpr */
8866         if (!lapic_in_kernel(vcpu)) {
8867                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8868                         r = -EINVAL;
8869                         goto out;
8870                 }
8871         }
8872
8873         if (unlikely(vcpu->arch.complete_userspace_io)) {
8874                 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8875                 vcpu->arch.complete_userspace_io = NULL;
8876                 r = cui(vcpu);
8877                 if (r <= 0)
8878                         goto out;
8879         } else
8880                 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8881
8882         if (kvm_run->immediate_exit)
8883                 r = -EINTR;
8884         else
8885                 r = vcpu_run(vcpu);
8886
8887 out:
8888         kvm_put_guest_fpu(vcpu);
8889         if (kvm_run->kvm_valid_regs)
8890                 store_regs(vcpu);
8891         post_kvm_run_save(vcpu);
8892         kvm_sigset_deactivate(vcpu);
8893
8894         vcpu_put(vcpu);
8895         return r;
8896 }
8897
8898 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8899 {
8900         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8901                 /*
8902                  * We are here if userspace calls get_regs() in the middle of
8903                  * instruction emulation. Registers state needs to be copied
8904                  * back from emulation context to vcpu. Userspace shouldn't do
8905                  * that usually, but some bad designed PV devices (vmware
8906                  * backdoor interface) need this to work
8907                  */
8908                 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
8909                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8910         }
8911         regs->rax = kvm_rax_read(vcpu);
8912         regs->rbx = kvm_rbx_read(vcpu);
8913         regs->rcx = kvm_rcx_read(vcpu);
8914         regs->rdx = kvm_rdx_read(vcpu);
8915         regs->rsi = kvm_rsi_read(vcpu);
8916         regs->rdi = kvm_rdi_read(vcpu);
8917         regs->rsp = kvm_rsp_read(vcpu);
8918         regs->rbp = kvm_rbp_read(vcpu);
8919 #ifdef CONFIG_X86_64
8920         regs->r8 = kvm_r8_read(vcpu);
8921         regs->r9 = kvm_r9_read(vcpu);
8922         regs->r10 = kvm_r10_read(vcpu);
8923         regs->r11 = kvm_r11_read(vcpu);
8924         regs->r12 = kvm_r12_read(vcpu);
8925         regs->r13 = kvm_r13_read(vcpu);
8926         regs->r14 = kvm_r14_read(vcpu);
8927         regs->r15 = kvm_r15_read(vcpu);
8928 #endif
8929
8930         regs->rip = kvm_rip_read(vcpu);
8931         regs->rflags = kvm_get_rflags(vcpu);
8932 }
8933
8934 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8935 {
8936         vcpu_load(vcpu);
8937         __get_regs(vcpu, regs);
8938         vcpu_put(vcpu);
8939         return 0;
8940 }
8941
8942 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8943 {
8944         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8945         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8946
8947         kvm_rax_write(vcpu, regs->rax);
8948         kvm_rbx_write(vcpu, regs->rbx);
8949         kvm_rcx_write(vcpu, regs->rcx);
8950         kvm_rdx_write(vcpu, regs->rdx);
8951         kvm_rsi_write(vcpu, regs->rsi);
8952         kvm_rdi_write(vcpu, regs->rdi);
8953         kvm_rsp_write(vcpu, regs->rsp);
8954         kvm_rbp_write(vcpu, regs->rbp);
8955 #ifdef CONFIG_X86_64
8956         kvm_r8_write(vcpu, regs->r8);
8957         kvm_r9_write(vcpu, regs->r9);
8958         kvm_r10_write(vcpu, regs->r10);
8959         kvm_r11_write(vcpu, regs->r11);
8960         kvm_r12_write(vcpu, regs->r12);
8961         kvm_r13_write(vcpu, regs->r13);
8962         kvm_r14_write(vcpu, regs->r14);
8963         kvm_r15_write(vcpu, regs->r15);
8964 #endif
8965
8966         kvm_rip_write(vcpu, regs->rip);
8967         kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8968
8969         vcpu->arch.exception.pending = false;
8970
8971         kvm_make_request(KVM_REQ_EVENT, vcpu);
8972 }
8973
8974 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8975 {
8976         vcpu_load(vcpu);
8977         __set_regs(vcpu, regs);
8978         vcpu_put(vcpu);
8979         return 0;
8980 }
8981
8982 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8983 {
8984         struct kvm_segment cs;
8985
8986         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8987         *db = cs.db;
8988         *l = cs.l;
8989 }
8990 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8991
8992 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8993 {
8994         struct desc_ptr dt;
8995
8996         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8997         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8998         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8999         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9000         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9001         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9002
9003         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9004         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9005
9006         kvm_x86_ops.get_idt(vcpu, &dt);
9007         sregs->idt.limit = dt.size;
9008         sregs->idt.base = dt.address;
9009         kvm_x86_ops.get_gdt(vcpu, &dt);
9010         sregs->gdt.limit = dt.size;
9011         sregs->gdt.base = dt.address;
9012
9013         sregs->cr0 = kvm_read_cr0(vcpu);
9014         sregs->cr2 = vcpu->arch.cr2;
9015         sregs->cr3 = kvm_read_cr3(vcpu);
9016         sregs->cr4 = kvm_read_cr4(vcpu);
9017         sregs->cr8 = kvm_get_cr8(vcpu);
9018         sregs->efer = vcpu->arch.efer;
9019         sregs->apic_base = kvm_get_apic_base(vcpu);
9020
9021         memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
9022
9023         if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
9024                 set_bit(vcpu->arch.interrupt.nr,
9025                         (unsigned long *)sregs->interrupt_bitmap);
9026 }
9027
9028 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
9029                                   struct kvm_sregs *sregs)
9030 {
9031         vcpu_load(vcpu);
9032         __get_sregs(vcpu, sregs);
9033         vcpu_put(vcpu);
9034         return 0;
9035 }
9036
9037 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
9038                                     struct kvm_mp_state *mp_state)
9039 {
9040         vcpu_load(vcpu);
9041         if (kvm_mpx_supported())
9042                 kvm_load_guest_fpu(vcpu);
9043
9044         kvm_apic_accept_events(vcpu);
9045         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
9046                                         vcpu->arch.pv.pv_unhalted)
9047                 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
9048         else
9049                 mp_state->mp_state = vcpu->arch.mp_state;
9050
9051         if (kvm_mpx_supported())
9052                 kvm_put_guest_fpu(vcpu);
9053         vcpu_put(vcpu);
9054         return 0;
9055 }
9056
9057 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
9058                                     struct kvm_mp_state *mp_state)
9059 {
9060         int ret = -EINVAL;
9061
9062         vcpu_load(vcpu);
9063
9064         if (!lapic_in_kernel(vcpu) &&
9065             mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
9066                 goto out;
9067
9068         /*
9069          * KVM_MP_STATE_INIT_RECEIVED means the processor is in
9070          * INIT state; latched init should be reported using
9071          * KVM_SET_VCPU_EVENTS, so reject it here.
9072          */
9073         if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
9074             (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
9075              mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
9076                 goto out;
9077
9078         if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
9079                 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
9080                 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
9081         } else
9082                 vcpu->arch.mp_state = mp_state->mp_state;
9083         kvm_make_request(KVM_REQ_EVENT, vcpu);
9084
9085         ret = 0;
9086 out:
9087         vcpu_put(vcpu);
9088         return ret;
9089 }
9090
9091 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
9092                     int reason, bool has_error_code, u32 error_code)
9093 {
9094         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9095         int ret;
9096
9097         init_emulate_ctxt(vcpu);
9098
9099         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9100                                    has_error_code, error_code);
9101         if (ret) {
9102                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9103                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
9104                 vcpu->run->internal.ndata = 0;
9105                 return 0;
9106         }
9107
9108         kvm_rip_write(vcpu, ctxt->eip);
9109         kvm_set_rflags(vcpu, ctxt->eflags);
9110         return 1;
9111 }
9112 EXPORT_SYMBOL_GPL(kvm_task_switch);
9113
9114 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9115 {
9116         if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
9117                 /*
9118                  * When EFER.LME and CR0.PG are set, the processor is in
9119                  * 64-bit mode (though maybe in a 32-bit code segment).
9120                  * CR4.PAE and EFER.LMA must be set.
9121                  */
9122                 if (!(sregs->cr4 & X86_CR4_PAE)
9123                     || !(sregs->efer & EFER_LMA))
9124                         return -EINVAL;
9125         } else {
9126                 /*
9127                  * Not in 64-bit mode: EFER.LMA is clear and the code
9128                  * segment cannot be 64-bit.
9129                  */
9130                 if (sregs->efer & EFER_LMA || sregs->cs.l)
9131                         return -EINVAL;
9132         }
9133
9134         return kvm_valid_cr4(vcpu, sregs->cr4);
9135 }
9136
9137 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9138 {
9139         struct msr_data apic_base_msr;
9140         int mmu_reset_needed = 0;
9141         int cpuid_update_needed = 0;
9142         int pending_vec, max_bits, idx;
9143         struct desc_ptr dt;
9144         int ret = -EINVAL;
9145
9146         if (kvm_valid_sregs(vcpu, sregs))
9147                 goto out;
9148
9149         apic_base_msr.data = sregs->apic_base;
9150         apic_base_msr.host_initiated = true;
9151         if (kvm_set_apic_base(vcpu, &apic_base_msr))
9152                 goto out;
9153
9154         dt.size = sregs->idt.limit;
9155         dt.address = sregs->idt.base;
9156         kvm_x86_ops.set_idt(vcpu, &dt);
9157         dt.size = sregs->gdt.limit;
9158         dt.address = sregs->gdt.base;
9159         kvm_x86_ops.set_gdt(vcpu, &dt);
9160
9161         vcpu->arch.cr2 = sregs->cr2;
9162         mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9163         vcpu->arch.cr3 = sregs->cr3;
9164         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9165
9166         kvm_set_cr8(vcpu, sregs->cr8);
9167
9168         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9169         kvm_x86_ops.set_efer(vcpu, sregs->efer);
9170
9171         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9172         kvm_x86_ops.set_cr0(vcpu, sregs->cr0);
9173         vcpu->arch.cr0 = sregs->cr0;
9174
9175         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9176         cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
9177                                 (X86_CR4_OSXSAVE | X86_CR4_PKE));
9178         kvm_x86_ops.set_cr4(vcpu, sregs->cr4);
9179         if (cpuid_update_needed)
9180                 kvm_update_cpuid(vcpu);
9181
9182         idx = srcu_read_lock(&vcpu->kvm->srcu);
9183         if (is_pae_paging(vcpu)) {
9184                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9185                 mmu_reset_needed = 1;
9186         }
9187         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9188
9189         if (mmu_reset_needed)
9190                 kvm_mmu_reset_context(vcpu);
9191
9192         max_bits = KVM_NR_INTERRUPTS;
9193         pending_vec = find_first_bit(
9194                 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9195         if (pending_vec < max_bits) {
9196                 kvm_queue_interrupt(vcpu, pending_vec, false);
9197                 pr_debug("Set back pending irq %d\n", pending_vec);
9198         }
9199
9200         kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9201         kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9202         kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9203         kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9204         kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9205         kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9206
9207         kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9208         kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9209
9210         update_cr8_intercept(vcpu);
9211
9212         /* Older userspace won't unhalt the vcpu on reset. */
9213         if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9214             sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9215             !is_protmode(vcpu))
9216                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9217
9218         kvm_make_request(KVM_REQ_EVENT, vcpu);
9219
9220         ret = 0;
9221 out:
9222         return ret;
9223 }
9224
9225 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9226                                   struct kvm_sregs *sregs)
9227 {
9228         int ret;
9229
9230         vcpu_load(vcpu);
9231         ret = __set_sregs(vcpu, sregs);
9232         vcpu_put(vcpu);
9233         return ret;
9234 }
9235
9236 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9237                                         struct kvm_guest_debug *dbg)
9238 {
9239         unsigned long rflags;
9240         int i, r;
9241
9242         vcpu_load(vcpu);
9243
9244         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9245                 r = -EBUSY;
9246                 if (vcpu->arch.exception.pending)
9247                         goto out;
9248                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9249                         kvm_queue_exception(vcpu, DB_VECTOR);
9250                 else
9251                         kvm_queue_exception(vcpu, BP_VECTOR);
9252         }
9253
9254         /*
9255          * Read rflags as long as potentially injected trace flags are still
9256          * filtered out.
9257          */
9258         rflags = kvm_get_rflags(vcpu);
9259
9260         vcpu->guest_debug = dbg->control;
9261         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9262                 vcpu->guest_debug = 0;
9263
9264         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9265                 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9266                         vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9267                 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9268         } else {
9269                 for (i = 0; i < KVM_NR_DB_REGS; i++)
9270                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9271         }
9272         kvm_update_dr7(vcpu);
9273
9274         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9275                 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9276                         get_segment_base(vcpu, VCPU_SREG_CS);
9277
9278         /*
9279          * Trigger an rflags update that will inject or remove the trace
9280          * flags.
9281          */
9282         kvm_set_rflags(vcpu, rflags);
9283
9284         kvm_x86_ops.update_bp_intercept(vcpu);
9285
9286         r = 0;
9287
9288 out:
9289         vcpu_put(vcpu);
9290         return r;
9291 }
9292
9293 /*
9294  * Translate a guest virtual address to a guest physical address.
9295  */
9296 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9297                                     struct kvm_translation *tr)
9298 {
9299         unsigned long vaddr = tr->linear_address;
9300         gpa_t gpa;
9301         int idx;
9302
9303         vcpu_load(vcpu);
9304
9305         idx = srcu_read_lock(&vcpu->kvm->srcu);
9306         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9307         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9308         tr->physical_address = gpa;
9309         tr->valid = gpa != UNMAPPED_GVA;
9310         tr->writeable = 1;
9311         tr->usermode = 0;
9312
9313         vcpu_put(vcpu);
9314         return 0;
9315 }
9316
9317 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9318 {
9319         struct fxregs_state *fxsave;
9320
9321         vcpu_load(vcpu);
9322
9323         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9324         memcpy(fpu->fpr, fxsave->st_space, 128);
9325         fpu->fcw = fxsave->cwd;
9326         fpu->fsw = fxsave->swd;
9327         fpu->ftwx = fxsave->twd;
9328         fpu->last_opcode = fxsave->fop;
9329         fpu->last_ip = fxsave->rip;
9330         fpu->last_dp = fxsave->rdp;
9331         memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9332
9333         vcpu_put(vcpu);
9334         return 0;
9335 }
9336
9337 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9338 {
9339         struct fxregs_state *fxsave;
9340
9341         vcpu_load(vcpu);
9342
9343         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9344
9345         memcpy(fxsave->st_space, fpu->fpr, 128);
9346         fxsave->cwd = fpu->fcw;
9347         fxsave->swd = fpu->fsw;
9348         fxsave->twd = fpu->ftwx;
9349         fxsave->fop = fpu->last_opcode;
9350         fxsave->rip = fpu->last_ip;
9351         fxsave->rdp = fpu->last_dp;
9352         memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9353
9354         vcpu_put(vcpu);
9355         return 0;
9356 }
9357
9358 static void store_regs(struct kvm_vcpu *vcpu)
9359 {
9360         BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9361
9362         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9363                 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9364
9365         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9366                 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9367
9368         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9369                 kvm_vcpu_ioctl_x86_get_vcpu_events(
9370                                 vcpu, &vcpu->run->s.regs.events);
9371 }
9372
9373 static int sync_regs(struct kvm_vcpu *vcpu)
9374 {
9375         if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9376                 return -EINVAL;
9377
9378         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9379                 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9380                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9381         }
9382         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9383                 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9384                         return -EINVAL;
9385                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9386         }
9387         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9388                 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9389                                 vcpu, &vcpu->run->s.regs.events))
9390                         return -EINVAL;
9391                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9392         }
9393
9394         return 0;
9395 }
9396
9397 static void fx_init(struct kvm_vcpu *vcpu)
9398 {
9399         fpstate_init(&vcpu->arch.guest_fpu->state);
9400         if (boot_cpu_has(X86_FEATURE_XSAVES))
9401                 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9402                         host_xcr0 | XSTATE_COMPACTION_ENABLED;
9403
9404         /*
9405          * Ensure guest xcr0 is valid for loading
9406          */
9407         vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9408
9409         vcpu->arch.cr0 |= X86_CR0_ET;
9410 }
9411
9412 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9413 {
9414         if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9415                 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9416                              "guest TSC will not be reliable\n");
9417
9418         return 0;
9419 }
9420
9421 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9422 {
9423         struct page *page;
9424         int r;
9425
9426         if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9427                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9428         else
9429                 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9430
9431         kvm_set_tsc_khz(vcpu, max_tsc_khz);
9432
9433         r = kvm_mmu_create(vcpu);
9434         if (r < 0)
9435                 return r;
9436
9437         if (irqchip_in_kernel(vcpu->kvm)) {
9438                 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9439                 if (r < 0)
9440                         goto fail_mmu_destroy;
9441                 if (kvm_apicv_activated(vcpu->kvm))
9442                         vcpu->arch.apicv_active = true;
9443         } else
9444                 static_key_slow_inc(&kvm_no_apic_vcpu);
9445
9446         r = -ENOMEM;
9447
9448         page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9449         if (!page)
9450                 goto fail_free_lapic;
9451         vcpu->arch.pio_data = page_address(page);
9452
9453         vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9454                                        GFP_KERNEL_ACCOUNT);
9455         if (!vcpu->arch.mce_banks)
9456                 goto fail_free_pio_data;
9457         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9458
9459         if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9460                                 GFP_KERNEL_ACCOUNT))
9461                 goto fail_free_mce_banks;
9462
9463         if (!alloc_emulate_ctxt(vcpu))
9464                 goto free_wbinvd_dirty_mask;
9465
9466         vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9467                                                 GFP_KERNEL_ACCOUNT);
9468         if (!vcpu->arch.user_fpu) {
9469                 pr_err("kvm: failed to allocate userspace's fpu\n");
9470                 goto free_emulate_ctxt;
9471         }
9472
9473         vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9474                                                  GFP_KERNEL_ACCOUNT);
9475         if (!vcpu->arch.guest_fpu) {
9476                 pr_err("kvm: failed to allocate vcpu's fpu\n");
9477                 goto free_user_fpu;
9478         }
9479         fx_init(vcpu);
9480
9481         vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9482         vcpu->arch.tdp_level = kvm_x86_ops.get_tdp_level(vcpu);
9483
9484         vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9485
9486         kvm_async_pf_hash_reset(vcpu);
9487         kvm_pmu_init(vcpu);
9488
9489         vcpu->arch.pending_external_vector = -1;
9490         vcpu->arch.preempted_in_kernel = false;
9491
9492         kvm_hv_vcpu_init(vcpu);
9493
9494         r = kvm_x86_ops.vcpu_create(vcpu);
9495         if (r)
9496                 goto free_guest_fpu;
9497
9498         vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9499         vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9500         kvm_vcpu_mtrr_init(vcpu);
9501         vcpu_load(vcpu);
9502         kvm_vcpu_reset(vcpu, false);
9503         kvm_init_mmu(vcpu, false);
9504         vcpu_put(vcpu);
9505         return 0;
9506
9507 free_guest_fpu:
9508         kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9509 free_user_fpu:
9510         kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9511 free_emulate_ctxt:
9512         kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9513 free_wbinvd_dirty_mask:
9514         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9515 fail_free_mce_banks:
9516         kfree(vcpu->arch.mce_banks);
9517 fail_free_pio_data:
9518         free_page((unsigned long)vcpu->arch.pio_data);
9519 fail_free_lapic:
9520         kvm_free_lapic(vcpu);
9521 fail_mmu_destroy:
9522         kvm_mmu_destroy(vcpu);
9523         return r;
9524 }
9525
9526 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9527 {
9528         struct msr_data msr;
9529         struct kvm *kvm = vcpu->kvm;
9530
9531         kvm_hv_vcpu_postcreate(vcpu);
9532
9533         if (mutex_lock_killable(&vcpu->mutex))
9534                 return;
9535         vcpu_load(vcpu);
9536         msr.data = 0x0;
9537         msr.index = MSR_IA32_TSC;
9538         msr.host_initiated = true;
9539         kvm_write_tsc(vcpu, &msr);
9540         vcpu_put(vcpu);
9541
9542         /* poll control enabled by default */
9543         vcpu->arch.msr_kvm_poll_control = 1;
9544
9545         mutex_unlock(&vcpu->mutex);
9546
9547         if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
9548                 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9549                                                 KVMCLOCK_SYNC_PERIOD);
9550 }
9551
9552 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9553 {
9554         struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9555         int idx;
9556
9557         kvm_release_pfn(cache->pfn, cache->dirty, cache);
9558
9559         kvmclock_reset(vcpu);
9560
9561         kvm_x86_ops.vcpu_free(vcpu);
9562
9563         kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9564         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9565         kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9566         kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9567
9568         kvm_hv_vcpu_uninit(vcpu);
9569         kvm_pmu_destroy(vcpu);
9570         kfree(vcpu->arch.mce_banks);
9571         kvm_free_lapic(vcpu);
9572         idx = srcu_read_lock(&vcpu->kvm->srcu);
9573         kvm_mmu_destroy(vcpu);
9574         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9575         free_page((unsigned long)vcpu->arch.pio_data);
9576         if (!lapic_in_kernel(vcpu))
9577                 static_key_slow_dec(&kvm_no_apic_vcpu);
9578 }
9579
9580 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9581 {
9582         kvm_lapic_reset(vcpu, init_event);
9583
9584         vcpu->arch.hflags = 0;
9585
9586         vcpu->arch.smi_pending = 0;
9587         vcpu->arch.smi_count = 0;
9588         atomic_set(&vcpu->arch.nmi_queued, 0);
9589         vcpu->arch.nmi_pending = 0;
9590         vcpu->arch.nmi_injected = false;
9591         kvm_clear_interrupt_queue(vcpu);
9592         kvm_clear_exception_queue(vcpu);
9593
9594         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9595         kvm_update_dr0123(vcpu);
9596         vcpu->arch.dr6 = DR6_INIT;
9597         vcpu->arch.dr7 = DR7_FIXED_1;
9598         kvm_update_dr7(vcpu);
9599
9600         vcpu->arch.cr2 = 0;
9601
9602         kvm_make_request(KVM_REQ_EVENT, vcpu);
9603         vcpu->arch.apf.msr_en_val = 0;
9604         vcpu->arch.apf.msr_int_val = 0;
9605         vcpu->arch.st.msr_val = 0;
9606
9607         kvmclock_reset(vcpu);
9608
9609         kvm_clear_async_pf_completion_queue(vcpu);
9610         kvm_async_pf_hash_reset(vcpu);
9611         vcpu->arch.apf.halted = false;
9612
9613         if (kvm_mpx_supported()) {
9614                 void *mpx_state_buffer;
9615
9616                 /*
9617                  * To avoid have the INIT path from kvm_apic_has_events() that be
9618                  * called with loaded FPU and does not let userspace fix the state.
9619                  */
9620                 if (init_event)
9621                         kvm_put_guest_fpu(vcpu);
9622                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9623                                         XFEATURE_BNDREGS);
9624                 if (mpx_state_buffer)
9625                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9626                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9627                                         XFEATURE_BNDCSR);
9628                 if (mpx_state_buffer)
9629                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9630                 if (init_event)
9631                         kvm_load_guest_fpu(vcpu);
9632         }
9633
9634         if (!init_event) {
9635                 kvm_pmu_reset(vcpu);
9636                 vcpu->arch.smbase = 0x30000;
9637
9638                 vcpu->arch.msr_misc_features_enables = 0;
9639
9640                 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9641         }
9642
9643         memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9644         vcpu->arch.regs_avail = ~0;
9645         vcpu->arch.regs_dirty = ~0;
9646
9647         vcpu->arch.ia32_xss = 0;
9648
9649         kvm_x86_ops.vcpu_reset(vcpu, init_event);
9650 }
9651
9652 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9653 {
9654         struct kvm_segment cs;
9655
9656         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9657         cs.selector = vector << 8;
9658         cs.base = vector << 12;
9659         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9660         kvm_rip_write(vcpu, 0);
9661 }
9662
9663 int kvm_arch_hardware_enable(void)
9664 {
9665         struct kvm *kvm;
9666         struct kvm_vcpu *vcpu;
9667         int i;
9668         int ret;
9669         u64 local_tsc;
9670         u64 max_tsc = 0;
9671         bool stable, backwards_tsc = false;
9672
9673         kvm_shared_msr_cpu_online();
9674         ret = kvm_x86_ops.hardware_enable();
9675         if (ret != 0)
9676                 return ret;
9677
9678         local_tsc = rdtsc();
9679         stable = !kvm_check_tsc_unstable();
9680         list_for_each_entry(kvm, &vm_list, vm_list) {
9681                 kvm_for_each_vcpu(i, vcpu, kvm) {
9682                         if (!stable && vcpu->cpu == smp_processor_id())
9683                                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9684                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9685                                 backwards_tsc = true;
9686                                 if (vcpu->arch.last_host_tsc > max_tsc)
9687                                         max_tsc = vcpu->arch.last_host_tsc;
9688                         }
9689                 }
9690         }
9691
9692         /*
9693          * Sometimes, even reliable TSCs go backwards.  This happens on
9694          * platforms that reset TSC during suspend or hibernate actions, but
9695          * maintain synchronization.  We must compensate.  Fortunately, we can
9696          * detect that condition here, which happens early in CPU bringup,
9697          * before any KVM threads can be running.  Unfortunately, we can't
9698          * bring the TSCs fully up to date with real time, as we aren't yet far
9699          * enough into CPU bringup that we know how much real time has actually
9700          * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9701          * variables that haven't been updated yet.
9702          *
9703          * So we simply find the maximum observed TSC above, then record the
9704          * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
9705          * the adjustment will be applied.  Note that we accumulate
9706          * adjustments, in case multiple suspend cycles happen before some VCPU
9707          * gets a chance to run again.  In the event that no KVM threads get a
9708          * chance to run, we will miss the entire elapsed period, as we'll have
9709          * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9710          * loose cycle time.  This isn't too big a deal, since the loss will be
9711          * uniform across all VCPUs (not to mention the scenario is extremely
9712          * unlikely). It is possible that a second hibernate recovery happens
9713          * much faster than a first, causing the observed TSC here to be
9714          * smaller; this would require additional padding adjustment, which is
9715          * why we set last_host_tsc to the local tsc observed here.
9716          *
9717          * N.B. - this code below runs only on platforms with reliable TSC,
9718          * as that is the only way backwards_tsc is set above.  Also note
9719          * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9720          * have the same delta_cyc adjustment applied if backwards_tsc
9721          * is detected.  Note further, this adjustment is only done once,
9722          * as we reset last_host_tsc on all VCPUs to stop this from being
9723          * called multiple times (one for each physical CPU bringup).
9724          *
9725          * Platforms with unreliable TSCs don't have to deal with this, they
9726          * will be compensated by the logic in vcpu_load, which sets the TSC to
9727          * catchup mode.  This will catchup all VCPUs to real time, but cannot
9728          * guarantee that they stay in perfect synchronization.
9729          */
9730         if (backwards_tsc) {
9731                 u64 delta_cyc = max_tsc - local_tsc;
9732                 list_for_each_entry(kvm, &vm_list, vm_list) {
9733                         kvm->arch.backwards_tsc_observed = true;
9734                         kvm_for_each_vcpu(i, vcpu, kvm) {
9735                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9736                                 vcpu->arch.last_host_tsc = local_tsc;
9737                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9738                         }
9739
9740                         /*
9741                          * We have to disable TSC offset matching.. if you were
9742                          * booting a VM while issuing an S4 host suspend....
9743                          * you may have some problem.  Solving this issue is
9744                          * left as an exercise to the reader.
9745                          */
9746                         kvm->arch.last_tsc_nsec = 0;
9747                         kvm->arch.last_tsc_write = 0;
9748                 }
9749
9750         }
9751         return 0;
9752 }
9753
9754 void kvm_arch_hardware_disable(void)
9755 {
9756         kvm_x86_ops.hardware_disable();
9757         drop_user_return_notifiers();
9758 }
9759
9760 int kvm_arch_hardware_setup(void *opaque)
9761 {
9762         struct kvm_x86_init_ops *ops = opaque;
9763         int r;
9764
9765         rdmsrl_safe(MSR_EFER, &host_efer);
9766
9767         if (boot_cpu_has(X86_FEATURE_XSAVES))
9768                 rdmsrl(MSR_IA32_XSS, host_xss);
9769
9770         r = ops->hardware_setup();
9771         if (r != 0)
9772                 return r;
9773
9774         memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
9775
9776         if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
9777                 supported_xss = 0;
9778
9779 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
9780         cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
9781 #undef __kvm_cpu_cap_has
9782
9783         if (kvm_has_tsc_control) {
9784                 /*
9785                  * Make sure the user can only configure tsc_khz values that
9786                  * fit into a signed integer.
9787                  * A min value is not calculated because it will always
9788                  * be 1 on all machines.
9789                  */
9790                 u64 max = min(0x7fffffffULL,
9791                               __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9792                 kvm_max_guest_tsc_khz = max;
9793
9794                 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9795         }
9796
9797         kvm_init_msr_list();
9798         return 0;
9799 }
9800
9801 void kvm_arch_hardware_unsetup(void)
9802 {
9803         kvm_x86_ops.hardware_unsetup();
9804 }
9805
9806 int kvm_arch_check_processor_compat(void *opaque)
9807 {
9808         struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
9809         struct kvm_x86_init_ops *ops = opaque;
9810
9811         WARN_ON(!irqs_disabled());
9812
9813         if (__cr4_reserved_bits(cpu_has, c) !=
9814             __cr4_reserved_bits(cpu_has, &boot_cpu_data))
9815                 return -EIO;
9816
9817         return ops->check_processor_compatibility();
9818 }
9819
9820 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9821 {
9822         return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9823 }
9824 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9825
9826 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9827 {
9828         return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9829 }
9830
9831 struct static_key kvm_no_apic_vcpu __read_mostly;
9832 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9833
9834 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9835 {
9836         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
9837
9838         vcpu->arch.l1tf_flush_l1d = true;
9839         if (pmu->version && unlikely(pmu->event_count)) {
9840                 pmu->need_cleanup = true;
9841                 kvm_make_request(KVM_REQ_PMU, vcpu);
9842         }
9843         kvm_x86_ops.sched_in(vcpu, cpu);
9844 }
9845
9846 void kvm_arch_free_vm(struct kvm *kvm)
9847 {
9848         kfree(kvm->arch.hyperv.hv_pa_pg);
9849         vfree(kvm);
9850 }
9851
9852
9853 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9854 {
9855         if (type)
9856                 return -EINVAL;
9857
9858         INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9859         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9860         INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9861         INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
9862         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9863         atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9864
9865         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9866         set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9867         /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9868         set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9869                 &kvm->arch.irq_sources_bitmap);
9870
9871         raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9872         mutex_init(&kvm->arch.apic_map_lock);
9873         spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9874
9875         kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
9876         pvclock_update_vm_gtod_copy(kvm);
9877
9878         kvm->arch.guest_can_read_msr_platform_info = true;
9879
9880         INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9881         INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9882
9883         kvm_hv_init_vm(kvm);
9884         kvm_page_track_init(kvm);
9885         kvm_mmu_init_vm(kvm);
9886
9887         return kvm_x86_ops.vm_init(kvm);
9888 }
9889
9890 int kvm_arch_post_init_vm(struct kvm *kvm)
9891 {
9892         return kvm_mmu_post_init_vm(kvm);
9893 }
9894
9895 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9896 {
9897         vcpu_load(vcpu);
9898         kvm_mmu_unload(vcpu);
9899         vcpu_put(vcpu);
9900 }
9901
9902 static void kvm_free_vcpus(struct kvm *kvm)
9903 {
9904         unsigned int i;
9905         struct kvm_vcpu *vcpu;
9906
9907         /*
9908          * Unpin any mmu pages first.
9909          */
9910         kvm_for_each_vcpu(i, vcpu, kvm) {
9911                 kvm_clear_async_pf_completion_queue(vcpu);
9912                 kvm_unload_vcpu_mmu(vcpu);
9913         }
9914         kvm_for_each_vcpu(i, vcpu, kvm)
9915                 kvm_vcpu_destroy(vcpu);
9916
9917         mutex_lock(&kvm->lock);
9918         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9919                 kvm->vcpus[i] = NULL;
9920
9921         atomic_set(&kvm->online_vcpus, 0);
9922         mutex_unlock(&kvm->lock);
9923 }
9924
9925 void kvm_arch_sync_events(struct kvm *kvm)
9926 {
9927         cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9928         cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9929         kvm_free_pit(kvm);
9930 }
9931
9932 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9933 {
9934         int i, r;
9935         unsigned long hva, uninitialized_var(old_npages);
9936         struct kvm_memslots *slots = kvm_memslots(kvm);
9937         struct kvm_memory_slot *slot;
9938
9939         /* Called with kvm->slots_lock held.  */
9940         if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9941                 return -EINVAL;
9942
9943         slot = id_to_memslot(slots, id);
9944         if (size) {
9945                 if (slot && slot->npages)
9946                         return -EEXIST;
9947
9948                 /*
9949                  * MAP_SHARED to prevent internal slot pages from being moved
9950                  * by fork()/COW.
9951                  */
9952                 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9953                               MAP_SHARED | MAP_ANONYMOUS, 0);
9954                 if (IS_ERR((void *)hva))
9955                         return PTR_ERR((void *)hva);
9956         } else {
9957                 if (!slot || !slot->npages)
9958                         return 0;
9959
9960                 old_npages = slot->npages;
9961                 hva = 0;
9962         }
9963
9964         for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9965                 struct kvm_userspace_memory_region m;
9966
9967                 m.slot = id | (i << 16);
9968                 m.flags = 0;
9969                 m.guest_phys_addr = gpa;
9970                 m.userspace_addr = hva;
9971                 m.memory_size = size;
9972                 r = __kvm_set_memory_region(kvm, &m);
9973                 if (r < 0)
9974                         return r;
9975         }
9976
9977         if (!size)
9978                 vm_munmap(hva, old_npages * PAGE_SIZE);
9979
9980         return 0;
9981 }
9982 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9983
9984 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
9985 {
9986         kvm_mmu_pre_destroy_vm(kvm);
9987 }
9988
9989 void kvm_arch_destroy_vm(struct kvm *kvm)
9990 {
9991         if (current->mm == kvm->mm) {
9992                 /*
9993                  * Free memory regions allocated on behalf of userspace,
9994                  * unless the the memory map has changed due to process exit
9995                  * or fd copying.
9996                  */
9997                 mutex_lock(&kvm->slots_lock);
9998                 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
9999                                         0, 0);
10000                 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
10001                                         0, 0);
10002                 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
10003                 mutex_unlock(&kvm->slots_lock);
10004         }
10005         if (kvm_x86_ops.vm_destroy)
10006                 kvm_x86_ops.vm_destroy(kvm);
10007         kvm_pic_destroy(kvm);
10008         kvm_ioapic_destroy(kvm);
10009         kvm_free_vcpus(kvm);
10010         kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
10011         kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
10012         kvm_mmu_uninit_vm(kvm);
10013         kvm_page_track_cleanup(kvm);
10014         kvm_hv_destroy_vm(kvm);
10015 }
10016
10017 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
10018 {
10019         int i;
10020
10021         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10022                 kvfree(slot->arch.rmap[i]);
10023                 slot->arch.rmap[i] = NULL;
10024
10025                 if (i == 0)
10026                         continue;
10027
10028                 kvfree(slot->arch.lpage_info[i - 1]);
10029                 slot->arch.lpage_info[i - 1] = NULL;
10030         }
10031
10032         kvm_page_track_free_memslot(slot);
10033 }
10034
10035 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
10036                                       unsigned long npages)
10037 {
10038         int i;
10039
10040         /*
10041          * Clear out the previous array pointers for the KVM_MR_MOVE case.  The
10042          * old arrays will be freed by __kvm_set_memory_region() if installing
10043          * the new memslot is successful.
10044          */
10045         memset(&slot->arch, 0, sizeof(slot->arch));
10046
10047         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10048                 struct kvm_lpage_info *linfo;
10049                 unsigned long ugfn;
10050                 int lpages;
10051                 int level = i + 1;
10052
10053                 lpages = gfn_to_index(slot->base_gfn + npages - 1,
10054                                       slot->base_gfn, level) + 1;
10055
10056                 slot->arch.rmap[i] =
10057                         kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
10058                                  GFP_KERNEL_ACCOUNT);
10059                 if (!slot->arch.rmap[i])
10060                         goto out_free;
10061                 if (i == 0)
10062                         continue;
10063
10064                 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
10065                 if (!linfo)
10066                         goto out_free;
10067
10068                 slot->arch.lpage_info[i - 1] = linfo;
10069
10070                 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
10071                         linfo[0].disallow_lpage = 1;
10072                 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
10073                         linfo[lpages - 1].disallow_lpage = 1;
10074                 ugfn = slot->userspace_addr >> PAGE_SHIFT;
10075                 /*
10076                  * If the gfn and userspace address are not aligned wrt each
10077                  * other, disable large page support for this slot.
10078                  */
10079                 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
10080                         unsigned long j;
10081
10082                         for (j = 0; j < lpages; ++j)
10083                                 linfo[j].disallow_lpage = 1;
10084                 }
10085         }
10086
10087         if (kvm_page_track_create_memslot(slot, npages))
10088                 goto out_free;
10089
10090         return 0;
10091
10092 out_free:
10093         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10094                 kvfree(slot->arch.rmap[i]);
10095                 slot->arch.rmap[i] = NULL;
10096                 if (i == 0)
10097                         continue;
10098
10099                 kvfree(slot->arch.lpage_info[i - 1]);
10100                 slot->arch.lpage_info[i - 1] = NULL;
10101         }
10102         return -ENOMEM;
10103 }
10104
10105 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
10106 {
10107         struct kvm_vcpu *vcpu;
10108         int i;
10109
10110         /*
10111          * memslots->generation has been incremented.
10112          * mmio generation may have reached its maximum value.
10113          */
10114         kvm_mmu_invalidate_mmio_sptes(kvm, gen);
10115
10116         /* Force re-initialization of steal_time cache */
10117         kvm_for_each_vcpu(i, vcpu, kvm)
10118                 kvm_vcpu_kick(vcpu);
10119 }
10120
10121 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10122                                 struct kvm_memory_slot *memslot,
10123                                 const struct kvm_userspace_memory_region *mem,
10124                                 enum kvm_mr_change change)
10125 {
10126         if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10127                 return kvm_alloc_memslot_metadata(memslot,
10128                                                   mem->memory_size >> PAGE_SHIFT);
10129         return 0;
10130 }
10131
10132 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10133                                      struct kvm_memory_slot *old,
10134                                      struct kvm_memory_slot *new,
10135                                      enum kvm_mr_change change)
10136 {
10137         /*
10138          * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot.
10139          * See comments below.
10140          */
10141         if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY))
10142                 return;
10143
10144         /*
10145          * Dirty logging tracks sptes in 4k granularity, meaning that large
10146          * sptes have to be split.  If live migration is successful, the guest
10147          * in the source machine will be destroyed and large sptes will be
10148          * created in the destination. However, if the guest continues to run
10149          * in the source machine (for example if live migration fails), small
10150          * sptes will remain around and cause bad performance.
10151          *
10152          * Scan sptes if dirty logging has been stopped, dropping those
10153          * which can be collapsed into a single large-page spte.  Later
10154          * page faults will create the large-page sptes.
10155          *
10156          * There is no need to do this in any of the following cases:
10157          * CREATE:      No dirty mappings will already exist.
10158          * MOVE/DELETE: The old mappings will already have been cleaned up by
10159          *              kvm_arch_flush_shadow_memslot()
10160          */
10161         if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10162             !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10163                 kvm_mmu_zap_collapsible_sptes(kvm, new);
10164
10165         /*
10166          * Enable or disable dirty logging for the slot.
10167          *
10168          * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old
10169          * slot have been zapped so no dirty logging updates are needed for
10170          * the old slot.
10171          * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible
10172          * any mappings that might be created in it will consume the
10173          * properties of the new slot and do not need to be updated here.
10174          *
10175          * When PML is enabled, the kvm_x86_ops dirty logging hooks are
10176          * called to enable/disable dirty logging.
10177          *
10178          * When disabling dirty logging with PML enabled, the D-bit is set
10179          * for sptes in the slot in order to prevent unnecessary GPA
10180          * logging in the PML buffer (and potential PML buffer full VMEXIT).
10181          * This guarantees leaving PML enabled for the guest's lifetime
10182          * won't have any additional overhead from PML when the guest is
10183          * running with dirty logging disabled.
10184          *
10185          * When enabling dirty logging, large sptes are write-protected
10186          * so they can be split on first write.  New large sptes cannot
10187          * be created for this slot until the end of the logging.
10188          * See the comments in fast_page_fault().
10189          * For small sptes, nothing is done if the dirty log is in the
10190          * initial-all-set state.  Otherwise, depending on whether pml
10191          * is enabled the D-bit or the W-bit will be cleared.
10192          */
10193         if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10194                 if (kvm_x86_ops.slot_enable_log_dirty) {
10195                         kvm_x86_ops.slot_enable_log_dirty(kvm, new);
10196                 } else {
10197                         int level =
10198                                 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10199                                 PG_LEVEL_2M : PG_LEVEL_4K;
10200
10201                         /*
10202                          * If we're with initial-all-set, we don't need
10203                          * to write protect any small page because
10204                          * they're reported as dirty already.  However
10205                          * we still need to write-protect huge pages
10206                          * so that the page split can happen lazily on
10207                          * the first write to the huge page.
10208                          */
10209                         kvm_mmu_slot_remove_write_access(kvm, new, level);
10210                 }
10211         } else {
10212                 if (kvm_x86_ops.slot_disable_log_dirty)
10213                         kvm_x86_ops.slot_disable_log_dirty(kvm, new);
10214         }
10215 }
10216
10217 void kvm_arch_commit_memory_region(struct kvm *kvm,
10218                                 const struct kvm_userspace_memory_region *mem,
10219                                 struct kvm_memory_slot *old,
10220                                 const struct kvm_memory_slot *new,
10221                                 enum kvm_mr_change change)
10222 {
10223         if (!kvm->arch.n_requested_mmu_pages)
10224                 kvm_mmu_change_mmu_pages(kvm,
10225                                 kvm_mmu_calculate_default_mmu_pages(kvm));
10226
10227         /*
10228          * FIXME: const-ify all uses of struct kvm_memory_slot.
10229          */
10230         kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change);
10231
10232         /* Free the arrays associated with the old memslot. */
10233         if (change == KVM_MR_MOVE)
10234                 kvm_arch_free_memslot(kvm, old);
10235 }
10236
10237 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10238 {
10239         kvm_mmu_zap_all(kvm);
10240 }
10241
10242 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10243                                    struct kvm_memory_slot *slot)
10244 {
10245         kvm_page_track_flush_slot(kvm, slot);
10246 }
10247
10248 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10249 {
10250         return (is_guest_mode(vcpu) &&
10251                         kvm_x86_ops.guest_apic_has_interrupt &&
10252                         kvm_x86_ops.guest_apic_has_interrupt(vcpu));
10253 }
10254
10255 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10256 {
10257         if (!list_empty_careful(&vcpu->async_pf.done))
10258                 return true;
10259
10260         if (kvm_apic_has_events(vcpu))
10261                 return true;
10262
10263         if (vcpu->arch.pv.pv_unhalted)
10264                 return true;
10265
10266         if (vcpu->arch.exception.pending)
10267                 return true;
10268
10269         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10270             (vcpu->arch.nmi_pending &&
10271              kvm_x86_ops.nmi_allowed(vcpu, false)))
10272                 return true;
10273
10274         if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10275             (vcpu->arch.smi_pending &&
10276              kvm_x86_ops.smi_allowed(vcpu, false)))
10277                 return true;
10278
10279         if (kvm_arch_interrupt_allowed(vcpu) &&
10280             (kvm_cpu_has_interrupt(vcpu) ||
10281             kvm_guest_apic_has_interrupt(vcpu)))
10282                 return true;
10283
10284         if (kvm_hv_has_stimer_pending(vcpu))
10285                 return true;
10286
10287         if (is_guest_mode(vcpu) &&
10288             kvm_x86_ops.nested_ops->hv_timer_pending &&
10289             kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
10290                 return true;
10291
10292         return false;
10293 }
10294
10295 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10296 {
10297         return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10298 }
10299
10300 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10301 {
10302         if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10303                 return true;
10304
10305         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10306                 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10307                  kvm_test_request(KVM_REQ_EVENT, vcpu))
10308                 return true;
10309
10310         if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu))
10311                 return true;
10312
10313         return false;
10314 }
10315
10316 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10317 {
10318         return vcpu->arch.preempted_in_kernel;
10319 }
10320
10321 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10322 {
10323         return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10324 }
10325
10326 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10327 {
10328         return kvm_x86_ops.interrupt_allowed(vcpu, false);
10329 }
10330
10331 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10332 {
10333         if (is_64_bit_mode(vcpu))
10334                 return kvm_rip_read(vcpu);
10335         return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10336                      kvm_rip_read(vcpu));
10337 }
10338 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10339
10340 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10341 {
10342         return kvm_get_linear_rip(vcpu) == linear_rip;
10343 }
10344 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10345
10346 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10347 {
10348         unsigned long rflags;
10349
10350         rflags = kvm_x86_ops.get_rflags(vcpu);
10351         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10352                 rflags &= ~X86_EFLAGS_TF;
10353         return rflags;
10354 }
10355 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10356
10357 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10358 {
10359         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10360             kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10361                 rflags |= X86_EFLAGS_TF;
10362         kvm_x86_ops.set_rflags(vcpu, rflags);
10363 }
10364
10365 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10366 {
10367         __kvm_set_rflags(vcpu, rflags);
10368         kvm_make_request(KVM_REQ_EVENT, vcpu);
10369 }
10370 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10371
10372 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10373 {
10374         int r;
10375
10376         if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10377               work->wakeup_all)
10378                 return;
10379
10380         r = kvm_mmu_reload(vcpu);
10381         if (unlikely(r))
10382                 return;
10383
10384         if (!vcpu->arch.mmu->direct_map &&
10385               work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10386                 return;
10387
10388         kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10389 }
10390
10391 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10392 {
10393         BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
10394
10395         return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10396 }
10397
10398 static inline u32 kvm_async_pf_next_probe(u32 key)
10399 {
10400         return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
10401 }
10402
10403 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10404 {
10405         u32 key = kvm_async_pf_hash_fn(gfn);
10406
10407         while (vcpu->arch.apf.gfns[key] != ~0)
10408                 key = kvm_async_pf_next_probe(key);
10409
10410         vcpu->arch.apf.gfns[key] = gfn;
10411 }
10412
10413 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10414 {
10415         int i;
10416         u32 key = kvm_async_pf_hash_fn(gfn);
10417
10418         for (i = 0; i < ASYNC_PF_PER_VCPU &&
10419                      (vcpu->arch.apf.gfns[key] != gfn &&
10420                       vcpu->arch.apf.gfns[key] != ~0); i++)
10421                 key = kvm_async_pf_next_probe(key);
10422
10423         return key;
10424 }
10425
10426 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10427 {
10428         return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10429 }
10430
10431 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10432 {
10433         u32 i, j, k;
10434
10435         i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10436
10437         if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
10438                 return;
10439
10440         while (true) {
10441                 vcpu->arch.apf.gfns[i] = ~0;
10442                 do {
10443                         j = kvm_async_pf_next_probe(j);
10444                         if (vcpu->arch.apf.gfns[j] == ~0)
10445                                 return;
10446                         k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10447                         /*
10448                          * k lies cyclically in ]i,j]
10449                          * |    i.k.j |
10450                          * |....j i.k.| or  |.k..j i...|
10451                          */
10452                 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10453                 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10454                 i = j;
10455         }
10456 }
10457
10458 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
10459 {
10460         u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
10461
10462         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
10463                                       sizeof(reason));
10464 }
10465
10466 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
10467 {
10468         unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
10469
10470         return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
10471                                              &token, offset, sizeof(token));
10472 }
10473
10474 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
10475 {
10476         unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
10477         u32 val;
10478
10479         if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
10480                                          &val, offset, sizeof(val)))
10481                 return false;
10482
10483         return !val;
10484 }
10485
10486 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10487 {
10488         if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10489                 return false;
10490
10491         if (!kvm_pv_async_pf_enabled(vcpu) ||
10492             (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0))
10493                 return false;
10494
10495         return true;
10496 }
10497
10498 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10499 {
10500         if (unlikely(!lapic_in_kernel(vcpu) ||
10501                      kvm_event_needs_reinjection(vcpu) ||
10502                      vcpu->arch.exception.pending))
10503                 return false;
10504
10505         if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10506                 return false;
10507
10508         /*
10509          * If interrupts are off we cannot even use an artificial
10510          * halt state.
10511          */
10512         return kvm_arch_interrupt_allowed(vcpu);
10513 }
10514
10515 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10516                                      struct kvm_async_pf *work)
10517 {
10518         struct x86_exception fault;
10519
10520         trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10521         kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10522
10523         if (kvm_can_deliver_async_pf(vcpu) &&
10524             !apf_put_user_notpresent(vcpu)) {
10525                 fault.vector = PF_VECTOR;
10526                 fault.error_code_valid = true;
10527                 fault.error_code = 0;
10528                 fault.nested_page_fault = false;
10529                 fault.address = work->arch.token;
10530                 fault.async_page_fault = true;
10531                 kvm_inject_page_fault(vcpu, &fault);
10532                 return true;
10533         } else {
10534                 /*
10535                  * It is not possible to deliver a paravirtualized asynchronous
10536                  * page fault, but putting the guest in an artificial halt state
10537                  * can be beneficial nevertheless: if an interrupt arrives, we
10538                  * can deliver it timely and perhaps the guest will schedule
10539                  * another process.  When the instruction that triggered a page
10540                  * fault is retried, hopefully the page will be ready in the host.
10541                  */
10542                 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10543                 return false;
10544         }
10545 }
10546
10547 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10548                                  struct kvm_async_pf *work)
10549 {
10550         struct kvm_lapic_irq irq = {
10551                 .delivery_mode = APIC_DM_FIXED,
10552                 .vector = vcpu->arch.apf.vec
10553         };
10554
10555         if (work->wakeup_all)
10556                 work->arch.token = ~0; /* broadcast wakeup */
10557         else
10558                 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10559         trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
10560
10561         if ((work->wakeup_all || work->notpresent_injected) &&
10562             kvm_pv_async_pf_enabled(vcpu) &&
10563             !apf_put_user_ready(vcpu, work->arch.token)) {
10564                 vcpu->arch.apf.pageready_pending = true;
10565                 kvm_apic_set_irq(vcpu, &irq, NULL);
10566         }
10567
10568         vcpu->arch.apf.halted = false;
10569         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10570 }
10571
10572 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
10573 {
10574         kvm_make_request(KVM_REQ_APF_READY, vcpu);
10575         if (!vcpu->arch.apf.pageready_pending)
10576                 kvm_vcpu_kick(vcpu);
10577 }
10578
10579 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
10580 {
10581         if (!kvm_pv_async_pf_enabled(vcpu))
10582                 return true;
10583         else
10584                 return apf_pageready_slot_free(vcpu);
10585 }
10586
10587 void kvm_arch_start_assignment(struct kvm *kvm)
10588 {
10589         atomic_inc(&kvm->arch.assigned_device_count);
10590 }
10591 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10592
10593 void kvm_arch_end_assignment(struct kvm *kvm)
10594 {
10595         atomic_dec(&kvm->arch.assigned_device_count);
10596 }
10597 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10598
10599 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10600 {
10601         return atomic_read(&kvm->arch.assigned_device_count);
10602 }
10603 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10604
10605 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10606 {
10607         atomic_inc(&kvm->arch.noncoherent_dma_count);
10608 }
10609 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10610
10611 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10612 {
10613         atomic_dec(&kvm->arch.noncoherent_dma_count);
10614 }
10615 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10616
10617 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10618 {
10619         return atomic_read(&kvm->arch.noncoherent_dma_count);
10620 }
10621 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10622
10623 bool kvm_arch_has_irq_bypass(void)
10624 {
10625         return true;
10626 }
10627
10628 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10629                                       struct irq_bypass_producer *prod)
10630 {
10631         struct kvm_kernel_irqfd *irqfd =
10632                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10633
10634         irqfd->producer = prod;
10635
10636         return kvm_x86_ops.update_pi_irte(irqfd->kvm,
10637                                            prod->irq, irqfd->gsi, 1);
10638 }
10639
10640 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10641                                       struct irq_bypass_producer *prod)
10642 {
10643         int ret;
10644         struct kvm_kernel_irqfd *irqfd =
10645                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10646
10647         WARN_ON(irqfd->producer != prod);
10648         irqfd->producer = NULL;
10649
10650         /*
10651          * When producer of consumer is unregistered, we change back to
10652          * remapped mode, so we can re-use the current implementation
10653          * when the irq is masked/disabled or the consumer side (KVM
10654          * int this case doesn't want to receive the interrupts.
10655         */
10656         ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10657         if (ret)
10658                 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10659                        " fails: %d\n", irqfd->consumer.token, ret);
10660 }
10661
10662 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10663                                    uint32_t guest_irq, bool set)
10664 {
10665         return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set);
10666 }
10667
10668 bool kvm_vector_hashing_enabled(void)
10669 {
10670         return vector_hashing;
10671 }
10672
10673 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10674 {
10675         return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10676 }
10677 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10678
10679 u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu)
10680 {
10681         uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD;
10682
10683         /* The STIBP bit doesn't fault even if it's not advertised */
10684         if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
10685             !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
10686                 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10687         if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
10688             !boot_cpu_has(X86_FEATURE_AMD_IBRS))
10689                 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10690
10691         if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) &&
10692             !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
10693                 bits &= ~SPEC_CTRL_SSBD;
10694         if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
10695             !boot_cpu_has(X86_FEATURE_AMD_SSBD))
10696                 bits &= ~SPEC_CTRL_SSBD;
10697
10698         return bits;
10699 }
10700 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits);
10701
10702 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10703 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10704 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10705 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10706 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10707 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10708 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10709 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10710 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10711 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10712 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10713 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10714 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10715 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10716 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10717 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10718 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10719 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10720 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10721 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
10722 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
10723 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);