1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
30 #include <linux/clocksource.h>
31 #include <linux/interrupt.h>
32 #include <linux/kvm.h>
34 #include <linux/vmalloc.h>
35 #include <linux/export.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <linux/kvm_irqfd.h>
52 #include <linux/irqbypass.h>
53 #include <linux/sched/stat.h>
54 #include <linux/sched/isolation.h>
55 #include <linux/mem_encrypt.h>
57 #include <trace/events/kvm.h>
59 #include <asm/debugreg.h>
63 #include <linux/kernel_stat.h>
64 #include <asm/fpu/internal.h> /* Ugh! */
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67 #include <asm/irq_remapping.h>
68 #include <asm/mshyperv.h>
69 #include <asm/hypervisor.h>
70 #include <asm/intel_pt.h>
71 #include <clocksource/hyperv_timer.h>
73 #define CREATE_TRACE_POINTS
76 #define MAX_IO_MSRS 256
77 #define KVM_MAX_MCE_BANKS 32
78 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
81 #define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
90 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
92 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
95 #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__
96 #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__
98 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
101 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
102 static void process_nmi(struct kvm_vcpu *vcpu);
103 static void enter_smm(struct kvm_vcpu *vcpu);
104 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
105 static void store_regs(struct kvm_vcpu *vcpu);
106 static int sync_regs(struct kvm_vcpu *vcpu);
108 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
109 EXPORT_SYMBOL_GPL(kvm_x86_ops);
111 static bool __read_mostly ignore_msrs = 0;
112 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
114 static bool __read_mostly report_ignored_msrs = true;
115 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
117 unsigned int min_timer_period_us = 200;
118 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
120 static bool __read_mostly kvmclock_periodic_sync = true;
121 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
123 bool __read_mostly kvm_has_tsc_control;
124 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
125 u32 __read_mostly kvm_max_guest_tsc_khz;
126 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
127 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129 u64 __read_mostly kvm_max_tsc_scaling_ratio;
130 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
131 u64 __read_mostly kvm_default_tsc_scaling_ratio;
132 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
134 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
135 static u32 __read_mostly tsc_tolerance_ppm = 250;
136 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
139 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
140 * adaptive tuning starting from default advancment of 1000ns. '0' disables
141 * advancement entirely. Any other value is used as-is and disables adaptive
142 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
144 static int __read_mostly lapic_timer_advance_ns = -1;
145 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
147 static bool __read_mostly vector_hashing = true;
148 module_param(vector_hashing, bool, S_IRUGO);
150 bool __read_mostly enable_vmware_backdoor = false;
151 module_param(enable_vmware_backdoor, bool, S_IRUGO);
152 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
154 static bool __read_mostly force_emulation_prefix = false;
155 module_param(force_emulation_prefix, bool, S_IRUGO);
157 int __read_mostly pi_inject_timer = -1;
158 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
160 #define KVM_NR_SHARED_MSRS 16
162 struct kvm_shared_msrs_global {
164 u32 msrs[KVM_NR_SHARED_MSRS];
167 struct kvm_shared_msrs {
168 struct user_return_notifier urn;
170 struct kvm_shared_msr_values {
173 } values[KVM_NR_SHARED_MSRS];
176 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
177 static struct kvm_shared_msrs __percpu *shared_msrs;
179 struct kvm_stats_debugfs_item debugfs_entries[] = {
180 { "pf_fixed", VCPU_STAT(pf_fixed) },
181 { "pf_guest", VCPU_STAT(pf_guest) },
182 { "tlb_flush", VCPU_STAT(tlb_flush) },
183 { "invlpg", VCPU_STAT(invlpg) },
184 { "exits", VCPU_STAT(exits) },
185 { "io_exits", VCPU_STAT(io_exits) },
186 { "mmio_exits", VCPU_STAT(mmio_exits) },
187 { "signal_exits", VCPU_STAT(signal_exits) },
188 { "irq_window", VCPU_STAT(irq_window_exits) },
189 { "nmi_window", VCPU_STAT(nmi_window_exits) },
190 { "halt_exits", VCPU_STAT(halt_exits) },
191 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
192 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
193 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
194 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
195 { "hypercalls", VCPU_STAT(hypercalls) },
196 { "request_irq", VCPU_STAT(request_irq_exits) },
197 { "irq_exits", VCPU_STAT(irq_exits) },
198 { "host_state_reload", VCPU_STAT(host_state_reload) },
199 { "fpu_reload", VCPU_STAT(fpu_reload) },
200 { "insn_emulation", VCPU_STAT(insn_emulation) },
201 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
202 { "irq_injections", VCPU_STAT(irq_injections) },
203 { "nmi_injections", VCPU_STAT(nmi_injections) },
204 { "req_event", VCPU_STAT(req_event) },
205 { "l1d_flush", VCPU_STAT(l1d_flush) },
206 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
207 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
208 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
209 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
210 { "mmu_flooded", VM_STAT(mmu_flooded) },
211 { "mmu_recycled", VM_STAT(mmu_recycled) },
212 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
213 { "mmu_unsync", VM_STAT(mmu_unsync) },
214 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
215 { "largepages", VM_STAT(lpages, .mode = 0444) },
216 { "max_mmu_page_hash_collisions",
217 VM_STAT(max_mmu_page_hash_collisions) },
221 u64 __read_mostly host_xcr0;
223 struct kmem_cache *x86_fpu_cache;
224 EXPORT_SYMBOL_GPL(x86_fpu_cache);
226 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
228 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
231 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
232 vcpu->arch.apf.gfns[i] = ~0;
235 static void kvm_on_user_return(struct user_return_notifier *urn)
238 struct kvm_shared_msrs *locals
239 = container_of(urn, struct kvm_shared_msrs, urn);
240 struct kvm_shared_msr_values *values;
244 * Disabling irqs at this point since the following code could be
245 * interrupted and executed through kvm_arch_hardware_disable()
247 local_irq_save(flags);
248 if (locals->registered) {
249 locals->registered = false;
250 user_return_notifier_unregister(urn);
252 local_irq_restore(flags);
253 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
254 values = &locals->values[slot];
255 if (values->host != values->curr) {
256 wrmsrl(shared_msrs_global.msrs[slot], values->host);
257 values->curr = values->host;
262 static void shared_msr_update(unsigned slot, u32 msr)
265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
268 /* only read, and nobody should modify it at this time,
269 * so don't need lock */
270 if (slot >= shared_msrs_global.nr) {
271 printk(KERN_ERR "kvm: invalid MSR slot!");
274 rdmsrl_safe(msr, &value);
275 smsr->values[slot].host = value;
276 smsr->values[slot].curr = value;
279 void kvm_define_shared_msr(unsigned slot, u32 msr)
281 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
282 shared_msrs_global.msrs[slot] = msr;
283 if (slot >= shared_msrs_global.nr)
284 shared_msrs_global.nr = slot + 1;
286 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
288 static void kvm_shared_msr_cpu_online(void)
292 for (i = 0; i < shared_msrs_global.nr; ++i)
293 shared_msr_update(i, shared_msrs_global.msrs[i]);
296 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
302 if (((value ^ smsr->values[slot].curr) & mask) == 0)
304 smsr->values[slot].curr = value;
305 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
309 if (!smsr->registered) {
310 smsr->urn.on_user_return = kvm_on_user_return;
311 user_return_notifier_register(&smsr->urn);
312 smsr->registered = true;
316 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
318 static void drop_user_return_notifiers(void)
320 unsigned int cpu = smp_processor_id();
321 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
323 if (smsr->registered)
324 kvm_on_user_return(&smsr->urn);
327 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
329 return vcpu->arch.apic_base;
331 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
333 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
335 return kvm_apic_mode(kvm_get_apic_base(vcpu));
337 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
339 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
341 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
342 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
343 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
344 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
346 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
348 if (!msr_info->host_initiated) {
349 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
351 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
355 kvm_lapic_set_base(vcpu, msr_info->data);
358 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
360 asmlinkage __visible void kvm_spurious_fault(void)
362 /* Fault while not rebooting. We want the trace. */
366 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
368 #define EXCPT_BENIGN 0
369 #define EXCPT_CONTRIBUTORY 1
372 static int exception_class(int vector)
382 return EXCPT_CONTRIBUTORY;
389 #define EXCPT_FAULT 0
391 #define EXCPT_ABORT 2
392 #define EXCPT_INTERRUPT 3
394 static int exception_type(int vector)
398 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
399 return EXCPT_INTERRUPT;
403 /* #DB is trap, as instruction watchpoints are handled elsewhere */
404 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
407 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
410 /* Reserved exceptions will result in fault */
414 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
416 unsigned nr = vcpu->arch.exception.nr;
417 bool has_payload = vcpu->arch.exception.has_payload;
418 unsigned long payload = vcpu->arch.exception.payload;
426 * "Certain debug exceptions may clear bit 0-3. The
427 * remaining contents of the DR6 register are never
428 * cleared by the processor".
430 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
432 * DR6.RTM is set by all #DB exceptions that don't clear it.
434 vcpu->arch.dr6 |= DR6_RTM;
435 vcpu->arch.dr6 |= payload;
437 * Bit 16 should be set in the payload whenever the #DB
438 * exception should clear DR6.RTM. This makes the payload
439 * compatible with the pending debug exceptions under VMX.
440 * Though not currently documented in the SDM, this also
441 * makes the payload compatible with the exit qualification
442 * for #DB exceptions under VMX.
444 vcpu->arch.dr6 ^= payload & DR6_RTM;
447 vcpu->arch.cr2 = payload;
451 vcpu->arch.exception.has_payload = false;
452 vcpu->arch.exception.payload = 0;
454 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
456 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
457 unsigned nr, bool has_error, u32 error_code,
458 bool has_payload, unsigned long payload, bool reinject)
463 kvm_make_request(KVM_REQ_EVENT, vcpu);
465 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
467 if (has_error && !is_protmode(vcpu))
471 * On vmentry, vcpu->arch.exception.pending is only
472 * true if an event injection was blocked by
473 * nested_run_pending. In that case, however,
474 * vcpu_enter_guest requests an immediate exit,
475 * and the guest shouldn't proceed far enough to
478 WARN_ON_ONCE(vcpu->arch.exception.pending);
479 vcpu->arch.exception.injected = true;
480 if (WARN_ON_ONCE(has_payload)) {
482 * A reinjected event has already
483 * delivered its payload.
489 vcpu->arch.exception.pending = true;
490 vcpu->arch.exception.injected = false;
492 vcpu->arch.exception.has_error_code = has_error;
493 vcpu->arch.exception.nr = nr;
494 vcpu->arch.exception.error_code = error_code;
495 vcpu->arch.exception.has_payload = has_payload;
496 vcpu->arch.exception.payload = payload;
498 * In guest mode, payload delivery should be deferred,
499 * so that the L1 hypervisor can intercept #PF before
500 * CR2 is modified (or intercept #DB before DR6 is
501 * modified under nVMX). However, for ABI
502 * compatibility with KVM_GET_VCPU_EVENTS and
503 * KVM_SET_VCPU_EVENTS, we can't delay payload
504 * delivery unless userspace has enabled this
505 * functionality via the per-VM capability,
506 * KVM_CAP_EXCEPTION_PAYLOAD.
508 if (!vcpu->kvm->arch.exception_payload_enabled ||
509 !is_guest_mode(vcpu))
510 kvm_deliver_exception_payload(vcpu);
514 /* to check exception */
515 prev_nr = vcpu->arch.exception.nr;
516 if (prev_nr == DF_VECTOR) {
517 /* triple fault -> shutdown */
518 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
521 class1 = exception_class(prev_nr);
522 class2 = exception_class(nr);
523 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
524 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
526 * Generate double fault per SDM Table 5-5. Set
527 * exception.pending = true so that the double fault
528 * can trigger a nested vmexit.
530 vcpu->arch.exception.pending = true;
531 vcpu->arch.exception.injected = false;
532 vcpu->arch.exception.has_error_code = true;
533 vcpu->arch.exception.nr = DF_VECTOR;
534 vcpu->arch.exception.error_code = 0;
535 vcpu->arch.exception.has_payload = false;
536 vcpu->arch.exception.payload = 0;
538 /* replace previous exception with a new one in a hope
539 that instruction re-execution will regenerate lost
544 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
546 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
548 EXPORT_SYMBOL_GPL(kvm_queue_exception);
550 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
552 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
554 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
556 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
557 unsigned long payload)
559 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
562 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
563 u32 error_code, unsigned long payload)
565 kvm_multiple_exception(vcpu, nr, true, error_code,
566 true, payload, false);
569 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
572 kvm_inject_gp(vcpu, 0);
574 return kvm_skip_emulated_instruction(vcpu);
578 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
580 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
582 ++vcpu->stat.pf_guest;
583 vcpu->arch.exception.nested_apf =
584 is_guest_mode(vcpu) && fault->async_page_fault;
585 if (vcpu->arch.exception.nested_apf) {
586 vcpu->arch.apf.nested_apf_token = fault->address;
587 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
589 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
593 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
595 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
597 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
598 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
600 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
602 return fault->nested_page_fault;
605 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
607 atomic_inc(&vcpu->arch.nmi_queued);
608 kvm_make_request(KVM_REQ_NMI, vcpu);
610 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
612 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
614 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
616 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
618 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
620 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
622 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
625 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
626 * a #GP and return false.
628 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
630 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
632 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
635 EXPORT_SYMBOL_GPL(kvm_require_cpl);
637 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
639 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
642 kvm_queue_exception(vcpu, UD_VECTOR);
645 EXPORT_SYMBOL_GPL(kvm_require_dr);
648 * This function will be used to read from the physical memory of the currently
649 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
650 * can read from guest physical or from the guest's guest physical memory.
652 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
653 gfn_t ngfn, void *data, int offset, int len,
656 struct x86_exception exception;
660 ngpa = gfn_to_gpa(ngfn);
661 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
662 if (real_gfn == UNMAPPED_GVA)
665 real_gfn = gpa_to_gfn(real_gfn);
667 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
669 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
671 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
672 void *data, int offset, int len, u32 access)
674 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
675 data, offset, len, access);
678 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
680 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
685 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
687 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
689 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
690 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
693 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
695 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
696 offset * sizeof(u64), sizeof(pdpte),
697 PFERR_USER_MASK|PFERR_WRITE_MASK);
702 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
703 if ((pdpte[i] & PT_PRESENT_MASK) &&
704 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
711 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
712 __set_bit(VCPU_EXREG_PDPTR,
713 (unsigned long *)&vcpu->arch.regs_avail);
714 __set_bit(VCPU_EXREG_PDPTR,
715 (unsigned long *)&vcpu->arch.regs_dirty);
720 EXPORT_SYMBOL_GPL(load_pdptrs);
722 bool pdptrs_changed(struct kvm_vcpu *vcpu)
724 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
730 if (!is_pae_paging(vcpu))
733 if (!test_bit(VCPU_EXREG_PDPTR,
734 (unsigned long *)&vcpu->arch.regs_avail))
737 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
738 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
739 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
740 PFERR_USER_MASK | PFERR_WRITE_MASK);
743 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
748 EXPORT_SYMBOL_GPL(pdptrs_changed);
750 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
752 unsigned long old_cr0 = kvm_read_cr0(vcpu);
753 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
758 if (cr0 & 0xffffffff00000000UL)
762 cr0 &= ~CR0_RESERVED_BITS;
764 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
767 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
770 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
772 if ((vcpu->arch.efer & EFER_LME)) {
777 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
782 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
787 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
790 kvm_x86_ops->set_cr0(vcpu, cr0);
792 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
793 kvm_clear_async_pf_completion_queue(vcpu);
794 kvm_async_pf_hash_reset(vcpu);
797 if ((cr0 ^ old_cr0) & update_bits)
798 kvm_mmu_reset_context(vcpu);
800 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
801 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
802 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
803 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
807 EXPORT_SYMBOL_GPL(kvm_set_cr0);
809 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
811 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
813 EXPORT_SYMBOL_GPL(kvm_lmsw);
815 void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
817 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
818 !vcpu->guest_xcr0_loaded) {
819 /* kvm_set_xcr() also depends on this */
820 if (vcpu->arch.xcr0 != host_xcr0)
821 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
822 vcpu->guest_xcr0_loaded = 1;
825 EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
827 void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
829 if (vcpu->guest_xcr0_loaded) {
830 if (vcpu->arch.xcr0 != host_xcr0)
831 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
832 vcpu->guest_xcr0_loaded = 0;
835 EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
837 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
840 u64 old_xcr0 = vcpu->arch.xcr0;
843 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
844 if (index != XCR_XFEATURE_ENABLED_MASK)
846 if (!(xcr0 & XFEATURE_MASK_FP))
848 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
852 * Do not allow the guest to set bits that we do not support
853 * saving. However, xcr0 bit 0 is always set, even if the
854 * emulated CPU does not support XSAVE (see fx_init).
856 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
857 if (xcr0 & ~valid_bits)
860 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
861 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
864 if (xcr0 & XFEATURE_MASK_AVX512) {
865 if (!(xcr0 & XFEATURE_MASK_YMM))
867 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
870 vcpu->arch.xcr0 = xcr0;
872 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
873 kvm_update_cpuid(vcpu);
877 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
879 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
880 __kvm_set_xcr(vcpu, index, xcr)) {
881 kvm_inject_gp(vcpu, 0);
886 EXPORT_SYMBOL_GPL(kvm_set_xcr);
888 static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
890 if (cr4 & CR4_RESERVED_BITS)
893 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
896 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
899 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
902 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
905 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
908 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
911 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
917 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
919 unsigned long old_cr4 = kvm_read_cr4(vcpu);
920 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
921 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
923 if (kvm_valid_cr4(vcpu, cr4))
926 if (is_long_mode(vcpu)) {
927 if (!(cr4 & X86_CR4_PAE))
929 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
930 && ((cr4 ^ old_cr4) & pdptr_bits)
931 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
935 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
936 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
939 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
940 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
944 if (kvm_x86_ops->set_cr4(vcpu, cr4))
947 if (((cr4 ^ old_cr4) & pdptr_bits) ||
948 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
949 kvm_mmu_reset_context(vcpu);
951 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
952 kvm_update_cpuid(vcpu);
956 EXPORT_SYMBOL_GPL(kvm_set_cr4);
958 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
960 bool skip_tlb_flush = false;
962 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
965 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
966 cr3 &= ~X86_CR3_PCID_NOFLUSH;
970 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
971 if (!skip_tlb_flush) {
972 kvm_mmu_sync_roots(vcpu);
973 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
978 if (is_long_mode(vcpu) &&
979 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
981 else if (is_pae_paging(vcpu) &&
982 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
985 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
986 vcpu->arch.cr3 = cr3;
987 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
991 EXPORT_SYMBOL_GPL(kvm_set_cr3);
993 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
995 if (cr8 & CR8_RESERVED_BITS)
997 if (lapic_in_kernel(vcpu))
998 kvm_lapic_set_tpr(vcpu, cr8);
1000 vcpu->arch.cr8 = cr8;
1003 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1005 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1007 if (lapic_in_kernel(vcpu))
1008 return kvm_lapic_get_cr8(vcpu);
1010 return vcpu->arch.cr8;
1012 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1014 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1018 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1019 for (i = 0; i < KVM_NR_DB_REGS; i++)
1020 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1021 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1025 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1027 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1028 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1031 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1035 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1036 dr7 = vcpu->arch.guest_debug_dr7;
1038 dr7 = vcpu->arch.dr7;
1039 kvm_x86_ops->set_dr7(vcpu, dr7);
1040 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1041 if (dr7 & DR7_BP_EN_MASK)
1042 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1045 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1047 u64 fixed = DR6_FIXED_1;
1049 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1054 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1058 vcpu->arch.db[dr] = val;
1059 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1060 vcpu->arch.eff_db[dr] = val;
1065 if (val & 0xffffffff00000000ULL)
1066 return -1; /* #GP */
1067 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1068 kvm_update_dr6(vcpu);
1073 if (val & 0xffffffff00000000ULL)
1074 return -1; /* #GP */
1075 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1076 kvm_update_dr7(vcpu);
1083 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1085 if (__kvm_set_dr(vcpu, dr, val)) {
1086 kvm_inject_gp(vcpu, 0);
1091 EXPORT_SYMBOL_GPL(kvm_set_dr);
1093 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1097 *val = vcpu->arch.db[dr];
1102 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1103 *val = vcpu->arch.dr6;
1105 *val = kvm_x86_ops->get_dr6(vcpu);
1110 *val = vcpu->arch.dr7;
1115 EXPORT_SYMBOL_GPL(kvm_get_dr);
1117 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1119 u32 ecx = kvm_rcx_read(vcpu);
1123 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1126 kvm_rax_write(vcpu, (u32)data);
1127 kvm_rdx_write(vcpu, data >> 32);
1130 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1133 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1134 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1136 * This list is modified at module load time to reflect the
1137 * capabilities of the host cpu. This capabilities test skips MSRs that are
1138 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1139 * may depend on host virtualization features rather than host cpu features.
1142 static u32 msrs_to_save[] = {
1143 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1145 #ifdef CONFIG_X86_64
1146 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1148 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1149 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1151 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1152 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1153 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1154 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1155 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1156 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1157 MSR_IA32_UMWAIT_CONTROL,
1159 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1160 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1161 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1162 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1163 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1164 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1165 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1166 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1167 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1168 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1169 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1170 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1171 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1172 MSR_ARCH_PERFMON_PERFCTR0 + 18, MSR_ARCH_PERFMON_PERFCTR0 + 19,
1173 MSR_ARCH_PERFMON_PERFCTR0 + 20, MSR_ARCH_PERFMON_PERFCTR0 + 21,
1174 MSR_ARCH_PERFMON_PERFCTR0 + 22, MSR_ARCH_PERFMON_PERFCTR0 + 23,
1175 MSR_ARCH_PERFMON_PERFCTR0 + 24, MSR_ARCH_PERFMON_PERFCTR0 + 25,
1176 MSR_ARCH_PERFMON_PERFCTR0 + 26, MSR_ARCH_PERFMON_PERFCTR0 + 27,
1177 MSR_ARCH_PERFMON_PERFCTR0 + 28, MSR_ARCH_PERFMON_PERFCTR0 + 29,
1178 MSR_ARCH_PERFMON_PERFCTR0 + 30, MSR_ARCH_PERFMON_PERFCTR0 + 31,
1179 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1180 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1181 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1182 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1183 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1184 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1185 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1186 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1187 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1188 MSR_ARCH_PERFMON_EVENTSEL0 + 18, MSR_ARCH_PERFMON_EVENTSEL0 + 19,
1189 MSR_ARCH_PERFMON_EVENTSEL0 + 20, MSR_ARCH_PERFMON_EVENTSEL0 + 21,
1190 MSR_ARCH_PERFMON_EVENTSEL0 + 22, MSR_ARCH_PERFMON_EVENTSEL0 + 23,
1191 MSR_ARCH_PERFMON_EVENTSEL0 + 24, MSR_ARCH_PERFMON_EVENTSEL0 + 25,
1192 MSR_ARCH_PERFMON_EVENTSEL0 + 26, MSR_ARCH_PERFMON_EVENTSEL0 + 27,
1193 MSR_ARCH_PERFMON_EVENTSEL0 + 28, MSR_ARCH_PERFMON_EVENTSEL0 + 29,
1194 MSR_ARCH_PERFMON_EVENTSEL0 + 30, MSR_ARCH_PERFMON_EVENTSEL0 + 31,
1197 static unsigned num_msrs_to_save;
1199 static u32 emulated_msrs[] = {
1200 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1201 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1202 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1203 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1204 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1205 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1206 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1208 HV_X64_MSR_VP_INDEX,
1209 HV_X64_MSR_VP_RUNTIME,
1210 HV_X64_MSR_SCONTROL,
1211 HV_X64_MSR_STIMER0_CONFIG,
1212 HV_X64_MSR_VP_ASSIST_PAGE,
1213 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1214 HV_X64_MSR_TSC_EMULATION_STATUS,
1216 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1219 MSR_IA32_TSC_ADJUST,
1220 MSR_IA32_TSCDEADLINE,
1221 MSR_IA32_ARCH_CAPABILITIES,
1222 MSR_IA32_MISC_ENABLE,
1223 MSR_IA32_MCG_STATUS,
1225 MSR_IA32_MCG_EXT_CTL,
1229 MSR_MISC_FEATURES_ENABLES,
1230 MSR_AMD64_VIRT_SPEC_CTRL,
1234 * The following list leaves out MSRs whose values are determined
1235 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1236 * We always support the "true" VMX control MSRs, even if the host
1237 * processor does not, so I am putting these registers here rather
1238 * than in msrs_to_save.
1241 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1242 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1243 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1244 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1246 MSR_IA32_VMX_CR0_FIXED0,
1247 MSR_IA32_VMX_CR4_FIXED0,
1248 MSR_IA32_VMX_VMCS_ENUM,
1249 MSR_IA32_VMX_PROCBASED_CTLS2,
1250 MSR_IA32_VMX_EPT_VPID_CAP,
1251 MSR_IA32_VMX_VMFUNC,
1254 MSR_KVM_POLL_CONTROL,
1257 static unsigned num_emulated_msrs;
1260 * List of msr numbers which are used to expose MSR-based features that
1261 * can be used by a hypervisor to validate requested CPU features.
1263 static u32 msr_based_features[] = {
1265 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1266 MSR_IA32_VMX_PINBASED_CTLS,
1267 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1268 MSR_IA32_VMX_PROCBASED_CTLS,
1269 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1270 MSR_IA32_VMX_EXIT_CTLS,
1271 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1272 MSR_IA32_VMX_ENTRY_CTLS,
1274 MSR_IA32_VMX_CR0_FIXED0,
1275 MSR_IA32_VMX_CR0_FIXED1,
1276 MSR_IA32_VMX_CR4_FIXED0,
1277 MSR_IA32_VMX_CR4_FIXED1,
1278 MSR_IA32_VMX_VMCS_ENUM,
1279 MSR_IA32_VMX_PROCBASED_CTLS2,
1280 MSR_IA32_VMX_EPT_VPID_CAP,
1281 MSR_IA32_VMX_VMFUNC,
1285 MSR_IA32_ARCH_CAPABILITIES,
1288 static unsigned int num_msr_based_features;
1290 static u64 kvm_get_arch_capabilities(void)
1294 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1295 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1298 * If we're doing cache flushes (either "always" or "cond")
1299 * we will do one whenever the guest does a vmlaunch/vmresume.
1300 * If an outer hypervisor is doing the cache flush for us
1301 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1302 * capability to the guest too, and if EPT is disabled we're not
1303 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1304 * require a nested hypervisor to do a flush of its own.
1306 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1307 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1309 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1310 data |= ARCH_CAP_RDCL_NO;
1311 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1312 data |= ARCH_CAP_SSB_NO;
1313 if (!boot_cpu_has_bug(X86_BUG_MDS))
1314 data |= ARCH_CAP_MDS_NO;
1319 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1321 switch (msr->index) {
1322 case MSR_IA32_ARCH_CAPABILITIES:
1323 msr->data = kvm_get_arch_capabilities();
1325 case MSR_IA32_UCODE_REV:
1326 rdmsrl_safe(msr->index, &msr->data);
1329 if (kvm_x86_ops->get_msr_feature(msr))
1335 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1337 struct kvm_msr_entry msr;
1341 r = kvm_get_msr_feature(&msr);
1350 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1352 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1355 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1358 if (efer & (EFER_LME | EFER_LMA) &&
1359 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1362 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1368 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1370 if (efer & efer_reserved_bits)
1373 return __kvm_valid_efer(vcpu, efer);
1375 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1377 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1379 u64 old_efer = vcpu->arch.efer;
1380 u64 efer = msr_info->data;
1382 if (efer & efer_reserved_bits)
1385 if (!msr_info->host_initiated) {
1386 if (!__kvm_valid_efer(vcpu, efer))
1389 if (is_paging(vcpu) &&
1390 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1395 efer |= vcpu->arch.efer & EFER_LMA;
1397 kvm_x86_ops->set_efer(vcpu, efer);
1399 /* Update reserved bits */
1400 if ((efer ^ old_efer) & EFER_NX)
1401 kvm_mmu_reset_context(vcpu);
1406 void kvm_enable_efer_bits(u64 mask)
1408 efer_reserved_bits &= ~mask;
1410 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1413 * Write @data into the MSR specified by @index. Select MSR specific fault
1414 * checks are bypassed if @host_initiated is %true.
1415 * Returns 0 on success, non-0 otherwise.
1416 * Assumes vcpu_load() was already called.
1418 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1419 bool host_initiated)
1421 struct msr_data msr;
1426 case MSR_KERNEL_GS_BASE:
1429 if (is_noncanonical_address(data, vcpu))
1432 case MSR_IA32_SYSENTER_EIP:
1433 case MSR_IA32_SYSENTER_ESP:
1435 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1436 * non-canonical address is written on Intel but not on
1437 * AMD (which ignores the top 32-bits, because it does
1438 * not implement 64-bit SYSENTER).
1440 * 64-bit code should hence be able to write a non-canonical
1441 * value on AMD. Making the address canonical ensures that
1442 * vmentry does not fail on Intel after writing a non-canonical
1443 * value, and that something deterministic happens if the guest
1444 * invokes 64-bit SYSENTER.
1446 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1451 msr.host_initiated = host_initiated;
1453 return kvm_x86_ops->set_msr(vcpu, &msr);
1457 * Read the MSR specified by @index into @data. Select MSR specific fault
1458 * checks are bypassed if @host_initiated is %true.
1459 * Returns 0 on success, non-0 otherwise.
1460 * Assumes vcpu_load() was already called.
1462 static int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1463 bool host_initiated)
1465 struct msr_data msr;
1469 msr.host_initiated = host_initiated;
1471 ret = kvm_x86_ops->get_msr(vcpu, &msr);
1477 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1479 return __kvm_get_msr(vcpu, index, data, false);
1481 EXPORT_SYMBOL_GPL(kvm_get_msr);
1483 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1485 return __kvm_set_msr(vcpu, index, data, false);
1487 EXPORT_SYMBOL_GPL(kvm_set_msr);
1489 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1491 u32 ecx = kvm_rcx_read(vcpu);
1494 if (kvm_get_msr(vcpu, ecx, &data)) {
1495 trace_kvm_msr_read_ex(ecx);
1496 kvm_inject_gp(vcpu, 0);
1500 trace_kvm_msr_read(ecx, data);
1502 kvm_rax_write(vcpu, data & -1u);
1503 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1504 return kvm_skip_emulated_instruction(vcpu);
1506 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1508 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1510 u32 ecx = kvm_rcx_read(vcpu);
1511 u64 data = kvm_read_edx_eax(vcpu);
1513 if (kvm_set_msr(vcpu, ecx, data)) {
1514 trace_kvm_msr_write_ex(ecx, data);
1515 kvm_inject_gp(vcpu, 0);
1519 trace_kvm_msr_write(ecx, data);
1520 return kvm_skip_emulated_instruction(vcpu);
1522 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1525 * Adapt set_msr() to msr_io()'s calling convention
1527 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1529 return __kvm_get_msr(vcpu, index, data, true);
1532 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1534 return __kvm_set_msr(vcpu, index, *data, true);
1537 #ifdef CONFIG_X86_64
1538 struct pvclock_gtod_data {
1541 struct { /* extract of a clocksource struct */
1554 static struct pvclock_gtod_data pvclock_gtod_data;
1556 static void update_pvclock_gtod(struct timekeeper *tk)
1558 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1561 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1563 write_seqcount_begin(&vdata->seq);
1565 /* copy pvclock gtod data */
1566 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1567 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1568 vdata->clock.mask = tk->tkr_mono.mask;
1569 vdata->clock.mult = tk->tkr_mono.mult;
1570 vdata->clock.shift = tk->tkr_mono.shift;
1572 vdata->boot_ns = boot_ns;
1573 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1575 vdata->wall_time_sec = tk->xtime_sec;
1577 write_seqcount_end(&vdata->seq);
1581 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1583 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1584 kvm_vcpu_kick(vcpu);
1587 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1591 struct pvclock_wall_clock wc;
1592 struct timespec64 boot;
1597 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1602 ++version; /* first time write, random junk */
1606 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1610 * The guest calculates current wall clock time by adding
1611 * system time (updated by kvm_guest_time_update below) to the
1612 * wall clock specified here. guest system time equals host
1613 * system time for us, thus we must fill in host boot time here.
1615 getboottime64(&boot);
1617 if (kvm->arch.kvmclock_offset) {
1618 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1619 boot = timespec64_sub(boot, ts);
1621 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1622 wc.nsec = boot.tv_nsec;
1623 wc.version = version;
1625 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1628 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1631 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1633 do_shl32_div32(dividend, divisor);
1637 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1638 s8 *pshift, u32 *pmultiplier)
1646 scaled64 = scaled_hz;
1647 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1652 tps32 = (uint32_t)tps64;
1653 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1654 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1662 *pmultiplier = div_frac(scaled64, tps32);
1665 #ifdef CONFIG_X86_64
1666 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1669 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1670 static unsigned long max_tsc_khz;
1672 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1674 u64 v = (u64)khz * (1000000 + ppm);
1679 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1683 /* Guest TSC same frequency as host TSC? */
1685 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1689 /* TSC scaling supported? */
1690 if (!kvm_has_tsc_control) {
1691 if (user_tsc_khz > tsc_khz) {
1692 vcpu->arch.tsc_catchup = 1;
1693 vcpu->arch.tsc_always_catchup = 1;
1696 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1701 /* TSC scaling required - calculate ratio */
1702 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1703 user_tsc_khz, tsc_khz);
1705 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1706 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1711 vcpu->arch.tsc_scaling_ratio = ratio;
1715 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1717 u32 thresh_lo, thresh_hi;
1718 int use_scaling = 0;
1720 /* tsc_khz can be zero if TSC calibration fails */
1721 if (user_tsc_khz == 0) {
1722 /* set tsc_scaling_ratio to a safe value */
1723 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1727 /* Compute a scale to convert nanoseconds in TSC cycles */
1728 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1729 &vcpu->arch.virtual_tsc_shift,
1730 &vcpu->arch.virtual_tsc_mult);
1731 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1734 * Compute the variation in TSC rate which is acceptable
1735 * within the range of tolerance and decide if the
1736 * rate being applied is within that bounds of the hardware
1737 * rate. If so, no scaling or compensation need be done.
1739 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1740 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1741 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1742 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1745 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1748 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1750 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1751 vcpu->arch.virtual_tsc_mult,
1752 vcpu->arch.virtual_tsc_shift);
1753 tsc += vcpu->arch.this_tsc_write;
1757 static inline int gtod_is_based_on_tsc(int mode)
1759 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1762 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1764 #ifdef CONFIG_X86_64
1766 struct kvm_arch *ka = &vcpu->kvm->arch;
1767 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1769 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1770 atomic_read(&vcpu->kvm->online_vcpus));
1773 * Once the masterclock is enabled, always perform request in
1774 * order to update it.
1776 * In order to enable masterclock, the host clocksource must be TSC
1777 * and the vcpus need to have matched TSCs. When that happens,
1778 * perform request to enable masterclock.
1780 if (ka->use_master_clock ||
1781 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1782 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1784 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1785 atomic_read(&vcpu->kvm->online_vcpus),
1786 ka->use_master_clock, gtod->clock.vclock_mode);
1790 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1792 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1793 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1797 * Multiply tsc by a fixed point number represented by ratio.
1799 * The most significant 64-N bits (mult) of ratio represent the
1800 * integral part of the fixed point number; the remaining N bits
1801 * (frac) represent the fractional part, ie. ratio represents a fixed
1802 * point number (mult + frac * 2^(-N)).
1804 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1806 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1808 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1811 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1814 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1816 if (ratio != kvm_default_tsc_scaling_ratio)
1817 _tsc = __scale_tsc(ratio, tsc);
1821 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1823 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1827 tsc = kvm_scale_tsc(vcpu, rdtsc());
1829 return target_tsc - tsc;
1832 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1834 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1836 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1838 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1840 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1842 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1845 static inline bool kvm_check_tsc_unstable(void)
1847 #ifdef CONFIG_X86_64
1849 * TSC is marked unstable when we're running on Hyper-V,
1850 * 'TSC page' clocksource is good.
1852 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1855 return check_tsc_unstable();
1858 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1860 struct kvm *kvm = vcpu->kvm;
1861 u64 offset, ns, elapsed;
1862 unsigned long flags;
1864 bool already_matched;
1865 u64 data = msr->data;
1866 bool synchronizing = false;
1868 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1869 offset = kvm_compute_tsc_offset(vcpu, data);
1870 ns = ktime_get_boottime_ns();
1871 elapsed = ns - kvm->arch.last_tsc_nsec;
1873 if (vcpu->arch.virtual_tsc_khz) {
1874 if (data == 0 && msr->host_initiated) {
1876 * detection of vcpu initialization -- need to sync
1877 * with other vCPUs. This particularly helps to keep
1878 * kvm_clock stable after CPU hotplug
1880 synchronizing = true;
1882 u64 tsc_exp = kvm->arch.last_tsc_write +
1883 nsec_to_cycles(vcpu, elapsed);
1884 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1886 * Special case: TSC write with a small delta (1 second)
1887 * of virtual cycle time against real time is
1888 * interpreted as an attempt to synchronize the CPU.
1890 synchronizing = data < tsc_exp + tsc_hz &&
1891 data + tsc_hz > tsc_exp;
1896 * For a reliable TSC, we can match TSC offsets, and for an unstable
1897 * TSC, we add elapsed time in this computation. We could let the
1898 * compensation code attempt to catch up if we fall behind, but
1899 * it's better to try to match offsets from the beginning.
1901 if (synchronizing &&
1902 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1903 if (!kvm_check_tsc_unstable()) {
1904 offset = kvm->arch.cur_tsc_offset;
1906 u64 delta = nsec_to_cycles(vcpu, elapsed);
1908 offset = kvm_compute_tsc_offset(vcpu, data);
1911 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1914 * We split periods of matched TSC writes into generations.
1915 * For each generation, we track the original measured
1916 * nanosecond time, offset, and write, so if TSCs are in
1917 * sync, we can match exact offset, and if not, we can match
1918 * exact software computation in compute_guest_tsc()
1920 * These values are tracked in kvm->arch.cur_xxx variables.
1922 kvm->arch.cur_tsc_generation++;
1923 kvm->arch.cur_tsc_nsec = ns;
1924 kvm->arch.cur_tsc_write = data;
1925 kvm->arch.cur_tsc_offset = offset;
1930 * We also track th most recent recorded KHZ, write and time to
1931 * allow the matching interval to be extended at each write.
1933 kvm->arch.last_tsc_nsec = ns;
1934 kvm->arch.last_tsc_write = data;
1935 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1937 vcpu->arch.last_guest_tsc = data;
1939 /* Keep track of which generation this VCPU has synchronized to */
1940 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1941 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1942 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1944 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1945 update_ia32_tsc_adjust_msr(vcpu, offset);
1947 kvm_vcpu_write_tsc_offset(vcpu, offset);
1948 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1950 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1952 kvm->arch.nr_vcpus_matched_tsc = 0;
1953 } else if (!already_matched) {
1954 kvm->arch.nr_vcpus_matched_tsc++;
1957 kvm_track_tsc_matching(vcpu);
1958 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1961 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1963 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1966 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1967 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
1970 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1972 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1973 WARN_ON(adjustment < 0);
1974 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1975 adjust_tsc_offset_guest(vcpu, adjustment);
1978 #ifdef CONFIG_X86_64
1980 static u64 read_tsc(void)
1982 u64 ret = (u64)rdtsc_ordered();
1983 u64 last = pvclock_gtod_data.clock.cycle_last;
1985 if (likely(ret >= last))
1989 * GCC likes to generate cmov here, but this branch is extremely
1990 * predictable (it's just a function of time and the likely is
1991 * very likely) and there's a data dependence, so force GCC
1992 * to generate a branch instead. I don't barrier() because
1993 * we don't actually need a barrier, and if this function
1994 * ever gets inlined it will generate worse code.
2000 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
2003 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2006 switch (gtod->clock.vclock_mode) {
2007 case VCLOCK_HVCLOCK:
2008 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2010 if (tsc_pg_val != U64_MAX) {
2011 /* TSC page valid */
2012 *mode = VCLOCK_HVCLOCK;
2013 v = (tsc_pg_val - gtod->clock.cycle_last) &
2016 /* TSC page invalid */
2017 *mode = VCLOCK_NONE;
2022 *tsc_timestamp = read_tsc();
2023 v = (*tsc_timestamp - gtod->clock.cycle_last) &
2027 *mode = VCLOCK_NONE;
2030 if (*mode == VCLOCK_NONE)
2031 *tsc_timestamp = v = 0;
2033 return v * gtod->clock.mult;
2036 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
2038 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2044 seq = read_seqcount_begin(>od->seq);
2045 ns = gtod->nsec_base;
2046 ns += vgettsc(tsc_timestamp, &mode);
2047 ns >>= gtod->clock.shift;
2048 ns += gtod->boot_ns;
2049 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2055 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2057 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2063 seq = read_seqcount_begin(>od->seq);
2064 ts->tv_sec = gtod->wall_time_sec;
2065 ns = gtod->nsec_base;
2066 ns += vgettsc(tsc_timestamp, &mode);
2067 ns >>= gtod->clock.shift;
2068 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2070 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2076 /* returns true if host is using TSC based clocksource */
2077 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2079 /* checked again under seqlock below */
2080 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2083 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
2087 /* returns true if host is using TSC based clocksource */
2088 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2091 /* checked again under seqlock below */
2092 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2095 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2101 * Assuming a stable TSC across physical CPUS, and a stable TSC
2102 * across virtual CPUs, the following condition is possible.
2103 * Each numbered line represents an event visible to both
2104 * CPUs at the next numbered event.
2106 * "timespecX" represents host monotonic time. "tscX" represents
2109 * VCPU0 on CPU0 | VCPU1 on CPU1
2111 * 1. read timespec0,tsc0
2112 * 2. | timespec1 = timespec0 + N
2114 * 3. transition to guest | transition to guest
2115 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2116 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2117 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2119 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2122 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2124 * - 0 < N - M => M < N
2126 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2127 * always the case (the difference between two distinct xtime instances
2128 * might be smaller then the difference between corresponding TSC reads,
2129 * when updating guest vcpus pvclock areas).
2131 * To avoid that problem, do not allow visibility of distinct
2132 * system_timestamp/tsc_timestamp values simultaneously: use a master
2133 * copy of host monotonic time values. Update that master copy
2136 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2140 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2142 #ifdef CONFIG_X86_64
2143 struct kvm_arch *ka = &kvm->arch;
2145 bool host_tsc_clocksource, vcpus_matched;
2147 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2148 atomic_read(&kvm->online_vcpus));
2151 * If the host uses TSC clock, then passthrough TSC as stable
2154 host_tsc_clocksource = kvm_get_time_and_clockread(
2155 &ka->master_kernel_ns,
2156 &ka->master_cycle_now);
2158 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2159 && !ka->backwards_tsc_observed
2160 && !ka->boot_vcpu_runs_old_kvmclock;
2162 if (ka->use_master_clock)
2163 atomic_set(&kvm_guest_has_master_clock, 1);
2165 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2166 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2171 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2173 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2176 static void kvm_gen_update_masterclock(struct kvm *kvm)
2178 #ifdef CONFIG_X86_64
2180 struct kvm_vcpu *vcpu;
2181 struct kvm_arch *ka = &kvm->arch;
2183 spin_lock(&ka->pvclock_gtod_sync_lock);
2184 kvm_make_mclock_inprogress_request(kvm);
2185 /* no guest entries from this point */
2186 pvclock_update_vm_gtod_copy(kvm);
2188 kvm_for_each_vcpu(i, vcpu, kvm)
2189 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2191 /* guest entries allowed */
2192 kvm_for_each_vcpu(i, vcpu, kvm)
2193 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2195 spin_unlock(&ka->pvclock_gtod_sync_lock);
2199 u64 get_kvmclock_ns(struct kvm *kvm)
2201 struct kvm_arch *ka = &kvm->arch;
2202 struct pvclock_vcpu_time_info hv_clock;
2205 spin_lock(&ka->pvclock_gtod_sync_lock);
2206 if (!ka->use_master_clock) {
2207 spin_unlock(&ka->pvclock_gtod_sync_lock);
2208 return ktime_get_boottime_ns() + ka->kvmclock_offset;
2211 hv_clock.tsc_timestamp = ka->master_cycle_now;
2212 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2213 spin_unlock(&ka->pvclock_gtod_sync_lock);
2215 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2218 if (__this_cpu_read(cpu_tsc_khz)) {
2219 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2220 &hv_clock.tsc_shift,
2221 &hv_clock.tsc_to_system_mul);
2222 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2224 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
2231 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2233 struct kvm_vcpu_arch *vcpu = &v->arch;
2234 struct pvclock_vcpu_time_info guest_hv_clock;
2236 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2237 &guest_hv_clock, sizeof(guest_hv_clock))))
2240 /* This VCPU is paused, but it's legal for a guest to read another
2241 * VCPU's kvmclock, so we really have to follow the specification where
2242 * it says that version is odd if data is being modified, and even after
2245 * Version field updates must be kept separate. This is because
2246 * kvm_write_guest_cached might use a "rep movs" instruction, and
2247 * writes within a string instruction are weakly ordered. So there
2248 * are three writes overall.
2250 * As a small optimization, only write the version field in the first
2251 * and third write. The vcpu->pv_time cache is still valid, because the
2252 * version field is the first in the struct.
2254 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2256 if (guest_hv_clock.version & 1)
2257 ++guest_hv_clock.version; /* first time write, random junk */
2259 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2260 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2262 sizeof(vcpu->hv_clock.version));
2266 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2267 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2269 if (vcpu->pvclock_set_guest_stopped_request) {
2270 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2271 vcpu->pvclock_set_guest_stopped_request = false;
2274 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2276 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2278 sizeof(vcpu->hv_clock));
2282 vcpu->hv_clock.version++;
2283 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2285 sizeof(vcpu->hv_clock.version));
2288 static int kvm_guest_time_update(struct kvm_vcpu *v)
2290 unsigned long flags, tgt_tsc_khz;
2291 struct kvm_vcpu_arch *vcpu = &v->arch;
2292 struct kvm_arch *ka = &v->kvm->arch;
2294 u64 tsc_timestamp, host_tsc;
2296 bool use_master_clock;
2302 * If the host uses TSC clock, then passthrough TSC as stable
2305 spin_lock(&ka->pvclock_gtod_sync_lock);
2306 use_master_clock = ka->use_master_clock;
2307 if (use_master_clock) {
2308 host_tsc = ka->master_cycle_now;
2309 kernel_ns = ka->master_kernel_ns;
2311 spin_unlock(&ka->pvclock_gtod_sync_lock);
2313 /* Keep irq disabled to prevent changes to the clock */
2314 local_irq_save(flags);
2315 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2316 if (unlikely(tgt_tsc_khz == 0)) {
2317 local_irq_restore(flags);
2318 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2321 if (!use_master_clock) {
2323 kernel_ns = ktime_get_boottime_ns();
2326 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2329 * We may have to catch up the TSC to match elapsed wall clock
2330 * time for two reasons, even if kvmclock is used.
2331 * 1) CPU could have been running below the maximum TSC rate
2332 * 2) Broken TSC compensation resets the base at each VCPU
2333 * entry to avoid unknown leaps of TSC even when running
2334 * again on the same CPU. This may cause apparent elapsed
2335 * time to disappear, and the guest to stand still or run
2338 if (vcpu->tsc_catchup) {
2339 u64 tsc = compute_guest_tsc(v, kernel_ns);
2340 if (tsc > tsc_timestamp) {
2341 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2342 tsc_timestamp = tsc;
2346 local_irq_restore(flags);
2348 /* With all the info we got, fill in the values */
2350 if (kvm_has_tsc_control)
2351 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2353 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2354 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2355 &vcpu->hv_clock.tsc_shift,
2356 &vcpu->hv_clock.tsc_to_system_mul);
2357 vcpu->hw_tsc_khz = tgt_tsc_khz;
2360 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2361 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2362 vcpu->last_guest_tsc = tsc_timestamp;
2364 /* If the host uses TSC clocksource, then it is stable */
2366 if (use_master_clock)
2367 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2369 vcpu->hv_clock.flags = pvclock_flags;
2371 if (vcpu->pv_time_enabled)
2372 kvm_setup_pvclock_page(v);
2373 if (v == kvm_get_vcpu(v->kvm, 0))
2374 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2379 * kvmclock updates which are isolated to a given vcpu, such as
2380 * vcpu->cpu migration, should not allow system_timestamp from
2381 * the rest of the vcpus to remain static. Otherwise ntp frequency
2382 * correction applies to one vcpu's system_timestamp but not
2385 * So in those cases, request a kvmclock update for all vcpus.
2386 * We need to rate-limit these requests though, as they can
2387 * considerably slow guests that have a large number of vcpus.
2388 * The time for a remote vcpu to update its kvmclock is bound
2389 * by the delay we use to rate-limit the updates.
2392 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2394 static void kvmclock_update_fn(struct work_struct *work)
2397 struct delayed_work *dwork = to_delayed_work(work);
2398 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2399 kvmclock_update_work);
2400 struct kvm *kvm = container_of(ka, struct kvm, arch);
2401 struct kvm_vcpu *vcpu;
2403 kvm_for_each_vcpu(i, vcpu, kvm) {
2404 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2405 kvm_vcpu_kick(vcpu);
2409 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2411 struct kvm *kvm = v->kvm;
2413 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2414 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2415 KVMCLOCK_UPDATE_DELAY);
2418 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2420 static void kvmclock_sync_fn(struct work_struct *work)
2422 struct delayed_work *dwork = to_delayed_work(work);
2423 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2424 kvmclock_sync_work);
2425 struct kvm *kvm = container_of(ka, struct kvm, arch);
2427 if (!kvmclock_periodic_sync)
2430 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2431 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2432 KVMCLOCK_SYNC_PERIOD);
2436 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2438 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2440 /* McStatusWrEn enabled? */
2441 if (guest_cpuid_is_amd(vcpu))
2442 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2447 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2449 u64 mcg_cap = vcpu->arch.mcg_cap;
2450 unsigned bank_num = mcg_cap & 0xff;
2451 u32 msr = msr_info->index;
2452 u64 data = msr_info->data;
2455 case MSR_IA32_MCG_STATUS:
2456 vcpu->arch.mcg_status = data;
2458 case MSR_IA32_MCG_CTL:
2459 if (!(mcg_cap & MCG_CTL_P) &&
2460 (data || !msr_info->host_initiated))
2462 if (data != 0 && data != ~(u64)0)
2464 vcpu->arch.mcg_ctl = data;
2467 if (msr >= MSR_IA32_MC0_CTL &&
2468 msr < MSR_IA32_MCx_CTL(bank_num)) {
2469 u32 offset = msr - MSR_IA32_MC0_CTL;
2470 /* only 0 or all 1s can be written to IA32_MCi_CTL
2471 * some Linux kernels though clear bit 10 in bank 4 to
2472 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2473 * this to avoid an uncatched #GP in the guest
2475 if ((offset & 0x3) == 0 &&
2476 data != 0 && (data | (1 << 10)) != ~(u64)0)
2480 if (!msr_info->host_initiated &&
2481 (offset & 0x3) == 1 && data != 0) {
2482 if (!can_set_mci_status(vcpu))
2486 vcpu->arch.mce_banks[offset] = data;
2494 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2496 struct kvm *kvm = vcpu->kvm;
2497 int lm = is_long_mode(vcpu);
2498 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2499 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2500 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2501 : kvm->arch.xen_hvm_config.blob_size_32;
2502 u32 page_num = data & ~PAGE_MASK;
2503 u64 page_addr = data & PAGE_MASK;
2508 if (page_num >= blob_size)
2511 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2516 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2525 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2527 gpa_t gpa = data & ~0x3f;
2529 /* Bits 3:5 are reserved, Should be zero */
2533 vcpu->arch.apf.msr_val = data;
2535 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2536 kvm_clear_async_pf_completion_queue(vcpu);
2537 kvm_async_pf_hash_reset(vcpu);
2541 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2545 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2546 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2547 kvm_async_pf_wakeup_all(vcpu);
2551 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2553 vcpu->arch.pv_time_enabled = false;
2556 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2558 ++vcpu->stat.tlb_flush;
2559 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2562 static void record_steal_time(struct kvm_vcpu *vcpu)
2564 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2567 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2568 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2572 * Doing a TLB flush here, on the guest's behalf, can avoid
2575 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2576 vcpu->arch.st.steal.preempted & KVM_VCPU_FLUSH_TLB);
2577 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2578 kvm_vcpu_flush_tlb(vcpu, false);
2580 if (vcpu->arch.st.steal.version & 1)
2581 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2583 vcpu->arch.st.steal.version += 1;
2585 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2586 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2590 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2591 vcpu->arch.st.last_steal;
2592 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2594 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2595 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2599 vcpu->arch.st.steal.version += 1;
2601 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2602 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2605 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2608 u32 msr = msr_info->index;
2609 u64 data = msr_info->data;
2612 case MSR_AMD64_NB_CFG:
2613 case MSR_IA32_UCODE_WRITE:
2614 case MSR_VM_HSAVE_PA:
2615 case MSR_AMD64_PATCH_LOADER:
2616 case MSR_AMD64_BU_CFG2:
2617 case MSR_AMD64_DC_CFG:
2618 case MSR_F15H_EX_CFG:
2621 case MSR_IA32_UCODE_REV:
2622 if (msr_info->host_initiated)
2623 vcpu->arch.microcode_version = data;
2625 case MSR_IA32_ARCH_CAPABILITIES:
2626 if (!msr_info->host_initiated)
2628 vcpu->arch.arch_capabilities = data;
2631 return set_efer(vcpu, msr_info);
2633 data &= ~(u64)0x40; /* ignore flush filter disable */
2634 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2635 data &= ~(u64)0x8; /* ignore TLB cache disable */
2637 /* Handle McStatusWrEn */
2638 if (data == BIT_ULL(18)) {
2639 vcpu->arch.msr_hwcr = data;
2640 } else if (data != 0) {
2641 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2646 case MSR_FAM10H_MMIO_CONF_BASE:
2648 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2653 case MSR_IA32_DEBUGCTLMSR:
2655 /* We support the non-activated case already */
2657 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2658 /* Values other than LBR and BTF are vendor-specific,
2659 thus reserved and should throw a #GP */
2662 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2665 case 0x200 ... 0x2ff:
2666 return kvm_mtrr_set_msr(vcpu, msr, data);
2667 case MSR_IA32_APICBASE:
2668 return kvm_set_apic_base(vcpu, msr_info);
2669 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2670 return kvm_x2apic_msr_write(vcpu, msr, data);
2671 case MSR_IA32_TSCDEADLINE:
2672 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2674 case MSR_IA32_TSC_ADJUST:
2675 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2676 if (!msr_info->host_initiated) {
2677 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2678 adjust_tsc_offset_guest(vcpu, adj);
2680 vcpu->arch.ia32_tsc_adjust_msr = data;
2683 case MSR_IA32_MISC_ENABLE:
2684 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2685 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2686 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2688 vcpu->arch.ia32_misc_enable_msr = data;
2689 kvm_update_cpuid(vcpu);
2691 vcpu->arch.ia32_misc_enable_msr = data;
2694 case MSR_IA32_SMBASE:
2695 if (!msr_info->host_initiated)
2697 vcpu->arch.smbase = data;
2699 case MSR_IA32_POWER_CTL:
2700 vcpu->arch.msr_ia32_power_ctl = data;
2703 kvm_write_tsc(vcpu, msr_info);
2706 if (!msr_info->host_initiated)
2708 vcpu->arch.smi_count = data;
2710 case MSR_KVM_WALL_CLOCK_NEW:
2711 case MSR_KVM_WALL_CLOCK:
2712 vcpu->kvm->arch.wall_clock = data;
2713 kvm_write_wall_clock(vcpu->kvm, data);
2715 case MSR_KVM_SYSTEM_TIME_NEW:
2716 case MSR_KVM_SYSTEM_TIME: {
2717 struct kvm_arch *ka = &vcpu->kvm->arch;
2719 kvmclock_reset(vcpu);
2721 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2722 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2724 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2725 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2727 ka->boot_vcpu_runs_old_kvmclock = tmp;
2730 vcpu->arch.time = data;
2731 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2733 /* we verify if the enable bit is set... */
2737 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2738 &vcpu->arch.pv_time, data & ~1ULL,
2739 sizeof(struct pvclock_vcpu_time_info)))
2740 vcpu->arch.pv_time_enabled = false;
2742 vcpu->arch.pv_time_enabled = true;
2746 case MSR_KVM_ASYNC_PF_EN:
2747 if (kvm_pv_enable_async_pf(vcpu, data))
2750 case MSR_KVM_STEAL_TIME:
2752 if (unlikely(!sched_info_on()))
2755 if (data & KVM_STEAL_RESERVED_MASK)
2758 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2759 data & KVM_STEAL_VALID_BITS,
2760 sizeof(struct kvm_steal_time)))
2763 vcpu->arch.st.msr_val = data;
2765 if (!(data & KVM_MSR_ENABLED))
2768 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2771 case MSR_KVM_PV_EOI_EN:
2772 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2776 case MSR_KVM_POLL_CONTROL:
2777 /* only enable bit supported */
2778 if (data & (-1ULL << 1))
2781 vcpu->arch.msr_kvm_poll_control = data;
2784 case MSR_IA32_MCG_CTL:
2785 case MSR_IA32_MCG_STATUS:
2786 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2787 return set_msr_mce(vcpu, msr_info);
2789 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2790 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2791 pr = true; /* fall through */
2792 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2793 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2794 if (kvm_pmu_is_valid_msr(vcpu, msr))
2795 return kvm_pmu_set_msr(vcpu, msr_info);
2797 if (pr || data != 0)
2798 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2799 "0x%x data 0x%llx\n", msr, data);
2801 case MSR_K7_CLK_CTL:
2803 * Ignore all writes to this no longer documented MSR.
2804 * Writes are only relevant for old K7 processors,
2805 * all pre-dating SVM, but a recommended workaround from
2806 * AMD for these chips. It is possible to specify the
2807 * affected processor models on the command line, hence
2808 * the need to ignore the workaround.
2811 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2812 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2813 case HV_X64_MSR_CRASH_CTL:
2814 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2815 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2816 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2817 case HV_X64_MSR_TSC_EMULATION_STATUS:
2818 return kvm_hv_set_msr_common(vcpu, msr, data,
2819 msr_info->host_initiated);
2820 case MSR_IA32_BBL_CR_CTL3:
2821 /* Drop writes to this legacy MSR -- see rdmsr
2822 * counterpart for further detail.
2824 if (report_ignored_msrs)
2825 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2828 case MSR_AMD64_OSVW_ID_LENGTH:
2829 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2831 vcpu->arch.osvw.length = data;
2833 case MSR_AMD64_OSVW_STATUS:
2834 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2836 vcpu->arch.osvw.status = data;
2838 case MSR_PLATFORM_INFO:
2839 if (!msr_info->host_initiated ||
2840 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2841 cpuid_fault_enabled(vcpu)))
2843 vcpu->arch.msr_platform_info = data;
2845 case MSR_MISC_FEATURES_ENABLES:
2846 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2847 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2848 !supports_cpuid_fault(vcpu)))
2850 vcpu->arch.msr_misc_features_enables = data;
2853 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2854 return xen_hvm_config(vcpu, data);
2855 if (kvm_pmu_is_valid_msr(vcpu, msr))
2856 return kvm_pmu_set_msr(vcpu, msr_info);
2858 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2862 if (report_ignored_msrs)
2864 "ignored wrmsr: 0x%x data 0x%llx\n",
2871 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2873 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2876 u64 mcg_cap = vcpu->arch.mcg_cap;
2877 unsigned bank_num = mcg_cap & 0xff;
2880 case MSR_IA32_P5_MC_ADDR:
2881 case MSR_IA32_P5_MC_TYPE:
2884 case MSR_IA32_MCG_CAP:
2885 data = vcpu->arch.mcg_cap;
2887 case MSR_IA32_MCG_CTL:
2888 if (!(mcg_cap & MCG_CTL_P) && !host)
2890 data = vcpu->arch.mcg_ctl;
2892 case MSR_IA32_MCG_STATUS:
2893 data = vcpu->arch.mcg_status;
2896 if (msr >= MSR_IA32_MC0_CTL &&
2897 msr < MSR_IA32_MCx_CTL(bank_num)) {
2898 u32 offset = msr - MSR_IA32_MC0_CTL;
2899 data = vcpu->arch.mce_banks[offset];
2908 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2910 switch (msr_info->index) {
2911 case MSR_IA32_PLATFORM_ID:
2912 case MSR_IA32_EBL_CR_POWERON:
2913 case MSR_IA32_DEBUGCTLMSR:
2914 case MSR_IA32_LASTBRANCHFROMIP:
2915 case MSR_IA32_LASTBRANCHTOIP:
2916 case MSR_IA32_LASTINTFROMIP:
2917 case MSR_IA32_LASTINTTOIP:
2919 case MSR_K8_TSEG_ADDR:
2920 case MSR_K8_TSEG_MASK:
2921 case MSR_VM_HSAVE_PA:
2922 case MSR_K8_INT_PENDING_MSG:
2923 case MSR_AMD64_NB_CFG:
2924 case MSR_FAM10H_MMIO_CONF_BASE:
2925 case MSR_AMD64_BU_CFG2:
2926 case MSR_IA32_PERF_CTL:
2927 case MSR_AMD64_DC_CFG:
2928 case MSR_F15H_EX_CFG:
2931 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
2932 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2933 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2934 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2935 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2936 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2937 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2940 case MSR_IA32_UCODE_REV:
2941 msr_info->data = vcpu->arch.microcode_version;
2943 case MSR_IA32_ARCH_CAPABILITIES:
2944 if (!msr_info->host_initiated &&
2945 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2947 msr_info->data = vcpu->arch.arch_capabilities;
2949 case MSR_IA32_POWER_CTL:
2950 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
2953 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2956 case 0x200 ... 0x2ff:
2957 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2958 case 0xcd: /* fsb frequency */
2962 * MSR_EBC_FREQUENCY_ID
2963 * Conservative value valid for even the basic CPU models.
2964 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2965 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2966 * and 266MHz for model 3, or 4. Set Core Clock
2967 * Frequency to System Bus Frequency Ratio to 1 (bits
2968 * 31:24) even though these are only valid for CPU
2969 * models > 2, however guests may end up dividing or
2970 * multiplying by zero otherwise.
2972 case MSR_EBC_FREQUENCY_ID:
2973 msr_info->data = 1 << 24;
2975 case MSR_IA32_APICBASE:
2976 msr_info->data = kvm_get_apic_base(vcpu);
2978 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2979 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2981 case MSR_IA32_TSCDEADLINE:
2982 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2984 case MSR_IA32_TSC_ADJUST:
2985 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2987 case MSR_IA32_MISC_ENABLE:
2988 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2990 case MSR_IA32_SMBASE:
2991 if (!msr_info->host_initiated)
2993 msr_info->data = vcpu->arch.smbase;
2996 msr_info->data = vcpu->arch.smi_count;
2998 case MSR_IA32_PERF_STATUS:
2999 /* TSC increment by tick */
3000 msr_info->data = 1000ULL;
3001 /* CPU multiplier */
3002 msr_info->data |= (((uint64_t)4ULL) << 40);
3005 msr_info->data = vcpu->arch.efer;
3007 case MSR_KVM_WALL_CLOCK:
3008 case MSR_KVM_WALL_CLOCK_NEW:
3009 msr_info->data = vcpu->kvm->arch.wall_clock;
3011 case MSR_KVM_SYSTEM_TIME:
3012 case MSR_KVM_SYSTEM_TIME_NEW:
3013 msr_info->data = vcpu->arch.time;
3015 case MSR_KVM_ASYNC_PF_EN:
3016 msr_info->data = vcpu->arch.apf.msr_val;
3018 case MSR_KVM_STEAL_TIME:
3019 msr_info->data = vcpu->arch.st.msr_val;
3021 case MSR_KVM_PV_EOI_EN:
3022 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3024 case MSR_KVM_POLL_CONTROL:
3025 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3027 case MSR_IA32_P5_MC_ADDR:
3028 case MSR_IA32_P5_MC_TYPE:
3029 case MSR_IA32_MCG_CAP:
3030 case MSR_IA32_MCG_CTL:
3031 case MSR_IA32_MCG_STATUS:
3032 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3033 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3034 msr_info->host_initiated);
3035 case MSR_K7_CLK_CTL:
3037 * Provide expected ramp-up count for K7. All other
3038 * are set to zero, indicating minimum divisors for
3041 * This prevents guest kernels on AMD host with CPU
3042 * type 6, model 8 and higher from exploding due to
3043 * the rdmsr failing.
3045 msr_info->data = 0x20000000;
3047 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3048 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3049 case HV_X64_MSR_CRASH_CTL:
3050 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3051 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3052 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3053 case HV_X64_MSR_TSC_EMULATION_STATUS:
3054 return kvm_hv_get_msr_common(vcpu,
3055 msr_info->index, &msr_info->data,
3056 msr_info->host_initiated);
3058 case MSR_IA32_BBL_CR_CTL3:
3059 /* This legacy MSR exists but isn't fully documented in current
3060 * silicon. It is however accessed by winxp in very narrow
3061 * scenarios where it sets bit #19, itself documented as
3062 * a "reserved" bit. Best effort attempt to source coherent
3063 * read data here should the balance of the register be
3064 * interpreted by the guest:
3066 * L2 cache control register 3: 64GB range, 256KB size,
3067 * enabled, latency 0x1, configured
3069 msr_info->data = 0xbe702111;
3071 case MSR_AMD64_OSVW_ID_LENGTH:
3072 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3074 msr_info->data = vcpu->arch.osvw.length;
3076 case MSR_AMD64_OSVW_STATUS:
3077 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3079 msr_info->data = vcpu->arch.osvw.status;
3081 case MSR_PLATFORM_INFO:
3082 if (!msr_info->host_initiated &&
3083 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3085 msr_info->data = vcpu->arch.msr_platform_info;
3087 case MSR_MISC_FEATURES_ENABLES:
3088 msr_info->data = vcpu->arch.msr_misc_features_enables;
3091 msr_info->data = vcpu->arch.msr_hwcr;
3094 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3095 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3097 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3101 if (report_ignored_msrs)
3102 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3110 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3113 * Read or write a bunch of msrs. All parameters are kernel addresses.
3115 * @return number of msrs set successfully.
3117 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3118 struct kvm_msr_entry *entries,
3119 int (*do_msr)(struct kvm_vcpu *vcpu,
3120 unsigned index, u64 *data))
3124 for (i = 0; i < msrs->nmsrs; ++i)
3125 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3132 * Read or write a bunch of msrs. Parameters are user addresses.
3134 * @return number of msrs set successfully.
3136 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3137 int (*do_msr)(struct kvm_vcpu *vcpu,
3138 unsigned index, u64 *data),
3141 struct kvm_msrs msrs;
3142 struct kvm_msr_entry *entries;
3147 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3151 if (msrs.nmsrs >= MAX_IO_MSRS)
3154 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3155 entries = memdup_user(user_msrs->entries, size);
3156 if (IS_ERR(entries)) {
3157 r = PTR_ERR(entries);
3161 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3166 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3177 static inline bool kvm_can_mwait_in_guest(void)
3179 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3180 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3181 boot_cpu_has(X86_FEATURE_ARAT);
3184 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3189 case KVM_CAP_IRQCHIP:
3191 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3192 case KVM_CAP_SET_TSS_ADDR:
3193 case KVM_CAP_EXT_CPUID:
3194 case KVM_CAP_EXT_EMUL_CPUID:
3195 case KVM_CAP_CLOCKSOURCE:
3197 case KVM_CAP_NOP_IO_DELAY:
3198 case KVM_CAP_MP_STATE:
3199 case KVM_CAP_SYNC_MMU:
3200 case KVM_CAP_USER_NMI:
3201 case KVM_CAP_REINJECT_CONTROL:
3202 case KVM_CAP_IRQ_INJECT_STATUS:
3203 case KVM_CAP_IOEVENTFD:
3204 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3206 case KVM_CAP_PIT_STATE2:
3207 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3208 case KVM_CAP_XEN_HVM:
3209 case KVM_CAP_VCPU_EVENTS:
3210 case KVM_CAP_HYPERV:
3211 case KVM_CAP_HYPERV_VAPIC:
3212 case KVM_CAP_HYPERV_SPIN:
3213 case KVM_CAP_HYPERV_SYNIC:
3214 case KVM_CAP_HYPERV_SYNIC2:
3215 case KVM_CAP_HYPERV_VP_INDEX:
3216 case KVM_CAP_HYPERV_EVENTFD:
3217 case KVM_CAP_HYPERV_TLBFLUSH:
3218 case KVM_CAP_HYPERV_SEND_IPI:
3219 case KVM_CAP_HYPERV_CPUID:
3220 case KVM_CAP_PCI_SEGMENT:
3221 case KVM_CAP_DEBUGREGS:
3222 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3224 case KVM_CAP_ASYNC_PF:
3225 case KVM_CAP_GET_TSC_KHZ:
3226 case KVM_CAP_KVMCLOCK_CTRL:
3227 case KVM_CAP_READONLY_MEM:
3228 case KVM_CAP_HYPERV_TIME:
3229 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3230 case KVM_CAP_TSC_DEADLINE_TIMER:
3231 case KVM_CAP_DISABLE_QUIRKS:
3232 case KVM_CAP_SET_BOOT_CPU_ID:
3233 case KVM_CAP_SPLIT_IRQCHIP:
3234 case KVM_CAP_IMMEDIATE_EXIT:
3235 case KVM_CAP_PMU_EVENT_FILTER:
3236 case KVM_CAP_GET_MSR_FEATURES:
3237 case KVM_CAP_MSR_PLATFORM_INFO:
3238 case KVM_CAP_EXCEPTION_PAYLOAD:
3241 case KVM_CAP_SYNC_REGS:
3242 r = KVM_SYNC_X86_VALID_FIELDS;
3244 case KVM_CAP_ADJUST_CLOCK:
3245 r = KVM_CLOCK_TSC_STABLE;
3247 case KVM_CAP_X86_DISABLE_EXITS:
3248 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3249 KVM_X86_DISABLE_EXITS_CSTATE;
3250 if(kvm_can_mwait_in_guest())
3251 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3253 case KVM_CAP_X86_SMM:
3254 /* SMBASE is usually relocated above 1M on modern chipsets,
3255 * and SMM handlers might indeed rely on 4G segment limits,
3256 * so do not report SMM to be available if real mode is
3257 * emulated via vm86 mode. Still, do not go to great lengths
3258 * to avoid userspace's usage of the feature, because it is a
3259 * fringe case that is not enabled except via specific settings
3260 * of the module parameters.
3262 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3265 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3267 case KVM_CAP_NR_VCPUS:
3268 r = KVM_SOFT_MAX_VCPUS;
3270 case KVM_CAP_MAX_VCPUS:
3273 case KVM_CAP_MAX_VCPU_ID:
3274 r = KVM_MAX_VCPU_ID;
3276 case KVM_CAP_PV_MMU: /* obsolete */
3280 r = KVM_MAX_MCE_BANKS;
3283 r = boot_cpu_has(X86_FEATURE_XSAVE);
3285 case KVM_CAP_TSC_CONTROL:
3286 r = kvm_has_tsc_control;
3288 case KVM_CAP_X2APIC_API:
3289 r = KVM_X2APIC_API_VALID_FLAGS;
3291 case KVM_CAP_NESTED_STATE:
3292 r = kvm_x86_ops->get_nested_state ?
3293 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
3295 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3296 r = kvm_x86_ops->enable_direct_tlbflush != NULL;
3298 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3299 r = kvm_x86_ops->nested_enable_evmcs != NULL;
3308 long kvm_arch_dev_ioctl(struct file *filp,
3309 unsigned int ioctl, unsigned long arg)
3311 void __user *argp = (void __user *)arg;
3315 case KVM_GET_MSR_INDEX_LIST: {
3316 struct kvm_msr_list __user *user_msr_list = argp;
3317 struct kvm_msr_list msr_list;
3321 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3324 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3325 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3328 if (n < msr_list.nmsrs)
3331 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3332 num_msrs_to_save * sizeof(u32)))
3334 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3336 num_emulated_msrs * sizeof(u32)))
3341 case KVM_GET_SUPPORTED_CPUID:
3342 case KVM_GET_EMULATED_CPUID: {
3343 struct kvm_cpuid2 __user *cpuid_arg = argp;
3344 struct kvm_cpuid2 cpuid;
3347 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3350 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3356 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3361 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3363 if (copy_to_user(argp, &kvm_mce_cap_supported,
3364 sizeof(kvm_mce_cap_supported)))
3368 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3369 struct kvm_msr_list __user *user_msr_list = argp;
3370 struct kvm_msr_list msr_list;
3374 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3377 msr_list.nmsrs = num_msr_based_features;
3378 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3381 if (n < msr_list.nmsrs)
3384 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3385 num_msr_based_features * sizeof(u32)))
3391 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3401 static void wbinvd_ipi(void *garbage)
3406 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3408 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3411 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3413 /* Address WBINVD may be executed by guest */
3414 if (need_emulate_wbinvd(vcpu)) {
3415 if (kvm_x86_ops->has_wbinvd_exit())
3416 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3417 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3418 smp_call_function_single(vcpu->cpu,
3419 wbinvd_ipi, NULL, 1);
3422 kvm_x86_ops->vcpu_load(vcpu, cpu);
3424 fpregs_assert_state_consistent();
3425 if (test_thread_flag(TIF_NEED_FPU_LOAD))
3426 switch_fpu_return();
3428 /* Apply any externally detected TSC adjustments (due to suspend) */
3429 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3430 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3431 vcpu->arch.tsc_offset_adjustment = 0;
3432 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3435 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3436 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3437 rdtsc() - vcpu->arch.last_host_tsc;
3439 mark_tsc_unstable("KVM discovered backwards TSC");
3441 if (kvm_check_tsc_unstable()) {
3442 u64 offset = kvm_compute_tsc_offset(vcpu,
3443 vcpu->arch.last_guest_tsc);
3444 kvm_vcpu_write_tsc_offset(vcpu, offset);
3445 vcpu->arch.tsc_catchup = 1;
3448 if (kvm_lapic_hv_timer_in_use(vcpu))
3449 kvm_lapic_restart_hv_timer(vcpu);
3452 * On a host with synchronized TSC, there is no need to update
3453 * kvmclock on vcpu->cpu migration
3455 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3456 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3457 if (vcpu->cpu != cpu)
3458 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3462 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3465 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3467 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3470 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
3472 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3473 &vcpu->arch.st.steal.preempted,
3474 offsetof(struct kvm_steal_time, preempted),
3475 sizeof(vcpu->arch.st.steal.preempted));
3478 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3482 if (vcpu->preempted)
3483 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3486 * Disable page faults because we're in atomic context here.
3487 * kvm_write_guest_offset_cached() would call might_fault()
3488 * that relies on pagefault_disable() to tell if there's a
3489 * bug. NOTE: the write to guest memory may not go through if
3490 * during postcopy live migration or if there's heavy guest
3493 pagefault_disable();
3495 * kvm_memslots() will be called by
3496 * kvm_write_guest_offset_cached() so take the srcu lock.
3498 idx = srcu_read_lock(&vcpu->kvm->srcu);
3499 kvm_steal_time_set_preempted(vcpu);
3500 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3502 kvm_x86_ops->vcpu_put(vcpu);
3503 vcpu->arch.last_host_tsc = rdtsc();
3505 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3506 * on every vmexit, but if not, we might have a stale dr6 from the
3507 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3512 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3513 struct kvm_lapic_state *s)
3515 if (vcpu->arch.apicv_active)
3516 kvm_x86_ops->sync_pir_to_irr(vcpu);
3518 return kvm_apic_get_state(vcpu, s);
3521 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3522 struct kvm_lapic_state *s)
3526 r = kvm_apic_set_state(vcpu, s);
3529 update_cr8_intercept(vcpu);
3534 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3536 return (!lapic_in_kernel(vcpu) ||
3537 kvm_apic_accept_pic_intr(vcpu));
3541 * if userspace requested an interrupt window, check that the
3542 * interrupt window is open.
3544 * No need to exit to userspace if we already have an interrupt queued.
3546 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3548 return kvm_arch_interrupt_allowed(vcpu) &&
3549 !kvm_cpu_has_interrupt(vcpu) &&
3550 !kvm_event_needs_reinjection(vcpu) &&
3551 kvm_cpu_accept_dm_intr(vcpu);
3554 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3555 struct kvm_interrupt *irq)
3557 if (irq->irq >= KVM_NR_INTERRUPTS)
3560 if (!irqchip_in_kernel(vcpu->kvm)) {
3561 kvm_queue_interrupt(vcpu, irq->irq, false);
3562 kvm_make_request(KVM_REQ_EVENT, vcpu);
3567 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3568 * fail for in-kernel 8259.
3570 if (pic_in_kernel(vcpu->kvm))
3573 if (vcpu->arch.pending_external_vector != -1)
3576 vcpu->arch.pending_external_vector = irq->irq;
3577 kvm_make_request(KVM_REQ_EVENT, vcpu);
3581 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3583 kvm_inject_nmi(vcpu);
3588 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3590 kvm_make_request(KVM_REQ_SMI, vcpu);
3595 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3596 struct kvm_tpr_access_ctl *tac)
3600 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3604 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3608 unsigned bank_num = mcg_cap & 0xff, bank;
3611 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3613 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3616 vcpu->arch.mcg_cap = mcg_cap;
3617 /* Init IA32_MCG_CTL to all 1s */
3618 if (mcg_cap & MCG_CTL_P)
3619 vcpu->arch.mcg_ctl = ~(u64)0;
3620 /* Init IA32_MCi_CTL to all 1s */
3621 for (bank = 0; bank < bank_num; bank++)
3622 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3624 kvm_x86_ops->setup_mce(vcpu);
3629 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3630 struct kvm_x86_mce *mce)
3632 u64 mcg_cap = vcpu->arch.mcg_cap;
3633 unsigned bank_num = mcg_cap & 0xff;
3634 u64 *banks = vcpu->arch.mce_banks;
3636 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3639 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3640 * reporting is disabled
3642 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3643 vcpu->arch.mcg_ctl != ~(u64)0)
3645 banks += 4 * mce->bank;
3647 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3648 * reporting is disabled for the bank
3650 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3652 if (mce->status & MCI_STATUS_UC) {
3653 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3654 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3655 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3658 if (banks[1] & MCI_STATUS_VAL)
3659 mce->status |= MCI_STATUS_OVER;
3660 banks[2] = mce->addr;
3661 banks[3] = mce->misc;
3662 vcpu->arch.mcg_status = mce->mcg_status;
3663 banks[1] = mce->status;
3664 kvm_queue_exception(vcpu, MC_VECTOR);
3665 } else if (!(banks[1] & MCI_STATUS_VAL)
3666 || !(banks[1] & MCI_STATUS_UC)) {
3667 if (banks[1] & MCI_STATUS_VAL)
3668 mce->status |= MCI_STATUS_OVER;
3669 banks[2] = mce->addr;
3670 banks[3] = mce->misc;
3671 banks[1] = mce->status;
3673 banks[1] |= MCI_STATUS_OVER;
3677 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3678 struct kvm_vcpu_events *events)
3683 * The API doesn't provide the instruction length for software
3684 * exceptions, so don't report them. As long as the guest RIP
3685 * isn't advanced, we should expect to encounter the exception
3688 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3689 events->exception.injected = 0;
3690 events->exception.pending = 0;
3692 events->exception.injected = vcpu->arch.exception.injected;
3693 events->exception.pending = vcpu->arch.exception.pending;
3695 * For ABI compatibility, deliberately conflate
3696 * pending and injected exceptions when
3697 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3699 if (!vcpu->kvm->arch.exception_payload_enabled)
3700 events->exception.injected |=
3701 vcpu->arch.exception.pending;
3703 events->exception.nr = vcpu->arch.exception.nr;
3704 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3705 events->exception.error_code = vcpu->arch.exception.error_code;
3706 events->exception_has_payload = vcpu->arch.exception.has_payload;
3707 events->exception_payload = vcpu->arch.exception.payload;
3709 events->interrupt.injected =
3710 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3711 events->interrupt.nr = vcpu->arch.interrupt.nr;
3712 events->interrupt.soft = 0;
3713 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3715 events->nmi.injected = vcpu->arch.nmi_injected;
3716 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3717 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3718 events->nmi.pad = 0;
3720 events->sipi_vector = 0; /* never valid when reporting to user space */
3722 events->smi.smm = is_smm(vcpu);
3723 events->smi.pending = vcpu->arch.smi_pending;
3724 events->smi.smm_inside_nmi =
3725 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3726 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3728 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3729 | KVM_VCPUEVENT_VALID_SHADOW
3730 | KVM_VCPUEVENT_VALID_SMM);
3731 if (vcpu->kvm->arch.exception_payload_enabled)
3732 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3734 memset(&events->reserved, 0, sizeof(events->reserved));
3737 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3739 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3740 struct kvm_vcpu_events *events)
3742 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3743 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3744 | KVM_VCPUEVENT_VALID_SHADOW
3745 | KVM_VCPUEVENT_VALID_SMM
3746 | KVM_VCPUEVENT_VALID_PAYLOAD))
3749 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3750 if (!vcpu->kvm->arch.exception_payload_enabled)
3752 if (events->exception.pending)
3753 events->exception.injected = 0;
3755 events->exception_has_payload = 0;
3757 events->exception.pending = 0;
3758 events->exception_has_payload = 0;
3761 if ((events->exception.injected || events->exception.pending) &&
3762 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3765 /* INITs are latched while in SMM */
3766 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3767 (events->smi.smm || events->smi.pending) &&
3768 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3772 vcpu->arch.exception.injected = events->exception.injected;
3773 vcpu->arch.exception.pending = events->exception.pending;
3774 vcpu->arch.exception.nr = events->exception.nr;
3775 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3776 vcpu->arch.exception.error_code = events->exception.error_code;
3777 vcpu->arch.exception.has_payload = events->exception_has_payload;
3778 vcpu->arch.exception.payload = events->exception_payload;
3780 vcpu->arch.interrupt.injected = events->interrupt.injected;
3781 vcpu->arch.interrupt.nr = events->interrupt.nr;
3782 vcpu->arch.interrupt.soft = events->interrupt.soft;
3783 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3784 kvm_x86_ops->set_interrupt_shadow(vcpu,
3785 events->interrupt.shadow);
3787 vcpu->arch.nmi_injected = events->nmi.injected;
3788 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3789 vcpu->arch.nmi_pending = events->nmi.pending;
3790 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3792 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3793 lapic_in_kernel(vcpu))
3794 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3796 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3797 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3798 if (events->smi.smm)
3799 vcpu->arch.hflags |= HF_SMM_MASK;
3801 vcpu->arch.hflags &= ~HF_SMM_MASK;
3802 kvm_smm_changed(vcpu);
3805 vcpu->arch.smi_pending = events->smi.pending;
3807 if (events->smi.smm) {
3808 if (events->smi.smm_inside_nmi)
3809 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3811 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3812 if (lapic_in_kernel(vcpu)) {
3813 if (events->smi.latched_init)
3814 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3816 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3821 kvm_make_request(KVM_REQ_EVENT, vcpu);
3826 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3827 struct kvm_debugregs *dbgregs)
3831 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3832 kvm_get_dr(vcpu, 6, &val);
3834 dbgregs->dr7 = vcpu->arch.dr7;
3836 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3839 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3840 struct kvm_debugregs *dbgregs)
3845 if (dbgregs->dr6 & ~0xffffffffull)
3847 if (dbgregs->dr7 & ~0xffffffffull)
3850 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3851 kvm_update_dr0123(vcpu);
3852 vcpu->arch.dr6 = dbgregs->dr6;
3853 kvm_update_dr6(vcpu);
3854 vcpu->arch.dr7 = dbgregs->dr7;
3855 kvm_update_dr7(vcpu);
3860 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3862 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3864 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3865 u64 xstate_bv = xsave->header.xfeatures;
3869 * Copy legacy XSAVE area, to avoid complications with CPUID
3870 * leaves 0 and 1 in the loop below.
3872 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3875 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3876 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3879 * Copy each region from the possibly compacted offset to the
3880 * non-compacted offset.
3882 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3884 u64 xfeature_mask = valid & -valid;
3885 int xfeature_nr = fls64(xfeature_mask) - 1;
3886 void *src = get_xsave_addr(xsave, xfeature_nr);
3889 u32 size, offset, ecx, edx;
3890 cpuid_count(XSTATE_CPUID, xfeature_nr,
3891 &size, &offset, &ecx, &edx);
3892 if (xfeature_nr == XFEATURE_PKRU)
3893 memcpy(dest + offset, &vcpu->arch.pkru,
3894 sizeof(vcpu->arch.pkru));
3896 memcpy(dest + offset, src, size);
3900 valid -= xfeature_mask;
3904 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3906 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3907 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3911 * Copy legacy XSAVE area, to avoid complications with CPUID
3912 * leaves 0 and 1 in the loop below.
3914 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3916 /* Set XSTATE_BV and possibly XCOMP_BV. */
3917 xsave->header.xfeatures = xstate_bv;
3918 if (boot_cpu_has(X86_FEATURE_XSAVES))
3919 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3922 * Copy each region from the non-compacted offset to the
3923 * possibly compacted offset.
3925 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3927 u64 xfeature_mask = valid & -valid;
3928 int xfeature_nr = fls64(xfeature_mask) - 1;
3929 void *dest = get_xsave_addr(xsave, xfeature_nr);
3932 u32 size, offset, ecx, edx;
3933 cpuid_count(XSTATE_CPUID, xfeature_nr,
3934 &size, &offset, &ecx, &edx);
3935 if (xfeature_nr == XFEATURE_PKRU)
3936 memcpy(&vcpu->arch.pkru, src + offset,
3937 sizeof(vcpu->arch.pkru));
3939 memcpy(dest, src + offset, size);
3942 valid -= xfeature_mask;
3946 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3947 struct kvm_xsave *guest_xsave)
3949 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3950 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3951 fill_xsave((u8 *) guest_xsave->region, vcpu);
3953 memcpy(guest_xsave->region,
3954 &vcpu->arch.guest_fpu->state.fxsave,
3955 sizeof(struct fxregs_state));
3956 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3957 XFEATURE_MASK_FPSSE;
3961 #define XSAVE_MXCSR_OFFSET 24
3963 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3964 struct kvm_xsave *guest_xsave)
3967 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3968 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3970 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3972 * Here we allow setting states that are not present in
3973 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3974 * with old userspace.
3976 if (xstate_bv & ~kvm_supported_xcr0() ||
3977 mxcsr & ~mxcsr_feature_mask)
3979 load_xsave(vcpu, (u8 *)guest_xsave->region);
3981 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3982 mxcsr & ~mxcsr_feature_mask)
3984 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
3985 guest_xsave->region, sizeof(struct fxregs_state));
3990 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3991 struct kvm_xcrs *guest_xcrs)
3993 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3994 guest_xcrs->nr_xcrs = 0;
3998 guest_xcrs->nr_xcrs = 1;
3999 guest_xcrs->flags = 0;
4000 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4001 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4004 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4005 struct kvm_xcrs *guest_xcrs)
4009 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4012 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4015 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4016 /* Only support XCR0 currently */
4017 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4018 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4019 guest_xcrs->xcrs[i].value);
4028 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4029 * stopped by the hypervisor. This function will be called from the host only.
4030 * EINVAL is returned when the host attempts to set the flag for a guest that
4031 * does not support pv clocks.
4033 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4035 if (!vcpu->arch.pv_time_enabled)
4037 vcpu->arch.pvclock_set_guest_stopped_request = true;
4038 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4042 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4043 struct kvm_enable_cap *cap)
4046 uint16_t vmcs_version;
4047 void __user *user_ptr;
4053 case KVM_CAP_HYPERV_SYNIC2:
4058 case KVM_CAP_HYPERV_SYNIC:
4059 if (!irqchip_in_kernel(vcpu->kvm))
4061 return kvm_hv_activate_synic(vcpu, cap->cap ==
4062 KVM_CAP_HYPERV_SYNIC2);
4063 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4064 if (!kvm_x86_ops->nested_enable_evmcs)
4066 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
4068 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4069 if (copy_to_user(user_ptr, &vmcs_version,
4070 sizeof(vmcs_version)))
4074 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4075 if (!kvm_x86_ops->enable_direct_tlbflush)
4078 return kvm_x86_ops->enable_direct_tlbflush(vcpu);
4085 long kvm_arch_vcpu_ioctl(struct file *filp,
4086 unsigned int ioctl, unsigned long arg)
4088 struct kvm_vcpu *vcpu = filp->private_data;
4089 void __user *argp = (void __user *)arg;
4092 struct kvm_lapic_state *lapic;
4093 struct kvm_xsave *xsave;
4094 struct kvm_xcrs *xcrs;
4102 case KVM_GET_LAPIC: {
4104 if (!lapic_in_kernel(vcpu))
4106 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4107 GFP_KERNEL_ACCOUNT);
4112 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4116 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4121 case KVM_SET_LAPIC: {
4123 if (!lapic_in_kernel(vcpu))
4125 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4126 if (IS_ERR(u.lapic)) {
4127 r = PTR_ERR(u.lapic);
4131 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4134 case KVM_INTERRUPT: {
4135 struct kvm_interrupt irq;
4138 if (copy_from_user(&irq, argp, sizeof(irq)))
4140 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4144 r = kvm_vcpu_ioctl_nmi(vcpu);
4148 r = kvm_vcpu_ioctl_smi(vcpu);
4151 case KVM_SET_CPUID: {
4152 struct kvm_cpuid __user *cpuid_arg = argp;
4153 struct kvm_cpuid cpuid;
4156 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4158 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4161 case KVM_SET_CPUID2: {
4162 struct kvm_cpuid2 __user *cpuid_arg = argp;
4163 struct kvm_cpuid2 cpuid;
4166 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4168 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4169 cpuid_arg->entries);
4172 case KVM_GET_CPUID2: {
4173 struct kvm_cpuid2 __user *cpuid_arg = argp;
4174 struct kvm_cpuid2 cpuid;
4177 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4179 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4180 cpuid_arg->entries);
4184 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4189 case KVM_GET_MSRS: {
4190 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4191 r = msr_io(vcpu, argp, do_get_msr, 1);
4192 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4195 case KVM_SET_MSRS: {
4196 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4197 r = msr_io(vcpu, argp, do_set_msr, 0);
4198 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4201 case KVM_TPR_ACCESS_REPORTING: {
4202 struct kvm_tpr_access_ctl tac;
4205 if (copy_from_user(&tac, argp, sizeof(tac)))
4207 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4211 if (copy_to_user(argp, &tac, sizeof(tac)))
4216 case KVM_SET_VAPIC_ADDR: {
4217 struct kvm_vapic_addr va;
4221 if (!lapic_in_kernel(vcpu))
4224 if (copy_from_user(&va, argp, sizeof(va)))
4226 idx = srcu_read_lock(&vcpu->kvm->srcu);
4227 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4228 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4231 case KVM_X86_SETUP_MCE: {
4235 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4237 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4240 case KVM_X86_SET_MCE: {
4241 struct kvm_x86_mce mce;
4244 if (copy_from_user(&mce, argp, sizeof(mce)))
4246 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4249 case KVM_GET_VCPU_EVENTS: {
4250 struct kvm_vcpu_events events;
4252 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4255 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4260 case KVM_SET_VCPU_EVENTS: {
4261 struct kvm_vcpu_events events;
4264 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4267 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4270 case KVM_GET_DEBUGREGS: {
4271 struct kvm_debugregs dbgregs;
4273 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4276 if (copy_to_user(argp, &dbgregs,
4277 sizeof(struct kvm_debugregs)))
4282 case KVM_SET_DEBUGREGS: {
4283 struct kvm_debugregs dbgregs;
4286 if (copy_from_user(&dbgregs, argp,
4287 sizeof(struct kvm_debugregs)))
4290 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4293 case KVM_GET_XSAVE: {
4294 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4299 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4302 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4307 case KVM_SET_XSAVE: {
4308 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4309 if (IS_ERR(u.xsave)) {
4310 r = PTR_ERR(u.xsave);
4314 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4317 case KVM_GET_XCRS: {
4318 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4323 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4326 if (copy_to_user(argp, u.xcrs,
4327 sizeof(struct kvm_xcrs)))
4332 case KVM_SET_XCRS: {
4333 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4334 if (IS_ERR(u.xcrs)) {
4335 r = PTR_ERR(u.xcrs);
4339 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4342 case KVM_SET_TSC_KHZ: {
4346 user_tsc_khz = (u32)arg;
4348 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4351 if (user_tsc_khz == 0)
4352 user_tsc_khz = tsc_khz;
4354 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4359 case KVM_GET_TSC_KHZ: {
4360 r = vcpu->arch.virtual_tsc_khz;
4363 case KVM_KVMCLOCK_CTRL: {
4364 r = kvm_set_guest_paused(vcpu);
4367 case KVM_ENABLE_CAP: {
4368 struct kvm_enable_cap cap;
4371 if (copy_from_user(&cap, argp, sizeof(cap)))
4373 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4376 case KVM_GET_NESTED_STATE: {
4377 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4381 if (!kvm_x86_ops->get_nested_state)
4384 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4386 if (get_user(user_data_size, &user_kvm_nested_state->size))
4389 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4394 if (r > user_data_size) {
4395 if (put_user(r, &user_kvm_nested_state->size))
4405 case KVM_SET_NESTED_STATE: {
4406 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4407 struct kvm_nested_state kvm_state;
4410 if (!kvm_x86_ops->set_nested_state)
4414 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4418 if (kvm_state.size < sizeof(kvm_state))
4421 if (kvm_state.flags &
4422 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4423 | KVM_STATE_NESTED_EVMCS))
4426 /* nested_run_pending implies guest_mode. */
4427 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4428 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4431 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4434 case KVM_GET_SUPPORTED_HV_CPUID: {
4435 struct kvm_cpuid2 __user *cpuid_arg = argp;
4436 struct kvm_cpuid2 cpuid;
4439 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4442 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4443 cpuid_arg->entries);
4448 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4463 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4465 return VM_FAULT_SIGBUS;
4468 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4472 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4474 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4478 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4481 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4484 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4485 unsigned long kvm_nr_mmu_pages)
4487 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4490 mutex_lock(&kvm->slots_lock);
4492 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4493 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4495 mutex_unlock(&kvm->slots_lock);
4499 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4501 return kvm->arch.n_max_mmu_pages;
4504 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4506 struct kvm_pic *pic = kvm->arch.vpic;
4510 switch (chip->chip_id) {
4511 case KVM_IRQCHIP_PIC_MASTER:
4512 memcpy(&chip->chip.pic, &pic->pics[0],
4513 sizeof(struct kvm_pic_state));
4515 case KVM_IRQCHIP_PIC_SLAVE:
4516 memcpy(&chip->chip.pic, &pic->pics[1],
4517 sizeof(struct kvm_pic_state));
4519 case KVM_IRQCHIP_IOAPIC:
4520 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4529 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4531 struct kvm_pic *pic = kvm->arch.vpic;
4535 switch (chip->chip_id) {
4536 case KVM_IRQCHIP_PIC_MASTER:
4537 spin_lock(&pic->lock);
4538 memcpy(&pic->pics[0], &chip->chip.pic,
4539 sizeof(struct kvm_pic_state));
4540 spin_unlock(&pic->lock);
4542 case KVM_IRQCHIP_PIC_SLAVE:
4543 spin_lock(&pic->lock);
4544 memcpy(&pic->pics[1], &chip->chip.pic,
4545 sizeof(struct kvm_pic_state));
4546 spin_unlock(&pic->lock);
4548 case KVM_IRQCHIP_IOAPIC:
4549 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4555 kvm_pic_update_irq(pic);
4559 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4561 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4563 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4565 mutex_lock(&kps->lock);
4566 memcpy(ps, &kps->channels, sizeof(*ps));
4567 mutex_unlock(&kps->lock);
4571 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4574 struct kvm_pit *pit = kvm->arch.vpit;
4576 mutex_lock(&pit->pit_state.lock);
4577 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4578 for (i = 0; i < 3; i++)
4579 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4580 mutex_unlock(&pit->pit_state.lock);
4584 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4586 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4587 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4588 sizeof(ps->channels));
4589 ps->flags = kvm->arch.vpit->pit_state.flags;
4590 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4591 memset(&ps->reserved, 0, sizeof(ps->reserved));
4595 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4599 u32 prev_legacy, cur_legacy;
4600 struct kvm_pit *pit = kvm->arch.vpit;
4602 mutex_lock(&pit->pit_state.lock);
4603 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4604 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4605 if (!prev_legacy && cur_legacy)
4607 memcpy(&pit->pit_state.channels, &ps->channels,
4608 sizeof(pit->pit_state.channels));
4609 pit->pit_state.flags = ps->flags;
4610 for (i = 0; i < 3; i++)
4611 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4613 mutex_unlock(&pit->pit_state.lock);
4617 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4618 struct kvm_reinject_control *control)
4620 struct kvm_pit *pit = kvm->arch.vpit;
4625 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4626 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4627 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4629 mutex_lock(&pit->pit_state.lock);
4630 kvm_pit_set_reinject(pit, control->pit_reinject);
4631 mutex_unlock(&pit->pit_state.lock);
4637 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4638 * @kvm: kvm instance
4639 * @log: slot id and address to which we copy the log
4641 * Steps 1-4 below provide general overview of dirty page logging. See
4642 * kvm_get_dirty_log_protect() function description for additional details.
4644 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4645 * always flush the TLB (step 4) even if previous step failed and the dirty
4646 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4647 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4648 * writes will be marked dirty for next log read.
4650 * 1. Take a snapshot of the bit and clear it if needed.
4651 * 2. Write protect the corresponding page.
4652 * 3. Copy the snapshot to the userspace.
4653 * 4. Flush TLB's if needed.
4655 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4660 mutex_lock(&kvm->slots_lock);
4663 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4665 if (kvm_x86_ops->flush_log_dirty)
4666 kvm_x86_ops->flush_log_dirty(kvm);
4668 r = kvm_get_dirty_log_protect(kvm, log, &flush);
4671 * All the TLBs can be flushed out of mmu lock, see the comments in
4672 * kvm_mmu_slot_remove_write_access().
4674 lockdep_assert_held(&kvm->slots_lock);
4676 kvm_flush_remote_tlbs(kvm);
4678 mutex_unlock(&kvm->slots_lock);
4682 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4687 mutex_lock(&kvm->slots_lock);
4690 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4692 if (kvm_x86_ops->flush_log_dirty)
4693 kvm_x86_ops->flush_log_dirty(kvm);
4695 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4698 * All the TLBs can be flushed out of mmu lock, see the comments in
4699 * kvm_mmu_slot_remove_write_access().
4701 lockdep_assert_held(&kvm->slots_lock);
4703 kvm_flush_remote_tlbs(kvm);
4705 mutex_unlock(&kvm->slots_lock);
4709 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4712 if (!irqchip_in_kernel(kvm))
4715 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4716 irq_event->irq, irq_event->level,
4721 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4722 struct kvm_enable_cap *cap)
4730 case KVM_CAP_DISABLE_QUIRKS:
4731 kvm->arch.disabled_quirks = cap->args[0];
4734 case KVM_CAP_SPLIT_IRQCHIP: {
4735 mutex_lock(&kvm->lock);
4737 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4738 goto split_irqchip_unlock;
4740 if (irqchip_in_kernel(kvm))
4741 goto split_irqchip_unlock;
4742 if (kvm->created_vcpus)
4743 goto split_irqchip_unlock;
4744 r = kvm_setup_empty_irq_routing(kvm);
4746 goto split_irqchip_unlock;
4747 /* Pairs with irqchip_in_kernel. */
4749 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4750 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4752 split_irqchip_unlock:
4753 mutex_unlock(&kvm->lock);
4756 case KVM_CAP_X2APIC_API:
4758 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4761 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4762 kvm->arch.x2apic_format = true;
4763 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4764 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4768 case KVM_CAP_X86_DISABLE_EXITS:
4770 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4773 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4774 kvm_can_mwait_in_guest())
4775 kvm->arch.mwait_in_guest = true;
4776 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4777 kvm->arch.hlt_in_guest = true;
4778 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4779 kvm->arch.pause_in_guest = true;
4780 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4781 kvm->arch.cstate_in_guest = true;
4784 case KVM_CAP_MSR_PLATFORM_INFO:
4785 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4788 case KVM_CAP_EXCEPTION_PAYLOAD:
4789 kvm->arch.exception_payload_enabled = cap->args[0];
4799 long kvm_arch_vm_ioctl(struct file *filp,
4800 unsigned int ioctl, unsigned long arg)
4802 struct kvm *kvm = filp->private_data;
4803 void __user *argp = (void __user *)arg;
4806 * This union makes it completely explicit to gcc-3.x
4807 * that these two variables' stack usage should be
4808 * combined, not added together.
4811 struct kvm_pit_state ps;
4812 struct kvm_pit_state2 ps2;
4813 struct kvm_pit_config pit_config;
4817 case KVM_SET_TSS_ADDR:
4818 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4820 case KVM_SET_IDENTITY_MAP_ADDR: {
4823 mutex_lock(&kvm->lock);
4825 if (kvm->created_vcpus)
4826 goto set_identity_unlock;
4828 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4829 goto set_identity_unlock;
4830 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4831 set_identity_unlock:
4832 mutex_unlock(&kvm->lock);
4835 case KVM_SET_NR_MMU_PAGES:
4836 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4838 case KVM_GET_NR_MMU_PAGES:
4839 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4841 case KVM_CREATE_IRQCHIP: {
4842 mutex_lock(&kvm->lock);
4845 if (irqchip_in_kernel(kvm))
4846 goto create_irqchip_unlock;
4849 if (kvm->created_vcpus)
4850 goto create_irqchip_unlock;
4852 r = kvm_pic_init(kvm);
4854 goto create_irqchip_unlock;
4856 r = kvm_ioapic_init(kvm);
4858 kvm_pic_destroy(kvm);
4859 goto create_irqchip_unlock;
4862 r = kvm_setup_default_irq_routing(kvm);
4864 kvm_ioapic_destroy(kvm);
4865 kvm_pic_destroy(kvm);
4866 goto create_irqchip_unlock;
4868 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4870 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4871 create_irqchip_unlock:
4872 mutex_unlock(&kvm->lock);
4875 case KVM_CREATE_PIT:
4876 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4878 case KVM_CREATE_PIT2:
4880 if (copy_from_user(&u.pit_config, argp,
4881 sizeof(struct kvm_pit_config)))
4884 mutex_lock(&kvm->lock);
4887 goto create_pit_unlock;
4889 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4893 mutex_unlock(&kvm->lock);
4895 case KVM_GET_IRQCHIP: {
4896 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4897 struct kvm_irqchip *chip;
4899 chip = memdup_user(argp, sizeof(*chip));
4906 if (!irqchip_kernel(kvm))
4907 goto get_irqchip_out;
4908 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4910 goto get_irqchip_out;
4912 if (copy_to_user(argp, chip, sizeof(*chip)))
4913 goto get_irqchip_out;
4919 case KVM_SET_IRQCHIP: {
4920 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4921 struct kvm_irqchip *chip;
4923 chip = memdup_user(argp, sizeof(*chip));
4930 if (!irqchip_kernel(kvm))
4931 goto set_irqchip_out;
4932 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4934 goto set_irqchip_out;
4942 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4945 if (!kvm->arch.vpit)
4947 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4951 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4958 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
4961 if (!kvm->arch.vpit)
4963 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4966 case KVM_GET_PIT2: {
4968 if (!kvm->arch.vpit)
4970 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4974 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4979 case KVM_SET_PIT2: {
4981 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4984 if (!kvm->arch.vpit)
4986 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4989 case KVM_REINJECT_CONTROL: {
4990 struct kvm_reinject_control control;
4992 if (copy_from_user(&control, argp, sizeof(control)))
4994 r = kvm_vm_ioctl_reinject(kvm, &control);
4997 case KVM_SET_BOOT_CPU_ID:
4999 mutex_lock(&kvm->lock);
5000 if (kvm->created_vcpus)
5003 kvm->arch.bsp_vcpu_id = arg;
5004 mutex_unlock(&kvm->lock);
5006 case KVM_XEN_HVM_CONFIG: {
5007 struct kvm_xen_hvm_config xhc;
5009 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5014 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5018 case KVM_SET_CLOCK: {
5019 struct kvm_clock_data user_ns;
5023 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5032 * TODO: userspace has to take care of races with VCPU_RUN, so
5033 * kvm_gen_update_masterclock() can be cut down to locked
5034 * pvclock_update_vm_gtod_copy().
5036 kvm_gen_update_masterclock(kvm);
5037 now_ns = get_kvmclock_ns(kvm);
5038 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5039 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5042 case KVM_GET_CLOCK: {
5043 struct kvm_clock_data user_ns;
5046 now_ns = get_kvmclock_ns(kvm);
5047 user_ns.clock = now_ns;
5048 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5049 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5052 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5057 case KVM_MEMORY_ENCRYPT_OP: {
5059 if (kvm_x86_ops->mem_enc_op)
5060 r = kvm_x86_ops->mem_enc_op(kvm, argp);
5063 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5064 struct kvm_enc_region region;
5067 if (copy_from_user(®ion, argp, sizeof(region)))
5071 if (kvm_x86_ops->mem_enc_reg_region)
5072 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion);
5075 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5076 struct kvm_enc_region region;
5079 if (copy_from_user(®ion, argp, sizeof(region)))
5083 if (kvm_x86_ops->mem_enc_unreg_region)
5084 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion);
5087 case KVM_HYPERV_EVENTFD: {
5088 struct kvm_hyperv_eventfd hvevfd;
5091 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5093 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5096 case KVM_SET_PMU_EVENT_FILTER:
5097 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5106 static void kvm_init_msr_list(void)
5111 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5112 "Please update the fixed PMCs in msrs_to_save[]");
5113 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_GENERIC != 32,
5114 "Please update the generic perfctr/eventsel MSRs in msrs_to_save[]");
5116 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
5117 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
5121 * Even MSRs that are valid in the host may not be exposed
5122 * to the guests in some cases.
5124 switch (msrs_to_save[i]) {
5125 case MSR_IA32_BNDCFGS:
5126 if (!kvm_mpx_supported())
5130 if (!kvm_x86_ops->rdtscp_supported())
5133 case MSR_IA32_RTIT_CTL:
5134 case MSR_IA32_RTIT_STATUS:
5135 if (!kvm_x86_ops->pt_supported())
5138 case MSR_IA32_RTIT_CR3_MATCH:
5139 if (!kvm_x86_ops->pt_supported() ||
5140 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5143 case MSR_IA32_RTIT_OUTPUT_BASE:
5144 case MSR_IA32_RTIT_OUTPUT_MASK:
5145 if (!kvm_x86_ops->pt_supported() ||
5146 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5147 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5150 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5151 if (!kvm_x86_ops->pt_supported() ||
5152 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
5153 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5162 msrs_to_save[j] = msrs_to_save[i];
5165 num_msrs_to_save = j;
5167 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
5168 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5172 emulated_msrs[j] = emulated_msrs[i];
5175 num_emulated_msrs = j;
5177 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5178 struct kvm_msr_entry msr;
5180 msr.index = msr_based_features[i];
5181 if (kvm_get_msr_feature(&msr))
5185 msr_based_features[j] = msr_based_features[i];
5188 num_msr_based_features = j;
5191 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5199 if (!(lapic_in_kernel(vcpu) &&
5200 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5201 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5212 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5219 if (!(lapic_in_kernel(vcpu) &&
5220 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5222 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5224 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5234 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5235 struct kvm_segment *var, int seg)
5237 kvm_x86_ops->set_segment(vcpu, var, seg);
5240 void kvm_get_segment(struct kvm_vcpu *vcpu,
5241 struct kvm_segment *var, int seg)
5243 kvm_x86_ops->get_segment(vcpu, var, seg);
5246 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5247 struct x86_exception *exception)
5251 BUG_ON(!mmu_is_nested(vcpu));
5253 /* NPT walks are always user-walks */
5254 access |= PFERR_USER_MASK;
5255 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5260 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5261 struct x86_exception *exception)
5263 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5264 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5267 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5268 struct x86_exception *exception)
5270 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5271 access |= PFERR_FETCH_MASK;
5272 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5275 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5276 struct x86_exception *exception)
5278 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5279 access |= PFERR_WRITE_MASK;
5280 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5283 /* uses this to access any guest's mapped memory without checking CPL */
5284 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5285 struct x86_exception *exception)
5287 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5290 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5291 struct kvm_vcpu *vcpu, u32 access,
5292 struct x86_exception *exception)
5295 int r = X86EMUL_CONTINUE;
5298 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5300 unsigned offset = addr & (PAGE_SIZE-1);
5301 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5304 if (gpa == UNMAPPED_GVA)
5305 return X86EMUL_PROPAGATE_FAULT;
5306 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5309 r = X86EMUL_IO_NEEDED;
5321 /* used for instruction fetching */
5322 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5323 gva_t addr, void *val, unsigned int bytes,
5324 struct x86_exception *exception)
5326 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5327 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5331 /* Inline kvm_read_guest_virt_helper for speed. */
5332 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5334 if (unlikely(gpa == UNMAPPED_GVA))
5335 return X86EMUL_PROPAGATE_FAULT;
5337 offset = addr & (PAGE_SIZE-1);
5338 if (WARN_ON(offset + bytes > PAGE_SIZE))
5339 bytes = (unsigned)PAGE_SIZE - offset;
5340 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5342 if (unlikely(ret < 0))
5343 return X86EMUL_IO_NEEDED;
5345 return X86EMUL_CONTINUE;
5348 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5349 gva_t addr, void *val, unsigned int bytes,
5350 struct x86_exception *exception)
5352 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5355 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5356 * is returned, but our callers are not ready for that and they blindly
5357 * call kvm_inject_page_fault. Ensure that they at least do not leak
5358 * uninitialized kernel stack memory into cr2 and error code.
5360 memset(exception, 0, sizeof(*exception));
5361 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5364 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5366 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5367 gva_t addr, void *val, unsigned int bytes,
5368 struct x86_exception *exception, bool system)
5370 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5373 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5374 access |= PFERR_USER_MASK;
5376 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5379 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5380 unsigned long addr, void *val, unsigned int bytes)
5382 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5383 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5385 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5388 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5389 struct kvm_vcpu *vcpu, u32 access,
5390 struct x86_exception *exception)
5393 int r = X86EMUL_CONTINUE;
5396 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5399 unsigned offset = addr & (PAGE_SIZE-1);
5400 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5403 if (gpa == UNMAPPED_GVA)
5404 return X86EMUL_PROPAGATE_FAULT;
5405 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5407 r = X86EMUL_IO_NEEDED;
5419 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5420 unsigned int bytes, struct x86_exception *exception,
5423 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5424 u32 access = PFERR_WRITE_MASK;
5426 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5427 access |= PFERR_USER_MASK;
5429 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5433 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5434 unsigned int bytes, struct x86_exception *exception)
5436 /* kvm_write_guest_virt_system can pull in tons of pages. */
5437 vcpu->arch.l1tf_flush_l1d = true;
5440 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5441 * is returned, but our callers are not ready for that and they blindly
5442 * call kvm_inject_page_fault. Ensure that they at least do not leak
5443 * uninitialized kernel stack memory into cr2 and error code.
5445 memset(exception, 0, sizeof(*exception));
5446 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5447 PFERR_WRITE_MASK, exception);
5449 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5451 int handle_ud(struct kvm_vcpu *vcpu)
5453 int emul_type = EMULTYPE_TRAP_UD;
5454 char sig[5]; /* ud2; .ascii "kvm" */
5455 struct x86_exception e;
5457 if (force_emulation_prefix &&
5458 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5459 sig, sizeof(sig), &e) == 0 &&
5460 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5461 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5462 emul_type = EMULTYPE_TRAP_UD_FORCED;
5465 return kvm_emulate_instruction(vcpu, emul_type);
5467 EXPORT_SYMBOL_GPL(handle_ud);
5469 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5470 gpa_t gpa, bool write)
5472 /* For APIC access vmexit */
5473 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5476 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5477 trace_vcpu_match_mmio(gva, gpa, write, true);
5484 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5485 gpa_t *gpa, struct x86_exception *exception,
5488 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5489 | (write ? PFERR_WRITE_MASK : 0);
5492 * currently PKRU is only applied to ept enabled guest so
5493 * there is no pkey in EPT page table for L1 guest or EPT
5494 * shadow page table for L2 guest.
5496 if (vcpu_match_mmio_gva(vcpu, gva)
5497 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5498 vcpu->arch.mmio_access, 0, access)) {
5499 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5500 (gva & (PAGE_SIZE - 1));
5501 trace_vcpu_match_mmio(gva, *gpa, write, false);
5505 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5507 if (*gpa == UNMAPPED_GVA)
5510 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5513 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5514 const void *val, int bytes)
5518 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5521 kvm_page_track_write(vcpu, gpa, val, bytes);
5525 struct read_write_emulator_ops {
5526 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5528 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5529 void *val, int bytes);
5530 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5531 int bytes, void *val);
5532 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5533 void *val, int bytes);
5537 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5539 if (vcpu->mmio_read_completed) {
5540 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5541 vcpu->mmio_fragments[0].gpa, val);
5542 vcpu->mmio_read_completed = 0;
5549 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5550 void *val, int bytes)
5552 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5555 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5556 void *val, int bytes)
5558 return emulator_write_phys(vcpu, gpa, val, bytes);
5561 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5563 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5564 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5567 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5568 void *val, int bytes)
5570 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5571 return X86EMUL_IO_NEEDED;
5574 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5575 void *val, int bytes)
5577 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5579 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5580 return X86EMUL_CONTINUE;
5583 static const struct read_write_emulator_ops read_emultor = {
5584 .read_write_prepare = read_prepare,
5585 .read_write_emulate = read_emulate,
5586 .read_write_mmio = vcpu_mmio_read,
5587 .read_write_exit_mmio = read_exit_mmio,
5590 static const struct read_write_emulator_ops write_emultor = {
5591 .read_write_emulate = write_emulate,
5592 .read_write_mmio = write_mmio,
5593 .read_write_exit_mmio = write_exit_mmio,
5597 static int emulator_read_write_onepage(unsigned long addr, void *val,
5599 struct x86_exception *exception,
5600 struct kvm_vcpu *vcpu,
5601 const struct read_write_emulator_ops *ops)
5605 bool write = ops->write;
5606 struct kvm_mmio_fragment *frag;
5607 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5610 * If the exit was due to a NPF we may already have a GPA.
5611 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5612 * Note, this cannot be used on string operations since string
5613 * operation using rep will only have the initial GPA from the NPF
5616 if (vcpu->arch.gpa_available &&
5617 emulator_can_use_gpa(ctxt) &&
5618 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5619 gpa = vcpu->arch.gpa_val;
5620 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5622 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5624 return X86EMUL_PROPAGATE_FAULT;
5627 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5628 return X86EMUL_CONTINUE;
5631 * Is this MMIO handled locally?
5633 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5634 if (handled == bytes)
5635 return X86EMUL_CONTINUE;
5641 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5642 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5646 return X86EMUL_CONTINUE;
5649 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5651 void *val, unsigned int bytes,
5652 struct x86_exception *exception,
5653 const struct read_write_emulator_ops *ops)
5655 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5659 if (ops->read_write_prepare &&
5660 ops->read_write_prepare(vcpu, val, bytes))
5661 return X86EMUL_CONTINUE;
5663 vcpu->mmio_nr_fragments = 0;
5665 /* Crossing a page boundary? */
5666 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5669 now = -addr & ~PAGE_MASK;
5670 rc = emulator_read_write_onepage(addr, val, now, exception,
5673 if (rc != X86EMUL_CONTINUE)
5676 if (ctxt->mode != X86EMUL_MODE_PROT64)
5682 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5684 if (rc != X86EMUL_CONTINUE)
5687 if (!vcpu->mmio_nr_fragments)
5690 gpa = vcpu->mmio_fragments[0].gpa;
5692 vcpu->mmio_needed = 1;
5693 vcpu->mmio_cur_fragment = 0;
5695 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5696 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5697 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5698 vcpu->run->mmio.phys_addr = gpa;
5700 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5703 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5707 struct x86_exception *exception)
5709 return emulator_read_write(ctxt, addr, val, bytes,
5710 exception, &read_emultor);
5713 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5717 struct x86_exception *exception)
5719 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5720 exception, &write_emultor);
5723 #define CMPXCHG_TYPE(t, ptr, old, new) \
5724 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5726 #ifdef CONFIG_X86_64
5727 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5729 # define CMPXCHG64(ptr, old, new) \
5730 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5733 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5738 struct x86_exception *exception)
5740 struct kvm_host_map map;
5741 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5746 /* guests cmpxchg8b have to be emulated atomically */
5747 if (bytes > 8 || (bytes & (bytes - 1)))
5750 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5752 if (gpa == UNMAPPED_GVA ||
5753 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5756 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5759 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5762 kaddr = map.hva + offset_in_page(gpa);
5766 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5769 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5772 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5775 exchanged = CMPXCHG64(kaddr, old, new);
5781 kvm_vcpu_unmap(vcpu, &map, true);
5784 return X86EMUL_CMPXCHG_FAILED;
5786 kvm_page_track_write(vcpu, gpa, new, bytes);
5788 return X86EMUL_CONTINUE;
5791 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5793 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5796 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5800 for (i = 0; i < vcpu->arch.pio.count; i++) {
5801 if (vcpu->arch.pio.in)
5802 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5803 vcpu->arch.pio.size, pd);
5805 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5806 vcpu->arch.pio.port, vcpu->arch.pio.size,
5810 pd += vcpu->arch.pio.size;
5815 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5816 unsigned short port, void *val,
5817 unsigned int count, bool in)
5819 vcpu->arch.pio.port = port;
5820 vcpu->arch.pio.in = in;
5821 vcpu->arch.pio.count = count;
5822 vcpu->arch.pio.size = size;
5824 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5825 vcpu->arch.pio.count = 0;
5829 vcpu->run->exit_reason = KVM_EXIT_IO;
5830 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5831 vcpu->run->io.size = size;
5832 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5833 vcpu->run->io.count = count;
5834 vcpu->run->io.port = port;
5839 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5840 int size, unsigned short port, void *val,
5843 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5846 if (vcpu->arch.pio.count)
5849 memset(vcpu->arch.pio_data, 0, size * count);
5851 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5854 memcpy(val, vcpu->arch.pio_data, size * count);
5855 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5856 vcpu->arch.pio.count = 0;
5863 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5864 int size, unsigned short port,
5865 const void *val, unsigned int count)
5867 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5869 memcpy(vcpu->arch.pio_data, val, size * count);
5870 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5871 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5874 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5876 return kvm_x86_ops->get_segment_base(vcpu, seg);
5879 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5881 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5884 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5886 if (!need_emulate_wbinvd(vcpu))
5887 return X86EMUL_CONTINUE;
5889 if (kvm_x86_ops->has_wbinvd_exit()) {
5890 int cpu = get_cpu();
5892 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5893 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5894 wbinvd_ipi, NULL, 1);
5896 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5899 return X86EMUL_CONTINUE;
5902 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5904 kvm_emulate_wbinvd_noskip(vcpu);
5905 return kvm_skip_emulated_instruction(vcpu);
5907 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5911 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5913 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5916 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5917 unsigned long *dest)
5919 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5922 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5923 unsigned long value)
5926 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5929 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5931 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5934 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5936 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5937 unsigned long value;
5941 value = kvm_read_cr0(vcpu);
5944 value = vcpu->arch.cr2;
5947 value = kvm_read_cr3(vcpu);
5950 value = kvm_read_cr4(vcpu);
5953 value = kvm_get_cr8(vcpu);
5956 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5963 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5965 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5970 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5973 vcpu->arch.cr2 = val;
5976 res = kvm_set_cr3(vcpu, val);
5979 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5982 res = kvm_set_cr8(vcpu, val);
5985 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5992 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5994 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5997 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5999 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
6002 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6004 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
6007 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6009 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
6012 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6014 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
6017 static unsigned long emulator_get_cached_segment_base(
6018 struct x86_emulate_ctxt *ctxt, int seg)
6020 return get_segment_base(emul_to_vcpu(ctxt), seg);
6023 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6024 struct desc_struct *desc, u32 *base3,
6027 struct kvm_segment var;
6029 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6030 *selector = var.selector;
6033 memset(desc, 0, sizeof(*desc));
6041 set_desc_limit(desc, var.limit);
6042 set_desc_base(desc, (unsigned long)var.base);
6043 #ifdef CONFIG_X86_64
6045 *base3 = var.base >> 32;
6047 desc->type = var.type;
6049 desc->dpl = var.dpl;
6050 desc->p = var.present;
6051 desc->avl = var.avl;
6059 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6060 struct desc_struct *desc, u32 base3,
6063 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6064 struct kvm_segment var;
6066 var.selector = selector;
6067 var.base = get_desc_base(desc);
6068 #ifdef CONFIG_X86_64
6069 var.base |= ((u64)base3) << 32;
6071 var.limit = get_desc_limit(desc);
6073 var.limit = (var.limit << 12) | 0xfff;
6074 var.type = desc->type;
6075 var.dpl = desc->dpl;
6080 var.avl = desc->avl;
6081 var.present = desc->p;
6082 var.unusable = !var.present;
6085 kvm_set_segment(vcpu, &var, seg);
6089 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6090 u32 msr_index, u64 *pdata)
6092 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6095 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6096 u32 msr_index, u64 data)
6098 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6101 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6103 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6105 return vcpu->arch.smbase;
6108 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6110 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6112 vcpu->arch.smbase = smbase;
6115 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6118 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
6121 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6122 u32 pmc, u64 *pdata)
6124 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6127 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6129 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6132 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6133 struct x86_instruction_info *info,
6134 enum x86_intercept_stage stage)
6136 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
6139 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6140 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
6142 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
6145 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6147 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6150 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6152 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6155 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6157 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6160 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6162 return emul_to_vcpu(ctxt)->arch.hflags;
6165 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6167 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6170 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6171 const char *smstate)
6173 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6176 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6178 kvm_smm_changed(emul_to_vcpu(ctxt));
6181 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6183 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6186 static const struct x86_emulate_ops emulate_ops = {
6187 .read_gpr = emulator_read_gpr,
6188 .write_gpr = emulator_write_gpr,
6189 .read_std = emulator_read_std,
6190 .write_std = emulator_write_std,
6191 .read_phys = kvm_read_guest_phys_system,
6192 .fetch = kvm_fetch_guest_virt,
6193 .read_emulated = emulator_read_emulated,
6194 .write_emulated = emulator_write_emulated,
6195 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6196 .invlpg = emulator_invlpg,
6197 .pio_in_emulated = emulator_pio_in_emulated,
6198 .pio_out_emulated = emulator_pio_out_emulated,
6199 .get_segment = emulator_get_segment,
6200 .set_segment = emulator_set_segment,
6201 .get_cached_segment_base = emulator_get_cached_segment_base,
6202 .get_gdt = emulator_get_gdt,
6203 .get_idt = emulator_get_idt,
6204 .set_gdt = emulator_set_gdt,
6205 .set_idt = emulator_set_idt,
6206 .get_cr = emulator_get_cr,
6207 .set_cr = emulator_set_cr,
6208 .cpl = emulator_get_cpl,
6209 .get_dr = emulator_get_dr,
6210 .set_dr = emulator_set_dr,
6211 .get_smbase = emulator_get_smbase,
6212 .set_smbase = emulator_set_smbase,
6213 .set_msr = emulator_set_msr,
6214 .get_msr = emulator_get_msr,
6215 .check_pmc = emulator_check_pmc,
6216 .read_pmc = emulator_read_pmc,
6217 .halt = emulator_halt,
6218 .wbinvd = emulator_wbinvd,
6219 .fix_hypercall = emulator_fix_hypercall,
6220 .intercept = emulator_intercept,
6221 .get_cpuid = emulator_get_cpuid,
6222 .set_nmi_mask = emulator_set_nmi_mask,
6223 .get_hflags = emulator_get_hflags,
6224 .set_hflags = emulator_set_hflags,
6225 .pre_leave_smm = emulator_pre_leave_smm,
6226 .post_leave_smm = emulator_post_leave_smm,
6227 .set_xcr = emulator_set_xcr,
6230 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6232 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6234 * an sti; sti; sequence only disable interrupts for the first
6235 * instruction. So, if the last instruction, be it emulated or
6236 * not, left the system with the INT_STI flag enabled, it
6237 * means that the last instruction is an sti. We should not
6238 * leave the flag on in this case. The same goes for mov ss
6240 if (int_shadow & mask)
6242 if (unlikely(int_shadow || mask)) {
6243 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6245 kvm_make_request(KVM_REQ_EVENT, vcpu);
6249 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6251 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6252 if (ctxt->exception.vector == PF_VECTOR)
6253 return kvm_propagate_fault(vcpu, &ctxt->exception);
6255 if (ctxt->exception.error_code_valid)
6256 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6257 ctxt->exception.error_code);
6259 kvm_queue_exception(vcpu, ctxt->exception.vector);
6263 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6265 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6268 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6270 ctxt->eflags = kvm_get_rflags(vcpu);
6271 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6273 ctxt->eip = kvm_rip_read(vcpu);
6274 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6275 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6276 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6277 cs_db ? X86EMUL_MODE_PROT32 :
6278 X86EMUL_MODE_PROT16;
6279 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6280 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6281 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6283 init_decode_cache(ctxt);
6284 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6287 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6289 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6292 init_emulate_ctxt(vcpu);
6296 ctxt->_eip = ctxt->eip + inc_eip;
6297 ret = emulate_int_real(ctxt, irq);
6299 if (ret != X86EMUL_CONTINUE) {
6300 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6302 ctxt->eip = ctxt->_eip;
6303 kvm_rip_write(vcpu, ctxt->eip);
6304 kvm_set_rflags(vcpu, ctxt->eflags);
6307 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6309 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6311 ++vcpu->stat.insn_emulation_fail;
6312 trace_kvm_emulate_insn_failed(vcpu);
6314 if (emulation_type & EMULTYPE_VMWARE_GP) {
6315 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6319 if (emulation_type & EMULTYPE_SKIP) {
6320 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6321 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6322 vcpu->run->internal.ndata = 0;
6326 kvm_queue_exception(vcpu, UD_VECTOR);
6328 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6329 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6330 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6331 vcpu->run->internal.ndata = 0;
6338 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
6339 bool write_fault_to_shadow_pgtable,
6345 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6348 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6351 if (!vcpu->arch.mmu->direct_map) {
6353 * Write permission should be allowed since only
6354 * write access need to be emulated.
6356 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6359 * If the mapping is invalid in guest, let cpu retry
6360 * it to generate fault.
6362 if (gpa == UNMAPPED_GVA)
6367 * Do not retry the unhandleable instruction if it faults on the
6368 * readonly host memory, otherwise it will goto a infinite loop:
6369 * retry instruction -> write #PF -> emulation fail -> retry
6370 * instruction -> ...
6372 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6375 * If the instruction failed on the error pfn, it can not be fixed,
6376 * report the error to userspace.
6378 if (is_error_noslot_pfn(pfn))
6381 kvm_release_pfn_clean(pfn);
6383 /* The instructions are well-emulated on direct mmu. */
6384 if (vcpu->arch.mmu->direct_map) {
6385 unsigned int indirect_shadow_pages;
6387 spin_lock(&vcpu->kvm->mmu_lock);
6388 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6389 spin_unlock(&vcpu->kvm->mmu_lock);
6391 if (indirect_shadow_pages)
6392 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6398 * if emulation was due to access to shadowed page table
6399 * and it failed try to unshadow page and re-enter the
6400 * guest to let CPU execute the instruction.
6402 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6405 * If the access faults on its page table, it can not
6406 * be fixed by unprotecting shadow page and it should
6407 * be reported to userspace.
6409 return !write_fault_to_shadow_pgtable;
6412 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6413 unsigned long cr2, int emulation_type)
6415 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6416 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6418 last_retry_eip = vcpu->arch.last_retry_eip;
6419 last_retry_addr = vcpu->arch.last_retry_addr;
6422 * If the emulation is caused by #PF and it is non-page_table
6423 * writing instruction, it means the VM-EXIT is caused by shadow
6424 * page protected, we can zap the shadow page and retry this
6425 * instruction directly.
6427 * Note: if the guest uses a non-page-table modifying instruction
6428 * on the PDE that points to the instruction, then we will unmap
6429 * the instruction and go to an infinite loop. So, we cache the
6430 * last retried eip and the last fault address, if we meet the eip
6431 * and the address again, we can break out of the potential infinite
6434 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6436 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6439 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6442 if (x86_page_table_writing_insn(ctxt))
6445 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6448 vcpu->arch.last_retry_eip = ctxt->eip;
6449 vcpu->arch.last_retry_addr = cr2;
6451 if (!vcpu->arch.mmu->direct_map)
6452 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6454 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6459 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6460 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6462 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6464 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6465 /* This is a good place to trace that we are exiting SMM. */
6466 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6468 /* Process a latched INIT or SMI, if any. */
6469 kvm_make_request(KVM_REQ_EVENT, vcpu);
6472 kvm_mmu_reset_context(vcpu);
6475 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6484 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6485 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6490 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6492 struct kvm_run *kvm_run = vcpu->run;
6494 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6495 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6496 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6497 kvm_run->debug.arch.exception = DB_VECTOR;
6498 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6501 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6505 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6507 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6510 r = kvm_x86_ops->skip_emulated_instruction(vcpu);
6515 * rflags is the old, "raw" value of the flags. The new value has
6516 * not been saved yet.
6518 * This is correct even for TF set by the guest, because "the
6519 * processor will not generate this exception after the instruction
6520 * that sets the TF flag".
6522 if (unlikely(rflags & X86_EFLAGS_TF))
6523 r = kvm_vcpu_do_singlestep(vcpu);
6526 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6528 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6530 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6531 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6532 struct kvm_run *kvm_run = vcpu->run;
6533 unsigned long eip = kvm_get_linear_rip(vcpu);
6534 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6535 vcpu->arch.guest_debug_dr7,
6539 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6540 kvm_run->debug.arch.pc = eip;
6541 kvm_run->debug.arch.exception = DB_VECTOR;
6542 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6548 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6549 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6550 unsigned long eip = kvm_get_linear_rip(vcpu);
6551 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6556 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6557 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6558 kvm_queue_exception(vcpu, DB_VECTOR);
6567 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6569 switch (ctxt->opcode_len) {
6576 case 0xe6: /* OUT */
6580 case 0x6c: /* INS */
6582 case 0x6e: /* OUTS */
6589 case 0x33: /* RDPMC */
6598 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6605 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6606 bool writeback = true;
6607 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6609 vcpu->arch.l1tf_flush_l1d = true;
6612 * Clear write_fault_to_shadow_pgtable here to ensure it is
6615 vcpu->arch.write_fault_to_shadow_pgtable = false;
6616 kvm_clear_exception_queue(vcpu);
6618 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6619 init_emulate_ctxt(vcpu);
6622 * We will reenter on the same instruction since
6623 * we do not set complete_userspace_io. This does not
6624 * handle watchpoints yet, those would be handled in
6627 if (!(emulation_type & EMULTYPE_SKIP) &&
6628 kvm_vcpu_check_breakpoint(vcpu, &r))
6631 ctxt->interruptibility = 0;
6632 ctxt->have_exception = false;
6633 ctxt->exception.vector = -1;
6634 ctxt->perm_ok = false;
6636 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6638 r = x86_decode_insn(ctxt, insn, insn_len);
6640 trace_kvm_emulate_insn_start(vcpu);
6641 ++vcpu->stat.insn_emulation;
6642 if (r != EMULATION_OK) {
6643 if ((emulation_type & EMULTYPE_TRAP_UD) ||
6644 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6645 kvm_queue_exception(vcpu, UD_VECTOR);
6648 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6651 if (ctxt->have_exception) {
6653 * #UD should result in just EMULATION_FAILED, and trap-like
6654 * exception should not be encountered during decode.
6656 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6657 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6658 inject_emulated_exception(vcpu);
6661 return handle_emulation_failure(vcpu, emulation_type);
6665 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6666 !is_vmware_backdoor_opcode(ctxt)) {
6667 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6672 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6673 * for kvm_skip_emulated_instruction(). The caller is responsible for
6674 * updating interruptibility state and injecting single-step #DBs.
6676 if (emulation_type & EMULTYPE_SKIP) {
6677 kvm_rip_write(vcpu, ctxt->_eip);
6678 if (ctxt->eflags & X86_EFLAGS_RF)
6679 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6683 if (retry_instruction(ctxt, cr2, emulation_type))
6686 /* this is needed for vmware backdoor interface to work since it
6687 changes registers values during IO operation */
6688 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6689 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6690 emulator_invalidate_register_cache(ctxt);
6694 /* Save the faulting GPA (cr2) in the address field */
6695 ctxt->exception.address = cr2;
6697 r = x86_emulate_insn(ctxt);
6699 if (r == EMULATION_INTERCEPTED)
6702 if (r == EMULATION_FAILED) {
6703 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6707 return handle_emulation_failure(vcpu, emulation_type);
6710 if (ctxt->have_exception) {
6712 if (inject_emulated_exception(vcpu))
6714 } else if (vcpu->arch.pio.count) {
6715 if (!vcpu->arch.pio.in) {
6716 /* FIXME: return into emulator if single-stepping. */
6717 vcpu->arch.pio.count = 0;
6720 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6723 } else if (vcpu->mmio_needed) {
6724 ++vcpu->stat.mmio_exits;
6726 if (!vcpu->mmio_is_write)
6729 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6730 } else if (r == EMULATION_RESTART)
6736 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6737 toggle_interruptibility(vcpu, ctxt->interruptibility);
6738 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6739 if (!ctxt->have_exception ||
6740 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6741 kvm_rip_write(vcpu, ctxt->eip);
6743 r = kvm_vcpu_do_singlestep(vcpu);
6744 __kvm_set_rflags(vcpu, ctxt->eflags);
6748 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6749 * do nothing, and it will be requested again as soon as
6750 * the shadow expires. But we still need to check here,
6751 * because POPF has no interrupt shadow.
6753 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6754 kvm_make_request(KVM_REQ_EVENT, vcpu);
6756 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6761 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6763 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6765 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6767 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6768 void *insn, int insn_len)
6770 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6772 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6774 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6776 vcpu->arch.pio.count = 0;
6780 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6782 vcpu->arch.pio.count = 0;
6784 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6787 return kvm_skip_emulated_instruction(vcpu);
6790 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6791 unsigned short port)
6793 unsigned long val = kvm_rax_read(vcpu);
6794 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6795 size, port, &val, 1);
6800 * Workaround userspace that relies on old KVM behavior of %rip being
6801 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6804 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6805 vcpu->arch.complete_userspace_io =
6806 complete_fast_pio_out_port_0x7e;
6807 kvm_skip_emulated_instruction(vcpu);
6809 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6810 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6815 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6819 /* We should only ever be called with arch.pio.count equal to 1 */
6820 BUG_ON(vcpu->arch.pio.count != 1);
6822 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6823 vcpu->arch.pio.count = 0;
6827 /* For size less than 4 we merge, else we zero extend */
6828 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6831 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6832 * the copy and tracing
6834 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6835 vcpu->arch.pio.port, &val, 1);
6836 kvm_rax_write(vcpu, val);
6838 return kvm_skip_emulated_instruction(vcpu);
6841 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6842 unsigned short port)
6847 /* For size less than 4 we merge, else we zero extend */
6848 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
6850 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6853 kvm_rax_write(vcpu, val);
6857 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6858 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6863 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6868 ret = kvm_fast_pio_in(vcpu, size, port);
6870 ret = kvm_fast_pio_out(vcpu, size, port);
6871 return ret && kvm_skip_emulated_instruction(vcpu);
6873 EXPORT_SYMBOL_GPL(kvm_fast_pio);
6875 static int kvmclock_cpu_down_prep(unsigned int cpu)
6877 __this_cpu_write(cpu_tsc_khz, 0);
6881 static void tsc_khz_changed(void *data)
6883 struct cpufreq_freqs *freq = data;
6884 unsigned long khz = 0;
6888 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6889 khz = cpufreq_quick_get(raw_smp_processor_id());
6892 __this_cpu_write(cpu_tsc_khz, khz);
6895 #ifdef CONFIG_X86_64
6896 static void kvm_hyperv_tsc_notifier(void)
6899 struct kvm_vcpu *vcpu;
6902 mutex_lock(&kvm_lock);
6903 list_for_each_entry(kvm, &vm_list, vm_list)
6904 kvm_make_mclock_inprogress_request(kvm);
6906 hyperv_stop_tsc_emulation();
6908 /* TSC frequency always matches when on Hyper-V */
6909 for_each_present_cpu(cpu)
6910 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6911 kvm_max_guest_tsc_khz = tsc_khz;
6913 list_for_each_entry(kvm, &vm_list, vm_list) {
6914 struct kvm_arch *ka = &kvm->arch;
6916 spin_lock(&ka->pvclock_gtod_sync_lock);
6918 pvclock_update_vm_gtod_copy(kvm);
6920 kvm_for_each_vcpu(cpu, vcpu, kvm)
6921 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6923 kvm_for_each_vcpu(cpu, vcpu, kvm)
6924 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6926 spin_unlock(&ka->pvclock_gtod_sync_lock);
6928 mutex_unlock(&kvm_lock);
6932 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
6935 struct kvm_vcpu *vcpu;
6936 int i, send_ipi = 0;
6939 * We allow guests to temporarily run on slowing clocks,
6940 * provided we notify them after, or to run on accelerating
6941 * clocks, provided we notify them before. Thus time never
6944 * However, we have a problem. We can't atomically update
6945 * the frequency of a given CPU from this function; it is
6946 * merely a notifier, which can be called from any CPU.
6947 * Changing the TSC frequency at arbitrary points in time
6948 * requires a recomputation of local variables related to
6949 * the TSC for each VCPU. We must flag these local variables
6950 * to be updated and be sure the update takes place with the
6951 * new frequency before any guests proceed.
6953 * Unfortunately, the combination of hotplug CPU and frequency
6954 * change creates an intractable locking scenario; the order
6955 * of when these callouts happen is undefined with respect to
6956 * CPU hotplug, and they can race with each other. As such,
6957 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6958 * undefined; you can actually have a CPU frequency change take
6959 * place in between the computation of X and the setting of the
6960 * variable. To protect against this problem, all updates of
6961 * the per_cpu tsc_khz variable are done in an interrupt
6962 * protected IPI, and all callers wishing to update the value
6963 * must wait for a synchronous IPI to complete (which is trivial
6964 * if the caller is on the CPU already). This establishes the
6965 * necessary total order on variable updates.
6967 * Note that because a guest time update may take place
6968 * anytime after the setting of the VCPU's request bit, the
6969 * correct TSC value must be set before the request. However,
6970 * to ensure the update actually makes it to any guest which
6971 * starts running in hardware virtualization between the set
6972 * and the acquisition of the spinlock, we must also ping the
6973 * CPU after setting the request bit.
6977 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6979 mutex_lock(&kvm_lock);
6980 list_for_each_entry(kvm, &vm_list, vm_list) {
6981 kvm_for_each_vcpu(i, vcpu, kvm) {
6982 if (vcpu->cpu != cpu)
6984 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6985 if (vcpu->cpu != raw_smp_processor_id())
6989 mutex_unlock(&kvm_lock);
6991 if (freq->old < freq->new && send_ipi) {
6993 * We upscale the frequency. Must make the guest
6994 * doesn't see old kvmclock values while running with
6995 * the new frequency, otherwise we risk the guest sees
6996 * time go backwards.
6998 * In case we update the frequency for another cpu
6999 * (which might be in guest context) send an interrupt
7000 * to kick the cpu out of guest context. Next time
7001 * guest context is entered kvmclock will be updated,
7002 * so the guest will not see stale values.
7004 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7008 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7011 struct cpufreq_freqs *freq = data;
7014 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7016 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7019 for_each_cpu(cpu, freq->policy->cpus)
7020 __kvmclock_cpufreq_notifier(freq, cpu);
7025 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7026 .notifier_call = kvmclock_cpufreq_notifier
7029 static int kvmclock_cpu_online(unsigned int cpu)
7031 tsc_khz_changed(NULL);
7035 static void kvm_timer_init(void)
7037 max_tsc_khz = tsc_khz;
7039 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7040 #ifdef CONFIG_CPU_FREQ
7041 struct cpufreq_policy policy;
7044 memset(&policy, 0, sizeof(policy));
7046 cpufreq_get_policy(&policy, cpu);
7047 if (policy.cpuinfo.max_freq)
7048 max_tsc_khz = policy.cpuinfo.max_freq;
7051 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7052 CPUFREQ_TRANSITION_NOTIFIER);
7055 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7056 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7059 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7060 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7062 int kvm_is_in_guest(void)
7064 return __this_cpu_read(current_vcpu) != NULL;
7067 static int kvm_is_user_mode(void)
7071 if (__this_cpu_read(current_vcpu))
7072 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
7074 return user_mode != 0;
7077 static unsigned long kvm_get_guest_ip(void)
7079 unsigned long ip = 0;
7081 if (__this_cpu_read(current_vcpu))
7082 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7087 static void kvm_handle_intel_pt_intr(void)
7089 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7091 kvm_make_request(KVM_REQ_PMI, vcpu);
7092 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7093 (unsigned long *)&vcpu->arch.pmu.global_status);
7096 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7097 .is_in_guest = kvm_is_in_guest,
7098 .is_user_mode = kvm_is_user_mode,
7099 .get_guest_ip = kvm_get_guest_ip,
7100 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7103 #ifdef CONFIG_X86_64
7104 static void pvclock_gtod_update_fn(struct work_struct *work)
7108 struct kvm_vcpu *vcpu;
7111 mutex_lock(&kvm_lock);
7112 list_for_each_entry(kvm, &vm_list, vm_list)
7113 kvm_for_each_vcpu(i, vcpu, kvm)
7114 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7115 atomic_set(&kvm_guest_has_master_clock, 0);
7116 mutex_unlock(&kvm_lock);
7119 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7122 * Notification about pvclock gtod data update.
7124 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7127 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7128 struct timekeeper *tk = priv;
7130 update_pvclock_gtod(tk);
7132 /* disable master clock if host does not trust, or does not
7133 * use, TSC based clocksource.
7135 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7136 atomic_read(&kvm_guest_has_master_clock) != 0)
7137 queue_work(system_long_wq, &pvclock_gtod_work);
7142 static struct notifier_block pvclock_gtod_notifier = {
7143 .notifier_call = pvclock_gtod_notify,
7147 int kvm_arch_init(void *opaque)
7150 struct kvm_x86_ops *ops = opaque;
7153 printk(KERN_ERR "kvm: already loaded the other module\n");
7158 if (!ops->cpu_has_kvm_support()) {
7159 printk(KERN_ERR "kvm: no hardware support\n");
7163 if (ops->disabled_by_bios()) {
7164 printk(KERN_ERR "kvm: disabled by bios\n");
7170 * KVM explicitly assumes that the guest has an FPU and
7171 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7172 * vCPU's FPU state as a fxregs_state struct.
7174 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7175 printk(KERN_ERR "kvm: inadequate fpu\n");
7181 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7182 __alignof__(struct fpu), SLAB_ACCOUNT,
7184 if (!x86_fpu_cache) {
7185 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7189 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7191 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7192 goto out_free_x86_fpu_cache;
7195 r = kvm_mmu_module_init();
7197 goto out_free_percpu;
7201 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7202 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7203 PT_PRESENT_MASK, 0, sme_me_mask);
7206 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7208 if (boot_cpu_has(X86_FEATURE_XSAVE))
7209 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7212 if (pi_inject_timer == -1)
7213 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7214 #ifdef CONFIG_X86_64
7215 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7217 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7218 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7224 free_percpu(shared_msrs);
7225 out_free_x86_fpu_cache:
7226 kmem_cache_destroy(x86_fpu_cache);
7231 void kvm_arch_exit(void)
7233 #ifdef CONFIG_X86_64
7234 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7235 clear_hv_tscchange_cb();
7238 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7240 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7241 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7242 CPUFREQ_TRANSITION_NOTIFIER);
7243 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7244 #ifdef CONFIG_X86_64
7245 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7248 kvm_mmu_module_exit();
7249 free_percpu(shared_msrs);
7250 kmem_cache_destroy(x86_fpu_cache);
7253 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7255 ++vcpu->stat.halt_exits;
7256 if (lapic_in_kernel(vcpu)) {
7257 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7260 vcpu->run->exit_reason = KVM_EXIT_HLT;
7264 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7266 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7268 int ret = kvm_skip_emulated_instruction(vcpu);
7270 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7271 * KVM_EXIT_DEBUG here.
7273 return kvm_vcpu_halt(vcpu) && ret;
7275 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7277 #ifdef CONFIG_X86_64
7278 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7279 unsigned long clock_type)
7281 struct kvm_clock_pairing clock_pairing;
7282 struct timespec64 ts;
7286 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7287 return -KVM_EOPNOTSUPP;
7289 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7290 return -KVM_EOPNOTSUPP;
7292 clock_pairing.sec = ts.tv_sec;
7293 clock_pairing.nsec = ts.tv_nsec;
7294 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7295 clock_pairing.flags = 0;
7296 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7299 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7300 sizeof(struct kvm_clock_pairing)))
7308 * kvm_pv_kick_cpu_op: Kick a vcpu.
7310 * @apicid - apicid of vcpu to be kicked.
7312 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7314 struct kvm_lapic_irq lapic_irq;
7316 lapic_irq.shorthand = 0;
7317 lapic_irq.dest_mode = 0;
7318 lapic_irq.level = 0;
7319 lapic_irq.dest_id = apicid;
7320 lapic_irq.msi_redir_hint = false;
7322 lapic_irq.delivery_mode = APIC_DM_REMRD;
7323 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7326 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7328 if (!lapic_in_kernel(vcpu)) {
7329 WARN_ON_ONCE(vcpu->arch.apicv_active);
7332 if (!vcpu->arch.apicv_active)
7335 vcpu->arch.apicv_active = false;
7336 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7339 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7341 struct kvm_vcpu *target = NULL;
7342 struct kvm_apic_map *map;
7345 map = rcu_dereference(kvm->arch.apic_map);
7347 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7348 target = map->phys_map[dest_id]->vcpu;
7352 if (target && READ_ONCE(target->ready))
7353 kvm_vcpu_yield_to(target);
7356 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7358 unsigned long nr, a0, a1, a2, a3, ret;
7361 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7362 return kvm_hv_hypercall(vcpu);
7364 nr = kvm_rax_read(vcpu);
7365 a0 = kvm_rbx_read(vcpu);
7366 a1 = kvm_rcx_read(vcpu);
7367 a2 = kvm_rdx_read(vcpu);
7368 a3 = kvm_rsi_read(vcpu);
7370 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7372 op_64_bit = is_64_bit_mode(vcpu);
7381 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7387 case KVM_HC_VAPIC_POLL_IRQ:
7390 case KVM_HC_KICK_CPU:
7391 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7392 kvm_sched_yield(vcpu->kvm, a1);
7395 #ifdef CONFIG_X86_64
7396 case KVM_HC_CLOCK_PAIRING:
7397 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7400 case KVM_HC_SEND_IPI:
7401 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7403 case KVM_HC_SCHED_YIELD:
7404 kvm_sched_yield(vcpu->kvm, a0);
7414 kvm_rax_write(vcpu, ret);
7416 ++vcpu->stat.hypercalls;
7417 return kvm_skip_emulated_instruction(vcpu);
7419 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7421 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7423 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7424 char instruction[3];
7425 unsigned long rip = kvm_rip_read(vcpu);
7427 kvm_x86_ops->patch_hypercall(vcpu, instruction);
7429 return emulator_write_emulated(ctxt, rip, instruction, 3,
7433 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7435 return vcpu->run->request_interrupt_window &&
7436 likely(!pic_in_kernel(vcpu->kvm));
7439 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7441 struct kvm_run *kvm_run = vcpu->run;
7443 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7444 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7445 kvm_run->cr8 = kvm_get_cr8(vcpu);
7446 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7447 kvm_run->ready_for_interrupt_injection =
7448 pic_in_kernel(vcpu->kvm) ||
7449 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7452 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7456 if (!kvm_x86_ops->update_cr8_intercept)
7459 if (!lapic_in_kernel(vcpu))
7462 if (vcpu->arch.apicv_active)
7465 if (!vcpu->arch.apic->vapic_addr)
7466 max_irr = kvm_lapic_find_highest_irr(vcpu);
7473 tpr = kvm_lapic_get_cr8(vcpu);
7475 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7478 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7482 /* try to reinject previous events if any */
7484 if (vcpu->arch.exception.injected)
7485 kvm_x86_ops->queue_exception(vcpu);
7487 * Do not inject an NMI or interrupt if there is a pending
7488 * exception. Exceptions and interrupts are recognized at
7489 * instruction boundaries, i.e. the start of an instruction.
7490 * Trap-like exceptions, e.g. #DB, have higher priority than
7491 * NMIs and interrupts, i.e. traps are recognized before an
7492 * NMI/interrupt that's pending on the same instruction.
7493 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7494 * priority, but are only generated (pended) during instruction
7495 * execution, i.e. a pending fault-like exception means the
7496 * fault occurred on the *previous* instruction and must be
7497 * serviced prior to recognizing any new events in order to
7498 * fully complete the previous instruction.
7500 else if (!vcpu->arch.exception.pending) {
7501 if (vcpu->arch.nmi_injected)
7502 kvm_x86_ops->set_nmi(vcpu);
7503 else if (vcpu->arch.interrupt.injected)
7504 kvm_x86_ops->set_irq(vcpu);
7508 * Call check_nested_events() even if we reinjected a previous event
7509 * in order for caller to determine if it should require immediate-exit
7510 * from L2 to L1 due to pending L1 events which require exit
7513 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7514 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7519 /* try to inject new event if pending */
7520 if (vcpu->arch.exception.pending) {
7521 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7522 vcpu->arch.exception.has_error_code,
7523 vcpu->arch.exception.error_code);
7525 WARN_ON_ONCE(vcpu->arch.exception.injected);
7526 vcpu->arch.exception.pending = false;
7527 vcpu->arch.exception.injected = true;
7529 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7530 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7533 if (vcpu->arch.exception.nr == DB_VECTOR) {
7535 * This code assumes that nSVM doesn't use
7536 * check_nested_events(). If it does, the
7537 * DR6/DR7 changes should happen before L1
7538 * gets a #VMEXIT for an intercepted #DB in
7539 * L2. (Under VMX, on the other hand, the
7540 * DR6/DR7 changes should not happen in the
7541 * event of a VM-exit to L1 for an intercepted
7544 kvm_deliver_exception_payload(vcpu);
7545 if (vcpu->arch.dr7 & DR7_GD) {
7546 vcpu->arch.dr7 &= ~DR7_GD;
7547 kvm_update_dr7(vcpu);
7551 kvm_x86_ops->queue_exception(vcpu);
7554 /* Don't consider new event if we re-injected an event */
7555 if (kvm_event_needs_reinjection(vcpu))
7558 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7559 kvm_x86_ops->smi_allowed(vcpu)) {
7560 vcpu->arch.smi_pending = false;
7561 ++vcpu->arch.smi_count;
7563 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7564 --vcpu->arch.nmi_pending;
7565 vcpu->arch.nmi_injected = true;
7566 kvm_x86_ops->set_nmi(vcpu);
7567 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7569 * Because interrupts can be injected asynchronously, we are
7570 * calling check_nested_events again here to avoid a race condition.
7571 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7572 * proposal and current concerns. Perhaps we should be setting
7573 * KVM_REQ_EVENT only on certain events and not unconditionally?
7575 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7576 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7580 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7581 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7583 kvm_x86_ops->set_irq(vcpu);
7590 static void process_nmi(struct kvm_vcpu *vcpu)
7595 * x86 is limited to one NMI running, and one NMI pending after it.
7596 * If an NMI is already in progress, limit further NMIs to just one.
7597 * Otherwise, allow two (and we'll inject the first one immediately).
7599 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7602 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7603 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7604 kvm_make_request(KVM_REQ_EVENT, vcpu);
7607 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7610 flags |= seg->g << 23;
7611 flags |= seg->db << 22;
7612 flags |= seg->l << 21;
7613 flags |= seg->avl << 20;
7614 flags |= seg->present << 15;
7615 flags |= seg->dpl << 13;
7616 flags |= seg->s << 12;
7617 flags |= seg->type << 8;
7621 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7623 struct kvm_segment seg;
7626 kvm_get_segment(vcpu, &seg, n);
7627 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7630 offset = 0x7f84 + n * 12;
7632 offset = 0x7f2c + (n - 3) * 12;
7634 put_smstate(u32, buf, offset + 8, seg.base);
7635 put_smstate(u32, buf, offset + 4, seg.limit);
7636 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7639 #ifdef CONFIG_X86_64
7640 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7642 struct kvm_segment seg;
7646 kvm_get_segment(vcpu, &seg, n);
7647 offset = 0x7e00 + n * 16;
7649 flags = enter_smm_get_segment_flags(&seg) >> 8;
7650 put_smstate(u16, buf, offset, seg.selector);
7651 put_smstate(u16, buf, offset + 2, flags);
7652 put_smstate(u32, buf, offset + 4, seg.limit);
7653 put_smstate(u64, buf, offset + 8, seg.base);
7657 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7660 struct kvm_segment seg;
7664 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7665 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7666 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7667 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7669 for (i = 0; i < 8; i++)
7670 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7672 kvm_get_dr(vcpu, 6, &val);
7673 put_smstate(u32, buf, 0x7fcc, (u32)val);
7674 kvm_get_dr(vcpu, 7, &val);
7675 put_smstate(u32, buf, 0x7fc8, (u32)val);
7677 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7678 put_smstate(u32, buf, 0x7fc4, seg.selector);
7679 put_smstate(u32, buf, 0x7f64, seg.base);
7680 put_smstate(u32, buf, 0x7f60, seg.limit);
7681 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7683 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7684 put_smstate(u32, buf, 0x7fc0, seg.selector);
7685 put_smstate(u32, buf, 0x7f80, seg.base);
7686 put_smstate(u32, buf, 0x7f7c, seg.limit);
7687 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7689 kvm_x86_ops->get_gdt(vcpu, &dt);
7690 put_smstate(u32, buf, 0x7f74, dt.address);
7691 put_smstate(u32, buf, 0x7f70, dt.size);
7693 kvm_x86_ops->get_idt(vcpu, &dt);
7694 put_smstate(u32, buf, 0x7f58, dt.address);
7695 put_smstate(u32, buf, 0x7f54, dt.size);
7697 for (i = 0; i < 6; i++)
7698 enter_smm_save_seg_32(vcpu, buf, i);
7700 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7703 put_smstate(u32, buf, 0x7efc, 0x00020000);
7704 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7707 #ifdef CONFIG_X86_64
7708 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7711 struct kvm_segment seg;
7715 for (i = 0; i < 16; i++)
7716 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7718 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7719 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7721 kvm_get_dr(vcpu, 6, &val);
7722 put_smstate(u64, buf, 0x7f68, val);
7723 kvm_get_dr(vcpu, 7, &val);
7724 put_smstate(u64, buf, 0x7f60, val);
7726 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7727 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7728 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7730 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7733 put_smstate(u32, buf, 0x7efc, 0x00020064);
7735 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7737 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7738 put_smstate(u16, buf, 0x7e90, seg.selector);
7739 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7740 put_smstate(u32, buf, 0x7e94, seg.limit);
7741 put_smstate(u64, buf, 0x7e98, seg.base);
7743 kvm_x86_ops->get_idt(vcpu, &dt);
7744 put_smstate(u32, buf, 0x7e84, dt.size);
7745 put_smstate(u64, buf, 0x7e88, dt.address);
7747 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7748 put_smstate(u16, buf, 0x7e70, seg.selector);
7749 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7750 put_smstate(u32, buf, 0x7e74, seg.limit);
7751 put_smstate(u64, buf, 0x7e78, seg.base);
7753 kvm_x86_ops->get_gdt(vcpu, &dt);
7754 put_smstate(u32, buf, 0x7e64, dt.size);
7755 put_smstate(u64, buf, 0x7e68, dt.address);
7757 for (i = 0; i < 6; i++)
7758 enter_smm_save_seg_64(vcpu, buf, i);
7762 static void enter_smm(struct kvm_vcpu *vcpu)
7764 struct kvm_segment cs, ds;
7769 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7770 memset(buf, 0, 512);
7771 #ifdef CONFIG_X86_64
7772 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7773 enter_smm_save_state_64(vcpu, buf);
7776 enter_smm_save_state_32(vcpu, buf);
7779 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7780 * vCPU state (e.g. leave guest mode) after we've saved the state into
7781 * the SMM state-save area.
7783 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7785 vcpu->arch.hflags |= HF_SMM_MASK;
7786 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7788 if (kvm_x86_ops->get_nmi_mask(vcpu))
7789 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7791 kvm_x86_ops->set_nmi_mask(vcpu, true);
7793 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7794 kvm_rip_write(vcpu, 0x8000);
7796 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7797 kvm_x86_ops->set_cr0(vcpu, cr0);
7798 vcpu->arch.cr0 = cr0;
7800 kvm_x86_ops->set_cr4(vcpu, 0);
7802 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7803 dt.address = dt.size = 0;
7804 kvm_x86_ops->set_idt(vcpu, &dt);
7806 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7808 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7809 cs.base = vcpu->arch.smbase;
7814 cs.limit = ds.limit = 0xffffffff;
7815 cs.type = ds.type = 0x3;
7816 cs.dpl = ds.dpl = 0;
7821 cs.avl = ds.avl = 0;
7822 cs.present = ds.present = 1;
7823 cs.unusable = ds.unusable = 0;
7824 cs.padding = ds.padding = 0;
7826 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7827 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7828 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7829 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7830 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7831 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7833 #ifdef CONFIG_X86_64
7834 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7835 kvm_x86_ops->set_efer(vcpu, 0);
7838 kvm_update_cpuid(vcpu);
7839 kvm_mmu_reset_context(vcpu);
7842 static void process_smi(struct kvm_vcpu *vcpu)
7844 vcpu->arch.smi_pending = true;
7845 kvm_make_request(KVM_REQ_EVENT, vcpu);
7848 void kvm_make_scan_ioapic_request(struct kvm *kvm)
7850 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7853 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
7855 if (!kvm_apic_present(vcpu))
7858 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
7860 if (irqchip_split(vcpu->kvm))
7861 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
7863 if (vcpu->arch.apicv_active)
7864 kvm_x86_ops->sync_pir_to_irr(vcpu);
7865 if (ioapic_in_kernel(vcpu->kvm))
7866 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
7869 if (is_guest_mode(vcpu))
7870 vcpu->arch.load_eoi_exitmap_pending = true;
7872 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7875 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7877 u64 eoi_exit_bitmap[4];
7879 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7882 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7883 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7884 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
7887 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7888 unsigned long start, unsigned long end,
7891 unsigned long apic_address;
7894 * The physical address of apic access page is stored in the VMCS.
7895 * Update it when it becomes invalid.
7897 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7898 if (start <= apic_address && apic_address < end)
7899 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7904 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7906 struct page *page = NULL;
7908 if (!lapic_in_kernel(vcpu))
7911 if (!kvm_x86_ops->set_apic_access_page_addr)
7914 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7915 if (is_error_page(page))
7917 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7920 * Do not pin apic access page in memory, the MMU notifier
7921 * will call us again if it is migrated or swapped out.
7925 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7927 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7929 smp_send_reschedule(vcpu->cpu);
7931 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7934 * Returns 1 to let vcpu_run() continue the guest execution loop without
7935 * exiting to the userspace. Otherwise, the value will be returned to the
7938 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
7942 dm_request_for_irq_injection(vcpu) &&
7943 kvm_cpu_accept_dm_intr(vcpu);
7945 bool req_immediate_exit = false;
7947 if (kvm_request_pending(vcpu)) {
7948 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7949 kvm_x86_ops->get_vmcs12_pages(vcpu);
7950 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
7951 kvm_mmu_unload(vcpu);
7952 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
7953 __kvm_migrate_timers(vcpu);
7954 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7955 kvm_gen_update_masterclock(vcpu->kvm);
7956 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7957 kvm_gen_kvmclock_update(vcpu);
7958 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7959 r = kvm_guest_time_update(vcpu);
7963 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
7964 kvm_mmu_sync_roots(vcpu);
7965 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7966 kvm_mmu_load_cr3(vcpu);
7967 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
7968 kvm_vcpu_flush_tlb(vcpu, true);
7969 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
7970 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
7974 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
7975 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7976 vcpu->mmio_needed = 0;
7980 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7981 /* Page is swapped out. Do synthetic halt */
7982 vcpu->arch.apf.halted = true;
7986 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7987 record_steal_time(vcpu);
7988 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7990 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7992 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7993 kvm_pmu_handle_event(vcpu);
7994 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7995 kvm_pmu_deliver_pmi(vcpu);
7996 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7997 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7998 if (test_bit(vcpu->arch.pending_ioapic_eoi,
7999 vcpu->arch.ioapic_handled_vectors)) {
8000 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8001 vcpu->run->eoi.vector =
8002 vcpu->arch.pending_ioapic_eoi;
8007 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8008 vcpu_scan_ioapic(vcpu);
8009 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8010 vcpu_load_eoi_exitmap(vcpu);
8011 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8012 kvm_vcpu_reload_apic_access_page(vcpu);
8013 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8014 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8015 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8019 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8020 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8021 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8025 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8026 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8027 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8033 * KVM_REQ_HV_STIMER has to be processed after
8034 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8035 * depend on the guest clock being up-to-date
8037 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8038 kvm_hv_process_stimers(vcpu);
8041 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8042 ++vcpu->stat.req_event;
8043 kvm_apic_accept_events(vcpu);
8044 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8049 if (inject_pending_event(vcpu, req_int_win) != 0)
8050 req_immediate_exit = true;
8052 /* Enable SMI/NMI/IRQ window open exits if needed.
8054 * SMIs have three cases:
8055 * 1) They can be nested, and then there is nothing to
8056 * do here because RSM will cause a vmexit anyway.
8057 * 2) There is an ISA-specific reason why SMI cannot be
8058 * injected, and the moment when this changes can be
8060 * 3) Or the SMI can be pending because
8061 * inject_pending_event has completed the injection
8062 * of an IRQ or NMI from the previous vmexit, and
8063 * then we request an immediate exit to inject the
8066 if (vcpu->arch.smi_pending && !is_smm(vcpu))
8067 if (!kvm_x86_ops->enable_smi_window(vcpu))
8068 req_immediate_exit = true;
8069 if (vcpu->arch.nmi_pending)
8070 kvm_x86_ops->enable_nmi_window(vcpu);
8071 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8072 kvm_x86_ops->enable_irq_window(vcpu);
8073 WARN_ON(vcpu->arch.exception.pending);
8076 if (kvm_lapic_enabled(vcpu)) {
8077 update_cr8_intercept(vcpu);
8078 kvm_lapic_sync_to_vapic(vcpu);
8082 r = kvm_mmu_reload(vcpu);
8084 goto cancel_injection;
8089 kvm_x86_ops->prepare_guest_switch(vcpu);
8092 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8093 * IPI are then delayed after guest entry, which ensures that they
8094 * result in virtual interrupt delivery.
8096 local_irq_disable();
8097 vcpu->mode = IN_GUEST_MODE;
8099 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8102 * 1) We should set ->mode before checking ->requests. Please see
8103 * the comment in kvm_vcpu_exiting_guest_mode().
8105 * 2) For APICv, we should set ->mode before checking PID.ON. This
8106 * pairs with the memory barrier implicit in pi_test_and_set_on
8107 * (see vmx_deliver_posted_interrupt).
8109 * 3) This also orders the write to mode from any reads to the page
8110 * tables done while the VCPU is running. Please see the comment
8111 * in kvm_flush_remote_tlbs.
8113 smp_mb__after_srcu_read_unlock();
8116 * This handles the case where a posted interrupt was
8117 * notified with kvm_vcpu_kick.
8119 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8120 kvm_x86_ops->sync_pir_to_irr(vcpu);
8122 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
8123 || need_resched() || signal_pending(current)) {
8124 vcpu->mode = OUTSIDE_GUEST_MODE;
8128 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8130 goto cancel_injection;
8133 if (req_immediate_exit) {
8134 kvm_make_request(KVM_REQ_EVENT, vcpu);
8135 kvm_x86_ops->request_immediate_exit(vcpu);
8138 trace_kvm_entry(vcpu->vcpu_id);
8139 guest_enter_irqoff();
8141 /* The preempt notifier should have taken care of the FPU already. */
8142 WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD));
8144 if (unlikely(vcpu->arch.switch_db_regs)) {
8146 set_debugreg(vcpu->arch.eff_db[0], 0);
8147 set_debugreg(vcpu->arch.eff_db[1], 1);
8148 set_debugreg(vcpu->arch.eff_db[2], 2);
8149 set_debugreg(vcpu->arch.eff_db[3], 3);
8150 set_debugreg(vcpu->arch.dr6, 6);
8151 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8154 kvm_x86_ops->run(vcpu);
8157 * Do this here before restoring debug registers on the host. And
8158 * since we do this before handling the vmexit, a DR access vmexit
8159 * can (a) read the correct value of the debug registers, (b) set
8160 * KVM_DEBUGREG_WONT_EXIT again.
8162 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8163 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8164 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
8165 kvm_update_dr0123(vcpu);
8166 kvm_update_dr6(vcpu);
8167 kvm_update_dr7(vcpu);
8168 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8172 * If the guest has used debug registers, at least dr7
8173 * will be disabled while returning to the host.
8174 * If we don't have active breakpoints in the host, we don't
8175 * care about the messed up debug address registers. But if
8176 * we have some of them active, restore the old state.
8178 if (hw_breakpoint_active())
8179 hw_breakpoint_restore();
8181 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8183 vcpu->mode = OUTSIDE_GUEST_MODE;
8186 kvm_x86_ops->handle_exit_irqoff(vcpu);
8189 * Consume any pending interrupts, including the possible source of
8190 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8191 * An instruction is required after local_irq_enable() to fully unblock
8192 * interrupts on processors that implement an interrupt shadow, the
8193 * stat.exits increment will do nicely.
8195 kvm_before_interrupt(vcpu);
8198 local_irq_disable();
8199 kvm_after_interrupt(vcpu);
8201 guest_exit_irqoff();
8202 if (lapic_in_kernel(vcpu)) {
8203 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8204 if (delta != S64_MIN) {
8205 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8206 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8213 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8216 * Profile KVM exit RIPs:
8218 if (unlikely(prof_on == KVM_PROFILING)) {
8219 unsigned long rip = kvm_rip_read(vcpu);
8220 profile_hit(KVM_PROFILING, (void *)rip);
8223 if (unlikely(vcpu->arch.tsc_always_catchup))
8224 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8226 if (vcpu->arch.apic_attention)
8227 kvm_lapic_sync_from_vapic(vcpu);
8229 vcpu->arch.gpa_available = false;
8230 r = kvm_x86_ops->handle_exit(vcpu);
8234 kvm_x86_ops->cancel_injection(vcpu);
8235 if (unlikely(vcpu->arch.apic_attention))
8236 kvm_lapic_sync_from_vapic(vcpu);
8241 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8243 if (!kvm_arch_vcpu_runnable(vcpu) &&
8244 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
8245 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8246 kvm_vcpu_block(vcpu);
8247 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8249 if (kvm_x86_ops->post_block)
8250 kvm_x86_ops->post_block(vcpu);
8252 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8256 kvm_apic_accept_events(vcpu);
8257 switch(vcpu->arch.mp_state) {
8258 case KVM_MP_STATE_HALTED:
8259 vcpu->arch.pv.pv_unhalted = false;
8260 vcpu->arch.mp_state =
8261 KVM_MP_STATE_RUNNABLE;
8263 case KVM_MP_STATE_RUNNABLE:
8264 vcpu->arch.apf.halted = false;
8266 case KVM_MP_STATE_INIT_RECEIVED:
8275 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8277 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8278 kvm_x86_ops->check_nested_events(vcpu, false);
8280 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8281 !vcpu->arch.apf.halted);
8284 static int vcpu_run(struct kvm_vcpu *vcpu)
8287 struct kvm *kvm = vcpu->kvm;
8289 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8290 vcpu->arch.l1tf_flush_l1d = true;
8293 if (kvm_vcpu_running(vcpu)) {
8294 r = vcpu_enter_guest(vcpu);
8296 r = vcpu_block(kvm, vcpu);
8302 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8303 if (kvm_cpu_has_pending_timer(vcpu))
8304 kvm_inject_pending_timer_irqs(vcpu);
8306 if (dm_request_for_irq_injection(vcpu) &&
8307 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8309 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8310 ++vcpu->stat.request_irq_exits;
8314 kvm_check_async_pf_completion(vcpu);
8316 if (signal_pending(current)) {
8318 vcpu->run->exit_reason = KVM_EXIT_INTR;
8319 ++vcpu->stat.signal_exits;
8322 if (need_resched()) {
8323 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8325 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8329 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8334 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8338 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8339 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8340 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8344 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8346 BUG_ON(!vcpu->arch.pio.count);
8348 return complete_emulated_io(vcpu);
8352 * Implements the following, as a state machine:
8356 * for each mmio piece in the fragment
8364 * for each mmio piece in the fragment
8369 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8371 struct kvm_run *run = vcpu->run;
8372 struct kvm_mmio_fragment *frag;
8375 BUG_ON(!vcpu->mmio_needed);
8377 /* Complete previous fragment */
8378 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8379 len = min(8u, frag->len);
8380 if (!vcpu->mmio_is_write)
8381 memcpy(frag->data, run->mmio.data, len);
8383 if (frag->len <= 8) {
8384 /* Switch to the next fragment. */
8386 vcpu->mmio_cur_fragment++;
8388 /* Go forward to the next mmio piece. */
8394 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8395 vcpu->mmio_needed = 0;
8397 /* FIXME: return into emulator if single-stepping. */
8398 if (vcpu->mmio_is_write)
8400 vcpu->mmio_read_completed = 1;
8401 return complete_emulated_io(vcpu);
8404 run->exit_reason = KVM_EXIT_MMIO;
8405 run->mmio.phys_addr = frag->gpa;
8406 if (vcpu->mmio_is_write)
8407 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8408 run->mmio.len = min(8u, frag->len);
8409 run->mmio.is_write = vcpu->mmio_is_write;
8410 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8414 /* Swap (qemu) user FPU context for the guest FPU context. */
8415 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8419 copy_fpregs_to_fpstate(vcpu->arch.user_fpu);
8420 /* PKRU is separately restored in kvm_x86_ops->run. */
8421 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8422 ~XFEATURE_MASK_PKRU);
8424 fpregs_mark_activate();
8430 /* When vcpu_run ends, restore user space FPU context. */
8431 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8435 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
8436 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8438 fpregs_mark_activate();
8441 ++vcpu->stat.fpu_reload;
8445 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8450 kvm_sigset_activate(vcpu);
8451 kvm_load_guest_fpu(vcpu);
8453 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8454 if (kvm_run->immediate_exit) {
8458 kvm_vcpu_block(vcpu);
8459 kvm_apic_accept_events(vcpu);
8460 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8462 if (signal_pending(current)) {
8464 vcpu->run->exit_reason = KVM_EXIT_INTR;
8465 ++vcpu->stat.signal_exits;
8470 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8475 if (vcpu->run->kvm_dirty_regs) {
8476 r = sync_regs(vcpu);
8481 /* re-sync apic's tpr */
8482 if (!lapic_in_kernel(vcpu)) {
8483 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8489 if (unlikely(vcpu->arch.complete_userspace_io)) {
8490 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8491 vcpu->arch.complete_userspace_io = NULL;
8496 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8498 if (kvm_run->immediate_exit)
8504 kvm_put_guest_fpu(vcpu);
8505 if (vcpu->run->kvm_valid_regs)
8507 post_kvm_run_save(vcpu);
8508 kvm_sigset_deactivate(vcpu);
8514 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8516 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8518 * We are here if userspace calls get_regs() in the middle of
8519 * instruction emulation. Registers state needs to be copied
8520 * back from emulation context to vcpu. Userspace shouldn't do
8521 * that usually, but some bad designed PV devices (vmware
8522 * backdoor interface) need this to work
8524 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8525 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8527 regs->rax = kvm_rax_read(vcpu);
8528 regs->rbx = kvm_rbx_read(vcpu);
8529 regs->rcx = kvm_rcx_read(vcpu);
8530 regs->rdx = kvm_rdx_read(vcpu);
8531 regs->rsi = kvm_rsi_read(vcpu);
8532 regs->rdi = kvm_rdi_read(vcpu);
8533 regs->rsp = kvm_rsp_read(vcpu);
8534 regs->rbp = kvm_rbp_read(vcpu);
8535 #ifdef CONFIG_X86_64
8536 regs->r8 = kvm_r8_read(vcpu);
8537 regs->r9 = kvm_r9_read(vcpu);
8538 regs->r10 = kvm_r10_read(vcpu);
8539 regs->r11 = kvm_r11_read(vcpu);
8540 regs->r12 = kvm_r12_read(vcpu);
8541 regs->r13 = kvm_r13_read(vcpu);
8542 regs->r14 = kvm_r14_read(vcpu);
8543 regs->r15 = kvm_r15_read(vcpu);
8546 regs->rip = kvm_rip_read(vcpu);
8547 regs->rflags = kvm_get_rflags(vcpu);
8550 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8553 __get_regs(vcpu, regs);
8558 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8560 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8561 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8563 kvm_rax_write(vcpu, regs->rax);
8564 kvm_rbx_write(vcpu, regs->rbx);
8565 kvm_rcx_write(vcpu, regs->rcx);
8566 kvm_rdx_write(vcpu, regs->rdx);
8567 kvm_rsi_write(vcpu, regs->rsi);
8568 kvm_rdi_write(vcpu, regs->rdi);
8569 kvm_rsp_write(vcpu, regs->rsp);
8570 kvm_rbp_write(vcpu, regs->rbp);
8571 #ifdef CONFIG_X86_64
8572 kvm_r8_write(vcpu, regs->r8);
8573 kvm_r9_write(vcpu, regs->r9);
8574 kvm_r10_write(vcpu, regs->r10);
8575 kvm_r11_write(vcpu, regs->r11);
8576 kvm_r12_write(vcpu, regs->r12);
8577 kvm_r13_write(vcpu, regs->r13);
8578 kvm_r14_write(vcpu, regs->r14);
8579 kvm_r15_write(vcpu, regs->r15);
8582 kvm_rip_write(vcpu, regs->rip);
8583 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8585 vcpu->arch.exception.pending = false;
8587 kvm_make_request(KVM_REQ_EVENT, vcpu);
8590 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8593 __set_regs(vcpu, regs);
8598 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8600 struct kvm_segment cs;
8602 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8606 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8608 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8612 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8613 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8614 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8615 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8616 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8617 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8619 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8620 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8622 kvm_x86_ops->get_idt(vcpu, &dt);
8623 sregs->idt.limit = dt.size;
8624 sregs->idt.base = dt.address;
8625 kvm_x86_ops->get_gdt(vcpu, &dt);
8626 sregs->gdt.limit = dt.size;
8627 sregs->gdt.base = dt.address;
8629 sregs->cr0 = kvm_read_cr0(vcpu);
8630 sregs->cr2 = vcpu->arch.cr2;
8631 sregs->cr3 = kvm_read_cr3(vcpu);
8632 sregs->cr4 = kvm_read_cr4(vcpu);
8633 sregs->cr8 = kvm_get_cr8(vcpu);
8634 sregs->efer = vcpu->arch.efer;
8635 sregs->apic_base = kvm_get_apic_base(vcpu);
8637 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8639 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8640 set_bit(vcpu->arch.interrupt.nr,
8641 (unsigned long *)sregs->interrupt_bitmap);
8644 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8645 struct kvm_sregs *sregs)
8648 __get_sregs(vcpu, sregs);
8653 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8654 struct kvm_mp_state *mp_state)
8658 kvm_apic_accept_events(vcpu);
8659 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8660 vcpu->arch.pv.pv_unhalted)
8661 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8663 mp_state->mp_state = vcpu->arch.mp_state;
8669 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8670 struct kvm_mp_state *mp_state)
8676 if (!lapic_in_kernel(vcpu) &&
8677 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8680 /* INITs are latched while in SMM */
8681 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8682 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8683 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8686 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8687 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8688 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8690 vcpu->arch.mp_state = mp_state->mp_state;
8691 kvm_make_request(KVM_REQ_EVENT, vcpu);
8699 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8700 int reason, bool has_error_code, u32 error_code)
8702 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8705 init_emulate_ctxt(vcpu);
8707 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8708 has_error_code, error_code);
8710 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8711 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
8712 vcpu->run->internal.ndata = 0;
8716 kvm_rip_write(vcpu, ctxt->eip);
8717 kvm_set_rflags(vcpu, ctxt->eflags);
8718 kvm_make_request(KVM_REQ_EVENT, vcpu);
8721 EXPORT_SYMBOL_GPL(kvm_task_switch);
8723 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8725 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8727 * When EFER.LME and CR0.PG are set, the processor is in
8728 * 64-bit mode (though maybe in a 32-bit code segment).
8729 * CR4.PAE and EFER.LMA must be set.
8731 if (!(sregs->cr4 & X86_CR4_PAE)
8732 || !(sregs->efer & EFER_LMA))
8736 * Not in 64-bit mode: EFER.LMA is clear and the code
8737 * segment cannot be 64-bit.
8739 if (sregs->efer & EFER_LMA || sregs->cs.l)
8743 return kvm_valid_cr4(vcpu, sregs->cr4);
8746 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8748 struct msr_data apic_base_msr;
8749 int mmu_reset_needed = 0;
8750 int cpuid_update_needed = 0;
8751 int pending_vec, max_bits, idx;
8755 if (kvm_valid_sregs(vcpu, sregs))
8758 apic_base_msr.data = sregs->apic_base;
8759 apic_base_msr.host_initiated = true;
8760 if (kvm_set_apic_base(vcpu, &apic_base_msr))
8763 dt.size = sregs->idt.limit;
8764 dt.address = sregs->idt.base;
8765 kvm_x86_ops->set_idt(vcpu, &dt);
8766 dt.size = sregs->gdt.limit;
8767 dt.address = sregs->gdt.base;
8768 kvm_x86_ops->set_gdt(vcpu, &dt);
8770 vcpu->arch.cr2 = sregs->cr2;
8771 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
8772 vcpu->arch.cr3 = sregs->cr3;
8773 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
8775 kvm_set_cr8(vcpu, sregs->cr8);
8777 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
8778 kvm_x86_ops->set_efer(vcpu, sregs->efer);
8780 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
8781 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
8782 vcpu->arch.cr0 = sregs->cr0;
8784 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
8785 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8786 (X86_CR4_OSXSAVE | X86_CR4_PKE));
8787 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
8788 if (cpuid_update_needed)
8789 kvm_update_cpuid(vcpu);
8791 idx = srcu_read_lock(&vcpu->kvm->srcu);
8792 if (is_pae_paging(vcpu)) {
8793 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
8794 mmu_reset_needed = 1;
8796 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8798 if (mmu_reset_needed)
8799 kvm_mmu_reset_context(vcpu);
8801 max_bits = KVM_NR_INTERRUPTS;
8802 pending_vec = find_first_bit(
8803 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8804 if (pending_vec < max_bits) {
8805 kvm_queue_interrupt(vcpu, pending_vec, false);
8806 pr_debug("Set back pending irq %d\n", pending_vec);
8809 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8810 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8811 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8812 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8813 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8814 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8816 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8817 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8819 update_cr8_intercept(vcpu);
8821 /* Older userspace won't unhalt the vcpu on reset. */
8822 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
8823 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
8825 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8827 kvm_make_request(KVM_REQ_EVENT, vcpu);
8834 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8835 struct kvm_sregs *sregs)
8840 ret = __set_sregs(vcpu, sregs);
8845 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8846 struct kvm_guest_debug *dbg)
8848 unsigned long rflags;
8853 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8855 if (vcpu->arch.exception.pending)
8857 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8858 kvm_queue_exception(vcpu, DB_VECTOR);
8860 kvm_queue_exception(vcpu, BP_VECTOR);
8864 * Read rflags as long as potentially injected trace flags are still
8867 rflags = kvm_get_rflags(vcpu);
8869 vcpu->guest_debug = dbg->control;
8870 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8871 vcpu->guest_debug = 0;
8873 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
8874 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8875 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
8876 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
8878 for (i = 0; i < KVM_NR_DB_REGS; i++)
8879 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
8881 kvm_update_dr7(vcpu);
8883 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8884 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8885 get_segment_base(vcpu, VCPU_SREG_CS);
8888 * Trigger an rflags update that will inject or remove the trace
8891 kvm_set_rflags(vcpu, rflags);
8893 kvm_x86_ops->update_bp_intercept(vcpu);
8903 * Translate a guest virtual address to a guest physical address.
8905 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8906 struct kvm_translation *tr)
8908 unsigned long vaddr = tr->linear_address;
8914 idx = srcu_read_lock(&vcpu->kvm->srcu);
8915 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
8916 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8917 tr->physical_address = gpa;
8918 tr->valid = gpa != UNMAPPED_GVA;
8926 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8928 struct fxregs_state *fxsave;
8932 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8933 memcpy(fpu->fpr, fxsave->st_space, 128);
8934 fpu->fcw = fxsave->cwd;
8935 fpu->fsw = fxsave->swd;
8936 fpu->ftwx = fxsave->twd;
8937 fpu->last_opcode = fxsave->fop;
8938 fpu->last_ip = fxsave->rip;
8939 fpu->last_dp = fxsave->rdp;
8940 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
8946 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8948 struct fxregs_state *fxsave;
8952 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8954 memcpy(fxsave->st_space, fpu->fpr, 128);
8955 fxsave->cwd = fpu->fcw;
8956 fxsave->swd = fpu->fsw;
8957 fxsave->twd = fpu->ftwx;
8958 fxsave->fop = fpu->last_opcode;
8959 fxsave->rip = fpu->last_ip;
8960 fxsave->rdp = fpu->last_dp;
8961 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
8967 static void store_regs(struct kvm_vcpu *vcpu)
8969 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8971 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8972 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8974 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8975 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8977 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8978 kvm_vcpu_ioctl_x86_get_vcpu_events(
8979 vcpu, &vcpu->run->s.regs.events);
8982 static int sync_regs(struct kvm_vcpu *vcpu)
8984 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8987 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8988 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8989 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8991 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8992 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8994 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8996 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8997 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8998 vcpu, &vcpu->run->s.regs.events))
9000 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9006 static void fx_init(struct kvm_vcpu *vcpu)
9008 fpstate_init(&vcpu->arch.guest_fpu->state);
9009 if (boot_cpu_has(X86_FEATURE_XSAVES))
9010 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9011 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9014 * Ensure guest xcr0 is valid for loading
9016 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9018 vcpu->arch.cr0 |= X86_CR0_ET;
9021 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
9023 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
9025 kvmclock_reset(vcpu);
9027 kvm_x86_ops->vcpu_free(vcpu);
9028 free_cpumask_var(wbinvd_dirty_mask);
9031 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
9034 struct kvm_vcpu *vcpu;
9036 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9037 printk_once(KERN_WARNING
9038 "kvm: SMP vm created on host with unstable TSC; "
9039 "guest TSC will not be reliable\n");
9041 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
9046 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
9048 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9049 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9050 kvm_vcpu_mtrr_init(vcpu);
9052 kvm_vcpu_reset(vcpu, false);
9053 kvm_init_mmu(vcpu, false);
9058 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9060 struct msr_data msr;
9061 struct kvm *kvm = vcpu->kvm;
9063 kvm_hv_vcpu_postcreate(vcpu);
9065 if (mutex_lock_killable(&vcpu->mutex))
9069 msr.index = MSR_IA32_TSC;
9070 msr.host_initiated = true;
9071 kvm_write_tsc(vcpu, &msr);
9074 /* poll control enabled by default */
9075 vcpu->arch.msr_kvm_poll_control = 1;
9077 mutex_unlock(&vcpu->mutex);
9079 if (!kvmclock_periodic_sync)
9082 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9083 KVMCLOCK_SYNC_PERIOD);
9086 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9088 vcpu->arch.apf.msr_val = 0;
9091 kvm_mmu_unload(vcpu);
9094 kvm_x86_ops->vcpu_free(vcpu);
9097 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9099 kvm_lapic_reset(vcpu, init_event);
9101 vcpu->arch.hflags = 0;
9103 vcpu->arch.smi_pending = 0;
9104 vcpu->arch.smi_count = 0;
9105 atomic_set(&vcpu->arch.nmi_queued, 0);
9106 vcpu->arch.nmi_pending = 0;
9107 vcpu->arch.nmi_injected = false;
9108 kvm_clear_interrupt_queue(vcpu);
9109 kvm_clear_exception_queue(vcpu);
9110 vcpu->arch.exception.pending = false;
9112 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9113 kvm_update_dr0123(vcpu);
9114 vcpu->arch.dr6 = DR6_INIT;
9115 kvm_update_dr6(vcpu);
9116 vcpu->arch.dr7 = DR7_FIXED_1;
9117 kvm_update_dr7(vcpu);
9121 kvm_make_request(KVM_REQ_EVENT, vcpu);
9122 vcpu->arch.apf.msr_val = 0;
9123 vcpu->arch.st.msr_val = 0;
9125 kvmclock_reset(vcpu);
9127 kvm_clear_async_pf_completion_queue(vcpu);
9128 kvm_async_pf_hash_reset(vcpu);
9129 vcpu->arch.apf.halted = false;
9131 if (kvm_mpx_supported()) {
9132 void *mpx_state_buffer;
9135 * To avoid have the INIT path from kvm_apic_has_events() that be
9136 * called with loaded FPU and does not let userspace fix the state.
9139 kvm_put_guest_fpu(vcpu);
9140 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9142 if (mpx_state_buffer)
9143 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9144 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9146 if (mpx_state_buffer)
9147 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9149 kvm_load_guest_fpu(vcpu);
9153 kvm_pmu_reset(vcpu);
9154 vcpu->arch.smbase = 0x30000;
9156 vcpu->arch.msr_misc_features_enables = 0;
9158 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9161 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9162 vcpu->arch.regs_avail = ~0;
9163 vcpu->arch.regs_dirty = ~0;
9165 vcpu->arch.ia32_xss = 0;
9167 kvm_x86_ops->vcpu_reset(vcpu, init_event);
9170 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9172 struct kvm_segment cs;
9174 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9175 cs.selector = vector << 8;
9176 cs.base = vector << 12;
9177 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9178 kvm_rip_write(vcpu, 0);
9181 int kvm_arch_hardware_enable(void)
9184 struct kvm_vcpu *vcpu;
9189 bool stable, backwards_tsc = false;
9191 kvm_shared_msr_cpu_online();
9192 ret = kvm_x86_ops->hardware_enable();
9196 local_tsc = rdtsc();
9197 stable = !kvm_check_tsc_unstable();
9198 list_for_each_entry(kvm, &vm_list, vm_list) {
9199 kvm_for_each_vcpu(i, vcpu, kvm) {
9200 if (!stable && vcpu->cpu == smp_processor_id())
9201 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9202 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9203 backwards_tsc = true;
9204 if (vcpu->arch.last_host_tsc > max_tsc)
9205 max_tsc = vcpu->arch.last_host_tsc;
9211 * Sometimes, even reliable TSCs go backwards. This happens on
9212 * platforms that reset TSC during suspend or hibernate actions, but
9213 * maintain synchronization. We must compensate. Fortunately, we can
9214 * detect that condition here, which happens early in CPU bringup,
9215 * before any KVM threads can be running. Unfortunately, we can't
9216 * bring the TSCs fully up to date with real time, as we aren't yet far
9217 * enough into CPU bringup that we know how much real time has actually
9218 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9219 * variables that haven't been updated yet.
9221 * So we simply find the maximum observed TSC above, then record the
9222 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9223 * the adjustment will be applied. Note that we accumulate
9224 * adjustments, in case multiple suspend cycles happen before some VCPU
9225 * gets a chance to run again. In the event that no KVM threads get a
9226 * chance to run, we will miss the entire elapsed period, as we'll have
9227 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9228 * loose cycle time. This isn't too big a deal, since the loss will be
9229 * uniform across all VCPUs (not to mention the scenario is extremely
9230 * unlikely). It is possible that a second hibernate recovery happens
9231 * much faster than a first, causing the observed TSC here to be
9232 * smaller; this would require additional padding adjustment, which is
9233 * why we set last_host_tsc to the local tsc observed here.
9235 * N.B. - this code below runs only on platforms with reliable TSC,
9236 * as that is the only way backwards_tsc is set above. Also note
9237 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9238 * have the same delta_cyc adjustment applied if backwards_tsc
9239 * is detected. Note further, this adjustment is only done once,
9240 * as we reset last_host_tsc on all VCPUs to stop this from being
9241 * called multiple times (one for each physical CPU bringup).
9243 * Platforms with unreliable TSCs don't have to deal with this, they
9244 * will be compensated by the logic in vcpu_load, which sets the TSC to
9245 * catchup mode. This will catchup all VCPUs to real time, but cannot
9246 * guarantee that they stay in perfect synchronization.
9248 if (backwards_tsc) {
9249 u64 delta_cyc = max_tsc - local_tsc;
9250 list_for_each_entry(kvm, &vm_list, vm_list) {
9251 kvm->arch.backwards_tsc_observed = true;
9252 kvm_for_each_vcpu(i, vcpu, kvm) {
9253 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9254 vcpu->arch.last_host_tsc = local_tsc;
9255 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9259 * We have to disable TSC offset matching.. if you were
9260 * booting a VM while issuing an S4 host suspend....
9261 * you may have some problem. Solving this issue is
9262 * left as an exercise to the reader.
9264 kvm->arch.last_tsc_nsec = 0;
9265 kvm->arch.last_tsc_write = 0;
9272 void kvm_arch_hardware_disable(void)
9274 kvm_x86_ops->hardware_disable();
9275 drop_user_return_notifiers();
9278 int kvm_arch_hardware_setup(void)
9282 r = kvm_x86_ops->hardware_setup();
9286 if (kvm_has_tsc_control) {
9288 * Make sure the user can only configure tsc_khz values that
9289 * fit into a signed integer.
9290 * A min value is not calculated because it will always
9291 * be 1 on all machines.
9293 u64 max = min(0x7fffffffULL,
9294 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9295 kvm_max_guest_tsc_khz = max;
9297 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9300 kvm_init_msr_list();
9304 void kvm_arch_hardware_unsetup(void)
9306 kvm_x86_ops->hardware_unsetup();
9309 int kvm_arch_check_processor_compat(void)
9311 return kvm_x86_ops->check_processor_compatibility();
9314 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9316 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9318 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9320 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9322 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9325 struct static_key kvm_no_apic_vcpu __read_mostly;
9326 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9328 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9333 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9334 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9335 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9337 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9339 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9344 vcpu->arch.pio_data = page_address(page);
9346 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9348 r = kvm_mmu_create(vcpu);
9350 goto fail_free_pio_data;
9352 if (irqchip_in_kernel(vcpu->kvm)) {
9353 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9354 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9356 goto fail_mmu_destroy;
9358 static_key_slow_inc(&kvm_no_apic_vcpu);
9360 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9361 GFP_KERNEL_ACCOUNT);
9362 if (!vcpu->arch.mce_banks) {
9364 goto fail_free_lapic;
9366 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9368 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9369 GFP_KERNEL_ACCOUNT)) {
9371 goto fail_free_mce_banks;
9376 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9378 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9380 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9382 kvm_async_pf_hash_reset(vcpu);
9385 vcpu->arch.pending_external_vector = -1;
9386 vcpu->arch.preempted_in_kernel = false;
9388 kvm_hv_vcpu_init(vcpu);
9392 fail_free_mce_banks:
9393 kfree(vcpu->arch.mce_banks);
9395 kvm_free_lapic(vcpu);
9397 kvm_mmu_destroy(vcpu);
9399 free_page((unsigned long)vcpu->arch.pio_data);
9404 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9408 kvm_hv_vcpu_uninit(vcpu);
9409 kvm_pmu_destroy(vcpu);
9410 kfree(vcpu->arch.mce_banks);
9411 kvm_free_lapic(vcpu);
9412 idx = srcu_read_lock(&vcpu->kvm->srcu);
9413 kvm_mmu_destroy(vcpu);
9414 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9415 free_page((unsigned long)vcpu->arch.pio_data);
9416 if (!lapic_in_kernel(vcpu))
9417 static_key_slow_dec(&kvm_no_apic_vcpu);
9420 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9422 vcpu->arch.l1tf_flush_l1d = true;
9423 kvm_x86_ops->sched_in(vcpu, cpu);
9426 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9431 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9432 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9433 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9434 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9435 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9437 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9438 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9439 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9440 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9441 &kvm->arch.irq_sources_bitmap);
9443 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9444 mutex_init(&kvm->arch.apic_map_lock);
9445 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9447 kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
9448 pvclock_update_vm_gtod_copy(kvm);
9450 kvm->arch.guest_can_read_msr_platform_info = true;
9452 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9453 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9455 kvm_hv_init_vm(kvm);
9456 kvm_page_track_init(kvm);
9457 kvm_mmu_init_vm(kvm);
9459 return kvm_x86_ops->vm_init(kvm);
9462 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9465 kvm_mmu_unload(vcpu);
9469 static void kvm_free_vcpus(struct kvm *kvm)
9472 struct kvm_vcpu *vcpu;
9475 * Unpin any mmu pages first.
9477 kvm_for_each_vcpu(i, vcpu, kvm) {
9478 kvm_clear_async_pf_completion_queue(vcpu);
9479 kvm_unload_vcpu_mmu(vcpu);
9481 kvm_for_each_vcpu(i, vcpu, kvm)
9482 kvm_arch_vcpu_free(vcpu);
9484 mutex_lock(&kvm->lock);
9485 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9486 kvm->vcpus[i] = NULL;
9488 atomic_set(&kvm->online_vcpus, 0);
9489 mutex_unlock(&kvm->lock);
9492 void kvm_arch_sync_events(struct kvm *kvm)
9494 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9495 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9499 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9503 struct kvm_memslots *slots = kvm_memslots(kvm);
9504 struct kvm_memory_slot *slot, old;
9506 /* Called with kvm->slots_lock held. */
9507 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9510 slot = id_to_memslot(slots, id);
9516 * MAP_SHARED to prevent internal slot pages from being moved
9519 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9520 MAP_SHARED | MAP_ANONYMOUS, 0);
9521 if (IS_ERR((void *)hva))
9522 return PTR_ERR((void *)hva);
9531 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9532 struct kvm_userspace_memory_region m;
9534 m.slot = id | (i << 16);
9536 m.guest_phys_addr = gpa;
9537 m.userspace_addr = hva;
9538 m.memory_size = size;
9539 r = __kvm_set_memory_region(kvm, &m);
9545 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
9549 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9551 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9555 mutex_lock(&kvm->slots_lock);
9556 r = __x86_set_memory_region(kvm, id, gpa, size);
9557 mutex_unlock(&kvm->slots_lock);
9561 EXPORT_SYMBOL_GPL(x86_set_memory_region);
9563 void kvm_arch_destroy_vm(struct kvm *kvm)
9565 if (current->mm == kvm->mm) {
9567 * Free memory regions allocated on behalf of userspace,
9568 * unless the the memory map has changed due to process exit
9571 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9572 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9573 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9575 if (kvm_x86_ops->vm_destroy)
9576 kvm_x86_ops->vm_destroy(kvm);
9577 kvm_pic_destroy(kvm);
9578 kvm_ioapic_destroy(kvm);
9579 kvm_free_vcpus(kvm);
9580 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9581 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9582 kvm_mmu_uninit_vm(kvm);
9583 kvm_page_track_cleanup(kvm);
9584 kvm_hv_destroy_vm(kvm);
9587 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
9588 struct kvm_memory_slot *dont)
9592 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9593 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
9594 kvfree(free->arch.rmap[i]);
9595 free->arch.rmap[i] = NULL;
9600 if (!dont || free->arch.lpage_info[i - 1] !=
9601 dont->arch.lpage_info[i - 1]) {
9602 kvfree(free->arch.lpage_info[i - 1]);
9603 free->arch.lpage_info[i - 1] = NULL;
9607 kvm_page_track_free_memslot(free, dont);
9610 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9611 unsigned long npages)
9615 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9616 struct kvm_lpage_info *linfo;
9621 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9622 slot->base_gfn, level) + 1;
9624 slot->arch.rmap[i] =
9625 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9626 GFP_KERNEL_ACCOUNT);
9627 if (!slot->arch.rmap[i])
9632 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9636 slot->arch.lpage_info[i - 1] = linfo;
9638 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9639 linfo[0].disallow_lpage = 1;
9640 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9641 linfo[lpages - 1].disallow_lpage = 1;
9642 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9644 * If the gfn and userspace address are not aligned wrt each
9645 * other, or if explicitly asked to, disable large page
9646 * support for this slot
9648 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9649 !kvm_largepages_enabled()) {
9652 for (j = 0; j < lpages; ++j)
9653 linfo[j].disallow_lpage = 1;
9657 if (kvm_page_track_create_memslot(slot, npages))
9663 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9664 kvfree(slot->arch.rmap[i]);
9665 slot->arch.rmap[i] = NULL;
9669 kvfree(slot->arch.lpage_info[i - 1]);
9670 slot->arch.lpage_info[i - 1] = NULL;
9675 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9678 * memslots->generation has been incremented.
9679 * mmio generation may have reached its maximum value.
9681 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9684 int kvm_arch_prepare_memory_region(struct kvm *kvm,
9685 struct kvm_memory_slot *memslot,
9686 const struct kvm_userspace_memory_region *mem,
9687 enum kvm_mr_change change)
9692 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9693 struct kvm_memory_slot *new)
9695 /* Still write protect RO slot */
9696 if (new->flags & KVM_MEM_READONLY) {
9697 kvm_mmu_slot_remove_write_access(kvm, new);
9702 * Call kvm_x86_ops dirty logging hooks when they are valid.
9704 * kvm_x86_ops->slot_disable_log_dirty is called when:
9706 * - KVM_MR_CREATE with dirty logging is disabled
9707 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9709 * The reason is, in case of PML, we need to set D-bit for any slots
9710 * with dirty logging disabled in order to eliminate unnecessary GPA
9711 * logging in PML buffer (and potential PML buffer full VMEXT). This
9712 * guarantees leaving PML enabled during guest's lifetime won't have
9713 * any additional overhead from PML when guest is running with dirty
9714 * logging disabled for memory slots.
9716 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9717 * to dirty logging mode.
9719 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9721 * In case of write protect:
9723 * Write protect all pages for dirty logging.
9725 * All the sptes including the large sptes which point to this
9726 * slot are set to readonly. We can not create any new large
9727 * spte on this slot until the end of the logging.
9729 * See the comments in fast_page_fault().
9731 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9732 if (kvm_x86_ops->slot_enable_log_dirty)
9733 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9735 kvm_mmu_slot_remove_write_access(kvm, new);
9737 if (kvm_x86_ops->slot_disable_log_dirty)
9738 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9742 void kvm_arch_commit_memory_region(struct kvm *kvm,
9743 const struct kvm_userspace_memory_region *mem,
9744 const struct kvm_memory_slot *old,
9745 const struct kvm_memory_slot *new,
9746 enum kvm_mr_change change)
9748 if (!kvm->arch.n_requested_mmu_pages)
9749 kvm_mmu_change_mmu_pages(kvm,
9750 kvm_mmu_calculate_default_mmu_pages(kvm));
9753 * Dirty logging tracks sptes in 4k granularity, meaning that large
9754 * sptes have to be split. If live migration is successful, the guest
9755 * in the source machine will be destroyed and large sptes will be
9756 * created in the destination. However, if the guest continues to run
9757 * in the source machine (for example if live migration fails), small
9758 * sptes will remain around and cause bad performance.
9760 * Scan sptes if dirty logging has been stopped, dropping those
9761 * which can be collapsed into a single large-page spte. Later
9762 * page faults will create the large-page sptes.
9764 * There is no need to do this in any of the following cases:
9765 * CREATE: No dirty mappings will already exist.
9766 * MOVE/DELETE: The old mappings will already have been cleaned up by
9767 * kvm_arch_flush_shadow_memslot()
9769 if (change == KVM_MR_FLAGS_ONLY &&
9770 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9771 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9772 kvm_mmu_zap_collapsible_sptes(kvm, new);
9775 * Set up write protection and/or dirty logging for the new slot.
9777 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9778 * been zapped so no dirty logging staff is needed for old slot. For
9779 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9780 * new and it's also covered when dealing with the new slot.
9782 * FIXME: const-ify all uses of struct kvm_memory_slot.
9784 if (change != KVM_MR_DELETE)
9785 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
9788 void kvm_arch_flush_shadow_all(struct kvm *kvm)
9790 kvm_mmu_zap_all(kvm);
9793 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9794 struct kvm_memory_slot *slot)
9796 kvm_page_track_flush_slot(kvm, slot);
9799 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9801 return (is_guest_mode(vcpu) &&
9802 kvm_x86_ops->guest_apic_has_interrupt &&
9803 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9806 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9808 if (!list_empty_careful(&vcpu->async_pf.done))
9811 if (kvm_apic_has_events(vcpu))
9814 if (vcpu->arch.pv.pv_unhalted)
9817 if (vcpu->arch.exception.pending)
9820 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9821 (vcpu->arch.nmi_pending &&
9822 kvm_x86_ops->nmi_allowed(vcpu)))
9825 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9826 (vcpu->arch.smi_pending && !is_smm(vcpu)))
9829 if (kvm_arch_interrupt_allowed(vcpu) &&
9830 (kvm_cpu_has_interrupt(vcpu) ||
9831 kvm_guest_apic_has_interrupt(vcpu)))
9834 if (kvm_hv_has_stimer_pending(vcpu))
9840 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9842 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
9845 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
9847 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
9850 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9851 kvm_test_request(KVM_REQ_SMI, vcpu) ||
9852 kvm_test_request(KVM_REQ_EVENT, vcpu))
9855 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
9861 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9863 return vcpu->arch.preempted_in_kernel;
9866 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
9868 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
9871 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9873 return kvm_x86_ops->interrupt_allowed(vcpu);
9876 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
9878 if (is_64_bit_mode(vcpu))
9879 return kvm_rip_read(vcpu);
9880 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9881 kvm_rip_read(vcpu));
9883 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
9885 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9887 return kvm_get_linear_rip(vcpu) == linear_rip;
9889 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9891 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9893 unsigned long rflags;
9895 rflags = kvm_x86_ops->get_rflags(vcpu);
9896 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9897 rflags &= ~X86_EFLAGS_TF;
9900 EXPORT_SYMBOL_GPL(kvm_get_rflags);
9902 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9904 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
9905 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
9906 rflags |= X86_EFLAGS_TF;
9907 kvm_x86_ops->set_rflags(vcpu, rflags);
9910 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9912 __kvm_set_rflags(vcpu, rflags);
9913 kvm_make_request(KVM_REQ_EVENT, vcpu);
9915 EXPORT_SYMBOL_GPL(kvm_set_rflags);
9917 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9921 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
9925 r = kvm_mmu_reload(vcpu);
9929 if (!vcpu->arch.mmu->direct_map &&
9930 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
9933 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
9936 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9938 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9941 static inline u32 kvm_async_pf_next_probe(u32 key)
9943 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9946 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9948 u32 key = kvm_async_pf_hash_fn(gfn);
9950 while (vcpu->arch.apf.gfns[key] != ~0)
9951 key = kvm_async_pf_next_probe(key);
9953 vcpu->arch.apf.gfns[key] = gfn;
9956 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9959 u32 key = kvm_async_pf_hash_fn(gfn);
9961 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
9962 (vcpu->arch.apf.gfns[key] != gfn &&
9963 vcpu->arch.apf.gfns[key] != ~0); i++)
9964 key = kvm_async_pf_next_probe(key);
9969 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9971 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9974 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9978 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9980 vcpu->arch.apf.gfns[i] = ~0;
9982 j = kvm_async_pf_next_probe(j);
9983 if (vcpu->arch.apf.gfns[j] == ~0)
9985 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9987 * k lies cyclically in ]i,j]
9989 * |....j i.k.| or |.k..j i...|
9991 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9992 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9997 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
10000 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
10004 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
10007 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10011 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10013 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10016 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10017 (vcpu->arch.apf.send_user_only &&
10018 kvm_x86_ops->get_cpl(vcpu) == 0))
10024 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10026 if (unlikely(!lapic_in_kernel(vcpu) ||
10027 kvm_event_needs_reinjection(vcpu) ||
10028 vcpu->arch.exception.pending))
10031 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10035 * If interrupts are off we cannot even use an artificial
10038 return kvm_x86_ops->interrupt_allowed(vcpu);
10041 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10042 struct kvm_async_pf *work)
10044 struct x86_exception fault;
10046 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
10047 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10049 if (kvm_can_deliver_async_pf(vcpu) &&
10050 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
10051 fault.vector = PF_VECTOR;
10052 fault.error_code_valid = true;
10053 fault.error_code = 0;
10054 fault.nested_page_fault = false;
10055 fault.address = work->arch.token;
10056 fault.async_page_fault = true;
10057 kvm_inject_page_fault(vcpu, &fault);
10060 * It is not possible to deliver a paravirtualized asynchronous
10061 * page fault, but putting the guest in an artificial halt state
10062 * can be beneficial nevertheless: if an interrupt arrives, we
10063 * can deliver it timely and perhaps the guest will schedule
10064 * another process. When the instruction that triggered a page
10065 * fault is retried, hopefully the page will be ready in the host.
10067 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10071 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10072 struct kvm_async_pf *work)
10074 struct x86_exception fault;
10077 if (work->wakeup_all)
10078 work->arch.token = ~0; /* broadcast wakeup */
10080 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10081 trace_kvm_async_pf_ready(work->arch.token, work->gva);
10083 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10084 !apf_get_user(vcpu, &val)) {
10085 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10086 vcpu->arch.exception.pending &&
10087 vcpu->arch.exception.nr == PF_VECTOR &&
10088 !apf_put_user(vcpu, 0)) {
10089 vcpu->arch.exception.injected = false;
10090 vcpu->arch.exception.pending = false;
10091 vcpu->arch.exception.nr = 0;
10092 vcpu->arch.exception.has_error_code = false;
10093 vcpu->arch.exception.error_code = 0;
10094 vcpu->arch.exception.has_payload = false;
10095 vcpu->arch.exception.payload = 0;
10096 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10097 fault.vector = PF_VECTOR;
10098 fault.error_code_valid = true;
10099 fault.error_code = 0;
10100 fault.nested_page_fault = false;
10101 fault.address = work->arch.token;
10102 fault.async_page_fault = true;
10103 kvm_inject_page_fault(vcpu, &fault);
10106 vcpu->arch.apf.halted = false;
10107 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10110 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10112 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10115 return kvm_can_do_async_pf(vcpu);
10118 void kvm_arch_start_assignment(struct kvm *kvm)
10120 atomic_inc(&kvm->arch.assigned_device_count);
10122 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10124 void kvm_arch_end_assignment(struct kvm *kvm)
10126 atomic_dec(&kvm->arch.assigned_device_count);
10128 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10130 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10132 return atomic_read(&kvm->arch.assigned_device_count);
10134 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10136 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10138 atomic_inc(&kvm->arch.noncoherent_dma_count);
10140 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10142 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10144 atomic_dec(&kvm->arch.noncoherent_dma_count);
10146 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10148 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10150 return atomic_read(&kvm->arch.noncoherent_dma_count);
10152 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10154 bool kvm_arch_has_irq_bypass(void)
10159 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10160 struct irq_bypass_producer *prod)
10162 struct kvm_kernel_irqfd *irqfd =
10163 container_of(cons, struct kvm_kernel_irqfd, consumer);
10165 irqfd->producer = prod;
10167 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10168 prod->irq, irqfd->gsi, 1);
10171 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10172 struct irq_bypass_producer *prod)
10175 struct kvm_kernel_irqfd *irqfd =
10176 container_of(cons, struct kvm_kernel_irqfd, consumer);
10178 WARN_ON(irqfd->producer != prod);
10179 irqfd->producer = NULL;
10182 * When producer of consumer is unregistered, we change back to
10183 * remapped mode, so we can re-use the current implementation
10184 * when the irq is masked/disabled or the consumer side (KVM
10185 * int this case doesn't want to receive the interrupts.
10187 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10189 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10190 " fails: %d\n", irqfd->consumer.token, ret);
10193 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10194 uint32_t guest_irq, bool set)
10196 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10199 bool kvm_vector_hashing_enabled(void)
10201 return vector_hashing;
10203 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
10205 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10207 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10209 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10212 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10213 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10214 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10215 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10216 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10217 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10218 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10219 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10220 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10221 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10222 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10223 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10224 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10225 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10226 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10227 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10228 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10229 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10230 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10231 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);