1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/sched/isolation.h>
58 #include <linux/mem_encrypt.h>
59 #include <linux/entry-kvm.h>
61 #include <trace/events/kvm.h>
63 #include <asm/debugreg.h>
67 #include <linux/kernel_stat.h>
68 #include <asm/fpu/internal.h> /* Ugh! */
69 #include <asm/pvclock.h>
70 #include <asm/div64.h>
71 #include <asm/irq_remapping.h>
72 #include <asm/mshyperv.h>
73 #include <asm/hypervisor.h>
74 #include <asm/tlbflush.h>
75 #include <asm/intel_pt.h>
76 #include <asm/emulate_prefix.h>
77 #include <clocksource/hyperv_timer.h>
79 #define CREATE_TRACE_POINTS
82 #define MAX_IO_MSRS 256
83 #define KVM_MAX_MCE_BANKS 32
84 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
85 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
87 #define emul_to_vcpu(ctxt) \
88 ((struct kvm_vcpu *)(ctxt)->vcpu)
91 * - enable syscall per default because its emulated by KVM
92 * - enable LME and LMA per default on 64 bit KVM
96 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
98 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
101 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
103 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
104 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
106 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
107 static void process_nmi(struct kvm_vcpu *vcpu);
108 static void enter_smm(struct kvm_vcpu *vcpu);
109 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
110 static void store_regs(struct kvm_vcpu *vcpu);
111 static int sync_regs(struct kvm_vcpu *vcpu);
113 struct kvm_x86_ops kvm_x86_ops __read_mostly;
114 EXPORT_SYMBOL_GPL(kvm_x86_ops);
116 static bool __read_mostly ignore_msrs = 0;
117 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
119 static bool __read_mostly report_ignored_msrs = true;
120 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
122 unsigned int min_timer_period_us = 200;
123 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
125 static bool __read_mostly kvmclock_periodic_sync = true;
126 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
128 bool __read_mostly kvm_has_tsc_control;
129 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
130 u32 __read_mostly kvm_max_guest_tsc_khz;
131 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
132 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
133 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
134 u64 __read_mostly kvm_max_tsc_scaling_ratio;
135 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
136 u64 __read_mostly kvm_default_tsc_scaling_ratio;
137 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
139 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
140 static u32 __read_mostly tsc_tolerance_ppm = 250;
141 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
144 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
145 * adaptive tuning starting from default advancment of 1000ns. '0' disables
146 * advancement entirely. Any other value is used as-is and disables adaptive
147 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
149 static int __read_mostly lapic_timer_advance_ns = -1;
150 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
152 static bool __read_mostly vector_hashing = true;
153 module_param(vector_hashing, bool, S_IRUGO);
155 bool __read_mostly enable_vmware_backdoor = false;
156 module_param(enable_vmware_backdoor, bool, S_IRUGO);
157 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
159 static bool __read_mostly force_emulation_prefix = false;
160 module_param(force_emulation_prefix, bool, S_IRUGO);
162 int __read_mostly pi_inject_timer = -1;
163 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
166 * Restoring the host value for MSRs that are only consumed when running in
167 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
168 * returns to userspace, i.e. the kernel can run with the guest's value.
170 #define KVM_MAX_NR_USER_RETURN_MSRS 16
172 struct kvm_user_return_msrs_global {
174 u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS];
177 struct kvm_user_return_msrs {
178 struct user_return_notifier urn;
180 struct kvm_user_return_msr_values {
183 } values[KVM_MAX_NR_USER_RETURN_MSRS];
186 static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global;
187 static struct kvm_user_return_msrs __percpu *user_return_msrs;
189 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
190 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
191 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
192 | XFEATURE_MASK_PKRU)
194 u64 __read_mostly host_efer;
195 EXPORT_SYMBOL_GPL(host_efer);
197 bool __read_mostly allow_smaller_maxphyaddr = 0;
198 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
200 static u64 __read_mostly host_xss;
201 u64 __read_mostly supported_xss;
202 EXPORT_SYMBOL_GPL(supported_xss);
204 struct kvm_stats_debugfs_item debugfs_entries[] = {
205 VCPU_STAT("pf_fixed", pf_fixed),
206 VCPU_STAT("pf_guest", pf_guest),
207 VCPU_STAT("tlb_flush", tlb_flush),
208 VCPU_STAT("invlpg", invlpg),
209 VCPU_STAT("exits", exits),
210 VCPU_STAT("io_exits", io_exits),
211 VCPU_STAT("mmio_exits", mmio_exits),
212 VCPU_STAT("signal_exits", signal_exits),
213 VCPU_STAT("irq_window", irq_window_exits),
214 VCPU_STAT("nmi_window", nmi_window_exits),
215 VCPU_STAT("halt_exits", halt_exits),
216 VCPU_STAT("halt_successful_poll", halt_successful_poll),
217 VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
218 VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
219 VCPU_STAT("halt_wakeup", halt_wakeup),
220 VCPU_STAT("hypercalls", hypercalls),
221 VCPU_STAT("request_irq", request_irq_exits),
222 VCPU_STAT("irq_exits", irq_exits),
223 VCPU_STAT("host_state_reload", host_state_reload),
224 VCPU_STAT("fpu_reload", fpu_reload),
225 VCPU_STAT("insn_emulation", insn_emulation),
226 VCPU_STAT("insn_emulation_fail", insn_emulation_fail),
227 VCPU_STAT("irq_injections", irq_injections),
228 VCPU_STAT("nmi_injections", nmi_injections),
229 VCPU_STAT("req_event", req_event),
230 VCPU_STAT("l1d_flush", l1d_flush),
231 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
232 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
233 VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped),
234 VM_STAT("mmu_pte_write", mmu_pte_write),
235 VM_STAT("mmu_pte_updated", mmu_pte_updated),
236 VM_STAT("mmu_pde_zapped", mmu_pde_zapped),
237 VM_STAT("mmu_flooded", mmu_flooded),
238 VM_STAT("mmu_recycled", mmu_recycled),
239 VM_STAT("mmu_cache_miss", mmu_cache_miss),
240 VM_STAT("mmu_unsync", mmu_unsync),
241 VM_STAT("remote_tlb_flush", remote_tlb_flush),
242 VM_STAT("largepages", lpages, .mode = 0444),
243 VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444),
244 VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions),
248 u64 __read_mostly host_xcr0;
249 u64 __read_mostly supported_xcr0;
250 EXPORT_SYMBOL_GPL(supported_xcr0);
252 static struct kmem_cache *x86_fpu_cache;
254 static struct kmem_cache *x86_emulator_cache;
257 * When called, it means the previous get/set msr reached an invalid msr.
258 * Return true if we want to ignore/silent this failed msr access.
260 static bool kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr,
261 u64 data, bool write)
263 const char *op = write ? "wrmsr" : "rdmsr";
266 if (report_ignored_msrs)
267 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
272 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
278 static struct kmem_cache *kvm_alloc_emulator_cache(void)
280 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
281 unsigned int size = sizeof(struct x86_emulate_ctxt);
283 return kmem_cache_create_usercopy("x86_emulator", size,
284 __alignof__(struct x86_emulate_ctxt),
285 SLAB_ACCOUNT, useroffset,
286 size - useroffset, NULL);
289 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
291 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
294 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
295 vcpu->arch.apf.gfns[i] = ~0;
298 static void kvm_on_user_return(struct user_return_notifier *urn)
301 struct kvm_user_return_msrs *msrs
302 = container_of(urn, struct kvm_user_return_msrs, urn);
303 struct kvm_user_return_msr_values *values;
307 * Disabling irqs at this point since the following code could be
308 * interrupted and executed through kvm_arch_hardware_disable()
310 local_irq_save(flags);
311 if (msrs->registered) {
312 msrs->registered = false;
313 user_return_notifier_unregister(urn);
315 local_irq_restore(flags);
316 for (slot = 0; slot < user_return_msrs_global.nr; ++slot) {
317 values = &msrs->values[slot];
318 if (values->host != values->curr) {
319 wrmsrl(user_return_msrs_global.msrs[slot], values->host);
320 values->curr = values->host;
325 void kvm_define_user_return_msr(unsigned slot, u32 msr)
327 BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS);
328 user_return_msrs_global.msrs[slot] = msr;
329 if (slot >= user_return_msrs_global.nr)
330 user_return_msrs_global.nr = slot + 1;
332 EXPORT_SYMBOL_GPL(kvm_define_user_return_msr);
334 static void kvm_user_return_msr_cpu_online(void)
336 unsigned int cpu = smp_processor_id();
337 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
341 for (i = 0; i < user_return_msrs_global.nr; ++i) {
342 rdmsrl_safe(user_return_msrs_global.msrs[i], &value);
343 msrs->values[i].host = value;
344 msrs->values[i].curr = value;
348 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
350 unsigned int cpu = smp_processor_id();
351 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
354 value = (value & mask) | (msrs->values[slot].host & ~mask);
355 if (value == msrs->values[slot].curr)
357 err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value);
361 msrs->values[slot].curr = value;
362 if (!msrs->registered) {
363 msrs->urn.on_user_return = kvm_on_user_return;
364 user_return_notifier_register(&msrs->urn);
365 msrs->registered = true;
369 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
371 static void drop_user_return_notifiers(void)
373 unsigned int cpu = smp_processor_id();
374 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
376 if (msrs->registered)
377 kvm_on_user_return(&msrs->urn);
380 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
382 return vcpu->arch.apic_base;
384 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
386 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
388 return kvm_apic_mode(kvm_get_apic_base(vcpu));
390 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
392 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
394 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
395 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
396 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
397 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
399 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
401 if (!msr_info->host_initiated) {
402 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
404 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
408 kvm_lapic_set_base(vcpu, msr_info->data);
409 kvm_recalculate_apic_map(vcpu->kvm);
412 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
414 asmlinkage __visible noinstr void kvm_spurious_fault(void)
416 /* Fault while not rebooting. We want the trace. */
417 BUG_ON(!kvm_rebooting);
419 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
421 #define EXCPT_BENIGN 0
422 #define EXCPT_CONTRIBUTORY 1
425 static int exception_class(int vector)
435 return EXCPT_CONTRIBUTORY;
442 #define EXCPT_FAULT 0
444 #define EXCPT_ABORT 2
445 #define EXCPT_INTERRUPT 3
447 static int exception_type(int vector)
451 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
452 return EXCPT_INTERRUPT;
456 /* #DB is trap, as instruction watchpoints are handled elsewhere */
457 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
460 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
463 /* Reserved exceptions will result in fault */
467 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
469 unsigned nr = vcpu->arch.exception.nr;
470 bool has_payload = vcpu->arch.exception.has_payload;
471 unsigned long payload = vcpu->arch.exception.payload;
479 * "Certain debug exceptions may clear bit 0-3. The
480 * remaining contents of the DR6 register are never
481 * cleared by the processor".
483 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
485 * DR6.RTM is set by all #DB exceptions that don't clear it.
487 vcpu->arch.dr6 |= DR6_RTM;
488 vcpu->arch.dr6 |= payload;
490 * Bit 16 should be set in the payload whenever the #DB
491 * exception should clear DR6.RTM. This makes the payload
492 * compatible with the pending debug exceptions under VMX.
493 * Though not currently documented in the SDM, this also
494 * makes the payload compatible with the exit qualification
495 * for #DB exceptions under VMX.
497 vcpu->arch.dr6 ^= payload & DR6_RTM;
500 * The #DB payload is defined as compatible with the 'pending
501 * debug exceptions' field under VMX, not DR6. While bit 12 is
502 * defined in the 'pending debug exceptions' field (enabled
503 * breakpoint), it is reserved and must be zero in DR6.
505 vcpu->arch.dr6 &= ~BIT(12);
508 vcpu->arch.cr2 = payload;
512 vcpu->arch.exception.has_payload = false;
513 vcpu->arch.exception.payload = 0;
515 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
517 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
518 unsigned nr, bool has_error, u32 error_code,
519 bool has_payload, unsigned long payload, bool reinject)
524 kvm_make_request(KVM_REQ_EVENT, vcpu);
526 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
528 if (has_error && !is_protmode(vcpu))
532 * On vmentry, vcpu->arch.exception.pending is only
533 * true if an event injection was blocked by
534 * nested_run_pending. In that case, however,
535 * vcpu_enter_guest requests an immediate exit,
536 * and the guest shouldn't proceed far enough to
539 WARN_ON_ONCE(vcpu->arch.exception.pending);
540 vcpu->arch.exception.injected = true;
541 if (WARN_ON_ONCE(has_payload)) {
543 * A reinjected event has already
544 * delivered its payload.
550 vcpu->arch.exception.pending = true;
551 vcpu->arch.exception.injected = false;
553 vcpu->arch.exception.has_error_code = has_error;
554 vcpu->arch.exception.nr = nr;
555 vcpu->arch.exception.error_code = error_code;
556 vcpu->arch.exception.has_payload = has_payload;
557 vcpu->arch.exception.payload = payload;
558 if (!is_guest_mode(vcpu))
559 kvm_deliver_exception_payload(vcpu);
563 /* to check exception */
564 prev_nr = vcpu->arch.exception.nr;
565 if (prev_nr == DF_VECTOR) {
566 /* triple fault -> shutdown */
567 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
570 class1 = exception_class(prev_nr);
571 class2 = exception_class(nr);
572 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
573 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
575 * Generate double fault per SDM Table 5-5. Set
576 * exception.pending = true so that the double fault
577 * can trigger a nested vmexit.
579 vcpu->arch.exception.pending = true;
580 vcpu->arch.exception.injected = false;
581 vcpu->arch.exception.has_error_code = true;
582 vcpu->arch.exception.nr = DF_VECTOR;
583 vcpu->arch.exception.error_code = 0;
584 vcpu->arch.exception.has_payload = false;
585 vcpu->arch.exception.payload = 0;
587 /* replace previous exception with a new one in a hope
588 that instruction re-execution will regenerate lost
593 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
595 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
597 EXPORT_SYMBOL_GPL(kvm_queue_exception);
599 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
601 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
603 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
605 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
606 unsigned long payload)
608 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
610 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
612 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
613 u32 error_code, unsigned long payload)
615 kvm_multiple_exception(vcpu, nr, true, error_code,
616 true, payload, false);
619 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
622 kvm_inject_gp(vcpu, 0);
624 return kvm_skip_emulated_instruction(vcpu);
628 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
630 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
632 ++vcpu->stat.pf_guest;
633 vcpu->arch.exception.nested_apf =
634 is_guest_mode(vcpu) && fault->async_page_fault;
635 if (vcpu->arch.exception.nested_apf) {
636 vcpu->arch.apf.nested_apf_token = fault->address;
637 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
639 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
643 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
645 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
646 struct x86_exception *fault)
648 struct kvm_mmu *fault_mmu;
649 WARN_ON_ONCE(fault->vector != PF_VECTOR);
651 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
655 * Invalidate the TLB entry for the faulting address, if it exists,
656 * else the access will fault indefinitely (and to emulate hardware).
658 if ((fault->error_code & PFERR_PRESENT_MASK) &&
659 !(fault->error_code & PFERR_RSVD_MASK))
660 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
661 fault_mmu->root_hpa);
663 fault_mmu->inject_page_fault(vcpu, fault);
664 return fault->nested_page_fault;
666 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
668 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
670 atomic_inc(&vcpu->arch.nmi_queued);
671 kvm_make_request(KVM_REQ_NMI, vcpu);
673 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
675 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
677 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
679 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
681 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
683 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
685 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
688 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
689 * a #GP and return false.
691 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
693 if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl)
695 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
698 EXPORT_SYMBOL_GPL(kvm_require_cpl);
700 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
702 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705 kvm_queue_exception(vcpu, UD_VECTOR);
708 EXPORT_SYMBOL_GPL(kvm_require_dr);
711 * This function will be used to read from the physical memory of the currently
712 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
713 * can read from guest physical or from the guest's guest physical memory.
715 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
716 gfn_t ngfn, void *data, int offset, int len,
719 struct x86_exception exception;
723 ngpa = gfn_to_gpa(ngfn);
724 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
725 if (real_gfn == UNMAPPED_GVA)
728 real_gfn = gpa_to_gfn(real_gfn);
730 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
732 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
734 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
735 void *data, int offset, int len, u32 access)
737 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
738 data, offset, len, access);
741 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
743 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
748 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
750 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
752 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
753 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
756 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
758 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
759 offset * sizeof(u64), sizeof(pdpte),
760 PFERR_USER_MASK|PFERR_WRITE_MASK);
765 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
766 if ((pdpte[i] & PT_PRESENT_MASK) &&
767 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
774 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
775 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
781 EXPORT_SYMBOL_GPL(load_pdptrs);
783 bool pdptrs_changed(struct kvm_vcpu *vcpu)
785 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
790 if (!is_pae_paging(vcpu))
793 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
796 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
797 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
798 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
799 PFERR_USER_MASK | PFERR_WRITE_MASK);
803 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
805 EXPORT_SYMBOL_GPL(pdptrs_changed);
807 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
809 unsigned long old_cr0 = kvm_read_cr0(vcpu);
810 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG;
811 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
816 if (cr0 & 0xffffffff00000000UL)
820 cr0 &= ~CR0_RESERVED_BITS;
822 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
825 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
829 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
830 (cr0 & X86_CR0_PG)) {
835 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
840 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
841 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) &&
842 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)))
845 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
848 kvm_x86_ops.set_cr0(vcpu, cr0);
850 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
851 kvm_clear_async_pf_completion_queue(vcpu);
852 kvm_async_pf_hash_reset(vcpu);
855 if ((cr0 ^ old_cr0) & update_bits)
856 kvm_mmu_reset_context(vcpu);
858 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
859 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
860 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
861 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
865 EXPORT_SYMBOL_GPL(kvm_set_cr0);
867 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
869 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
871 EXPORT_SYMBOL_GPL(kvm_lmsw);
873 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
875 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
877 if (vcpu->arch.xcr0 != host_xcr0)
878 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
880 if (vcpu->arch.xsaves_enabled &&
881 vcpu->arch.ia32_xss != host_xss)
882 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
885 if (static_cpu_has(X86_FEATURE_PKU) &&
886 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
887 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
888 vcpu->arch.pkru != vcpu->arch.host_pkru)
889 __write_pkru(vcpu->arch.pkru);
891 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
893 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
895 if (static_cpu_has(X86_FEATURE_PKU) &&
896 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
897 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
898 vcpu->arch.pkru = rdpkru();
899 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
900 __write_pkru(vcpu->arch.host_pkru);
903 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
905 if (vcpu->arch.xcr0 != host_xcr0)
906 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
908 if (vcpu->arch.xsaves_enabled &&
909 vcpu->arch.ia32_xss != host_xss)
910 wrmsrl(MSR_IA32_XSS, host_xss);
914 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
916 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
919 u64 old_xcr0 = vcpu->arch.xcr0;
922 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
923 if (index != XCR_XFEATURE_ENABLED_MASK)
925 if (!(xcr0 & XFEATURE_MASK_FP))
927 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
931 * Do not allow the guest to set bits that we do not support
932 * saving. However, xcr0 bit 0 is always set, even if the
933 * emulated CPU does not support XSAVE (see fx_init).
935 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
936 if (xcr0 & ~valid_bits)
939 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
940 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
943 if (xcr0 & XFEATURE_MASK_AVX512) {
944 if (!(xcr0 & XFEATURE_MASK_YMM))
946 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
949 vcpu->arch.xcr0 = xcr0;
951 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
952 kvm_update_cpuid_runtime(vcpu);
956 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
958 if (kvm_x86_ops.get_cpl(vcpu) != 0 ||
959 __kvm_set_xcr(vcpu, index, xcr)) {
960 kvm_inject_gp(vcpu, 0);
965 EXPORT_SYMBOL_GPL(kvm_set_xcr);
967 int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
969 if (cr4 & cr4_reserved_bits)
972 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
977 EXPORT_SYMBOL_GPL(kvm_valid_cr4);
979 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
981 unsigned long old_cr4 = kvm_read_cr4(vcpu);
982 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
984 unsigned long mmu_role_bits = pdptr_bits | X86_CR4_SMAP | X86_CR4_PKE;
986 if (kvm_valid_cr4(vcpu, cr4))
989 if (is_long_mode(vcpu)) {
990 if (!(cr4 & X86_CR4_PAE))
992 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
994 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
995 && ((cr4 ^ old_cr4) & pdptr_bits)
996 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
1000 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1001 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1004 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1005 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1009 if (kvm_x86_ops.set_cr4(vcpu, cr4))
1012 if (((cr4 ^ old_cr4) & mmu_role_bits) ||
1013 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1014 kvm_mmu_reset_context(vcpu);
1016 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1017 kvm_update_cpuid_runtime(vcpu);
1021 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1023 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1025 bool skip_tlb_flush = false;
1026 #ifdef CONFIG_X86_64
1027 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1030 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1031 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1035 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1036 if (!skip_tlb_flush) {
1037 kvm_mmu_sync_roots(vcpu);
1038 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1043 if (is_long_mode(vcpu) &&
1044 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
1046 else if (is_pae_paging(vcpu) &&
1047 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1050 kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush);
1051 vcpu->arch.cr3 = cr3;
1052 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1056 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1058 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1060 if (cr8 & CR8_RESERVED_BITS)
1062 if (lapic_in_kernel(vcpu))
1063 kvm_lapic_set_tpr(vcpu, cr8);
1065 vcpu->arch.cr8 = cr8;
1068 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1070 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1072 if (lapic_in_kernel(vcpu))
1073 return kvm_lapic_get_cr8(vcpu);
1075 return vcpu->arch.cr8;
1077 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1079 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1083 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1084 for (i = 0; i < KVM_NR_DB_REGS; i++)
1085 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1086 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1090 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1094 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1095 dr7 = vcpu->arch.guest_debug_dr7;
1097 dr7 = vcpu->arch.dr7;
1098 kvm_x86_ops.set_dr7(vcpu, dr7);
1099 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1100 if (dr7 & DR7_BP_EN_MASK)
1101 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1103 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1105 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1107 u64 fixed = DR6_FIXED_1;
1109 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1114 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1116 size_t size = ARRAY_SIZE(vcpu->arch.db);
1120 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1121 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1122 vcpu->arch.eff_db[dr] = val;
1126 if (!kvm_dr6_valid(val))
1127 return -1; /* #GP */
1128 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1132 if (!kvm_dr7_valid(val))
1133 return -1; /* #GP */
1134 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1135 kvm_update_dr7(vcpu);
1142 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1144 if (__kvm_set_dr(vcpu, dr, val)) {
1145 kvm_inject_gp(vcpu, 0);
1150 EXPORT_SYMBOL_GPL(kvm_set_dr);
1152 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1154 size_t size = ARRAY_SIZE(vcpu->arch.db);
1158 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1162 *val = vcpu->arch.dr6;
1166 *val = vcpu->arch.dr7;
1171 EXPORT_SYMBOL_GPL(kvm_get_dr);
1173 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1175 u32 ecx = kvm_rcx_read(vcpu);
1179 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1182 kvm_rax_write(vcpu, (u32)data);
1183 kvm_rdx_write(vcpu, data >> 32);
1186 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1189 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1190 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1192 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1193 * extract the supported MSRs from the related const lists.
1194 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1195 * capabilities of the host cpu. This capabilities test skips MSRs that are
1196 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1197 * may depend on host virtualization features rather than host cpu features.
1200 static const u32 msrs_to_save_all[] = {
1201 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1203 #ifdef CONFIG_X86_64
1204 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1206 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1207 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1209 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1210 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1211 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1212 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1213 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1214 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1215 MSR_IA32_UMWAIT_CONTROL,
1217 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1218 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1219 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1220 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1221 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1222 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1223 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1224 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1225 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1226 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1227 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1228 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1229 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1230 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1231 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1232 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1233 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1234 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1235 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1236 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1237 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1238 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1241 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1242 static unsigned num_msrs_to_save;
1244 static const u32 emulated_msrs_all[] = {
1245 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1246 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1247 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1248 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1249 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1250 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1251 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1253 HV_X64_MSR_VP_INDEX,
1254 HV_X64_MSR_VP_RUNTIME,
1255 HV_X64_MSR_SCONTROL,
1256 HV_X64_MSR_STIMER0_CONFIG,
1257 HV_X64_MSR_VP_ASSIST_PAGE,
1258 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1259 HV_X64_MSR_TSC_EMULATION_STATUS,
1260 HV_X64_MSR_SYNDBG_OPTIONS,
1261 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1262 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1263 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1265 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1266 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1268 MSR_IA32_TSC_ADJUST,
1269 MSR_IA32_TSCDEADLINE,
1270 MSR_IA32_ARCH_CAPABILITIES,
1271 MSR_IA32_PERF_CAPABILITIES,
1272 MSR_IA32_MISC_ENABLE,
1273 MSR_IA32_MCG_STATUS,
1275 MSR_IA32_MCG_EXT_CTL,
1279 MSR_MISC_FEATURES_ENABLES,
1280 MSR_AMD64_VIRT_SPEC_CTRL,
1285 * The following list leaves out MSRs whose values are determined
1286 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1287 * We always support the "true" VMX control MSRs, even if the host
1288 * processor does not, so I am putting these registers here rather
1289 * than in msrs_to_save_all.
1292 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1293 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1294 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1295 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1297 MSR_IA32_VMX_CR0_FIXED0,
1298 MSR_IA32_VMX_CR4_FIXED0,
1299 MSR_IA32_VMX_VMCS_ENUM,
1300 MSR_IA32_VMX_PROCBASED_CTLS2,
1301 MSR_IA32_VMX_EPT_VPID_CAP,
1302 MSR_IA32_VMX_VMFUNC,
1305 MSR_KVM_POLL_CONTROL,
1308 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1309 static unsigned num_emulated_msrs;
1312 * List of msr numbers which are used to expose MSR-based features that
1313 * can be used by a hypervisor to validate requested CPU features.
1315 static const u32 msr_based_features_all[] = {
1317 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1318 MSR_IA32_VMX_PINBASED_CTLS,
1319 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1320 MSR_IA32_VMX_PROCBASED_CTLS,
1321 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1322 MSR_IA32_VMX_EXIT_CTLS,
1323 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1324 MSR_IA32_VMX_ENTRY_CTLS,
1326 MSR_IA32_VMX_CR0_FIXED0,
1327 MSR_IA32_VMX_CR0_FIXED1,
1328 MSR_IA32_VMX_CR4_FIXED0,
1329 MSR_IA32_VMX_CR4_FIXED1,
1330 MSR_IA32_VMX_VMCS_ENUM,
1331 MSR_IA32_VMX_PROCBASED_CTLS2,
1332 MSR_IA32_VMX_EPT_VPID_CAP,
1333 MSR_IA32_VMX_VMFUNC,
1337 MSR_IA32_ARCH_CAPABILITIES,
1338 MSR_IA32_PERF_CAPABILITIES,
1341 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1342 static unsigned int num_msr_based_features;
1344 static u64 kvm_get_arch_capabilities(void)
1348 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1349 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1352 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1353 * the nested hypervisor runs with NX huge pages. If it is not,
1354 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1355 * L1 guests, so it need not worry about its own (L2) guests.
1357 data |= ARCH_CAP_PSCHANGE_MC_NO;
1360 * If we're doing cache flushes (either "always" or "cond")
1361 * we will do one whenever the guest does a vmlaunch/vmresume.
1362 * If an outer hypervisor is doing the cache flush for us
1363 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1364 * capability to the guest too, and if EPT is disabled we're not
1365 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1366 * require a nested hypervisor to do a flush of its own.
1368 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1369 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1371 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1372 data |= ARCH_CAP_RDCL_NO;
1373 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1374 data |= ARCH_CAP_SSB_NO;
1375 if (!boot_cpu_has_bug(X86_BUG_MDS))
1376 data |= ARCH_CAP_MDS_NO;
1379 * On TAA affected systems:
1380 * - nothing to do if TSX is disabled on the host.
1381 * - we emulate TSX_CTRL if present on the host.
1382 * This lets the guest use VERW to clear CPU buffers.
1384 if (!boot_cpu_has(X86_FEATURE_RTM))
1385 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1386 else if (!boot_cpu_has_bug(X86_BUG_TAA))
1387 data |= ARCH_CAP_TAA_NO;
1392 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1394 switch (msr->index) {
1395 case MSR_IA32_ARCH_CAPABILITIES:
1396 msr->data = kvm_get_arch_capabilities();
1398 case MSR_IA32_UCODE_REV:
1399 rdmsrl_safe(msr->index, &msr->data);
1402 return kvm_x86_ops.get_msr_feature(msr);
1407 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1409 struct kvm_msr_entry msr;
1413 r = kvm_get_msr_feature(&msr);
1415 if (r == KVM_MSR_RET_INVALID) {
1416 /* Unconditionally clear the output for simplicity */
1418 if (kvm_msr_ignored_check(vcpu, index, 0, false))
1430 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1432 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1435 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1438 if (efer & (EFER_LME | EFER_LMA) &&
1439 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1442 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1448 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1450 if (efer & efer_reserved_bits)
1453 return __kvm_valid_efer(vcpu, efer);
1455 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1457 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1459 u64 old_efer = vcpu->arch.efer;
1460 u64 efer = msr_info->data;
1463 if (efer & efer_reserved_bits)
1466 if (!msr_info->host_initiated) {
1467 if (!__kvm_valid_efer(vcpu, efer))
1470 if (is_paging(vcpu) &&
1471 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1476 efer |= vcpu->arch.efer & EFER_LMA;
1478 r = kvm_x86_ops.set_efer(vcpu, efer);
1484 /* Update reserved bits */
1485 if ((efer ^ old_efer) & EFER_NX)
1486 kvm_mmu_reset_context(vcpu);
1491 void kvm_enable_efer_bits(u64 mask)
1493 efer_reserved_bits &= ~mask;
1495 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1497 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1499 struct kvm *kvm = vcpu->kvm;
1500 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
1501 u32 count = kvm->arch.msr_filter.count;
1503 bool r = kvm->arch.msr_filter.default_allow;
1506 /* MSR filtering not set up or x2APIC enabled, allow everything */
1507 if (!count || (index >= 0x800 && index <= 0x8ff))
1510 /* Prevent collision with set_msr_filter */
1511 idx = srcu_read_lock(&kvm->srcu);
1513 for (i = 0; i < count; i++) {
1514 u32 start = ranges[i].base;
1515 u32 end = start + ranges[i].nmsrs;
1516 u32 flags = ranges[i].flags;
1517 unsigned long *bitmap = ranges[i].bitmap;
1519 if ((index >= start) && (index < end) && (flags & type)) {
1520 r = !!test_bit(index - start, bitmap);
1525 srcu_read_unlock(&kvm->srcu, idx);
1529 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1532 * Write @data into the MSR specified by @index. Select MSR specific fault
1533 * checks are bypassed if @host_initiated is %true.
1534 * Returns 0 on success, non-0 otherwise.
1535 * Assumes vcpu_load() was already called.
1537 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1538 bool host_initiated)
1540 struct msr_data msr;
1542 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1543 return KVM_MSR_RET_FILTERED;
1548 case MSR_KERNEL_GS_BASE:
1551 if (is_noncanonical_address(data, vcpu))
1554 case MSR_IA32_SYSENTER_EIP:
1555 case MSR_IA32_SYSENTER_ESP:
1557 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1558 * non-canonical address is written on Intel but not on
1559 * AMD (which ignores the top 32-bits, because it does
1560 * not implement 64-bit SYSENTER).
1562 * 64-bit code should hence be able to write a non-canonical
1563 * value on AMD. Making the address canonical ensures that
1564 * vmentry does not fail on Intel after writing a non-canonical
1565 * value, and that something deterministic happens if the guest
1566 * invokes 64-bit SYSENTER.
1568 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1573 msr.host_initiated = host_initiated;
1575 return kvm_x86_ops.set_msr(vcpu, &msr);
1578 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1579 u32 index, u64 data, bool host_initiated)
1581 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1583 if (ret == KVM_MSR_RET_INVALID)
1584 if (kvm_msr_ignored_check(vcpu, index, data, true))
1591 * Read the MSR specified by @index into @data. Select MSR specific fault
1592 * checks are bypassed if @host_initiated is %true.
1593 * Returns 0 on success, non-0 otherwise.
1594 * Assumes vcpu_load() was already called.
1596 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1597 bool host_initiated)
1599 struct msr_data msr;
1602 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1603 return KVM_MSR_RET_FILTERED;
1606 msr.host_initiated = host_initiated;
1608 ret = kvm_x86_ops.get_msr(vcpu, &msr);
1614 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1615 u32 index, u64 *data, bool host_initiated)
1617 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1619 if (ret == KVM_MSR_RET_INVALID) {
1620 /* Unconditionally clear *data for simplicity */
1622 if (kvm_msr_ignored_check(vcpu, index, 0, false))
1629 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1631 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1633 EXPORT_SYMBOL_GPL(kvm_get_msr);
1635 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1637 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1639 EXPORT_SYMBOL_GPL(kvm_set_msr);
1641 static int complete_emulated_msr(struct kvm_vcpu *vcpu, bool is_read)
1643 if (vcpu->run->msr.error) {
1644 kvm_inject_gp(vcpu, 0);
1646 } else if (is_read) {
1647 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1648 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1651 return kvm_skip_emulated_instruction(vcpu);
1654 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1656 return complete_emulated_msr(vcpu, true);
1659 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu)
1661 return complete_emulated_msr(vcpu, false);
1664 static u64 kvm_msr_reason(int r)
1667 case KVM_MSR_RET_INVALID:
1668 return KVM_MSR_EXIT_REASON_UNKNOWN;
1669 case KVM_MSR_RET_FILTERED:
1670 return KVM_MSR_EXIT_REASON_FILTER;
1672 return KVM_MSR_EXIT_REASON_INVAL;
1676 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1677 u32 exit_reason, u64 data,
1678 int (*completion)(struct kvm_vcpu *vcpu),
1681 u64 msr_reason = kvm_msr_reason(r);
1683 /* Check if the user wanted to know about this MSR fault */
1684 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
1687 vcpu->run->exit_reason = exit_reason;
1688 vcpu->run->msr.error = 0;
1689 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
1690 vcpu->run->msr.reason = msr_reason;
1691 vcpu->run->msr.index = index;
1692 vcpu->run->msr.data = data;
1693 vcpu->arch.complete_userspace_io = completion;
1698 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r)
1700 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0,
1701 complete_emulated_rdmsr, r);
1704 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r)
1706 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data,
1707 complete_emulated_wrmsr, r);
1710 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1712 u32 ecx = kvm_rcx_read(vcpu);
1716 r = kvm_get_msr(vcpu, ecx, &data);
1718 /* MSR read failed? See if we should ask user space */
1719 if (r && kvm_get_msr_user_space(vcpu, ecx, r)) {
1720 /* Bounce to user space */
1724 /* MSR read failed? Inject a #GP */
1726 trace_kvm_msr_read_ex(ecx);
1727 kvm_inject_gp(vcpu, 0);
1731 trace_kvm_msr_read(ecx, data);
1733 kvm_rax_write(vcpu, data & -1u);
1734 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1735 return kvm_skip_emulated_instruction(vcpu);
1737 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1739 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1741 u32 ecx = kvm_rcx_read(vcpu);
1742 u64 data = kvm_read_edx_eax(vcpu);
1745 r = kvm_set_msr(vcpu, ecx, data);
1747 /* MSR write failed? See if we should ask user space */
1748 if (r && kvm_set_msr_user_space(vcpu, ecx, data, r))
1749 /* Bounce to user space */
1752 /* Signal all other negative errors to userspace */
1756 /* MSR write failed? Inject a #GP */
1758 trace_kvm_msr_write_ex(ecx, data);
1759 kvm_inject_gp(vcpu, 0);
1763 trace_kvm_msr_write(ecx, data);
1764 return kvm_skip_emulated_instruction(vcpu);
1766 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1768 bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
1770 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
1771 xfer_to_guest_mode_work_pending();
1773 EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request);
1776 * The fast path for frequent and performance sensitive wrmsr emulation,
1777 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1778 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1779 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1780 * other cases which must be called after interrupts are enabled on the host.
1782 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1784 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1787 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1788 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1789 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1790 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1793 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1794 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1795 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1796 trace_kvm_apic_write(APIC_ICR, (u32)data);
1803 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
1805 if (!kvm_can_use_hv_timer(vcpu))
1808 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1812 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1814 u32 msr = kvm_rcx_read(vcpu);
1816 fastpath_t ret = EXIT_FASTPATH_NONE;
1819 case APIC_BASE_MSR + (APIC_ICR >> 4):
1820 data = kvm_read_edx_eax(vcpu);
1821 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
1822 kvm_skip_emulated_instruction(vcpu);
1823 ret = EXIT_FASTPATH_EXIT_HANDLED;
1826 case MSR_IA32_TSCDEADLINE:
1827 data = kvm_read_edx_eax(vcpu);
1828 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
1829 kvm_skip_emulated_instruction(vcpu);
1830 ret = EXIT_FASTPATH_REENTER_GUEST;
1837 if (ret != EXIT_FASTPATH_NONE)
1838 trace_kvm_msr_write(msr, data);
1842 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1845 * Adapt set_msr() to msr_io()'s calling convention
1847 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1849 return kvm_get_msr_ignored_check(vcpu, index, data, true);
1852 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1854 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
1857 #ifdef CONFIG_X86_64
1858 struct pvclock_clock {
1868 struct pvclock_gtod_data {
1871 struct pvclock_clock clock; /* extract of a clocksource struct */
1872 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1878 static struct pvclock_gtod_data pvclock_gtod_data;
1880 static void update_pvclock_gtod(struct timekeeper *tk)
1882 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1884 write_seqcount_begin(&vdata->seq);
1886 /* copy pvclock gtod data */
1887 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
1888 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1889 vdata->clock.mask = tk->tkr_mono.mask;
1890 vdata->clock.mult = tk->tkr_mono.mult;
1891 vdata->clock.shift = tk->tkr_mono.shift;
1892 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
1893 vdata->clock.offset = tk->tkr_mono.base;
1895 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
1896 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1897 vdata->raw_clock.mask = tk->tkr_raw.mask;
1898 vdata->raw_clock.mult = tk->tkr_raw.mult;
1899 vdata->raw_clock.shift = tk->tkr_raw.shift;
1900 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
1901 vdata->raw_clock.offset = tk->tkr_raw.base;
1903 vdata->wall_time_sec = tk->xtime_sec;
1905 vdata->offs_boot = tk->offs_boot;
1907 write_seqcount_end(&vdata->seq);
1910 static s64 get_kvmclock_base_ns(void)
1912 /* Count up from boot time, but with the frequency of the raw clock. */
1913 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1916 static s64 get_kvmclock_base_ns(void)
1918 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
1919 return ktime_get_boottime_ns();
1923 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1927 struct pvclock_wall_clock wc;
1930 kvm->arch.wall_clock = wall_clock;
1935 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1940 ++version; /* first time write, random junk */
1944 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1948 * The guest calculates current wall clock time by adding
1949 * system time (updated by kvm_guest_time_update below) to the
1950 * wall clock specified here. We do the reverse here.
1952 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1954 wc.nsec = do_div(wall_nsec, 1000000000);
1955 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1956 wc.version = version;
1958 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1961 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1964 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
1965 bool old_msr, bool host_initiated)
1967 struct kvm_arch *ka = &vcpu->kvm->arch;
1969 if (vcpu->vcpu_id == 0 && !host_initiated) {
1970 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
1971 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1973 ka->boot_vcpu_runs_old_kvmclock = old_msr;
1976 vcpu->arch.time = system_time;
1977 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
1979 /* we verify if the enable bit is set... */
1980 vcpu->arch.pv_time_enabled = false;
1981 if (!(system_time & 1))
1984 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
1985 &vcpu->arch.pv_time, system_time & ~1ULL,
1986 sizeof(struct pvclock_vcpu_time_info)))
1987 vcpu->arch.pv_time_enabled = true;
1992 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1994 do_shl32_div32(dividend, divisor);
1998 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1999 s8 *pshift, u32 *pmultiplier)
2007 scaled64 = scaled_hz;
2008 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2013 tps32 = (uint32_t)tps64;
2014 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2015 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2023 *pmultiplier = div_frac(scaled64, tps32);
2026 #ifdef CONFIG_X86_64
2027 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2030 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2031 static unsigned long max_tsc_khz;
2033 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2035 u64 v = (u64)khz * (1000000 + ppm);
2040 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2044 /* Guest TSC same frequency as host TSC? */
2046 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2050 /* TSC scaling supported? */
2051 if (!kvm_has_tsc_control) {
2052 if (user_tsc_khz > tsc_khz) {
2053 vcpu->arch.tsc_catchup = 1;
2054 vcpu->arch.tsc_always_catchup = 1;
2057 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2062 /* TSC scaling required - calculate ratio */
2063 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
2064 user_tsc_khz, tsc_khz);
2066 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
2067 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2072 vcpu->arch.tsc_scaling_ratio = ratio;
2076 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2078 u32 thresh_lo, thresh_hi;
2079 int use_scaling = 0;
2081 /* tsc_khz can be zero if TSC calibration fails */
2082 if (user_tsc_khz == 0) {
2083 /* set tsc_scaling_ratio to a safe value */
2084 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2088 /* Compute a scale to convert nanoseconds in TSC cycles */
2089 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2090 &vcpu->arch.virtual_tsc_shift,
2091 &vcpu->arch.virtual_tsc_mult);
2092 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2095 * Compute the variation in TSC rate which is acceptable
2096 * within the range of tolerance and decide if the
2097 * rate being applied is within that bounds of the hardware
2098 * rate. If so, no scaling or compensation need be done.
2100 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2101 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2102 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2103 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2106 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2109 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2111 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2112 vcpu->arch.virtual_tsc_mult,
2113 vcpu->arch.virtual_tsc_shift);
2114 tsc += vcpu->arch.this_tsc_write;
2118 static inline int gtod_is_based_on_tsc(int mode)
2120 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2123 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2125 #ifdef CONFIG_X86_64
2127 struct kvm_arch *ka = &vcpu->kvm->arch;
2128 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2130 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2131 atomic_read(&vcpu->kvm->online_vcpus));
2134 * Once the masterclock is enabled, always perform request in
2135 * order to update it.
2137 * In order to enable masterclock, the host clocksource must be TSC
2138 * and the vcpus need to have matched TSCs. When that happens,
2139 * perform request to enable masterclock.
2141 if (ka->use_master_clock ||
2142 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2143 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2145 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2146 atomic_read(&vcpu->kvm->online_vcpus),
2147 ka->use_master_clock, gtod->clock.vclock_mode);
2152 * Multiply tsc by a fixed point number represented by ratio.
2154 * The most significant 64-N bits (mult) of ratio represent the
2155 * integral part of the fixed point number; the remaining N bits
2156 * (frac) represent the fractional part, ie. ratio represents a fixed
2157 * point number (mult + frac * 2^(-N)).
2159 * N equals to kvm_tsc_scaling_ratio_frac_bits.
2161 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2163 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
2166 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
2169 u64 ratio = vcpu->arch.tsc_scaling_ratio;
2171 if (ratio != kvm_default_tsc_scaling_ratio)
2172 _tsc = __scale_tsc(ratio, tsc);
2176 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2178 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2182 tsc = kvm_scale_tsc(vcpu, rdtsc());
2184 return target_tsc - tsc;
2187 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2189 return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
2191 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2193 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2195 vcpu->arch.l1_tsc_offset = offset;
2196 vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset);
2199 static inline bool kvm_check_tsc_unstable(void)
2201 #ifdef CONFIG_X86_64
2203 * TSC is marked unstable when we're running on Hyper-V,
2204 * 'TSC page' clocksource is good.
2206 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2209 return check_tsc_unstable();
2212 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2214 struct kvm *kvm = vcpu->kvm;
2215 u64 offset, ns, elapsed;
2216 unsigned long flags;
2218 bool already_matched;
2219 bool synchronizing = false;
2221 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2222 offset = kvm_compute_tsc_offset(vcpu, data);
2223 ns = get_kvmclock_base_ns();
2224 elapsed = ns - kvm->arch.last_tsc_nsec;
2226 if (vcpu->arch.virtual_tsc_khz) {
2229 * detection of vcpu initialization -- need to sync
2230 * with other vCPUs. This particularly helps to keep
2231 * kvm_clock stable after CPU hotplug
2233 synchronizing = true;
2235 u64 tsc_exp = kvm->arch.last_tsc_write +
2236 nsec_to_cycles(vcpu, elapsed);
2237 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2239 * Special case: TSC write with a small delta (1 second)
2240 * of virtual cycle time against real time is
2241 * interpreted as an attempt to synchronize the CPU.
2243 synchronizing = data < tsc_exp + tsc_hz &&
2244 data + tsc_hz > tsc_exp;
2249 * For a reliable TSC, we can match TSC offsets, and for an unstable
2250 * TSC, we add elapsed time in this computation. We could let the
2251 * compensation code attempt to catch up if we fall behind, but
2252 * it's better to try to match offsets from the beginning.
2254 if (synchronizing &&
2255 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2256 if (!kvm_check_tsc_unstable()) {
2257 offset = kvm->arch.cur_tsc_offset;
2259 u64 delta = nsec_to_cycles(vcpu, elapsed);
2261 offset = kvm_compute_tsc_offset(vcpu, data);
2264 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2267 * We split periods of matched TSC writes into generations.
2268 * For each generation, we track the original measured
2269 * nanosecond time, offset, and write, so if TSCs are in
2270 * sync, we can match exact offset, and if not, we can match
2271 * exact software computation in compute_guest_tsc()
2273 * These values are tracked in kvm->arch.cur_xxx variables.
2275 kvm->arch.cur_tsc_generation++;
2276 kvm->arch.cur_tsc_nsec = ns;
2277 kvm->arch.cur_tsc_write = data;
2278 kvm->arch.cur_tsc_offset = offset;
2283 * We also track th most recent recorded KHZ, write and time to
2284 * allow the matching interval to be extended at each write.
2286 kvm->arch.last_tsc_nsec = ns;
2287 kvm->arch.last_tsc_write = data;
2288 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2290 vcpu->arch.last_guest_tsc = data;
2292 /* Keep track of which generation this VCPU has synchronized to */
2293 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2294 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2295 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2297 kvm_vcpu_write_tsc_offset(vcpu, offset);
2298 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2300 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2302 kvm->arch.nr_vcpus_matched_tsc = 0;
2303 } else if (!already_matched) {
2304 kvm->arch.nr_vcpus_matched_tsc++;
2307 kvm_track_tsc_matching(vcpu);
2308 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2311 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2314 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2315 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2318 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2320 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2321 WARN_ON(adjustment < 0);
2322 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2323 adjust_tsc_offset_guest(vcpu, adjustment);
2326 #ifdef CONFIG_X86_64
2328 static u64 read_tsc(void)
2330 u64 ret = (u64)rdtsc_ordered();
2331 u64 last = pvclock_gtod_data.clock.cycle_last;
2333 if (likely(ret >= last))
2337 * GCC likes to generate cmov here, but this branch is extremely
2338 * predictable (it's just a function of time and the likely is
2339 * very likely) and there's a data dependence, so force GCC
2340 * to generate a branch instead. I don't barrier() because
2341 * we don't actually need a barrier, and if this function
2342 * ever gets inlined it will generate worse code.
2348 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2354 switch (clock->vclock_mode) {
2355 case VDSO_CLOCKMODE_HVCLOCK:
2356 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2358 if (tsc_pg_val != U64_MAX) {
2359 /* TSC page valid */
2360 *mode = VDSO_CLOCKMODE_HVCLOCK;
2361 v = (tsc_pg_val - clock->cycle_last) &
2364 /* TSC page invalid */
2365 *mode = VDSO_CLOCKMODE_NONE;
2368 case VDSO_CLOCKMODE_TSC:
2369 *mode = VDSO_CLOCKMODE_TSC;
2370 *tsc_timestamp = read_tsc();
2371 v = (*tsc_timestamp - clock->cycle_last) &
2375 *mode = VDSO_CLOCKMODE_NONE;
2378 if (*mode == VDSO_CLOCKMODE_NONE)
2379 *tsc_timestamp = v = 0;
2381 return v * clock->mult;
2384 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2386 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2392 seq = read_seqcount_begin(>od->seq);
2393 ns = gtod->raw_clock.base_cycles;
2394 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2395 ns >>= gtod->raw_clock.shift;
2396 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2397 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2403 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2405 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2411 seq = read_seqcount_begin(>od->seq);
2412 ts->tv_sec = gtod->wall_time_sec;
2413 ns = gtod->clock.base_cycles;
2414 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2415 ns >>= gtod->clock.shift;
2416 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2418 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2424 /* returns true if host is using TSC based clocksource */
2425 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2427 /* checked again under seqlock below */
2428 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2431 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2435 /* returns true if host is using TSC based clocksource */
2436 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2439 /* checked again under seqlock below */
2440 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2443 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2449 * Assuming a stable TSC across physical CPUS, and a stable TSC
2450 * across virtual CPUs, the following condition is possible.
2451 * Each numbered line represents an event visible to both
2452 * CPUs at the next numbered event.
2454 * "timespecX" represents host monotonic time. "tscX" represents
2457 * VCPU0 on CPU0 | VCPU1 on CPU1
2459 * 1. read timespec0,tsc0
2460 * 2. | timespec1 = timespec0 + N
2462 * 3. transition to guest | transition to guest
2463 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2464 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2465 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2467 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2470 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2472 * - 0 < N - M => M < N
2474 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2475 * always the case (the difference between two distinct xtime instances
2476 * might be smaller then the difference between corresponding TSC reads,
2477 * when updating guest vcpus pvclock areas).
2479 * To avoid that problem, do not allow visibility of distinct
2480 * system_timestamp/tsc_timestamp values simultaneously: use a master
2481 * copy of host monotonic time values. Update that master copy
2484 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2488 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2490 #ifdef CONFIG_X86_64
2491 struct kvm_arch *ka = &kvm->arch;
2493 bool host_tsc_clocksource, vcpus_matched;
2495 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2496 atomic_read(&kvm->online_vcpus));
2499 * If the host uses TSC clock, then passthrough TSC as stable
2502 host_tsc_clocksource = kvm_get_time_and_clockread(
2503 &ka->master_kernel_ns,
2504 &ka->master_cycle_now);
2506 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2507 && !ka->backwards_tsc_observed
2508 && !ka->boot_vcpu_runs_old_kvmclock;
2510 if (ka->use_master_clock)
2511 atomic_set(&kvm_guest_has_master_clock, 1);
2513 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2514 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2519 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2521 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2524 static void kvm_gen_update_masterclock(struct kvm *kvm)
2526 #ifdef CONFIG_X86_64
2528 struct kvm_vcpu *vcpu;
2529 struct kvm_arch *ka = &kvm->arch;
2531 spin_lock(&ka->pvclock_gtod_sync_lock);
2532 kvm_make_mclock_inprogress_request(kvm);
2533 /* no guest entries from this point */
2534 pvclock_update_vm_gtod_copy(kvm);
2536 kvm_for_each_vcpu(i, vcpu, kvm)
2537 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2539 /* guest entries allowed */
2540 kvm_for_each_vcpu(i, vcpu, kvm)
2541 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2543 spin_unlock(&ka->pvclock_gtod_sync_lock);
2547 u64 get_kvmclock_ns(struct kvm *kvm)
2549 struct kvm_arch *ka = &kvm->arch;
2550 struct pvclock_vcpu_time_info hv_clock;
2553 spin_lock(&ka->pvclock_gtod_sync_lock);
2554 if (!ka->use_master_clock) {
2555 spin_unlock(&ka->pvclock_gtod_sync_lock);
2556 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2559 hv_clock.tsc_timestamp = ka->master_cycle_now;
2560 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2561 spin_unlock(&ka->pvclock_gtod_sync_lock);
2563 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2566 if (__this_cpu_read(cpu_tsc_khz)) {
2567 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2568 &hv_clock.tsc_shift,
2569 &hv_clock.tsc_to_system_mul);
2570 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2572 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2579 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2581 struct kvm_vcpu_arch *vcpu = &v->arch;
2582 struct pvclock_vcpu_time_info guest_hv_clock;
2584 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2585 &guest_hv_clock, sizeof(guest_hv_clock))))
2588 /* This VCPU is paused, but it's legal for a guest to read another
2589 * VCPU's kvmclock, so we really have to follow the specification where
2590 * it says that version is odd if data is being modified, and even after
2593 * Version field updates must be kept separate. This is because
2594 * kvm_write_guest_cached might use a "rep movs" instruction, and
2595 * writes within a string instruction are weakly ordered. So there
2596 * are three writes overall.
2598 * As a small optimization, only write the version field in the first
2599 * and third write. The vcpu->pv_time cache is still valid, because the
2600 * version field is the first in the struct.
2602 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2604 if (guest_hv_clock.version & 1)
2605 ++guest_hv_clock.version; /* first time write, random junk */
2607 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2608 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2610 sizeof(vcpu->hv_clock.version));
2614 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2615 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2617 if (vcpu->pvclock_set_guest_stopped_request) {
2618 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2619 vcpu->pvclock_set_guest_stopped_request = false;
2622 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2624 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2626 sizeof(vcpu->hv_clock));
2630 vcpu->hv_clock.version++;
2631 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2633 sizeof(vcpu->hv_clock.version));
2636 static int kvm_guest_time_update(struct kvm_vcpu *v)
2638 unsigned long flags, tgt_tsc_khz;
2639 struct kvm_vcpu_arch *vcpu = &v->arch;
2640 struct kvm_arch *ka = &v->kvm->arch;
2642 u64 tsc_timestamp, host_tsc;
2644 bool use_master_clock;
2650 * If the host uses TSC clock, then passthrough TSC as stable
2653 spin_lock(&ka->pvclock_gtod_sync_lock);
2654 use_master_clock = ka->use_master_clock;
2655 if (use_master_clock) {
2656 host_tsc = ka->master_cycle_now;
2657 kernel_ns = ka->master_kernel_ns;
2659 spin_unlock(&ka->pvclock_gtod_sync_lock);
2661 /* Keep irq disabled to prevent changes to the clock */
2662 local_irq_save(flags);
2663 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2664 if (unlikely(tgt_tsc_khz == 0)) {
2665 local_irq_restore(flags);
2666 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2669 if (!use_master_clock) {
2671 kernel_ns = get_kvmclock_base_ns();
2674 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2677 * We may have to catch up the TSC to match elapsed wall clock
2678 * time for two reasons, even if kvmclock is used.
2679 * 1) CPU could have been running below the maximum TSC rate
2680 * 2) Broken TSC compensation resets the base at each VCPU
2681 * entry to avoid unknown leaps of TSC even when running
2682 * again on the same CPU. This may cause apparent elapsed
2683 * time to disappear, and the guest to stand still or run
2686 if (vcpu->tsc_catchup) {
2687 u64 tsc = compute_guest_tsc(v, kernel_ns);
2688 if (tsc > tsc_timestamp) {
2689 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2690 tsc_timestamp = tsc;
2694 local_irq_restore(flags);
2696 /* With all the info we got, fill in the values */
2698 if (kvm_has_tsc_control)
2699 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2701 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2702 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2703 &vcpu->hv_clock.tsc_shift,
2704 &vcpu->hv_clock.tsc_to_system_mul);
2705 vcpu->hw_tsc_khz = tgt_tsc_khz;
2708 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2709 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2710 vcpu->last_guest_tsc = tsc_timestamp;
2712 /* If the host uses TSC clocksource, then it is stable */
2714 if (use_master_clock)
2715 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2717 vcpu->hv_clock.flags = pvclock_flags;
2719 if (vcpu->pv_time_enabled)
2720 kvm_setup_pvclock_page(v);
2721 if (v == kvm_get_vcpu(v->kvm, 0))
2722 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2727 * kvmclock updates which are isolated to a given vcpu, such as
2728 * vcpu->cpu migration, should not allow system_timestamp from
2729 * the rest of the vcpus to remain static. Otherwise ntp frequency
2730 * correction applies to one vcpu's system_timestamp but not
2733 * So in those cases, request a kvmclock update for all vcpus.
2734 * We need to rate-limit these requests though, as they can
2735 * considerably slow guests that have a large number of vcpus.
2736 * The time for a remote vcpu to update its kvmclock is bound
2737 * by the delay we use to rate-limit the updates.
2740 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2742 static void kvmclock_update_fn(struct work_struct *work)
2745 struct delayed_work *dwork = to_delayed_work(work);
2746 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2747 kvmclock_update_work);
2748 struct kvm *kvm = container_of(ka, struct kvm, arch);
2749 struct kvm_vcpu *vcpu;
2751 kvm_for_each_vcpu(i, vcpu, kvm) {
2752 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2753 kvm_vcpu_kick(vcpu);
2757 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2759 struct kvm *kvm = v->kvm;
2761 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2762 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2763 KVMCLOCK_UPDATE_DELAY);
2766 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2768 static void kvmclock_sync_fn(struct work_struct *work)
2770 struct delayed_work *dwork = to_delayed_work(work);
2771 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2772 kvmclock_sync_work);
2773 struct kvm *kvm = container_of(ka, struct kvm, arch);
2775 if (!kvmclock_periodic_sync)
2778 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2779 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2780 KVMCLOCK_SYNC_PERIOD);
2784 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2786 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2788 /* McStatusWrEn enabled? */
2789 if (guest_cpuid_is_amd_or_hygon(vcpu))
2790 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2795 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2797 u64 mcg_cap = vcpu->arch.mcg_cap;
2798 unsigned bank_num = mcg_cap & 0xff;
2799 u32 msr = msr_info->index;
2800 u64 data = msr_info->data;
2803 case MSR_IA32_MCG_STATUS:
2804 vcpu->arch.mcg_status = data;
2806 case MSR_IA32_MCG_CTL:
2807 if (!(mcg_cap & MCG_CTL_P) &&
2808 (data || !msr_info->host_initiated))
2810 if (data != 0 && data != ~(u64)0)
2812 vcpu->arch.mcg_ctl = data;
2815 if (msr >= MSR_IA32_MC0_CTL &&
2816 msr < MSR_IA32_MCx_CTL(bank_num)) {
2817 u32 offset = array_index_nospec(
2818 msr - MSR_IA32_MC0_CTL,
2819 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2821 /* only 0 or all 1s can be written to IA32_MCi_CTL
2822 * some Linux kernels though clear bit 10 in bank 4 to
2823 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2824 * this to avoid an uncatched #GP in the guest
2826 if ((offset & 0x3) == 0 &&
2827 data != 0 && (data | (1 << 10)) != ~(u64)0)
2831 if (!msr_info->host_initiated &&
2832 (offset & 0x3) == 1 && data != 0) {
2833 if (!can_set_mci_status(vcpu))
2837 vcpu->arch.mce_banks[offset] = data;
2845 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2847 struct kvm *kvm = vcpu->kvm;
2848 int lm = is_long_mode(vcpu);
2849 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2850 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2851 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2852 : kvm->arch.xen_hvm_config.blob_size_32;
2853 u32 page_num = data & ~PAGE_MASK;
2854 u64 page_addr = data & PAGE_MASK;
2857 if (page_num >= blob_size)
2860 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2862 return PTR_ERR(page);
2864 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) {
2871 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
2873 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
2875 return (vcpu->arch.apf.msr_en_val & mask) == mask;
2878 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2880 gpa_t gpa = data & ~0x3f;
2882 /* Bits 4:5 are reserved, Should be zero */
2886 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
2887 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
2890 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
2891 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
2894 if (!lapic_in_kernel(vcpu))
2895 return data ? 1 : 0;
2897 vcpu->arch.apf.msr_en_val = data;
2899 if (!kvm_pv_async_pf_enabled(vcpu)) {
2900 kvm_clear_async_pf_completion_queue(vcpu);
2901 kvm_async_pf_hash_reset(vcpu);
2905 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2909 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2910 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2912 kvm_async_pf_wakeup_all(vcpu);
2917 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
2919 /* Bits 8-63 are reserved */
2923 if (!lapic_in_kernel(vcpu))
2926 vcpu->arch.apf.msr_int_val = data;
2928 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
2933 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2935 vcpu->arch.pv_time_enabled = false;
2936 vcpu->arch.time = 0;
2939 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
2941 ++vcpu->stat.tlb_flush;
2942 kvm_x86_ops.tlb_flush_all(vcpu);
2945 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
2947 ++vcpu->stat.tlb_flush;
2948 kvm_x86_ops.tlb_flush_guest(vcpu);
2951 static void record_steal_time(struct kvm_vcpu *vcpu)
2953 struct kvm_host_map map;
2954 struct kvm_steal_time *st;
2956 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2959 /* -EAGAIN is returned in atomic context so we can just return. */
2960 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2961 &map, &vcpu->arch.st.cache, false))
2965 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2968 * Doing a TLB flush here, on the guest's behalf, can avoid
2971 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
2972 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2973 st->preempted & KVM_VCPU_FLUSH_TLB);
2974 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2975 kvm_vcpu_flush_tlb_guest(vcpu);
2978 vcpu->arch.st.preempted = 0;
2980 if (st->version & 1)
2981 st->version += 1; /* first time write, random junk */
2987 st->steal += current->sched_info.run_delay -
2988 vcpu->arch.st.last_steal;
2989 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2995 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2998 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3001 u32 msr = msr_info->index;
3002 u64 data = msr_info->data;
3005 case MSR_AMD64_NB_CFG:
3006 case MSR_IA32_UCODE_WRITE:
3007 case MSR_VM_HSAVE_PA:
3008 case MSR_AMD64_PATCH_LOADER:
3009 case MSR_AMD64_BU_CFG2:
3010 case MSR_AMD64_DC_CFG:
3011 case MSR_F15H_EX_CFG:
3014 case MSR_IA32_UCODE_REV:
3015 if (msr_info->host_initiated)
3016 vcpu->arch.microcode_version = data;
3018 case MSR_IA32_ARCH_CAPABILITIES:
3019 if (!msr_info->host_initiated)
3021 vcpu->arch.arch_capabilities = data;
3023 case MSR_IA32_PERF_CAPABILITIES: {
3024 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
3026 if (!msr_info->host_initiated)
3028 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent))
3030 if (data & ~msr_ent.data)
3033 vcpu->arch.perf_capabilities = data;
3038 return set_efer(vcpu, msr_info);
3040 data &= ~(u64)0x40; /* ignore flush filter disable */
3041 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3042 data &= ~(u64)0x8; /* ignore TLB cache disable */
3044 /* Handle McStatusWrEn */
3045 if (data == BIT_ULL(18)) {
3046 vcpu->arch.msr_hwcr = data;
3047 } else if (data != 0) {
3048 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3053 case MSR_FAM10H_MMIO_CONF_BASE:
3055 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3060 case MSR_IA32_DEBUGCTLMSR:
3062 /* We support the non-activated case already */
3064 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
3065 /* Values other than LBR and BTF are vendor-specific,
3066 thus reserved and should throw a #GP */
3068 } else if (report_ignored_msrs)
3069 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
3072 case 0x200 ... 0x2ff:
3073 return kvm_mtrr_set_msr(vcpu, msr, data);
3074 case MSR_IA32_APICBASE:
3075 return kvm_set_apic_base(vcpu, msr_info);
3076 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3077 return kvm_x2apic_msr_write(vcpu, msr, data);
3078 case MSR_IA32_TSCDEADLINE:
3079 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3081 case MSR_IA32_TSC_ADJUST:
3082 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3083 if (!msr_info->host_initiated) {
3084 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3085 adjust_tsc_offset_guest(vcpu, adj);
3087 vcpu->arch.ia32_tsc_adjust_msr = data;
3090 case MSR_IA32_MISC_ENABLE:
3091 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3092 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3093 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3095 vcpu->arch.ia32_misc_enable_msr = data;
3096 kvm_update_cpuid_runtime(vcpu);
3098 vcpu->arch.ia32_misc_enable_msr = data;
3101 case MSR_IA32_SMBASE:
3102 if (!msr_info->host_initiated)
3104 vcpu->arch.smbase = data;
3106 case MSR_IA32_POWER_CTL:
3107 vcpu->arch.msr_ia32_power_ctl = data;
3110 if (msr_info->host_initiated) {
3111 kvm_synchronize_tsc(vcpu, data);
3113 u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3114 adjust_tsc_offset_guest(vcpu, adj);
3115 vcpu->arch.ia32_tsc_adjust_msr += adj;
3119 if (!msr_info->host_initiated &&
3120 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3123 * KVM supports exposing PT to the guest, but does not support
3124 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3125 * XSAVES/XRSTORS to save/restore PT MSRs.
3127 if (data & ~supported_xss)
3129 vcpu->arch.ia32_xss = data;
3132 if (!msr_info->host_initiated)
3134 vcpu->arch.smi_count = data;
3136 case MSR_KVM_WALL_CLOCK_NEW:
3137 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3140 kvm_write_wall_clock(vcpu->kvm, data);
3142 case MSR_KVM_WALL_CLOCK:
3143 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3146 kvm_write_wall_clock(vcpu->kvm, data);
3148 case MSR_KVM_SYSTEM_TIME_NEW:
3149 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3152 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3154 case MSR_KVM_SYSTEM_TIME:
3155 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3158 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3160 case MSR_KVM_ASYNC_PF_EN:
3161 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3164 if (kvm_pv_enable_async_pf(vcpu, data))
3167 case MSR_KVM_ASYNC_PF_INT:
3168 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3171 if (kvm_pv_enable_async_pf_int(vcpu, data))
3174 case MSR_KVM_ASYNC_PF_ACK:
3175 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3178 vcpu->arch.apf.pageready_pending = false;
3179 kvm_check_async_pf_completion(vcpu);
3182 case MSR_KVM_STEAL_TIME:
3183 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3186 if (unlikely(!sched_info_on()))
3189 if (data & KVM_STEAL_RESERVED_MASK)
3192 vcpu->arch.st.msr_val = data;
3194 if (!(data & KVM_MSR_ENABLED))
3197 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3200 case MSR_KVM_PV_EOI_EN:
3201 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3204 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
3208 case MSR_KVM_POLL_CONTROL:
3209 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3212 /* only enable bit supported */
3213 if (data & (-1ULL << 1))
3216 vcpu->arch.msr_kvm_poll_control = data;
3219 case MSR_IA32_MCG_CTL:
3220 case MSR_IA32_MCG_STATUS:
3221 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3222 return set_msr_mce(vcpu, msr_info);
3224 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3225 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3228 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3229 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3230 if (kvm_pmu_is_valid_msr(vcpu, msr))
3231 return kvm_pmu_set_msr(vcpu, msr_info);
3233 if (pr || data != 0)
3234 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3235 "0x%x data 0x%llx\n", msr, data);
3237 case MSR_K7_CLK_CTL:
3239 * Ignore all writes to this no longer documented MSR.
3240 * Writes are only relevant for old K7 processors,
3241 * all pre-dating SVM, but a recommended workaround from
3242 * AMD for these chips. It is possible to specify the
3243 * affected processor models on the command line, hence
3244 * the need to ignore the workaround.
3247 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3248 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3249 case HV_X64_MSR_SYNDBG_OPTIONS:
3250 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3251 case HV_X64_MSR_CRASH_CTL:
3252 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3253 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3254 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3255 case HV_X64_MSR_TSC_EMULATION_STATUS:
3256 return kvm_hv_set_msr_common(vcpu, msr, data,
3257 msr_info->host_initiated);
3258 case MSR_IA32_BBL_CR_CTL3:
3259 /* Drop writes to this legacy MSR -- see rdmsr
3260 * counterpart for further detail.
3262 if (report_ignored_msrs)
3263 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3266 case MSR_AMD64_OSVW_ID_LENGTH:
3267 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3269 vcpu->arch.osvw.length = data;
3271 case MSR_AMD64_OSVW_STATUS:
3272 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3274 vcpu->arch.osvw.status = data;
3276 case MSR_PLATFORM_INFO:
3277 if (!msr_info->host_initiated ||
3278 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3279 cpuid_fault_enabled(vcpu)))
3281 vcpu->arch.msr_platform_info = data;
3283 case MSR_MISC_FEATURES_ENABLES:
3284 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3285 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3286 !supports_cpuid_fault(vcpu)))
3288 vcpu->arch.msr_misc_features_enables = data;
3291 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
3292 return xen_hvm_config(vcpu, data);
3293 if (kvm_pmu_is_valid_msr(vcpu, msr))
3294 return kvm_pmu_set_msr(vcpu, msr_info);
3295 return KVM_MSR_RET_INVALID;
3299 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3301 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3304 u64 mcg_cap = vcpu->arch.mcg_cap;
3305 unsigned bank_num = mcg_cap & 0xff;
3308 case MSR_IA32_P5_MC_ADDR:
3309 case MSR_IA32_P5_MC_TYPE:
3312 case MSR_IA32_MCG_CAP:
3313 data = vcpu->arch.mcg_cap;
3315 case MSR_IA32_MCG_CTL:
3316 if (!(mcg_cap & MCG_CTL_P) && !host)
3318 data = vcpu->arch.mcg_ctl;
3320 case MSR_IA32_MCG_STATUS:
3321 data = vcpu->arch.mcg_status;
3324 if (msr >= MSR_IA32_MC0_CTL &&
3325 msr < MSR_IA32_MCx_CTL(bank_num)) {
3326 u32 offset = array_index_nospec(
3327 msr - MSR_IA32_MC0_CTL,
3328 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3330 data = vcpu->arch.mce_banks[offset];
3339 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3341 switch (msr_info->index) {
3342 case MSR_IA32_PLATFORM_ID:
3343 case MSR_IA32_EBL_CR_POWERON:
3344 case MSR_IA32_DEBUGCTLMSR:
3345 case MSR_IA32_LASTBRANCHFROMIP:
3346 case MSR_IA32_LASTBRANCHTOIP:
3347 case MSR_IA32_LASTINTFROMIP:
3348 case MSR_IA32_LASTINTTOIP:
3350 case MSR_K8_TSEG_ADDR:
3351 case MSR_K8_TSEG_MASK:
3352 case MSR_VM_HSAVE_PA:
3353 case MSR_K8_INT_PENDING_MSG:
3354 case MSR_AMD64_NB_CFG:
3355 case MSR_FAM10H_MMIO_CONF_BASE:
3356 case MSR_AMD64_BU_CFG2:
3357 case MSR_IA32_PERF_CTL:
3358 case MSR_AMD64_DC_CFG:
3359 case MSR_F15H_EX_CFG:
3361 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3362 * limit) MSRs. Just return 0, as we do not want to expose the host
3363 * data here. Do not conditionalize this on CPUID, as KVM does not do
3364 * so for existing CPU-specific MSRs.
3366 case MSR_RAPL_POWER_UNIT:
3367 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3368 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3369 case MSR_PKG_ENERGY_STATUS: /* Total package */
3370 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3373 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3374 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3375 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3376 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3377 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3378 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3379 return kvm_pmu_get_msr(vcpu, msr_info);
3382 case MSR_IA32_UCODE_REV:
3383 msr_info->data = vcpu->arch.microcode_version;
3385 case MSR_IA32_ARCH_CAPABILITIES:
3386 if (!msr_info->host_initiated &&
3387 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3389 msr_info->data = vcpu->arch.arch_capabilities;
3391 case MSR_IA32_PERF_CAPABILITIES:
3392 if (!msr_info->host_initiated &&
3393 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3395 msr_info->data = vcpu->arch.perf_capabilities;
3397 case MSR_IA32_POWER_CTL:
3398 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3400 case MSR_IA32_TSC: {
3402 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
3403 * even when not intercepted. AMD manual doesn't explicitly
3404 * state this but appears to behave the same.
3406 * On userspace reads and writes, however, we unconditionally
3407 * return L1's TSC value to ensure backwards-compatible
3408 * behavior for migration.
3410 u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset :
3411 vcpu->arch.tsc_offset;
3413 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset;
3417 case 0x200 ... 0x2ff:
3418 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3419 case 0xcd: /* fsb frequency */
3423 * MSR_EBC_FREQUENCY_ID
3424 * Conservative value valid for even the basic CPU models.
3425 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3426 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3427 * and 266MHz for model 3, or 4. Set Core Clock
3428 * Frequency to System Bus Frequency Ratio to 1 (bits
3429 * 31:24) even though these are only valid for CPU
3430 * models > 2, however guests may end up dividing or
3431 * multiplying by zero otherwise.
3433 case MSR_EBC_FREQUENCY_ID:
3434 msr_info->data = 1 << 24;
3436 case MSR_IA32_APICBASE:
3437 msr_info->data = kvm_get_apic_base(vcpu);
3439 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3440 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3441 case MSR_IA32_TSCDEADLINE:
3442 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3444 case MSR_IA32_TSC_ADJUST:
3445 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3447 case MSR_IA32_MISC_ENABLE:
3448 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3450 case MSR_IA32_SMBASE:
3451 if (!msr_info->host_initiated)
3453 msr_info->data = vcpu->arch.smbase;
3456 msr_info->data = vcpu->arch.smi_count;
3458 case MSR_IA32_PERF_STATUS:
3459 /* TSC increment by tick */
3460 msr_info->data = 1000ULL;
3461 /* CPU multiplier */
3462 msr_info->data |= (((uint64_t)4ULL) << 40);
3465 msr_info->data = vcpu->arch.efer;
3467 case MSR_KVM_WALL_CLOCK:
3468 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3471 msr_info->data = vcpu->kvm->arch.wall_clock;
3473 case MSR_KVM_WALL_CLOCK_NEW:
3474 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3477 msr_info->data = vcpu->kvm->arch.wall_clock;
3479 case MSR_KVM_SYSTEM_TIME:
3480 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3483 msr_info->data = vcpu->arch.time;
3485 case MSR_KVM_SYSTEM_TIME_NEW:
3486 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3489 msr_info->data = vcpu->arch.time;
3491 case MSR_KVM_ASYNC_PF_EN:
3492 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3495 msr_info->data = vcpu->arch.apf.msr_en_val;
3497 case MSR_KVM_ASYNC_PF_INT:
3498 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3501 msr_info->data = vcpu->arch.apf.msr_int_val;
3503 case MSR_KVM_ASYNC_PF_ACK:
3504 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3509 case MSR_KVM_STEAL_TIME:
3510 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3513 msr_info->data = vcpu->arch.st.msr_val;
3515 case MSR_KVM_PV_EOI_EN:
3516 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3519 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3521 case MSR_KVM_POLL_CONTROL:
3522 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3525 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3527 case MSR_IA32_P5_MC_ADDR:
3528 case MSR_IA32_P5_MC_TYPE:
3529 case MSR_IA32_MCG_CAP:
3530 case MSR_IA32_MCG_CTL:
3531 case MSR_IA32_MCG_STATUS:
3532 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3533 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3534 msr_info->host_initiated);
3536 if (!msr_info->host_initiated &&
3537 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3539 msr_info->data = vcpu->arch.ia32_xss;
3541 case MSR_K7_CLK_CTL:
3543 * Provide expected ramp-up count for K7. All other
3544 * are set to zero, indicating minimum divisors for
3547 * This prevents guest kernels on AMD host with CPU
3548 * type 6, model 8 and higher from exploding due to
3549 * the rdmsr failing.
3551 msr_info->data = 0x20000000;
3553 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3554 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3555 case HV_X64_MSR_SYNDBG_OPTIONS:
3556 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3557 case HV_X64_MSR_CRASH_CTL:
3558 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3559 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3560 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3561 case HV_X64_MSR_TSC_EMULATION_STATUS:
3562 return kvm_hv_get_msr_common(vcpu,
3563 msr_info->index, &msr_info->data,
3564 msr_info->host_initiated);
3565 case MSR_IA32_BBL_CR_CTL3:
3566 /* This legacy MSR exists but isn't fully documented in current
3567 * silicon. It is however accessed by winxp in very narrow
3568 * scenarios where it sets bit #19, itself documented as
3569 * a "reserved" bit. Best effort attempt to source coherent
3570 * read data here should the balance of the register be
3571 * interpreted by the guest:
3573 * L2 cache control register 3: 64GB range, 256KB size,
3574 * enabled, latency 0x1, configured
3576 msr_info->data = 0xbe702111;
3578 case MSR_AMD64_OSVW_ID_LENGTH:
3579 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3581 msr_info->data = vcpu->arch.osvw.length;
3583 case MSR_AMD64_OSVW_STATUS:
3584 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3586 msr_info->data = vcpu->arch.osvw.status;
3588 case MSR_PLATFORM_INFO:
3589 if (!msr_info->host_initiated &&
3590 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3592 msr_info->data = vcpu->arch.msr_platform_info;
3594 case MSR_MISC_FEATURES_ENABLES:
3595 msr_info->data = vcpu->arch.msr_misc_features_enables;
3598 msr_info->data = vcpu->arch.msr_hwcr;
3601 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3602 return kvm_pmu_get_msr(vcpu, msr_info);
3603 return KVM_MSR_RET_INVALID;
3607 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3610 * Read or write a bunch of msrs. All parameters are kernel addresses.
3612 * @return number of msrs set successfully.
3614 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3615 struct kvm_msr_entry *entries,
3616 int (*do_msr)(struct kvm_vcpu *vcpu,
3617 unsigned index, u64 *data))
3621 for (i = 0; i < msrs->nmsrs; ++i)
3622 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3629 * Read or write a bunch of msrs. Parameters are user addresses.
3631 * @return number of msrs set successfully.
3633 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3634 int (*do_msr)(struct kvm_vcpu *vcpu,
3635 unsigned index, u64 *data),
3638 struct kvm_msrs msrs;
3639 struct kvm_msr_entry *entries;
3644 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3648 if (msrs.nmsrs >= MAX_IO_MSRS)
3651 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3652 entries = memdup_user(user_msrs->entries, size);
3653 if (IS_ERR(entries)) {
3654 r = PTR_ERR(entries);
3658 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3663 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3674 static inline bool kvm_can_mwait_in_guest(void)
3676 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3677 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3678 boot_cpu_has(X86_FEATURE_ARAT);
3681 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3686 case KVM_CAP_IRQCHIP:
3688 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3689 case KVM_CAP_SET_TSS_ADDR:
3690 case KVM_CAP_EXT_CPUID:
3691 case KVM_CAP_EXT_EMUL_CPUID:
3692 case KVM_CAP_CLOCKSOURCE:
3694 case KVM_CAP_NOP_IO_DELAY:
3695 case KVM_CAP_MP_STATE:
3696 case KVM_CAP_SYNC_MMU:
3697 case KVM_CAP_USER_NMI:
3698 case KVM_CAP_REINJECT_CONTROL:
3699 case KVM_CAP_IRQ_INJECT_STATUS:
3700 case KVM_CAP_IOEVENTFD:
3701 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3703 case KVM_CAP_PIT_STATE2:
3704 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3705 case KVM_CAP_XEN_HVM:
3706 case KVM_CAP_VCPU_EVENTS:
3707 case KVM_CAP_HYPERV:
3708 case KVM_CAP_HYPERV_VAPIC:
3709 case KVM_CAP_HYPERV_SPIN:
3710 case KVM_CAP_HYPERV_SYNIC:
3711 case KVM_CAP_HYPERV_SYNIC2:
3712 case KVM_CAP_HYPERV_VP_INDEX:
3713 case KVM_CAP_HYPERV_EVENTFD:
3714 case KVM_CAP_HYPERV_TLBFLUSH:
3715 case KVM_CAP_HYPERV_SEND_IPI:
3716 case KVM_CAP_HYPERV_CPUID:
3717 case KVM_CAP_PCI_SEGMENT:
3718 case KVM_CAP_DEBUGREGS:
3719 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3721 case KVM_CAP_ASYNC_PF:
3722 case KVM_CAP_ASYNC_PF_INT:
3723 case KVM_CAP_GET_TSC_KHZ:
3724 case KVM_CAP_KVMCLOCK_CTRL:
3725 case KVM_CAP_READONLY_MEM:
3726 case KVM_CAP_HYPERV_TIME:
3727 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3728 case KVM_CAP_TSC_DEADLINE_TIMER:
3729 case KVM_CAP_DISABLE_QUIRKS:
3730 case KVM_CAP_SET_BOOT_CPU_ID:
3731 case KVM_CAP_SPLIT_IRQCHIP:
3732 case KVM_CAP_IMMEDIATE_EXIT:
3733 case KVM_CAP_PMU_EVENT_FILTER:
3734 case KVM_CAP_GET_MSR_FEATURES:
3735 case KVM_CAP_MSR_PLATFORM_INFO:
3736 case KVM_CAP_EXCEPTION_PAYLOAD:
3737 case KVM_CAP_SET_GUEST_DEBUG:
3738 case KVM_CAP_LAST_CPU:
3739 case KVM_CAP_X86_USER_SPACE_MSR:
3740 case KVM_CAP_X86_MSR_FILTER:
3741 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
3744 case KVM_CAP_SYNC_REGS:
3745 r = KVM_SYNC_X86_VALID_FIELDS;
3747 case KVM_CAP_ADJUST_CLOCK:
3748 r = KVM_CLOCK_TSC_STABLE;
3750 case KVM_CAP_X86_DISABLE_EXITS:
3751 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3752 KVM_X86_DISABLE_EXITS_CSTATE;
3753 if(kvm_can_mwait_in_guest())
3754 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3756 case KVM_CAP_X86_SMM:
3757 /* SMBASE is usually relocated above 1M on modern chipsets,
3758 * and SMM handlers might indeed rely on 4G segment limits,
3759 * so do not report SMM to be available if real mode is
3760 * emulated via vm86 mode. Still, do not go to great lengths
3761 * to avoid userspace's usage of the feature, because it is a
3762 * fringe case that is not enabled except via specific settings
3763 * of the module parameters.
3765 r = kvm_x86_ops.has_emulated_msr(MSR_IA32_SMBASE);
3768 r = !kvm_x86_ops.cpu_has_accelerated_tpr();
3770 case KVM_CAP_NR_VCPUS:
3771 r = KVM_SOFT_MAX_VCPUS;
3773 case KVM_CAP_MAX_VCPUS:
3776 case KVM_CAP_MAX_VCPU_ID:
3777 r = KVM_MAX_VCPU_ID;
3779 case KVM_CAP_PV_MMU: /* obsolete */
3783 r = KVM_MAX_MCE_BANKS;
3786 r = boot_cpu_has(X86_FEATURE_XSAVE);
3788 case KVM_CAP_TSC_CONTROL:
3789 r = kvm_has_tsc_control;
3791 case KVM_CAP_X2APIC_API:
3792 r = KVM_X2APIC_API_VALID_FLAGS;
3794 case KVM_CAP_NESTED_STATE:
3795 r = kvm_x86_ops.nested_ops->get_state ?
3796 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
3798 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3799 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3801 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3802 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
3804 case KVM_CAP_SMALLER_MAXPHYADDR:
3805 r = (int) allow_smaller_maxphyaddr;
3807 case KVM_CAP_STEAL_TIME:
3808 r = sched_info_on();
3817 long kvm_arch_dev_ioctl(struct file *filp,
3818 unsigned int ioctl, unsigned long arg)
3820 void __user *argp = (void __user *)arg;
3824 case KVM_GET_MSR_INDEX_LIST: {
3825 struct kvm_msr_list __user *user_msr_list = argp;
3826 struct kvm_msr_list msr_list;
3830 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3833 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3834 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3837 if (n < msr_list.nmsrs)
3840 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3841 num_msrs_to_save * sizeof(u32)))
3843 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3845 num_emulated_msrs * sizeof(u32)))
3850 case KVM_GET_SUPPORTED_CPUID:
3851 case KVM_GET_EMULATED_CPUID: {
3852 struct kvm_cpuid2 __user *cpuid_arg = argp;
3853 struct kvm_cpuid2 cpuid;
3856 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3859 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3865 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3870 case KVM_X86_GET_MCE_CAP_SUPPORTED:
3872 if (copy_to_user(argp, &kvm_mce_cap_supported,
3873 sizeof(kvm_mce_cap_supported)))
3877 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3878 struct kvm_msr_list __user *user_msr_list = argp;
3879 struct kvm_msr_list msr_list;
3883 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3886 msr_list.nmsrs = num_msr_based_features;
3887 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3890 if (n < msr_list.nmsrs)
3893 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3894 num_msr_based_features * sizeof(u32)))
3900 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3910 static void wbinvd_ipi(void *garbage)
3915 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3917 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3920 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3922 /* Address WBINVD may be executed by guest */
3923 if (need_emulate_wbinvd(vcpu)) {
3924 if (kvm_x86_ops.has_wbinvd_exit())
3925 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3926 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3927 smp_call_function_single(vcpu->cpu,
3928 wbinvd_ipi, NULL, 1);
3931 kvm_x86_ops.vcpu_load(vcpu, cpu);
3933 /* Save host pkru register if supported */
3934 vcpu->arch.host_pkru = read_pkru();
3936 /* Apply any externally detected TSC adjustments (due to suspend) */
3937 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3938 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3939 vcpu->arch.tsc_offset_adjustment = 0;
3940 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3943 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3944 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3945 rdtsc() - vcpu->arch.last_host_tsc;
3947 mark_tsc_unstable("KVM discovered backwards TSC");
3949 if (kvm_check_tsc_unstable()) {
3950 u64 offset = kvm_compute_tsc_offset(vcpu,
3951 vcpu->arch.last_guest_tsc);
3952 kvm_vcpu_write_tsc_offset(vcpu, offset);
3953 vcpu->arch.tsc_catchup = 1;
3956 if (kvm_lapic_hv_timer_in_use(vcpu))
3957 kvm_lapic_restart_hv_timer(vcpu);
3960 * On a host with synchronized TSC, there is no need to update
3961 * kvmclock on vcpu->cpu migration
3963 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3964 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3965 if (vcpu->cpu != cpu)
3966 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3970 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3973 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3975 struct kvm_host_map map;
3976 struct kvm_steal_time *st;
3978 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3981 if (vcpu->arch.st.preempted)
3984 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3985 &vcpu->arch.st.cache, true))
3989 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
3991 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
3993 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
3996 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4000 if (vcpu->preempted)
4001 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu);
4004 * Disable page faults because we're in atomic context here.
4005 * kvm_write_guest_offset_cached() would call might_fault()
4006 * that relies on pagefault_disable() to tell if there's a
4007 * bug. NOTE: the write to guest memory may not go through if
4008 * during postcopy live migration or if there's heavy guest
4011 pagefault_disable();
4013 * kvm_memslots() will be called by
4014 * kvm_write_guest_offset_cached() so take the srcu lock.
4016 idx = srcu_read_lock(&vcpu->kvm->srcu);
4017 kvm_steal_time_set_preempted(vcpu);
4018 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4020 kvm_x86_ops.vcpu_put(vcpu);
4021 vcpu->arch.last_host_tsc = rdtsc();
4023 * If userspace has set any breakpoints or watchpoints, dr6 is restored
4024 * on every vmexit, but if not, we might have a stale dr6 from the
4025 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
4030 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4031 struct kvm_lapic_state *s)
4033 if (vcpu->arch.apicv_active)
4034 kvm_x86_ops.sync_pir_to_irr(vcpu);
4036 return kvm_apic_get_state(vcpu, s);
4039 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4040 struct kvm_lapic_state *s)
4044 r = kvm_apic_set_state(vcpu, s);
4047 update_cr8_intercept(vcpu);
4052 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4054 return (!lapic_in_kernel(vcpu) ||
4055 kvm_apic_accept_pic_intr(vcpu));
4059 * if userspace requested an interrupt window, check that the
4060 * interrupt window is open.
4062 * No need to exit to userspace if we already have an interrupt queued.
4064 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4066 return kvm_arch_interrupt_allowed(vcpu) &&
4067 !kvm_cpu_has_interrupt(vcpu) &&
4068 !kvm_event_needs_reinjection(vcpu) &&
4069 kvm_cpu_accept_dm_intr(vcpu);
4072 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4073 struct kvm_interrupt *irq)
4075 if (irq->irq >= KVM_NR_INTERRUPTS)
4078 if (!irqchip_in_kernel(vcpu->kvm)) {
4079 kvm_queue_interrupt(vcpu, irq->irq, false);
4080 kvm_make_request(KVM_REQ_EVENT, vcpu);
4085 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4086 * fail for in-kernel 8259.
4088 if (pic_in_kernel(vcpu->kvm))
4091 if (vcpu->arch.pending_external_vector != -1)
4094 vcpu->arch.pending_external_vector = irq->irq;
4095 kvm_make_request(KVM_REQ_EVENT, vcpu);
4099 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4101 kvm_inject_nmi(vcpu);
4106 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
4108 kvm_make_request(KVM_REQ_SMI, vcpu);
4113 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4114 struct kvm_tpr_access_ctl *tac)
4118 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4122 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4126 unsigned bank_num = mcg_cap & 0xff, bank;
4129 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4131 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
4134 vcpu->arch.mcg_cap = mcg_cap;
4135 /* Init IA32_MCG_CTL to all 1s */
4136 if (mcg_cap & MCG_CTL_P)
4137 vcpu->arch.mcg_ctl = ~(u64)0;
4138 /* Init IA32_MCi_CTL to all 1s */
4139 for (bank = 0; bank < bank_num; bank++)
4140 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4142 kvm_x86_ops.setup_mce(vcpu);
4147 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4148 struct kvm_x86_mce *mce)
4150 u64 mcg_cap = vcpu->arch.mcg_cap;
4151 unsigned bank_num = mcg_cap & 0xff;
4152 u64 *banks = vcpu->arch.mce_banks;
4154 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
4157 * if IA32_MCG_CTL is not all 1s, the uncorrected error
4158 * reporting is disabled
4160 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
4161 vcpu->arch.mcg_ctl != ~(u64)0)
4163 banks += 4 * mce->bank;
4165 * if IA32_MCi_CTL is not all 1s, the uncorrected error
4166 * reporting is disabled for the bank
4168 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
4170 if (mce->status & MCI_STATUS_UC) {
4171 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
4172 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
4173 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4176 if (banks[1] & MCI_STATUS_VAL)
4177 mce->status |= MCI_STATUS_OVER;
4178 banks[2] = mce->addr;
4179 banks[3] = mce->misc;
4180 vcpu->arch.mcg_status = mce->mcg_status;
4181 banks[1] = mce->status;
4182 kvm_queue_exception(vcpu, MC_VECTOR);
4183 } else if (!(banks[1] & MCI_STATUS_VAL)
4184 || !(banks[1] & MCI_STATUS_UC)) {
4185 if (banks[1] & MCI_STATUS_VAL)
4186 mce->status |= MCI_STATUS_OVER;
4187 banks[2] = mce->addr;
4188 banks[3] = mce->misc;
4189 banks[1] = mce->status;
4191 banks[1] |= MCI_STATUS_OVER;
4195 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
4196 struct kvm_vcpu_events *events)
4201 * In guest mode, payload delivery should be deferred,
4202 * so that the L1 hypervisor can intercept #PF before
4203 * CR2 is modified (or intercept #DB before DR6 is
4204 * modified under nVMX). Unless the per-VM capability,
4205 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
4206 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
4207 * opportunistically defer the exception payload, deliver it if the
4208 * capability hasn't been requested before processing a
4209 * KVM_GET_VCPU_EVENTS.
4211 if (!vcpu->kvm->arch.exception_payload_enabled &&
4212 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
4213 kvm_deliver_exception_payload(vcpu);
4216 * The API doesn't provide the instruction length for software
4217 * exceptions, so don't report them. As long as the guest RIP
4218 * isn't advanced, we should expect to encounter the exception
4221 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
4222 events->exception.injected = 0;
4223 events->exception.pending = 0;
4225 events->exception.injected = vcpu->arch.exception.injected;
4226 events->exception.pending = vcpu->arch.exception.pending;
4228 * For ABI compatibility, deliberately conflate
4229 * pending and injected exceptions when
4230 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
4232 if (!vcpu->kvm->arch.exception_payload_enabled)
4233 events->exception.injected |=
4234 vcpu->arch.exception.pending;
4236 events->exception.nr = vcpu->arch.exception.nr;
4237 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
4238 events->exception.error_code = vcpu->arch.exception.error_code;
4239 events->exception_has_payload = vcpu->arch.exception.has_payload;
4240 events->exception_payload = vcpu->arch.exception.payload;
4242 events->interrupt.injected =
4243 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
4244 events->interrupt.nr = vcpu->arch.interrupt.nr;
4245 events->interrupt.soft = 0;
4246 events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
4248 events->nmi.injected = vcpu->arch.nmi_injected;
4249 events->nmi.pending = vcpu->arch.nmi_pending != 0;
4250 events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu);
4251 events->nmi.pad = 0;
4253 events->sipi_vector = 0; /* never valid when reporting to user space */
4255 events->smi.smm = is_smm(vcpu);
4256 events->smi.pending = vcpu->arch.smi_pending;
4257 events->smi.smm_inside_nmi =
4258 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
4259 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
4261 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
4262 | KVM_VCPUEVENT_VALID_SHADOW
4263 | KVM_VCPUEVENT_VALID_SMM);
4264 if (vcpu->kvm->arch.exception_payload_enabled)
4265 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4267 memset(&events->reserved, 0, sizeof(events->reserved));
4270 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
4272 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4273 struct kvm_vcpu_events *events)
4275 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4276 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4277 | KVM_VCPUEVENT_VALID_SHADOW
4278 | KVM_VCPUEVENT_VALID_SMM
4279 | KVM_VCPUEVENT_VALID_PAYLOAD))
4282 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4283 if (!vcpu->kvm->arch.exception_payload_enabled)
4285 if (events->exception.pending)
4286 events->exception.injected = 0;
4288 events->exception_has_payload = 0;
4290 events->exception.pending = 0;
4291 events->exception_has_payload = 0;
4294 if ((events->exception.injected || events->exception.pending) &&
4295 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4298 /* INITs are latched while in SMM */
4299 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4300 (events->smi.smm || events->smi.pending) &&
4301 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4305 vcpu->arch.exception.injected = events->exception.injected;
4306 vcpu->arch.exception.pending = events->exception.pending;
4307 vcpu->arch.exception.nr = events->exception.nr;
4308 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4309 vcpu->arch.exception.error_code = events->exception.error_code;
4310 vcpu->arch.exception.has_payload = events->exception_has_payload;
4311 vcpu->arch.exception.payload = events->exception_payload;
4313 vcpu->arch.interrupt.injected = events->interrupt.injected;
4314 vcpu->arch.interrupt.nr = events->interrupt.nr;
4315 vcpu->arch.interrupt.soft = events->interrupt.soft;
4316 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4317 kvm_x86_ops.set_interrupt_shadow(vcpu,
4318 events->interrupt.shadow);
4320 vcpu->arch.nmi_injected = events->nmi.injected;
4321 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4322 vcpu->arch.nmi_pending = events->nmi.pending;
4323 kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked);
4325 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4326 lapic_in_kernel(vcpu))
4327 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4329 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4330 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4331 if (events->smi.smm)
4332 vcpu->arch.hflags |= HF_SMM_MASK;
4334 vcpu->arch.hflags &= ~HF_SMM_MASK;
4335 kvm_smm_changed(vcpu);
4338 vcpu->arch.smi_pending = events->smi.pending;
4340 if (events->smi.smm) {
4341 if (events->smi.smm_inside_nmi)
4342 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4344 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4347 if (lapic_in_kernel(vcpu)) {
4348 if (events->smi.latched_init)
4349 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4351 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4355 kvm_make_request(KVM_REQ_EVENT, vcpu);
4360 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4361 struct kvm_debugregs *dbgregs)
4365 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4366 kvm_get_dr(vcpu, 6, &val);
4368 dbgregs->dr7 = vcpu->arch.dr7;
4370 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4373 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4374 struct kvm_debugregs *dbgregs)
4379 if (dbgregs->dr6 & ~0xffffffffull)
4381 if (dbgregs->dr7 & ~0xffffffffull)
4384 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4385 kvm_update_dr0123(vcpu);
4386 vcpu->arch.dr6 = dbgregs->dr6;
4387 vcpu->arch.dr7 = dbgregs->dr7;
4388 kvm_update_dr7(vcpu);
4393 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4395 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4397 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4398 u64 xstate_bv = xsave->header.xfeatures;
4402 * Copy legacy XSAVE area, to avoid complications with CPUID
4403 * leaves 0 and 1 in the loop below.
4405 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4408 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4409 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4412 * Copy each region from the possibly compacted offset to the
4413 * non-compacted offset.
4415 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4417 u64 xfeature_mask = valid & -valid;
4418 int xfeature_nr = fls64(xfeature_mask) - 1;
4419 void *src = get_xsave_addr(xsave, xfeature_nr);
4422 u32 size, offset, ecx, edx;
4423 cpuid_count(XSTATE_CPUID, xfeature_nr,
4424 &size, &offset, &ecx, &edx);
4425 if (xfeature_nr == XFEATURE_PKRU)
4426 memcpy(dest + offset, &vcpu->arch.pkru,
4427 sizeof(vcpu->arch.pkru));
4429 memcpy(dest + offset, src, size);
4433 valid -= xfeature_mask;
4437 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4439 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4440 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4444 * Copy legacy XSAVE area, to avoid complications with CPUID
4445 * leaves 0 and 1 in the loop below.
4447 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4449 /* Set XSTATE_BV and possibly XCOMP_BV. */
4450 xsave->header.xfeatures = xstate_bv;
4451 if (boot_cpu_has(X86_FEATURE_XSAVES))
4452 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4455 * Copy each region from the non-compacted offset to the
4456 * possibly compacted offset.
4458 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4460 u64 xfeature_mask = valid & -valid;
4461 int xfeature_nr = fls64(xfeature_mask) - 1;
4462 void *dest = get_xsave_addr(xsave, xfeature_nr);
4465 u32 size, offset, ecx, edx;
4466 cpuid_count(XSTATE_CPUID, xfeature_nr,
4467 &size, &offset, &ecx, &edx);
4468 if (xfeature_nr == XFEATURE_PKRU)
4469 memcpy(&vcpu->arch.pkru, src + offset,
4470 sizeof(vcpu->arch.pkru));
4472 memcpy(dest, src + offset, size);
4475 valid -= xfeature_mask;
4479 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4480 struct kvm_xsave *guest_xsave)
4482 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4483 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4484 fill_xsave((u8 *) guest_xsave->region, vcpu);
4486 memcpy(guest_xsave->region,
4487 &vcpu->arch.guest_fpu->state.fxsave,
4488 sizeof(struct fxregs_state));
4489 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4490 XFEATURE_MASK_FPSSE;
4494 #define XSAVE_MXCSR_OFFSET 24
4496 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4497 struct kvm_xsave *guest_xsave)
4500 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4501 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4503 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4505 * Here we allow setting states that are not present in
4506 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4507 * with old userspace.
4509 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4511 load_xsave(vcpu, (u8 *)guest_xsave->region);
4513 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4514 mxcsr & ~mxcsr_feature_mask)
4516 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4517 guest_xsave->region, sizeof(struct fxregs_state));
4522 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4523 struct kvm_xcrs *guest_xcrs)
4525 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4526 guest_xcrs->nr_xcrs = 0;
4530 guest_xcrs->nr_xcrs = 1;
4531 guest_xcrs->flags = 0;
4532 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4533 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4536 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4537 struct kvm_xcrs *guest_xcrs)
4541 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4544 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4547 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4548 /* Only support XCR0 currently */
4549 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4550 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4551 guest_xcrs->xcrs[i].value);
4560 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4561 * stopped by the hypervisor. This function will be called from the host only.
4562 * EINVAL is returned when the host attempts to set the flag for a guest that
4563 * does not support pv clocks.
4565 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4567 if (!vcpu->arch.pv_time_enabled)
4569 vcpu->arch.pvclock_set_guest_stopped_request = true;
4570 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4574 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4575 struct kvm_enable_cap *cap)
4578 uint16_t vmcs_version;
4579 void __user *user_ptr;
4585 case KVM_CAP_HYPERV_SYNIC2:
4590 case KVM_CAP_HYPERV_SYNIC:
4591 if (!irqchip_in_kernel(vcpu->kvm))
4593 return kvm_hv_activate_synic(vcpu, cap->cap ==
4594 KVM_CAP_HYPERV_SYNIC2);
4595 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4596 if (!kvm_x86_ops.nested_ops->enable_evmcs)
4598 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
4600 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4601 if (copy_to_user(user_ptr, &vmcs_version,
4602 sizeof(vmcs_version)))
4606 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4607 if (!kvm_x86_ops.enable_direct_tlbflush)
4610 return kvm_x86_ops.enable_direct_tlbflush(vcpu);
4612 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4613 vcpu->arch.pv_cpuid.enforce = cap->args[0];
4614 if (vcpu->arch.pv_cpuid.enforce)
4615 kvm_update_pv_runtime(vcpu);
4624 long kvm_arch_vcpu_ioctl(struct file *filp,
4625 unsigned int ioctl, unsigned long arg)
4627 struct kvm_vcpu *vcpu = filp->private_data;
4628 void __user *argp = (void __user *)arg;
4631 struct kvm_lapic_state *lapic;
4632 struct kvm_xsave *xsave;
4633 struct kvm_xcrs *xcrs;
4641 case KVM_GET_LAPIC: {
4643 if (!lapic_in_kernel(vcpu))
4645 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4646 GFP_KERNEL_ACCOUNT);
4651 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4655 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4660 case KVM_SET_LAPIC: {
4662 if (!lapic_in_kernel(vcpu))
4664 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4665 if (IS_ERR(u.lapic)) {
4666 r = PTR_ERR(u.lapic);
4670 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4673 case KVM_INTERRUPT: {
4674 struct kvm_interrupt irq;
4677 if (copy_from_user(&irq, argp, sizeof(irq)))
4679 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4683 r = kvm_vcpu_ioctl_nmi(vcpu);
4687 r = kvm_vcpu_ioctl_smi(vcpu);
4690 case KVM_SET_CPUID: {
4691 struct kvm_cpuid __user *cpuid_arg = argp;
4692 struct kvm_cpuid cpuid;
4695 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4697 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4700 case KVM_SET_CPUID2: {
4701 struct kvm_cpuid2 __user *cpuid_arg = argp;
4702 struct kvm_cpuid2 cpuid;
4705 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4707 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4708 cpuid_arg->entries);
4711 case KVM_GET_CPUID2: {
4712 struct kvm_cpuid2 __user *cpuid_arg = argp;
4713 struct kvm_cpuid2 cpuid;
4716 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4718 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4719 cpuid_arg->entries);
4723 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4728 case KVM_GET_MSRS: {
4729 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4730 r = msr_io(vcpu, argp, do_get_msr, 1);
4731 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4734 case KVM_SET_MSRS: {
4735 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4736 r = msr_io(vcpu, argp, do_set_msr, 0);
4737 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4740 case KVM_TPR_ACCESS_REPORTING: {
4741 struct kvm_tpr_access_ctl tac;
4744 if (copy_from_user(&tac, argp, sizeof(tac)))
4746 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4750 if (copy_to_user(argp, &tac, sizeof(tac)))
4755 case KVM_SET_VAPIC_ADDR: {
4756 struct kvm_vapic_addr va;
4760 if (!lapic_in_kernel(vcpu))
4763 if (copy_from_user(&va, argp, sizeof(va)))
4765 idx = srcu_read_lock(&vcpu->kvm->srcu);
4766 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4767 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4770 case KVM_X86_SETUP_MCE: {
4774 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4776 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4779 case KVM_X86_SET_MCE: {
4780 struct kvm_x86_mce mce;
4783 if (copy_from_user(&mce, argp, sizeof(mce)))
4785 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4788 case KVM_GET_VCPU_EVENTS: {
4789 struct kvm_vcpu_events events;
4791 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4794 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4799 case KVM_SET_VCPU_EVENTS: {
4800 struct kvm_vcpu_events events;
4803 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4806 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4809 case KVM_GET_DEBUGREGS: {
4810 struct kvm_debugregs dbgregs;
4812 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4815 if (copy_to_user(argp, &dbgregs,
4816 sizeof(struct kvm_debugregs)))
4821 case KVM_SET_DEBUGREGS: {
4822 struct kvm_debugregs dbgregs;
4825 if (copy_from_user(&dbgregs, argp,
4826 sizeof(struct kvm_debugregs)))
4829 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4832 case KVM_GET_XSAVE: {
4833 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4838 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4841 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4846 case KVM_SET_XSAVE: {
4847 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4848 if (IS_ERR(u.xsave)) {
4849 r = PTR_ERR(u.xsave);
4853 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4856 case KVM_GET_XCRS: {
4857 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4862 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4865 if (copy_to_user(argp, u.xcrs,
4866 sizeof(struct kvm_xcrs)))
4871 case KVM_SET_XCRS: {
4872 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4873 if (IS_ERR(u.xcrs)) {
4874 r = PTR_ERR(u.xcrs);
4878 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4881 case KVM_SET_TSC_KHZ: {
4885 user_tsc_khz = (u32)arg;
4887 if (kvm_has_tsc_control &&
4888 user_tsc_khz >= kvm_max_guest_tsc_khz)
4891 if (user_tsc_khz == 0)
4892 user_tsc_khz = tsc_khz;
4894 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4899 case KVM_GET_TSC_KHZ: {
4900 r = vcpu->arch.virtual_tsc_khz;
4903 case KVM_KVMCLOCK_CTRL: {
4904 r = kvm_set_guest_paused(vcpu);
4907 case KVM_ENABLE_CAP: {
4908 struct kvm_enable_cap cap;
4911 if (copy_from_user(&cap, argp, sizeof(cap)))
4913 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4916 case KVM_GET_NESTED_STATE: {
4917 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4921 if (!kvm_x86_ops.nested_ops->get_state)
4924 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4926 if (get_user(user_data_size, &user_kvm_nested_state->size))
4929 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
4934 if (r > user_data_size) {
4935 if (put_user(r, &user_kvm_nested_state->size))
4945 case KVM_SET_NESTED_STATE: {
4946 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4947 struct kvm_nested_state kvm_state;
4951 if (!kvm_x86_ops.nested_ops->set_state)
4955 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4959 if (kvm_state.size < sizeof(kvm_state))
4962 if (kvm_state.flags &
4963 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4964 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
4965 | KVM_STATE_NESTED_GIF_SET))
4968 /* nested_run_pending implies guest_mode. */
4969 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4970 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4973 idx = srcu_read_lock(&vcpu->kvm->srcu);
4974 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
4975 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4978 case KVM_GET_SUPPORTED_HV_CPUID: {
4979 struct kvm_cpuid2 __user *cpuid_arg = argp;
4980 struct kvm_cpuid2 cpuid;
4983 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4986 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4987 cpuid_arg->entries);
4992 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
5007 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5009 return VM_FAULT_SIGBUS;
5012 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
5016 if (addr > (unsigned int)(-3 * PAGE_SIZE))
5018 ret = kvm_x86_ops.set_tss_addr(kvm, addr);
5022 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
5025 return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr);
5028 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
5029 unsigned long kvm_nr_mmu_pages)
5031 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
5034 mutex_lock(&kvm->slots_lock);
5036 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
5037 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
5039 mutex_unlock(&kvm->slots_lock);
5043 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
5045 return kvm->arch.n_max_mmu_pages;
5048 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5050 struct kvm_pic *pic = kvm->arch.vpic;
5054 switch (chip->chip_id) {
5055 case KVM_IRQCHIP_PIC_MASTER:
5056 memcpy(&chip->chip.pic, &pic->pics[0],
5057 sizeof(struct kvm_pic_state));
5059 case KVM_IRQCHIP_PIC_SLAVE:
5060 memcpy(&chip->chip.pic, &pic->pics[1],
5061 sizeof(struct kvm_pic_state));
5063 case KVM_IRQCHIP_IOAPIC:
5064 kvm_get_ioapic(kvm, &chip->chip.ioapic);
5073 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5075 struct kvm_pic *pic = kvm->arch.vpic;
5079 switch (chip->chip_id) {
5080 case KVM_IRQCHIP_PIC_MASTER:
5081 spin_lock(&pic->lock);
5082 memcpy(&pic->pics[0], &chip->chip.pic,
5083 sizeof(struct kvm_pic_state));
5084 spin_unlock(&pic->lock);
5086 case KVM_IRQCHIP_PIC_SLAVE:
5087 spin_lock(&pic->lock);
5088 memcpy(&pic->pics[1], &chip->chip.pic,
5089 sizeof(struct kvm_pic_state));
5090 spin_unlock(&pic->lock);
5092 case KVM_IRQCHIP_IOAPIC:
5093 kvm_set_ioapic(kvm, &chip->chip.ioapic);
5099 kvm_pic_update_irq(pic);
5103 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5105 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
5107 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
5109 mutex_lock(&kps->lock);
5110 memcpy(ps, &kps->channels, sizeof(*ps));
5111 mutex_unlock(&kps->lock);
5115 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5118 struct kvm_pit *pit = kvm->arch.vpit;
5120 mutex_lock(&pit->pit_state.lock);
5121 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
5122 for (i = 0; i < 3; i++)
5123 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
5124 mutex_unlock(&pit->pit_state.lock);
5128 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5130 mutex_lock(&kvm->arch.vpit->pit_state.lock);
5131 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
5132 sizeof(ps->channels));
5133 ps->flags = kvm->arch.vpit->pit_state.flags;
5134 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
5135 memset(&ps->reserved, 0, sizeof(ps->reserved));
5139 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5143 u32 prev_legacy, cur_legacy;
5144 struct kvm_pit *pit = kvm->arch.vpit;
5146 mutex_lock(&pit->pit_state.lock);
5147 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
5148 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
5149 if (!prev_legacy && cur_legacy)
5151 memcpy(&pit->pit_state.channels, &ps->channels,
5152 sizeof(pit->pit_state.channels));
5153 pit->pit_state.flags = ps->flags;
5154 for (i = 0; i < 3; i++)
5155 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
5157 mutex_unlock(&pit->pit_state.lock);
5161 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
5162 struct kvm_reinject_control *control)
5164 struct kvm_pit *pit = kvm->arch.vpit;
5166 /* pit->pit_state.lock was overloaded to prevent userspace from getting
5167 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
5168 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
5170 mutex_lock(&pit->pit_state.lock);
5171 kvm_pit_set_reinject(pit, control->pit_reinject);
5172 mutex_unlock(&pit->pit_state.lock);
5177 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
5180 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
5182 if (kvm_x86_ops.flush_log_dirty)
5183 kvm_x86_ops.flush_log_dirty(kvm);
5186 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
5189 if (!irqchip_in_kernel(kvm))
5192 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
5193 irq_event->irq, irq_event->level,
5198 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
5199 struct kvm_enable_cap *cap)
5207 case KVM_CAP_DISABLE_QUIRKS:
5208 kvm->arch.disabled_quirks = cap->args[0];
5211 case KVM_CAP_SPLIT_IRQCHIP: {
5212 mutex_lock(&kvm->lock);
5214 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
5215 goto split_irqchip_unlock;
5217 if (irqchip_in_kernel(kvm))
5218 goto split_irqchip_unlock;
5219 if (kvm->created_vcpus)
5220 goto split_irqchip_unlock;
5221 r = kvm_setup_empty_irq_routing(kvm);
5223 goto split_irqchip_unlock;
5224 /* Pairs with irqchip_in_kernel. */
5226 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
5227 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
5229 split_irqchip_unlock:
5230 mutex_unlock(&kvm->lock);
5233 case KVM_CAP_X2APIC_API:
5235 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
5238 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
5239 kvm->arch.x2apic_format = true;
5240 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
5241 kvm->arch.x2apic_broadcast_quirk_disabled = true;
5245 case KVM_CAP_X86_DISABLE_EXITS:
5247 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
5250 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
5251 kvm_can_mwait_in_guest())
5252 kvm->arch.mwait_in_guest = true;
5253 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
5254 kvm->arch.hlt_in_guest = true;
5255 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
5256 kvm->arch.pause_in_guest = true;
5257 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
5258 kvm->arch.cstate_in_guest = true;
5261 case KVM_CAP_MSR_PLATFORM_INFO:
5262 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
5265 case KVM_CAP_EXCEPTION_PAYLOAD:
5266 kvm->arch.exception_payload_enabled = cap->args[0];
5269 case KVM_CAP_X86_USER_SPACE_MSR:
5270 kvm->arch.user_space_msr_mask = cap->args[0];
5280 static void kvm_clear_msr_filter(struct kvm *kvm)
5283 u32 count = kvm->arch.msr_filter.count;
5284 struct msr_bitmap_range ranges[16];
5286 mutex_lock(&kvm->lock);
5287 kvm->arch.msr_filter.count = 0;
5288 memcpy(ranges, kvm->arch.msr_filter.ranges, count * sizeof(ranges[0]));
5289 mutex_unlock(&kvm->lock);
5290 synchronize_srcu(&kvm->srcu);
5292 for (i = 0; i < count; i++)
5293 kfree(ranges[i].bitmap);
5296 static int kvm_add_msr_filter(struct kvm *kvm, struct kvm_msr_filter_range *user_range)
5298 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
5299 struct msr_bitmap_range range;
5300 unsigned long *bitmap = NULL;
5304 if (!user_range->nmsrs)
5307 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
5308 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
5311 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
5313 return PTR_ERR(bitmap);
5315 range = (struct msr_bitmap_range) {
5316 .flags = user_range->flags,
5317 .base = user_range->base,
5318 .nmsrs = user_range->nmsrs,
5322 if (range.flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) {
5332 /* Everything ok, add this range identifier to our global pool */
5333 ranges[kvm->arch.msr_filter.count] = range;
5334 /* Make sure we filled the array before we tell anyone to walk it */
5336 kvm->arch.msr_filter.count++;
5344 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp)
5346 struct kvm_msr_filter __user *user_msr_filter = argp;
5347 struct kvm_msr_filter filter;
5353 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
5356 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++)
5357 empty &= !filter.ranges[i].nmsrs;
5359 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY);
5360 if (empty && !default_allow)
5363 kvm_clear_msr_filter(kvm);
5365 kvm->arch.msr_filter.default_allow = default_allow;
5368 * Protect from concurrent calls to this function that could trigger
5369 * a TOCTOU violation on kvm->arch.msr_filter.count.
5371 mutex_lock(&kvm->lock);
5372 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
5373 r = kvm_add_msr_filter(kvm, &filter.ranges[i]);
5378 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
5379 mutex_unlock(&kvm->lock);
5384 long kvm_arch_vm_ioctl(struct file *filp,
5385 unsigned int ioctl, unsigned long arg)
5387 struct kvm *kvm = filp->private_data;
5388 void __user *argp = (void __user *)arg;
5391 * This union makes it completely explicit to gcc-3.x
5392 * that these two variables' stack usage should be
5393 * combined, not added together.
5396 struct kvm_pit_state ps;
5397 struct kvm_pit_state2 ps2;
5398 struct kvm_pit_config pit_config;
5402 case KVM_SET_TSS_ADDR:
5403 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
5405 case KVM_SET_IDENTITY_MAP_ADDR: {
5408 mutex_lock(&kvm->lock);
5410 if (kvm->created_vcpus)
5411 goto set_identity_unlock;
5413 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
5414 goto set_identity_unlock;
5415 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
5416 set_identity_unlock:
5417 mutex_unlock(&kvm->lock);
5420 case KVM_SET_NR_MMU_PAGES:
5421 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
5423 case KVM_GET_NR_MMU_PAGES:
5424 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
5426 case KVM_CREATE_IRQCHIP: {
5427 mutex_lock(&kvm->lock);
5430 if (irqchip_in_kernel(kvm))
5431 goto create_irqchip_unlock;
5434 if (kvm->created_vcpus)
5435 goto create_irqchip_unlock;
5437 r = kvm_pic_init(kvm);
5439 goto create_irqchip_unlock;
5441 r = kvm_ioapic_init(kvm);
5443 kvm_pic_destroy(kvm);
5444 goto create_irqchip_unlock;
5447 r = kvm_setup_default_irq_routing(kvm);
5449 kvm_ioapic_destroy(kvm);
5450 kvm_pic_destroy(kvm);
5451 goto create_irqchip_unlock;
5453 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
5455 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
5456 create_irqchip_unlock:
5457 mutex_unlock(&kvm->lock);
5460 case KVM_CREATE_PIT:
5461 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
5463 case KVM_CREATE_PIT2:
5465 if (copy_from_user(&u.pit_config, argp,
5466 sizeof(struct kvm_pit_config)))
5469 mutex_lock(&kvm->lock);
5472 goto create_pit_unlock;
5474 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5478 mutex_unlock(&kvm->lock);
5480 case KVM_GET_IRQCHIP: {
5481 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5482 struct kvm_irqchip *chip;
5484 chip = memdup_user(argp, sizeof(*chip));
5491 if (!irqchip_kernel(kvm))
5492 goto get_irqchip_out;
5493 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5495 goto get_irqchip_out;
5497 if (copy_to_user(argp, chip, sizeof(*chip)))
5498 goto get_irqchip_out;
5504 case KVM_SET_IRQCHIP: {
5505 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5506 struct kvm_irqchip *chip;
5508 chip = memdup_user(argp, sizeof(*chip));
5515 if (!irqchip_kernel(kvm))
5516 goto set_irqchip_out;
5517 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5524 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5527 if (!kvm->arch.vpit)
5529 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5533 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5540 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5542 mutex_lock(&kvm->lock);
5544 if (!kvm->arch.vpit)
5546 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5548 mutex_unlock(&kvm->lock);
5551 case KVM_GET_PIT2: {
5553 if (!kvm->arch.vpit)
5555 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5559 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5564 case KVM_SET_PIT2: {
5566 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5568 mutex_lock(&kvm->lock);
5570 if (!kvm->arch.vpit)
5572 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5574 mutex_unlock(&kvm->lock);
5577 case KVM_REINJECT_CONTROL: {
5578 struct kvm_reinject_control control;
5580 if (copy_from_user(&control, argp, sizeof(control)))
5583 if (!kvm->arch.vpit)
5585 r = kvm_vm_ioctl_reinject(kvm, &control);
5588 case KVM_SET_BOOT_CPU_ID:
5590 mutex_lock(&kvm->lock);
5591 if (kvm->created_vcpus)
5594 kvm->arch.bsp_vcpu_id = arg;
5595 mutex_unlock(&kvm->lock);
5597 case KVM_XEN_HVM_CONFIG: {
5598 struct kvm_xen_hvm_config xhc;
5600 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5605 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5609 case KVM_SET_CLOCK: {
5610 struct kvm_clock_data user_ns;
5614 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5623 * TODO: userspace has to take care of races with VCPU_RUN, so
5624 * kvm_gen_update_masterclock() can be cut down to locked
5625 * pvclock_update_vm_gtod_copy().
5627 kvm_gen_update_masterclock(kvm);
5628 now_ns = get_kvmclock_ns(kvm);
5629 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5630 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5633 case KVM_GET_CLOCK: {
5634 struct kvm_clock_data user_ns;
5637 now_ns = get_kvmclock_ns(kvm);
5638 user_ns.clock = now_ns;
5639 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5640 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5643 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5648 case KVM_MEMORY_ENCRYPT_OP: {
5650 if (kvm_x86_ops.mem_enc_op)
5651 r = kvm_x86_ops.mem_enc_op(kvm, argp);
5654 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5655 struct kvm_enc_region region;
5658 if (copy_from_user(®ion, argp, sizeof(region)))
5662 if (kvm_x86_ops.mem_enc_reg_region)
5663 r = kvm_x86_ops.mem_enc_reg_region(kvm, ®ion);
5666 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5667 struct kvm_enc_region region;
5670 if (copy_from_user(®ion, argp, sizeof(region)))
5674 if (kvm_x86_ops.mem_enc_unreg_region)
5675 r = kvm_x86_ops.mem_enc_unreg_region(kvm, ®ion);
5678 case KVM_HYPERV_EVENTFD: {
5679 struct kvm_hyperv_eventfd hvevfd;
5682 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5684 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5687 case KVM_SET_PMU_EVENT_FILTER:
5688 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5690 case KVM_X86_SET_MSR_FILTER:
5691 r = kvm_vm_ioctl_set_msr_filter(kvm, argp);
5700 static void kvm_init_msr_list(void)
5702 struct x86_pmu_capability x86_pmu;
5706 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5707 "Please update the fixed PMCs in msrs_to_saved_all[]");
5709 perf_get_x86_pmu_capability(&x86_pmu);
5711 num_msrs_to_save = 0;
5712 num_emulated_msrs = 0;
5713 num_msr_based_features = 0;
5715 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5716 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5720 * Even MSRs that are valid in the host may not be exposed
5721 * to the guests in some cases.
5723 switch (msrs_to_save_all[i]) {
5724 case MSR_IA32_BNDCFGS:
5725 if (!kvm_mpx_supported())
5729 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5732 case MSR_IA32_UMWAIT_CONTROL:
5733 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
5736 case MSR_IA32_RTIT_CTL:
5737 case MSR_IA32_RTIT_STATUS:
5738 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5741 case MSR_IA32_RTIT_CR3_MATCH:
5742 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5743 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5746 case MSR_IA32_RTIT_OUTPUT_BASE:
5747 case MSR_IA32_RTIT_OUTPUT_MASK:
5748 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5749 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5750 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5753 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
5754 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5755 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5756 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5759 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5760 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5761 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5764 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5765 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5766 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5773 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5776 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5777 if (!kvm_x86_ops.has_emulated_msr(emulated_msrs_all[i]))
5780 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5783 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5784 struct kvm_msr_entry msr;
5786 msr.index = msr_based_features_all[i];
5787 if (kvm_get_msr_feature(&msr))
5790 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5794 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5802 if (!(lapic_in_kernel(vcpu) &&
5803 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5804 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5815 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5822 if (!(lapic_in_kernel(vcpu) &&
5823 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5825 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5827 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5837 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5838 struct kvm_segment *var, int seg)
5840 kvm_x86_ops.set_segment(vcpu, var, seg);
5843 void kvm_get_segment(struct kvm_vcpu *vcpu,
5844 struct kvm_segment *var, int seg)
5846 kvm_x86_ops.get_segment(vcpu, var, seg);
5849 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5850 struct x86_exception *exception)
5854 BUG_ON(!mmu_is_nested(vcpu));
5856 /* NPT walks are always user-walks */
5857 access |= PFERR_USER_MASK;
5858 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5863 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5864 struct x86_exception *exception)
5866 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5867 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5870 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5871 struct x86_exception *exception)
5873 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5874 access |= PFERR_FETCH_MASK;
5875 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5878 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5879 struct x86_exception *exception)
5881 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5882 access |= PFERR_WRITE_MASK;
5883 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5886 /* uses this to access any guest's mapped memory without checking CPL */
5887 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5888 struct x86_exception *exception)
5890 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5893 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5894 struct kvm_vcpu *vcpu, u32 access,
5895 struct x86_exception *exception)
5898 int r = X86EMUL_CONTINUE;
5901 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5903 unsigned offset = addr & (PAGE_SIZE-1);
5904 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5907 if (gpa == UNMAPPED_GVA)
5908 return X86EMUL_PROPAGATE_FAULT;
5909 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5912 r = X86EMUL_IO_NEEDED;
5924 /* used for instruction fetching */
5925 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5926 gva_t addr, void *val, unsigned int bytes,
5927 struct x86_exception *exception)
5929 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5930 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5934 /* Inline kvm_read_guest_virt_helper for speed. */
5935 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5937 if (unlikely(gpa == UNMAPPED_GVA))
5938 return X86EMUL_PROPAGATE_FAULT;
5940 offset = addr & (PAGE_SIZE-1);
5941 if (WARN_ON(offset + bytes > PAGE_SIZE))
5942 bytes = (unsigned)PAGE_SIZE - offset;
5943 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5945 if (unlikely(ret < 0))
5946 return X86EMUL_IO_NEEDED;
5948 return X86EMUL_CONTINUE;
5951 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5952 gva_t addr, void *val, unsigned int bytes,
5953 struct x86_exception *exception)
5955 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5958 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5959 * is returned, but our callers are not ready for that and they blindly
5960 * call kvm_inject_page_fault. Ensure that they at least do not leak
5961 * uninitialized kernel stack memory into cr2 and error code.
5963 memset(exception, 0, sizeof(*exception));
5964 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5967 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5969 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5970 gva_t addr, void *val, unsigned int bytes,
5971 struct x86_exception *exception, bool system)
5973 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5976 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5977 access |= PFERR_USER_MASK;
5979 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5982 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5983 unsigned long addr, void *val, unsigned int bytes)
5985 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5986 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5988 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5991 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5992 struct kvm_vcpu *vcpu, u32 access,
5993 struct x86_exception *exception)
5996 int r = X86EMUL_CONTINUE;
5999 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
6002 unsigned offset = addr & (PAGE_SIZE-1);
6003 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
6006 if (gpa == UNMAPPED_GVA)
6007 return X86EMUL_PROPAGATE_FAULT;
6008 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
6010 r = X86EMUL_IO_NEEDED;
6022 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
6023 unsigned int bytes, struct x86_exception *exception,
6026 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6027 u32 access = PFERR_WRITE_MASK;
6029 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
6030 access |= PFERR_USER_MASK;
6032 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6036 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
6037 unsigned int bytes, struct x86_exception *exception)
6039 /* kvm_write_guest_virt_system can pull in tons of pages. */
6040 vcpu->arch.l1tf_flush_l1d = true;
6042 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6043 PFERR_WRITE_MASK, exception);
6045 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
6047 int handle_ud(struct kvm_vcpu *vcpu)
6049 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
6050 int emul_type = EMULTYPE_TRAP_UD;
6051 char sig[5]; /* ud2; .ascii "kvm" */
6052 struct x86_exception e;
6054 if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, NULL, 0)))
6057 if (force_emulation_prefix &&
6058 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
6059 sig, sizeof(sig), &e) == 0 &&
6060 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
6061 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
6062 emul_type = EMULTYPE_TRAP_UD_FORCED;
6065 return kvm_emulate_instruction(vcpu, emul_type);
6067 EXPORT_SYMBOL_GPL(handle_ud);
6069 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6070 gpa_t gpa, bool write)
6072 /* For APIC access vmexit */
6073 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6076 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
6077 trace_vcpu_match_mmio(gva, gpa, write, true);
6084 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6085 gpa_t *gpa, struct x86_exception *exception,
6088 u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
6089 | (write ? PFERR_WRITE_MASK : 0);
6092 * currently PKRU is only applied to ept enabled guest so
6093 * there is no pkey in EPT page table for L1 guest or EPT
6094 * shadow page table for L2 guest.
6096 if (vcpu_match_mmio_gva(vcpu, gva)
6097 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
6098 vcpu->arch.mmio_access, 0, access)) {
6099 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
6100 (gva & (PAGE_SIZE - 1));
6101 trace_vcpu_match_mmio(gva, *gpa, write, false);
6105 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
6107 if (*gpa == UNMAPPED_GVA)
6110 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
6113 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
6114 const void *val, int bytes)
6118 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
6121 kvm_page_track_write(vcpu, gpa, val, bytes);
6125 struct read_write_emulator_ops {
6126 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
6128 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
6129 void *val, int bytes);
6130 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6131 int bytes, void *val);
6132 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6133 void *val, int bytes);
6137 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
6139 if (vcpu->mmio_read_completed) {
6140 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
6141 vcpu->mmio_fragments[0].gpa, val);
6142 vcpu->mmio_read_completed = 0;
6149 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6150 void *val, int bytes)
6152 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
6155 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6156 void *val, int bytes)
6158 return emulator_write_phys(vcpu, gpa, val, bytes);
6161 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
6163 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
6164 return vcpu_mmio_write(vcpu, gpa, bytes, val);
6167 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6168 void *val, int bytes)
6170 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
6171 return X86EMUL_IO_NEEDED;
6174 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6175 void *val, int bytes)
6177 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
6179 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
6180 return X86EMUL_CONTINUE;
6183 static const struct read_write_emulator_ops read_emultor = {
6184 .read_write_prepare = read_prepare,
6185 .read_write_emulate = read_emulate,
6186 .read_write_mmio = vcpu_mmio_read,
6187 .read_write_exit_mmio = read_exit_mmio,
6190 static const struct read_write_emulator_ops write_emultor = {
6191 .read_write_emulate = write_emulate,
6192 .read_write_mmio = write_mmio,
6193 .read_write_exit_mmio = write_exit_mmio,
6197 static int emulator_read_write_onepage(unsigned long addr, void *val,
6199 struct x86_exception *exception,
6200 struct kvm_vcpu *vcpu,
6201 const struct read_write_emulator_ops *ops)
6205 bool write = ops->write;
6206 struct kvm_mmio_fragment *frag;
6207 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6210 * If the exit was due to a NPF we may already have a GPA.
6211 * If the GPA is present, use it to avoid the GVA to GPA table walk.
6212 * Note, this cannot be used on string operations since string
6213 * operation using rep will only have the initial GPA from the NPF
6216 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
6217 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
6218 gpa = ctxt->gpa_val;
6219 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
6221 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
6223 return X86EMUL_PROPAGATE_FAULT;
6226 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
6227 return X86EMUL_CONTINUE;
6230 * Is this MMIO handled locally?
6232 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
6233 if (handled == bytes)
6234 return X86EMUL_CONTINUE;
6240 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
6241 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
6245 return X86EMUL_CONTINUE;
6248 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
6250 void *val, unsigned int bytes,
6251 struct x86_exception *exception,
6252 const struct read_write_emulator_ops *ops)
6254 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6258 if (ops->read_write_prepare &&
6259 ops->read_write_prepare(vcpu, val, bytes))
6260 return X86EMUL_CONTINUE;
6262 vcpu->mmio_nr_fragments = 0;
6264 /* Crossing a page boundary? */
6265 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
6268 now = -addr & ~PAGE_MASK;
6269 rc = emulator_read_write_onepage(addr, val, now, exception,
6272 if (rc != X86EMUL_CONTINUE)
6275 if (ctxt->mode != X86EMUL_MODE_PROT64)
6281 rc = emulator_read_write_onepage(addr, val, bytes, exception,
6283 if (rc != X86EMUL_CONTINUE)
6286 if (!vcpu->mmio_nr_fragments)
6289 gpa = vcpu->mmio_fragments[0].gpa;
6291 vcpu->mmio_needed = 1;
6292 vcpu->mmio_cur_fragment = 0;
6294 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
6295 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
6296 vcpu->run->exit_reason = KVM_EXIT_MMIO;
6297 vcpu->run->mmio.phys_addr = gpa;
6299 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
6302 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
6306 struct x86_exception *exception)
6308 return emulator_read_write(ctxt, addr, val, bytes,
6309 exception, &read_emultor);
6312 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
6316 struct x86_exception *exception)
6318 return emulator_read_write(ctxt, addr, (void *)val, bytes,
6319 exception, &write_emultor);
6322 #define CMPXCHG_TYPE(t, ptr, old, new) \
6323 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
6325 #ifdef CONFIG_X86_64
6326 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
6328 # define CMPXCHG64(ptr, old, new) \
6329 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
6332 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
6337 struct x86_exception *exception)
6339 struct kvm_host_map map;
6340 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6346 /* guests cmpxchg8b have to be emulated atomically */
6347 if (bytes > 8 || (bytes & (bytes - 1)))
6350 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
6352 if (gpa == UNMAPPED_GVA ||
6353 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6357 * Emulate the atomic as a straight write to avoid #AC if SLD is
6358 * enabled in the host and the access splits a cache line.
6360 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
6361 page_line_mask = ~(cache_line_size() - 1);
6363 page_line_mask = PAGE_MASK;
6365 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
6368 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
6371 kaddr = map.hva + offset_in_page(gpa);
6375 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
6378 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
6381 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
6384 exchanged = CMPXCHG64(kaddr, old, new);
6390 kvm_vcpu_unmap(vcpu, &map, true);
6393 return X86EMUL_CMPXCHG_FAILED;
6395 kvm_page_track_write(vcpu, gpa, new, bytes);
6397 return X86EMUL_CONTINUE;
6400 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
6402 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
6405 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
6409 for (i = 0; i < vcpu->arch.pio.count; i++) {
6410 if (vcpu->arch.pio.in)
6411 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
6412 vcpu->arch.pio.size, pd);
6414 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
6415 vcpu->arch.pio.port, vcpu->arch.pio.size,
6419 pd += vcpu->arch.pio.size;
6424 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
6425 unsigned short port, void *val,
6426 unsigned int count, bool in)
6428 vcpu->arch.pio.port = port;
6429 vcpu->arch.pio.in = in;
6430 vcpu->arch.pio.count = count;
6431 vcpu->arch.pio.size = size;
6433 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
6434 vcpu->arch.pio.count = 0;
6438 vcpu->run->exit_reason = KVM_EXIT_IO;
6439 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
6440 vcpu->run->io.size = size;
6441 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
6442 vcpu->run->io.count = count;
6443 vcpu->run->io.port = port;
6448 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
6449 unsigned short port, void *val, unsigned int count)
6453 if (vcpu->arch.pio.count)
6456 memset(vcpu->arch.pio_data, 0, size * count);
6458 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
6461 memcpy(val, vcpu->arch.pio_data, size * count);
6462 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
6463 vcpu->arch.pio.count = 0;
6470 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
6471 int size, unsigned short port, void *val,
6474 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
6478 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
6479 unsigned short port, const void *val,
6482 memcpy(vcpu->arch.pio_data, val, size * count);
6483 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6484 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6487 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
6488 int size, unsigned short port,
6489 const void *val, unsigned int count)
6491 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
6494 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6496 return kvm_x86_ops.get_segment_base(vcpu, seg);
6499 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6501 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6504 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6506 if (!need_emulate_wbinvd(vcpu))
6507 return X86EMUL_CONTINUE;
6509 if (kvm_x86_ops.has_wbinvd_exit()) {
6510 int cpu = get_cpu();
6512 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6513 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6514 wbinvd_ipi, NULL, 1);
6516 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6519 return X86EMUL_CONTINUE;
6522 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6524 kvm_emulate_wbinvd_noskip(vcpu);
6525 return kvm_skip_emulated_instruction(vcpu);
6527 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6531 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6533 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6536 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6537 unsigned long *dest)
6539 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6542 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6543 unsigned long value)
6546 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6549 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6551 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6554 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6556 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6557 unsigned long value;
6561 value = kvm_read_cr0(vcpu);
6564 value = vcpu->arch.cr2;
6567 value = kvm_read_cr3(vcpu);
6570 value = kvm_read_cr4(vcpu);
6573 value = kvm_get_cr8(vcpu);
6576 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6583 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6585 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6590 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6593 vcpu->arch.cr2 = val;
6596 res = kvm_set_cr3(vcpu, val);
6599 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6602 res = kvm_set_cr8(vcpu, val);
6605 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6612 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6614 return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt));
6617 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6619 kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt);
6622 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6624 kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt);
6627 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6629 kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt);
6632 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6634 kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt);
6637 static unsigned long emulator_get_cached_segment_base(
6638 struct x86_emulate_ctxt *ctxt, int seg)
6640 return get_segment_base(emul_to_vcpu(ctxt), seg);
6643 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6644 struct desc_struct *desc, u32 *base3,
6647 struct kvm_segment var;
6649 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6650 *selector = var.selector;
6653 memset(desc, 0, sizeof(*desc));
6661 set_desc_limit(desc, var.limit);
6662 set_desc_base(desc, (unsigned long)var.base);
6663 #ifdef CONFIG_X86_64
6665 *base3 = var.base >> 32;
6667 desc->type = var.type;
6669 desc->dpl = var.dpl;
6670 desc->p = var.present;
6671 desc->avl = var.avl;
6679 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6680 struct desc_struct *desc, u32 base3,
6683 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6684 struct kvm_segment var;
6686 var.selector = selector;
6687 var.base = get_desc_base(desc);
6688 #ifdef CONFIG_X86_64
6689 var.base |= ((u64)base3) << 32;
6691 var.limit = get_desc_limit(desc);
6693 var.limit = (var.limit << 12) | 0xfff;
6694 var.type = desc->type;
6695 var.dpl = desc->dpl;
6700 var.avl = desc->avl;
6701 var.present = desc->p;
6702 var.unusable = !var.present;
6705 kvm_set_segment(vcpu, &var, seg);
6709 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6710 u32 msr_index, u64 *pdata)
6712 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6715 r = kvm_get_msr(vcpu, msr_index, pdata);
6717 if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) {
6718 /* Bounce to user space */
6719 return X86EMUL_IO_NEEDED;
6725 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6726 u32 msr_index, u64 data)
6728 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6731 r = kvm_set_msr(vcpu, msr_index, data);
6733 if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) {
6734 /* Bounce to user space */
6735 return X86EMUL_IO_NEEDED;
6741 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6743 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6745 return vcpu->arch.smbase;
6748 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6750 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6752 vcpu->arch.smbase = smbase;
6755 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6758 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6761 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6762 u32 pmc, u64 *pdata)
6764 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6767 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6769 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6772 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6773 struct x86_instruction_info *info,
6774 enum x86_intercept_stage stage)
6776 return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage,
6780 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6781 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6784 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6787 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6789 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6792 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6794 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6797 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6799 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6802 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6804 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6807 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6809 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6812 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6814 kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked);
6817 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6819 return emul_to_vcpu(ctxt)->arch.hflags;
6822 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6824 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6827 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6828 const char *smstate)
6830 return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6833 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6835 kvm_smm_changed(emul_to_vcpu(ctxt));
6838 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6840 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6843 static const struct x86_emulate_ops emulate_ops = {
6844 .read_gpr = emulator_read_gpr,
6845 .write_gpr = emulator_write_gpr,
6846 .read_std = emulator_read_std,
6847 .write_std = emulator_write_std,
6848 .read_phys = kvm_read_guest_phys_system,
6849 .fetch = kvm_fetch_guest_virt,
6850 .read_emulated = emulator_read_emulated,
6851 .write_emulated = emulator_write_emulated,
6852 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6853 .invlpg = emulator_invlpg,
6854 .pio_in_emulated = emulator_pio_in_emulated,
6855 .pio_out_emulated = emulator_pio_out_emulated,
6856 .get_segment = emulator_get_segment,
6857 .set_segment = emulator_set_segment,
6858 .get_cached_segment_base = emulator_get_cached_segment_base,
6859 .get_gdt = emulator_get_gdt,
6860 .get_idt = emulator_get_idt,
6861 .set_gdt = emulator_set_gdt,
6862 .set_idt = emulator_set_idt,
6863 .get_cr = emulator_get_cr,
6864 .set_cr = emulator_set_cr,
6865 .cpl = emulator_get_cpl,
6866 .get_dr = emulator_get_dr,
6867 .set_dr = emulator_set_dr,
6868 .get_smbase = emulator_get_smbase,
6869 .set_smbase = emulator_set_smbase,
6870 .set_msr = emulator_set_msr,
6871 .get_msr = emulator_get_msr,
6872 .check_pmc = emulator_check_pmc,
6873 .read_pmc = emulator_read_pmc,
6874 .halt = emulator_halt,
6875 .wbinvd = emulator_wbinvd,
6876 .fix_hypercall = emulator_fix_hypercall,
6877 .intercept = emulator_intercept,
6878 .get_cpuid = emulator_get_cpuid,
6879 .guest_has_long_mode = emulator_guest_has_long_mode,
6880 .guest_has_movbe = emulator_guest_has_movbe,
6881 .guest_has_fxsr = emulator_guest_has_fxsr,
6882 .set_nmi_mask = emulator_set_nmi_mask,
6883 .get_hflags = emulator_get_hflags,
6884 .set_hflags = emulator_set_hflags,
6885 .pre_leave_smm = emulator_pre_leave_smm,
6886 .post_leave_smm = emulator_post_leave_smm,
6887 .set_xcr = emulator_set_xcr,
6890 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6892 u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
6894 * an sti; sti; sequence only disable interrupts for the first
6895 * instruction. So, if the last instruction, be it emulated or
6896 * not, left the system with the INT_STI flag enabled, it
6897 * means that the last instruction is an sti. We should not
6898 * leave the flag on in this case. The same goes for mov ss
6900 if (int_shadow & mask)
6902 if (unlikely(int_shadow || mask)) {
6903 kvm_x86_ops.set_interrupt_shadow(vcpu, mask);
6905 kvm_make_request(KVM_REQ_EVENT, vcpu);
6909 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6911 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6912 if (ctxt->exception.vector == PF_VECTOR)
6913 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
6915 if (ctxt->exception.error_code_valid)
6916 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6917 ctxt->exception.error_code);
6919 kvm_queue_exception(vcpu, ctxt->exception.vector);
6923 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6925 struct x86_emulate_ctxt *ctxt;
6927 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6929 pr_err("kvm: failed to allocate vcpu's emulator\n");
6934 ctxt->ops = &emulate_ops;
6935 vcpu->arch.emulate_ctxt = ctxt;
6940 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6942 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6945 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6947 ctxt->gpa_available = false;
6948 ctxt->eflags = kvm_get_rflags(vcpu);
6949 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6951 ctxt->eip = kvm_rip_read(vcpu);
6952 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6953 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6954 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6955 cs_db ? X86EMUL_MODE_PROT32 :
6956 X86EMUL_MODE_PROT16;
6957 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6958 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6959 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6961 init_decode_cache(ctxt);
6962 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6965 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6967 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6970 init_emulate_ctxt(vcpu);
6974 ctxt->_eip = ctxt->eip + inc_eip;
6975 ret = emulate_int_real(ctxt, irq);
6977 if (ret != X86EMUL_CONTINUE) {
6978 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6980 ctxt->eip = ctxt->_eip;
6981 kvm_rip_write(vcpu, ctxt->eip);
6982 kvm_set_rflags(vcpu, ctxt->eflags);
6985 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6987 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6989 ++vcpu->stat.insn_emulation_fail;
6990 trace_kvm_emulate_insn_failed(vcpu);
6992 if (emulation_type & EMULTYPE_VMWARE_GP) {
6993 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6997 if (emulation_type & EMULTYPE_SKIP) {
6998 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6999 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7000 vcpu->run->internal.ndata = 0;
7004 kvm_queue_exception(vcpu, UD_VECTOR);
7006 if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) {
7007 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7008 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7009 vcpu->run->internal.ndata = 0;
7016 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7017 bool write_fault_to_shadow_pgtable,
7020 gpa_t gpa = cr2_or_gpa;
7023 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7026 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7027 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7030 if (!vcpu->arch.mmu->direct_map) {
7032 * Write permission should be allowed since only
7033 * write access need to be emulated.
7035 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7038 * If the mapping is invalid in guest, let cpu retry
7039 * it to generate fault.
7041 if (gpa == UNMAPPED_GVA)
7046 * Do not retry the unhandleable instruction if it faults on the
7047 * readonly host memory, otherwise it will goto a infinite loop:
7048 * retry instruction -> write #PF -> emulation fail -> retry
7049 * instruction -> ...
7051 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
7054 * If the instruction failed on the error pfn, it can not be fixed,
7055 * report the error to userspace.
7057 if (is_error_noslot_pfn(pfn))
7060 kvm_release_pfn_clean(pfn);
7062 /* The instructions are well-emulated on direct mmu. */
7063 if (vcpu->arch.mmu->direct_map) {
7064 unsigned int indirect_shadow_pages;
7066 spin_lock(&vcpu->kvm->mmu_lock);
7067 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
7068 spin_unlock(&vcpu->kvm->mmu_lock);
7070 if (indirect_shadow_pages)
7071 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7077 * if emulation was due to access to shadowed page table
7078 * and it failed try to unshadow page and re-enter the
7079 * guest to let CPU execute the instruction.
7081 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7084 * If the access faults on its page table, it can not
7085 * be fixed by unprotecting shadow page and it should
7086 * be reported to userspace.
7088 return !write_fault_to_shadow_pgtable;
7091 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
7092 gpa_t cr2_or_gpa, int emulation_type)
7094 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7095 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
7097 last_retry_eip = vcpu->arch.last_retry_eip;
7098 last_retry_addr = vcpu->arch.last_retry_addr;
7101 * If the emulation is caused by #PF and it is non-page_table
7102 * writing instruction, it means the VM-EXIT is caused by shadow
7103 * page protected, we can zap the shadow page and retry this
7104 * instruction directly.
7106 * Note: if the guest uses a non-page-table modifying instruction
7107 * on the PDE that points to the instruction, then we will unmap
7108 * the instruction and go to an infinite loop. So, we cache the
7109 * last retried eip and the last fault address, if we meet the eip
7110 * and the address again, we can break out of the potential infinite
7113 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
7115 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7118 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7119 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7122 if (x86_page_table_writing_insn(ctxt))
7125 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
7128 vcpu->arch.last_retry_eip = ctxt->eip;
7129 vcpu->arch.last_retry_addr = cr2_or_gpa;
7131 if (!vcpu->arch.mmu->direct_map)
7132 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7134 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7139 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
7140 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
7142 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
7144 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
7145 /* This is a good place to trace that we are exiting SMM. */
7146 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
7148 /* Process a latched INIT or SMI, if any. */
7149 kvm_make_request(KVM_REQ_EVENT, vcpu);
7152 kvm_mmu_reset_context(vcpu);
7155 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
7164 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
7165 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
7170 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
7172 struct kvm_run *kvm_run = vcpu->run;
7174 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
7175 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
7176 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
7177 kvm_run->debug.arch.exception = DB_VECTOR;
7178 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7181 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
7185 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
7187 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7190 r = kvm_x86_ops.skip_emulated_instruction(vcpu);
7195 * rflags is the old, "raw" value of the flags. The new value has
7196 * not been saved yet.
7198 * This is correct even for TF set by the guest, because "the
7199 * processor will not generate this exception after the instruction
7200 * that sets the TF flag".
7202 if (unlikely(rflags & X86_EFLAGS_TF))
7203 r = kvm_vcpu_do_singlestep(vcpu);
7206 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
7208 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
7210 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
7211 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
7212 struct kvm_run *kvm_run = vcpu->run;
7213 unsigned long eip = kvm_get_linear_rip(vcpu);
7214 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7215 vcpu->arch.guest_debug_dr7,
7219 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
7220 kvm_run->debug.arch.pc = eip;
7221 kvm_run->debug.arch.exception = DB_VECTOR;
7222 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7228 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
7229 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
7230 unsigned long eip = kvm_get_linear_rip(vcpu);
7231 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7236 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
7245 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
7247 switch (ctxt->opcode_len) {
7254 case 0xe6: /* OUT */
7258 case 0x6c: /* INS */
7260 case 0x6e: /* OUTS */
7267 case 0x33: /* RDPMC */
7276 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7277 int emulation_type, void *insn, int insn_len)
7280 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7281 bool writeback = true;
7282 bool write_fault_to_spt;
7284 if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, insn, insn_len)))
7287 vcpu->arch.l1tf_flush_l1d = true;
7290 * Clear write_fault_to_shadow_pgtable here to ensure it is
7293 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
7294 vcpu->arch.write_fault_to_shadow_pgtable = false;
7295 kvm_clear_exception_queue(vcpu);
7297 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
7298 init_emulate_ctxt(vcpu);
7301 * We will reenter on the same instruction since
7302 * we do not set complete_userspace_io. This does not
7303 * handle watchpoints yet, those would be handled in
7306 if (!(emulation_type & EMULTYPE_SKIP) &&
7307 kvm_vcpu_check_breakpoint(vcpu, &r))
7310 ctxt->interruptibility = 0;
7311 ctxt->have_exception = false;
7312 ctxt->exception.vector = -1;
7313 ctxt->perm_ok = false;
7315 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
7317 r = x86_decode_insn(ctxt, insn, insn_len);
7319 trace_kvm_emulate_insn_start(vcpu);
7320 ++vcpu->stat.insn_emulation;
7321 if (r != EMULATION_OK) {
7322 if ((emulation_type & EMULTYPE_TRAP_UD) ||
7323 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
7324 kvm_queue_exception(vcpu, UD_VECTOR);
7327 if (reexecute_instruction(vcpu, cr2_or_gpa,
7331 if (ctxt->have_exception) {
7333 * #UD should result in just EMULATION_FAILED, and trap-like
7334 * exception should not be encountered during decode.
7336 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
7337 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
7338 inject_emulated_exception(vcpu);
7341 return handle_emulation_failure(vcpu, emulation_type);
7345 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
7346 !is_vmware_backdoor_opcode(ctxt)) {
7347 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7352 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
7353 * for kvm_skip_emulated_instruction(). The caller is responsible for
7354 * updating interruptibility state and injecting single-step #DBs.
7356 if (emulation_type & EMULTYPE_SKIP) {
7357 kvm_rip_write(vcpu, ctxt->_eip);
7358 if (ctxt->eflags & X86_EFLAGS_RF)
7359 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
7363 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
7366 /* this is needed for vmware backdoor interface to work since it
7367 changes registers values during IO operation */
7368 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
7369 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7370 emulator_invalidate_register_cache(ctxt);
7374 if (emulation_type & EMULTYPE_PF) {
7375 /* Save the faulting GPA (cr2) in the address field */
7376 ctxt->exception.address = cr2_or_gpa;
7378 /* With shadow page tables, cr2 contains a GVA or nGPA. */
7379 if (vcpu->arch.mmu->direct_map) {
7380 ctxt->gpa_available = true;
7381 ctxt->gpa_val = cr2_or_gpa;
7384 /* Sanitize the address out of an abundance of paranoia. */
7385 ctxt->exception.address = 0;
7388 r = x86_emulate_insn(ctxt);
7390 if (r == EMULATION_INTERCEPTED)
7393 if (r == EMULATION_FAILED) {
7394 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
7398 return handle_emulation_failure(vcpu, emulation_type);
7401 if (ctxt->have_exception) {
7403 if (inject_emulated_exception(vcpu))
7405 } else if (vcpu->arch.pio.count) {
7406 if (!vcpu->arch.pio.in) {
7407 /* FIXME: return into emulator if single-stepping. */
7408 vcpu->arch.pio.count = 0;
7411 vcpu->arch.complete_userspace_io = complete_emulated_pio;
7414 } else if (vcpu->mmio_needed) {
7415 ++vcpu->stat.mmio_exits;
7417 if (!vcpu->mmio_is_write)
7420 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7421 } else if (r == EMULATION_RESTART)
7427 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7428 toggle_interruptibility(vcpu, ctxt->interruptibility);
7429 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7430 if (!ctxt->have_exception ||
7431 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
7432 kvm_rip_write(vcpu, ctxt->eip);
7433 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
7434 r = kvm_vcpu_do_singlestep(vcpu);
7435 if (kvm_x86_ops.update_emulated_instruction)
7436 kvm_x86_ops.update_emulated_instruction(vcpu);
7437 __kvm_set_rflags(vcpu, ctxt->eflags);
7441 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
7442 * do nothing, and it will be requested again as soon as
7443 * the shadow expires. But we still need to check here,
7444 * because POPF has no interrupt shadow.
7446 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
7447 kvm_make_request(KVM_REQ_EVENT, vcpu);
7449 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
7454 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
7456 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
7458 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
7460 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
7461 void *insn, int insn_len)
7463 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
7465 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
7467 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
7469 vcpu->arch.pio.count = 0;
7473 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
7475 vcpu->arch.pio.count = 0;
7477 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
7480 return kvm_skip_emulated_instruction(vcpu);
7483 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
7484 unsigned short port)
7486 unsigned long val = kvm_rax_read(vcpu);
7487 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
7493 * Workaround userspace that relies on old KVM behavior of %rip being
7494 * incremented prior to exiting to userspace to handle "OUT 0x7e".
7497 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
7498 vcpu->arch.complete_userspace_io =
7499 complete_fast_pio_out_port_0x7e;
7500 kvm_skip_emulated_instruction(vcpu);
7502 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7503 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
7508 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
7512 /* We should only ever be called with arch.pio.count equal to 1 */
7513 BUG_ON(vcpu->arch.pio.count != 1);
7515 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
7516 vcpu->arch.pio.count = 0;
7520 /* For size less than 4 we merge, else we zero extend */
7521 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7524 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7525 * the copy and tracing
7527 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7528 kvm_rax_write(vcpu, val);
7530 return kvm_skip_emulated_instruction(vcpu);
7533 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7534 unsigned short port)
7539 /* For size less than 4 we merge, else we zero extend */
7540 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7542 ret = emulator_pio_in(vcpu, size, port, &val, 1);
7544 kvm_rax_write(vcpu, val);
7548 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7549 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7554 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7559 ret = kvm_fast_pio_in(vcpu, size, port);
7561 ret = kvm_fast_pio_out(vcpu, size, port);
7562 return ret && kvm_skip_emulated_instruction(vcpu);
7564 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7566 static int kvmclock_cpu_down_prep(unsigned int cpu)
7568 __this_cpu_write(cpu_tsc_khz, 0);
7572 static void tsc_khz_changed(void *data)
7574 struct cpufreq_freqs *freq = data;
7575 unsigned long khz = 0;
7579 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7580 khz = cpufreq_quick_get(raw_smp_processor_id());
7583 __this_cpu_write(cpu_tsc_khz, khz);
7586 #ifdef CONFIG_X86_64
7587 static void kvm_hyperv_tsc_notifier(void)
7590 struct kvm_vcpu *vcpu;
7593 mutex_lock(&kvm_lock);
7594 list_for_each_entry(kvm, &vm_list, vm_list)
7595 kvm_make_mclock_inprogress_request(kvm);
7597 hyperv_stop_tsc_emulation();
7599 /* TSC frequency always matches when on Hyper-V */
7600 for_each_present_cpu(cpu)
7601 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7602 kvm_max_guest_tsc_khz = tsc_khz;
7604 list_for_each_entry(kvm, &vm_list, vm_list) {
7605 struct kvm_arch *ka = &kvm->arch;
7607 spin_lock(&ka->pvclock_gtod_sync_lock);
7609 pvclock_update_vm_gtod_copy(kvm);
7611 kvm_for_each_vcpu(cpu, vcpu, kvm)
7612 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7614 kvm_for_each_vcpu(cpu, vcpu, kvm)
7615 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7617 spin_unlock(&ka->pvclock_gtod_sync_lock);
7619 mutex_unlock(&kvm_lock);
7623 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7626 struct kvm_vcpu *vcpu;
7627 int i, send_ipi = 0;
7630 * We allow guests to temporarily run on slowing clocks,
7631 * provided we notify them after, or to run on accelerating
7632 * clocks, provided we notify them before. Thus time never
7635 * However, we have a problem. We can't atomically update
7636 * the frequency of a given CPU from this function; it is
7637 * merely a notifier, which can be called from any CPU.
7638 * Changing the TSC frequency at arbitrary points in time
7639 * requires a recomputation of local variables related to
7640 * the TSC for each VCPU. We must flag these local variables
7641 * to be updated and be sure the update takes place with the
7642 * new frequency before any guests proceed.
7644 * Unfortunately, the combination of hotplug CPU and frequency
7645 * change creates an intractable locking scenario; the order
7646 * of when these callouts happen is undefined with respect to
7647 * CPU hotplug, and they can race with each other. As such,
7648 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7649 * undefined; you can actually have a CPU frequency change take
7650 * place in between the computation of X and the setting of the
7651 * variable. To protect against this problem, all updates of
7652 * the per_cpu tsc_khz variable are done in an interrupt
7653 * protected IPI, and all callers wishing to update the value
7654 * must wait for a synchronous IPI to complete (which is trivial
7655 * if the caller is on the CPU already). This establishes the
7656 * necessary total order on variable updates.
7658 * Note that because a guest time update may take place
7659 * anytime after the setting of the VCPU's request bit, the
7660 * correct TSC value must be set before the request. However,
7661 * to ensure the update actually makes it to any guest which
7662 * starts running in hardware virtualization between the set
7663 * and the acquisition of the spinlock, we must also ping the
7664 * CPU after setting the request bit.
7668 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7670 mutex_lock(&kvm_lock);
7671 list_for_each_entry(kvm, &vm_list, vm_list) {
7672 kvm_for_each_vcpu(i, vcpu, kvm) {
7673 if (vcpu->cpu != cpu)
7675 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7676 if (vcpu->cpu != raw_smp_processor_id())
7680 mutex_unlock(&kvm_lock);
7682 if (freq->old < freq->new && send_ipi) {
7684 * We upscale the frequency. Must make the guest
7685 * doesn't see old kvmclock values while running with
7686 * the new frequency, otherwise we risk the guest sees
7687 * time go backwards.
7689 * In case we update the frequency for another cpu
7690 * (which might be in guest context) send an interrupt
7691 * to kick the cpu out of guest context. Next time
7692 * guest context is entered kvmclock will be updated,
7693 * so the guest will not see stale values.
7695 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7699 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7702 struct cpufreq_freqs *freq = data;
7705 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7707 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7710 for_each_cpu(cpu, freq->policy->cpus)
7711 __kvmclock_cpufreq_notifier(freq, cpu);
7716 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7717 .notifier_call = kvmclock_cpufreq_notifier
7720 static int kvmclock_cpu_online(unsigned int cpu)
7722 tsc_khz_changed(NULL);
7726 static void kvm_timer_init(void)
7728 max_tsc_khz = tsc_khz;
7730 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7731 #ifdef CONFIG_CPU_FREQ
7732 struct cpufreq_policy *policy;
7736 policy = cpufreq_cpu_get(cpu);
7738 if (policy->cpuinfo.max_freq)
7739 max_tsc_khz = policy->cpuinfo.max_freq;
7740 cpufreq_cpu_put(policy);
7744 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7745 CPUFREQ_TRANSITION_NOTIFIER);
7748 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7749 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7752 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7753 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7755 int kvm_is_in_guest(void)
7757 return __this_cpu_read(current_vcpu) != NULL;
7760 static int kvm_is_user_mode(void)
7764 if (__this_cpu_read(current_vcpu))
7765 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu));
7767 return user_mode != 0;
7770 static unsigned long kvm_get_guest_ip(void)
7772 unsigned long ip = 0;
7774 if (__this_cpu_read(current_vcpu))
7775 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7780 static void kvm_handle_intel_pt_intr(void)
7782 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7784 kvm_make_request(KVM_REQ_PMI, vcpu);
7785 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7786 (unsigned long *)&vcpu->arch.pmu.global_status);
7789 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7790 .is_in_guest = kvm_is_in_guest,
7791 .is_user_mode = kvm_is_user_mode,
7792 .get_guest_ip = kvm_get_guest_ip,
7793 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7796 #ifdef CONFIG_X86_64
7797 static void pvclock_gtod_update_fn(struct work_struct *work)
7801 struct kvm_vcpu *vcpu;
7804 mutex_lock(&kvm_lock);
7805 list_for_each_entry(kvm, &vm_list, vm_list)
7806 kvm_for_each_vcpu(i, vcpu, kvm)
7807 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7808 atomic_set(&kvm_guest_has_master_clock, 0);
7809 mutex_unlock(&kvm_lock);
7812 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7815 * Notification about pvclock gtod data update.
7817 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7820 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7821 struct timekeeper *tk = priv;
7823 update_pvclock_gtod(tk);
7825 /* disable master clock if host does not trust, or does not
7826 * use, TSC based clocksource.
7828 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7829 atomic_read(&kvm_guest_has_master_clock) != 0)
7830 queue_work(system_long_wq, &pvclock_gtod_work);
7835 static struct notifier_block pvclock_gtod_notifier = {
7836 .notifier_call = pvclock_gtod_notify,
7840 int kvm_arch_init(void *opaque)
7842 struct kvm_x86_init_ops *ops = opaque;
7845 if (kvm_x86_ops.hardware_enable) {
7846 printk(KERN_ERR "kvm: already loaded the other module\n");
7851 if (!ops->cpu_has_kvm_support()) {
7852 pr_err_ratelimited("kvm: no hardware support\n");
7856 if (ops->disabled_by_bios()) {
7857 pr_err_ratelimited("kvm: disabled by bios\n");
7863 * KVM explicitly assumes that the guest has an FPU and
7864 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7865 * vCPU's FPU state as a fxregs_state struct.
7867 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7868 printk(KERN_ERR "kvm: inadequate fpu\n");
7874 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7875 __alignof__(struct fpu), SLAB_ACCOUNT,
7877 if (!x86_fpu_cache) {
7878 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7882 x86_emulator_cache = kvm_alloc_emulator_cache();
7883 if (!x86_emulator_cache) {
7884 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7885 goto out_free_x86_fpu_cache;
7888 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
7889 if (!user_return_msrs) {
7890 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
7891 goto out_free_x86_emulator_cache;
7894 r = kvm_mmu_module_init();
7896 goto out_free_percpu;
7898 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7899 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7900 PT_PRESENT_MASK, 0, sme_me_mask);
7903 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7905 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7906 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7907 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7911 if (pi_inject_timer == -1)
7912 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7913 #ifdef CONFIG_X86_64
7914 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7916 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7917 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7923 free_percpu(user_return_msrs);
7924 out_free_x86_emulator_cache:
7925 kmem_cache_destroy(x86_emulator_cache);
7926 out_free_x86_fpu_cache:
7927 kmem_cache_destroy(x86_fpu_cache);
7932 void kvm_arch_exit(void)
7934 #ifdef CONFIG_X86_64
7935 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7936 clear_hv_tscchange_cb();
7939 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7941 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7942 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7943 CPUFREQ_TRANSITION_NOTIFIER);
7944 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7945 #ifdef CONFIG_X86_64
7946 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7948 kvm_x86_ops.hardware_enable = NULL;
7949 kvm_mmu_module_exit();
7950 free_percpu(user_return_msrs);
7951 kmem_cache_destroy(x86_fpu_cache);
7954 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7956 ++vcpu->stat.halt_exits;
7957 if (lapic_in_kernel(vcpu)) {
7958 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7961 vcpu->run->exit_reason = KVM_EXIT_HLT;
7965 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7967 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7969 int ret = kvm_skip_emulated_instruction(vcpu);
7971 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7972 * KVM_EXIT_DEBUG here.
7974 return kvm_vcpu_halt(vcpu) && ret;
7976 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7978 #ifdef CONFIG_X86_64
7979 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7980 unsigned long clock_type)
7982 struct kvm_clock_pairing clock_pairing;
7983 struct timespec64 ts;
7987 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7988 return -KVM_EOPNOTSUPP;
7990 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7991 return -KVM_EOPNOTSUPP;
7993 clock_pairing.sec = ts.tv_sec;
7994 clock_pairing.nsec = ts.tv_nsec;
7995 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7996 clock_pairing.flags = 0;
7997 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
8000 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
8001 sizeof(struct kvm_clock_pairing)))
8009 * kvm_pv_kick_cpu_op: Kick a vcpu.
8011 * @apicid - apicid of vcpu to be kicked.
8013 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
8015 struct kvm_lapic_irq lapic_irq;
8017 lapic_irq.shorthand = APIC_DEST_NOSHORT;
8018 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
8019 lapic_irq.level = 0;
8020 lapic_irq.dest_id = apicid;
8021 lapic_irq.msi_redir_hint = false;
8023 lapic_irq.delivery_mode = APIC_DM_REMRD;
8024 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
8027 bool kvm_apicv_activated(struct kvm *kvm)
8029 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
8031 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
8033 void kvm_apicv_init(struct kvm *kvm, bool enable)
8036 clear_bit(APICV_INHIBIT_REASON_DISABLE,
8037 &kvm->arch.apicv_inhibit_reasons);
8039 set_bit(APICV_INHIBIT_REASON_DISABLE,
8040 &kvm->arch.apicv_inhibit_reasons);
8042 EXPORT_SYMBOL_GPL(kvm_apicv_init);
8044 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
8046 struct kvm_vcpu *target = NULL;
8047 struct kvm_apic_map *map;
8050 map = rcu_dereference(kvm->arch.apic_map);
8052 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
8053 target = map->phys_map[dest_id]->vcpu;
8057 if (target && READ_ONCE(target->ready))
8058 kvm_vcpu_yield_to(target);
8061 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
8063 unsigned long nr, a0, a1, a2, a3, ret;
8066 if (kvm_hv_hypercall_enabled(vcpu->kvm))
8067 return kvm_hv_hypercall(vcpu);
8069 nr = kvm_rax_read(vcpu);
8070 a0 = kvm_rbx_read(vcpu);
8071 a1 = kvm_rcx_read(vcpu);
8072 a2 = kvm_rdx_read(vcpu);
8073 a3 = kvm_rsi_read(vcpu);
8075 trace_kvm_hypercall(nr, a0, a1, a2, a3);
8077 op_64_bit = is_64_bit_mode(vcpu);
8086 if (kvm_x86_ops.get_cpl(vcpu) != 0) {
8094 case KVM_HC_VAPIC_POLL_IRQ:
8097 case KVM_HC_KICK_CPU:
8098 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
8101 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
8102 kvm_sched_yield(vcpu->kvm, a1);
8105 #ifdef CONFIG_X86_64
8106 case KVM_HC_CLOCK_PAIRING:
8107 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
8110 case KVM_HC_SEND_IPI:
8111 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
8114 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
8116 case KVM_HC_SCHED_YIELD:
8117 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
8120 kvm_sched_yield(vcpu->kvm, a0);
8130 kvm_rax_write(vcpu, ret);
8132 ++vcpu->stat.hypercalls;
8133 return kvm_skip_emulated_instruction(vcpu);
8135 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
8137 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8139 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8140 char instruction[3];
8141 unsigned long rip = kvm_rip_read(vcpu);
8143 kvm_x86_ops.patch_hypercall(vcpu, instruction);
8145 return emulator_write_emulated(ctxt, rip, instruction, 3,
8149 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
8151 return vcpu->run->request_interrupt_window &&
8152 likely(!pic_in_kernel(vcpu->kvm));
8155 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
8157 struct kvm_run *kvm_run = vcpu->run;
8159 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
8160 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
8161 kvm_run->cr8 = kvm_get_cr8(vcpu);
8162 kvm_run->apic_base = kvm_get_apic_base(vcpu);
8163 kvm_run->ready_for_interrupt_injection =
8164 pic_in_kernel(vcpu->kvm) ||
8165 kvm_vcpu_ready_for_interrupt_injection(vcpu);
8168 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
8172 if (!kvm_x86_ops.update_cr8_intercept)
8175 if (!lapic_in_kernel(vcpu))
8178 if (vcpu->arch.apicv_active)
8181 if (!vcpu->arch.apic->vapic_addr)
8182 max_irr = kvm_lapic_find_highest_irr(vcpu);
8189 tpr = kvm_lapic_get_cr8(vcpu);
8191 kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr);
8194 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
8197 bool can_inject = true;
8199 /* try to reinject previous events if any */
8201 if (vcpu->arch.exception.injected) {
8202 kvm_x86_ops.queue_exception(vcpu);
8206 * Do not inject an NMI or interrupt if there is a pending
8207 * exception. Exceptions and interrupts are recognized at
8208 * instruction boundaries, i.e. the start of an instruction.
8209 * Trap-like exceptions, e.g. #DB, have higher priority than
8210 * NMIs and interrupts, i.e. traps are recognized before an
8211 * NMI/interrupt that's pending on the same instruction.
8212 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
8213 * priority, but are only generated (pended) during instruction
8214 * execution, i.e. a pending fault-like exception means the
8215 * fault occurred on the *previous* instruction and must be
8216 * serviced prior to recognizing any new events in order to
8217 * fully complete the previous instruction.
8219 else if (!vcpu->arch.exception.pending) {
8220 if (vcpu->arch.nmi_injected) {
8221 kvm_x86_ops.set_nmi(vcpu);
8223 } else if (vcpu->arch.interrupt.injected) {
8224 kvm_x86_ops.set_irq(vcpu);
8229 WARN_ON_ONCE(vcpu->arch.exception.injected &&
8230 vcpu->arch.exception.pending);
8233 * Call check_nested_events() even if we reinjected a previous event
8234 * in order for caller to determine if it should require immediate-exit
8235 * from L2 to L1 due to pending L1 events which require exit
8238 if (is_guest_mode(vcpu)) {
8239 r = kvm_x86_ops.nested_ops->check_events(vcpu);
8244 /* try to inject new event if pending */
8245 if (vcpu->arch.exception.pending) {
8246 trace_kvm_inj_exception(vcpu->arch.exception.nr,
8247 vcpu->arch.exception.has_error_code,
8248 vcpu->arch.exception.error_code);
8250 vcpu->arch.exception.pending = false;
8251 vcpu->arch.exception.injected = true;
8253 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
8254 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
8257 if (vcpu->arch.exception.nr == DB_VECTOR) {
8258 kvm_deliver_exception_payload(vcpu);
8259 if (vcpu->arch.dr7 & DR7_GD) {
8260 vcpu->arch.dr7 &= ~DR7_GD;
8261 kvm_update_dr7(vcpu);
8265 kvm_x86_ops.queue_exception(vcpu);
8270 * Finally, inject interrupt events. If an event cannot be injected
8271 * due to architectural conditions (e.g. IF=0) a window-open exit
8272 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
8273 * and can architecturally be injected, but we cannot do it right now:
8274 * an interrupt could have arrived just now and we have to inject it
8275 * as a vmexit, or there could already an event in the queue, which is
8276 * indicated by can_inject. In that case we request an immediate exit
8277 * in order to make progress and get back here for another iteration.
8278 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
8280 if (vcpu->arch.smi_pending) {
8281 r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY;
8285 vcpu->arch.smi_pending = false;
8286 ++vcpu->arch.smi_count;
8290 kvm_x86_ops.enable_smi_window(vcpu);
8293 if (vcpu->arch.nmi_pending) {
8294 r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY;
8298 --vcpu->arch.nmi_pending;
8299 vcpu->arch.nmi_injected = true;
8300 kvm_x86_ops.set_nmi(vcpu);
8302 WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0);
8304 if (vcpu->arch.nmi_pending)
8305 kvm_x86_ops.enable_nmi_window(vcpu);
8308 if (kvm_cpu_has_injectable_intr(vcpu)) {
8309 r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY;
8313 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
8314 kvm_x86_ops.set_irq(vcpu);
8315 WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0);
8317 if (kvm_cpu_has_injectable_intr(vcpu))
8318 kvm_x86_ops.enable_irq_window(vcpu);
8321 if (is_guest_mode(vcpu) &&
8322 kvm_x86_ops.nested_ops->hv_timer_pending &&
8323 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
8324 *req_immediate_exit = true;
8326 WARN_ON(vcpu->arch.exception.pending);
8330 *req_immediate_exit = true;
8334 static void process_nmi(struct kvm_vcpu *vcpu)
8339 * x86 is limited to one NMI running, and one NMI pending after it.
8340 * If an NMI is already in progress, limit further NMIs to just one.
8341 * Otherwise, allow two (and we'll inject the first one immediately).
8343 if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
8346 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
8347 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
8348 kvm_make_request(KVM_REQ_EVENT, vcpu);
8351 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
8354 flags |= seg->g << 23;
8355 flags |= seg->db << 22;
8356 flags |= seg->l << 21;
8357 flags |= seg->avl << 20;
8358 flags |= seg->present << 15;
8359 flags |= seg->dpl << 13;
8360 flags |= seg->s << 12;
8361 flags |= seg->type << 8;
8365 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
8367 struct kvm_segment seg;
8370 kvm_get_segment(vcpu, &seg, n);
8371 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
8374 offset = 0x7f84 + n * 12;
8376 offset = 0x7f2c + (n - 3) * 12;
8378 put_smstate(u32, buf, offset + 8, seg.base);
8379 put_smstate(u32, buf, offset + 4, seg.limit);
8380 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
8383 #ifdef CONFIG_X86_64
8384 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
8386 struct kvm_segment seg;
8390 kvm_get_segment(vcpu, &seg, n);
8391 offset = 0x7e00 + n * 16;
8393 flags = enter_smm_get_segment_flags(&seg) >> 8;
8394 put_smstate(u16, buf, offset, seg.selector);
8395 put_smstate(u16, buf, offset + 2, flags);
8396 put_smstate(u32, buf, offset + 4, seg.limit);
8397 put_smstate(u64, buf, offset + 8, seg.base);
8401 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
8404 struct kvm_segment seg;
8408 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
8409 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
8410 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
8411 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
8413 for (i = 0; i < 8; i++)
8414 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
8416 kvm_get_dr(vcpu, 6, &val);
8417 put_smstate(u32, buf, 0x7fcc, (u32)val);
8418 kvm_get_dr(vcpu, 7, &val);
8419 put_smstate(u32, buf, 0x7fc8, (u32)val);
8421 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8422 put_smstate(u32, buf, 0x7fc4, seg.selector);
8423 put_smstate(u32, buf, 0x7f64, seg.base);
8424 put_smstate(u32, buf, 0x7f60, seg.limit);
8425 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
8427 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8428 put_smstate(u32, buf, 0x7fc0, seg.selector);
8429 put_smstate(u32, buf, 0x7f80, seg.base);
8430 put_smstate(u32, buf, 0x7f7c, seg.limit);
8431 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
8433 kvm_x86_ops.get_gdt(vcpu, &dt);
8434 put_smstate(u32, buf, 0x7f74, dt.address);
8435 put_smstate(u32, buf, 0x7f70, dt.size);
8437 kvm_x86_ops.get_idt(vcpu, &dt);
8438 put_smstate(u32, buf, 0x7f58, dt.address);
8439 put_smstate(u32, buf, 0x7f54, dt.size);
8441 for (i = 0; i < 6; i++)
8442 enter_smm_save_seg_32(vcpu, buf, i);
8444 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
8447 put_smstate(u32, buf, 0x7efc, 0x00020000);
8448 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
8451 #ifdef CONFIG_X86_64
8452 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
8455 struct kvm_segment seg;
8459 for (i = 0; i < 16; i++)
8460 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
8462 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
8463 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
8465 kvm_get_dr(vcpu, 6, &val);
8466 put_smstate(u64, buf, 0x7f68, val);
8467 kvm_get_dr(vcpu, 7, &val);
8468 put_smstate(u64, buf, 0x7f60, val);
8470 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
8471 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
8472 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
8474 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
8477 put_smstate(u32, buf, 0x7efc, 0x00020064);
8479 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
8481 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8482 put_smstate(u16, buf, 0x7e90, seg.selector);
8483 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
8484 put_smstate(u32, buf, 0x7e94, seg.limit);
8485 put_smstate(u64, buf, 0x7e98, seg.base);
8487 kvm_x86_ops.get_idt(vcpu, &dt);
8488 put_smstate(u32, buf, 0x7e84, dt.size);
8489 put_smstate(u64, buf, 0x7e88, dt.address);
8491 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8492 put_smstate(u16, buf, 0x7e70, seg.selector);
8493 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
8494 put_smstate(u32, buf, 0x7e74, seg.limit);
8495 put_smstate(u64, buf, 0x7e78, seg.base);
8497 kvm_x86_ops.get_gdt(vcpu, &dt);
8498 put_smstate(u32, buf, 0x7e64, dt.size);
8499 put_smstate(u64, buf, 0x7e68, dt.address);
8501 for (i = 0; i < 6; i++)
8502 enter_smm_save_seg_64(vcpu, buf, i);
8506 static void enter_smm(struct kvm_vcpu *vcpu)
8508 struct kvm_segment cs, ds;
8513 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
8514 memset(buf, 0, 512);
8515 #ifdef CONFIG_X86_64
8516 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8517 enter_smm_save_state_64(vcpu, buf);
8520 enter_smm_save_state_32(vcpu, buf);
8523 * Give pre_enter_smm() a chance to make ISA-specific changes to the
8524 * vCPU state (e.g. leave guest mode) after we've saved the state into
8525 * the SMM state-save area.
8527 kvm_x86_ops.pre_enter_smm(vcpu, buf);
8529 vcpu->arch.hflags |= HF_SMM_MASK;
8530 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
8532 if (kvm_x86_ops.get_nmi_mask(vcpu))
8533 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
8535 kvm_x86_ops.set_nmi_mask(vcpu, true);
8537 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
8538 kvm_rip_write(vcpu, 0x8000);
8540 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
8541 kvm_x86_ops.set_cr0(vcpu, cr0);
8542 vcpu->arch.cr0 = cr0;
8544 kvm_x86_ops.set_cr4(vcpu, 0);
8546 /* Undocumented: IDT limit is set to zero on entry to SMM. */
8547 dt.address = dt.size = 0;
8548 kvm_x86_ops.set_idt(vcpu, &dt);
8550 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
8552 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
8553 cs.base = vcpu->arch.smbase;
8558 cs.limit = ds.limit = 0xffffffff;
8559 cs.type = ds.type = 0x3;
8560 cs.dpl = ds.dpl = 0;
8565 cs.avl = ds.avl = 0;
8566 cs.present = ds.present = 1;
8567 cs.unusable = ds.unusable = 0;
8568 cs.padding = ds.padding = 0;
8570 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8571 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8572 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8573 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8574 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8575 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8577 #ifdef CONFIG_X86_64
8578 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8579 kvm_x86_ops.set_efer(vcpu, 0);
8582 kvm_update_cpuid_runtime(vcpu);
8583 kvm_mmu_reset_context(vcpu);
8586 static void process_smi(struct kvm_vcpu *vcpu)
8588 vcpu->arch.smi_pending = true;
8589 kvm_make_request(KVM_REQ_EVENT, vcpu);
8592 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8593 unsigned long *vcpu_bitmap)
8597 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8599 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8600 NULL, vcpu_bitmap, cpus);
8602 free_cpumask_var(cpus);
8605 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8607 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8610 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8612 if (!lapic_in_kernel(vcpu))
8615 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8616 kvm_apic_update_apicv(vcpu);
8617 kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu);
8619 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8622 * NOTE: Do not hold any lock prior to calling this.
8624 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8625 * locked, because it calls __x86_set_memory_region() which does
8626 * synchronize_srcu(&kvm->srcu).
8628 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8630 struct kvm_vcpu *except;
8631 unsigned long old, new, expected;
8633 if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8634 !kvm_x86_ops.check_apicv_inhibit_reasons(bit))
8637 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8639 expected = new = old;
8641 __clear_bit(bit, &new);
8643 __set_bit(bit, &new);
8646 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8647 } while (old != expected);
8652 trace_kvm_apicv_update_request(activate, bit);
8653 if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8654 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate);
8657 * Sending request to update APICV for all other vcpus,
8658 * while update the calling vcpu immediately instead of
8659 * waiting for another #VMEXIT to handle the request.
8661 except = kvm_get_running_vcpu();
8662 kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE,
8665 kvm_vcpu_update_apicv(except);
8667 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8669 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8671 if (!kvm_apic_present(vcpu))
8674 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8676 if (irqchip_split(vcpu->kvm))
8677 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8679 if (vcpu->arch.apicv_active)
8680 kvm_x86_ops.sync_pir_to_irr(vcpu);
8681 if (ioapic_in_kernel(vcpu->kvm))
8682 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8685 if (is_guest_mode(vcpu))
8686 vcpu->arch.load_eoi_exitmap_pending = true;
8688 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8691 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8693 u64 eoi_exit_bitmap[4];
8695 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8698 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8699 vcpu_to_synic(vcpu)->vec_bitmap, 256);
8700 kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8703 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8704 unsigned long start, unsigned long end)
8706 unsigned long apic_address;
8709 * The physical address of apic access page is stored in the VMCS.
8710 * Update it when it becomes invalid.
8712 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8713 if (start <= apic_address && apic_address < end)
8714 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8717 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8719 if (!lapic_in_kernel(vcpu))
8722 if (!kvm_x86_ops.set_apic_access_page_addr)
8725 kvm_x86_ops.set_apic_access_page_addr(vcpu);
8728 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8730 smp_send_reschedule(vcpu->cpu);
8732 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8735 * Returns 1 to let vcpu_run() continue the guest execution loop without
8736 * exiting to the userspace. Otherwise, the value will be returned to the
8739 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8743 dm_request_for_irq_injection(vcpu) &&
8744 kvm_cpu_accept_dm_intr(vcpu);
8745 fastpath_t exit_fastpath;
8747 bool req_immediate_exit = false;
8749 if (kvm_request_pending(vcpu)) {
8750 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
8751 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
8756 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8757 kvm_mmu_unload(vcpu);
8758 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8759 __kvm_migrate_timers(vcpu);
8760 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8761 kvm_gen_update_masterclock(vcpu->kvm);
8762 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8763 kvm_gen_kvmclock_update(vcpu);
8764 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8765 r = kvm_guest_time_update(vcpu);
8769 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8770 kvm_mmu_sync_roots(vcpu);
8771 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8772 kvm_mmu_load_pgd(vcpu);
8773 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
8774 kvm_vcpu_flush_tlb_all(vcpu);
8776 /* Flushing all ASIDs flushes the current ASID... */
8777 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
8779 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
8780 kvm_vcpu_flush_tlb_current(vcpu);
8781 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu))
8782 kvm_vcpu_flush_tlb_guest(vcpu);
8784 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8785 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8789 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8790 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8791 vcpu->mmio_needed = 0;
8795 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8796 /* Page is swapped out. Do synthetic halt */
8797 vcpu->arch.apf.halted = true;
8801 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8802 record_steal_time(vcpu);
8803 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8805 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8807 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8808 kvm_pmu_handle_event(vcpu);
8809 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8810 kvm_pmu_deliver_pmi(vcpu);
8811 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8812 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8813 if (test_bit(vcpu->arch.pending_ioapic_eoi,
8814 vcpu->arch.ioapic_handled_vectors)) {
8815 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8816 vcpu->run->eoi.vector =
8817 vcpu->arch.pending_ioapic_eoi;
8822 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8823 vcpu_scan_ioapic(vcpu);
8824 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8825 vcpu_load_eoi_exitmap(vcpu);
8826 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8827 kvm_vcpu_reload_apic_access_page(vcpu);
8828 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8829 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8830 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8834 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8835 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8836 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8840 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8841 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8842 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8848 * KVM_REQ_HV_STIMER has to be processed after
8849 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8850 * depend on the guest clock being up-to-date
8852 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8853 kvm_hv_process_stimers(vcpu);
8854 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8855 kvm_vcpu_update_apicv(vcpu);
8856 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
8857 kvm_check_async_pf_completion(vcpu);
8858 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
8859 kvm_x86_ops.msr_filter_changed(vcpu);
8862 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8863 ++vcpu->stat.req_event;
8864 kvm_apic_accept_events(vcpu);
8865 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8870 inject_pending_event(vcpu, &req_immediate_exit);
8872 kvm_x86_ops.enable_irq_window(vcpu);
8874 if (kvm_lapic_enabled(vcpu)) {
8875 update_cr8_intercept(vcpu);
8876 kvm_lapic_sync_to_vapic(vcpu);
8880 r = kvm_mmu_reload(vcpu);
8882 goto cancel_injection;
8887 kvm_x86_ops.prepare_guest_switch(vcpu);
8890 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8891 * IPI are then delayed after guest entry, which ensures that they
8892 * result in virtual interrupt delivery.
8894 local_irq_disable();
8895 vcpu->mode = IN_GUEST_MODE;
8897 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8900 * 1) We should set ->mode before checking ->requests. Please see
8901 * the comment in kvm_vcpu_exiting_guest_mode().
8903 * 2) For APICv, we should set ->mode before checking PID.ON. This
8904 * pairs with the memory barrier implicit in pi_test_and_set_on
8905 * (see vmx_deliver_posted_interrupt).
8907 * 3) This also orders the write to mode from any reads to the page
8908 * tables done while the VCPU is running. Please see the comment
8909 * in kvm_flush_remote_tlbs.
8911 smp_mb__after_srcu_read_unlock();
8914 * This handles the case where a posted interrupt was
8915 * notified with kvm_vcpu_kick.
8917 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8918 kvm_x86_ops.sync_pir_to_irr(vcpu);
8920 if (kvm_vcpu_exit_request(vcpu)) {
8921 vcpu->mode = OUTSIDE_GUEST_MODE;
8925 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8927 goto cancel_injection;
8930 if (req_immediate_exit) {
8931 kvm_make_request(KVM_REQ_EVENT, vcpu);
8932 kvm_x86_ops.request_immediate_exit(vcpu);
8935 trace_kvm_entry(vcpu);
8937 fpregs_assert_state_consistent();
8938 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8939 switch_fpu_return();
8941 if (unlikely(vcpu->arch.switch_db_regs)) {
8943 set_debugreg(vcpu->arch.eff_db[0], 0);
8944 set_debugreg(vcpu->arch.eff_db[1], 1);
8945 set_debugreg(vcpu->arch.eff_db[2], 2);
8946 set_debugreg(vcpu->arch.eff_db[3], 3);
8947 set_debugreg(vcpu->arch.dr6, 6);
8948 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8951 exit_fastpath = kvm_x86_ops.run(vcpu);
8954 * Do this here before restoring debug registers on the host. And
8955 * since we do this before handling the vmexit, a DR access vmexit
8956 * can (a) read the correct value of the debug registers, (b) set
8957 * KVM_DEBUGREG_WONT_EXIT again.
8959 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8960 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8961 kvm_x86_ops.sync_dirty_debug_regs(vcpu);
8962 kvm_update_dr0123(vcpu);
8963 kvm_update_dr7(vcpu);
8964 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8968 * If the guest has used debug registers, at least dr7
8969 * will be disabled while returning to the host.
8970 * If we don't have active breakpoints in the host, we don't
8971 * care about the messed up debug address registers. But if
8972 * we have some of them active, restore the old state.
8974 if (hw_breakpoint_active())
8975 hw_breakpoint_restore();
8977 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
8978 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8980 vcpu->mode = OUTSIDE_GUEST_MODE;
8983 kvm_x86_ops.handle_exit_irqoff(vcpu);
8986 * Consume any pending interrupts, including the possible source of
8987 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8988 * An instruction is required after local_irq_enable() to fully unblock
8989 * interrupts on processors that implement an interrupt shadow, the
8990 * stat.exits increment will do nicely.
8992 kvm_before_interrupt(vcpu);
8995 local_irq_disable();
8996 kvm_after_interrupt(vcpu);
8998 if (lapic_in_kernel(vcpu)) {
8999 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
9000 if (delta != S64_MIN) {
9001 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
9002 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
9009 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9012 * Profile KVM exit RIPs:
9014 if (unlikely(prof_on == KVM_PROFILING)) {
9015 unsigned long rip = kvm_rip_read(vcpu);
9016 profile_hit(KVM_PROFILING, (void *)rip);
9019 if (unlikely(vcpu->arch.tsc_always_catchup))
9020 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9022 if (vcpu->arch.apic_attention)
9023 kvm_lapic_sync_from_vapic(vcpu);
9025 r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath);
9029 if (req_immediate_exit)
9030 kvm_make_request(KVM_REQ_EVENT, vcpu);
9031 kvm_x86_ops.cancel_injection(vcpu);
9032 if (unlikely(vcpu->arch.apic_attention))
9033 kvm_lapic_sync_from_vapic(vcpu);
9038 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
9040 if (!kvm_arch_vcpu_runnable(vcpu) &&
9041 (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) {
9042 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9043 kvm_vcpu_block(vcpu);
9044 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9046 if (kvm_x86_ops.post_block)
9047 kvm_x86_ops.post_block(vcpu);
9049 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
9053 kvm_apic_accept_events(vcpu);
9054 switch(vcpu->arch.mp_state) {
9055 case KVM_MP_STATE_HALTED:
9056 vcpu->arch.pv.pv_unhalted = false;
9057 vcpu->arch.mp_state =
9058 KVM_MP_STATE_RUNNABLE;
9060 case KVM_MP_STATE_RUNNABLE:
9061 vcpu->arch.apf.halted = false;
9063 case KVM_MP_STATE_INIT_RECEIVED:
9071 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
9073 if (is_guest_mode(vcpu))
9074 kvm_x86_ops.nested_ops->check_events(vcpu);
9076 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
9077 !vcpu->arch.apf.halted);
9080 static int vcpu_run(struct kvm_vcpu *vcpu)
9083 struct kvm *kvm = vcpu->kvm;
9085 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9086 vcpu->arch.l1tf_flush_l1d = true;
9089 if (kvm_vcpu_running(vcpu)) {
9090 r = vcpu_enter_guest(vcpu);
9092 r = vcpu_block(kvm, vcpu);
9098 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
9099 if (kvm_cpu_has_pending_timer(vcpu))
9100 kvm_inject_pending_timer_irqs(vcpu);
9102 if (dm_request_for_irq_injection(vcpu) &&
9103 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
9105 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
9106 ++vcpu->stat.request_irq_exits;
9110 if (__xfer_to_guest_mode_work_pending()) {
9111 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9112 r = xfer_to_guest_mode_handle_work(vcpu);
9115 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9119 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9124 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
9128 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9129 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
9130 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
9134 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
9136 BUG_ON(!vcpu->arch.pio.count);
9138 return complete_emulated_io(vcpu);
9142 * Implements the following, as a state machine:
9146 * for each mmio piece in the fragment
9154 * for each mmio piece in the fragment
9159 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
9161 struct kvm_run *run = vcpu->run;
9162 struct kvm_mmio_fragment *frag;
9165 BUG_ON(!vcpu->mmio_needed);
9167 /* Complete previous fragment */
9168 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
9169 len = min(8u, frag->len);
9170 if (!vcpu->mmio_is_write)
9171 memcpy(frag->data, run->mmio.data, len);
9173 if (frag->len <= 8) {
9174 /* Switch to the next fragment. */
9176 vcpu->mmio_cur_fragment++;
9178 /* Go forward to the next mmio piece. */
9184 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
9185 vcpu->mmio_needed = 0;
9187 /* FIXME: return into emulator if single-stepping. */
9188 if (vcpu->mmio_is_write)
9190 vcpu->mmio_read_completed = 1;
9191 return complete_emulated_io(vcpu);
9194 run->exit_reason = KVM_EXIT_MMIO;
9195 run->mmio.phys_addr = frag->gpa;
9196 if (vcpu->mmio_is_write)
9197 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
9198 run->mmio.len = min(8u, frag->len);
9199 run->mmio.is_write = vcpu->mmio_is_write;
9200 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
9204 static void kvm_save_current_fpu(struct fpu *fpu)
9207 * If the target FPU state is not resident in the CPU registers, just
9208 * memcpy() from current, else save CPU state directly to the target.
9210 if (test_thread_flag(TIF_NEED_FPU_LOAD))
9211 memcpy(&fpu->state, ¤t->thread.fpu.state,
9212 fpu_kernel_xstate_size);
9214 copy_fpregs_to_fpstate(fpu);
9217 /* Swap (qemu) user FPU context for the guest FPU context. */
9218 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
9222 kvm_save_current_fpu(vcpu->arch.user_fpu);
9224 /* PKRU is separately restored in kvm_x86_ops.run. */
9225 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
9226 ~XFEATURE_MASK_PKRU);
9228 fpregs_mark_activate();
9234 /* When vcpu_run ends, restore user space FPU context. */
9235 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
9239 kvm_save_current_fpu(vcpu->arch.guest_fpu);
9241 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
9243 fpregs_mark_activate();
9246 ++vcpu->stat.fpu_reload;
9250 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
9252 struct kvm_run *kvm_run = vcpu->run;
9256 kvm_sigset_activate(vcpu);
9257 kvm_load_guest_fpu(vcpu);
9259 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
9260 if (kvm_run->immediate_exit) {
9264 kvm_vcpu_block(vcpu);
9265 kvm_apic_accept_events(vcpu);
9266 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
9268 if (signal_pending(current)) {
9270 kvm_run->exit_reason = KVM_EXIT_INTR;
9271 ++vcpu->stat.signal_exits;
9276 if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
9281 if (kvm_run->kvm_dirty_regs) {
9282 r = sync_regs(vcpu);
9287 /* re-sync apic's tpr */
9288 if (!lapic_in_kernel(vcpu)) {
9289 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
9295 if (unlikely(vcpu->arch.complete_userspace_io)) {
9296 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
9297 vcpu->arch.complete_userspace_io = NULL;
9302 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
9304 if (kvm_run->immediate_exit)
9310 kvm_put_guest_fpu(vcpu);
9311 if (kvm_run->kvm_valid_regs)
9313 post_kvm_run_save(vcpu);
9314 kvm_sigset_deactivate(vcpu);
9320 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9322 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
9324 * We are here if userspace calls get_regs() in the middle of
9325 * instruction emulation. Registers state needs to be copied
9326 * back from emulation context to vcpu. Userspace shouldn't do
9327 * that usually, but some bad designed PV devices (vmware
9328 * backdoor interface) need this to work
9330 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
9331 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9333 regs->rax = kvm_rax_read(vcpu);
9334 regs->rbx = kvm_rbx_read(vcpu);
9335 regs->rcx = kvm_rcx_read(vcpu);
9336 regs->rdx = kvm_rdx_read(vcpu);
9337 regs->rsi = kvm_rsi_read(vcpu);
9338 regs->rdi = kvm_rdi_read(vcpu);
9339 regs->rsp = kvm_rsp_read(vcpu);
9340 regs->rbp = kvm_rbp_read(vcpu);
9341 #ifdef CONFIG_X86_64
9342 regs->r8 = kvm_r8_read(vcpu);
9343 regs->r9 = kvm_r9_read(vcpu);
9344 regs->r10 = kvm_r10_read(vcpu);
9345 regs->r11 = kvm_r11_read(vcpu);
9346 regs->r12 = kvm_r12_read(vcpu);
9347 regs->r13 = kvm_r13_read(vcpu);
9348 regs->r14 = kvm_r14_read(vcpu);
9349 regs->r15 = kvm_r15_read(vcpu);
9352 regs->rip = kvm_rip_read(vcpu);
9353 regs->rflags = kvm_get_rflags(vcpu);
9356 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9359 __get_regs(vcpu, regs);
9364 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9366 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
9367 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9369 kvm_rax_write(vcpu, regs->rax);
9370 kvm_rbx_write(vcpu, regs->rbx);
9371 kvm_rcx_write(vcpu, regs->rcx);
9372 kvm_rdx_write(vcpu, regs->rdx);
9373 kvm_rsi_write(vcpu, regs->rsi);
9374 kvm_rdi_write(vcpu, regs->rdi);
9375 kvm_rsp_write(vcpu, regs->rsp);
9376 kvm_rbp_write(vcpu, regs->rbp);
9377 #ifdef CONFIG_X86_64
9378 kvm_r8_write(vcpu, regs->r8);
9379 kvm_r9_write(vcpu, regs->r9);
9380 kvm_r10_write(vcpu, regs->r10);
9381 kvm_r11_write(vcpu, regs->r11);
9382 kvm_r12_write(vcpu, regs->r12);
9383 kvm_r13_write(vcpu, regs->r13);
9384 kvm_r14_write(vcpu, regs->r14);
9385 kvm_r15_write(vcpu, regs->r15);
9388 kvm_rip_write(vcpu, regs->rip);
9389 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
9391 vcpu->arch.exception.pending = false;
9393 kvm_make_request(KVM_REQ_EVENT, vcpu);
9396 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9399 __set_regs(vcpu, regs);
9404 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
9406 struct kvm_segment cs;
9408 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9412 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
9414 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9418 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9419 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9420 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9421 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9422 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9423 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9425 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9426 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9428 kvm_x86_ops.get_idt(vcpu, &dt);
9429 sregs->idt.limit = dt.size;
9430 sregs->idt.base = dt.address;
9431 kvm_x86_ops.get_gdt(vcpu, &dt);
9432 sregs->gdt.limit = dt.size;
9433 sregs->gdt.base = dt.address;
9435 sregs->cr0 = kvm_read_cr0(vcpu);
9436 sregs->cr2 = vcpu->arch.cr2;
9437 sregs->cr3 = kvm_read_cr3(vcpu);
9438 sregs->cr4 = kvm_read_cr4(vcpu);
9439 sregs->cr8 = kvm_get_cr8(vcpu);
9440 sregs->efer = vcpu->arch.efer;
9441 sregs->apic_base = kvm_get_apic_base(vcpu);
9443 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
9445 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
9446 set_bit(vcpu->arch.interrupt.nr,
9447 (unsigned long *)sregs->interrupt_bitmap);
9450 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
9451 struct kvm_sregs *sregs)
9454 __get_sregs(vcpu, sregs);
9459 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
9460 struct kvm_mp_state *mp_state)
9463 if (kvm_mpx_supported())
9464 kvm_load_guest_fpu(vcpu);
9466 kvm_apic_accept_events(vcpu);
9467 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
9468 vcpu->arch.pv.pv_unhalted)
9469 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
9471 mp_state->mp_state = vcpu->arch.mp_state;
9473 if (kvm_mpx_supported())
9474 kvm_put_guest_fpu(vcpu);
9479 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
9480 struct kvm_mp_state *mp_state)
9486 if (!lapic_in_kernel(vcpu) &&
9487 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
9491 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
9492 * INIT state; latched init should be reported using
9493 * KVM_SET_VCPU_EVENTS, so reject it here.
9495 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
9496 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
9497 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
9500 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
9501 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
9502 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
9504 vcpu->arch.mp_state = mp_state->mp_state;
9505 kvm_make_request(KVM_REQ_EVENT, vcpu);
9513 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
9514 int reason, bool has_error_code, u32 error_code)
9516 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9519 init_emulate_ctxt(vcpu);
9521 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9522 has_error_code, error_code);
9524 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9525 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
9526 vcpu->run->internal.ndata = 0;
9530 kvm_rip_write(vcpu, ctxt->eip);
9531 kvm_set_rflags(vcpu, ctxt->eflags);
9534 EXPORT_SYMBOL_GPL(kvm_task_switch);
9536 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9538 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
9540 * When EFER.LME and CR0.PG are set, the processor is in
9541 * 64-bit mode (though maybe in a 32-bit code segment).
9542 * CR4.PAE and EFER.LMA must be set.
9544 if (!(sregs->cr4 & X86_CR4_PAE)
9545 || !(sregs->efer & EFER_LMA))
9549 * Not in 64-bit mode: EFER.LMA is clear and the code
9550 * segment cannot be 64-bit.
9552 if (sregs->efer & EFER_LMA || sregs->cs.l)
9556 return kvm_valid_cr4(vcpu, sregs->cr4);
9559 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9561 struct msr_data apic_base_msr;
9562 int mmu_reset_needed = 0;
9563 int cpuid_update_needed = 0;
9564 int pending_vec, max_bits, idx;
9568 if (kvm_valid_sregs(vcpu, sregs))
9571 apic_base_msr.data = sregs->apic_base;
9572 apic_base_msr.host_initiated = true;
9573 if (kvm_set_apic_base(vcpu, &apic_base_msr))
9576 dt.size = sregs->idt.limit;
9577 dt.address = sregs->idt.base;
9578 kvm_x86_ops.set_idt(vcpu, &dt);
9579 dt.size = sregs->gdt.limit;
9580 dt.address = sregs->gdt.base;
9581 kvm_x86_ops.set_gdt(vcpu, &dt);
9583 vcpu->arch.cr2 = sregs->cr2;
9584 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9585 vcpu->arch.cr3 = sregs->cr3;
9586 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9588 kvm_set_cr8(vcpu, sregs->cr8);
9590 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9591 kvm_x86_ops.set_efer(vcpu, sregs->efer);
9593 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9594 kvm_x86_ops.set_cr0(vcpu, sregs->cr0);
9595 vcpu->arch.cr0 = sregs->cr0;
9597 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9598 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
9599 (X86_CR4_OSXSAVE | X86_CR4_PKE));
9600 kvm_x86_ops.set_cr4(vcpu, sregs->cr4);
9601 if (cpuid_update_needed)
9602 kvm_update_cpuid_runtime(vcpu);
9604 idx = srcu_read_lock(&vcpu->kvm->srcu);
9605 if (is_pae_paging(vcpu)) {
9606 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9607 mmu_reset_needed = 1;
9609 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9611 if (mmu_reset_needed)
9612 kvm_mmu_reset_context(vcpu);
9614 max_bits = KVM_NR_INTERRUPTS;
9615 pending_vec = find_first_bit(
9616 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9617 if (pending_vec < max_bits) {
9618 kvm_queue_interrupt(vcpu, pending_vec, false);
9619 pr_debug("Set back pending irq %d\n", pending_vec);
9622 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9623 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9624 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9625 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9626 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9627 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9629 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9630 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9632 update_cr8_intercept(vcpu);
9634 /* Older userspace won't unhalt the vcpu on reset. */
9635 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9636 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9638 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9640 kvm_make_request(KVM_REQ_EVENT, vcpu);
9647 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9648 struct kvm_sregs *sregs)
9653 ret = __set_sregs(vcpu, sregs);
9658 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9659 struct kvm_guest_debug *dbg)
9661 unsigned long rflags;
9666 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9668 if (vcpu->arch.exception.pending)
9670 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9671 kvm_queue_exception(vcpu, DB_VECTOR);
9673 kvm_queue_exception(vcpu, BP_VECTOR);
9677 * Read rflags as long as potentially injected trace flags are still
9680 rflags = kvm_get_rflags(vcpu);
9682 vcpu->guest_debug = dbg->control;
9683 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9684 vcpu->guest_debug = 0;
9686 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9687 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9688 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9689 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9691 for (i = 0; i < KVM_NR_DB_REGS; i++)
9692 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9694 kvm_update_dr7(vcpu);
9696 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9697 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9698 get_segment_base(vcpu, VCPU_SREG_CS);
9701 * Trigger an rflags update that will inject or remove the trace
9704 kvm_set_rflags(vcpu, rflags);
9706 kvm_x86_ops.update_exception_bitmap(vcpu);
9716 * Translate a guest virtual address to a guest physical address.
9718 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9719 struct kvm_translation *tr)
9721 unsigned long vaddr = tr->linear_address;
9727 idx = srcu_read_lock(&vcpu->kvm->srcu);
9728 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9729 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9730 tr->physical_address = gpa;
9731 tr->valid = gpa != UNMAPPED_GVA;
9739 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9741 struct fxregs_state *fxsave;
9745 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9746 memcpy(fpu->fpr, fxsave->st_space, 128);
9747 fpu->fcw = fxsave->cwd;
9748 fpu->fsw = fxsave->swd;
9749 fpu->ftwx = fxsave->twd;
9750 fpu->last_opcode = fxsave->fop;
9751 fpu->last_ip = fxsave->rip;
9752 fpu->last_dp = fxsave->rdp;
9753 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9759 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9761 struct fxregs_state *fxsave;
9765 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9767 memcpy(fxsave->st_space, fpu->fpr, 128);
9768 fxsave->cwd = fpu->fcw;
9769 fxsave->swd = fpu->fsw;
9770 fxsave->twd = fpu->ftwx;
9771 fxsave->fop = fpu->last_opcode;
9772 fxsave->rip = fpu->last_ip;
9773 fxsave->rdp = fpu->last_dp;
9774 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9780 static void store_regs(struct kvm_vcpu *vcpu)
9782 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9784 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9785 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9787 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9788 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9790 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9791 kvm_vcpu_ioctl_x86_get_vcpu_events(
9792 vcpu, &vcpu->run->s.regs.events);
9795 static int sync_regs(struct kvm_vcpu *vcpu)
9797 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9800 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9801 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9802 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9804 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9805 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9807 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9809 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9810 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9811 vcpu, &vcpu->run->s.regs.events))
9813 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9819 static void fx_init(struct kvm_vcpu *vcpu)
9821 fpstate_init(&vcpu->arch.guest_fpu->state);
9822 if (boot_cpu_has(X86_FEATURE_XSAVES))
9823 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9824 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9827 * Ensure guest xcr0 is valid for loading
9829 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9831 vcpu->arch.cr0 |= X86_CR0_ET;
9834 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9836 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9837 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9838 "guest TSC will not be reliable\n");
9843 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9848 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9849 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9851 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9853 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9855 r = kvm_mmu_create(vcpu);
9859 if (irqchip_in_kernel(vcpu->kvm)) {
9860 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9862 goto fail_mmu_destroy;
9863 if (kvm_apicv_activated(vcpu->kvm))
9864 vcpu->arch.apicv_active = true;
9866 static_key_slow_inc(&kvm_no_apic_vcpu);
9870 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9872 goto fail_free_lapic;
9873 vcpu->arch.pio_data = page_address(page);
9875 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9876 GFP_KERNEL_ACCOUNT);
9877 if (!vcpu->arch.mce_banks)
9878 goto fail_free_pio_data;
9879 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9881 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9882 GFP_KERNEL_ACCOUNT))
9883 goto fail_free_mce_banks;
9885 if (!alloc_emulate_ctxt(vcpu))
9886 goto free_wbinvd_dirty_mask;
9888 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9889 GFP_KERNEL_ACCOUNT);
9890 if (!vcpu->arch.user_fpu) {
9891 pr_err("kvm: failed to allocate userspace's fpu\n");
9892 goto free_emulate_ctxt;
9895 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9896 GFP_KERNEL_ACCOUNT);
9897 if (!vcpu->arch.guest_fpu) {
9898 pr_err("kvm: failed to allocate vcpu's fpu\n");
9903 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9905 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9907 kvm_async_pf_hash_reset(vcpu);
9910 vcpu->arch.pending_external_vector = -1;
9911 vcpu->arch.preempted_in_kernel = false;
9913 kvm_hv_vcpu_init(vcpu);
9915 r = kvm_x86_ops.vcpu_create(vcpu);
9917 goto free_guest_fpu;
9919 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9920 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9921 kvm_vcpu_mtrr_init(vcpu);
9923 kvm_vcpu_reset(vcpu, false);
9924 kvm_init_mmu(vcpu, false);
9929 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9931 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9933 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9934 free_wbinvd_dirty_mask:
9935 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9936 fail_free_mce_banks:
9937 kfree(vcpu->arch.mce_banks);
9939 free_page((unsigned long)vcpu->arch.pio_data);
9941 kvm_free_lapic(vcpu);
9943 kvm_mmu_destroy(vcpu);
9947 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9949 struct kvm *kvm = vcpu->kvm;
9951 kvm_hv_vcpu_postcreate(vcpu);
9953 if (mutex_lock_killable(&vcpu->mutex))
9956 kvm_synchronize_tsc(vcpu, 0);
9959 /* poll control enabled by default */
9960 vcpu->arch.msr_kvm_poll_control = 1;
9962 mutex_unlock(&vcpu->mutex);
9964 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
9965 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9966 KVMCLOCK_SYNC_PERIOD);
9969 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9971 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9974 kvm_release_pfn(cache->pfn, cache->dirty, cache);
9976 kvmclock_reset(vcpu);
9978 kvm_x86_ops.vcpu_free(vcpu);
9980 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9981 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9982 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9983 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9985 kvm_hv_vcpu_uninit(vcpu);
9986 kvm_pmu_destroy(vcpu);
9987 kfree(vcpu->arch.mce_banks);
9988 kvm_free_lapic(vcpu);
9989 idx = srcu_read_lock(&vcpu->kvm->srcu);
9990 kvm_mmu_destroy(vcpu);
9991 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9992 free_page((unsigned long)vcpu->arch.pio_data);
9993 kvfree(vcpu->arch.cpuid_entries);
9994 if (!lapic_in_kernel(vcpu))
9995 static_key_slow_dec(&kvm_no_apic_vcpu);
9998 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
10000 kvm_lapic_reset(vcpu, init_event);
10002 vcpu->arch.hflags = 0;
10004 vcpu->arch.smi_pending = 0;
10005 vcpu->arch.smi_count = 0;
10006 atomic_set(&vcpu->arch.nmi_queued, 0);
10007 vcpu->arch.nmi_pending = 0;
10008 vcpu->arch.nmi_injected = false;
10009 kvm_clear_interrupt_queue(vcpu);
10010 kvm_clear_exception_queue(vcpu);
10012 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
10013 kvm_update_dr0123(vcpu);
10014 vcpu->arch.dr6 = DR6_INIT;
10015 vcpu->arch.dr7 = DR7_FIXED_1;
10016 kvm_update_dr7(vcpu);
10018 vcpu->arch.cr2 = 0;
10020 kvm_make_request(KVM_REQ_EVENT, vcpu);
10021 vcpu->arch.apf.msr_en_val = 0;
10022 vcpu->arch.apf.msr_int_val = 0;
10023 vcpu->arch.st.msr_val = 0;
10025 kvmclock_reset(vcpu);
10027 kvm_clear_async_pf_completion_queue(vcpu);
10028 kvm_async_pf_hash_reset(vcpu);
10029 vcpu->arch.apf.halted = false;
10031 if (kvm_mpx_supported()) {
10032 void *mpx_state_buffer;
10035 * To avoid have the INIT path from kvm_apic_has_events() that be
10036 * called with loaded FPU and does not let userspace fix the state.
10039 kvm_put_guest_fpu(vcpu);
10040 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
10042 if (mpx_state_buffer)
10043 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
10044 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
10046 if (mpx_state_buffer)
10047 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
10049 kvm_load_guest_fpu(vcpu);
10053 kvm_pmu_reset(vcpu);
10054 vcpu->arch.smbase = 0x30000;
10056 vcpu->arch.msr_misc_features_enables = 0;
10058 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
10061 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
10062 vcpu->arch.regs_avail = ~0;
10063 vcpu->arch.regs_dirty = ~0;
10065 vcpu->arch.ia32_xss = 0;
10067 kvm_x86_ops.vcpu_reset(vcpu, init_event);
10070 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
10072 struct kvm_segment cs;
10074 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
10075 cs.selector = vector << 8;
10076 cs.base = vector << 12;
10077 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
10078 kvm_rip_write(vcpu, 0);
10081 int kvm_arch_hardware_enable(void)
10084 struct kvm_vcpu *vcpu;
10089 bool stable, backwards_tsc = false;
10091 kvm_user_return_msr_cpu_online();
10092 ret = kvm_x86_ops.hardware_enable();
10096 local_tsc = rdtsc();
10097 stable = !kvm_check_tsc_unstable();
10098 list_for_each_entry(kvm, &vm_list, vm_list) {
10099 kvm_for_each_vcpu(i, vcpu, kvm) {
10100 if (!stable && vcpu->cpu == smp_processor_id())
10101 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10102 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
10103 backwards_tsc = true;
10104 if (vcpu->arch.last_host_tsc > max_tsc)
10105 max_tsc = vcpu->arch.last_host_tsc;
10111 * Sometimes, even reliable TSCs go backwards. This happens on
10112 * platforms that reset TSC during suspend or hibernate actions, but
10113 * maintain synchronization. We must compensate. Fortunately, we can
10114 * detect that condition here, which happens early in CPU bringup,
10115 * before any KVM threads can be running. Unfortunately, we can't
10116 * bring the TSCs fully up to date with real time, as we aren't yet far
10117 * enough into CPU bringup that we know how much real time has actually
10118 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
10119 * variables that haven't been updated yet.
10121 * So we simply find the maximum observed TSC above, then record the
10122 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
10123 * the adjustment will be applied. Note that we accumulate
10124 * adjustments, in case multiple suspend cycles happen before some VCPU
10125 * gets a chance to run again. In the event that no KVM threads get a
10126 * chance to run, we will miss the entire elapsed period, as we'll have
10127 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
10128 * loose cycle time. This isn't too big a deal, since the loss will be
10129 * uniform across all VCPUs (not to mention the scenario is extremely
10130 * unlikely). It is possible that a second hibernate recovery happens
10131 * much faster than a first, causing the observed TSC here to be
10132 * smaller; this would require additional padding adjustment, which is
10133 * why we set last_host_tsc to the local tsc observed here.
10135 * N.B. - this code below runs only on platforms with reliable TSC,
10136 * as that is the only way backwards_tsc is set above. Also note
10137 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
10138 * have the same delta_cyc adjustment applied if backwards_tsc
10139 * is detected. Note further, this adjustment is only done once,
10140 * as we reset last_host_tsc on all VCPUs to stop this from being
10141 * called multiple times (one for each physical CPU bringup).
10143 * Platforms with unreliable TSCs don't have to deal with this, they
10144 * will be compensated by the logic in vcpu_load, which sets the TSC to
10145 * catchup mode. This will catchup all VCPUs to real time, but cannot
10146 * guarantee that they stay in perfect synchronization.
10148 if (backwards_tsc) {
10149 u64 delta_cyc = max_tsc - local_tsc;
10150 list_for_each_entry(kvm, &vm_list, vm_list) {
10151 kvm->arch.backwards_tsc_observed = true;
10152 kvm_for_each_vcpu(i, vcpu, kvm) {
10153 vcpu->arch.tsc_offset_adjustment += delta_cyc;
10154 vcpu->arch.last_host_tsc = local_tsc;
10155 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
10159 * We have to disable TSC offset matching.. if you were
10160 * booting a VM while issuing an S4 host suspend....
10161 * you may have some problem. Solving this issue is
10162 * left as an exercise to the reader.
10164 kvm->arch.last_tsc_nsec = 0;
10165 kvm->arch.last_tsc_write = 0;
10172 void kvm_arch_hardware_disable(void)
10174 kvm_x86_ops.hardware_disable();
10175 drop_user_return_notifiers();
10178 int kvm_arch_hardware_setup(void *opaque)
10180 struct kvm_x86_init_ops *ops = opaque;
10183 rdmsrl_safe(MSR_EFER, &host_efer);
10185 if (boot_cpu_has(X86_FEATURE_XSAVES))
10186 rdmsrl(MSR_IA32_XSS, host_xss);
10188 r = ops->hardware_setup();
10192 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
10194 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
10197 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
10198 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
10199 #undef __kvm_cpu_cap_has
10201 if (kvm_has_tsc_control) {
10203 * Make sure the user can only configure tsc_khz values that
10204 * fit into a signed integer.
10205 * A min value is not calculated because it will always
10206 * be 1 on all machines.
10208 u64 max = min(0x7fffffffULL,
10209 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
10210 kvm_max_guest_tsc_khz = max;
10212 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
10215 kvm_init_msr_list();
10219 void kvm_arch_hardware_unsetup(void)
10221 kvm_x86_ops.hardware_unsetup();
10224 int kvm_arch_check_processor_compat(void *opaque)
10226 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
10227 struct kvm_x86_init_ops *ops = opaque;
10229 WARN_ON(!irqs_disabled());
10231 if (__cr4_reserved_bits(cpu_has, c) !=
10232 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
10235 return ops->check_processor_compatibility();
10238 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
10240 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
10242 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
10244 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
10246 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
10249 struct static_key kvm_no_apic_vcpu __read_mostly;
10250 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
10252 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
10254 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
10256 vcpu->arch.l1tf_flush_l1d = true;
10257 if (pmu->version && unlikely(pmu->event_count)) {
10258 pmu->need_cleanup = true;
10259 kvm_make_request(KVM_REQ_PMU, vcpu);
10261 kvm_x86_ops.sched_in(vcpu, cpu);
10264 void kvm_arch_free_vm(struct kvm *kvm)
10266 kfree(kvm->arch.hyperv.hv_pa_pg);
10271 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
10276 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
10277 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
10278 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
10279 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
10280 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
10281 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
10283 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
10284 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
10285 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
10286 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
10287 &kvm->arch.irq_sources_bitmap);
10289 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
10290 mutex_init(&kvm->arch.apic_map_lock);
10291 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
10293 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
10294 pvclock_update_vm_gtod_copy(kvm);
10296 kvm->arch.guest_can_read_msr_platform_info = true;
10298 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
10299 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
10301 kvm_hv_init_vm(kvm);
10302 kvm_page_track_init(kvm);
10303 kvm_mmu_init_vm(kvm);
10305 return kvm_x86_ops.vm_init(kvm);
10308 int kvm_arch_post_init_vm(struct kvm *kvm)
10310 return kvm_mmu_post_init_vm(kvm);
10313 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
10316 kvm_mmu_unload(vcpu);
10320 static void kvm_free_vcpus(struct kvm *kvm)
10323 struct kvm_vcpu *vcpu;
10326 * Unpin any mmu pages first.
10328 kvm_for_each_vcpu(i, vcpu, kvm) {
10329 kvm_clear_async_pf_completion_queue(vcpu);
10330 kvm_unload_vcpu_mmu(vcpu);
10332 kvm_for_each_vcpu(i, vcpu, kvm)
10333 kvm_vcpu_destroy(vcpu);
10335 mutex_lock(&kvm->lock);
10336 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
10337 kvm->vcpus[i] = NULL;
10339 atomic_set(&kvm->online_vcpus, 0);
10340 mutex_unlock(&kvm->lock);
10343 void kvm_arch_sync_events(struct kvm *kvm)
10345 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
10346 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
10350 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
10353 unsigned long hva, old_npages;
10354 struct kvm_memslots *slots = kvm_memslots(kvm);
10355 struct kvm_memory_slot *slot;
10357 /* Called with kvm->slots_lock held. */
10358 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
10361 slot = id_to_memslot(slots, id);
10363 if (slot && slot->npages)
10367 * MAP_SHARED to prevent internal slot pages from being moved
10370 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
10371 MAP_SHARED | MAP_ANONYMOUS, 0);
10372 if (IS_ERR((void *)hva))
10373 return PTR_ERR((void *)hva);
10375 if (!slot || !slot->npages)
10378 old_npages = slot->npages;
10382 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
10383 struct kvm_userspace_memory_region m;
10385 m.slot = id | (i << 16);
10387 m.guest_phys_addr = gpa;
10388 m.userspace_addr = hva;
10389 m.memory_size = size;
10390 r = __kvm_set_memory_region(kvm, &m);
10396 vm_munmap(hva, old_npages * PAGE_SIZE);
10400 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
10402 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
10404 kvm_mmu_pre_destroy_vm(kvm);
10407 void kvm_arch_destroy_vm(struct kvm *kvm)
10411 if (current->mm == kvm->mm) {
10413 * Free memory regions allocated on behalf of userspace,
10414 * unless the the memory map has changed due to process exit
10417 mutex_lock(&kvm->slots_lock);
10418 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
10420 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
10422 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
10423 mutex_unlock(&kvm->slots_lock);
10425 if (kvm_x86_ops.vm_destroy)
10426 kvm_x86_ops.vm_destroy(kvm);
10427 for (i = 0; i < kvm->arch.msr_filter.count; i++)
10428 kfree(kvm->arch.msr_filter.ranges[i].bitmap);
10429 kvm_pic_destroy(kvm);
10430 kvm_ioapic_destroy(kvm);
10431 kvm_free_vcpus(kvm);
10432 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
10433 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
10434 kvm_mmu_uninit_vm(kvm);
10435 kvm_page_track_cleanup(kvm);
10436 kvm_hv_destroy_vm(kvm);
10439 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
10443 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10444 kvfree(slot->arch.rmap[i]);
10445 slot->arch.rmap[i] = NULL;
10450 kvfree(slot->arch.lpage_info[i - 1]);
10451 slot->arch.lpage_info[i - 1] = NULL;
10454 kvm_page_track_free_memslot(slot);
10457 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
10458 unsigned long npages)
10463 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
10464 * old arrays will be freed by __kvm_set_memory_region() if installing
10465 * the new memslot is successful.
10467 memset(&slot->arch, 0, sizeof(slot->arch));
10469 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10470 struct kvm_lpage_info *linfo;
10471 unsigned long ugfn;
10475 lpages = gfn_to_index(slot->base_gfn + npages - 1,
10476 slot->base_gfn, level) + 1;
10478 slot->arch.rmap[i] =
10479 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
10480 GFP_KERNEL_ACCOUNT);
10481 if (!slot->arch.rmap[i])
10486 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
10490 slot->arch.lpage_info[i - 1] = linfo;
10492 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
10493 linfo[0].disallow_lpage = 1;
10494 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
10495 linfo[lpages - 1].disallow_lpage = 1;
10496 ugfn = slot->userspace_addr >> PAGE_SHIFT;
10498 * If the gfn and userspace address are not aligned wrt each
10499 * other, disable large page support for this slot.
10501 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
10504 for (j = 0; j < lpages; ++j)
10505 linfo[j].disallow_lpage = 1;
10509 if (kvm_page_track_create_memslot(slot, npages))
10515 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10516 kvfree(slot->arch.rmap[i]);
10517 slot->arch.rmap[i] = NULL;
10521 kvfree(slot->arch.lpage_info[i - 1]);
10522 slot->arch.lpage_info[i - 1] = NULL;
10527 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
10529 struct kvm_vcpu *vcpu;
10533 * memslots->generation has been incremented.
10534 * mmio generation may have reached its maximum value.
10536 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
10538 /* Force re-initialization of steal_time cache */
10539 kvm_for_each_vcpu(i, vcpu, kvm)
10540 kvm_vcpu_kick(vcpu);
10543 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10544 struct kvm_memory_slot *memslot,
10545 const struct kvm_userspace_memory_region *mem,
10546 enum kvm_mr_change change)
10548 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10549 return kvm_alloc_memslot_metadata(memslot,
10550 mem->memory_size >> PAGE_SHIFT);
10554 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10555 struct kvm_memory_slot *old,
10556 struct kvm_memory_slot *new,
10557 enum kvm_mr_change change)
10560 * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot.
10561 * See comments below.
10563 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY))
10567 * Dirty logging tracks sptes in 4k granularity, meaning that large
10568 * sptes have to be split. If live migration is successful, the guest
10569 * in the source machine will be destroyed and large sptes will be
10570 * created in the destination. However, if the guest continues to run
10571 * in the source machine (for example if live migration fails), small
10572 * sptes will remain around and cause bad performance.
10574 * Scan sptes if dirty logging has been stopped, dropping those
10575 * which can be collapsed into a single large-page spte. Later
10576 * page faults will create the large-page sptes.
10578 * There is no need to do this in any of the following cases:
10579 * CREATE: No dirty mappings will already exist.
10580 * MOVE/DELETE: The old mappings will already have been cleaned up by
10581 * kvm_arch_flush_shadow_memslot()
10583 if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10584 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10585 kvm_mmu_zap_collapsible_sptes(kvm, new);
10588 * Enable or disable dirty logging for the slot.
10590 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old
10591 * slot have been zapped so no dirty logging updates are needed for
10593 * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible
10594 * any mappings that might be created in it will consume the
10595 * properties of the new slot and do not need to be updated here.
10597 * When PML is enabled, the kvm_x86_ops dirty logging hooks are
10598 * called to enable/disable dirty logging.
10600 * When disabling dirty logging with PML enabled, the D-bit is set
10601 * for sptes in the slot in order to prevent unnecessary GPA
10602 * logging in the PML buffer (and potential PML buffer full VMEXIT).
10603 * This guarantees leaving PML enabled for the guest's lifetime
10604 * won't have any additional overhead from PML when the guest is
10605 * running with dirty logging disabled.
10607 * When enabling dirty logging, large sptes are write-protected
10608 * so they can be split on first write. New large sptes cannot
10609 * be created for this slot until the end of the logging.
10610 * See the comments in fast_page_fault().
10611 * For small sptes, nothing is done if the dirty log is in the
10612 * initial-all-set state. Otherwise, depending on whether pml
10613 * is enabled the D-bit or the W-bit will be cleared.
10615 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10616 if (kvm_x86_ops.slot_enable_log_dirty) {
10617 kvm_x86_ops.slot_enable_log_dirty(kvm, new);
10620 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10621 PG_LEVEL_2M : PG_LEVEL_4K;
10624 * If we're with initial-all-set, we don't need
10625 * to write protect any small page because
10626 * they're reported as dirty already. However
10627 * we still need to write-protect huge pages
10628 * so that the page split can happen lazily on
10629 * the first write to the huge page.
10631 kvm_mmu_slot_remove_write_access(kvm, new, level);
10634 if (kvm_x86_ops.slot_disable_log_dirty)
10635 kvm_x86_ops.slot_disable_log_dirty(kvm, new);
10639 void kvm_arch_commit_memory_region(struct kvm *kvm,
10640 const struct kvm_userspace_memory_region *mem,
10641 struct kvm_memory_slot *old,
10642 const struct kvm_memory_slot *new,
10643 enum kvm_mr_change change)
10645 if (!kvm->arch.n_requested_mmu_pages)
10646 kvm_mmu_change_mmu_pages(kvm,
10647 kvm_mmu_calculate_default_mmu_pages(kvm));
10650 * FIXME: const-ify all uses of struct kvm_memory_slot.
10652 kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change);
10654 /* Free the arrays associated with the old memslot. */
10655 if (change == KVM_MR_MOVE)
10656 kvm_arch_free_memslot(kvm, old);
10659 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10661 kvm_mmu_zap_all(kvm);
10664 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10665 struct kvm_memory_slot *slot)
10667 kvm_page_track_flush_slot(kvm, slot);
10670 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10672 return (is_guest_mode(vcpu) &&
10673 kvm_x86_ops.guest_apic_has_interrupt &&
10674 kvm_x86_ops.guest_apic_has_interrupt(vcpu));
10677 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10679 if (!list_empty_careful(&vcpu->async_pf.done))
10682 if (kvm_apic_has_events(vcpu))
10685 if (vcpu->arch.pv.pv_unhalted)
10688 if (vcpu->arch.exception.pending)
10691 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10692 (vcpu->arch.nmi_pending &&
10693 kvm_x86_ops.nmi_allowed(vcpu, false)))
10696 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10697 (vcpu->arch.smi_pending &&
10698 kvm_x86_ops.smi_allowed(vcpu, false)))
10701 if (kvm_arch_interrupt_allowed(vcpu) &&
10702 (kvm_cpu_has_interrupt(vcpu) ||
10703 kvm_guest_apic_has_interrupt(vcpu)))
10706 if (kvm_hv_has_stimer_pending(vcpu))
10709 if (is_guest_mode(vcpu) &&
10710 kvm_x86_ops.nested_ops->hv_timer_pending &&
10711 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
10717 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10719 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10722 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10724 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10727 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10728 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10729 kvm_test_request(KVM_REQ_EVENT, vcpu))
10732 if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu))
10738 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10740 return vcpu->arch.preempted_in_kernel;
10743 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10745 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10748 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10750 return kvm_x86_ops.interrupt_allowed(vcpu, false);
10753 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10755 if (is_64_bit_mode(vcpu))
10756 return kvm_rip_read(vcpu);
10757 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10758 kvm_rip_read(vcpu));
10760 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10762 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10764 return kvm_get_linear_rip(vcpu) == linear_rip;
10766 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10768 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10770 unsigned long rflags;
10772 rflags = kvm_x86_ops.get_rflags(vcpu);
10773 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10774 rflags &= ~X86_EFLAGS_TF;
10777 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10779 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10781 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10782 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10783 rflags |= X86_EFLAGS_TF;
10784 kvm_x86_ops.set_rflags(vcpu, rflags);
10787 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10789 __kvm_set_rflags(vcpu, rflags);
10790 kvm_make_request(KVM_REQ_EVENT, vcpu);
10792 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10794 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10798 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10802 r = kvm_mmu_reload(vcpu);
10806 if (!vcpu->arch.mmu->direct_map &&
10807 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10810 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10813 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10815 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
10817 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10820 static inline u32 kvm_async_pf_next_probe(u32 key)
10822 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
10825 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10827 u32 key = kvm_async_pf_hash_fn(gfn);
10829 while (vcpu->arch.apf.gfns[key] != ~0)
10830 key = kvm_async_pf_next_probe(key);
10832 vcpu->arch.apf.gfns[key] = gfn;
10835 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10838 u32 key = kvm_async_pf_hash_fn(gfn);
10840 for (i = 0; i < ASYNC_PF_PER_VCPU &&
10841 (vcpu->arch.apf.gfns[key] != gfn &&
10842 vcpu->arch.apf.gfns[key] != ~0); i++)
10843 key = kvm_async_pf_next_probe(key);
10848 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10850 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10853 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10857 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10859 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
10863 vcpu->arch.apf.gfns[i] = ~0;
10865 j = kvm_async_pf_next_probe(j);
10866 if (vcpu->arch.apf.gfns[j] == ~0)
10868 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10870 * k lies cyclically in ]i,j]
10872 * |....j i.k.| or |.k..j i...|
10874 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10875 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10880 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
10882 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
10884 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
10888 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
10890 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
10892 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
10893 &token, offset, sizeof(token));
10896 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
10898 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
10901 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
10902 &val, offset, sizeof(val)))
10908 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10910 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10913 if (!kvm_pv_async_pf_enabled(vcpu) ||
10914 (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0))
10920 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10922 if (unlikely(!lapic_in_kernel(vcpu) ||
10923 kvm_event_needs_reinjection(vcpu) ||
10924 vcpu->arch.exception.pending))
10927 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10931 * If interrupts are off we cannot even use an artificial
10934 return kvm_arch_interrupt_allowed(vcpu);
10937 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10938 struct kvm_async_pf *work)
10940 struct x86_exception fault;
10942 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10943 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10945 if (kvm_can_deliver_async_pf(vcpu) &&
10946 !apf_put_user_notpresent(vcpu)) {
10947 fault.vector = PF_VECTOR;
10948 fault.error_code_valid = true;
10949 fault.error_code = 0;
10950 fault.nested_page_fault = false;
10951 fault.address = work->arch.token;
10952 fault.async_page_fault = true;
10953 kvm_inject_page_fault(vcpu, &fault);
10957 * It is not possible to deliver a paravirtualized asynchronous
10958 * page fault, but putting the guest in an artificial halt state
10959 * can be beneficial nevertheless: if an interrupt arrives, we
10960 * can deliver it timely and perhaps the guest will schedule
10961 * another process. When the instruction that triggered a page
10962 * fault is retried, hopefully the page will be ready in the host.
10964 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10969 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10970 struct kvm_async_pf *work)
10972 struct kvm_lapic_irq irq = {
10973 .delivery_mode = APIC_DM_FIXED,
10974 .vector = vcpu->arch.apf.vec
10977 if (work->wakeup_all)
10978 work->arch.token = ~0; /* broadcast wakeup */
10980 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10981 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
10983 if ((work->wakeup_all || work->notpresent_injected) &&
10984 kvm_pv_async_pf_enabled(vcpu) &&
10985 !apf_put_user_ready(vcpu, work->arch.token)) {
10986 vcpu->arch.apf.pageready_pending = true;
10987 kvm_apic_set_irq(vcpu, &irq, NULL);
10990 vcpu->arch.apf.halted = false;
10991 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10994 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
10996 kvm_make_request(KVM_REQ_APF_READY, vcpu);
10997 if (!vcpu->arch.apf.pageready_pending)
10998 kvm_vcpu_kick(vcpu);
11001 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
11003 if (!kvm_pv_async_pf_enabled(vcpu))
11006 return apf_pageready_slot_free(vcpu);
11009 void kvm_arch_start_assignment(struct kvm *kvm)
11011 atomic_inc(&kvm->arch.assigned_device_count);
11013 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
11015 void kvm_arch_end_assignment(struct kvm *kvm)
11017 atomic_dec(&kvm->arch.assigned_device_count);
11019 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
11021 bool kvm_arch_has_assigned_device(struct kvm *kvm)
11023 return atomic_read(&kvm->arch.assigned_device_count);
11025 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
11027 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
11029 atomic_inc(&kvm->arch.noncoherent_dma_count);
11031 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
11033 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
11035 atomic_dec(&kvm->arch.noncoherent_dma_count);
11037 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
11039 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
11041 return atomic_read(&kvm->arch.noncoherent_dma_count);
11043 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
11045 bool kvm_arch_has_irq_bypass(void)
11050 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
11051 struct irq_bypass_producer *prod)
11053 struct kvm_kernel_irqfd *irqfd =
11054 container_of(cons, struct kvm_kernel_irqfd, consumer);
11057 irqfd->producer = prod;
11058 kvm_arch_start_assignment(irqfd->kvm);
11059 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm,
11060 prod->irq, irqfd->gsi, 1);
11063 kvm_arch_end_assignment(irqfd->kvm);
11068 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
11069 struct irq_bypass_producer *prod)
11072 struct kvm_kernel_irqfd *irqfd =
11073 container_of(cons, struct kvm_kernel_irqfd, consumer);
11075 WARN_ON(irqfd->producer != prod);
11076 irqfd->producer = NULL;
11079 * When producer of consumer is unregistered, we change back to
11080 * remapped mode, so we can re-use the current implementation
11081 * when the irq is masked/disabled or the consumer side (KVM
11082 * int this case doesn't want to receive the interrupts.
11084 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
11086 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
11087 " fails: %d\n", irqfd->consumer.token, ret);
11089 kvm_arch_end_assignment(irqfd->kvm);
11092 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
11093 uint32_t guest_irq, bool set)
11095 return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set);
11098 bool kvm_vector_hashing_enabled(void)
11100 return vector_hashing;
11103 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
11105 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
11107 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
11110 int kvm_spec_ctrl_test_value(u64 value)
11113 * test that setting IA32_SPEC_CTRL to given value
11114 * is allowed by the host processor
11118 unsigned long flags;
11121 local_irq_save(flags);
11123 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
11125 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
11128 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
11130 local_irq_restore(flags);
11134 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
11136 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
11138 struct x86_exception fault;
11139 u32 access = error_code &
11140 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
11142 if (!(error_code & PFERR_PRESENT_MASK) ||
11143 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) {
11145 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
11146 * tables probably do not match the TLB. Just proceed
11147 * with the error code that the processor gave.
11149 fault.vector = PF_VECTOR;
11150 fault.error_code_valid = true;
11151 fault.error_code = error_code;
11152 fault.nested_page_fault = false;
11153 fault.address = gva;
11155 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
11157 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
11160 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
11161 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
11162 * indicates whether exit to userspace is needed.
11164 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
11165 struct x86_exception *e)
11167 if (r == X86EMUL_PROPAGATE_FAULT) {
11168 kvm_inject_emulated_page_fault(vcpu, e);
11173 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
11174 * while handling a VMX instruction KVM could've handled the request
11175 * correctly by exiting to userspace and performing I/O but there
11176 * doesn't seem to be a real use-case behind such requests, just return
11177 * KVM_EXIT_INTERNAL_ERROR for now.
11179 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11180 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11181 vcpu->run->internal.ndata = 0;
11185 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
11187 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
11190 struct x86_exception e;
11192 unsigned long roots_to_free = 0;
11199 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
11200 if (r != X86EMUL_CONTINUE)
11201 return kvm_handle_memory_failure(vcpu, r, &e);
11203 if (operand.pcid >> 12 != 0) {
11204 kvm_inject_gp(vcpu, 0);
11208 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
11211 case INVPCID_TYPE_INDIV_ADDR:
11212 if ((!pcid_enabled && (operand.pcid != 0)) ||
11213 is_noncanonical_address(operand.gla, vcpu)) {
11214 kvm_inject_gp(vcpu, 0);
11217 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
11218 return kvm_skip_emulated_instruction(vcpu);
11220 case INVPCID_TYPE_SINGLE_CTXT:
11221 if (!pcid_enabled && (operand.pcid != 0)) {
11222 kvm_inject_gp(vcpu, 0);
11226 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
11227 kvm_mmu_sync_roots(vcpu);
11228 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
11231 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
11232 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd)
11234 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
11236 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
11238 * If neither the current cr3 nor any of the prev_roots use the
11239 * given PCID, then nothing needs to be done here because a
11240 * resync will happen anyway before switching to any other CR3.
11243 return kvm_skip_emulated_instruction(vcpu);
11245 case INVPCID_TYPE_ALL_NON_GLOBAL:
11247 * Currently, KVM doesn't mark global entries in the shadow
11248 * page tables, so a non-global flush just degenerates to a
11249 * global flush. If needed, we could optimize this later by
11250 * keeping track of global entries in shadow page tables.
11254 case INVPCID_TYPE_ALL_INCL_GLOBAL:
11255 kvm_mmu_unload(vcpu);
11256 return kvm_skip_emulated_instruction(vcpu);
11259 BUG(); /* We have already checked above that type <= 3 */
11262 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
11264 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
11265 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
11266 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
11267 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
11268 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
11269 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
11270 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
11271 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
11272 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
11273 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
11274 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
11275 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
11276 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
11277 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
11278 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
11279 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
11280 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
11281 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
11282 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
11283 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
11284 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
11285 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);