2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/mem_encrypt.h>
59 #include <trace/events/kvm.h>
61 #include <asm/debugreg.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70 #include <asm/mshyperv.h>
71 #include <asm/hypervisor.h>
72 #include <asm/intel_pt.h>
74 #define CREATE_TRACE_POINTS
77 #define MAX_IO_MSRS 256
78 #define KVM_MAX_MCE_BANKS 32
79 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
80 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
82 #define emul_to_vcpu(ctxt) \
83 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
86 * - enable syscall per default because its emulated by KVM
87 * - enable LME and LMA per default on 64 bit KVM
91 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
93 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
96 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
97 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
99 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
100 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
102 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
103 static void process_nmi(struct kvm_vcpu *vcpu);
104 static void enter_smm(struct kvm_vcpu *vcpu);
105 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
106 static void store_regs(struct kvm_vcpu *vcpu);
107 static int sync_regs(struct kvm_vcpu *vcpu);
109 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
110 EXPORT_SYMBOL_GPL(kvm_x86_ops);
112 static bool __read_mostly ignore_msrs = 0;
113 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
115 static bool __read_mostly report_ignored_msrs = true;
116 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
118 unsigned int min_timer_period_us = 200;
119 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
121 static bool __read_mostly kvmclock_periodic_sync = true;
122 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
124 bool __read_mostly kvm_has_tsc_control;
125 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
126 u32 __read_mostly kvm_max_guest_tsc_khz;
127 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
128 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
129 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
130 u64 __read_mostly kvm_max_tsc_scaling_ratio;
131 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
132 u64 __read_mostly kvm_default_tsc_scaling_ratio;
133 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
135 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
136 static u32 __read_mostly tsc_tolerance_ppm = 250;
137 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
139 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
140 unsigned int __read_mostly lapic_timer_advance_ns = 1000;
141 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
142 EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
144 static bool __read_mostly vector_hashing = true;
145 module_param(vector_hashing, bool, S_IRUGO);
147 bool __read_mostly enable_vmware_backdoor = false;
148 module_param(enable_vmware_backdoor, bool, S_IRUGO);
149 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
151 static bool __read_mostly force_emulation_prefix = false;
152 module_param(force_emulation_prefix, bool, S_IRUGO);
154 #define KVM_NR_SHARED_MSRS 16
156 struct kvm_shared_msrs_global {
158 u32 msrs[KVM_NR_SHARED_MSRS];
161 struct kvm_shared_msrs {
162 struct user_return_notifier urn;
164 struct kvm_shared_msr_values {
167 } values[KVM_NR_SHARED_MSRS];
170 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
171 static struct kvm_shared_msrs __percpu *shared_msrs;
173 struct kvm_stats_debugfs_item debugfs_entries[] = {
174 { "pf_fixed", VCPU_STAT(pf_fixed) },
175 { "pf_guest", VCPU_STAT(pf_guest) },
176 { "tlb_flush", VCPU_STAT(tlb_flush) },
177 { "invlpg", VCPU_STAT(invlpg) },
178 { "exits", VCPU_STAT(exits) },
179 { "io_exits", VCPU_STAT(io_exits) },
180 { "mmio_exits", VCPU_STAT(mmio_exits) },
181 { "signal_exits", VCPU_STAT(signal_exits) },
182 { "irq_window", VCPU_STAT(irq_window_exits) },
183 { "nmi_window", VCPU_STAT(nmi_window_exits) },
184 { "halt_exits", VCPU_STAT(halt_exits) },
185 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
186 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
187 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
188 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
189 { "hypercalls", VCPU_STAT(hypercalls) },
190 { "request_irq", VCPU_STAT(request_irq_exits) },
191 { "irq_exits", VCPU_STAT(irq_exits) },
192 { "host_state_reload", VCPU_STAT(host_state_reload) },
193 { "fpu_reload", VCPU_STAT(fpu_reload) },
194 { "insn_emulation", VCPU_STAT(insn_emulation) },
195 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
196 { "irq_injections", VCPU_STAT(irq_injections) },
197 { "nmi_injections", VCPU_STAT(nmi_injections) },
198 { "req_event", VCPU_STAT(req_event) },
199 { "l1d_flush", VCPU_STAT(l1d_flush) },
200 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
201 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
202 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
203 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
204 { "mmu_flooded", VM_STAT(mmu_flooded) },
205 { "mmu_recycled", VM_STAT(mmu_recycled) },
206 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
207 { "mmu_unsync", VM_STAT(mmu_unsync) },
208 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
209 { "largepages", VM_STAT(lpages) },
210 { "max_mmu_page_hash_collisions",
211 VM_STAT(max_mmu_page_hash_collisions) },
215 u64 __read_mostly host_xcr0;
217 struct kmem_cache *x86_fpu_cache;
218 EXPORT_SYMBOL_GPL(x86_fpu_cache);
220 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
222 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
225 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
226 vcpu->arch.apf.gfns[i] = ~0;
229 static void kvm_on_user_return(struct user_return_notifier *urn)
232 struct kvm_shared_msrs *locals
233 = container_of(urn, struct kvm_shared_msrs, urn);
234 struct kvm_shared_msr_values *values;
238 * Disabling irqs at this point since the following code could be
239 * interrupted and executed through kvm_arch_hardware_disable()
241 local_irq_save(flags);
242 if (locals->registered) {
243 locals->registered = false;
244 user_return_notifier_unregister(urn);
246 local_irq_restore(flags);
247 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
248 values = &locals->values[slot];
249 if (values->host != values->curr) {
250 wrmsrl(shared_msrs_global.msrs[slot], values->host);
251 values->curr = values->host;
256 static void shared_msr_update(unsigned slot, u32 msr)
259 unsigned int cpu = smp_processor_id();
260 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
262 /* only read, and nobody should modify it at this time,
263 * so don't need lock */
264 if (slot >= shared_msrs_global.nr) {
265 printk(KERN_ERR "kvm: invalid MSR slot!");
268 rdmsrl_safe(msr, &value);
269 smsr->values[slot].host = value;
270 smsr->values[slot].curr = value;
273 void kvm_define_shared_msr(unsigned slot, u32 msr)
275 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
276 shared_msrs_global.msrs[slot] = msr;
277 if (slot >= shared_msrs_global.nr)
278 shared_msrs_global.nr = slot + 1;
280 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
282 static void kvm_shared_msr_cpu_online(void)
286 for (i = 0; i < shared_msrs_global.nr; ++i)
287 shared_msr_update(i, shared_msrs_global.msrs[i]);
290 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
292 unsigned int cpu = smp_processor_id();
293 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
296 if (((value ^ smsr->values[slot].curr) & mask) == 0)
298 smsr->values[slot].curr = value;
299 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
303 if (!smsr->registered) {
304 smsr->urn.on_user_return = kvm_on_user_return;
305 user_return_notifier_register(&smsr->urn);
306 smsr->registered = true;
310 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
312 static void drop_user_return_notifiers(void)
314 unsigned int cpu = smp_processor_id();
315 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
317 if (smsr->registered)
318 kvm_on_user_return(&smsr->urn);
321 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
323 return vcpu->arch.apic_base;
325 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
327 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
329 return kvm_apic_mode(kvm_get_apic_base(vcpu));
331 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
333 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
335 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
336 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
337 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
338 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
340 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
342 if (!msr_info->host_initiated) {
343 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
345 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
349 kvm_lapic_set_base(vcpu, msr_info->data);
352 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
354 asmlinkage __visible void kvm_spurious_fault(void)
356 /* Fault while not rebooting. We want the trace. */
359 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
361 #define EXCPT_BENIGN 0
362 #define EXCPT_CONTRIBUTORY 1
365 static int exception_class(int vector)
375 return EXCPT_CONTRIBUTORY;
382 #define EXCPT_FAULT 0
384 #define EXCPT_ABORT 2
385 #define EXCPT_INTERRUPT 3
387 static int exception_type(int vector)
391 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
392 return EXCPT_INTERRUPT;
396 /* #DB is trap, as instruction watchpoints are handled elsewhere */
397 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
400 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
403 /* Reserved exceptions will result in fault */
407 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
409 unsigned nr = vcpu->arch.exception.nr;
410 bool has_payload = vcpu->arch.exception.has_payload;
411 unsigned long payload = vcpu->arch.exception.payload;
419 * "Certain debug exceptions may clear bit 0-3. The
420 * remaining contents of the DR6 register are never
421 * cleared by the processor".
423 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
425 * DR6.RTM is set by all #DB exceptions that don't clear it.
427 vcpu->arch.dr6 |= DR6_RTM;
428 vcpu->arch.dr6 |= payload;
430 * Bit 16 should be set in the payload whenever the #DB
431 * exception should clear DR6.RTM. This makes the payload
432 * compatible with the pending debug exceptions under VMX.
433 * Though not currently documented in the SDM, this also
434 * makes the payload compatible with the exit qualification
435 * for #DB exceptions under VMX.
437 vcpu->arch.dr6 ^= payload & DR6_RTM;
440 vcpu->arch.cr2 = payload;
444 vcpu->arch.exception.has_payload = false;
445 vcpu->arch.exception.payload = 0;
447 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
449 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
450 unsigned nr, bool has_error, u32 error_code,
451 bool has_payload, unsigned long payload, bool reinject)
456 kvm_make_request(KVM_REQ_EVENT, vcpu);
458 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
460 if (has_error && !is_protmode(vcpu))
464 * On vmentry, vcpu->arch.exception.pending is only
465 * true if an event injection was blocked by
466 * nested_run_pending. In that case, however,
467 * vcpu_enter_guest requests an immediate exit,
468 * and the guest shouldn't proceed far enough to
471 WARN_ON_ONCE(vcpu->arch.exception.pending);
472 vcpu->arch.exception.injected = true;
473 if (WARN_ON_ONCE(has_payload)) {
475 * A reinjected event has already
476 * delivered its payload.
482 vcpu->arch.exception.pending = true;
483 vcpu->arch.exception.injected = false;
485 vcpu->arch.exception.has_error_code = has_error;
486 vcpu->arch.exception.nr = nr;
487 vcpu->arch.exception.error_code = error_code;
488 vcpu->arch.exception.has_payload = has_payload;
489 vcpu->arch.exception.payload = payload;
491 * In guest mode, payload delivery should be deferred,
492 * so that the L1 hypervisor can intercept #PF before
493 * CR2 is modified (or intercept #DB before DR6 is
494 * modified under nVMX). However, for ABI
495 * compatibility with KVM_GET_VCPU_EVENTS and
496 * KVM_SET_VCPU_EVENTS, we can't delay payload
497 * delivery unless userspace has enabled this
498 * functionality via the per-VM capability,
499 * KVM_CAP_EXCEPTION_PAYLOAD.
501 if (!vcpu->kvm->arch.exception_payload_enabled ||
502 !is_guest_mode(vcpu))
503 kvm_deliver_exception_payload(vcpu);
507 /* to check exception */
508 prev_nr = vcpu->arch.exception.nr;
509 if (prev_nr == DF_VECTOR) {
510 /* triple fault -> shutdown */
511 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
514 class1 = exception_class(prev_nr);
515 class2 = exception_class(nr);
516 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
517 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
519 * Generate double fault per SDM Table 5-5. Set
520 * exception.pending = true so that the double fault
521 * can trigger a nested vmexit.
523 vcpu->arch.exception.pending = true;
524 vcpu->arch.exception.injected = false;
525 vcpu->arch.exception.has_error_code = true;
526 vcpu->arch.exception.nr = DF_VECTOR;
527 vcpu->arch.exception.error_code = 0;
528 vcpu->arch.exception.has_payload = false;
529 vcpu->arch.exception.payload = 0;
531 /* replace previous exception with a new one in a hope
532 that instruction re-execution will regenerate lost
537 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
539 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
541 EXPORT_SYMBOL_GPL(kvm_queue_exception);
543 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
545 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
547 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
549 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
550 unsigned long payload)
552 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
555 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
556 u32 error_code, unsigned long payload)
558 kvm_multiple_exception(vcpu, nr, true, error_code,
559 true, payload, false);
562 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
565 kvm_inject_gp(vcpu, 0);
567 return kvm_skip_emulated_instruction(vcpu);
571 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
573 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
575 ++vcpu->stat.pf_guest;
576 vcpu->arch.exception.nested_apf =
577 is_guest_mode(vcpu) && fault->async_page_fault;
578 if (vcpu->arch.exception.nested_apf) {
579 vcpu->arch.apf.nested_apf_token = fault->address;
580 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
582 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
586 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
588 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
590 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
591 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
593 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
595 return fault->nested_page_fault;
598 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
600 atomic_inc(&vcpu->arch.nmi_queued);
601 kvm_make_request(KVM_REQ_NMI, vcpu);
603 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
605 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
607 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
609 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
611 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
613 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
615 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
618 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
619 * a #GP and return false.
621 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
623 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
625 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
628 EXPORT_SYMBOL_GPL(kvm_require_cpl);
630 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
632 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
635 kvm_queue_exception(vcpu, UD_VECTOR);
638 EXPORT_SYMBOL_GPL(kvm_require_dr);
641 * This function will be used to read from the physical memory of the currently
642 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
643 * can read from guest physical or from the guest's guest physical memory.
645 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
646 gfn_t ngfn, void *data, int offset, int len,
649 struct x86_exception exception;
653 ngpa = gfn_to_gpa(ngfn);
654 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
655 if (real_gfn == UNMAPPED_GVA)
658 real_gfn = gpa_to_gfn(real_gfn);
660 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
662 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
664 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
665 void *data, int offset, int len, u32 access)
667 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
668 data, offset, len, access);
672 * Load the pae pdptrs. Return true is they are all valid.
674 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
676 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
677 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
680 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
682 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
683 offset * sizeof(u64), sizeof(pdpte),
684 PFERR_USER_MASK|PFERR_WRITE_MASK);
689 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
690 if ((pdpte[i] & PT_PRESENT_MASK) &&
692 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
699 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
700 __set_bit(VCPU_EXREG_PDPTR,
701 (unsigned long *)&vcpu->arch.regs_avail);
702 __set_bit(VCPU_EXREG_PDPTR,
703 (unsigned long *)&vcpu->arch.regs_dirty);
708 EXPORT_SYMBOL_GPL(load_pdptrs);
710 bool pdptrs_changed(struct kvm_vcpu *vcpu)
712 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
718 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu))
721 if (!test_bit(VCPU_EXREG_PDPTR,
722 (unsigned long *)&vcpu->arch.regs_avail))
725 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
726 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
727 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
728 PFERR_USER_MASK | PFERR_WRITE_MASK);
731 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
736 EXPORT_SYMBOL_GPL(pdptrs_changed);
738 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
740 unsigned long old_cr0 = kvm_read_cr0(vcpu);
741 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
746 if (cr0 & 0xffffffff00000000UL)
750 cr0 &= ~CR0_RESERVED_BITS;
752 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
755 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
758 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
760 if ((vcpu->arch.efer & EFER_LME)) {
765 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
770 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
775 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
778 kvm_x86_ops->set_cr0(vcpu, cr0);
780 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
781 kvm_clear_async_pf_completion_queue(vcpu);
782 kvm_async_pf_hash_reset(vcpu);
785 if ((cr0 ^ old_cr0) & update_bits)
786 kvm_mmu_reset_context(vcpu);
788 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
789 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
790 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
791 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
795 EXPORT_SYMBOL_GPL(kvm_set_cr0);
797 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
799 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
801 EXPORT_SYMBOL_GPL(kvm_lmsw);
803 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
805 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
806 !vcpu->guest_xcr0_loaded) {
807 /* kvm_set_xcr() also depends on this */
808 if (vcpu->arch.xcr0 != host_xcr0)
809 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
810 vcpu->guest_xcr0_loaded = 1;
814 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
816 if (vcpu->guest_xcr0_loaded) {
817 if (vcpu->arch.xcr0 != host_xcr0)
818 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
819 vcpu->guest_xcr0_loaded = 0;
823 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
826 u64 old_xcr0 = vcpu->arch.xcr0;
829 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
830 if (index != XCR_XFEATURE_ENABLED_MASK)
832 if (!(xcr0 & XFEATURE_MASK_FP))
834 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
838 * Do not allow the guest to set bits that we do not support
839 * saving. However, xcr0 bit 0 is always set, even if the
840 * emulated CPU does not support XSAVE (see fx_init).
842 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
843 if (xcr0 & ~valid_bits)
846 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
847 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
850 if (xcr0 & XFEATURE_MASK_AVX512) {
851 if (!(xcr0 & XFEATURE_MASK_YMM))
853 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
856 vcpu->arch.xcr0 = xcr0;
858 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
859 kvm_update_cpuid(vcpu);
863 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
865 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
866 __kvm_set_xcr(vcpu, index, xcr)) {
867 kvm_inject_gp(vcpu, 0);
872 EXPORT_SYMBOL_GPL(kvm_set_xcr);
874 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
876 unsigned long old_cr4 = kvm_read_cr4(vcpu);
877 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
878 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
880 if (cr4 & CR4_RESERVED_BITS)
883 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
886 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
889 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
892 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
895 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
898 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
901 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
904 if (is_long_mode(vcpu)) {
905 if (!(cr4 & X86_CR4_PAE))
907 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
908 && ((cr4 ^ old_cr4) & pdptr_bits)
909 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
913 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
914 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
917 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
918 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
922 if (kvm_x86_ops->set_cr4(vcpu, cr4))
925 if (((cr4 ^ old_cr4) & pdptr_bits) ||
926 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
927 kvm_mmu_reset_context(vcpu);
929 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
930 kvm_update_cpuid(vcpu);
934 EXPORT_SYMBOL_GPL(kvm_set_cr4);
936 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
938 bool skip_tlb_flush = false;
940 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
943 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
944 cr3 &= ~X86_CR3_PCID_NOFLUSH;
948 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
949 if (!skip_tlb_flush) {
950 kvm_mmu_sync_roots(vcpu);
951 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956 if (is_long_mode(vcpu) &&
957 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
959 else if (is_pae(vcpu) && is_paging(vcpu) &&
960 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
963 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
964 vcpu->arch.cr3 = cr3;
965 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
969 EXPORT_SYMBOL_GPL(kvm_set_cr3);
971 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
973 if (cr8 & CR8_RESERVED_BITS)
975 if (lapic_in_kernel(vcpu))
976 kvm_lapic_set_tpr(vcpu, cr8);
978 vcpu->arch.cr8 = cr8;
981 EXPORT_SYMBOL_GPL(kvm_set_cr8);
983 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
985 if (lapic_in_kernel(vcpu))
986 return kvm_lapic_get_cr8(vcpu);
988 return vcpu->arch.cr8;
990 EXPORT_SYMBOL_GPL(kvm_get_cr8);
992 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
996 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
997 for (i = 0; i < KVM_NR_DB_REGS; i++)
998 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
999 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1003 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1005 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1006 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1009 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1013 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1014 dr7 = vcpu->arch.guest_debug_dr7;
1016 dr7 = vcpu->arch.dr7;
1017 kvm_x86_ops->set_dr7(vcpu, dr7);
1018 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1019 if (dr7 & DR7_BP_EN_MASK)
1020 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1023 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1025 u64 fixed = DR6_FIXED_1;
1027 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1032 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1036 vcpu->arch.db[dr] = val;
1037 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1038 vcpu->arch.eff_db[dr] = val;
1043 if (val & 0xffffffff00000000ULL)
1044 return -1; /* #GP */
1045 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1046 kvm_update_dr6(vcpu);
1051 if (val & 0xffffffff00000000ULL)
1052 return -1; /* #GP */
1053 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1054 kvm_update_dr7(vcpu);
1061 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1063 if (__kvm_set_dr(vcpu, dr, val)) {
1064 kvm_inject_gp(vcpu, 0);
1069 EXPORT_SYMBOL_GPL(kvm_set_dr);
1071 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1075 *val = vcpu->arch.db[dr];
1080 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1081 *val = vcpu->arch.dr6;
1083 *val = kvm_x86_ops->get_dr6(vcpu);
1088 *val = vcpu->arch.dr7;
1093 EXPORT_SYMBOL_GPL(kvm_get_dr);
1095 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1097 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1101 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1104 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1105 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1108 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1111 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1112 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1114 * This list is modified at module load time to reflect the
1115 * capabilities of the host cpu. This capabilities test skips MSRs that are
1116 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1117 * may depend on host virtualization features rather than host cpu features.
1120 static u32 msrs_to_save[] = {
1121 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1123 #ifdef CONFIG_X86_64
1124 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1126 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1127 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1128 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES,
1129 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1130 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1131 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1132 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1133 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1134 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1137 static unsigned num_msrs_to_save;
1139 static u32 emulated_msrs[] = {
1140 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1141 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1142 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1143 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1144 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1145 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1146 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1148 HV_X64_MSR_VP_INDEX,
1149 HV_X64_MSR_VP_RUNTIME,
1150 HV_X64_MSR_SCONTROL,
1151 HV_X64_MSR_STIMER0_CONFIG,
1152 HV_X64_MSR_VP_ASSIST_PAGE,
1153 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1154 HV_X64_MSR_TSC_EMULATION_STATUS,
1156 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1159 MSR_IA32_TSC_ADJUST,
1160 MSR_IA32_TSCDEADLINE,
1161 MSR_IA32_MISC_ENABLE,
1162 MSR_IA32_MCG_STATUS,
1164 MSR_IA32_MCG_EXT_CTL,
1168 MSR_MISC_FEATURES_ENABLES,
1169 MSR_AMD64_VIRT_SPEC_CTRL,
1172 static unsigned num_emulated_msrs;
1175 * List of msr numbers which are used to expose MSR-based features that
1176 * can be used by a hypervisor to validate requested CPU features.
1178 static u32 msr_based_features[] = {
1180 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1181 MSR_IA32_VMX_PINBASED_CTLS,
1182 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1183 MSR_IA32_VMX_PROCBASED_CTLS,
1184 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1185 MSR_IA32_VMX_EXIT_CTLS,
1186 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1187 MSR_IA32_VMX_ENTRY_CTLS,
1189 MSR_IA32_VMX_CR0_FIXED0,
1190 MSR_IA32_VMX_CR0_FIXED1,
1191 MSR_IA32_VMX_CR4_FIXED0,
1192 MSR_IA32_VMX_CR4_FIXED1,
1193 MSR_IA32_VMX_VMCS_ENUM,
1194 MSR_IA32_VMX_PROCBASED_CTLS2,
1195 MSR_IA32_VMX_EPT_VPID_CAP,
1196 MSR_IA32_VMX_VMFUNC,
1200 MSR_IA32_ARCH_CAPABILITIES,
1203 static unsigned int num_msr_based_features;
1205 u64 kvm_get_arch_capabilities(void)
1209 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1212 * If we're doing cache flushes (either "always" or "cond")
1213 * we will do one whenever the guest does a vmlaunch/vmresume.
1214 * If an outer hypervisor is doing the cache flush for us
1215 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1216 * capability to the guest too, and if EPT is disabled we're not
1217 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1218 * require a nested hypervisor to do a flush of its own.
1220 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1221 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1225 EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1227 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1229 switch (msr->index) {
1230 case MSR_IA32_ARCH_CAPABILITIES:
1231 msr->data = kvm_get_arch_capabilities();
1233 case MSR_IA32_UCODE_REV:
1234 rdmsrl_safe(msr->index, &msr->data);
1237 if (kvm_x86_ops->get_msr_feature(msr))
1243 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1245 struct kvm_msr_entry msr;
1249 r = kvm_get_msr_feature(&msr);
1258 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1260 if (efer & efer_reserved_bits)
1263 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1266 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1271 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1273 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1275 u64 old_efer = vcpu->arch.efer;
1277 if (!kvm_valid_efer(vcpu, efer))
1281 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1285 efer |= vcpu->arch.efer & EFER_LMA;
1287 kvm_x86_ops->set_efer(vcpu, efer);
1289 /* Update reserved bits */
1290 if ((efer ^ old_efer) & EFER_NX)
1291 kvm_mmu_reset_context(vcpu);
1296 void kvm_enable_efer_bits(u64 mask)
1298 efer_reserved_bits &= ~mask;
1300 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1303 * Writes msr value into into the appropriate "register".
1304 * Returns 0 on success, non-0 otherwise.
1305 * Assumes vcpu_load() was already called.
1307 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1309 switch (msr->index) {
1312 case MSR_KERNEL_GS_BASE:
1315 if (is_noncanonical_address(msr->data, vcpu))
1318 case MSR_IA32_SYSENTER_EIP:
1319 case MSR_IA32_SYSENTER_ESP:
1321 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1322 * non-canonical address is written on Intel but not on
1323 * AMD (which ignores the top 32-bits, because it does
1324 * not implement 64-bit SYSENTER).
1326 * 64-bit code should hence be able to write a non-canonical
1327 * value on AMD. Making the address canonical ensures that
1328 * vmentry does not fail on Intel after writing a non-canonical
1329 * value, and that something deterministic happens if the guest
1330 * invokes 64-bit SYSENTER.
1332 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
1334 return kvm_x86_ops->set_msr(vcpu, msr);
1336 EXPORT_SYMBOL_GPL(kvm_set_msr);
1339 * Adapt set_msr() to msr_io()'s calling convention
1341 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1343 struct msr_data msr;
1347 msr.host_initiated = true;
1348 r = kvm_get_msr(vcpu, &msr);
1356 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1358 struct msr_data msr;
1362 msr.host_initiated = true;
1363 return kvm_set_msr(vcpu, &msr);
1366 #ifdef CONFIG_X86_64
1367 struct pvclock_gtod_data {
1370 struct { /* extract of a clocksource struct */
1383 static struct pvclock_gtod_data pvclock_gtod_data;
1385 static void update_pvclock_gtod(struct timekeeper *tk)
1387 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1390 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1392 write_seqcount_begin(&vdata->seq);
1394 /* copy pvclock gtod data */
1395 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1396 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1397 vdata->clock.mask = tk->tkr_mono.mask;
1398 vdata->clock.mult = tk->tkr_mono.mult;
1399 vdata->clock.shift = tk->tkr_mono.shift;
1401 vdata->boot_ns = boot_ns;
1402 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1404 vdata->wall_time_sec = tk->xtime_sec;
1406 write_seqcount_end(&vdata->seq);
1410 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1413 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1414 * vcpu_enter_guest. This function is only called from
1415 * the physical CPU that is running vcpu.
1417 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1420 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1424 struct pvclock_wall_clock wc;
1425 struct timespec64 boot;
1430 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1435 ++version; /* first time write, random junk */
1439 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1443 * The guest calculates current wall clock time by adding
1444 * system time (updated by kvm_guest_time_update below) to the
1445 * wall clock specified here. guest system time equals host
1446 * system time for us, thus we must fill in host boot time here.
1448 getboottime64(&boot);
1450 if (kvm->arch.kvmclock_offset) {
1451 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1452 boot = timespec64_sub(boot, ts);
1454 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1455 wc.nsec = boot.tv_nsec;
1456 wc.version = version;
1458 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1461 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1464 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1466 do_shl32_div32(dividend, divisor);
1470 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1471 s8 *pshift, u32 *pmultiplier)
1479 scaled64 = scaled_hz;
1480 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1485 tps32 = (uint32_t)tps64;
1486 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1487 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1495 *pmultiplier = div_frac(scaled64, tps32);
1497 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1498 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1501 #ifdef CONFIG_X86_64
1502 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1505 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1506 static unsigned long max_tsc_khz;
1508 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1510 u64 v = (u64)khz * (1000000 + ppm);
1515 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1519 /* Guest TSC same frequency as host TSC? */
1521 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1525 /* TSC scaling supported? */
1526 if (!kvm_has_tsc_control) {
1527 if (user_tsc_khz > tsc_khz) {
1528 vcpu->arch.tsc_catchup = 1;
1529 vcpu->arch.tsc_always_catchup = 1;
1532 WARN(1, "user requested TSC rate below hardware speed\n");
1537 /* TSC scaling required - calculate ratio */
1538 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1539 user_tsc_khz, tsc_khz);
1541 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1542 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1547 vcpu->arch.tsc_scaling_ratio = ratio;
1551 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1553 u32 thresh_lo, thresh_hi;
1554 int use_scaling = 0;
1556 /* tsc_khz can be zero if TSC calibration fails */
1557 if (user_tsc_khz == 0) {
1558 /* set tsc_scaling_ratio to a safe value */
1559 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1563 /* Compute a scale to convert nanoseconds in TSC cycles */
1564 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1565 &vcpu->arch.virtual_tsc_shift,
1566 &vcpu->arch.virtual_tsc_mult);
1567 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1570 * Compute the variation in TSC rate which is acceptable
1571 * within the range of tolerance and decide if the
1572 * rate being applied is within that bounds of the hardware
1573 * rate. If so, no scaling or compensation need be done.
1575 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1576 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1577 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1578 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1581 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1584 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1586 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1587 vcpu->arch.virtual_tsc_mult,
1588 vcpu->arch.virtual_tsc_shift);
1589 tsc += vcpu->arch.this_tsc_write;
1593 static inline int gtod_is_based_on_tsc(int mode)
1595 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1598 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1600 #ifdef CONFIG_X86_64
1602 struct kvm_arch *ka = &vcpu->kvm->arch;
1603 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1605 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1606 atomic_read(&vcpu->kvm->online_vcpus));
1609 * Once the masterclock is enabled, always perform request in
1610 * order to update it.
1612 * In order to enable masterclock, the host clocksource must be TSC
1613 * and the vcpus need to have matched TSCs. When that happens,
1614 * perform request to enable masterclock.
1616 if (ka->use_master_clock ||
1617 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1618 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1620 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1621 atomic_read(&vcpu->kvm->online_vcpus),
1622 ka->use_master_clock, gtod->clock.vclock_mode);
1626 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1628 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1629 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1633 * Multiply tsc by a fixed point number represented by ratio.
1635 * The most significant 64-N bits (mult) of ratio represent the
1636 * integral part of the fixed point number; the remaining N bits
1637 * (frac) represent the fractional part, ie. ratio represents a fixed
1638 * point number (mult + frac * 2^(-N)).
1640 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1642 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1644 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1647 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1650 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1652 if (ratio != kvm_default_tsc_scaling_ratio)
1653 _tsc = __scale_tsc(ratio, tsc);
1657 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1659 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1663 tsc = kvm_scale_tsc(vcpu, rdtsc());
1665 return target_tsc - tsc;
1668 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1670 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1672 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1674 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1676 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1678 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1681 static inline bool kvm_check_tsc_unstable(void)
1683 #ifdef CONFIG_X86_64
1685 * TSC is marked unstable when we're running on Hyper-V,
1686 * 'TSC page' clocksource is good.
1688 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1691 return check_tsc_unstable();
1694 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1696 struct kvm *kvm = vcpu->kvm;
1697 u64 offset, ns, elapsed;
1698 unsigned long flags;
1700 bool already_matched;
1701 u64 data = msr->data;
1702 bool synchronizing = false;
1704 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1705 offset = kvm_compute_tsc_offset(vcpu, data);
1706 ns = ktime_get_boot_ns();
1707 elapsed = ns - kvm->arch.last_tsc_nsec;
1709 if (vcpu->arch.virtual_tsc_khz) {
1710 if (data == 0 && msr->host_initiated) {
1712 * detection of vcpu initialization -- need to sync
1713 * with other vCPUs. This particularly helps to keep
1714 * kvm_clock stable after CPU hotplug
1716 synchronizing = true;
1718 u64 tsc_exp = kvm->arch.last_tsc_write +
1719 nsec_to_cycles(vcpu, elapsed);
1720 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1722 * Special case: TSC write with a small delta (1 second)
1723 * of virtual cycle time against real time is
1724 * interpreted as an attempt to synchronize the CPU.
1726 synchronizing = data < tsc_exp + tsc_hz &&
1727 data + tsc_hz > tsc_exp;
1732 * For a reliable TSC, we can match TSC offsets, and for an unstable
1733 * TSC, we add elapsed time in this computation. We could let the
1734 * compensation code attempt to catch up if we fall behind, but
1735 * it's better to try to match offsets from the beginning.
1737 if (synchronizing &&
1738 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1739 if (!kvm_check_tsc_unstable()) {
1740 offset = kvm->arch.cur_tsc_offset;
1741 pr_debug("kvm: matched tsc offset for %llu\n", data);
1743 u64 delta = nsec_to_cycles(vcpu, elapsed);
1745 offset = kvm_compute_tsc_offset(vcpu, data);
1746 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1749 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1752 * We split periods of matched TSC writes into generations.
1753 * For each generation, we track the original measured
1754 * nanosecond time, offset, and write, so if TSCs are in
1755 * sync, we can match exact offset, and if not, we can match
1756 * exact software computation in compute_guest_tsc()
1758 * These values are tracked in kvm->arch.cur_xxx variables.
1760 kvm->arch.cur_tsc_generation++;
1761 kvm->arch.cur_tsc_nsec = ns;
1762 kvm->arch.cur_tsc_write = data;
1763 kvm->arch.cur_tsc_offset = offset;
1765 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1766 kvm->arch.cur_tsc_generation, data);
1770 * We also track th most recent recorded KHZ, write and time to
1771 * allow the matching interval to be extended at each write.
1773 kvm->arch.last_tsc_nsec = ns;
1774 kvm->arch.last_tsc_write = data;
1775 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1777 vcpu->arch.last_guest_tsc = data;
1779 /* Keep track of which generation this VCPU has synchronized to */
1780 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1781 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1782 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1784 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1785 update_ia32_tsc_adjust_msr(vcpu, offset);
1787 kvm_vcpu_write_tsc_offset(vcpu, offset);
1788 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1790 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1792 kvm->arch.nr_vcpus_matched_tsc = 0;
1793 } else if (!already_matched) {
1794 kvm->arch.nr_vcpus_matched_tsc++;
1797 kvm_track_tsc_matching(vcpu);
1798 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1801 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1803 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1806 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1807 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
1810 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1812 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1813 WARN_ON(adjustment < 0);
1814 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1815 adjust_tsc_offset_guest(vcpu, adjustment);
1818 #ifdef CONFIG_X86_64
1820 static u64 read_tsc(void)
1822 u64 ret = (u64)rdtsc_ordered();
1823 u64 last = pvclock_gtod_data.clock.cycle_last;
1825 if (likely(ret >= last))
1829 * GCC likes to generate cmov here, but this branch is extremely
1830 * predictable (it's just a function of time and the likely is
1831 * very likely) and there's a data dependence, so force GCC
1832 * to generate a branch instead. I don't barrier() because
1833 * we don't actually need a barrier, and if this function
1834 * ever gets inlined it will generate worse code.
1840 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
1843 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1846 switch (gtod->clock.vclock_mode) {
1847 case VCLOCK_HVCLOCK:
1848 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1850 if (tsc_pg_val != U64_MAX) {
1851 /* TSC page valid */
1852 *mode = VCLOCK_HVCLOCK;
1853 v = (tsc_pg_val - gtod->clock.cycle_last) &
1856 /* TSC page invalid */
1857 *mode = VCLOCK_NONE;
1862 *tsc_timestamp = read_tsc();
1863 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1867 *mode = VCLOCK_NONE;
1870 if (*mode == VCLOCK_NONE)
1871 *tsc_timestamp = v = 0;
1873 return v * gtod->clock.mult;
1876 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
1878 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1884 seq = read_seqcount_begin(>od->seq);
1885 ns = gtod->nsec_base;
1886 ns += vgettsc(tsc_timestamp, &mode);
1887 ns >>= gtod->clock.shift;
1888 ns += gtod->boot_ns;
1889 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1895 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
1897 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1903 seq = read_seqcount_begin(>od->seq);
1904 ts->tv_sec = gtod->wall_time_sec;
1905 ns = gtod->nsec_base;
1906 ns += vgettsc(tsc_timestamp, &mode);
1907 ns >>= gtod->clock.shift;
1908 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1910 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1916 /* returns true if host is using TSC based clocksource */
1917 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
1919 /* checked again under seqlock below */
1920 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1923 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1927 /* returns true if host is using TSC based clocksource */
1928 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
1931 /* checked again under seqlock below */
1932 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1935 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
1941 * Assuming a stable TSC across physical CPUS, and a stable TSC
1942 * across virtual CPUs, the following condition is possible.
1943 * Each numbered line represents an event visible to both
1944 * CPUs at the next numbered event.
1946 * "timespecX" represents host monotonic time. "tscX" represents
1949 * VCPU0 on CPU0 | VCPU1 on CPU1
1951 * 1. read timespec0,tsc0
1952 * 2. | timespec1 = timespec0 + N
1954 * 3. transition to guest | transition to guest
1955 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1956 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1957 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1959 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1962 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1964 * - 0 < N - M => M < N
1966 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1967 * always the case (the difference between two distinct xtime instances
1968 * might be smaller then the difference between corresponding TSC reads,
1969 * when updating guest vcpus pvclock areas).
1971 * To avoid that problem, do not allow visibility of distinct
1972 * system_timestamp/tsc_timestamp values simultaneously: use a master
1973 * copy of host monotonic time values. Update that master copy
1976 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1980 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1982 #ifdef CONFIG_X86_64
1983 struct kvm_arch *ka = &kvm->arch;
1985 bool host_tsc_clocksource, vcpus_matched;
1987 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1988 atomic_read(&kvm->online_vcpus));
1991 * If the host uses TSC clock, then passthrough TSC as stable
1994 host_tsc_clocksource = kvm_get_time_and_clockread(
1995 &ka->master_kernel_ns,
1996 &ka->master_cycle_now);
1998 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1999 && !ka->backwards_tsc_observed
2000 && !ka->boot_vcpu_runs_old_kvmclock;
2002 if (ka->use_master_clock)
2003 atomic_set(&kvm_guest_has_master_clock, 1);
2005 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2006 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2011 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2013 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2016 static void kvm_gen_update_masterclock(struct kvm *kvm)
2018 #ifdef CONFIG_X86_64
2020 struct kvm_vcpu *vcpu;
2021 struct kvm_arch *ka = &kvm->arch;
2023 spin_lock(&ka->pvclock_gtod_sync_lock);
2024 kvm_make_mclock_inprogress_request(kvm);
2025 /* no guest entries from this point */
2026 pvclock_update_vm_gtod_copy(kvm);
2028 kvm_for_each_vcpu(i, vcpu, kvm)
2029 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2031 /* guest entries allowed */
2032 kvm_for_each_vcpu(i, vcpu, kvm)
2033 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2035 spin_unlock(&ka->pvclock_gtod_sync_lock);
2039 u64 get_kvmclock_ns(struct kvm *kvm)
2041 struct kvm_arch *ka = &kvm->arch;
2042 struct pvclock_vcpu_time_info hv_clock;
2045 spin_lock(&ka->pvclock_gtod_sync_lock);
2046 if (!ka->use_master_clock) {
2047 spin_unlock(&ka->pvclock_gtod_sync_lock);
2048 return ktime_get_boot_ns() + ka->kvmclock_offset;
2051 hv_clock.tsc_timestamp = ka->master_cycle_now;
2052 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2053 spin_unlock(&ka->pvclock_gtod_sync_lock);
2055 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2058 if (__this_cpu_read(cpu_tsc_khz)) {
2059 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2060 &hv_clock.tsc_shift,
2061 &hv_clock.tsc_to_system_mul);
2062 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2064 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
2071 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2073 struct kvm_vcpu_arch *vcpu = &v->arch;
2074 struct pvclock_vcpu_time_info guest_hv_clock;
2076 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2077 &guest_hv_clock, sizeof(guest_hv_clock))))
2080 /* This VCPU is paused, but it's legal for a guest to read another
2081 * VCPU's kvmclock, so we really have to follow the specification where
2082 * it says that version is odd if data is being modified, and even after
2085 * Version field updates must be kept separate. This is because
2086 * kvm_write_guest_cached might use a "rep movs" instruction, and
2087 * writes within a string instruction are weakly ordered. So there
2088 * are three writes overall.
2090 * As a small optimization, only write the version field in the first
2091 * and third write. The vcpu->pv_time cache is still valid, because the
2092 * version field is the first in the struct.
2094 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2096 if (guest_hv_clock.version & 1)
2097 ++guest_hv_clock.version; /* first time write, random junk */
2099 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2100 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2102 sizeof(vcpu->hv_clock.version));
2106 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2107 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2109 if (vcpu->pvclock_set_guest_stopped_request) {
2110 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2111 vcpu->pvclock_set_guest_stopped_request = false;
2114 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2116 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2118 sizeof(vcpu->hv_clock));
2122 vcpu->hv_clock.version++;
2123 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2125 sizeof(vcpu->hv_clock.version));
2128 static int kvm_guest_time_update(struct kvm_vcpu *v)
2130 unsigned long flags, tgt_tsc_khz;
2131 struct kvm_vcpu_arch *vcpu = &v->arch;
2132 struct kvm_arch *ka = &v->kvm->arch;
2134 u64 tsc_timestamp, host_tsc;
2136 bool use_master_clock;
2142 * If the host uses TSC clock, then passthrough TSC as stable
2145 spin_lock(&ka->pvclock_gtod_sync_lock);
2146 use_master_clock = ka->use_master_clock;
2147 if (use_master_clock) {
2148 host_tsc = ka->master_cycle_now;
2149 kernel_ns = ka->master_kernel_ns;
2151 spin_unlock(&ka->pvclock_gtod_sync_lock);
2153 /* Keep irq disabled to prevent changes to the clock */
2154 local_irq_save(flags);
2155 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2156 if (unlikely(tgt_tsc_khz == 0)) {
2157 local_irq_restore(flags);
2158 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2161 if (!use_master_clock) {
2163 kernel_ns = ktime_get_boot_ns();
2166 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2169 * We may have to catch up the TSC to match elapsed wall clock
2170 * time for two reasons, even if kvmclock is used.
2171 * 1) CPU could have been running below the maximum TSC rate
2172 * 2) Broken TSC compensation resets the base at each VCPU
2173 * entry to avoid unknown leaps of TSC even when running
2174 * again on the same CPU. This may cause apparent elapsed
2175 * time to disappear, and the guest to stand still or run
2178 if (vcpu->tsc_catchup) {
2179 u64 tsc = compute_guest_tsc(v, kernel_ns);
2180 if (tsc > tsc_timestamp) {
2181 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2182 tsc_timestamp = tsc;
2186 local_irq_restore(flags);
2188 /* With all the info we got, fill in the values */
2190 if (kvm_has_tsc_control)
2191 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2193 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2194 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2195 &vcpu->hv_clock.tsc_shift,
2196 &vcpu->hv_clock.tsc_to_system_mul);
2197 vcpu->hw_tsc_khz = tgt_tsc_khz;
2200 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2201 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2202 vcpu->last_guest_tsc = tsc_timestamp;
2204 /* If the host uses TSC clocksource, then it is stable */
2206 if (use_master_clock)
2207 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2209 vcpu->hv_clock.flags = pvclock_flags;
2211 if (vcpu->pv_time_enabled)
2212 kvm_setup_pvclock_page(v);
2213 if (v == kvm_get_vcpu(v->kvm, 0))
2214 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2219 * kvmclock updates which are isolated to a given vcpu, such as
2220 * vcpu->cpu migration, should not allow system_timestamp from
2221 * the rest of the vcpus to remain static. Otherwise ntp frequency
2222 * correction applies to one vcpu's system_timestamp but not
2225 * So in those cases, request a kvmclock update for all vcpus.
2226 * We need to rate-limit these requests though, as they can
2227 * considerably slow guests that have a large number of vcpus.
2228 * The time for a remote vcpu to update its kvmclock is bound
2229 * by the delay we use to rate-limit the updates.
2232 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2234 static void kvmclock_update_fn(struct work_struct *work)
2237 struct delayed_work *dwork = to_delayed_work(work);
2238 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2239 kvmclock_update_work);
2240 struct kvm *kvm = container_of(ka, struct kvm, arch);
2241 struct kvm_vcpu *vcpu;
2243 kvm_for_each_vcpu(i, vcpu, kvm) {
2244 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2245 kvm_vcpu_kick(vcpu);
2249 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2251 struct kvm *kvm = v->kvm;
2253 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2254 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2255 KVMCLOCK_UPDATE_DELAY);
2258 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2260 static void kvmclock_sync_fn(struct work_struct *work)
2262 struct delayed_work *dwork = to_delayed_work(work);
2263 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2264 kvmclock_sync_work);
2265 struct kvm *kvm = container_of(ka, struct kvm, arch);
2267 if (!kvmclock_periodic_sync)
2270 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2271 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2272 KVMCLOCK_SYNC_PERIOD);
2275 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2277 u64 mcg_cap = vcpu->arch.mcg_cap;
2278 unsigned bank_num = mcg_cap & 0xff;
2279 u32 msr = msr_info->index;
2280 u64 data = msr_info->data;
2283 case MSR_IA32_MCG_STATUS:
2284 vcpu->arch.mcg_status = data;
2286 case MSR_IA32_MCG_CTL:
2287 if (!(mcg_cap & MCG_CTL_P) &&
2288 (data || !msr_info->host_initiated))
2290 if (data != 0 && data != ~(u64)0)
2292 vcpu->arch.mcg_ctl = data;
2295 if (msr >= MSR_IA32_MC0_CTL &&
2296 msr < MSR_IA32_MCx_CTL(bank_num)) {
2297 u32 offset = msr - MSR_IA32_MC0_CTL;
2298 /* only 0 or all 1s can be written to IA32_MCi_CTL
2299 * some Linux kernels though clear bit 10 in bank 4 to
2300 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2301 * this to avoid an uncatched #GP in the guest
2303 if ((offset & 0x3) == 0 &&
2304 data != 0 && (data | (1 << 10)) != ~(u64)0)
2306 if (!msr_info->host_initiated &&
2307 (offset & 0x3) == 1 && data != 0)
2309 vcpu->arch.mce_banks[offset] = data;
2317 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2319 struct kvm *kvm = vcpu->kvm;
2320 int lm = is_long_mode(vcpu);
2321 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2322 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2323 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2324 : kvm->arch.xen_hvm_config.blob_size_32;
2325 u32 page_num = data & ~PAGE_MASK;
2326 u64 page_addr = data & PAGE_MASK;
2331 if (page_num >= blob_size)
2334 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2339 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2348 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2350 gpa_t gpa = data & ~0x3f;
2352 /* Bits 3:5 are reserved, Should be zero */
2356 vcpu->arch.apf.msr_val = data;
2358 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2359 kvm_clear_async_pf_completion_queue(vcpu);
2360 kvm_async_pf_hash_reset(vcpu);
2364 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2368 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2369 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2370 kvm_async_pf_wakeup_all(vcpu);
2374 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2376 vcpu->arch.pv_time_enabled = false;
2379 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2381 ++vcpu->stat.tlb_flush;
2382 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2385 static void record_steal_time(struct kvm_vcpu *vcpu)
2387 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2390 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2391 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2395 * Doing a TLB flush here, on the guest's behalf, can avoid
2398 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2399 kvm_vcpu_flush_tlb(vcpu, false);
2401 if (vcpu->arch.st.steal.version & 1)
2402 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2404 vcpu->arch.st.steal.version += 1;
2406 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2407 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2411 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2412 vcpu->arch.st.last_steal;
2413 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2415 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2416 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2420 vcpu->arch.st.steal.version += 1;
2422 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2423 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2426 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2429 u32 msr = msr_info->index;
2430 u64 data = msr_info->data;
2433 case MSR_AMD64_NB_CFG:
2434 case MSR_IA32_UCODE_WRITE:
2435 case MSR_VM_HSAVE_PA:
2436 case MSR_AMD64_PATCH_LOADER:
2437 case MSR_AMD64_BU_CFG2:
2438 case MSR_AMD64_DC_CFG:
2439 case MSR_F15H_EX_CFG:
2442 case MSR_IA32_UCODE_REV:
2443 if (msr_info->host_initiated)
2444 vcpu->arch.microcode_version = data;
2447 return set_efer(vcpu, data);
2449 data &= ~(u64)0x40; /* ignore flush filter disable */
2450 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2451 data &= ~(u64)0x8; /* ignore TLB cache disable */
2452 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2454 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2459 case MSR_FAM10H_MMIO_CONF_BASE:
2461 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2466 case MSR_IA32_DEBUGCTLMSR:
2468 /* We support the non-activated case already */
2470 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2471 /* Values other than LBR and BTF are vendor-specific,
2472 thus reserved and should throw a #GP */
2475 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2478 case 0x200 ... 0x2ff:
2479 return kvm_mtrr_set_msr(vcpu, msr, data);
2480 case MSR_IA32_APICBASE:
2481 return kvm_set_apic_base(vcpu, msr_info);
2482 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2483 return kvm_x2apic_msr_write(vcpu, msr, data);
2484 case MSR_IA32_TSCDEADLINE:
2485 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2487 case MSR_IA32_TSC_ADJUST:
2488 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2489 if (!msr_info->host_initiated) {
2490 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2491 adjust_tsc_offset_guest(vcpu, adj);
2493 vcpu->arch.ia32_tsc_adjust_msr = data;
2496 case MSR_IA32_MISC_ENABLE:
2497 vcpu->arch.ia32_misc_enable_msr = data;
2499 case MSR_IA32_SMBASE:
2500 if (!msr_info->host_initiated)
2502 vcpu->arch.smbase = data;
2505 kvm_write_tsc(vcpu, msr_info);
2508 if (!msr_info->host_initiated)
2510 vcpu->arch.smi_count = data;
2512 case MSR_KVM_WALL_CLOCK_NEW:
2513 case MSR_KVM_WALL_CLOCK:
2514 vcpu->kvm->arch.wall_clock = data;
2515 kvm_write_wall_clock(vcpu->kvm, data);
2517 case MSR_KVM_SYSTEM_TIME_NEW:
2518 case MSR_KVM_SYSTEM_TIME: {
2519 struct kvm_arch *ka = &vcpu->kvm->arch;
2521 kvmclock_reset(vcpu);
2523 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2524 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2526 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2527 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2529 ka->boot_vcpu_runs_old_kvmclock = tmp;
2532 vcpu->arch.time = data;
2533 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2535 /* we verify if the enable bit is set... */
2539 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2540 &vcpu->arch.pv_time, data & ~1ULL,
2541 sizeof(struct pvclock_vcpu_time_info)))
2542 vcpu->arch.pv_time_enabled = false;
2544 vcpu->arch.pv_time_enabled = true;
2548 case MSR_KVM_ASYNC_PF_EN:
2549 if (kvm_pv_enable_async_pf(vcpu, data))
2552 case MSR_KVM_STEAL_TIME:
2554 if (unlikely(!sched_info_on()))
2557 if (data & KVM_STEAL_RESERVED_MASK)
2560 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2561 data & KVM_STEAL_VALID_BITS,
2562 sizeof(struct kvm_steal_time)))
2565 vcpu->arch.st.msr_val = data;
2567 if (!(data & KVM_MSR_ENABLED))
2570 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2573 case MSR_KVM_PV_EOI_EN:
2574 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2578 case MSR_IA32_MCG_CTL:
2579 case MSR_IA32_MCG_STATUS:
2580 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2581 return set_msr_mce(vcpu, msr_info);
2583 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2584 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2585 pr = true; /* fall through */
2586 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2587 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2588 if (kvm_pmu_is_valid_msr(vcpu, msr))
2589 return kvm_pmu_set_msr(vcpu, msr_info);
2591 if (pr || data != 0)
2592 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2593 "0x%x data 0x%llx\n", msr, data);
2595 case MSR_K7_CLK_CTL:
2597 * Ignore all writes to this no longer documented MSR.
2598 * Writes are only relevant for old K7 processors,
2599 * all pre-dating SVM, but a recommended workaround from
2600 * AMD for these chips. It is possible to specify the
2601 * affected processor models on the command line, hence
2602 * the need to ignore the workaround.
2605 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2606 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2607 case HV_X64_MSR_CRASH_CTL:
2608 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2609 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2610 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2611 case HV_X64_MSR_TSC_EMULATION_STATUS:
2612 return kvm_hv_set_msr_common(vcpu, msr, data,
2613 msr_info->host_initiated);
2614 case MSR_IA32_BBL_CR_CTL3:
2615 /* Drop writes to this legacy MSR -- see rdmsr
2616 * counterpart for further detail.
2618 if (report_ignored_msrs)
2619 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2622 case MSR_AMD64_OSVW_ID_LENGTH:
2623 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2625 vcpu->arch.osvw.length = data;
2627 case MSR_AMD64_OSVW_STATUS:
2628 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2630 vcpu->arch.osvw.status = data;
2632 case MSR_PLATFORM_INFO:
2633 if (!msr_info->host_initiated ||
2634 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2635 cpuid_fault_enabled(vcpu)))
2637 vcpu->arch.msr_platform_info = data;
2639 case MSR_MISC_FEATURES_ENABLES:
2640 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2641 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2642 !supports_cpuid_fault(vcpu)))
2644 vcpu->arch.msr_misc_features_enables = data;
2647 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2648 return xen_hvm_config(vcpu, data);
2649 if (kvm_pmu_is_valid_msr(vcpu, msr))
2650 return kvm_pmu_set_msr(vcpu, msr_info);
2652 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2656 if (report_ignored_msrs)
2658 "ignored wrmsr: 0x%x data 0x%llx\n",
2665 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2669 * Reads an msr value (of 'msr_index') into 'pdata'.
2670 * Returns 0 on success, non-0 otherwise.
2671 * Assumes vcpu_load() was already called.
2673 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2675 return kvm_x86_ops->get_msr(vcpu, msr);
2677 EXPORT_SYMBOL_GPL(kvm_get_msr);
2679 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2682 u64 mcg_cap = vcpu->arch.mcg_cap;
2683 unsigned bank_num = mcg_cap & 0xff;
2686 case MSR_IA32_P5_MC_ADDR:
2687 case MSR_IA32_P5_MC_TYPE:
2690 case MSR_IA32_MCG_CAP:
2691 data = vcpu->arch.mcg_cap;
2693 case MSR_IA32_MCG_CTL:
2694 if (!(mcg_cap & MCG_CTL_P) && !host)
2696 data = vcpu->arch.mcg_ctl;
2698 case MSR_IA32_MCG_STATUS:
2699 data = vcpu->arch.mcg_status;
2702 if (msr >= MSR_IA32_MC0_CTL &&
2703 msr < MSR_IA32_MCx_CTL(bank_num)) {
2704 u32 offset = msr - MSR_IA32_MC0_CTL;
2705 data = vcpu->arch.mce_banks[offset];
2714 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2716 switch (msr_info->index) {
2717 case MSR_IA32_PLATFORM_ID:
2718 case MSR_IA32_EBL_CR_POWERON:
2719 case MSR_IA32_DEBUGCTLMSR:
2720 case MSR_IA32_LASTBRANCHFROMIP:
2721 case MSR_IA32_LASTBRANCHTOIP:
2722 case MSR_IA32_LASTINTFROMIP:
2723 case MSR_IA32_LASTINTTOIP:
2725 case MSR_K8_TSEG_ADDR:
2726 case MSR_K8_TSEG_MASK:
2728 case MSR_VM_HSAVE_PA:
2729 case MSR_K8_INT_PENDING_MSG:
2730 case MSR_AMD64_NB_CFG:
2731 case MSR_FAM10H_MMIO_CONF_BASE:
2732 case MSR_AMD64_BU_CFG2:
2733 case MSR_IA32_PERF_CTL:
2734 case MSR_AMD64_DC_CFG:
2735 case MSR_F15H_EX_CFG:
2738 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
2739 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2740 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2741 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2742 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2743 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2744 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2747 case MSR_IA32_UCODE_REV:
2748 msr_info->data = vcpu->arch.microcode_version;
2751 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2754 case 0x200 ... 0x2ff:
2755 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2756 case 0xcd: /* fsb frequency */
2760 * MSR_EBC_FREQUENCY_ID
2761 * Conservative value valid for even the basic CPU models.
2762 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2763 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2764 * and 266MHz for model 3, or 4. Set Core Clock
2765 * Frequency to System Bus Frequency Ratio to 1 (bits
2766 * 31:24) even though these are only valid for CPU
2767 * models > 2, however guests may end up dividing or
2768 * multiplying by zero otherwise.
2770 case MSR_EBC_FREQUENCY_ID:
2771 msr_info->data = 1 << 24;
2773 case MSR_IA32_APICBASE:
2774 msr_info->data = kvm_get_apic_base(vcpu);
2776 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2777 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2779 case MSR_IA32_TSCDEADLINE:
2780 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2782 case MSR_IA32_TSC_ADJUST:
2783 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2785 case MSR_IA32_MISC_ENABLE:
2786 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2788 case MSR_IA32_SMBASE:
2789 if (!msr_info->host_initiated)
2791 msr_info->data = vcpu->arch.smbase;
2794 msr_info->data = vcpu->arch.smi_count;
2796 case MSR_IA32_PERF_STATUS:
2797 /* TSC increment by tick */
2798 msr_info->data = 1000ULL;
2799 /* CPU multiplier */
2800 msr_info->data |= (((uint64_t)4ULL) << 40);
2803 msr_info->data = vcpu->arch.efer;
2805 case MSR_KVM_WALL_CLOCK:
2806 case MSR_KVM_WALL_CLOCK_NEW:
2807 msr_info->data = vcpu->kvm->arch.wall_clock;
2809 case MSR_KVM_SYSTEM_TIME:
2810 case MSR_KVM_SYSTEM_TIME_NEW:
2811 msr_info->data = vcpu->arch.time;
2813 case MSR_KVM_ASYNC_PF_EN:
2814 msr_info->data = vcpu->arch.apf.msr_val;
2816 case MSR_KVM_STEAL_TIME:
2817 msr_info->data = vcpu->arch.st.msr_val;
2819 case MSR_KVM_PV_EOI_EN:
2820 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2822 case MSR_IA32_P5_MC_ADDR:
2823 case MSR_IA32_P5_MC_TYPE:
2824 case MSR_IA32_MCG_CAP:
2825 case MSR_IA32_MCG_CTL:
2826 case MSR_IA32_MCG_STATUS:
2827 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2828 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2829 msr_info->host_initiated);
2830 case MSR_K7_CLK_CTL:
2832 * Provide expected ramp-up count for K7. All other
2833 * are set to zero, indicating minimum divisors for
2836 * This prevents guest kernels on AMD host with CPU
2837 * type 6, model 8 and higher from exploding due to
2838 * the rdmsr failing.
2840 msr_info->data = 0x20000000;
2842 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2843 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2844 case HV_X64_MSR_CRASH_CTL:
2845 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2846 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2847 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2848 case HV_X64_MSR_TSC_EMULATION_STATUS:
2849 return kvm_hv_get_msr_common(vcpu,
2850 msr_info->index, &msr_info->data,
2851 msr_info->host_initiated);
2853 case MSR_IA32_BBL_CR_CTL3:
2854 /* This legacy MSR exists but isn't fully documented in current
2855 * silicon. It is however accessed by winxp in very narrow
2856 * scenarios where it sets bit #19, itself documented as
2857 * a "reserved" bit. Best effort attempt to source coherent
2858 * read data here should the balance of the register be
2859 * interpreted by the guest:
2861 * L2 cache control register 3: 64GB range, 256KB size,
2862 * enabled, latency 0x1, configured
2864 msr_info->data = 0xbe702111;
2866 case MSR_AMD64_OSVW_ID_LENGTH:
2867 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2869 msr_info->data = vcpu->arch.osvw.length;
2871 case MSR_AMD64_OSVW_STATUS:
2872 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2874 msr_info->data = vcpu->arch.osvw.status;
2876 case MSR_PLATFORM_INFO:
2877 if (!msr_info->host_initiated &&
2878 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2880 msr_info->data = vcpu->arch.msr_platform_info;
2882 case MSR_MISC_FEATURES_ENABLES:
2883 msr_info->data = vcpu->arch.msr_misc_features_enables;
2886 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2887 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2889 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2893 if (report_ignored_msrs)
2894 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2902 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2905 * Read or write a bunch of msrs. All parameters are kernel addresses.
2907 * @return number of msrs set successfully.
2909 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2910 struct kvm_msr_entry *entries,
2911 int (*do_msr)(struct kvm_vcpu *vcpu,
2912 unsigned index, u64 *data))
2916 for (i = 0; i < msrs->nmsrs; ++i)
2917 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2924 * Read or write a bunch of msrs. Parameters are user addresses.
2926 * @return number of msrs set successfully.
2928 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2929 int (*do_msr)(struct kvm_vcpu *vcpu,
2930 unsigned index, u64 *data),
2933 struct kvm_msrs msrs;
2934 struct kvm_msr_entry *entries;
2939 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
2943 if (msrs.nmsrs >= MAX_IO_MSRS)
2946 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2947 entries = memdup_user(user_msrs->entries, size);
2948 if (IS_ERR(entries)) {
2949 r = PTR_ERR(entries);
2953 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2958 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2969 static inline bool kvm_can_mwait_in_guest(void)
2971 return boot_cpu_has(X86_FEATURE_MWAIT) &&
2972 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2973 boot_cpu_has(X86_FEATURE_ARAT);
2976 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2981 case KVM_CAP_IRQCHIP:
2983 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2984 case KVM_CAP_SET_TSS_ADDR:
2985 case KVM_CAP_EXT_CPUID:
2986 case KVM_CAP_EXT_EMUL_CPUID:
2987 case KVM_CAP_CLOCKSOURCE:
2989 case KVM_CAP_NOP_IO_DELAY:
2990 case KVM_CAP_MP_STATE:
2991 case KVM_CAP_SYNC_MMU:
2992 case KVM_CAP_USER_NMI:
2993 case KVM_CAP_REINJECT_CONTROL:
2994 case KVM_CAP_IRQ_INJECT_STATUS:
2995 case KVM_CAP_IOEVENTFD:
2996 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2998 case KVM_CAP_PIT_STATE2:
2999 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3000 case KVM_CAP_XEN_HVM:
3001 case KVM_CAP_VCPU_EVENTS:
3002 case KVM_CAP_HYPERV:
3003 case KVM_CAP_HYPERV_VAPIC:
3004 case KVM_CAP_HYPERV_SPIN:
3005 case KVM_CAP_HYPERV_SYNIC:
3006 case KVM_CAP_HYPERV_SYNIC2:
3007 case KVM_CAP_HYPERV_VP_INDEX:
3008 case KVM_CAP_HYPERV_EVENTFD:
3009 case KVM_CAP_HYPERV_TLBFLUSH:
3010 case KVM_CAP_HYPERV_SEND_IPI:
3011 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3012 case KVM_CAP_HYPERV_CPUID:
3013 case KVM_CAP_PCI_SEGMENT:
3014 case KVM_CAP_DEBUGREGS:
3015 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3017 case KVM_CAP_ASYNC_PF:
3018 case KVM_CAP_GET_TSC_KHZ:
3019 case KVM_CAP_KVMCLOCK_CTRL:
3020 case KVM_CAP_READONLY_MEM:
3021 case KVM_CAP_HYPERV_TIME:
3022 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3023 case KVM_CAP_TSC_DEADLINE_TIMER:
3024 case KVM_CAP_DISABLE_QUIRKS:
3025 case KVM_CAP_SET_BOOT_CPU_ID:
3026 case KVM_CAP_SPLIT_IRQCHIP:
3027 case KVM_CAP_IMMEDIATE_EXIT:
3028 case KVM_CAP_GET_MSR_FEATURES:
3029 case KVM_CAP_MSR_PLATFORM_INFO:
3030 case KVM_CAP_EXCEPTION_PAYLOAD:
3033 case KVM_CAP_SYNC_REGS:
3034 r = KVM_SYNC_X86_VALID_FIELDS;
3036 case KVM_CAP_ADJUST_CLOCK:
3037 r = KVM_CLOCK_TSC_STABLE;
3039 case KVM_CAP_X86_DISABLE_EXITS:
3040 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
3041 if(kvm_can_mwait_in_guest())
3042 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3044 case KVM_CAP_X86_SMM:
3045 /* SMBASE is usually relocated above 1M on modern chipsets,
3046 * and SMM handlers might indeed rely on 4G segment limits,
3047 * so do not report SMM to be available if real mode is
3048 * emulated via vm86 mode. Still, do not go to great lengths
3049 * to avoid userspace's usage of the feature, because it is a
3050 * fringe case that is not enabled except via specific settings
3051 * of the module parameters.
3053 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3056 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3058 case KVM_CAP_NR_VCPUS:
3059 r = KVM_SOFT_MAX_VCPUS;
3061 case KVM_CAP_MAX_VCPUS:
3064 case KVM_CAP_NR_MEMSLOTS:
3065 r = KVM_USER_MEM_SLOTS;
3067 case KVM_CAP_PV_MMU: /* obsolete */
3071 r = KVM_MAX_MCE_BANKS;
3074 r = boot_cpu_has(X86_FEATURE_XSAVE);
3076 case KVM_CAP_TSC_CONTROL:
3077 r = kvm_has_tsc_control;
3079 case KVM_CAP_X2APIC_API:
3080 r = KVM_X2APIC_API_VALID_FLAGS;
3082 case KVM_CAP_NESTED_STATE:
3083 r = kvm_x86_ops->get_nested_state ?
3084 kvm_x86_ops->get_nested_state(NULL, 0, 0) : 0;
3093 long kvm_arch_dev_ioctl(struct file *filp,
3094 unsigned int ioctl, unsigned long arg)
3096 void __user *argp = (void __user *)arg;
3100 case KVM_GET_MSR_INDEX_LIST: {
3101 struct kvm_msr_list __user *user_msr_list = argp;
3102 struct kvm_msr_list msr_list;
3106 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3109 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3110 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3113 if (n < msr_list.nmsrs)
3116 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3117 num_msrs_to_save * sizeof(u32)))
3119 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3121 num_emulated_msrs * sizeof(u32)))
3126 case KVM_GET_SUPPORTED_CPUID:
3127 case KVM_GET_EMULATED_CPUID: {
3128 struct kvm_cpuid2 __user *cpuid_arg = argp;
3129 struct kvm_cpuid2 cpuid;
3132 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3135 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3141 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3146 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3148 if (copy_to_user(argp, &kvm_mce_cap_supported,
3149 sizeof(kvm_mce_cap_supported)))
3153 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3154 struct kvm_msr_list __user *user_msr_list = argp;
3155 struct kvm_msr_list msr_list;
3159 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3162 msr_list.nmsrs = num_msr_based_features;
3163 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3166 if (n < msr_list.nmsrs)
3169 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3170 num_msr_based_features * sizeof(u32)))
3176 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3186 static void wbinvd_ipi(void *garbage)
3191 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3193 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3196 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3198 /* Address WBINVD may be executed by guest */
3199 if (need_emulate_wbinvd(vcpu)) {
3200 if (kvm_x86_ops->has_wbinvd_exit())
3201 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3202 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3203 smp_call_function_single(vcpu->cpu,
3204 wbinvd_ipi, NULL, 1);
3207 kvm_x86_ops->vcpu_load(vcpu, cpu);
3209 /* Apply any externally detected TSC adjustments (due to suspend) */
3210 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3211 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3212 vcpu->arch.tsc_offset_adjustment = 0;
3213 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3216 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3217 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3218 rdtsc() - vcpu->arch.last_host_tsc;
3220 mark_tsc_unstable("KVM discovered backwards TSC");
3222 if (kvm_check_tsc_unstable()) {
3223 u64 offset = kvm_compute_tsc_offset(vcpu,
3224 vcpu->arch.last_guest_tsc);
3225 kvm_vcpu_write_tsc_offset(vcpu, offset);
3226 vcpu->arch.tsc_catchup = 1;
3229 if (kvm_lapic_hv_timer_in_use(vcpu))
3230 kvm_lapic_restart_hv_timer(vcpu);
3233 * On a host with synchronized TSC, there is no need to update
3234 * kvmclock on vcpu->cpu migration
3236 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3237 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3238 if (vcpu->cpu != cpu)
3239 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3243 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3246 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3248 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3251 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
3253 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3254 &vcpu->arch.st.steal.preempted,
3255 offsetof(struct kvm_steal_time, preempted),
3256 sizeof(vcpu->arch.st.steal.preempted));
3259 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3263 if (vcpu->preempted)
3264 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3267 * Disable page faults because we're in atomic context here.
3268 * kvm_write_guest_offset_cached() would call might_fault()
3269 * that relies on pagefault_disable() to tell if there's a
3270 * bug. NOTE: the write to guest memory may not go through if
3271 * during postcopy live migration or if there's heavy guest
3274 pagefault_disable();
3276 * kvm_memslots() will be called by
3277 * kvm_write_guest_offset_cached() so take the srcu lock.
3279 idx = srcu_read_lock(&vcpu->kvm->srcu);
3280 kvm_steal_time_set_preempted(vcpu);
3281 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3283 kvm_x86_ops->vcpu_put(vcpu);
3284 vcpu->arch.last_host_tsc = rdtsc();
3286 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3287 * on every vmexit, but if not, we might have a stale dr6 from the
3288 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3293 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3294 struct kvm_lapic_state *s)
3296 if (vcpu->arch.apicv_active)
3297 kvm_x86_ops->sync_pir_to_irr(vcpu);
3299 return kvm_apic_get_state(vcpu, s);
3302 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3303 struct kvm_lapic_state *s)
3307 r = kvm_apic_set_state(vcpu, s);
3310 update_cr8_intercept(vcpu);
3315 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3317 return (!lapic_in_kernel(vcpu) ||
3318 kvm_apic_accept_pic_intr(vcpu));
3322 * if userspace requested an interrupt window, check that the
3323 * interrupt window is open.
3325 * No need to exit to userspace if we already have an interrupt queued.
3327 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3329 return kvm_arch_interrupt_allowed(vcpu) &&
3330 !kvm_cpu_has_interrupt(vcpu) &&
3331 !kvm_event_needs_reinjection(vcpu) &&
3332 kvm_cpu_accept_dm_intr(vcpu);
3335 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3336 struct kvm_interrupt *irq)
3338 if (irq->irq >= KVM_NR_INTERRUPTS)
3341 if (!irqchip_in_kernel(vcpu->kvm)) {
3342 kvm_queue_interrupt(vcpu, irq->irq, false);
3343 kvm_make_request(KVM_REQ_EVENT, vcpu);
3348 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3349 * fail for in-kernel 8259.
3351 if (pic_in_kernel(vcpu->kvm))
3354 if (vcpu->arch.pending_external_vector != -1)
3357 vcpu->arch.pending_external_vector = irq->irq;
3358 kvm_make_request(KVM_REQ_EVENT, vcpu);
3362 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3364 kvm_inject_nmi(vcpu);
3369 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3371 kvm_make_request(KVM_REQ_SMI, vcpu);
3376 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3377 struct kvm_tpr_access_ctl *tac)
3381 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3385 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3389 unsigned bank_num = mcg_cap & 0xff, bank;
3392 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3394 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3397 vcpu->arch.mcg_cap = mcg_cap;
3398 /* Init IA32_MCG_CTL to all 1s */
3399 if (mcg_cap & MCG_CTL_P)
3400 vcpu->arch.mcg_ctl = ~(u64)0;
3401 /* Init IA32_MCi_CTL to all 1s */
3402 for (bank = 0; bank < bank_num; bank++)
3403 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3405 if (kvm_x86_ops->setup_mce)
3406 kvm_x86_ops->setup_mce(vcpu);
3411 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3412 struct kvm_x86_mce *mce)
3414 u64 mcg_cap = vcpu->arch.mcg_cap;
3415 unsigned bank_num = mcg_cap & 0xff;
3416 u64 *banks = vcpu->arch.mce_banks;
3418 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3421 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3422 * reporting is disabled
3424 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3425 vcpu->arch.mcg_ctl != ~(u64)0)
3427 banks += 4 * mce->bank;
3429 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3430 * reporting is disabled for the bank
3432 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3434 if (mce->status & MCI_STATUS_UC) {
3435 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3436 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3437 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3440 if (banks[1] & MCI_STATUS_VAL)
3441 mce->status |= MCI_STATUS_OVER;
3442 banks[2] = mce->addr;
3443 banks[3] = mce->misc;
3444 vcpu->arch.mcg_status = mce->mcg_status;
3445 banks[1] = mce->status;
3446 kvm_queue_exception(vcpu, MC_VECTOR);
3447 } else if (!(banks[1] & MCI_STATUS_VAL)
3448 || !(banks[1] & MCI_STATUS_UC)) {
3449 if (banks[1] & MCI_STATUS_VAL)
3450 mce->status |= MCI_STATUS_OVER;
3451 banks[2] = mce->addr;
3452 banks[3] = mce->misc;
3453 banks[1] = mce->status;
3455 banks[1] |= MCI_STATUS_OVER;
3459 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3460 struct kvm_vcpu_events *events)
3465 * The API doesn't provide the instruction length for software
3466 * exceptions, so don't report them. As long as the guest RIP
3467 * isn't advanced, we should expect to encounter the exception
3470 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3471 events->exception.injected = 0;
3472 events->exception.pending = 0;
3474 events->exception.injected = vcpu->arch.exception.injected;
3475 events->exception.pending = vcpu->arch.exception.pending;
3477 * For ABI compatibility, deliberately conflate
3478 * pending and injected exceptions when
3479 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3481 if (!vcpu->kvm->arch.exception_payload_enabled)
3482 events->exception.injected |=
3483 vcpu->arch.exception.pending;
3485 events->exception.nr = vcpu->arch.exception.nr;
3486 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3487 events->exception.error_code = vcpu->arch.exception.error_code;
3488 events->exception_has_payload = vcpu->arch.exception.has_payload;
3489 events->exception_payload = vcpu->arch.exception.payload;
3491 events->interrupt.injected =
3492 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3493 events->interrupt.nr = vcpu->arch.interrupt.nr;
3494 events->interrupt.soft = 0;
3495 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3497 events->nmi.injected = vcpu->arch.nmi_injected;
3498 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3499 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3500 events->nmi.pad = 0;
3502 events->sipi_vector = 0; /* never valid when reporting to user space */
3504 events->smi.smm = is_smm(vcpu);
3505 events->smi.pending = vcpu->arch.smi_pending;
3506 events->smi.smm_inside_nmi =
3507 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3508 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3510 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3511 | KVM_VCPUEVENT_VALID_SHADOW
3512 | KVM_VCPUEVENT_VALID_SMM);
3513 if (vcpu->kvm->arch.exception_payload_enabled)
3514 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3516 memset(&events->reserved, 0, sizeof(events->reserved));
3519 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3521 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3522 struct kvm_vcpu_events *events)
3524 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3525 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3526 | KVM_VCPUEVENT_VALID_SHADOW
3527 | KVM_VCPUEVENT_VALID_SMM
3528 | KVM_VCPUEVENT_VALID_PAYLOAD))
3531 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3532 if (!vcpu->kvm->arch.exception_payload_enabled)
3534 if (events->exception.pending)
3535 events->exception.injected = 0;
3537 events->exception_has_payload = 0;
3539 events->exception.pending = 0;
3540 events->exception_has_payload = 0;
3543 if ((events->exception.injected || events->exception.pending) &&
3544 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3547 /* INITs are latched while in SMM */
3548 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3549 (events->smi.smm || events->smi.pending) &&
3550 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3554 vcpu->arch.exception.injected = events->exception.injected;
3555 vcpu->arch.exception.pending = events->exception.pending;
3556 vcpu->arch.exception.nr = events->exception.nr;
3557 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3558 vcpu->arch.exception.error_code = events->exception.error_code;
3559 vcpu->arch.exception.has_payload = events->exception_has_payload;
3560 vcpu->arch.exception.payload = events->exception_payload;
3562 vcpu->arch.interrupt.injected = events->interrupt.injected;
3563 vcpu->arch.interrupt.nr = events->interrupt.nr;
3564 vcpu->arch.interrupt.soft = events->interrupt.soft;
3565 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3566 kvm_x86_ops->set_interrupt_shadow(vcpu,
3567 events->interrupt.shadow);
3569 vcpu->arch.nmi_injected = events->nmi.injected;
3570 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3571 vcpu->arch.nmi_pending = events->nmi.pending;
3572 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3574 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3575 lapic_in_kernel(vcpu))
3576 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3578 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3579 u32 hflags = vcpu->arch.hflags;
3580 if (events->smi.smm)
3581 hflags |= HF_SMM_MASK;
3583 hflags &= ~HF_SMM_MASK;
3584 kvm_set_hflags(vcpu, hflags);
3586 vcpu->arch.smi_pending = events->smi.pending;
3588 if (events->smi.smm) {
3589 if (events->smi.smm_inside_nmi)
3590 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3592 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3593 if (lapic_in_kernel(vcpu)) {
3594 if (events->smi.latched_init)
3595 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3597 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3602 kvm_make_request(KVM_REQ_EVENT, vcpu);
3607 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3608 struct kvm_debugregs *dbgregs)
3612 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3613 kvm_get_dr(vcpu, 6, &val);
3615 dbgregs->dr7 = vcpu->arch.dr7;
3617 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3620 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3621 struct kvm_debugregs *dbgregs)
3626 if (dbgregs->dr6 & ~0xffffffffull)
3628 if (dbgregs->dr7 & ~0xffffffffull)
3631 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3632 kvm_update_dr0123(vcpu);
3633 vcpu->arch.dr6 = dbgregs->dr6;
3634 kvm_update_dr6(vcpu);
3635 vcpu->arch.dr7 = dbgregs->dr7;
3636 kvm_update_dr7(vcpu);
3641 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3643 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3645 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3646 u64 xstate_bv = xsave->header.xfeatures;
3650 * Copy legacy XSAVE area, to avoid complications with CPUID
3651 * leaves 0 and 1 in the loop below.
3653 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3656 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3657 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3660 * Copy each region from the possibly compacted offset to the
3661 * non-compacted offset.
3663 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3665 u64 feature = valid & -valid;
3666 int index = fls64(feature) - 1;
3667 void *src = get_xsave_addr(xsave, feature);
3670 u32 size, offset, ecx, edx;
3671 cpuid_count(XSTATE_CPUID, index,
3672 &size, &offset, &ecx, &edx);
3673 if (feature == XFEATURE_MASK_PKRU)
3674 memcpy(dest + offset, &vcpu->arch.pkru,
3675 sizeof(vcpu->arch.pkru));
3677 memcpy(dest + offset, src, size);
3685 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3687 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3688 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3692 * Copy legacy XSAVE area, to avoid complications with CPUID
3693 * leaves 0 and 1 in the loop below.
3695 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3697 /* Set XSTATE_BV and possibly XCOMP_BV. */
3698 xsave->header.xfeatures = xstate_bv;
3699 if (boot_cpu_has(X86_FEATURE_XSAVES))
3700 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3703 * Copy each region from the non-compacted offset to the
3704 * possibly compacted offset.
3706 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3708 u64 feature = valid & -valid;
3709 int index = fls64(feature) - 1;
3710 void *dest = get_xsave_addr(xsave, feature);
3713 u32 size, offset, ecx, edx;
3714 cpuid_count(XSTATE_CPUID, index,
3715 &size, &offset, &ecx, &edx);
3716 if (feature == XFEATURE_MASK_PKRU)
3717 memcpy(&vcpu->arch.pkru, src + offset,
3718 sizeof(vcpu->arch.pkru));
3720 memcpy(dest, src + offset, size);
3727 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3728 struct kvm_xsave *guest_xsave)
3730 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3731 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3732 fill_xsave((u8 *) guest_xsave->region, vcpu);
3734 memcpy(guest_xsave->region,
3735 &vcpu->arch.guest_fpu->state.fxsave,
3736 sizeof(struct fxregs_state));
3737 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3738 XFEATURE_MASK_FPSSE;
3742 #define XSAVE_MXCSR_OFFSET 24
3744 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3745 struct kvm_xsave *guest_xsave)
3748 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3749 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3751 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3753 * Here we allow setting states that are not present in
3754 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3755 * with old userspace.
3757 if (xstate_bv & ~kvm_supported_xcr0() ||
3758 mxcsr & ~mxcsr_feature_mask)
3760 load_xsave(vcpu, (u8 *)guest_xsave->region);
3762 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3763 mxcsr & ~mxcsr_feature_mask)
3765 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
3766 guest_xsave->region, sizeof(struct fxregs_state));
3771 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3772 struct kvm_xcrs *guest_xcrs)
3774 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3775 guest_xcrs->nr_xcrs = 0;
3779 guest_xcrs->nr_xcrs = 1;
3780 guest_xcrs->flags = 0;
3781 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3782 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3785 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3786 struct kvm_xcrs *guest_xcrs)
3790 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3793 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3796 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3797 /* Only support XCR0 currently */
3798 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3799 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3800 guest_xcrs->xcrs[i].value);
3809 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3810 * stopped by the hypervisor. This function will be called from the host only.
3811 * EINVAL is returned when the host attempts to set the flag for a guest that
3812 * does not support pv clocks.
3814 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3816 if (!vcpu->arch.pv_time_enabled)
3818 vcpu->arch.pvclock_set_guest_stopped_request = true;
3819 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3823 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3824 struct kvm_enable_cap *cap)
3827 uint16_t vmcs_version;
3828 void __user *user_ptr;
3834 case KVM_CAP_HYPERV_SYNIC2:
3837 case KVM_CAP_HYPERV_SYNIC:
3838 if (!irqchip_in_kernel(vcpu->kvm))
3840 return kvm_hv_activate_synic(vcpu, cap->cap ==
3841 KVM_CAP_HYPERV_SYNIC2);
3842 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3843 if (!kvm_x86_ops->nested_enable_evmcs)
3845 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3847 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3848 if (copy_to_user(user_ptr, &vmcs_version,
3849 sizeof(vmcs_version)))
3859 long kvm_arch_vcpu_ioctl(struct file *filp,
3860 unsigned int ioctl, unsigned long arg)
3862 struct kvm_vcpu *vcpu = filp->private_data;
3863 void __user *argp = (void __user *)arg;
3866 struct kvm_lapic_state *lapic;
3867 struct kvm_xsave *xsave;
3868 struct kvm_xcrs *xcrs;
3876 case KVM_GET_LAPIC: {
3878 if (!lapic_in_kernel(vcpu))
3880 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3885 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3889 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3894 case KVM_SET_LAPIC: {
3896 if (!lapic_in_kernel(vcpu))
3898 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3899 if (IS_ERR(u.lapic)) {
3900 r = PTR_ERR(u.lapic);
3904 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3907 case KVM_INTERRUPT: {
3908 struct kvm_interrupt irq;
3911 if (copy_from_user(&irq, argp, sizeof(irq)))
3913 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3917 r = kvm_vcpu_ioctl_nmi(vcpu);
3921 r = kvm_vcpu_ioctl_smi(vcpu);
3924 case KVM_SET_CPUID: {
3925 struct kvm_cpuid __user *cpuid_arg = argp;
3926 struct kvm_cpuid cpuid;
3929 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3931 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3934 case KVM_SET_CPUID2: {
3935 struct kvm_cpuid2 __user *cpuid_arg = argp;
3936 struct kvm_cpuid2 cpuid;
3939 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3941 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3942 cpuid_arg->entries);
3945 case KVM_GET_CPUID2: {
3946 struct kvm_cpuid2 __user *cpuid_arg = argp;
3947 struct kvm_cpuid2 cpuid;
3950 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3952 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3953 cpuid_arg->entries);
3957 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3962 case KVM_GET_MSRS: {
3963 int idx = srcu_read_lock(&vcpu->kvm->srcu);
3964 r = msr_io(vcpu, argp, do_get_msr, 1);
3965 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3968 case KVM_SET_MSRS: {
3969 int idx = srcu_read_lock(&vcpu->kvm->srcu);
3970 r = msr_io(vcpu, argp, do_set_msr, 0);
3971 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3974 case KVM_TPR_ACCESS_REPORTING: {
3975 struct kvm_tpr_access_ctl tac;
3978 if (copy_from_user(&tac, argp, sizeof(tac)))
3980 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3984 if (copy_to_user(argp, &tac, sizeof(tac)))
3989 case KVM_SET_VAPIC_ADDR: {
3990 struct kvm_vapic_addr va;
3994 if (!lapic_in_kernel(vcpu))
3997 if (copy_from_user(&va, argp, sizeof(va)))
3999 idx = srcu_read_lock(&vcpu->kvm->srcu);
4000 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4001 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4004 case KVM_X86_SETUP_MCE: {
4008 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4010 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4013 case KVM_X86_SET_MCE: {
4014 struct kvm_x86_mce mce;
4017 if (copy_from_user(&mce, argp, sizeof(mce)))
4019 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4022 case KVM_GET_VCPU_EVENTS: {
4023 struct kvm_vcpu_events events;
4025 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4028 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4033 case KVM_SET_VCPU_EVENTS: {
4034 struct kvm_vcpu_events events;
4037 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4040 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4043 case KVM_GET_DEBUGREGS: {
4044 struct kvm_debugregs dbgregs;
4046 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4049 if (copy_to_user(argp, &dbgregs,
4050 sizeof(struct kvm_debugregs)))
4055 case KVM_SET_DEBUGREGS: {
4056 struct kvm_debugregs dbgregs;
4059 if (copy_from_user(&dbgregs, argp,
4060 sizeof(struct kvm_debugregs)))
4063 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4066 case KVM_GET_XSAVE: {
4067 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
4072 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4075 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4080 case KVM_SET_XSAVE: {
4081 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4082 if (IS_ERR(u.xsave)) {
4083 r = PTR_ERR(u.xsave);
4087 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4090 case KVM_GET_XCRS: {
4091 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
4096 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4099 if (copy_to_user(argp, u.xcrs,
4100 sizeof(struct kvm_xcrs)))
4105 case KVM_SET_XCRS: {
4106 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4107 if (IS_ERR(u.xcrs)) {
4108 r = PTR_ERR(u.xcrs);
4112 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4115 case KVM_SET_TSC_KHZ: {
4119 user_tsc_khz = (u32)arg;
4121 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4124 if (user_tsc_khz == 0)
4125 user_tsc_khz = tsc_khz;
4127 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4132 case KVM_GET_TSC_KHZ: {
4133 r = vcpu->arch.virtual_tsc_khz;
4136 case KVM_KVMCLOCK_CTRL: {
4137 r = kvm_set_guest_paused(vcpu);
4140 case KVM_ENABLE_CAP: {
4141 struct kvm_enable_cap cap;
4144 if (copy_from_user(&cap, argp, sizeof(cap)))
4146 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4149 case KVM_GET_NESTED_STATE: {
4150 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4154 if (!kvm_x86_ops->get_nested_state)
4157 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4159 if (get_user(user_data_size, &user_kvm_nested_state->size))
4162 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4167 if (r > user_data_size) {
4168 if (put_user(r, &user_kvm_nested_state->size))
4178 case KVM_SET_NESTED_STATE: {
4179 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4180 struct kvm_nested_state kvm_state;
4183 if (!kvm_x86_ops->set_nested_state)
4187 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4191 if (kvm_state.size < sizeof(kvm_state))
4194 if (kvm_state.flags &
4195 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4196 | KVM_STATE_NESTED_EVMCS))
4199 /* nested_run_pending implies guest_mode. */
4200 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4201 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4204 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4207 case KVM_GET_SUPPORTED_HV_CPUID: {
4208 struct kvm_cpuid2 __user *cpuid_arg = argp;
4209 struct kvm_cpuid2 cpuid;
4212 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4215 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4216 cpuid_arg->entries);
4221 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4236 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4238 return VM_FAULT_SIGBUS;
4241 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4245 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4247 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4251 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4254 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4257 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4258 u32 kvm_nr_mmu_pages)
4260 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4263 mutex_lock(&kvm->slots_lock);
4265 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4266 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4268 mutex_unlock(&kvm->slots_lock);
4272 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4274 return kvm->arch.n_max_mmu_pages;
4277 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4279 struct kvm_pic *pic = kvm->arch.vpic;
4283 switch (chip->chip_id) {
4284 case KVM_IRQCHIP_PIC_MASTER:
4285 memcpy(&chip->chip.pic, &pic->pics[0],
4286 sizeof(struct kvm_pic_state));
4288 case KVM_IRQCHIP_PIC_SLAVE:
4289 memcpy(&chip->chip.pic, &pic->pics[1],
4290 sizeof(struct kvm_pic_state));
4292 case KVM_IRQCHIP_IOAPIC:
4293 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4302 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4304 struct kvm_pic *pic = kvm->arch.vpic;
4308 switch (chip->chip_id) {
4309 case KVM_IRQCHIP_PIC_MASTER:
4310 spin_lock(&pic->lock);
4311 memcpy(&pic->pics[0], &chip->chip.pic,
4312 sizeof(struct kvm_pic_state));
4313 spin_unlock(&pic->lock);
4315 case KVM_IRQCHIP_PIC_SLAVE:
4316 spin_lock(&pic->lock);
4317 memcpy(&pic->pics[1], &chip->chip.pic,
4318 sizeof(struct kvm_pic_state));
4319 spin_unlock(&pic->lock);
4321 case KVM_IRQCHIP_IOAPIC:
4322 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4328 kvm_pic_update_irq(pic);
4332 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4334 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4336 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4338 mutex_lock(&kps->lock);
4339 memcpy(ps, &kps->channels, sizeof(*ps));
4340 mutex_unlock(&kps->lock);
4344 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4347 struct kvm_pit *pit = kvm->arch.vpit;
4349 mutex_lock(&pit->pit_state.lock);
4350 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4351 for (i = 0; i < 3; i++)
4352 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4353 mutex_unlock(&pit->pit_state.lock);
4357 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4359 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4360 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4361 sizeof(ps->channels));
4362 ps->flags = kvm->arch.vpit->pit_state.flags;
4363 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4364 memset(&ps->reserved, 0, sizeof(ps->reserved));
4368 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4372 u32 prev_legacy, cur_legacy;
4373 struct kvm_pit *pit = kvm->arch.vpit;
4375 mutex_lock(&pit->pit_state.lock);
4376 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4377 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4378 if (!prev_legacy && cur_legacy)
4380 memcpy(&pit->pit_state.channels, &ps->channels,
4381 sizeof(pit->pit_state.channels));
4382 pit->pit_state.flags = ps->flags;
4383 for (i = 0; i < 3; i++)
4384 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4386 mutex_unlock(&pit->pit_state.lock);
4390 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4391 struct kvm_reinject_control *control)
4393 struct kvm_pit *pit = kvm->arch.vpit;
4398 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4399 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4400 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4402 mutex_lock(&pit->pit_state.lock);
4403 kvm_pit_set_reinject(pit, control->pit_reinject);
4404 mutex_unlock(&pit->pit_state.lock);
4410 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4411 * @kvm: kvm instance
4412 * @log: slot id and address to which we copy the log
4414 * Steps 1-4 below provide general overview of dirty page logging. See
4415 * kvm_get_dirty_log_protect() function description for additional details.
4417 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4418 * always flush the TLB (step 4) even if previous step failed and the dirty
4419 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4420 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4421 * writes will be marked dirty for next log read.
4423 * 1. Take a snapshot of the bit and clear it if needed.
4424 * 2. Write protect the corresponding page.
4425 * 3. Copy the snapshot to the userspace.
4426 * 4. Flush TLB's if needed.
4428 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4433 mutex_lock(&kvm->slots_lock);
4436 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4438 if (kvm_x86_ops->flush_log_dirty)
4439 kvm_x86_ops->flush_log_dirty(kvm);
4441 r = kvm_get_dirty_log_protect(kvm, log, &flush);
4444 * All the TLBs can be flushed out of mmu lock, see the comments in
4445 * kvm_mmu_slot_remove_write_access().
4447 lockdep_assert_held(&kvm->slots_lock);
4449 kvm_flush_remote_tlbs(kvm);
4451 mutex_unlock(&kvm->slots_lock);
4455 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4460 mutex_lock(&kvm->slots_lock);
4463 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4465 if (kvm_x86_ops->flush_log_dirty)
4466 kvm_x86_ops->flush_log_dirty(kvm);
4468 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4471 * All the TLBs can be flushed out of mmu lock, see the comments in
4472 * kvm_mmu_slot_remove_write_access().
4474 lockdep_assert_held(&kvm->slots_lock);
4476 kvm_flush_remote_tlbs(kvm);
4478 mutex_unlock(&kvm->slots_lock);
4482 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4485 if (!irqchip_in_kernel(kvm))
4488 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4489 irq_event->irq, irq_event->level,
4494 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4495 struct kvm_enable_cap *cap)
4503 case KVM_CAP_DISABLE_QUIRKS:
4504 kvm->arch.disabled_quirks = cap->args[0];
4507 case KVM_CAP_SPLIT_IRQCHIP: {
4508 mutex_lock(&kvm->lock);
4510 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4511 goto split_irqchip_unlock;
4513 if (irqchip_in_kernel(kvm))
4514 goto split_irqchip_unlock;
4515 if (kvm->created_vcpus)
4516 goto split_irqchip_unlock;
4517 r = kvm_setup_empty_irq_routing(kvm);
4519 goto split_irqchip_unlock;
4520 /* Pairs with irqchip_in_kernel. */
4522 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4523 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4525 split_irqchip_unlock:
4526 mutex_unlock(&kvm->lock);
4529 case KVM_CAP_X2APIC_API:
4531 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4534 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4535 kvm->arch.x2apic_format = true;
4536 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4537 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4541 case KVM_CAP_X86_DISABLE_EXITS:
4543 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4546 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4547 kvm_can_mwait_in_guest())
4548 kvm->arch.mwait_in_guest = true;
4549 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4550 kvm->arch.hlt_in_guest = true;
4551 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4552 kvm->arch.pause_in_guest = true;
4555 case KVM_CAP_MSR_PLATFORM_INFO:
4556 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4559 case KVM_CAP_EXCEPTION_PAYLOAD:
4560 kvm->arch.exception_payload_enabled = cap->args[0];
4570 long kvm_arch_vm_ioctl(struct file *filp,
4571 unsigned int ioctl, unsigned long arg)
4573 struct kvm *kvm = filp->private_data;
4574 void __user *argp = (void __user *)arg;
4577 * This union makes it completely explicit to gcc-3.x
4578 * that these two variables' stack usage should be
4579 * combined, not added together.
4582 struct kvm_pit_state ps;
4583 struct kvm_pit_state2 ps2;
4584 struct kvm_pit_config pit_config;
4588 case KVM_SET_TSS_ADDR:
4589 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4591 case KVM_SET_IDENTITY_MAP_ADDR: {
4594 mutex_lock(&kvm->lock);
4596 if (kvm->created_vcpus)
4597 goto set_identity_unlock;
4599 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4600 goto set_identity_unlock;
4601 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4602 set_identity_unlock:
4603 mutex_unlock(&kvm->lock);
4606 case KVM_SET_NR_MMU_PAGES:
4607 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4609 case KVM_GET_NR_MMU_PAGES:
4610 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4612 case KVM_CREATE_IRQCHIP: {
4613 mutex_lock(&kvm->lock);
4616 if (irqchip_in_kernel(kvm))
4617 goto create_irqchip_unlock;
4620 if (kvm->created_vcpus)
4621 goto create_irqchip_unlock;
4623 r = kvm_pic_init(kvm);
4625 goto create_irqchip_unlock;
4627 r = kvm_ioapic_init(kvm);
4629 kvm_pic_destroy(kvm);
4630 goto create_irqchip_unlock;
4633 r = kvm_setup_default_irq_routing(kvm);
4635 kvm_ioapic_destroy(kvm);
4636 kvm_pic_destroy(kvm);
4637 goto create_irqchip_unlock;
4639 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4641 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4642 create_irqchip_unlock:
4643 mutex_unlock(&kvm->lock);
4646 case KVM_CREATE_PIT:
4647 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4649 case KVM_CREATE_PIT2:
4651 if (copy_from_user(&u.pit_config, argp,
4652 sizeof(struct kvm_pit_config)))
4655 mutex_lock(&kvm->lock);
4658 goto create_pit_unlock;
4660 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4664 mutex_unlock(&kvm->lock);
4666 case KVM_GET_IRQCHIP: {
4667 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4668 struct kvm_irqchip *chip;
4670 chip = memdup_user(argp, sizeof(*chip));
4677 if (!irqchip_kernel(kvm))
4678 goto get_irqchip_out;
4679 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4681 goto get_irqchip_out;
4683 if (copy_to_user(argp, chip, sizeof(*chip)))
4684 goto get_irqchip_out;
4690 case KVM_SET_IRQCHIP: {
4691 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4692 struct kvm_irqchip *chip;
4694 chip = memdup_user(argp, sizeof(*chip));
4701 if (!irqchip_kernel(kvm))
4702 goto set_irqchip_out;
4703 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4705 goto set_irqchip_out;
4713 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4716 if (!kvm->arch.vpit)
4718 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4722 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4729 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
4732 if (!kvm->arch.vpit)
4734 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4737 case KVM_GET_PIT2: {
4739 if (!kvm->arch.vpit)
4741 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4745 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4750 case KVM_SET_PIT2: {
4752 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4755 if (!kvm->arch.vpit)
4757 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4760 case KVM_REINJECT_CONTROL: {
4761 struct kvm_reinject_control control;
4763 if (copy_from_user(&control, argp, sizeof(control)))
4765 r = kvm_vm_ioctl_reinject(kvm, &control);
4768 case KVM_SET_BOOT_CPU_ID:
4770 mutex_lock(&kvm->lock);
4771 if (kvm->created_vcpus)
4774 kvm->arch.bsp_vcpu_id = arg;
4775 mutex_unlock(&kvm->lock);
4777 case KVM_XEN_HVM_CONFIG: {
4778 struct kvm_xen_hvm_config xhc;
4780 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4785 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4789 case KVM_SET_CLOCK: {
4790 struct kvm_clock_data user_ns;
4794 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4803 * TODO: userspace has to take care of races with VCPU_RUN, so
4804 * kvm_gen_update_masterclock() can be cut down to locked
4805 * pvclock_update_vm_gtod_copy().
4807 kvm_gen_update_masterclock(kvm);
4808 now_ns = get_kvmclock_ns(kvm);
4809 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4810 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4813 case KVM_GET_CLOCK: {
4814 struct kvm_clock_data user_ns;
4817 now_ns = get_kvmclock_ns(kvm);
4818 user_ns.clock = now_ns;
4819 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4820 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4823 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4828 case KVM_MEMORY_ENCRYPT_OP: {
4830 if (kvm_x86_ops->mem_enc_op)
4831 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4834 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4835 struct kvm_enc_region region;
4838 if (copy_from_user(®ion, argp, sizeof(region)))
4842 if (kvm_x86_ops->mem_enc_reg_region)
4843 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion);
4846 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4847 struct kvm_enc_region region;
4850 if (copy_from_user(®ion, argp, sizeof(region)))
4854 if (kvm_x86_ops->mem_enc_unreg_region)
4855 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion);
4858 case KVM_HYPERV_EVENTFD: {
4859 struct kvm_hyperv_eventfd hvevfd;
4862 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4864 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4874 static void kvm_init_msr_list(void)
4879 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4880 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4884 * Even MSRs that are valid in the host may not be exposed
4885 * to the guests in some cases.
4887 switch (msrs_to_save[i]) {
4888 case MSR_IA32_BNDCFGS:
4889 if (!kvm_mpx_supported())
4893 if (!kvm_x86_ops->rdtscp_supported())
4896 case MSR_IA32_RTIT_CTL:
4897 case MSR_IA32_RTIT_STATUS:
4898 if (!kvm_x86_ops->pt_supported())
4901 case MSR_IA32_RTIT_CR3_MATCH:
4902 if (!kvm_x86_ops->pt_supported() ||
4903 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
4906 case MSR_IA32_RTIT_OUTPUT_BASE:
4907 case MSR_IA32_RTIT_OUTPUT_MASK:
4908 if (!kvm_x86_ops->pt_supported() ||
4909 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
4910 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
4913 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
4914 if (!kvm_x86_ops->pt_supported() ||
4915 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
4916 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
4925 msrs_to_save[j] = msrs_to_save[i];
4928 num_msrs_to_save = j;
4930 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4931 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4935 emulated_msrs[j] = emulated_msrs[i];
4938 num_emulated_msrs = j;
4940 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4941 struct kvm_msr_entry msr;
4943 msr.index = msr_based_features[i];
4944 if (kvm_get_msr_feature(&msr))
4948 msr_based_features[j] = msr_based_features[i];
4951 num_msr_based_features = j;
4954 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4962 if (!(lapic_in_kernel(vcpu) &&
4963 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4964 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4975 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4982 if (!(lapic_in_kernel(vcpu) &&
4983 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4985 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4987 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
4997 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4998 struct kvm_segment *var, int seg)
5000 kvm_x86_ops->set_segment(vcpu, var, seg);
5003 void kvm_get_segment(struct kvm_vcpu *vcpu,
5004 struct kvm_segment *var, int seg)
5006 kvm_x86_ops->get_segment(vcpu, var, seg);
5009 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5010 struct x86_exception *exception)
5014 BUG_ON(!mmu_is_nested(vcpu));
5016 /* NPT walks are always user-walks */
5017 access |= PFERR_USER_MASK;
5018 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5023 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5024 struct x86_exception *exception)
5026 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5027 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5030 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5031 struct x86_exception *exception)
5033 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5034 access |= PFERR_FETCH_MASK;
5035 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5038 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5039 struct x86_exception *exception)
5041 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5042 access |= PFERR_WRITE_MASK;
5043 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5046 /* uses this to access any guest's mapped memory without checking CPL */
5047 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5048 struct x86_exception *exception)
5050 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5053 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5054 struct kvm_vcpu *vcpu, u32 access,
5055 struct x86_exception *exception)
5058 int r = X86EMUL_CONTINUE;
5061 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5063 unsigned offset = addr & (PAGE_SIZE-1);
5064 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5067 if (gpa == UNMAPPED_GVA)
5068 return X86EMUL_PROPAGATE_FAULT;
5069 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5072 r = X86EMUL_IO_NEEDED;
5084 /* used for instruction fetching */
5085 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5086 gva_t addr, void *val, unsigned int bytes,
5087 struct x86_exception *exception)
5089 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5090 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5094 /* Inline kvm_read_guest_virt_helper for speed. */
5095 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5097 if (unlikely(gpa == UNMAPPED_GVA))
5098 return X86EMUL_PROPAGATE_FAULT;
5100 offset = addr & (PAGE_SIZE-1);
5101 if (WARN_ON(offset + bytes > PAGE_SIZE))
5102 bytes = (unsigned)PAGE_SIZE - offset;
5103 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5105 if (unlikely(ret < 0))
5106 return X86EMUL_IO_NEEDED;
5108 return X86EMUL_CONTINUE;
5111 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5112 gva_t addr, void *val, unsigned int bytes,
5113 struct x86_exception *exception)
5115 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5117 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5120 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5122 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5123 gva_t addr, void *val, unsigned int bytes,
5124 struct x86_exception *exception, bool system)
5126 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5129 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5130 access |= PFERR_USER_MASK;
5132 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5135 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5136 unsigned long addr, void *val, unsigned int bytes)
5138 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5139 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5141 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5144 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5145 struct kvm_vcpu *vcpu, u32 access,
5146 struct x86_exception *exception)
5149 int r = X86EMUL_CONTINUE;
5152 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5155 unsigned offset = addr & (PAGE_SIZE-1);
5156 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5159 if (gpa == UNMAPPED_GVA)
5160 return X86EMUL_PROPAGATE_FAULT;
5161 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5163 r = X86EMUL_IO_NEEDED;
5175 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5176 unsigned int bytes, struct x86_exception *exception,
5179 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5180 u32 access = PFERR_WRITE_MASK;
5182 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5183 access |= PFERR_USER_MASK;
5185 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5189 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5190 unsigned int bytes, struct x86_exception *exception)
5192 /* kvm_write_guest_virt_system can pull in tons of pages. */
5193 vcpu->arch.l1tf_flush_l1d = true;
5195 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5196 PFERR_WRITE_MASK, exception);
5198 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5200 int handle_ud(struct kvm_vcpu *vcpu)
5202 int emul_type = EMULTYPE_TRAP_UD;
5203 enum emulation_result er;
5204 char sig[5]; /* ud2; .ascii "kvm" */
5205 struct x86_exception e;
5207 if (force_emulation_prefix &&
5208 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5209 sig, sizeof(sig), &e) == 0 &&
5210 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5211 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5215 er = kvm_emulate_instruction(vcpu, emul_type);
5216 if (er == EMULATE_USER_EXIT)
5218 if (er != EMULATE_DONE)
5219 kvm_queue_exception(vcpu, UD_VECTOR);
5222 EXPORT_SYMBOL_GPL(handle_ud);
5224 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5225 gpa_t gpa, bool write)
5227 /* For APIC access vmexit */
5228 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5231 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5232 trace_vcpu_match_mmio(gva, gpa, write, true);
5239 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5240 gpa_t *gpa, struct x86_exception *exception,
5243 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5244 | (write ? PFERR_WRITE_MASK : 0);
5247 * currently PKRU is only applied to ept enabled guest so
5248 * there is no pkey in EPT page table for L1 guest or EPT
5249 * shadow page table for L2 guest.
5251 if (vcpu_match_mmio_gva(vcpu, gva)
5252 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5253 vcpu->arch.access, 0, access)) {
5254 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5255 (gva & (PAGE_SIZE - 1));
5256 trace_vcpu_match_mmio(gva, *gpa, write, false);
5260 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5262 if (*gpa == UNMAPPED_GVA)
5265 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5268 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5269 const void *val, int bytes)
5273 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5276 kvm_page_track_write(vcpu, gpa, val, bytes);
5280 struct read_write_emulator_ops {
5281 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5283 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5284 void *val, int bytes);
5285 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5286 int bytes, void *val);
5287 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5288 void *val, int bytes);
5292 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5294 if (vcpu->mmio_read_completed) {
5295 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5296 vcpu->mmio_fragments[0].gpa, val);
5297 vcpu->mmio_read_completed = 0;
5304 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5305 void *val, int bytes)
5307 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5310 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5311 void *val, int bytes)
5313 return emulator_write_phys(vcpu, gpa, val, bytes);
5316 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5318 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5319 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5322 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5323 void *val, int bytes)
5325 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5326 return X86EMUL_IO_NEEDED;
5329 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5330 void *val, int bytes)
5332 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5334 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5335 return X86EMUL_CONTINUE;
5338 static const struct read_write_emulator_ops read_emultor = {
5339 .read_write_prepare = read_prepare,
5340 .read_write_emulate = read_emulate,
5341 .read_write_mmio = vcpu_mmio_read,
5342 .read_write_exit_mmio = read_exit_mmio,
5345 static const struct read_write_emulator_ops write_emultor = {
5346 .read_write_emulate = write_emulate,
5347 .read_write_mmio = write_mmio,
5348 .read_write_exit_mmio = write_exit_mmio,
5352 static int emulator_read_write_onepage(unsigned long addr, void *val,
5354 struct x86_exception *exception,
5355 struct kvm_vcpu *vcpu,
5356 const struct read_write_emulator_ops *ops)
5360 bool write = ops->write;
5361 struct kvm_mmio_fragment *frag;
5362 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5365 * If the exit was due to a NPF we may already have a GPA.
5366 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5367 * Note, this cannot be used on string operations since string
5368 * operation using rep will only have the initial GPA from the NPF
5371 if (vcpu->arch.gpa_available &&
5372 emulator_can_use_gpa(ctxt) &&
5373 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5374 gpa = vcpu->arch.gpa_val;
5375 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5377 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5379 return X86EMUL_PROPAGATE_FAULT;
5382 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5383 return X86EMUL_CONTINUE;
5386 * Is this MMIO handled locally?
5388 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5389 if (handled == bytes)
5390 return X86EMUL_CONTINUE;
5396 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5397 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5401 return X86EMUL_CONTINUE;
5404 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5406 void *val, unsigned int bytes,
5407 struct x86_exception *exception,
5408 const struct read_write_emulator_ops *ops)
5410 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5414 if (ops->read_write_prepare &&
5415 ops->read_write_prepare(vcpu, val, bytes))
5416 return X86EMUL_CONTINUE;
5418 vcpu->mmio_nr_fragments = 0;
5420 /* Crossing a page boundary? */
5421 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5424 now = -addr & ~PAGE_MASK;
5425 rc = emulator_read_write_onepage(addr, val, now, exception,
5428 if (rc != X86EMUL_CONTINUE)
5431 if (ctxt->mode != X86EMUL_MODE_PROT64)
5437 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5439 if (rc != X86EMUL_CONTINUE)
5442 if (!vcpu->mmio_nr_fragments)
5445 gpa = vcpu->mmio_fragments[0].gpa;
5447 vcpu->mmio_needed = 1;
5448 vcpu->mmio_cur_fragment = 0;
5450 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5451 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5452 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5453 vcpu->run->mmio.phys_addr = gpa;
5455 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5458 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5462 struct x86_exception *exception)
5464 return emulator_read_write(ctxt, addr, val, bytes,
5465 exception, &read_emultor);
5468 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5472 struct x86_exception *exception)
5474 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5475 exception, &write_emultor);
5478 #define CMPXCHG_TYPE(t, ptr, old, new) \
5479 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5481 #ifdef CONFIG_X86_64
5482 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5484 # define CMPXCHG64(ptr, old, new) \
5485 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5488 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5493 struct x86_exception *exception)
5495 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5501 /* guests cmpxchg8b have to be emulated atomically */
5502 if (bytes > 8 || (bytes & (bytes - 1)))
5505 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5507 if (gpa == UNMAPPED_GVA ||
5508 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5511 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5514 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
5515 if (is_error_page(page))
5518 kaddr = kmap_atomic(page);
5519 kaddr += offset_in_page(gpa);
5522 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5525 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5528 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5531 exchanged = CMPXCHG64(kaddr, old, new);
5536 kunmap_atomic(kaddr);
5537 kvm_release_page_dirty(page);
5540 return X86EMUL_CMPXCHG_FAILED;
5542 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5543 kvm_page_track_write(vcpu, gpa, new, bytes);
5545 return X86EMUL_CONTINUE;
5548 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5550 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5553 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5557 for (i = 0; i < vcpu->arch.pio.count; i++) {
5558 if (vcpu->arch.pio.in)
5559 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5560 vcpu->arch.pio.size, pd);
5562 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5563 vcpu->arch.pio.port, vcpu->arch.pio.size,
5567 pd += vcpu->arch.pio.size;
5572 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5573 unsigned short port, void *val,
5574 unsigned int count, bool in)
5576 vcpu->arch.pio.port = port;
5577 vcpu->arch.pio.in = in;
5578 vcpu->arch.pio.count = count;
5579 vcpu->arch.pio.size = size;
5581 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5582 vcpu->arch.pio.count = 0;
5586 vcpu->run->exit_reason = KVM_EXIT_IO;
5587 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5588 vcpu->run->io.size = size;
5589 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5590 vcpu->run->io.count = count;
5591 vcpu->run->io.port = port;
5596 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5597 int size, unsigned short port, void *val,
5600 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5603 if (vcpu->arch.pio.count)
5606 memset(vcpu->arch.pio_data, 0, size * count);
5608 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5611 memcpy(val, vcpu->arch.pio_data, size * count);
5612 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5613 vcpu->arch.pio.count = 0;
5620 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5621 int size, unsigned short port,
5622 const void *val, unsigned int count)
5624 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5626 memcpy(vcpu->arch.pio_data, val, size * count);
5627 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5628 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5631 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5633 return kvm_x86_ops->get_segment_base(vcpu, seg);
5636 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5638 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5641 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5643 if (!need_emulate_wbinvd(vcpu))
5644 return X86EMUL_CONTINUE;
5646 if (kvm_x86_ops->has_wbinvd_exit()) {
5647 int cpu = get_cpu();
5649 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5650 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5651 wbinvd_ipi, NULL, 1);
5653 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5656 return X86EMUL_CONTINUE;
5659 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5661 kvm_emulate_wbinvd_noskip(vcpu);
5662 return kvm_skip_emulated_instruction(vcpu);
5664 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5668 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5670 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5673 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5674 unsigned long *dest)
5676 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5679 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5680 unsigned long value)
5683 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5686 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5688 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5691 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5693 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5694 unsigned long value;
5698 value = kvm_read_cr0(vcpu);
5701 value = vcpu->arch.cr2;
5704 value = kvm_read_cr3(vcpu);
5707 value = kvm_read_cr4(vcpu);
5710 value = kvm_get_cr8(vcpu);
5713 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5720 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5722 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5727 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5730 vcpu->arch.cr2 = val;
5733 res = kvm_set_cr3(vcpu, val);
5736 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5739 res = kvm_set_cr8(vcpu, val);
5742 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5749 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5751 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5754 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5756 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5759 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5761 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5764 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5766 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5769 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5771 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5774 static unsigned long emulator_get_cached_segment_base(
5775 struct x86_emulate_ctxt *ctxt, int seg)
5777 return get_segment_base(emul_to_vcpu(ctxt), seg);
5780 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5781 struct desc_struct *desc, u32 *base3,
5784 struct kvm_segment var;
5786 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5787 *selector = var.selector;
5790 memset(desc, 0, sizeof(*desc));
5798 set_desc_limit(desc, var.limit);
5799 set_desc_base(desc, (unsigned long)var.base);
5800 #ifdef CONFIG_X86_64
5802 *base3 = var.base >> 32;
5804 desc->type = var.type;
5806 desc->dpl = var.dpl;
5807 desc->p = var.present;
5808 desc->avl = var.avl;
5816 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5817 struct desc_struct *desc, u32 base3,
5820 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5821 struct kvm_segment var;
5823 var.selector = selector;
5824 var.base = get_desc_base(desc);
5825 #ifdef CONFIG_X86_64
5826 var.base |= ((u64)base3) << 32;
5828 var.limit = get_desc_limit(desc);
5830 var.limit = (var.limit << 12) | 0xfff;
5831 var.type = desc->type;
5832 var.dpl = desc->dpl;
5837 var.avl = desc->avl;
5838 var.present = desc->p;
5839 var.unusable = !var.present;
5842 kvm_set_segment(vcpu, &var, seg);
5846 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5847 u32 msr_index, u64 *pdata)
5849 struct msr_data msr;
5852 msr.index = msr_index;
5853 msr.host_initiated = false;
5854 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5862 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5863 u32 msr_index, u64 data)
5865 struct msr_data msr;
5868 msr.index = msr_index;
5869 msr.host_initiated = false;
5870 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5873 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5875 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5877 return vcpu->arch.smbase;
5880 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5882 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5884 vcpu->arch.smbase = smbase;
5887 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5890 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5893 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5894 u32 pmc, u64 *pdata)
5896 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5899 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5901 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5904 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5905 struct x86_instruction_info *info,
5906 enum x86_intercept_stage stage)
5908 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5911 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5912 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
5914 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
5917 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5919 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5922 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5924 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5927 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5929 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5932 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5934 return emul_to_vcpu(ctxt)->arch.hflags;
5937 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5939 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5942 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5944 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5947 static const struct x86_emulate_ops emulate_ops = {
5948 .read_gpr = emulator_read_gpr,
5949 .write_gpr = emulator_write_gpr,
5950 .read_std = emulator_read_std,
5951 .write_std = emulator_write_std,
5952 .read_phys = kvm_read_guest_phys_system,
5953 .fetch = kvm_fetch_guest_virt,
5954 .read_emulated = emulator_read_emulated,
5955 .write_emulated = emulator_write_emulated,
5956 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5957 .invlpg = emulator_invlpg,
5958 .pio_in_emulated = emulator_pio_in_emulated,
5959 .pio_out_emulated = emulator_pio_out_emulated,
5960 .get_segment = emulator_get_segment,
5961 .set_segment = emulator_set_segment,
5962 .get_cached_segment_base = emulator_get_cached_segment_base,
5963 .get_gdt = emulator_get_gdt,
5964 .get_idt = emulator_get_idt,
5965 .set_gdt = emulator_set_gdt,
5966 .set_idt = emulator_set_idt,
5967 .get_cr = emulator_get_cr,
5968 .set_cr = emulator_set_cr,
5969 .cpl = emulator_get_cpl,
5970 .get_dr = emulator_get_dr,
5971 .set_dr = emulator_set_dr,
5972 .get_smbase = emulator_get_smbase,
5973 .set_smbase = emulator_set_smbase,
5974 .set_msr = emulator_set_msr,
5975 .get_msr = emulator_get_msr,
5976 .check_pmc = emulator_check_pmc,
5977 .read_pmc = emulator_read_pmc,
5978 .halt = emulator_halt,
5979 .wbinvd = emulator_wbinvd,
5980 .fix_hypercall = emulator_fix_hypercall,
5981 .intercept = emulator_intercept,
5982 .get_cpuid = emulator_get_cpuid,
5983 .set_nmi_mask = emulator_set_nmi_mask,
5984 .get_hflags = emulator_get_hflags,
5985 .set_hflags = emulator_set_hflags,
5986 .pre_leave_smm = emulator_pre_leave_smm,
5989 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5991 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5993 * an sti; sti; sequence only disable interrupts for the first
5994 * instruction. So, if the last instruction, be it emulated or
5995 * not, left the system with the INT_STI flag enabled, it
5996 * means that the last instruction is an sti. We should not
5997 * leave the flag on in this case. The same goes for mov ss
5999 if (int_shadow & mask)
6001 if (unlikely(int_shadow || mask)) {
6002 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6004 kvm_make_request(KVM_REQ_EVENT, vcpu);
6008 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6010 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6011 if (ctxt->exception.vector == PF_VECTOR)
6012 return kvm_propagate_fault(vcpu, &ctxt->exception);
6014 if (ctxt->exception.error_code_valid)
6015 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6016 ctxt->exception.error_code);
6018 kvm_queue_exception(vcpu, ctxt->exception.vector);
6022 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6024 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6027 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6029 ctxt->eflags = kvm_get_rflags(vcpu);
6030 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6032 ctxt->eip = kvm_rip_read(vcpu);
6033 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6034 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6035 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6036 cs_db ? X86EMUL_MODE_PROT32 :
6037 X86EMUL_MODE_PROT16;
6038 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6039 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6040 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6042 init_decode_cache(ctxt);
6043 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6046 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6048 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6051 init_emulate_ctxt(vcpu);
6055 ctxt->_eip = ctxt->eip + inc_eip;
6056 ret = emulate_int_real(ctxt, irq);
6058 if (ret != X86EMUL_CONTINUE)
6059 return EMULATE_FAIL;
6061 ctxt->eip = ctxt->_eip;
6062 kvm_rip_write(vcpu, ctxt->eip);
6063 kvm_set_rflags(vcpu, ctxt->eflags);
6065 return EMULATE_DONE;
6067 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6069 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6071 int r = EMULATE_DONE;
6073 ++vcpu->stat.insn_emulation_fail;
6074 trace_kvm_emulate_insn_failed(vcpu);
6076 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6077 return EMULATE_FAIL;
6079 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6080 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6081 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6082 vcpu->run->internal.ndata = 0;
6083 r = EMULATE_USER_EXIT;
6086 kvm_queue_exception(vcpu, UD_VECTOR);
6091 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
6092 bool write_fault_to_shadow_pgtable,
6098 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6101 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6104 if (!vcpu->arch.mmu->direct_map) {
6106 * Write permission should be allowed since only
6107 * write access need to be emulated.
6109 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6112 * If the mapping is invalid in guest, let cpu retry
6113 * it to generate fault.
6115 if (gpa == UNMAPPED_GVA)
6120 * Do not retry the unhandleable instruction if it faults on the
6121 * readonly host memory, otherwise it will goto a infinite loop:
6122 * retry instruction -> write #PF -> emulation fail -> retry
6123 * instruction -> ...
6125 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6128 * If the instruction failed on the error pfn, it can not be fixed,
6129 * report the error to userspace.
6131 if (is_error_noslot_pfn(pfn))
6134 kvm_release_pfn_clean(pfn);
6136 /* The instructions are well-emulated on direct mmu. */
6137 if (vcpu->arch.mmu->direct_map) {
6138 unsigned int indirect_shadow_pages;
6140 spin_lock(&vcpu->kvm->mmu_lock);
6141 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6142 spin_unlock(&vcpu->kvm->mmu_lock);
6144 if (indirect_shadow_pages)
6145 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6151 * if emulation was due to access to shadowed page table
6152 * and it failed try to unshadow page and re-enter the
6153 * guest to let CPU execute the instruction.
6155 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6158 * If the access faults on its page table, it can not
6159 * be fixed by unprotecting shadow page and it should
6160 * be reported to userspace.
6162 return !write_fault_to_shadow_pgtable;
6165 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6166 unsigned long cr2, int emulation_type)
6168 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6169 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6171 last_retry_eip = vcpu->arch.last_retry_eip;
6172 last_retry_addr = vcpu->arch.last_retry_addr;
6175 * If the emulation is caused by #PF and it is non-page_table
6176 * writing instruction, it means the VM-EXIT is caused by shadow
6177 * page protected, we can zap the shadow page and retry this
6178 * instruction directly.
6180 * Note: if the guest uses a non-page-table modifying instruction
6181 * on the PDE that points to the instruction, then we will unmap
6182 * the instruction and go to an infinite loop. So, we cache the
6183 * last retried eip and the last fault address, if we meet the eip
6184 * and the address again, we can break out of the potential infinite
6187 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6189 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6192 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6195 if (x86_page_table_writing_insn(ctxt))
6198 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6201 vcpu->arch.last_retry_eip = ctxt->eip;
6202 vcpu->arch.last_retry_addr = cr2;
6204 if (!vcpu->arch.mmu->direct_map)
6205 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6207 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6212 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6213 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6215 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6217 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6218 /* This is a good place to trace that we are exiting SMM. */
6219 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6221 /* Process a latched INIT or SMI, if any. */
6222 kvm_make_request(KVM_REQ_EVENT, vcpu);
6225 kvm_mmu_reset_context(vcpu);
6228 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
6230 unsigned changed = vcpu->arch.hflags ^ emul_flags;
6232 vcpu->arch.hflags = emul_flags;
6234 if (changed & HF_SMM_MASK)
6235 kvm_smm_changed(vcpu);
6238 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6247 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6248 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6253 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
6255 struct kvm_run *kvm_run = vcpu->run;
6257 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6258 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6259 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6260 kvm_run->debug.arch.exception = DB_VECTOR;
6261 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6262 *r = EMULATE_USER_EXIT;
6264 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6268 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6270 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6271 int r = EMULATE_DONE;
6273 kvm_x86_ops->skip_emulated_instruction(vcpu);
6276 * rflags is the old, "raw" value of the flags. The new value has
6277 * not been saved yet.
6279 * This is correct even for TF set by the guest, because "the
6280 * processor will not generate this exception after the instruction
6281 * that sets the TF flag".
6283 if (unlikely(rflags & X86_EFLAGS_TF))
6284 kvm_vcpu_do_singlestep(vcpu, &r);
6285 return r == EMULATE_DONE;
6287 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6289 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6291 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6292 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6293 struct kvm_run *kvm_run = vcpu->run;
6294 unsigned long eip = kvm_get_linear_rip(vcpu);
6295 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6296 vcpu->arch.guest_debug_dr7,
6300 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6301 kvm_run->debug.arch.pc = eip;
6302 kvm_run->debug.arch.exception = DB_VECTOR;
6303 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6304 *r = EMULATE_USER_EXIT;
6309 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6310 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6311 unsigned long eip = kvm_get_linear_rip(vcpu);
6312 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6317 vcpu->arch.dr6 &= ~15;
6318 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6319 kvm_queue_exception(vcpu, DB_VECTOR);
6328 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6330 switch (ctxt->opcode_len) {
6337 case 0xe6: /* OUT */
6341 case 0x6c: /* INS */
6343 case 0x6e: /* OUTS */
6350 case 0x33: /* RDPMC */
6359 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6366 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6367 bool writeback = true;
6368 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6370 vcpu->arch.l1tf_flush_l1d = true;
6373 * Clear write_fault_to_shadow_pgtable here to ensure it is
6376 vcpu->arch.write_fault_to_shadow_pgtable = false;
6377 kvm_clear_exception_queue(vcpu);
6379 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6380 init_emulate_ctxt(vcpu);
6383 * We will reenter on the same instruction since
6384 * we do not set complete_userspace_io. This does not
6385 * handle watchpoints yet, those would be handled in
6388 if (!(emulation_type & EMULTYPE_SKIP) &&
6389 kvm_vcpu_check_breakpoint(vcpu, &r))
6392 ctxt->interruptibility = 0;
6393 ctxt->have_exception = false;
6394 ctxt->exception.vector = -1;
6395 ctxt->perm_ok = false;
6397 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6399 r = x86_decode_insn(ctxt, insn, insn_len);
6401 trace_kvm_emulate_insn_start(vcpu);
6402 ++vcpu->stat.insn_emulation;
6403 if (r != EMULATION_OK) {
6404 if (emulation_type & EMULTYPE_TRAP_UD)
6405 return EMULATE_FAIL;
6406 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6408 return EMULATE_DONE;
6409 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6410 return EMULATE_DONE;
6411 if (emulation_type & EMULTYPE_SKIP)
6412 return EMULATE_FAIL;
6413 return handle_emulation_failure(vcpu, emulation_type);
6417 if ((emulation_type & EMULTYPE_VMWARE) &&
6418 !is_vmware_backdoor_opcode(ctxt))
6419 return EMULATE_FAIL;
6421 if (emulation_type & EMULTYPE_SKIP) {
6422 kvm_rip_write(vcpu, ctxt->_eip);
6423 if (ctxt->eflags & X86_EFLAGS_RF)
6424 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6425 return EMULATE_DONE;
6428 if (retry_instruction(ctxt, cr2, emulation_type))
6429 return EMULATE_DONE;
6431 /* this is needed for vmware backdoor interface to work since it
6432 changes registers values during IO operation */
6433 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6434 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6435 emulator_invalidate_register_cache(ctxt);
6439 /* Save the faulting GPA (cr2) in the address field */
6440 ctxt->exception.address = cr2;
6442 r = x86_emulate_insn(ctxt);
6444 if (r == EMULATION_INTERCEPTED)
6445 return EMULATE_DONE;
6447 if (r == EMULATION_FAILED) {
6448 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6450 return EMULATE_DONE;
6452 return handle_emulation_failure(vcpu, emulation_type);
6455 if (ctxt->have_exception) {
6457 if (inject_emulated_exception(vcpu))
6459 } else if (vcpu->arch.pio.count) {
6460 if (!vcpu->arch.pio.in) {
6461 /* FIXME: return into emulator if single-stepping. */
6462 vcpu->arch.pio.count = 0;
6465 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6467 r = EMULATE_USER_EXIT;
6468 } else if (vcpu->mmio_needed) {
6469 if (!vcpu->mmio_is_write)
6471 r = EMULATE_USER_EXIT;
6472 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6473 } else if (r == EMULATION_RESTART)
6479 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6480 toggle_interruptibility(vcpu, ctxt->interruptibility);
6481 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6482 kvm_rip_write(vcpu, ctxt->eip);
6483 if (r == EMULATE_DONE &&
6484 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6485 kvm_vcpu_do_singlestep(vcpu, &r);
6486 if (!ctxt->have_exception ||
6487 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6488 __kvm_set_rflags(vcpu, ctxt->eflags);
6491 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6492 * do nothing, and it will be requested again as soon as
6493 * the shadow expires. But we still need to check here,
6494 * because POPF has no interrupt shadow.
6496 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6497 kvm_make_request(KVM_REQ_EVENT, vcpu);
6499 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6504 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6506 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6508 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6510 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6511 void *insn, int insn_len)
6513 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6515 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6517 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6518 unsigned short port)
6520 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
6521 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6522 size, port, &val, 1);
6523 /* do not return to emulator after return from userspace */
6524 vcpu->arch.pio.count = 0;
6528 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6532 /* We should only ever be called with arch.pio.count equal to 1 */
6533 BUG_ON(vcpu->arch.pio.count != 1);
6535 /* For size less than 4 we merge, else we zero extend */
6536 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6540 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6541 * the copy and tracing
6543 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6544 vcpu->arch.pio.port, &val, 1);
6545 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6550 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6551 unsigned short port)
6556 /* For size less than 4 we merge, else we zero extend */
6557 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6559 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6562 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6566 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6571 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6573 int ret = kvm_skip_emulated_instruction(vcpu);
6576 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6577 * KVM_EXIT_DEBUG here.
6580 return kvm_fast_pio_in(vcpu, size, port) && ret;
6582 return kvm_fast_pio_out(vcpu, size, port) && ret;
6584 EXPORT_SYMBOL_GPL(kvm_fast_pio);
6586 static int kvmclock_cpu_down_prep(unsigned int cpu)
6588 __this_cpu_write(cpu_tsc_khz, 0);
6592 static void tsc_khz_changed(void *data)
6594 struct cpufreq_freqs *freq = data;
6595 unsigned long khz = 0;
6599 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6600 khz = cpufreq_quick_get(raw_smp_processor_id());
6603 __this_cpu_write(cpu_tsc_khz, khz);
6606 #ifdef CONFIG_X86_64
6607 static void kvm_hyperv_tsc_notifier(void)
6610 struct kvm_vcpu *vcpu;
6613 spin_lock(&kvm_lock);
6614 list_for_each_entry(kvm, &vm_list, vm_list)
6615 kvm_make_mclock_inprogress_request(kvm);
6617 hyperv_stop_tsc_emulation();
6619 /* TSC frequency always matches when on Hyper-V */
6620 for_each_present_cpu(cpu)
6621 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6622 kvm_max_guest_tsc_khz = tsc_khz;
6624 list_for_each_entry(kvm, &vm_list, vm_list) {
6625 struct kvm_arch *ka = &kvm->arch;
6627 spin_lock(&ka->pvclock_gtod_sync_lock);
6629 pvclock_update_vm_gtod_copy(kvm);
6631 kvm_for_each_vcpu(cpu, vcpu, kvm)
6632 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6634 kvm_for_each_vcpu(cpu, vcpu, kvm)
6635 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6637 spin_unlock(&ka->pvclock_gtod_sync_lock);
6639 spin_unlock(&kvm_lock);
6643 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6646 struct cpufreq_freqs *freq = data;
6648 struct kvm_vcpu *vcpu;
6649 int i, send_ipi = 0;
6652 * We allow guests to temporarily run on slowing clocks,
6653 * provided we notify them after, or to run on accelerating
6654 * clocks, provided we notify them before. Thus time never
6657 * However, we have a problem. We can't atomically update
6658 * the frequency of a given CPU from this function; it is
6659 * merely a notifier, which can be called from any CPU.
6660 * Changing the TSC frequency at arbitrary points in time
6661 * requires a recomputation of local variables related to
6662 * the TSC for each VCPU. We must flag these local variables
6663 * to be updated and be sure the update takes place with the
6664 * new frequency before any guests proceed.
6666 * Unfortunately, the combination of hotplug CPU and frequency
6667 * change creates an intractable locking scenario; the order
6668 * of when these callouts happen is undefined with respect to
6669 * CPU hotplug, and they can race with each other. As such,
6670 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6671 * undefined; you can actually have a CPU frequency change take
6672 * place in between the computation of X and the setting of the
6673 * variable. To protect against this problem, all updates of
6674 * the per_cpu tsc_khz variable are done in an interrupt
6675 * protected IPI, and all callers wishing to update the value
6676 * must wait for a synchronous IPI to complete (which is trivial
6677 * if the caller is on the CPU already). This establishes the
6678 * necessary total order on variable updates.
6680 * Note that because a guest time update may take place
6681 * anytime after the setting of the VCPU's request bit, the
6682 * correct TSC value must be set before the request. However,
6683 * to ensure the update actually makes it to any guest which
6684 * starts running in hardware virtualization between the set
6685 * and the acquisition of the spinlock, we must also ping the
6686 * CPU after setting the request bit.
6690 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6692 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6695 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6697 spin_lock(&kvm_lock);
6698 list_for_each_entry(kvm, &vm_list, vm_list) {
6699 kvm_for_each_vcpu(i, vcpu, kvm) {
6700 if (vcpu->cpu != freq->cpu)
6702 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6703 if (vcpu->cpu != smp_processor_id())
6707 spin_unlock(&kvm_lock);
6709 if (freq->old < freq->new && send_ipi) {
6711 * We upscale the frequency. Must make the guest
6712 * doesn't see old kvmclock values while running with
6713 * the new frequency, otherwise we risk the guest sees
6714 * time go backwards.
6716 * In case we update the frequency for another cpu
6717 * (which might be in guest context) send an interrupt
6718 * to kick the cpu out of guest context. Next time
6719 * guest context is entered kvmclock will be updated,
6720 * so the guest will not see stale values.
6722 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6727 static struct notifier_block kvmclock_cpufreq_notifier_block = {
6728 .notifier_call = kvmclock_cpufreq_notifier
6731 static int kvmclock_cpu_online(unsigned int cpu)
6733 tsc_khz_changed(NULL);
6737 static void kvm_timer_init(void)
6739 max_tsc_khz = tsc_khz;
6741 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
6742 #ifdef CONFIG_CPU_FREQ
6743 struct cpufreq_policy policy;
6746 memset(&policy, 0, sizeof(policy));
6748 cpufreq_get_policy(&policy, cpu);
6749 if (policy.cpuinfo.max_freq)
6750 max_tsc_khz = policy.cpuinfo.max_freq;
6753 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6754 CPUFREQ_TRANSITION_NOTIFIER);
6756 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
6758 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6759 kvmclock_cpu_online, kvmclock_cpu_down_prep);
6762 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6763 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
6765 int kvm_is_in_guest(void)
6767 return __this_cpu_read(current_vcpu) != NULL;
6770 static int kvm_is_user_mode(void)
6774 if (__this_cpu_read(current_vcpu))
6775 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6777 return user_mode != 0;
6780 static unsigned long kvm_get_guest_ip(void)
6782 unsigned long ip = 0;
6784 if (__this_cpu_read(current_vcpu))
6785 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6790 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6791 .is_in_guest = kvm_is_in_guest,
6792 .is_user_mode = kvm_is_user_mode,
6793 .get_guest_ip = kvm_get_guest_ip,
6796 static void kvm_set_mmio_spte_mask(void)
6799 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6802 * Set the reserved bits and the present bit of an paging-structure
6803 * entry to generate page fault with PFER.RSV = 1.
6807 * Mask the uppermost physical address bit, which would be reserved as
6808 * long as the supported physical address width is less than 52.
6812 /* Set the present bit. */
6816 * If reserved bit is not supported, clear the present bit to disable
6819 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
6822 kvm_mmu_set_mmio_spte_mask(mask, mask);
6825 #ifdef CONFIG_X86_64
6826 static void pvclock_gtod_update_fn(struct work_struct *work)
6830 struct kvm_vcpu *vcpu;
6833 spin_lock(&kvm_lock);
6834 list_for_each_entry(kvm, &vm_list, vm_list)
6835 kvm_for_each_vcpu(i, vcpu, kvm)
6836 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6837 atomic_set(&kvm_guest_has_master_clock, 0);
6838 spin_unlock(&kvm_lock);
6841 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6844 * Notification about pvclock gtod data update.
6846 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6849 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6850 struct timekeeper *tk = priv;
6852 update_pvclock_gtod(tk);
6854 /* disable master clock if host does not trust, or does not
6855 * use, TSC based clocksource.
6857 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
6858 atomic_read(&kvm_guest_has_master_clock) != 0)
6859 queue_work(system_long_wq, &pvclock_gtod_work);
6864 static struct notifier_block pvclock_gtod_notifier = {
6865 .notifier_call = pvclock_gtod_notify,
6869 int kvm_arch_init(void *opaque)
6872 struct kvm_x86_ops *ops = opaque;
6875 printk(KERN_ERR "kvm: already loaded the other module\n");
6880 if (!ops->cpu_has_kvm_support()) {
6881 printk(KERN_ERR "kvm: no hardware support\n");
6885 if (ops->disabled_by_bios()) {
6886 printk(KERN_ERR "kvm: disabled by bios\n");
6892 * KVM explicitly assumes that the guest has an FPU and
6893 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
6894 * vCPU's FPU state as a fxregs_state struct.
6896 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
6897 printk(KERN_ERR "kvm: inadequate fpu\n");
6903 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
6904 __alignof__(struct fpu), SLAB_ACCOUNT,
6906 if (!x86_fpu_cache) {
6907 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
6911 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6913 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6914 goto out_free_x86_fpu_cache;
6917 r = kvm_mmu_module_init();
6919 goto out_free_percpu;
6921 kvm_set_mmio_spte_mask();
6925 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
6926 PT_DIRTY_MASK, PT64_NX_MASK, 0,
6927 PT_PRESENT_MASK, 0, sme_me_mask);
6930 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6932 if (boot_cpu_has(X86_FEATURE_XSAVE))
6933 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6936 #ifdef CONFIG_X86_64
6937 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6939 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
6940 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
6946 free_percpu(shared_msrs);
6947 out_free_x86_fpu_cache:
6948 kmem_cache_destroy(x86_fpu_cache);
6953 void kvm_arch_exit(void)
6955 #ifdef CONFIG_X86_64
6956 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
6957 clear_hv_tscchange_cb();
6960 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6962 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6963 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6964 CPUFREQ_TRANSITION_NOTIFIER);
6965 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
6966 #ifdef CONFIG_X86_64
6967 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6970 kvm_mmu_module_exit();
6971 free_percpu(shared_msrs);
6972 kmem_cache_destroy(x86_fpu_cache);
6975 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
6977 ++vcpu->stat.halt_exits;
6978 if (lapic_in_kernel(vcpu)) {
6979 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
6982 vcpu->run->exit_reason = KVM_EXIT_HLT;
6986 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6988 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6990 int ret = kvm_skip_emulated_instruction(vcpu);
6992 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6993 * KVM_EXIT_DEBUG here.
6995 return kvm_vcpu_halt(vcpu) && ret;
6997 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6999 #ifdef CONFIG_X86_64
7000 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7001 unsigned long clock_type)
7003 struct kvm_clock_pairing clock_pairing;
7004 struct timespec64 ts;
7008 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7009 return -KVM_EOPNOTSUPP;
7011 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7012 return -KVM_EOPNOTSUPP;
7014 clock_pairing.sec = ts.tv_sec;
7015 clock_pairing.nsec = ts.tv_nsec;
7016 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7017 clock_pairing.flags = 0;
7018 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7021 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7022 sizeof(struct kvm_clock_pairing)))
7030 * kvm_pv_kick_cpu_op: Kick a vcpu.
7032 * @apicid - apicid of vcpu to be kicked.
7034 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7036 struct kvm_lapic_irq lapic_irq;
7038 lapic_irq.shorthand = 0;
7039 lapic_irq.dest_mode = 0;
7040 lapic_irq.level = 0;
7041 lapic_irq.dest_id = apicid;
7042 lapic_irq.msi_redir_hint = false;
7044 lapic_irq.delivery_mode = APIC_DM_REMRD;
7045 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7048 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7050 vcpu->arch.apicv_active = false;
7051 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7054 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7056 unsigned long nr, a0, a1, a2, a3, ret;
7059 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7060 return kvm_hv_hypercall(vcpu);
7062 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
7063 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
7064 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
7065 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
7066 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
7068 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7070 op_64_bit = is_64_bit_mode(vcpu);
7079 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7085 case KVM_HC_VAPIC_POLL_IRQ:
7088 case KVM_HC_KICK_CPU:
7089 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7092 #ifdef CONFIG_X86_64
7093 case KVM_HC_CLOCK_PAIRING:
7094 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7096 case KVM_HC_SEND_IPI:
7097 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7107 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
7109 ++vcpu->stat.hypercalls;
7110 return kvm_skip_emulated_instruction(vcpu);
7112 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7114 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7116 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7117 char instruction[3];
7118 unsigned long rip = kvm_rip_read(vcpu);
7120 kvm_x86_ops->patch_hypercall(vcpu, instruction);
7122 return emulator_write_emulated(ctxt, rip, instruction, 3,
7126 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7128 return vcpu->run->request_interrupt_window &&
7129 likely(!pic_in_kernel(vcpu->kvm));
7132 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7134 struct kvm_run *kvm_run = vcpu->run;
7136 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7137 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7138 kvm_run->cr8 = kvm_get_cr8(vcpu);
7139 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7140 kvm_run->ready_for_interrupt_injection =
7141 pic_in_kernel(vcpu->kvm) ||
7142 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7145 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7149 if (!kvm_x86_ops->update_cr8_intercept)
7152 if (!lapic_in_kernel(vcpu))
7155 if (vcpu->arch.apicv_active)
7158 if (!vcpu->arch.apic->vapic_addr)
7159 max_irr = kvm_lapic_find_highest_irr(vcpu);
7166 tpr = kvm_lapic_get_cr8(vcpu);
7168 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7171 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7175 /* try to reinject previous events if any */
7177 if (vcpu->arch.exception.injected)
7178 kvm_x86_ops->queue_exception(vcpu);
7180 * Do not inject an NMI or interrupt if there is a pending
7181 * exception. Exceptions and interrupts are recognized at
7182 * instruction boundaries, i.e. the start of an instruction.
7183 * Trap-like exceptions, e.g. #DB, have higher priority than
7184 * NMIs and interrupts, i.e. traps are recognized before an
7185 * NMI/interrupt that's pending on the same instruction.
7186 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7187 * priority, but are only generated (pended) during instruction
7188 * execution, i.e. a pending fault-like exception means the
7189 * fault occurred on the *previous* instruction and must be
7190 * serviced prior to recognizing any new events in order to
7191 * fully complete the previous instruction.
7193 else if (!vcpu->arch.exception.pending) {
7194 if (vcpu->arch.nmi_injected)
7195 kvm_x86_ops->set_nmi(vcpu);
7196 else if (vcpu->arch.interrupt.injected)
7197 kvm_x86_ops->set_irq(vcpu);
7201 * Call check_nested_events() even if we reinjected a previous event
7202 * in order for caller to determine if it should require immediate-exit
7203 * from L2 to L1 due to pending L1 events which require exit
7206 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7207 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7212 /* try to inject new event if pending */
7213 if (vcpu->arch.exception.pending) {
7214 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7215 vcpu->arch.exception.has_error_code,
7216 vcpu->arch.exception.error_code);
7218 WARN_ON_ONCE(vcpu->arch.exception.injected);
7219 vcpu->arch.exception.pending = false;
7220 vcpu->arch.exception.injected = true;
7222 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7223 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7226 if (vcpu->arch.exception.nr == DB_VECTOR) {
7228 * This code assumes that nSVM doesn't use
7229 * check_nested_events(). If it does, the
7230 * DR6/DR7 changes should happen before L1
7231 * gets a #VMEXIT for an intercepted #DB in
7232 * L2. (Under VMX, on the other hand, the
7233 * DR6/DR7 changes should not happen in the
7234 * event of a VM-exit to L1 for an intercepted
7237 kvm_deliver_exception_payload(vcpu);
7238 if (vcpu->arch.dr7 & DR7_GD) {
7239 vcpu->arch.dr7 &= ~DR7_GD;
7240 kvm_update_dr7(vcpu);
7244 kvm_x86_ops->queue_exception(vcpu);
7247 /* Don't consider new event if we re-injected an event */
7248 if (kvm_event_needs_reinjection(vcpu))
7251 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7252 kvm_x86_ops->smi_allowed(vcpu)) {
7253 vcpu->arch.smi_pending = false;
7254 ++vcpu->arch.smi_count;
7256 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7257 --vcpu->arch.nmi_pending;
7258 vcpu->arch.nmi_injected = true;
7259 kvm_x86_ops->set_nmi(vcpu);
7260 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7262 * Because interrupts can be injected asynchronously, we are
7263 * calling check_nested_events again here to avoid a race condition.
7264 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7265 * proposal and current concerns. Perhaps we should be setting
7266 * KVM_REQ_EVENT only on certain events and not unconditionally?
7268 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7269 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7273 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7274 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7276 kvm_x86_ops->set_irq(vcpu);
7283 static void process_nmi(struct kvm_vcpu *vcpu)
7288 * x86 is limited to one NMI running, and one NMI pending after it.
7289 * If an NMI is already in progress, limit further NMIs to just one.
7290 * Otherwise, allow two (and we'll inject the first one immediately).
7292 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7295 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7296 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7297 kvm_make_request(KVM_REQ_EVENT, vcpu);
7300 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7303 flags |= seg->g << 23;
7304 flags |= seg->db << 22;
7305 flags |= seg->l << 21;
7306 flags |= seg->avl << 20;
7307 flags |= seg->present << 15;
7308 flags |= seg->dpl << 13;
7309 flags |= seg->s << 12;
7310 flags |= seg->type << 8;
7314 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7316 struct kvm_segment seg;
7319 kvm_get_segment(vcpu, &seg, n);
7320 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7323 offset = 0x7f84 + n * 12;
7325 offset = 0x7f2c + (n - 3) * 12;
7327 put_smstate(u32, buf, offset + 8, seg.base);
7328 put_smstate(u32, buf, offset + 4, seg.limit);
7329 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7332 #ifdef CONFIG_X86_64
7333 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7335 struct kvm_segment seg;
7339 kvm_get_segment(vcpu, &seg, n);
7340 offset = 0x7e00 + n * 16;
7342 flags = enter_smm_get_segment_flags(&seg) >> 8;
7343 put_smstate(u16, buf, offset, seg.selector);
7344 put_smstate(u16, buf, offset + 2, flags);
7345 put_smstate(u32, buf, offset + 4, seg.limit);
7346 put_smstate(u64, buf, offset + 8, seg.base);
7350 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7353 struct kvm_segment seg;
7357 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7358 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7359 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7360 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7362 for (i = 0; i < 8; i++)
7363 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7365 kvm_get_dr(vcpu, 6, &val);
7366 put_smstate(u32, buf, 0x7fcc, (u32)val);
7367 kvm_get_dr(vcpu, 7, &val);
7368 put_smstate(u32, buf, 0x7fc8, (u32)val);
7370 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7371 put_smstate(u32, buf, 0x7fc4, seg.selector);
7372 put_smstate(u32, buf, 0x7f64, seg.base);
7373 put_smstate(u32, buf, 0x7f60, seg.limit);
7374 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7376 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7377 put_smstate(u32, buf, 0x7fc0, seg.selector);
7378 put_smstate(u32, buf, 0x7f80, seg.base);
7379 put_smstate(u32, buf, 0x7f7c, seg.limit);
7380 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7382 kvm_x86_ops->get_gdt(vcpu, &dt);
7383 put_smstate(u32, buf, 0x7f74, dt.address);
7384 put_smstate(u32, buf, 0x7f70, dt.size);
7386 kvm_x86_ops->get_idt(vcpu, &dt);
7387 put_smstate(u32, buf, 0x7f58, dt.address);
7388 put_smstate(u32, buf, 0x7f54, dt.size);
7390 for (i = 0; i < 6; i++)
7391 enter_smm_save_seg_32(vcpu, buf, i);
7393 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7396 put_smstate(u32, buf, 0x7efc, 0x00020000);
7397 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7400 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7402 #ifdef CONFIG_X86_64
7404 struct kvm_segment seg;
7408 for (i = 0; i < 16; i++)
7409 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7411 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7412 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7414 kvm_get_dr(vcpu, 6, &val);
7415 put_smstate(u64, buf, 0x7f68, val);
7416 kvm_get_dr(vcpu, 7, &val);
7417 put_smstate(u64, buf, 0x7f60, val);
7419 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7420 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7421 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7423 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7426 put_smstate(u32, buf, 0x7efc, 0x00020064);
7428 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7430 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7431 put_smstate(u16, buf, 0x7e90, seg.selector);
7432 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7433 put_smstate(u32, buf, 0x7e94, seg.limit);
7434 put_smstate(u64, buf, 0x7e98, seg.base);
7436 kvm_x86_ops->get_idt(vcpu, &dt);
7437 put_smstate(u32, buf, 0x7e84, dt.size);
7438 put_smstate(u64, buf, 0x7e88, dt.address);
7440 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7441 put_smstate(u16, buf, 0x7e70, seg.selector);
7442 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7443 put_smstate(u32, buf, 0x7e74, seg.limit);
7444 put_smstate(u64, buf, 0x7e78, seg.base);
7446 kvm_x86_ops->get_gdt(vcpu, &dt);
7447 put_smstate(u32, buf, 0x7e64, dt.size);
7448 put_smstate(u64, buf, 0x7e68, dt.address);
7450 for (i = 0; i < 6; i++)
7451 enter_smm_save_seg_64(vcpu, buf, i);
7457 static void enter_smm(struct kvm_vcpu *vcpu)
7459 struct kvm_segment cs, ds;
7464 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7465 memset(buf, 0, 512);
7466 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7467 enter_smm_save_state_64(vcpu, buf);
7469 enter_smm_save_state_32(vcpu, buf);
7472 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7473 * vCPU state (e.g. leave guest mode) after we've saved the state into
7474 * the SMM state-save area.
7476 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7478 vcpu->arch.hflags |= HF_SMM_MASK;
7479 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7481 if (kvm_x86_ops->get_nmi_mask(vcpu))
7482 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7484 kvm_x86_ops->set_nmi_mask(vcpu, true);
7486 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7487 kvm_rip_write(vcpu, 0x8000);
7489 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7490 kvm_x86_ops->set_cr0(vcpu, cr0);
7491 vcpu->arch.cr0 = cr0;
7493 kvm_x86_ops->set_cr4(vcpu, 0);
7495 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7496 dt.address = dt.size = 0;
7497 kvm_x86_ops->set_idt(vcpu, &dt);
7499 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7501 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7502 cs.base = vcpu->arch.smbase;
7507 cs.limit = ds.limit = 0xffffffff;
7508 cs.type = ds.type = 0x3;
7509 cs.dpl = ds.dpl = 0;
7514 cs.avl = ds.avl = 0;
7515 cs.present = ds.present = 1;
7516 cs.unusable = ds.unusable = 0;
7517 cs.padding = ds.padding = 0;
7519 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7520 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7521 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7522 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7523 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7524 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7526 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7527 kvm_x86_ops->set_efer(vcpu, 0);
7529 kvm_update_cpuid(vcpu);
7530 kvm_mmu_reset_context(vcpu);
7533 static void process_smi(struct kvm_vcpu *vcpu)
7535 vcpu->arch.smi_pending = true;
7536 kvm_make_request(KVM_REQ_EVENT, vcpu);
7539 void kvm_make_scan_ioapic_request(struct kvm *kvm)
7541 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7544 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
7546 if (!kvm_apic_present(vcpu))
7549 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
7551 if (irqchip_split(vcpu->kvm))
7552 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
7554 if (vcpu->arch.apicv_active)
7555 kvm_x86_ops->sync_pir_to_irr(vcpu);
7556 if (ioapic_in_kernel(vcpu->kvm))
7557 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
7560 if (is_guest_mode(vcpu))
7561 vcpu->arch.load_eoi_exitmap_pending = true;
7563 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7566 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7568 u64 eoi_exit_bitmap[4];
7570 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7573 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7574 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7575 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
7578 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7579 unsigned long start, unsigned long end,
7582 unsigned long apic_address;
7585 * The physical address of apic access page is stored in the VMCS.
7586 * Update it when it becomes invalid.
7588 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7589 if (start <= apic_address && apic_address < end)
7590 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7595 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7597 struct page *page = NULL;
7599 if (!lapic_in_kernel(vcpu))
7602 if (!kvm_x86_ops->set_apic_access_page_addr)
7605 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7606 if (is_error_page(page))
7608 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7611 * Do not pin apic access page in memory, the MMU notifier
7612 * will call us again if it is migrated or swapped out.
7616 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7618 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7620 smp_send_reschedule(vcpu->cpu);
7622 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7625 * Returns 1 to let vcpu_run() continue the guest execution loop without
7626 * exiting to the userspace. Otherwise, the value will be returned to the
7629 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
7633 dm_request_for_irq_injection(vcpu) &&
7634 kvm_cpu_accept_dm_intr(vcpu);
7636 bool req_immediate_exit = false;
7638 if (kvm_request_pending(vcpu)) {
7639 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7640 kvm_x86_ops->get_vmcs12_pages(vcpu);
7641 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
7642 kvm_mmu_unload(vcpu);
7643 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
7644 __kvm_migrate_timers(vcpu);
7645 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7646 kvm_gen_update_masterclock(vcpu->kvm);
7647 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7648 kvm_gen_kvmclock_update(vcpu);
7649 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7650 r = kvm_guest_time_update(vcpu);
7654 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
7655 kvm_mmu_sync_roots(vcpu);
7656 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7657 kvm_mmu_load_cr3(vcpu);
7658 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
7659 kvm_vcpu_flush_tlb(vcpu, true);
7660 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
7661 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
7665 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
7666 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7667 vcpu->mmio_needed = 0;
7671 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7672 /* Page is swapped out. Do synthetic halt */
7673 vcpu->arch.apf.halted = true;
7677 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7678 record_steal_time(vcpu);
7679 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7681 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7683 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7684 kvm_pmu_handle_event(vcpu);
7685 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7686 kvm_pmu_deliver_pmi(vcpu);
7687 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7688 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7689 if (test_bit(vcpu->arch.pending_ioapic_eoi,
7690 vcpu->arch.ioapic_handled_vectors)) {
7691 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7692 vcpu->run->eoi.vector =
7693 vcpu->arch.pending_ioapic_eoi;
7698 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7699 vcpu_scan_ioapic(vcpu);
7700 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7701 vcpu_load_eoi_exitmap(vcpu);
7702 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7703 kvm_vcpu_reload_apic_access_page(vcpu);
7704 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7705 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7706 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7710 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7711 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7712 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7716 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7717 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7718 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7724 * KVM_REQ_HV_STIMER has to be processed after
7725 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7726 * depend on the guest clock being up-to-date
7728 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7729 kvm_hv_process_stimers(vcpu);
7732 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
7733 ++vcpu->stat.req_event;
7734 kvm_apic_accept_events(vcpu);
7735 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7740 if (inject_pending_event(vcpu, req_int_win) != 0)
7741 req_immediate_exit = true;
7743 /* Enable SMI/NMI/IRQ window open exits if needed.
7745 * SMIs have three cases:
7746 * 1) They can be nested, and then there is nothing to
7747 * do here because RSM will cause a vmexit anyway.
7748 * 2) There is an ISA-specific reason why SMI cannot be
7749 * injected, and the moment when this changes can be
7751 * 3) Or the SMI can be pending because
7752 * inject_pending_event has completed the injection
7753 * of an IRQ or NMI from the previous vmexit, and
7754 * then we request an immediate exit to inject the
7757 if (vcpu->arch.smi_pending && !is_smm(vcpu))
7758 if (!kvm_x86_ops->enable_smi_window(vcpu))
7759 req_immediate_exit = true;
7760 if (vcpu->arch.nmi_pending)
7761 kvm_x86_ops->enable_nmi_window(vcpu);
7762 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7763 kvm_x86_ops->enable_irq_window(vcpu);
7764 WARN_ON(vcpu->arch.exception.pending);
7767 if (kvm_lapic_enabled(vcpu)) {
7768 update_cr8_intercept(vcpu);
7769 kvm_lapic_sync_to_vapic(vcpu);
7773 r = kvm_mmu_reload(vcpu);
7775 goto cancel_injection;
7780 kvm_x86_ops->prepare_guest_switch(vcpu);
7783 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7784 * IPI are then delayed after guest entry, which ensures that they
7785 * result in virtual interrupt delivery.
7787 local_irq_disable();
7788 vcpu->mode = IN_GUEST_MODE;
7790 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7793 * 1) We should set ->mode before checking ->requests. Please see
7794 * the comment in kvm_vcpu_exiting_guest_mode().
7796 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7797 * pairs with the memory barrier implicit in pi_test_and_set_on
7798 * (see vmx_deliver_posted_interrupt).
7800 * 3) This also orders the write to mode from any reads to the page
7801 * tables done while the VCPU is running. Please see the comment
7802 * in kvm_flush_remote_tlbs.
7804 smp_mb__after_srcu_read_unlock();
7807 * This handles the case where a posted interrupt was
7808 * notified with kvm_vcpu_kick.
7810 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7811 kvm_x86_ops->sync_pir_to_irr(vcpu);
7813 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
7814 || need_resched() || signal_pending(current)) {
7815 vcpu->mode = OUTSIDE_GUEST_MODE;
7819 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7821 goto cancel_injection;
7824 kvm_load_guest_xcr0(vcpu);
7826 if (req_immediate_exit) {
7827 kvm_make_request(KVM_REQ_EVENT, vcpu);
7828 kvm_x86_ops->request_immediate_exit(vcpu);
7831 trace_kvm_entry(vcpu->vcpu_id);
7832 if (lapic_timer_advance_ns)
7833 wait_lapic_expire(vcpu);
7834 guest_enter_irqoff();
7836 if (unlikely(vcpu->arch.switch_db_regs)) {
7838 set_debugreg(vcpu->arch.eff_db[0], 0);
7839 set_debugreg(vcpu->arch.eff_db[1], 1);
7840 set_debugreg(vcpu->arch.eff_db[2], 2);
7841 set_debugreg(vcpu->arch.eff_db[3], 3);
7842 set_debugreg(vcpu->arch.dr6, 6);
7843 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7846 kvm_x86_ops->run(vcpu);
7849 * Do this here before restoring debug registers on the host. And
7850 * since we do this before handling the vmexit, a DR access vmexit
7851 * can (a) read the correct value of the debug registers, (b) set
7852 * KVM_DEBUGREG_WONT_EXIT again.
7854 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
7855 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7856 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
7857 kvm_update_dr0123(vcpu);
7858 kvm_update_dr6(vcpu);
7859 kvm_update_dr7(vcpu);
7860 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7864 * If the guest has used debug registers, at least dr7
7865 * will be disabled while returning to the host.
7866 * If we don't have active breakpoints in the host, we don't
7867 * care about the messed up debug address registers. But if
7868 * we have some of them active, restore the old state.
7870 if (hw_breakpoint_active())
7871 hw_breakpoint_restore();
7873 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
7875 vcpu->mode = OUTSIDE_GUEST_MODE;
7878 kvm_put_guest_xcr0(vcpu);
7880 kvm_before_interrupt(vcpu);
7881 kvm_x86_ops->handle_external_intr(vcpu);
7882 kvm_after_interrupt(vcpu);
7886 guest_exit_irqoff();
7891 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7894 * Profile KVM exit RIPs:
7896 if (unlikely(prof_on == KVM_PROFILING)) {
7897 unsigned long rip = kvm_rip_read(vcpu);
7898 profile_hit(KVM_PROFILING, (void *)rip);
7901 if (unlikely(vcpu->arch.tsc_always_catchup))
7902 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7904 if (vcpu->arch.apic_attention)
7905 kvm_lapic_sync_from_vapic(vcpu);
7907 vcpu->arch.gpa_available = false;
7908 r = kvm_x86_ops->handle_exit(vcpu);
7912 kvm_x86_ops->cancel_injection(vcpu);
7913 if (unlikely(vcpu->arch.apic_attention))
7914 kvm_lapic_sync_from_vapic(vcpu);
7919 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7921 if (!kvm_arch_vcpu_runnable(vcpu) &&
7922 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
7923 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7924 kvm_vcpu_block(vcpu);
7925 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7927 if (kvm_x86_ops->post_block)
7928 kvm_x86_ops->post_block(vcpu);
7930 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7934 kvm_apic_accept_events(vcpu);
7935 switch(vcpu->arch.mp_state) {
7936 case KVM_MP_STATE_HALTED:
7937 vcpu->arch.pv.pv_unhalted = false;
7938 vcpu->arch.mp_state =
7939 KVM_MP_STATE_RUNNABLE;
7940 case KVM_MP_STATE_RUNNABLE:
7941 vcpu->arch.apf.halted = false;
7943 case KVM_MP_STATE_INIT_RECEIVED:
7952 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7954 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7955 kvm_x86_ops->check_nested_events(vcpu, false);
7957 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7958 !vcpu->arch.apf.halted);
7961 static int vcpu_run(struct kvm_vcpu *vcpu)
7964 struct kvm *kvm = vcpu->kvm;
7966 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7967 vcpu->arch.l1tf_flush_l1d = true;
7970 if (kvm_vcpu_running(vcpu)) {
7971 r = vcpu_enter_guest(vcpu);
7973 r = vcpu_block(kvm, vcpu);
7979 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
7980 if (kvm_cpu_has_pending_timer(vcpu))
7981 kvm_inject_pending_timer_irqs(vcpu);
7983 if (dm_request_for_irq_injection(vcpu) &&
7984 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
7986 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
7987 ++vcpu->stat.request_irq_exits;
7991 kvm_check_async_pf_completion(vcpu);
7993 if (signal_pending(current)) {
7995 vcpu->run->exit_reason = KVM_EXIT_INTR;
7996 ++vcpu->stat.signal_exits;
7999 if (need_resched()) {
8000 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8002 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8006 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8011 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8014 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8015 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8016 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8017 if (r != EMULATE_DONE)
8022 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8024 BUG_ON(!vcpu->arch.pio.count);
8026 return complete_emulated_io(vcpu);
8030 * Implements the following, as a state machine:
8034 * for each mmio piece in the fragment
8042 * for each mmio piece in the fragment
8047 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8049 struct kvm_run *run = vcpu->run;
8050 struct kvm_mmio_fragment *frag;
8053 BUG_ON(!vcpu->mmio_needed);
8055 /* Complete previous fragment */
8056 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8057 len = min(8u, frag->len);
8058 if (!vcpu->mmio_is_write)
8059 memcpy(frag->data, run->mmio.data, len);
8061 if (frag->len <= 8) {
8062 /* Switch to the next fragment. */
8064 vcpu->mmio_cur_fragment++;
8066 /* Go forward to the next mmio piece. */
8072 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8073 vcpu->mmio_needed = 0;
8075 /* FIXME: return into emulator if single-stepping. */
8076 if (vcpu->mmio_is_write)
8078 vcpu->mmio_read_completed = 1;
8079 return complete_emulated_io(vcpu);
8082 run->exit_reason = KVM_EXIT_MMIO;
8083 run->mmio.phys_addr = frag->gpa;
8084 if (vcpu->mmio_is_write)
8085 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8086 run->mmio.len = min(8u, frag->len);
8087 run->mmio.is_write = vcpu->mmio_is_write;
8088 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8092 /* Swap (qemu) user FPU context for the guest FPU context. */
8093 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8096 copy_fpregs_to_fpstate(¤t->thread.fpu);
8097 /* PKRU is separately restored in kvm_x86_ops->run. */
8098 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8099 ~XFEATURE_MASK_PKRU);
8104 /* When vcpu_run ends, restore user space FPU context. */
8105 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8108 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
8109 copy_kernel_to_fpregs(¤t->thread.fpu.state);
8111 ++vcpu->stat.fpu_reload;
8115 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8120 kvm_sigset_activate(vcpu);
8121 kvm_load_guest_fpu(vcpu);
8123 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8124 if (kvm_run->immediate_exit) {
8128 kvm_vcpu_block(vcpu);
8129 kvm_apic_accept_events(vcpu);
8130 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8132 if (signal_pending(current)) {
8134 vcpu->run->exit_reason = KVM_EXIT_INTR;
8135 ++vcpu->stat.signal_exits;
8140 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8145 if (vcpu->run->kvm_dirty_regs) {
8146 r = sync_regs(vcpu);
8151 /* re-sync apic's tpr */
8152 if (!lapic_in_kernel(vcpu)) {
8153 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8159 if (unlikely(vcpu->arch.complete_userspace_io)) {
8160 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8161 vcpu->arch.complete_userspace_io = NULL;
8166 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8168 if (kvm_run->immediate_exit)
8174 kvm_put_guest_fpu(vcpu);
8175 if (vcpu->run->kvm_valid_regs)
8177 post_kvm_run_save(vcpu);
8178 kvm_sigset_deactivate(vcpu);
8184 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8186 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8188 * We are here if userspace calls get_regs() in the middle of
8189 * instruction emulation. Registers state needs to be copied
8190 * back from emulation context to vcpu. Userspace shouldn't do
8191 * that usually, but some bad designed PV devices (vmware
8192 * backdoor interface) need this to work
8194 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8195 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8197 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
8198 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
8199 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
8200 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
8201 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
8202 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
8203 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8204 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
8205 #ifdef CONFIG_X86_64
8206 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
8207 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
8208 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
8209 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
8210 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
8211 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
8212 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
8213 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
8216 regs->rip = kvm_rip_read(vcpu);
8217 regs->rflags = kvm_get_rflags(vcpu);
8220 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8223 __get_regs(vcpu, regs);
8228 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8230 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8231 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8233 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
8234 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
8235 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
8236 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
8237 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
8238 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
8239 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
8240 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
8241 #ifdef CONFIG_X86_64
8242 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
8243 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
8244 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
8245 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
8246 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
8247 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
8248 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
8249 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
8252 kvm_rip_write(vcpu, regs->rip);
8253 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8255 vcpu->arch.exception.pending = false;
8257 kvm_make_request(KVM_REQ_EVENT, vcpu);
8260 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8263 __set_regs(vcpu, regs);
8268 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8270 struct kvm_segment cs;
8272 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8276 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8278 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8282 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8283 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8284 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8285 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8286 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8287 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8289 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8290 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8292 kvm_x86_ops->get_idt(vcpu, &dt);
8293 sregs->idt.limit = dt.size;
8294 sregs->idt.base = dt.address;
8295 kvm_x86_ops->get_gdt(vcpu, &dt);
8296 sregs->gdt.limit = dt.size;
8297 sregs->gdt.base = dt.address;
8299 sregs->cr0 = kvm_read_cr0(vcpu);
8300 sregs->cr2 = vcpu->arch.cr2;
8301 sregs->cr3 = kvm_read_cr3(vcpu);
8302 sregs->cr4 = kvm_read_cr4(vcpu);
8303 sregs->cr8 = kvm_get_cr8(vcpu);
8304 sregs->efer = vcpu->arch.efer;
8305 sregs->apic_base = kvm_get_apic_base(vcpu);
8307 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8309 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8310 set_bit(vcpu->arch.interrupt.nr,
8311 (unsigned long *)sregs->interrupt_bitmap);
8314 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8315 struct kvm_sregs *sregs)
8318 __get_sregs(vcpu, sregs);
8323 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8324 struct kvm_mp_state *mp_state)
8328 kvm_apic_accept_events(vcpu);
8329 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8330 vcpu->arch.pv.pv_unhalted)
8331 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8333 mp_state->mp_state = vcpu->arch.mp_state;
8339 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8340 struct kvm_mp_state *mp_state)
8346 if (!lapic_in_kernel(vcpu) &&
8347 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8350 /* INITs are latched while in SMM */
8351 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8352 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8353 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8356 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8357 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8358 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8360 vcpu->arch.mp_state = mp_state->mp_state;
8361 kvm_make_request(KVM_REQ_EVENT, vcpu);
8369 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8370 int reason, bool has_error_code, u32 error_code)
8372 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8375 init_emulate_ctxt(vcpu);
8377 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8378 has_error_code, error_code);
8381 return EMULATE_FAIL;
8383 kvm_rip_write(vcpu, ctxt->eip);
8384 kvm_set_rflags(vcpu, ctxt->eflags);
8385 kvm_make_request(KVM_REQ_EVENT, vcpu);
8386 return EMULATE_DONE;
8388 EXPORT_SYMBOL_GPL(kvm_task_switch);
8390 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8392 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8393 (sregs->cr4 & X86_CR4_OSXSAVE))
8396 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8398 * When EFER.LME and CR0.PG are set, the processor is in
8399 * 64-bit mode (though maybe in a 32-bit code segment).
8400 * CR4.PAE and EFER.LMA must be set.
8402 if (!(sregs->cr4 & X86_CR4_PAE)
8403 || !(sregs->efer & EFER_LMA))
8407 * Not in 64-bit mode: EFER.LMA is clear and the code
8408 * segment cannot be 64-bit.
8410 if (sregs->efer & EFER_LMA || sregs->cs.l)
8417 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8419 struct msr_data apic_base_msr;
8420 int mmu_reset_needed = 0;
8421 int cpuid_update_needed = 0;
8422 int pending_vec, max_bits, idx;
8426 if (kvm_valid_sregs(vcpu, sregs))
8429 apic_base_msr.data = sregs->apic_base;
8430 apic_base_msr.host_initiated = true;
8431 if (kvm_set_apic_base(vcpu, &apic_base_msr))
8434 dt.size = sregs->idt.limit;
8435 dt.address = sregs->idt.base;
8436 kvm_x86_ops->set_idt(vcpu, &dt);
8437 dt.size = sregs->gdt.limit;
8438 dt.address = sregs->gdt.base;
8439 kvm_x86_ops->set_gdt(vcpu, &dt);
8441 vcpu->arch.cr2 = sregs->cr2;
8442 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
8443 vcpu->arch.cr3 = sregs->cr3;
8444 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
8446 kvm_set_cr8(vcpu, sregs->cr8);
8448 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
8449 kvm_x86_ops->set_efer(vcpu, sregs->efer);
8451 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
8452 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
8453 vcpu->arch.cr0 = sregs->cr0;
8455 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
8456 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8457 (X86_CR4_OSXSAVE | X86_CR4_PKE));
8458 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
8459 if (cpuid_update_needed)
8460 kvm_update_cpuid(vcpu);
8462 idx = srcu_read_lock(&vcpu->kvm->srcu);
8463 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) {
8464 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
8465 mmu_reset_needed = 1;
8467 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8469 if (mmu_reset_needed)
8470 kvm_mmu_reset_context(vcpu);
8472 max_bits = KVM_NR_INTERRUPTS;
8473 pending_vec = find_first_bit(
8474 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8475 if (pending_vec < max_bits) {
8476 kvm_queue_interrupt(vcpu, pending_vec, false);
8477 pr_debug("Set back pending irq %d\n", pending_vec);
8480 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8481 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8482 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8483 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8484 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8485 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8487 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8488 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8490 update_cr8_intercept(vcpu);
8492 /* Older userspace won't unhalt the vcpu on reset. */
8493 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
8494 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
8496 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8498 kvm_make_request(KVM_REQ_EVENT, vcpu);
8505 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8506 struct kvm_sregs *sregs)
8511 ret = __set_sregs(vcpu, sregs);
8516 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8517 struct kvm_guest_debug *dbg)
8519 unsigned long rflags;
8524 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8526 if (vcpu->arch.exception.pending)
8528 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8529 kvm_queue_exception(vcpu, DB_VECTOR);
8531 kvm_queue_exception(vcpu, BP_VECTOR);
8535 * Read rflags as long as potentially injected trace flags are still
8538 rflags = kvm_get_rflags(vcpu);
8540 vcpu->guest_debug = dbg->control;
8541 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8542 vcpu->guest_debug = 0;
8544 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
8545 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8546 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
8547 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
8549 for (i = 0; i < KVM_NR_DB_REGS; i++)
8550 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
8552 kvm_update_dr7(vcpu);
8554 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8555 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8556 get_segment_base(vcpu, VCPU_SREG_CS);
8559 * Trigger an rflags update that will inject or remove the trace
8562 kvm_set_rflags(vcpu, rflags);
8564 kvm_x86_ops->update_bp_intercept(vcpu);
8574 * Translate a guest virtual address to a guest physical address.
8576 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8577 struct kvm_translation *tr)
8579 unsigned long vaddr = tr->linear_address;
8585 idx = srcu_read_lock(&vcpu->kvm->srcu);
8586 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
8587 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8588 tr->physical_address = gpa;
8589 tr->valid = gpa != UNMAPPED_GVA;
8597 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8599 struct fxregs_state *fxsave;
8603 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8604 memcpy(fpu->fpr, fxsave->st_space, 128);
8605 fpu->fcw = fxsave->cwd;
8606 fpu->fsw = fxsave->swd;
8607 fpu->ftwx = fxsave->twd;
8608 fpu->last_opcode = fxsave->fop;
8609 fpu->last_ip = fxsave->rip;
8610 fpu->last_dp = fxsave->rdp;
8611 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
8617 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8619 struct fxregs_state *fxsave;
8623 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8625 memcpy(fxsave->st_space, fpu->fpr, 128);
8626 fxsave->cwd = fpu->fcw;
8627 fxsave->swd = fpu->fsw;
8628 fxsave->twd = fpu->ftwx;
8629 fxsave->fop = fpu->last_opcode;
8630 fxsave->rip = fpu->last_ip;
8631 fxsave->rdp = fpu->last_dp;
8632 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
8638 static void store_regs(struct kvm_vcpu *vcpu)
8640 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8642 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8643 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8645 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8646 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8648 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8649 kvm_vcpu_ioctl_x86_get_vcpu_events(
8650 vcpu, &vcpu->run->s.regs.events);
8653 static int sync_regs(struct kvm_vcpu *vcpu)
8655 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8658 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8659 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8660 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8662 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8663 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8665 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8667 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8668 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8669 vcpu, &vcpu->run->s.regs.events))
8671 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8677 static void fx_init(struct kvm_vcpu *vcpu)
8679 fpstate_init(&vcpu->arch.guest_fpu->state);
8680 if (boot_cpu_has(X86_FEATURE_XSAVES))
8681 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
8682 host_xcr0 | XSTATE_COMPACTION_ENABLED;
8685 * Ensure guest xcr0 is valid for loading
8687 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8689 vcpu->arch.cr0 |= X86_CR0_ET;
8692 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8694 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8696 kvmclock_reset(vcpu);
8698 kvm_x86_ops->vcpu_free(vcpu);
8699 free_cpumask_var(wbinvd_dirty_mask);
8702 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8705 struct kvm_vcpu *vcpu;
8707 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
8708 printk_once(KERN_WARNING
8709 "kvm: SMP vm created on host with unstable TSC; "
8710 "guest TSC will not be reliable\n");
8712 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8717 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8719 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8720 kvm_vcpu_mtrr_init(vcpu);
8722 kvm_vcpu_reset(vcpu, false);
8723 kvm_init_mmu(vcpu, false);
8728 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
8730 struct msr_data msr;
8731 struct kvm *kvm = vcpu->kvm;
8733 kvm_hv_vcpu_postcreate(vcpu);
8735 if (mutex_lock_killable(&vcpu->mutex))
8739 msr.index = MSR_IA32_TSC;
8740 msr.host_initiated = true;
8741 kvm_write_tsc(vcpu, &msr);
8743 mutex_unlock(&vcpu->mutex);
8745 if (!kvmclock_periodic_sync)
8748 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8749 KVMCLOCK_SYNC_PERIOD);
8752 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
8754 vcpu->arch.apf.msr_val = 0;
8757 kvm_mmu_unload(vcpu);
8760 kvm_x86_ops->vcpu_free(vcpu);
8763 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
8765 kvm_lapic_reset(vcpu, init_event);
8767 vcpu->arch.hflags = 0;
8769 vcpu->arch.smi_pending = 0;
8770 vcpu->arch.smi_count = 0;
8771 atomic_set(&vcpu->arch.nmi_queued, 0);
8772 vcpu->arch.nmi_pending = 0;
8773 vcpu->arch.nmi_injected = false;
8774 kvm_clear_interrupt_queue(vcpu);
8775 kvm_clear_exception_queue(vcpu);
8776 vcpu->arch.exception.pending = false;
8778 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
8779 kvm_update_dr0123(vcpu);
8780 vcpu->arch.dr6 = DR6_INIT;
8781 kvm_update_dr6(vcpu);
8782 vcpu->arch.dr7 = DR7_FIXED_1;
8783 kvm_update_dr7(vcpu);
8787 kvm_make_request(KVM_REQ_EVENT, vcpu);
8788 vcpu->arch.apf.msr_val = 0;
8789 vcpu->arch.st.msr_val = 0;
8791 kvmclock_reset(vcpu);
8793 kvm_clear_async_pf_completion_queue(vcpu);
8794 kvm_async_pf_hash_reset(vcpu);
8795 vcpu->arch.apf.halted = false;
8797 if (kvm_mpx_supported()) {
8798 void *mpx_state_buffer;
8801 * To avoid have the INIT path from kvm_apic_has_events() that be
8802 * called with loaded FPU and does not let userspace fix the state.
8805 kvm_put_guest_fpu(vcpu);
8806 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
8807 XFEATURE_MASK_BNDREGS);
8808 if (mpx_state_buffer)
8809 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8810 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
8811 XFEATURE_MASK_BNDCSR);
8812 if (mpx_state_buffer)
8813 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
8815 kvm_load_guest_fpu(vcpu);
8819 kvm_pmu_reset(vcpu);
8820 vcpu->arch.smbase = 0x30000;
8822 vcpu->arch.msr_misc_features_enables = 0;
8824 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8827 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8828 vcpu->arch.regs_avail = ~0;
8829 vcpu->arch.regs_dirty = ~0;
8831 vcpu->arch.ia32_xss = 0;
8833 kvm_x86_ops->vcpu_reset(vcpu, init_event);
8836 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
8838 struct kvm_segment cs;
8840 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8841 cs.selector = vector << 8;
8842 cs.base = vector << 12;
8843 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8844 kvm_rip_write(vcpu, 0);
8847 int kvm_arch_hardware_enable(void)
8850 struct kvm_vcpu *vcpu;
8855 bool stable, backwards_tsc = false;
8857 kvm_shared_msr_cpu_online();
8858 ret = kvm_x86_ops->hardware_enable();
8862 local_tsc = rdtsc();
8863 stable = !kvm_check_tsc_unstable();
8864 list_for_each_entry(kvm, &vm_list, vm_list) {
8865 kvm_for_each_vcpu(i, vcpu, kvm) {
8866 if (!stable && vcpu->cpu == smp_processor_id())
8867 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8868 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8869 backwards_tsc = true;
8870 if (vcpu->arch.last_host_tsc > max_tsc)
8871 max_tsc = vcpu->arch.last_host_tsc;
8877 * Sometimes, even reliable TSCs go backwards. This happens on
8878 * platforms that reset TSC during suspend or hibernate actions, but
8879 * maintain synchronization. We must compensate. Fortunately, we can
8880 * detect that condition here, which happens early in CPU bringup,
8881 * before any KVM threads can be running. Unfortunately, we can't
8882 * bring the TSCs fully up to date with real time, as we aren't yet far
8883 * enough into CPU bringup that we know how much real time has actually
8884 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
8885 * variables that haven't been updated yet.
8887 * So we simply find the maximum observed TSC above, then record the
8888 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8889 * the adjustment will be applied. Note that we accumulate
8890 * adjustments, in case multiple suspend cycles happen before some VCPU
8891 * gets a chance to run again. In the event that no KVM threads get a
8892 * chance to run, we will miss the entire elapsed period, as we'll have
8893 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8894 * loose cycle time. This isn't too big a deal, since the loss will be
8895 * uniform across all VCPUs (not to mention the scenario is extremely
8896 * unlikely). It is possible that a second hibernate recovery happens
8897 * much faster than a first, causing the observed TSC here to be
8898 * smaller; this would require additional padding adjustment, which is
8899 * why we set last_host_tsc to the local tsc observed here.
8901 * N.B. - this code below runs only on platforms with reliable TSC,
8902 * as that is the only way backwards_tsc is set above. Also note
8903 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8904 * have the same delta_cyc adjustment applied if backwards_tsc
8905 * is detected. Note further, this adjustment is only done once,
8906 * as we reset last_host_tsc on all VCPUs to stop this from being
8907 * called multiple times (one for each physical CPU bringup).
8909 * Platforms with unreliable TSCs don't have to deal with this, they
8910 * will be compensated by the logic in vcpu_load, which sets the TSC to
8911 * catchup mode. This will catchup all VCPUs to real time, but cannot
8912 * guarantee that they stay in perfect synchronization.
8914 if (backwards_tsc) {
8915 u64 delta_cyc = max_tsc - local_tsc;
8916 list_for_each_entry(kvm, &vm_list, vm_list) {
8917 kvm->arch.backwards_tsc_observed = true;
8918 kvm_for_each_vcpu(i, vcpu, kvm) {
8919 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8920 vcpu->arch.last_host_tsc = local_tsc;
8921 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
8925 * We have to disable TSC offset matching.. if you were
8926 * booting a VM while issuing an S4 host suspend....
8927 * you may have some problem. Solving this issue is
8928 * left as an exercise to the reader.
8930 kvm->arch.last_tsc_nsec = 0;
8931 kvm->arch.last_tsc_write = 0;
8938 void kvm_arch_hardware_disable(void)
8940 kvm_x86_ops->hardware_disable();
8941 drop_user_return_notifiers();
8944 int kvm_arch_hardware_setup(void)
8948 r = kvm_x86_ops->hardware_setup();
8952 if (kvm_has_tsc_control) {
8954 * Make sure the user can only configure tsc_khz values that
8955 * fit into a signed integer.
8956 * A min value is not calculated because it will always
8957 * be 1 on all machines.
8959 u64 max = min(0x7fffffffULL,
8960 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8961 kvm_max_guest_tsc_khz = max;
8963 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
8966 kvm_init_msr_list();
8970 void kvm_arch_hardware_unsetup(void)
8972 kvm_x86_ops->hardware_unsetup();
8975 void kvm_arch_check_processor_compat(void *rtn)
8977 kvm_x86_ops->check_processor_compatibility(rtn);
8980 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8982 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8984 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8986 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8988 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
8991 struct static_key kvm_no_apic_vcpu __read_mostly;
8992 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
8994 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8999 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9000 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9001 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9002 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9004 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9006 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9011 vcpu->arch.pio_data = page_address(page);
9013 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9015 r = kvm_mmu_create(vcpu);
9017 goto fail_free_pio_data;
9019 if (irqchip_in_kernel(vcpu->kvm)) {
9020 r = kvm_create_lapic(vcpu);
9022 goto fail_mmu_destroy;
9024 static_key_slow_inc(&kvm_no_apic_vcpu);
9026 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9028 if (!vcpu->arch.mce_banks) {
9030 goto fail_free_lapic;
9032 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9034 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
9036 goto fail_free_mce_banks;
9041 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9043 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9045 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9047 kvm_async_pf_hash_reset(vcpu);
9050 vcpu->arch.pending_external_vector = -1;
9051 vcpu->arch.preempted_in_kernel = false;
9053 kvm_hv_vcpu_init(vcpu);
9057 fail_free_mce_banks:
9058 kfree(vcpu->arch.mce_banks);
9060 kvm_free_lapic(vcpu);
9062 kvm_mmu_destroy(vcpu);
9064 free_page((unsigned long)vcpu->arch.pio_data);
9069 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9073 kvm_hv_vcpu_uninit(vcpu);
9074 kvm_pmu_destroy(vcpu);
9075 kfree(vcpu->arch.mce_banks);
9076 kvm_free_lapic(vcpu);
9077 idx = srcu_read_lock(&vcpu->kvm->srcu);
9078 kvm_mmu_destroy(vcpu);
9079 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9080 free_page((unsigned long)vcpu->arch.pio_data);
9081 if (!lapic_in_kernel(vcpu))
9082 static_key_slow_dec(&kvm_no_apic_vcpu);
9085 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9087 vcpu->arch.l1tf_flush_l1d = true;
9088 kvm_x86_ops->sched_in(vcpu, cpu);
9091 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9096 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9097 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9098 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9099 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9100 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9102 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9103 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9104 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9105 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9106 &kvm->arch.irq_sources_bitmap);
9108 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9109 mutex_init(&kvm->arch.apic_map_lock);
9110 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9112 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
9113 pvclock_update_vm_gtod_copy(kvm);
9115 kvm->arch.guest_can_read_msr_platform_info = true;
9117 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9118 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9120 kvm_hv_init_vm(kvm);
9121 kvm_page_track_init(kvm);
9122 kvm_mmu_init_vm(kvm);
9124 if (kvm_x86_ops->vm_init)
9125 return kvm_x86_ops->vm_init(kvm);
9130 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9133 kvm_mmu_unload(vcpu);
9137 static void kvm_free_vcpus(struct kvm *kvm)
9140 struct kvm_vcpu *vcpu;
9143 * Unpin any mmu pages first.
9145 kvm_for_each_vcpu(i, vcpu, kvm) {
9146 kvm_clear_async_pf_completion_queue(vcpu);
9147 kvm_unload_vcpu_mmu(vcpu);
9149 kvm_for_each_vcpu(i, vcpu, kvm)
9150 kvm_arch_vcpu_free(vcpu);
9152 mutex_lock(&kvm->lock);
9153 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9154 kvm->vcpus[i] = NULL;
9156 atomic_set(&kvm->online_vcpus, 0);
9157 mutex_unlock(&kvm->lock);
9160 void kvm_arch_sync_events(struct kvm *kvm)
9162 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9163 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9167 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9171 struct kvm_memslots *slots = kvm_memslots(kvm);
9172 struct kvm_memory_slot *slot, old;
9174 /* Called with kvm->slots_lock held. */
9175 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9178 slot = id_to_memslot(slots, id);
9184 * MAP_SHARED to prevent internal slot pages from being moved
9187 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9188 MAP_SHARED | MAP_ANONYMOUS, 0);
9189 if (IS_ERR((void *)hva))
9190 return PTR_ERR((void *)hva);
9199 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9200 struct kvm_userspace_memory_region m;
9202 m.slot = id | (i << 16);
9204 m.guest_phys_addr = gpa;
9205 m.userspace_addr = hva;
9206 m.memory_size = size;
9207 r = __kvm_set_memory_region(kvm, &m);
9213 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
9217 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9219 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9223 mutex_lock(&kvm->slots_lock);
9224 r = __x86_set_memory_region(kvm, id, gpa, size);
9225 mutex_unlock(&kvm->slots_lock);
9229 EXPORT_SYMBOL_GPL(x86_set_memory_region);
9231 void kvm_arch_destroy_vm(struct kvm *kvm)
9233 if (current->mm == kvm->mm) {
9235 * Free memory regions allocated on behalf of userspace,
9236 * unless the the memory map has changed due to process exit
9239 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9240 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9241 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9243 if (kvm_x86_ops->vm_destroy)
9244 kvm_x86_ops->vm_destroy(kvm);
9245 kvm_pic_destroy(kvm);
9246 kvm_ioapic_destroy(kvm);
9247 kvm_free_vcpus(kvm);
9248 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9249 kvm_mmu_uninit_vm(kvm);
9250 kvm_page_track_cleanup(kvm);
9251 kvm_hv_destroy_vm(kvm);
9254 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
9255 struct kvm_memory_slot *dont)
9259 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9260 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
9261 kvfree(free->arch.rmap[i]);
9262 free->arch.rmap[i] = NULL;
9267 if (!dont || free->arch.lpage_info[i - 1] !=
9268 dont->arch.lpage_info[i - 1]) {
9269 kvfree(free->arch.lpage_info[i - 1]);
9270 free->arch.lpage_info[i - 1] = NULL;
9274 kvm_page_track_free_memslot(free, dont);
9277 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9278 unsigned long npages)
9282 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9283 struct kvm_lpage_info *linfo;
9288 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9289 slot->base_gfn, level) + 1;
9291 slot->arch.rmap[i] =
9292 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9294 if (!slot->arch.rmap[i])
9299 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL);
9303 slot->arch.lpage_info[i - 1] = linfo;
9305 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9306 linfo[0].disallow_lpage = 1;
9307 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9308 linfo[lpages - 1].disallow_lpage = 1;
9309 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9311 * If the gfn and userspace address are not aligned wrt each
9312 * other, or if explicitly asked to, disable large page
9313 * support for this slot
9315 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9316 !kvm_largepages_enabled()) {
9319 for (j = 0; j < lpages; ++j)
9320 linfo[j].disallow_lpage = 1;
9324 if (kvm_page_track_create_memslot(slot, npages))
9330 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9331 kvfree(slot->arch.rmap[i]);
9332 slot->arch.rmap[i] = NULL;
9336 kvfree(slot->arch.lpage_info[i - 1]);
9337 slot->arch.lpage_info[i - 1] = NULL;
9342 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
9345 * memslots->generation has been incremented.
9346 * mmio generation may have reached its maximum value.
9348 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
9351 int kvm_arch_prepare_memory_region(struct kvm *kvm,
9352 struct kvm_memory_slot *memslot,
9353 const struct kvm_userspace_memory_region *mem,
9354 enum kvm_mr_change change)
9359 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9360 struct kvm_memory_slot *new)
9362 /* Still write protect RO slot */
9363 if (new->flags & KVM_MEM_READONLY) {
9364 kvm_mmu_slot_remove_write_access(kvm, new);
9369 * Call kvm_x86_ops dirty logging hooks when they are valid.
9371 * kvm_x86_ops->slot_disable_log_dirty is called when:
9373 * - KVM_MR_CREATE with dirty logging is disabled
9374 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9376 * The reason is, in case of PML, we need to set D-bit for any slots
9377 * with dirty logging disabled in order to eliminate unnecessary GPA
9378 * logging in PML buffer (and potential PML buffer full VMEXT). This
9379 * guarantees leaving PML enabled during guest's lifetime won't have
9380 * any additional overhead from PML when guest is running with dirty
9381 * logging disabled for memory slots.
9383 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9384 * to dirty logging mode.
9386 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9388 * In case of write protect:
9390 * Write protect all pages for dirty logging.
9392 * All the sptes including the large sptes which point to this
9393 * slot are set to readonly. We can not create any new large
9394 * spte on this slot until the end of the logging.
9396 * See the comments in fast_page_fault().
9398 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9399 if (kvm_x86_ops->slot_enable_log_dirty)
9400 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9402 kvm_mmu_slot_remove_write_access(kvm, new);
9404 if (kvm_x86_ops->slot_disable_log_dirty)
9405 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9409 void kvm_arch_commit_memory_region(struct kvm *kvm,
9410 const struct kvm_userspace_memory_region *mem,
9411 const struct kvm_memory_slot *old,
9412 const struct kvm_memory_slot *new,
9413 enum kvm_mr_change change)
9415 int nr_mmu_pages = 0;
9417 if (!kvm->arch.n_requested_mmu_pages)
9418 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9421 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
9424 * Dirty logging tracks sptes in 4k granularity, meaning that large
9425 * sptes have to be split. If live migration is successful, the guest
9426 * in the source machine will be destroyed and large sptes will be
9427 * created in the destination. However, if the guest continues to run
9428 * in the source machine (for example if live migration fails), small
9429 * sptes will remain around and cause bad performance.
9431 * Scan sptes if dirty logging has been stopped, dropping those
9432 * which can be collapsed into a single large-page spte. Later
9433 * page faults will create the large-page sptes.
9435 if ((change != KVM_MR_DELETE) &&
9436 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9437 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9438 kvm_mmu_zap_collapsible_sptes(kvm, new);
9441 * Set up write protection and/or dirty logging for the new slot.
9443 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9444 * been zapped so no dirty logging staff is needed for old slot. For
9445 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9446 * new and it's also covered when dealing with the new slot.
9448 * FIXME: const-ify all uses of struct kvm_memory_slot.
9450 if (change != KVM_MR_DELETE)
9451 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
9454 void kvm_arch_flush_shadow_all(struct kvm *kvm)
9456 kvm_mmu_invalidate_zap_all_pages(kvm);
9459 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9460 struct kvm_memory_slot *slot)
9462 kvm_page_track_flush_slot(kvm, slot);
9465 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9467 return (is_guest_mode(vcpu) &&
9468 kvm_x86_ops->guest_apic_has_interrupt &&
9469 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9472 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9474 if (!list_empty_careful(&vcpu->async_pf.done))
9477 if (kvm_apic_has_events(vcpu))
9480 if (vcpu->arch.pv.pv_unhalted)
9483 if (vcpu->arch.exception.pending)
9486 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9487 (vcpu->arch.nmi_pending &&
9488 kvm_x86_ops->nmi_allowed(vcpu)))
9491 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9492 (vcpu->arch.smi_pending && !is_smm(vcpu)))
9495 if (kvm_arch_interrupt_allowed(vcpu) &&
9496 (kvm_cpu_has_interrupt(vcpu) ||
9497 kvm_guest_apic_has_interrupt(vcpu)))
9500 if (kvm_hv_has_stimer_pending(vcpu))
9506 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9508 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
9511 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9513 return vcpu->arch.preempted_in_kernel;
9516 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
9518 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
9521 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9523 return kvm_x86_ops->interrupt_allowed(vcpu);
9526 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
9528 if (is_64_bit_mode(vcpu))
9529 return kvm_rip_read(vcpu);
9530 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9531 kvm_rip_read(vcpu));
9533 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
9535 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9537 return kvm_get_linear_rip(vcpu) == linear_rip;
9539 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9541 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9543 unsigned long rflags;
9545 rflags = kvm_x86_ops->get_rflags(vcpu);
9546 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9547 rflags &= ~X86_EFLAGS_TF;
9550 EXPORT_SYMBOL_GPL(kvm_get_rflags);
9552 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9554 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
9555 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
9556 rflags |= X86_EFLAGS_TF;
9557 kvm_x86_ops->set_rflags(vcpu, rflags);
9560 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9562 __kvm_set_rflags(vcpu, rflags);
9563 kvm_make_request(KVM_REQ_EVENT, vcpu);
9565 EXPORT_SYMBOL_GPL(kvm_set_rflags);
9567 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9571 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
9575 r = kvm_mmu_reload(vcpu);
9579 if (!vcpu->arch.mmu->direct_map &&
9580 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
9583 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
9586 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9588 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9591 static inline u32 kvm_async_pf_next_probe(u32 key)
9593 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9596 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9598 u32 key = kvm_async_pf_hash_fn(gfn);
9600 while (vcpu->arch.apf.gfns[key] != ~0)
9601 key = kvm_async_pf_next_probe(key);
9603 vcpu->arch.apf.gfns[key] = gfn;
9606 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9609 u32 key = kvm_async_pf_hash_fn(gfn);
9611 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
9612 (vcpu->arch.apf.gfns[key] != gfn &&
9613 vcpu->arch.apf.gfns[key] != ~0); i++)
9614 key = kvm_async_pf_next_probe(key);
9619 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9621 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9624 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9628 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9630 vcpu->arch.apf.gfns[i] = ~0;
9632 j = kvm_async_pf_next_probe(j);
9633 if (vcpu->arch.apf.gfns[j] == ~0)
9635 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9637 * k lies cyclically in ]i,j]
9639 * |....j i.k.| or |.k..j i...|
9641 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9642 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9647 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9650 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9654 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9657 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9661 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9662 struct kvm_async_pf *work)
9664 struct x86_exception fault;
9666 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
9667 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
9669 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
9670 (vcpu->arch.apf.send_user_only &&
9671 kvm_x86_ops->get_cpl(vcpu) == 0))
9672 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9673 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
9674 fault.vector = PF_VECTOR;
9675 fault.error_code_valid = true;
9676 fault.error_code = 0;
9677 fault.nested_page_fault = false;
9678 fault.address = work->arch.token;
9679 fault.async_page_fault = true;
9680 kvm_inject_page_fault(vcpu, &fault);
9684 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9685 struct kvm_async_pf *work)
9687 struct x86_exception fault;
9690 if (work->wakeup_all)
9691 work->arch.token = ~0; /* broadcast wakeup */
9693 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
9694 trace_kvm_async_pf_ready(work->arch.token, work->gva);
9696 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9697 !apf_get_user(vcpu, &val)) {
9698 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9699 vcpu->arch.exception.pending &&
9700 vcpu->arch.exception.nr == PF_VECTOR &&
9701 !apf_put_user(vcpu, 0)) {
9702 vcpu->arch.exception.injected = false;
9703 vcpu->arch.exception.pending = false;
9704 vcpu->arch.exception.nr = 0;
9705 vcpu->arch.exception.has_error_code = false;
9706 vcpu->arch.exception.error_code = 0;
9707 vcpu->arch.exception.has_payload = false;
9708 vcpu->arch.exception.payload = 0;
9709 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9710 fault.vector = PF_VECTOR;
9711 fault.error_code_valid = true;
9712 fault.error_code = 0;
9713 fault.nested_page_fault = false;
9714 fault.address = work->arch.token;
9715 fault.async_page_fault = true;
9716 kvm_inject_page_fault(vcpu, &fault);
9719 vcpu->arch.apf.halted = false;
9720 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9723 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9725 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9728 return kvm_can_do_async_pf(vcpu);
9731 void kvm_arch_start_assignment(struct kvm *kvm)
9733 atomic_inc(&kvm->arch.assigned_device_count);
9735 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9737 void kvm_arch_end_assignment(struct kvm *kvm)
9739 atomic_dec(&kvm->arch.assigned_device_count);
9741 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9743 bool kvm_arch_has_assigned_device(struct kvm *kvm)
9745 return atomic_read(&kvm->arch.assigned_device_count);
9747 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9749 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9751 atomic_inc(&kvm->arch.noncoherent_dma_count);
9753 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9755 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9757 atomic_dec(&kvm->arch.noncoherent_dma_count);
9759 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9761 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9763 return atomic_read(&kvm->arch.noncoherent_dma_count);
9765 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9767 bool kvm_arch_has_irq_bypass(void)
9769 return kvm_x86_ops->update_pi_irte != NULL;
9772 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9773 struct irq_bypass_producer *prod)
9775 struct kvm_kernel_irqfd *irqfd =
9776 container_of(cons, struct kvm_kernel_irqfd, consumer);
9778 irqfd->producer = prod;
9780 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9781 prod->irq, irqfd->gsi, 1);
9784 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9785 struct irq_bypass_producer *prod)
9788 struct kvm_kernel_irqfd *irqfd =
9789 container_of(cons, struct kvm_kernel_irqfd, consumer);
9791 WARN_ON(irqfd->producer != prod);
9792 irqfd->producer = NULL;
9795 * When producer of consumer is unregistered, we change back to
9796 * remapped mode, so we can re-use the current implementation
9797 * when the irq is masked/disabled or the consumer side (KVM
9798 * int this case doesn't want to receive the interrupts.
9800 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9802 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9803 " fails: %d\n", irqfd->consumer.token, ret);
9806 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9807 uint32_t guest_irq, bool set)
9809 if (!kvm_x86_ops->update_pi_irte)
9812 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9815 bool kvm_vector_hashing_enabled(void)
9817 return vector_hashing;
9819 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9821 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
9822 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
9823 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9824 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9825 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9826 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
9827 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
9828 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
9829 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
9830 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
9831 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
9832 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
9833 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
9834 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
9835 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
9836 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
9837 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
9838 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9839 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);