arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/frame.h>
  37 #include <linux/nospec.h>
  38 #include "kvm_cache_regs.h"
  39 #include "x86.h"
  40
  41 #include <asm/cpu.h>
  42 #include <asm/io.h>
  43 #include <asm/desc.h>
  44 #include <asm/vmx.h>
  45 #include <asm/virtext.h>
  46 #include <asm/mce.h>
  47 #include <asm/fpu/internal.h>
  48 #include <asm/perf_event.h>
  49 #include <asm/debugreg.h>
  50 #include <asm/kexec.h>
  51 #include <asm/apic.h>
  52 #include <asm/irq_remapping.h>
  53 #include <asm/mmu_context.h>
  54 #include <asm/nospec-branch.h>
  55 #include <asm/mshyperv.h>
  56
  57 #include "trace.h"
  58 #include "pmu.h"
  59 #include "vmx_evmcs.h"
  60
  61 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  62 #define __ex_clear(x, reg) \
  63         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  64
  65 MODULE_AUTHOR("Qumranet");
  66 MODULE_LICENSE("GPL");
  67
  68 static const struct x86_cpu_id vmx_cpu_id[] = {
  69         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  70         {}
  71 };
  72 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  73
  74 static bool __read_mostly enable_vpid = 1;
  75 module_param_named(vpid, enable_vpid, bool, 0444);
  76
  77 static bool __read_mostly enable_vnmi = 1;
  78 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  79
  80 static bool __read_mostly flexpriority_enabled = 1;
  81 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  82
  83 static bool __read_mostly enable_ept = 1;
  84 module_param_named(ept, enable_ept, bool, S_IRUGO);
  85
  86 static bool __read_mostly enable_unrestricted_guest = 1;
  87 module_param_named(unrestricted_guest,
  88                         enable_unrestricted_guest, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_ept_ad_bits = 1;
  91 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  92
  93 static bool __read_mostly emulate_invalid_guest_state = true;
  94 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  95
  96 static bool __read_mostly fasteoi = 1;
  97 module_param(fasteoi, bool, S_IRUGO);
  98
  99 static bool __read_mostly enable_apicv = 1;
 100 module_param(enable_apicv, bool, S_IRUGO);
 101
 102 static bool __read_mostly enable_shadow_vmcs = 1;
 103 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
 104 /*
 105  * If nested=1, nested virtualization is supported, i.e., guests may use
 106  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 107  * use VMX instructions.
 108  */
 109 static bool __read_mostly nested = 0;
 110 module_param(nested, bool, S_IRUGO);
 111
 112 static u64 __read_mostly host_xss;
 113
 114 static bool __read_mostly enable_pml = 1;
 115 module_param_named(pml, enable_pml, bool, S_IRUGO);
 116
 117 #define MSR_TYPE_R      1
 118 #define MSR_TYPE_W      2
 119 #define MSR_TYPE_RW     3
 120
 121 #define MSR_BITMAP_MODE_X2APIC          1
 122 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 123 #define MSR_BITMAP_MODE_LM              4
 124
 125 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 126
 127 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 128 static int __read_mostly cpu_preemption_timer_multi;
 129 static bool __read_mostly enable_preemption_timer = 1;
 130 #ifdef CONFIG_X86_64
 131 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 132 #endif
 133
 134 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 135 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 136 #define KVM_VM_CR0_ALWAYS_ON                            \
 137         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 138          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 139 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 140         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 141          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 142
 143 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 144 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 145 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 146
 147 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 148
 149 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 150
 151 /*
 152  * Hyper-V requires all of these, so mark them as supported even though
 153  * they are just treated the same as all-context.
 154  */
 155 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 156         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 157         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 158         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 159         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 160
 161 /*
 162  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 163  * ple_gap:    upper bound on the amount of time between two successive
 164  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 165  *             According to test, this time is usually smaller than 128 cycles.
 166  * ple_window: upper bound on the amount of time a guest is allowed to execute
 167  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 168  *             less than 2^12 cycles
 169  * Time is measured based on a counter that runs at the same rate as the TSC,
 170  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 171  */
 172 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 173
 174 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 175 module_param(ple_window, uint, 0444);
 176
 177 /* Default doubles per-vcpu window every exit. */
 178 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 179 module_param(ple_window_grow, uint, 0444);
 180
 181 /* Default resets per-vcpu window every exit to ple_window. */
 182 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 183 module_param(ple_window_shrink, uint, 0444);
 184
 185 /* Default is to compute the maximum so we can never overflow. */
 186 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 187 module_param(ple_window_max, uint, 0444);
 188
 189 extern const ulong vmx_return;
 190
 191 struct kvm_vmx {
 192         struct kvm kvm;
 193
 194         unsigned int tss_addr;
 195         bool ept_identity_pagetable_done;
 196         gpa_t ept_identity_map_addr;
 197 };
 198
 199 #define NR_AUTOLOAD_MSRS 8
 200
 201 struct vmcs {
 202         u32 revision_id;
 203         u32 abort;
 204         char data[0];
 205 };
 206
 207 /*
 208  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 209  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 210  * loaded on this CPU (so we can clear them if the CPU goes down).
 211  */
 212 struct loaded_vmcs {
 213         struct vmcs *vmcs;
 214         struct vmcs *shadow_vmcs;
 215         int cpu;
 216         bool launched;
 217         bool nmi_known_unmasked;
 218         unsigned long vmcs_host_cr3;    /* May not match real cr3 */
 219         unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 220         /* Support for vnmi-less CPUs */
 221         int soft_vnmi_blocked;
 222         ktime_t entry_time;
 223         s64 vnmi_blocked_time;
 224         unsigned long *msr_bitmap;
 225         struct list_head loaded_vmcss_on_cpu_link;
 226 };
 227
 228 struct shared_msr_entry {
 229         unsigned index;
 230         u64 data;
 231         u64 mask;
 232 };
 233
 234 /*
 235  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 236  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 237  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 238  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 239  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 240  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 241  * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
 242  * underlying hardware which will be used to run L2.
 243  * This structure is packed to ensure that its layout is identical across
 244  * machines (necessary for live migration).
 245  *
 246  * IMPORTANT: Changing the layout of existing fields in this structure
 247  * will break save/restore compatibility with older kvm releases. When
 248  * adding new fields, either use space in the reserved padding* arrays
 249  * or add the new fields to the end of the structure.
 250  */
 251 typedef u64 natural_width;
 252 struct __packed vmcs12 {
 253         /* According to the Intel spec, a VMCS region must start with the
 254          * following two fields. Then follow implementation-specific data.
 255          */
 256         u32 revision_id;
 257         u32 abort;
 258
 259         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 260         u32 padding[7]; /* room for future expansion */
 261
 262         u64 io_bitmap_a;
 263         u64 io_bitmap_b;
 264         u64 msr_bitmap;
 265         u64 vm_exit_msr_store_addr;
 266         u64 vm_exit_msr_load_addr;
 267         u64 vm_entry_msr_load_addr;
 268         u64 tsc_offset;
 269         u64 virtual_apic_page_addr;
 270         u64 apic_access_addr;
 271         u64 posted_intr_desc_addr;
 272         u64 ept_pointer;
 273         u64 eoi_exit_bitmap0;
 274         u64 eoi_exit_bitmap1;
 275         u64 eoi_exit_bitmap2;
 276         u64 eoi_exit_bitmap3;
 277         u64 xss_exit_bitmap;
 278         u64 guest_physical_address;
 279         u64 vmcs_link_pointer;
 280         u64 guest_ia32_debugctl;
 281         u64 guest_ia32_pat;
 282         u64 guest_ia32_efer;
 283         u64 guest_ia32_perf_global_ctrl;
 284         u64 guest_pdptr0;
 285         u64 guest_pdptr1;
 286         u64 guest_pdptr2;
 287         u64 guest_pdptr3;
 288         u64 guest_bndcfgs;
 289         u64 host_ia32_pat;
 290         u64 host_ia32_efer;
 291         u64 host_ia32_perf_global_ctrl;
 292         u64 vmread_bitmap;
 293         u64 vmwrite_bitmap;
 294         u64 vm_function_control;
 295         u64 eptp_list_address;
 296         u64 pml_address;
 297         u64 padding64[3]; /* room for future expansion */
 298         /*
 299          * To allow migration of L1 (complete with its L2 guests) between
 300          * machines of different natural widths (32 or 64 bit), we cannot have
 301          * unsigned long fields with no explict size. We use u64 (aliased
 302          * natural_width) instead. Luckily, x86 is little-endian.
 303          */
 304         natural_width cr0_guest_host_mask;
 305         natural_width cr4_guest_host_mask;
 306         natural_width cr0_read_shadow;
 307         natural_width cr4_read_shadow;
 308         natural_width cr3_target_value0;
 309         natural_width cr3_target_value1;
 310         natural_width cr3_target_value2;
 311         natural_width cr3_target_value3;
 312         natural_width exit_qualification;
 313         natural_width guest_linear_address;
 314         natural_width guest_cr0;
 315         natural_width guest_cr3;
 316         natural_width guest_cr4;
 317         natural_width guest_es_base;
 318         natural_width guest_cs_base;
 319         natural_width guest_ss_base;
 320         natural_width guest_ds_base;
 321         natural_width guest_fs_base;
 322         natural_width guest_gs_base;
 323         natural_width guest_ldtr_base;
 324         natural_width guest_tr_base;
 325         natural_width guest_gdtr_base;
 326         natural_width guest_idtr_base;
 327         natural_width guest_dr7;
 328         natural_width guest_rsp;
 329         natural_width guest_rip;
 330         natural_width guest_rflags;
 331         natural_width guest_pending_dbg_exceptions;
 332         natural_width guest_sysenter_esp;
 333         natural_width guest_sysenter_eip;
 334         natural_width host_cr0;
 335         natural_width host_cr3;
 336         natural_width host_cr4;
 337         natural_width host_fs_base;
 338         natural_width host_gs_base;
 339         natural_width host_tr_base;
 340         natural_width host_gdtr_base;
 341         natural_width host_idtr_base;
 342         natural_width host_ia32_sysenter_esp;
 343         natural_width host_ia32_sysenter_eip;
 344         natural_width host_rsp;
 345         natural_width host_rip;
 346         natural_width paddingl[8]; /* room for future expansion */
 347         u32 pin_based_vm_exec_control;
 348         u32 cpu_based_vm_exec_control;
 349         u32 exception_bitmap;
 350         u32 page_fault_error_code_mask;
 351         u32 page_fault_error_code_match;
 352         u32 cr3_target_count;
 353         u32 vm_exit_controls;
 354         u32 vm_exit_msr_store_count;
 355         u32 vm_exit_msr_load_count;
 356         u32 vm_entry_controls;
 357         u32 vm_entry_msr_load_count;
 358         u32 vm_entry_intr_info_field;
 359         u32 vm_entry_exception_error_code;
 360         u32 vm_entry_instruction_len;
 361         u32 tpr_threshold;
 362         u32 secondary_vm_exec_control;
 363         u32 vm_instruction_error;
 364         u32 vm_exit_reason;
 365         u32 vm_exit_intr_info;
 366         u32 vm_exit_intr_error_code;
 367         u32 idt_vectoring_info_field;
 368         u32 idt_vectoring_error_code;
 369         u32 vm_exit_instruction_len;
 370         u32 vmx_instruction_info;
 371         u32 guest_es_limit;
 372         u32 guest_cs_limit;
 373         u32 guest_ss_limit;
 374         u32 guest_ds_limit;
 375         u32 guest_fs_limit;
 376         u32 guest_gs_limit;
 377         u32 guest_ldtr_limit;
 378         u32 guest_tr_limit;
 379         u32 guest_gdtr_limit;
 380         u32 guest_idtr_limit;
 381         u32 guest_es_ar_bytes;
 382         u32 guest_cs_ar_bytes;
 383         u32 guest_ss_ar_bytes;
 384         u32 guest_ds_ar_bytes;
 385         u32 guest_fs_ar_bytes;
 386         u32 guest_gs_ar_bytes;
 387         u32 guest_ldtr_ar_bytes;
 388         u32 guest_tr_ar_bytes;
 389         u32 guest_interruptibility_info;
 390         u32 guest_activity_state;
 391         u32 guest_sysenter_cs;
 392         u32 host_ia32_sysenter_cs;
 393         u32 vmx_preemption_timer_value;
 394         u32 padding32[7]; /* room for future expansion */
 395         u16 virtual_processor_id;
 396         u16 posted_intr_nv;
 397         u16 guest_es_selector;
 398         u16 guest_cs_selector;
 399         u16 guest_ss_selector;
 400         u16 guest_ds_selector;
 401         u16 guest_fs_selector;
 402         u16 guest_gs_selector;
 403         u16 guest_ldtr_selector;
 404         u16 guest_tr_selector;
 405         u16 guest_intr_status;
 406         u16 host_es_selector;
 407         u16 host_cs_selector;
 408         u16 host_ss_selector;
 409         u16 host_ds_selector;
 410         u16 host_fs_selector;
 411         u16 host_gs_selector;
 412         u16 host_tr_selector;
 413         u16 guest_pml_index;
 414 };
 415
 416 /*
 417  * For save/restore compatibility, the vmcs12 field offsets must not change.
 418  */
 419 #define CHECK_OFFSET(field, loc)                                \
 420         BUILD_BUG_ON_MSG(offsetof(struct vmcs12, field) != (loc),       \
 421                 "Offset of " #field " in struct vmcs12 has changed.")
 422
 423 static inline void vmx_check_vmcs12_offsets(void) {
 424         CHECK_OFFSET(revision_id, 0);
 425         CHECK_OFFSET(abort, 4);
 426         CHECK_OFFSET(launch_state, 8);
 427         CHECK_OFFSET(io_bitmap_a, 40);
 428         CHECK_OFFSET(io_bitmap_b, 48);
 429         CHECK_OFFSET(msr_bitmap, 56);
 430         CHECK_OFFSET(vm_exit_msr_store_addr, 64);
 431         CHECK_OFFSET(vm_exit_msr_load_addr, 72);
 432         CHECK_OFFSET(vm_entry_msr_load_addr, 80);
 433         CHECK_OFFSET(tsc_offset, 88);
 434         CHECK_OFFSET(virtual_apic_page_addr, 96);
 435         CHECK_OFFSET(apic_access_addr, 104);
 436         CHECK_OFFSET(posted_intr_desc_addr, 112);
 437         CHECK_OFFSET(ept_pointer, 120);
 438         CHECK_OFFSET(eoi_exit_bitmap0, 128);
 439         CHECK_OFFSET(eoi_exit_bitmap1, 136);
 440         CHECK_OFFSET(eoi_exit_bitmap2, 144);
 441         CHECK_OFFSET(eoi_exit_bitmap3, 152);
 442         CHECK_OFFSET(xss_exit_bitmap, 160);
 443         CHECK_OFFSET(guest_physical_address, 168);
 444         CHECK_OFFSET(vmcs_link_pointer, 176);
 445         CHECK_OFFSET(guest_ia32_debugctl, 184);
 446         CHECK_OFFSET(guest_ia32_pat, 192);
 447         CHECK_OFFSET(guest_ia32_efer, 200);
 448         CHECK_OFFSET(guest_ia32_perf_global_ctrl, 208);
 449         CHECK_OFFSET(guest_pdptr0, 216);
 450         CHECK_OFFSET(guest_pdptr1, 224);
 451         CHECK_OFFSET(guest_pdptr2, 232);
 452         CHECK_OFFSET(guest_pdptr3, 240);
 453         CHECK_OFFSET(guest_bndcfgs, 248);
 454         CHECK_OFFSET(host_ia32_pat, 256);
 455         CHECK_OFFSET(host_ia32_efer, 264);
 456         CHECK_OFFSET(host_ia32_perf_global_ctrl, 272);
 457         CHECK_OFFSET(vmread_bitmap, 280);
 458         CHECK_OFFSET(vmwrite_bitmap, 288);
 459         CHECK_OFFSET(vm_function_control, 296);
 460         CHECK_OFFSET(eptp_list_address, 304);
 461         CHECK_OFFSET(pml_address, 312);
 462         CHECK_OFFSET(cr0_guest_host_mask, 344);
 463         CHECK_OFFSET(cr4_guest_host_mask, 352);
 464         CHECK_OFFSET(cr0_read_shadow, 360);
 465         CHECK_OFFSET(cr4_read_shadow, 368);
 466         CHECK_OFFSET(cr3_target_value0, 376);
 467         CHECK_OFFSET(cr3_target_value1, 384);
 468         CHECK_OFFSET(cr3_target_value2, 392);
 469         CHECK_OFFSET(cr3_target_value3, 400);
 470         CHECK_OFFSET(exit_qualification, 408);
 471         CHECK_OFFSET(guest_linear_address, 416);
 472         CHECK_OFFSET(guest_cr0, 424);
 473         CHECK_OFFSET(guest_cr3, 432);
 474         CHECK_OFFSET(guest_cr4, 440);
 475         CHECK_OFFSET(guest_es_base, 448);
 476         CHECK_OFFSET(guest_cs_base, 456);
 477         CHECK_OFFSET(guest_ss_base, 464);
 478         CHECK_OFFSET(guest_ds_base, 472);
 479         CHECK_OFFSET(guest_fs_base, 480);
 480         CHECK_OFFSET(guest_gs_base, 488);
 481         CHECK_OFFSET(guest_ldtr_base, 496);
 482         CHECK_OFFSET(guest_tr_base, 504);
 483         CHECK_OFFSET(guest_gdtr_base, 512);
 484         CHECK_OFFSET(guest_idtr_base, 520);
 485         CHECK_OFFSET(guest_dr7, 528);
 486         CHECK_OFFSET(guest_rsp, 536);
 487         CHECK_OFFSET(guest_rip, 544);
 488         CHECK_OFFSET(guest_rflags, 552);
 489         CHECK_OFFSET(guest_pending_dbg_exceptions, 560);
 490         CHECK_OFFSET(guest_sysenter_esp, 568);
 491         CHECK_OFFSET(guest_sysenter_eip, 576);
 492         CHECK_OFFSET(host_cr0, 584);
 493         CHECK_OFFSET(host_cr3, 592);
 494         CHECK_OFFSET(host_cr4, 600);
 495         CHECK_OFFSET(host_fs_base, 608);
 496         CHECK_OFFSET(host_gs_base, 616);
 497         CHECK_OFFSET(host_tr_base, 624);
 498         CHECK_OFFSET(host_gdtr_base, 632);
 499         CHECK_OFFSET(host_idtr_base, 640);
 500         CHECK_OFFSET(host_ia32_sysenter_esp, 648);
 501         CHECK_OFFSET(host_ia32_sysenter_eip, 656);
 502         CHECK_OFFSET(host_rsp, 664);
 503         CHECK_OFFSET(host_rip, 672);
 504         CHECK_OFFSET(pin_based_vm_exec_control, 744);
 505         CHECK_OFFSET(cpu_based_vm_exec_control, 748);
 506         CHECK_OFFSET(exception_bitmap, 752);
 507         CHECK_OFFSET(page_fault_error_code_mask, 756);
 508         CHECK_OFFSET(page_fault_error_code_match, 760);
 509         CHECK_OFFSET(cr3_target_count, 764);
 510         CHECK_OFFSET(vm_exit_controls, 768);
 511         CHECK_OFFSET(vm_exit_msr_store_count, 772);
 512         CHECK_OFFSET(vm_exit_msr_load_count, 776);
 513         CHECK_OFFSET(vm_entry_controls, 780);
 514         CHECK_OFFSET(vm_entry_msr_load_count, 784);
 515         CHECK_OFFSET(vm_entry_intr_info_field, 788);
 516         CHECK_OFFSET(vm_entry_exception_error_code, 792);
 517         CHECK_OFFSET(vm_entry_instruction_len, 796);
 518         CHECK_OFFSET(tpr_threshold, 800);
 519         CHECK_OFFSET(secondary_vm_exec_control, 804);
 520         CHECK_OFFSET(vm_instruction_error, 808);
 521         CHECK_OFFSET(vm_exit_reason, 812);
 522         CHECK_OFFSET(vm_exit_intr_info, 816);
 523         CHECK_OFFSET(vm_exit_intr_error_code, 820);
 524         CHECK_OFFSET(idt_vectoring_info_field, 824);
 525         CHECK_OFFSET(idt_vectoring_error_code, 828);
 526         CHECK_OFFSET(vm_exit_instruction_len, 832);
 527         CHECK_OFFSET(vmx_instruction_info, 836);
 528         CHECK_OFFSET(guest_es_limit, 840);
 529         CHECK_OFFSET(guest_cs_limit, 844);
 530         CHECK_OFFSET(guest_ss_limit, 848);
 531         CHECK_OFFSET(guest_ds_limit, 852);
 532         CHECK_OFFSET(guest_fs_limit, 856);
 533         CHECK_OFFSET(guest_gs_limit, 860);
 534         CHECK_OFFSET(guest_ldtr_limit, 864);
 535         CHECK_OFFSET(guest_tr_limit, 868);
 536         CHECK_OFFSET(guest_gdtr_limit, 872);
 537         CHECK_OFFSET(guest_idtr_limit, 876);
 538         CHECK_OFFSET(guest_es_ar_bytes, 880);
 539         CHECK_OFFSET(guest_cs_ar_bytes, 884);
 540         CHECK_OFFSET(guest_ss_ar_bytes, 888);
 541         CHECK_OFFSET(guest_ds_ar_bytes, 892);
 542         CHECK_OFFSET(guest_fs_ar_bytes, 896);
 543         CHECK_OFFSET(guest_gs_ar_bytes, 900);
 544         CHECK_OFFSET(guest_ldtr_ar_bytes, 904);
 545         CHECK_OFFSET(guest_tr_ar_bytes, 908);
 546         CHECK_OFFSET(guest_interruptibility_info, 912);
 547         CHECK_OFFSET(guest_activity_state, 916);
 548         CHECK_OFFSET(guest_sysenter_cs, 920);
 549         CHECK_OFFSET(host_ia32_sysenter_cs, 924);
 550         CHECK_OFFSET(vmx_preemption_timer_value, 928);
 551         CHECK_OFFSET(virtual_processor_id, 960);
 552         CHECK_OFFSET(posted_intr_nv, 962);
 553         CHECK_OFFSET(guest_es_selector, 964);
 554         CHECK_OFFSET(guest_cs_selector, 966);
 555         CHECK_OFFSET(guest_ss_selector, 968);
 556         CHECK_OFFSET(guest_ds_selector, 970);
 557         CHECK_OFFSET(guest_fs_selector, 972);
 558         CHECK_OFFSET(guest_gs_selector, 974);
 559         CHECK_OFFSET(guest_ldtr_selector, 976);
 560         CHECK_OFFSET(guest_tr_selector, 978);
 561         CHECK_OFFSET(guest_intr_status, 980);
 562         CHECK_OFFSET(host_es_selector, 982);
 563         CHECK_OFFSET(host_cs_selector, 984);
 564         CHECK_OFFSET(host_ss_selector, 986);
 565         CHECK_OFFSET(host_ds_selector, 988);
 566         CHECK_OFFSET(host_fs_selector, 990);
 567         CHECK_OFFSET(host_gs_selector, 992);
 568         CHECK_OFFSET(host_tr_selector, 994);
 569         CHECK_OFFSET(guest_pml_index, 996);
 570 }
 571
 572 /*
 573  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 574  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 575  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 576  *
 577  * IMPORTANT: Changing this value will break save/restore compatibility with
 578  * older kvm releases.
 579  */
 580 #define VMCS12_REVISION 0x11e57ed0
 581
 582 /*
 583  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 584  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 585  * current implementation, 4K are reserved to avoid future complications.
 586  */
 587 #define VMCS12_SIZE 0x1000
 588
 589 /*
 590  * VMCS12_MAX_FIELD_INDEX is the highest index value used in any
 591  * supported VMCS12 field encoding.
 592  */
 593 #define VMCS12_MAX_FIELD_INDEX 0x17
 594
 595 struct nested_vmx_msrs {
 596         /*
 597          * We only store the "true" versions of the VMX capability MSRs. We
 598          * generate the "non-true" versions by setting the must-be-1 bits
 599          * according to the SDM.
 600          */
 601         u32 procbased_ctls_low;
 602         u32 procbased_ctls_high;
 603         u32 secondary_ctls_low;
 604         u32 secondary_ctls_high;
 605         u32 pinbased_ctls_low;
 606         u32 pinbased_ctls_high;
 607         u32 exit_ctls_low;
 608         u32 exit_ctls_high;
 609         u32 entry_ctls_low;
 610         u32 entry_ctls_high;
 611         u32 misc_low;
 612         u32 misc_high;
 613         u32 ept_caps;
 614         u32 vpid_caps;
 615         u64 basic;
 616         u64 cr0_fixed0;
 617         u64 cr0_fixed1;
 618         u64 cr4_fixed0;
 619         u64 cr4_fixed1;
 620         u64 vmcs_enum;
 621         u64 vmfunc_controls;
 622 };
 623
 624 /*
 625  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 626  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 627  */
 628 struct nested_vmx {
 629         /* Has the level1 guest done vmxon? */
 630         bool vmxon;
 631         gpa_t vmxon_ptr;
 632         bool pml_full;
 633
 634         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 635         gpa_t current_vmptr;
 636         /*
 637          * Cache of the guest's VMCS, existing outside of guest memory.
 638          * Loaded from guest memory during VMPTRLD. Flushed to guest
 639          * memory during VMCLEAR and VMPTRLD.
 640          */
 641         struct vmcs12 *cached_vmcs12;
 642         /*
 643          * Indicates if the shadow vmcs must be updated with the
 644          * data hold by vmcs12
 645          */
 646         bool sync_shadow_vmcs;
 647         bool dirty_vmcs12;
 648
 649         bool change_vmcs01_virtual_apic_mode;
 650
 651         /* L2 must run next, and mustn't decide to exit to L1. */
 652         bool nested_run_pending;
 653
 654         struct loaded_vmcs vmcs02;
 655
 656         /*
 657          * Guest pages referred to in the vmcs02 with host-physical
 658          * pointers, so we must keep them pinned while L2 runs.
 659          */
 660         struct page *apic_access_page;
 661         struct page *virtual_apic_page;
 662         struct page *pi_desc_page;
 663         struct pi_desc *pi_desc;
 664         bool pi_pending;
 665         u16 posted_intr_nv;
 666
 667         struct hrtimer preemption_timer;
 668         bool preemption_timer_expired;
 669
 670         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 671         u64 vmcs01_debugctl;
 672
 673         u16 vpid02;
 674         u16 last_vpid;
 675
 676         struct nested_vmx_msrs msrs;
 677
 678         /* SMM related state */
 679         struct {
 680                 /* in VMX operation on SMM entry? */
 681                 bool vmxon;
 682                 /* in guest mode on SMM entry? */
 683                 bool guest_mode;
 684         } smm;
 685 };
 686
 687 #define POSTED_INTR_ON  0
 688 #define POSTED_INTR_SN  1
 689
 690 /* Posted-Interrupt Descriptor */
 691 struct pi_desc {
 692         u32 pir[8];     /* Posted interrupt requested */
 693         union {
 694                 struct {
 695                                 /* bit 256 - Outstanding Notification */
 696                         u16     on      : 1,
 697                                 /* bit 257 - Suppress Notification */
 698                                 sn      : 1,
 699                                 /* bit 271:258 - Reserved */
 700                                 rsvd_1  : 14;
 701                                 /* bit 279:272 - Notification Vector */
 702                         u8      nv;
 703                                 /* bit 287:280 - Reserved */
 704                         u8      rsvd_2;
 705                                 /* bit 319:288 - Notification Destination */
 706                         u32     ndst;
 707                 };
 708                 u64 control;
 709         };
 710         u32 rsvd[6];
 711 } __aligned(64);
 712
 713 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 714 {
 715         return test_and_set_bit(POSTED_INTR_ON,
 716                         (unsigned long *)&pi_desc->control);
 717 }
 718
 719 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 720 {
 721         return test_and_clear_bit(POSTED_INTR_ON,
 722                         (unsigned long *)&pi_desc->control);
 723 }
 724
 725 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 726 {
 727         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 728 }
 729
 730 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 731 {
 732         return clear_bit(POSTED_INTR_SN,
 733                         (unsigned long *)&pi_desc->control);
 734 }
 735
 736 static inline void pi_set_sn(struct pi_desc *pi_desc)
 737 {
 738         return set_bit(POSTED_INTR_SN,
 739                         (unsigned long *)&pi_desc->control);
 740 }
 741
 742 static inline void pi_clear_on(struct pi_desc *pi_desc)
 743 {
 744         clear_bit(POSTED_INTR_ON,
 745                   (unsigned long *)&pi_desc->control);
 746 }
 747
 748 static inline int pi_test_on(struct pi_desc *pi_desc)
 749 {
 750         return test_bit(POSTED_INTR_ON,
 751                         (unsigned long *)&pi_desc->control);
 752 }
 753
 754 static inline int pi_test_sn(struct pi_desc *pi_desc)
 755 {
 756         return test_bit(POSTED_INTR_SN,
 757                         (unsigned long *)&pi_desc->control);
 758 }
 759
 760 struct vcpu_vmx {
 761         struct kvm_vcpu       vcpu;
 762         unsigned long         host_rsp;
 763         u8                    fail;
 764         u8                    msr_bitmap_mode;
 765         u32                   exit_intr_info;
 766         u32                   idt_vectoring_info;
 767         ulong                 rflags;
 768         struct shared_msr_entry *guest_msrs;
 769         int                   nmsrs;
 770         int                   save_nmsrs;
 771         unsigned long         host_idt_base;
 772 #ifdef CONFIG_X86_64
 773         u64                   msr_host_kernel_gs_base;
 774         u64                   msr_guest_kernel_gs_base;
 775 #endif
 776
 777         u64                   arch_capabilities;
 778         u64                   spec_ctrl;
 779
 780         u32 vm_entry_controls_shadow;
 781         u32 vm_exit_controls_shadow;
 782         u32 secondary_exec_control;
 783
 784         /*
 785          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 786          * non-nested (L1) guest, it always points to vmcs01. For a nested
 787          * guest (L2), it points to a different VMCS.
 788          */
 789         struct loaded_vmcs    vmcs01;
 790         struct loaded_vmcs   *loaded_vmcs;
 791         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 792         struct msr_autoload {
 793                 unsigned nr;
 794                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 795                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 796         } msr_autoload;
 797         struct {
 798                 int           loaded;
 799                 u16           fs_sel, gs_sel, ldt_sel;
 800 #ifdef CONFIG_X86_64
 801                 u16           ds_sel, es_sel;
 802 #endif
 803                 int           gs_ldt_reload_needed;
 804                 int           fs_reload_needed;
 805                 u64           msr_host_bndcfgs;
 806         } host_state;
 807         struct {
 808                 int vm86_active;
 809                 ulong save_rflags;
 810                 struct kvm_segment segs[8];
 811         } rmode;
 812         struct {
 813                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 814                 struct kvm_save_segment {
 815                         u16 selector;
 816                         unsigned long base;
 817                         u32 limit;
 818                         u32 ar;
 819                 } seg[8];
 820         } segment_cache;
 821         int vpid;
 822         bool emulation_required;
 823
 824         u32 exit_reason;
 825
 826         /* Posted interrupt descriptor */
 827         struct pi_desc pi_desc;
 828
 829         /* Support for a guest hypervisor (nested VMX) */
 830         struct nested_vmx nested;
 831
 832         /* Dynamic PLE window. */
 833         int ple_window;
 834         bool ple_window_dirty;
 835
 836         /* Support for PML */
 837 #define PML_ENTITY_NUM          512
 838         struct page *pml_pg;
 839
 840         /* apic deadline value in host tsc */
 841         u64 hv_deadline_tsc;
 842
 843         u64 current_tsc_ratio;
 844
 845         u32 host_pkru;
 846
 847         unsigned long host_debugctlmsr;
 848
 849         /*
 850          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 851          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 852          * in msr_ia32_feature_control_valid_bits.
 853          */
 854         u64 msr_ia32_feature_control;
 855         u64 msr_ia32_feature_control_valid_bits;
 856 };
 857
 858 enum segment_cache_field {
 859         SEG_FIELD_SEL = 0,
 860         SEG_FIELD_BASE = 1,
 861         SEG_FIELD_LIMIT = 2,
 862         SEG_FIELD_AR = 3,
 863
 864         SEG_FIELD_NR = 4
 865 };
 866
 867 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
 868 {
 869         return container_of(kvm, struct kvm_vmx, kvm);
 870 }
 871
 872 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 873 {
 874         return container_of(vcpu, struct vcpu_vmx, vcpu);
 875 }
 876
 877 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 878 {
 879         return &(to_vmx(vcpu)->pi_desc);
 880 }
 881
 882 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
 883 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 884 #define FIELD(number, name)     [ROL16(number, 6)] = VMCS12_OFFSET(name)
 885 #define FIELD64(number, name)                                           \
 886         FIELD(number, name),                                            \
 887         [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
 888
 889
 890 static u16 shadow_read_only_fields[] = {
 891 #define SHADOW_FIELD_RO(x) x,
 892 #include "vmx_shadow_fields.h"
 893 };
 894 static int max_shadow_read_only_fields =
 895         ARRAY_SIZE(shadow_read_only_fields);
 896
 897 static u16 shadow_read_write_fields[] = {
 898 #define SHADOW_FIELD_RW(x) x,
 899 #include "vmx_shadow_fields.h"
 900 };
 901 static int max_shadow_read_write_fields =
 902         ARRAY_SIZE(shadow_read_write_fields);
 903
 904 static const unsigned short vmcs_field_to_offset_table[] = {
 905         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 906         FIELD(POSTED_INTR_NV, posted_intr_nv),
 907         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 908         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 909         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 910         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 911         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 912         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 913         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 914         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 915         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 916         FIELD(GUEST_PML_INDEX, guest_pml_index),
 917         FIELD(HOST_ES_SELECTOR, host_es_selector),
 918         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 919         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 920         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 921         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 922         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 923         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 924         FIELD64(IO_BITMAP_A, io_bitmap_a),
 925         FIELD64(IO_BITMAP_B, io_bitmap_b),
 926         FIELD64(MSR_BITMAP, msr_bitmap),
 927         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 928         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 929         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 930         FIELD64(PML_ADDRESS, pml_address),
 931         FIELD64(TSC_OFFSET, tsc_offset),
 932         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 933         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 934         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 935         FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
 936         FIELD64(EPT_POINTER, ept_pointer),
 937         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 938         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 939         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 940         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 941         FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
 942         FIELD64(VMREAD_BITMAP, vmread_bitmap),
 943         FIELD64(VMWRITE_BITMAP, vmwrite_bitmap),
 944         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 945         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 946         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 947         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 948         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 949         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 950         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 951         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 952         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 953         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 954         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 955         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 956         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 957         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 958         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 959         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 960         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 961         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 962         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 963         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 964         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 965         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 966         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 967         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 968         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 969         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 970         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 971         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 972         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 973         FIELD(TPR_THRESHOLD, tpr_threshold),
 974         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 975         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 976         FIELD(VM_EXIT_REASON, vm_exit_reason),
 977         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 978         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 979         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 980         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 981         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 982         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 983         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 984         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 985         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 986         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 987         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 988         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 989         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 990         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 991         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 992         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 993         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 994         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 995         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 996         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 997         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 998         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 999         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
1000         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
1001         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
1002         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
1003         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
1004         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
1005         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
1006         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
1007         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
1008         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
1009         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
1010         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
1011         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
1012         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
1013         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
1014         FIELD(EXIT_QUALIFICATION, exit_qualification),
1015         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
1016         FIELD(GUEST_CR0, guest_cr0),
1017         FIELD(GUEST_CR3, guest_cr3),
1018         FIELD(GUEST_CR4, guest_cr4),
1019         FIELD(GUEST_ES_BASE, guest_es_base),
1020         FIELD(GUEST_CS_BASE, guest_cs_base),
1021         FIELD(GUEST_SS_BASE, guest_ss_base),
1022         FIELD(GUEST_DS_BASE, guest_ds_base),
1023         FIELD(GUEST_FS_BASE, guest_fs_base),
1024         FIELD(GUEST_GS_BASE, guest_gs_base),
1025         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
1026         FIELD(GUEST_TR_BASE, guest_tr_base),
1027         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
1028         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
1029         FIELD(GUEST_DR7, guest_dr7),
1030         FIELD(GUEST_RSP, guest_rsp),
1031         FIELD(GUEST_RIP, guest_rip),
1032         FIELD(GUEST_RFLAGS, guest_rflags),
1033         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
1034         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
1035         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
1036         FIELD(HOST_CR0, host_cr0),
1037         FIELD(HOST_CR3, host_cr3),
1038         FIELD(HOST_CR4, host_cr4),
1039         FIELD(HOST_FS_BASE, host_fs_base),
1040         FIELD(HOST_GS_BASE, host_gs_base),
1041         FIELD(HOST_TR_BASE, host_tr_base),
1042         FIELD(HOST_GDTR_BASE, host_gdtr_base),
1043         FIELD(HOST_IDTR_BASE, host_idtr_base),
1044         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
1045         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
1046         FIELD(HOST_RSP, host_rsp),
1047         FIELD(HOST_RIP, host_rip),
1048 };
1049
1050 static inline short vmcs_field_to_offset(unsigned long field)
1051 {
1052         const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
1053         unsigned short offset;
1054         unsigned index;
1055
1056         if (field >> 15)
1057                 return -ENOENT;
1058
1059         index = ROL16(field, 6);
1060         if (index >= size)
1061                 return -ENOENT;
1062
1063         index = array_index_nospec(index, size);
1064         offset = vmcs_field_to_offset_table[index];
1065         if (offset == 0)
1066                 return -ENOENT;
1067         return offset;
1068 }
1069
1070 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
1071 {
1072         return to_vmx(vcpu)->nested.cached_vmcs12;
1073 }
1074
1075 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
1076 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
1077 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
1078 static bool vmx_xsaves_supported(void);
1079 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1080                             struct kvm_segment *var, int seg);
1081 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1082                             struct kvm_segment *var, int seg);
1083 static bool guest_state_valid(struct kvm_vcpu *vcpu);
1084 static u32 vmx_segment_access_rights(struct kvm_segment *var);
1085 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
1086 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
1087 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
1088 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
1089                                             u16 error_code);
1090 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
1091 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
1092                                                           u32 msr, int type);
1093
1094 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
1095 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
1096 /*
1097  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
1098  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
1099  */
1100 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
1101
1102 /*
1103  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
1104  * can find which vCPU should be waken up.
1105  */
1106 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
1107 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
1108
1109 enum {
1110         VMX_VMREAD_BITMAP,
1111         VMX_VMWRITE_BITMAP,
1112         VMX_BITMAP_NR
1113 };
1114
1115 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
1116
1117 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
1118 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
1119
1120 static bool cpu_has_load_ia32_efer;
1121 static bool cpu_has_load_perf_global_ctrl;
1122
1123 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
1124 static DEFINE_SPINLOCK(vmx_vpid_lock);
1125
1126 static struct vmcs_config {
1127         int size;
1128         int order;
1129         u32 basic_cap;
1130         u32 revision_id;
1131         u32 pin_based_exec_ctrl;
1132         u32 cpu_based_exec_ctrl;
1133         u32 cpu_based_2nd_exec_ctrl;
1134         u32 vmexit_ctrl;
1135         u32 vmentry_ctrl;
1136         struct nested_vmx_msrs nested;
1137 } vmcs_config;
1138
1139 static struct vmx_capability {
1140         u32 ept;
1141         u32 vpid;
1142 } vmx_capability;
1143
1144 #define VMX_SEGMENT_FIELD(seg)                                  \
1145         [VCPU_SREG_##seg] = {                                   \
1146                 .selector = GUEST_##seg##_SELECTOR,             \
1147                 .base = GUEST_##seg##_BASE,                     \
1148                 .limit = GUEST_##seg##_LIMIT,                   \
1149                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1150         }
1151
1152 static const struct kvm_vmx_segment_field {
1153         unsigned selector;
1154         unsigned base;
1155         unsigned limit;
1156         unsigned ar_bytes;
1157 } kvm_vmx_segment_fields[] = {
1158         VMX_SEGMENT_FIELD(CS),
1159         VMX_SEGMENT_FIELD(DS),
1160         VMX_SEGMENT_FIELD(ES),
1161         VMX_SEGMENT_FIELD(FS),
1162         VMX_SEGMENT_FIELD(GS),
1163         VMX_SEGMENT_FIELD(SS),
1164         VMX_SEGMENT_FIELD(TR),
1165         VMX_SEGMENT_FIELD(LDTR),
1166 };
1167
1168 static u64 host_efer;
1169
1170 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1171
1172 /*
1173  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1174  * away by decrementing the array size.
1175  */
1176 static const u32 vmx_msr_index[] = {
1177 #ifdef CONFIG_X86_64
1178         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1179 #endif
1180         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1181 };
1182
1183 DEFINE_STATIC_KEY_FALSE(enable_evmcs);
1184
1185 #define current_evmcs ((struct hv_enlightened_vmcs *)this_cpu_read(current_vmcs))
1186
1187 #define KVM_EVMCS_VERSION 1
1188
1189 #if IS_ENABLED(CONFIG_HYPERV)
1190 static bool __read_mostly enlightened_vmcs = true;
1191 module_param(enlightened_vmcs, bool, 0444);
1192
1193 static inline void evmcs_write64(unsigned long field, u64 value)
1194 {
1195         u16 clean_field;
1196         int offset = get_evmcs_offset(field, &clean_field);
1197
1198         if (offset < 0)
1199                 return;
1200
1201         *(u64 *)((char *)current_evmcs + offset) = value;
1202
1203         current_evmcs->hv_clean_fields &= ~clean_field;
1204 }
1205
1206 static inline void evmcs_write32(unsigned long field, u32 value)
1207 {
1208         u16 clean_field;
1209         int offset = get_evmcs_offset(field, &clean_field);
1210
1211         if (offset < 0)
1212                 return;
1213
1214         *(u32 *)((char *)current_evmcs + offset) = value;
1215         current_evmcs->hv_clean_fields &= ~clean_field;
1216 }
1217
1218 static inline void evmcs_write16(unsigned long field, u16 value)
1219 {
1220         u16 clean_field;
1221         int offset = get_evmcs_offset(field, &clean_field);
1222
1223         if (offset < 0)
1224                 return;
1225
1226         *(u16 *)((char *)current_evmcs + offset) = value;
1227         current_evmcs->hv_clean_fields &= ~clean_field;
1228 }
1229
1230 static inline u64 evmcs_read64(unsigned long field)
1231 {
1232         int offset = get_evmcs_offset(field, NULL);
1233
1234         if (offset < 0)
1235                 return 0;
1236
1237         return *(u64 *)((char *)current_evmcs + offset);
1238 }
1239
1240 static inline u32 evmcs_read32(unsigned long field)
1241 {
1242         int offset = get_evmcs_offset(field, NULL);
1243
1244         if (offset < 0)
1245                 return 0;
1246
1247         return *(u32 *)((char *)current_evmcs + offset);
1248 }
1249
1250 static inline u16 evmcs_read16(unsigned long field)
1251 {
1252         int offset = get_evmcs_offset(field, NULL);
1253
1254         if (offset < 0)
1255                 return 0;
1256
1257         return *(u16 *)((char *)current_evmcs + offset);
1258 }
1259
1260 static inline void evmcs_touch_msr_bitmap(void)
1261 {
1262         if (unlikely(!current_evmcs))
1263                 return;
1264
1265         if (current_evmcs->hv_enlightenments_control.msr_bitmap)
1266                 current_evmcs->hv_clean_fields &=
1267                         ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP;
1268 }
1269
1270 static void evmcs_load(u64 phys_addr)
1271 {
1272         struct hv_vp_assist_page *vp_ap =
1273                 hv_get_vp_assist_page(smp_processor_id());
1274
1275         vp_ap->current_nested_vmcs = phys_addr;
1276         vp_ap->enlighten_vmentry = 1;
1277 }
1278
1279 static void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf)
1280 {
1281         /*
1282          * Enlightened VMCSv1 doesn't support these:
1283          *
1284          *      POSTED_INTR_NV                  = 0x00000002,
1285          *      GUEST_INTR_STATUS               = 0x00000810,
1286          *      APIC_ACCESS_ADDR                = 0x00002014,
1287          *      POSTED_INTR_DESC_ADDR           = 0x00002016,
1288          *      EOI_EXIT_BITMAP0                = 0x0000201c,
1289          *      EOI_EXIT_BITMAP1                = 0x0000201e,
1290          *      EOI_EXIT_BITMAP2                = 0x00002020,
1291          *      EOI_EXIT_BITMAP3                = 0x00002022,
1292          */
1293         vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
1294         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1295                 ~SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1296         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1297                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1298         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1299                 ~SECONDARY_EXEC_APIC_REGISTER_VIRT;
1300
1301         /*
1302          *      GUEST_PML_INDEX                 = 0x00000812,
1303          *      PML_ADDRESS                     = 0x0000200e,
1304          */
1305         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_PML;
1306
1307         /*      VM_FUNCTION_CONTROL             = 0x00002018, */
1308         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_VMFUNC;
1309
1310         /*
1311          *      EPTP_LIST_ADDRESS               = 0x00002024,
1312          *      VMREAD_BITMAP                   = 0x00002026,
1313          *      VMWRITE_BITMAP                  = 0x00002028,
1314          */
1315         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_SHADOW_VMCS;
1316
1317         /*
1318          *      TSC_MULTIPLIER                  = 0x00002032,
1319          */
1320         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_TSC_SCALING;
1321
1322         /*
1323          *      PLE_GAP                         = 0x00004020,
1324          *      PLE_WINDOW                      = 0x00004022,
1325          */
1326         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1327
1328         /*
1329          *      VMX_PREEMPTION_TIMER_VALUE      = 0x0000482E,
1330          */
1331         vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
1332
1333         /*
1334          *      GUEST_IA32_PERF_GLOBAL_CTRL     = 0x00002808,
1335          *      HOST_IA32_PERF_GLOBAL_CTRL      = 0x00002c04,
1336          */
1337         vmcs_conf->vmexit_ctrl &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
1338         vmcs_conf->vmentry_ctrl &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
1339
1340         /*
1341          * Currently unsupported in KVM:
1342          *      GUEST_IA32_RTIT_CTL             = 0x00002814,
1343          */
1344 }
1345 #else /* !IS_ENABLED(CONFIG_HYPERV) */
1346 static inline void evmcs_write64(unsigned long field, u64 value) {}
1347 static inline void evmcs_write32(unsigned long field, u32 value) {}
1348 static inline void evmcs_write16(unsigned long field, u16 value) {}
1349 static inline u64 evmcs_read64(unsigned long field) { return 0; }
1350 static inline u32 evmcs_read32(unsigned long field) { return 0; }
1351 static inline u16 evmcs_read16(unsigned long field) { return 0; }
1352 static inline void evmcs_load(u64 phys_addr) {}
1353 static inline void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf) {}
1354 static inline void evmcs_touch_msr_bitmap(void) {}
1355 #endif /* IS_ENABLED(CONFIG_HYPERV) */
1356
1357 static inline bool is_exception_n(u32 intr_info, u8 vector)
1358 {
1359         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1360                              INTR_INFO_VALID_MASK)) ==
1361                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1362 }
1363
1364 static inline bool is_debug(u32 intr_info)
1365 {
1366         return is_exception_n(intr_info, DB_VECTOR);
1367 }
1368
1369 static inline bool is_breakpoint(u32 intr_info)
1370 {
1371         return is_exception_n(intr_info, BP_VECTOR);
1372 }
1373
1374 static inline bool is_page_fault(u32 intr_info)
1375 {
1376         return is_exception_n(intr_info, PF_VECTOR);
1377 }
1378
1379 static inline bool is_no_device(u32 intr_info)
1380 {
1381         return is_exception_n(intr_info, NM_VECTOR);
1382 }
1383
1384 static inline bool is_invalid_opcode(u32 intr_info)
1385 {
1386         return is_exception_n(intr_info, UD_VECTOR);
1387 }
1388
1389 static inline bool is_gp_fault(u32 intr_info)
1390 {
1391         return is_exception_n(intr_info, GP_VECTOR);
1392 }
1393
1394 static inline bool is_external_interrupt(u32 intr_info)
1395 {
1396         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1397                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1398 }
1399
1400 static inline bool is_machine_check(u32 intr_info)
1401 {
1402         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1403                              INTR_INFO_VALID_MASK)) ==
1404                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1405 }
1406
1407 /* Undocumented: icebp/int1 */
1408 static inline bool is_icebp(u32 intr_info)
1409 {
1410         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1411                 == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
1412 }
1413
1414 static inline bool cpu_has_vmx_msr_bitmap(void)
1415 {
1416         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1417 }
1418
1419 static inline bool cpu_has_vmx_tpr_shadow(void)
1420 {
1421         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1422 }
1423
1424 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1425 {
1426         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1427 }
1428
1429 static inline bool cpu_has_secondary_exec_ctrls(void)
1430 {
1431         return vmcs_config.cpu_based_exec_ctrl &
1432                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1433 }
1434
1435 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1436 {
1437         return vmcs_config.cpu_based_2nd_exec_ctrl &
1438                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1439 }
1440
1441 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1442 {
1443         return vmcs_config.cpu_based_2nd_exec_ctrl &
1444                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1445 }
1446
1447 static inline bool cpu_has_vmx_apic_register_virt(void)
1448 {
1449         return vmcs_config.cpu_based_2nd_exec_ctrl &
1450                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1451 }
1452
1453 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1454 {
1455         return vmcs_config.cpu_based_2nd_exec_ctrl &
1456                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1457 }
1458
1459 /*
1460  * Comment's format: document - errata name - stepping - processor name.
1461  * Refer from
1462  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1463  */
1464 static u32 vmx_preemption_cpu_tfms[] = {
1465 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1466 0x000206E6,
1467 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1468 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1469 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1470 0x00020652,
1471 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1472 0x00020655,
1473 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1474 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1475 /*
1476  * 320767.pdf - AAP86  - B1 -
1477  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1478  */
1479 0x000106E5,
1480 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1481 0x000106A0,
1482 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1483 0x000106A1,
1484 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1485 0x000106A4,
1486  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1487  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1488  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1489 0x000106A5,
1490 };
1491
1492 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1493 {
1494         u32 eax = cpuid_eax(0x00000001), i;
1495
1496         /* Clear the reserved bits */
1497         eax &= ~(0x3U << 14 | 0xfU << 28);
1498         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1499                 if (eax == vmx_preemption_cpu_tfms[i])
1500                         return true;
1501
1502         return false;
1503 }
1504
1505 static inline bool cpu_has_vmx_preemption_timer(void)
1506 {
1507         return vmcs_config.pin_based_exec_ctrl &
1508                 PIN_BASED_VMX_PREEMPTION_TIMER;
1509 }
1510
1511 static inline bool cpu_has_vmx_posted_intr(void)
1512 {
1513         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1514                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1515 }
1516
1517 static inline bool cpu_has_vmx_apicv(void)
1518 {
1519         return cpu_has_vmx_apic_register_virt() &&
1520                 cpu_has_vmx_virtual_intr_delivery() &&
1521                 cpu_has_vmx_posted_intr();
1522 }
1523
1524 static inline bool cpu_has_vmx_flexpriority(void)
1525 {
1526         return cpu_has_vmx_tpr_shadow() &&
1527                 cpu_has_vmx_virtualize_apic_accesses();
1528 }
1529
1530 static inline bool cpu_has_vmx_ept_execute_only(void)
1531 {
1532         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1533 }
1534
1535 static inline bool cpu_has_vmx_ept_2m_page(void)
1536 {
1537         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1538 }
1539
1540 static inline bool cpu_has_vmx_ept_1g_page(void)
1541 {
1542         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1543 }
1544
1545 static inline bool cpu_has_vmx_ept_4levels(void)
1546 {
1547         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1548 }
1549
1550 static inline bool cpu_has_vmx_ept_mt_wb(void)
1551 {
1552         return vmx_capability.ept & VMX_EPTP_WB_BIT;
1553 }
1554
1555 static inline bool cpu_has_vmx_ept_5levels(void)
1556 {
1557         return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1558 }
1559
1560 static inline bool cpu_has_vmx_ept_ad_bits(void)
1561 {
1562         return vmx_capability.ept & VMX_EPT_AD_BIT;
1563 }
1564
1565 static inline bool cpu_has_vmx_invept_context(void)
1566 {
1567         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1568 }
1569
1570 static inline bool cpu_has_vmx_invept_global(void)
1571 {
1572         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1573 }
1574
1575 static inline bool cpu_has_vmx_invvpid_individual_addr(void)
1576 {
1577         return vmx_capability.vpid & VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT;
1578 }
1579
1580 static inline bool cpu_has_vmx_invvpid_single(void)
1581 {
1582         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1583 }
1584
1585 static inline bool cpu_has_vmx_invvpid_global(void)
1586 {
1587         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1588 }
1589
1590 static inline bool cpu_has_vmx_invvpid(void)
1591 {
1592         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1593 }
1594
1595 static inline bool cpu_has_vmx_ept(void)
1596 {
1597         return vmcs_config.cpu_based_2nd_exec_ctrl &
1598                 SECONDARY_EXEC_ENABLE_EPT;
1599 }
1600
1601 static inline bool cpu_has_vmx_unrestricted_guest(void)
1602 {
1603         return vmcs_config.cpu_based_2nd_exec_ctrl &
1604                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1605 }
1606
1607 static inline bool cpu_has_vmx_ple(void)
1608 {
1609         return vmcs_config.cpu_based_2nd_exec_ctrl &
1610                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1611 }
1612
1613 static inline bool cpu_has_vmx_basic_inout(void)
1614 {
1615         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1616 }
1617
1618 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1619 {
1620         return flexpriority_enabled && lapic_in_kernel(vcpu);
1621 }
1622
1623 static inline bool cpu_has_vmx_vpid(void)
1624 {
1625         return vmcs_config.cpu_based_2nd_exec_ctrl &
1626                 SECONDARY_EXEC_ENABLE_VPID;
1627 }
1628
1629 static inline bool cpu_has_vmx_rdtscp(void)
1630 {
1631         return vmcs_config.cpu_based_2nd_exec_ctrl &
1632                 SECONDARY_EXEC_RDTSCP;
1633 }
1634
1635 static inline bool cpu_has_vmx_invpcid(void)
1636 {
1637         return vmcs_config.cpu_based_2nd_exec_ctrl &
1638                 SECONDARY_EXEC_ENABLE_INVPCID;
1639 }
1640
1641 static inline bool cpu_has_virtual_nmis(void)
1642 {
1643         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1644 }
1645
1646 static inline bool cpu_has_vmx_wbinvd_exit(void)
1647 {
1648         return vmcs_config.cpu_based_2nd_exec_ctrl &
1649                 SECONDARY_EXEC_WBINVD_EXITING;
1650 }
1651
1652 static inline bool cpu_has_vmx_shadow_vmcs(void)
1653 {
1654         u64 vmx_msr;
1655         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1656         /* check if the cpu supports writing r/o exit information fields */
1657         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1658                 return false;
1659
1660         return vmcs_config.cpu_based_2nd_exec_ctrl &
1661                 SECONDARY_EXEC_SHADOW_VMCS;
1662 }
1663
1664 static inline bool cpu_has_vmx_pml(void)
1665 {
1666         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1667 }
1668
1669 static inline bool cpu_has_vmx_tsc_scaling(void)
1670 {
1671         return vmcs_config.cpu_based_2nd_exec_ctrl &
1672                 SECONDARY_EXEC_TSC_SCALING;
1673 }
1674
1675 static inline bool cpu_has_vmx_vmfunc(void)
1676 {
1677         return vmcs_config.cpu_based_2nd_exec_ctrl &
1678                 SECONDARY_EXEC_ENABLE_VMFUNC;
1679 }
1680
1681 static bool vmx_umip_emulated(void)
1682 {
1683         return vmcs_config.cpu_based_2nd_exec_ctrl &
1684                 SECONDARY_EXEC_DESC;
1685 }
1686
1687 static inline bool report_flexpriority(void)
1688 {
1689         return flexpriority_enabled;
1690 }
1691
1692 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1693 {
1694         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low);
1695 }
1696
1697 /*
1698  * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE
1699  * to modify any valid field of the VMCS, or are the VM-exit
1700  * information fields read-only?
1701  */
1702 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu)
1703 {
1704         return to_vmx(vcpu)->nested.msrs.misc_low &
1705                 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS;
1706 }
1707
1708 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1709 {
1710         return vmcs12->cpu_based_vm_exec_control & bit;
1711 }
1712
1713 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1714 {
1715         return (vmcs12->cpu_based_vm_exec_control &
1716                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1717                 (vmcs12->secondary_vm_exec_control & bit);
1718 }
1719
1720 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1721 {
1722         return vmcs12->pin_based_vm_exec_control &
1723                 PIN_BASED_VMX_PREEMPTION_TIMER;
1724 }
1725
1726 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12)
1727 {
1728         return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING;
1729 }
1730
1731 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1732 {
1733         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1734 }
1735
1736 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1737 {
1738         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1739 }
1740
1741 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1742 {
1743         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
1744 }
1745
1746 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1747 {
1748         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1749 }
1750
1751 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1752 {
1753         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1754 }
1755
1756 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1757 {
1758         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1759 }
1760
1761 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1762 {
1763         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1764 }
1765
1766 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1767 {
1768         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1769 }
1770
1771 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1772 {
1773         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1774 }
1775
1776 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1777 {
1778         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1779 }
1780
1781 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1782 {
1783         return nested_cpu_has_vmfunc(vmcs12) &&
1784                 (vmcs12->vm_function_control &
1785                  VMX_VMFUNC_EPTP_SWITCHING);
1786 }
1787
1788 static inline bool is_nmi(u32 intr_info)
1789 {
1790         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1791                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1792 }
1793
1794 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1795                               u32 exit_intr_info,
1796                               unsigned long exit_qualification);
1797 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1798                         struct vmcs12 *vmcs12,
1799                         u32 reason, unsigned long qualification);
1800
1801 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1802 {
1803         int i;
1804
1805         for (i = 0; i < vmx->nmsrs; ++i)
1806                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1807                         return i;
1808         return -1;
1809 }
1810
1811 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1812 {
1813     struct {
1814         u64 vpid : 16;
1815         u64 rsvd : 48;
1816         u64 gva;
1817     } operand = { vpid, 0, gva };
1818
1819     asm volatile (__ex(ASM_VMX_INVVPID)
1820                   /* CF==1 or ZF==1 --> rc = -1 */
1821                   "; ja 1f ; ud2 ; 1:"
1822                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1823 }
1824
1825 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1826 {
1827         struct {
1828                 u64 eptp, gpa;
1829         } operand = {eptp, gpa};
1830
1831         asm volatile (__ex(ASM_VMX_INVEPT)
1832                         /* CF==1 or ZF==1 --> rc = -1 */
1833                         "; ja 1f ; ud2 ; 1:\n"
1834                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1835 }
1836
1837 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1838 {
1839         int i;
1840
1841         i = __find_msr_index(vmx, msr);
1842         if (i >= 0)
1843                 return &vmx->guest_msrs[i];
1844         return NULL;
1845 }
1846
1847 static void vmcs_clear(struct vmcs *vmcs)
1848 {
1849         u64 phys_addr = __pa(vmcs);
1850         u8 error;
1851
1852         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1853                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1854                       : "cc", "memory");
1855         if (error)
1856                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1857                        vmcs, phys_addr);
1858 }
1859
1860 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1861 {
1862         vmcs_clear(loaded_vmcs->vmcs);
1863         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1864                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1865         loaded_vmcs->cpu = -1;
1866         loaded_vmcs->launched = 0;
1867 }
1868
1869 static void vmcs_load(struct vmcs *vmcs)
1870 {
1871         u64 phys_addr = __pa(vmcs);
1872         u8 error;
1873
1874         if (static_branch_unlikely(&enable_evmcs))
1875                 return evmcs_load(phys_addr);
1876
1877         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1878                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1879                         : "cc", "memory");
1880         if (error)
1881                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1882                        vmcs, phys_addr);
1883 }
1884
1885 #ifdef CONFIG_KEXEC_CORE
1886 /*
1887  * This bitmap is used to indicate whether the vmclear
1888  * operation is enabled on all cpus. All disabled by
1889  * default.
1890  */
1891 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1892
1893 static inline void crash_enable_local_vmclear(int cpu)
1894 {
1895         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1896 }
1897
1898 static inline void crash_disable_local_vmclear(int cpu)
1899 {
1900         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1901 }
1902
1903 static inline int crash_local_vmclear_enabled(int cpu)
1904 {
1905         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1906 }
1907
1908 static void crash_vmclear_local_loaded_vmcss(void)
1909 {
1910         int cpu = raw_smp_processor_id();
1911         struct loaded_vmcs *v;
1912
1913         if (!crash_local_vmclear_enabled(cpu))
1914                 return;
1915
1916         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1917                             loaded_vmcss_on_cpu_link)
1918                 vmcs_clear(v->vmcs);
1919 }
1920 #else
1921 static inline void crash_enable_local_vmclear(int cpu) { }
1922 static inline void crash_disable_local_vmclear(int cpu) { }
1923 #endif /* CONFIG_KEXEC_CORE */
1924
1925 static void __loaded_vmcs_clear(void *arg)
1926 {
1927         struct loaded_vmcs *loaded_vmcs = arg;
1928         int cpu = raw_smp_processor_id();
1929
1930         if (loaded_vmcs->cpu != cpu)
1931                 return; /* vcpu migration can race with cpu offline */
1932         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1933                 per_cpu(current_vmcs, cpu) = NULL;
1934         crash_disable_local_vmclear(cpu);
1935         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1936
1937         /*
1938          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1939          * is before setting loaded_vmcs->vcpu to -1 which is done in
1940          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1941          * then adds the vmcs into percpu list before it is deleted.
1942          */
1943         smp_wmb();
1944
1945         loaded_vmcs_init(loaded_vmcs);
1946         crash_enable_local_vmclear(cpu);
1947 }
1948
1949 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1950 {
1951         int cpu = loaded_vmcs->cpu;
1952
1953         if (cpu != -1)
1954                 smp_call_function_single(cpu,
1955                          __loaded_vmcs_clear, loaded_vmcs, 1);
1956 }
1957
1958 static inline void vpid_sync_vcpu_single(int vpid)
1959 {
1960         if (vpid == 0)
1961                 return;
1962
1963         if (cpu_has_vmx_invvpid_single())
1964                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1965 }
1966
1967 static inline void vpid_sync_vcpu_global(void)
1968 {
1969         if (cpu_has_vmx_invvpid_global())
1970                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1971 }
1972
1973 static inline void vpid_sync_context(int vpid)
1974 {
1975         if (cpu_has_vmx_invvpid_single())
1976                 vpid_sync_vcpu_single(vpid);
1977         else
1978                 vpid_sync_vcpu_global();
1979 }
1980
1981 static inline void ept_sync_global(void)
1982 {
1983         __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1984 }
1985
1986 static inline void ept_sync_context(u64 eptp)
1987 {
1988         if (cpu_has_vmx_invept_context())
1989                 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1990         else
1991                 ept_sync_global();
1992 }
1993
1994 static __always_inline void vmcs_check16(unsigned long field)
1995 {
1996         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1997                          "16-bit accessor invalid for 64-bit field");
1998         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1999                          "16-bit accessor invalid for 64-bit high field");
2000         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2001                          "16-bit accessor invalid for 32-bit high field");
2002         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2003                          "16-bit accessor invalid for natural width field");
2004 }
2005
2006 static __always_inline void vmcs_check32(unsigned long field)
2007 {
2008         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2009                          "32-bit accessor invalid for 16-bit field");
2010         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2011                          "32-bit accessor invalid for natural width field");
2012 }
2013
2014 static __always_inline void vmcs_check64(unsigned long field)
2015 {
2016         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2017                          "64-bit accessor invalid for 16-bit field");
2018         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2019                          "64-bit accessor invalid for 64-bit high field");
2020         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2021                          "64-bit accessor invalid for 32-bit field");
2022         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2023                          "64-bit accessor invalid for natural width field");
2024 }
2025
2026 static __always_inline void vmcs_checkl(unsigned long field)
2027 {
2028         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2029                          "Natural width accessor invalid for 16-bit field");
2030         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2031                          "Natural width accessor invalid for 64-bit field");
2032         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2033                          "Natural width accessor invalid for 64-bit high field");
2034         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2035                          "Natural width accessor invalid for 32-bit field");
2036 }
2037
2038 static __always_inline unsigned long __vmcs_readl(unsigned long field)
2039 {
2040         unsigned long value;
2041
2042         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
2043                       : "=a"(value) : "d"(field) : "cc");
2044         return value;
2045 }
2046
2047 static __always_inline u16 vmcs_read16(unsigned long field)
2048 {
2049         vmcs_check16(field);
2050         if (static_branch_unlikely(&enable_evmcs))
2051                 return evmcs_read16(field);
2052         return __vmcs_readl(field);
2053 }
2054
2055 static __always_inline u32 vmcs_read32(unsigned long field)
2056 {
2057         vmcs_check32(field);
2058         if (static_branch_unlikely(&enable_evmcs))
2059                 return evmcs_read32(field);
2060         return __vmcs_readl(field);
2061 }
2062
2063 static __always_inline u64 vmcs_read64(unsigned long field)
2064 {
2065         vmcs_check64(field);
2066         if (static_branch_unlikely(&enable_evmcs))
2067                 return evmcs_read64(field);
2068 #ifdef CONFIG_X86_64
2069         return __vmcs_readl(field);
2070 #else
2071         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
2072 #endif
2073 }
2074
2075 static __always_inline unsigned long vmcs_readl(unsigned long field)
2076 {
2077         vmcs_checkl(field);
2078         if (static_branch_unlikely(&enable_evmcs))
2079                 return evmcs_read64(field);
2080         return __vmcs_readl(field);
2081 }
2082
2083 static noinline void vmwrite_error(unsigned long field, unsigned long value)
2084 {
2085         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
2086                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
2087         dump_stack();
2088 }
2089
2090 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
2091 {
2092         u8 error;
2093
2094         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
2095                        : "=q"(error) : "a"(value), "d"(field) : "cc");
2096         if (unlikely(error))
2097                 vmwrite_error(field, value);
2098 }
2099
2100 static __always_inline void vmcs_write16(unsigned long field, u16 value)
2101 {
2102         vmcs_check16(field);
2103         if (static_branch_unlikely(&enable_evmcs))
2104                 return evmcs_write16(field, value);
2105
2106         __vmcs_writel(field, value);
2107 }
2108
2109 static __always_inline void vmcs_write32(unsigned long field, u32 value)
2110 {
2111         vmcs_check32(field);
2112         if (static_branch_unlikely(&enable_evmcs))
2113                 return evmcs_write32(field, value);
2114
2115         __vmcs_writel(field, value);
2116 }
2117
2118 static __always_inline void vmcs_write64(unsigned long field, u64 value)
2119 {
2120         vmcs_check64(field);
2121         if (static_branch_unlikely(&enable_evmcs))
2122                 return evmcs_write64(field, value);
2123
2124         __vmcs_writel(field, value);
2125 #ifndef CONFIG_X86_64
2126         asm volatile ("");
2127         __vmcs_writel(field+1, value >> 32);
2128 #endif
2129 }
2130
2131 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
2132 {
2133         vmcs_checkl(field);
2134         if (static_branch_unlikely(&enable_evmcs))
2135                 return evmcs_write64(field, value);
2136
2137         __vmcs_writel(field, value);
2138 }
2139
2140 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
2141 {
2142         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2143                          "vmcs_clear_bits does not support 64-bit fields");
2144         if (static_branch_unlikely(&enable_evmcs))
2145                 return evmcs_write32(field, evmcs_read32(field) & ~mask);
2146
2147         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
2148 }
2149
2150 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
2151 {
2152         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2153                          "vmcs_set_bits does not support 64-bit fields");
2154         if (static_branch_unlikely(&enable_evmcs))
2155                 return evmcs_write32(field, evmcs_read32(field) | mask);
2156
2157         __vmcs_writel(field, __vmcs_readl(field) | mask);
2158 }
2159
2160 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
2161 {
2162         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
2163 }
2164
2165 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
2166 {
2167         vmcs_write32(VM_ENTRY_CONTROLS, val);
2168         vmx->vm_entry_controls_shadow = val;
2169 }
2170
2171 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
2172 {
2173         if (vmx->vm_entry_controls_shadow != val)
2174                 vm_entry_controls_init(vmx, val);
2175 }
2176
2177 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
2178 {
2179         return vmx->vm_entry_controls_shadow;
2180 }
2181
2182
2183 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2184 {
2185         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
2186 }
2187
2188 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2189 {
2190         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
2191 }
2192
2193 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
2194 {
2195         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
2196 }
2197
2198 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
2199 {
2200         vmcs_write32(VM_EXIT_CONTROLS, val);
2201         vmx->vm_exit_controls_shadow = val;
2202 }
2203
2204 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
2205 {
2206         if (vmx->vm_exit_controls_shadow != val)
2207                 vm_exit_controls_init(vmx, val);
2208 }
2209
2210 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
2211 {
2212         return vmx->vm_exit_controls_shadow;
2213 }
2214
2215
2216 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2217 {
2218         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
2219 }
2220
2221 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2222 {
2223         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
2224 }
2225
2226 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
2227 {
2228         vmx->segment_cache.bitmask = 0;
2229 }
2230
2231 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
2232                                        unsigned field)
2233 {
2234         bool ret;
2235         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
2236
2237         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
2238                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
2239                 vmx->segment_cache.bitmask = 0;
2240         }
2241         ret = vmx->segment_cache.bitmask & mask;
2242         vmx->segment_cache.bitmask |= mask;
2243         return ret;
2244 }
2245
2246 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
2247 {
2248         u16 *p = &vmx->segment_cache.seg[seg].selector;
2249
2250         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
2251                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
2252         return *p;
2253 }
2254
2255 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
2256 {
2257         ulong *p = &vmx->segment_cache.seg[seg].base;
2258
2259         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
2260                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
2261         return *p;
2262 }
2263
2264 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
2265 {
2266         u32 *p = &vmx->segment_cache.seg[seg].limit;
2267
2268         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
2269                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
2270         return *p;
2271 }
2272
2273 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
2274 {
2275         u32 *p = &vmx->segment_cache.seg[seg].ar;
2276
2277         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
2278                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
2279         return *p;
2280 }
2281
2282 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
2283 {
2284         u32 eb;
2285
2286         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
2287              (1u << DB_VECTOR) | (1u << AC_VECTOR);
2288         /*
2289          * Guest access to VMware backdoor ports could legitimately
2290          * trigger #GP because of TSS I/O permission bitmap.
2291          * We intercept those #GP and allow access to them anyway
2292          * as VMware does.
2293          */
2294         if (enable_vmware_backdoor)
2295                 eb |= (1u << GP_VECTOR);
2296         if ((vcpu->guest_debug &
2297              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
2298             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
2299                 eb |= 1u << BP_VECTOR;
2300         if (to_vmx(vcpu)->rmode.vm86_active)
2301                 eb = ~0;
2302         if (enable_ept)
2303                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
2304
2305         /* When we are running a nested L2 guest and L1 specified for it a
2306          * certain exception bitmap, we must trap the same exceptions and pass
2307          * them to L1. When running L2, we will only handle the exceptions
2308          * specified above if L1 did not want them.
2309          */
2310         if (is_guest_mode(vcpu))
2311                 eb |= get_vmcs12(vcpu)->exception_bitmap;
2312
2313         vmcs_write32(EXCEPTION_BITMAP, eb);
2314 }
2315
2316 /*
2317  * Check if MSR is intercepted for currently loaded MSR bitmap.
2318  */
2319 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
2320 {
2321         unsigned long *msr_bitmap;
2322         int f = sizeof(unsigned long);
2323
2324         if (!cpu_has_vmx_msr_bitmap())
2325                 return true;
2326
2327         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
2328
2329         if (msr <= 0x1fff) {
2330                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2331         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2332                 msr &= 0x1fff;
2333                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2334         }
2335
2336         return true;
2337 }
2338
2339 /*
2340  * Check if MSR is intercepted for L01 MSR bitmap.
2341  */
2342 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
2343 {
2344         unsigned long *msr_bitmap;
2345         int f = sizeof(unsigned long);
2346
2347         if (!cpu_has_vmx_msr_bitmap())
2348                 return true;
2349
2350         msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
2351
2352         if (msr <= 0x1fff) {
2353                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2354         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2355                 msr &= 0x1fff;
2356                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2357         }
2358
2359         return true;
2360 }
2361
2362 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2363                 unsigned long entry, unsigned long exit)
2364 {
2365         vm_entry_controls_clearbit(vmx, entry);
2366         vm_exit_controls_clearbit(vmx, exit);
2367 }
2368
2369 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
2370 {
2371         unsigned i;
2372         struct msr_autoload *m = &vmx->msr_autoload;
2373
2374         switch (msr) {
2375         case MSR_EFER:
2376                 if (cpu_has_load_ia32_efer) {
2377                         clear_atomic_switch_msr_special(vmx,
2378                                         VM_ENTRY_LOAD_IA32_EFER,
2379                                         VM_EXIT_LOAD_IA32_EFER);
2380                         return;
2381                 }
2382                 break;
2383         case MSR_CORE_PERF_GLOBAL_CTRL:
2384                 if (cpu_has_load_perf_global_ctrl) {
2385                         clear_atomic_switch_msr_special(vmx,
2386                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2387                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2388                         return;
2389                 }
2390                 break;
2391         }
2392
2393         for (i = 0; i < m->nr; ++i)
2394                 if (m->guest[i].index == msr)
2395                         break;
2396
2397         if (i == m->nr)
2398                 return;
2399         --m->nr;
2400         m->guest[i] = m->guest[m->nr];
2401         m->host[i] = m->host[m->nr];
2402         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2403         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2404 }
2405
2406 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2407                 unsigned long entry, unsigned long exit,
2408                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
2409                 u64 guest_val, u64 host_val)
2410 {
2411         vmcs_write64(guest_val_vmcs, guest_val);
2412         vmcs_write64(host_val_vmcs, host_val);
2413         vm_entry_controls_setbit(vmx, entry);
2414         vm_exit_controls_setbit(vmx, exit);
2415 }
2416
2417 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
2418                                   u64 guest_val, u64 host_val)
2419 {
2420         unsigned i;
2421         struct msr_autoload *m = &vmx->msr_autoload;
2422
2423         switch (msr) {
2424         case MSR_EFER:
2425                 if (cpu_has_load_ia32_efer) {
2426                         add_atomic_switch_msr_special(vmx,
2427                                         VM_ENTRY_LOAD_IA32_EFER,
2428                                         VM_EXIT_LOAD_IA32_EFER,
2429                                         GUEST_IA32_EFER,
2430                                         HOST_IA32_EFER,
2431                                         guest_val, host_val);
2432                         return;
2433                 }
2434                 break;
2435         case MSR_CORE_PERF_GLOBAL_CTRL:
2436                 if (cpu_has_load_perf_global_ctrl) {
2437                         add_atomic_switch_msr_special(vmx,
2438                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2439                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2440                                         GUEST_IA32_PERF_GLOBAL_CTRL,
2441                                         HOST_IA32_PERF_GLOBAL_CTRL,
2442                                         guest_val, host_val);
2443                         return;
2444                 }
2445                 break;
2446         case MSR_IA32_PEBS_ENABLE:
2447                 /* PEBS needs a quiescent period after being disabled (to write
2448                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
2449                  * provide that period, so a CPU could write host's record into
2450                  * guest's memory.
2451                  */
2452                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2453         }
2454
2455         for (i = 0; i < m->nr; ++i)
2456                 if (m->guest[i].index == msr)
2457                         break;
2458
2459         if (i == NR_AUTOLOAD_MSRS) {
2460                 printk_once(KERN_WARNING "Not enough msr switch entries. "
2461                                 "Can't add msr %x\n", msr);
2462                 return;
2463         } else if (i == m->nr) {
2464                 ++m->nr;
2465                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2466                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2467         }
2468
2469         m->guest[i].index = msr;
2470         m->guest[i].value = guest_val;
2471         m->host[i].index = msr;
2472         m->host[i].value = host_val;
2473 }
2474
2475 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2476 {
2477         u64 guest_efer = vmx->vcpu.arch.efer;
2478         u64 ignore_bits = 0;
2479
2480         if (!enable_ept) {
2481                 /*
2482                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2483                  * host CPUID is more efficient than testing guest CPUID
2484                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2485                  */
2486                 if (boot_cpu_has(X86_FEATURE_SMEP))
2487                         guest_efer |= EFER_NX;
2488                 else if (!(guest_efer & EFER_NX))
2489                         ignore_bits |= EFER_NX;
2490         }
2491
2492         /*
2493          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2494          */
2495         ignore_bits |= EFER_SCE;
2496 #ifdef CONFIG_X86_64
2497         ignore_bits |= EFER_LMA | EFER_LME;
2498         /* SCE is meaningful only in long mode on Intel */
2499         if (guest_efer & EFER_LMA)
2500                 ignore_bits &= ~(u64)EFER_SCE;
2501 #endif
2502
2503         clear_atomic_switch_msr(vmx, MSR_EFER);
2504
2505         /*
2506          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2507          * On CPUs that support "load IA32_EFER", always switch EFER
2508          * atomically, since it's faster than switching it manually.
2509          */
2510         if (cpu_has_load_ia32_efer ||
2511             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2512                 if (!(guest_efer & EFER_LMA))
2513                         guest_efer &= ~EFER_LME;
2514                 if (guest_efer != host_efer)
2515                         add_atomic_switch_msr(vmx, MSR_EFER,
2516                                               guest_efer, host_efer);
2517                 return false;
2518         } else {
2519                 guest_efer &= ~ignore_bits;
2520                 guest_efer |= host_efer & ignore_bits;
2521
2522                 vmx->guest_msrs[efer_offset].data = guest_efer;
2523                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2524
2525                 return true;
2526         }
2527 }
2528
2529 #ifdef CONFIG_X86_32
2530 /*
2531  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2532  * VMCS rather than the segment table.  KVM uses this helper to figure
2533  * out the current bases to poke them into the VMCS before entry.
2534  */
2535 static unsigned long segment_base(u16 selector)
2536 {
2537         struct desc_struct *table;
2538         unsigned long v;
2539
2540         if (!(selector & ~SEGMENT_RPL_MASK))
2541                 return 0;
2542
2543         table = get_current_gdt_ro();
2544
2545         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2546                 u16 ldt_selector = kvm_read_ldt();
2547
2548                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2549                         return 0;
2550
2551                 table = (struct desc_struct *)segment_base(ldt_selector);
2552         }
2553         v = get_desc_base(&table[selector >> 3]);
2554         return v;
2555 }
2556 #endif
2557
2558 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2559 {
2560         struct vcpu_vmx *vmx = to_vmx(vcpu);
2561 #ifdef CONFIG_X86_64
2562         int cpu = raw_smp_processor_id();
2563 #endif
2564         int i;
2565
2566         if (vmx->host_state.loaded)
2567                 return;
2568
2569         vmx->host_state.loaded = 1;
2570         /*
2571          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2572          * allow segment selectors with cpl > 0 or ti == 1.
2573          */
2574         vmx->host_state.ldt_sel = kvm_read_ldt();
2575         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2576
2577 #ifdef CONFIG_X86_64
2578         save_fsgs_for_kvm();
2579         vmx->host_state.fs_sel = current->thread.fsindex;
2580         vmx->host_state.gs_sel = current->thread.gsindex;
2581 #else
2582         savesegment(fs, vmx->host_state.fs_sel);
2583         savesegment(gs, vmx->host_state.gs_sel);
2584 #endif
2585         if (!(vmx->host_state.fs_sel & 7)) {
2586                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2587                 vmx->host_state.fs_reload_needed = 0;
2588         } else {
2589                 vmcs_write16(HOST_FS_SELECTOR, 0);
2590                 vmx->host_state.fs_reload_needed = 1;
2591         }
2592         if (!(vmx->host_state.gs_sel & 7))
2593                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2594         else {
2595                 vmcs_write16(HOST_GS_SELECTOR, 0);
2596                 vmx->host_state.gs_ldt_reload_needed = 1;
2597         }
2598
2599 #ifdef CONFIG_X86_64
2600         savesegment(ds, vmx->host_state.ds_sel);
2601         savesegment(es, vmx->host_state.es_sel);
2602
2603         vmcs_writel(HOST_FS_BASE, current->thread.fsbase);
2604         vmcs_writel(HOST_GS_BASE, cpu_kernelmode_gs_base(cpu));
2605
2606         vmx->msr_host_kernel_gs_base = current->thread.gsbase;
2607         if (is_long_mode(&vmx->vcpu))
2608                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2609 #else
2610         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2611         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2612 #endif
2613         if (boot_cpu_has(X86_FEATURE_MPX))
2614                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2615         for (i = 0; i < vmx->save_nmsrs; ++i)
2616                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2617                                    vmx->guest_msrs[i].data,
2618                                    vmx->guest_msrs[i].mask);
2619 }
2620
2621 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2622 {
2623         if (!vmx->host_state.loaded)
2624                 return;
2625
2626         ++vmx->vcpu.stat.host_state_reload;
2627         vmx->host_state.loaded = 0;
2628 #ifdef CONFIG_X86_64
2629         if (is_long_mode(&vmx->vcpu))
2630                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2631 #endif
2632         if (vmx->host_state.gs_ldt_reload_needed) {
2633                 kvm_load_ldt(vmx->host_state.ldt_sel);
2634 #ifdef CONFIG_X86_64
2635                 load_gs_index(vmx->host_state.gs_sel);
2636 #else
2637                 loadsegment(gs, vmx->host_state.gs_sel);
2638 #endif
2639         }
2640         if (vmx->host_state.fs_reload_needed)
2641                 loadsegment(fs, vmx->host_state.fs_sel);
2642 #ifdef CONFIG_X86_64
2643         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2644                 loadsegment(ds, vmx->host_state.ds_sel);
2645                 loadsegment(es, vmx->host_state.es_sel);
2646         }
2647 #endif
2648         invalidate_tss_limit();
2649 #ifdef CONFIG_X86_64
2650         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2651 #endif
2652         if (vmx->host_state.msr_host_bndcfgs)
2653                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2654         load_fixmap_gdt(raw_smp_processor_id());
2655 }
2656
2657 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2658 {
2659         preempt_disable();
2660         __vmx_load_host_state(vmx);
2661         preempt_enable();
2662 }
2663
2664 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2665 {
2666         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2667         struct pi_desc old, new;
2668         unsigned int dest;
2669
2670         /*
2671          * In case of hot-plug or hot-unplug, we may have to undo
2672          * vmx_vcpu_pi_put even if there is no assigned device.  And we
2673          * always keep PI.NDST up to date for simplicity: it makes the
2674          * code easier, and CPU migration is not a fast path.
2675          */
2676         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2677                 return;
2678
2679         /*
2680          * First handle the simple case where no cmpxchg is necessary; just
2681          * allow posting non-urgent interrupts.
2682          *
2683          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2684          * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2685          * expects the VCPU to be on the blocked_vcpu_list that matches
2686          * PI.NDST.
2687          */
2688         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2689             vcpu->cpu == cpu) {
2690                 pi_clear_sn(pi_desc);
2691                 return;
2692         }
2693
2694         /* The full case.  */
2695         do {
2696                 old.control = new.control = pi_desc->control;
2697
2698                 dest = cpu_physical_id(cpu);
2699
2700                 if (x2apic_enabled())
2701                         new.ndst = dest;
2702                 else
2703                         new.ndst = (dest << 8) & 0xFF00;
2704
2705                 new.sn = 0;
2706         } while (cmpxchg64(&pi_desc->control, old.control,
2707                            new.control) != old.control);
2708 }
2709
2710 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2711 {
2712         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2713         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2714 }
2715
2716 /*
2717  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2718  * vcpu mutex is already taken.
2719  */
2720 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2721 {
2722         struct vcpu_vmx *vmx = to_vmx(vcpu);
2723         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2724
2725         if (!already_loaded) {
2726                 loaded_vmcs_clear(vmx->loaded_vmcs);
2727                 local_irq_disable();
2728                 crash_disable_local_vmclear(cpu);
2729
2730                 /*
2731                  * Read loaded_vmcs->cpu should be before fetching
2732                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2733                  * See the comments in __loaded_vmcs_clear().
2734                  */
2735                 smp_rmb();
2736
2737                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2738                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2739                 crash_enable_local_vmclear(cpu);
2740                 local_irq_enable();
2741         }
2742
2743         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2744                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2745                 vmcs_load(vmx->loaded_vmcs->vmcs);
2746                 indirect_branch_prediction_barrier();
2747         }
2748
2749         if (!already_loaded) {
2750                 void *gdt = get_current_gdt_ro();
2751                 unsigned long sysenter_esp;
2752
2753                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2754
2755                 /*
2756                  * Linux uses per-cpu TSS and GDT, so set these when switching
2757                  * processors.  See 22.2.4.
2758                  */
2759                 vmcs_writel(HOST_TR_BASE,
2760                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
2761                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
2762
2763                 /*
2764                  * VM exits change the host TR limit to 0x67 after a VM
2765                  * exit.  This is okay, since 0x67 covers everything except
2766                  * the IO bitmap and have have code to handle the IO bitmap
2767                  * being lost after a VM exit.
2768                  */
2769                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2770
2771                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2772                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2773
2774                 vmx->loaded_vmcs->cpu = cpu;
2775         }
2776
2777         /* Setup TSC multiplier */
2778         if (kvm_has_tsc_control &&
2779             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2780                 decache_tsc_multiplier(vmx);
2781
2782         vmx_vcpu_pi_load(vcpu, cpu);
2783         vmx->host_pkru = read_pkru();
2784         vmx->host_debugctlmsr = get_debugctlmsr();
2785 }
2786
2787 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2788 {
2789         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2790
2791         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2792                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2793                 !kvm_vcpu_apicv_active(vcpu))
2794                 return;
2795
2796         /* Set SN when the vCPU is preempted */
2797         if (vcpu->preempted)
2798                 pi_set_sn(pi_desc);
2799 }
2800
2801 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2802 {
2803         vmx_vcpu_pi_put(vcpu);
2804
2805         __vmx_load_host_state(to_vmx(vcpu));
2806 }
2807
2808 static bool emulation_required(struct kvm_vcpu *vcpu)
2809 {
2810         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2811 }
2812
2813 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2814
2815 /*
2816  * Return the cr0 value that a nested guest would read. This is a combination
2817  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2818  * its hypervisor (cr0_read_shadow).
2819  */
2820 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2821 {
2822         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2823                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2824 }
2825 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2826 {
2827         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2828                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2829 }
2830
2831 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2832 {
2833         unsigned long rflags, save_rflags;
2834
2835         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2836                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2837                 rflags = vmcs_readl(GUEST_RFLAGS);
2838                 if (to_vmx(vcpu)->rmode.vm86_active) {
2839                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2840                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2841                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2842                 }
2843                 to_vmx(vcpu)->rflags = rflags;
2844         }
2845         return to_vmx(vcpu)->rflags;
2846 }
2847
2848 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2849 {
2850         unsigned long old_rflags = vmx_get_rflags(vcpu);
2851
2852         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2853         to_vmx(vcpu)->rflags = rflags;
2854         if (to_vmx(vcpu)->rmode.vm86_active) {
2855                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2856                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2857         }
2858         vmcs_writel(GUEST_RFLAGS, rflags);
2859
2860         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2861                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2862 }
2863
2864 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2865 {
2866         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2867         int ret = 0;
2868
2869         if (interruptibility & GUEST_INTR_STATE_STI)
2870                 ret |= KVM_X86_SHADOW_INT_STI;
2871         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2872                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2873
2874         return ret;
2875 }
2876
2877 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2878 {
2879         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2880         u32 interruptibility = interruptibility_old;
2881
2882         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2883
2884         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2885                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2886         else if (mask & KVM_X86_SHADOW_INT_STI)
2887                 interruptibility |= GUEST_INTR_STATE_STI;
2888
2889         if ((interruptibility != interruptibility_old))
2890                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2891 }
2892
2893 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2894 {
2895         unsigned long rip;
2896
2897         rip = kvm_rip_read(vcpu);
2898         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2899         kvm_rip_write(vcpu, rip);
2900
2901         /* skipping an emulated instruction also counts */
2902         vmx_set_interrupt_shadow(vcpu, 0);
2903 }
2904
2905 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2906                                                unsigned long exit_qual)
2907 {
2908         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2909         unsigned int nr = vcpu->arch.exception.nr;
2910         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2911
2912         if (vcpu->arch.exception.has_error_code) {
2913                 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2914                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2915         }
2916
2917         if (kvm_exception_is_soft(nr))
2918                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2919         else
2920                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2921
2922         if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2923             vmx_get_nmi_mask(vcpu))
2924                 intr_info |= INTR_INFO_UNBLOCK_NMI;
2925
2926         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2927 }
2928
2929 /*
2930  * KVM wants to inject page-faults which it got to the guest. This function
2931  * checks whether in a nested guest, we need to inject them to L1 or L2.
2932  */
2933 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
2934 {
2935         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2936         unsigned int nr = vcpu->arch.exception.nr;
2937
2938         if (nr == PF_VECTOR) {
2939                 if (vcpu->arch.exception.nested_apf) {
2940                         *exit_qual = vcpu->arch.apf.nested_apf_token;
2941                         return 1;
2942                 }
2943                 /*
2944                  * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2945                  * The fix is to add the ancillary datum (CR2 or DR6) to structs
2946                  * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2947                  * can be written only when inject_pending_event runs.  This should be
2948                  * conditional on a new capability---if the capability is disabled,
2949                  * kvm_multiple_exception would write the ancillary information to
2950                  * CR2 or DR6, for backwards ABI-compatibility.
2951                  */
2952                 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2953                                                     vcpu->arch.exception.error_code)) {
2954                         *exit_qual = vcpu->arch.cr2;
2955                         return 1;
2956                 }
2957         } else {
2958                 if (vmcs12->exception_bitmap & (1u << nr)) {
2959                         if (nr == DB_VECTOR)
2960                                 *exit_qual = vcpu->arch.dr6;
2961                         else
2962                                 *exit_qual = 0;
2963                         return 1;
2964                 }
2965         }
2966
2967         return 0;
2968 }
2969
2970 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
2971 {
2972         /*
2973          * Ensure that we clear the HLT state in the VMCS.  We don't need to
2974          * explicitly skip the instruction because if the HLT state is set,
2975          * then the instruction is already executing and RIP has already been
2976          * advanced.
2977          */
2978         if (kvm_hlt_in_guest(vcpu->kvm) &&
2979                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
2980                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
2981 }
2982
2983 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2984 {
2985         struct vcpu_vmx *vmx = to_vmx(vcpu);
2986         unsigned nr = vcpu->arch.exception.nr;
2987         bool has_error_code = vcpu->arch.exception.has_error_code;
2988         u32 error_code = vcpu->arch.exception.error_code;
2989         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2990
2991         if (has_error_code) {
2992                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2993                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2994         }
2995
2996         if (vmx->rmode.vm86_active) {
2997                 int inc_eip = 0;
2998                 if (kvm_exception_is_soft(nr))
2999                         inc_eip = vcpu->arch.event_exit_inst_len;
3000                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
3001                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3002                 return;
3003         }
3004
3005         WARN_ON_ONCE(vmx->emulation_required);
3006
3007         if (kvm_exception_is_soft(nr)) {
3008                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3009                              vmx->vcpu.arch.event_exit_inst_len);
3010                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3011         } else
3012                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3013
3014         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
3015
3016         vmx_clear_hlt(vcpu);
3017 }
3018
3019 static bool vmx_rdtscp_supported(void)
3020 {
3021         return cpu_has_vmx_rdtscp();
3022 }
3023
3024 static bool vmx_invpcid_supported(void)
3025 {
3026         return cpu_has_vmx_invpcid() && enable_ept;
3027 }
3028
3029 /*
3030  * Swap MSR entry in host/guest MSR entry array.
3031  */
3032 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
3033 {
3034         struct shared_msr_entry tmp;
3035
3036         tmp = vmx->guest_msrs[to];
3037         vmx->guest_msrs[to] = vmx->guest_msrs[from];
3038         vmx->guest_msrs[from] = tmp;
3039 }
3040
3041 /*
3042  * Set up the vmcs to automatically save and restore system
3043  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
3044  * mode, as fiddling with msrs is very expensive.
3045  */
3046 static void setup_msrs(struct vcpu_vmx *vmx)
3047 {
3048         int save_nmsrs, index;
3049
3050         save_nmsrs = 0;
3051 #ifdef CONFIG_X86_64
3052         if (is_long_mode(&vmx->vcpu)) {
3053                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
3054                 if (index >= 0)
3055                         move_msr_up(vmx, index, save_nmsrs++);
3056                 index = __find_msr_index(vmx, MSR_LSTAR);
3057                 if (index >= 0)
3058                         move_msr_up(vmx, index, save_nmsrs++);
3059                 index = __find_msr_index(vmx, MSR_CSTAR);
3060                 if (index >= 0)
3061                         move_msr_up(vmx, index, save_nmsrs++);
3062                 index = __find_msr_index(vmx, MSR_TSC_AUX);
3063                 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
3064                         move_msr_up(vmx, index, save_nmsrs++);
3065                 /*
3066                  * MSR_STAR is only needed on long mode guests, and only
3067                  * if efer.sce is enabled.
3068                  */
3069                 index = __find_msr_index(vmx, MSR_STAR);
3070                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
3071                         move_msr_up(vmx, index, save_nmsrs++);
3072         }
3073 #endif
3074         index = __find_msr_index(vmx, MSR_EFER);
3075         if (index >= 0 && update_transition_efer(vmx, index))
3076                 move_msr_up(vmx, index, save_nmsrs++);
3077
3078         vmx->save_nmsrs = save_nmsrs;
3079
3080         if (cpu_has_vmx_msr_bitmap())
3081                 vmx_update_msr_bitmap(&vmx->vcpu);
3082 }
3083
3084 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
3085 {
3086         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3087
3088         if (is_guest_mode(vcpu) &&
3089             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
3090                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
3091
3092         return vcpu->arch.tsc_offset;
3093 }
3094
3095 /*
3096  * writes 'offset' into guest's timestamp counter offset register
3097  */
3098 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
3099 {
3100         if (is_guest_mode(vcpu)) {
3101                 /*
3102                  * We're here if L1 chose not to trap WRMSR to TSC. According
3103                  * to the spec, this should set L1's TSC; The offset that L1
3104                  * set for L2 remains unchanged, and still needs to be added
3105                  * to the newly set TSC to get L2's TSC.
3106                  */
3107                 struct vmcs12 *vmcs12;
3108                 /* recalculate vmcs02.TSC_OFFSET: */
3109                 vmcs12 = get_vmcs12(vcpu);
3110                 vmcs_write64(TSC_OFFSET, offset +
3111                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
3112                          vmcs12->tsc_offset : 0));
3113         } else {
3114                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
3115                                            vmcs_read64(TSC_OFFSET), offset);
3116                 vmcs_write64(TSC_OFFSET, offset);
3117         }
3118 }
3119
3120 /*
3121  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
3122  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
3123  * all guests if the "nested" module option is off, and can also be disabled
3124  * for a single guest by disabling its VMX cpuid bit.
3125  */
3126 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
3127 {
3128         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
3129 }
3130
3131 /*
3132  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
3133  * returned for the various VMX controls MSRs when nested VMX is enabled.
3134  * The same values should also be used to verify that vmcs12 control fields are
3135  * valid during nested entry from L1 to L2.
3136  * Each of these control msrs has a low and high 32-bit half: A low bit is on
3137  * if the corresponding bit in the (32-bit) control field *must* be on, and a
3138  * bit in the high half is on if the corresponding bit in the control field
3139  * may be on. See also vmx_control_verify().
3140  */
3141 static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv)
3142 {
3143         if (!nested) {
3144                 memset(msrs, 0, sizeof(*msrs));
3145                 return;
3146         }
3147
3148         /*
3149          * Note that as a general rule, the high half of the MSRs (bits in
3150          * the control fields which may be 1) should be initialized by the
3151          * intersection of the underlying hardware's MSR (i.e., features which
3152          * can be supported) and the list of features we want to expose -
3153          * because they are known to be properly supported in our code.
3154          * Also, usually, the low half of the MSRs (bits which must be 1) can
3155          * be set to 0, meaning that L1 may turn off any of these bits. The
3156          * reason is that if one of these bits is necessary, it will appear
3157          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
3158          * fields of vmcs01 and vmcs02, will turn these bits off - and
3159          * nested_vmx_exit_reflected() will not pass related exits to L1.
3160          * These rules have exceptions below.
3161          */
3162
3163         /* pin-based controls */
3164         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
3165                 msrs->pinbased_ctls_low,
3166                 msrs->pinbased_ctls_high);
3167         msrs->pinbased_ctls_low |=
3168                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3169         msrs->pinbased_ctls_high &=
3170                 PIN_BASED_EXT_INTR_MASK |
3171                 PIN_BASED_NMI_EXITING |
3172                 PIN_BASED_VIRTUAL_NMIS |
3173                 (apicv ? PIN_BASED_POSTED_INTR : 0);
3174         msrs->pinbased_ctls_high |=
3175                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3176                 PIN_BASED_VMX_PREEMPTION_TIMER;
3177
3178         /* exit controls */
3179         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
3180                 msrs->exit_ctls_low,
3181                 msrs->exit_ctls_high);
3182         msrs->exit_ctls_low =
3183                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3184
3185         msrs->exit_ctls_high &=
3186 #ifdef CONFIG_X86_64
3187                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
3188 #endif
3189                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
3190         msrs->exit_ctls_high |=
3191                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
3192                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
3193                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
3194
3195         if (kvm_mpx_supported())
3196                 msrs->exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
3197
3198         /* We support free control of debug control saving. */
3199         msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
3200
3201         /* entry controls */
3202         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
3203                 msrs->entry_ctls_low,
3204                 msrs->entry_ctls_high);
3205         msrs->entry_ctls_low =
3206                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3207         msrs->entry_ctls_high &=
3208 #ifdef CONFIG_X86_64
3209                 VM_ENTRY_IA32E_MODE |
3210 #endif
3211                 VM_ENTRY_LOAD_IA32_PAT;
3212         msrs->entry_ctls_high |=
3213                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
3214         if (kvm_mpx_supported())
3215                 msrs->entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
3216
3217         /* We support free control of debug control loading. */
3218         msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
3219
3220         /* cpu-based controls */
3221         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
3222                 msrs->procbased_ctls_low,
3223                 msrs->procbased_ctls_high);
3224         msrs->procbased_ctls_low =
3225                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3226         msrs->procbased_ctls_high &=
3227                 CPU_BASED_VIRTUAL_INTR_PENDING |
3228                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
3229                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
3230                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
3231                 CPU_BASED_CR3_STORE_EXITING |
3232 #ifdef CONFIG_X86_64
3233                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
3234 #endif
3235                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
3236                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
3237                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
3238                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
3239                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3240         /*
3241          * We can allow some features even when not supported by the
3242          * hardware. For example, L1 can specify an MSR bitmap - and we
3243          * can use it to avoid exits to L1 - even when L0 runs L2
3244          * without MSR bitmaps.
3245          */
3246         msrs->procbased_ctls_high |=
3247                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3248                 CPU_BASED_USE_MSR_BITMAPS;
3249
3250         /* We support free control of CR3 access interception. */
3251         msrs->procbased_ctls_low &=
3252                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
3253
3254         /*
3255          * secondary cpu-based controls.  Do not include those that
3256          * depend on CPUID bits, they are added later by vmx_cpuid_update.
3257          */
3258         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
3259                 msrs->secondary_ctls_low,
3260                 msrs->secondary_ctls_high);
3261         msrs->secondary_ctls_low = 0;
3262         msrs->secondary_ctls_high &=
3263                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3264                 SECONDARY_EXEC_DESC |
3265                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3266                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3267                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3268                 SECONDARY_EXEC_WBINVD_EXITING;
3269
3270         if (enable_ept) {
3271                 /* nested EPT: emulate EPT also to L1 */
3272                 msrs->secondary_ctls_high |=
3273                         SECONDARY_EXEC_ENABLE_EPT;
3274                 msrs->ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
3275                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
3276                 if (cpu_has_vmx_ept_execute_only())
3277                         msrs->ept_caps |=
3278                                 VMX_EPT_EXECUTE_ONLY_BIT;
3279                 msrs->ept_caps &= vmx_capability.ept;
3280                 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
3281                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
3282                         VMX_EPT_1GB_PAGE_BIT;
3283                 if (enable_ept_ad_bits) {
3284                         msrs->secondary_ctls_high |=
3285                                 SECONDARY_EXEC_ENABLE_PML;
3286                         msrs->ept_caps |= VMX_EPT_AD_BIT;
3287                 }
3288         }
3289
3290         if (cpu_has_vmx_vmfunc()) {
3291                 msrs->secondary_ctls_high |=
3292                         SECONDARY_EXEC_ENABLE_VMFUNC;
3293                 /*
3294                  * Advertise EPTP switching unconditionally
3295                  * since we emulate it
3296                  */
3297                 if (enable_ept)
3298                         msrs->vmfunc_controls =
3299                                 VMX_VMFUNC_EPTP_SWITCHING;
3300         }
3301
3302         /*
3303          * Old versions of KVM use the single-context version without
3304          * checking for support, so declare that it is supported even
3305          * though it is treated as global context.  The alternative is
3306          * not failing the single-context invvpid, and it is worse.
3307          */
3308         if (enable_vpid) {
3309                 msrs->secondary_ctls_high |=
3310                         SECONDARY_EXEC_ENABLE_VPID;
3311                 msrs->vpid_caps = VMX_VPID_INVVPID_BIT |
3312                         VMX_VPID_EXTENT_SUPPORTED_MASK;
3313         }
3314
3315         if (enable_unrestricted_guest)
3316                 msrs->secondary_ctls_high |=
3317                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
3318
3319         /* miscellaneous data */
3320         rdmsr(MSR_IA32_VMX_MISC,
3321                 msrs->misc_low,
3322                 msrs->misc_high);
3323         msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA;
3324         msrs->misc_low |=
3325                 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
3326                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
3327                 VMX_MISC_ACTIVITY_HLT;
3328         msrs->misc_high = 0;
3329
3330         /*
3331          * This MSR reports some information about VMX support. We
3332          * should return information about the VMX we emulate for the
3333          * guest, and the VMCS structure we give it - not about the
3334          * VMX support of the underlying hardware.
3335          */
3336         msrs->basic =
3337                 VMCS12_REVISION |
3338                 VMX_BASIC_TRUE_CTLS |
3339                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
3340                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
3341
3342         if (cpu_has_vmx_basic_inout())
3343                 msrs->basic |= VMX_BASIC_INOUT;
3344
3345         /*
3346          * These MSRs specify bits which the guest must keep fixed on
3347          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
3348          * We picked the standard core2 setting.
3349          */
3350 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
3351 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
3352         msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON;
3353         msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
3354
3355         /* These MSRs specify bits which the guest must keep fixed off. */
3356         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
3357         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
3358
3359         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
3360         msrs->vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1;
3361 }
3362
3363 /*
3364  * if fixed0[i] == 1: val[i] must be 1
3365  * if fixed1[i] == 0: val[i] must be 0
3366  */
3367 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
3368 {
3369         return ((val & fixed1) | fixed0) == val;
3370 }
3371
3372 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
3373 {
3374         return fixed_bits_valid(control, low, high);
3375 }
3376
3377 static inline u64 vmx_control_msr(u32 low, u32 high)
3378 {
3379         return low | ((u64)high << 32);
3380 }
3381
3382 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
3383 {
3384         superset &= mask;
3385         subset &= mask;
3386
3387         return (superset | subset) == superset;
3388 }
3389
3390 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
3391 {
3392         const u64 feature_and_reserved =
3393                 /* feature (except bit 48; see below) */
3394                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
3395                 /* reserved */
3396                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
3397         u64 vmx_basic = vmx->nested.msrs.basic;
3398
3399         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
3400                 return -EINVAL;
3401
3402         /*
3403          * KVM does not emulate a version of VMX that constrains physical
3404          * addresses of VMX structures (e.g. VMCS) to 32-bits.
3405          */
3406         if (data & BIT_ULL(48))
3407                 return -EINVAL;
3408
3409         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
3410             vmx_basic_vmcs_revision_id(data))
3411                 return -EINVAL;
3412
3413         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
3414                 return -EINVAL;
3415
3416         vmx->nested.msrs.basic = data;
3417         return 0;
3418 }
3419
3420 static int
3421 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3422 {
3423         u64 supported;
3424         u32 *lowp, *highp;
3425
3426         switch (msr_index) {
3427         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3428                 lowp = &vmx->nested.msrs.pinbased_ctls_low;
3429                 highp = &vmx->nested.msrs.pinbased_ctls_high;
3430                 break;
3431         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3432                 lowp = &vmx->nested.msrs.procbased_ctls_low;
3433                 highp = &vmx->nested.msrs.procbased_ctls_high;
3434                 break;
3435         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3436                 lowp = &vmx->nested.msrs.exit_ctls_low;
3437                 highp = &vmx->nested.msrs.exit_ctls_high;
3438                 break;
3439         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3440                 lowp = &vmx->nested.msrs.entry_ctls_low;
3441                 highp = &vmx->nested.msrs.entry_ctls_high;
3442                 break;
3443         case MSR_IA32_VMX_PROCBASED_CTLS2:
3444                 lowp = &vmx->nested.msrs.secondary_ctls_low;
3445                 highp = &vmx->nested.msrs.secondary_ctls_high;
3446                 break;
3447         default:
3448                 BUG();
3449         }
3450
3451         supported = vmx_control_msr(*lowp, *highp);
3452
3453         /* Check must-be-1 bits are still 1. */
3454         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3455                 return -EINVAL;
3456
3457         /* Check must-be-0 bits are still 0. */
3458         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3459                 return -EINVAL;
3460
3461         *lowp = data;
3462         *highp = data >> 32;
3463         return 0;
3464 }
3465
3466 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3467 {
3468         const u64 feature_and_reserved_bits =
3469                 /* feature */
3470                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3471                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3472                 /* reserved */
3473                 GENMASK_ULL(13, 9) | BIT_ULL(31);
3474         u64 vmx_misc;
3475
3476         vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
3477                                    vmx->nested.msrs.misc_high);
3478
3479         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3480                 return -EINVAL;
3481
3482         if ((vmx->nested.msrs.pinbased_ctls_high &
3483              PIN_BASED_VMX_PREEMPTION_TIMER) &&
3484             vmx_misc_preemption_timer_rate(data) !=
3485             vmx_misc_preemption_timer_rate(vmx_misc))
3486                 return -EINVAL;
3487
3488         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3489                 return -EINVAL;
3490
3491         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3492                 return -EINVAL;
3493
3494         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3495                 return -EINVAL;
3496
3497         vmx->nested.msrs.misc_low = data;
3498         vmx->nested.msrs.misc_high = data >> 32;
3499
3500         /*
3501          * If L1 has read-only VM-exit information fields, use the
3502          * less permissive vmx_vmwrite_bitmap to specify write
3503          * permissions for the shadow VMCS.
3504          */
3505         if (enable_shadow_vmcs && !nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
3506                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
3507
3508         return 0;
3509 }
3510
3511 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3512 {
3513         u64 vmx_ept_vpid_cap;
3514
3515         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps,
3516                                            vmx->nested.msrs.vpid_caps);
3517
3518         /* Every bit is either reserved or a feature bit. */
3519         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3520                 return -EINVAL;
3521
3522         vmx->nested.msrs.ept_caps = data;
3523         vmx->nested.msrs.vpid_caps = data >> 32;
3524         return 0;
3525 }
3526
3527 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3528 {
3529         u64 *msr;
3530
3531         switch (msr_index) {
3532         case MSR_IA32_VMX_CR0_FIXED0:
3533                 msr = &vmx->nested.msrs.cr0_fixed0;
3534                 break;
3535         case MSR_IA32_VMX_CR4_FIXED0:
3536                 msr = &vmx->nested.msrs.cr4_fixed0;
3537                 break;
3538         default:
3539                 BUG();
3540         }
3541
3542         /*
3543          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3544          * must be 1 in the restored value.
3545          */
3546         if (!is_bitwise_subset(data, *msr, -1ULL))
3547                 return -EINVAL;
3548
3549         *msr = data;
3550         return 0;
3551 }
3552
3553 /*
3554  * Called when userspace is restoring VMX MSRs.
3555  *
3556  * Returns 0 on success, non-0 otherwise.
3557  */
3558 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3559 {
3560         struct vcpu_vmx *vmx = to_vmx(vcpu);
3561
3562         /*
3563          * Don't allow changes to the VMX capability MSRs while the vCPU
3564          * is in VMX operation.
3565          */
3566         if (vmx->nested.vmxon)
3567                 return -EBUSY;
3568
3569         switch (msr_index) {
3570         case MSR_IA32_VMX_BASIC:
3571                 return vmx_restore_vmx_basic(vmx, data);
3572         case MSR_IA32_VMX_PINBASED_CTLS:
3573         case MSR_IA32_VMX_PROCBASED_CTLS:
3574         case MSR_IA32_VMX_EXIT_CTLS:
3575         case MSR_IA32_VMX_ENTRY_CTLS:
3576                 /*
3577                  * The "non-true" VMX capability MSRs are generated from the
3578                  * "true" MSRs, so we do not support restoring them directly.
3579                  *
3580                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3581                  * should restore the "true" MSRs with the must-be-1 bits
3582                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3583                  * DEFAULT SETTINGS".
3584                  */
3585                 return -EINVAL;
3586         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3587         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3588         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3589         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3590         case MSR_IA32_VMX_PROCBASED_CTLS2:
3591                 return vmx_restore_control_msr(vmx, msr_index, data);
3592         case MSR_IA32_VMX_MISC:
3593                 return vmx_restore_vmx_misc(vmx, data);
3594         case MSR_IA32_VMX_CR0_FIXED0:
3595         case MSR_IA32_VMX_CR4_FIXED0:
3596                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3597         case MSR_IA32_VMX_CR0_FIXED1:
3598         case MSR_IA32_VMX_CR4_FIXED1:
3599                 /*
3600                  * These MSRs are generated based on the vCPU's CPUID, so we
3601                  * do not support restoring them directly.
3602                  */
3603                 return -EINVAL;
3604         case MSR_IA32_VMX_EPT_VPID_CAP:
3605                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3606         case MSR_IA32_VMX_VMCS_ENUM:
3607                 vmx->nested.msrs.vmcs_enum = data;
3608                 return 0;
3609         default:
3610                 /*
3611                  * The rest of the VMX capability MSRs do not support restore.
3612                  */
3613                 return -EINVAL;
3614         }
3615 }
3616
3617 /* Returns 0 on success, non-0 otherwise. */
3618 static int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata)
3619 {
3620         switch (msr_index) {
3621         case MSR_IA32_VMX_BASIC:
3622                 *pdata = msrs->basic;
3623                 break;
3624         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3625         case MSR_IA32_VMX_PINBASED_CTLS:
3626                 *pdata = vmx_control_msr(
3627                         msrs->pinbased_ctls_low,
3628                         msrs->pinbased_ctls_high);
3629                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3630                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3631                 break;
3632         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3633         case MSR_IA32_VMX_PROCBASED_CTLS:
3634                 *pdata = vmx_control_msr(
3635                         msrs->procbased_ctls_low,
3636                         msrs->procbased_ctls_high);
3637                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3638                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3639                 break;
3640         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3641         case MSR_IA32_VMX_EXIT_CTLS:
3642                 *pdata = vmx_control_msr(
3643                         msrs->exit_ctls_low,
3644                         msrs->exit_ctls_high);
3645                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3646                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3647                 break;
3648         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3649         case MSR_IA32_VMX_ENTRY_CTLS:
3650                 *pdata = vmx_control_msr(
3651                         msrs->entry_ctls_low,
3652                         msrs->entry_ctls_high);
3653                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3654                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3655                 break;
3656         case MSR_IA32_VMX_MISC:
3657                 *pdata = vmx_control_msr(
3658                         msrs->misc_low,
3659                         msrs->misc_high);
3660                 break;
3661         case MSR_IA32_VMX_CR0_FIXED0:
3662                 *pdata = msrs->cr0_fixed0;
3663                 break;
3664         case MSR_IA32_VMX_CR0_FIXED1:
3665                 *pdata = msrs->cr0_fixed1;
3666                 break;
3667         case MSR_IA32_VMX_CR4_FIXED0:
3668                 *pdata = msrs->cr4_fixed0;
3669                 break;
3670         case MSR_IA32_VMX_CR4_FIXED1:
3671                 *pdata = msrs->cr4_fixed1;
3672                 break;
3673         case MSR_IA32_VMX_VMCS_ENUM:
3674                 *pdata = msrs->vmcs_enum;
3675                 break;
3676         case MSR_IA32_VMX_PROCBASED_CTLS2:
3677                 *pdata = vmx_control_msr(
3678                         msrs->secondary_ctls_low,
3679                         msrs->secondary_ctls_high);
3680                 break;
3681         case MSR_IA32_VMX_EPT_VPID_CAP:
3682                 *pdata = msrs->ept_caps |
3683                         ((u64)msrs->vpid_caps << 32);
3684                 break;
3685         case MSR_IA32_VMX_VMFUNC:
3686                 *pdata = msrs->vmfunc_controls;
3687                 break;
3688         default:
3689                 return 1;
3690         }
3691
3692         return 0;
3693 }
3694
3695 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3696                                                  uint64_t val)
3697 {
3698         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3699
3700         return !(val & ~valid_bits);
3701 }
3702
3703 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
3704 {
3705         switch (msr->index) {
3706         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3707                 if (!nested)
3708                         return 1;
3709                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
3710         default:
3711                 return 1;
3712         }
3713
3714         return 0;
3715 }
3716
3717 /*
3718  * Reads an msr value (of 'msr_index') into 'pdata'.
3719  * Returns 0 on success, non-0 otherwise.
3720  * Assumes vcpu_load() was already called.
3721  */
3722 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3723 {
3724         struct vcpu_vmx *vmx = to_vmx(vcpu);
3725         struct shared_msr_entry *msr;
3726
3727         switch (msr_info->index) {
3728 #ifdef CONFIG_X86_64
3729         case MSR_FS_BASE:
3730                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3731                 break;
3732         case MSR_GS_BASE:
3733                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3734                 break;
3735         case MSR_KERNEL_GS_BASE:
3736                 vmx_load_host_state(vmx);
3737                 msr_info->data = vmx->msr_guest_kernel_gs_base;
3738                 break;
3739 #endif
3740         case MSR_EFER:
3741                 return kvm_get_msr_common(vcpu, msr_info);
3742         case MSR_IA32_SPEC_CTRL:
3743                 if (!msr_info->host_initiated &&
3744                     !guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&
3745                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3746                         return 1;
3747
3748                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
3749                 break;
3750         case MSR_IA32_ARCH_CAPABILITIES:
3751                 if (!msr_info->host_initiated &&
3752                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3753                         return 1;
3754                 msr_info->data = to_vmx(vcpu)->arch_capabilities;
3755                 break;
3756         case MSR_IA32_SYSENTER_CS:
3757                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3758                 break;
3759         case MSR_IA32_SYSENTER_EIP:
3760                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3761                 break;
3762         case MSR_IA32_SYSENTER_ESP:
3763                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3764                 break;
3765         case MSR_IA32_BNDCFGS:
3766                 if (!kvm_mpx_supported() ||
3767                     (!msr_info->host_initiated &&
3768                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3769                         return 1;
3770                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3771                 break;
3772         case MSR_IA32_MCG_EXT_CTL:
3773                 if (!msr_info->host_initiated &&
3774                     !(vmx->msr_ia32_feature_control &
3775                       FEATURE_CONTROL_LMCE))
3776                         return 1;
3777                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3778                 break;
3779         case MSR_IA32_FEATURE_CONTROL:
3780                 msr_info->data = vmx->msr_ia32_feature_control;
3781                 break;
3782         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3783                 if (!nested_vmx_allowed(vcpu))
3784                         return 1;
3785                 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
3786                                        &msr_info->data);
3787         case MSR_IA32_XSS:
3788                 if (!vmx_xsaves_supported())
3789                         return 1;
3790                 msr_info->data = vcpu->arch.ia32_xss;
3791                 break;
3792         case MSR_TSC_AUX:
3793                 if (!msr_info->host_initiated &&
3794                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3795                         return 1;
3796                 /* Otherwise falls through */
3797         default:
3798                 msr = find_msr_entry(vmx, msr_info->index);
3799                 if (msr) {
3800                         msr_info->data = msr->data;
3801                         break;
3802                 }
3803                 return kvm_get_msr_common(vcpu, msr_info);
3804         }
3805
3806         return 0;
3807 }
3808
3809 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3810
3811 /*
3812  * Writes msr value into into the appropriate "register".
3813  * Returns 0 on success, non-0 otherwise.
3814  * Assumes vcpu_load() was already called.
3815  */
3816 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3817 {
3818         struct vcpu_vmx *vmx = to_vmx(vcpu);
3819         struct shared_msr_entry *msr;
3820         int ret = 0;
3821         u32 msr_index = msr_info->index;
3822         u64 data = msr_info->data;
3823
3824         switch (msr_index) {
3825         case MSR_EFER:
3826                 ret = kvm_set_msr_common(vcpu, msr_info);
3827                 break;
3828 #ifdef CONFIG_X86_64
3829         case MSR_FS_BASE:
3830                 vmx_segment_cache_clear(vmx);
3831                 vmcs_writel(GUEST_FS_BASE, data);
3832                 break;
3833         case MSR_GS_BASE:
3834                 vmx_segment_cache_clear(vmx);
3835                 vmcs_writel(GUEST_GS_BASE, data);
3836                 break;
3837         case MSR_KERNEL_GS_BASE:
3838                 vmx_load_host_state(vmx);
3839                 vmx->msr_guest_kernel_gs_base = data;
3840                 break;
3841 #endif
3842         case MSR_IA32_SYSENTER_CS:
3843                 vmcs_write32(GUEST_SYSENTER_CS, data);
3844                 break;
3845         case MSR_IA32_SYSENTER_EIP:
3846                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3847                 break;
3848         case MSR_IA32_SYSENTER_ESP:
3849                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3850                 break;
3851         case MSR_IA32_BNDCFGS:
3852                 if (!kvm_mpx_supported() ||
3853                     (!msr_info->host_initiated &&
3854                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3855                         return 1;
3856                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
3857                     (data & MSR_IA32_BNDCFGS_RSVD))
3858                         return 1;
3859                 vmcs_write64(GUEST_BNDCFGS, data);
3860                 break;
3861         case MSR_IA32_SPEC_CTRL:
3862                 if (!msr_info->host_initiated &&
3863                     !guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&
3864                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3865                         return 1;
3866
3867                 /* The STIBP bit doesn't fault even if it's not advertised */
3868                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP))
3869                         return 1;
3870
3871                 vmx->spec_ctrl = data;
3872
3873                 if (!data)
3874                         break;
3875
3876                 /*
3877                  * For non-nested:
3878                  * When it's written (to non-zero) for the first time, pass
3879                  * it through.
3880                  *
3881                  * For nested:
3882                  * The handling of the MSR bitmap for L2 guests is done in
3883                  * nested_vmx_merge_msr_bitmap. We should not touch the
3884                  * vmcs02.msr_bitmap here since it gets completely overwritten
3885                  * in the merging. We update the vmcs01 here for L1 as well
3886                  * since it will end up touching the MSR anyway now.
3887                  */
3888                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
3889                                               MSR_IA32_SPEC_CTRL,
3890                                               MSR_TYPE_RW);
3891                 break;
3892         case MSR_IA32_PRED_CMD:
3893                 if (!msr_info->host_initiated &&
3894                     !guest_cpuid_has(vcpu, X86_FEATURE_IBPB) &&
3895                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3896                         return 1;
3897
3898                 if (data & ~PRED_CMD_IBPB)
3899                         return 1;
3900
3901                 if (!data)
3902                         break;
3903
3904                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3905
3906                 /*
3907                  * For non-nested:
3908                  * When it's written (to non-zero) for the first time, pass
3909                  * it through.
3910                  *
3911                  * For nested:
3912                  * The handling of the MSR bitmap for L2 guests is done in
3913                  * nested_vmx_merge_msr_bitmap. We should not touch the
3914                  * vmcs02.msr_bitmap here since it gets completely overwritten
3915                  * in the merging.
3916                  */
3917                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
3918                                               MSR_TYPE_W);
3919                 break;
3920         case MSR_IA32_ARCH_CAPABILITIES:
3921                 if (!msr_info->host_initiated)
3922                         return 1;
3923                 vmx->arch_capabilities = data;
3924                 break;
3925         case MSR_IA32_CR_PAT:
3926                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3927                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3928                                 return 1;
3929                         vmcs_write64(GUEST_IA32_PAT, data);
3930                         vcpu->arch.pat = data;
3931                         break;
3932                 }
3933                 ret = kvm_set_msr_common(vcpu, msr_info);
3934                 break;
3935         case MSR_IA32_TSC_ADJUST:
3936                 ret = kvm_set_msr_common(vcpu, msr_info);
3937                 break;
3938         case MSR_IA32_MCG_EXT_CTL:
3939                 if ((!msr_info->host_initiated &&
3940                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3941                        FEATURE_CONTROL_LMCE)) ||
3942                     (data & ~MCG_EXT_CTL_LMCE_EN))
3943                         return 1;
3944                 vcpu->arch.mcg_ext_ctl = data;
3945                 break;
3946         case MSR_IA32_FEATURE_CONTROL:
3947                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3948                     (to_vmx(vcpu)->msr_ia32_feature_control &
3949                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3950                         return 1;
3951                 vmx->msr_ia32_feature_control = data;
3952                 if (msr_info->host_initiated && data == 0)
3953                         vmx_leave_nested(vcpu);
3954                 break;
3955         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3956                 if (!msr_info->host_initiated)
3957                         return 1; /* they are read-only */
3958                 if (!nested_vmx_allowed(vcpu))
3959                         return 1;
3960                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3961         case MSR_IA32_XSS:
3962                 if (!vmx_xsaves_supported())
3963                         return 1;
3964                 /*
3965                  * The only supported bit as of Skylake is bit 8, but
3966                  * it is not supported on KVM.
3967                  */
3968                 if (data != 0)
3969                         return 1;
3970                 vcpu->arch.ia32_xss = data;
3971                 if (vcpu->arch.ia32_xss != host_xss)
3972                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3973                                 vcpu->arch.ia32_xss, host_xss);
3974                 else
3975                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3976                 break;
3977         case MSR_TSC_AUX:
3978                 if (!msr_info->host_initiated &&
3979                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3980                         return 1;
3981                 /* Check reserved bit, higher 32 bits should be zero */
3982                 if ((data >> 32) != 0)
3983                         return 1;
3984                 /* Otherwise falls through */
3985         default:
3986                 msr = find_msr_entry(vmx, msr_index);
3987                 if (msr) {
3988                         u64 old_msr_data = msr->data;
3989                         msr->data = data;
3990                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3991                                 preempt_disable();
3992                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3993                                                          msr->mask);
3994                                 preempt_enable();
3995                                 if (ret)
3996                                         msr->data = old_msr_data;
3997                         }
3998                         break;
3999                 }
4000                 ret = kvm_set_msr_common(vcpu, msr_info);
4001         }
4002
4003         return ret;
4004 }
4005
4006 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
4007 {
4008         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
4009         switch (reg) {
4010         case VCPU_REGS_RSP:
4011                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
4012                 break;
4013         case VCPU_REGS_RIP:
4014                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
4015                 break;
4016         case VCPU_EXREG_PDPTR:
4017                 if (enable_ept)
4018                         ept_save_pdptrs(vcpu);
4019                 break;
4020         default:
4021                 break;
4022         }
4023 }
4024
4025 static __init int cpu_has_kvm_support(void)
4026 {
4027         return cpu_has_vmx();
4028 }
4029
4030 static __init int vmx_disabled_by_bios(void)
4031 {
4032         u64 msr;
4033
4034         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
4035         if (msr & FEATURE_CONTROL_LOCKED) {
4036                 /* launched w/ TXT and VMX disabled */
4037                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4038                         && tboot_enabled())
4039                         return 1;
4040                 /* launched w/o TXT and VMX only enabled w/ TXT */
4041                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4042                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4043                         && !tboot_enabled()) {
4044                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
4045                                 "activate TXT before enabling KVM\n");
4046                         return 1;
4047                 }
4048                 /* launched w/o TXT and VMX disabled */
4049                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4050                         && !tboot_enabled())
4051                         return 1;
4052         }
4053
4054         return 0;
4055 }
4056
4057 static void kvm_cpu_vmxon(u64 addr)
4058 {
4059         cr4_set_bits(X86_CR4_VMXE);
4060         intel_pt_handle_vmx(1);
4061
4062         asm volatile (ASM_VMX_VMXON_RAX
4063                         : : "a"(&addr), "m"(addr)
4064                         : "memory", "cc");
4065 }
4066
4067 static int hardware_enable(void)
4068 {
4069         int cpu = raw_smp_processor_id();
4070         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
4071         u64 old, test_bits;
4072
4073         if (cr4_read_shadow() & X86_CR4_VMXE)
4074                 return -EBUSY;
4075
4076         /*
4077          * This can happen if we hot-added a CPU but failed to allocate
4078          * VP assist page for it.
4079          */
4080         if (static_branch_unlikely(&enable_evmcs) &&
4081             !hv_get_vp_assist_page(cpu))
4082                 return -EFAULT;
4083
4084         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
4085         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
4086         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
4087
4088         /*
4089          * Now we can enable the vmclear operation in kdump
4090          * since the loaded_vmcss_on_cpu list on this cpu
4091          * has been initialized.
4092          *
4093          * Though the cpu is not in VMX operation now, there
4094          * is no problem to enable the vmclear operation
4095          * for the loaded_vmcss_on_cpu list is empty!
4096          */
4097         crash_enable_local_vmclear(cpu);
4098
4099         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
4100
4101         test_bits = FEATURE_CONTROL_LOCKED;
4102         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
4103         if (tboot_enabled())
4104                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
4105
4106         if ((old & test_bits) != test_bits) {
4107                 /* enable and lock */
4108                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
4109         }
4110         kvm_cpu_vmxon(phys_addr);
4111         if (enable_ept)
4112                 ept_sync_global();
4113
4114         return 0;
4115 }
4116
4117 static void vmclear_local_loaded_vmcss(void)
4118 {
4119         int cpu = raw_smp_processor_id();
4120         struct loaded_vmcs *v, *n;
4121
4122         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
4123                                  loaded_vmcss_on_cpu_link)
4124                 __loaded_vmcs_clear(v);
4125 }
4126
4127
4128 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
4129  * tricks.
4130  */
4131 static void kvm_cpu_vmxoff(void)
4132 {
4133         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
4134
4135         intel_pt_handle_vmx(0);
4136         cr4_clear_bits(X86_CR4_VMXE);
4137 }
4138
4139 static void hardware_disable(void)
4140 {
4141         vmclear_local_loaded_vmcss();
4142         kvm_cpu_vmxoff();
4143 }
4144
4145 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
4146                                       u32 msr, u32 *result)
4147 {
4148         u32 vmx_msr_low, vmx_msr_high;
4149         u32 ctl = ctl_min | ctl_opt;
4150
4151         rdmsr(msr, vmx_msr_low, vmx_msr_high);
4152
4153         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
4154         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
4155
4156         /* Ensure minimum (required) set of control bits are supported. */
4157         if (ctl_min & ~ctl)
4158                 return -EIO;
4159
4160         *result = ctl;
4161         return 0;
4162 }
4163
4164 static __init bool allow_1_setting(u32 msr, u32 ctl)
4165 {
4166         u32 vmx_msr_low, vmx_msr_high;
4167
4168         rdmsr(msr, vmx_msr_low, vmx_msr_high);
4169         return vmx_msr_high & ctl;
4170 }
4171
4172 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
4173 {
4174         u32 vmx_msr_low, vmx_msr_high;
4175         u32 min, opt, min2, opt2;
4176         u32 _pin_based_exec_control = 0;
4177         u32 _cpu_based_exec_control = 0;
4178         u32 _cpu_based_2nd_exec_control = 0;
4179         u32 _vmexit_control = 0;
4180         u32 _vmentry_control = 0;
4181
4182         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
4183         min = CPU_BASED_HLT_EXITING |
4184 #ifdef CONFIG_X86_64
4185               CPU_BASED_CR8_LOAD_EXITING |
4186               CPU_BASED_CR8_STORE_EXITING |
4187 #endif
4188               CPU_BASED_CR3_LOAD_EXITING |
4189               CPU_BASED_CR3_STORE_EXITING |
4190               CPU_BASED_UNCOND_IO_EXITING |
4191               CPU_BASED_MOV_DR_EXITING |
4192               CPU_BASED_USE_TSC_OFFSETING |
4193               CPU_BASED_MWAIT_EXITING |
4194               CPU_BASED_MONITOR_EXITING |
4195               CPU_BASED_INVLPG_EXITING |
4196               CPU_BASED_RDPMC_EXITING;
4197
4198         opt = CPU_BASED_TPR_SHADOW |
4199               CPU_BASED_USE_MSR_BITMAPS |
4200               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
4201         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
4202                                 &_cpu_based_exec_control) < 0)
4203                 return -EIO;
4204 #ifdef CONFIG_X86_64
4205         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4206                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
4207                                            ~CPU_BASED_CR8_STORE_EXITING;
4208 #endif
4209         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
4210                 min2 = 0;
4211                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4212                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4213                         SECONDARY_EXEC_WBINVD_EXITING |
4214                         SECONDARY_EXEC_ENABLE_VPID |
4215                         SECONDARY_EXEC_ENABLE_EPT |
4216                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
4217                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
4218                         SECONDARY_EXEC_DESC |
4219                         SECONDARY_EXEC_RDTSCP |
4220                         SECONDARY_EXEC_ENABLE_INVPCID |
4221                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4222                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4223                         SECONDARY_EXEC_SHADOW_VMCS |
4224                         SECONDARY_EXEC_XSAVES |
4225                         SECONDARY_EXEC_RDSEED_EXITING |
4226                         SECONDARY_EXEC_RDRAND_EXITING |
4227                         SECONDARY_EXEC_ENABLE_PML |
4228                         SECONDARY_EXEC_TSC_SCALING |
4229                         SECONDARY_EXEC_ENABLE_VMFUNC;
4230                 if (adjust_vmx_controls(min2, opt2,
4231                                         MSR_IA32_VMX_PROCBASED_CTLS2,
4232                                         &_cpu_based_2nd_exec_control) < 0)
4233                         return -EIO;
4234         }
4235 #ifndef CONFIG_X86_64
4236         if (!(_cpu_based_2nd_exec_control &
4237                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
4238                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
4239 #endif
4240
4241         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4242                 _cpu_based_2nd_exec_control &= ~(
4243                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4244                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4245                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4246
4247         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
4248                 &vmx_capability.ept, &vmx_capability.vpid);
4249
4250         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
4251                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
4252                    enabled */
4253                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
4254                                              CPU_BASED_CR3_STORE_EXITING |
4255                                              CPU_BASED_INVLPG_EXITING);
4256         } else if (vmx_capability.ept) {
4257                 vmx_capability.ept = 0;
4258                 pr_warn_once("EPT CAP should not exist if not support "
4259                                 "1-setting enable EPT VM-execution control\n");
4260         }
4261         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
4262                 vmx_capability.vpid) {
4263                 vmx_capability.vpid = 0;
4264                 pr_warn_once("VPID CAP should not exist if not support "
4265                                 "1-setting enable VPID VM-execution control\n");
4266         }
4267
4268         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
4269 #ifdef CONFIG_X86_64
4270         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
4271 #endif
4272         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
4273                 VM_EXIT_CLEAR_BNDCFGS;
4274         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
4275                                 &_vmexit_control) < 0)
4276                 return -EIO;
4277
4278         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
4279         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
4280                  PIN_BASED_VMX_PREEMPTION_TIMER;
4281         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
4282                                 &_pin_based_exec_control) < 0)
4283                 return -EIO;
4284
4285         if (cpu_has_broken_vmx_preemption_timer())
4286                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4287         if (!(_cpu_based_2nd_exec_control &
4288                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
4289                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
4290
4291         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
4292         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
4293         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
4294                                 &_vmentry_control) < 0)
4295                 return -EIO;
4296
4297         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
4298
4299         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
4300         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
4301                 return -EIO;
4302
4303 #ifdef CONFIG_X86_64
4304         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
4305         if (vmx_msr_high & (1u<<16))
4306                 return -EIO;
4307 #endif
4308
4309         /* Require Write-Back (WB) memory type for VMCS accesses. */
4310         if (((vmx_msr_high >> 18) & 15) != 6)
4311                 return -EIO;
4312
4313         vmcs_conf->size = vmx_msr_high & 0x1fff;
4314         vmcs_conf->order = get_order(vmcs_conf->size);
4315         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
4316
4317         /* KVM supports Enlightened VMCS v1 only */
4318         if (static_branch_unlikely(&enable_evmcs))
4319                 vmcs_conf->revision_id = KVM_EVMCS_VERSION;
4320         else
4321                 vmcs_conf->revision_id = vmx_msr_low;
4322
4323         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
4324         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
4325         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
4326         vmcs_conf->vmexit_ctrl         = _vmexit_control;
4327         vmcs_conf->vmentry_ctrl        = _vmentry_control;
4328
4329         if (static_branch_unlikely(&enable_evmcs))
4330                 evmcs_sanitize_exec_ctrls(vmcs_conf);
4331
4332         cpu_has_load_ia32_efer =
4333                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4334                                 VM_ENTRY_LOAD_IA32_EFER)
4335                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4336                                    VM_EXIT_LOAD_IA32_EFER);
4337
4338         cpu_has_load_perf_global_ctrl =
4339                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4340                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
4341                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4342                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
4343
4344         /*
4345          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
4346          * but due to errata below it can't be used. Workaround is to use
4347          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
4348          *
4349          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
4350          *
4351          * AAK155             (model 26)
4352          * AAP115             (model 30)
4353          * AAT100             (model 37)
4354          * BC86,AAY89,BD102   (model 44)
4355          * BA97               (model 46)
4356          *
4357          */
4358         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
4359                 switch (boot_cpu_data.x86_model) {
4360                 case 26:
4361                 case 30:
4362                 case 37:
4363                 case 44:
4364                 case 46:
4365                         cpu_has_load_perf_global_ctrl = false;
4366                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
4367                                         "does not work properly. Using workaround\n");
4368                         break;
4369                 default:
4370                         break;
4371                 }
4372         }
4373
4374         if (boot_cpu_has(X86_FEATURE_XSAVES))
4375                 rdmsrl(MSR_IA32_XSS, host_xss);
4376
4377         return 0;
4378 }
4379
4380 static struct vmcs *alloc_vmcs_cpu(int cpu)
4381 {
4382         int node = cpu_to_node(cpu);
4383         struct page *pages;
4384         struct vmcs *vmcs;
4385
4386         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
4387         if (!pages)
4388                 return NULL;
4389         vmcs = page_address(pages);
4390         memset(vmcs, 0, vmcs_config.size);
4391         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
4392         return vmcs;
4393 }
4394
4395 static void free_vmcs(struct vmcs *vmcs)
4396 {
4397         free_pages((unsigned long)vmcs, vmcs_config.order);
4398 }
4399
4400 /*
4401  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
4402  */
4403 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4404 {
4405         if (!loaded_vmcs->vmcs)
4406                 return;
4407         loaded_vmcs_clear(loaded_vmcs);
4408         free_vmcs(loaded_vmcs->vmcs);
4409         loaded_vmcs->vmcs = NULL;
4410         if (loaded_vmcs->msr_bitmap)
4411                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
4412         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
4413 }
4414
4415 static struct vmcs *alloc_vmcs(void)
4416 {
4417         return alloc_vmcs_cpu(raw_smp_processor_id());
4418 }
4419
4420 static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4421 {
4422         loaded_vmcs->vmcs = alloc_vmcs();
4423         if (!loaded_vmcs->vmcs)
4424                 return -ENOMEM;
4425
4426         loaded_vmcs->shadow_vmcs = NULL;
4427         loaded_vmcs_init(loaded_vmcs);
4428
4429         if (cpu_has_vmx_msr_bitmap()) {
4430                 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
4431                 if (!loaded_vmcs->msr_bitmap)
4432                         goto out_vmcs;
4433                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
4434
4435                 if (static_branch_unlikely(&enable_evmcs) &&
4436                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
4437                         struct hv_enlightened_vmcs *evmcs =
4438                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
4439
4440                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
4441                 }
4442         }
4443         return 0;
4444
4445 out_vmcs:
4446         free_loaded_vmcs(loaded_vmcs);
4447         return -ENOMEM;
4448 }
4449
4450 static void free_kvm_area(void)
4451 {
4452         int cpu;
4453
4454         for_each_possible_cpu(cpu) {
4455                 free_vmcs(per_cpu(vmxarea, cpu));
4456                 per_cpu(vmxarea, cpu) = NULL;
4457         }
4458 }
4459
4460 enum vmcs_field_width {
4461         VMCS_FIELD_WIDTH_U16 = 0,
4462         VMCS_FIELD_WIDTH_U64 = 1,
4463         VMCS_FIELD_WIDTH_U32 = 2,
4464         VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
4465 };
4466
4467 static inline int vmcs_field_width(unsigned long field)
4468 {
4469         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
4470                 return VMCS_FIELD_WIDTH_U32;
4471         return (field >> 13) & 0x3 ;
4472 }
4473
4474 static inline int vmcs_field_readonly(unsigned long field)
4475 {
4476         return (((field >> 10) & 0x3) == 1);
4477 }
4478
4479 static void init_vmcs_shadow_fields(void)
4480 {
4481         int i, j;
4482
4483         for (i = j = 0; i < max_shadow_read_only_fields; i++) {
4484                 u16 field = shadow_read_only_fields[i];
4485                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4486                     (i + 1 == max_shadow_read_only_fields ||
4487                      shadow_read_only_fields[i + 1] != field + 1))
4488                         pr_err("Missing field from shadow_read_only_field %x\n",
4489                                field + 1);
4490
4491                 clear_bit(field, vmx_vmread_bitmap);
4492 #ifdef CONFIG_X86_64
4493                 if (field & 1)
4494                         continue;
4495 #endif
4496                 if (j < i)
4497                         shadow_read_only_fields[j] = field;
4498                 j++;
4499         }
4500         max_shadow_read_only_fields = j;
4501
4502         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
4503                 u16 field = shadow_read_write_fields[i];
4504                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4505                     (i + 1 == max_shadow_read_write_fields ||
4506                      shadow_read_write_fields[i + 1] != field + 1))
4507                         pr_err("Missing field from shadow_read_write_field %x\n",
4508                                field + 1);
4509
4510                 /*
4511                  * PML and the preemption timer can be emulated, but the
4512                  * processor cannot vmwrite to fields that don't exist
4513                  * on bare metal.
4514                  */
4515                 switch (field) {
4516                 case GUEST_PML_INDEX:
4517                         if (!cpu_has_vmx_pml())
4518                                 continue;
4519                         break;
4520                 case VMX_PREEMPTION_TIMER_VALUE:
4521                         if (!cpu_has_vmx_preemption_timer())
4522                                 continue;
4523                         break;
4524                 case GUEST_INTR_STATUS:
4525                         if (!cpu_has_vmx_apicv())
4526                                 continue;
4527                         break;
4528                 default:
4529                         break;
4530                 }
4531
4532                 clear_bit(field, vmx_vmwrite_bitmap);
4533                 clear_bit(field, vmx_vmread_bitmap);
4534 #ifdef CONFIG_X86_64
4535                 if (field & 1)
4536                         continue;
4537 #endif
4538                 if (j < i)
4539                         shadow_read_write_fields[j] = field;
4540                 j++;
4541         }
4542         max_shadow_read_write_fields = j;
4543 }
4544
4545 static __init int alloc_kvm_area(void)
4546 {
4547         int cpu;
4548
4549         for_each_possible_cpu(cpu) {
4550                 struct vmcs *vmcs;
4551
4552                 vmcs = alloc_vmcs_cpu(cpu);
4553                 if (!vmcs) {
4554                         free_kvm_area();
4555                         return -ENOMEM;
4556                 }
4557
4558                 per_cpu(vmxarea, cpu) = vmcs;
4559         }
4560         return 0;
4561 }
4562
4563 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
4564                 struct kvm_segment *save)
4565 {
4566         if (!emulate_invalid_guest_state) {
4567                 /*
4568                  * CS and SS RPL should be equal during guest entry according
4569                  * to VMX spec, but in reality it is not always so. Since vcpu
4570                  * is in the middle of the transition from real mode to
4571                  * protected mode it is safe to assume that RPL 0 is a good
4572                  * default value.
4573                  */
4574                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4575                         save->selector &= ~SEGMENT_RPL_MASK;
4576                 save->dpl = save->selector & SEGMENT_RPL_MASK;
4577                 save->s = 1;
4578         }
4579         vmx_set_segment(vcpu, save, seg);
4580 }
4581
4582 static void enter_pmode(struct kvm_vcpu *vcpu)
4583 {
4584         unsigned long flags;
4585         struct vcpu_vmx *vmx = to_vmx(vcpu);
4586
4587         /*
4588          * Update real mode segment cache. It may be not up-to-date if sement
4589          * register was written while vcpu was in a guest mode.
4590          */
4591         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4592         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4593         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4594         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4595         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4596         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4597
4598         vmx->rmode.vm86_active = 0;
4599
4600         vmx_segment_cache_clear(vmx);
4601
4602         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4603
4604         flags = vmcs_readl(GUEST_RFLAGS);
4605         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
4606         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
4607         vmcs_writel(GUEST_RFLAGS, flags);
4608
4609         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
4610                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4611
4612         update_exception_bitmap(vcpu);
4613
4614         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4615         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4616         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4617         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4618         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4619         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4620 }
4621
4622 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4623 {
4624         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4625         struct kvm_segment var = *save;
4626
4627         var.dpl = 0x3;
4628         if (seg == VCPU_SREG_CS)
4629                 var.type = 0x3;
4630
4631         if (!emulate_invalid_guest_state) {
4632                 var.selector = var.base >> 4;
4633                 var.base = var.base & 0xffff0;
4634                 var.limit = 0xffff;
4635                 var.g = 0;
4636                 var.db = 0;
4637                 var.present = 1;
4638                 var.s = 1;
4639                 var.l = 0;
4640                 var.unusable = 0;
4641                 var.type = 0x3;
4642                 var.avl = 0;
4643                 if (save->base & 0xf)
4644                         printk_once(KERN_WARNING "kvm: segment base is not "
4645                                         "paragraph aligned when entering "
4646                                         "protected mode (seg=%d)", seg);
4647         }
4648
4649         vmcs_write16(sf->selector, var.selector);
4650         vmcs_writel(sf->base, var.base);
4651         vmcs_write32(sf->limit, var.limit);
4652         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
4653 }
4654
4655 static void enter_rmode(struct kvm_vcpu *vcpu)
4656 {
4657         unsigned long flags;
4658         struct vcpu_vmx *vmx = to_vmx(vcpu);
4659         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
4660
4661         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4662         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4663         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4664         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4665         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4666         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4667         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4668
4669         vmx->rmode.vm86_active = 1;
4670
4671         /*
4672          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4673          * vcpu. Warn the user that an update is overdue.
4674          */
4675         if (!kvm_vmx->tss_addr)
4676                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4677                              "called before entering vcpu\n");
4678
4679         vmx_segment_cache_clear(vmx);
4680
4681         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
4682         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4683         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4684
4685         flags = vmcs_readl(GUEST_RFLAGS);
4686         vmx->rmode.save_rflags = flags;
4687
4688         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4689
4690         vmcs_writel(GUEST_RFLAGS, flags);
4691         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4692         update_exception_bitmap(vcpu);
4693
4694         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4695         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4696         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4697         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4698         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4699         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4700
4701         kvm_mmu_reset_context(vcpu);
4702 }
4703
4704 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4705 {
4706         struct vcpu_vmx *vmx = to_vmx(vcpu);
4707         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4708
4709         if (!msr)
4710                 return;
4711
4712         /*
4713          * Force kernel_gs_base reloading before EFER changes, as control
4714          * of this msr depends on is_long_mode().
4715          */
4716         vmx_load_host_state(to_vmx(vcpu));
4717         vcpu->arch.efer = efer;
4718         if (efer & EFER_LMA) {
4719                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4720                 msr->data = efer;
4721         } else {
4722                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4723
4724                 msr->data = efer & ~EFER_LME;
4725         }
4726         setup_msrs(vmx);
4727 }
4728
4729 #ifdef CONFIG_X86_64
4730
4731 static void enter_lmode(struct kvm_vcpu *vcpu)
4732 {
4733         u32 guest_tr_ar;
4734
4735         vmx_segment_cache_clear(to_vmx(vcpu));
4736
4737         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4738         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4739                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4740                                      __func__);
4741                 vmcs_write32(GUEST_TR_AR_BYTES,
4742                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4743                              | VMX_AR_TYPE_BUSY_64_TSS);
4744         }
4745         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4746 }
4747
4748 static void exit_lmode(struct kvm_vcpu *vcpu)
4749 {
4750         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4751         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4752 }
4753
4754 #endif
4755
4756 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
4757                                 bool invalidate_gpa)
4758 {
4759         if (enable_ept && (invalidate_gpa || !enable_vpid)) {
4760                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4761                         return;
4762                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4763         } else {
4764                 vpid_sync_context(vpid);
4765         }
4766 }
4767
4768 static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
4769 {
4770         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
4771 }
4772
4773 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4774 {
4775         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4776
4777         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4778         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4779 }
4780
4781 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4782 {
4783         if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
4784                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4785         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4786 }
4787
4788 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4789 {
4790         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4791
4792         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4793         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4794 }
4795
4796 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4797 {
4798         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4799
4800         if (!test_bit(VCPU_EXREG_PDPTR,
4801                       (unsigned long *)&vcpu->arch.regs_dirty))
4802                 return;
4803
4804         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4805                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4806                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4807                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4808                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4809         }
4810 }
4811
4812 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4813 {
4814         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4815
4816         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4817                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4818                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4819                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4820                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4821         }
4822
4823         __set_bit(VCPU_EXREG_PDPTR,
4824                   (unsigned long *)&vcpu->arch.regs_avail);
4825         __set_bit(VCPU_EXREG_PDPTR,
4826                   (unsigned long *)&vcpu->arch.regs_dirty);
4827 }
4828
4829 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4830 {
4831         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
4832         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
4833         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4834
4835         if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
4836                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4837             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4838                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4839
4840         return fixed_bits_valid(val, fixed0, fixed1);
4841 }
4842
4843 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4844 {
4845         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
4846         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
4847
4848         return fixed_bits_valid(val, fixed0, fixed1);
4849 }
4850
4851 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4852 {
4853         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0;
4854         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1;
4855
4856         return fixed_bits_valid(val, fixed0, fixed1);
4857 }
4858
4859 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4860 #define nested_guest_cr4_valid  nested_cr4_valid
4861 #define nested_host_cr4_valid   nested_cr4_valid
4862
4863 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4864
4865 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4866                                         unsigned long cr0,
4867                                         struct kvm_vcpu *vcpu)
4868 {
4869         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4870                 vmx_decache_cr3(vcpu);
4871         if (!(cr0 & X86_CR0_PG)) {
4872                 /* From paging/starting to nonpaging */
4873                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4874                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4875                              (CPU_BASED_CR3_LOAD_EXITING |
4876                               CPU_BASED_CR3_STORE_EXITING));
4877                 vcpu->arch.cr0 = cr0;
4878                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4879         } else if (!is_paging(vcpu)) {
4880                 /* From nonpaging to paging */
4881                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4882                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4883                              ~(CPU_BASED_CR3_LOAD_EXITING |
4884                                CPU_BASED_CR3_STORE_EXITING));
4885                 vcpu->arch.cr0 = cr0;
4886                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4887         }
4888
4889         if (!(cr0 & X86_CR0_WP))
4890                 *hw_cr0 &= ~X86_CR0_WP;
4891 }
4892
4893 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4894 {
4895         struct vcpu_vmx *vmx = to_vmx(vcpu);
4896         unsigned long hw_cr0;
4897
4898         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4899         if (enable_unrestricted_guest)
4900                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4901         else {
4902                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4903
4904                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4905                         enter_pmode(vcpu);
4906
4907                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4908                         enter_rmode(vcpu);
4909         }
4910
4911 #ifdef CONFIG_X86_64
4912         if (vcpu->arch.efer & EFER_LME) {
4913                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4914                         enter_lmode(vcpu);
4915                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4916                         exit_lmode(vcpu);
4917         }
4918 #endif
4919
4920         if (enable_ept && !enable_unrestricted_guest)
4921                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4922
4923         vmcs_writel(CR0_READ_SHADOW, cr0);
4924         vmcs_writel(GUEST_CR0, hw_cr0);
4925         vcpu->arch.cr0 = cr0;
4926
4927         /* depends on vcpu->arch.cr0 to be set to a new value */
4928         vmx->emulation_required = emulation_required(vcpu);
4929 }
4930
4931 static int get_ept_level(struct kvm_vcpu *vcpu)
4932 {
4933         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
4934                 return 5;
4935         return 4;
4936 }
4937
4938 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4939 {
4940         u64 eptp = VMX_EPTP_MT_WB;
4941
4942         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
4943
4944         if (enable_ept_ad_bits &&
4945             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4946                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
4947         eptp |= (root_hpa & PAGE_MASK);
4948
4949         return eptp;
4950 }
4951
4952 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4953 {
4954         unsigned long guest_cr3;
4955         u64 eptp;
4956
4957         guest_cr3 = cr3;
4958         if (enable_ept) {
4959                 eptp = construct_eptp(vcpu, cr3);
4960                 vmcs_write64(EPT_POINTER, eptp);
4961                 if (enable_unrestricted_guest || is_paging(vcpu) ||
4962                     is_guest_mode(vcpu))
4963                         guest_cr3 = kvm_read_cr3(vcpu);
4964                 else
4965                         guest_cr3 = to_kvm_vmx(vcpu->kvm)->ept_identity_map_addr;
4966                 ept_load_pdptrs(vcpu);
4967         }
4968
4969         vmx_flush_tlb(vcpu, true);
4970         vmcs_writel(GUEST_CR3, guest_cr3);
4971 }
4972
4973 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4974 {
4975         /*
4976          * Pass through host's Machine Check Enable value to hw_cr4, which
4977          * is in force while we are in guest mode.  Do not let guests control
4978          * this bit, even if host CR4.MCE == 0.
4979          */
4980         unsigned long hw_cr4;
4981
4982         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
4983         if (enable_unrestricted_guest)
4984                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
4985         else if (to_vmx(vcpu)->rmode.vm86_active)
4986                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
4987         else
4988                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
4989
4990         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
4991                 if (cr4 & X86_CR4_UMIP) {
4992                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
4993                                 SECONDARY_EXEC_DESC);
4994                         hw_cr4 &= ~X86_CR4_UMIP;
4995                 } else if (!is_guest_mode(vcpu) ||
4996                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
4997                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
4998                                         SECONDARY_EXEC_DESC);
4999         }
5000
5001         if (cr4 & X86_CR4_VMXE) {
5002                 /*
5003                  * To use VMXON (and later other VMX instructions), a guest
5004                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
5005                  * So basically the check on whether to allow nested VMX
5006                  * is here.
5007                  */
5008                 if (!nested_vmx_allowed(vcpu))
5009                         return 1;
5010         }
5011
5012         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5013                 return 1;
5014
5015         vcpu->arch.cr4 = cr4;
5016
5017         if (!enable_unrestricted_guest) {
5018                 if (enable_ept) {
5019                         if (!is_paging(vcpu)) {
5020                                 hw_cr4 &= ~X86_CR4_PAE;
5021                                 hw_cr4 |= X86_CR4_PSE;
5022                         } else if (!(cr4 & X86_CR4_PAE)) {
5023                                 hw_cr4 &= ~X86_CR4_PAE;
5024                         }
5025                 }
5026
5027                 /*
5028                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
5029                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
5030                  * to be manually disabled when guest switches to non-paging
5031                  * mode.
5032                  *
5033                  * If !enable_unrestricted_guest, the CPU is always running
5034                  * with CR0.PG=1 and CR4 needs to be modified.
5035                  * If enable_unrestricted_guest, the CPU automatically
5036                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
5037                  */
5038                 if (!is_paging(vcpu))
5039                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
5040         }
5041
5042         vmcs_writel(CR4_READ_SHADOW, cr4);
5043         vmcs_writel(GUEST_CR4, hw_cr4);
5044         return 0;
5045 }
5046
5047 static void vmx_get_segment(struct kvm_vcpu *vcpu,
5048                             struct kvm_segment *var, int seg)
5049 {
5050         struct vcpu_vmx *vmx = to_vmx(vcpu);
5051         u32 ar;
5052
5053         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5054                 *var = vmx->rmode.segs[seg];
5055                 if (seg == VCPU_SREG_TR
5056                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
5057                         return;
5058                 var->base = vmx_read_guest_seg_base(vmx, seg);
5059                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
5060                 return;
5061         }
5062         var->base = vmx_read_guest_seg_base(vmx, seg);
5063         var->limit = vmx_read_guest_seg_limit(vmx, seg);
5064         var->selector = vmx_read_guest_seg_selector(vmx, seg);
5065         ar = vmx_read_guest_seg_ar(vmx, seg);
5066         var->unusable = (ar >> 16) & 1;
5067         var->type = ar & 15;
5068         var->s = (ar >> 4) & 1;
5069         var->dpl = (ar >> 5) & 3;
5070         /*
5071          * Some userspaces do not preserve unusable property. Since usable
5072          * segment has to be present according to VMX spec we can use present
5073          * property to amend userspace bug by making unusable segment always
5074          * nonpresent. vmx_segment_access_rights() already marks nonpresent
5075          * segment as unusable.
5076          */
5077         var->present = !var->unusable;
5078         var->avl = (ar >> 12) & 1;
5079         var->l = (ar >> 13) & 1;
5080         var->db = (ar >> 14) & 1;
5081         var->g = (ar >> 15) & 1;
5082 }
5083
5084 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
5085 {
5086         struct kvm_segment s;
5087
5088         if (to_vmx(vcpu)->rmode.vm86_active) {
5089                 vmx_get_segment(vcpu, &s, seg);
5090                 return s.base;
5091         }
5092         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
5093 }
5094
5095 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
5096 {
5097         struct vcpu_vmx *vmx = to_vmx(vcpu);
5098
5099         if (unlikely(vmx->rmode.vm86_active))
5100                 return 0;
5101         else {
5102                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
5103                 return VMX_AR_DPL(ar);
5104         }
5105 }
5106
5107 static u32 vmx_segment_access_rights(struct kvm_segment *var)
5108 {
5109         u32 ar;
5110
5111         if (var->unusable || !var->present)
5112                 ar = 1 << 16;
5113         else {
5114                 ar = var->type & 15;
5115                 ar |= (var->s & 1) << 4;
5116                 ar |= (var->dpl & 3) << 5;
5117                 ar |= (var->present & 1) << 7;
5118                 ar |= (var->avl & 1) << 12;
5119                 ar |= (var->l & 1) << 13;
5120                 ar |= (var->db & 1) << 14;
5121                 ar |= (var->g & 1) << 15;
5122         }
5123
5124         return ar;
5125 }
5126
5127 static void vmx_set_segment(struct kvm_vcpu *vcpu,
5128                             struct kvm_segment *var, int seg)
5129 {
5130         struct vcpu_vmx *vmx = to_vmx(vcpu);
5131         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5132
5133         vmx_segment_cache_clear(vmx);
5134
5135         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5136                 vmx->rmode.segs[seg] = *var;
5137                 if (seg == VCPU_SREG_TR)
5138                         vmcs_write16(sf->selector, var->selector);
5139                 else if (var->s)
5140                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
5141                 goto out;
5142         }
5143
5144         vmcs_writel(sf->base, var->base);
5145         vmcs_write32(sf->limit, var->limit);
5146         vmcs_write16(sf->selector, var->selector);
5147
5148         /*
5149          *   Fix the "Accessed" bit in AR field of segment registers for older
5150          * qemu binaries.
5151          *   IA32 arch specifies that at the time of processor reset the
5152          * "Accessed" bit in the AR field of segment registers is 1. And qemu
5153          * is setting it to 0 in the userland code. This causes invalid guest
5154          * state vmexit when "unrestricted guest" mode is turned on.
5155          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
5156          * tree. Newer qemu binaries with that qemu fix would not need this
5157          * kvm hack.
5158          */
5159         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
5160                 var->type |= 0x1; /* Accessed */
5161
5162         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
5163
5164 out:
5165         vmx->emulation_required = emulation_required(vcpu);
5166 }
5167
5168 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5169 {
5170         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
5171
5172         *db = (ar >> 14) & 1;
5173         *l = (ar >> 13) & 1;
5174 }
5175
5176 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5177 {
5178         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
5179         dt->address = vmcs_readl(GUEST_IDTR_BASE);
5180 }
5181
5182 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5183 {
5184         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
5185         vmcs_writel(GUEST_IDTR_BASE, dt->address);
5186 }
5187
5188 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5189 {
5190         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
5191         dt->address = vmcs_readl(GUEST_GDTR_BASE);
5192 }
5193
5194 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5195 {
5196         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
5197         vmcs_writel(GUEST_GDTR_BASE, dt->address);
5198 }
5199
5200 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
5201 {
5202         struct kvm_segment var;
5203         u32 ar;
5204
5205         vmx_get_segment(vcpu, &var, seg);
5206         var.dpl = 0x3;
5207         if (seg == VCPU_SREG_CS)
5208                 var.type = 0x3;
5209         ar = vmx_segment_access_rights(&var);
5210
5211         if (var.base != (var.selector << 4))
5212                 return false;
5213         if (var.limit != 0xffff)
5214                 return false;
5215         if (ar != 0xf3)
5216                 return false;
5217
5218         return true;
5219 }
5220
5221 static bool code_segment_valid(struct kvm_vcpu *vcpu)
5222 {
5223         struct kvm_segment cs;
5224         unsigned int cs_rpl;
5225
5226         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5227         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
5228
5229         if (cs.unusable)
5230                 return false;
5231         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
5232                 return false;
5233         if (!cs.s)
5234                 return false;
5235         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
5236                 if (cs.dpl > cs_rpl)
5237                         return false;
5238         } else {
5239                 if (cs.dpl != cs_rpl)
5240                         return false;
5241         }
5242         if (!cs.present)
5243                 return false;
5244
5245         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
5246         return true;
5247 }
5248
5249 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
5250 {
5251         struct kvm_segment ss;
5252         unsigned int ss_rpl;
5253
5254         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5255         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
5256
5257         if (ss.unusable)
5258                 return true;
5259         if (ss.type != 3 && ss.type != 7)
5260                 return false;
5261         if (!ss.s)
5262                 return false;
5263         if (ss.dpl != ss_rpl) /* DPL != RPL */
5264                 return false;
5265         if (!ss.present)
5266                 return false;
5267
5268         return true;
5269 }
5270
5271 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
5272 {
5273         struct kvm_segment var;
5274         unsigned int rpl;
5275
5276         vmx_get_segment(vcpu, &var, seg);
5277         rpl = var.selector & SEGMENT_RPL_MASK;
5278
5279         if (var.unusable)
5280                 return true;
5281         if (!var.s)
5282                 return false;
5283         if (!var.present)
5284                 return false;
5285         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
5286                 if (var.dpl < rpl) /* DPL < RPL */
5287                         return false;
5288         }
5289
5290         /* TODO: Add other members to kvm_segment_field to allow checking for other access
5291          * rights flags
5292          */
5293         return true;
5294 }
5295
5296 static bool tr_valid(struct kvm_vcpu *vcpu)
5297 {
5298         struct kvm_segment tr;
5299
5300         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
5301
5302         if (tr.unusable)
5303                 return false;
5304         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
5305                 return false;
5306         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
5307                 return false;
5308         if (!tr.present)
5309                 return false;
5310
5311         return true;
5312 }
5313
5314 static bool ldtr_valid(struct kvm_vcpu *vcpu)
5315 {
5316         struct kvm_segment ldtr;
5317
5318         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
5319
5320         if (ldtr.unusable)
5321                 return true;
5322         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
5323                 return false;
5324         if (ldtr.type != 2)
5325                 return false;
5326         if (!ldtr.present)
5327                 return false;
5328
5329         return true;
5330 }
5331
5332 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
5333 {
5334         struct kvm_segment cs, ss;
5335
5336         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5337         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5338
5339         return ((cs.selector & SEGMENT_RPL_MASK) ==
5340                  (ss.selector & SEGMENT_RPL_MASK));
5341 }
5342
5343 /*
5344  * Check if guest state is valid. Returns true if valid, false if
5345  * not.
5346  * We assume that registers are always usable
5347  */
5348 static bool guest_state_valid(struct kvm_vcpu *vcpu)
5349 {
5350         if (enable_unrestricted_guest)
5351                 return true;
5352
5353         /* real mode guest state checks */
5354         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5355                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
5356                         return false;
5357                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
5358                         return false;
5359                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
5360                         return false;
5361                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
5362                         return false;
5363                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
5364                         return false;
5365                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
5366                         return false;
5367         } else {
5368         /* protected mode guest state checks */
5369                 if (!cs_ss_rpl_check(vcpu))
5370                         return false;
5371                 if (!code_segment_valid(vcpu))
5372                         return false;
5373                 if (!stack_segment_valid(vcpu))
5374                         return false;
5375                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
5376                         return false;
5377                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
5378                         return false;
5379                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
5380                         return false;
5381                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
5382                         return false;
5383                 if (!tr_valid(vcpu))
5384                         return false;
5385                 if (!ldtr_valid(vcpu))
5386                         return false;
5387         }
5388         /* TODO:
5389          * - Add checks on RIP
5390          * - Add checks on RFLAGS
5391          */
5392
5393         return true;
5394 }
5395
5396 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
5397 {
5398         return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
5399 }
5400
5401 static int init_rmode_tss(struct kvm *kvm)
5402 {
5403         gfn_t fn;
5404         u16 data = 0;
5405         int idx, r;
5406
5407         idx = srcu_read_lock(&kvm->srcu);
5408         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
5409         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5410         if (r < 0)
5411                 goto out;
5412         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
5413         r = kvm_write_guest_page(kvm, fn++, &data,
5414                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
5415         if (r < 0)
5416                 goto out;
5417         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
5418         if (r < 0)
5419                 goto out;
5420         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5421         if (r < 0)
5422                 goto out;
5423         data = ~0;
5424         r = kvm_write_guest_page(kvm, fn, &data,
5425                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
5426                                  sizeof(u8));
5427 out:
5428         srcu_read_unlock(&kvm->srcu, idx);
5429         return r;
5430 }
5431
5432 static int init_rmode_identity_map(struct kvm *kvm)
5433 {
5434         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
5435         int i, idx, r = 0;
5436         kvm_pfn_t identity_map_pfn;
5437         u32 tmp;
5438
5439         /* Protect kvm_vmx->ept_identity_pagetable_done. */
5440         mutex_lock(&kvm->slots_lock);
5441
5442         if (likely(kvm_vmx->ept_identity_pagetable_done))
5443                 goto out2;
5444
5445         if (!kvm_vmx->ept_identity_map_addr)
5446                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
5447         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
5448
5449         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
5450                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
5451         if (r < 0)
5452                 goto out2;
5453
5454         idx = srcu_read_lock(&kvm->srcu);
5455         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
5456         if (r < 0)
5457                 goto out;
5458         /* Set up identity-mapping pagetable for EPT in real mode */
5459         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
5460                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
5461                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
5462                 r = kvm_write_guest_page(kvm, identity_map_pfn,
5463                                 &tmp, i * sizeof(tmp), sizeof(tmp));
5464                 if (r < 0)
5465                         goto out;
5466         }
5467         kvm_vmx->ept_identity_pagetable_done = true;
5468
5469 out:
5470         srcu_read_unlock(&kvm->srcu, idx);
5471
5472 out2:
5473         mutex_unlock(&kvm->slots_lock);
5474         return r;
5475 }
5476
5477 static void seg_setup(int seg)
5478 {
5479         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5480         unsigned int ar;
5481
5482         vmcs_write16(sf->selector, 0);
5483         vmcs_writel(sf->base, 0);
5484         vmcs_write32(sf->limit, 0xffff);
5485         ar = 0x93;
5486         if (seg == VCPU_SREG_CS)
5487                 ar |= 0x08; /* code segment */
5488
5489         vmcs_write32(sf->ar_bytes, ar);
5490 }
5491
5492 static int alloc_apic_access_page(struct kvm *kvm)
5493 {
5494         struct page *page;
5495         int r = 0;
5496
5497         mutex_lock(&kvm->slots_lock);
5498         if (kvm->arch.apic_access_page_done)
5499                 goto out;
5500         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
5501                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
5502         if (r)
5503                 goto out;
5504
5505         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
5506         if (is_error_page(page)) {
5507                 r = -EFAULT;
5508                 goto out;
5509         }
5510
5511         /*
5512          * Do not pin the page in memory, so that memory hot-unplug
5513          * is able to migrate it.
5514          */
5515         put_page(page);
5516         kvm->arch.apic_access_page_done = true;
5517 out:
5518         mutex_unlock(&kvm->slots_lock);
5519         return r;
5520 }
5521
5522 static int allocate_vpid(void)
5523 {
5524         int vpid;
5525
5526         if (!enable_vpid)
5527                 return 0;
5528         spin_lock(&vmx_vpid_lock);
5529         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
5530         if (vpid < VMX_NR_VPIDS)
5531                 __set_bit(vpid, vmx_vpid_bitmap);
5532         else
5533                 vpid = 0;
5534         spin_unlock(&vmx_vpid_lock);
5535         return vpid;
5536 }
5537
5538 static void free_vpid(int vpid)
5539 {
5540         if (!enable_vpid || vpid == 0)
5541                 return;
5542         spin_lock(&vmx_vpid_lock);
5543         __clear_bit(vpid, vmx_vpid_bitmap);
5544         spin_unlock(&vmx_vpid_lock);
5545 }
5546
5547 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
5548                                                           u32 msr, int type)
5549 {
5550         int f = sizeof(unsigned long);
5551
5552         if (!cpu_has_vmx_msr_bitmap())
5553                 return;
5554
5555         if (static_branch_unlikely(&enable_evmcs))
5556                 evmcs_touch_msr_bitmap();
5557
5558         /*
5559          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5560          * have the write-low and read-high bitmap offsets the wrong way round.
5561          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5562          */
5563         if (msr <= 0x1fff) {
5564                 if (type & MSR_TYPE_R)
5565                         /* read-low */
5566                         __clear_bit(msr, msr_bitmap + 0x000 / f);
5567
5568                 if (type & MSR_TYPE_W)
5569                         /* write-low */
5570                         __clear_bit(msr, msr_bitmap + 0x800 / f);
5571
5572         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5573                 msr &= 0x1fff;
5574                 if (type & MSR_TYPE_R)
5575                         /* read-high */
5576                         __clear_bit(msr, msr_bitmap + 0x400 / f);
5577
5578                 if (type & MSR_TYPE_W)
5579                         /* write-high */
5580                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
5581
5582         }
5583 }
5584
5585 static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
5586                                                          u32 msr, int type)
5587 {
5588         int f = sizeof(unsigned long);
5589
5590         if (!cpu_has_vmx_msr_bitmap())
5591                 return;
5592
5593         if (static_branch_unlikely(&enable_evmcs))
5594                 evmcs_touch_msr_bitmap();
5595
5596         /*
5597          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5598          * have the write-low and read-high bitmap offsets the wrong way round.
5599          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5600          */
5601         if (msr <= 0x1fff) {
5602                 if (type & MSR_TYPE_R)
5603                         /* read-low */
5604                         __set_bit(msr, msr_bitmap + 0x000 / f);
5605
5606                 if (type & MSR_TYPE_W)
5607                         /* write-low */
5608                         __set_bit(msr, msr_bitmap + 0x800 / f);
5609
5610         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5611                 msr &= 0x1fff;
5612                 if (type & MSR_TYPE_R)
5613                         /* read-high */
5614                         __set_bit(msr, msr_bitmap + 0x400 / f);
5615
5616                 if (type & MSR_TYPE_W)
5617                         /* write-high */
5618                         __set_bit(msr, msr_bitmap + 0xc00 / f);
5619
5620         }
5621 }
5622
5623 static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
5624                                                       u32 msr, int type, bool value)
5625 {
5626         if (value)
5627                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
5628         else
5629                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
5630 }
5631
5632 /*
5633  * If a msr is allowed by L0, we should check whether it is allowed by L1.
5634  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
5635  */
5636 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
5637                                                unsigned long *msr_bitmap_nested,
5638                                                u32 msr, int type)
5639 {
5640         int f = sizeof(unsigned long);
5641
5642         /*
5643          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5644          * have the write-low and read-high bitmap offsets the wrong way round.
5645          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5646          */
5647         if (msr <= 0x1fff) {
5648                 if (type & MSR_TYPE_R &&
5649                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
5650                         /* read-low */
5651                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
5652
5653                 if (type & MSR_TYPE_W &&
5654                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
5655                         /* write-low */
5656                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
5657
5658         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5659                 msr &= 0x1fff;
5660                 if (type & MSR_TYPE_R &&
5661                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
5662                         /* read-high */
5663                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
5664
5665                 if (type & MSR_TYPE_W &&
5666                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
5667                         /* write-high */
5668                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
5669
5670         }
5671 }
5672
5673 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5674 {
5675         u8 mode = 0;
5676
5677         if (cpu_has_secondary_exec_ctrls() &&
5678             (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
5679              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
5680                 mode |= MSR_BITMAP_MODE_X2APIC;
5681                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
5682                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
5683         }
5684
5685         if (is_long_mode(vcpu))
5686                 mode |= MSR_BITMAP_MODE_LM;
5687
5688         return mode;
5689 }
5690
5691 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
5692
5693 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
5694                                          u8 mode)
5695 {
5696         int msr;
5697
5698         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
5699                 unsigned word = msr / BITS_PER_LONG;
5700                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
5701                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
5702         }
5703
5704         if (mode & MSR_BITMAP_MODE_X2APIC) {
5705                 /*
5706                  * TPR reads and writes can be virtualized even if virtual interrupt
5707                  * delivery is not in use.
5708                  */
5709                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
5710                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
5711                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
5712                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
5713                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
5714                 }
5715         }
5716 }
5717
5718 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
5719 {
5720         struct vcpu_vmx *vmx = to_vmx(vcpu);
5721         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
5722         u8 mode = vmx_msr_bitmap_mode(vcpu);
5723         u8 changed = mode ^ vmx->msr_bitmap_mode;
5724
5725         if (!changed)
5726                 return;
5727
5728         vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW,
5729                                   !(mode & MSR_BITMAP_MODE_LM));
5730
5731         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
5732                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
5733
5734         vmx->msr_bitmap_mode = mode;
5735 }
5736
5737 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
5738 {
5739         return enable_apicv;
5740 }
5741
5742 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5743 {
5744         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5745         gfn_t gfn;
5746
5747         /*
5748          * Don't need to mark the APIC access page dirty; it is never
5749          * written to by the CPU during APIC virtualization.
5750          */
5751
5752         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5753                 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5754                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5755         }
5756
5757         if (nested_cpu_has_posted_intr(vmcs12)) {
5758                 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5759                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5760         }
5761 }
5762
5763
5764 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5765 {
5766         struct vcpu_vmx *vmx = to_vmx(vcpu);
5767         int max_irr;
5768         void *vapic_page;
5769         u16 status;
5770
5771         if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5772                 return;
5773
5774         vmx->nested.pi_pending = false;
5775         if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5776                 return;
5777
5778         max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5779         if (max_irr != 256) {
5780                 vapic_page = kmap(vmx->nested.virtual_apic_page);
5781                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
5782                         vapic_page, &max_irr);
5783                 kunmap(vmx->nested.virtual_apic_page);
5784
5785                 status = vmcs_read16(GUEST_INTR_STATUS);
5786                 if ((u8)max_irr > ((u8)status & 0xff)) {
5787                         status &= ~0xff;
5788                         status |= (u8)max_irr;
5789                         vmcs_write16(GUEST_INTR_STATUS, status);
5790                 }
5791         }
5792
5793         nested_mark_vmcs12_pages_dirty(vcpu);
5794 }
5795
5796 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5797                                                      bool nested)
5798 {
5799 #ifdef CONFIG_SMP
5800         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5801
5802         if (vcpu->mode == IN_GUEST_MODE) {
5803                 /*
5804                  * The vector of interrupt to be delivered to vcpu had
5805                  * been set in PIR before this function.
5806                  *
5807                  * Following cases will be reached in this block, and
5808                  * we always send a notification event in all cases as
5809                  * explained below.
5810                  *
5811                  * Case 1: vcpu keeps in non-root mode. Sending a
5812                  * notification event posts the interrupt to vcpu.
5813                  *
5814                  * Case 2: vcpu exits to root mode and is still
5815                  * runnable. PIR will be synced to vIRR before the
5816                  * next vcpu entry. Sending a notification event in
5817                  * this case has no effect, as vcpu is not in root
5818                  * mode.
5819                  *
5820                  * Case 3: vcpu exits to root mode and is blocked.
5821                  * vcpu_block() has already synced PIR to vIRR and
5822                  * never blocks vcpu if vIRR is not cleared. Therefore,
5823                  * a blocked vcpu here does not wait for any requested
5824                  * interrupts in PIR, and sending a notification event
5825                  * which has no effect is safe here.
5826                  */
5827
5828                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5829                 return true;
5830         }
5831 #endif
5832         return false;
5833 }
5834
5835 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5836                                                 int vector)
5837 {
5838         struct vcpu_vmx *vmx = to_vmx(vcpu);
5839
5840         if (is_guest_mode(vcpu) &&
5841             vector == vmx->nested.posted_intr_nv) {
5842                 /*
5843                  * If a posted intr is not recognized by hardware,
5844                  * we will accomplish it in the next vmentry.
5845                  */
5846                 vmx->nested.pi_pending = true;
5847                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5848                 /* the PIR and ON have been set by L1. */
5849                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
5850                         kvm_vcpu_kick(vcpu);
5851                 return 0;
5852         }
5853         return -1;
5854 }
5855 /*
5856  * Send interrupt to vcpu via posted interrupt way.
5857  * 1. If target vcpu is running(non-root mode), send posted interrupt
5858  * notification to vcpu and hardware will sync PIR to vIRR atomically.
5859  * 2. If target vcpu isn't running(root mode), kick it to pick up the
5860  * interrupt from PIR in next vmentry.
5861  */
5862 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5863 {
5864         struct vcpu_vmx *vmx = to_vmx(vcpu);
5865         int r;
5866
5867         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5868         if (!r)
5869                 return;
5870
5871         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5872                 return;
5873
5874         /* If a previous notification has sent the IPI, nothing to do.  */
5875         if (pi_test_and_set_on(&vmx->pi_desc))
5876                 return;
5877
5878         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5879                 kvm_vcpu_kick(vcpu);
5880 }
5881
5882 /*
5883  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5884  * will not change in the lifetime of the guest.
5885  * Note that host-state that does change is set elsewhere. E.g., host-state
5886  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5887  */
5888 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5889 {
5890         u32 low32, high32;
5891         unsigned long tmpl;
5892         struct desc_ptr dt;
5893         unsigned long cr0, cr3, cr4;
5894
5895         cr0 = read_cr0();
5896         WARN_ON(cr0 & X86_CR0_TS);
5897         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5898
5899         /*
5900          * Save the most likely value for this task's CR3 in the VMCS.
5901          * We can't use __get_current_cr3_fast() because we're not atomic.
5902          */
5903         cr3 = __read_cr3();
5904         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
5905         vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5906
5907         /* Save the most likely value for this task's CR4 in the VMCS. */
5908         cr4 = cr4_read_shadow();
5909         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5910         vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5911
5912         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5913 #ifdef CONFIG_X86_64
5914         /*
5915          * Load null selectors, so we can avoid reloading them in
5916          * __vmx_load_host_state(), in case userspace uses the null selectors
5917          * too (the expected case).
5918          */
5919         vmcs_write16(HOST_DS_SELECTOR, 0);
5920         vmcs_write16(HOST_ES_SELECTOR, 0);
5921 #else
5922         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5923         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5924 #endif
5925         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5926         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5927
5928         store_idt(&dt);
5929         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5930         vmx->host_idt_base = dt.address;
5931
5932         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5933
5934         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5935         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5936         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5937         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5938
5939         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5940                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5941                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5942         }
5943 }
5944
5945 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5946 {
5947         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5948         if (enable_ept)
5949                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5950         if (is_guest_mode(&vmx->vcpu))
5951                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5952                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5953         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5954 }
5955
5956 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5957 {
5958         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5959
5960         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5961                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5962
5963         if (!enable_vnmi)
5964                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
5965
5966         /* Enable the preemption timer dynamically */
5967         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5968         return pin_based_exec_ctrl;
5969 }
5970
5971 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5972 {
5973         struct vcpu_vmx *vmx = to_vmx(vcpu);
5974
5975         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5976         if (cpu_has_secondary_exec_ctrls()) {
5977                 if (kvm_vcpu_apicv_active(vcpu))
5978                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5979                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5980                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5981                 else
5982                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5983                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5984                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5985         }
5986
5987         if (cpu_has_vmx_msr_bitmap())
5988                 vmx_update_msr_bitmap(vcpu);
5989 }
5990
5991 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5992 {
5993         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5994
5995         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5996                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5997
5998         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5999                 exec_control &= ~CPU_BASED_TPR_SHADOW;
6000 #ifdef CONFIG_X86_64
6001                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
6002                                 CPU_BASED_CR8_LOAD_EXITING;
6003 #endif
6004         }
6005         if (!enable_ept)
6006                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
6007                                 CPU_BASED_CR3_LOAD_EXITING  |
6008                                 CPU_BASED_INVLPG_EXITING;
6009         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
6010                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
6011                                 CPU_BASED_MONITOR_EXITING);
6012         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
6013                 exec_control &= ~CPU_BASED_HLT_EXITING;
6014         return exec_control;
6015 }
6016
6017 static bool vmx_rdrand_supported(void)
6018 {
6019         return vmcs_config.cpu_based_2nd_exec_ctrl &
6020                 SECONDARY_EXEC_RDRAND_EXITING;
6021 }
6022
6023 static bool vmx_rdseed_supported(void)
6024 {
6025         return vmcs_config.cpu_based_2nd_exec_ctrl &
6026                 SECONDARY_EXEC_RDSEED_EXITING;
6027 }
6028
6029 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
6030 {
6031         struct kvm_vcpu *vcpu = &vmx->vcpu;
6032
6033         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
6034
6035         if (!cpu_need_virtualize_apic_accesses(vcpu))
6036                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6037         if (vmx->vpid == 0)
6038                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
6039         if (!enable_ept) {
6040                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
6041                 enable_unrestricted_guest = 0;
6042                 /* Enable INVPCID for non-ept guests may cause performance regression. */
6043                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6044         }
6045         if (!enable_unrestricted_guest)
6046                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
6047         if (kvm_pause_in_guest(vmx->vcpu.kvm))
6048                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
6049         if (!kvm_vcpu_apicv_active(vcpu))
6050                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
6051                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6052         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6053
6054         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
6055          * in vmx_set_cr4.  */
6056         exec_control &= ~SECONDARY_EXEC_DESC;
6057
6058         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
6059            (handle_vmptrld).
6060            We can NOT enable shadow_vmcs here because we don't have yet
6061            a current VMCS12
6062         */
6063         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6064
6065         if (!enable_pml)
6066                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
6067
6068         if (vmx_xsaves_supported()) {
6069                 /* Exposing XSAVES only when XSAVE is exposed */
6070                 bool xsaves_enabled =
6071                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
6072                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
6073
6074                 if (!xsaves_enabled)
6075                         exec_control &= ~SECONDARY_EXEC_XSAVES;
6076
6077                 if (nested) {
6078                         if (xsaves_enabled)
6079                                 vmx->nested.msrs.secondary_ctls_high |=
6080                                         SECONDARY_EXEC_XSAVES;
6081                         else
6082                                 vmx->nested.msrs.secondary_ctls_high &=
6083                                         ~SECONDARY_EXEC_XSAVES;
6084                 }
6085         }
6086
6087         if (vmx_rdtscp_supported()) {
6088                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
6089                 if (!rdtscp_enabled)
6090                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6091
6092                 if (nested) {
6093                         if (rdtscp_enabled)
6094                                 vmx->nested.msrs.secondary_ctls_high |=
6095                                         SECONDARY_EXEC_RDTSCP;
6096                         else
6097                                 vmx->nested.msrs.secondary_ctls_high &=
6098                                         ~SECONDARY_EXEC_RDTSCP;
6099                 }
6100         }
6101
6102         if (vmx_invpcid_supported()) {
6103                 /* Exposing INVPCID only when PCID is exposed */
6104                 bool invpcid_enabled =
6105                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
6106                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
6107
6108                 if (!invpcid_enabled) {
6109                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6110                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
6111                 }
6112
6113                 if (nested) {
6114                         if (invpcid_enabled)
6115                                 vmx->nested.msrs.secondary_ctls_high |=
6116                                         SECONDARY_EXEC_ENABLE_INVPCID;
6117                         else
6118                                 vmx->nested.msrs.secondary_ctls_high &=
6119                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
6120                 }
6121         }
6122
6123         if (vmx_rdrand_supported()) {
6124                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
6125                 if (rdrand_enabled)
6126                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
6127
6128                 if (nested) {
6129                         if (rdrand_enabled)
6130                                 vmx->nested.msrs.secondary_ctls_high |=
6131                                         SECONDARY_EXEC_RDRAND_EXITING;
6132                         else
6133                                 vmx->nested.msrs.secondary_ctls_high &=
6134                                         ~SECONDARY_EXEC_RDRAND_EXITING;
6135                 }
6136         }
6137
6138         if (vmx_rdseed_supported()) {
6139                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
6140                 if (rdseed_enabled)
6141                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
6142
6143                 if (nested) {
6144                         if (rdseed_enabled)
6145                                 vmx->nested.msrs.secondary_ctls_high |=
6146                                         SECONDARY_EXEC_RDSEED_EXITING;
6147                         else
6148                                 vmx->nested.msrs.secondary_ctls_high &=
6149                                         ~SECONDARY_EXEC_RDSEED_EXITING;
6150                 }
6151         }
6152
6153         vmx->secondary_exec_control = exec_control;
6154 }
6155
6156 static void ept_set_mmio_spte_mask(void)
6157 {
6158         /*
6159          * EPT Misconfigurations can be generated if the value of bits 2:0
6160          * of an EPT paging-structure entry is 110b (write/execute).
6161          */
6162         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
6163                                    VMX_EPT_MISCONFIG_WX_VALUE);
6164 }
6165
6166 #define VMX_XSS_EXIT_BITMAP 0
6167 /*
6168  * Sets up the vmcs for emulated real mode.
6169  */
6170 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
6171 {
6172 #ifdef CONFIG_X86_64
6173         unsigned long a;
6174 #endif
6175         int i;
6176
6177         if (enable_shadow_vmcs) {
6178                 /*
6179                  * At vCPU creation, "VMWRITE to any supported field
6180                  * in the VMCS" is supported, so use the more
6181                  * permissive vmx_vmread_bitmap to specify both read
6182                  * and write permissions for the shadow VMCS.
6183                  */
6184                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
6185                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmread_bitmap));
6186         }
6187         if (cpu_has_vmx_msr_bitmap())
6188                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
6189
6190         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
6191
6192         /* Control */
6193         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6194         vmx->hv_deadline_tsc = -1;
6195
6196         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6197
6198         if (cpu_has_secondary_exec_ctrls()) {
6199                 vmx_compute_secondary_exec_control(vmx);
6200                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6201                              vmx->secondary_exec_control);
6202         }
6203
6204         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
6205                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
6206                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
6207                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
6208                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
6209
6210                 vmcs_write16(GUEST_INTR_STATUS, 0);
6211
6212                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
6213                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
6214         }
6215
6216         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
6217                 vmcs_write32(PLE_GAP, ple_gap);
6218                 vmx->ple_window = ple_window;
6219                 vmx->ple_window_dirty = true;
6220         }
6221
6222         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
6223         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6224         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
6225
6226         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
6227         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
6228         vmx_set_constant_host_state(vmx);
6229 #ifdef CONFIG_X86_64
6230         rdmsrl(MSR_FS_BASE, a);
6231         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
6232         rdmsrl(MSR_GS_BASE, a);
6233         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
6234 #else
6235         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
6236         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6237 #endif
6238
6239         if (cpu_has_vmx_vmfunc())
6240                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
6241
6242         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
6243         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
6244         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
6245         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6246         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6247
6248         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6249                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6250
6251         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6252                 u32 index = vmx_msr_index[i];
6253                 u32 data_low, data_high;
6254                 int j = vmx->nmsrs;
6255
6256                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6257                         continue;
6258                 if (wrmsr_safe(index, data_low, data_high) < 0)
6259                         continue;
6260                 vmx->guest_msrs[j].index = i;
6261                 vmx->guest_msrs[j].data = 0;
6262                 vmx->guest_msrs[j].mask = -1ull;
6263                 ++vmx->nmsrs;
6264         }
6265
6266         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
6267                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, vmx->arch_capabilities);
6268
6269         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6270
6271         /* 22.2.1, 20.8.1 */
6272         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
6273
6274         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
6275         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
6276
6277         set_cr4_guest_host_mask(vmx);
6278
6279         if (vmx_xsaves_supported())
6280                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
6281
6282         if (enable_pml) {
6283                 ASSERT(vmx->pml_pg);
6284                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
6285                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
6286         }
6287 }
6288
6289 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
6290 {
6291         struct vcpu_vmx *vmx = to_vmx(vcpu);
6292         struct msr_data apic_base_msr;
6293         u64 cr0;
6294
6295         vmx->rmode.vm86_active = 0;
6296         vmx->spec_ctrl = 0;
6297
6298         vcpu->arch.microcode_version = 0x100000000ULL;
6299         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
6300         kvm_set_cr8(vcpu, 0);
6301
6302         if (!init_event) {
6303                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
6304                                      MSR_IA32_APICBASE_ENABLE;
6305                 if (kvm_vcpu_is_reset_bsp(vcpu))
6306                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
6307                 apic_base_msr.host_initiated = true;
6308                 kvm_set_apic_base(vcpu, &apic_base_msr);
6309         }
6310
6311         vmx_segment_cache_clear(vmx);
6312
6313         seg_setup(VCPU_SREG_CS);
6314         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
6315         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
6316
6317         seg_setup(VCPU_SREG_DS);
6318         seg_setup(VCPU_SREG_ES);
6319         seg_setup(VCPU_SREG_FS);
6320         seg_setup(VCPU_SREG_GS);
6321         seg_setup(VCPU_SREG_SS);
6322
6323         vmcs_write16(GUEST_TR_SELECTOR, 0);
6324         vmcs_writel(GUEST_TR_BASE, 0);
6325         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
6326         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
6327
6328         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
6329         vmcs_writel(GUEST_LDTR_BASE, 0);
6330         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
6331         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
6332
6333         if (!init_event) {
6334                 vmcs_write32(GUEST_SYSENTER_CS, 0);
6335                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
6336                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
6337                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
6338         }
6339
6340         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6341         kvm_rip_write(vcpu, 0xfff0);
6342
6343         vmcs_writel(GUEST_GDTR_BASE, 0);
6344         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
6345
6346         vmcs_writel(GUEST_IDTR_BASE, 0);
6347         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
6348
6349         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
6350         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
6351         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
6352         if (kvm_mpx_supported())
6353                 vmcs_write64(GUEST_BNDCFGS, 0);
6354
6355         setup_msrs(vmx);
6356
6357         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
6358
6359         if (cpu_has_vmx_tpr_shadow() && !init_event) {
6360                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
6361                 if (cpu_need_tpr_shadow(vcpu))
6362                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
6363                                      __pa(vcpu->arch.apic->regs));
6364                 vmcs_write32(TPR_THRESHOLD, 0);
6365         }
6366
6367         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6368
6369         if (vmx->vpid != 0)
6370                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6371
6372         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
6373         vmx->vcpu.arch.cr0 = cr0;
6374         vmx_set_cr0(vcpu, cr0); /* enter rmode */
6375         vmx_set_cr4(vcpu, 0);
6376         vmx_set_efer(vcpu, 0);
6377
6378         update_exception_bitmap(vcpu);
6379
6380         vpid_sync_context(vmx->vpid);
6381         if (init_event)
6382                 vmx_clear_hlt(vcpu);
6383 }
6384
6385 /*
6386  * In nested virtualization, check if L1 asked to exit on external interrupts.
6387  * For most existing hypervisors, this will always return true.
6388  */
6389 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
6390 {
6391         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
6392                 PIN_BASED_EXT_INTR_MASK;
6393 }
6394
6395 /*
6396  * In nested virtualization, check if L1 has set
6397  * VM_EXIT_ACK_INTR_ON_EXIT
6398  */
6399 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
6400 {
6401         return get_vmcs12(vcpu)->vm_exit_controls &
6402                 VM_EXIT_ACK_INTR_ON_EXIT;
6403 }
6404
6405 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
6406 {
6407         return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu));
6408 }
6409
6410 static void enable_irq_window(struct kvm_vcpu *vcpu)
6411 {
6412         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6413                       CPU_BASED_VIRTUAL_INTR_PENDING);
6414 }
6415
6416 static void enable_nmi_window(struct kvm_vcpu *vcpu)
6417 {
6418         if (!enable_vnmi ||
6419             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
6420                 enable_irq_window(vcpu);
6421                 return;
6422         }
6423
6424         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6425                       CPU_BASED_VIRTUAL_NMI_PENDING);
6426 }
6427
6428 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
6429 {
6430         struct vcpu_vmx *vmx = to_vmx(vcpu);
6431         uint32_t intr;
6432         int irq = vcpu->arch.interrupt.nr;
6433
6434         trace_kvm_inj_virq(irq);
6435
6436         ++vcpu->stat.irq_injections;
6437         if (vmx->rmode.vm86_active) {
6438                 int inc_eip = 0;
6439                 if (vcpu->arch.interrupt.soft)
6440                         inc_eip = vcpu->arch.event_exit_inst_len;
6441                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
6442                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6443                 return;
6444         }
6445         intr = irq | INTR_INFO_VALID_MASK;
6446         if (vcpu->arch.interrupt.soft) {
6447                 intr |= INTR_TYPE_SOFT_INTR;
6448                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6449                              vmx->vcpu.arch.event_exit_inst_len);
6450         } else
6451                 intr |= INTR_TYPE_EXT_INTR;
6452         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
6453
6454         vmx_clear_hlt(vcpu);
6455 }
6456
6457 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
6458 {
6459         struct vcpu_vmx *vmx = to_vmx(vcpu);
6460
6461         if (!enable_vnmi) {
6462                 /*
6463                  * Tracking the NMI-blocked state in software is built upon
6464                  * finding the next open IRQ window. This, in turn, depends on
6465                  * well-behaving guests: They have to keep IRQs disabled at
6466                  * least as long as the NMI handler runs. Otherwise we may
6467                  * cause NMI nesting, maybe breaking the guest. But as this is
6468                  * highly unlikely, we can live with the residual risk.
6469                  */
6470                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
6471                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6472         }
6473
6474         ++vcpu->stat.nmi_injections;
6475         vmx->loaded_vmcs->nmi_known_unmasked = false;
6476
6477         if (vmx->rmode.vm86_active) {
6478                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
6479                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6480                 return;
6481         }
6482
6483         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6484                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
6485
6486         vmx_clear_hlt(vcpu);
6487 }
6488
6489 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
6490 {
6491         struct vcpu_vmx *vmx = to_vmx(vcpu);
6492         bool masked;
6493
6494         if (!enable_vnmi)
6495                 return vmx->loaded_vmcs->soft_vnmi_blocked;
6496         if (vmx->loaded_vmcs->nmi_known_unmasked)
6497                 return false;
6498         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
6499         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6500         return masked;
6501 }
6502
6503 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
6504 {
6505         struct vcpu_vmx *vmx = to_vmx(vcpu);
6506
6507         if (!enable_vnmi) {
6508                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
6509                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
6510                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
6511                 }
6512         } else {
6513                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6514                 if (masked)
6515                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6516                                       GUEST_INTR_STATE_NMI);
6517                 else
6518                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
6519                                         GUEST_INTR_STATE_NMI);
6520         }
6521 }
6522
6523 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
6524 {
6525         if (to_vmx(vcpu)->nested.nested_run_pending)
6526                 return 0;
6527
6528         if (!enable_vnmi &&
6529             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
6530                 return 0;
6531
6532         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6533                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
6534                    | GUEST_INTR_STATE_NMI));
6535 }
6536
6537 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
6538 {
6539         return (!to_vmx(vcpu)->nested.nested_run_pending &&
6540                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
6541                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6542                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
6543 }
6544
6545 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
6546 {
6547         int ret;
6548
6549         if (enable_unrestricted_guest)
6550                 return 0;
6551
6552         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
6553                                     PAGE_SIZE * 3);
6554         if (ret)
6555                 return ret;
6556         to_kvm_vmx(kvm)->tss_addr = addr;
6557         return init_rmode_tss(kvm);
6558 }
6559
6560 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
6561 {
6562         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
6563         return 0;
6564 }
6565
6566 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6567 {
6568         switch (vec) {
6569         case BP_VECTOR:
6570                 /*
6571                  * Update instruction length as we may reinject the exception
6572                  * from user space while in guest debugging mode.
6573                  */
6574                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
6575                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6576                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6577                         return false;
6578                 /* fall through */
6579         case DB_VECTOR:
6580                 if (vcpu->guest_debug &
6581                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6582                         return false;
6583                 /* fall through */
6584         case DE_VECTOR:
6585         case OF_VECTOR:
6586         case BR_VECTOR:
6587         case UD_VECTOR:
6588         case DF_VECTOR:
6589         case SS_VECTOR:
6590         case GP_VECTOR:
6591         case MF_VECTOR:
6592                 return true;
6593         break;
6594         }
6595         return false;
6596 }
6597
6598 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
6599                                   int vec, u32 err_code)
6600 {
6601         /*
6602          * Instruction with address size override prefix opcode 0x67
6603          * Cause the #SS fault with 0 error code in VM86 mode.
6604          */
6605         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
6606                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
6607                         if (vcpu->arch.halt_request) {
6608                                 vcpu->arch.halt_request = 0;
6609                                 return kvm_vcpu_halt(vcpu);
6610                         }
6611                         return 1;
6612                 }
6613                 return 0;
6614         }
6615
6616         /*
6617          * Forward all other exceptions that are valid in real mode.
6618          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
6619          *        the required debugging infrastructure rework.
6620          */
6621         kvm_queue_exception(vcpu, vec);
6622         return 1;
6623 }
6624
6625 /*
6626  * Trigger machine check on the host. We assume all the MSRs are already set up
6627  * by the CPU and that we still run on the same CPU as the MCE occurred on.
6628  * We pass a fake environment to the machine check handler because we want
6629  * the guest to be always treated like user space, no matter what context
6630  * it used internally.
6631  */
6632 static void kvm_machine_check(void)
6633 {
6634 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
6635         struct pt_regs regs = {
6636                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
6637                 .flags = X86_EFLAGS_IF,
6638         };
6639
6640         do_machine_check(&regs, 0);
6641 #endif
6642 }
6643
6644 static int handle_machine_check(struct kvm_vcpu *vcpu)
6645 {
6646         /* already handled by vcpu_run */
6647         return 1;
6648 }
6649
6650 static int handle_exception(struct kvm_vcpu *vcpu)
6651 {
6652         struct vcpu_vmx *vmx = to_vmx(vcpu);
6653         struct kvm_run *kvm_run = vcpu->run;
6654         u32 intr_info, ex_no, error_code;
6655         unsigned long cr2, rip, dr6;
6656         u32 vect_info;
6657         enum emulation_result er;
6658
6659         vect_info = vmx->idt_vectoring_info;
6660         intr_info = vmx->exit_intr_info;
6661
6662         if (is_machine_check(intr_info))
6663                 return handle_machine_check(vcpu);
6664
6665         if (is_nmi(intr_info))
6666                 return 1;  /* already handled by vmx_vcpu_run() */
6667
6668         if (is_invalid_opcode(intr_info))
6669                 return handle_ud(vcpu);
6670
6671         error_code = 0;
6672         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6673                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6674
6675         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
6676                 WARN_ON_ONCE(!enable_vmware_backdoor);
6677                 er = emulate_instruction(vcpu,
6678                         EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
6679                 if (er == EMULATE_USER_EXIT)
6680                         return 0;
6681                 else if (er != EMULATE_DONE)
6682                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
6683                 return 1;
6684         }
6685
6686         /*
6687          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
6688          * MMIO, it is better to report an internal error.
6689          * See the comments in vmx_handle_exit.
6690          */
6691         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
6692             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
6693                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6694                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
6695                 vcpu->run->internal.ndata = 3;
6696                 vcpu->run->internal.data[0] = vect_info;
6697                 vcpu->run->internal.data[1] = intr_info;
6698                 vcpu->run->internal.data[2] = error_code;
6699                 return 0;
6700         }
6701
6702         if (is_page_fault(intr_info)) {
6703                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
6704                 /* EPT won't cause page fault directly */
6705                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
6706                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6707         }
6708
6709         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
6710
6711         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
6712                 return handle_rmode_exception(vcpu, ex_no, error_code);
6713
6714         switch (ex_no) {
6715         case AC_VECTOR:
6716                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
6717                 return 1;
6718         case DB_VECTOR:
6719                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
6720                 if (!(vcpu->guest_debug &
6721                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
6722                         vcpu->arch.dr6 &= ~15;
6723                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
6724                         if (is_icebp(intr_info))
6725                                 skip_emulated_instruction(vcpu);
6726
6727                         kvm_queue_exception(vcpu, DB_VECTOR);
6728                         return 1;
6729                 }
6730                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
6731                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
6732                 /* fall through */
6733         case BP_VECTOR:
6734                 /*
6735                  * Update instruction length as we may reinject #BP from
6736                  * user space while in guest debugging mode. Reading it for
6737                  * #DB as well causes no harm, it is not used in that case.
6738                  */
6739                 vmx->vcpu.arch.event_exit_inst_len =
6740                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6741                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6742                 rip = kvm_rip_read(vcpu);
6743                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
6744                 kvm_run->debug.arch.exception = ex_no;
6745                 break;
6746         default:
6747                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
6748                 kvm_run->ex.exception = ex_no;
6749                 kvm_run->ex.error_code = error_code;
6750                 break;
6751         }
6752         return 0;
6753 }
6754
6755 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6756 {
6757         ++vcpu->stat.irq_exits;
6758         return 1;
6759 }
6760
6761 static int handle_triple_fault(struct kvm_vcpu *vcpu)
6762 {
6763         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6764         vcpu->mmio_needed = 0;
6765         return 0;
6766 }
6767
6768 static int handle_io(struct kvm_vcpu *vcpu)
6769 {
6770         unsigned long exit_qualification;
6771         int size, in, string;
6772         unsigned port;
6773
6774         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6775         string = (exit_qualification & 16) != 0;
6776
6777         ++vcpu->stat.io_exits;
6778
6779         if (string)
6780                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6781
6782         port = exit_qualification >> 16;
6783         size = (exit_qualification & 7) + 1;
6784         in = (exit_qualification & 8) != 0;
6785
6786         return kvm_fast_pio(vcpu, size, port, in);
6787 }
6788
6789 static void
6790 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
6791 {
6792         /*
6793          * Patch in the VMCALL instruction:
6794          */
6795         hypercall[0] = 0x0f;
6796         hypercall[1] = 0x01;
6797         hypercall[2] = 0xc1;
6798 }
6799
6800 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6801 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
6802 {
6803         if (is_guest_mode(vcpu)) {
6804                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6805                 unsigned long orig_val = val;
6806
6807                 /*
6808                  * We get here when L2 changed cr0 in a way that did not change
6809                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6810                  * but did change L0 shadowed bits. So we first calculate the
6811                  * effective cr0 value that L1 would like to write into the
6812                  * hardware. It consists of the L2-owned bits from the new
6813                  * value combined with the L1-owned bits from L1's guest_cr0.
6814                  */
6815                 val = (val & ~vmcs12->cr0_guest_host_mask) |
6816                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
6817
6818                 if (!nested_guest_cr0_valid(vcpu, val))
6819                         return 1;
6820
6821                 if (kvm_set_cr0(vcpu, val))
6822                         return 1;
6823                 vmcs_writel(CR0_READ_SHADOW, orig_val);
6824                 return 0;
6825         } else {
6826                 if (to_vmx(vcpu)->nested.vmxon &&
6827                     !nested_host_cr0_valid(vcpu, val))
6828                         return 1;
6829
6830                 return kvm_set_cr0(vcpu, val);
6831         }
6832 }
6833
6834 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
6835 {
6836         if (is_guest_mode(vcpu)) {
6837                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6838                 unsigned long orig_val = val;
6839
6840                 /* analogously to handle_set_cr0 */
6841                 val = (val & ~vmcs12->cr4_guest_host_mask) |
6842                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
6843                 if (kvm_set_cr4(vcpu, val))
6844                         return 1;
6845                 vmcs_writel(CR4_READ_SHADOW, orig_val);
6846                 return 0;
6847         } else
6848                 return kvm_set_cr4(vcpu, val);
6849 }
6850
6851 static int handle_desc(struct kvm_vcpu *vcpu)
6852 {
6853         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
6854         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6855 }
6856
6857 static int handle_cr(struct kvm_vcpu *vcpu)
6858 {
6859         unsigned long exit_qualification, val;
6860         int cr;
6861         int reg;
6862         int err;
6863         int ret;
6864
6865         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6866         cr = exit_qualification & 15;
6867         reg = (exit_qualification >> 8) & 15;
6868         switch ((exit_qualification >> 4) & 3) {
6869         case 0: /* mov to cr */
6870                 val = kvm_register_readl(vcpu, reg);
6871                 trace_kvm_cr_write(cr, val);
6872                 switch (cr) {
6873                 case 0:
6874                         err = handle_set_cr0(vcpu, val);
6875                         return kvm_complete_insn_gp(vcpu, err);
6876                 case 3:
6877                         WARN_ON_ONCE(enable_unrestricted_guest);
6878                         err = kvm_set_cr3(vcpu, val);
6879                         return kvm_complete_insn_gp(vcpu, err);
6880                 case 4:
6881                         err = handle_set_cr4(vcpu, val);
6882                         return kvm_complete_insn_gp(vcpu, err);
6883                 case 8: {
6884                                 u8 cr8_prev = kvm_get_cr8(vcpu);
6885                                 u8 cr8 = (u8)val;
6886                                 err = kvm_set_cr8(vcpu, cr8);
6887                                 ret = kvm_complete_insn_gp(vcpu, err);
6888                                 if (lapic_in_kernel(vcpu))
6889                                         return ret;
6890                                 if (cr8_prev <= cr8)
6891                                         return ret;
6892                                 /*
6893                                  * TODO: we might be squashing a
6894                                  * KVM_GUESTDBG_SINGLESTEP-triggered
6895                                  * KVM_EXIT_DEBUG here.
6896                                  */
6897                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
6898                                 return 0;
6899                         }
6900                 }
6901                 break;
6902         case 2: /* clts */
6903                 WARN_ONCE(1, "Guest should always own CR0.TS");
6904                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6905                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6906                 return kvm_skip_emulated_instruction(vcpu);
6907         case 1: /*mov from cr*/
6908                 switch (cr) {
6909                 case 3:
6910                         WARN_ON_ONCE(enable_unrestricted_guest);
6911                         val = kvm_read_cr3(vcpu);
6912                         kvm_register_write(vcpu, reg, val);
6913                         trace_kvm_cr_read(cr, val);
6914                         return kvm_skip_emulated_instruction(vcpu);
6915                 case 8:
6916                         val = kvm_get_cr8(vcpu);
6917                         kvm_register_write(vcpu, reg, val);
6918                         trace_kvm_cr_read(cr, val);
6919                         return kvm_skip_emulated_instruction(vcpu);
6920                 }
6921                 break;
6922         case 3: /* lmsw */
6923                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6924                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6925                 kvm_lmsw(vcpu, val);
6926
6927                 return kvm_skip_emulated_instruction(vcpu);
6928         default:
6929                 break;
6930         }
6931         vcpu->run->exit_reason = 0;
6932         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6933                (int)(exit_qualification >> 4) & 3, cr);
6934         return 0;
6935 }
6936
6937 static int handle_dr(struct kvm_vcpu *vcpu)
6938 {
6939         unsigned long exit_qualification;
6940         int dr, dr7, reg;
6941
6942         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6943         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6944
6945         /* First, if DR does not exist, trigger UD */
6946         if (!kvm_require_dr(vcpu, dr))
6947                 return 1;
6948
6949         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6950         if (!kvm_require_cpl(vcpu, 0))
6951                 return 1;
6952         dr7 = vmcs_readl(GUEST_DR7);
6953         if (dr7 & DR7_GD) {
6954                 /*
6955                  * As the vm-exit takes precedence over the debug trap, we
6956                  * need to emulate the latter, either for the host or the
6957                  * guest debugging itself.
6958                  */
6959                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6960                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6961                         vcpu->run->debug.arch.dr7 = dr7;
6962                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6963                         vcpu->run->debug.arch.exception = DB_VECTOR;
6964                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6965                         return 0;
6966                 } else {
6967                         vcpu->arch.dr6 &= ~15;
6968                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6969                         kvm_queue_exception(vcpu, DB_VECTOR);
6970                         return 1;
6971                 }
6972         }
6973
6974         if (vcpu->guest_debug == 0) {
6975                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6976                                 CPU_BASED_MOV_DR_EXITING);
6977
6978                 /*
6979                  * No more DR vmexits; force a reload of the debug registers
6980                  * and reenter on this instruction.  The next vmexit will
6981                  * retrieve the full state of the debug registers.
6982                  */
6983                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6984                 return 1;
6985         }
6986
6987         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6988         if (exit_qualification & TYPE_MOV_FROM_DR) {
6989                 unsigned long val;
6990
6991                 if (kvm_get_dr(vcpu, dr, &val))
6992                         return 1;
6993                 kvm_register_write(vcpu, reg, val);
6994         } else
6995                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6996                         return 1;
6997
6998         return kvm_skip_emulated_instruction(vcpu);
6999 }
7000
7001 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
7002 {
7003         return vcpu->arch.dr6;
7004 }
7005
7006 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
7007 {
7008 }
7009
7010 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
7011 {
7012         get_debugreg(vcpu->arch.db[0], 0);
7013         get_debugreg(vcpu->arch.db[1], 1);
7014         get_debugreg(vcpu->arch.db[2], 2);
7015         get_debugreg(vcpu->arch.db[3], 3);
7016         get_debugreg(vcpu->arch.dr6, 6);
7017         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
7018
7019         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
7020         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
7021 }
7022
7023 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
7024 {
7025         vmcs_writel(GUEST_DR7, val);
7026 }
7027
7028 static int handle_cpuid(struct kvm_vcpu *vcpu)
7029 {
7030         return kvm_emulate_cpuid(vcpu);
7031 }
7032
7033 static int handle_rdmsr(struct kvm_vcpu *vcpu)
7034 {
7035         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7036         struct msr_data msr_info;
7037
7038         msr_info.index = ecx;
7039         msr_info.host_initiated = false;
7040         if (vmx_get_msr(vcpu, &msr_info)) {
7041                 trace_kvm_msr_read_ex(ecx);
7042                 kvm_inject_gp(vcpu, 0);
7043                 return 1;
7044         }
7045
7046         trace_kvm_msr_read(ecx, msr_info.data);
7047
7048         /* FIXME: handling of bits 32:63 of rax, rdx */
7049         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
7050         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
7051         return kvm_skip_emulated_instruction(vcpu);
7052 }
7053
7054 static int handle_wrmsr(struct kvm_vcpu *vcpu)
7055 {
7056         struct msr_data msr;
7057         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7058         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
7059                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
7060
7061         msr.data = data;
7062         msr.index = ecx;
7063         msr.host_initiated = false;
7064         if (kvm_set_msr(vcpu, &msr) != 0) {
7065                 trace_kvm_msr_write_ex(ecx, data);
7066                 kvm_inject_gp(vcpu, 0);
7067                 return 1;
7068         }
7069
7070         trace_kvm_msr_write(ecx, data);
7071         return kvm_skip_emulated_instruction(vcpu);
7072 }
7073
7074 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
7075 {
7076         kvm_apic_update_ppr(vcpu);
7077         return 1;
7078 }
7079
7080 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
7081 {
7082         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7083                         CPU_BASED_VIRTUAL_INTR_PENDING);
7084
7085         kvm_make_request(KVM_REQ_EVENT, vcpu);
7086
7087         ++vcpu->stat.irq_window_exits;
7088         return 1;
7089 }
7090
7091 static int handle_halt(struct kvm_vcpu *vcpu)
7092 {
7093         return kvm_emulate_halt(vcpu);
7094 }
7095
7096 static int handle_vmcall(struct kvm_vcpu *vcpu)
7097 {
7098         return kvm_emulate_hypercall(vcpu);
7099 }
7100
7101 static int handle_invd(struct kvm_vcpu *vcpu)
7102 {
7103         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
7104 }
7105
7106 static int handle_invlpg(struct kvm_vcpu *vcpu)
7107 {
7108         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7109
7110         kvm_mmu_invlpg(vcpu, exit_qualification);
7111         return kvm_skip_emulated_instruction(vcpu);
7112 }
7113
7114 static int handle_rdpmc(struct kvm_vcpu *vcpu)
7115 {
7116         int err;
7117
7118         err = kvm_rdpmc(vcpu);
7119         return kvm_complete_insn_gp(vcpu, err);
7120 }
7121
7122 static int handle_wbinvd(struct kvm_vcpu *vcpu)
7123 {
7124         return kvm_emulate_wbinvd(vcpu);
7125 }
7126
7127 static int handle_xsetbv(struct kvm_vcpu *vcpu)
7128 {
7129         u64 new_bv = kvm_read_edx_eax(vcpu);
7130         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
7131
7132         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
7133                 return kvm_skip_emulated_instruction(vcpu);
7134         return 1;
7135 }
7136
7137 static int handle_xsaves(struct kvm_vcpu *vcpu)
7138 {
7139         kvm_skip_emulated_instruction(vcpu);
7140         WARN(1, "this should never happen\n");
7141         return 1;
7142 }
7143
7144 static int handle_xrstors(struct kvm_vcpu *vcpu)
7145 {
7146         kvm_skip_emulated_instruction(vcpu);
7147         WARN(1, "this should never happen\n");
7148         return 1;
7149 }
7150
7151 static int handle_apic_access(struct kvm_vcpu *vcpu)
7152 {
7153         if (likely(fasteoi)) {
7154                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7155                 int access_type, offset;
7156
7157                 access_type = exit_qualification & APIC_ACCESS_TYPE;
7158                 offset = exit_qualification & APIC_ACCESS_OFFSET;
7159                 /*
7160                  * Sane guest uses MOV to write EOI, with written value
7161                  * not cared. So make a short-circuit here by avoiding
7162                  * heavy instruction emulation.
7163                  */
7164                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
7165                     (offset == APIC_EOI)) {
7166                         kvm_lapic_set_eoi(vcpu);
7167                         return kvm_skip_emulated_instruction(vcpu);
7168                 }
7169         }
7170         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
7171 }
7172
7173 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
7174 {
7175         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7176         int vector = exit_qualification & 0xff;
7177
7178         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
7179         kvm_apic_set_eoi_accelerated(vcpu, vector);
7180         return 1;
7181 }
7182
7183 static int handle_apic_write(struct kvm_vcpu *vcpu)
7184 {
7185         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7186         u32 offset = exit_qualification & 0xfff;
7187
7188         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
7189         kvm_apic_write_nodecode(vcpu, offset);
7190         return 1;
7191 }
7192
7193 static int handle_task_switch(struct kvm_vcpu *vcpu)
7194 {
7195         struct vcpu_vmx *vmx = to_vmx(vcpu);
7196         unsigned long exit_qualification;
7197         bool has_error_code = false;
7198         u32 error_code = 0;
7199         u16 tss_selector;
7200         int reason, type, idt_v, idt_index;
7201
7202         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7203         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
7204         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
7205
7206         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7207
7208         reason = (u32)exit_qualification >> 30;
7209         if (reason == TASK_SWITCH_GATE && idt_v) {
7210                 switch (type) {
7211                 case INTR_TYPE_NMI_INTR:
7212                         vcpu->arch.nmi_injected = false;
7213                         vmx_set_nmi_mask(vcpu, true);
7214                         break;
7215                 case INTR_TYPE_EXT_INTR:
7216                 case INTR_TYPE_SOFT_INTR:
7217                         kvm_clear_interrupt_queue(vcpu);
7218                         break;
7219                 case INTR_TYPE_HARD_EXCEPTION:
7220                         if (vmx->idt_vectoring_info &
7221                             VECTORING_INFO_DELIVER_CODE_MASK) {
7222                                 has_error_code = true;
7223                                 error_code =
7224                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
7225                         }
7226                         /* fall through */
7227                 case INTR_TYPE_SOFT_EXCEPTION:
7228                         kvm_clear_exception_queue(vcpu);
7229                         break;
7230                 default:
7231                         break;
7232                 }
7233         }
7234         tss_selector = exit_qualification;
7235
7236         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
7237                        type != INTR_TYPE_EXT_INTR &&
7238                        type != INTR_TYPE_NMI_INTR))
7239                 skip_emulated_instruction(vcpu);
7240
7241         if (kvm_task_switch(vcpu, tss_selector,
7242                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
7243                             has_error_code, error_code) == EMULATE_FAIL) {
7244                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7245                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7246                 vcpu->run->internal.ndata = 0;
7247                 return 0;
7248         }
7249
7250         /*
7251          * TODO: What about debug traps on tss switch?
7252          *       Are we supposed to inject them and update dr6?
7253          */
7254
7255         return 1;
7256 }
7257
7258 static int handle_ept_violation(struct kvm_vcpu *vcpu)
7259 {
7260         unsigned long exit_qualification;
7261         gpa_t gpa;
7262         u64 error_code;
7263
7264         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7265
7266         /*
7267          * EPT violation happened while executing iret from NMI,
7268          * "blocked by NMI" bit has to be set before next VM entry.
7269          * There are errata that may cause this bit to not be set:
7270          * AAK134, BY25.
7271          */
7272         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7273                         enable_vnmi &&
7274                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7275                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
7276
7277         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7278         trace_kvm_page_fault(gpa, exit_qualification);
7279
7280         /* Is it a read fault? */
7281         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
7282                      ? PFERR_USER_MASK : 0;
7283         /* Is it a write fault? */
7284         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
7285                       ? PFERR_WRITE_MASK : 0;
7286         /* Is it a fetch fault? */
7287         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
7288                       ? PFERR_FETCH_MASK : 0;
7289         /* ept page table entry is present? */
7290         error_code |= (exit_qualification &
7291                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
7292                         EPT_VIOLATION_EXECUTABLE))
7293                       ? PFERR_PRESENT_MASK : 0;
7294
7295         error_code |= (exit_qualification & 0x100) != 0 ?
7296                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
7297
7298         vcpu->arch.exit_qualification = exit_qualification;
7299         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
7300 }
7301
7302 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
7303 {
7304         gpa_t gpa;
7305
7306         /*
7307          * A nested guest cannot optimize MMIO vmexits, because we have an
7308          * nGPA here instead of the required GPA.
7309          */
7310         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7311         if (!is_guest_mode(vcpu) &&
7312             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
7313                 trace_kvm_fast_mmio(gpa);
7314                 /*
7315                  * Doing kvm_skip_emulated_instruction() depends on undefined
7316                  * behavior: Intel's manual doesn't mandate
7317                  * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
7318                  * occurs and while on real hardware it was observed to be set,
7319                  * other hypervisors (namely Hyper-V) don't set it, we end up
7320                  * advancing IP with some random value. Disable fast mmio when
7321                  * running nested and keep it for real hardware in hope that
7322                  * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
7323                  */
7324                 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
7325                         return kvm_skip_emulated_instruction(vcpu);
7326                 else
7327                         return x86_emulate_instruction(vcpu, gpa, EMULTYPE_SKIP,
7328                                                        NULL, 0) == EMULATE_DONE;
7329         }
7330
7331         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
7332 }
7333
7334 static int handle_nmi_window(struct kvm_vcpu *vcpu)
7335 {
7336         WARN_ON_ONCE(!enable_vnmi);
7337         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7338                         CPU_BASED_VIRTUAL_NMI_PENDING);
7339         ++vcpu->stat.nmi_window_exits;
7340         kvm_make_request(KVM_REQ_EVENT, vcpu);
7341
7342         return 1;
7343 }
7344
7345 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
7346 {
7347         struct vcpu_vmx *vmx = to_vmx(vcpu);
7348         enum emulation_result err = EMULATE_DONE;
7349         int ret = 1;
7350         u32 cpu_exec_ctrl;
7351         bool intr_window_requested;
7352         unsigned count = 130;
7353
7354         /*
7355          * We should never reach the point where we are emulating L2
7356          * due to invalid guest state as that means we incorrectly
7357          * allowed a nested VMEntry with an invalid vmcs12.
7358          */
7359         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
7360
7361         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7362         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
7363
7364         while (vmx->emulation_required && count-- != 0) {
7365                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
7366                         return handle_interrupt_window(&vmx->vcpu);
7367
7368                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
7369                         return 1;
7370
7371                 err = emulate_instruction(vcpu, 0);
7372
7373                 if (err == EMULATE_USER_EXIT) {
7374                         ++vcpu->stat.mmio_exits;
7375                         ret = 0;
7376                         goto out;
7377                 }
7378
7379                 if (err != EMULATE_DONE)
7380                         goto emulation_error;
7381
7382                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
7383                     vcpu->arch.exception.pending)
7384                         goto emulation_error;
7385
7386                 if (vcpu->arch.halt_request) {
7387                         vcpu->arch.halt_request = 0;
7388                         ret = kvm_vcpu_halt(vcpu);
7389                         goto out;
7390                 }
7391
7392                 if (signal_pending(current))
7393                         goto out;
7394                 if (need_resched())
7395                         schedule();
7396         }
7397
7398 out:
7399         return ret;
7400
7401 emulation_error:
7402         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7403         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7404         vcpu->run->internal.ndata = 0;
7405         return 0;
7406 }
7407
7408 static void grow_ple_window(struct kvm_vcpu *vcpu)
7409 {
7410         struct vcpu_vmx *vmx = to_vmx(vcpu);
7411         int old = vmx->ple_window;
7412
7413         vmx->ple_window = __grow_ple_window(old, ple_window,
7414                                             ple_window_grow,
7415                                             ple_window_max);
7416
7417         if (vmx->ple_window != old)
7418                 vmx->ple_window_dirty = true;
7419
7420         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
7421 }
7422
7423 static void shrink_ple_window(struct kvm_vcpu *vcpu)
7424 {
7425         struct vcpu_vmx *vmx = to_vmx(vcpu);
7426         int old = vmx->ple_window;
7427
7428         vmx->ple_window = __shrink_ple_window(old, ple_window,
7429                                               ple_window_shrink,
7430                                               ple_window);
7431
7432         if (vmx->ple_window != old)
7433                 vmx->ple_window_dirty = true;
7434
7435         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
7436 }
7437
7438 /*
7439  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
7440  */
7441 static void wakeup_handler(void)
7442 {
7443         struct kvm_vcpu *vcpu;
7444         int cpu = smp_processor_id();
7445
7446         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7447         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
7448                         blocked_vcpu_list) {
7449                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7450
7451                 if (pi_test_on(pi_desc) == 1)
7452                         kvm_vcpu_kick(vcpu);
7453         }
7454         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7455 }
7456
7457 static void vmx_enable_tdp(void)
7458 {
7459         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
7460                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
7461                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
7462                 0ull, VMX_EPT_EXECUTABLE_MASK,
7463                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
7464                 VMX_EPT_RWX_MASK, 0ull);
7465
7466         ept_set_mmio_spte_mask();
7467         kvm_enable_tdp();
7468 }
7469
7470 static __init int hardware_setup(void)
7471 {
7472         int r = -ENOMEM, i;
7473
7474         rdmsrl_safe(MSR_EFER, &host_efer);
7475
7476         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7477                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7478
7479         for (i = 0; i < VMX_BITMAP_NR; i++) {
7480                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
7481                 if (!vmx_bitmap[i])
7482                         goto out;
7483         }
7484
7485         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
7486         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
7487
7488         if (setup_vmcs_config(&vmcs_config) < 0) {
7489                 r = -EIO;
7490                 goto out;
7491         }
7492
7493         if (boot_cpu_has(X86_FEATURE_NX))
7494                 kvm_enable_efer_bits(EFER_NX);
7495
7496         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7497                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7498                 enable_vpid = 0;
7499
7500         if (!cpu_has_vmx_ept() ||
7501             !cpu_has_vmx_ept_4levels() ||
7502             !cpu_has_vmx_ept_mt_wb() ||
7503             !cpu_has_vmx_invept_global())
7504                 enable_ept = 0;
7505
7506         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7507                 enable_ept_ad_bits = 0;
7508
7509         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7510                 enable_unrestricted_guest = 0;
7511
7512         if (!cpu_has_vmx_flexpriority())
7513                 flexpriority_enabled = 0;
7514
7515         if (!cpu_has_virtual_nmis())
7516                 enable_vnmi = 0;
7517
7518         /*
7519          * set_apic_access_page_addr() is used to reload apic access
7520          * page upon invalidation.  No need to do anything if not
7521          * using the APIC_ACCESS_ADDR VMCS field.
7522          */
7523         if (!flexpriority_enabled)
7524                 kvm_x86_ops->set_apic_access_page_addr = NULL;
7525
7526         if (!cpu_has_vmx_tpr_shadow())
7527                 kvm_x86_ops->update_cr8_intercept = NULL;
7528
7529         if (enable_ept && !cpu_has_vmx_ept_2m_page())
7530                 kvm_disable_largepages();
7531
7532         if (!cpu_has_vmx_ple()) {
7533                 ple_gap = 0;
7534                 ple_window = 0;
7535                 ple_window_grow = 0;
7536                 ple_window_max = 0;
7537                 ple_window_shrink = 0;
7538         }
7539
7540         if (!cpu_has_vmx_apicv()) {
7541                 enable_apicv = 0;
7542                 kvm_x86_ops->sync_pir_to_irr = NULL;
7543         }
7544
7545         if (cpu_has_vmx_tsc_scaling()) {
7546                 kvm_has_tsc_control = true;
7547                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7548                 kvm_tsc_scaling_ratio_frac_bits = 48;
7549         }
7550
7551         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7552
7553         if (enable_ept)
7554                 vmx_enable_tdp();
7555         else
7556                 kvm_disable_tdp();
7557
7558         /*
7559          * Only enable PML when hardware supports PML feature, and both EPT
7560          * and EPT A/D bit features are enabled -- PML depends on them to work.
7561          */
7562         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7563                 enable_pml = 0;
7564
7565         if (!enable_pml) {
7566                 kvm_x86_ops->slot_enable_log_dirty = NULL;
7567                 kvm_x86_ops->slot_disable_log_dirty = NULL;
7568                 kvm_x86_ops->flush_log_dirty = NULL;
7569                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7570         }
7571
7572         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7573                 u64 vmx_msr;
7574
7575                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7576                 cpu_preemption_timer_multi =
7577                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7578         } else {
7579                 kvm_x86_ops->set_hv_timer = NULL;
7580                 kvm_x86_ops->cancel_hv_timer = NULL;
7581         }
7582
7583         if (!cpu_has_vmx_shadow_vmcs())
7584                 enable_shadow_vmcs = 0;
7585         if (enable_shadow_vmcs)
7586                 init_vmcs_shadow_fields();
7587
7588         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7589         nested_vmx_setup_ctls_msrs(&vmcs_config.nested, enable_apicv);
7590
7591         kvm_mce_cap_supported |= MCG_LMCE_P;
7592
7593         return alloc_kvm_area();
7594
7595 out:
7596         for (i = 0; i < VMX_BITMAP_NR; i++)
7597                 free_page((unsigned long)vmx_bitmap[i]);
7598
7599     return r;
7600 }
7601
7602 static __exit void hardware_unsetup(void)
7603 {
7604         int i;
7605
7606         for (i = 0; i < VMX_BITMAP_NR; i++)
7607                 free_page((unsigned long)vmx_bitmap[i]);
7608
7609         free_kvm_area();
7610 }
7611
7612 /*
7613  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
7614  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
7615  */
7616 static int handle_pause(struct kvm_vcpu *vcpu)
7617 {
7618         if (!kvm_pause_in_guest(vcpu->kvm))
7619                 grow_ple_window(vcpu);
7620
7621         /*
7622          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
7623          * VM-execution control is ignored if CPL > 0. OTOH, KVM
7624          * never set PAUSE_EXITING and just set PLE if supported,
7625          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
7626          */
7627         kvm_vcpu_on_spin(vcpu, true);
7628         return kvm_skip_emulated_instruction(vcpu);
7629 }
7630
7631 static int handle_nop(struct kvm_vcpu *vcpu)
7632 {
7633         return kvm_skip_emulated_instruction(vcpu);
7634 }
7635
7636 static int handle_mwait(struct kvm_vcpu *vcpu)
7637 {
7638         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
7639         return handle_nop(vcpu);
7640 }
7641
7642 static int handle_invalid_op(struct kvm_vcpu *vcpu)
7643 {
7644         kvm_queue_exception(vcpu, UD_VECTOR);
7645         return 1;
7646 }
7647
7648 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
7649 {
7650         return 1;
7651 }
7652
7653 static int handle_monitor(struct kvm_vcpu *vcpu)
7654 {
7655         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
7656         return handle_nop(vcpu);
7657 }
7658
7659 /*
7660  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7661  * set the success or error code of an emulated VMX instruction, as specified
7662  * by Vol 2B, VMX Instruction Reference, "Conventions".
7663  */
7664 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
7665 {
7666         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
7667                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7668                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
7669 }
7670
7671 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
7672 {
7673         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7674                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
7675                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7676                         | X86_EFLAGS_CF);
7677 }
7678
7679 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
7680                                         u32 vm_instruction_error)
7681 {
7682         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
7683                 /*
7684                  * failValid writes the error number to the current VMCS, which
7685                  * can't be done there isn't a current VMCS.
7686                  */
7687                 nested_vmx_failInvalid(vcpu);
7688                 return;
7689         }
7690         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7691                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7692                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7693                         | X86_EFLAGS_ZF);
7694         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
7695         /*
7696          * We don't need to force a shadow sync because
7697          * VM_INSTRUCTION_ERROR is not shadowed
7698          */
7699 }
7700
7701 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
7702 {
7703         /* TODO: not to reset guest simply here. */
7704         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7705         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
7706 }
7707
7708 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
7709 {
7710         struct vcpu_vmx *vmx =
7711                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
7712
7713         vmx->nested.preemption_timer_expired = true;
7714         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
7715         kvm_vcpu_kick(&vmx->vcpu);
7716
7717         return HRTIMER_NORESTART;
7718 }
7719
7720 /*
7721  * Decode the memory-address operand of a vmx instruction, as recorded on an
7722  * exit caused by such an instruction (run by a guest hypervisor).
7723  * On success, returns 0. When the operand is invalid, returns 1 and throws
7724  * #UD or #GP.
7725  */
7726 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
7727                                  unsigned long exit_qualification,
7728                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
7729 {
7730         gva_t off;
7731         bool exn;
7732         struct kvm_segment s;
7733
7734         /*
7735          * According to Vol. 3B, "Information for VM Exits Due to Instruction
7736          * Execution", on an exit, vmx_instruction_info holds most of the
7737          * addressing components of the operand. Only the displacement part
7738          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7739          * For how an actual address is calculated from all these components,
7740          * refer to Vol. 1, "Operand Addressing".
7741          */
7742         int  scaling = vmx_instruction_info & 3;
7743         int  addr_size = (vmx_instruction_info >> 7) & 7;
7744         bool is_reg = vmx_instruction_info & (1u << 10);
7745         int  seg_reg = (vmx_instruction_info >> 15) & 7;
7746         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
7747         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
7748         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
7749         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
7750
7751         if (is_reg) {
7752                 kvm_queue_exception(vcpu, UD_VECTOR);
7753                 return 1;
7754         }
7755
7756         /* Addr = segment_base + offset */
7757         /* offset = base + [index * scale] + displacement */
7758         off = exit_qualification; /* holds the displacement */
7759         if (base_is_valid)
7760                 off += kvm_register_read(vcpu, base_reg);
7761         if (index_is_valid)
7762                 off += kvm_register_read(vcpu, index_reg)<<scaling;
7763         vmx_get_segment(vcpu, &s, seg_reg);
7764         *ret = s.base + off;
7765
7766         if (addr_size == 1) /* 32 bit */
7767                 *ret &= 0xffffffff;
7768
7769         /* Checks for #GP/#SS exceptions. */
7770         exn = false;
7771         if (is_long_mode(vcpu)) {
7772                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7773                  * non-canonical form. This is the only check on the memory
7774                  * destination for long mode!
7775                  */
7776                 exn = is_noncanonical_address(*ret, vcpu);
7777         } else if (is_protmode(vcpu)) {
7778                 /* Protected mode: apply checks for segment validity in the
7779                  * following order:
7780                  * - segment type check (#GP(0) may be thrown)
7781                  * - usability check (#GP(0)/#SS(0))
7782                  * - limit check (#GP(0)/#SS(0))
7783                  */
7784                 if (wr)
7785                         /* #GP(0) if the destination operand is located in a
7786                          * read-only data segment or any code segment.
7787                          */
7788                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
7789                 else
7790                         /* #GP(0) if the source operand is located in an
7791                          * execute-only code segment
7792                          */
7793                         exn = ((s.type & 0xa) == 8);
7794                 if (exn) {
7795                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7796                         return 1;
7797                 }
7798                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7799                  */
7800                 exn = (s.unusable != 0);
7801                 /* Protected mode: #GP(0)/#SS(0) if the memory
7802                  * operand is outside the segment limit.
7803                  */
7804                 exn = exn || (off + sizeof(u64) > s.limit);
7805         }
7806         if (exn) {
7807                 kvm_queue_exception_e(vcpu,
7808                                       seg_reg == VCPU_SREG_SS ?
7809                                                 SS_VECTOR : GP_VECTOR,
7810                                       0);
7811                 return 1;
7812         }
7813
7814         return 0;
7815 }
7816
7817 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7818 {
7819         gva_t gva;
7820         struct x86_exception e;
7821
7822         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7823                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7824                 return 1;
7825
7826         if (kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e)) {
7827                 kvm_inject_page_fault(vcpu, &e);
7828                 return 1;
7829         }
7830
7831         return 0;
7832 }
7833
7834 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7835 {
7836         struct vcpu_vmx *vmx = to_vmx(vcpu);
7837         struct vmcs *shadow_vmcs;
7838         int r;
7839
7840         r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
7841         if (r < 0)
7842                 goto out_vmcs02;
7843
7844         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7845         if (!vmx->nested.cached_vmcs12)
7846                 goto out_cached_vmcs12;
7847
7848         if (enable_shadow_vmcs) {
7849                 shadow_vmcs = alloc_vmcs();
7850                 if (!shadow_vmcs)
7851                         goto out_shadow_vmcs;
7852                 /* mark vmcs as shadow */
7853                 shadow_vmcs->revision_id |= (1u << 31);
7854                 /* init shadow vmcs */
7855                 vmcs_clear(shadow_vmcs);
7856                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7857         }
7858
7859         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7860                      HRTIMER_MODE_REL_PINNED);
7861         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7862
7863         vmx->nested.vmxon = true;
7864         return 0;
7865
7866 out_shadow_vmcs:
7867         kfree(vmx->nested.cached_vmcs12);
7868
7869 out_cached_vmcs12:
7870         free_loaded_vmcs(&vmx->nested.vmcs02);
7871
7872 out_vmcs02:
7873         return -ENOMEM;
7874 }
7875
7876 /*
7877  * Emulate the VMXON instruction.
7878  * Currently, we just remember that VMX is active, and do not save or even
7879  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7880  * do not currently need to store anything in that guest-allocated memory
7881  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7882  * argument is different from the VMXON pointer (which the spec says they do).
7883  */
7884 static int handle_vmon(struct kvm_vcpu *vcpu)
7885 {
7886         int ret;
7887         gpa_t vmptr;
7888         struct page *page;
7889         struct vcpu_vmx *vmx = to_vmx(vcpu);
7890         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7891                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7892
7893         /*
7894          * The Intel VMX Instruction Reference lists a bunch of bits that are
7895          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7896          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7897          * Otherwise, we should fail with #UD.  But most faulting conditions
7898          * have already been checked by hardware, prior to the VM-exit for
7899          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
7900          * that bit set to 1 in non-root mode.
7901          */
7902         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7903                 kvm_queue_exception(vcpu, UD_VECTOR);
7904                 return 1;
7905         }
7906
7907         /* CPL=0 must be checked manually. */
7908         if (vmx_get_cpl(vcpu)) {
7909                 kvm_queue_exception(vcpu, UD_VECTOR);
7910                 return 1;
7911         }
7912
7913         if (vmx->nested.vmxon) {
7914                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7915                 return kvm_skip_emulated_instruction(vcpu);
7916         }
7917
7918         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7919                         != VMXON_NEEDED_FEATURES) {
7920                 kvm_inject_gp(vcpu, 0);
7921                 return 1;
7922         }
7923
7924         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7925                 return 1;
7926
7927         /*
7928          * SDM 3: 24.11.5
7929          * The first 4 bytes of VMXON region contain the supported
7930          * VMCS revision identifier
7931          *
7932          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7933          * which replaces physical address width with 32
7934          */
7935         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7936                 nested_vmx_failInvalid(vcpu);
7937                 return kvm_skip_emulated_instruction(vcpu);
7938         }
7939
7940         page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7941         if (is_error_page(page)) {
7942                 nested_vmx_failInvalid(vcpu);
7943                 return kvm_skip_emulated_instruction(vcpu);
7944         }
7945         if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7946                 kunmap(page);
7947                 kvm_release_page_clean(page);
7948                 nested_vmx_failInvalid(vcpu);
7949                 return kvm_skip_emulated_instruction(vcpu);
7950         }
7951         kunmap(page);
7952         kvm_release_page_clean(page);
7953
7954         vmx->nested.vmxon_ptr = vmptr;
7955         ret = enter_vmx_operation(vcpu);
7956         if (ret)
7957                 return ret;
7958
7959         nested_vmx_succeed(vcpu);
7960         return kvm_skip_emulated_instruction(vcpu);
7961 }
7962
7963 /*
7964  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7965  * for running VMX instructions (except VMXON, whose prerequisites are
7966  * slightly different). It also specifies what exception to inject otherwise.
7967  * Note that many of these exceptions have priority over VM exits, so they
7968  * don't have to be checked again here.
7969  */
7970 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7971 {
7972         if (vmx_get_cpl(vcpu)) {
7973                 kvm_queue_exception(vcpu, UD_VECTOR);
7974                 return 0;
7975         }
7976
7977         if (!to_vmx(vcpu)->nested.vmxon) {
7978                 kvm_queue_exception(vcpu, UD_VECTOR);
7979                 return 0;
7980         }
7981         return 1;
7982 }
7983
7984 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
7985 {
7986         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
7987         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7988 }
7989
7990 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7991 {
7992         if (vmx->nested.current_vmptr == -1ull)
7993                 return;
7994
7995         if (enable_shadow_vmcs) {
7996                 /* copy to memory all shadowed fields in case
7997                    they were modified */
7998                 copy_shadow_to_vmcs12(vmx);
7999                 vmx->nested.sync_shadow_vmcs = false;
8000                 vmx_disable_shadow_vmcs(vmx);
8001         }
8002         vmx->nested.posted_intr_nv = -1;
8003
8004         /* Flush VMCS12 to guest memory */
8005         kvm_vcpu_write_guest_page(&vmx->vcpu,
8006                                   vmx->nested.current_vmptr >> PAGE_SHIFT,
8007                                   vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
8008
8009         vmx->nested.current_vmptr = -1ull;
8010 }
8011
8012 /*
8013  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
8014  * just stops using VMX.
8015  */
8016 static void free_nested(struct vcpu_vmx *vmx)
8017 {
8018         if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
8019                 return;
8020
8021         vmx->nested.vmxon = false;
8022         vmx->nested.smm.vmxon = false;
8023         free_vpid(vmx->nested.vpid02);
8024         vmx->nested.posted_intr_nv = -1;
8025         vmx->nested.current_vmptr = -1ull;
8026         if (enable_shadow_vmcs) {
8027                 vmx_disable_shadow_vmcs(vmx);
8028                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
8029                 free_vmcs(vmx->vmcs01.shadow_vmcs);
8030                 vmx->vmcs01.shadow_vmcs = NULL;
8031         }
8032         kfree(vmx->nested.cached_vmcs12);
8033         /* Unpin physical memory we referred to in the vmcs02 */
8034         if (vmx->nested.apic_access_page) {
8035                 kvm_release_page_dirty(vmx->nested.apic_access_page);
8036                 vmx->nested.apic_access_page = NULL;
8037         }
8038         if (vmx->nested.virtual_apic_page) {
8039                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
8040                 vmx->nested.virtual_apic_page = NULL;
8041         }
8042         if (vmx->nested.pi_desc_page) {
8043                 kunmap(vmx->nested.pi_desc_page);
8044                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
8045                 vmx->nested.pi_desc_page = NULL;
8046                 vmx->nested.pi_desc = NULL;
8047         }
8048
8049         free_loaded_vmcs(&vmx->nested.vmcs02);
8050 }
8051
8052 /* Emulate the VMXOFF instruction */
8053 static int handle_vmoff(struct kvm_vcpu *vcpu)
8054 {
8055         if (!nested_vmx_check_permission(vcpu))
8056                 return 1;
8057         free_nested(to_vmx(vcpu));
8058         nested_vmx_succeed(vcpu);
8059         return kvm_skip_emulated_instruction(vcpu);
8060 }
8061
8062 /* Emulate the VMCLEAR instruction */
8063 static int handle_vmclear(struct kvm_vcpu *vcpu)
8064 {
8065         struct vcpu_vmx *vmx = to_vmx(vcpu);
8066         u32 zero = 0;
8067         gpa_t vmptr;
8068
8069         if (!nested_vmx_check_permission(vcpu))
8070                 return 1;
8071
8072         if (nested_vmx_get_vmptr(vcpu, &vmptr))
8073                 return 1;
8074
8075         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8076                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
8077                 return kvm_skip_emulated_instruction(vcpu);
8078         }
8079
8080         if (vmptr == vmx->nested.vmxon_ptr) {
8081                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
8082                 return kvm_skip_emulated_instruction(vcpu);
8083         }
8084
8085         if (vmptr == vmx->nested.current_vmptr)
8086                 nested_release_vmcs12(vmx);
8087
8088         kvm_vcpu_write_guest(vcpu,
8089                         vmptr + offsetof(struct vmcs12, launch_state),
8090                         &zero, sizeof(zero));
8091
8092         nested_vmx_succeed(vcpu);
8093         return kvm_skip_emulated_instruction(vcpu);
8094 }
8095
8096 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
8097
8098 /* Emulate the VMLAUNCH instruction */
8099 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
8100 {
8101         return nested_vmx_run(vcpu, true);
8102 }
8103
8104 /* Emulate the VMRESUME instruction */
8105 static int handle_vmresume(struct kvm_vcpu *vcpu)
8106 {
8107
8108         return nested_vmx_run(vcpu, false);
8109 }
8110
8111 /*
8112  * Read a vmcs12 field. Since these can have varying lengths and we return
8113  * one type, we chose the biggest type (u64) and zero-extend the return value
8114  * to that size. Note that the caller, handle_vmread, might need to use only
8115  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
8116  * 64-bit fields are to be returned).
8117  */
8118 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
8119                                   unsigned long field, u64 *ret)
8120 {
8121         short offset = vmcs_field_to_offset(field);
8122         char *p;
8123
8124         if (offset < 0)
8125                 return offset;
8126
8127         p = ((char *)(get_vmcs12(vcpu))) + offset;
8128
8129         switch (vmcs_field_width(field)) {
8130         case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8131                 *ret = *((natural_width *)p);
8132                 return 0;
8133         case VMCS_FIELD_WIDTH_U16:
8134                 *ret = *((u16 *)p);
8135                 return 0;
8136         case VMCS_FIELD_WIDTH_U32:
8137                 *ret = *((u32 *)p);
8138                 return 0;
8139         case VMCS_FIELD_WIDTH_U64:
8140                 *ret = *((u64 *)p);
8141                 return 0;
8142         default:
8143                 WARN_ON(1);
8144                 return -ENOENT;
8145         }
8146 }
8147
8148
8149 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
8150                                    unsigned long field, u64 field_value){
8151         short offset = vmcs_field_to_offset(field);
8152         char *p = ((char *) get_vmcs12(vcpu)) + offset;
8153         if (offset < 0)
8154                 return offset;
8155
8156         switch (vmcs_field_width(field)) {
8157         case VMCS_FIELD_WIDTH_U16:
8158                 *(u16 *)p = field_value;
8159                 return 0;
8160         case VMCS_FIELD_WIDTH_U32:
8161                 *(u32 *)p = field_value;
8162                 return 0;
8163         case VMCS_FIELD_WIDTH_U64:
8164                 *(u64 *)p = field_value;
8165                 return 0;
8166         case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8167                 *(natural_width *)p = field_value;
8168                 return 0;
8169         default:
8170                 WARN_ON(1);
8171                 return -ENOENT;
8172         }
8173
8174 }
8175
8176 /*
8177  * Copy the writable VMCS shadow fields back to the VMCS12, in case
8178  * they have been modified by the L1 guest. Note that the "read-only"
8179  * VM-exit information fields are actually writable if the vCPU is
8180  * configured to support "VMWRITE to any supported field in the VMCS."
8181  */
8182 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
8183 {
8184         const u16 *fields[] = {
8185                 shadow_read_write_fields,
8186                 shadow_read_only_fields
8187         };
8188         const int max_fields[] = {
8189                 max_shadow_read_write_fields,
8190                 max_shadow_read_only_fields
8191         };
8192         int i, q;
8193         unsigned long field;
8194         u64 field_value;
8195         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8196
8197         preempt_disable();
8198
8199         vmcs_load(shadow_vmcs);
8200
8201         for (q = 0; q < ARRAY_SIZE(fields); q++) {
8202                 for (i = 0; i < max_fields[q]; i++) {
8203                         field = fields[q][i];
8204                         field_value = __vmcs_readl(field);
8205                         vmcs12_write_any(&vmx->vcpu, field, field_value);
8206                 }
8207                 /*
8208                  * Skip the VM-exit information fields if they are read-only.
8209                  */
8210                 if (!nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
8211                         break;
8212         }
8213
8214         vmcs_clear(shadow_vmcs);
8215         vmcs_load(vmx->loaded_vmcs->vmcs);
8216
8217         preempt_enable();
8218 }
8219
8220 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
8221 {
8222         const u16 *fields[] = {
8223                 shadow_read_write_fields,
8224                 shadow_read_only_fields
8225         };
8226         const int max_fields[] = {
8227                 max_shadow_read_write_fields,
8228                 max_shadow_read_only_fields
8229         };
8230         int i, q;
8231         unsigned long field;
8232         u64 field_value = 0;
8233         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8234
8235         vmcs_load(shadow_vmcs);
8236
8237         for (q = 0; q < ARRAY_SIZE(fields); q++) {
8238                 for (i = 0; i < max_fields[q]; i++) {
8239                         field = fields[q][i];
8240                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
8241                         __vmcs_writel(field, field_value);
8242                 }
8243         }
8244
8245         vmcs_clear(shadow_vmcs);
8246         vmcs_load(vmx->loaded_vmcs->vmcs);
8247 }
8248
8249 /*
8250  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
8251  * used before) all generate the same failure when it is missing.
8252  */
8253 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
8254 {
8255         struct vcpu_vmx *vmx = to_vmx(vcpu);
8256         if (vmx->nested.current_vmptr == -1ull) {
8257                 nested_vmx_failInvalid(vcpu);
8258                 return 0;
8259         }
8260         return 1;
8261 }
8262
8263 static int handle_vmread(struct kvm_vcpu *vcpu)
8264 {
8265         unsigned long field;
8266         u64 field_value;
8267         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8268         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8269         gva_t gva = 0;
8270
8271         if (!nested_vmx_check_permission(vcpu))
8272                 return 1;
8273
8274         if (!nested_vmx_check_vmcs12(vcpu))
8275                 return kvm_skip_emulated_instruction(vcpu);
8276
8277         /* Decode instruction info and find the field to read */
8278         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8279         /* Read the field, zero-extended to a u64 field_value */
8280         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
8281                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8282                 return kvm_skip_emulated_instruction(vcpu);
8283         }
8284         /*
8285          * Now copy part of this value to register or memory, as requested.
8286          * Note that the number of bits actually copied is 32 or 64 depending
8287          * on the guest's mode (32 or 64 bit), not on the given field's length.
8288          */
8289         if (vmx_instruction_info & (1u << 10)) {
8290                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
8291                         field_value);
8292         } else {
8293                 if (get_vmx_mem_address(vcpu, exit_qualification,
8294                                 vmx_instruction_info, true, &gva))
8295                         return 1;
8296                 /* _system ok, nested_vmx_check_permission has verified cpl=0 */
8297                 kvm_write_guest_virt_system(vcpu, gva, &field_value,
8298                                             (is_long_mode(vcpu) ? 8 : 4), NULL);
8299         }
8300
8301         nested_vmx_succeed(vcpu);
8302         return kvm_skip_emulated_instruction(vcpu);
8303 }
8304
8305
8306 static int handle_vmwrite(struct kvm_vcpu *vcpu)
8307 {
8308         unsigned long field;
8309         gva_t gva;
8310         struct vcpu_vmx *vmx = to_vmx(vcpu);
8311         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8312         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8313
8314         /* The value to write might be 32 or 64 bits, depending on L1's long
8315          * mode, and eventually we need to write that into a field of several
8316          * possible lengths. The code below first zero-extends the value to 64
8317          * bit (field_value), and then copies only the appropriate number of
8318          * bits into the vmcs12 field.
8319          */
8320         u64 field_value = 0;
8321         struct x86_exception e;
8322
8323         if (!nested_vmx_check_permission(vcpu))
8324                 return 1;
8325
8326         if (!nested_vmx_check_vmcs12(vcpu))
8327                 return kvm_skip_emulated_instruction(vcpu);
8328
8329         if (vmx_instruction_info & (1u << 10))
8330                 field_value = kvm_register_readl(vcpu,
8331                         (((vmx_instruction_info) >> 3) & 0xf));
8332         else {
8333                 if (get_vmx_mem_address(vcpu, exit_qualification,
8334                                 vmx_instruction_info, false, &gva))
8335                         return 1;
8336                 if (kvm_read_guest_virt(vcpu, gva, &field_value,
8337                                         (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
8338                         kvm_inject_page_fault(vcpu, &e);
8339                         return 1;
8340                 }
8341         }
8342
8343
8344         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8345         /*
8346          * If the vCPU supports "VMWRITE to any supported field in the
8347          * VMCS," then the "read-only" fields are actually read/write.
8348          */
8349         if (vmcs_field_readonly(field) &&
8350             !nested_cpu_has_vmwrite_any_field(vcpu)) {
8351                 nested_vmx_failValid(vcpu,
8352                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
8353                 return kvm_skip_emulated_instruction(vcpu);
8354         }
8355
8356         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
8357                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8358                 return kvm_skip_emulated_instruction(vcpu);
8359         }
8360
8361         switch (field) {
8362 #define SHADOW_FIELD_RW(x) case x:
8363 #include "vmx_shadow_fields.h"
8364                 /*
8365                  * The fields that can be updated by L1 without a vmexit are
8366                  * always updated in the vmcs02, the others go down the slow
8367                  * path of prepare_vmcs02.
8368                  */
8369                 break;
8370         default:
8371                 vmx->nested.dirty_vmcs12 = true;
8372                 break;
8373         }
8374
8375         nested_vmx_succeed(vcpu);
8376         return kvm_skip_emulated_instruction(vcpu);
8377 }
8378
8379 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
8380 {
8381         vmx->nested.current_vmptr = vmptr;
8382         if (enable_shadow_vmcs) {
8383                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
8384                               SECONDARY_EXEC_SHADOW_VMCS);
8385                 vmcs_write64(VMCS_LINK_POINTER,
8386                              __pa(vmx->vmcs01.shadow_vmcs));
8387                 vmx->nested.sync_shadow_vmcs = true;
8388         }
8389         vmx->nested.dirty_vmcs12 = true;
8390 }
8391
8392 /* Emulate the VMPTRLD instruction */
8393 static int handle_vmptrld(struct kvm_vcpu *vcpu)
8394 {
8395         struct vcpu_vmx *vmx = to_vmx(vcpu);
8396         gpa_t vmptr;
8397
8398         if (!nested_vmx_check_permission(vcpu))
8399                 return 1;
8400
8401         if (nested_vmx_get_vmptr(vcpu, &vmptr))
8402                 return 1;
8403
8404         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8405                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
8406                 return kvm_skip_emulated_instruction(vcpu);
8407         }
8408
8409         if (vmptr == vmx->nested.vmxon_ptr) {
8410                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
8411                 return kvm_skip_emulated_instruction(vcpu);
8412         }
8413
8414         if (vmx->nested.current_vmptr != vmptr) {
8415                 struct vmcs12 *new_vmcs12;
8416                 struct page *page;
8417                 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8418                 if (is_error_page(page)) {
8419                         nested_vmx_failInvalid(vcpu);
8420                         return kvm_skip_emulated_instruction(vcpu);
8421                 }
8422                 new_vmcs12 = kmap(page);
8423                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
8424                         kunmap(page);
8425                         kvm_release_page_clean(page);
8426                         nested_vmx_failValid(vcpu,
8427                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
8428                         return kvm_skip_emulated_instruction(vcpu);
8429                 }
8430
8431                 nested_release_vmcs12(vmx);
8432                 /*
8433                  * Load VMCS12 from guest memory since it is not already
8434                  * cached.
8435                  */
8436                 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
8437                 kunmap(page);
8438                 kvm_release_page_clean(page);
8439
8440                 set_current_vmptr(vmx, vmptr);
8441         }
8442
8443         nested_vmx_succeed(vcpu);
8444         return kvm_skip_emulated_instruction(vcpu);
8445 }
8446
8447 /* Emulate the VMPTRST instruction */
8448 static int handle_vmptrst(struct kvm_vcpu *vcpu)
8449 {
8450         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8451         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8452         gva_t vmcs_gva;
8453         struct x86_exception e;
8454
8455         if (!nested_vmx_check_permission(vcpu))
8456                 return 1;
8457
8458         if (get_vmx_mem_address(vcpu, exit_qualification,
8459                         vmx_instruction_info, true, &vmcs_gva))
8460                 return 1;
8461         /* *_system ok, nested_vmx_check_permission has verified cpl=0 */
8462         if (kvm_write_guest_virt_system(vcpu, vmcs_gva,
8463                                         (void *)&to_vmx(vcpu)->nested.current_vmptr,
8464                                         sizeof(u64), &e)) {
8465                 kvm_inject_page_fault(vcpu, &e);
8466                 return 1;
8467         }
8468         nested_vmx_succeed(vcpu);
8469         return kvm_skip_emulated_instruction(vcpu);
8470 }
8471
8472 /* Emulate the INVEPT instruction */
8473 static int handle_invept(struct kvm_vcpu *vcpu)
8474 {
8475         struct vcpu_vmx *vmx = to_vmx(vcpu);
8476         u32 vmx_instruction_info, types;
8477         unsigned long type;
8478         gva_t gva;
8479         struct x86_exception e;
8480         struct {
8481                 u64 eptp, gpa;
8482         } operand;
8483
8484         if (!(vmx->nested.msrs.secondary_ctls_high &
8485               SECONDARY_EXEC_ENABLE_EPT) ||
8486             !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) {
8487                 kvm_queue_exception(vcpu, UD_VECTOR);
8488                 return 1;
8489         }
8490
8491         if (!nested_vmx_check_permission(vcpu))
8492                 return 1;
8493
8494         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8495         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8496
8497         types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
8498
8499         if (type >= 32 || !(types & (1 << type))) {
8500                 nested_vmx_failValid(vcpu,
8501                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8502                 return kvm_skip_emulated_instruction(vcpu);
8503         }
8504
8505         /* According to the Intel VMX instruction reference, the memory
8506          * operand is read even if it isn't needed (e.g., for type==global)
8507          */
8508         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8509                         vmx_instruction_info, false, &gva))
8510                 return 1;
8511         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
8512                 kvm_inject_page_fault(vcpu, &e);
8513                 return 1;
8514         }
8515
8516         switch (type) {
8517         case VMX_EPT_EXTENT_GLOBAL:
8518         /*
8519          * TODO: track mappings and invalidate
8520          * single context requests appropriately
8521          */
8522         case VMX_EPT_EXTENT_CONTEXT:
8523                 kvm_mmu_sync_roots(vcpu);
8524                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
8525                 nested_vmx_succeed(vcpu);
8526                 break;
8527         default:
8528                 BUG_ON(1);
8529                 break;
8530         }
8531
8532         return kvm_skip_emulated_instruction(vcpu);
8533 }
8534
8535 static int handle_invvpid(struct kvm_vcpu *vcpu)
8536 {
8537         struct vcpu_vmx *vmx = to_vmx(vcpu);
8538         u32 vmx_instruction_info;
8539         unsigned long type, types;
8540         gva_t gva;
8541         struct x86_exception e;
8542         struct {
8543                 u64 vpid;
8544                 u64 gla;
8545         } operand;
8546
8547         if (!(vmx->nested.msrs.secondary_ctls_high &
8548               SECONDARY_EXEC_ENABLE_VPID) ||
8549                         !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) {
8550                 kvm_queue_exception(vcpu, UD_VECTOR);
8551                 return 1;
8552         }
8553
8554         if (!nested_vmx_check_permission(vcpu))
8555                 return 1;
8556
8557         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8558         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8559
8560         types = (vmx->nested.msrs.vpid_caps &
8561                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
8562
8563         if (type >= 32 || !(types & (1 << type))) {
8564                 nested_vmx_failValid(vcpu,
8565                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8566                 return kvm_skip_emulated_instruction(vcpu);
8567         }
8568
8569         /* according to the intel vmx instruction reference, the memory
8570          * operand is read even if it isn't needed (e.g., for type==global)
8571          */
8572         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8573                         vmx_instruction_info, false, &gva))
8574                 return 1;
8575         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
8576                 kvm_inject_page_fault(vcpu, &e);
8577                 return 1;
8578         }
8579         if (operand.vpid >> 16) {
8580                 nested_vmx_failValid(vcpu,
8581                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8582                 return kvm_skip_emulated_instruction(vcpu);
8583         }
8584
8585         switch (type) {
8586         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
8587                 if (!operand.vpid ||
8588                     is_noncanonical_address(operand.gla, vcpu)) {
8589                         nested_vmx_failValid(vcpu,
8590                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8591                         return kvm_skip_emulated_instruction(vcpu);
8592                 }
8593                 if (cpu_has_vmx_invvpid_individual_addr() &&
8594                     vmx->nested.vpid02) {
8595                         __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR,
8596                                 vmx->nested.vpid02, operand.gla);
8597                 } else
8598                         __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8599                 break;
8600         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
8601         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
8602                 if (!operand.vpid) {
8603                         nested_vmx_failValid(vcpu,
8604                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8605                         return kvm_skip_emulated_instruction(vcpu);
8606                 }
8607                 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8608                 break;
8609         case VMX_VPID_EXTENT_ALL_CONTEXT:
8610                 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8611                 break;
8612         default:
8613                 WARN_ON_ONCE(1);
8614                 return kvm_skip_emulated_instruction(vcpu);
8615         }
8616
8617         nested_vmx_succeed(vcpu);
8618
8619         return kvm_skip_emulated_instruction(vcpu);
8620 }
8621
8622 static int handle_pml_full(struct kvm_vcpu *vcpu)
8623 {
8624         unsigned long exit_qualification;
8625
8626         trace_kvm_pml_full(vcpu->vcpu_id);
8627
8628         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8629
8630         /*
8631          * PML buffer FULL happened while executing iret from NMI,
8632          * "blocked by NMI" bit has to be set before next VM entry.
8633          */
8634         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
8635                         enable_vnmi &&
8636                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
8637                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8638                                 GUEST_INTR_STATE_NMI);
8639
8640         /*
8641          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
8642          * here.., and there's no userspace involvement needed for PML.
8643          */
8644         return 1;
8645 }
8646
8647 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8648 {
8649         kvm_lapic_expired_hv_timer(vcpu);
8650         return 1;
8651 }
8652
8653 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
8654 {
8655         struct vcpu_vmx *vmx = to_vmx(vcpu);
8656         int maxphyaddr = cpuid_maxphyaddr(vcpu);
8657
8658         /* Check for memory type validity */
8659         switch (address & VMX_EPTP_MT_MASK) {
8660         case VMX_EPTP_MT_UC:
8661                 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT))
8662                         return false;
8663                 break;
8664         case VMX_EPTP_MT_WB:
8665                 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT))
8666                         return false;
8667                 break;
8668         default:
8669                 return false;
8670         }
8671
8672         /* only 4 levels page-walk length are valid */
8673         if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
8674                 return false;
8675
8676         /* Reserved bits should not be set */
8677         if (address >> maxphyaddr || ((address >> 7) & 0x1f))
8678                 return false;
8679
8680         /* AD, if set, should be supported */
8681         if (address & VMX_EPTP_AD_ENABLE_BIT) {
8682                 if (!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT))
8683                         return false;
8684         }
8685
8686         return true;
8687 }
8688
8689 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
8690                                      struct vmcs12 *vmcs12)
8691 {
8692         u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
8693         u64 address;
8694         bool accessed_dirty;
8695         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
8696
8697         if (!nested_cpu_has_eptp_switching(vmcs12) ||
8698             !nested_cpu_has_ept(vmcs12))
8699                 return 1;
8700
8701         if (index >= VMFUNC_EPTP_ENTRIES)
8702                 return 1;
8703
8704
8705         if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
8706                                      &address, index * 8, 8))
8707                 return 1;
8708
8709         accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
8710
8711         /*
8712          * If the (L2) guest does a vmfunc to the currently
8713          * active ept pointer, we don't have to do anything else
8714          */
8715         if (vmcs12->ept_pointer != address) {
8716                 if (!valid_ept_address(vcpu, address))
8717                         return 1;
8718
8719                 kvm_mmu_unload(vcpu);
8720                 mmu->ept_ad = accessed_dirty;
8721                 mmu->base_role.ad_disabled = !accessed_dirty;
8722                 vmcs12->ept_pointer = address;
8723                 /*
8724                  * TODO: Check what's the correct approach in case
8725                  * mmu reload fails. Currently, we just let the next
8726                  * reload potentially fail
8727                  */
8728                 kvm_mmu_reload(vcpu);
8729         }
8730
8731         return 0;
8732 }
8733
8734 static int handle_vmfunc(struct kvm_vcpu *vcpu)
8735 {
8736         struct vcpu_vmx *vmx = to_vmx(vcpu);
8737         struct vmcs12 *vmcs12;
8738         u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
8739
8740         /*
8741          * VMFUNC is only supported for nested guests, but we always enable the
8742          * secondary control for simplicity; for non-nested mode, fake that we
8743          * didn't by injecting #UD.
8744          */
8745         if (!is_guest_mode(vcpu)) {
8746                 kvm_queue_exception(vcpu, UD_VECTOR);
8747                 return 1;
8748         }
8749
8750         vmcs12 = get_vmcs12(vcpu);
8751         if ((vmcs12->vm_function_control & (1 << function)) == 0)
8752                 goto fail;
8753
8754         switch (function) {
8755         case 0:
8756                 if (nested_vmx_eptp_switching(vcpu, vmcs12))
8757                         goto fail;
8758                 break;
8759         default:
8760                 goto fail;
8761         }
8762         return kvm_skip_emulated_instruction(vcpu);
8763
8764 fail:
8765         nested_vmx_vmexit(vcpu, vmx->exit_reason,
8766                           vmcs_read32(VM_EXIT_INTR_INFO),
8767                           vmcs_readl(EXIT_QUALIFICATION));
8768         return 1;
8769 }
8770
8771 /*
8772  * The exit handlers return 1 if the exit was handled fully and guest execution
8773  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
8774  * to be done to userspace and return 0.
8775  */
8776 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
8777         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
8778         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
8779         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
8780         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
8781         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
8782         [EXIT_REASON_CR_ACCESS]               = handle_cr,
8783         [EXIT_REASON_DR_ACCESS]               = handle_dr,
8784         [EXIT_REASON_CPUID]                   = handle_cpuid,
8785         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
8786         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
8787         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
8788         [EXIT_REASON_HLT]                     = handle_halt,
8789         [EXIT_REASON_INVD]                    = handle_invd,
8790         [EXIT_REASON_INVLPG]                  = handle_invlpg,
8791         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
8792         [EXIT_REASON_VMCALL]                  = handle_vmcall,
8793         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
8794         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
8795         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
8796         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
8797         [EXIT_REASON_VMREAD]                  = handle_vmread,
8798         [EXIT_REASON_VMRESUME]                = handle_vmresume,
8799         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
8800         [EXIT_REASON_VMOFF]                   = handle_vmoff,
8801         [EXIT_REASON_VMON]                    = handle_vmon,
8802         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
8803         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
8804         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
8805         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
8806         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
8807         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
8808         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
8809         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
8810         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
8811         [EXIT_REASON_LDTR_TR]                 = handle_desc,
8812         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
8813         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
8814         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
8815         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
8816         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
8817         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
8818         [EXIT_REASON_INVEPT]                  = handle_invept,
8819         [EXIT_REASON_INVVPID]                 = handle_invvpid,
8820         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
8821         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
8822         [EXIT_REASON_XSAVES]                  = handle_xsaves,
8823         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
8824         [EXIT_REASON_PML_FULL]                = handle_pml_full,
8825         [EXIT_REASON_VMFUNC]                  = handle_vmfunc,
8826         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
8827 };
8828
8829 static const int kvm_vmx_max_exit_handlers =
8830         ARRAY_SIZE(kvm_vmx_exit_handlers);
8831
8832 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
8833                                        struct vmcs12 *vmcs12)
8834 {
8835         unsigned long exit_qualification;
8836         gpa_t bitmap, last_bitmap;
8837         unsigned int port;
8838         int size;
8839         u8 b;
8840
8841         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
8842                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
8843
8844         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8845
8846         port = exit_qualification >> 16;
8847         size = (exit_qualification & 7) + 1;
8848
8849         last_bitmap = (gpa_t)-1;
8850         b = -1;
8851
8852         while (size > 0) {
8853                 if (port < 0x8000)
8854                         bitmap = vmcs12->io_bitmap_a;
8855                 else if (port < 0x10000)
8856                         bitmap = vmcs12->io_bitmap_b;
8857                 else
8858                         return true;
8859                 bitmap += (port & 0x7fff) / 8;
8860
8861                 if (last_bitmap != bitmap)
8862                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8863                                 return true;
8864                 if (b & (1 << (port & 7)))
8865                         return true;
8866
8867                 port++;
8868                 size--;
8869                 last_bitmap = bitmap;
8870         }
8871
8872         return false;
8873 }
8874
8875 /*
8876  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8877  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8878  * disinterest in the current event (read or write a specific MSR) by using an
8879  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8880  */
8881 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8882         struct vmcs12 *vmcs12, u32 exit_reason)
8883 {
8884         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8885         gpa_t bitmap;
8886
8887         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8888                 return true;
8889
8890         /*
8891          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8892          * for the four combinations of read/write and low/high MSR numbers.
8893          * First we need to figure out which of the four to use:
8894          */
8895         bitmap = vmcs12->msr_bitmap;
8896         if (exit_reason == EXIT_REASON_MSR_WRITE)
8897                 bitmap += 2048;
8898         if (msr_index >= 0xc0000000) {
8899                 msr_index -= 0xc0000000;
8900                 bitmap += 1024;
8901         }
8902
8903         /* Then read the msr_index'th bit from this bitmap: */
8904         if (msr_index < 1024*8) {
8905                 unsigned char b;
8906                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8907                         return true;
8908                 return 1 & (b >> (msr_index & 7));
8909         } else
8910                 return true; /* let L1 handle the wrong parameter */
8911 }
8912
8913 /*
8914  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8915  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8916  * intercept (via guest_host_mask etc.) the current event.
8917  */
8918 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8919         struct vmcs12 *vmcs12)
8920 {
8921         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8922         int cr = exit_qualification & 15;
8923         int reg;
8924         unsigned long val;
8925
8926         switch ((exit_qualification >> 4) & 3) {
8927         case 0: /* mov to cr */
8928                 reg = (exit_qualification >> 8) & 15;
8929                 val = kvm_register_readl(vcpu, reg);
8930                 switch (cr) {
8931                 case 0:
8932                         if (vmcs12->cr0_guest_host_mask &
8933                             (val ^ vmcs12->cr0_read_shadow))
8934                                 return true;
8935                         break;
8936                 case 3:
8937                         if ((vmcs12->cr3_target_count >= 1 &&
8938                                         vmcs12->cr3_target_value0 == val) ||
8939                                 (vmcs12->cr3_target_count >= 2 &&
8940                                         vmcs12->cr3_target_value1 == val) ||
8941                                 (vmcs12->cr3_target_count >= 3 &&
8942                                         vmcs12->cr3_target_value2 == val) ||
8943                                 (vmcs12->cr3_target_count >= 4 &&
8944                                         vmcs12->cr3_target_value3 == val))
8945                                 return false;
8946                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8947                                 return true;
8948                         break;
8949                 case 4:
8950                         if (vmcs12->cr4_guest_host_mask &
8951                             (vmcs12->cr4_read_shadow ^ val))
8952                                 return true;
8953                         break;
8954                 case 8:
8955                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8956                                 return true;
8957                         break;
8958                 }
8959                 break;
8960         case 2: /* clts */
8961                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8962                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
8963                         return true;
8964                 break;
8965         case 1: /* mov from cr */
8966                 switch (cr) {
8967                 case 3:
8968                         if (vmcs12->cpu_based_vm_exec_control &
8969                             CPU_BASED_CR3_STORE_EXITING)
8970                                 return true;
8971                         break;
8972                 case 8:
8973                         if (vmcs12->cpu_based_vm_exec_control &
8974                             CPU_BASED_CR8_STORE_EXITING)
8975                                 return true;
8976                         break;
8977                 }
8978                 break;
8979         case 3: /* lmsw */
8980                 /*
8981                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8982                  * cr0. Other attempted changes are ignored, with no exit.
8983                  */
8984                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8985                 if (vmcs12->cr0_guest_host_mask & 0xe &
8986                     (val ^ vmcs12->cr0_read_shadow))
8987                         return true;
8988                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8989                     !(vmcs12->cr0_read_shadow & 0x1) &&
8990                     (val & 0x1))
8991                         return true;
8992                 break;
8993         }
8994         return false;
8995 }
8996
8997 /*
8998  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8999  * should handle it ourselves in L0 (and then continue L2). Only call this
9000  * when in is_guest_mode (L2).
9001  */
9002 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
9003 {
9004         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9005         struct vcpu_vmx *vmx = to_vmx(vcpu);
9006         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9007
9008         if (vmx->nested.nested_run_pending)
9009                 return false;
9010
9011         if (unlikely(vmx->fail)) {
9012                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
9013                                     vmcs_read32(VM_INSTRUCTION_ERROR));
9014                 return true;
9015         }
9016
9017         /*
9018          * The host physical addresses of some pages of guest memory
9019          * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
9020          * Page). The CPU may write to these pages via their host
9021          * physical address while L2 is running, bypassing any
9022          * address-translation-based dirty tracking (e.g. EPT write
9023          * protection).
9024          *
9025          * Mark them dirty on every exit from L2 to prevent them from
9026          * getting out of sync with dirty tracking.
9027          */
9028         nested_mark_vmcs12_pages_dirty(vcpu);
9029
9030         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
9031                                 vmcs_readl(EXIT_QUALIFICATION),
9032                                 vmx->idt_vectoring_info,
9033                                 intr_info,
9034                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9035                                 KVM_ISA_VMX);
9036
9037         switch (exit_reason) {
9038         case EXIT_REASON_EXCEPTION_NMI:
9039                 if (is_nmi(intr_info))
9040                         return false;
9041                 else if (is_page_fault(intr_info))
9042                         return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
9043                 else if (is_no_device(intr_info) &&
9044                          !(vmcs12->guest_cr0 & X86_CR0_TS))
9045                         return false;
9046                 else if (is_debug(intr_info) &&
9047                          vcpu->guest_debug &
9048                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
9049                         return false;
9050                 else if (is_breakpoint(intr_info) &&
9051                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
9052                         return false;
9053                 return vmcs12->exception_bitmap &
9054                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
9055         case EXIT_REASON_EXTERNAL_INTERRUPT:
9056                 return false;
9057         case EXIT_REASON_TRIPLE_FAULT:
9058                 return true;
9059         case EXIT_REASON_PENDING_INTERRUPT:
9060                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
9061         case EXIT_REASON_NMI_WINDOW:
9062                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
9063         case EXIT_REASON_TASK_SWITCH:
9064                 return true;
9065         case EXIT_REASON_CPUID:
9066                 return true;
9067         case EXIT_REASON_HLT:
9068                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
9069         case EXIT_REASON_INVD:
9070                 return true;
9071         case EXIT_REASON_INVLPG:
9072                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9073         case EXIT_REASON_RDPMC:
9074                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
9075         case EXIT_REASON_RDRAND:
9076                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
9077         case EXIT_REASON_RDSEED:
9078                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
9079         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
9080                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
9081         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
9082         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
9083         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
9084         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
9085         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
9086         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
9087                 /*
9088                  * VMX instructions trap unconditionally. This allows L1 to
9089                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
9090                  */
9091                 return true;
9092         case EXIT_REASON_CR_ACCESS:
9093                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
9094         case EXIT_REASON_DR_ACCESS:
9095                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
9096         case EXIT_REASON_IO_INSTRUCTION:
9097                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
9098         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
9099                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
9100         case EXIT_REASON_MSR_READ:
9101         case EXIT_REASON_MSR_WRITE:
9102                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
9103         case EXIT_REASON_INVALID_STATE:
9104                 return true;
9105         case EXIT_REASON_MWAIT_INSTRUCTION:
9106                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
9107         case EXIT_REASON_MONITOR_TRAP_FLAG:
9108                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
9109         case EXIT_REASON_MONITOR_INSTRUCTION:
9110                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
9111         case EXIT_REASON_PAUSE_INSTRUCTION:
9112                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
9113                         nested_cpu_has2(vmcs12,
9114                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
9115         case EXIT_REASON_MCE_DURING_VMENTRY:
9116                 return false;
9117         case EXIT_REASON_TPR_BELOW_THRESHOLD:
9118                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
9119         case EXIT_REASON_APIC_ACCESS:
9120         case EXIT_REASON_APIC_WRITE:
9121         case EXIT_REASON_EOI_INDUCED:
9122                 /*
9123                  * The controls for "virtualize APIC accesses," "APIC-
9124                  * register virtualization," and "virtual-interrupt
9125                  * delivery" only come from vmcs12.
9126                  */
9127                 return true;
9128         case EXIT_REASON_EPT_VIOLATION:
9129                 /*
9130                  * L0 always deals with the EPT violation. If nested EPT is
9131                  * used, and the nested mmu code discovers that the address is
9132                  * missing in the guest EPT table (EPT12), the EPT violation
9133                  * will be injected with nested_ept_inject_page_fault()
9134                  */
9135                 return false;
9136         case EXIT_REASON_EPT_MISCONFIG:
9137                 /*
9138                  * L2 never uses directly L1's EPT, but rather L0's own EPT
9139                  * table (shadow on EPT) or a merged EPT table that L0 built
9140                  * (EPT on EPT). So any problems with the structure of the
9141                  * table is L0's fault.
9142                  */
9143                 return false;
9144         case EXIT_REASON_INVPCID:
9145                 return
9146                         nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
9147                         nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9148         case EXIT_REASON_WBINVD:
9149                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
9150         case EXIT_REASON_XSETBV:
9151                 return true;
9152         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
9153                 /*
9154                  * This should never happen, since it is not possible to
9155                  * set XSS to a non-zero value---neither in L1 nor in L2.
9156                  * If if it were, XSS would have to be checked against
9157                  * the XSS exit bitmap in vmcs12.
9158                  */
9159                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
9160         case EXIT_REASON_PREEMPTION_TIMER:
9161                 return false;
9162         case EXIT_REASON_PML_FULL:
9163                 /* We emulate PML support to L1. */
9164                 return false;
9165         case EXIT_REASON_VMFUNC:
9166                 /* VM functions are emulated through L2->L0 vmexits. */
9167                 return false;
9168         default:
9169                 return true;
9170         }
9171 }
9172
9173 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
9174 {
9175         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9176
9177         /*
9178          * At this point, the exit interruption info in exit_intr_info
9179          * is only valid for EXCEPTION_NMI exits.  For EXTERNAL_INTERRUPT
9180          * we need to query the in-kernel LAPIC.
9181          */
9182         WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
9183         if ((exit_intr_info &
9184              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9185             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
9186                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9187                 vmcs12->vm_exit_intr_error_code =
9188                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9189         }
9190
9191         nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
9192                           vmcs_readl(EXIT_QUALIFICATION));
9193         return 1;
9194 }
9195
9196 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
9197 {
9198         *info1 = vmcs_readl(EXIT_QUALIFICATION);
9199         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
9200 }
9201
9202 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
9203 {
9204         if (vmx->pml_pg) {
9205                 __free_page(vmx->pml_pg);
9206                 vmx->pml_pg = NULL;
9207         }
9208 }
9209
9210 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
9211 {
9212         struct vcpu_vmx *vmx = to_vmx(vcpu);
9213         u64 *pml_buf;
9214         u16 pml_idx;
9215
9216         pml_idx = vmcs_read16(GUEST_PML_INDEX);
9217
9218         /* Do nothing if PML buffer is empty */
9219         if (pml_idx == (PML_ENTITY_NUM - 1))
9220                 return;
9221
9222         /* PML index always points to next available PML buffer entity */
9223         if (pml_idx >= PML_ENTITY_NUM)
9224                 pml_idx = 0;
9225         else
9226                 pml_idx++;
9227
9228         pml_buf = page_address(vmx->pml_pg);
9229         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
9230                 u64 gpa;
9231
9232                 gpa = pml_buf[pml_idx];
9233                 WARN_ON(gpa & (PAGE_SIZE - 1));
9234                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
9235         }
9236
9237         /* reset PML index */
9238         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
9239 }
9240
9241 /*
9242  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
9243  * Called before reporting dirty_bitmap to userspace.
9244  */
9245 static void kvm_flush_pml_buffers(struct kvm *kvm)
9246 {
9247         int i;
9248         struct kvm_vcpu *vcpu;
9249         /*
9250          * We only need to kick vcpu out of guest mode here, as PML buffer
9251          * is flushed at beginning of all VMEXITs, and it's obvious that only
9252          * vcpus running in guest are possible to have unflushed GPAs in PML
9253          * buffer.
9254          */
9255         kvm_for_each_vcpu(i, vcpu, kvm)
9256                 kvm_vcpu_kick(vcpu);
9257 }
9258
9259 static void vmx_dump_sel(char *name, uint32_t sel)
9260 {
9261         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
9262                name, vmcs_read16(sel),
9263                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
9264                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
9265                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
9266 }
9267
9268 static void vmx_dump_dtsel(char *name, uint32_t limit)
9269 {
9270         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
9271                name, vmcs_read32(limit),
9272                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
9273 }
9274
9275 static void dump_vmcs(void)
9276 {
9277         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
9278         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
9279         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
9280         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
9281         u32 secondary_exec_control = 0;
9282         unsigned long cr4 = vmcs_readl(GUEST_CR4);
9283         u64 efer = vmcs_read64(GUEST_IA32_EFER);
9284         int i, n;
9285
9286         if (cpu_has_secondary_exec_ctrls())
9287                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9288
9289         pr_err("*** Guest State ***\n");
9290         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9291                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
9292                vmcs_readl(CR0_GUEST_HOST_MASK));
9293         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9294                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
9295         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
9296         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
9297             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
9298         {
9299                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
9300                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
9301                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
9302                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
9303         }
9304         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
9305                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
9306         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
9307                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
9308         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9309                vmcs_readl(GUEST_SYSENTER_ESP),
9310                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
9311         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
9312         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
9313         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
9314         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
9315         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
9316         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
9317         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
9318         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
9319         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
9320         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
9321         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
9322             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
9323                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
9324                        efer, vmcs_read64(GUEST_IA32_PAT));
9325         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
9326                vmcs_read64(GUEST_IA32_DEBUGCTL),
9327                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
9328         if (cpu_has_load_perf_global_ctrl &&
9329             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
9330                 pr_err("PerfGlobCtl = 0x%016llx\n",
9331                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
9332         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
9333                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
9334         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
9335                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
9336                vmcs_read32(GUEST_ACTIVITY_STATE));
9337         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
9338                 pr_err("InterruptStatus = %04x\n",
9339                        vmcs_read16(GUEST_INTR_STATUS));
9340
9341         pr_err("*** Host State ***\n");
9342         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
9343                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
9344         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
9345                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
9346                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
9347                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
9348                vmcs_read16(HOST_TR_SELECTOR));
9349         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
9350                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
9351                vmcs_readl(HOST_TR_BASE));
9352         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
9353                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
9354         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
9355                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
9356                vmcs_readl(HOST_CR4));
9357         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9358                vmcs_readl(HOST_IA32_SYSENTER_ESP),
9359                vmcs_read32(HOST_IA32_SYSENTER_CS),
9360                vmcs_readl(HOST_IA32_SYSENTER_EIP));
9361         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
9362                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
9363                        vmcs_read64(HOST_IA32_EFER),
9364                        vmcs_read64(HOST_IA32_PAT));
9365         if (cpu_has_load_perf_global_ctrl &&
9366             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9367                 pr_err("PerfGlobCtl = 0x%016llx\n",
9368                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
9369
9370         pr_err("*** Control State ***\n");
9371         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
9372                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
9373         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
9374         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
9375                vmcs_read32(EXCEPTION_BITMAP),
9376                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
9377                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
9378         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
9379                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9380                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
9381                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
9382         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
9383                vmcs_read32(VM_EXIT_INTR_INFO),
9384                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9385                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
9386         pr_err("        reason=%08x qualification=%016lx\n",
9387                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
9388         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
9389                vmcs_read32(IDT_VECTORING_INFO_FIELD),
9390                vmcs_read32(IDT_VECTORING_ERROR_CODE));
9391         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
9392         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
9393                 pr_err("TSC Multiplier = 0x%016llx\n",
9394                        vmcs_read64(TSC_MULTIPLIER));
9395         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
9396                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
9397         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
9398                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
9399         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
9400                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
9401         n = vmcs_read32(CR3_TARGET_COUNT);
9402         for (i = 0; i + 1 < n; i += 4)
9403                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
9404                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
9405                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
9406         if (i < n)
9407                 pr_err("CR3 target%u=%016lx\n",
9408                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
9409         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
9410                 pr_err("PLE Gap=%08x Window=%08x\n",
9411                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
9412         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
9413                 pr_err("Virtual processor ID = 0x%04x\n",
9414                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
9415 }
9416
9417 /*
9418  * The guest has exited.  See if we can fix it or if we need userspace
9419  * assistance.
9420  */
9421 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
9422 {
9423         struct vcpu_vmx *vmx = to_vmx(vcpu);
9424         u32 exit_reason = vmx->exit_reason;
9425         u32 vectoring_info = vmx->idt_vectoring_info;
9426
9427         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
9428
9429         /*
9430          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
9431          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
9432          * querying dirty_bitmap, we only need to kick all vcpus out of guest
9433          * mode as if vcpus is in root mode, the PML buffer must has been
9434          * flushed already.
9435          */
9436         if (enable_pml)
9437                 vmx_flush_pml_buffer(vcpu);
9438
9439         /* If guest state is invalid, start emulating */
9440         if (vmx->emulation_required)
9441                 return handle_invalid_guest_state(vcpu);
9442
9443         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
9444                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
9445
9446         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
9447                 dump_vmcs();
9448                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
9449                 vcpu->run->fail_entry.hardware_entry_failure_reason
9450                         = exit_reason;
9451                 return 0;
9452         }
9453
9454         if (unlikely(vmx->fail)) {
9455                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
9456                 vcpu->run->fail_entry.hardware_entry_failure_reason
9457                         = vmcs_read32(VM_INSTRUCTION_ERROR);
9458                 return 0;
9459         }
9460
9461         /*
9462          * Note:
9463          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
9464          * delivery event since it indicates guest is accessing MMIO.
9465          * The vm-exit can be triggered again after return to guest that
9466          * will cause infinite loop.
9467          */
9468         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
9469                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
9470                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
9471                         exit_reason != EXIT_REASON_PML_FULL &&
9472                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
9473                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9474                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
9475                 vcpu->run->internal.ndata = 3;
9476                 vcpu->run->internal.data[0] = vectoring_info;
9477                 vcpu->run->internal.data[1] = exit_reason;
9478                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
9479                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
9480                         vcpu->run->internal.ndata++;
9481                         vcpu->run->internal.data[3] =
9482                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
9483                 }
9484                 return 0;
9485         }
9486
9487         if (unlikely(!enable_vnmi &&
9488                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
9489                 if (vmx_interrupt_allowed(vcpu)) {
9490                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
9491                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
9492                            vcpu->arch.nmi_pending) {
9493                         /*
9494                          * This CPU don't support us in finding the end of an
9495                          * NMI-blocked window if the guest runs with IRQs
9496                          * disabled. So we pull the trigger after 1 s of
9497                          * futile waiting, but inform the user about this.
9498                          */
9499                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
9500                                "state on VCPU %d after 1 s timeout\n",
9501                                __func__, vcpu->vcpu_id);
9502                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
9503                 }
9504         }
9505
9506         if (exit_reason < kvm_vmx_max_exit_handlers
9507             && kvm_vmx_exit_handlers[exit_reason])
9508                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
9509         else {
9510                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
9511                                 exit_reason);
9512                 kvm_queue_exception(vcpu, UD_VECTOR);
9513                 return 1;
9514         }
9515 }
9516
9517 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
9518 {
9519         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9520
9521         if (is_guest_mode(vcpu) &&
9522                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9523                 return;
9524
9525         if (irr == -1 || tpr < irr) {
9526                 vmcs_write32(TPR_THRESHOLD, 0);
9527                 return;
9528         }
9529
9530         vmcs_write32(TPR_THRESHOLD, irr);
9531 }
9532
9533 static void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
9534 {
9535         u32 sec_exec_control;
9536
9537         if (!lapic_in_kernel(vcpu))
9538                 return;
9539
9540         /* Postpone execution until vmcs01 is the current VMCS. */
9541         if (is_guest_mode(vcpu)) {
9542                 to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
9543                 return;
9544         }
9545
9546         if (!cpu_need_tpr_shadow(vcpu))
9547                 return;
9548
9549         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9550         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9551                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
9552
9553         switch (kvm_get_apic_mode(vcpu)) {
9554         case LAPIC_MODE_INVALID:
9555                 WARN_ONCE(true, "Invalid local APIC state");
9556         case LAPIC_MODE_DISABLED:
9557                 break;
9558         case LAPIC_MODE_XAPIC:
9559                 if (flexpriority_enabled) {
9560                         sec_exec_control |=
9561                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9562                         vmx_flush_tlb(vcpu, true);
9563                 }
9564                 break;
9565         case LAPIC_MODE_X2APIC:
9566                 if (cpu_has_vmx_virtualize_x2apic_mode())
9567                         sec_exec_control |=
9568                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9569                 break;
9570         }
9571         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
9572
9573         vmx_update_msr_bitmap(vcpu);
9574 }
9575
9576 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
9577 {
9578         if (!is_guest_mode(vcpu)) {
9579                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9580                 vmx_flush_tlb(vcpu, true);
9581         }
9582 }
9583
9584 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
9585 {
9586         u16 status;
9587         u8 old;
9588
9589         if (max_isr == -1)
9590                 max_isr = 0;
9591
9592         status = vmcs_read16(GUEST_INTR_STATUS);
9593         old = status >> 8;
9594         if (max_isr != old) {
9595                 status &= 0xff;
9596                 status |= max_isr << 8;
9597                 vmcs_write16(GUEST_INTR_STATUS, status);
9598         }
9599 }
9600
9601 static void vmx_set_rvi(int vector)
9602 {
9603         u16 status;
9604         u8 old;
9605
9606         if (vector == -1)
9607                 vector = 0;
9608
9609         status = vmcs_read16(GUEST_INTR_STATUS);
9610         old = (u8)status & 0xff;
9611         if ((u8)vector != old) {
9612                 status &= ~0xff;
9613                 status |= (u8)vector;
9614                 vmcs_write16(GUEST_INTR_STATUS, status);
9615         }
9616 }
9617
9618 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
9619 {
9620         /*
9621          * When running L2, updating RVI is only relevant when
9622          * vmcs12 virtual-interrupt-delivery enabled.
9623          * However, it can be enabled only when L1 also
9624          * intercepts external-interrupts and in that case
9625          * we should not update vmcs02 RVI but instead intercept
9626          * interrupt. Therefore, do nothing when running L2.
9627          */
9628         if (!is_guest_mode(vcpu))
9629                 vmx_set_rvi(max_irr);
9630 }
9631
9632 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
9633 {
9634         struct vcpu_vmx *vmx = to_vmx(vcpu);
9635         int max_irr;
9636         bool max_irr_updated;
9637
9638         WARN_ON(!vcpu->arch.apicv_active);
9639         if (pi_test_on(&vmx->pi_desc)) {
9640                 pi_clear_on(&vmx->pi_desc);
9641                 /*
9642                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
9643                  * But on x86 this is just a compiler barrier anyway.
9644                  */
9645                 smp_mb__after_atomic();
9646                 max_irr_updated =
9647                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
9648
9649                 /*
9650                  * If we are running L2 and L1 has a new pending interrupt
9651                  * which can be injected, we should re-evaluate
9652                  * what should be done with this new L1 interrupt.
9653                  * If L1 intercepts external-interrupts, we should
9654                  * exit from L2 to L1. Otherwise, interrupt should be
9655                  * delivered directly to L2.
9656                  */
9657                 if (is_guest_mode(vcpu) && max_irr_updated) {
9658                         if (nested_exit_on_intr(vcpu))
9659                                 kvm_vcpu_exiting_guest_mode(vcpu);
9660                         else
9661                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9662                 }
9663         } else {
9664                 max_irr = kvm_lapic_find_highest_irr(vcpu);
9665         }
9666         vmx_hwapic_irr_update(vcpu, max_irr);
9667         return max_irr;
9668 }
9669
9670 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
9671 {
9672         if (!kvm_vcpu_apicv_active(vcpu))
9673                 return;
9674
9675         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
9676         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
9677         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
9678         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
9679 }
9680
9681 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
9682 {
9683         struct vcpu_vmx *vmx = to_vmx(vcpu);
9684
9685         pi_clear_on(&vmx->pi_desc);
9686         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
9687 }
9688
9689 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
9690 {
9691         u32 exit_intr_info = 0;
9692         u16 basic_exit_reason = (u16)vmx->exit_reason;
9693
9694         if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
9695               || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
9696                 return;
9697
9698         if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9699                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9700         vmx->exit_intr_info = exit_intr_info;
9701
9702         /* if exit due to PF check for async PF */
9703         if (is_page_fault(exit_intr_info))
9704                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
9705
9706         /* Handle machine checks before interrupts are enabled */
9707         if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
9708             is_machine_check(exit_intr_info))
9709                 kvm_machine_check();
9710
9711         /* We need to handle NMIs before interrupts are enabled */
9712         if (is_nmi(exit_intr_info)) {
9713                 kvm_before_interrupt(&vmx->vcpu);
9714                 asm("int $2");
9715                 kvm_after_interrupt(&vmx->vcpu);
9716         }
9717 }
9718
9719 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
9720 {
9721         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9722
9723         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
9724                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
9725                 unsigned int vector;
9726                 unsigned long entry;
9727                 gate_desc *desc;
9728                 struct vcpu_vmx *vmx = to_vmx(vcpu);
9729 #ifdef CONFIG_X86_64
9730                 unsigned long tmp;
9731 #endif
9732
9733                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
9734                 desc = (gate_desc *)vmx->host_idt_base + vector;
9735                 entry = gate_offset(desc);
9736                 asm volatile(
9737 #ifdef CONFIG_X86_64
9738                         "mov %%" _ASM_SP ", %[sp]\n\t"
9739                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
9740                         "push $%c[ss]\n\t"
9741                         "push %[sp]\n\t"
9742 #endif
9743                         "pushf\n\t"
9744                         __ASM_SIZE(push) " $%c[cs]\n\t"
9745                         CALL_NOSPEC
9746                         :
9747 #ifdef CONFIG_X86_64
9748                         [sp]"=&r"(tmp),
9749 #endif
9750                         ASM_CALL_CONSTRAINT
9751                         :
9752                         THUNK_TARGET(entry),
9753                         [ss]"i"(__KERNEL_DS),
9754                         [cs]"i"(__KERNEL_CS)
9755                         );
9756         }
9757 }
9758 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
9759
9760 static bool vmx_has_high_real_mode_segbase(void)
9761 {
9762         return enable_unrestricted_guest || emulate_invalid_guest_state;
9763 }
9764
9765 static bool vmx_mpx_supported(void)
9766 {
9767         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
9768                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
9769 }
9770
9771 static bool vmx_xsaves_supported(void)
9772 {
9773         return vmcs_config.cpu_based_2nd_exec_ctrl &
9774                 SECONDARY_EXEC_XSAVES;
9775 }
9776
9777 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
9778 {
9779         u32 exit_intr_info;
9780         bool unblock_nmi;
9781         u8 vector;
9782         bool idtv_info_valid;
9783
9784         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9785
9786         if (enable_vnmi) {
9787                 if (vmx->loaded_vmcs->nmi_known_unmasked)
9788                         return;
9789                 /*
9790                  * Can't use vmx->exit_intr_info since we're not sure what
9791                  * the exit reason is.
9792                  */
9793                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9794                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
9795                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9796                 /*
9797                  * SDM 3: 27.7.1.2 (September 2008)
9798                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
9799                  * a guest IRET fault.
9800                  * SDM 3: 23.2.2 (September 2008)
9801                  * Bit 12 is undefined in any of the following cases:
9802                  *  If the VM exit sets the valid bit in the IDT-vectoring
9803                  *   information field.
9804                  *  If the VM exit is due to a double fault.
9805                  */
9806                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
9807                     vector != DF_VECTOR && !idtv_info_valid)
9808                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9809                                       GUEST_INTR_STATE_NMI);
9810                 else
9811                         vmx->loaded_vmcs->nmi_known_unmasked =
9812                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
9813                                   & GUEST_INTR_STATE_NMI);
9814         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
9815                 vmx->loaded_vmcs->vnmi_blocked_time +=
9816                         ktime_to_ns(ktime_sub(ktime_get(),
9817                                               vmx->loaded_vmcs->entry_time));
9818 }
9819
9820 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
9821                                       u32 idt_vectoring_info,
9822                                       int instr_len_field,
9823                                       int error_code_field)
9824 {
9825         u8 vector;
9826         int type;
9827         bool idtv_info_valid;
9828
9829         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9830
9831         vcpu->arch.nmi_injected = false;
9832         kvm_clear_exception_queue(vcpu);
9833         kvm_clear_interrupt_queue(vcpu);
9834
9835         if (!idtv_info_valid)
9836                 return;
9837
9838         kvm_make_request(KVM_REQ_EVENT, vcpu);
9839
9840         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
9841         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
9842
9843         switch (type) {
9844         case INTR_TYPE_NMI_INTR:
9845                 vcpu->arch.nmi_injected = true;
9846                 /*
9847                  * SDM 3: 27.7.1.2 (September 2008)
9848                  * Clear bit "block by NMI" before VM entry if a NMI
9849                  * delivery faulted.
9850                  */
9851                 vmx_set_nmi_mask(vcpu, false);
9852                 break;
9853         case INTR_TYPE_SOFT_EXCEPTION:
9854                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9855                 /* fall through */
9856         case INTR_TYPE_HARD_EXCEPTION:
9857                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
9858                         u32 err = vmcs_read32(error_code_field);
9859                         kvm_requeue_exception_e(vcpu, vector, err);
9860                 } else
9861                         kvm_requeue_exception(vcpu, vector);
9862                 break;
9863         case INTR_TYPE_SOFT_INTR:
9864                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9865                 /* fall through */
9866         case INTR_TYPE_EXT_INTR:
9867                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
9868                 break;
9869         default:
9870                 break;
9871         }
9872 }
9873
9874 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
9875 {
9876         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
9877                                   VM_EXIT_INSTRUCTION_LEN,
9878                                   IDT_VECTORING_ERROR_CODE);
9879 }
9880
9881 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
9882 {
9883         __vmx_complete_interrupts(vcpu,
9884                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9885                                   VM_ENTRY_INSTRUCTION_LEN,
9886                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
9887
9888         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9889 }
9890
9891 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
9892 {
9893         int i, nr_msrs;
9894         struct perf_guest_switch_msr *msrs;
9895
9896         msrs = perf_guest_get_msrs(&nr_msrs);
9897
9898         if (!msrs)
9899                 return;
9900
9901         for (i = 0; i < nr_msrs; i++)
9902                 if (msrs[i].host == msrs[i].guest)
9903                         clear_atomic_switch_msr(vmx, msrs[i].msr);
9904                 else
9905                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
9906                                         msrs[i].host);
9907 }
9908
9909 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
9910 {
9911         struct vcpu_vmx *vmx = to_vmx(vcpu);
9912         u64 tscl;
9913         u32 delta_tsc;
9914
9915         if (vmx->hv_deadline_tsc == -1)
9916                 return;
9917
9918         tscl = rdtsc();
9919         if (vmx->hv_deadline_tsc > tscl)
9920                 /* sure to be 32 bit only because checked on set_hv_timer */
9921                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
9922                         cpu_preemption_timer_multi);
9923         else
9924                 delta_tsc = 0;
9925
9926         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9927 }
9928
9929 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
9930 {
9931         struct vcpu_vmx *vmx = to_vmx(vcpu);
9932         unsigned long cr3, cr4, evmcs_rsp;
9933
9934         /* Record the guest's net vcpu time for enforced NMI injections. */
9935         if (unlikely(!enable_vnmi &&
9936                      vmx->loaded_vmcs->soft_vnmi_blocked))
9937                 vmx->loaded_vmcs->entry_time = ktime_get();
9938
9939         /* Don't enter VMX if guest state is invalid, let the exit handler
9940            start emulation until we arrive back to a valid state */
9941         if (vmx->emulation_required)
9942                 return;
9943
9944         if (vmx->ple_window_dirty) {
9945                 vmx->ple_window_dirty = false;
9946                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9947         }
9948
9949         if (vmx->nested.sync_shadow_vmcs) {
9950                 copy_vmcs12_to_shadow(vmx);
9951                 vmx->nested.sync_shadow_vmcs = false;
9952         }
9953
9954         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9955                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9956         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9957                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9958
9959         cr3 = __get_current_cr3_fast();
9960         if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) {
9961                 vmcs_writel(HOST_CR3, cr3);
9962                 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
9963         }
9964
9965         cr4 = cr4_read_shadow();
9966         if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) {
9967                 vmcs_writel(HOST_CR4, cr4);
9968                 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
9969         }
9970
9971         /* When single-stepping over STI and MOV SS, we must clear the
9972          * corresponding interruptibility bits in the guest state. Otherwise
9973          * vmentry fails as it then expects bit 14 (BS) in pending debug
9974          * exceptions being set, but that's not correct for the guest debugging
9975          * case. */
9976         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9977                 vmx_set_interrupt_shadow(vcpu, 0);
9978
9979         if (static_cpu_has(X86_FEATURE_PKU) &&
9980             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
9981             vcpu->arch.pkru != vmx->host_pkru)
9982                 __write_pkru(vcpu->arch.pkru);
9983
9984         atomic_switch_perf_msrs(vmx);
9985
9986         vmx_arm_hv_timer(vcpu);
9987
9988         /*
9989          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
9990          * it's non-zero. Since vmentry is serialising on affected CPUs, there
9991          * is no need to worry about the conditional branch over the wrmsr
9992          * being speculatively taken.
9993          */
9994         if (vmx->spec_ctrl)
9995                 native_wrmsrl(MSR_IA32_SPEC_CTRL, vmx->spec_ctrl);
9996
9997         vmx->__launched = vmx->loaded_vmcs->launched;
9998
9999         evmcs_rsp = static_branch_unlikely(&enable_evmcs) ?
10000                 (unsigned long)&current_evmcs->host_rsp : 0;
10001
10002         asm(
10003                 /* Store host registers */
10004                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
10005                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
10006                 "push %%" _ASM_CX " \n\t"
10007                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10008                 "je 1f \n\t"
10009                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10010                 /* Avoid VMWRITE when Enlightened VMCS is in use */
10011                 "test %%" _ASM_SI ", %%" _ASM_SI " \n\t"
10012                 "jz 2f \n\t"
10013                 "mov %%" _ASM_SP ", (%%" _ASM_SI ") \n\t"
10014                 "jmp 1f \n\t"
10015                 "2: \n\t"
10016                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
10017                 "1: \n\t"
10018                 /* Reload cr2 if changed */
10019                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
10020                 "mov %%cr2, %%" _ASM_DX " \n\t"
10021                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
10022                 "je 3f \n\t"
10023                 "mov %%" _ASM_AX", %%cr2 \n\t"
10024                 "3: \n\t"
10025                 /* Check if vmlaunch of vmresume is needed */
10026                 "cmpl $0, %c[launched](%0) \n\t"
10027                 /* Load guest registers.  Don't clobber flags. */
10028                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
10029                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
10030                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
10031                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
10032                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
10033                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
10034 #ifdef CONFIG_X86_64
10035                 "mov %c[r8](%0),  %%r8  \n\t"
10036                 "mov %c[r9](%0),  %%r9  \n\t"
10037                 "mov %c[r10](%0), %%r10 \n\t"
10038                 "mov %c[r11](%0), %%r11 \n\t"
10039                 "mov %c[r12](%0), %%r12 \n\t"
10040                 "mov %c[r13](%0), %%r13 \n\t"
10041                 "mov %c[r14](%0), %%r14 \n\t"
10042                 "mov %c[r15](%0), %%r15 \n\t"
10043 #endif
10044                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
10045
10046                 /* Enter guest mode */
10047                 "jne 1f \n\t"
10048                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
10049                 "jmp 2f \n\t"
10050                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
10051                 "2: "
10052                 /* Save guest registers, load host registers, keep flags */
10053                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
10054                 "pop %0 \n\t"
10055                 "setbe %c[fail](%0)\n\t"
10056                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
10057                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
10058                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
10059                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
10060                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
10061                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
10062                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
10063 #ifdef CONFIG_X86_64
10064                 "mov %%r8,  %c[r8](%0) \n\t"
10065                 "mov %%r9,  %c[r9](%0) \n\t"
10066                 "mov %%r10, %c[r10](%0) \n\t"
10067                 "mov %%r11, %c[r11](%0) \n\t"
10068                 "mov %%r12, %c[r12](%0) \n\t"
10069                 "mov %%r13, %c[r13](%0) \n\t"
10070                 "mov %%r14, %c[r14](%0) \n\t"
10071                 "mov %%r15, %c[r15](%0) \n\t"
10072                 "xor %%r8d,  %%r8d \n\t"
10073                 "xor %%r9d,  %%r9d \n\t"
10074                 "xor %%r10d, %%r10d \n\t"
10075                 "xor %%r11d, %%r11d \n\t"
10076                 "xor %%r12d, %%r12d \n\t"
10077                 "xor %%r13d, %%r13d \n\t"
10078                 "xor %%r14d, %%r14d \n\t"
10079                 "xor %%r15d, %%r15d \n\t"
10080 #endif
10081                 "mov %%cr2, %%" _ASM_AX "   \n\t"
10082                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
10083
10084                 "xor %%eax, %%eax \n\t"
10085                 "xor %%ebx, %%ebx \n\t"
10086                 "xor %%esi, %%esi \n\t"
10087                 "xor %%edi, %%edi \n\t"
10088                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
10089                 ".pushsection .rodata \n\t"
10090                 ".global vmx_return \n\t"
10091                 "vmx_return: " _ASM_PTR " 2b \n\t"
10092                 ".popsection"
10093               : : "c"(vmx), "d"((unsigned long)HOST_RSP), "S"(evmcs_rsp),
10094                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
10095                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
10096                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
10097                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
10098                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
10099                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
10100                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
10101                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
10102                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
10103                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
10104 #ifdef CONFIG_X86_64
10105                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
10106                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
10107                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
10108                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
10109                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
10110                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
10111                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
10112                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
10113 #endif
10114                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
10115                 [wordsize]"i"(sizeof(ulong))
10116               : "cc", "memory"
10117 #ifdef CONFIG_X86_64
10118                 , "rax", "rbx", "rdi"
10119                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
10120 #else
10121                 , "eax", "ebx", "edi"
10122 #endif
10123               );
10124
10125         /*
10126          * We do not use IBRS in the kernel. If this vCPU has used the
10127          * SPEC_CTRL MSR it may have left it on; save the value and
10128          * turn it off. This is much more efficient than blindly adding
10129          * it to the atomic save/restore list. Especially as the former
10130          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
10131          *
10132          * For non-nested case:
10133          * If the L01 MSR bitmap does not intercept the MSR, then we need to
10134          * save it.
10135          *
10136          * For nested case:
10137          * If the L02 MSR bitmap does not intercept the MSR, then we need to
10138          * save it.
10139          */
10140         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
10141                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
10142
10143         if (vmx->spec_ctrl)
10144                 native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
10145
10146         /* Eliminate branch target predictions from guest mode */
10147         vmexit_fill_RSB();
10148
10149         /* All fields are clean at this point */
10150         if (static_branch_unlikely(&enable_evmcs))
10151                 current_evmcs->hv_clean_fields |=
10152                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
10153
10154         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
10155         if (vmx->host_debugctlmsr)
10156                 update_debugctlmsr(vmx->host_debugctlmsr);
10157
10158 #ifndef CONFIG_X86_64
10159         /*
10160          * The sysexit path does not restore ds/es, so we must set them to
10161          * a reasonable value ourselves.
10162          *
10163          * We can't defer this to vmx_load_host_state() since that function
10164          * may be executed in interrupt context, which saves and restore segments
10165          * around it, nullifying its effect.
10166          */
10167         loadsegment(ds, __USER_DS);
10168         loadsegment(es, __USER_DS);
10169 #endif
10170
10171         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
10172                                   | (1 << VCPU_EXREG_RFLAGS)
10173                                   | (1 << VCPU_EXREG_PDPTR)
10174                                   | (1 << VCPU_EXREG_SEGMENTS)
10175                                   | (1 << VCPU_EXREG_CR3));
10176         vcpu->arch.regs_dirty = 0;
10177
10178         /*
10179          * eager fpu is enabled if PKEY is supported and CR4 is switched
10180          * back on host, so it is safe to read guest PKRU from current
10181          * XSAVE.
10182          */
10183         if (static_cpu_has(X86_FEATURE_PKU) &&
10184             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
10185                 vcpu->arch.pkru = __read_pkru();
10186                 if (vcpu->arch.pkru != vmx->host_pkru)
10187                         __write_pkru(vmx->host_pkru);
10188         }
10189
10190         vmx->nested.nested_run_pending = 0;
10191         vmx->idt_vectoring_info = 0;
10192
10193         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
10194         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
10195                 return;
10196
10197         vmx->loaded_vmcs->launched = 1;
10198         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
10199
10200         vmx_complete_atomic_exit(vmx);
10201         vmx_recover_nmi_blocking(vmx);
10202         vmx_complete_interrupts(vmx);
10203 }
10204 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
10205
10206 static struct kvm *vmx_vm_alloc(void)
10207 {
10208         struct kvm_vmx *kvm_vmx = vzalloc(sizeof(struct kvm_vmx));
10209         return &kvm_vmx->kvm;
10210 }
10211
10212 static void vmx_vm_free(struct kvm *kvm)
10213 {
10214         vfree(to_kvm_vmx(kvm));
10215 }
10216
10217 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
10218 {
10219         struct vcpu_vmx *vmx = to_vmx(vcpu);
10220         int cpu;
10221
10222         if (vmx->loaded_vmcs == vmcs)
10223                 return;
10224
10225         cpu = get_cpu();
10226         vmx->loaded_vmcs = vmcs;
10227         vmx_vcpu_put(vcpu);
10228         vmx_vcpu_load(vcpu, cpu);
10229         put_cpu();
10230 }
10231
10232 /*
10233  * Ensure that the current vmcs of the logical processor is the
10234  * vmcs01 of the vcpu before calling free_nested().
10235  */
10236 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
10237 {
10238        struct vcpu_vmx *vmx = to_vmx(vcpu);
10239
10240        vcpu_load(vcpu);
10241        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10242        free_nested(vmx);
10243        vcpu_put(vcpu);
10244 }
10245
10246 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
10247 {
10248         struct vcpu_vmx *vmx = to_vmx(vcpu);
10249
10250         if (enable_pml)
10251                 vmx_destroy_pml_buffer(vmx);
10252         free_vpid(vmx->vpid);
10253         leave_guest_mode(vcpu);
10254         vmx_free_vcpu_nested(vcpu);
10255         free_loaded_vmcs(vmx->loaded_vmcs);
10256         kfree(vmx->guest_msrs);
10257         kvm_vcpu_uninit(vcpu);
10258         kmem_cache_free(kvm_vcpu_cache, vmx);
10259 }
10260
10261 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
10262 {
10263         int err;
10264         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
10265         unsigned long *msr_bitmap;
10266         int cpu;
10267
10268         if (!vmx)
10269                 return ERR_PTR(-ENOMEM);
10270
10271         vmx->vpid = allocate_vpid();
10272
10273         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
10274         if (err)
10275                 goto free_vcpu;
10276
10277         err = -ENOMEM;
10278
10279         /*
10280          * If PML is turned on, failure on enabling PML just results in failure
10281          * of creating the vcpu, therefore we can simplify PML logic (by
10282          * avoiding dealing with cases, such as enabling PML partially on vcpus
10283          * for the guest, etc.
10284          */
10285         if (enable_pml) {
10286                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
10287                 if (!vmx->pml_pg)
10288                         goto uninit_vcpu;
10289         }
10290
10291         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
10292         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
10293                      > PAGE_SIZE);
10294
10295         if (!vmx->guest_msrs)
10296                 goto free_pml;
10297
10298         err = alloc_loaded_vmcs(&vmx->vmcs01);
10299         if (err < 0)
10300                 goto free_msrs;
10301
10302         msr_bitmap = vmx->vmcs01.msr_bitmap;
10303         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
10304         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
10305         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
10306         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
10307         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
10308         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
10309         vmx->msr_bitmap_mode = 0;
10310
10311         vmx->loaded_vmcs = &vmx->vmcs01;
10312         cpu = get_cpu();
10313         vmx_vcpu_load(&vmx->vcpu, cpu);
10314         vmx->vcpu.cpu = cpu;
10315         vmx_vcpu_setup(vmx);
10316         vmx_vcpu_put(&vmx->vcpu);
10317         put_cpu();
10318         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
10319                 err = alloc_apic_access_page(kvm);
10320                 if (err)
10321                         goto free_vmcs;
10322         }
10323
10324         if (enable_ept && !enable_unrestricted_guest) {
10325                 err = init_rmode_identity_map(kvm);
10326                 if (err)
10327                         goto free_vmcs;
10328         }
10329
10330         if (nested) {
10331                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
10332                                            kvm_vcpu_apicv_active(&vmx->vcpu));
10333                 vmx->nested.vpid02 = allocate_vpid();
10334         }
10335
10336         vmx->nested.posted_intr_nv = -1;
10337         vmx->nested.current_vmptr = -1ull;
10338
10339         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
10340
10341         /*
10342          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
10343          * or POSTED_INTR_WAKEUP_VECTOR.
10344          */
10345         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
10346         vmx->pi_desc.sn = 1;
10347
10348         return &vmx->vcpu;
10349
10350 free_vmcs:
10351         free_vpid(vmx->nested.vpid02);
10352         free_loaded_vmcs(vmx->loaded_vmcs);
10353 free_msrs:
10354         kfree(vmx->guest_msrs);
10355 free_pml:
10356         vmx_destroy_pml_buffer(vmx);
10357 uninit_vcpu:
10358         kvm_vcpu_uninit(&vmx->vcpu);
10359 free_vcpu:
10360         free_vpid(vmx->vpid);
10361         kmem_cache_free(kvm_vcpu_cache, vmx);
10362         return ERR_PTR(err);
10363 }
10364
10365 static int vmx_vm_init(struct kvm *kvm)
10366 {
10367         if (!ple_gap)
10368                 kvm->arch.pause_in_guest = true;
10369         return 0;
10370 }
10371
10372 static void __init vmx_check_processor_compat(void *rtn)
10373 {
10374         struct vmcs_config vmcs_conf;
10375
10376         *(int *)rtn = 0;
10377         if (setup_vmcs_config(&vmcs_conf) < 0)
10378                 *(int *)rtn = -EIO;
10379         nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, enable_apicv);
10380         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
10381                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
10382                                 smp_processor_id());
10383                 *(int *)rtn = -EIO;
10384         }
10385 }
10386
10387 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
10388 {
10389         u8 cache;
10390         u64 ipat = 0;
10391
10392         /* For VT-d and EPT combination
10393          * 1. MMIO: always map as UC
10394          * 2. EPT with VT-d:
10395          *   a. VT-d without snooping control feature: can't guarantee the
10396          *      result, try to trust guest.
10397          *   b. VT-d with snooping control feature: snooping control feature of
10398          *      VT-d engine can guarantee the cache correctness. Just set it
10399          *      to WB to keep consistent with host. So the same as item 3.
10400          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
10401          *    consistent with host MTRR
10402          */
10403         if (is_mmio) {
10404                 cache = MTRR_TYPE_UNCACHABLE;
10405                 goto exit;
10406         }
10407
10408         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
10409                 ipat = VMX_EPT_IPAT_BIT;
10410                 cache = MTRR_TYPE_WRBACK;
10411                 goto exit;
10412         }
10413
10414         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
10415                 ipat = VMX_EPT_IPAT_BIT;
10416                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
10417                         cache = MTRR_TYPE_WRBACK;
10418                 else
10419                         cache = MTRR_TYPE_UNCACHABLE;
10420                 goto exit;
10421         }
10422
10423         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
10424
10425 exit:
10426         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
10427 }
10428
10429 static int vmx_get_lpage_level(void)
10430 {
10431         if (enable_ept && !cpu_has_vmx_ept_1g_page())
10432                 return PT_DIRECTORY_LEVEL;
10433         else
10434                 /* For shadow and EPT supported 1GB page */
10435                 return PT_PDPE_LEVEL;
10436 }
10437
10438 static void vmcs_set_secondary_exec_control(u32 new_ctl)
10439 {
10440         /*
10441          * These bits in the secondary execution controls field
10442          * are dynamic, the others are mostly based on the hypervisor
10443          * architecture and the guest's CPUID.  Do not touch the
10444          * dynamic bits.
10445          */
10446         u32 mask =
10447                 SECONDARY_EXEC_SHADOW_VMCS |
10448                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
10449                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10450                 SECONDARY_EXEC_DESC;
10451
10452         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
10453
10454         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
10455                      (new_ctl & ~mask) | (cur_ctl & mask));
10456 }
10457
10458 /*
10459  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
10460  * (indicating "allowed-1") if they are supported in the guest's CPUID.
10461  */
10462 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
10463 {
10464         struct vcpu_vmx *vmx = to_vmx(vcpu);
10465         struct kvm_cpuid_entry2 *entry;
10466
10467         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
10468         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
10469
10470 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
10471         if (entry && (entry->_reg & (_cpuid_mask)))                     \
10472                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
10473 } while (0)
10474
10475         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
10476         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
10477         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
10478         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
10479         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
10480         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
10481         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
10482         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
10483         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
10484         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
10485         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
10486         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
10487         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
10488         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
10489         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
10490
10491         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
10492         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
10493         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
10494         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
10495         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
10496         cr4_fixed1_update(X86_CR4_UMIP,       ecx, bit(X86_FEATURE_UMIP));
10497
10498 #undef cr4_fixed1_update
10499 }
10500
10501 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
10502 {
10503         struct vcpu_vmx *vmx = to_vmx(vcpu);
10504
10505         if (cpu_has_secondary_exec_ctrls()) {
10506                 vmx_compute_secondary_exec_control(vmx);
10507                 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
10508         }
10509
10510         if (nested_vmx_allowed(vcpu))
10511                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
10512                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
10513         else
10514                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
10515                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
10516
10517         if (nested_vmx_allowed(vcpu))
10518                 nested_vmx_cr_fixed1_bits_update(vcpu);
10519 }
10520
10521 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
10522 {
10523         if (func == 1 && nested)
10524                 entry->ecx |= bit(X86_FEATURE_VMX);
10525 }
10526
10527 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
10528                 struct x86_exception *fault)
10529 {
10530         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10531         struct vcpu_vmx *vmx = to_vmx(vcpu);
10532         u32 exit_reason;
10533         unsigned long exit_qualification = vcpu->arch.exit_qualification;
10534
10535         if (vmx->nested.pml_full) {
10536                 exit_reason = EXIT_REASON_PML_FULL;
10537                 vmx->nested.pml_full = false;
10538                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
10539         } else if (fault->error_code & PFERR_RSVD_MASK)
10540                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
10541         else
10542                 exit_reason = EXIT_REASON_EPT_VIOLATION;
10543
10544         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
10545         vmcs12->guest_physical_address = fault->address;
10546 }
10547
10548 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
10549 {
10550         return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
10551 }
10552
10553 /* Callbacks for nested_ept_init_mmu_context: */
10554
10555 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
10556 {
10557         /* return the page table to be shadowed - in our case, EPT12 */
10558         return get_vmcs12(vcpu)->ept_pointer;
10559 }
10560
10561 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
10562 {
10563         WARN_ON(mmu_is_nested(vcpu));
10564         if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
10565                 return 1;
10566
10567         kvm_mmu_unload(vcpu);
10568         kvm_init_shadow_ept_mmu(vcpu,
10569                         to_vmx(vcpu)->nested.msrs.ept_caps &
10570                         VMX_EPT_EXECUTE_ONLY_BIT,
10571                         nested_ept_ad_enabled(vcpu));
10572         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
10573         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
10574         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
10575
10576         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
10577         return 0;
10578 }
10579
10580 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
10581 {
10582         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
10583 }
10584
10585 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
10586                                             u16 error_code)
10587 {
10588         bool inequality, bit;
10589
10590         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
10591         inequality =
10592                 (error_code & vmcs12->page_fault_error_code_mask) !=
10593                  vmcs12->page_fault_error_code_match;
10594         return inequality ^ bit;
10595 }
10596
10597 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
10598                 struct x86_exception *fault)
10599 {
10600         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10601
10602         WARN_ON(!is_guest_mode(vcpu));
10603
10604         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
10605                 !to_vmx(vcpu)->nested.nested_run_pending) {
10606                 vmcs12->vm_exit_intr_error_code = fault->error_code;
10607                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10608                                   PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
10609                                   INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
10610                                   fault->address);
10611         } else {
10612                 kvm_inject_page_fault(vcpu, fault);
10613         }
10614 }
10615
10616 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10617                                                  struct vmcs12 *vmcs12);
10618
10619 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
10620                                         struct vmcs12 *vmcs12)
10621 {
10622         struct vcpu_vmx *vmx = to_vmx(vcpu);
10623         struct page *page;
10624         u64 hpa;
10625
10626         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10627                 /*
10628                  * Translate L1 physical address to host physical
10629                  * address for vmcs02. Keep the page pinned, so this
10630                  * physical address remains valid. We keep a reference
10631                  * to it so we can release it later.
10632                  */
10633                 if (vmx->nested.apic_access_page) { /* shouldn't happen */
10634                         kvm_release_page_dirty(vmx->nested.apic_access_page);
10635                         vmx->nested.apic_access_page = NULL;
10636                 }
10637                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
10638                 /*
10639                  * If translation failed, no matter: This feature asks
10640                  * to exit when accessing the given address, and if it
10641                  * can never be accessed, this feature won't do
10642                  * anything anyway.
10643                  */
10644                 if (!is_error_page(page)) {
10645                         vmx->nested.apic_access_page = page;
10646                         hpa = page_to_phys(vmx->nested.apic_access_page);
10647                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
10648                 } else {
10649                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
10650                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10651                 }
10652         }
10653
10654         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
10655                 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
10656                         kvm_release_page_dirty(vmx->nested.virtual_apic_page);
10657                         vmx->nested.virtual_apic_page = NULL;
10658                 }
10659                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
10660
10661                 /*
10662                  * If translation failed, VM entry will fail because
10663                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
10664                  * Failing the vm entry is _not_ what the processor
10665                  * does but it's basically the only possibility we
10666                  * have.  We could still enter the guest if CR8 load
10667                  * exits are enabled, CR8 store exits are enabled, and
10668                  * virtualize APIC access is disabled; in this case
10669                  * the processor would never use the TPR shadow and we
10670                  * could simply clear the bit from the execution
10671                  * control.  But such a configuration is useless, so
10672                  * let's keep the code simple.
10673                  */
10674                 if (!is_error_page(page)) {
10675                         vmx->nested.virtual_apic_page = page;
10676                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
10677                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
10678                 }
10679         }
10680
10681         if (nested_cpu_has_posted_intr(vmcs12)) {
10682                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
10683                         kunmap(vmx->nested.pi_desc_page);
10684                         kvm_release_page_dirty(vmx->nested.pi_desc_page);
10685                         vmx->nested.pi_desc_page = NULL;
10686                 }
10687                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
10688                 if (is_error_page(page))
10689                         return;
10690                 vmx->nested.pi_desc_page = page;
10691                 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
10692                 vmx->nested.pi_desc =
10693                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
10694                         (unsigned long)(vmcs12->posted_intr_desc_addr &
10695                         (PAGE_SIZE - 1)));
10696                 vmcs_write64(POSTED_INTR_DESC_ADDR,
10697                         page_to_phys(vmx->nested.pi_desc_page) +
10698                         (unsigned long)(vmcs12->posted_intr_desc_addr &
10699                         (PAGE_SIZE - 1)));
10700         }
10701         if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
10702                 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
10703                               CPU_BASED_USE_MSR_BITMAPS);
10704         else
10705                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
10706                                 CPU_BASED_USE_MSR_BITMAPS);
10707 }
10708
10709 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
10710 {
10711         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
10712         struct vcpu_vmx *vmx = to_vmx(vcpu);
10713
10714         if (vcpu->arch.virtual_tsc_khz == 0)
10715                 return;
10716
10717         /* Make sure short timeouts reliably trigger an immediate vmexit.
10718          * hrtimer_start does not guarantee this. */
10719         if (preemption_timeout <= 1) {
10720                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
10721                 return;
10722         }
10723
10724         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10725         preemption_timeout *= 1000000;
10726         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
10727         hrtimer_start(&vmx->nested.preemption_timer,
10728                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
10729 }
10730
10731 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
10732                                                struct vmcs12 *vmcs12)
10733 {
10734         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
10735                 return 0;
10736
10737         if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
10738             !page_address_valid(vcpu, vmcs12->io_bitmap_b))
10739                 return -EINVAL;
10740
10741         return 0;
10742 }
10743
10744 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
10745                                                 struct vmcs12 *vmcs12)
10746 {
10747         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10748                 return 0;
10749
10750         if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
10751                 return -EINVAL;
10752
10753         return 0;
10754 }
10755
10756 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
10757                                                 struct vmcs12 *vmcs12)
10758 {
10759         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10760                 return 0;
10761
10762         if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
10763                 return -EINVAL;
10764
10765         return 0;
10766 }
10767
10768 /*
10769  * Merge L0's and L1's MSR bitmap, return false to indicate that
10770  * we do not use the hardware.
10771  */
10772 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10773                                                  struct vmcs12 *vmcs12)
10774 {
10775         int msr;
10776         struct page *page;
10777         unsigned long *msr_bitmap_l1;
10778         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
10779         /*
10780          * pred_cmd & spec_ctrl are trying to verify two things:
10781          *
10782          * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
10783          *    ensures that we do not accidentally generate an L02 MSR bitmap
10784          *    from the L12 MSR bitmap that is too permissive.
10785          * 2. That L1 or L2s have actually used the MSR. This avoids
10786          *    unnecessarily merging of the bitmap if the MSR is unused. This
10787          *    works properly because we only update the L01 MSR bitmap lazily.
10788          *    So even if L0 should pass L1 these MSRs, the L01 bitmap is only
10789          *    updated to reflect this when L1 (or its L2s) actually write to
10790          *    the MSR.
10791          */
10792         bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
10793         bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
10794
10795         /* Nothing to do if the MSR bitmap is not in use.  */
10796         if (!cpu_has_vmx_msr_bitmap() ||
10797             !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10798                 return false;
10799
10800         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10801             !pred_cmd && !spec_ctrl)
10802                 return false;
10803
10804         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
10805         if (is_error_page(page))
10806                 return false;
10807
10808         msr_bitmap_l1 = (unsigned long *)kmap(page);
10809         if (nested_cpu_has_apic_reg_virt(vmcs12)) {
10810                 /*
10811                  * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it
10812                  * just lets the processor take the value from the virtual-APIC page;
10813                  * take those 256 bits directly from the L1 bitmap.
10814                  */
10815                 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10816                         unsigned word = msr / BITS_PER_LONG;
10817                         msr_bitmap_l0[word] = msr_bitmap_l1[word];
10818                         msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10819                 }
10820         } else {
10821                 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10822                         unsigned word = msr / BITS_PER_LONG;
10823                         msr_bitmap_l0[word] = ~0;
10824                         msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10825                 }
10826         }
10827
10828         nested_vmx_disable_intercept_for_msr(
10829                 msr_bitmap_l1, msr_bitmap_l0,
10830                 X2APIC_MSR(APIC_TASKPRI),
10831                 MSR_TYPE_W);
10832
10833         if (nested_cpu_has_vid(vmcs12)) {
10834                 nested_vmx_disable_intercept_for_msr(
10835                         msr_bitmap_l1, msr_bitmap_l0,
10836                         X2APIC_MSR(APIC_EOI),
10837                         MSR_TYPE_W);
10838                 nested_vmx_disable_intercept_for_msr(
10839                         msr_bitmap_l1, msr_bitmap_l0,
10840                         X2APIC_MSR(APIC_SELF_IPI),
10841                         MSR_TYPE_W);
10842         }
10843
10844         if (spec_ctrl)
10845                 nested_vmx_disable_intercept_for_msr(
10846                                         msr_bitmap_l1, msr_bitmap_l0,
10847                                         MSR_IA32_SPEC_CTRL,
10848                                         MSR_TYPE_R | MSR_TYPE_W);
10849
10850         if (pred_cmd)
10851                 nested_vmx_disable_intercept_for_msr(
10852                                         msr_bitmap_l1, msr_bitmap_l0,
10853                                         MSR_IA32_PRED_CMD,
10854                                         MSR_TYPE_W);
10855
10856         kunmap(page);
10857         kvm_release_page_clean(page);
10858
10859         return true;
10860 }
10861
10862 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu,
10863                                           struct vmcs12 *vmcs12)
10864 {
10865         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
10866             !page_address_valid(vcpu, vmcs12->apic_access_addr))
10867                 return -EINVAL;
10868         else
10869                 return 0;
10870 }
10871
10872 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
10873                                            struct vmcs12 *vmcs12)
10874 {
10875         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10876             !nested_cpu_has_apic_reg_virt(vmcs12) &&
10877             !nested_cpu_has_vid(vmcs12) &&
10878             !nested_cpu_has_posted_intr(vmcs12))
10879                 return 0;
10880
10881         /*
10882          * If virtualize x2apic mode is enabled,
10883          * virtualize apic access must be disabled.
10884          */
10885         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10886             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
10887                 return -EINVAL;
10888
10889         /*
10890          * If virtual interrupt delivery is enabled,
10891          * we must exit on external interrupts.
10892          */
10893         if (nested_cpu_has_vid(vmcs12) &&
10894            !nested_exit_on_intr(vcpu))
10895                 return -EINVAL;
10896
10897         /*
10898          * bits 15:8 should be zero in posted_intr_nv,
10899          * the descriptor address has been already checked
10900          * in nested_get_vmcs12_pages.
10901          */
10902         if (nested_cpu_has_posted_intr(vmcs12) &&
10903            (!nested_cpu_has_vid(vmcs12) ||
10904             !nested_exit_intr_ack_set(vcpu) ||
10905             vmcs12->posted_intr_nv & 0xff00))
10906                 return -EINVAL;
10907
10908         /* tpr shadow is needed by all apicv features. */
10909         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10910                 return -EINVAL;
10911
10912         return 0;
10913 }
10914
10915 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
10916                                        unsigned long count_field,
10917                                        unsigned long addr_field)
10918 {
10919         int maxphyaddr;
10920         u64 count, addr;
10921
10922         if (vmcs12_read_any(vcpu, count_field, &count) ||
10923             vmcs12_read_any(vcpu, addr_field, &addr)) {
10924                 WARN_ON(1);
10925                 return -EINVAL;
10926         }
10927         if (count == 0)
10928                 return 0;
10929         maxphyaddr = cpuid_maxphyaddr(vcpu);
10930         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
10931             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
10932                 pr_debug_ratelimited(
10933                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10934                         addr_field, maxphyaddr, count, addr);
10935                 return -EINVAL;
10936         }
10937         return 0;
10938 }
10939
10940 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
10941                                                 struct vmcs12 *vmcs12)
10942 {
10943         if (vmcs12->vm_exit_msr_load_count == 0 &&
10944             vmcs12->vm_exit_msr_store_count == 0 &&
10945             vmcs12->vm_entry_msr_load_count == 0)
10946                 return 0; /* Fast path */
10947         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
10948                                         VM_EXIT_MSR_LOAD_ADDR) ||
10949             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
10950                                         VM_EXIT_MSR_STORE_ADDR) ||
10951             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
10952                                         VM_ENTRY_MSR_LOAD_ADDR))
10953                 return -EINVAL;
10954         return 0;
10955 }
10956
10957 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
10958                                          struct vmcs12 *vmcs12)
10959 {
10960         u64 address = vmcs12->pml_address;
10961         int maxphyaddr = cpuid_maxphyaddr(vcpu);
10962
10963         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
10964                 if (!nested_cpu_has_ept(vmcs12) ||
10965                     !IS_ALIGNED(address, 4096)  ||
10966                     address >> maxphyaddr)
10967                         return -EINVAL;
10968         }
10969
10970         return 0;
10971 }
10972
10973 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
10974                                        struct vmx_msr_entry *e)
10975 {
10976         /* x2APIC MSR accesses are not allowed */
10977         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
10978                 return -EINVAL;
10979         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
10980             e->index == MSR_IA32_UCODE_REV)
10981                 return -EINVAL;
10982         if (e->reserved != 0)
10983                 return -EINVAL;
10984         return 0;
10985 }
10986
10987 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
10988                                      struct vmx_msr_entry *e)
10989 {
10990         if (e->index == MSR_FS_BASE ||
10991             e->index == MSR_GS_BASE ||
10992             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
10993             nested_vmx_msr_check_common(vcpu, e))
10994                 return -EINVAL;
10995         return 0;
10996 }
10997
10998 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
10999                                       struct vmx_msr_entry *e)
11000 {
11001         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
11002             nested_vmx_msr_check_common(vcpu, e))
11003                 return -EINVAL;
11004         return 0;
11005 }
11006
11007 /*
11008  * Load guest's/host's msr at nested entry/exit.
11009  * return 0 for success, entry index for failure.
11010  */
11011 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11012 {
11013         u32 i;
11014         struct vmx_msr_entry e;
11015         struct msr_data msr;
11016
11017         msr.host_initiated = false;
11018         for (i = 0; i < count; i++) {
11019                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
11020                                         &e, sizeof(e))) {
11021                         pr_debug_ratelimited(
11022                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11023                                 __func__, i, gpa + i * sizeof(e));
11024                         goto fail;
11025                 }
11026                 if (nested_vmx_load_msr_check(vcpu, &e)) {
11027                         pr_debug_ratelimited(
11028                                 "%s check failed (%u, 0x%x, 0x%x)\n",
11029                                 __func__, i, e.index, e.reserved);
11030                         goto fail;
11031                 }
11032                 msr.index = e.index;
11033                 msr.data = e.value;
11034                 if (kvm_set_msr(vcpu, &msr)) {
11035                         pr_debug_ratelimited(
11036                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11037                                 __func__, i, e.index, e.value);
11038                         goto fail;
11039                 }
11040         }
11041         return 0;
11042 fail:
11043         return i + 1;
11044 }
11045
11046 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11047 {
11048         u32 i;
11049         struct vmx_msr_entry e;
11050
11051         for (i = 0; i < count; i++) {
11052                 struct msr_data msr_info;
11053                 if (kvm_vcpu_read_guest(vcpu,
11054                                         gpa + i * sizeof(e),
11055                                         &e, 2 * sizeof(u32))) {
11056                         pr_debug_ratelimited(
11057                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11058                                 __func__, i, gpa + i * sizeof(e));
11059                         return -EINVAL;
11060                 }
11061                 if (nested_vmx_store_msr_check(vcpu, &e)) {
11062                         pr_debug_ratelimited(
11063                                 "%s check failed (%u, 0x%x, 0x%x)\n",
11064                                 __func__, i, e.index, e.reserved);
11065                         return -EINVAL;
11066                 }
11067                 msr_info.host_initiated = false;
11068                 msr_info.index = e.index;
11069                 if (kvm_get_msr(vcpu, &msr_info)) {
11070                         pr_debug_ratelimited(
11071                                 "%s cannot read MSR (%u, 0x%x)\n",
11072                                 __func__, i, e.index);
11073                         return -EINVAL;
11074                 }
11075                 if (kvm_vcpu_write_guest(vcpu,
11076                                          gpa + i * sizeof(e) +
11077                                              offsetof(struct vmx_msr_entry, value),
11078                                          &msr_info.data, sizeof(msr_info.data))) {
11079                         pr_debug_ratelimited(
11080                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11081                                 __func__, i, e.index, msr_info.data);
11082                         return -EINVAL;
11083                 }
11084         }
11085         return 0;
11086 }
11087
11088 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
11089 {
11090         unsigned long invalid_mask;
11091
11092         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
11093         return (val & invalid_mask) == 0;
11094 }
11095
11096 /*
11097  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
11098  * emulating VM entry into a guest with EPT enabled.
11099  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
11100  * is assigned to entry_failure_code on failure.
11101  */
11102 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
11103                                u32 *entry_failure_code)
11104 {
11105         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
11106                 if (!nested_cr3_valid(vcpu, cr3)) {
11107                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
11108                         return 1;
11109                 }
11110
11111                 /*
11112                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
11113                  * must not be dereferenced.
11114                  */
11115                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
11116                     !nested_ept) {
11117                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
11118                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
11119                                 return 1;
11120                         }
11121                 }
11122
11123                 vcpu->arch.cr3 = cr3;
11124                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
11125         }
11126
11127         kvm_mmu_reset_context(vcpu);
11128         return 0;
11129 }
11130
11131 static void prepare_vmcs02_full(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11132 {
11133         struct vcpu_vmx *vmx = to_vmx(vcpu);
11134
11135         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
11136         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
11137         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
11138         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
11139         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
11140         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
11141         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
11142         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
11143         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
11144         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
11145         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
11146         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
11147         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
11148         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
11149         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
11150         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
11151         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
11152         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
11153         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
11154         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
11155         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
11156         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
11157         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
11158         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
11159         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
11160         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
11161         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
11162         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
11163         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
11164         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
11165         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
11166
11167         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
11168         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
11169                 vmcs12->guest_pending_dbg_exceptions);
11170         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
11171         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
11172
11173         if (nested_cpu_has_xsaves(vmcs12))
11174                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
11175         vmcs_write64(VMCS_LINK_POINTER, -1ull);
11176
11177         if (cpu_has_vmx_posted_intr())
11178                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
11179
11180         /*
11181          * Whether page-faults are trapped is determined by a combination of
11182          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
11183          * If enable_ept, L0 doesn't care about page faults and we should
11184          * set all of these to L1's desires. However, if !enable_ept, L0 does
11185          * care about (at least some) page faults, and because it is not easy
11186          * (if at all possible?) to merge L0 and L1's desires, we simply ask
11187          * to exit on each and every L2 page fault. This is done by setting
11188          * MASK=MATCH=0 and (see below) EB.PF=1.
11189          * Note that below we don't need special code to set EB.PF beyond the
11190          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
11191          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
11192          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
11193          */
11194         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
11195                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
11196         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
11197                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
11198
11199         /* All VMFUNCs are currently emulated through L0 vmexits.  */
11200         if (cpu_has_vmx_vmfunc())
11201                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
11202
11203         if (cpu_has_vmx_apicv()) {
11204                 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
11205                 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
11206                 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
11207                 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
11208         }
11209
11210         /*
11211          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
11212          * Some constant fields are set here by vmx_set_constant_host_state().
11213          * Other fields are different per CPU, and will be set later when
11214          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
11215          */
11216         vmx_set_constant_host_state(vmx);
11217
11218         /*
11219          * Set the MSR load/store lists to match L0's settings.
11220          */
11221         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
11222         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11223         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
11224         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11225         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
11226
11227         set_cr4_guest_host_mask(vmx);
11228
11229         if (vmx_mpx_supported())
11230                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
11231
11232         if (enable_vpid) {
11233                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
11234                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
11235                 else
11236                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
11237         }
11238
11239         /*
11240          * L1 may access the L2's PDPTR, so save them to construct vmcs12
11241          */
11242         if (enable_ept) {
11243                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
11244                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
11245                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
11246                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
11247         }
11248
11249         if (cpu_has_vmx_msr_bitmap())
11250                 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
11251 }
11252
11253 /*
11254  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
11255  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
11256  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
11257  * guest in a way that will both be appropriate to L1's requests, and our
11258  * needs. In addition to modifying the active vmcs (which is vmcs02), this
11259  * function also has additional necessary side-effects, like setting various
11260  * vcpu->arch fields.
11261  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
11262  * is assigned to entry_failure_code on failure.
11263  */
11264 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11265                           u32 *entry_failure_code)
11266 {
11267         struct vcpu_vmx *vmx = to_vmx(vcpu);
11268         u32 exec_control, vmcs12_exec_ctrl;
11269
11270         if (vmx->nested.dirty_vmcs12) {
11271                 prepare_vmcs02_full(vcpu, vmcs12);
11272                 vmx->nested.dirty_vmcs12 = false;
11273         }
11274
11275         /*
11276          * First, the fields that are shadowed.  This must be kept in sync
11277          * with vmx_shadow_fields.h.
11278          */
11279
11280         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
11281         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
11282         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
11283         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
11284         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
11285
11286         /*
11287          * Not in vmcs02: GUEST_PML_INDEX, HOST_FS_SELECTOR, HOST_GS_SELECTOR,
11288          * HOST_FS_BASE, HOST_GS_BASE.
11289          */
11290
11291         if (vmx->nested.nested_run_pending &&
11292             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
11293                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
11294                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
11295         } else {
11296                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
11297                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
11298         }
11299         if (vmx->nested.nested_run_pending) {
11300                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
11301                              vmcs12->vm_entry_intr_info_field);
11302                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
11303                              vmcs12->vm_entry_exception_error_code);
11304                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
11305                              vmcs12->vm_entry_instruction_len);
11306                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
11307                              vmcs12->guest_interruptibility_info);
11308                 vmx->loaded_vmcs->nmi_known_unmasked =
11309                         !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
11310         } else {
11311                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
11312         }
11313         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
11314
11315         exec_control = vmcs12->pin_based_vm_exec_control;
11316
11317         /* Preemption timer setting is only taken from vmcs01.  */
11318         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
11319         exec_control |= vmcs_config.pin_based_exec_ctrl;
11320         if (vmx->hv_deadline_tsc == -1)
11321                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
11322
11323         /* Posted interrupts setting is only taken from vmcs12.  */
11324         if (nested_cpu_has_posted_intr(vmcs12)) {
11325                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
11326                 vmx->nested.pi_pending = false;
11327         } else {
11328                 exec_control &= ~PIN_BASED_POSTED_INTR;
11329         }
11330
11331         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
11332
11333         vmx->nested.preemption_timer_expired = false;
11334         if (nested_cpu_has_preemption_timer(vmcs12))
11335                 vmx_start_preemption_timer(vcpu);
11336
11337         if (cpu_has_secondary_exec_ctrls()) {
11338                 exec_control = vmx->secondary_exec_control;
11339
11340                 /* Take the following fields only from vmcs12 */
11341                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
11342                                   SECONDARY_EXEC_ENABLE_INVPCID |
11343                                   SECONDARY_EXEC_RDTSCP |
11344                                   SECONDARY_EXEC_XSAVES |
11345                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
11346                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
11347                                   SECONDARY_EXEC_ENABLE_VMFUNC);
11348                 if (nested_cpu_has(vmcs12,
11349                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
11350                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
11351                                 ~SECONDARY_EXEC_ENABLE_PML;
11352                         exec_control |= vmcs12_exec_ctrl;
11353                 }
11354
11355                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
11356                         vmcs_write16(GUEST_INTR_STATUS,
11357                                 vmcs12->guest_intr_status);
11358
11359                 /*
11360                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
11361                  * nested_get_vmcs12_pages will either fix it up or
11362                  * remove the VM execution control.
11363                  */
11364                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
11365                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
11366
11367                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
11368         }
11369
11370         /*
11371          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
11372          * entry, but only if the current (host) sp changed from the value
11373          * we wrote last (vmx->host_rsp). This cache is no longer relevant
11374          * if we switch vmcs, and rather than hold a separate cache per vmcs,
11375          * here we just force the write to happen on entry.
11376          */
11377         vmx->host_rsp = 0;
11378
11379         exec_control = vmx_exec_control(vmx); /* L0's desires */
11380         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
11381         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
11382         exec_control &= ~CPU_BASED_TPR_SHADOW;
11383         exec_control |= vmcs12->cpu_based_vm_exec_control;
11384
11385         /*
11386          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
11387          * nested_get_vmcs12_pages can't fix it up, the illegal value
11388          * will result in a VM entry failure.
11389          */
11390         if (exec_control & CPU_BASED_TPR_SHADOW) {
11391                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
11392                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
11393         } else {
11394 #ifdef CONFIG_X86_64
11395                 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
11396                                 CPU_BASED_CR8_STORE_EXITING;
11397 #endif
11398         }
11399
11400         /*
11401          * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
11402          * for I/O port accesses.
11403          */
11404         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
11405         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
11406
11407         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
11408
11409         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
11410          * bitwise-or of what L1 wants to trap for L2, and what we want to
11411          * trap. Note that CR0.TS also needs updating - we do this later.
11412          */
11413         update_exception_bitmap(vcpu);
11414         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
11415         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
11416
11417         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
11418          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
11419          * bits are further modified by vmx_set_efer() below.
11420          */
11421         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
11422
11423         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
11424          * emulated by vmx_set_efer(), below.
11425          */
11426         vm_entry_controls_init(vmx,
11427                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
11428                         ~VM_ENTRY_IA32E_MODE) |
11429                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
11430
11431         if (vmx->nested.nested_run_pending &&
11432             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
11433                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
11434                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
11435         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
11436                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
11437         }
11438
11439         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11440
11441         if (kvm_has_tsc_control)
11442                 decache_tsc_multiplier(vmx);
11443
11444         if (enable_vpid) {
11445                 /*
11446                  * There is no direct mapping between vpid02 and vpid12, the
11447                  * vpid02 is per-vCPU for L0 and reused while the value of
11448                  * vpid12 is changed w/ one invvpid during nested vmentry.
11449                  * The vpid12 is allocated by L1 for L2, so it will not
11450                  * influence global bitmap(for vpid01 and vpid02 allocation)
11451                  * even if spawn a lot of nested vCPUs.
11452                  */
11453                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
11454                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
11455                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
11456                                 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
11457                         }
11458                 } else {
11459                         vmx_flush_tlb(vcpu, true);
11460                 }
11461         }
11462
11463         if (enable_pml) {
11464                 /*
11465                  * Conceptually we want to copy the PML address and index from
11466                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
11467                  * since we always flush the log on each vmexit, this happens
11468                  * to be equivalent to simply resetting the fields in vmcs02.
11469                  */
11470                 ASSERT(vmx->pml_pg);
11471                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
11472                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
11473         }
11474
11475         if (nested_cpu_has_ept(vmcs12)) {
11476                 if (nested_ept_init_mmu_context(vcpu)) {
11477                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
11478                         return 1;
11479                 }
11480         } else if (nested_cpu_has2(vmcs12,
11481                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11482                 vmx_flush_tlb(vcpu, true);
11483         }
11484
11485         /*
11486          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
11487          * bits which we consider mandatory enabled.
11488          * The CR0_READ_SHADOW is what L2 should have expected to read given
11489          * the specifications by L1; It's not enough to take
11490          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
11491          * have more bits than L1 expected.
11492          */
11493         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
11494         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
11495
11496         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
11497         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
11498
11499         if (vmx->nested.nested_run_pending &&
11500             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
11501                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
11502         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
11503                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11504         else
11505                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11506         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
11507         vmx_set_efer(vcpu, vcpu->arch.efer);
11508
11509         /*
11510          * Guest state is invalid and unrestricted guest is disabled,
11511          * which means L1 attempted VMEntry to L2 with invalid state.
11512          * Fail the VMEntry.
11513          */
11514         if (vmx->emulation_required) {
11515                 *entry_failure_code = ENTRY_FAIL_DEFAULT;
11516                 return 1;
11517         }
11518
11519         /* Shadow page tables on either EPT or shadow page tables. */
11520         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
11521                                 entry_failure_code))
11522                 return 1;
11523
11524         if (!enable_ept)
11525                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
11526
11527         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
11528         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
11529         return 0;
11530 }
11531
11532 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12)
11533 {
11534         if (!nested_cpu_has_nmi_exiting(vmcs12) &&
11535             nested_cpu_has_virtual_nmis(vmcs12))
11536                 return -EINVAL;
11537
11538         if (!nested_cpu_has_virtual_nmis(vmcs12) &&
11539             nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING))
11540                 return -EINVAL;
11541
11542         return 0;
11543 }
11544
11545 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11546 {
11547         struct vcpu_vmx *vmx = to_vmx(vcpu);
11548
11549         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
11550             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
11551                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11552
11553         if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
11554                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11555
11556         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
11557                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11558
11559         if (nested_vmx_check_apic_access_controls(vcpu, vmcs12))
11560                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11561
11562         if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
11563                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11564
11565         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
11566                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11567
11568         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
11569                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11570
11571         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
11572                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11573
11574         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
11575                                 vmx->nested.msrs.procbased_ctls_low,
11576                                 vmx->nested.msrs.procbased_ctls_high) ||
11577             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
11578              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
11579                                  vmx->nested.msrs.secondary_ctls_low,
11580                                  vmx->nested.msrs.secondary_ctls_high)) ||
11581             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
11582                                 vmx->nested.msrs.pinbased_ctls_low,
11583                                 vmx->nested.msrs.pinbased_ctls_high) ||
11584             !vmx_control_verify(vmcs12->vm_exit_controls,
11585                                 vmx->nested.msrs.exit_ctls_low,
11586                                 vmx->nested.msrs.exit_ctls_high) ||
11587             !vmx_control_verify(vmcs12->vm_entry_controls,
11588                                 vmx->nested.msrs.entry_ctls_low,
11589                                 vmx->nested.msrs.entry_ctls_high))
11590                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11591
11592         if (nested_vmx_check_nmi_controls(vmcs12))
11593                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11594
11595         if (nested_cpu_has_vmfunc(vmcs12)) {
11596                 if (vmcs12->vm_function_control &
11597                     ~vmx->nested.msrs.vmfunc_controls)
11598                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11599
11600                 if (nested_cpu_has_eptp_switching(vmcs12)) {
11601                         if (!nested_cpu_has_ept(vmcs12) ||
11602                             !page_address_valid(vcpu, vmcs12->eptp_list_address))
11603                                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11604                 }
11605         }
11606
11607         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
11608                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11609
11610         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
11611             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
11612             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
11613                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
11614
11615         return 0;
11616 }
11617
11618 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11619                                   u32 *exit_qual)
11620 {
11621         bool ia32e;
11622
11623         *exit_qual = ENTRY_FAIL_DEFAULT;
11624
11625         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
11626             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
11627                 return 1;
11628
11629         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
11630             vmcs12->vmcs_link_pointer != -1ull) {
11631                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
11632                 return 1;
11633         }
11634
11635         /*
11636          * If the load IA32_EFER VM-entry control is 1, the following checks
11637          * are performed on the field for the IA32_EFER MSR:
11638          * - Bits reserved in the IA32_EFER MSR must be 0.
11639          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
11640          *   the IA-32e mode guest VM-exit control. It must also be identical
11641          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
11642          *   CR0.PG) is 1.
11643          */
11644         if (to_vmx(vcpu)->nested.nested_run_pending &&
11645             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
11646                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
11647                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
11648                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
11649                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
11650                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
11651                         return 1;
11652         }
11653
11654         /*
11655          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
11656          * IA32_EFER MSR must be 0 in the field for that register. In addition,
11657          * the values of the LMA and LME bits in the field must each be that of
11658          * the host address-space size VM-exit control.
11659          */
11660         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
11661                 ia32e = (vmcs12->vm_exit_controls &
11662                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
11663                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
11664                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
11665                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
11666                         return 1;
11667         }
11668
11669         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
11670                 (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) ||
11671                 (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))
11672                         return 1;
11673
11674         return 0;
11675 }
11676
11677 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu)
11678 {
11679         struct vcpu_vmx *vmx = to_vmx(vcpu);
11680         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11681         u32 msr_entry_idx;
11682         u32 exit_qual;
11683         int r;
11684
11685         enter_guest_mode(vcpu);
11686
11687         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
11688                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11689
11690         vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
11691         vmx_segment_cache_clear(vmx);
11692
11693         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
11694                 vcpu->arch.tsc_offset += vmcs12->tsc_offset;
11695
11696         r = EXIT_REASON_INVALID_STATE;
11697         if (prepare_vmcs02(vcpu, vmcs12, &exit_qual))
11698                 goto fail;
11699
11700         nested_get_vmcs12_pages(vcpu, vmcs12);
11701
11702         r = EXIT_REASON_MSR_LOAD_FAIL;
11703         msr_entry_idx = nested_vmx_load_msr(vcpu,
11704                                             vmcs12->vm_entry_msr_load_addr,
11705                                             vmcs12->vm_entry_msr_load_count);
11706         if (msr_entry_idx)
11707                 goto fail;
11708
11709         /*
11710          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
11711          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
11712          * returned as far as L1 is concerned. It will only return (and set
11713          * the success flag) when L2 exits (see nested_vmx_vmexit()).
11714          */
11715         return 0;
11716
11717 fail:
11718         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
11719                 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
11720         leave_guest_mode(vcpu);
11721         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11722         nested_vmx_entry_failure(vcpu, vmcs12, r, exit_qual);
11723         return 1;
11724 }
11725
11726 /*
11727  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
11728  * for running an L2 nested guest.
11729  */
11730 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
11731 {
11732         struct vmcs12 *vmcs12;
11733         struct vcpu_vmx *vmx = to_vmx(vcpu);
11734         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
11735         u32 exit_qual;
11736         int ret;
11737
11738         if (!nested_vmx_check_permission(vcpu))
11739                 return 1;
11740
11741         if (!nested_vmx_check_vmcs12(vcpu))
11742                 goto out;
11743
11744         vmcs12 = get_vmcs12(vcpu);
11745
11746         if (enable_shadow_vmcs)
11747                 copy_shadow_to_vmcs12(vmx);
11748
11749         /*
11750          * The nested entry process starts with enforcing various prerequisites
11751          * on vmcs12 as required by the Intel SDM, and act appropriately when
11752          * they fail: As the SDM explains, some conditions should cause the
11753          * instruction to fail, while others will cause the instruction to seem
11754          * to succeed, but return an EXIT_REASON_INVALID_STATE.
11755          * To speed up the normal (success) code path, we should avoid checking
11756          * for misconfigurations which will anyway be caught by the processor
11757          * when using the merged vmcs02.
11758          */
11759         if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
11760                 nested_vmx_failValid(vcpu,
11761                                      VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
11762                 goto out;
11763         }
11764
11765         if (vmcs12->launch_state == launch) {
11766                 nested_vmx_failValid(vcpu,
11767                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
11768                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
11769                 goto out;
11770         }
11771
11772         ret = check_vmentry_prereqs(vcpu, vmcs12);
11773         if (ret) {
11774                 nested_vmx_failValid(vcpu, ret);
11775                 goto out;
11776         }
11777
11778         /*
11779          * After this point, the trap flag no longer triggers a singlestep trap
11780          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
11781          * This is not 100% correct; for performance reasons, we delegate most
11782          * of the checks on host state to the processor.  If those fail,
11783          * the singlestep trap is missed.
11784          */
11785         skip_emulated_instruction(vcpu);
11786
11787         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
11788         if (ret) {
11789                 nested_vmx_entry_failure(vcpu, vmcs12,
11790                                          EXIT_REASON_INVALID_STATE, exit_qual);
11791                 return 1;
11792         }
11793
11794         /*
11795          * We're finally done with prerequisite checking, and can start with
11796          * the nested entry.
11797          */
11798
11799         vmx->nested.nested_run_pending = 1;
11800         ret = enter_vmx_non_root_mode(vcpu);
11801         if (ret) {
11802                 vmx->nested.nested_run_pending = 0;
11803                 return ret;
11804         }
11805
11806         /*
11807          * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken
11808          * by event injection, halt vcpu.
11809          */
11810         if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) &&
11811             !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK)) {
11812                 vmx->nested.nested_run_pending = 0;
11813                 return kvm_vcpu_halt(vcpu);
11814         }
11815         return 1;
11816
11817 out:
11818         return kvm_skip_emulated_instruction(vcpu);
11819 }
11820
11821 /*
11822  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11823  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11824  * This function returns the new value we should put in vmcs12.guest_cr0.
11825  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11826  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11827  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11828  *     didn't trap the bit, because if L1 did, so would L0).
11829  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11830  *     been modified by L2, and L1 knows it. So just leave the old value of
11831  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11832  *     isn't relevant, because if L0 traps this bit it can set it to anything.
11833  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11834  *     changed these bits, and therefore they need to be updated, but L0
11835  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11836  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11837  */
11838 static inline unsigned long
11839 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11840 {
11841         return
11842         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
11843         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
11844         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
11845                         vcpu->arch.cr0_guest_owned_bits));
11846 }
11847
11848 static inline unsigned long
11849 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11850 {
11851         return
11852         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
11853         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
11854         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
11855                         vcpu->arch.cr4_guest_owned_bits));
11856 }
11857
11858 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
11859                                        struct vmcs12 *vmcs12)
11860 {
11861         u32 idt_vectoring;
11862         unsigned int nr;
11863
11864         if (vcpu->arch.exception.injected) {
11865                 nr = vcpu->arch.exception.nr;
11866                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11867
11868                 if (kvm_exception_is_soft(nr)) {
11869                         vmcs12->vm_exit_instruction_len =
11870                                 vcpu->arch.event_exit_inst_len;
11871                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
11872                 } else
11873                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
11874
11875                 if (vcpu->arch.exception.has_error_code) {
11876                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
11877                         vmcs12->idt_vectoring_error_code =
11878                                 vcpu->arch.exception.error_code;
11879                 }
11880
11881                 vmcs12->idt_vectoring_info_field = idt_vectoring;
11882         } else if (vcpu->arch.nmi_injected) {
11883                 vmcs12->idt_vectoring_info_field =
11884                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
11885         } else if (vcpu->arch.interrupt.injected) {
11886                 nr = vcpu->arch.interrupt.nr;
11887                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11888
11889                 if (vcpu->arch.interrupt.soft) {
11890                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
11891                         vmcs12->vm_entry_instruction_len =
11892                                 vcpu->arch.event_exit_inst_len;
11893                 } else
11894                         idt_vectoring |= INTR_TYPE_EXT_INTR;
11895
11896                 vmcs12->idt_vectoring_info_field = idt_vectoring;
11897         }
11898 }
11899
11900 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
11901 {
11902         struct vcpu_vmx *vmx = to_vmx(vcpu);
11903         unsigned long exit_qual;
11904         bool block_nested_events =
11905             vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
11906
11907         if (vcpu->arch.exception.pending &&
11908                 nested_vmx_check_exception(vcpu, &exit_qual)) {
11909                 if (block_nested_events)
11910                         return -EBUSY;
11911                 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
11912                 return 0;
11913         }
11914
11915         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
11916             vmx->nested.preemption_timer_expired) {
11917                 if (block_nested_events)
11918                         return -EBUSY;
11919                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
11920                 return 0;
11921         }
11922
11923         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
11924                 if (block_nested_events)
11925                         return -EBUSY;
11926                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
11927                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
11928                                   INTR_INFO_VALID_MASK, 0);
11929                 /*
11930                  * The NMI-triggered VM exit counts as injection:
11931                  * clear this one and block further NMIs.
11932                  */
11933                 vcpu->arch.nmi_pending = 0;
11934                 vmx_set_nmi_mask(vcpu, true);
11935                 return 0;
11936         }
11937
11938         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
11939             nested_exit_on_intr(vcpu)) {
11940                 if (block_nested_events)
11941                         return -EBUSY;
11942                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
11943                 return 0;
11944         }
11945
11946         vmx_complete_nested_posted_interrupt(vcpu);
11947         return 0;
11948 }
11949
11950 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
11951 {
11952         ktime_t remaining =
11953                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
11954         u64 value;
11955
11956         if (ktime_to_ns(remaining) <= 0)
11957                 return 0;
11958
11959         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
11960         do_div(value, 1000000);
11961         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
11962 }
11963
11964 /*
11965  * Update the guest state fields of vmcs12 to reflect changes that
11966  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11967  * VM-entry controls is also updated, since this is really a guest
11968  * state bit.)
11969  */
11970 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11971 {
11972         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
11973         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
11974
11975         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
11976         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
11977         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
11978
11979         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
11980         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
11981         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
11982         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
11983         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
11984         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
11985         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
11986         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
11987         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
11988         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
11989         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
11990         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
11991         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
11992         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
11993         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
11994         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
11995         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
11996         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
11997         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
11998         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
11999         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
12000         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
12001         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
12002         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
12003         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
12004         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
12005         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
12006         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
12007         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
12008         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
12009         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
12010         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
12011         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
12012         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
12013         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
12014         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
12015
12016         vmcs12->guest_interruptibility_info =
12017                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
12018         vmcs12->guest_pending_dbg_exceptions =
12019                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
12020         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
12021                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
12022         else
12023                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
12024
12025         if (nested_cpu_has_preemption_timer(vmcs12)) {
12026                 if (vmcs12->vm_exit_controls &
12027                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
12028                         vmcs12->vmx_preemption_timer_value =
12029                                 vmx_get_preemption_timer_value(vcpu);
12030                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
12031         }
12032
12033         /*
12034          * In some cases (usually, nested EPT), L2 is allowed to change its
12035          * own CR3 without exiting. If it has changed it, we must keep it.
12036          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
12037          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
12038          *
12039          * Additionally, restore L2's PDPTR to vmcs12.
12040          */
12041         if (enable_ept) {
12042                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
12043                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
12044                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
12045                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
12046                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
12047         }
12048
12049         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
12050
12051         if (nested_cpu_has_vid(vmcs12))
12052                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
12053
12054         vmcs12->vm_entry_controls =
12055                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
12056                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
12057
12058         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
12059                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
12060                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
12061         }
12062
12063         /* TODO: These cannot have changed unless we have MSR bitmaps and
12064          * the relevant bit asks not to trap the change */
12065         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
12066                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
12067         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
12068                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
12069         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
12070         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
12071         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
12072         if (kvm_mpx_supported())
12073                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
12074 }
12075
12076 /*
12077  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
12078  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
12079  * and this function updates it to reflect the changes to the guest state while
12080  * L2 was running (and perhaps made some exits which were handled directly by L0
12081  * without going back to L1), and to reflect the exit reason.
12082  * Note that we do not have to copy here all VMCS fields, just those that
12083  * could have changed by the L2 guest or the exit - i.e., the guest-state and
12084  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
12085  * which already writes to vmcs12 directly.
12086  */
12087 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
12088                            u32 exit_reason, u32 exit_intr_info,
12089                            unsigned long exit_qualification)
12090 {
12091         /* update guest state fields: */
12092         sync_vmcs12(vcpu, vmcs12);
12093
12094         /* update exit information fields: */
12095
12096         vmcs12->vm_exit_reason = exit_reason;
12097         vmcs12->exit_qualification = exit_qualification;
12098         vmcs12->vm_exit_intr_info = exit_intr_info;
12099
12100         vmcs12->idt_vectoring_info_field = 0;
12101         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
12102         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
12103
12104         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
12105                 vmcs12->launch_state = 1;
12106
12107                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
12108                  * instead of reading the real value. */
12109                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
12110
12111                 /*
12112                  * Transfer the event that L0 or L1 may wanted to inject into
12113                  * L2 to IDT_VECTORING_INFO_FIELD.
12114                  */
12115                 vmcs12_save_pending_event(vcpu, vmcs12);
12116         }
12117
12118         /*
12119          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
12120          * preserved above and would only end up incorrectly in L1.
12121          */
12122         vcpu->arch.nmi_injected = false;
12123         kvm_clear_exception_queue(vcpu);
12124         kvm_clear_interrupt_queue(vcpu);
12125 }
12126
12127 static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu,
12128                         struct vmcs12 *vmcs12)
12129 {
12130         u32 entry_failure_code;
12131
12132         nested_ept_uninit_mmu_context(vcpu);
12133
12134         /*
12135          * Only PDPTE load can fail as the value of cr3 was checked on entry and
12136          * couldn't have changed.
12137          */
12138         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
12139                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
12140
12141         if (!enable_ept)
12142                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
12143 }
12144
12145 /*
12146  * A part of what we need to when the nested L2 guest exits and we want to
12147  * run its L1 parent, is to reset L1's guest state to the host state specified
12148  * in vmcs12.
12149  * This function is to be called not only on normal nested exit, but also on
12150  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
12151  * Failures During or After Loading Guest State").
12152  * This function should be called when the active VMCS is L1's (vmcs01).
12153  */
12154 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
12155                                    struct vmcs12 *vmcs12)
12156 {
12157         struct kvm_segment seg;
12158
12159         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
12160                 vcpu->arch.efer = vmcs12->host_ia32_efer;
12161         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
12162                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
12163         else
12164                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
12165         vmx_set_efer(vcpu, vcpu->arch.efer);
12166
12167         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
12168         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
12169         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
12170         /*
12171          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
12172          * actually changed, because vmx_set_cr0 refers to efer set above.
12173          *
12174          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
12175          * (KVM doesn't change it);
12176          */
12177         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
12178         vmx_set_cr0(vcpu, vmcs12->host_cr0);
12179
12180         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
12181         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
12182         vmx_set_cr4(vcpu, vmcs12->host_cr4);
12183
12184         load_vmcs12_mmu_host_state(vcpu, vmcs12);
12185
12186         /*
12187          * If vmcs01 don't use VPID, CPU flushes TLB on every
12188          * VMEntry/VMExit. Thus, no need to flush TLB.
12189          *
12190          * If vmcs12 uses VPID, TLB entries populated by L2 are
12191          * tagged with vmx->nested.vpid02 while L1 entries are tagged
12192          * with vmx->vpid. Thus, no need to flush TLB.
12193          *
12194          * Therefore, flush TLB only in case vmcs01 uses VPID and
12195          * vmcs12 don't use VPID as in this case L1 & L2 TLB entries
12196          * are both tagged with vmx->vpid.
12197          */
12198         if (enable_vpid &&
12199             !(nested_cpu_has_vpid(vmcs12) && to_vmx(vcpu)->nested.vpid02)) {
12200                 vmx_flush_tlb(vcpu, true);
12201         }
12202
12203         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
12204         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
12205         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
12206         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
12207         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
12208         vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
12209         vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
12210
12211         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
12212         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
12213                 vmcs_write64(GUEST_BNDCFGS, 0);
12214
12215         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
12216                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
12217                 vcpu->arch.pat = vmcs12->host_ia32_pat;
12218         }
12219         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
12220                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
12221                         vmcs12->host_ia32_perf_global_ctrl);
12222
12223         /* Set L1 segment info according to Intel SDM
12224             27.5.2 Loading Host Segment and Descriptor-Table Registers */
12225         seg = (struct kvm_segment) {
12226                 .base = 0,
12227                 .limit = 0xFFFFFFFF,
12228                 .selector = vmcs12->host_cs_selector,
12229                 .type = 11,
12230                 .present = 1,
12231                 .s = 1,
12232                 .g = 1
12233         };
12234         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
12235                 seg.l = 1;
12236         else
12237                 seg.db = 1;
12238         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
12239         seg = (struct kvm_segment) {
12240                 .base = 0,
12241                 .limit = 0xFFFFFFFF,
12242                 .type = 3,
12243                 .present = 1,
12244                 .s = 1,
12245                 .db = 1,
12246                 .g = 1
12247         };
12248         seg.selector = vmcs12->host_ds_selector;
12249         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
12250         seg.selector = vmcs12->host_es_selector;
12251         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
12252         seg.selector = vmcs12->host_ss_selector;
12253         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
12254         seg.selector = vmcs12->host_fs_selector;
12255         seg.base = vmcs12->host_fs_base;
12256         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
12257         seg.selector = vmcs12->host_gs_selector;
12258         seg.base = vmcs12->host_gs_base;
12259         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
12260         seg = (struct kvm_segment) {
12261                 .base = vmcs12->host_tr_base,
12262                 .limit = 0x67,
12263                 .selector = vmcs12->host_tr_selector,
12264                 .type = 11,
12265                 .present = 1
12266         };
12267         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
12268
12269         kvm_set_dr(vcpu, 7, 0x400);
12270         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
12271
12272         if (cpu_has_vmx_msr_bitmap())
12273                 vmx_update_msr_bitmap(vcpu);
12274
12275         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
12276                                 vmcs12->vm_exit_msr_load_count))
12277                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
12278 }
12279
12280 /*
12281  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
12282  * and modify vmcs12 to make it see what it would expect to see there if
12283  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
12284  */
12285 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
12286                               u32 exit_intr_info,
12287                               unsigned long exit_qualification)
12288 {
12289         struct vcpu_vmx *vmx = to_vmx(vcpu);
12290         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12291
12292         /* trying to cancel vmlaunch/vmresume is a bug */
12293         WARN_ON_ONCE(vmx->nested.nested_run_pending);
12294
12295         /*
12296          * The only expected VM-instruction error is "VM entry with
12297          * invalid control field(s)." Anything else indicates a
12298          * problem with L0.
12299          */
12300         WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
12301                                    VMXERR_ENTRY_INVALID_CONTROL_FIELD));
12302
12303         leave_guest_mode(vcpu);
12304
12305         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
12306                 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
12307
12308         if (likely(!vmx->fail)) {
12309                 if (exit_reason == -1)
12310                         sync_vmcs12(vcpu, vmcs12);
12311                 else
12312                         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
12313                                        exit_qualification);
12314
12315                 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
12316                                          vmcs12->vm_exit_msr_store_count))
12317                         nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
12318         }
12319
12320         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
12321         vm_entry_controls_reset_shadow(vmx);
12322         vm_exit_controls_reset_shadow(vmx);
12323         vmx_segment_cache_clear(vmx);
12324
12325         /* Update any VMCS fields that might have changed while L2 ran */
12326         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
12327         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
12328         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
12329         if (vmx->hv_deadline_tsc == -1)
12330                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
12331                                 PIN_BASED_VMX_PREEMPTION_TIMER);
12332         else
12333                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
12334                               PIN_BASED_VMX_PREEMPTION_TIMER);
12335         if (kvm_has_tsc_control)
12336                 decache_tsc_multiplier(vmx);
12337
12338         if (vmx->nested.change_vmcs01_virtual_apic_mode) {
12339                 vmx->nested.change_vmcs01_virtual_apic_mode = false;
12340                 vmx_set_virtual_apic_mode(vcpu);
12341         } else if (!nested_cpu_has_ept(vmcs12) &&
12342                    nested_cpu_has2(vmcs12,
12343                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
12344                 vmx_flush_tlb(vcpu, true);
12345         }
12346
12347         /* This is needed for same reason as it was needed in prepare_vmcs02 */
12348         vmx->host_rsp = 0;
12349
12350         /* Unpin physical memory we referred to in vmcs02 */
12351         if (vmx->nested.apic_access_page) {
12352                 kvm_release_page_dirty(vmx->nested.apic_access_page);
12353                 vmx->nested.apic_access_page = NULL;
12354         }
12355         if (vmx->nested.virtual_apic_page) {
12356                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
12357                 vmx->nested.virtual_apic_page = NULL;
12358         }
12359         if (vmx->nested.pi_desc_page) {
12360                 kunmap(vmx->nested.pi_desc_page);
12361                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
12362                 vmx->nested.pi_desc_page = NULL;
12363                 vmx->nested.pi_desc = NULL;
12364         }
12365
12366         /*
12367          * We are now running in L2, mmu_notifier will force to reload the
12368          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
12369          */
12370         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
12371
12372         if (enable_shadow_vmcs && exit_reason != -1)
12373                 vmx->nested.sync_shadow_vmcs = true;
12374
12375         /* in case we halted in L2 */
12376         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
12377
12378         if (likely(!vmx->fail)) {
12379                 /*
12380                  * TODO: SDM says that with acknowledge interrupt on
12381                  * exit, bit 31 of the VM-exit interrupt information
12382                  * (valid interrupt) is always set to 1 on
12383                  * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
12384                  * need kvm_cpu_has_interrupt().  See the commit
12385                  * message for details.
12386                  */
12387                 if (nested_exit_intr_ack_set(vcpu) &&
12388                     exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
12389                     kvm_cpu_has_interrupt(vcpu)) {
12390                         int irq = kvm_cpu_get_interrupt(vcpu);
12391                         WARN_ON(irq < 0);
12392                         vmcs12->vm_exit_intr_info = irq |
12393                                 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
12394                 }
12395
12396                 if (exit_reason != -1)
12397                         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
12398                                                        vmcs12->exit_qualification,
12399                                                        vmcs12->idt_vectoring_info_field,
12400                                                        vmcs12->vm_exit_intr_info,
12401                                                        vmcs12->vm_exit_intr_error_code,
12402                                                        KVM_ISA_VMX);
12403
12404                 load_vmcs12_host_state(vcpu, vmcs12);
12405
12406                 return;
12407         }
12408
12409         /*
12410          * After an early L2 VM-entry failure, we're now back
12411          * in L1 which thinks it just finished a VMLAUNCH or
12412          * VMRESUME instruction, so we need to set the failure
12413          * flag and the VM-instruction error field of the VMCS
12414          * accordingly.
12415          */
12416         nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
12417
12418         load_vmcs12_mmu_host_state(vcpu, vmcs12);
12419
12420         /*
12421          * The emulated instruction was already skipped in
12422          * nested_vmx_run, but the updated RIP was never
12423          * written back to the vmcs01.
12424          */
12425         skip_emulated_instruction(vcpu);
12426         vmx->fail = 0;
12427 }
12428
12429 /*
12430  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
12431  */
12432 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
12433 {
12434         if (is_guest_mode(vcpu)) {
12435                 to_vmx(vcpu)->nested.nested_run_pending = 0;
12436                 nested_vmx_vmexit(vcpu, -1, 0, 0);
12437         }
12438         free_nested(to_vmx(vcpu));
12439 }
12440
12441 /*
12442  * L1's failure to enter L2 is a subset of a normal exit, as explained in
12443  * 23.7 "VM-entry failures during or after loading guest state" (this also
12444  * lists the acceptable exit-reason and exit-qualification parameters).
12445  * It should only be called before L2 actually succeeded to run, and when
12446  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
12447  */
12448 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
12449                         struct vmcs12 *vmcs12,
12450                         u32 reason, unsigned long qualification)
12451 {
12452         load_vmcs12_host_state(vcpu, vmcs12);
12453         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
12454         vmcs12->exit_qualification = qualification;
12455         nested_vmx_succeed(vcpu);
12456         if (enable_shadow_vmcs)
12457                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
12458 }
12459
12460 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
12461                                struct x86_instruction_info *info,
12462                                enum x86_intercept_stage stage)
12463 {
12464         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12465         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
12466
12467         /*
12468          * RDPID causes #UD if disabled through secondary execution controls.
12469          * Because it is marked as EmulateOnUD, we need to intercept it here.
12470          */
12471         if (info->intercept == x86_intercept_rdtscp &&
12472             !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
12473                 ctxt->exception.vector = UD_VECTOR;
12474                 ctxt->exception.error_code_valid = false;
12475                 return X86EMUL_PROPAGATE_FAULT;
12476         }
12477
12478         /* TODO: check more intercepts... */
12479         return X86EMUL_CONTINUE;
12480 }
12481
12482 #ifdef CONFIG_X86_64
12483 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
12484 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
12485                                   u64 divisor, u64 *result)
12486 {
12487         u64 low = a << shift, high = a >> (64 - shift);
12488
12489         /* To avoid the overflow on divq */
12490         if (high >= divisor)
12491                 return 1;
12492
12493         /* Low hold the result, high hold rem which is discarded */
12494         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
12495             "rm" (divisor), "0" (low), "1" (high));
12496         *result = low;
12497
12498         return 0;
12499 }
12500
12501 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
12502 {
12503         struct vcpu_vmx *vmx;
12504         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
12505
12506         if (kvm_mwait_in_guest(vcpu->kvm))
12507                 return -EOPNOTSUPP;
12508
12509         vmx = to_vmx(vcpu);
12510         tscl = rdtsc();
12511         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
12512         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
12513         lapic_timer_advance_cycles = nsec_to_cycles(vcpu, lapic_timer_advance_ns);
12514
12515         if (delta_tsc > lapic_timer_advance_cycles)
12516                 delta_tsc -= lapic_timer_advance_cycles;
12517         else
12518                 delta_tsc = 0;
12519
12520         /* Convert to host delta tsc if tsc scaling is enabled */
12521         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
12522                         u64_shl_div_u64(delta_tsc,
12523                                 kvm_tsc_scaling_ratio_frac_bits,
12524                                 vcpu->arch.tsc_scaling_ratio,
12525                                 &delta_tsc))
12526                 return -ERANGE;
12527
12528         /*
12529          * If the delta tsc can't fit in the 32 bit after the multi shift,
12530          * we can't use the preemption timer.
12531          * It's possible that it fits on later vmentries, but checking
12532          * on every vmentry is costly so we just use an hrtimer.
12533          */
12534         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
12535                 return -ERANGE;
12536
12537         vmx->hv_deadline_tsc = tscl + delta_tsc;
12538         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
12539                         PIN_BASED_VMX_PREEMPTION_TIMER);
12540
12541         return delta_tsc == 0;
12542 }
12543
12544 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
12545 {
12546         struct vcpu_vmx *vmx = to_vmx(vcpu);
12547         vmx->hv_deadline_tsc = -1;
12548         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
12549                         PIN_BASED_VMX_PREEMPTION_TIMER);
12550 }
12551 #endif
12552
12553 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
12554 {
12555         if (!kvm_pause_in_guest(vcpu->kvm))
12556                 shrink_ple_window(vcpu);
12557 }
12558
12559 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
12560                                      struct kvm_memory_slot *slot)
12561 {
12562         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
12563         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
12564 }
12565
12566 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
12567                                        struct kvm_memory_slot *slot)
12568 {
12569         kvm_mmu_slot_set_dirty(kvm, slot);
12570 }
12571
12572 static void vmx_flush_log_dirty(struct kvm *kvm)
12573 {
12574         kvm_flush_pml_buffers(kvm);
12575 }
12576
12577 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
12578 {
12579         struct vmcs12 *vmcs12;
12580         struct vcpu_vmx *vmx = to_vmx(vcpu);
12581         gpa_t gpa;
12582         struct page *page = NULL;
12583         u64 *pml_address;
12584
12585         if (is_guest_mode(vcpu)) {
12586                 WARN_ON_ONCE(vmx->nested.pml_full);
12587
12588                 /*
12589                  * Check if PML is enabled for the nested guest.
12590                  * Whether eptp bit 6 is set is already checked
12591                  * as part of A/D emulation.
12592                  */
12593                 vmcs12 = get_vmcs12(vcpu);
12594                 if (!nested_cpu_has_pml(vmcs12))
12595                         return 0;
12596
12597                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
12598                         vmx->nested.pml_full = true;
12599                         return 1;
12600                 }
12601
12602                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
12603
12604                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
12605                 if (is_error_page(page))
12606                         return 0;
12607
12608                 pml_address = kmap(page);
12609                 pml_address[vmcs12->guest_pml_index--] = gpa;
12610                 kunmap(page);
12611                 kvm_release_page_clean(page);
12612         }
12613
12614         return 0;
12615 }
12616
12617 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
12618                                            struct kvm_memory_slot *memslot,
12619                                            gfn_t offset, unsigned long mask)
12620 {
12621         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
12622 }
12623
12624 static void __pi_post_block(struct kvm_vcpu *vcpu)
12625 {
12626         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12627         struct pi_desc old, new;
12628         unsigned int dest;
12629
12630         do {
12631                 old.control = new.control = pi_desc->control;
12632                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
12633                      "Wakeup handler not enabled while the VCPU is blocked\n");
12634
12635                 dest = cpu_physical_id(vcpu->cpu);
12636
12637                 if (x2apic_enabled())
12638                         new.ndst = dest;
12639                 else
12640                         new.ndst = (dest << 8) & 0xFF00;
12641
12642                 /* set 'NV' to 'notification vector' */
12643                 new.nv = POSTED_INTR_VECTOR;
12644         } while (cmpxchg64(&pi_desc->control, old.control,
12645                            new.control) != old.control);
12646
12647         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
12648                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12649                 list_del(&vcpu->blocked_vcpu_list);
12650                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12651                 vcpu->pre_pcpu = -1;
12652         }
12653 }
12654
12655 /*
12656  * This routine does the following things for vCPU which is going
12657  * to be blocked if VT-d PI is enabled.
12658  * - Store the vCPU to the wakeup list, so when interrupts happen
12659  *   we can find the right vCPU to wake up.
12660  * - Change the Posted-interrupt descriptor as below:
12661  *      'NDST' <-- vcpu->pre_pcpu
12662  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
12663  * - If 'ON' is set during this process, which means at least one
12664  *   interrupt is posted for this vCPU, we cannot block it, in
12665  *   this case, return 1, otherwise, return 0.
12666  *
12667  */
12668 static int pi_pre_block(struct kvm_vcpu *vcpu)
12669 {
12670         unsigned int dest;
12671         struct pi_desc old, new;
12672         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12673
12674         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
12675                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
12676                 !kvm_vcpu_apicv_active(vcpu))
12677                 return 0;
12678
12679         WARN_ON(irqs_disabled());
12680         local_irq_disable();
12681         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
12682                 vcpu->pre_pcpu = vcpu->cpu;
12683                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12684                 list_add_tail(&vcpu->blocked_vcpu_list,
12685                               &per_cpu(blocked_vcpu_on_cpu,
12686                                        vcpu->pre_pcpu));
12687                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12688         }
12689
12690         do {
12691                 old.control = new.control = pi_desc->control;
12692
12693                 WARN((pi_desc->sn == 1),
12694                      "Warning: SN field of posted-interrupts "
12695                      "is set before blocking\n");
12696
12697                 /*
12698                  * Since vCPU can be preempted during this process,
12699                  * vcpu->cpu could be different with pre_pcpu, we
12700                  * need to set pre_pcpu as the destination of wakeup
12701                  * notification event, then we can find the right vCPU
12702                  * to wakeup in wakeup handler if interrupts happen
12703                  * when the vCPU is in blocked state.
12704                  */
12705                 dest = cpu_physical_id(vcpu->pre_pcpu);
12706
12707                 if (x2apic_enabled())
12708                         new.ndst = dest;
12709                 else
12710                         new.ndst = (dest << 8) & 0xFF00;
12711
12712                 /* set 'NV' to 'wakeup vector' */
12713                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
12714         } while (cmpxchg64(&pi_desc->control, old.control,
12715                            new.control) != old.control);
12716
12717         /* We should not block the vCPU if an interrupt is posted for it.  */
12718         if (pi_test_on(pi_desc) == 1)
12719                 __pi_post_block(vcpu);
12720
12721         local_irq_enable();
12722         return (vcpu->pre_pcpu == -1);
12723 }
12724
12725 static int vmx_pre_block(struct kvm_vcpu *vcpu)
12726 {
12727         if (pi_pre_block(vcpu))
12728                 return 1;
12729
12730         if (kvm_lapic_hv_timer_in_use(vcpu))
12731                 kvm_lapic_switch_to_sw_timer(vcpu);
12732
12733         return 0;
12734 }
12735
12736 static void pi_post_block(struct kvm_vcpu *vcpu)
12737 {
12738         if (vcpu->pre_pcpu == -1)
12739                 return;
12740
12741         WARN_ON(irqs_disabled());
12742         local_irq_disable();
12743         __pi_post_block(vcpu);
12744         local_irq_enable();
12745 }
12746
12747 static void vmx_post_block(struct kvm_vcpu *vcpu)
12748 {
12749         if (kvm_x86_ops->set_hv_timer)
12750                 kvm_lapic_switch_to_hv_timer(vcpu);
12751
12752         pi_post_block(vcpu);
12753 }
12754
12755 /*
12756  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
12757  *
12758  * @kvm: kvm
12759  * @host_irq: host irq of the interrupt
12760  * @guest_irq: gsi of the interrupt
12761  * @set: set or unset PI
12762  * returns 0 on success, < 0 on failure
12763  */
12764 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
12765                               uint32_t guest_irq, bool set)
12766 {
12767         struct kvm_kernel_irq_routing_entry *e;
12768         struct kvm_irq_routing_table *irq_rt;
12769         struct kvm_lapic_irq irq;
12770         struct kvm_vcpu *vcpu;
12771         struct vcpu_data vcpu_info;
12772         int idx, ret = 0;
12773
12774         if (!kvm_arch_has_assigned_device(kvm) ||
12775                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
12776                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
12777                 return 0;
12778
12779         idx = srcu_read_lock(&kvm->irq_srcu);
12780         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
12781         if (guest_irq >= irq_rt->nr_rt_entries ||
12782             hlist_empty(&irq_rt->map[guest_irq])) {
12783                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
12784                              guest_irq, irq_rt->nr_rt_entries);
12785                 goto out;
12786         }
12787
12788         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
12789                 if (e->type != KVM_IRQ_ROUTING_MSI)
12790                         continue;
12791                 /*
12792                  * VT-d PI cannot support posting multicast/broadcast
12793                  * interrupts to a vCPU, we still use interrupt remapping
12794                  * for these kind of interrupts.
12795                  *
12796                  * For lowest-priority interrupts, we only support
12797                  * those with single CPU as the destination, e.g. user
12798                  * configures the interrupts via /proc/irq or uses
12799                  * irqbalance to make the interrupts single-CPU.
12800                  *
12801                  * We will support full lowest-priority interrupt later.
12802                  */
12803
12804                 kvm_set_msi_irq(kvm, e, &irq);
12805                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
12806                         /*
12807                          * Make sure the IRTE is in remapped mode if
12808                          * we don't handle it in posted mode.
12809                          */
12810                         ret = irq_set_vcpu_affinity(host_irq, NULL);
12811                         if (ret < 0) {
12812                                 printk(KERN_INFO
12813                                    "failed to back to remapped mode, irq: %u\n",
12814                                    host_irq);
12815                                 goto out;
12816                         }
12817
12818                         continue;
12819                 }
12820
12821                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
12822                 vcpu_info.vector = irq.vector;
12823
12824                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
12825                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
12826
12827                 if (set)
12828                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
12829                 else
12830                         ret = irq_set_vcpu_affinity(host_irq, NULL);
12831
12832                 if (ret < 0) {
12833                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
12834                                         __func__);
12835                         goto out;
12836                 }
12837         }
12838
12839         ret = 0;
12840 out:
12841         srcu_read_unlock(&kvm->irq_srcu, idx);
12842         return ret;
12843 }
12844
12845 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
12846 {
12847         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
12848                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
12849                         FEATURE_CONTROL_LMCE;
12850         else
12851                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
12852                         ~FEATURE_CONTROL_LMCE;
12853 }
12854
12855 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
12856 {
12857         /* we need a nested vmexit to enter SMM, postpone if run is pending */
12858         if (to_vmx(vcpu)->nested.nested_run_pending)
12859                 return 0;
12860         return 1;
12861 }
12862
12863 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
12864 {
12865         struct vcpu_vmx *vmx = to_vmx(vcpu);
12866
12867         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
12868         if (vmx->nested.smm.guest_mode)
12869                 nested_vmx_vmexit(vcpu, -1, 0, 0);
12870
12871         vmx->nested.smm.vmxon = vmx->nested.vmxon;
12872         vmx->nested.vmxon = false;
12873         vmx_clear_hlt(vcpu);
12874         return 0;
12875 }
12876
12877 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
12878 {
12879         struct vcpu_vmx *vmx = to_vmx(vcpu);
12880         int ret;
12881
12882         if (vmx->nested.smm.vmxon) {
12883                 vmx->nested.vmxon = true;
12884                 vmx->nested.smm.vmxon = false;
12885         }
12886
12887         if (vmx->nested.smm.guest_mode) {
12888                 vcpu->arch.hflags &= ~HF_SMM_MASK;
12889                 ret = enter_vmx_non_root_mode(vcpu);
12890                 vcpu->arch.hflags |= HF_SMM_MASK;
12891                 if (ret)
12892                         return ret;
12893
12894                 vmx->nested.smm.guest_mode = false;
12895         }
12896         return 0;
12897 }
12898
12899 static int enable_smi_window(struct kvm_vcpu *vcpu)
12900 {
12901         return 0;
12902 }
12903
12904 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
12905         .cpu_has_kvm_support = cpu_has_kvm_support,
12906         .disabled_by_bios = vmx_disabled_by_bios,
12907         .hardware_setup = hardware_setup,
12908         .hardware_unsetup = hardware_unsetup,
12909         .check_processor_compatibility = vmx_check_processor_compat,
12910         .hardware_enable = hardware_enable,
12911         .hardware_disable = hardware_disable,
12912         .cpu_has_accelerated_tpr = report_flexpriority,
12913         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
12914
12915         .vm_init = vmx_vm_init,
12916         .vm_alloc = vmx_vm_alloc,
12917         .vm_free = vmx_vm_free,
12918
12919         .vcpu_create = vmx_create_vcpu,
12920         .vcpu_free = vmx_free_vcpu,
12921         .vcpu_reset = vmx_vcpu_reset,
12922
12923         .prepare_guest_switch = vmx_save_host_state,
12924         .vcpu_load = vmx_vcpu_load,
12925         .vcpu_put = vmx_vcpu_put,
12926
12927         .update_bp_intercept = update_exception_bitmap,
12928         .get_msr_feature = vmx_get_msr_feature,
12929         .get_msr = vmx_get_msr,
12930         .set_msr = vmx_set_msr,
12931         .get_segment_base = vmx_get_segment_base,
12932         .get_segment = vmx_get_segment,
12933         .set_segment = vmx_set_segment,
12934         .get_cpl = vmx_get_cpl,
12935         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
12936         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
12937         .decache_cr3 = vmx_decache_cr3,
12938         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
12939         .set_cr0 = vmx_set_cr0,
12940         .set_cr3 = vmx_set_cr3,
12941         .set_cr4 = vmx_set_cr4,
12942         .set_efer = vmx_set_efer,
12943         .get_idt = vmx_get_idt,
12944         .set_idt = vmx_set_idt,
12945         .get_gdt = vmx_get_gdt,
12946         .set_gdt = vmx_set_gdt,
12947         .get_dr6 = vmx_get_dr6,
12948         .set_dr6 = vmx_set_dr6,
12949         .set_dr7 = vmx_set_dr7,
12950         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
12951         .cache_reg = vmx_cache_reg,
12952         .get_rflags = vmx_get_rflags,
12953         .set_rflags = vmx_set_rflags,
12954
12955         .tlb_flush = vmx_flush_tlb,
12956
12957         .run = vmx_vcpu_run,
12958         .handle_exit = vmx_handle_exit,
12959         .skip_emulated_instruction = skip_emulated_instruction,
12960         .set_interrupt_shadow = vmx_set_interrupt_shadow,
12961         .get_interrupt_shadow = vmx_get_interrupt_shadow,
12962         .patch_hypercall = vmx_patch_hypercall,
12963         .set_irq = vmx_inject_irq,
12964         .set_nmi = vmx_inject_nmi,
12965         .queue_exception = vmx_queue_exception,
12966         .cancel_injection = vmx_cancel_injection,
12967         .interrupt_allowed = vmx_interrupt_allowed,
12968         .nmi_allowed = vmx_nmi_allowed,
12969         .get_nmi_mask = vmx_get_nmi_mask,
12970         .set_nmi_mask = vmx_set_nmi_mask,
12971         .enable_nmi_window = enable_nmi_window,
12972         .enable_irq_window = enable_irq_window,
12973         .update_cr8_intercept = update_cr8_intercept,
12974         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
12975         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
12976         .get_enable_apicv = vmx_get_enable_apicv,
12977         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
12978         .load_eoi_exitmap = vmx_load_eoi_exitmap,
12979         .apicv_post_state_restore = vmx_apicv_post_state_restore,
12980         .hwapic_irr_update = vmx_hwapic_irr_update,
12981         .hwapic_isr_update = vmx_hwapic_isr_update,
12982         .sync_pir_to_irr = vmx_sync_pir_to_irr,
12983         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
12984
12985         .set_tss_addr = vmx_set_tss_addr,
12986         .set_identity_map_addr = vmx_set_identity_map_addr,
12987         .get_tdp_level = get_ept_level,
12988         .get_mt_mask = vmx_get_mt_mask,
12989
12990         .get_exit_info = vmx_get_exit_info,
12991
12992         .get_lpage_level = vmx_get_lpage_level,
12993
12994         .cpuid_update = vmx_cpuid_update,
12995
12996         .rdtscp_supported = vmx_rdtscp_supported,
12997         .invpcid_supported = vmx_invpcid_supported,
12998
12999         .set_supported_cpuid = vmx_set_supported_cpuid,
13000
13001         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
13002
13003         .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
13004         .write_tsc_offset = vmx_write_tsc_offset,
13005
13006         .set_tdp_cr3 = vmx_set_cr3,
13007
13008         .check_intercept = vmx_check_intercept,
13009         .handle_external_intr = vmx_handle_external_intr,
13010         .mpx_supported = vmx_mpx_supported,
13011         .xsaves_supported = vmx_xsaves_supported,
13012         .umip_emulated = vmx_umip_emulated,
13013
13014         .check_nested_events = vmx_check_nested_events,
13015
13016         .sched_in = vmx_sched_in,
13017
13018         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
13019         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
13020         .flush_log_dirty = vmx_flush_log_dirty,
13021         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
13022         .write_log_dirty = vmx_write_pml_buffer,
13023
13024         .pre_block = vmx_pre_block,
13025         .post_block = vmx_post_block,
13026
13027         .pmu_ops = &intel_pmu_ops,
13028
13029         .update_pi_irte = vmx_update_pi_irte,
13030
13031 #ifdef CONFIG_X86_64
13032         .set_hv_timer = vmx_set_hv_timer,
13033         .cancel_hv_timer = vmx_cancel_hv_timer,
13034 #endif
13035
13036         .setup_mce = vmx_setup_mce,
13037
13038         .smi_allowed = vmx_smi_allowed,
13039         .pre_enter_smm = vmx_pre_enter_smm,
13040         .pre_leave_smm = vmx_pre_leave_smm,
13041         .enable_smi_window = enable_smi_window,
13042 };
13043
13044 static int __init vmx_init(void)
13045 {
13046         int r;
13047
13048 #if IS_ENABLED(CONFIG_HYPERV)
13049         /*
13050          * Enlightened VMCS usage should be recommended and the host needs
13051          * to support eVMCS v1 or above. We can also disable eVMCS support
13052          * with module parameter.
13053          */
13054         if (enlightened_vmcs &&
13055             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
13056             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
13057             KVM_EVMCS_VERSION) {
13058                 int cpu;
13059
13060                 /* Check that we have assist pages on all online CPUs */
13061                 for_each_online_cpu(cpu) {
13062                         if (!hv_get_vp_assist_page(cpu)) {
13063                                 enlightened_vmcs = false;
13064                                 break;
13065                         }
13066                 }
13067
13068                 if (enlightened_vmcs) {
13069                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
13070                         static_branch_enable(&enable_evmcs);
13071                 }
13072         } else {
13073                 enlightened_vmcs = false;
13074         }
13075 #endif
13076
13077         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
13078                      __alignof__(struct vcpu_vmx), THIS_MODULE);
13079         if (r)
13080                 return r;
13081
13082 #ifdef CONFIG_KEXEC_CORE
13083         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
13084                            crash_vmclear_local_loaded_vmcss);
13085 #endif
13086         vmx_check_vmcs12_offsets();
13087
13088         return 0;
13089 }
13090
13091 static void __exit vmx_exit(void)
13092 {
13093 #ifdef CONFIG_KEXEC_CORE
13094         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
13095         synchronize_rcu();
13096 #endif
13097
13098         kvm_exit();
13099
13100 #if IS_ENABLED(CONFIG_HYPERV)
13101         if (static_branch_unlikely(&enable_evmcs)) {
13102                 int cpu;
13103                 struct hv_vp_assist_page *vp_ap;
13104                 /*
13105                  * Reset everything to support using non-enlightened VMCS
13106                  * access later (e.g. when we reload the module with
13107                  * enlightened_vmcs=0)
13108                  */
13109                 for_each_online_cpu(cpu) {
13110                         vp_ap = hv_get_vp_assist_page(cpu);
13111
13112                         if (!vp_ap)
13113                                 continue;
13114
13115                         vp_ap->current_nested_vmcs = 0;
13116                         vp_ap->enlighten_vmentry = 0;
13117                 }
13118
13119                 static_branch_disable(&enable_evmcs);
13120         }
13121 #endif
13122 }
13123
13124 module_init(vmx_init)
13125 module_exit(vmx_exit)