2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include <linux/nospec.h>
38 #include "kvm_cache_regs.h"
45 #include <asm/virtext.h>
47 #include <asm/fpu/internal.h>
48 #include <asm/perf_event.h>
49 #include <asm/debugreg.h>
50 #include <asm/kexec.h>
52 #include <asm/irq_remapping.h>
53 #include <asm/mmu_context.h>
54 #include <asm/spec-ctrl.h>
55 #include <asm/mshyperv.h>
59 #include "vmx_evmcs.h"
61 #define __ex(x) __kvm_handle_fault_on_reboot(x)
62 #define __ex_clear(x, reg) \
63 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
65 MODULE_AUTHOR("Qumranet");
66 MODULE_LICENSE("GPL");
68 static const struct x86_cpu_id vmx_cpu_id[] = {
69 X86_FEATURE_MATCH(X86_FEATURE_VMX),
72 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
74 static bool __read_mostly enable_vpid = 1;
75 module_param_named(vpid, enable_vpid, bool, 0444);
77 static bool __read_mostly enable_vnmi = 1;
78 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
80 static bool __read_mostly flexpriority_enabled = 1;
81 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
83 static bool __read_mostly enable_ept = 1;
84 module_param_named(ept, enable_ept, bool, S_IRUGO);
86 static bool __read_mostly enable_unrestricted_guest = 1;
87 module_param_named(unrestricted_guest,
88 enable_unrestricted_guest, bool, S_IRUGO);
90 static bool __read_mostly enable_ept_ad_bits = 1;
91 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
93 static bool __read_mostly emulate_invalid_guest_state = true;
94 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
96 static bool __read_mostly fasteoi = 1;
97 module_param(fasteoi, bool, S_IRUGO);
99 static bool __read_mostly enable_apicv = 1;
100 module_param(enable_apicv, bool, S_IRUGO);
102 static bool __read_mostly enable_shadow_vmcs = 1;
103 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
105 * If nested=1, nested virtualization is supported, i.e., guests may use
106 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
107 * use VMX instructions.
109 static bool __read_mostly nested = 0;
110 module_param(nested, bool, S_IRUGO);
112 static u64 __read_mostly host_xss;
114 static bool __read_mostly enable_pml = 1;
115 module_param_named(pml, enable_pml, bool, S_IRUGO);
119 #define MSR_TYPE_RW 3
121 #define MSR_BITMAP_MODE_X2APIC 1
122 #define MSR_BITMAP_MODE_X2APIC_APICV 2
123 #define MSR_BITMAP_MODE_LM 4
125 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
127 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
128 static int __read_mostly cpu_preemption_timer_multi;
129 static bool __read_mostly enable_preemption_timer = 1;
131 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
134 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
135 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
136 #define KVM_VM_CR0_ALWAYS_ON \
137 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
138 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
139 #define KVM_CR4_GUEST_OWNED_BITS \
140 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
141 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
143 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
144 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
145 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
147 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
149 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
152 * Hyper-V requires all of these, so mark them as supported even though
153 * they are just treated the same as all-context.
155 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
156 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
157 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
158 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
159 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
162 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
163 * ple_gap: upper bound on the amount of time between two successive
164 * executions of PAUSE in a loop. Also indicate if ple enabled.
165 * According to test, this time is usually smaller than 128 cycles.
166 * ple_window: upper bound on the amount of time a guest is allowed to execute
167 * in a PAUSE loop. Tests indicate that most spinlocks are held for
168 * less than 2^12 cycles
169 * Time is measured based on a counter that runs at the same rate as the TSC,
170 * refer SDM volume 3b section 21.6.13 & 22.1.3.
172 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
174 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
175 module_param(ple_window, uint, 0444);
177 /* Default doubles per-vcpu window every exit. */
178 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
179 module_param(ple_window_grow, uint, 0444);
181 /* Default resets per-vcpu window every exit to ple_window. */
182 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
183 module_param(ple_window_shrink, uint, 0444);
185 /* Default is to compute the maximum so we can never overflow. */
186 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
187 module_param(ple_window_max, uint, 0444);
189 extern const ulong vmx_return;
194 unsigned int tss_addr;
195 bool ept_identity_pagetable_done;
196 gpa_t ept_identity_map_addr;
199 #define NR_AUTOLOAD_MSRS 8
208 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
209 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
210 * loaded on this CPU (so we can clear them if the CPU goes down).
214 struct vmcs *shadow_vmcs;
217 bool nmi_known_unmasked;
218 unsigned long vmcs_host_cr3; /* May not match real cr3 */
219 unsigned long vmcs_host_cr4; /* May not match real cr4 */
220 /* Support for vnmi-less CPUs */
221 int soft_vnmi_blocked;
223 s64 vnmi_blocked_time;
224 unsigned long *msr_bitmap;
225 struct list_head loaded_vmcss_on_cpu_link;
228 struct shared_msr_entry {
235 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
236 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
237 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
238 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
239 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
240 * More than one of these structures may exist, if L1 runs multiple L2 guests.
241 * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
242 * underlying hardware which will be used to run L2.
243 * This structure is packed to ensure that its layout is identical across
244 * machines (necessary for live migration).
246 * IMPORTANT: Changing the layout of existing fields in this structure
247 * will break save/restore compatibility with older kvm releases. When
248 * adding new fields, either use space in the reserved padding* arrays
249 * or add the new fields to the end of the structure.
251 typedef u64 natural_width;
252 struct __packed vmcs12 {
253 /* According to the Intel spec, a VMCS region must start with the
254 * following two fields. Then follow implementation-specific data.
259 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
260 u32 padding[7]; /* room for future expansion */
265 u64 vm_exit_msr_store_addr;
266 u64 vm_exit_msr_load_addr;
267 u64 vm_entry_msr_load_addr;
269 u64 virtual_apic_page_addr;
270 u64 apic_access_addr;
271 u64 posted_intr_desc_addr;
273 u64 eoi_exit_bitmap0;
274 u64 eoi_exit_bitmap1;
275 u64 eoi_exit_bitmap2;
276 u64 eoi_exit_bitmap3;
278 u64 guest_physical_address;
279 u64 vmcs_link_pointer;
280 u64 guest_ia32_debugctl;
283 u64 guest_ia32_perf_global_ctrl;
291 u64 host_ia32_perf_global_ctrl;
294 u64 vm_function_control;
295 u64 eptp_list_address;
297 u64 padding64[3]; /* room for future expansion */
299 * To allow migration of L1 (complete with its L2 guests) between
300 * machines of different natural widths (32 or 64 bit), we cannot have
301 * unsigned long fields with no explict size. We use u64 (aliased
302 * natural_width) instead. Luckily, x86 is little-endian.
304 natural_width cr0_guest_host_mask;
305 natural_width cr4_guest_host_mask;
306 natural_width cr0_read_shadow;
307 natural_width cr4_read_shadow;
308 natural_width cr3_target_value0;
309 natural_width cr3_target_value1;
310 natural_width cr3_target_value2;
311 natural_width cr3_target_value3;
312 natural_width exit_qualification;
313 natural_width guest_linear_address;
314 natural_width guest_cr0;
315 natural_width guest_cr3;
316 natural_width guest_cr4;
317 natural_width guest_es_base;
318 natural_width guest_cs_base;
319 natural_width guest_ss_base;
320 natural_width guest_ds_base;
321 natural_width guest_fs_base;
322 natural_width guest_gs_base;
323 natural_width guest_ldtr_base;
324 natural_width guest_tr_base;
325 natural_width guest_gdtr_base;
326 natural_width guest_idtr_base;
327 natural_width guest_dr7;
328 natural_width guest_rsp;
329 natural_width guest_rip;
330 natural_width guest_rflags;
331 natural_width guest_pending_dbg_exceptions;
332 natural_width guest_sysenter_esp;
333 natural_width guest_sysenter_eip;
334 natural_width host_cr0;
335 natural_width host_cr3;
336 natural_width host_cr4;
337 natural_width host_fs_base;
338 natural_width host_gs_base;
339 natural_width host_tr_base;
340 natural_width host_gdtr_base;
341 natural_width host_idtr_base;
342 natural_width host_ia32_sysenter_esp;
343 natural_width host_ia32_sysenter_eip;
344 natural_width host_rsp;
345 natural_width host_rip;
346 natural_width paddingl[8]; /* room for future expansion */
347 u32 pin_based_vm_exec_control;
348 u32 cpu_based_vm_exec_control;
349 u32 exception_bitmap;
350 u32 page_fault_error_code_mask;
351 u32 page_fault_error_code_match;
352 u32 cr3_target_count;
353 u32 vm_exit_controls;
354 u32 vm_exit_msr_store_count;
355 u32 vm_exit_msr_load_count;
356 u32 vm_entry_controls;
357 u32 vm_entry_msr_load_count;
358 u32 vm_entry_intr_info_field;
359 u32 vm_entry_exception_error_code;
360 u32 vm_entry_instruction_len;
362 u32 secondary_vm_exec_control;
363 u32 vm_instruction_error;
365 u32 vm_exit_intr_info;
366 u32 vm_exit_intr_error_code;
367 u32 idt_vectoring_info_field;
368 u32 idt_vectoring_error_code;
369 u32 vm_exit_instruction_len;
370 u32 vmx_instruction_info;
377 u32 guest_ldtr_limit;
379 u32 guest_gdtr_limit;
380 u32 guest_idtr_limit;
381 u32 guest_es_ar_bytes;
382 u32 guest_cs_ar_bytes;
383 u32 guest_ss_ar_bytes;
384 u32 guest_ds_ar_bytes;
385 u32 guest_fs_ar_bytes;
386 u32 guest_gs_ar_bytes;
387 u32 guest_ldtr_ar_bytes;
388 u32 guest_tr_ar_bytes;
389 u32 guest_interruptibility_info;
390 u32 guest_activity_state;
391 u32 guest_sysenter_cs;
392 u32 host_ia32_sysenter_cs;
393 u32 vmx_preemption_timer_value;
394 u32 padding32[7]; /* room for future expansion */
395 u16 virtual_processor_id;
397 u16 guest_es_selector;
398 u16 guest_cs_selector;
399 u16 guest_ss_selector;
400 u16 guest_ds_selector;
401 u16 guest_fs_selector;
402 u16 guest_gs_selector;
403 u16 guest_ldtr_selector;
404 u16 guest_tr_selector;
405 u16 guest_intr_status;
406 u16 host_es_selector;
407 u16 host_cs_selector;
408 u16 host_ss_selector;
409 u16 host_ds_selector;
410 u16 host_fs_selector;
411 u16 host_gs_selector;
412 u16 host_tr_selector;
417 * For save/restore compatibility, the vmcs12 field offsets must not change.
419 #define CHECK_OFFSET(field, loc) \
420 BUILD_BUG_ON_MSG(offsetof(struct vmcs12, field) != (loc), \
421 "Offset of " #field " in struct vmcs12 has changed.")
423 static inline void vmx_check_vmcs12_offsets(void) {
424 CHECK_OFFSET(revision_id, 0);
425 CHECK_OFFSET(abort, 4);
426 CHECK_OFFSET(launch_state, 8);
427 CHECK_OFFSET(io_bitmap_a, 40);
428 CHECK_OFFSET(io_bitmap_b, 48);
429 CHECK_OFFSET(msr_bitmap, 56);
430 CHECK_OFFSET(vm_exit_msr_store_addr, 64);
431 CHECK_OFFSET(vm_exit_msr_load_addr, 72);
432 CHECK_OFFSET(vm_entry_msr_load_addr, 80);
433 CHECK_OFFSET(tsc_offset, 88);
434 CHECK_OFFSET(virtual_apic_page_addr, 96);
435 CHECK_OFFSET(apic_access_addr, 104);
436 CHECK_OFFSET(posted_intr_desc_addr, 112);
437 CHECK_OFFSET(ept_pointer, 120);
438 CHECK_OFFSET(eoi_exit_bitmap0, 128);
439 CHECK_OFFSET(eoi_exit_bitmap1, 136);
440 CHECK_OFFSET(eoi_exit_bitmap2, 144);
441 CHECK_OFFSET(eoi_exit_bitmap3, 152);
442 CHECK_OFFSET(xss_exit_bitmap, 160);
443 CHECK_OFFSET(guest_physical_address, 168);
444 CHECK_OFFSET(vmcs_link_pointer, 176);
445 CHECK_OFFSET(guest_ia32_debugctl, 184);
446 CHECK_OFFSET(guest_ia32_pat, 192);
447 CHECK_OFFSET(guest_ia32_efer, 200);
448 CHECK_OFFSET(guest_ia32_perf_global_ctrl, 208);
449 CHECK_OFFSET(guest_pdptr0, 216);
450 CHECK_OFFSET(guest_pdptr1, 224);
451 CHECK_OFFSET(guest_pdptr2, 232);
452 CHECK_OFFSET(guest_pdptr3, 240);
453 CHECK_OFFSET(guest_bndcfgs, 248);
454 CHECK_OFFSET(host_ia32_pat, 256);
455 CHECK_OFFSET(host_ia32_efer, 264);
456 CHECK_OFFSET(host_ia32_perf_global_ctrl, 272);
457 CHECK_OFFSET(vmread_bitmap, 280);
458 CHECK_OFFSET(vmwrite_bitmap, 288);
459 CHECK_OFFSET(vm_function_control, 296);
460 CHECK_OFFSET(eptp_list_address, 304);
461 CHECK_OFFSET(pml_address, 312);
462 CHECK_OFFSET(cr0_guest_host_mask, 344);
463 CHECK_OFFSET(cr4_guest_host_mask, 352);
464 CHECK_OFFSET(cr0_read_shadow, 360);
465 CHECK_OFFSET(cr4_read_shadow, 368);
466 CHECK_OFFSET(cr3_target_value0, 376);
467 CHECK_OFFSET(cr3_target_value1, 384);
468 CHECK_OFFSET(cr3_target_value2, 392);
469 CHECK_OFFSET(cr3_target_value3, 400);
470 CHECK_OFFSET(exit_qualification, 408);
471 CHECK_OFFSET(guest_linear_address, 416);
472 CHECK_OFFSET(guest_cr0, 424);
473 CHECK_OFFSET(guest_cr3, 432);
474 CHECK_OFFSET(guest_cr4, 440);
475 CHECK_OFFSET(guest_es_base, 448);
476 CHECK_OFFSET(guest_cs_base, 456);
477 CHECK_OFFSET(guest_ss_base, 464);
478 CHECK_OFFSET(guest_ds_base, 472);
479 CHECK_OFFSET(guest_fs_base, 480);
480 CHECK_OFFSET(guest_gs_base, 488);
481 CHECK_OFFSET(guest_ldtr_base, 496);
482 CHECK_OFFSET(guest_tr_base, 504);
483 CHECK_OFFSET(guest_gdtr_base, 512);
484 CHECK_OFFSET(guest_idtr_base, 520);
485 CHECK_OFFSET(guest_dr7, 528);
486 CHECK_OFFSET(guest_rsp, 536);
487 CHECK_OFFSET(guest_rip, 544);
488 CHECK_OFFSET(guest_rflags, 552);
489 CHECK_OFFSET(guest_pending_dbg_exceptions, 560);
490 CHECK_OFFSET(guest_sysenter_esp, 568);
491 CHECK_OFFSET(guest_sysenter_eip, 576);
492 CHECK_OFFSET(host_cr0, 584);
493 CHECK_OFFSET(host_cr3, 592);
494 CHECK_OFFSET(host_cr4, 600);
495 CHECK_OFFSET(host_fs_base, 608);
496 CHECK_OFFSET(host_gs_base, 616);
497 CHECK_OFFSET(host_tr_base, 624);
498 CHECK_OFFSET(host_gdtr_base, 632);
499 CHECK_OFFSET(host_idtr_base, 640);
500 CHECK_OFFSET(host_ia32_sysenter_esp, 648);
501 CHECK_OFFSET(host_ia32_sysenter_eip, 656);
502 CHECK_OFFSET(host_rsp, 664);
503 CHECK_OFFSET(host_rip, 672);
504 CHECK_OFFSET(pin_based_vm_exec_control, 744);
505 CHECK_OFFSET(cpu_based_vm_exec_control, 748);
506 CHECK_OFFSET(exception_bitmap, 752);
507 CHECK_OFFSET(page_fault_error_code_mask, 756);
508 CHECK_OFFSET(page_fault_error_code_match, 760);
509 CHECK_OFFSET(cr3_target_count, 764);
510 CHECK_OFFSET(vm_exit_controls, 768);
511 CHECK_OFFSET(vm_exit_msr_store_count, 772);
512 CHECK_OFFSET(vm_exit_msr_load_count, 776);
513 CHECK_OFFSET(vm_entry_controls, 780);
514 CHECK_OFFSET(vm_entry_msr_load_count, 784);
515 CHECK_OFFSET(vm_entry_intr_info_field, 788);
516 CHECK_OFFSET(vm_entry_exception_error_code, 792);
517 CHECK_OFFSET(vm_entry_instruction_len, 796);
518 CHECK_OFFSET(tpr_threshold, 800);
519 CHECK_OFFSET(secondary_vm_exec_control, 804);
520 CHECK_OFFSET(vm_instruction_error, 808);
521 CHECK_OFFSET(vm_exit_reason, 812);
522 CHECK_OFFSET(vm_exit_intr_info, 816);
523 CHECK_OFFSET(vm_exit_intr_error_code, 820);
524 CHECK_OFFSET(idt_vectoring_info_field, 824);
525 CHECK_OFFSET(idt_vectoring_error_code, 828);
526 CHECK_OFFSET(vm_exit_instruction_len, 832);
527 CHECK_OFFSET(vmx_instruction_info, 836);
528 CHECK_OFFSET(guest_es_limit, 840);
529 CHECK_OFFSET(guest_cs_limit, 844);
530 CHECK_OFFSET(guest_ss_limit, 848);
531 CHECK_OFFSET(guest_ds_limit, 852);
532 CHECK_OFFSET(guest_fs_limit, 856);
533 CHECK_OFFSET(guest_gs_limit, 860);
534 CHECK_OFFSET(guest_ldtr_limit, 864);
535 CHECK_OFFSET(guest_tr_limit, 868);
536 CHECK_OFFSET(guest_gdtr_limit, 872);
537 CHECK_OFFSET(guest_idtr_limit, 876);
538 CHECK_OFFSET(guest_es_ar_bytes, 880);
539 CHECK_OFFSET(guest_cs_ar_bytes, 884);
540 CHECK_OFFSET(guest_ss_ar_bytes, 888);
541 CHECK_OFFSET(guest_ds_ar_bytes, 892);
542 CHECK_OFFSET(guest_fs_ar_bytes, 896);
543 CHECK_OFFSET(guest_gs_ar_bytes, 900);
544 CHECK_OFFSET(guest_ldtr_ar_bytes, 904);
545 CHECK_OFFSET(guest_tr_ar_bytes, 908);
546 CHECK_OFFSET(guest_interruptibility_info, 912);
547 CHECK_OFFSET(guest_activity_state, 916);
548 CHECK_OFFSET(guest_sysenter_cs, 920);
549 CHECK_OFFSET(host_ia32_sysenter_cs, 924);
550 CHECK_OFFSET(vmx_preemption_timer_value, 928);
551 CHECK_OFFSET(virtual_processor_id, 960);
552 CHECK_OFFSET(posted_intr_nv, 962);
553 CHECK_OFFSET(guest_es_selector, 964);
554 CHECK_OFFSET(guest_cs_selector, 966);
555 CHECK_OFFSET(guest_ss_selector, 968);
556 CHECK_OFFSET(guest_ds_selector, 970);
557 CHECK_OFFSET(guest_fs_selector, 972);
558 CHECK_OFFSET(guest_gs_selector, 974);
559 CHECK_OFFSET(guest_ldtr_selector, 976);
560 CHECK_OFFSET(guest_tr_selector, 978);
561 CHECK_OFFSET(guest_intr_status, 980);
562 CHECK_OFFSET(host_es_selector, 982);
563 CHECK_OFFSET(host_cs_selector, 984);
564 CHECK_OFFSET(host_ss_selector, 986);
565 CHECK_OFFSET(host_ds_selector, 988);
566 CHECK_OFFSET(host_fs_selector, 990);
567 CHECK_OFFSET(host_gs_selector, 992);
568 CHECK_OFFSET(host_tr_selector, 994);
569 CHECK_OFFSET(guest_pml_index, 996);
573 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
574 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
575 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
577 * IMPORTANT: Changing this value will break save/restore compatibility with
578 * older kvm releases.
580 #define VMCS12_REVISION 0x11e57ed0
583 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
584 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
585 * current implementation, 4K are reserved to avoid future complications.
587 #define VMCS12_SIZE 0x1000
590 * VMCS12_MAX_FIELD_INDEX is the highest index value used in any
591 * supported VMCS12 field encoding.
593 #define VMCS12_MAX_FIELD_INDEX 0x17
595 struct nested_vmx_msrs {
597 * We only store the "true" versions of the VMX capability MSRs. We
598 * generate the "non-true" versions by setting the must-be-1 bits
599 * according to the SDM.
601 u32 procbased_ctls_low;
602 u32 procbased_ctls_high;
603 u32 secondary_ctls_low;
604 u32 secondary_ctls_high;
605 u32 pinbased_ctls_low;
606 u32 pinbased_ctls_high;
625 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
626 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
629 /* Has the level1 guest done vmxon? */
634 /* The guest-physical address of the current VMCS L1 keeps for L2 */
637 * Cache of the guest's VMCS, existing outside of guest memory.
638 * Loaded from guest memory during VMPTRLD. Flushed to guest
639 * memory during VMCLEAR and VMPTRLD.
641 struct vmcs12 *cached_vmcs12;
643 * Indicates if the shadow vmcs must be updated with the
644 * data hold by vmcs12
646 bool sync_shadow_vmcs;
649 bool change_vmcs01_virtual_apic_mode;
651 /* L2 must run next, and mustn't decide to exit to L1. */
652 bool nested_run_pending;
654 struct loaded_vmcs vmcs02;
657 * Guest pages referred to in the vmcs02 with host-physical
658 * pointers, so we must keep them pinned while L2 runs.
660 struct page *apic_access_page;
661 struct page *virtual_apic_page;
662 struct page *pi_desc_page;
663 struct pi_desc *pi_desc;
667 struct hrtimer preemption_timer;
668 bool preemption_timer_expired;
670 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
676 struct nested_vmx_msrs msrs;
678 /* SMM related state */
680 /* in VMX operation on SMM entry? */
682 /* in guest mode on SMM entry? */
687 #define POSTED_INTR_ON 0
688 #define POSTED_INTR_SN 1
690 /* Posted-Interrupt Descriptor */
692 u32 pir[8]; /* Posted interrupt requested */
695 /* bit 256 - Outstanding Notification */
697 /* bit 257 - Suppress Notification */
699 /* bit 271:258 - Reserved */
701 /* bit 279:272 - Notification Vector */
703 /* bit 287:280 - Reserved */
705 /* bit 319:288 - Notification Destination */
713 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
715 return test_and_set_bit(POSTED_INTR_ON,
716 (unsigned long *)&pi_desc->control);
719 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
721 return test_and_clear_bit(POSTED_INTR_ON,
722 (unsigned long *)&pi_desc->control);
725 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
727 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
730 static inline void pi_clear_sn(struct pi_desc *pi_desc)
732 return clear_bit(POSTED_INTR_SN,
733 (unsigned long *)&pi_desc->control);
736 static inline void pi_set_sn(struct pi_desc *pi_desc)
738 return set_bit(POSTED_INTR_SN,
739 (unsigned long *)&pi_desc->control);
742 static inline void pi_clear_on(struct pi_desc *pi_desc)
744 clear_bit(POSTED_INTR_ON,
745 (unsigned long *)&pi_desc->control);
748 static inline int pi_test_on(struct pi_desc *pi_desc)
750 return test_bit(POSTED_INTR_ON,
751 (unsigned long *)&pi_desc->control);
754 static inline int pi_test_sn(struct pi_desc *pi_desc)
756 return test_bit(POSTED_INTR_SN,
757 (unsigned long *)&pi_desc->control);
761 struct kvm_vcpu vcpu;
762 unsigned long host_rsp;
766 u32 idt_vectoring_info;
768 struct shared_msr_entry *guest_msrs;
771 unsigned long host_idt_base;
773 u64 msr_host_kernel_gs_base;
774 u64 msr_guest_kernel_gs_base;
777 u64 arch_capabilities;
780 u32 vm_entry_controls_shadow;
781 u32 vm_exit_controls_shadow;
782 u32 secondary_exec_control;
785 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
786 * non-nested (L1) guest, it always points to vmcs01. For a nested
787 * guest (L2), it points to a different VMCS.
789 struct loaded_vmcs vmcs01;
790 struct loaded_vmcs *loaded_vmcs;
791 bool __launched; /* temporary, used in vmx_vcpu_run */
792 struct msr_autoload {
794 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
795 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
799 u16 fs_sel, gs_sel, ldt_sel;
803 int gs_ldt_reload_needed;
804 int fs_reload_needed;
805 u64 msr_host_bndcfgs;
810 struct kvm_segment segs[8];
813 u32 bitmask; /* 4 bits per segment (1 bit per field) */
814 struct kvm_save_segment {
822 bool emulation_required;
826 /* Posted interrupt descriptor */
827 struct pi_desc pi_desc;
829 /* Support for a guest hypervisor (nested VMX) */
830 struct nested_vmx nested;
832 /* Dynamic PLE window. */
834 bool ple_window_dirty;
836 /* Support for PML */
837 #define PML_ENTITY_NUM 512
840 /* apic deadline value in host tsc */
843 u64 current_tsc_ratio;
847 unsigned long host_debugctlmsr;
850 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
851 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
852 * in msr_ia32_feature_control_valid_bits.
854 u64 msr_ia32_feature_control;
855 u64 msr_ia32_feature_control_valid_bits;
858 enum segment_cache_field {
867 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
869 return container_of(kvm, struct kvm_vmx, kvm);
872 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
874 return container_of(vcpu, struct vcpu_vmx, vcpu);
877 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
879 return &(to_vmx(vcpu)->pi_desc);
882 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
883 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
884 #define FIELD(number, name) [ROL16(number, 6)] = VMCS12_OFFSET(name)
885 #define FIELD64(number, name) \
886 FIELD(number, name), \
887 [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
890 static u16 shadow_read_only_fields[] = {
891 #define SHADOW_FIELD_RO(x) x,
892 #include "vmx_shadow_fields.h"
894 static int max_shadow_read_only_fields =
895 ARRAY_SIZE(shadow_read_only_fields);
897 static u16 shadow_read_write_fields[] = {
898 #define SHADOW_FIELD_RW(x) x,
899 #include "vmx_shadow_fields.h"
901 static int max_shadow_read_write_fields =
902 ARRAY_SIZE(shadow_read_write_fields);
904 static const unsigned short vmcs_field_to_offset_table[] = {
905 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
906 FIELD(POSTED_INTR_NV, posted_intr_nv),
907 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
908 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
909 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
910 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
911 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
912 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
913 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
914 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
915 FIELD(GUEST_INTR_STATUS, guest_intr_status),
916 FIELD(GUEST_PML_INDEX, guest_pml_index),
917 FIELD(HOST_ES_SELECTOR, host_es_selector),
918 FIELD(HOST_CS_SELECTOR, host_cs_selector),
919 FIELD(HOST_SS_SELECTOR, host_ss_selector),
920 FIELD(HOST_DS_SELECTOR, host_ds_selector),
921 FIELD(HOST_FS_SELECTOR, host_fs_selector),
922 FIELD(HOST_GS_SELECTOR, host_gs_selector),
923 FIELD(HOST_TR_SELECTOR, host_tr_selector),
924 FIELD64(IO_BITMAP_A, io_bitmap_a),
925 FIELD64(IO_BITMAP_B, io_bitmap_b),
926 FIELD64(MSR_BITMAP, msr_bitmap),
927 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
928 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
929 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
930 FIELD64(PML_ADDRESS, pml_address),
931 FIELD64(TSC_OFFSET, tsc_offset),
932 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
933 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
934 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
935 FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
936 FIELD64(EPT_POINTER, ept_pointer),
937 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
938 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
939 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
940 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
941 FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
942 FIELD64(VMREAD_BITMAP, vmread_bitmap),
943 FIELD64(VMWRITE_BITMAP, vmwrite_bitmap),
944 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
945 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
946 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
947 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
948 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
949 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
950 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
951 FIELD64(GUEST_PDPTR0, guest_pdptr0),
952 FIELD64(GUEST_PDPTR1, guest_pdptr1),
953 FIELD64(GUEST_PDPTR2, guest_pdptr2),
954 FIELD64(GUEST_PDPTR3, guest_pdptr3),
955 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
956 FIELD64(HOST_IA32_PAT, host_ia32_pat),
957 FIELD64(HOST_IA32_EFER, host_ia32_efer),
958 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
959 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
960 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
961 FIELD(EXCEPTION_BITMAP, exception_bitmap),
962 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
963 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
964 FIELD(CR3_TARGET_COUNT, cr3_target_count),
965 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
966 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
967 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
968 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
969 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
970 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
971 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
972 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
973 FIELD(TPR_THRESHOLD, tpr_threshold),
974 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
975 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
976 FIELD(VM_EXIT_REASON, vm_exit_reason),
977 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
978 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
979 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
980 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
981 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
982 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
983 FIELD(GUEST_ES_LIMIT, guest_es_limit),
984 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
985 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
986 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
987 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
988 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
989 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
990 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
991 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
992 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
993 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
994 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
995 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
996 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
997 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
998 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
999 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
1000 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
1001 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
1002 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
1003 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
1004 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
1005 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
1006 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
1007 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
1008 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
1009 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
1010 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
1011 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
1012 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
1013 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
1014 FIELD(EXIT_QUALIFICATION, exit_qualification),
1015 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
1016 FIELD(GUEST_CR0, guest_cr0),
1017 FIELD(GUEST_CR3, guest_cr3),
1018 FIELD(GUEST_CR4, guest_cr4),
1019 FIELD(GUEST_ES_BASE, guest_es_base),
1020 FIELD(GUEST_CS_BASE, guest_cs_base),
1021 FIELD(GUEST_SS_BASE, guest_ss_base),
1022 FIELD(GUEST_DS_BASE, guest_ds_base),
1023 FIELD(GUEST_FS_BASE, guest_fs_base),
1024 FIELD(GUEST_GS_BASE, guest_gs_base),
1025 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
1026 FIELD(GUEST_TR_BASE, guest_tr_base),
1027 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
1028 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
1029 FIELD(GUEST_DR7, guest_dr7),
1030 FIELD(GUEST_RSP, guest_rsp),
1031 FIELD(GUEST_RIP, guest_rip),
1032 FIELD(GUEST_RFLAGS, guest_rflags),
1033 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
1034 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
1035 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
1036 FIELD(HOST_CR0, host_cr0),
1037 FIELD(HOST_CR3, host_cr3),
1038 FIELD(HOST_CR4, host_cr4),
1039 FIELD(HOST_FS_BASE, host_fs_base),
1040 FIELD(HOST_GS_BASE, host_gs_base),
1041 FIELD(HOST_TR_BASE, host_tr_base),
1042 FIELD(HOST_GDTR_BASE, host_gdtr_base),
1043 FIELD(HOST_IDTR_BASE, host_idtr_base),
1044 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
1045 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
1046 FIELD(HOST_RSP, host_rsp),
1047 FIELD(HOST_RIP, host_rip),
1050 static inline short vmcs_field_to_offset(unsigned long field)
1052 const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
1053 unsigned short offset;
1059 index = ROL16(field, 6);
1063 index = array_index_nospec(index, size);
1064 offset = vmcs_field_to_offset_table[index];
1070 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
1072 return to_vmx(vcpu)->nested.cached_vmcs12;
1075 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
1076 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
1077 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
1078 static bool vmx_xsaves_supported(void);
1079 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1080 struct kvm_segment *var, int seg);
1081 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1082 struct kvm_segment *var, int seg);
1083 static bool guest_state_valid(struct kvm_vcpu *vcpu);
1084 static u32 vmx_segment_access_rights(struct kvm_segment *var);
1085 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
1086 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
1087 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
1088 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
1090 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
1091 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
1094 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
1095 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
1097 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
1098 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
1100 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
1103 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
1104 * can find which vCPU should be waken up.
1106 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
1107 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
1115 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
1117 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
1118 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
1120 static bool cpu_has_load_ia32_efer;
1121 static bool cpu_has_load_perf_global_ctrl;
1123 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
1124 static DEFINE_SPINLOCK(vmx_vpid_lock);
1126 static struct vmcs_config {
1131 u32 pin_based_exec_ctrl;
1132 u32 cpu_based_exec_ctrl;
1133 u32 cpu_based_2nd_exec_ctrl;
1136 struct nested_vmx_msrs nested;
1139 static struct vmx_capability {
1144 #define VMX_SEGMENT_FIELD(seg) \
1145 [VCPU_SREG_##seg] = { \
1146 .selector = GUEST_##seg##_SELECTOR, \
1147 .base = GUEST_##seg##_BASE, \
1148 .limit = GUEST_##seg##_LIMIT, \
1149 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1152 static const struct kvm_vmx_segment_field {
1157 } kvm_vmx_segment_fields[] = {
1158 VMX_SEGMENT_FIELD(CS),
1159 VMX_SEGMENT_FIELD(DS),
1160 VMX_SEGMENT_FIELD(ES),
1161 VMX_SEGMENT_FIELD(FS),
1162 VMX_SEGMENT_FIELD(GS),
1163 VMX_SEGMENT_FIELD(SS),
1164 VMX_SEGMENT_FIELD(TR),
1165 VMX_SEGMENT_FIELD(LDTR),
1168 static u64 host_efer;
1170 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1173 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1174 * away by decrementing the array size.
1176 static const u32 vmx_msr_index[] = {
1177 #ifdef CONFIG_X86_64
1178 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1180 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1183 DEFINE_STATIC_KEY_FALSE(enable_evmcs);
1185 #define current_evmcs ((struct hv_enlightened_vmcs *)this_cpu_read(current_vmcs))
1187 #define KVM_EVMCS_VERSION 1
1189 #if IS_ENABLED(CONFIG_HYPERV)
1190 static bool __read_mostly enlightened_vmcs = true;
1191 module_param(enlightened_vmcs, bool, 0444);
1193 static inline void evmcs_write64(unsigned long field, u64 value)
1196 int offset = get_evmcs_offset(field, &clean_field);
1201 *(u64 *)((char *)current_evmcs + offset) = value;
1203 current_evmcs->hv_clean_fields &= ~clean_field;
1206 static inline void evmcs_write32(unsigned long field, u32 value)
1209 int offset = get_evmcs_offset(field, &clean_field);
1214 *(u32 *)((char *)current_evmcs + offset) = value;
1215 current_evmcs->hv_clean_fields &= ~clean_field;
1218 static inline void evmcs_write16(unsigned long field, u16 value)
1221 int offset = get_evmcs_offset(field, &clean_field);
1226 *(u16 *)((char *)current_evmcs + offset) = value;
1227 current_evmcs->hv_clean_fields &= ~clean_field;
1230 static inline u64 evmcs_read64(unsigned long field)
1232 int offset = get_evmcs_offset(field, NULL);
1237 return *(u64 *)((char *)current_evmcs + offset);
1240 static inline u32 evmcs_read32(unsigned long field)
1242 int offset = get_evmcs_offset(field, NULL);
1247 return *(u32 *)((char *)current_evmcs + offset);
1250 static inline u16 evmcs_read16(unsigned long field)
1252 int offset = get_evmcs_offset(field, NULL);
1257 return *(u16 *)((char *)current_evmcs + offset);
1260 static inline void evmcs_touch_msr_bitmap(void)
1262 if (unlikely(!current_evmcs))
1265 if (current_evmcs->hv_enlightenments_control.msr_bitmap)
1266 current_evmcs->hv_clean_fields &=
1267 ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP;
1270 static void evmcs_load(u64 phys_addr)
1272 struct hv_vp_assist_page *vp_ap =
1273 hv_get_vp_assist_page(smp_processor_id());
1275 vp_ap->current_nested_vmcs = phys_addr;
1276 vp_ap->enlighten_vmentry = 1;
1279 static void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf)
1282 * Enlightened VMCSv1 doesn't support these:
1284 * POSTED_INTR_NV = 0x00000002,
1285 * GUEST_INTR_STATUS = 0x00000810,
1286 * APIC_ACCESS_ADDR = 0x00002014,
1287 * POSTED_INTR_DESC_ADDR = 0x00002016,
1288 * EOI_EXIT_BITMAP0 = 0x0000201c,
1289 * EOI_EXIT_BITMAP1 = 0x0000201e,
1290 * EOI_EXIT_BITMAP2 = 0x00002020,
1291 * EOI_EXIT_BITMAP3 = 0x00002022,
1293 vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
1294 vmcs_conf->cpu_based_2nd_exec_ctrl &=
1295 ~SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1296 vmcs_conf->cpu_based_2nd_exec_ctrl &=
1297 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1298 vmcs_conf->cpu_based_2nd_exec_ctrl &=
1299 ~SECONDARY_EXEC_APIC_REGISTER_VIRT;
1302 * GUEST_PML_INDEX = 0x00000812,
1303 * PML_ADDRESS = 0x0000200e,
1305 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_PML;
1307 /* VM_FUNCTION_CONTROL = 0x00002018, */
1308 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_VMFUNC;
1311 * EPTP_LIST_ADDRESS = 0x00002024,
1312 * VMREAD_BITMAP = 0x00002026,
1313 * VMWRITE_BITMAP = 0x00002028,
1315 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_SHADOW_VMCS;
1318 * TSC_MULTIPLIER = 0x00002032,
1320 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_TSC_SCALING;
1323 * PLE_GAP = 0x00004020,
1324 * PLE_WINDOW = 0x00004022,
1326 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1329 * VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
1331 vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
1334 * GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
1335 * HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
1337 vmcs_conf->vmexit_ctrl &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
1338 vmcs_conf->vmentry_ctrl &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
1341 * Currently unsupported in KVM:
1342 * GUEST_IA32_RTIT_CTL = 0x00002814,
1345 #else /* !IS_ENABLED(CONFIG_HYPERV) */
1346 static inline void evmcs_write64(unsigned long field, u64 value) {}
1347 static inline void evmcs_write32(unsigned long field, u32 value) {}
1348 static inline void evmcs_write16(unsigned long field, u16 value) {}
1349 static inline u64 evmcs_read64(unsigned long field) { return 0; }
1350 static inline u32 evmcs_read32(unsigned long field) { return 0; }
1351 static inline u16 evmcs_read16(unsigned long field) { return 0; }
1352 static inline void evmcs_load(u64 phys_addr) {}
1353 static inline void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf) {}
1354 static inline void evmcs_touch_msr_bitmap(void) {}
1355 #endif /* IS_ENABLED(CONFIG_HYPERV) */
1357 static inline bool is_exception_n(u32 intr_info, u8 vector)
1359 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1360 INTR_INFO_VALID_MASK)) ==
1361 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1364 static inline bool is_debug(u32 intr_info)
1366 return is_exception_n(intr_info, DB_VECTOR);
1369 static inline bool is_breakpoint(u32 intr_info)
1371 return is_exception_n(intr_info, BP_VECTOR);
1374 static inline bool is_page_fault(u32 intr_info)
1376 return is_exception_n(intr_info, PF_VECTOR);
1379 static inline bool is_no_device(u32 intr_info)
1381 return is_exception_n(intr_info, NM_VECTOR);
1384 static inline bool is_invalid_opcode(u32 intr_info)
1386 return is_exception_n(intr_info, UD_VECTOR);
1389 static inline bool is_gp_fault(u32 intr_info)
1391 return is_exception_n(intr_info, GP_VECTOR);
1394 static inline bool is_external_interrupt(u32 intr_info)
1396 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1397 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1400 static inline bool is_machine_check(u32 intr_info)
1402 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1403 INTR_INFO_VALID_MASK)) ==
1404 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1407 /* Undocumented: icebp/int1 */
1408 static inline bool is_icebp(u32 intr_info)
1410 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1411 == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
1414 static inline bool cpu_has_vmx_msr_bitmap(void)
1416 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1419 static inline bool cpu_has_vmx_tpr_shadow(void)
1421 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1424 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1426 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1429 static inline bool cpu_has_secondary_exec_ctrls(void)
1431 return vmcs_config.cpu_based_exec_ctrl &
1432 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1435 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1437 return vmcs_config.cpu_based_2nd_exec_ctrl &
1438 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1441 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1443 return vmcs_config.cpu_based_2nd_exec_ctrl &
1444 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1447 static inline bool cpu_has_vmx_apic_register_virt(void)
1449 return vmcs_config.cpu_based_2nd_exec_ctrl &
1450 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1453 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1455 return vmcs_config.cpu_based_2nd_exec_ctrl &
1456 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1460 * Comment's format: document - errata name - stepping - processor name.
1462 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1464 static u32 vmx_preemption_cpu_tfms[] = {
1465 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1467 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1468 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1469 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1471 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1473 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1474 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1476 * 320767.pdf - AAP86 - B1 -
1477 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1480 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1482 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1484 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1486 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1487 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1488 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1492 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1494 u32 eax = cpuid_eax(0x00000001), i;
1496 /* Clear the reserved bits */
1497 eax &= ~(0x3U << 14 | 0xfU << 28);
1498 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1499 if (eax == vmx_preemption_cpu_tfms[i])
1505 static inline bool cpu_has_vmx_preemption_timer(void)
1507 return vmcs_config.pin_based_exec_ctrl &
1508 PIN_BASED_VMX_PREEMPTION_TIMER;
1511 static inline bool cpu_has_vmx_posted_intr(void)
1513 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1514 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1517 static inline bool cpu_has_vmx_apicv(void)
1519 return cpu_has_vmx_apic_register_virt() &&
1520 cpu_has_vmx_virtual_intr_delivery() &&
1521 cpu_has_vmx_posted_intr();
1524 static inline bool cpu_has_vmx_flexpriority(void)
1526 return cpu_has_vmx_tpr_shadow() &&
1527 cpu_has_vmx_virtualize_apic_accesses();
1530 static inline bool cpu_has_vmx_ept_execute_only(void)
1532 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1535 static inline bool cpu_has_vmx_ept_2m_page(void)
1537 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1540 static inline bool cpu_has_vmx_ept_1g_page(void)
1542 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1545 static inline bool cpu_has_vmx_ept_4levels(void)
1547 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1550 static inline bool cpu_has_vmx_ept_mt_wb(void)
1552 return vmx_capability.ept & VMX_EPTP_WB_BIT;
1555 static inline bool cpu_has_vmx_ept_5levels(void)
1557 return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1560 static inline bool cpu_has_vmx_ept_ad_bits(void)
1562 return vmx_capability.ept & VMX_EPT_AD_BIT;
1565 static inline bool cpu_has_vmx_invept_context(void)
1567 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1570 static inline bool cpu_has_vmx_invept_global(void)
1572 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1575 static inline bool cpu_has_vmx_invvpid_individual_addr(void)
1577 return vmx_capability.vpid & VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT;
1580 static inline bool cpu_has_vmx_invvpid_single(void)
1582 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1585 static inline bool cpu_has_vmx_invvpid_global(void)
1587 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1590 static inline bool cpu_has_vmx_invvpid(void)
1592 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1595 static inline bool cpu_has_vmx_ept(void)
1597 return vmcs_config.cpu_based_2nd_exec_ctrl &
1598 SECONDARY_EXEC_ENABLE_EPT;
1601 static inline bool cpu_has_vmx_unrestricted_guest(void)
1603 return vmcs_config.cpu_based_2nd_exec_ctrl &
1604 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1607 static inline bool cpu_has_vmx_ple(void)
1609 return vmcs_config.cpu_based_2nd_exec_ctrl &
1610 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1613 static inline bool cpu_has_vmx_basic_inout(void)
1615 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1618 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1620 return flexpriority_enabled && lapic_in_kernel(vcpu);
1623 static inline bool cpu_has_vmx_vpid(void)
1625 return vmcs_config.cpu_based_2nd_exec_ctrl &
1626 SECONDARY_EXEC_ENABLE_VPID;
1629 static inline bool cpu_has_vmx_rdtscp(void)
1631 return vmcs_config.cpu_based_2nd_exec_ctrl &
1632 SECONDARY_EXEC_RDTSCP;
1635 static inline bool cpu_has_vmx_invpcid(void)
1637 return vmcs_config.cpu_based_2nd_exec_ctrl &
1638 SECONDARY_EXEC_ENABLE_INVPCID;
1641 static inline bool cpu_has_virtual_nmis(void)
1643 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1646 static inline bool cpu_has_vmx_wbinvd_exit(void)
1648 return vmcs_config.cpu_based_2nd_exec_ctrl &
1649 SECONDARY_EXEC_WBINVD_EXITING;
1652 static inline bool cpu_has_vmx_shadow_vmcs(void)
1655 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1656 /* check if the cpu supports writing r/o exit information fields */
1657 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1660 return vmcs_config.cpu_based_2nd_exec_ctrl &
1661 SECONDARY_EXEC_SHADOW_VMCS;
1664 static inline bool cpu_has_vmx_pml(void)
1666 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1669 static inline bool cpu_has_vmx_tsc_scaling(void)
1671 return vmcs_config.cpu_based_2nd_exec_ctrl &
1672 SECONDARY_EXEC_TSC_SCALING;
1675 static inline bool cpu_has_vmx_vmfunc(void)
1677 return vmcs_config.cpu_based_2nd_exec_ctrl &
1678 SECONDARY_EXEC_ENABLE_VMFUNC;
1681 static bool vmx_umip_emulated(void)
1683 return vmcs_config.cpu_based_2nd_exec_ctrl &
1684 SECONDARY_EXEC_DESC;
1687 static inline bool report_flexpriority(void)
1689 return flexpriority_enabled;
1692 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1694 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low);
1698 * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE
1699 * to modify any valid field of the VMCS, or are the VM-exit
1700 * information fields read-only?
1702 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu)
1704 return to_vmx(vcpu)->nested.msrs.misc_low &
1705 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS;
1708 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1710 return vmcs12->cpu_based_vm_exec_control & bit;
1713 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1715 return (vmcs12->cpu_based_vm_exec_control &
1716 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1717 (vmcs12->secondary_vm_exec_control & bit);
1720 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1722 return vmcs12->pin_based_vm_exec_control &
1723 PIN_BASED_VMX_PREEMPTION_TIMER;
1726 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12)
1728 return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING;
1731 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1733 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1736 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1738 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1741 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1743 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
1746 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1748 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1751 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1753 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1756 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1758 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1761 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1763 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1766 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1768 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1771 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1773 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1776 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1778 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1781 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1783 return nested_cpu_has_vmfunc(vmcs12) &&
1784 (vmcs12->vm_function_control &
1785 VMX_VMFUNC_EPTP_SWITCHING);
1788 static inline bool is_nmi(u32 intr_info)
1790 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1791 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1794 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1796 unsigned long exit_qualification);
1797 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1798 struct vmcs12 *vmcs12,
1799 u32 reason, unsigned long qualification);
1801 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1805 for (i = 0; i < vmx->nmsrs; ++i)
1806 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1811 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1817 } operand = { vpid, 0, gva };
1819 asm volatile (__ex(ASM_VMX_INVVPID)
1820 /* CF==1 or ZF==1 --> rc = -1 */
1821 "; ja 1f ; ud2 ; 1:"
1822 : : "a"(&operand), "c"(ext) : "cc", "memory");
1825 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1829 } operand = {eptp, gpa};
1831 asm volatile (__ex(ASM_VMX_INVEPT)
1832 /* CF==1 or ZF==1 --> rc = -1 */
1833 "; ja 1f ; ud2 ; 1:\n"
1834 : : "a" (&operand), "c" (ext) : "cc", "memory");
1837 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1841 i = __find_msr_index(vmx, msr);
1843 return &vmx->guest_msrs[i];
1847 static void vmcs_clear(struct vmcs *vmcs)
1849 u64 phys_addr = __pa(vmcs);
1852 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1853 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1856 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1860 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1862 vmcs_clear(loaded_vmcs->vmcs);
1863 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1864 vmcs_clear(loaded_vmcs->shadow_vmcs);
1865 loaded_vmcs->cpu = -1;
1866 loaded_vmcs->launched = 0;
1869 static void vmcs_load(struct vmcs *vmcs)
1871 u64 phys_addr = __pa(vmcs);
1874 if (static_branch_unlikely(&enable_evmcs))
1875 return evmcs_load(phys_addr);
1877 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1878 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1881 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1885 #ifdef CONFIG_KEXEC_CORE
1887 * This bitmap is used to indicate whether the vmclear
1888 * operation is enabled on all cpus. All disabled by
1891 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1893 static inline void crash_enable_local_vmclear(int cpu)
1895 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1898 static inline void crash_disable_local_vmclear(int cpu)
1900 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1903 static inline int crash_local_vmclear_enabled(int cpu)
1905 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1908 static void crash_vmclear_local_loaded_vmcss(void)
1910 int cpu = raw_smp_processor_id();
1911 struct loaded_vmcs *v;
1913 if (!crash_local_vmclear_enabled(cpu))
1916 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1917 loaded_vmcss_on_cpu_link)
1918 vmcs_clear(v->vmcs);
1921 static inline void crash_enable_local_vmclear(int cpu) { }
1922 static inline void crash_disable_local_vmclear(int cpu) { }
1923 #endif /* CONFIG_KEXEC_CORE */
1925 static void __loaded_vmcs_clear(void *arg)
1927 struct loaded_vmcs *loaded_vmcs = arg;
1928 int cpu = raw_smp_processor_id();
1930 if (loaded_vmcs->cpu != cpu)
1931 return; /* vcpu migration can race with cpu offline */
1932 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1933 per_cpu(current_vmcs, cpu) = NULL;
1934 crash_disable_local_vmclear(cpu);
1935 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1938 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1939 * is before setting loaded_vmcs->vcpu to -1 which is done in
1940 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1941 * then adds the vmcs into percpu list before it is deleted.
1945 loaded_vmcs_init(loaded_vmcs);
1946 crash_enable_local_vmclear(cpu);
1949 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1951 int cpu = loaded_vmcs->cpu;
1954 smp_call_function_single(cpu,
1955 __loaded_vmcs_clear, loaded_vmcs, 1);
1958 static inline void vpid_sync_vcpu_single(int vpid)
1963 if (cpu_has_vmx_invvpid_single())
1964 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1967 static inline void vpid_sync_vcpu_global(void)
1969 if (cpu_has_vmx_invvpid_global())
1970 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1973 static inline void vpid_sync_context(int vpid)
1975 if (cpu_has_vmx_invvpid_single())
1976 vpid_sync_vcpu_single(vpid);
1978 vpid_sync_vcpu_global();
1981 static inline void ept_sync_global(void)
1983 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1986 static inline void ept_sync_context(u64 eptp)
1988 if (cpu_has_vmx_invept_context())
1989 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1994 static __always_inline void vmcs_check16(unsigned long field)
1996 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1997 "16-bit accessor invalid for 64-bit field");
1998 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1999 "16-bit accessor invalid for 64-bit high field");
2000 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2001 "16-bit accessor invalid for 32-bit high field");
2002 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2003 "16-bit accessor invalid for natural width field");
2006 static __always_inline void vmcs_check32(unsigned long field)
2008 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2009 "32-bit accessor invalid for 16-bit field");
2010 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2011 "32-bit accessor invalid for natural width field");
2014 static __always_inline void vmcs_check64(unsigned long field)
2016 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2017 "64-bit accessor invalid for 16-bit field");
2018 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2019 "64-bit accessor invalid for 64-bit high field");
2020 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2021 "64-bit accessor invalid for 32-bit field");
2022 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2023 "64-bit accessor invalid for natural width field");
2026 static __always_inline void vmcs_checkl(unsigned long field)
2028 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2029 "Natural width accessor invalid for 16-bit field");
2030 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2031 "Natural width accessor invalid for 64-bit field");
2032 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2033 "Natural width accessor invalid for 64-bit high field");
2034 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2035 "Natural width accessor invalid for 32-bit field");
2038 static __always_inline unsigned long __vmcs_readl(unsigned long field)
2040 unsigned long value;
2042 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
2043 : "=a"(value) : "d"(field) : "cc");
2047 static __always_inline u16 vmcs_read16(unsigned long field)
2049 vmcs_check16(field);
2050 if (static_branch_unlikely(&enable_evmcs))
2051 return evmcs_read16(field);
2052 return __vmcs_readl(field);
2055 static __always_inline u32 vmcs_read32(unsigned long field)
2057 vmcs_check32(field);
2058 if (static_branch_unlikely(&enable_evmcs))
2059 return evmcs_read32(field);
2060 return __vmcs_readl(field);
2063 static __always_inline u64 vmcs_read64(unsigned long field)
2065 vmcs_check64(field);
2066 if (static_branch_unlikely(&enable_evmcs))
2067 return evmcs_read64(field);
2068 #ifdef CONFIG_X86_64
2069 return __vmcs_readl(field);
2071 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
2075 static __always_inline unsigned long vmcs_readl(unsigned long field)
2078 if (static_branch_unlikely(&enable_evmcs))
2079 return evmcs_read64(field);
2080 return __vmcs_readl(field);
2083 static noinline void vmwrite_error(unsigned long field, unsigned long value)
2085 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
2086 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
2090 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
2094 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
2095 : "=q"(error) : "a"(value), "d"(field) : "cc");
2096 if (unlikely(error))
2097 vmwrite_error(field, value);
2100 static __always_inline void vmcs_write16(unsigned long field, u16 value)
2102 vmcs_check16(field);
2103 if (static_branch_unlikely(&enable_evmcs))
2104 return evmcs_write16(field, value);
2106 __vmcs_writel(field, value);
2109 static __always_inline void vmcs_write32(unsigned long field, u32 value)
2111 vmcs_check32(field);
2112 if (static_branch_unlikely(&enable_evmcs))
2113 return evmcs_write32(field, value);
2115 __vmcs_writel(field, value);
2118 static __always_inline void vmcs_write64(unsigned long field, u64 value)
2120 vmcs_check64(field);
2121 if (static_branch_unlikely(&enable_evmcs))
2122 return evmcs_write64(field, value);
2124 __vmcs_writel(field, value);
2125 #ifndef CONFIG_X86_64
2127 __vmcs_writel(field+1, value >> 32);
2131 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
2134 if (static_branch_unlikely(&enable_evmcs))
2135 return evmcs_write64(field, value);
2137 __vmcs_writel(field, value);
2140 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
2142 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2143 "vmcs_clear_bits does not support 64-bit fields");
2144 if (static_branch_unlikely(&enable_evmcs))
2145 return evmcs_write32(field, evmcs_read32(field) & ~mask);
2147 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
2150 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
2152 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2153 "vmcs_set_bits does not support 64-bit fields");
2154 if (static_branch_unlikely(&enable_evmcs))
2155 return evmcs_write32(field, evmcs_read32(field) | mask);
2157 __vmcs_writel(field, __vmcs_readl(field) | mask);
2160 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
2162 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
2165 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
2167 vmcs_write32(VM_ENTRY_CONTROLS, val);
2168 vmx->vm_entry_controls_shadow = val;
2171 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
2173 if (vmx->vm_entry_controls_shadow != val)
2174 vm_entry_controls_init(vmx, val);
2177 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
2179 return vmx->vm_entry_controls_shadow;
2183 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2185 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
2188 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2190 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
2193 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
2195 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
2198 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
2200 vmcs_write32(VM_EXIT_CONTROLS, val);
2201 vmx->vm_exit_controls_shadow = val;
2204 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
2206 if (vmx->vm_exit_controls_shadow != val)
2207 vm_exit_controls_init(vmx, val);
2210 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
2212 return vmx->vm_exit_controls_shadow;
2216 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2218 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
2221 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2223 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
2226 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
2228 vmx->segment_cache.bitmask = 0;
2231 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
2235 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
2237 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
2238 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
2239 vmx->segment_cache.bitmask = 0;
2241 ret = vmx->segment_cache.bitmask & mask;
2242 vmx->segment_cache.bitmask |= mask;
2246 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
2248 u16 *p = &vmx->segment_cache.seg[seg].selector;
2250 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
2251 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
2255 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
2257 ulong *p = &vmx->segment_cache.seg[seg].base;
2259 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
2260 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
2264 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
2266 u32 *p = &vmx->segment_cache.seg[seg].limit;
2268 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
2269 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
2273 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
2275 u32 *p = &vmx->segment_cache.seg[seg].ar;
2277 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
2278 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
2282 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
2286 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
2287 (1u << DB_VECTOR) | (1u << AC_VECTOR);
2289 * Guest access to VMware backdoor ports could legitimately
2290 * trigger #GP because of TSS I/O permission bitmap.
2291 * We intercept those #GP and allow access to them anyway
2294 if (enable_vmware_backdoor)
2295 eb |= (1u << GP_VECTOR);
2296 if ((vcpu->guest_debug &
2297 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
2298 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
2299 eb |= 1u << BP_VECTOR;
2300 if (to_vmx(vcpu)->rmode.vm86_active)
2303 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
2305 /* When we are running a nested L2 guest and L1 specified for it a
2306 * certain exception bitmap, we must trap the same exceptions and pass
2307 * them to L1. When running L2, we will only handle the exceptions
2308 * specified above if L1 did not want them.
2310 if (is_guest_mode(vcpu))
2311 eb |= get_vmcs12(vcpu)->exception_bitmap;
2313 vmcs_write32(EXCEPTION_BITMAP, eb);
2317 * Check if MSR is intercepted for currently loaded MSR bitmap.
2319 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
2321 unsigned long *msr_bitmap;
2322 int f = sizeof(unsigned long);
2324 if (!cpu_has_vmx_msr_bitmap())
2327 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
2329 if (msr <= 0x1fff) {
2330 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2331 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2333 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2340 * Check if MSR is intercepted for L01 MSR bitmap.
2342 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
2344 unsigned long *msr_bitmap;
2345 int f = sizeof(unsigned long);
2347 if (!cpu_has_vmx_msr_bitmap())
2350 msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
2352 if (msr <= 0x1fff) {
2353 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2354 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2356 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2362 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2363 unsigned long entry, unsigned long exit)
2365 vm_entry_controls_clearbit(vmx, entry);
2366 vm_exit_controls_clearbit(vmx, exit);
2369 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
2372 struct msr_autoload *m = &vmx->msr_autoload;
2376 if (cpu_has_load_ia32_efer) {
2377 clear_atomic_switch_msr_special(vmx,
2378 VM_ENTRY_LOAD_IA32_EFER,
2379 VM_EXIT_LOAD_IA32_EFER);
2383 case MSR_CORE_PERF_GLOBAL_CTRL:
2384 if (cpu_has_load_perf_global_ctrl) {
2385 clear_atomic_switch_msr_special(vmx,
2386 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2387 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2393 for (i = 0; i < m->nr; ++i)
2394 if (m->guest[i].index == msr)
2400 m->guest[i] = m->guest[m->nr];
2401 m->host[i] = m->host[m->nr];
2402 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2403 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2406 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2407 unsigned long entry, unsigned long exit,
2408 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
2409 u64 guest_val, u64 host_val)
2411 vmcs_write64(guest_val_vmcs, guest_val);
2412 vmcs_write64(host_val_vmcs, host_val);
2413 vm_entry_controls_setbit(vmx, entry);
2414 vm_exit_controls_setbit(vmx, exit);
2417 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
2418 u64 guest_val, u64 host_val)
2421 struct msr_autoload *m = &vmx->msr_autoload;
2425 if (cpu_has_load_ia32_efer) {
2426 add_atomic_switch_msr_special(vmx,
2427 VM_ENTRY_LOAD_IA32_EFER,
2428 VM_EXIT_LOAD_IA32_EFER,
2431 guest_val, host_val);
2435 case MSR_CORE_PERF_GLOBAL_CTRL:
2436 if (cpu_has_load_perf_global_ctrl) {
2437 add_atomic_switch_msr_special(vmx,
2438 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2439 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2440 GUEST_IA32_PERF_GLOBAL_CTRL,
2441 HOST_IA32_PERF_GLOBAL_CTRL,
2442 guest_val, host_val);
2446 case MSR_IA32_PEBS_ENABLE:
2447 /* PEBS needs a quiescent period after being disabled (to write
2448 * a record). Disabling PEBS through VMX MSR swapping doesn't
2449 * provide that period, so a CPU could write host's record into
2452 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2455 for (i = 0; i < m->nr; ++i)
2456 if (m->guest[i].index == msr)
2459 if (i == NR_AUTOLOAD_MSRS) {
2460 printk_once(KERN_WARNING "Not enough msr switch entries. "
2461 "Can't add msr %x\n", msr);
2463 } else if (i == m->nr) {
2465 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2466 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2469 m->guest[i].index = msr;
2470 m->guest[i].value = guest_val;
2471 m->host[i].index = msr;
2472 m->host[i].value = host_val;
2475 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2477 u64 guest_efer = vmx->vcpu.arch.efer;
2478 u64 ignore_bits = 0;
2482 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2483 * host CPUID is more efficient than testing guest CPUID
2484 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2486 if (boot_cpu_has(X86_FEATURE_SMEP))
2487 guest_efer |= EFER_NX;
2488 else if (!(guest_efer & EFER_NX))
2489 ignore_bits |= EFER_NX;
2493 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2495 ignore_bits |= EFER_SCE;
2496 #ifdef CONFIG_X86_64
2497 ignore_bits |= EFER_LMA | EFER_LME;
2498 /* SCE is meaningful only in long mode on Intel */
2499 if (guest_efer & EFER_LMA)
2500 ignore_bits &= ~(u64)EFER_SCE;
2503 clear_atomic_switch_msr(vmx, MSR_EFER);
2506 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2507 * On CPUs that support "load IA32_EFER", always switch EFER
2508 * atomically, since it's faster than switching it manually.
2510 if (cpu_has_load_ia32_efer ||
2511 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2512 if (!(guest_efer & EFER_LMA))
2513 guest_efer &= ~EFER_LME;
2514 if (guest_efer != host_efer)
2515 add_atomic_switch_msr(vmx, MSR_EFER,
2516 guest_efer, host_efer);
2519 guest_efer &= ~ignore_bits;
2520 guest_efer |= host_efer & ignore_bits;
2522 vmx->guest_msrs[efer_offset].data = guest_efer;
2523 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2529 #ifdef CONFIG_X86_32
2531 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2532 * VMCS rather than the segment table. KVM uses this helper to figure
2533 * out the current bases to poke them into the VMCS before entry.
2535 static unsigned long segment_base(u16 selector)
2537 struct desc_struct *table;
2540 if (!(selector & ~SEGMENT_RPL_MASK))
2543 table = get_current_gdt_ro();
2545 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2546 u16 ldt_selector = kvm_read_ldt();
2548 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2551 table = (struct desc_struct *)segment_base(ldt_selector);
2553 v = get_desc_base(&table[selector >> 3]);
2558 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2560 struct vcpu_vmx *vmx = to_vmx(vcpu);
2561 #ifdef CONFIG_X86_64
2562 int cpu = raw_smp_processor_id();
2566 if (vmx->host_state.loaded)
2569 vmx->host_state.loaded = 1;
2571 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2572 * allow segment selectors with cpl > 0 or ti == 1.
2574 vmx->host_state.ldt_sel = kvm_read_ldt();
2575 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2577 #ifdef CONFIG_X86_64
2578 save_fsgs_for_kvm();
2579 vmx->host_state.fs_sel = current->thread.fsindex;
2580 vmx->host_state.gs_sel = current->thread.gsindex;
2582 savesegment(fs, vmx->host_state.fs_sel);
2583 savesegment(gs, vmx->host_state.gs_sel);
2585 if (!(vmx->host_state.fs_sel & 7)) {
2586 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2587 vmx->host_state.fs_reload_needed = 0;
2589 vmcs_write16(HOST_FS_SELECTOR, 0);
2590 vmx->host_state.fs_reload_needed = 1;
2592 if (!(vmx->host_state.gs_sel & 7))
2593 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2595 vmcs_write16(HOST_GS_SELECTOR, 0);
2596 vmx->host_state.gs_ldt_reload_needed = 1;
2599 #ifdef CONFIG_X86_64
2600 savesegment(ds, vmx->host_state.ds_sel);
2601 savesegment(es, vmx->host_state.es_sel);
2603 vmcs_writel(HOST_FS_BASE, current->thread.fsbase);
2604 vmcs_writel(HOST_GS_BASE, cpu_kernelmode_gs_base(cpu));
2606 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
2607 if (is_long_mode(&vmx->vcpu))
2608 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2610 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2611 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2613 if (boot_cpu_has(X86_FEATURE_MPX))
2614 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2615 for (i = 0; i < vmx->save_nmsrs; ++i)
2616 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2617 vmx->guest_msrs[i].data,
2618 vmx->guest_msrs[i].mask);
2621 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2623 if (!vmx->host_state.loaded)
2626 ++vmx->vcpu.stat.host_state_reload;
2627 vmx->host_state.loaded = 0;
2628 #ifdef CONFIG_X86_64
2629 if (is_long_mode(&vmx->vcpu))
2630 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2632 if (vmx->host_state.gs_ldt_reload_needed) {
2633 kvm_load_ldt(vmx->host_state.ldt_sel);
2634 #ifdef CONFIG_X86_64
2635 load_gs_index(vmx->host_state.gs_sel);
2637 loadsegment(gs, vmx->host_state.gs_sel);
2640 if (vmx->host_state.fs_reload_needed)
2641 loadsegment(fs, vmx->host_state.fs_sel);
2642 #ifdef CONFIG_X86_64
2643 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2644 loadsegment(ds, vmx->host_state.ds_sel);
2645 loadsegment(es, vmx->host_state.es_sel);
2648 invalidate_tss_limit();
2649 #ifdef CONFIG_X86_64
2650 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2652 if (vmx->host_state.msr_host_bndcfgs)
2653 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2654 load_fixmap_gdt(raw_smp_processor_id());
2657 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2660 __vmx_load_host_state(vmx);
2664 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2666 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2667 struct pi_desc old, new;
2671 * In case of hot-plug or hot-unplug, we may have to undo
2672 * vmx_vcpu_pi_put even if there is no assigned device. And we
2673 * always keep PI.NDST up to date for simplicity: it makes the
2674 * code easier, and CPU migration is not a fast path.
2676 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2680 * First handle the simple case where no cmpxchg is necessary; just
2681 * allow posting non-urgent interrupts.
2683 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2684 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2685 * expects the VCPU to be on the blocked_vcpu_list that matches
2688 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2690 pi_clear_sn(pi_desc);
2694 /* The full case. */
2696 old.control = new.control = pi_desc->control;
2698 dest = cpu_physical_id(cpu);
2700 if (x2apic_enabled())
2703 new.ndst = (dest << 8) & 0xFF00;
2706 } while (cmpxchg64(&pi_desc->control, old.control,
2707 new.control) != old.control);
2710 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2712 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2713 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2717 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2718 * vcpu mutex is already taken.
2720 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2722 struct vcpu_vmx *vmx = to_vmx(vcpu);
2723 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2725 if (!already_loaded) {
2726 loaded_vmcs_clear(vmx->loaded_vmcs);
2727 local_irq_disable();
2728 crash_disable_local_vmclear(cpu);
2731 * Read loaded_vmcs->cpu should be before fetching
2732 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2733 * See the comments in __loaded_vmcs_clear().
2737 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2738 &per_cpu(loaded_vmcss_on_cpu, cpu));
2739 crash_enable_local_vmclear(cpu);
2743 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2744 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2745 vmcs_load(vmx->loaded_vmcs->vmcs);
2746 indirect_branch_prediction_barrier();
2749 if (!already_loaded) {
2750 void *gdt = get_current_gdt_ro();
2751 unsigned long sysenter_esp;
2753 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2756 * Linux uses per-cpu TSS and GDT, so set these when switching
2757 * processors. See 22.2.4.
2759 vmcs_writel(HOST_TR_BASE,
2760 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
2761 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
2764 * VM exits change the host TR limit to 0x67 after a VM
2765 * exit. This is okay, since 0x67 covers everything except
2766 * the IO bitmap and have have code to handle the IO bitmap
2767 * being lost after a VM exit.
2769 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2771 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2772 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2774 vmx->loaded_vmcs->cpu = cpu;
2777 /* Setup TSC multiplier */
2778 if (kvm_has_tsc_control &&
2779 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2780 decache_tsc_multiplier(vmx);
2782 vmx_vcpu_pi_load(vcpu, cpu);
2783 vmx->host_pkru = read_pkru();
2784 vmx->host_debugctlmsr = get_debugctlmsr();
2787 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2789 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2791 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2792 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2793 !kvm_vcpu_apicv_active(vcpu))
2796 /* Set SN when the vCPU is preempted */
2797 if (vcpu->preempted)
2801 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2803 vmx_vcpu_pi_put(vcpu);
2805 __vmx_load_host_state(to_vmx(vcpu));
2808 static bool emulation_required(struct kvm_vcpu *vcpu)
2810 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2813 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2816 * Return the cr0 value that a nested guest would read. This is a combination
2817 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2818 * its hypervisor (cr0_read_shadow).
2820 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2822 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2823 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2825 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2827 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2828 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2831 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2833 unsigned long rflags, save_rflags;
2835 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2836 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2837 rflags = vmcs_readl(GUEST_RFLAGS);
2838 if (to_vmx(vcpu)->rmode.vm86_active) {
2839 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2840 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2841 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2843 to_vmx(vcpu)->rflags = rflags;
2845 return to_vmx(vcpu)->rflags;
2848 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2850 unsigned long old_rflags = vmx_get_rflags(vcpu);
2852 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2853 to_vmx(vcpu)->rflags = rflags;
2854 if (to_vmx(vcpu)->rmode.vm86_active) {
2855 to_vmx(vcpu)->rmode.save_rflags = rflags;
2856 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2858 vmcs_writel(GUEST_RFLAGS, rflags);
2860 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2861 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2864 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2866 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2869 if (interruptibility & GUEST_INTR_STATE_STI)
2870 ret |= KVM_X86_SHADOW_INT_STI;
2871 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2872 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2877 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2879 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2880 u32 interruptibility = interruptibility_old;
2882 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2884 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2885 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2886 else if (mask & KVM_X86_SHADOW_INT_STI)
2887 interruptibility |= GUEST_INTR_STATE_STI;
2889 if ((interruptibility != interruptibility_old))
2890 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2893 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2897 rip = kvm_rip_read(vcpu);
2898 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2899 kvm_rip_write(vcpu, rip);
2901 /* skipping an emulated instruction also counts */
2902 vmx_set_interrupt_shadow(vcpu, 0);
2905 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2906 unsigned long exit_qual)
2908 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2909 unsigned int nr = vcpu->arch.exception.nr;
2910 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2912 if (vcpu->arch.exception.has_error_code) {
2913 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2914 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2917 if (kvm_exception_is_soft(nr))
2918 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2920 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2922 if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2923 vmx_get_nmi_mask(vcpu))
2924 intr_info |= INTR_INFO_UNBLOCK_NMI;
2926 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2930 * KVM wants to inject page-faults which it got to the guest. This function
2931 * checks whether in a nested guest, we need to inject them to L1 or L2.
2933 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
2935 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2936 unsigned int nr = vcpu->arch.exception.nr;
2938 if (nr == PF_VECTOR) {
2939 if (vcpu->arch.exception.nested_apf) {
2940 *exit_qual = vcpu->arch.apf.nested_apf_token;
2944 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2945 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2946 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2947 * can be written only when inject_pending_event runs. This should be
2948 * conditional on a new capability---if the capability is disabled,
2949 * kvm_multiple_exception would write the ancillary information to
2950 * CR2 or DR6, for backwards ABI-compatibility.
2952 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2953 vcpu->arch.exception.error_code)) {
2954 *exit_qual = vcpu->arch.cr2;
2958 if (vmcs12->exception_bitmap & (1u << nr)) {
2959 if (nr == DB_VECTOR)
2960 *exit_qual = vcpu->arch.dr6;
2970 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
2973 * Ensure that we clear the HLT state in the VMCS. We don't need to
2974 * explicitly skip the instruction because if the HLT state is set,
2975 * then the instruction is already executing and RIP has already been
2978 if (kvm_hlt_in_guest(vcpu->kvm) &&
2979 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
2980 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
2983 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2985 struct vcpu_vmx *vmx = to_vmx(vcpu);
2986 unsigned nr = vcpu->arch.exception.nr;
2987 bool has_error_code = vcpu->arch.exception.has_error_code;
2988 u32 error_code = vcpu->arch.exception.error_code;
2989 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2991 if (has_error_code) {
2992 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2993 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2996 if (vmx->rmode.vm86_active) {
2998 if (kvm_exception_is_soft(nr))
2999 inc_eip = vcpu->arch.event_exit_inst_len;
3000 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
3001 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3005 WARN_ON_ONCE(vmx->emulation_required);
3007 if (kvm_exception_is_soft(nr)) {
3008 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3009 vmx->vcpu.arch.event_exit_inst_len);
3010 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3012 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3014 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
3016 vmx_clear_hlt(vcpu);
3019 static bool vmx_rdtscp_supported(void)
3021 return cpu_has_vmx_rdtscp();
3024 static bool vmx_invpcid_supported(void)
3026 return cpu_has_vmx_invpcid() && enable_ept;
3030 * Swap MSR entry in host/guest MSR entry array.
3032 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
3034 struct shared_msr_entry tmp;
3036 tmp = vmx->guest_msrs[to];
3037 vmx->guest_msrs[to] = vmx->guest_msrs[from];
3038 vmx->guest_msrs[from] = tmp;
3042 * Set up the vmcs to automatically save and restore system
3043 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
3044 * mode, as fiddling with msrs is very expensive.
3046 static void setup_msrs(struct vcpu_vmx *vmx)
3048 int save_nmsrs, index;
3051 #ifdef CONFIG_X86_64
3052 if (is_long_mode(&vmx->vcpu)) {
3053 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
3055 move_msr_up(vmx, index, save_nmsrs++);
3056 index = __find_msr_index(vmx, MSR_LSTAR);
3058 move_msr_up(vmx, index, save_nmsrs++);
3059 index = __find_msr_index(vmx, MSR_CSTAR);
3061 move_msr_up(vmx, index, save_nmsrs++);
3062 index = __find_msr_index(vmx, MSR_TSC_AUX);
3063 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
3064 move_msr_up(vmx, index, save_nmsrs++);
3066 * MSR_STAR is only needed on long mode guests, and only
3067 * if efer.sce is enabled.
3069 index = __find_msr_index(vmx, MSR_STAR);
3070 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
3071 move_msr_up(vmx, index, save_nmsrs++);
3074 index = __find_msr_index(vmx, MSR_EFER);
3075 if (index >= 0 && update_transition_efer(vmx, index))
3076 move_msr_up(vmx, index, save_nmsrs++);
3078 vmx->save_nmsrs = save_nmsrs;
3080 if (cpu_has_vmx_msr_bitmap())
3081 vmx_update_msr_bitmap(&vmx->vcpu);
3084 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
3086 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3088 if (is_guest_mode(vcpu) &&
3089 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
3090 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
3092 return vcpu->arch.tsc_offset;
3096 * writes 'offset' into guest's timestamp counter offset register
3098 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
3100 if (is_guest_mode(vcpu)) {
3102 * We're here if L1 chose not to trap WRMSR to TSC. According
3103 * to the spec, this should set L1's TSC; The offset that L1
3104 * set for L2 remains unchanged, and still needs to be added
3105 * to the newly set TSC to get L2's TSC.
3107 struct vmcs12 *vmcs12;
3108 /* recalculate vmcs02.TSC_OFFSET: */
3109 vmcs12 = get_vmcs12(vcpu);
3110 vmcs_write64(TSC_OFFSET, offset +
3111 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
3112 vmcs12->tsc_offset : 0));
3114 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
3115 vmcs_read64(TSC_OFFSET), offset);
3116 vmcs_write64(TSC_OFFSET, offset);
3121 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
3122 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
3123 * all guests if the "nested" module option is off, and can also be disabled
3124 * for a single guest by disabling its VMX cpuid bit.
3126 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
3128 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
3132 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
3133 * returned for the various VMX controls MSRs when nested VMX is enabled.
3134 * The same values should also be used to verify that vmcs12 control fields are
3135 * valid during nested entry from L1 to L2.
3136 * Each of these control msrs has a low and high 32-bit half: A low bit is on
3137 * if the corresponding bit in the (32-bit) control field *must* be on, and a
3138 * bit in the high half is on if the corresponding bit in the control field
3139 * may be on. See also vmx_control_verify().
3141 static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv)
3144 memset(msrs, 0, sizeof(*msrs));
3149 * Note that as a general rule, the high half of the MSRs (bits in
3150 * the control fields which may be 1) should be initialized by the
3151 * intersection of the underlying hardware's MSR (i.e., features which
3152 * can be supported) and the list of features we want to expose -
3153 * because they are known to be properly supported in our code.
3154 * Also, usually, the low half of the MSRs (bits which must be 1) can
3155 * be set to 0, meaning that L1 may turn off any of these bits. The
3156 * reason is that if one of these bits is necessary, it will appear
3157 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
3158 * fields of vmcs01 and vmcs02, will turn these bits off - and
3159 * nested_vmx_exit_reflected() will not pass related exits to L1.
3160 * These rules have exceptions below.
3163 /* pin-based controls */
3164 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
3165 msrs->pinbased_ctls_low,
3166 msrs->pinbased_ctls_high);
3167 msrs->pinbased_ctls_low |=
3168 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3169 msrs->pinbased_ctls_high &=
3170 PIN_BASED_EXT_INTR_MASK |
3171 PIN_BASED_NMI_EXITING |
3172 PIN_BASED_VIRTUAL_NMIS |
3173 (apicv ? PIN_BASED_POSTED_INTR : 0);
3174 msrs->pinbased_ctls_high |=
3175 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3176 PIN_BASED_VMX_PREEMPTION_TIMER;
3179 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
3180 msrs->exit_ctls_low,
3181 msrs->exit_ctls_high);
3182 msrs->exit_ctls_low =
3183 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3185 msrs->exit_ctls_high &=
3186 #ifdef CONFIG_X86_64
3187 VM_EXIT_HOST_ADDR_SPACE_SIZE |
3189 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
3190 msrs->exit_ctls_high |=
3191 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
3192 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
3193 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
3195 if (kvm_mpx_supported())
3196 msrs->exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
3198 /* We support free control of debug control saving. */
3199 msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
3201 /* entry controls */
3202 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
3203 msrs->entry_ctls_low,
3204 msrs->entry_ctls_high);
3205 msrs->entry_ctls_low =
3206 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3207 msrs->entry_ctls_high &=
3208 #ifdef CONFIG_X86_64
3209 VM_ENTRY_IA32E_MODE |
3211 VM_ENTRY_LOAD_IA32_PAT;
3212 msrs->entry_ctls_high |=
3213 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
3214 if (kvm_mpx_supported())
3215 msrs->entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
3217 /* We support free control of debug control loading. */
3218 msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
3220 /* cpu-based controls */
3221 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
3222 msrs->procbased_ctls_low,
3223 msrs->procbased_ctls_high);
3224 msrs->procbased_ctls_low =
3225 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3226 msrs->procbased_ctls_high &=
3227 CPU_BASED_VIRTUAL_INTR_PENDING |
3228 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
3229 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
3230 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
3231 CPU_BASED_CR3_STORE_EXITING |
3232 #ifdef CONFIG_X86_64
3233 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
3235 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
3236 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
3237 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
3238 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
3239 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3241 * We can allow some features even when not supported by the
3242 * hardware. For example, L1 can specify an MSR bitmap - and we
3243 * can use it to avoid exits to L1 - even when L0 runs L2
3244 * without MSR bitmaps.
3246 msrs->procbased_ctls_high |=
3247 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3248 CPU_BASED_USE_MSR_BITMAPS;
3250 /* We support free control of CR3 access interception. */
3251 msrs->procbased_ctls_low &=
3252 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
3255 * secondary cpu-based controls. Do not include those that
3256 * depend on CPUID bits, they are added later by vmx_cpuid_update.
3258 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
3259 msrs->secondary_ctls_low,
3260 msrs->secondary_ctls_high);
3261 msrs->secondary_ctls_low = 0;
3262 msrs->secondary_ctls_high &=
3263 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3264 SECONDARY_EXEC_DESC |
3265 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3266 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3267 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3268 SECONDARY_EXEC_WBINVD_EXITING;
3271 /* nested EPT: emulate EPT also to L1 */
3272 msrs->secondary_ctls_high |=
3273 SECONDARY_EXEC_ENABLE_EPT;
3274 msrs->ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
3275 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
3276 if (cpu_has_vmx_ept_execute_only())
3278 VMX_EPT_EXECUTE_ONLY_BIT;
3279 msrs->ept_caps &= vmx_capability.ept;
3280 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
3281 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
3282 VMX_EPT_1GB_PAGE_BIT;
3283 if (enable_ept_ad_bits) {
3284 msrs->secondary_ctls_high |=
3285 SECONDARY_EXEC_ENABLE_PML;
3286 msrs->ept_caps |= VMX_EPT_AD_BIT;
3290 if (cpu_has_vmx_vmfunc()) {
3291 msrs->secondary_ctls_high |=
3292 SECONDARY_EXEC_ENABLE_VMFUNC;
3294 * Advertise EPTP switching unconditionally
3295 * since we emulate it
3298 msrs->vmfunc_controls =
3299 VMX_VMFUNC_EPTP_SWITCHING;
3303 * Old versions of KVM use the single-context version without
3304 * checking for support, so declare that it is supported even
3305 * though it is treated as global context. The alternative is
3306 * not failing the single-context invvpid, and it is worse.
3309 msrs->secondary_ctls_high |=
3310 SECONDARY_EXEC_ENABLE_VPID;
3311 msrs->vpid_caps = VMX_VPID_INVVPID_BIT |
3312 VMX_VPID_EXTENT_SUPPORTED_MASK;
3315 if (enable_unrestricted_guest)
3316 msrs->secondary_ctls_high |=
3317 SECONDARY_EXEC_UNRESTRICTED_GUEST;
3319 /* miscellaneous data */
3320 rdmsr(MSR_IA32_VMX_MISC,
3323 msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA;
3325 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
3326 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
3327 VMX_MISC_ACTIVITY_HLT;
3328 msrs->misc_high = 0;
3331 * This MSR reports some information about VMX support. We
3332 * should return information about the VMX we emulate for the
3333 * guest, and the VMCS structure we give it - not about the
3334 * VMX support of the underlying hardware.
3338 VMX_BASIC_TRUE_CTLS |
3339 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
3340 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
3342 if (cpu_has_vmx_basic_inout())
3343 msrs->basic |= VMX_BASIC_INOUT;
3346 * These MSRs specify bits which the guest must keep fixed on
3347 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
3348 * We picked the standard core2 setting.
3350 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
3351 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
3352 msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON;
3353 msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
3355 /* These MSRs specify bits which the guest must keep fixed off. */
3356 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
3357 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
3359 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
3360 msrs->vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1;
3364 * if fixed0[i] == 1: val[i] must be 1
3365 * if fixed1[i] == 0: val[i] must be 0
3367 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
3369 return ((val & fixed1) | fixed0) == val;
3372 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
3374 return fixed_bits_valid(control, low, high);
3377 static inline u64 vmx_control_msr(u32 low, u32 high)
3379 return low | ((u64)high << 32);
3382 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
3387 return (superset | subset) == superset;
3390 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
3392 const u64 feature_and_reserved =
3393 /* feature (except bit 48; see below) */
3394 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
3396 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
3397 u64 vmx_basic = vmx->nested.msrs.basic;
3399 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
3403 * KVM does not emulate a version of VMX that constrains physical
3404 * addresses of VMX structures (e.g. VMCS) to 32-bits.
3406 if (data & BIT_ULL(48))
3409 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
3410 vmx_basic_vmcs_revision_id(data))
3413 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
3416 vmx->nested.msrs.basic = data;
3421 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3426 switch (msr_index) {
3427 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3428 lowp = &vmx->nested.msrs.pinbased_ctls_low;
3429 highp = &vmx->nested.msrs.pinbased_ctls_high;
3431 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3432 lowp = &vmx->nested.msrs.procbased_ctls_low;
3433 highp = &vmx->nested.msrs.procbased_ctls_high;
3435 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3436 lowp = &vmx->nested.msrs.exit_ctls_low;
3437 highp = &vmx->nested.msrs.exit_ctls_high;
3439 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3440 lowp = &vmx->nested.msrs.entry_ctls_low;
3441 highp = &vmx->nested.msrs.entry_ctls_high;
3443 case MSR_IA32_VMX_PROCBASED_CTLS2:
3444 lowp = &vmx->nested.msrs.secondary_ctls_low;
3445 highp = &vmx->nested.msrs.secondary_ctls_high;
3451 supported = vmx_control_msr(*lowp, *highp);
3453 /* Check must-be-1 bits are still 1. */
3454 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3457 /* Check must-be-0 bits are still 0. */
3458 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3462 *highp = data >> 32;
3466 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3468 const u64 feature_and_reserved_bits =
3470 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3471 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3473 GENMASK_ULL(13, 9) | BIT_ULL(31);
3476 vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
3477 vmx->nested.msrs.misc_high);
3479 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3482 if ((vmx->nested.msrs.pinbased_ctls_high &
3483 PIN_BASED_VMX_PREEMPTION_TIMER) &&
3484 vmx_misc_preemption_timer_rate(data) !=
3485 vmx_misc_preemption_timer_rate(vmx_misc))
3488 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3491 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3494 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3497 vmx->nested.msrs.misc_low = data;
3498 vmx->nested.msrs.misc_high = data >> 32;
3501 * If L1 has read-only VM-exit information fields, use the
3502 * less permissive vmx_vmwrite_bitmap to specify write
3503 * permissions for the shadow VMCS.
3505 if (enable_shadow_vmcs && !nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
3506 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
3511 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3513 u64 vmx_ept_vpid_cap;
3515 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps,
3516 vmx->nested.msrs.vpid_caps);
3518 /* Every bit is either reserved or a feature bit. */
3519 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3522 vmx->nested.msrs.ept_caps = data;
3523 vmx->nested.msrs.vpid_caps = data >> 32;
3527 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3531 switch (msr_index) {
3532 case MSR_IA32_VMX_CR0_FIXED0:
3533 msr = &vmx->nested.msrs.cr0_fixed0;
3535 case MSR_IA32_VMX_CR4_FIXED0:
3536 msr = &vmx->nested.msrs.cr4_fixed0;
3543 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3544 * must be 1 in the restored value.
3546 if (!is_bitwise_subset(data, *msr, -1ULL))
3554 * Called when userspace is restoring VMX MSRs.
3556 * Returns 0 on success, non-0 otherwise.
3558 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3560 struct vcpu_vmx *vmx = to_vmx(vcpu);
3563 * Don't allow changes to the VMX capability MSRs while the vCPU
3564 * is in VMX operation.
3566 if (vmx->nested.vmxon)
3569 switch (msr_index) {
3570 case MSR_IA32_VMX_BASIC:
3571 return vmx_restore_vmx_basic(vmx, data);
3572 case MSR_IA32_VMX_PINBASED_CTLS:
3573 case MSR_IA32_VMX_PROCBASED_CTLS:
3574 case MSR_IA32_VMX_EXIT_CTLS:
3575 case MSR_IA32_VMX_ENTRY_CTLS:
3577 * The "non-true" VMX capability MSRs are generated from the
3578 * "true" MSRs, so we do not support restoring them directly.
3580 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3581 * should restore the "true" MSRs with the must-be-1 bits
3582 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3583 * DEFAULT SETTINGS".
3586 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3587 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3588 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3589 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3590 case MSR_IA32_VMX_PROCBASED_CTLS2:
3591 return vmx_restore_control_msr(vmx, msr_index, data);
3592 case MSR_IA32_VMX_MISC:
3593 return vmx_restore_vmx_misc(vmx, data);
3594 case MSR_IA32_VMX_CR0_FIXED0:
3595 case MSR_IA32_VMX_CR4_FIXED0:
3596 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3597 case MSR_IA32_VMX_CR0_FIXED1:
3598 case MSR_IA32_VMX_CR4_FIXED1:
3600 * These MSRs are generated based on the vCPU's CPUID, so we
3601 * do not support restoring them directly.
3604 case MSR_IA32_VMX_EPT_VPID_CAP:
3605 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3606 case MSR_IA32_VMX_VMCS_ENUM:
3607 vmx->nested.msrs.vmcs_enum = data;
3611 * The rest of the VMX capability MSRs do not support restore.
3617 /* Returns 0 on success, non-0 otherwise. */
3618 static int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata)
3620 switch (msr_index) {
3621 case MSR_IA32_VMX_BASIC:
3622 *pdata = msrs->basic;
3624 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3625 case MSR_IA32_VMX_PINBASED_CTLS:
3626 *pdata = vmx_control_msr(
3627 msrs->pinbased_ctls_low,
3628 msrs->pinbased_ctls_high);
3629 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3630 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3632 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3633 case MSR_IA32_VMX_PROCBASED_CTLS:
3634 *pdata = vmx_control_msr(
3635 msrs->procbased_ctls_low,
3636 msrs->procbased_ctls_high);
3637 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3638 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3640 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3641 case MSR_IA32_VMX_EXIT_CTLS:
3642 *pdata = vmx_control_msr(
3643 msrs->exit_ctls_low,
3644 msrs->exit_ctls_high);
3645 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3646 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3648 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3649 case MSR_IA32_VMX_ENTRY_CTLS:
3650 *pdata = vmx_control_msr(
3651 msrs->entry_ctls_low,
3652 msrs->entry_ctls_high);
3653 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3654 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3656 case MSR_IA32_VMX_MISC:
3657 *pdata = vmx_control_msr(
3661 case MSR_IA32_VMX_CR0_FIXED0:
3662 *pdata = msrs->cr0_fixed0;
3664 case MSR_IA32_VMX_CR0_FIXED1:
3665 *pdata = msrs->cr0_fixed1;
3667 case MSR_IA32_VMX_CR4_FIXED0:
3668 *pdata = msrs->cr4_fixed0;
3670 case MSR_IA32_VMX_CR4_FIXED1:
3671 *pdata = msrs->cr4_fixed1;
3673 case MSR_IA32_VMX_VMCS_ENUM:
3674 *pdata = msrs->vmcs_enum;
3676 case MSR_IA32_VMX_PROCBASED_CTLS2:
3677 *pdata = vmx_control_msr(
3678 msrs->secondary_ctls_low,
3679 msrs->secondary_ctls_high);
3681 case MSR_IA32_VMX_EPT_VPID_CAP:
3682 *pdata = msrs->ept_caps |
3683 ((u64)msrs->vpid_caps << 32);
3685 case MSR_IA32_VMX_VMFUNC:
3686 *pdata = msrs->vmfunc_controls;
3695 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3698 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3700 return !(val & ~valid_bits);
3703 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
3705 switch (msr->index) {
3706 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3709 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
3718 * Reads an msr value (of 'msr_index') into 'pdata'.
3719 * Returns 0 on success, non-0 otherwise.
3720 * Assumes vcpu_load() was already called.
3722 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3724 struct vcpu_vmx *vmx = to_vmx(vcpu);
3725 struct shared_msr_entry *msr;
3727 switch (msr_info->index) {
3728 #ifdef CONFIG_X86_64
3730 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3733 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3735 case MSR_KERNEL_GS_BASE:
3736 vmx_load_host_state(vmx);
3737 msr_info->data = vmx->msr_guest_kernel_gs_base;
3741 return kvm_get_msr_common(vcpu, msr_info);
3742 case MSR_IA32_SPEC_CTRL:
3743 if (!msr_info->host_initiated &&
3744 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3747 msr_info->data = to_vmx(vcpu)->spec_ctrl;
3749 case MSR_IA32_ARCH_CAPABILITIES:
3750 if (!msr_info->host_initiated &&
3751 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3753 msr_info->data = to_vmx(vcpu)->arch_capabilities;
3755 case MSR_IA32_SYSENTER_CS:
3756 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3758 case MSR_IA32_SYSENTER_EIP:
3759 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3761 case MSR_IA32_SYSENTER_ESP:
3762 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3764 case MSR_IA32_BNDCFGS:
3765 if (!kvm_mpx_supported() ||
3766 (!msr_info->host_initiated &&
3767 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3769 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3771 case MSR_IA32_MCG_EXT_CTL:
3772 if (!msr_info->host_initiated &&
3773 !(vmx->msr_ia32_feature_control &
3774 FEATURE_CONTROL_LMCE))
3776 msr_info->data = vcpu->arch.mcg_ext_ctl;
3778 case MSR_IA32_FEATURE_CONTROL:
3779 msr_info->data = vmx->msr_ia32_feature_control;
3781 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3782 if (!nested_vmx_allowed(vcpu))
3784 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
3787 if (!vmx_xsaves_supported())
3789 msr_info->data = vcpu->arch.ia32_xss;
3792 if (!msr_info->host_initiated &&
3793 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3795 /* Otherwise falls through */
3797 msr = find_msr_entry(vmx, msr_info->index);
3799 msr_info->data = msr->data;
3802 return kvm_get_msr_common(vcpu, msr_info);
3808 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3811 * Writes msr value into into the appropriate "register".
3812 * Returns 0 on success, non-0 otherwise.
3813 * Assumes vcpu_load() was already called.
3815 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3817 struct vcpu_vmx *vmx = to_vmx(vcpu);
3818 struct shared_msr_entry *msr;
3820 u32 msr_index = msr_info->index;
3821 u64 data = msr_info->data;
3823 switch (msr_index) {
3825 ret = kvm_set_msr_common(vcpu, msr_info);
3827 #ifdef CONFIG_X86_64
3829 vmx_segment_cache_clear(vmx);
3830 vmcs_writel(GUEST_FS_BASE, data);
3833 vmx_segment_cache_clear(vmx);
3834 vmcs_writel(GUEST_GS_BASE, data);
3836 case MSR_KERNEL_GS_BASE:
3837 vmx_load_host_state(vmx);
3838 vmx->msr_guest_kernel_gs_base = data;
3841 case MSR_IA32_SYSENTER_CS:
3842 vmcs_write32(GUEST_SYSENTER_CS, data);
3844 case MSR_IA32_SYSENTER_EIP:
3845 vmcs_writel(GUEST_SYSENTER_EIP, data);
3847 case MSR_IA32_SYSENTER_ESP:
3848 vmcs_writel(GUEST_SYSENTER_ESP, data);
3850 case MSR_IA32_BNDCFGS:
3851 if (!kvm_mpx_supported() ||
3852 (!msr_info->host_initiated &&
3853 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3855 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
3856 (data & MSR_IA32_BNDCFGS_RSVD))
3858 vmcs_write64(GUEST_BNDCFGS, data);
3860 case MSR_IA32_SPEC_CTRL:
3861 if (!msr_info->host_initiated &&
3862 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3865 /* The STIBP bit doesn't fault even if it's not advertised */
3866 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
3869 vmx->spec_ctrl = data;
3876 * When it's written (to non-zero) for the first time, pass
3880 * The handling of the MSR bitmap for L2 guests is done in
3881 * nested_vmx_merge_msr_bitmap. We should not touch the
3882 * vmcs02.msr_bitmap here since it gets completely overwritten
3883 * in the merging. We update the vmcs01 here for L1 as well
3884 * since it will end up touching the MSR anyway now.
3886 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
3890 case MSR_IA32_PRED_CMD:
3891 if (!msr_info->host_initiated &&
3892 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3895 if (data & ~PRED_CMD_IBPB)
3901 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3905 * When it's written (to non-zero) for the first time, pass
3909 * The handling of the MSR bitmap for L2 guests is done in
3910 * nested_vmx_merge_msr_bitmap. We should not touch the
3911 * vmcs02.msr_bitmap here since it gets completely overwritten
3914 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
3917 case MSR_IA32_ARCH_CAPABILITIES:
3918 if (!msr_info->host_initiated)
3920 vmx->arch_capabilities = data;
3922 case MSR_IA32_CR_PAT:
3923 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3924 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3926 vmcs_write64(GUEST_IA32_PAT, data);
3927 vcpu->arch.pat = data;
3930 ret = kvm_set_msr_common(vcpu, msr_info);
3932 case MSR_IA32_TSC_ADJUST:
3933 ret = kvm_set_msr_common(vcpu, msr_info);
3935 case MSR_IA32_MCG_EXT_CTL:
3936 if ((!msr_info->host_initiated &&
3937 !(to_vmx(vcpu)->msr_ia32_feature_control &
3938 FEATURE_CONTROL_LMCE)) ||
3939 (data & ~MCG_EXT_CTL_LMCE_EN))
3941 vcpu->arch.mcg_ext_ctl = data;
3943 case MSR_IA32_FEATURE_CONTROL:
3944 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3945 (to_vmx(vcpu)->msr_ia32_feature_control &
3946 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3948 vmx->msr_ia32_feature_control = data;
3949 if (msr_info->host_initiated && data == 0)
3950 vmx_leave_nested(vcpu);
3952 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3953 if (!msr_info->host_initiated)
3954 return 1; /* they are read-only */
3955 if (!nested_vmx_allowed(vcpu))
3957 return vmx_set_vmx_msr(vcpu, msr_index, data);
3959 if (!vmx_xsaves_supported())
3962 * The only supported bit as of Skylake is bit 8, but
3963 * it is not supported on KVM.
3967 vcpu->arch.ia32_xss = data;
3968 if (vcpu->arch.ia32_xss != host_xss)
3969 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3970 vcpu->arch.ia32_xss, host_xss);
3972 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3975 if (!msr_info->host_initiated &&
3976 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3978 /* Check reserved bit, higher 32 bits should be zero */
3979 if ((data >> 32) != 0)
3981 /* Otherwise falls through */
3983 msr = find_msr_entry(vmx, msr_index);
3985 u64 old_msr_data = msr->data;
3987 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3989 ret = kvm_set_shared_msr(msr->index, msr->data,
3993 msr->data = old_msr_data;
3997 ret = kvm_set_msr_common(vcpu, msr_info);
4003 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
4005 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
4008 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
4011 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
4013 case VCPU_EXREG_PDPTR:
4015 ept_save_pdptrs(vcpu);
4022 static __init int cpu_has_kvm_support(void)
4024 return cpu_has_vmx();
4027 static __init int vmx_disabled_by_bios(void)
4031 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
4032 if (msr & FEATURE_CONTROL_LOCKED) {
4033 /* launched w/ TXT and VMX disabled */
4034 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4037 /* launched w/o TXT and VMX only enabled w/ TXT */
4038 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4039 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4040 && !tboot_enabled()) {
4041 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
4042 "activate TXT before enabling KVM\n");
4045 /* launched w/o TXT and VMX disabled */
4046 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4047 && !tboot_enabled())
4054 static void kvm_cpu_vmxon(u64 addr)
4056 cr4_set_bits(X86_CR4_VMXE);
4057 intel_pt_handle_vmx(1);
4059 asm volatile (ASM_VMX_VMXON_RAX
4060 : : "a"(&addr), "m"(addr)
4064 static int hardware_enable(void)
4066 int cpu = raw_smp_processor_id();
4067 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
4070 if (cr4_read_shadow() & X86_CR4_VMXE)
4074 * This can happen if we hot-added a CPU but failed to allocate
4075 * VP assist page for it.
4077 if (static_branch_unlikely(&enable_evmcs) &&
4078 !hv_get_vp_assist_page(cpu))
4081 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
4082 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
4083 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
4086 * Now we can enable the vmclear operation in kdump
4087 * since the loaded_vmcss_on_cpu list on this cpu
4088 * has been initialized.
4090 * Though the cpu is not in VMX operation now, there
4091 * is no problem to enable the vmclear operation
4092 * for the loaded_vmcss_on_cpu list is empty!
4094 crash_enable_local_vmclear(cpu);
4096 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
4098 test_bits = FEATURE_CONTROL_LOCKED;
4099 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
4100 if (tboot_enabled())
4101 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
4103 if ((old & test_bits) != test_bits) {
4104 /* enable and lock */
4105 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
4107 kvm_cpu_vmxon(phys_addr);
4114 static void vmclear_local_loaded_vmcss(void)
4116 int cpu = raw_smp_processor_id();
4117 struct loaded_vmcs *v, *n;
4119 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
4120 loaded_vmcss_on_cpu_link)
4121 __loaded_vmcs_clear(v);
4125 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
4128 static void kvm_cpu_vmxoff(void)
4130 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
4132 intel_pt_handle_vmx(0);
4133 cr4_clear_bits(X86_CR4_VMXE);
4136 static void hardware_disable(void)
4138 vmclear_local_loaded_vmcss();
4142 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
4143 u32 msr, u32 *result)
4145 u32 vmx_msr_low, vmx_msr_high;
4146 u32 ctl = ctl_min | ctl_opt;
4148 rdmsr(msr, vmx_msr_low, vmx_msr_high);
4150 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
4151 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
4153 /* Ensure minimum (required) set of control bits are supported. */
4161 static __init bool allow_1_setting(u32 msr, u32 ctl)
4163 u32 vmx_msr_low, vmx_msr_high;
4165 rdmsr(msr, vmx_msr_low, vmx_msr_high);
4166 return vmx_msr_high & ctl;
4169 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
4171 u32 vmx_msr_low, vmx_msr_high;
4172 u32 min, opt, min2, opt2;
4173 u32 _pin_based_exec_control = 0;
4174 u32 _cpu_based_exec_control = 0;
4175 u32 _cpu_based_2nd_exec_control = 0;
4176 u32 _vmexit_control = 0;
4177 u32 _vmentry_control = 0;
4179 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
4180 min = CPU_BASED_HLT_EXITING |
4181 #ifdef CONFIG_X86_64
4182 CPU_BASED_CR8_LOAD_EXITING |
4183 CPU_BASED_CR8_STORE_EXITING |
4185 CPU_BASED_CR3_LOAD_EXITING |
4186 CPU_BASED_CR3_STORE_EXITING |
4187 CPU_BASED_UNCOND_IO_EXITING |
4188 CPU_BASED_MOV_DR_EXITING |
4189 CPU_BASED_USE_TSC_OFFSETING |
4190 CPU_BASED_MWAIT_EXITING |
4191 CPU_BASED_MONITOR_EXITING |
4192 CPU_BASED_INVLPG_EXITING |
4193 CPU_BASED_RDPMC_EXITING;
4195 opt = CPU_BASED_TPR_SHADOW |
4196 CPU_BASED_USE_MSR_BITMAPS |
4197 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
4198 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
4199 &_cpu_based_exec_control) < 0)
4201 #ifdef CONFIG_X86_64
4202 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4203 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
4204 ~CPU_BASED_CR8_STORE_EXITING;
4206 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
4208 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4209 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4210 SECONDARY_EXEC_WBINVD_EXITING |
4211 SECONDARY_EXEC_ENABLE_VPID |
4212 SECONDARY_EXEC_ENABLE_EPT |
4213 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4214 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
4215 SECONDARY_EXEC_DESC |
4216 SECONDARY_EXEC_RDTSCP |
4217 SECONDARY_EXEC_ENABLE_INVPCID |
4218 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4219 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4220 SECONDARY_EXEC_SHADOW_VMCS |
4221 SECONDARY_EXEC_XSAVES |
4222 SECONDARY_EXEC_RDSEED_EXITING |
4223 SECONDARY_EXEC_RDRAND_EXITING |
4224 SECONDARY_EXEC_ENABLE_PML |
4225 SECONDARY_EXEC_TSC_SCALING |
4226 SECONDARY_EXEC_ENABLE_VMFUNC;
4227 if (adjust_vmx_controls(min2, opt2,
4228 MSR_IA32_VMX_PROCBASED_CTLS2,
4229 &_cpu_based_2nd_exec_control) < 0)
4232 #ifndef CONFIG_X86_64
4233 if (!(_cpu_based_2nd_exec_control &
4234 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
4235 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
4238 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4239 _cpu_based_2nd_exec_control &= ~(
4240 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4241 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4242 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4244 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
4245 &vmx_capability.ept, &vmx_capability.vpid);
4247 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
4248 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
4250 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
4251 CPU_BASED_CR3_STORE_EXITING |
4252 CPU_BASED_INVLPG_EXITING);
4253 } else if (vmx_capability.ept) {
4254 vmx_capability.ept = 0;
4255 pr_warn_once("EPT CAP should not exist if not support "
4256 "1-setting enable EPT VM-execution control\n");
4258 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
4259 vmx_capability.vpid) {
4260 vmx_capability.vpid = 0;
4261 pr_warn_once("VPID CAP should not exist if not support "
4262 "1-setting enable VPID VM-execution control\n");
4265 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
4266 #ifdef CONFIG_X86_64
4267 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
4269 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
4270 VM_EXIT_CLEAR_BNDCFGS;
4271 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
4272 &_vmexit_control) < 0)
4275 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
4276 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
4277 PIN_BASED_VMX_PREEMPTION_TIMER;
4278 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
4279 &_pin_based_exec_control) < 0)
4282 if (cpu_has_broken_vmx_preemption_timer())
4283 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4284 if (!(_cpu_based_2nd_exec_control &
4285 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
4286 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
4288 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
4289 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
4290 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
4291 &_vmentry_control) < 0)
4294 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
4296 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
4297 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
4300 #ifdef CONFIG_X86_64
4301 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
4302 if (vmx_msr_high & (1u<<16))
4306 /* Require Write-Back (WB) memory type for VMCS accesses. */
4307 if (((vmx_msr_high >> 18) & 15) != 6)
4310 vmcs_conf->size = vmx_msr_high & 0x1fff;
4311 vmcs_conf->order = get_order(vmcs_conf->size);
4312 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
4314 /* KVM supports Enlightened VMCS v1 only */
4315 if (static_branch_unlikely(&enable_evmcs))
4316 vmcs_conf->revision_id = KVM_EVMCS_VERSION;
4318 vmcs_conf->revision_id = vmx_msr_low;
4320 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
4321 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
4322 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
4323 vmcs_conf->vmexit_ctrl = _vmexit_control;
4324 vmcs_conf->vmentry_ctrl = _vmentry_control;
4326 if (static_branch_unlikely(&enable_evmcs))
4327 evmcs_sanitize_exec_ctrls(vmcs_conf);
4329 cpu_has_load_ia32_efer =
4330 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4331 VM_ENTRY_LOAD_IA32_EFER)
4332 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4333 VM_EXIT_LOAD_IA32_EFER);
4335 cpu_has_load_perf_global_ctrl =
4336 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4337 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
4338 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4339 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
4342 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
4343 * but due to errata below it can't be used. Workaround is to use
4344 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
4346 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
4351 * BC86,AAY89,BD102 (model 44)
4355 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
4356 switch (boot_cpu_data.x86_model) {
4362 cpu_has_load_perf_global_ctrl = false;
4363 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
4364 "does not work properly. Using workaround\n");
4371 if (boot_cpu_has(X86_FEATURE_XSAVES))
4372 rdmsrl(MSR_IA32_XSS, host_xss);
4377 static struct vmcs *alloc_vmcs_cpu(int cpu)
4379 int node = cpu_to_node(cpu);
4383 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
4386 vmcs = page_address(pages);
4387 memset(vmcs, 0, vmcs_config.size);
4388 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
4392 static void free_vmcs(struct vmcs *vmcs)
4394 free_pages((unsigned long)vmcs, vmcs_config.order);
4398 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
4400 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4402 if (!loaded_vmcs->vmcs)
4404 loaded_vmcs_clear(loaded_vmcs);
4405 free_vmcs(loaded_vmcs->vmcs);
4406 loaded_vmcs->vmcs = NULL;
4407 if (loaded_vmcs->msr_bitmap)
4408 free_page((unsigned long)loaded_vmcs->msr_bitmap);
4409 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
4412 static struct vmcs *alloc_vmcs(void)
4414 return alloc_vmcs_cpu(raw_smp_processor_id());
4417 static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4419 loaded_vmcs->vmcs = alloc_vmcs();
4420 if (!loaded_vmcs->vmcs)
4423 loaded_vmcs->shadow_vmcs = NULL;
4424 loaded_vmcs_init(loaded_vmcs);
4426 if (cpu_has_vmx_msr_bitmap()) {
4427 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
4428 if (!loaded_vmcs->msr_bitmap)
4430 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
4432 #if IS_ENABLED(CONFIG_HYPERV)
4433 if (static_branch_unlikely(&enable_evmcs) &&
4434 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
4435 struct hv_enlightened_vmcs *evmcs =
4436 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
4438 evmcs->hv_enlightenments_control.msr_bitmap = 1;
4446 free_loaded_vmcs(loaded_vmcs);
4450 static void free_kvm_area(void)
4454 for_each_possible_cpu(cpu) {
4455 free_vmcs(per_cpu(vmxarea, cpu));
4456 per_cpu(vmxarea, cpu) = NULL;
4460 enum vmcs_field_width {
4461 VMCS_FIELD_WIDTH_U16 = 0,
4462 VMCS_FIELD_WIDTH_U64 = 1,
4463 VMCS_FIELD_WIDTH_U32 = 2,
4464 VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
4467 static inline int vmcs_field_width(unsigned long field)
4469 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
4470 return VMCS_FIELD_WIDTH_U32;
4471 return (field >> 13) & 0x3 ;
4474 static inline int vmcs_field_readonly(unsigned long field)
4476 return (((field >> 10) & 0x3) == 1);
4479 static void init_vmcs_shadow_fields(void)
4483 for (i = j = 0; i < max_shadow_read_only_fields; i++) {
4484 u16 field = shadow_read_only_fields[i];
4485 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4486 (i + 1 == max_shadow_read_only_fields ||
4487 shadow_read_only_fields[i + 1] != field + 1))
4488 pr_err("Missing field from shadow_read_only_field %x\n",
4491 clear_bit(field, vmx_vmread_bitmap);
4492 #ifdef CONFIG_X86_64
4497 shadow_read_only_fields[j] = field;
4500 max_shadow_read_only_fields = j;
4502 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
4503 u16 field = shadow_read_write_fields[i];
4504 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4505 (i + 1 == max_shadow_read_write_fields ||
4506 shadow_read_write_fields[i + 1] != field + 1))
4507 pr_err("Missing field from shadow_read_write_field %x\n",
4511 * PML and the preemption timer can be emulated, but the
4512 * processor cannot vmwrite to fields that don't exist
4516 case GUEST_PML_INDEX:
4517 if (!cpu_has_vmx_pml())
4520 case VMX_PREEMPTION_TIMER_VALUE:
4521 if (!cpu_has_vmx_preemption_timer())
4524 case GUEST_INTR_STATUS:
4525 if (!cpu_has_vmx_apicv())
4532 clear_bit(field, vmx_vmwrite_bitmap);
4533 clear_bit(field, vmx_vmread_bitmap);
4534 #ifdef CONFIG_X86_64
4539 shadow_read_write_fields[j] = field;
4542 max_shadow_read_write_fields = j;
4545 static __init int alloc_kvm_area(void)
4549 for_each_possible_cpu(cpu) {
4552 vmcs = alloc_vmcs_cpu(cpu);
4558 per_cpu(vmxarea, cpu) = vmcs;
4563 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
4564 struct kvm_segment *save)
4566 if (!emulate_invalid_guest_state) {
4568 * CS and SS RPL should be equal during guest entry according
4569 * to VMX spec, but in reality it is not always so. Since vcpu
4570 * is in the middle of the transition from real mode to
4571 * protected mode it is safe to assume that RPL 0 is a good
4574 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4575 save->selector &= ~SEGMENT_RPL_MASK;
4576 save->dpl = save->selector & SEGMENT_RPL_MASK;
4579 vmx_set_segment(vcpu, save, seg);
4582 static void enter_pmode(struct kvm_vcpu *vcpu)
4584 unsigned long flags;
4585 struct vcpu_vmx *vmx = to_vmx(vcpu);
4588 * Update real mode segment cache. It may be not up-to-date if sement
4589 * register was written while vcpu was in a guest mode.
4591 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4592 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4593 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4594 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4595 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4596 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4598 vmx->rmode.vm86_active = 0;
4600 vmx_segment_cache_clear(vmx);
4602 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4604 flags = vmcs_readl(GUEST_RFLAGS);
4605 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
4606 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
4607 vmcs_writel(GUEST_RFLAGS, flags);
4609 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
4610 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4612 update_exception_bitmap(vcpu);
4614 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4615 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4616 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4617 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4618 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4619 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4622 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4624 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4625 struct kvm_segment var = *save;
4628 if (seg == VCPU_SREG_CS)
4631 if (!emulate_invalid_guest_state) {
4632 var.selector = var.base >> 4;
4633 var.base = var.base & 0xffff0;
4643 if (save->base & 0xf)
4644 printk_once(KERN_WARNING "kvm: segment base is not "
4645 "paragraph aligned when entering "
4646 "protected mode (seg=%d)", seg);
4649 vmcs_write16(sf->selector, var.selector);
4650 vmcs_writel(sf->base, var.base);
4651 vmcs_write32(sf->limit, var.limit);
4652 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
4655 static void enter_rmode(struct kvm_vcpu *vcpu)
4657 unsigned long flags;
4658 struct vcpu_vmx *vmx = to_vmx(vcpu);
4659 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
4661 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4662 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4663 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4664 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4665 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4666 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4667 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4669 vmx->rmode.vm86_active = 1;
4672 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4673 * vcpu. Warn the user that an update is overdue.
4675 if (!kvm_vmx->tss_addr)
4676 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4677 "called before entering vcpu\n");
4679 vmx_segment_cache_clear(vmx);
4681 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
4682 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4683 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4685 flags = vmcs_readl(GUEST_RFLAGS);
4686 vmx->rmode.save_rflags = flags;
4688 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4690 vmcs_writel(GUEST_RFLAGS, flags);
4691 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4692 update_exception_bitmap(vcpu);
4694 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4695 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4696 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4697 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4698 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4699 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4701 kvm_mmu_reset_context(vcpu);
4704 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4706 struct vcpu_vmx *vmx = to_vmx(vcpu);
4707 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4713 * Force kernel_gs_base reloading before EFER changes, as control
4714 * of this msr depends on is_long_mode().
4716 vmx_load_host_state(to_vmx(vcpu));
4717 vcpu->arch.efer = efer;
4718 if (efer & EFER_LMA) {
4719 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4722 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4724 msr->data = efer & ~EFER_LME;
4729 #ifdef CONFIG_X86_64
4731 static void enter_lmode(struct kvm_vcpu *vcpu)
4735 vmx_segment_cache_clear(to_vmx(vcpu));
4737 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4738 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4739 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4741 vmcs_write32(GUEST_TR_AR_BYTES,
4742 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4743 | VMX_AR_TYPE_BUSY_64_TSS);
4745 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4748 static void exit_lmode(struct kvm_vcpu *vcpu)
4750 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4751 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4756 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
4757 bool invalidate_gpa)
4759 if (enable_ept && (invalidate_gpa || !enable_vpid)) {
4760 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4762 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4764 vpid_sync_context(vpid);
4768 static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
4770 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
4773 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4775 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4777 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4778 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4781 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4783 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
4784 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4785 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4788 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4790 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4792 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4793 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4796 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4798 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4800 if (!test_bit(VCPU_EXREG_PDPTR,
4801 (unsigned long *)&vcpu->arch.regs_dirty))
4804 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4805 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4806 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4807 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4808 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4812 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4814 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4816 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4817 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4818 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4819 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4820 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4823 __set_bit(VCPU_EXREG_PDPTR,
4824 (unsigned long *)&vcpu->arch.regs_avail);
4825 __set_bit(VCPU_EXREG_PDPTR,
4826 (unsigned long *)&vcpu->arch.regs_dirty);
4829 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4831 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
4832 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
4833 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4835 if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
4836 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4837 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4838 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4840 return fixed_bits_valid(val, fixed0, fixed1);
4843 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4845 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
4846 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
4848 return fixed_bits_valid(val, fixed0, fixed1);
4851 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4853 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0;
4854 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1;
4856 return fixed_bits_valid(val, fixed0, fixed1);
4859 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4860 #define nested_guest_cr4_valid nested_cr4_valid
4861 #define nested_host_cr4_valid nested_cr4_valid
4863 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4865 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4867 struct kvm_vcpu *vcpu)
4869 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4870 vmx_decache_cr3(vcpu);
4871 if (!(cr0 & X86_CR0_PG)) {
4872 /* From paging/starting to nonpaging */
4873 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4874 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4875 (CPU_BASED_CR3_LOAD_EXITING |
4876 CPU_BASED_CR3_STORE_EXITING));
4877 vcpu->arch.cr0 = cr0;
4878 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4879 } else if (!is_paging(vcpu)) {
4880 /* From nonpaging to paging */
4881 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4882 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4883 ~(CPU_BASED_CR3_LOAD_EXITING |
4884 CPU_BASED_CR3_STORE_EXITING));
4885 vcpu->arch.cr0 = cr0;
4886 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4889 if (!(cr0 & X86_CR0_WP))
4890 *hw_cr0 &= ~X86_CR0_WP;
4893 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4895 struct vcpu_vmx *vmx = to_vmx(vcpu);
4896 unsigned long hw_cr0;
4898 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4899 if (enable_unrestricted_guest)
4900 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4902 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4904 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4907 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4911 #ifdef CONFIG_X86_64
4912 if (vcpu->arch.efer & EFER_LME) {
4913 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4915 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4920 if (enable_ept && !enable_unrestricted_guest)
4921 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4923 vmcs_writel(CR0_READ_SHADOW, cr0);
4924 vmcs_writel(GUEST_CR0, hw_cr0);
4925 vcpu->arch.cr0 = cr0;
4927 /* depends on vcpu->arch.cr0 to be set to a new value */
4928 vmx->emulation_required = emulation_required(vcpu);
4931 static int get_ept_level(struct kvm_vcpu *vcpu)
4933 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
4938 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4940 u64 eptp = VMX_EPTP_MT_WB;
4942 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
4944 if (enable_ept_ad_bits &&
4945 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4946 eptp |= VMX_EPTP_AD_ENABLE_BIT;
4947 eptp |= (root_hpa & PAGE_MASK);
4952 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4954 unsigned long guest_cr3;
4959 eptp = construct_eptp(vcpu, cr3);
4960 vmcs_write64(EPT_POINTER, eptp);
4961 if (enable_unrestricted_guest || is_paging(vcpu) ||
4962 is_guest_mode(vcpu))
4963 guest_cr3 = kvm_read_cr3(vcpu);
4965 guest_cr3 = to_kvm_vmx(vcpu->kvm)->ept_identity_map_addr;
4966 ept_load_pdptrs(vcpu);
4969 vmx_flush_tlb(vcpu, true);
4970 vmcs_writel(GUEST_CR3, guest_cr3);
4973 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4976 * Pass through host's Machine Check Enable value to hw_cr4, which
4977 * is in force while we are in guest mode. Do not let guests control
4978 * this bit, even if host CR4.MCE == 0.
4980 unsigned long hw_cr4;
4982 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
4983 if (enable_unrestricted_guest)
4984 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
4985 else if (to_vmx(vcpu)->rmode.vm86_active)
4986 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
4988 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
4990 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
4991 if (cr4 & X86_CR4_UMIP) {
4992 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
4993 SECONDARY_EXEC_DESC);
4994 hw_cr4 &= ~X86_CR4_UMIP;
4995 } else if (!is_guest_mode(vcpu) ||
4996 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
4997 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
4998 SECONDARY_EXEC_DESC);
5001 if (cr4 & X86_CR4_VMXE) {
5003 * To use VMXON (and later other VMX instructions), a guest
5004 * must first be able to turn on cr4.VMXE (see handle_vmon()).
5005 * So basically the check on whether to allow nested VMX
5008 if (!nested_vmx_allowed(vcpu))
5012 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5015 vcpu->arch.cr4 = cr4;
5017 if (!enable_unrestricted_guest) {
5019 if (!is_paging(vcpu)) {
5020 hw_cr4 &= ~X86_CR4_PAE;
5021 hw_cr4 |= X86_CR4_PSE;
5022 } else if (!(cr4 & X86_CR4_PAE)) {
5023 hw_cr4 &= ~X86_CR4_PAE;
5028 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
5029 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
5030 * to be manually disabled when guest switches to non-paging
5033 * If !enable_unrestricted_guest, the CPU is always running
5034 * with CR0.PG=1 and CR4 needs to be modified.
5035 * If enable_unrestricted_guest, the CPU automatically
5036 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
5038 if (!is_paging(vcpu))
5039 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
5042 vmcs_writel(CR4_READ_SHADOW, cr4);
5043 vmcs_writel(GUEST_CR4, hw_cr4);
5047 static void vmx_get_segment(struct kvm_vcpu *vcpu,
5048 struct kvm_segment *var, int seg)
5050 struct vcpu_vmx *vmx = to_vmx(vcpu);
5053 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5054 *var = vmx->rmode.segs[seg];
5055 if (seg == VCPU_SREG_TR
5056 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
5058 var->base = vmx_read_guest_seg_base(vmx, seg);
5059 var->selector = vmx_read_guest_seg_selector(vmx, seg);
5062 var->base = vmx_read_guest_seg_base(vmx, seg);
5063 var->limit = vmx_read_guest_seg_limit(vmx, seg);
5064 var->selector = vmx_read_guest_seg_selector(vmx, seg);
5065 ar = vmx_read_guest_seg_ar(vmx, seg);
5066 var->unusable = (ar >> 16) & 1;
5067 var->type = ar & 15;
5068 var->s = (ar >> 4) & 1;
5069 var->dpl = (ar >> 5) & 3;
5071 * Some userspaces do not preserve unusable property. Since usable
5072 * segment has to be present according to VMX spec we can use present
5073 * property to amend userspace bug by making unusable segment always
5074 * nonpresent. vmx_segment_access_rights() already marks nonpresent
5075 * segment as unusable.
5077 var->present = !var->unusable;
5078 var->avl = (ar >> 12) & 1;
5079 var->l = (ar >> 13) & 1;
5080 var->db = (ar >> 14) & 1;
5081 var->g = (ar >> 15) & 1;
5084 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
5086 struct kvm_segment s;
5088 if (to_vmx(vcpu)->rmode.vm86_active) {
5089 vmx_get_segment(vcpu, &s, seg);
5092 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
5095 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
5097 struct vcpu_vmx *vmx = to_vmx(vcpu);
5099 if (unlikely(vmx->rmode.vm86_active))
5102 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
5103 return VMX_AR_DPL(ar);
5107 static u32 vmx_segment_access_rights(struct kvm_segment *var)
5111 if (var->unusable || !var->present)
5114 ar = var->type & 15;
5115 ar |= (var->s & 1) << 4;
5116 ar |= (var->dpl & 3) << 5;
5117 ar |= (var->present & 1) << 7;
5118 ar |= (var->avl & 1) << 12;
5119 ar |= (var->l & 1) << 13;
5120 ar |= (var->db & 1) << 14;
5121 ar |= (var->g & 1) << 15;
5127 static void vmx_set_segment(struct kvm_vcpu *vcpu,
5128 struct kvm_segment *var, int seg)
5130 struct vcpu_vmx *vmx = to_vmx(vcpu);
5131 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5133 vmx_segment_cache_clear(vmx);
5135 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5136 vmx->rmode.segs[seg] = *var;
5137 if (seg == VCPU_SREG_TR)
5138 vmcs_write16(sf->selector, var->selector);
5140 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
5144 vmcs_writel(sf->base, var->base);
5145 vmcs_write32(sf->limit, var->limit);
5146 vmcs_write16(sf->selector, var->selector);
5149 * Fix the "Accessed" bit in AR field of segment registers for older
5151 * IA32 arch specifies that at the time of processor reset the
5152 * "Accessed" bit in the AR field of segment registers is 1. And qemu
5153 * is setting it to 0 in the userland code. This causes invalid guest
5154 * state vmexit when "unrestricted guest" mode is turned on.
5155 * Fix for this setup issue in cpu_reset is being pushed in the qemu
5156 * tree. Newer qemu binaries with that qemu fix would not need this
5159 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
5160 var->type |= 0x1; /* Accessed */
5162 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
5165 vmx->emulation_required = emulation_required(vcpu);
5168 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5170 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
5172 *db = (ar >> 14) & 1;
5173 *l = (ar >> 13) & 1;
5176 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5178 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
5179 dt->address = vmcs_readl(GUEST_IDTR_BASE);
5182 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5184 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
5185 vmcs_writel(GUEST_IDTR_BASE, dt->address);
5188 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5190 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
5191 dt->address = vmcs_readl(GUEST_GDTR_BASE);
5194 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5196 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
5197 vmcs_writel(GUEST_GDTR_BASE, dt->address);
5200 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
5202 struct kvm_segment var;
5205 vmx_get_segment(vcpu, &var, seg);
5207 if (seg == VCPU_SREG_CS)
5209 ar = vmx_segment_access_rights(&var);
5211 if (var.base != (var.selector << 4))
5213 if (var.limit != 0xffff)
5221 static bool code_segment_valid(struct kvm_vcpu *vcpu)
5223 struct kvm_segment cs;
5224 unsigned int cs_rpl;
5226 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5227 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
5231 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
5235 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
5236 if (cs.dpl > cs_rpl)
5239 if (cs.dpl != cs_rpl)
5245 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
5249 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
5251 struct kvm_segment ss;
5252 unsigned int ss_rpl;
5254 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5255 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
5259 if (ss.type != 3 && ss.type != 7)
5263 if (ss.dpl != ss_rpl) /* DPL != RPL */
5271 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
5273 struct kvm_segment var;
5276 vmx_get_segment(vcpu, &var, seg);
5277 rpl = var.selector & SEGMENT_RPL_MASK;
5285 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
5286 if (var.dpl < rpl) /* DPL < RPL */
5290 /* TODO: Add other members to kvm_segment_field to allow checking for other access
5296 static bool tr_valid(struct kvm_vcpu *vcpu)
5298 struct kvm_segment tr;
5300 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
5304 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
5306 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
5314 static bool ldtr_valid(struct kvm_vcpu *vcpu)
5316 struct kvm_segment ldtr;
5318 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
5322 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
5332 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
5334 struct kvm_segment cs, ss;
5336 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5337 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5339 return ((cs.selector & SEGMENT_RPL_MASK) ==
5340 (ss.selector & SEGMENT_RPL_MASK));
5344 * Check if guest state is valid. Returns true if valid, false if
5346 * We assume that registers are always usable
5348 static bool guest_state_valid(struct kvm_vcpu *vcpu)
5350 if (enable_unrestricted_guest)
5353 /* real mode guest state checks */
5354 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5355 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
5357 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
5359 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
5361 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
5363 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
5365 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
5368 /* protected mode guest state checks */
5369 if (!cs_ss_rpl_check(vcpu))
5371 if (!code_segment_valid(vcpu))
5373 if (!stack_segment_valid(vcpu))
5375 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
5377 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
5379 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
5381 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
5383 if (!tr_valid(vcpu))
5385 if (!ldtr_valid(vcpu))
5389 * - Add checks on RIP
5390 * - Add checks on RFLAGS
5396 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
5398 return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
5401 static int init_rmode_tss(struct kvm *kvm)
5407 idx = srcu_read_lock(&kvm->srcu);
5408 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
5409 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5412 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
5413 r = kvm_write_guest_page(kvm, fn++, &data,
5414 TSS_IOPB_BASE_OFFSET, sizeof(u16));
5417 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
5420 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5424 r = kvm_write_guest_page(kvm, fn, &data,
5425 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
5428 srcu_read_unlock(&kvm->srcu, idx);
5432 static int init_rmode_identity_map(struct kvm *kvm)
5434 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
5436 kvm_pfn_t identity_map_pfn;
5439 /* Protect kvm_vmx->ept_identity_pagetable_done. */
5440 mutex_lock(&kvm->slots_lock);
5442 if (likely(kvm_vmx->ept_identity_pagetable_done))
5445 if (!kvm_vmx->ept_identity_map_addr)
5446 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
5447 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
5449 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
5450 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
5454 idx = srcu_read_lock(&kvm->srcu);
5455 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
5458 /* Set up identity-mapping pagetable for EPT in real mode */
5459 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
5460 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
5461 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
5462 r = kvm_write_guest_page(kvm, identity_map_pfn,
5463 &tmp, i * sizeof(tmp), sizeof(tmp));
5467 kvm_vmx->ept_identity_pagetable_done = true;
5470 srcu_read_unlock(&kvm->srcu, idx);
5473 mutex_unlock(&kvm->slots_lock);
5477 static void seg_setup(int seg)
5479 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5482 vmcs_write16(sf->selector, 0);
5483 vmcs_writel(sf->base, 0);
5484 vmcs_write32(sf->limit, 0xffff);
5486 if (seg == VCPU_SREG_CS)
5487 ar |= 0x08; /* code segment */
5489 vmcs_write32(sf->ar_bytes, ar);
5492 static int alloc_apic_access_page(struct kvm *kvm)
5497 mutex_lock(&kvm->slots_lock);
5498 if (kvm->arch.apic_access_page_done)
5500 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
5501 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
5505 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
5506 if (is_error_page(page)) {
5512 * Do not pin the page in memory, so that memory hot-unplug
5513 * is able to migrate it.
5516 kvm->arch.apic_access_page_done = true;
5518 mutex_unlock(&kvm->slots_lock);
5522 static int allocate_vpid(void)
5528 spin_lock(&vmx_vpid_lock);
5529 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
5530 if (vpid < VMX_NR_VPIDS)
5531 __set_bit(vpid, vmx_vpid_bitmap);
5534 spin_unlock(&vmx_vpid_lock);
5538 static void free_vpid(int vpid)
5540 if (!enable_vpid || vpid == 0)
5542 spin_lock(&vmx_vpid_lock);
5543 __clear_bit(vpid, vmx_vpid_bitmap);
5544 spin_unlock(&vmx_vpid_lock);
5547 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
5550 int f = sizeof(unsigned long);
5552 if (!cpu_has_vmx_msr_bitmap())
5555 if (static_branch_unlikely(&enable_evmcs))
5556 evmcs_touch_msr_bitmap();
5559 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5560 * have the write-low and read-high bitmap offsets the wrong way round.
5561 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5563 if (msr <= 0x1fff) {
5564 if (type & MSR_TYPE_R)
5566 __clear_bit(msr, msr_bitmap + 0x000 / f);
5568 if (type & MSR_TYPE_W)
5570 __clear_bit(msr, msr_bitmap + 0x800 / f);
5572 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5574 if (type & MSR_TYPE_R)
5576 __clear_bit(msr, msr_bitmap + 0x400 / f);
5578 if (type & MSR_TYPE_W)
5580 __clear_bit(msr, msr_bitmap + 0xc00 / f);
5585 static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
5588 int f = sizeof(unsigned long);
5590 if (!cpu_has_vmx_msr_bitmap())
5593 if (static_branch_unlikely(&enable_evmcs))
5594 evmcs_touch_msr_bitmap();
5597 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5598 * have the write-low and read-high bitmap offsets the wrong way round.
5599 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5601 if (msr <= 0x1fff) {
5602 if (type & MSR_TYPE_R)
5604 __set_bit(msr, msr_bitmap + 0x000 / f);
5606 if (type & MSR_TYPE_W)
5608 __set_bit(msr, msr_bitmap + 0x800 / f);
5610 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5612 if (type & MSR_TYPE_R)
5614 __set_bit(msr, msr_bitmap + 0x400 / f);
5616 if (type & MSR_TYPE_W)
5618 __set_bit(msr, msr_bitmap + 0xc00 / f);
5623 static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
5624 u32 msr, int type, bool value)
5627 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
5629 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
5633 * If a msr is allowed by L0, we should check whether it is allowed by L1.
5634 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
5636 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
5637 unsigned long *msr_bitmap_nested,
5640 int f = sizeof(unsigned long);
5643 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5644 * have the write-low and read-high bitmap offsets the wrong way round.
5645 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5647 if (msr <= 0x1fff) {
5648 if (type & MSR_TYPE_R &&
5649 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
5651 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
5653 if (type & MSR_TYPE_W &&
5654 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
5656 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
5658 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5660 if (type & MSR_TYPE_R &&
5661 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
5663 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
5665 if (type & MSR_TYPE_W &&
5666 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
5668 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
5673 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5677 if (cpu_has_secondary_exec_ctrls() &&
5678 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
5679 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
5680 mode |= MSR_BITMAP_MODE_X2APIC;
5681 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
5682 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
5685 if (is_long_mode(vcpu))
5686 mode |= MSR_BITMAP_MODE_LM;
5691 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
5693 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
5698 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
5699 unsigned word = msr / BITS_PER_LONG;
5700 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
5701 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
5704 if (mode & MSR_BITMAP_MODE_X2APIC) {
5706 * TPR reads and writes can be virtualized even if virtual interrupt
5707 * delivery is not in use.
5709 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
5710 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
5711 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
5712 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
5713 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
5718 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
5720 struct vcpu_vmx *vmx = to_vmx(vcpu);
5721 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
5722 u8 mode = vmx_msr_bitmap_mode(vcpu);
5723 u8 changed = mode ^ vmx->msr_bitmap_mode;
5728 vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW,
5729 !(mode & MSR_BITMAP_MODE_LM));
5731 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
5732 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
5734 vmx->msr_bitmap_mode = mode;
5737 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
5739 return enable_apicv;
5742 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5744 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5748 * Don't need to mark the APIC access page dirty; it is never
5749 * written to by the CPU during APIC virtualization.
5752 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5753 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5754 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5757 if (nested_cpu_has_posted_intr(vmcs12)) {
5758 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5759 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5764 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5766 struct vcpu_vmx *vmx = to_vmx(vcpu);
5771 if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5774 vmx->nested.pi_pending = false;
5775 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5778 max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5779 if (max_irr != 256) {
5780 vapic_page = kmap(vmx->nested.virtual_apic_page);
5781 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
5782 vapic_page, &max_irr);
5783 kunmap(vmx->nested.virtual_apic_page);
5785 status = vmcs_read16(GUEST_INTR_STATUS);
5786 if ((u8)max_irr > ((u8)status & 0xff)) {
5788 status |= (u8)max_irr;
5789 vmcs_write16(GUEST_INTR_STATUS, status);
5793 nested_mark_vmcs12_pages_dirty(vcpu);
5796 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5800 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5802 if (vcpu->mode == IN_GUEST_MODE) {
5804 * The vector of interrupt to be delivered to vcpu had
5805 * been set in PIR before this function.
5807 * Following cases will be reached in this block, and
5808 * we always send a notification event in all cases as
5811 * Case 1: vcpu keeps in non-root mode. Sending a
5812 * notification event posts the interrupt to vcpu.
5814 * Case 2: vcpu exits to root mode and is still
5815 * runnable. PIR will be synced to vIRR before the
5816 * next vcpu entry. Sending a notification event in
5817 * this case has no effect, as vcpu is not in root
5820 * Case 3: vcpu exits to root mode and is blocked.
5821 * vcpu_block() has already synced PIR to vIRR and
5822 * never blocks vcpu if vIRR is not cleared. Therefore,
5823 * a blocked vcpu here does not wait for any requested
5824 * interrupts in PIR, and sending a notification event
5825 * which has no effect is safe here.
5828 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5835 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5838 struct vcpu_vmx *vmx = to_vmx(vcpu);
5840 if (is_guest_mode(vcpu) &&
5841 vector == vmx->nested.posted_intr_nv) {
5843 * If a posted intr is not recognized by hardware,
5844 * we will accomplish it in the next vmentry.
5846 vmx->nested.pi_pending = true;
5847 kvm_make_request(KVM_REQ_EVENT, vcpu);
5848 /* the PIR and ON have been set by L1. */
5849 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
5850 kvm_vcpu_kick(vcpu);
5856 * Send interrupt to vcpu via posted interrupt way.
5857 * 1. If target vcpu is running(non-root mode), send posted interrupt
5858 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5859 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5860 * interrupt from PIR in next vmentry.
5862 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5864 struct vcpu_vmx *vmx = to_vmx(vcpu);
5867 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5871 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5874 /* If a previous notification has sent the IPI, nothing to do. */
5875 if (pi_test_and_set_on(&vmx->pi_desc))
5878 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5879 kvm_vcpu_kick(vcpu);
5883 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5884 * will not change in the lifetime of the guest.
5885 * Note that host-state that does change is set elsewhere. E.g., host-state
5886 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5888 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5893 unsigned long cr0, cr3, cr4;
5896 WARN_ON(cr0 & X86_CR0_TS);
5897 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
5900 * Save the most likely value for this task's CR3 in the VMCS.
5901 * We can't use __get_current_cr3_fast() because we're not atomic.
5904 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
5905 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5907 /* Save the most likely value for this task's CR4 in the VMCS. */
5908 cr4 = cr4_read_shadow();
5909 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5910 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5912 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
5913 #ifdef CONFIG_X86_64
5915 * Load null selectors, so we can avoid reloading them in
5916 * __vmx_load_host_state(), in case userspace uses the null selectors
5917 * too (the expected case).
5919 vmcs_write16(HOST_DS_SELECTOR, 0);
5920 vmcs_write16(HOST_ES_SELECTOR, 0);
5922 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5923 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5925 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5926 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5929 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
5930 vmx->host_idt_base = dt.address;
5932 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5934 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5935 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5936 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5937 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5939 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5940 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5941 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5945 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5947 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5949 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5950 if (is_guest_mode(&vmx->vcpu))
5951 vmx->vcpu.arch.cr4_guest_owned_bits &=
5952 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5953 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5956 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5958 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5960 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5961 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5964 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
5966 /* Enable the preemption timer dynamically */
5967 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5968 return pin_based_exec_ctrl;
5971 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5973 struct vcpu_vmx *vmx = to_vmx(vcpu);
5975 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5976 if (cpu_has_secondary_exec_ctrls()) {
5977 if (kvm_vcpu_apicv_active(vcpu))
5978 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5979 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5980 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5982 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5983 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5984 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5987 if (cpu_has_vmx_msr_bitmap())
5988 vmx_update_msr_bitmap(vcpu);
5991 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5993 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5995 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5996 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5998 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5999 exec_control &= ~CPU_BASED_TPR_SHADOW;
6000 #ifdef CONFIG_X86_64
6001 exec_control |= CPU_BASED_CR8_STORE_EXITING |
6002 CPU_BASED_CR8_LOAD_EXITING;
6006 exec_control |= CPU_BASED_CR3_STORE_EXITING |
6007 CPU_BASED_CR3_LOAD_EXITING |
6008 CPU_BASED_INVLPG_EXITING;
6009 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
6010 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
6011 CPU_BASED_MONITOR_EXITING);
6012 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
6013 exec_control &= ~CPU_BASED_HLT_EXITING;
6014 return exec_control;
6017 static bool vmx_rdrand_supported(void)
6019 return vmcs_config.cpu_based_2nd_exec_ctrl &
6020 SECONDARY_EXEC_RDRAND_EXITING;
6023 static bool vmx_rdseed_supported(void)
6025 return vmcs_config.cpu_based_2nd_exec_ctrl &
6026 SECONDARY_EXEC_RDSEED_EXITING;
6029 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
6031 struct kvm_vcpu *vcpu = &vmx->vcpu;
6033 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
6035 if (!cpu_need_virtualize_apic_accesses(vcpu))
6036 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6038 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
6040 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
6041 enable_unrestricted_guest = 0;
6042 /* Enable INVPCID for non-ept guests may cause performance regression. */
6043 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6045 if (!enable_unrestricted_guest)
6046 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
6047 if (kvm_pause_in_guest(vmx->vcpu.kvm))
6048 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
6049 if (!kvm_vcpu_apicv_active(vcpu))
6050 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
6051 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6052 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6054 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
6055 * in vmx_set_cr4. */
6056 exec_control &= ~SECONDARY_EXEC_DESC;
6058 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
6060 We can NOT enable shadow_vmcs here because we don't have yet
6063 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6066 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
6068 if (vmx_xsaves_supported()) {
6069 /* Exposing XSAVES only when XSAVE is exposed */
6070 bool xsaves_enabled =
6071 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
6072 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
6074 if (!xsaves_enabled)
6075 exec_control &= ~SECONDARY_EXEC_XSAVES;
6079 vmx->nested.msrs.secondary_ctls_high |=
6080 SECONDARY_EXEC_XSAVES;
6082 vmx->nested.msrs.secondary_ctls_high &=
6083 ~SECONDARY_EXEC_XSAVES;
6087 if (vmx_rdtscp_supported()) {
6088 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
6089 if (!rdtscp_enabled)
6090 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6094 vmx->nested.msrs.secondary_ctls_high |=
6095 SECONDARY_EXEC_RDTSCP;
6097 vmx->nested.msrs.secondary_ctls_high &=
6098 ~SECONDARY_EXEC_RDTSCP;
6102 if (vmx_invpcid_supported()) {
6103 /* Exposing INVPCID only when PCID is exposed */
6104 bool invpcid_enabled =
6105 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
6106 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
6108 if (!invpcid_enabled) {
6109 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6110 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
6114 if (invpcid_enabled)
6115 vmx->nested.msrs.secondary_ctls_high |=
6116 SECONDARY_EXEC_ENABLE_INVPCID;
6118 vmx->nested.msrs.secondary_ctls_high &=
6119 ~SECONDARY_EXEC_ENABLE_INVPCID;
6123 if (vmx_rdrand_supported()) {
6124 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
6126 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
6130 vmx->nested.msrs.secondary_ctls_high |=
6131 SECONDARY_EXEC_RDRAND_EXITING;
6133 vmx->nested.msrs.secondary_ctls_high &=
6134 ~SECONDARY_EXEC_RDRAND_EXITING;
6138 if (vmx_rdseed_supported()) {
6139 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
6141 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
6145 vmx->nested.msrs.secondary_ctls_high |=
6146 SECONDARY_EXEC_RDSEED_EXITING;
6148 vmx->nested.msrs.secondary_ctls_high &=
6149 ~SECONDARY_EXEC_RDSEED_EXITING;
6153 vmx->secondary_exec_control = exec_control;
6156 static void ept_set_mmio_spte_mask(void)
6159 * EPT Misconfigurations can be generated if the value of bits 2:0
6160 * of an EPT paging-structure entry is 110b (write/execute).
6162 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
6163 VMX_EPT_MISCONFIG_WX_VALUE);
6166 #define VMX_XSS_EXIT_BITMAP 0
6168 * Sets up the vmcs for emulated real mode.
6170 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
6172 #ifdef CONFIG_X86_64
6177 if (enable_shadow_vmcs) {
6179 * At vCPU creation, "VMWRITE to any supported field
6180 * in the VMCS" is supported, so use the more
6181 * permissive vmx_vmread_bitmap to specify both read
6182 * and write permissions for the shadow VMCS.
6184 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
6185 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmread_bitmap));
6187 if (cpu_has_vmx_msr_bitmap())
6188 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
6190 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
6193 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6194 vmx->hv_deadline_tsc = -1;
6196 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6198 if (cpu_has_secondary_exec_ctrls()) {
6199 vmx_compute_secondary_exec_control(vmx);
6200 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6201 vmx->secondary_exec_control);
6204 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
6205 vmcs_write64(EOI_EXIT_BITMAP0, 0);
6206 vmcs_write64(EOI_EXIT_BITMAP1, 0);
6207 vmcs_write64(EOI_EXIT_BITMAP2, 0);
6208 vmcs_write64(EOI_EXIT_BITMAP3, 0);
6210 vmcs_write16(GUEST_INTR_STATUS, 0);
6212 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
6213 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
6216 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
6217 vmcs_write32(PLE_GAP, ple_gap);
6218 vmx->ple_window = ple_window;
6219 vmx->ple_window_dirty = true;
6222 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
6223 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6224 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
6226 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
6227 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
6228 vmx_set_constant_host_state(vmx);
6229 #ifdef CONFIG_X86_64
6230 rdmsrl(MSR_FS_BASE, a);
6231 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
6232 rdmsrl(MSR_GS_BASE, a);
6233 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
6235 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
6236 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6239 if (cpu_has_vmx_vmfunc())
6240 vmcs_write64(VM_FUNCTION_CONTROL, 0);
6242 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
6243 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
6244 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
6245 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6246 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6248 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6249 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6251 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6252 u32 index = vmx_msr_index[i];
6253 u32 data_low, data_high;
6256 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6258 if (wrmsr_safe(index, data_low, data_high) < 0)
6260 vmx->guest_msrs[j].index = i;
6261 vmx->guest_msrs[j].data = 0;
6262 vmx->guest_msrs[j].mask = -1ull;
6266 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
6267 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, vmx->arch_capabilities);
6269 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6271 /* 22.2.1, 20.8.1 */
6272 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
6274 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
6275 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
6277 set_cr4_guest_host_mask(vmx);
6279 if (vmx_xsaves_supported())
6280 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
6283 ASSERT(vmx->pml_pg);
6284 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
6285 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
6289 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
6291 struct vcpu_vmx *vmx = to_vmx(vcpu);
6292 struct msr_data apic_base_msr;
6295 vmx->rmode.vm86_active = 0;
6298 vcpu->arch.microcode_version = 0x100000000ULL;
6299 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
6300 kvm_set_cr8(vcpu, 0);
6303 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
6304 MSR_IA32_APICBASE_ENABLE;
6305 if (kvm_vcpu_is_reset_bsp(vcpu))
6306 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
6307 apic_base_msr.host_initiated = true;
6308 kvm_set_apic_base(vcpu, &apic_base_msr);
6311 vmx_segment_cache_clear(vmx);
6313 seg_setup(VCPU_SREG_CS);
6314 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
6315 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
6317 seg_setup(VCPU_SREG_DS);
6318 seg_setup(VCPU_SREG_ES);
6319 seg_setup(VCPU_SREG_FS);
6320 seg_setup(VCPU_SREG_GS);
6321 seg_setup(VCPU_SREG_SS);
6323 vmcs_write16(GUEST_TR_SELECTOR, 0);
6324 vmcs_writel(GUEST_TR_BASE, 0);
6325 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
6326 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
6328 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
6329 vmcs_writel(GUEST_LDTR_BASE, 0);
6330 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
6331 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
6334 vmcs_write32(GUEST_SYSENTER_CS, 0);
6335 vmcs_writel(GUEST_SYSENTER_ESP, 0);
6336 vmcs_writel(GUEST_SYSENTER_EIP, 0);
6337 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
6340 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6341 kvm_rip_write(vcpu, 0xfff0);
6343 vmcs_writel(GUEST_GDTR_BASE, 0);
6344 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
6346 vmcs_writel(GUEST_IDTR_BASE, 0);
6347 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
6349 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
6350 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
6351 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
6352 if (kvm_mpx_supported())
6353 vmcs_write64(GUEST_BNDCFGS, 0);
6357 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
6359 if (cpu_has_vmx_tpr_shadow() && !init_event) {
6360 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
6361 if (cpu_need_tpr_shadow(vcpu))
6362 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
6363 __pa(vcpu->arch.apic->regs));
6364 vmcs_write32(TPR_THRESHOLD, 0);
6367 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6370 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6372 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
6373 vmx->vcpu.arch.cr0 = cr0;
6374 vmx_set_cr0(vcpu, cr0); /* enter rmode */
6375 vmx_set_cr4(vcpu, 0);
6376 vmx_set_efer(vcpu, 0);
6378 update_exception_bitmap(vcpu);
6380 vpid_sync_context(vmx->vpid);
6382 vmx_clear_hlt(vcpu);
6386 * In nested virtualization, check if L1 asked to exit on external interrupts.
6387 * For most existing hypervisors, this will always return true.
6389 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
6391 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
6392 PIN_BASED_EXT_INTR_MASK;
6396 * In nested virtualization, check if L1 has set
6397 * VM_EXIT_ACK_INTR_ON_EXIT
6399 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
6401 return get_vmcs12(vcpu)->vm_exit_controls &
6402 VM_EXIT_ACK_INTR_ON_EXIT;
6405 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
6407 return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu));
6410 static void enable_irq_window(struct kvm_vcpu *vcpu)
6412 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6413 CPU_BASED_VIRTUAL_INTR_PENDING);
6416 static void enable_nmi_window(struct kvm_vcpu *vcpu)
6419 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
6420 enable_irq_window(vcpu);
6424 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6425 CPU_BASED_VIRTUAL_NMI_PENDING);
6428 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
6430 struct vcpu_vmx *vmx = to_vmx(vcpu);
6432 int irq = vcpu->arch.interrupt.nr;
6434 trace_kvm_inj_virq(irq);
6436 ++vcpu->stat.irq_injections;
6437 if (vmx->rmode.vm86_active) {
6439 if (vcpu->arch.interrupt.soft)
6440 inc_eip = vcpu->arch.event_exit_inst_len;
6441 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
6442 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6445 intr = irq | INTR_INFO_VALID_MASK;
6446 if (vcpu->arch.interrupt.soft) {
6447 intr |= INTR_TYPE_SOFT_INTR;
6448 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6449 vmx->vcpu.arch.event_exit_inst_len);
6451 intr |= INTR_TYPE_EXT_INTR;
6452 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
6454 vmx_clear_hlt(vcpu);
6457 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
6459 struct vcpu_vmx *vmx = to_vmx(vcpu);
6463 * Tracking the NMI-blocked state in software is built upon
6464 * finding the next open IRQ window. This, in turn, depends on
6465 * well-behaving guests: They have to keep IRQs disabled at
6466 * least as long as the NMI handler runs. Otherwise we may
6467 * cause NMI nesting, maybe breaking the guest. But as this is
6468 * highly unlikely, we can live with the residual risk.
6470 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
6471 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6474 ++vcpu->stat.nmi_injections;
6475 vmx->loaded_vmcs->nmi_known_unmasked = false;
6477 if (vmx->rmode.vm86_active) {
6478 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
6479 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6483 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6484 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
6486 vmx_clear_hlt(vcpu);
6489 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
6491 struct vcpu_vmx *vmx = to_vmx(vcpu);
6495 return vmx->loaded_vmcs->soft_vnmi_blocked;
6496 if (vmx->loaded_vmcs->nmi_known_unmasked)
6498 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
6499 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6503 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
6505 struct vcpu_vmx *vmx = to_vmx(vcpu);
6508 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
6509 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
6510 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6513 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6515 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6516 GUEST_INTR_STATE_NMI);
6518 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
6519 GUEST_INTR_STATE_NMI);
6523 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
6525 if (to_vmx(vcpu)->nested.nested_run_pending)
6529 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
6532 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6533 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
6534 | GUEST_INTR_STATE_NMI));
6537 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
6539 return (!to_vmx(vcpu)->nested.nested_run_pending &&
6540 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
6541 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6542 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
6545 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
6549 if (enable_unrestricted_guest)
6552 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
6556 to_kvm_vmx(kvm)->tss_addr = addr;
6557 return init_rmode_tss(kvm);
6560 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
6562 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
6566 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6571 * Update instruction length as we may reinject the exception
6572 * from user space while in guest debugging mode.
6574 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
6575 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6576 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6580 if (vcpu->guest_debug &
6581 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6598 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
6599 int vec, u32 err_code)
6602 * Instruction with address size override prefix opcode 0x67
6603 * Cause the #SS fault with 0 error code in VM86 mode.
6605 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
6606 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
6607 if (vcpu->arch.halt_request) {
6608 vcpu->arch.halt_request = 0;
6609 return kvm_vcpu_halt(vcpu);
6617 * Forward all other exceptions that are valid in real mode.
6618 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
6619 * the required debugging infrastructure rework.
6621 kvm_queue_exception(vcpu, vec);
6626 * Trigger machine check on the host. We assume all the MSRs are already set up
6627 * by the CPU and that we still run on the same CPU as the MCE occurred on.
6628 * We pass a fake environment to the machine check handler because we want
6629 * the guest to be always treated like user space, no matter what context
6630 * it used internally.
6632 static void kvm_machine_check(void)
6634 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
6635 struct pt_regs regs = {
6636 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
6637 .flags = X86_EFLAGS_IF,
6640 do_machine_check(®s, 0);
6644 static int handle_machine_check(struct kvm_vcpu *vcpu)
6646 /* already handled by vcpu_run */
6650 static int handle_exception(struct kvm_vcpu *vcpu)
6652 struct vcpu_vmx *vmx = to_vmx(vcpu);
6653 struct kvm_run *kvm_run = vcpu->run;
6654 u32 intr_info, ex_no, error_code;
6655 unsigned long cr2, rip, dr6;
6657 enum emulation_result er;
6659 vect_info = vmx->idt_vectoring_info;
6660 intr_info = vmx->exit_intr_info;
6662 if (is_machine_check(intr_info))
6663 return handle_machine_check(vcpu);
6665 if (is_nmi(intr_info))
6666 return 1; /* already handled by vmx_vcpu_run() */
6668 if (is_invalid_opcode(intr_info))
6669 return handle_ud(vcpu);
6672 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6673 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6675 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
6676 WARN_ON_ONCE(!enable_vmware_backdoor);
6677 er = emulate_instruction(vcpu,
6678 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
6679 if (er == EMULATE_USER_EXIT)
6681 else if (er != EMULATE_DONE)
6682 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
6687 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
6688 * MMIO, it is better to report an internal error.
6689 * See the comments in vmx_handle_exit.
6691 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
6692 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
6693 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6694 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
6695 vcpu->run->internal.ndata = 3;
6696 vcpu->run->internal.data[0] = vect_info;
6697 vcpu->run->internal.data[1] = intr_info;
6698 vcpu->run->internal.data[2] = error_code;
6702 if (is_page_fault(intr_info)) {
6703 cr2 = vmcs_readl(EXIT_QUALIFICATION);
6704 /* EPT won't cause page fault directly */
6705 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
6706 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6709 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
6711 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
6712 return handle_rmode_exception(vcpu, ex_no, error_code);
6716 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
6719 dr6 = vmcs_readl(EXIT_QUALIFICATION);
6720 if (!(vcpu->guest_debug &
6721 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
6722 vcpu->arch.dr6 &= ~15;
6723 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6724 if (is_icebp(intr_info))
6725 skip_emulated_instruction(vcpu);
6727 kvm_queue_exception(vcpu, DB_VECTOR);
6730 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
6731 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
6735 * Update instruction length as we may reinject #BP from
6736 * user space while in guest debugging mode. Reading it for
6737 * #DB as well causes no harm, it is not used in that case.
6739 vmx->vcpu.arch.event_exit_inst_len =
6740 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6741 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6742 rip = kvm_rip_read(vcpu);
6743 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
6744 kvm_run->debug.arch.exception = ex_no;
6747 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
6748 kvm_run->ex.exception = ex_no;
6749 kvm_run->ex.error_code = error_code;
6755 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6757 ++vcpu->stat.irq_exits;
6761 static int handle_triple_fault(struct kvm_vcpu *vcpu)
6763 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6764 vcpu->mmio_needed = 0;
6768 static int handle_io(struct kvm_vcpu *vcpu)
6770 unsigned long exit_qualification;
6771 int size, in, string;
6774 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6775 string = (exit_qualification & 16) != 0;
6777 ++vcpu->stat.io_exits;
6780 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6782 port = exit_qualification >> 16;
6783 size = (exit_qualification & 7) + 1;
6784 in = (exit_qualification & 8) != 0;
6786 return kvm_fast_pio(vcpu, size, port, in);
6790 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
6793 * Patch in the VMCALL instruction:
6795 hypercall[0] = 0x0f;
6796 hypercall[1] = 0x01;
6797 hypercall[2] = 0xc1;
6800 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6801 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
6803 if (is_guest_mode(vcpu)) {
6804 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6805 unsigned long orig_val = val;
6808 * We get here when L2 changed cr0 in a way that did not change
6809 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6810 * but did change L0 shadowed bits. So we first calculate the
6811 * effective cr0 value that L1 would like to write into the
6812 * hardware. It consists of the L2-owned bits from the new
6813 * value combined with the L1-owned bits from L1's guest_cr0.
6815 val = (val & ~vmcs12->cr0_guest_host_mask) |
6816 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
6818 if (!nested_guest_cr0_valid(vcpu, val))
6821 if (kvm_set_cr0(vcpu, val))
6823 vmcs_writel(CR0_READ_SHADOW, orig_val);
6826 if (to_vmx(vcpu)->nested.vmxon &&
6827 !nested_host_cr0_valid(vcpu, val))
6830 return kvm_set_cr0(vcpu, val);
6834 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
6836 if (is_guest_mode(vcpu)) {
6837 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6838 unsigned long orig_val = val;
6840 /* analogously to handle_set_cr0 */
6841 val = (val & ~vmcs12->cr4_guest_host_mask) |
6842 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
6843 if (kvm_set_cr4(vcpu, val))
6845 vmcs_writel(CR4_READ_SHADOW, orig_val);
6848 return kvm_set_cr4(vcpu, val);
6851 static int handle_desc(struct kvm_vcpu *vcpu)
6853 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
6854 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6857 static int handle_cr(struct kvm_vcpu *vcpu)
6859 unsigned long exit_qualification, val;
6865 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6866 cr = exit_qualification & 15;
6867 reg = (exit_qualification >> 8) & 15;
6868 switch ((exit_qualification >> 4) & 3) {
6869 case 0: /* mov to cr */
6870 val = kvm_register_readl(vcpu, reg);
6871 trace_kvm_cr_write(cr, val);
6874 err = handle_set_cr0(vcpu, val);
6875 return kvm_complete_insn_gp(vcpu, err);
6877 WARN_ON_ONCE(enable_unrestricted_guest);
6878 err = kvm_set_cr3(vcpu, val);
6879 return kvm_complete_insn_gp(vcpu, err);
6881 err = handle_set_cr4(vcpu, val);
6882 return kvm_complete_insn_gp(vcpu, err);
6884 u8 cr8_prev = kvm_get_cr8(vcpu);
6886 err = kvm_set_cr8(vcpu, cr8);
6887 ret = kvm_complete_insn_gp(vcpu, err);
6888 if (lapic_in_kernel(vcpu))
6890 if (cr8_prev <= cr8)
6893 * TODO: we might be squashing a
6894 * KVM_GUESTDBG_SINGLESTEP-triggered
6895 * KVM_EXIT_DEBUG here.
6897 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
6903 WARN_ONCE(1, "Guest should always own CR0.TS");
6904 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6905 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6906 return kvm_skip_emulated_instruction(vcpu);
6907 case 1: /*mov from cr*/
6910 WARN_ON_ONCE(enable_unrestricted_guest);
6911 val = kvm_read_cr3(vcpu);
6912 kvm_register_write(vcpu, reg, val);
6913 trace_kvm_cr_read(cr, val);
6914 return kvm_skip_emulated_instruction(vcpu);
6916 val = kvm_get_cr8(vcpu);
6917 kvm_register_write(vcpu, reg, val);
6918 trace_kvm_cr_read(cr, val);
6919 return kvm_skip_emulated_instruction(vcpu);
6923 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6924 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6925 kvm_lmsw(vcpu, val);
6927 return kvm_skip_emulated_instruction(vcpu);
6931 vcpu->run->exit_reason = 0;
6932 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6933 (int)(exit_qualification >> 4) & 3, cr);
6937 static int handle_dr(struct kvm_vcpu *vcpu)
6939 unsigned long exit_qualification;
6942 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6943 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6945 /* First, if DR does not exist, trigger UD */
6946 if (!kvm_require_dr(vcpu, dr))
6949 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6950 if (!kvm_require_cpl(vcpu, 0))
6952 dr7 = vmcs_readl(GUEST_DR7);
6955 * As the vm-exit takes precedence over the debug trap, we
6956 * need to emulate the latter, either for the host or the
6957 * guest debugging itself.
6959 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6960 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6961 vcpu->run->debug.arch.dr7 = dr7;
6962 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6963 vcpu->run->debug.arch.exception = DB_VECTOR;
6964 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6967 vcpu->arch.dr6 &= ~15;
6968 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6969 kvm_queue_exception(vcpu, DB_VECTOR);
6974 if (vcpu->guest_debug == 0) {
6975 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6976 CPU_BASED_MOV_DR_EXITING);
6979 * No more DR vmexits; force a reload of the debug registers
6980 * and reenter on this instruction. The next vmexit will
6981 * retrieve the full state of the debug registers.
6983 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6987 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6988 if (exit_qualification & TYPE_MOV_FROM_DR) {
6991 if (kvm_get_dr(vcpu, dr, &val))
6993 kvm_register_write(vcpu, reg, val);
6995 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6998 return kvm_skip_emulated_instruction(vcpu);
7001 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
7003 return vcpu->arch.dr6;
7006 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
7010 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
7012 get_debugreg(vcpu->arch.db[0], 0);
7013 get_debugreg(vcpu->arch.db[1], 1);
7014 get_debugreg(vcpu->arch.db[2], 2);
7015 get_debugreg(vcpu->arch.db[3], 3);
7016 get_debugreg(vcpu->arch.dr6, 6);
7017 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
7019 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
7020 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
7023 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
7025 vmcs_writel(GUEST_DR7, val);
7028 static int handle_cpuid(struct kvm_vcpu *vcpu)
7030 return kvm_emulate_cpuid(vcpu);
7033 static int handle_rdmsr(struct kvm_vcpu *vcpu)
7035 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7036 struct msr_data msr_info;
7038 msr_info.index = ecx;
7039 msr_info.host_initiated = false;
7040 if (vmx_get_msr(vcpu, &msr_info)) {
7041 trace_kvm_msr_read_ex(ecx);
7042 kvm_inject_gp(vcpu, 0);
7046 trace_kvm_msr_read(ecx, msr_info.data);
7048 /* FIXME: handling of bits 32:63 of rax, rdx */
7049 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
7050 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
7051 return kvm_skip_emulated_instruction(vcpu);
7054 static int handle_wrmsr(struct kvm_vcpu *vcpu)
7056 struct msr_data msr;
7057 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7058 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
7059 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
7063 msr.host_initiated = false;
7064 if (kvm_set_msr(vcpu, &msr) != 0) {
7065 trace_kvm_msr_write_ex(ecx, data);
7066 kvm_inject_gp(vcpu, 0);
7070 trace_kvm_msr_write(ecx, data);
7071 return kvm_skip_emulated_instruction(vcpu);
7074 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
7076 kvm_apic_update_ppr(vcpu);
7080 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
7082 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7083 CPU_BASED_VIRTUAL_INTR_PENDING);
7085 kvm_make_request(KVM_REQ_EVENT, vcpu);
7087 ++vcpu->stat.irq_window_exits;
7091 static int handle_halt(struct kvm_vcpu *vcpu)
7093 return kvm_emulate_halt(vcpu);
7096 static int handle_vmcall(struct kvm_vcpu *vcpu)
7098 return kvm_emulate_hypercall(vcpu);
7101 static int handle_invd(struct kvm_vcpu *vcpu)
7103 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
7106 static int handle_invlpg(struct kvm_vcpu *vcpu)
7108 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7110 kvm_mmu_invlpg(vcpu, exit_qualification);
7111 return kvm_skip_emulated_instruction(vcpu);
7114 static int handle_rdpmc(struct kvm_vcpu *vcpu)
7118 err = kvm_rdpmc(vcpu);
7119 return kvm_complete_insn_gp(vcpu, err);
7122 static int handle_wbinvd(struct kvm_vcpu *vcpu)
7124 return kvm_emulate_wbinvd(vcpu);
7127 static int handle_xsetbv(struct kvm_vcpu *vcpu)
7129 u64 new_bv = kvm_read_edx_eax(vcpu);
7130 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
7132 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
7133 return kvm_skip_emulated_instruction(vcpu);
7137 static int handle_xsaves(struct kvm_vcpu *vcpu)
7139 kvm_skip_emulated_instruction(vcpu);
7140 WARN(1, "this should never happen\n");
7144 static int handle_xrstors(struct kvm_vcpu *vcpu)
7146 kvm_skip_emulated_instruction(vcpu);
7147 WARN(1, "this should never happen\n");
7151 static int handle_apic_access(struct kvm_vcpu *vcpu)
7153 if (likely(fasteoi)) {
7154 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7155 int access_type, offset;
7157 access_type = exit_qualification & APIC_ACCESS_TYPE;
7158 offset = exit_qualification & APIC_ACCESS_OFFSET;
7160 * Sane guest uses MOV to write EOI, with written value
7161 * not cared. So make a short-circuit here by avoiding
7162 * heavy instruction emulation.
7164 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
7165 (offset == APIC_EOI)) {
7166 kvm_lapic_set_eoi(vcpu);
7167 return kvm_skip_emulated_instruction(vcpu);
7170 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
7173 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
7175 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7176 int vector = exit_qualification & 0xff;
7178 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
7179 kvm_apic_set_eoi_accelerated(vcpu, vector);
7183 static int handle_apic_write(struct kvm_vcpu *vcpu)
7185 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7186 u32 offset = exit_qualification & 0xfff;
7188 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
7189 kvm_apic_write_nodecode(vcpu, offset);
7193 static int handle_task_switch(struct kvm_vcpu *vcpu)
7195 struct vcpu_vmx *vmx = to_vmx(vcpu);
7196 unsigned long exit_qualification;
7197 bool has_error_code = false;
7200 int reason, type, idt_v, idt_index;
7202 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7203 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
7204 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
7206 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7208 reason = (u32)exit_qualification >> 30;
7209 if (reason == TASK_SWITCH_GATE && idt_v) {
7211 case INTR_TYPE_NMI_INTR:
7212 vcpu->arch.nmi_injected = false;
7213 vmx_set_nmi_mask(vcpu, true);
7215 case INTR_TYPE_EXT_INTR:
7216 case INTR_TYPE_SOFT_INTR:
7217 kvm_clear_interrupt_queue(vcpu);
7219 case INTR_TYPE_HARD_EXCEPTION:
7220 if (vmx->idt_vectoring_info &
7221 VECTORING_INFO_DELIVER_CODE_MASK) {
7222 has_error_code = true;
7224 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7227 case INTR_TYPE_SOFT_EXCEPTION:
7228 kvm_clear_exception_queue(vcpu);
7234 tss_selector = exit_qualification;
7236 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
7237 type != INTR_TYPE_EXT_INTR &&
7238 type != INTR_TYPE_NMI_INTR))
7239 skip_emulated_instruction(vcpu);
7241 if (kvm_task_switch(vcpu, tss_selector,
7242 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
7243 has_error_code, error_code) == EMULATE_FAIL) {
7244 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7245 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7246 vcpu->run->internal.ndata = 0;
7251 * TODO: What about debug traps on tss switch?
7252 * Are we supposed to inject them and update dr6?
7258 static int handle_ept_violation(struct kvm_vcpu *vcpu)
7260 unsigned long exit_qualification;
7264 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7267 * EPT violation happened while executing iret from NMI,
7268 * "blocked by NMI" bit has to be set before next VM entry.
7269 * There are errata that may cause this bit to not be set:
7272 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7274 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7275 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
7277 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7278 trace_kvm_page_fault(gpa, exit_qualification);
7280 /* Is it a read fault? */
7281 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
7282 ? PFERR_USER_MASK : 0;
7283 /* Is it a write fault? */
7284 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
7285 ? PFERR_WRITE_MASK : 0;
7286 /* Is it a fetch fault? */
7287 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
7288 ? PFERR_FETCH_MASK : 0;
7289 /* ept page table entry is present? */
7290 error_code |= (exit_qualification &
7291 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
7292 EPT_VIOLATION_EXECUTABLE))
7293 ? PFERR_PRESENT_MASK : 0;
7295 error_code |= (exit_qualification & 0x100) != 0 ?
7296 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
7298 vcpu->arch.exit_qualification = exit_qualification;
7299 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
7302 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
7307 * A nested guest cannot optimize MMIO vmexits, because we have an
7308 * nGPA here instead of the required GPA.
7310 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7311 if (!is_guest_mode(vcpu) &&
7312 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
7313 trace_kvm_fast_mmio(gpa);
7315 * Doing kvm_skip_emulated_instruction() depends on undefined
7316 * behavior: Intel's manual doesn't mandate
7317 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
7318 * occurs and while on real hardware it was observed to be set,
7319 * other hypervisors (namely Hyper-V) don't set it, we end up
7320 * advancing IP with some random value. Disable fast mmio when
7321 * running nested and keep it for real hardware in hope that
7322 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
7324 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
7325 return kvm_skip_emulated_instruction(vcpu);
7327 return x86_emulate_instruction(vcpu, gpa, EMULTYPE_SKIP,
7328 NULL, 0) == EMULATE_DONE;
7331 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
7334 static int handle_nmi_window(struct kvm_vcpu *vcpu)
7336 WARN_ON_ONCE(!enable_vnmi);
7337 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7338 CPU_BASED_VIRTUAL_NMI_PENDING);
7339 ++vcpu->stat.nmi_window_exits;
7340 kvm_make_request(KVM_REQ_EVENT, vcpu);
7345 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
7347 struct vcpu_vmx *vmx = to_vmx(vcpu);
7348 enum emulation_result err = EMULATE_DONE;
7351 bool intr_window_requested;
7352 unsigned count = 130;
7355 * We should never reach the point where we are emulating L2
7356 * due to invalid guest state as that means we incorrectly
7357 * allowed a nested VMEntry with an invalid vmcs12.
7359 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
7361 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7362 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
7364 while (vmx->emulation_required && count-- != 0) {
7365 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
7366 return handle_interrupt_window(&vmx->vcpu);
7368 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
7371 err = emulate_instruction(vcpu, 0);
7373 if (err == EMULATE_USER_EXIT) {
7374 ++vcpu->stat.mmio_exits;
7379 if (err != EMULATE_DONE)
7380 goto emulation_error;
7382 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
7383 vcpu->arch.exception.pending)
7384 goto emulation_error;
7386 if (vcpu->arch.halt_request) {
7387 vcpu->arch.halt_request = 0;
7388 ret = kvm_vcpu_halt(vcpu);
7392 if (signal_pending(current))
7402 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7403 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7404 vcpu->run->internal.ndata = 0;
7408 static void grow_ple_window(struct kvm_vcpu *vcpu)
7410 struct vcpu_vmx *vmx = to_vmx(vcpu);
7411 int old = vmx->ple_window;
7413 vmx->ple_window = __grow_ple_window(old, ple_window,
7417 if (vmx->ple_window != old)
7418 vmx->ple_window_dirty = true;
7420 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
7423 static void shrink_ple_window(struct kvm_vcpu *vcpu)
7425 struct vcpu_vmx *vmx = to_vmx(vcpu);
7426 int old = vmx->ple_window;
7428 vmx->ple_window = __shrink_ple_window(old, ple_window,
7432 if (vmx->ple_window != old)
7433 vmx->ple_window_dirty = true;
7435 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
7439 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
7441 static void wakeup_handler(void)
7443 struct kvm_vcpu *vcpu;
7444 int cpu = smp_processor_id();
7446 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7447 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
7448 blocked_vcpu_list) {
7449 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7451 if (pi_test_on(pi_desc) == 1)
7452 kvm_vcpu_kick(vcpu);
7454 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7457 static void vmx_enable_tdp(void)
7459 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
7460 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
7461 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
7462 0ull, VMX_EPT_EXECUTABLE_MASK,
7463 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
7464 VMX_EPT_RWX_MASK, 0ull);
7466 ept_set_mmio_spte_mask();
7470 static __init int hardware_setup(void)
7474 rdmsrl_safe(MSR_EFER, &host_efer);
7476 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7477 kvm_define_shared_msr(i, vmx_msr_index[i]);
7479 for (i = 0; i < VMX_BITMAP_NR; i++) {
7480 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
7485 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
7486 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
7488 if (setup_vmcs_config(&vmcs_config) < 0) {
7493 if (boot_cpu_has(X86_FEATURE_NX))
7494 kvm_enable_efer_bits(EFER_NX);
7496 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7497 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7500 if (!cpu_has_vmx_ept() ||
7501 !cpu_has_vmx_ept_4levels() ||
7502 !cpu_has_vmx_ept_mt_wb() ||
7503 !cpu_has_vmx_invept_global())
7506 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7507 enable_ept_ad_bits = 0;
7509 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7510 enable_unrestricted_guest = 0;
7512 if (!cpu_has_vmx_flexpriority())
7513 flexpriority_enabled = 0;
7515 if (!cpu_has_virtual_nmis())
7519 * set_apic_access_page_addr() is used to reload apic access
7520 * page upon invalidation. No need to do anything if not
7521 * using the APIC_ACCESS_ADDR VMCS field.
7523 if (!flexpriority_enabled)
7524 kvm_x86_ops->set_apic_access_page_addr = NULL;
7526 if (!cpu_has_vmx_tpr_shadow())
7527 kvm_x86_ops->update_cr8_intercept = NULL;
7529 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7530 kvm_disable_largepages();
7532 if (!cpu_has_vmx_ple()) {
7535 ple_window_grow = 0;
7537 ple_window_shrink = 0;
7540 if (!cpu_has_vmx_apicv()) {
7542 kvm_x86_ops->sync_pir_to_irr = NULL;
7545 if (cpu_has_vmx_tsc_scaling()) {
7546 kvm_has_tsc_control = true;
7547 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7548 kvm_tsc_scaling_ratio_frac_bits = 48;
7551 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7559 * Only enable PML when hardware supports PML feature, and both EPT
7560 * and EPT A/D bit features are enabled -- PML depends on them to work.
7562 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7566 kvm_x86_ops->slot_enable_log_dirty = NULL;
7567 kvm_x86_ops->slot_disable_log_dirty = NULL;
7568 kvm_x86_ops->flush_log_dirty = NULL;
7569 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7572 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7575 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7576 cpu_preemption_timer_multi =
7577 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7579 kvm_x86_ops->set_hv_timer = NULL;
7580 kvm_x86_ops->cancel_hv_timer = NULL;
7583 if (!cpu_has_vmx_shadow_vmcs())
7584 enable_shadow_vmcs = 0;
7585 if (enable_shadow_vmcs)
7586 init_vmcs_shadow_fields();
7588 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7589 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, enable_apicv);
7591 kvm_mce_cap_supported |= MCG_LMCE_P;
7593 return alloc_kvm_area();
7596 for (i = 0; i < VMX_BITMAP_NR; i++)
7597 free_page((unsigned long)vmx_bitmap[i]);
7602 static __exit void hardware_unsetup(void)
7606 for (i = 0; i < VMX_BITMAP_NR; i++)
7607 free_page((unsigned long)vmx_bitmap[i]);
7613 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
7614 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
7616 static int handle_pause(struct kvm_vcpu *vcpu)
7618 if (!kvm_pause_in_guest(vcpu->kvm))
7619 grow_ple_window(vcpu);
7622 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
7623 * VM-execution control is ignored if CPL > 0. OTOH, KVM
7624 * never set PAUSE_EXITING and just set PLE if supported,
7625 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
7627 kvm_vcpu_on_spin(vcpu, true);
7628 return kvm_skip_emulated_instruction(vcpu);
7631 static int handle_nop(struct kvm_vcpu *vcpu)
7633 return kvm_skip_emulated_instruction(vcpu);
7636 static int handle_mwait(struct kvm_vcpu *vcpu)
7638 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
7639 return handle_nop(vcpu);
7642 static int handle_invalid_op(struct kvm_vcpu *vcpu)
7644 kvm_queue_exception(vcpu, UD_VECTOR);
7648 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
7653 static int handle_monitor(struct kvm_vcpu *vcpu)
7655 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
7656 return handle_nop(vcpu);
7660 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7661 * set the success or error code of an emulated VMX instruction, as specified
7662 * by Vol 2B, VMX Instruction Reference, "Conventions".
7664 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
7666 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
7667 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7668 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
7671 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
7673 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7674 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
7675 X86_EFLAGS_SF | X86_EFLAGS_OF))
7679 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
7680 u32 vm_instruction_error)
7682 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
7684 * failValid writes the error number to the current VMCS, which
7685 * can't be done there isn't a current VMCS.
7687 nested_vmx_failInvalid(vcpu);
7690 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7691 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7692 X86_EFLAGS_SF | X86_EFLAGS_OF))
7694 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
7696 * We don't need to force a shadow sync because
7697 * VM_INSTRUCTION_ERROR is not shadowed
7701 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
7703 /* TODO: not to reset guest simply here. */
7704 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7705 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
7708 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
7710 struct vcpu_vmx *vmx =
7711 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
7713 vmx->nested.preemption_timer_expired = true;
7714 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
7715 kvm_vcpu_kick(&vmx->vcpu);
7717 return HRTIMER_NORESTART;
7721 * Decode the memory-address operand of a vmx instruction, as recorded on an
7722 * exit caused by such an instruction (run by a guest hypervisor).
7723 * On success, returns 0. When the operand is invalid, returns 1 and throws
7726 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
7727 unsigned long exit_qualification,
7728 u32 vmx_instruction_info, bool wr, gva_t *ret)
7732 struct kvm_segment s;
7735 * According to Vol. 3B, "Information for VM Exits Due to Instruction
7736 * Execution", on an exit, vmx_instruction_info holds most of the
7737 * addressing components of the operand. Only the displacement part
7738 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7739 * For how an actual address is calculated from all these components,
7740 * refer to Vol. 1, "Operand Addressing".
7742 int scaling = vmx_instruction_info & 3;
7743 int addr_size = (vmx_instruction_info >> 7) & 7;
7744 bool is_reg = vmx_instruction_info & (1u << 10);
7745 int seg_reg = (vmx_instruction_info >> 15) & 7;
7746 int index_reg = (vmx_instruction_info >> 18) & 0xf;
7747 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
7748 int base_reg = (vmx_instruction_info >> 23) & 0xf;
7749 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
7752 kvm_queue_exception(vcpu, UD_VECTOR);
7756 /* Addr = segment_base + offset */
7757 /* offset = base + [index * scale] + displacement */
7758 off = exit_qualification; /* holds the displacement */
7760 off += kvm_register_read(vcpu, base_reg);
7762 off += kvm_register_read(vcpu, index_reg)<<scaling;
7763 vmx_get_segment(vcpu, &s, seg_reg);
7764 *ret = s.base + off;
7766 if (addr_size == 1) /* 32 bit */
7769 /* Checks for #GP/#SS exceptions. */
7771 if (is_long_mode(vcpu)) {
7772 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7773 * non-canonical form. This is the only check on the memory
7774 * destination for long mode!
7776 exn = is_noncanonical_address(*ret, vcpu);
7777 } else if (is_protmode(vcpu)) {
7778 /* Protected mode: apply checks for segment validity in the
7780 * - segment type check (#GP(0) may be thrown)
7781 * - usability check (#GP(0)/#SS(0))
7782 * - limit check (#GP(0)/#SS(0))
7785 /* #GP(0) if the destination operand is located in a
7786 * read-only data segment or any code segment.
7788 exn = ((s.type & 0xa) == 0 || (s.type & 8));
7790 /* #GP(0) if the source operand is located in an
7791 * execute-only code segment
7793 exn = ((s.type & 0xa) == 8);
7795 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7798 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7800 exn = (s.unusable != 0);
7801 /* Protected mode: #GP(0)/#SS(0) if the memory
7802 * operand is outside the segment limit.
7804 exn = exn || (off + sizeof(u64) > s.limit);
7807 kvm_queue_exception_e(vcpu,
7808 seg_reg == VCPU_SREG_SS ?
7809 SS_VECTOR : GP_VECTOR,
7817 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7820 struct x86_exception e;
7822 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7823 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7826 if (kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e)) {
7827 kvm_inject_page_fault(vcpu, &e);
7834 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7836 struct vcpu_vmx *vmx = to_vmx(vcpu);
7837 struct vmcs *shadow_vmcs;
7840 r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
7844 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7845 if (!vmx->nested.cached_vmcs12)
7846 goto out_cached_vmcs12;
7848 if (enable_shadow_vmcs) {
7849 shadow_vmcs = alloc_vmcs();
7851 goto out_shadow_vmcs;
7852 /* mark vmcs as shadow */
7853 shadow_vmcs->revision_id |= (1u << 31);
7854 /* init shadow vmcs */
7855 vmcs_clear(shadow_vmcs);
7856 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7859 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7860 HRTIMER_MODE_REL_PINNED);
7861 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7863 vmx->nested.vmxon = true;
7867 kfree(vmx->nested.cached_vmcs12);
7870 free_loaded_vmcs(&vmx->nested.vmcs02);
7877 * Emulate the VMXON instruction.
7878 * Currently, we just remember that VMX is active, and do not save or even
7879 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7880 * do not currently need to store anything in that guest-allocated memory
7881 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7882 * argument is different from the VMXON pointer (which the spec says they do).
7884 static int handle_vmon(struct kvm_vcpu *vcpu)
7889 struct vcpu_vmx *vmx = to_vmx(vcpu);
7890 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7891 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7894 * The Intel VMX Instruction Reference lists a bunch of bits that are
7895 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7896 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7897 * Otherwise, we should fail with #UD. But most faulting conditions
7898 * have already been checked by hardware, prior to the VM-exit for
7899 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7900 * that bit set to 1 in non-root mode.
7902 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7903 kvm_queue_exception(vcpu, UD_VECTOR);
7907 /* CPL=0 must be checked manually. */
7908 if (vmx_get_cpl(vcpu)) {
7909 kvm_queue_exception(vcpu, UD_VECTOR);
7913 if (vmx->nested.vmxon) {
7914 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7915 return kvm_skip_emulated_instruction(vcpu);
7918 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7919 != VMXON_NEEDED_FEATURES) {
7920 kvm_inject_gp(vcpu, 0);
7924 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7929 * The first 4 bytes of VMXON region contain the supported
7930 * VMCS revision identifier
7932 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7933 * which replaces physical address width with 32
7935 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7936 nested_vmx_failInvalid(vcpu);
7937 return kvm_skip_emulated_instruction(vcpu);
7940 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7941 if (is_error_page(page)) {
7942 nested_vmx_failInvalid(vcpu);
7943 return kvm_skip_emulated_instruction(vcpu);
7945 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7947 kvm_release_page_clean(page);
7948 nested_vmx_failInvalid(vcpu);
7949 return kvm_skip_emulated_instruction(vcpu);
7952 kvm_release_page_clean(page);
7954 vmx->nested.vmxon_ptr = vmptr;
7955 ret = enter_vmx_operation(vcpu);
7959 nested_vmx_succeed(vcpu);
7960 return kvm_skip_emulated_instruction(vcpu);
7964 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7965 * for running VMX instructions (except VMXON, whose prerequisites are
7966 * slightly different). It also specifies what exception to inject otherwise.
7967 * Note that many of these exceptions have priority over VM exits, so they
7968 * don't have to be checked again here.
7970 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7972 if (vmx_get_cpl(vcpu)) {
7973 kvm_queue_exception(vcpu, UD_VECTOR);
7977 if (!to_vmx(vcpu)->nested.vmxon) {
7978 kvm_queue_exception(vcpu, UD_VECTOR);
7984 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
7986 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
7987 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7990 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7992 if (vmx->nested.current_vmptr == -1ull)
7995 if (enable_shadow_vmcs) {
7996 /* copy to memory all shadowed fields in case
7997 they were modified */
7998 copy_shadow_to_vmcs12(vmx);
7999 vmx->nested.sync_shadow_vmcs = false;
8000 vmx_disable_shadow_vmcs(vmx);
8002 vmx->nested.posted_intr_nv = -1;
8004 /* Flush VMCS12 to guest memory */
8005 kvm_vcpu_write_guest_page(&vmx->vcpu,
8006 vmx->nested.current_vmptr >> PAGE_SHIFT,
8007 vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
8009 vmx->nested.current_vmptr = -1ull;
8013 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
8014 * just stops using VMX.
8016 static void free_nested(struct vcpu_vmx *vmx)
8018 if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
8021 vmx->nested.vmxon = false;
8022 vmx->nested.smm.vmxon = false;
8023 free_vpid(vmx->nested.vpid02);
8024 vmx->nested.posted_intr_nv = -1;
8025 vmx->nested.current_vmptr = -1ull;
8026 if (enable_shadow_vmcs) {
8027 vmx_disable_shadow_vmcs(vmx);
8028 vmcs_clear(vmx->vmcs01.shadow_vmcs);
8029 free_vmcs(vmx->vmcs01.shadow_vmcs);
8030 vmx->vmcs01.shadow_vmcs = NULL;
8032 kfree(vmx->nested.cached_vmcs12);
8033 /* Unpin physical memory we referred to in the vmcs02 */
8034 if (vmx->nested.apic_access_page) {
8035 kvm_release_page_dirty(vmx->nested.apic_access_page);
8036 vmx->nested.apic_access_page = NULL;
8038 if (vmx->nested.virtual_apic_page) {
8039 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
8040 vmx->nested.virtual_apic_page = NULL;
8042 if (vmx->nested.pi_desc_page) {
8043 kunmap(vmx->nested.pi_desc_page);
8044 kvm_release_page_dirty(vmx->nested.pi_desc_page);
8045 vmx->nested.pi_desc_page = NULL;
8046 vmx->nested.pi_desc = NULL;
8049 free_loaded_vmcs(&vmx->nested.vmcs02);
8052 /* Emulate the VMXOFF instruction */
8053 static int handle_vmoff(struct kvm_vcpu *vcpu)
8055 if (!nested_vmx_check_permission(vcpu))
8057 free_nested(to_vmx(vcpu));
8058 nested_vmx_succeed(vcpu);
8059 return kvm_skip_emulated_instruction(vcpu);
8062 /* Emulate the VMCLEAR instruction */
8063 static int handle_vmclear(struct kvm_vcpu *vcpu)
8065 struct vcpu_vmx *vmx = to_vmx(vcpu);
8069 if (!nested_vmx_check_permission(vcpu))
8072 if (nested_vmx_get_vmptr(vcpu, &vmptr))
8075 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8076 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
8077 return kvm_skip_emulated_instruction(vcpu);
8080 if (vmptr == vmx->nested.vmxon_ptr) {
8081 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
8082 return kvm_skip_emulated_instruction(vcpu);
8085 if (vmptr == vmx->nested.current_vmptr)
8086 nested_release_vmcs12(vmx);
8088 kvm_vcpu_write_guest(vcpu,
8089 vmptr + offsetof(struct vmcs12, launch_state),
8090 &zero, sizeof(zero));
8092 nested_vmx_succeed(vcpu);
8093 return kvm_skip_emulated_instruction(vcpu);
8096 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
8098 /* Emulate the VMLAUNCH instruction */
8099 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
8101 return nested_vmx_run(vcpu, true);
8104 /* Emulate the VMRESUME instruction */
8105 static int handle_vmresume(struct kvm_vcpu *vcpu)
8108 return nested_vmx_run(vcpu, false);
8112 * Read a vmcs12 field. Since these can have varying lengths and we return
8113 * one type, we chose the biggest type (u64) and zero-extend the return value
8114 * to that size. Note that the caller, handle_vmread, might need to use only
8115 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
8116 * 64-bit fields are to be returned).
8118 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
8119 unsigned long field, u64 *ret)
8121 short offset = vmcs_field_to_offset(field);
8127 p = ((char *)(get_vmcs12(vcpu))) + offset;
8129 switch (vmcs_field_width(field)) {
8130 case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8131 *ret = *((natural_width *)p);
8133 case VMCS_FIELD_WIDTH_U16:
8136 case VMCS_FIELD_WIDTH_U32:
8139 case VMCS_FIELD_WIDTH_U64:
8149 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
8150 unsigned long field, u64 field_value){
8151 short offset = vmcs_field_to_offset(field);
8152 char *p = ((char *) get_vmcs12(vcpu)) + offset;
8156 switch (vmcs_field_width(field)) {
8157 case VMCS_FIELD_WIDTH_U16:
8158 *(u16 *)p = field_value;
8160 case VMCS_FIELD_WIDTH_U32:
8161 *(u32 *)p = field_value;
8163 case VMCS_FIELD_WIDTH_U64:
8164 *(u64 *)p = field_value;
8166 case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8167 *(natural_width *)p = field_value;
8177 * Copy the writable VMCS shadow fields back to the VMCS12, in case
8178 * they have been modified by the L1 guest. Note that the "read-only"
8179 * VM-exit information fields are actually writable if the vCPU is
8180 * configured to support "VMWRITE to any supported field in the VMCS."
8182 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
8184 const u16 *fields[] = {
8185 shadow_read_write_fields,
8186 shadow_read_only_fields
8188 const int max_fields[] = {
8189 max_shadow_read_write_fields,
8190 max_shadow_read_only_fields
8193 unsigned long field;
8195 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8199 vmcs_load(shadow_vmcs);
8201 for (q = 0; q < ARRAY_SIZE(fields); q++) {
8202 for (i = 0; i < max_fields[q]; i++) {
8203 field = fields[q][i];
8204 field_value = __vmcs_readl(field);
8205 vmcs12_write_any(&vmx->vcpu, field, field_value);
8208 * Skip the VM-exit information fields if they are read-only.
8210 if (!nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
8214 vmcs_clear(shadow_vmcs);
8215 vmcs_load(vmx->loaded_vmcs->vmcs);
8220 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
8222 const u16 *fields[] = {
8223 shadow_read_write_fields,
8224 shadow_read_only_fields
8226 const int max_fields[] = {
8227 max_shadow_read_write_fields,
8228 max_shadow_read_only_fields
8231 unsigned long field;
8232 u64 field_value = 0;
8233 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8235 vmcs_load(shadow_vmcs);
8237 for (q = 0; q < ARRAY_SIZE(fields); q++) {
8238 for (i = 0; i < max_fields[q]; i++) {
8239 field = fields[q][i];
8240 vmcs12_read_any(&vmx->vcpu, field, &field_value);
8241 __vmcs_writel(field, field_value);
8245 vmcs_clear(shadow_vmcs);
8246 vmcs_load(vmx->loaded_vmcs->vmcs);
8250 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
8251 * used before) all generate the same failure when it is missing.
8253 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
8255 struct vcpu_vmx *vmx = to_vmx(vcpu);
8256 if (vmx->nested.current_vmptr == -1ull) {
8257 nested_vmx_failInvalid(vcpu);
8263 static int handle_vmread(struct kvm_vcpu *vcpu)
8265 unsigned long field;
8267 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8268 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8271 if (!nested_vmx_check_permission(vcpu))
8274 if (!nested_vmx_check_vmcs12(vcpu))
8275 return kvm_skip_emulated_instruction(vcpu);
8277 /* Decode instruction info and find the field to read */
8278 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8279 /* Read the field, zero-extended to a u64 field_value */
8280 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
8281 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8282 return kvm_skip_emulated_instruction(vcpu);
8285 * Now copy part of this value to register or memory, as requested.
8286 * Note that the number of bits actually copied is 32 or 64 depending
8287 * on the guest's mode (32 or 64 bit), not on the given field's length.
8289 if (vmx_instruction_info & (1u << 10)) {
8290 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
8293 if (get_vmx_mem_address(vcpu, exit_qualification,
8294 vmx_instruction_info, true, &gva))
8296 /* _system ok, nested_vmx_check_permission has verified cpl=0 */
8297 kvm_write_guest_virt_system(vcpu, gva, &field_value,
8298 (is_long_mode(vcpu) ? 8 : 4), NULL);
8301 nested_vmx_succeed(vcpu);
8302 return kvm_skip_emulated_instruction(vcpu);
8306 static int handle_vmwrite(struct kvm_vcpu *vcpu)
8308 unsigned long field;
8310 struct vcpu_vmx *vmx = to_vmx(vcpu);
8311 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8312 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8314 /* The value to write might be 32 or 64 bits, depending on L1's long
8315 * mode, and eventually we need to write that into a field of several
8316 * possible lengths. The code below first zero-extends the value to 64
8317 * bit (field_value), and then copies only the appropriate number of
8318 * bits into the vmcs12 field.
8320 u64 field_value = 0;
8321 struct x86_exception e;
8323 if (!nested_vmx_check_permission(vcpu))
8326 if (!nested_vmx_check_vmcs12(vcpu))
8327 return kvm_skip_emulated_instruction(vcpu);
8329 if (vmx_instruction_info & (1u << 10))
8330 field_value = kvm_register_readl(vcpu,
8331 (((vmx_instruction_info) >> 3) & 0xf));
8333 if (get_vmx_mem_address(vcpu, exit_qualification,
8334 vmx_instruction_info, false, &gva))
8336 if (kvm_read_guest_virt(vcpu, gva, &field_value,
8337 (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
8338 kvm_inject_page_fault(vcpu, &e);
8344 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8346 * If the vCPU supports "VMWRITE to any supported field in the
8347 * VMCS," then the "read-only" fields are actually read/write.
8349 if (vmcs_field_readonly(field) &&
8350 !nested_cpu_has_vmwrite_any_field(vcpu)) {
8351 nested_vmx_failValid(vcpu,
8352 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
8353 return kvm_skip_emulated_instruction(vcpu);
8356 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
8357 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8358 return kvm_skip_emulated_instruction(vcpu);
8362 #define SHADOW_FIELD_RW(x) case x:
8363 #include "vmx_shadow_fields.h"
8365 * The fields that can be updated by L1 without a vmexit are
8366 * always updated in the vmcs02, the others go down the slow
8367 * path of prepare_vmcs02.
8371 vmx->nested.dirty_vmcs12 = true;
8375 nested_vmx_succeed(vcpu);
8376 return kvm_skip_emulated_instruction(vcpu);
8379 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
8381 vmx->nested.current_vmptr = vmptr;
8382 if (enable_shadow_vmcs) {
8383 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
8384 SECONDARY_EXEC_SHADOW_VMCS);
8385 vmcs_write64(VMCS_LINK_POINTER,
8386 __pa(vmx->vmcs01.shadow_vmcs));
8387 vmx->nested.sync_shadow_vmcs = true;
8389 vmx->nested.dirty_vmcs12 = true;
8392 /* Emulate the VMPTRLD instruction */
8393 static int handle_vmptrld(struct kvm_vcpu *vcpu)
8395 struct vcpu_vmx *vmx = to_vmx(vcpu);
8398 if (!nested_vmx_check_permission(vcpu))
8401 if (nested_vmx_get_vmptr(vcpu, &vmptr))
8404 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8405 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
8406 return kvm_skip_emulated_instruction(vcpu);
8409 if (vmptr == vmx->nested.vmxon_ptr) {
8410 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
8411 return kvm_skip_emulated_instruction(vcpu);
8414 if (vmx->nested.current_vmptr != vmptr) {
8415 struct vmcs12 *new_vmcs12;
8417 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8418 if (is_error_page(page)) {
8419 nested_vmx_failInvalid(vcpu);
8420 return kvm_skip_emulated_instruction(vcpu);
8422 new_vmcs12 = kmap(page);
8423 if (new_vmcs12->revision_id != VMCS12_REVISION) {
8425 kvm_release_page_clean(page);
8426 nested_vmx_failValid(vcpu,
8427 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
8428 return kvm_skip_emulated_instruction(vcpu);
8431 nested_release_vmcs12(vmx);
8433 * Load VMCS12 from guest memory since it is not already
8436 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
8438 kvm_release_page_clean(page);
8440 set_current_vmptr(vmx, vmptr);
8443 nested_vmx_succeed(vcpu);
8444 return kvm_skip_emulated_instruction(vcpu);
8447 /* Emulate the VMPTRST instruction */
8448 static int handle_vmptrst(struct kvm_vcpu *vcpu)
8450 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8451 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8453 struct x86_exception e;
8455 if (!nested_vmx_check_permission(vcpu))
8458 if (get_vmx_mem_address(vcpu, exit_qualification,
8459 vmx_instruction_info, true, &vmcs_gva))
8461 /* *_system ok, nested_vmx_check_permission has verified cpl=0 */
8462 if (kvm_write_guest_virt_system(vcpu, vmcs_gva,
8463 (void *)&to_vmx(vcpu)->nested.current_vmptr,
8465 kvm_inject_page_fault(vcpu, &e);
8468 nested_vmx_succeed(vcpu);
8469 return kvm_skip_emulated_instruction(vcpu);
8472 /* Emulate the INVEPT instruction */
8473 static int handle_invept(struct kvm_vcpu *vcpu)
8475 struct vcpu_vmx *vmx = to_vmx(vcpu);
8476 u32 vmx_instruction_info, types;
8479 struct x86_exception e;
8484 if (!(vmx->nested.msrs.secondary_ctls_high &
8485 SECONDARY_EXEC_ENABLE_EPT) ||
8486 !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) {
8487 kvm_queue_exception(vcpu, UD_VECTOR);
8491 if (!nested_vmx_check_permission(vcpu))
8494 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8495 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8497 types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
8499 if (type >= 32 || !(types & (1 << type))) {
8500 nested_vmx_failValid(vcpu,
8501 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8502 return kvm_skip_emulated_instruction(vcpu);
8505 /* According to the Intel VMX instruction reference, the memory
8506 * operand is read even if it isn't needed (e.g., for type==global)
8508 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8509 vmx_instruction_info, false, &gva))
8511 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
8512 kvm_inject_page_fault(vcpu, &e);
8517 case VMX_EPT_EXTENT_GLOBAL:
8519 * TODO: track mappings and invalidate
8520 * single context requests appropriately
8522 case VMX_EPT_EXTENT_CONTEXT:
8523 kvm_mmu_sync_roots(vcpu);
8524 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
8525 nested_vmx_succeed(vcpu);
8532 return kvm_skip_emulated_instruction(vcpu);
8535 static int handle_invvpid(struct kvm_vcpu *vcpu)
8537 struct vcpu_vmx *vmx = to_vmx(vcpu);
8538 u32 vmx_instruction_info;
8539 unsigned long type, types;
8541 struct x86_exception e;
8547 if (!(vmx->nested.msrs.secondary_ctls_high &
8548 SECONDARY_EXEC_ENABLE_VPID) ||
8549 !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) {
8550 kvm_queue_exception(vcpu, UD_VECTOR);
8554 if (!nested_vmx_check_permission(vcpu))
8557 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8558 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8560 types = (vmx->nested.msrs.vpid_caps &
8561 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
8563 if (type >= 32 || !(types & (1 << type))) {
8564 nested_vmx_failValid(vcpu,
8565 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8566 return kvm_skip_emulated_instruction(vcpu);
8569 /* according to the intel vmx instruction reference, the memory
8570 * operand is read even if it isn't needed (e.g., for type==global)
8572 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8573 vmx_instruction_info, false, &gva))
8575 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
8576 kvm_inject_page_fault(vcpu, &e);
8579 if (operand.vpid >> 16) {
8580 nested_vmx_failValid(vcpu,
8581 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8582 return kvm_skip_emulated_instruction(vcpu);
8586 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
8587 if (!operand.vpid ||
8588 is_noncanonical_address(operand.gla, vcpu)) {
8589 nested_vmx_failValid(vcpu,
8590 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8591 return kvm_skip_emulated_instruction(vcpu);
8593 if (cpu_has_vmx_invvpid_individual_addr() &&
8594 vmx->nested.vpid02) {
8595 __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR,
8596 vmx->nested.vpid02, operand.gla);
8598 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8600 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
8601 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
8602 if (!operand.vpid) {
8603 nested_vmx_failValid(vcpu,
8604 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8605 return kvm_skip_emulated_instruction(vcpu);
8607 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8609 case VMX_VPID_EXTENT_ALL_CONTEXT:
8610 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8614 return kvm_skip_emulated_instruction(vcpu);
8617 nested_vmx_succeed(vcpu);
8619 return kvm_skip_emulated_instruction(vcpu);
8622 static int handle_pml_full(struct kvm_vcpu *vcpu)
8624 unsigned long exit_qualification;
8626 trace_kvm_pml_full(vcpu->vcpu_id);
8628 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8631 * PML buffer FULL happened while executing iret from NMI,
8632 * "blocked by NMI" bit has to be set before next VM entry.
8634 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
8636 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
8637 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8638 GUEST_INTR_STATE_NMI);
8641 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
8642 * here.., and there's no userspace involvement needed for PML.
8647 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8649 kvm_lapic_expired_hv_timer(vcpu);
8653 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
8655 struct vcpu_vmx *vmx = to_vmx(vcpu);
8656 int maxphyaddr = cpuid_maxphyaddr(vcpu);
8658 /* Check for memory type validity */
8659 switch (address & VMX_EPTP_MT_MASK) {
8660 case VMX_EPTP_MT_UC:
8661 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT))
8664 case VMX_EPTP_MT_WB:
8665 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT))
8672 /* only 4 levels page-walk length are valid */
8673 if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
8676 /* Reserved bits should not be set */
8677 if (address >> maxphyaddr || ((address >> 7) & 0x1f))
8680 /* AD, if set, should be supported */
8681 if (address & VMX_EPTP_AD_ENABLE_BIT) {
8682 if (!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT))
8689 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
8690 struct vmcs12 *vmcs12)
8692 u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
8694 bool accessed_dirty;
8695 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
8697 if (!nested_cpu_has_eptp_switching(vmcs12) ||
8698 !nested_cpu_has_ept(vmcs12))
8701 if (index >= VMFUNC_EPTP_ENTRIES)
8705 if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
8706 &address, index * 8, 8))
8709 accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
8712 * If the (L2) guest does a vmfunc to the currently
8713 * active ept pointer, we don't have to do anything else
8715 if (vmcs12->ept_pointer != address) {
8716 if (!valid_ept_address(vcpu, address))
8719 kvm_mmu_unload(vcpu);
8720 mmu->ept_ad = accessed_dirty;
8721 mmu->base_role.ad_disabled = !accessed_dirty;
8722 vmcs12->ept_pointer = address;
8724 * TODO: Check what's the correct approach in case
8725 * mmu reload fails. Currently, we just let the next
8726 * reload potentially fail
8728 kvm_mmu_reload(vcpu);
8734 static int handle_vmfunc(struct kvm_vcpu *vcpu)
8736 struct vcpu_vmx *vmx = to_vmx(vcpu);
8737 struct vmcs12 *vmcs12;
8738 u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
8741 * VMFUNC is only supported for nested guests, but we always enable the
8742 * secondary control for simplicity; for non-nested mode, fake that we
8743 * didn't by injecting #UD.
8745 if (!is_guest_mode(vcpu)) {
8746 kvm_queue_exception(vcpu, UD_VECTOR);
8750 vmcs12 = get_vmcs12(vcpu);
8751 if ((vmcs12->vm_function_control & (1 << function)) == 0)
8756 if (nested_vmx_eptp_switching(vcpu, vmcs12))
8762 return kvm_skip_emulated_instruction(vcpu);
8765 nested_vmx_vmexit(vcpu, vmx->exit_reason,
8766 vmcs_read32(VM_EXIT_INTR_INFO),
8767 vmcs_readl(EXIT_QUALIFICATION));
8772 * The exit handlers return 1 if the exit was handled fully and guest execution
8773 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
8774 * to be done to userspace and return 0.
8776 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
8777 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
8778 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
8779 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
8780 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
8781 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
8782 [EXIT_REASON_CR_ACCESS] = handle_cr,
8783 [EXIT_REASON_DR_ACCESS] = handle_dr,
8784 [EXIT_REASON_CPUID] = handle_cpuid,
8785 [EXIT_REASON_MSR_READ] = handle_rdmsr,
8786 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
8787 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
8788 [EXIT_REASON_HLT] = handle_halt,
8789 [EXIT_REASON_INVD] = handle_invd,
8790 [EXIT_REASON_INVLPG] = handle_invlpg,
8791 [EXIT_REASON_RDPMC] = handle_rdpmc,
8792 [EXIT_REASON_VMCALL] = handle_vmcall,
8793 [EXIT_REASON_VMCLEAR] = handle_vmclear,
8794 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
8795 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
8796 [EXIT_REASON_VMPTRST] = handle_vmptrst,
8797 [EXIT_REASON_VMREAD] = handle_vmread,
8798 [EXIT_REASON_VMRESUME] = handle_vmresume,
8799 [EXIT_REASON_VMWRITE] = handle_vmwrite,
8800 [EXIT_REASON_VMOFF] = handle_vmoff,
8801 [EXIT_REASON_VMON] = handle_vmon,
8802 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
8803 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
8804 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
8805 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
8806 [EXIT_REASON_WBINVD] = handle_wbinvd,
8807 [EXIT_REASON_XSETBV] = handle_xsetbv,
8808 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
8809 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
8810 [EXIT_REASON_GDTR_IDTR] = handle_desc,
8811 [EXIT_REASON_LDTR_TR] = handle_desc,
8812 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
8813 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
8814 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
8815 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
8816 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
8817 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
8818 [EXIT_REASON_INVEPT] = handle_invept,
8819 [EXIT_REASON_INVVPID] = handle_invvpid,
8820 [EXIT_REASON_RDRAND] = handle_invalid_op,
8821 [EXIT_REASON_RDSEED] = handle_invalid_op,
8822 [EXIT_REASON_XSAVES] = handle_xsaves,
8823 [EXIT_REASON_XRSTORS] = handle_xrstors,
8824 [EXIT_REASON_PML_FULL] = handle_pml_full,
8825 [EXIT_REASON_VMFUNC] = handle_vmfunc,
8826 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
8829 static const int kvm_vmx_max_exit_handlers =
8830 ARRAY_SIZE(kvm_vmx_exit_handlers);
8832 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
8833 struct vmcs12 *vmcs12)
8835 unsigned long exit_qualification;
8836 gpa_t bitmap, last_bitmap;
8841 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
8842 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
8844 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8846 port = exit_qualification >> 16;
8847 size = (exit_qualification & 7) + 1;
8849 last_bitmap = (gpa_t)-1;
8854 bitmap = vmcs12->io_bitmap_a;
8855 else if (port < 0x10000)
8856 bitmap = vmcs12->io_bitmap_b;
8859 bitmap += (port & 0x7fff) / 8;
8861 if (last_bitmap != bitmap)
8862 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8864 if (b & (1 << (port & 7)))
8869 last_bitmap = bitmap;
8876 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8877 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8878 * disinterest in the current event (read or write a specific MSR) by using an
8879 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8881 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8882 struct vmcs12 *vmcs12, u32 exit_reason)
8884 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8887 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8891 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8892 * for the four combinations of read/write and low/high MSR numbers.
8893 * First we need to figure out which of the four to use:
8895 bitmap = vmcs12->msr_bitmap;
8896 if (exit_reason == EXIT_REASON_MSR_WRITE)
8898 if (msr_index >= 0xc0000000) {
8899 msr_index -= 0xc0000000;
8903 /* Then read the msr_index'th bit from this bitmap: */
8904 if (msr_index < 1024*8) {
8906 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8908 return 1 & (b >> (msr_index & 7));
8910 return true; /* let L1 handle the wrong parameter */
8914 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8915 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8916 * intercept (via guest_host_mask etc.) the current event.
8918 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8919 struct vmcs12 *vmcs12)
8921 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8922 int cr = exit_qualification & 15;
8926 switch ((exit_qualification >> 4) & 3) {
8927 case 0: /* mov to cr */
8928 reg = (exit_qualification >> 8) & 15;
8929 val = kvm_register_readl(vcpu, reg);
8932 if (vmcs12->cr0_guest_host_mask &
8933 (val ^ vmcs12->cr0_read_shadow))
8937 if ((vmcs12->cr3_target_count >= 1 &&
8938 vmcs12->cr3_target_value0 == val) ||
8939 (vmcs12->cr3_target_count >= 2 &&
8940 vmcs12->cr3_target_value1 == val) ||
8941 (vmcs12->cr3_target_count >= 3 &&
8942 vmcs12->cr3_target_value2 == val) ||
8943 (vmcs12->cr3_target_count >= 4 &&
8944 vmcs12->cr3_target_value3 == val))
8946 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8950 if (vmcs12->cr4_guest_host_mask &
8951 (vmcs12->cr4_read_shadow ^ val))
8955 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8961 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8962 (vmcs12->cr0_read_shadow & X86_CR0_TS))
8965 case 1: /* mov from cr */
8968 if (vmcs12->cpu_based_vm_exec_control &
8969 CPU_BASED_CR3_STORE_EXITING)
8973 if (vmcs12->cpu_based_vm_exec_control &
8974 CPU_BASED_CR8_STORE_EXITING)
8981 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8982 * cr0. Other attempted changes are ignored, with no exit.
8984 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8985 if (vmcs12->cr0_guest_host_mask & 0xe &
8986 (val ^ vmcs12->cr0_read_shadow))
8988 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8989 !(vmcs12->cr0_read_shadow & 0x1) &&
8998 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8999 * should handle it ourselves in L0 (and then continue L2). Only call this
9000 * when in is_guest_mode (L2).
9002 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
9004 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9005 struct vcpu_vmx *vmx = to_vmx(vcpu);
9006 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9008 if (vmx->nested.nested_run_pending)
9011 if (unlikely(vmx->fail)) {
9012 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
9013 vmcs_read32(VM_INSTRUCTION_ERROR));
9018 * The host physical addresses of some pages of guest memory
9019 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
9020 * Page). The CPU may write to these pages via their host
9021 * physical address while L2 is running, bypassing any
9022 * address-translation-based dirty tracking (e.g. EPT write
9025 * Mark them dirty on every exit from L2 to prevent them from
9026 * getting out of sync with dirty tracking.
9028 nested_mark_vmcs12_pages_dirty(vcpu);
9030 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
9031 vmcs_readl(EXIT_QUALIFICATION),
9032 vmx->idt_vectoring_info,
9034 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9037 switch (exit_reason) {
9038 case EXIT_REASON_EXCEPTION_NMI:
9039 if (is_nmi(intr_info))
9041 else if (is_page_fault(intr_info))
9042 return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
9043 else if (is_no_device(intr_info) &&
9044 !(vmcs12->guest_cr0 & X86_CR0_TS))
9046 else if (is_debug(intr_info) &&
9048 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
9050 else if (is_breakpoint(intr_info) &&
9051 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
9053 return vmcs12->exception_bitmap &
9054 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
9055 case EXIT_REASON_EXTERNAL_INTERRUPT:
9057 case EXIT_REASON_TRIPLE_FAULT:
9059 case EXIT_REASON_PENDING_INTERRUPT:
9060 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
9061 case EXIT_REASON_NMI_WINDOW:
9062 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
9063 case EXIT_REASON_TASK_SWITCH:
9065 case EXIT_REASON_CPUID:
9067 case EXIT_REASON_HLT:
9068 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
9069 case EXIT_REASON_INVD:
9071 case EXIT_REASON_INVLPG:
9072 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9073 case EXIT_REASON_RDPMC:
9074 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
9075 case EXIT_REASON_RDRAND:
9076 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
9077 case EXIT_REASON_RDSEED:
9078 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
9079 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
9080 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
9081 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
9082 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
9083 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
9084 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
9085 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
9086 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
9088 * VMX instructions trap unconditionally. This allows L1 to
9089 * emulate them for its L2 guest, i.e., allows 3-level nesting!
9092 case EXIT_REASON_CR_ACCESS:
9093 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
9094 case EXIT_REASON_DR_ACCESS:
9095 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
9096 case EXIT_REASON_IO_INSTRUCTION:
9097 return nested_vmx_exit_handled_io(vcpu, vmcs12);
9098 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
9099 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
9100 case EXIT_REASON_MSR_READ:
9101 case EXIT_REASON_MSR_WRITE:
9102 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
9103 case EXIT_REASON_INVALID_STATE:
9105 case EXIT_REASON_MWAIT_INSTRUCTION:
9106 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
9107 case EXIT_REASON_MONITOR_TRAP_FLAG:
9108 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
9109 case EXIT_REASON_MONITOR_INSTRUCTION:
9110 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
9111 case EXIT_REASON_PAUSE_INSTRUCTION:
9112 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
9113 nested_cpu_has2(vmcs12,
9114 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
9115 case EXIT_REASON_MCE_DURING_VMENTRY:
9117 case EXIT_REASON_TPR_BELOW_THRESHOLD:
9118 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
9119 case EXIT_REASON_APIC_ACCESS:
9120 case EXIT_REASON_APIC_WRITE:
9121 case EXIT_REASON_EOI_INDUCED:
9123 * The controls for "virtualize APIC accesses," "APIC-
9124 * register virtualization," and "virtual-interrupt
9125 * delivery" only come from vmcs12.
9128 case EXIT_REASON_EPT_VIOLATION:
9130 * L0 always deals with the EPT violation. If nested EPT is
9131 * used, and the nested mmu code discovers that the address is
9132 * missing in the guest EPT table (EPT12), the EPT violation
9133 * will be injected with nested_ept_inject_page_fault()
9136 case EXIT_REASON_EPT_MISCONFIG:
9138 * L2 never uses directly L1's EPT, but rather L0's own EPT
9139 * table (shadow on EPT) or a merged EPT table that L0 built
9140 * (EPT on EPT). So any problems with the structure of the
9141 * table is L0's fault.
9144 case EXIT_REASON_INVPCID:
9146 nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
9147 nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9148 case EXIT_REASON_WBINVD:
9149 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
9150 case EXIT_REASON_XSETBV:
9152 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
9154 * This should never happen, since it is not possible to
9155 * set XSS to a non-zero value---neither in L1 nor in L2.
9156 * If if it were, XSS would have to be checked against
9157 * the XSS exit bitmap in vmcs12.
9159 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
9160 case EXIT_REASON_PREEMPTION_TIMER:
9162 case EXIT_REASON_PML_FULL:
9163 /* We emulate PML support to L1. */
9165 case EXIT_REASON_VMFUNC:
9166 /* VM functions are emulated through L2->L0 vmexits. */
9173 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
9175 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9178 * At this point, the exit interruption info in exit_intr_info
9179 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
9180 * we need to query the in-kernel LAPIC.
9182 WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
9183 if ((exit_intr_info &
9184 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9185 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
9186 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9187 vmcs12->vm_exit_intr_error_code =
9188 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9191 nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
9192 vmcs_readl(EXIT_QUALIFICATION));
9196 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
9198 *info1 = vmcs_readl(EXIT_QUALIFICATION);
9199 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
9202 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
9205 __free_page(vmx->pml_pg);
9210 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
9212 struct vcpu_vmx *vmx = to_vmx(vcpu);
9216 pml_idx = vmcs_read16(GUEST_PML_INDEX);
9218 /* Do nothing if PML buffer is empty */
9219 if (pml_idx == (PML_ENTITY_NUM - 1))
9222 /* PML index always points to next available PML buffer entity */
9223 if (pml_idx >= PML_ENTITY_NUM)
9228 pml_buf = page_address(vmx->pml_pg);
9229 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
9232 gpa = pml_buf[pml_idx];
9233 WARN_ON(gpa & (PAGE_SIZE - 1));
9234 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
9237 /* reset PML index */
9238 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
9242 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
9243 * Called before reporting dirty_bitmap to userspace.
9245 static void kvm_flush_pml_buffers(struct kvm *kvm)
9248 struct kvm_vcpu *vcpu;
9250 * We only need to kick vcpu out of guest mode here, as PML buffer
9251 * is flushed at beginning of all VMEXITs, and it's obvious that only
9252 * vcpus running in guest are possible to have unflushed GPAs in PML
9255 kvm_for_each_vcpu(i, vcpu, kvm)
9256 kvm_vcpu_kick(vcpu);
9259 static void vmx_dump_sel(char *name, uint32_t sel)
9261 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
9262 name, vmcs_read16(sel),
9263 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
9264 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
9265 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
9268 static void vmx_dump_dtsel(char *name, uint32_t limit)
9270 pr_err("%s limit=0x%08x, base=0x%016lx\n",
9271 name, vmcs_read32(limit),
9272 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
9275 static void dump_vmcs(void)
9277 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
9278 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
9279 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
9280 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
9281 u32 secondary_exec_control = 0;
9282 unsigned long cr4 = vmcs_readl(GUEST_CR4);
9283 u64 efer = vmcs_read64(GUEST_IA32_EFER);
9286 if (cpu_has_secondary_exec_ctrls())
9287 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9289 pr_err("*** Guest State ***\n");
9290 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9291 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
9292 vmcs_readl(CR0_GUEST_HOST_MASK));
9293 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9294 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
9295 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
9296 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
9297 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
9299 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
9300 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
9301 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
9302 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
9304 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
9305 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
9306 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
9307 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
9308 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9309 vmcs_readl(GUEST_SYSENTER_ESP),
9310 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
9311 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
9312 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
9313 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
9314 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
9315 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
9316 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
9317 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
9318 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
9319 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
9320 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
9321 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
9322 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
9323 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
9324 efer, vmcs_read64(GUEST_IA32_PAT));
9325 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
9326 vmcs_read64(GUEST_IA32_DEBUGCTL),
9327 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
9328 if (cpu_has_load_perf_global_ctrl &&
9329 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
9330 pr_err("PerfGlobCtl = 0x%016llx\n",
9331 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
9332 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
9333 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
9334 pr_err("Interruptibility = %08x ActivityState = %08x\n",
9335 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
9336 vmcs_read32(GUEST_ACTIVITY_STATE));
9337 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
9338 pr_err("InterruptStatus = %04x\n",
9339 vmcs_read16(GUEST_INTR_STATUS));
9341 pr_err("*** Host State ***\n");
9342 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
9343 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
9344 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
9345 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
9346 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
9347 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
9348 vmcs_read16(HOST_TR_SELECTOR));
9349 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
9350 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
9351 vmcs_readl(HOST_TR_BASE));
9352 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
9353 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
9354 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
9355 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
9356 vmcs_readl(HOST_CR4));
9357 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9358 vmcs_readl(HOST_IA32_SYSENTER_ESP),
9359 vmcs_read32(HOST_IA32_SYSENTER_CS),
9360 vmcs_readl(HOST_IA32_SYSENTER_EIP));
9361 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
9362 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
9363 vmcs_read64(HOST_IA32_EFER),
9364 vmcs_read64(HOST_IA32_PAT));
9365 if (cpu_has_load_perf_global_ctrl &&
9366 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9367 pr_err("PerfGlobCtl = 0x%016llx\n",
9368 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
9370 pr_err("*** Control State ***\n");
9371 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
9372 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
9373 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
9374 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
9375 vmcs_read32(EXCEPTION_BITMAP),
9376 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
9377 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
9378 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
9379 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9380 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
9381 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
9382 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
9383 vmcs_read32(VM_EXIT_INTR_INFO),
9384 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9385 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
9386 pr_err(" reason=%08x qualification=%016lx\n",
9387 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
9388 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
9389 vmcs_read32(IDT_VECTORING_INFO_FIELD),
9390 vmcs_read32(IDT_VECTORING_ERROR_CODE));
9391 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
9392 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
9393 pr_err("TSC Multiplier = 0x%016llx\n",
9394 vmcs_read64(TSC_MULTIPLIER));
9395 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
9396 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
9397 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
9398 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
9399 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
9400 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
9401 n = vmcs_read32(CR3_TARGET_COUNT);
9402 for (i = 0; i + 1 < n; i += 4)
9403 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
9404 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
9405 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
9407 pr_err("CR3 target%u=%016lx\n",
9408 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
9409 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
9410 pr_err("PLE Gap=%08x Window=%08x\n",
9411 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
9412 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
9413 pr_err("Virtual processor ID = 0x%04x\n",
9414 vmcs_read16(VIRTUAL_PROCESSOR_ID));
9418 * The guest has exited. See if we can fix it or if we need userspace
9421 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
9423 struct vcpu_vmx *vmx = to_vmx(vcpu);
9424 u32 exit_reason = vmx->exit_reason;
9425 u32 vectoring_info = vmx->idt_vectoring_info;
9427 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
9430 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
9431 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
9432 * querying dirty_bitmap, we only need to kick all vcpus out of guest
9433 * mode as if vcpus is in root mode, the PML buffer must has been
9437 vmx_flush_pml_buffer(vcpu);
9439 /* If guest state is invalid, start emulating */
9440 if (vmx->emulation_required)
9441 return handle_invalid_guest_state(vcpu);
9443 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
9444 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
9446 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
9448 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
9449 vcpu->run->fail_entry.hardware_entry_failure_reason
9454 if (unlikely(vmx->fail)) {
9455 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
9456 vcpu->run->fail_entry.hardware_entry_failure_reason
9457 = vmcs_read32(VM_INSTRUCTION_ERROR);
9463 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
9464 * delivery event since it indicates guest is accessing MMIO.
9465 * The vm-exit can be triggered again after return to guest that
9466 * will cause infinite loop.
9468 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
9469 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
9470 exit_reason != EXIT_REASON_EPT_VIOLATION &&
9471 exit_reason != EXIT_REASON_PML_FULL &&
9472 exit_reason != EXIT_REASON_TASK_SWITCH)) {
9473 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9474 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
9475 vcpu->run->internal.ndata = 3;
9476 vcpu->run->internal.data[0] = vectoring_info;
9477 vcpu->run->internal.data[1] = exit_reason;
9478 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
9479 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
9480 vcpu->run->internal.ndata++;
9481 vcpu->run->internal.data[3] =
9482 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
9487 if (unlikely(!enable_vnmi &&
9488 vmx->loaded_vmcs->soft_vnmi_blocked)) {
9489 if (vmx_interrupt_allowed(vcpu)) {
9490 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
9491 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
9492 vcpu->arch.nmi_pending) {
9494 * This CPU don't support us in finding the end of an
9495 * NMI-blocked window if the guest runs with IRQs
9496 * disabled. So we pull the trigger after 1 s of
9497 * futile waiting, but inform the user about this.
9499 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
9500 "state on VCPU %d after 1 s timeout\n",
9501 __func__, vcpu->vcpu_id);
9502 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
9506 if (exit_reason < kvm_vmx_max_exit_handlers
9507 && kvm_vmx_exit_handlers[exit_reason])
9508 return kvm_vmx_exit_handlers[exit_reason](vcpu);
9510 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
9512 kvm_queue_exception(vcpu, UD_VECTOR);
9517 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
9519 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9521 if (is_guest_mode(vcpu) &&
9522 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9525 if (irr == -1 || tpr < irr) {
9526 vmcs_write32(TPR_THRESHOLD, 0);
9530 vmcs_write32(TPR_THRESHOLD, irr);
9533 static void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
9535 u32 sec_exec_control;
9537 if (!lapic_in_kernel(vcpu))
9540 /* Postpone execution until vmcs01 is the current VMCS. */
9541 if (is_guest_mode(vcpu)) {
9542 to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
9546 if (!cpu_need_tpr_shadow(vcpu))
9549 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9550 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9551 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
9553 switch (kvm_get_apic_mode(vcpu)) {
9554 case LAPIC_MODE_INVALID:
9555 WARN_ONCE(true, "Invalid local APIC state");
9556 case LAPIC_MODE_DISABLED:
9558 case LAPIC_MODE_XAPIC:
9559 if (flexpriority_enabled) {
9561 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9562 vmx_flush_tlb(vcpu, true);
9565 case LAPIC_MODE_X2APIC:
9566 if (cpu_has_vmx_virtualize_x2apic_mode())
9568 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9571 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
9573 vmx_update_msr_bitmap(vcpu);
9576 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
9578 if (!is_guest_mode(vcpu)) {
9579 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9580 vmx_flush_tlb(vcpu, true);
9584 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
9592 status = vmcs_read16(GUEST_INTR_STATUS);
9594 if (max_isr != old) {
9596 status |= max_isr << 8;
9597 vmcs_write16(GUEST_INTR_STATUS, status);
9601 static void vmx_set_rvi(int vector)
9609 status = vmcs_read16(GUEST_INTR_STATUS);
9610 old = (u8)status & 0xff;
9611 if ((u8)vector != old) {
9613 status |= (u8)vector;
9614 vmcs_write16(GUEST_INTR_STATUS, status);
9618 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
9621 * When running L2, updating RVI is only relevant when
9622 * vmcs12 virtual-interrupt-delivery enabled.
9623 * However, it can be enabled only when L1 also
9624 * intercepts external-interrupts and in that case
9625 * we should not update vmcs02 RVI but instead intercept
9626 * interrupt. Therefore, do nothing when running L2.
9628 if (!is_guest_mode(vcpu))
9629 vmx_set_rvi(max_irr);
9632 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
9634 struct vcpu_vmx *vmx = to_vmx(vcpu);
9636 bool max_irr_updated;
9638 WARN_ON(!vcpu->arch.apicv_active);
9639 if (pi_test_on(&vmx->pi_desc)) {
9640 pi_clear_on(&vmx->pi_desc);
9642 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
9643 * But on x86 this is just a compiler barrier anyway.
9645 smp_mb__after_atomic();
9647 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
9650 * If we are running L2 and L1 has a new pending interrupt
9651 * which can be injected, we should re-evaluate
9652 * what should be done with this new L1 interrupt.
9653 * If L1 intercepts external-interrupts, we should
9654 * exit from L2 to L1. Otherwise, interrupt should be
9655 * delivered directly to L2.
9657 if (is_guest_mode(vcpu) && max_irr_updated) {
9658 if (nested_exit_on_intr(vcpu))
9659 kvm_vcpu_exiting_guest_mode(vcpu);
9661 kvm_make_request(KVM_REQ_EVENT, vcpu);
9664 max_irr = kvm_lapic_find_highest_irr(vcpu);
9666 vmx_hwapic_irr_update(vcpu, max_irr);
9670 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
9672 if (!kvm_vcpu_apicv_active(vcpu))
9675 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
9676 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
9677 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
9678 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
9681 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
9683 struct vcpu_vmx *vmx = to_vmx(vcpu);
9685 pi_clear_on(&vmx->pi_desc);
9686 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
9689 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
9691 u32 exit_intr_info = 0;
9692 u16 basic_exit_reason = (u16)vmx->exit_reason;
9694 if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
9695 || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
9698 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9699 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9700 vmx->exit_intr_info = exit_intr_info;
9702 /* if exit due to PF check for async PF */
9703 if (is_page_fault(exit_intr_info))
9704 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
9706 /* Handle machine checks before interrupts are enabled */
9707 if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
9708 is_machine_check(exit_intr_info))
9709 kvm_machine_check();
9711 /* We need to handle NMIs before interrupts are enabled */
9712 if (is_nmi(exit_intr_info)) {
9713 kvm_before_interrupt(&vmx->vcpu);
9715 kvm_after_interrupt(&vmx->vcpu);
9719 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
9721 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9723 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
9724 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
9725 unsigned int vector;
9726 unsigned long entry;
9728 struct vcpu_vmx *vmx = to_vmx(vcpu);
9729 #ifdef CONFIG_X86_64
9733 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9734 desc = (gate_desc *)vmx->host_idt_base + vector;
9735 entry = gate_offset(desc);
9737 #ifdef CONFIG_X86_64
9738 "mov %%" _ASM_SP ", %[sp]\n\t"
9739 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
9744 __ASM_SIZE(push) " $%c[cs]\n\t"
9747 #ifdef CONFIG_X86_64
9752 THUNK_TARGET(entry),
9753 [ss]"i"(__KERNEL_DS),
9754 [cs]"i"(__KERNEL_CS)
9758 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
9760 static bool vmx_has_emulated_msr(int index)
9763 case MSR_IA32_SMBASE:
9765 * We cannot do SMM unless we can run the guest in big
9768 return enable_unrestricted_guest || emulate_invalid_guest_state;
9769 case MSR_AMD64_VIRT_SPEC_CTRL:
9770 /* This is AMD only. */
9777 static bool vmx_mpx_supported(void)
9779 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
9780 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
9783 static bool vmx_xsaves_supported(void)
9785 return vmcs_config.cpu_based_2nd_exec_ctrl &
9786 SECONDARY_EXEC_XSAVES;
9789 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
9794 bool idtv_info_valid;
9796 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9799 if (vmx->loaded_vmcs->nmi_known_unmasked)
9802 * Can't use vmx->exit_intr_info since we're not sure what
9803 * the exit reason is.
9805 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9806 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
9807 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9809 * SDM 3: 27.7.1.2 (September 2008)
9810 * Re-set bit "block by NMI" before VM entry if vmexit caused by
9811 * a guest IRET fault.
9812 * SDM 3: 23.2.2 (September 2008)
9813 * Bit 12 is undefined in any of the following cases:
9814 * If the VM exit sets the valid bit in the IDT-vectoring
9815 * information field.
9816 * If the VM exit is due to a double fault.
9818 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
9819 vector != DF_VECTOR && !idtv_info_valid)
9820 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9821 GUEST_INTR_STATE_NMI);
9823 vmx->loaded_vmcs->nmi_known_unmasked =
9824 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
9825 & GUEST_INTR_STATE_NMI);
9826 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
9827 vmx->loaded_vmcs->vnmi_blocked_time +=
9828 ktime_to_ns(ktime_sub(ktime_get(),
9829 vmx->loaded_vmcs->entry_time));
9832 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
9833 u32 idt_vectoring_info,
9834 int instr_len_field,
9835 int error_code_field)
9839 bool idtv_info_valid;
9841 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9843 vcpu->arch.nmi_injected = false;
9844 kvm_clear_exception_queue(vcpu);
9845 kvm_clear_interrupt_queue(vcpu);
9847 if (!idtv_info_valid)
9850 kvm_make_request(KVM_REQ_EVENT, vcpu);
9852 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
9853 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
9856 case INTR_TYPE_NMI_INTR:
9857 vcpu->arch.nmi_injected = true;
9859 * SDM 3: 27.7.1.2 (September 2008)
9860 * Clear bit "block by NMI" before VM entry if a NMI
9863 vmx_set_nmi_mask(vcpu, false);
9865 case INTR_TYPE_SOFT_EXCEPTION:
9866 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9868 case INTR_TYPE_HARD_EXCEPTION:
9869 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
9870 u32 err = vmcs_read32(error_code_field);
9871 kvm_requeue_exception_e(vcpu, vector, err);
9873 kvm_requeue_exception(vcpu, vector);
9875 case INTR_TYPE_SOFT_INTR:
9876 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9878 case INTR_TYPE_EXT_INTR:
9879 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
9886 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
9888 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
9889 VM_EXIT_INSTRUCTION_LEN,
9890 IDT_VECTORING_ERROR_CODE);
9893 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
9895 __vmx_complete_interrupts(vcpu,
9896 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9897 VM_ENTRY_INSTRUCTION_LEN,
9898 VM_ENTRY_EXCEPTION_ERROR_CODE);
9900 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9903 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
9906 struct perf_guest_switch_msr *msrs;
9908 msrs = perf_guest_get_msrs(&nr_msrs);
9913 for (i = 0; i < nr_msrs; i++)
9914 if (msrs[i].host == msrs[i].guest)
9915 clear_atomic_switch_msr(vmx, msrs[i].msr);
9917 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
9921 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
9923 struct vcpu_vmx *vmx = to_vmx(vcpu);
9927 if (vmx->hv_deadline_tsc == -1)
9931 if (vmx->hv_deadline_tsc > tscl)
9932 /* sure to be 32 bit only because checked on set_hv_timer */
9933 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
9934 cpu_preemption_timer_multi);
9938 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9941 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
9943 struct vcpu_vmx *vmx = to_vmx(vcpu);
9944 unsigned long cr3, cr4, evmcs_rsp;
9946 /* Record the guest's net vcpu time for enforced NMI injections. */
9947 if (unlikely(!enable_vnmi &&
9948 vmx->loaded_vmcs->soft_vnmi_blocked))
9949 vmx->loaded_vmcs->entry_time = ktime_get();
9951 /* Don't enter VMX if guest state is invalid, let the exit handler
9952 start emulation until we arrive back to a valid state */
9953 if (vmx->emulation_required)
9956 if (vmx->ple_window_dirty) {
9957 vmx->ple_window_dirty = false;
9958 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9961 if (vmx->nested.sync_shadow_vmcs) {
9962 copy_vmcs12_to_shadow(vmx);
9963 vmx->nested.sync_shadow_vmcs = false;
9966 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9967 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9968 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9969 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9971 cr3 = __get_current_cr3_fast();
9972 if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) {
9973 vmcs_writel(HOST_CR3, cr3);
9974 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
9977 cr4 = cr4_read_shadow();
9978 if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) {
9979 vmcs_writel(HOST_CR4, cr4);
9980 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
9983 /* When single-stepping over STI and MOV SS, we must clear the
9984 * corresponding interruptibility bits in the guest state. Otherwise
9985 * vmentry fails as it then expects bit 14 (BS) in pending debug
9986 * exceptions being set, but that's not correct for the guest debugging
9988 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9989 vmx_set_interrupt_shadow(vcpu, 0);
9991 if (static_cpu_has(X86_FEATURE_PKU) &&
9992 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
9993 vcpu->arch.pkru != vmx->host_pkru)
9994 __write_pkru(vcpu->arch.pkru);
9996 atomic_switch_perf_msrs(vmx);
9998 vmx_arm_hv_timer(vcpu);
10001 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
10002 * it's non-zero. Since vmentry is serialising on affected CPUs, there
10003 * is no need to worry about the conditional branch over the wrmsr
10004 * being speculatively taken.
10006 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
10008 vmx->__launched = vmx->loaded_vmcs->launched;
10010 evmcs_rsp = static_branch_unlikely(&enable_evmcs) ?
10011 (unsigned long)¤t_evmcs->host_rsp : 0;
10014 /* Store host registers */
10015 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
10016 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
10017 "push %%" _ASM_CX " \n\t"
10018 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10020 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10021 /* Avoid VMWRITE when Enlightened VMCS is in use */
10022 "test %%" _ASM_SI ", %%" _ASM_SI " \n\t"
10024 "mov %%" _ASM_SP ", (%%" _ASM_SI ") \n\t"
10027 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
10029 /* Reload cr2 if changed */
10030 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
10031 "mov %%cr2, %%" _ASM_DX " \n\t"
10032 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
10034 "mov %%" _ASM_AX", %%cr2 \n\t"
10036 /* Check if vmlaunch of vmresume is needed */
10037 "cmpl $0, %c[launched](%0) \n\t"
10038 /* Load guest registers. Don't clobber flags. */
10039 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
10040 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
10041 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
10042 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
10043 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
10044 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
10045 #ifdef CONFIG_X86_64
10046 "mov %c[r8](%0), %%r8 \n\t"
10047 "mov %c[r9](%0), %%r9 \n\t"
10048 "mov %c[r10](%0), %%r10 \n\t"
10049 "mov %c[r11](%0), %%r11 \n\t"
10050 "mov %c[r12](%0), %%r12 \n\t"
10051 "mov %c[r13](%0), %%r13 \n\t"
10052 "mov %c[r14](%0), %%r14 \n\t"
10053 "mov %c[r15](%0), %%r15 \n\t"
10055 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
10057 /* Enter guest mode */
10059 __ex(ASM_VMX_VMLAUNCH) "\n\t"
10061 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
10063 /* Save guest registers, load host registers, keep flags */
10064 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
10066 "setbe %c[fail](%0)\n\t"
10067 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
10068 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
10069 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
10070 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
10071 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
10072 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
10073 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
10074 #ifdef CONFIG_X86_64
10075 "mov %%r8, %c[r8](%0) \n\t"
10076 "mov %%r9, %c[r9](%0) \n\t"
10077 "mov %%r10, %c[r10](%0) \n\t"
10078 "mov %%r11, %c[r11](%0) \n\t"
10079 "mov %%r12, %c[r12](%0) \n\t"
10080 "mov %%r13, %c[r13](%0) \n\t"
10081 "mov %%r14, %c[r14](%0) \n\t"
10082 "mov %%r15, %c[r15](%0) \n\t"
10083 "xor %%r8d, %%r8d \n\t"
10084 "xor %%r9d, %%r9d \n\t"
10085 "xor %%r10d, %%r10d \n\t"
10086 "xor %%r11d, %%r11d \n\t"
10087 "xor %%r12d, %%r12d \n\t"
10088 "xor %%r13d, %%r13d \n\t"
10089 "xor %%r14d, %%r14d \n\t"
10090 "xor %%r15d, %%r15d \n\t"
10092 "mov %%cr2, %%" _ASM_AX " \n\t"
10093 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
10095 "xor %%eax, %%eax \n\t"
10096 "xor %%ebx, %%ebx \n\t"
10097 "xor %%esi, %%esi \n\t"
10098 "xor %%edi, %%edi \n\t"
10099 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
10100 ".pushsection .rodata \n\t"
10101 ".global vmx_return \n\t"
10102 "vmx_return: " _ASM_PTR " 2b \n\t"
10104 : : "c"(vmx), "d"((unsigned long)HOST_RSP), "S"(evmcs_rsp),
10105 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
10106 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
10107 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
10108 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
10109 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
10110 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
10111 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
10112 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
10113 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
10114 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
10115 #ifdef CONFIG_X86_64
10116 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
10117 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
10118 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
10119 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
10120 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
10121 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
10122 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
10123 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
10125 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
10126 [wordsize]"i"(sizeof(ulong))
10128 #ifdef CONFIG_X86_64
10129 , "rax", "rbx", "rdi"
10130 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
10132 , "eax", "ebx", "edi"
10137 * We do not use IBRS in the kernel. If this vCPU has used the
10138 * SPEC_CTRL MSR it may have left it on; save the value and
10139 * turn it off. This is much more efficient than blindly adding
10140 * it to the atomic save/restore list. Especially as the former
10141 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
10143 * For non-nested case:
10144 * If the L01 MSR bitmap does not intercept the MSR, then we need to
10148 * If the L02 MSR bitmap does not intercept the MSR, then we need to
10151 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
10152 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
10154 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
10156 /* Eliminate branch target predictions from guest mode */
10159 /* All fields are clean at this point */
10160 if (static_branch_unlikely(&enable_evmcs))
10161 current_evmcs->hv_clean_fields |=
10162 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
10164 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
10165 if (vmx->host_debugctlmsr)
10166 update_debugctlmsr(vmx->host_debugctlmsr);
10168 #ifndef CONFIG_X86_64
10170 * The sysexit path does not restore ds/es, so we must set them to
10171 * a reasonable value ourselves.
10173 * We can't defer this to vmx_load_host_state() since that function
10174 * may be executed in interrupt context, which saves and restore segments
10175 * around it, nullifying its effect.
10177 loadsegment(ds, __USER_DS);
10178 loadsegment(es, __USER_DS);
10181 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
10182 | (1 << VCPU_EXREG_RFLAGS)
10183 | (1 << VCPU_EXREG_PDPTR)
10184 | (1 << VCPU_EXREG_SEGMENTS)
10185 | (1 << VCPU_EXREG_CR3));
10186 vcpu->arch.regs_dirty = 0;
10189 * eager fpu is enabled if PKEY is supported and CR4 is switched
10190 * back on host, so it is safe to read guest PKRU from current
10193 if (static_cpu_has(X86_FEATURE_PKU) &&
10194 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
10195 vcpu->arch.pkru = __read_pkru();
10196 if (vcpu->arch.pkru != vmx->host_pkru)
10197 __write_pkru(vmx->host_pkru);
10200 vmx->nested.nested_run_pending = 0;
10201 vmx->idt_vectoring_info = 0;
10203 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
10204 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
10207 vmx->loaded_vmcs->launched = 1;
10208 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
10210 vmx_complete_atomic_exit(vmx);
10211 vmx_recover_nmi_blocking(vmx);
10212 vmx_complete_interrupts(vmx);
10214 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
10216 static struct kvm *vmx_vm_alloc(void)
10218 struct kvm_vmx *kvm_vmx = vzalloc(sizeof(struct kvm_vmx));
10219 return &kvm_vmx->kvm;
10222 static void vmx_vm_free(struct kvm *kvm)
10224 vfree(to_kvm_vmx(kvm));
10227 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
10229 struct vcpu_vmx *vmx = to_vmx(vcpu);
10232 if (vmx->loaded_vmcs == vmcs)
10236 vmx->loaded_vmcs = vmcs;
10237 vmx_vcpu_put(vcpu);
10238 vmx_vcpu_load(vcpu, cpu);
10243 * Ensure that the current vmcs of the logical processor is the
10244 * vmcs01 of the vcpu before calling free_nested().
10246 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
10248 struct vcpu_vmx *vmx = to_vmx(vcpu);
10251 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10256 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
10258 struct vcpu_vmx *vmx = to_vmx(vcpu);
10261 vmx_destroy_pml_buffer(vmx);
10262 free_vpid(vmx->vpid);
10263 leave_guest_mode(vcpu);
10264 vmx_free_vcpu_nested(vcpu);
10265 free_loaded_vmcs(vmx->loaded_vmcs);
10266 kfree(vmx->guest_msrs);
10267 kvm_vcpu_uninit(vcpu);
10268 kmem_cache_free(kvm_vcpu_cache, vmx);
10271 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
10274 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
10275 unsigned long *msr_bitmap;
10279 return ERR_PTR(-ENOMEM);
10281 vmx->vpid = allocate_vpid();
10283 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
10290 * If PML is turned on, failure on enabling PML just results in failure
10291 * of creating the vcpu, therefore we can simplify PML logic (by
10292 * avoiding dealing with cases, such as enabling PML partially on vcpus
10293 * for the guest, etc.
10296 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
10301 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
10302 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
10305 if (!vmx->guest_msrs)
10308 err = alloc_loaded_vmcs(&vmx->vmcs01);
10312 msr_bitmap = vmx->vmcs01.msr_bitmap;
10313 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
10314 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
10315 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
10316 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
10317 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
10318 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
10319 vmx->msr_bitmap_mode = 0;
10321 vmx->loaded_vmcs = &vmx->vmcs01;
10323 vmx_vcpu_load(&vmx->vcpu, cpu);
10324 vmx->vcpu.cpu = cpu;
10325 vmx_vcpu_setup(vmx);
10326 vmx_vcpu_put(&vmx->vcpu);
10328 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
10329 err = alloc_apic_access_page(kvm);
10334 if (enable_ept && !enable_unrestricted_guest) {
10335 err = init_rmode_identity_map(kvm);
10341 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
10342 kvm_vcpu_apicv_active(&vmx->vcpu));
10343 vmx->nested.vpid02 = allocate_vpid();
10346 vmx->nested.posted_intr_nv = -1;
10347 vmx->nested.current_vmptr = -1ull;
10349 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
10352 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
10353 * or POSTED_INTR_WAKEUP_VECTOR.
10355 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
10356 vmx->pi_desc.sn = 1;
10361 free_vpid(vmx->nested.vpid02);
10362 free_loaded_vmcs(vmx->loaded_vmcs);
10364 kfree(vmx->guest_msrs);
10366 vmx_destroy_pml_buffer(vmx);
10368 kvm_vcpu_uninit(&vmx->vcpu);
10370 free_vpid(vmx->vpid);
10371 kmem_cache_free(kvm_vcpu_cache, vmx);
10372 return ERR_PTR(err);
10375 static int vmx_vm_init(struct kvm *kvm)
10378 kvm->arch.pause_in_guest = true;
10382 static void __init vmx_check_processor_compat(void *rtn)
10384 struct vmcs_config vmcs_conf;
10387 if (setup_vmcs_config(&vmcs_conf) < 0)
10388 *(int *)rtn = -EIO;
10389 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, enable_apicv);
10390 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
10391 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
10392 smp_processor_id());
10393 *(int *)rtn = -EIO;
10397 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
10402 /* For VT-d and EPT combination
10403 * 1. MMIO: always map as UC
10404 * 2. EPT with VT-d:
10405 * a. VT-d without snooping control feature: can't guarantee the
10406 * result, try to trust guest.
10407 * b. VT-d with snooping control feature: snooping control feature of
10408 * VT-d engine can guarantee the cache correctness. Just set it
10409 * to WB to keep consistent with host. So the same as item 3.
10410 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
10411 * consistent with host MTRR
10414 cache = MTRR_TYPE_UNCACHABLE;
10418 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
10419 ipat = VMX_EPT_IPAT_BIT;
10420 cache = MTRR_TYPE_WRBACK;
10424 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
10425 ipat = VMX_EPT_IPAT_BIT;
10426 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
10427 cache = MTRR_TYPE_WRBACK;
10429 cache = MTRR_TYPE_UNCACHABLE;
10433 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
10436 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
10439 static int vmx_get_lpage_level(void)
10441 if (enable_ept && !cpu_has_vmx_ept_1g_page())
10442 return PT_DIRECTORY_LEVEL;
10444 /* For shadow and EPT supported 1GB page */
10445 return PT_PDPE_LEVEL;
10448 static void vmcs_set_secondary_exec_control(u32 new_ctl)
10451 * These bits in the secondary execution controls field
10452 * are dynamic, the others are mostly based on the hypervisor
10453 * architecture and the guest's CPUID. Do not touch the
10457 SECONDARY_EXEC_SHADOW_VMCS |
10458 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
10459 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10460 SECONDARY_EXEC_DESC;
10462 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
10464 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
10465 (new_ctl & ~mask) | (cur_ctl & mask));
10469 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
10470 * (indicating "allowed-1") if they are supported in the guest's CPUID.
10472 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
10474 struct vcpu_vmx *vmx = to_vmx(vcpu);
10475 struct kvm_cpuid_entry2 *entry;
10477 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
10478 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
10480 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
10481 if (entry && (entry->_reg & (_cpuid_mask))) \
10482 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
10485 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
10486 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
10487 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
10488 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
10489 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
10490 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
10491 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
10492 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
10493 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
10494 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
10495 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
10496 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
10497 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
10498 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
10499 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
10501 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
10502 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
10503 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
10504 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
10505 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
10506 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
10508 #undef cr4_fixed1_update
10511 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
10513 struct vcpu_vmx *vmx = to_vmx(vcpu);
10515 if (cpu_has_secondary_exec_ctrls()) {
10516 vmx_compute_secondary_exec_control(vmx);
10517 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
10520 if (nested_vmx_allowed(vcpu))
10521 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
10522 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
10524 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
10525 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
10527 if (nested_vmx_allowed(vcpu))
10528 nested_vmx_cr_fixed1_bits_update(vcpu);
10531 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
10533 if (func == 1 && nested)
10534 entry->ecx |= bit(X86_FEATURE_VMX);
10537 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
10538 struct x86_exception *fault)
10540 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10541 struct vcpu_vmx *vmx = to_vmx(vcpu);
10543 unsigned long exit_qualification = vcpu->arch.exit_qualification;
10545 if (vmx->nested.pml_full) {
10546 exit_reason = EXIT_REASON_PML_FULL;
10547 vmx->nested.pml_full = false;
10548 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
10549 } else if (fault->error_code & PFERR_RSVD_MASK)
10550 exit_reason = EXIT_REASON_EPT_MISCONFIG;
10552 exit_reason = EXIT_REASON_EPT_VIOLATION;
10554 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
10555 vmcs12->guest_physical_address = fault->address;
10558 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
10560 return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
10563 /* Callbacks for nested_ept_init_mmu_context: */
10565 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
10567 /* return the page table to be shadowed - in our case, EPT12 */
10568 return get_vmcs12(vcpu)->ept_pointer;
10571 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
10573 WARN_ON(mmu_is_nested(vcpu));
10574 if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
10577 kvm_mmu_unload(vcpu);
10578 kvm_init_shadow_ept_mmu(vcpu,
10579 to_vmx(vcpu)->nested.msrs.ept_caps &
10580 VMX_EPT_EXECUTE_ONLY_BIT,
10581 nested_ept_ad_enabled(vcpu));
10582 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
10583 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
10584 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
10586 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
10590 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
10592 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
10595 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
10598 bool inequality, bit;
10600 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
10602 (error_code & vmcs12->page_fault_error_code_mask) !=
10603 vmcs12->page_fault_error_code_match;
10604 return inequality ^ bit;
10607 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
10608 struct x86_exception *fault)
10610 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10612 WARN_ON(!is_guest_mode(vcpu));
10614 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
10615 !to_vmx(vcpu)->nested.nested_run_pending) {
10616 vmcs12->vm_exit_intr_error_code = fault->error_code;
10617 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10618 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
10619 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
10622 kvm_inject_page_fault(vcpu, fault);
10626 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10627 struct vmcs12 *vmcs12);
10629 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
10630 struct vmcs12 *vmcs12)
10632 struct vcpu_vmx *vmx = to_vmx(vcpu);
10636 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10638 * Translate L1 physical address to host physical
10639 * address for vmcs02. Keep the page pinned, so this
10640 * physical address remains valid. We keep a reference
10641 * to it so we can release it later.
10643 if (vmx->nested.apic_access_page) { /* shouldn't happen */
10644 kvm_release_page_dirty(vmx->nested.apic_access_page);
10645 vmx->nested.apic_access_page = NULL;
10647 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
10649 * If translation failed, no matter: This feature asks
10650 * to exit when accessing the given address, and if it
10651 * can never be accessed, this feature won't do
10654 if (!is_error_page(page)) {
10655 vmx->nested.apic_access_page = page;
10656 hpa = page_to_phys(vmx->nested.apic_access_page);
10657 vmcs_write64(APIC_ACCESS_ADDR, hpa);
10659 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
10660 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10664 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
10665 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
10666 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
10667 vmx->nested.virtual_apic_page = NULL;
10669 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
10672 * If translation failed, VM entry will fail because
10673 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
10674 * Failing the vm entry is _not_ what the processor
10675 * does but it's basically the only possibility we
10676 * have. We could still enter the guest if CR8 load
10677 * exits are enabled, CR8 store exits are enabled, and
10678 * virtualize APIC access is disabled; in this case
10679 * the processor would never use the TPR shadow and we
10680 * could simply clear the bit from the execution
10681 * control. But such a configuration is useless, so
10682 * let's keep the code simple.
10684 if (!is_error_page(page)) {
10685 vmx->nested.virtual_apic_page = page;
10686 hpa = page_to_phys(vmx->nested.virtual_apic_page);
10687 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
10691 if (nested_cpu_has_posted_intr(vmcs12)) {
10692 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
10693 kunmap(vmx->nested.pi_desc_page);
10694 kvm_release_page_dirty(vmx->nested.pi_desc_page);
10695 vmx->nested.pi_desc_page = NULL;
10697 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
10698 if (is_error_page(page))
10700 vmx->nested.pi_desc_page = page;
10701 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
10702 vmx->nested.pi_desc =
10703 (struct pi_desc *)((void *)vmx->nested.pi_desc +
10704 (unsigned long)(vmcs12->posted_intr_desc_addr &
10706 vmcs_write64(POSTED_INTR_DESC_ADDR,
10707 page_to_phys(vmx->nested.pi_desc_page) +
10708 (unsigned long)(vmcs12->posted_intr_desc_addr &
10711 if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
10712 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
10713 CPU_BASED_USE_MSR_BITMAPS);
10715 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
10716 CPU_BASED_USE_MSR_BITMAPS);
10719 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
10721 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
10722 struct vcpu_vmx *vmx = to_vmx(vcpu);
10724 if (vcpu->arch.virtual_tsc_khz == 0)
10727 /* Make sure short timeouts reliably trigger an immediate vmexit.
10728 * hrtimer_start does not guarantee this. */
10729 if (preemption_timeout <= 1) {
10730 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
10734 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10735 preemption_timeout *= 1000000;
10736 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
10737 hrtimer_start(&vmx->nested.preemption_timer,
10738 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
10741 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
10742 struct vmcs12 *vmcs12)
10744 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
10747 if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
10748 !page_address_valid(vcpu, vmcs12->io_bitmap_b))
10754 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
10755 struct vmcs12 *vmcs12)
10757 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10760 if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
10766 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
10767 struct vmcs12 *vmcs12)
10769 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10772 if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
10779 * Merge L0's and L1's MSR bitmap, return false to indicate that
10780 * we do not use the hardware.
10782 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10783 struct vmcs12 *vmcs12)
10787 unsigned long *msr_bitmap_l1;
10788 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
10790 * pred_cmd & spec_ctrl are trying to verify two things:
10792 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
10793 * ensures that we do not accidentally generate an L02 MSR bitmap
10794 * from the L12 MSR bitmap that is too permissive.
10795 * 2. That L1 or L2s have actually used the MSR. This avoids
10796 * unnecessarily merging of the bitmap if the MSR is unused. This
10797 * works properly because we only update the L01 MSR bitmap lazily.
10798 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only
10799 * updated to reflect this when L1 (or its L2s) actually write to
10802 bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
10803 bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
10805 /* Nothing to do if the MSR bitmap is not in use. */
10806 if (!cpu_has_vmx_msr_bitmap() ||
10807 !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10810 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10811 !pred_cmd && !spec_ctrl)
10814 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
10815 if (is_error_page(page))
10818 msr_bitmap_l1 = (unsigned long *)kmap(page);
10819 if (nested_cpu_has_apic_reg_virt(vmcs12)) {
10821 * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it
10822 * just lets the processor take the value from the virtual-APIC page;
10823 * take those 256 bits directly from the L1 bitmap.
10825 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10826 unsigned word = msr / BITS_PER_LONG;
10827 msr_bitmap_l0[word] = msr_bitmap_l1[word];
10828 msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10831 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10832 unsigned word = msr / BITS_PER_LONG;
10833 msr_bitmap_l0[word] = ~0;
10834 msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10838 nested_vmx_disable_intercept_for_msr(
10839 msr_bitmap_l1, msr_bitmap_l0,
10840 X2APIC_MSR(APIC_TASKPRI),
10843 if (nested_cpu_has_vid(vmcs12)) {
10844 nested_vmx_disable_intercept_for_msr(
10845 msr_bitmap_l1, msr_bitmap_l0,
10846 X2APIC_MSR(APIC_EOI),
10848 nested_vmx_disable_intercept_for_msr(
10849 msr_bitmap_l1, msr_bitmap_l0,
10850 X2APIC_MSR(APIC_SELF_IPI),
10855 nested_vmx_disable_intercept_for_msr(
10856 msr_bitmap_l1, msr_bitmap_l0,
10857 MSR_IA32_SPEC_CTRL,
10858 MSR_TYPE_R | MSR_TYPE_W);
10861 nested_vmx_disable_intercept_for_msr(
10862 msr_bitmap_l1, msr_bitmap_l0,
10867 kvm_release_page_clean(page);
10872 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu,
10873 struct vmcs12 *vmcs12)
10875 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
10876 !page_address_valid(vcpu, vmcs12->apic_access_addr))
10882 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
10883 struct vmcs12 *vmcs12)
10885 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10886 !nested_cpu_has_apic_reg_virt(vmcs12) &&
10887 !nested_cpu_has_vid(vmcs12) &&
10888 !nested_cpu_has_posted_intr(vmcs12))
10892 * If virtualize x2apic mode is enabled,
10893 * virtualize apic access must be disabled.
10895 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10896 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
10900 * If virtual interrupt delivery is enabled,
10901 * we must exit on external interrupts.
10903 if (nested_cpu_has_vid(vmcs12) &&
10904 !nested_exit_on_intr(vcpu))
10908 * bits 15:8 should be zero in posted_intr_nv,
10909 * the descriptor address has been already checked
10910 * in nested_get_vmcs12_pages.
10912 if (nested_cpu_has_posted_intr(vmcs12) &&
10913 (!nested_cpu_has_vid(vmcs12) ||
10914 !nested_exit_intr_ack_set(vcpu) ||
10915 vmcs12->posted_intr_nv & 0xff00))
10918 /* tpr shadow is needed by all apicv features. */
10919 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10925 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
10926 unsigned long count_field,
10927 unsigned long addr_field)
10932 if (vmcs12_read_any(vcpu, count_field, &count) ||
10933 vmcs12_read_any(vcpu, addr_field, &addr)) {
10939 maxphyaddr = cpuid_maxphyaddr(vcpu);
10940 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
10941 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
10942 pr_debug_ratelimited(
10943 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10944 addr_field, maxphyaddr, count, addr);
10950 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
10951 struct vmcs12 *vmcs12)
10953 if (vmcs12->vm_exit_msr_load_count == 0 &&
10954 vmcs12->vm_exit_msr_store_count == 0 &&
10955 vmcs12->vm_entry_msr_load_count == 0)
10956 return 0; /* Fast path */
10957 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
10958 VM_EXIT_MSR_LOAD_ADDR) ||
10959 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
10960 VM_EXIT_MSR_STORE_ADDR) ||
10961 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
10962 VM_ENTRY_MSR_LOAD_ADDR))
10967 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
10968 struct vmcs12 *vmcs12)
10970 u64 address = vmcs12->pml_address;
10971 int maxphyaddr = cpuid_maxphyaddr(vcpu);
10973 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
10974 if (!nested_cpu_has_ept(vmcs12) ||
10975 !IS_ALIGNED(address, 4096) ||
10976 address >> maxphyaddr)
10983 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
10984 struct vmx_msr_entry *e)
10986 /* x2APIC MSR accesses are not allowed */
10987 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
10989 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
10990 e->index == MSR_IA32_UCODE_REV)
10992 if (e->reserved != 0)
10997 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
10998 struct vmx_msr_entry *e)
11000 if (e->index == MSR_FS_BASE ||
11001 e->index == MSR_GS_BASE ||
11002 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
11003 nested_vmx_msr_check_common(vcpu, e))
11008 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
11009 struct vmx_msr_entry *e)
11011 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
11012 nested_vmx_msr_check_common(vcpu, e))
11018 * Load guest's/host's msr at nested entry/exit.
11019 * return 0 for success, entry index for failure.
11021 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11024 struct vmx_msr_entry e;
11025 struct msr_data msr;
11027 msr.host_initiated = false;
11028 for (i = 0; i < count; i++) {
11029 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
11031 pr_debug_ratelimited(
11032 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11033 __func__, i, gpa + i * sizeof(e));
11036 if (nested_vmx_load_msr_check(vcpu, &e)) {
11037 pr_debug_ratelimited(
11038 "%s check failed (%u, 0x%x, 0x%x)\n",
11039 __func__, i, e.index, e.reserved);
11042 msr.index = e.index;
11043 msr.data = e.value;
11044 if (kvm_set_msr(vcpu, &msr)) {
11045 pr_debug_ratelimited(
11046 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11047 __func__, i, e.index, e.value);
11056 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11059 struct vmx_msr_entry e;
11061 for (i = 0; i < count; i++) {
11062 struct msr_data msr_info;
11063 if (kvm_vcpu_read_guest(vcpu,
11064 gpa + i * sizeof(e),
11065 &e, 2 * sizeof(u32))) {
11066 pr_debug_ratelimited(
11067 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11068 __func__, i, gpa + i * sizeof(e));
11071 if (nested_vmx_store_msr_check(vcpu, &e)) {
11072 pr_debug_ratelimited(
11073 "%s check failed (%u, 0x%x, 0x%x)\n",
11074 __func__, i, e.index, e.reserved);
11077 msr_info.host_initiated = false;
11078 msr_info.index = e.index;
11079 if (kvm_get_msr(vcpu, &msr_info)) {
11080 pr_debug_ratelimited(
11081 "%s cannot read MSR (%u, 0x%x)\n",
11082 __func__, i, e.index);
11085 if (kvm_vcpu_write_guest(vcpu,
11086 gpa + i * sizeof(e) +
11087 offsetof(struct vmx_msr_entry, value),
11088 &msr_info.data, sizeof(msr_info.data))) {
11089 pr_debug_ratelimited(
11090 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11091 __func__, i, e.index, msr_info.data);
11098 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
11100 unsigned long invalid_mask;
11102 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
11103 return (val & invalid_mask) == 0;
11107 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
11108 * emulating VM entry into a guest with EPT enabled.
11109 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
11110 * is assigned to entry_failure_code on failure.
11112 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
11113 u32 *entry_failure_code)
11115 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
11116 if (!nested_cr3_valid(vcpu, cr3)) {
11117 *entry_failure_code = ENTRY_FAIL_DEFAULT;
11122 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
11123 * must not be dereferenced.
11125 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
11127 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
11128 *entry_failure_code = ENTRY_FAIL_PDPTE;
11133 vcpu->arch.cr3 = cr3;
11134 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
11137 kvm_mmu_reset_context(vcpu);
11141 static void prepare_vmcs02_full(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11143 struct vcpu_vmx *vmx = to_vmx(vcpu);
11145 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
11146 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
11147 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
11148 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
11149 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
11150 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
11151 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
11152 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
11153 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
11154 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
11155 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
11156 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
11157 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
11158 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
11159 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
11160 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
11161 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
11162 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
11163 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
11164 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
11165 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
11166 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
11167 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
11168 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
11169 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
11170 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
11171 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
11172 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
11173 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
11174 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
11175 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
11177 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
11178 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
11179 vmcs12->guest_pending_dbg_exceptions);
11180 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
11181 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
11183 if (nested_cpu_has_xsaves(vmcs12))
11184 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
11185 vmcs_write64(VMCS_LINK_POINTER, -1ull);
11187 if (cpu_has_vmx_posted_intr())
11188 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
11191 * Whether page-faults are trapped is determined by a combination of
11192 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
11193 * If enable_ept, L0 doesn't care about page faults and we should
11194 * set all of these to L1's desires. However, if !enable_ept, L0 does
11195 * care about (at least some) page faults, and because it is not easy
11196 * (if at all possible?) to merge L0 and L1's desires, we simply ask
11197 * to exit on each and every L2 page fault. This is done by setting
11198 * MASK=MATCH=0 and (see below) EB.PF=1.
11199 * Note that below we don't need special code to set EB.PF beyond the
11200 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
11201 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
11202 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
11204 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
11205 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
11206 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
11207 enable_ept ? vmcs12->page_fault_error_code_match : 0);
11209 /* All VMFUNCs are currently emulated through L0 vmexits. */
11210 if (cpu_has_vmx_vmfunc())
11211 vmcs_write64(VM_FUNCTION_CONTROL, 0);
11213 if (cpu_has_vmx_apicv()) {
11214 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
11215 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
11216 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
11217 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
11221 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
11222 * Some constant fields are set here by vmx_set_constant_host_state().
11223 * Other fields are different per CPU, and will be set later when
11224 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
11226 vmx_set_constant_host_state(vmx);
11229 * Set the MSR load/store lists to match L0's settings.
11231 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
11232 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11233 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
11234 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11235 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
11237 set_cr4_guest_host_mask(vmx);
11239 if (vmx_mpx_supported())
11240 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
11243 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
11244 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
11246 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
11250 * L1 may access the L2's PDPTR, so save them to construct vmcs12
11253 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
11254 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
11255 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
11256 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
11259 if (cpu_has_vmx_msr_bitmap())
11260 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
11264 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
11265 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
11266 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
11267 * guest in a way that will both be appropriate to L1's requests, and our
11268 * needs. In addition to modifying the active vmcs (which is vmcs02), this
11269 * function also has additional necessary side-effects, like setting various
11270 * vcpu->arch fields.
11271 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
11272 * is assigned to entry_failure_code on failure.
11274 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11275 u32 *entry_failure_code)
11277 struct vcpu_vmx *vmx = to_vmx(vcpu);
11278 u32 exec_control, vmcs12_exec_ctrl;
11280 if (vmx->nested.dirty_vmcs12) {
11281 prepare_vmcs02_full(vcpu, vmcs12);
11282 vmx->nested.dirty_vmcs12 = false;
11286 * First, the fields that are shadowed. This must be kept in sync
11287 * with vmx_shadow_fields.h.
11290 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
11291 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
11292 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
11293 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
11294 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
11297 * Not in vmcs02: GUEST_PML_INDEX, HOST_FS_SELECTOR, HOST_GS_SELECTOR,
11298 * HOST_FS_BASE, HOST_GS_BASE.
11301 if (vmx->nested.nested_run_pending &&
11302 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
11303 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
11304 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
11306 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
11307 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
11309 if (vmx->nested.nested_run_pending) {
11310 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
11311 vmcs12->vm_entry_intr_info_field);
11312 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
11313 vmcs12->vm_entry_exception_error_code);
11314 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
11315 vmcs12->vm_entry_instruction_len);
11316 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
11317 vmcs12->guest_interruptibility_info);
11318 vmx->loaded_vmcs->nmi_known_unmasked =
11319 !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
11321 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
11323 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
11325 exec_control = vmcs12->pin_based_vm_exec_control;
11327 /* Preemption timer setting is only taken from vmcs01. */
11328 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
11329 exec_control |= vmcs_config.pin_based_exec_ctrl;
11330 if (vmx->hv_deadline_tsc == -1)
11331 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
11333 /* Posted interrupts setting is only taken from vmcs12. */
11334 if (nested_cpu_has_posted_intr(vmcs12)) {
11335 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
11336 vmx->nested.pi_pending = false;
11338 exec_control &= ~PIN_BASED_POSTED_INTR;
11341 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
11343 vmx->nested.preemption_timer_expired = false;
11344 if (nested_cpu_has_preemption_timer(vmcs12))
11345 vmx_start_preemption_timer(vcpu);
11347 if (cpu_has_secondary_exec_ctrls()) {
11348 exec_control = vmx->secondary_exec_control;
11350 /* Take the following fields only from vmcs12 */
11351 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
11352 SECONDARY_EXEC_ENABLE_INVPCID |
11353 SECONDARY_EXEC_RDTSCP |
11354 SECONDARY_EXEC_XSAVES |
11355 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
11356 SECONDARY_EXEC_APIC_REGISTER_VIRT |
11357 SECONDARY_EXEC_ENABLE_VMFUNC);
11358 if (nested_cpu_has(vmcs12,
11359 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
11360 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
11361 ~SECONDARY_EXEC_ENABLE_PML;
11362 exec_control |= vmcs12_exec_ctrl;
11365 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
11366 vmcs_write16(GUEST_INTR_STATUS,
11367 vmcs12->guest_intr_status);
11370 * Write an illegal value to APIC_ACCESS_ADDR. Later,
11371 * nested_get_vmcs12_pages will either fix it up or
11372 * remove the VM execution control.
11374 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
11375 vmcs_write64(APIC_ACCESS_ADDR, -1ull);
11377 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
11381 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
11382 * entry, but only if the current (host) sp changed from the value
11383 * we wrote last (vmx->host_rsp). This cache is no longer relevant
11384 * if we switch vmcs, and rather than hold a separate cache per vmcs,
11385 * here we just force the write to happen on entry.
11389 exec_control = vmx_exec_control(vmx); /* L0's desires */
11390 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
11391 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
11392 exec_control &= ~CPU_BASED_TPR_SHADOW;
11393 exec_control |= vmcs12->cpu_based_vm_exec_control;
11396 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
11397 * nested_get_vmcs12_pages can't fix it up, the illegal value
11398 * will result in a VM entry failure.
11400 if (exec_control & CPU_BASED_TPR_SHADOW) {
11401 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
11402 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
11404 #ifdef CONFIG_X86_64
11405 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
11406 CPU_BASED_CR8_STORE_EXITING;
11411 * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
11412 * for I/O port accesses.
11414 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
11415 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
11417 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
11419 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
11420 * bitwise-or of what L1 wants to trap for L2, and what we want to
11421 * trap. Note that CR0.TS also needs updating - we do this later.
11423 update_exception_bitmap(vcpu);
11424 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
11425 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
11427 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
11428 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
11429 * bits are further modified by vmx_set_efer() below.
11431 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
11433 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
11434 * emulated by vmx_set_efer(), below.
11436 vm_entry_controls_init(vmx,
11437 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
11438 ~VM_ENTRY_IA32E_MODE) |
11439 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
11441 if (vmx->nested.nested_run_pending &&
11442 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
11443 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
11444 vcpu->arch.pat = vmcs12->guest_ia32_pat;
11445 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
11446 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
11449 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11451 if (kvm_has_tsc_control)
11452 decache_tsc_multiplier(vmx);
11456 * There is no direct mapping between vpid02 and vpid12, the
11457 * vpid02 is per-vCPU for L0 and reused while the value of
11458 * vpid12 is changed w/ one invvpid during nested vmentry.
11459 * The vpid12 is allocated by L1 for L2, so it will not
11460 * influence global bitmap(for vpid01 and vpid02 allocation)
11461 * even if spawn a lot of nested vCPUs.
11463 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
11464 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
11465 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
11466 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
11469 vmx_flush_tlb(vcpu, true);
11475 * Conceptually we want to copy the PML address and index from
11476 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
11477 * since we always flush the log on each vmexit, this happens
11478 * to be equivalent to simply resetting the fields in vmcs02.
11480 ASSERT(vmx->pml_pg);
11481 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
11482 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
11485 if (nested_cpu_has_ept(vmcs12)) {
11486 if (nested_ept_init_mmu_context(vcpu)) {
11487 *entry_failure_code = ENTRY_FAIL_DEFAULT;
11490 } else if (nested_cpu_has2(vmcs12,
11491 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11492 vmx_flush_tlb(vcpu, true);
11496 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
11497 * bits which we consider mandatory enabled.
11498 * The CR0_READ_SHADOW is what L2 should have expected to read given
11499 * the specifications by L1; It's not enough to take
11500 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
11501 * have more bits than L1 expected.
11503 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
11504 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
11506 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
11507 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
11509 if (vmx->nested.nested_run_pending &&
11510 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
11511 vcpu->arch.efer = vmcs12->guest_ia32_efer;
11512 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
11513 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11515 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11516 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
11517 vmx_set_efer(vcpu, vcpu->arch.efer);
11520 * Guest state is invalid and unrestricted guest is disabled,
11521 * which means L1 attempted VMEntry to L2 with invalid state.
11522 * Fail the VMEntry.
11524 if (vmx->emulation_required) {
11525 *entry_failure_code = ENTRY_FAIL_DEFAULT;
11529 /* Shadow page tables on either EPT or shadow page tables. */
11530 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
11531 entry_failure_code))
11535 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
11537 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
11538 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
11542 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12)
11544 if (!nested_cpu_has_nmi_exiting(vmcs12) &&
11545 nested_cpu_has_virtual_nmis(vmcs12))
11548 if (!nested_cpu_has_virtual_nmis(vmcs12) &&
11549 nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING))
11555 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11557 struct vcpu_vmx *vmx = to_vmx(vcpu);
11559 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
11560 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
11561 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11563 if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
11564 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11566 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
11567 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11569 if (nested_vmx_check_apic_access_controls(vcpu, vmcs12))
11570 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11572 if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
11573 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11575 if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
11576 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11578 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
11579 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11581 if (nested_vmx_check_pml_controls(vcpu, vmcs12))
11582 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11584 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
11585 vmx->nested.msrs.procbased_ctls_low,
11586 vmx->nested.msrs.procbased_ctls_high) ||
11587 (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
11588 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
11589 vmx->nested.msrs.secondary_ctls_low,
11590 vmx->nested.msrs.secondary_ctls_high)) ||
11591 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
11592 vmx->nested.msrs.pinbased_ctls_low,
11593 vmx->nested.msrs.pinbased_ctls_high) ||
11594 !vmx_control_verify(vmcs12->vm_exit_controls,
11595 vmx->nested.msrs.exit_ctls_low,
11596 vmx->nested.msrs.exit_ctls_high) ||
11597 !vmx_control_verify(vmcs12->vm_entry_controls,
11598 vmx->nested.msrs.entry_ctls_low,
11599 vmx->nested.msrs.entry_ctls_high))
11600 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11602 if (nested_vmx_check_nmi_controls(vmcs12))
11603 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11605 if (nested_cpu_has_vmfunc(vmcs12)) {
11606 if (vmcs12->vm_function_control &
11607 ~vmx->nested.msrs.vmfunc_controls)
11608 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11610 if (nested_cpu_has_eptp_switching(vmcs12)) {
11611 if (!nested_cpu_has_ept(vmcs12) ||
11612 !page_address_valid(vcpu, vmcs12->eptp_list_address))
11613 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11617 if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
11618 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11620 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
11621 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
11622 !nested_cr3_valid(vcpu, vmcs12->host_cr3))
11623 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
11628 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11633 *exit_qual = ENTRY_FAIL_DEFAULT;
11635 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
11636 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
11639 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
11640 vmcs12->vmcs_link_pointer != -1ull) {
11641 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
11646 * If the load IA32_EFER VM-entry control is 1, the following checks
11647 * are performed on the field for the IA32_EFER MSR:
11648 * - Bits reserved in the IA32_EFER MSR must be 0.
11649 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
11650 * the IA-32e mode guest VM-exit control. It must also be identical
11651 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
11654 if (to_vmx(vcpu)->nested.nested_run_pending &&
11655 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
11656 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
11657 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
11658 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
11659 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
11660 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
11665 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
11666 * IA32_EFER MSR must be 0 in the field for that register. In addition,
11667 * the values of the LMA and LME bits in the field must each be that of
11668 * the host address-space size VM-exit control.
11670 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
11671 ia32e = (vmcs12->vm_exit_controls &
11672 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
11673 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
11674 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
11675 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
11679 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
11680 (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) ||
11681 (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))
11687 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu)
11689 struct vcpu_vmx *vmx = to_vmx(vcpu);
11690 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11695 enter_guest_mode(vcpu);
11697 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
11698 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11700 vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
11701 vmx_segment_cache_clear(vmx);
11703 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
11704 vcpu->arch.tsc_offset += vmcs12->tsc_offset;
11706 r = EXIT_REASON_INVALID_STATE;
11707 if (prepare_vmcs02(vcpu, vmcs12, &exit_qual))
11710 nested_get_vmcs12_pages(vcpu, vmcs12);
11712 r = EXIT_REASON_MSR_LOAD_FAIL;
11713 msr_entry_idx = nested_vmx_load_msr(vcpu,
11714 vmcs12->vm_entry_msr_load_addr,
11715 vmcs12->vm_entry_msr_load_count);
11720 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
11721 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
11722 * returned as far as L1 is concerned. It will only return (and set
11723 * the success flag) when L2 exits (see nested_vmx_vmexit()).
11728 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
11729 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
11730 leave_guest_mode(vcpu);
11731 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11732 nested_vmx_entry_failure(vcpu, vmcs12, r, exit_qual);
11737 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
11738 * for running an L2 nested guest.
11740 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
11742 struct vmcs12 *vmcs12;
11743 struct vcpu_vmx *vmx = to_vmx(vcpu);
11744 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
11748 if (!nested_vmx_check_permission(vcpu))
11751 if (!nested_vmx_check_vmcs12(vcpu))
11754 vmcs12 = get_vmcs12(vcpu);
11756 if (enable_shadow_vmcs)
11757 copy_shadow_to_vmcs12(vmx);
11760 * The nested entry process starts with enforcing various prerequisites
11761 * on vmcs12 as required by the Intel SDM, and act appropriately when
11762 * they fail: As the SDM explains, some conditions should cause the
11763 * instruction to fail, while others will cause the instruction to seem
11764 * to succeed, but return an EXIT_REASON_INVALID_STATE.
11765 * To speed up the normal (success) code path, we should avoid checking
11766 * for misconfigurations which will anyway be caught by the processor
11767 * when using the merged vmcs02.
11769 if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
11770 nested_vmx_failValid(vcpu,
11771 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
11775 if (vmcs12->launch_state == launch) {
11776 nested_vmx_failValid(vcpu,
11777 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
11778 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
11782 ret = check_vmentry_prereqs(vcpu, vmcs12);
11784 nested_vmx_failValid(vcpu, ret);
11789 * After this point, the trap flag no longer triggers a singlestep trap
11790 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
11791 * This is not 100% correct; for performance reasons, we delegate most
11792 * of the checks on host state to the processor. If those fail,
11793 * the singlestep trap is missed.
11795 skip_emulated_instruction(vcpu);
11797 ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
11799 nested_vmx_entry_failure(vcpu, vmcs12,
11800 EXIT_REASON_INVALID_STATE, exit_qual);
11805 * We're finally done with prerequisite checking, and can start with
11806 * the nested entry.
11809 vmx->nested.nested_run_pending = 1;
11810 ret = enter_vmx_non_root_mode(vcpu);
11812 vmx->nested.nested_run_pending = 0;
11817 * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken
11818 * by event injection, halt vcpu.
11820 if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) &&
11821 !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK)) {
11822 vmx->nested.nested_run_pending = 0;
11823 return kvm_vcpu_halt(vcpu);
11828 return kvm_skip_emulated_instruction(vcpu);
11832 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11833 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11834 * This function returns the new value we should put in vmcs12.guest_cr0.
11835 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11836 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11837 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11838 * didn't trap the bit, because if L1 did, so would L0).
11839 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11840 * been modified by L2, and L1 knows it. So just leave the old value of
11841 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11842 * isn't relevant, because if L0 traps this bit it can set it to anything.
11843 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11844 * changed these bits, and therefore they need to be updated, but L0
11845 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11846 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11848 static inline unsigned long
11849 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11852 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
11853 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
11854 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
11855 vcpu->arch.cr0_guest_owned_bits));
11858 static inline unsigned long
11859 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11862 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
11863 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
11864 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
11865 vcpu->arch.cr4_guest_owned_bits));
11868 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
11869 struct vmcs12 *vmcs12)
11874 if (vcpu->arch.exception.injected) {
11875 nr = vcpu->arch.exception.nr;
11876 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11878 if (kvm_exception_is_soft(nr)) {
11879 vmcs12->vm_exit_instruction_len =
11880 vcpu->arch.event_exit_inst_len;
11881 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
11883 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
11885 if (vcpu->arch.exception.has_error_code) {
11886 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
11887 vmcs12->idt_vectoring_error_code =
11888 vcpu->arch.exception.error_code;
11891 vmcs12->idt_vectoring_info_field = idt_vectoring;
11892 } else if (vcpu->arch.nmi_injected) {
11893 vmcs12->idt_vectoring_info_field =
11894 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
11895 } else if (vcpu->arch.interrupt.injected) {
11896 nr = vcpu->arch.interrupt.nr;
11897 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11899 if (vcpu->arch.interrupt.soft) {
11900 idt_vectoring |= INTR_TYPE_SOFT_INTR;
11901 vmcs12->vm_entry_instruction_len =
11902 vcpu->arch.event_exit_inst_len;
11904 idt_vectoring |= INTR_TYPE_EXT_INTR;
11906 vmcs12->idt_vectoring_info_field = idt_vectoring;
11910 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
11912 struct vcpu_vmx *vmx = to_vmx(vcpu);
11913 unsigned long exit_qual;
11914 bool block_nested_events =
11915 vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
11917 if (vcpu->arch.exception.pending &&
11918 nested_vmx_check_exception(vcpu, &exit_qual)) {
11919 if (block_nested_events)
11921 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
11925 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
11926 vmx->nested.preemption_timer_expired) {
11927 if (block_nested_events)
11929 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
11933 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
11934 if (block_nested_events)
11936 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
11937 NMI_VECTOR | INTR_TYPE_NMI_INTR |
11938 INTR_INFO_VALID_MASK, 0);
11940 * The NMI-triggered VM exit counts as injection:
11941 * clear this one and block further NMIs.
11943 vcpu->arch.nmi_pending = 0;
11944 vmx_set_nmi_mask(vcpu, true);
11948 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
11949 nested_exit_on_intr(vcpu)) {
11950 if (block_nested_events)
11952 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
11956 vmx_complete_nested_posted_interrupt(vcpu);
11960 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
11962 ktime_t remaining =
11963 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
11966 if (ktime_to_ns(remaining) <= 0)
11969 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
11970 do_div(value, 1000000);
11971 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
11975 * Update the guest state fields of vmcs12 to reflect changes that
11976 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11977 * VM-entry controls is also updated, since this is really a guest
11980 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11982 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
11983 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
11985 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
11986 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
11987 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
11989 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
11990 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
11991 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
11992 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
11993 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
11994 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
11995 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
11996 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
11997 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
11998 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
11999 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
12000 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
12001 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
12002 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
12003 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
12004 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
12005 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
12006 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
12007 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
12008 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
12009 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
12010 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
12011 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
12012 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
12013 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
12014 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
12015 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
12016 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
12017 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
12018 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
12019 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
12020 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
12021 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
12022 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
12023 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
12024 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
12026 vmcs12->guest_interruptibility_info =
12027 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
12028 vmcs12->guest_pending_dbg_exceptions =
12029 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
12030 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
12031 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
12033 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
12035 if (nested_cpu_has_preemption_timer(vmcs12)) {
12036 if (vmcs12->vm_exit_controls &
12037 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
12038 vmcs12->vmx_preemption_timer_value =
12039 vmx_get_preemption_timer_value(vcpu);
12040 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
12044 * In some cases (usually, nested EPT), L2 is allowed to change its
12045 * own CR3 without exiting. If it has changed it, we must keep it.
12046 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
12047 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
12049 * Additionally, restore L2's PDPTR to vmcs12.
12052 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
12053 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
12054 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
12055 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
12056 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
12059 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
12061 if (nested_cpu_has_vid(vmcs12))
12062 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
12064 vmcs12->vm_entry_controls =
12065 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
12066 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
12068 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
12069 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
12070 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
12073 /* TODO: These cannot have changed unless we have MSR bitmaps and
12074 * the relevant bit asks not to trap the change */
12075 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
12076 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
12077 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
12078 vmcs12->guest_ia32_efer = vcpu->arch.efer;
12079 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
12080 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
12081 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
12082 if (kvm_mpx_supported())
12083 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
12087 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
12088 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
12089 * and this function updates it to reflect the changes to the guest state while
12090 * L2 was running (and perhaps made some exits which were handled directly by L0
12091 * without going back to L1), and to reflect the exit reason.
12092 * Note that we do not have to copy here all VMCS fields, just those that
12093 * could have changed by the L2 guest or the exit - i.e., the guest-state and
12094 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
12095 * which already writes to vmcs12 directly.
12097 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
12098 u32 exit_reason, u32 exit_intr_info,
12099 unsigned long exit_qualification)
12101 /* update guest state fields: */
12102 sync_vmcs12(vcpu, vmcs12);
12104 /* update exit information fields: */
12106 vmcs12->vm_exit_reason = exit_reason;
12107 vmcs12->exit_qualification = exit_qualification;
12108 vmcs12->vm_exit_intr_info = exit_intr_info;
12110 vmcs12->idt_vectoring_info_field = 0;
12111 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
12112 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
12114 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
12115 vmcs12->launch_state = 1;
12117 /* vm_entry_intr_info_field is cleared on exit. Emulate this
12118 * instead of reading the real value. */
12119 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
12122 * Transfer the event that L0 or L1 may wanted to inject into
12123 * L2 to IDT_VECTORING_INFO_FIELD.
12125 vmcs12_save_pending_event(vcpu, vmcs12);
12129 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
12130 * preserved above and would only end up incorrectly in L1.
12132 vcpu->arch.nmi_injected = false;
12133 kvm_clear_exception_queue(vcpu);
12134 kvm_clear_interrupt_queue(vcpu);
12137 static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu,
12138 struct vmcs12 *vmcs12)
12140 u32 entry_failure_code;
12142 nested_ept_uninit_mmu_context(vcpu);
12145 * Only PDPTE load can fail as the value of cr3 was checked on entry and
12146 * couldn't have changed.
12148 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
12149 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
12152 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
12156 * A part of what we need to when the nested L2 guest exits and we want to
12157 * run its L1 parent, is to reset L1's guest state to the host state specified
12159 * This function is to be called not only on normal nested exit, but also on
12160 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
12161 * Failures During or After Loading Guest State").
12162 * This function should be called when the active VMCS is L1's (vmcs01).
12164 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
12165 struct vmcs12 *vmcs12)
12167 struct kvm_segment seg;
12169 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
12170 vcpu->arch.efer = vmcs12->host_ia32_efer;
12171 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
12172 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
12174 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
12175 vmx_set_efer(vcpu, vcpu->arch.efer);
12177 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
12178 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
12179 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
12181 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
12182 * actually changed, because vmx_set_cr0 refers to efer set above.
12184 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
12185 * (KVM doesn't change it);
12187 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
12188 vmx_set_cr0(vcpu, vmcs12->host_cr0);
12190 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
12191 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
12192 vmx_set_cr4(vcpu, vmcs12->host_cr4);
12194 load_vmcs12_mmu_host_state(vcpu, vmcs12);
12197 * If vmcs01 don't use VPID, CPU flushes TLB on every
12198 * VMEntry/VMExit. Thus, no need to flush TLB.
12200 * If vmcs12 uses VPID, TLB entries populated by L2 are
12201 * tagged with vmx->nested.vpid02 while L1 entries are tagged
12202 * with vmx->vpid. Thus, no need to flush TLB.
12204 * Therefore, flush TLB only in case vmcs01 uses VPID and
12205 * vmcs12 don't use VPID as in this case L1 & L2 TLB entries
12206 * are both tagged with vmx->vpid.
12209 !(nested_cpu_has_vpid(vmcs12) && to_vmx(vcpu)->nested.vpid02)) {
12210 vmx_flush_tlb(vcpu, true);
12213 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
12214 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
12215 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
12216 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
12217 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
12218 vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
12219 vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
12221 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
12222 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
12223 vmcs_write64(GUEST_BNDCFGS, 0);
12225 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
12226 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
12227 vcpu->arch.pat = vmcs12->host_ia32_pat;
12229 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
12230 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
12231 vmcs12->host_ia32_perf_global_ctrl);
12233 /* Set L1 segment info according to Intel SDM
12234 27.5.2 Loading Host Segment and Descriptor-Table Registers */
12235 seg = (struct kvm_segment) {
12237 .limit = 0xFFFFFFFF,
12238 .selector = vmcs12->host_cs_selector,
12244 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
12248 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
12249 seg = (struct kvm_segment) {
12251 .limit = 0xFFFFFFFF,
12258 seg.selector = vmcs12->host_ds_selector;
12259 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
12260 seg.selector = vmcs12->host_es_selector;
12261 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
12262 seg.selector = vmcs12->host_ss_selector;
12263 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
12264 seg.selector = vmcs12->host_fs_selector;
12265 seg.base = vmcs12->host_fs_base;
12266 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
12267 seg.selector = vmcs12->host_gs_selector;
12268 seg.base = vmcs12->host_gs_base;
12269 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
12270 seg = (struct kvm_segment) {
12271 .base = vmcs12->host_tr_base,
12273 .selector = vmcs12->host_tr_selector,
12277 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
12279 kvm_set_dr(vcpu, 7, 0x400);
12280 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
12282 if (cpu_has_vmx_msr_bitmap())
12283 vmx_update_msr_bitmap(vcpu);
12285 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
12286 vmcs12->vm_exit_msr_load_count))
12287 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
12291 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
12292 * and modify vmcs12 to make it see what it would expect to see there if
12293 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
12295 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
12296 u32 exit_intr_info,
12297 unsigned long exit_qualification)
12299 struct vcpu_vmx *vmx = to_vmx(vcpu);
12300 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12302 /* trying to cancel vmlaunch/vmresume is a bug */
12303 WARN_ON_ONCE(vmx->nested.nested_run_pending);
12306 * The only expected VM-instruction error is "VM entry with
12307 * invalid control field(s)." Anything else indicates a
12310 WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
12311 VMXERR_ENTRY_INVALID_CONTROL_FIELD));
12313 leave_guest_mode(vcpu);
12315 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
12316 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
12318 if (likely(!vmx->fail)) {
12319 if (exit_reason == -1)
12320 sync_vmcs12(vcpu, vmcs12);
12322 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
12323 exit_qualification);
12325 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
12326 vmcs12->vm_exit_msr_store_count))
12327 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
12330 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
12331 vm_entry_controls_reset_shadow(vmx);
12332 vm_exit_controls_reset_shadow(vmx);
12333 vmx_segment_cache_clear(vmx);
12335 /* Update any VMCS fields that might have changed while L2 ran */
12336 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
12337 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
12338 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
12339 if (vmx->hv_deadline_tsc == -1)
12340 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
12341 PIN_BASED_VMX_PREEMPTION_TIMER);
12343 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
12344 PIN_BASED_VMX_PREEMPTION_TIMER);
12345 if (kvm_has_tsc_control)
12346 decache_tsc_multiplier(vmx);
12348 if (vmx->nested.change_vmcs01_virtual_apic_mode) {
12349 vmx->nested.change_vmcs01_virtual_apic_mode = false;
12350 vmx_set_virtual_apic_mode(vcpu);
12351 } else if (!nested_cpu_has_ept(vmcs12) &&
12352 nested_cpu_has2(vmcs12,
12353 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
12354 vmx_flush_tlb(vcpu, true);
12357 /* This is needed for same reason as it was needed in prepare_vmcs02 */
12360 /* Unpin physical memory we referred to in vmcs02 */
12361 if (vmx->nested.apic_access_page) {
12362 kvm_release_page_dirty(vmx->nested.apic_access_page);
12363 vmx->nested.apic_access_page = NULL;
12365 if (vmx->nested.virtual_apic_page) {
12366 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
12367 vmx->nested.virtual_apic_page = NULL;
12369 if (vmx->nested.pi_desc_page) {
12370 kunmap(vmx->nested.pi_desc_page);
12371 kvm_release_page_dirty(vmx->nested.pi_desc_page);
12372 vmx->nested.pi_desc_page = NULL;
12373 vmx->nested.pi_desc = NULL;
12377 * We are now running in L2, mmu_notifier will force to reload the
12378 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
12380 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
12382 if (enable_shadow_vmcs && exit_reason != -1)
12383 vmx->nested.sync_shadow_vmcs = true;
12385 /* in case we halted in L2 */
12386 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
12388 if (likely(!vmx->fail)) {
12390 * TODO: SDM says that with acknowledge interrupt on
12391 * exit, bit 31 of the VM-exit interrupt information
12392 * (valid interrupt) is always set to 1 on
12393 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
12394 * need kvm_cpu_has_interrupt(). See the commit
12395 * message for details.
12397 if (nested_exit_intr_ack_set(vcpu) &&
12398 exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
12399 kvm_cpu_has_interrupt(vcpu)) {
12400 int irq = kvm_cpu_get_interrupt(vcpu);
12402 vmcs12->vm_exit_intr_info = irq |
12403 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
12406 if (exit_reason != -1)
12407 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
12408 vmcs12->exit_qualification,
12409 vmcs12->idt_vectoring_info_field,
12410 vmcs12->vm_exit_intr_info,
12411 vmcs12->vm_exit_intr_error_code,
12414 load_vmcs12_host_state(vcpu, vmcs12);
12420 * After an early L2 VM-entry failure, we're now back
12421 * in L1 which thinks it just finished a VMLAUNCH or
12422 * VMRESUME instruction, so we need to set the failure
12423 * flag and the VM-instruction error field of the VMCS
12426 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
12428 load_vmcs12_mmu_host_state(vcpu, vmcs12);
12431 * The emulated instruction was already skipped in
12432 * nested_vmx_run, but the updated RIP was never
12433 * written back to the vmcs01.
12435 skip_emulated_instruction(vcpu);
12440 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
12442 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
12444 if (is_guest_mode(vcpu)) {
12445 to_vmx(vcpu)->nested.nested_run_pending = 0;
12446 nested_vmx_vmexit(vcpu, -1, 0, 0);
12448 free_nested(to_vmx(vcpu));
12452 * L1's failure to enter L2 is a subset of a normal exit, as explained in
12453 * 23.7 "VM-entry failures during or after loading guest state" (this also
12454 * lists the acceptable exit-reason and exit-qualification parameters).
12455 * It should only be called before L2 actually succeeded to run, and when
12456 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
12458 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
12459 struct vmcs12 *vmcs12,
12460 u32 reason, unsigned long qualification)
12462 load_vmcs12_host_state(vcpu, vmcs12);
12463 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
12464 vmcs12->exit_qualification = qualification;
12465 nested_vmx_succeed(vcpu);
12466 if (enable_shadow_vmcs)
12467 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
12470 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
12471 struct x86_instruction_info *info,
12472 enum x86_intercept_stage stage)
12474 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12475 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
12478 * RDPID causes #UD if disabled through secondary execution controls.
12479 * Because it is marked as EmulateOnUD, we need to intercept it here.
12481 if (info->intercept == x86_intercept_rdtscp &&
12482 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
12483 ctxt->exception.vector = UD_VECTOR;
12484 ctxt->exception.error_code_valid = false;
12485 return X86EMUL_PROPAGATE_FAULT;
12488 /* TODO: check more intercepts... */
12489 return X86EMUL_CONTINUE;
12492 #ifdef CONFIG_X86_64
12493 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
12494 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
12495 u64 divisor, u64 *result)
12497 u64 low = a << shift, high = a >> (64 - shift);
12499 /* To avoid the overflow on divq */
12500 if (high >= divisor)
12503 /* Low hold the result, high hold rem which is discarded */
12504 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
12505 "rm" (divisor), "0" (low), "1" (high));
12511 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
12513 struct vcpu_vmx *vmx;
12514 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
12516 if (kvm_mwait_in_guest(vcpu->kvm))
12517 return -EOPNOTSUPP;
12519 vmx = to_vmx(vcpu);
12521 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
12522 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
12523 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, lapic_timer_advance_ns);
12525 if (delta_tsc > lapic_timer_advance_cycles)
12526 delta_tsc -= lapic_timer_advance_cycles;
12530 /* Convert to host delta tsc if tsc scaling is enabled */
12531 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
12532 u64_shl_div_u64(delta_tsc,
12533 kvm_tsc_scaling_ratio_frac_bits,
12534 vcpu->arch.tsc_scaling_ratio,
12539 * If the delta tsc can't fit in the 32 bit after the multi shift,
12540 * we can't use the preemption timer.
12541 * It's possible that it fits on later vmentries, but checking
12542 * on every vmentry is costly so we just use an hrtimer.
12544 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
12547 vmx->hv_deadline_tsc = tscl + delta_tsc;
12548 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
12549 PIN_BASED_VMX_PREEMPTION_TIMER);
12551 return delta_tsc == 0;
12554 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
12556 struct vcpu_vmx *vmx = to_vmx(vcpu);
12557 vmx->hv_deadline_tsc = -1;
12558 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
12559 PIN_BASED_VMX_PREEMPTION_TIMER);
12563 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
12565 if (!kvm_pause_in_guest(vcpu->kvm))
12566 shrink_ple_window(vcpu);
12569 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
12570 struct kvm_memory_slot *slot)
12572 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
12573 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
12576 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
12577 struct kvm_memory_slot *slot)
12579 kvm_mmu_slot_set_dirty(kvm, slot);
12582 static void vmx_flush_log_dirty(struct kvm *kvm)
12584 kvm_flush_pml_buffers(kvm);
12587 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
12589 struct vmcs12 *vmcs12;
12590 struct vcpu_vmx *vmx = to_vmx(vcpu);
12592 struct page *page = NULL;
12595 if (is_guest_mode(vcpu)) {
12596 WARN_ON_ONCE(vmx->nested.pml_full);
12599 * Check if PML is enabled for the nested guest.
12600 * Whether eptp bit 6 is set is already checked
12601 * as part of A/D emulation.
12603 vmcs12 = get_vmcs12(vcpu);
12604 if (!nested_cpu_has_pml(vmcs12))
12607 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
12608 vmx->nested.pml_full = true;
12612 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
12614 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
12615 if (is_error_page(page))
12618 pml_address = kmap(page);
12619 pml_address[vmcs12->guest_pml_index--] = gpa;
12621 kvm_release_page_clean(page);
12627 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
12628 struct kvm_memory_slot *memslot,
12629 gfn_t offset, unsigned long mask)
12631 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
12634 static void __pi_post_block(struct kvm_vcpu *vcpu)
12636 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12637 struct pi_desc old, new;
12641 old.control = new.control = pi_desc->control;
12642 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
12643 "Wakeup handler not enabled while the VCPU is blocked\n");
12645 dest = cpu_physical_id(vcpu->cpu);
12647 if (x2apic_enabled())
12650 new.ndst = (dest << 8) & 0xFF00;
12652 /* set 'NV' to 'notification vector' */
12653 new.nv = POSTED_INTR_VECTOR;
12654 } while (cmpxchg64(&pi_desc->control, old.control,
12655 new.control) != old.control);
12657 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
12658 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12659 list_del(&vcpu->blocked_vcpu_list);
12660 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12661 vcpu->pre_pcpu = -1;
12666 * This routine does the following things for vCPU which is going
12667 * to be blocked if VT-d PI is enabled.
12668 * - Store the vCPU to the wakeup list, so when interrupts happen
12669 * we can find the right vCPU to wake up.
12670 * - Change the Posted-interrupt descriptor as below:
12671 * 'NDST' <-- vcpu->pre_pcpu
12672 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
12673 * - If 'ON' is set during this process, which means at least one
12674 * interrupt is posted for this vCPU, we cannot block it, in
12675 * this case, return 1, otherwise, return 0.
12678 static int pi_pre_block(struct kvm_vcpu *vcpu)
12681 struct pi_desc old, new;
12682 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12684 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
12685 !irq_remapping_cap(IRQ_POSTING_CAP) ||
12686 !kvm_vcpu_apicv_active(vcpu))
12689 WARN_ON(irqs_disabled());
12690 local_irq_disable();
12691 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
12692 vcpu->pre_pcpu = vcpu->cpu;
12693 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12694 list_add_tail(&vcpu->blocked_vcpu_list,
12695 &per_cpu(blocked_vcpu_on_cpu,
12697 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12701 old.control = new.control = pi_desc->control;
12703 WARN((pi_desc->sn == 1),
12704 "Warning: SN field of posted-interrupts "
12705 "is set before blocking\n");
12708 * Since vCPU can be preempted during this process,
12709 * vcpu->cpu could be different with pre_pcpu, we
12710 * need to set pre_pcpu as the destination of wakeup
12711 * notification event, then we can find the right vCPU
12712 * to wakeup in wakeup handler if interrupts happen
12713 * when the vCPU is in blocked state.
12715 dest = cpu_physical_id(vcpu->pre_pcpu);
12717 if (x2apic_enabled())
12720 new.ndst = (dest << 8) & 0xFF00;
12722 /* set 'NV' to 'wakeup vector' */
12723 new.nv = POSTED_INTR_WAKEUP_VECTOR;
12724 } while (cmpxchg64(&pi_desc->control, old.control,
12725 new.control) != old.control);
12727 /* We should not block the vCPU if an interrupt is posted for it. */
12728 if (pi_test_on(pi_desc) == 1)
12729 __pi_post_block(vcpu);
12731 local_irq_enable();
12732 return (vcpu->pre_pcpu == -1);
12735 static int vmx_pre_block(struct kvm_vcpu *vcpu)
12737 if (pi_pre_block(vcpu))
12740 if (kvm_lapic_hv_timer_in_use(vcpu))
12741 kvm_lapic_switch_to_sw_timer(vcpu);
12746 static void pi_post_block(struct kvm_vcpu *vcpu)
12748 if (vcpu->pre_pcpu == -1)
12751 WARN_ON(irqs_disabled());
12752 local_irq_disable();
12753 __pi_post_block(vcpu);
12754 local_irq_enable();
12757 static void vmx_post_block(struct kvm_vcpu *vcpu)
12759 if (kvm_x86_ops->set_hv_timer)
12760 kvm_lapic_switch_to_hv_timer(vcpu);
12762 pi_post_block(vcpu);
12766 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
12769 * @host_irq: host irq of the interrupt
12770 * @guest_irq: gsi of the interrupt
12771 * @set: set or unset PI
12772 * returns 0 on success, < 0 on failure
12774 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
12775 uint32_t guest_irq, bool set)
12777 struct kvm_kernel_irq_routing_entry *e;
12778 struct kvm_irq_routing_table *irq_rt;
12779 struct kvm_lapic_irq irq;
12780 struct kvm_vcpu *vcpu;
12781 struct vcpu_data vcpu_info;
12784 if (!kvm_arch_has_assigned_device(kvm) ||
12785 !irq_remapping_cap(IRQ_POSTING_CAP) ||
12786 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
12789 idx = srcu_read_lock(&kvm->irq_srcu);
12790 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
12791 if (guest_irq >= irq_rt->nr_rt_entries ||
12792 hlist_empty(&irq_rt->map[guest_irq])) {
12793 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
12794 guest_irq, irq_rt->nr_rt_entries);
12798 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
12799 if (e->type != KVM_IRQ_ROUTING_MSI)
12802 * VT-d PI cannot support posting multicast/broadcast
12803 * interrupts to a vCPU, we still use interrupt remapping
12804 * for these kind of interrupts.
12806 * For lowest-priority interrupts, we only support
12807 * those with single CPU as the destination, e.g. user
12808 * configures the interrupts via /proc/irq or uses
12809 * irqbalance to make the interrupts single-CPU.
12811 * We will support full lowest-priority interrupt later.
12814 kvm_set_msi_irq(kvm, e, &irq);
12815 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
12817 * Make sure the IRTE is in remapped mode if
12818 * we don't handle it in posted mode.
12820 ret = irq_set_vcpu_affinity(host_irq, NULL);
12823 "failed to back to remapped mode, irq: %u\n",
12831 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
12832 vcpu_info.vector = irq.vector;
12834 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
12835 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
12838 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
12840 ret = irq_set_vcpu_affinity(host_irq, NULL);
12843 printk(KERN_INFO "%s: failed to update PI IRTE\n",
12851 srcu_read_unlock(&kvm->irq_srcu, idx);
12855 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
12857 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
12858 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
12859 FEATURE_CONTROL_LMCE;
12861 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
12862 ~FEATURE_CONTROL_LMCE;
12865 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
12867 /* we need a nested vmexit to enter SMM, postpone if run is pending */
12868 if (to_vmx(vcpu)->nested.nested_run_pending)
12873 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
12875 struct vcpu_vmx *vmx = to_vmx(vcpu);
12877 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
12878 if (vmx->nested.smm.guest_mode)
12879 nested_vmx_vmexit(vcpu, -1, 0, 0);
12881 vmx->nested.smm.vmxon = vmx->nested.vmxon;
12882 vmx->nested.vmxon = false;
12883 vmx_clear_hlt(vcpu);
12887 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
12889 struct vcpu_vmx *vmx = to_vmx(vcpu);
12892 if (vmx->nested.smm.vmxon) {
12893 vmx->nested.vmxon = true;
12894 vmx->nested.smm.vmxon = false;
12897 if (vmx->nested.smm.guest_mode) {
12898 vcpu->arch.hflags &= ~HF_SMM_MASK;
12899 ret = enter_vmx_non_root_mode(vcpu);
12900 vcpu->arch.hflags |= HF_SMM_MASK;
12904 vmx->nested.smm.guest_mode = false;
12909 static int enable_smi_window(struct kvm_vcpu *vcpu)
12914 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
12915 .cpu_has_kvm_support = cpu_has_kvm_support,
12916 .disabled_by_bios = vmx_disabled_by_bios,
12917 .hardware_setup = hardware_setup,
12918 .hardware_unsetup = hardware_unsetup,
12919 .check_processor_compatibility = vmx_check_processor_compat,
12920 .hardware_enable = hardware_enable,
12921 .hardware_disable = hardware_disable,
12922 .cpu_has_accelerated_tpr = report_flexpriority,
12923 .has_emulated_msr = vmx_has_emulated_msr,
12925 .vm_init = vmx_vm_init,
12926 .vm_alloc = vmx_vm_alloc,
12927 .vm_free = vmx_vm_free,
12929 .vcpu_create = vmx_create_vcpu,
12930 .vcpu_free = vmx_free_vcpu,
12931 .vcpu_reset = vmx_vcpu_reset,
12933 .prepare_guest_switch = vmx_save_host_state,
12934 .vcpu_load = vmx_vcpu_load,
12935 .vcpu_put = vmx_vcpu_put,
12937 .update_bp_intercept = update_exception_bitmap,
12938 .get_msr_feature = vmx_get_msr_feature,
12939 .get_msr = vmx_get_msr,
12940 .set_msr = vmx_set_msr,
12941 .get_segment_base = vmx_get_segment_base,
12942 .get_segment = vmx_get_segment,
12943 .set_segment = vmx_set_segment,
12944 .get_cpl = vmx_get_cpl,
12945 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
12946 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
12947 .decache_cr3 = vmx_decache_cr3,
12948 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
12949 .set_cr0 = vmx_set_cr0,
12950 .set_cr3 = vmx_set_cr3,
12951 .set_cr4 = vmx_set_cr4,
12952 .set_efer = vmx_set_efer,
12953 .get_idt = vmx_get_idt,
12954 .set_idt = vmx_set_idt,
12955 .get_gdt = vmx_get_gdt,
12956 .set_gdt = vmx_set_gdt,
12957 .get_dr6 = vmx_get_dr6,
12958 .set_dr6 = vmx_set_dr6,
12959 .set_dr7 = vmx_set_dr7,
12960 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
12961 .cache_reg = vmx_cache_reg,
12962 .get_rflags = vmx_get_rflags,
12963 .set_rflags = vmx_set_rflags,
12965 .tlb_flush = vmx_flush_tlb,
12967 .run = vmx_vcpu_run,
12968 .handle_exit = vmx_handle_exit,
12969 .skip_emulated_instruction = skip_emulated_instruction,
12970 .set_interrupt_shadow = vmx_set_interrupt_shadow,
12971 .get_interrupt_shadow = vmx_get_interrupt_shadow,
12972 .patch_hypercall = vmx_patch_hypercall,
12973 .set_irq = vmx_inject_irq,
12974 .set_nmi = vmx_inject_nmi,
12975 .queue_exception = vmx_queue_exception,
12976 .cancel_injection = vmx_cancel_injection,
12977 .interrupt_allowed = vmx_interrupt_allowed,
12978 .nmi_allowed = vmx_nmi_allowed,
12979 .get_nmi_mask = vmx_get_nmi_mask,
12980 .set_nmi_mask = vmx_set_nmi_mask,
12981 .enable_nmi_window = enable_nmi_window,
12982 .enable_irq_window = enable_irq_window,
12983 .update_cr8_intercept = update_cr8_intercept,
12984 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
12985 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
12986 .get_enable_apicv = vmx_get_enable_apicv,
12987 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
12988 .load_eoi_exitmap = vmx_load_eoi_exitmap,
12989 .apicv_post_state_restore = vmx_apicv_post_state_restore,
12990 .hwapic_irr_update = vmx_hwapic_irr_update,
12991 .hwapic_isr_update = vmx_hwapic_isr_update,
12992 .sync_pir_to_irr = vmx_sync_pir_to_irr,
12993 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
12995 .set_tss_addr = vmx_set_tss_addr,
12996 .set_identity_map_addr = vmx_set_identity_map_addr,
12997 .get_tdp_level = get_ept_level,
12998 .get_mt_mask = vmx_get_mt_mask,
13000 .get_exit_info = vmx_get_exit_info,
13002 .get_lpage_level = vmx_get_lpage_level,
13004 .cpuid_update = vmx_cpuid_update,
13006 .rdtscp_supported = vmx_rdtscp_supported,
13007 .invpcid_supported = vmx_invpcid_supported,
13009 .set_supported_cpuid = vmx_set_supported_cpuid,
13011 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
13013 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
13014 .write_tsc_offset = vmx_write_tsc_offset,
13016 .set_tdp_cr3 = vmx_set_cr3,
13018 .check_intercept = vmx_check_intercept,
13019 .handle_external_intr = vmx_handle_external_intr,
13020 .mpx_supported = vmx_mpx_supported,
13021 .xsaves_supported = vmx_xsaves_supported,
13022 .umip_emulated = vmx_umip_emulated,
13024 .check_nested_events = vmx_check_nested_events,
13026 .sched_in = vmx_sched_in,
13028 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
13029 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
13030 .flush_log_dirty = vmx_flush_log_dirty,
13031 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
13032 .write_log_dirty = vmx_write_pml_buffer,
13034 .pre_block = vmx_pre_block,
13035 .post_block = vmx_post_block,
13037 .pmu_ops = &intel_pmu_ops,
13039 .update_pi_irte = vmx_update_pi_irte,
13041 #ifdef CONFIG_X86_64
13042 .set_hv_timer = vmx_set_hv_timer,
13043 .cancel_hv_timer = vmx_cancel_hv_timer,
13046 .setup_mce = vmx_setup_mce,
13048 .smi_allowed = vmx_smi_allowed,
13049 .pre_enter_smm = vmx_pre_enter_smm,
13050 .pre_leave_smm = vmx_pre_leave_smm,
13051 .enable_smi_window = enable_smi_window,
13054 static int __init vmx_init(void)
13058 #if IS_ENABLED(CONFIG_HYPERV)
13060 * Enlightened VMCS usage should be recommended and the host needs
13061 * to support eVMCS v1 or above. We can also disable eVMCS support
13062 * with module parameter.
13064 if (enlightened_vmcs &&
13065 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
13066 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
13067 KVM_EVMCS_VERSION) {
13070 /* Check that we have assist pages on all online CPUs */
13071 for_each_online_cpu(cpu) {
13072 if (!hv_get_vp_assist_page(cpu)) {
13073 enlightened_vmcs = false;
13078 if (enlightened_vmcs) {
13079 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
13080 static_branch_enable(&enable_evmcs);
13083 enlightened_vmcs = false;
13087 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
13088 __alignof__(struct vcpu_vmx), THIS_MODULE);
13092 #ifdef CONFIG_KEXEC_CORE
13093 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
13094 crash_vmclear_local_loaded_vmcss);
13096 vmx_check_vmcs12_offsets();
13101 static void __exit vmx_exit(void)
13103 #ifdef CONFIG_KEXEC_CORE
13104 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
13110 #if IS_ENABLED(CONFIG_HYPERV)
13111 if (static_branch_unlikely(&enable_evmcs)) {
13113 struct hv_vp_assist_page *vp_ap;
13115 * Reset everything to support using non-enlightened VMCS
13116 * access later (e.g. when we reload the module with
13117 * enlightened_vmcs=0)
13119 for_each_online_cpu(cpu) {
13120 vp_ap = hv_get_vp_assist_page(cpu);
13125 vp_ap->current_nested_vmcs = 0;
13126 vp_ap->enlighten_vmentry = 0;
13129 static_branch_disable(&enable_evmcs);
13134 module_init(vmx_init)
13135 module_exit(vmx_exit)