2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include "kvm_cache_regs.h"
43 #include <asm/virtext.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/perf_event.h>
47 #include <asm/debugreg.h>
48 #include <asm/kexec.h>
50 #include <asm/irq_remapping.h>
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 #define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id vmx_cpu_id[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX),
66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
68 static bool __read_mostly enable_vpid = 1;
69 module_param_named(vpid, enable_vpid, bool, 0444);
71 static bool __read_mostly flexpriority_enabled = 1;
72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
74 static bool __read_mostly enable_ept = 1;
75 module_param_named(ept, enable_ept, bool, S_IRUGO);
77 static bool __read_mostly enable_unrestricted_guest = 1;
78 module_param_named(unrestricted_guest,
79 enable_unrestricted_guest, bool, S_IRUGO);
81 static bool __read_mostly enable_ept_ad_bits = 1;
82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
84 static bool __read_mostly emulate_invalid_guest_state = true;
85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
87 static bool __read_mostly vmm_exclusive = 1;
88 module_param(vmm_exclusive, bool, S_IRUGO);
90 static bool __read_mostly fasteoi = 1;
91 module_param(fasteoi, bool, S_IRUGO);
93 static bool __read_mostly enable_apicv = 1;
94 module_param(enable_apicv, bool, S_IRUGO);
96 static bool __read_mostly enable_shadow_vmcs = 1;
97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
99 * If nested=1, nested virtualization is supported, i.e., guests may use
100 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
101 * use VMX instructions.
103 static bool __read_mostly nested = 0;
104 module_param(nested, bool, S_IRUGO);
106 static u64 __read_mostly host_xss;
108 static bool __read_mostly enable_pml = 1;
109 module_param_named(pml, enable_pml, bool, S_IRUGO);
111 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
113 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
114 static int __read_mostly cpu_preemption_timer_multi;
115 static bool __read_mostly enable_preemption_timer = 1;
117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
122 #define KVM_VM_CR0_ALWAYS_ON \
123 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
124 #define KVM_CR4_GUEST_OWNED_BITS \
125 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
126 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
136 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
137 * ple_gap: upper bound on the amount of time between two successive
138 * executions of PAUSE in a loop. Also indicate if ple enabled.
139 * According to test, this time is usually smaller than 128 cycles.
140 * ple_window: upper bound on the amount of time a guest is allowed to execute
141 * in a PAUSE loop. Tests indicate that most spinlocks are held for
142 * less than 2^12 cycles
143 * Time is measured based on a counter that runs at the same rate as the TSC,
144 * refer SDM volume 3b section 21.6.13 & 22.1.3.
146 #define KVM_VMX_DEFAULT_PLE_GAP 128
147 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
148 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
149 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
150 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
151 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
153 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
154 module_param(ple_gap, int, S_IRUGO);
156 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
157 module_param(ple_window, int, S_IRUGO);
159 /* Default doubles per-vcpu window every exit. */
160 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
161 module_param(ple_window_grow, int, S_IRUGO);
163 /* Default resets per-vcpu window every exit to ple_window. */
164 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
165 module_param(ple_window_shrink, int, S_IRUGO);
167 /* Default is to compute the maximum so we can never overflow. */
168 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
169 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
170 module_param(ple_window_max, int, S_IRUGO);
172 extern const ulong vmx_return;
174 #define NR_AUTOLOAD_MSRS 8
175 #define VMCS02_POOL_SIZE 1
184 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
185 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
186 * loaded on this CPU (so we can clear them if the CPU goes down).
192 struct list_head loaded_vmcss_on_cpu_link;
195 struct shared_msr_entry {
202 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
203 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
204 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
205 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
206 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
207 * More than one of these structures may exist, if L1 runs multiple L2 guests.
208 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
209 * underlying hardware which will be used to run L2.
210 * This structure is packed to ensure that its layout is identical across
211 * machines (necessary for live migration).
212 * If there are changes in this struct, VMCS12_REVISION must be changed.
214 typedef u64 natural_width;
215 struct __packed vmcs12 {
216 /* According to the Intel spec, a VMCS region must start with the
217 * following two fields. Then follow implementation-specific data.
222 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
223 u32 padding[7]; /* room for future expansion */
228 u64 vm_exit_msr_store_addr;
229 u64 vm_exit_msr_load_addr;
230 u64 vm_entry_msr_load_addr;
232 u64 virtual_apic_page_addr;
233 u64 apic_access_addr;
234 u64 posted_intr_desc_addr;
236 u64 eoi_exit_bitmap0;
237 u64 eoi_exit_bitmap1;
238 u64 eoi_exit_bitmap2;
239 u64 eoi_exit_bitmap3;
241 u64 guest_physical_address;
242 u64 vmcs_link_pointer;
243 u64 guest_ia32_debugctl;
246 u64 guest_ia32_perf_global_ctrl;
254 u64 host_ia32_perf_global_ctrl;
255 u64 padding64[8]; /* room for future expansion */
257 * To allow migration of L1 (complete with its L2 guests) between
258 * machines of different natural widths (32 or 64 bit), we cannot have
259 * unsigned long fields with no explict size. We use u64 (aliased
260 * natural_width) instead. Luckily, x86 is little-endian.
262 natural_width cr0_guest_host_mask;
263 natural_width cr4_guest_host_mask;
264 natural_width cr0_read_shadow;
265 natural_width cr4_read_shadow;
266 natural_width cr3_target_value0;
267 natural_width cr3_target_value1;
268 natural_width cr3_target_value2;
269 natural_width cr3_target_value3;
270 natural_width exit_qualification;
271 natural_width guest_linear_address;
272 natural_width guest_cr0;
273 natural_width guest_cr3;
274 natural_width guest_cr4;
275 natural_width guest_es_base;
276 natural_width guest_cs_base;
277 natural_width guest_ss_base;
278 natural_width guest_ds_base;
279 natural_width guest_fs_base;
280 natural_width guest_gs_base;
281 natural_width guest_ldtr_base;
282 natural_width guest_tr_base;
283 natural_width guest_gdtr_base;
284 natural_width guest_idtr_base;
285 natural_width guest_dr7;
286 natural_width guest_rsp;
287 natural_width guest_rip;
288 natural_width guest_rflags;
289 natural_width guest_pending_dbg_exceptions;
290 natural_width guest_sysenter_esp;
291 natural_width guest_sysenter_eip;
292 natural_width host_cr0;
293 natural_width host_cr3;
294 natural_width host_cr4;
295 natural_width host_fs_base;
296 natural_width host_gs_base;
297 natural_width host_tr_base;
298 natural_width host_gdtr_base;
299 natural_width host_idtr_base;
300 natural_width host_ia32_sysenter_esp;
301 natural_width host_ia32_sysenter_eip;
302 natural_width host_rsp;
303 natural_width host_rip;
304 natural_width paddingl[8]; /* room for future expansion */
305 u32 pin_based_vm_exec_control;
306 u32 cpu_based_vm_exec_control;
307 u32 exception_bitmap;
308 u32 page_fault_error_code_mask;
309 u32 page_fault_error_code_match;
310 u32 cr3_target_count;
311 u32 vm_exit_controls;
312 u32 vm_exit_msr_store_count;
313 u32 vm_exit_msr_load_count;
314 u32 vm_entry_controls;
315 u32 vm_entry_msr_load_count;
316 u32 vm_entry_intr_info_field;
317 u32 vm_entry_exception_error_code;
318 u32 vm_entry_instruction_len;
320 u32 secondary_vm_exec_control;
321 u32 vm_instruction_error;
323 u32 vm_exit_intr_info;
324 u32 vm_exit_intr_error_code;
325 u32 idt_vectoring_info_field;
326 u32 idt_vectoring_error_code;
327 u32 vm_exit_instruction_len;
328 u32 vmx_instruction_info;
335 u32 guest_ldtr_limit;
337 u32 guest_gdtr_limit;
338 u32 guest_idtr_limit;
339 u32 guest_es_ar_bytes;
340 u32 guest_cs_ar_bytes;
341 u32 guest_ss_ar_bytes;
342 u32 guest_ds_ar_bytes;
343 u32 guest_fs_ar_bytes;
344 u32 guest_gs_ar_bytes;
345 u32 guest_ldtr_ar_bytes;
346 u32 guest_tr_ar_bytes;
347 u32 guest_interruptibility_info;
348 u32 guest_activity_state;
349 u32 guest_sysenter_cs;
350 u32 host_ia32_sysenter_cs;
351 u32 vmx_preemption_timer_value;
352 u32 padding32[7]; /* room for future expansion */
353 u16 virtual_processor_id;
355 u16 guest_es_selector;
356 u16 guest_cs_selector;
357 u16 guest_ss_selector;
358 u16 guest_ds_selector;
359 u16 guest_fs_selector;
360 u16 guest_gs_selector;
361 u16 guest_ldtr_selector;
362 u16 guest_tr_selector;
363 u16 guest_intr_status;
364 u16 host_es_selector;
365 u16 host_cs_selector;
366 u16 host_ss_selector;
367 u16 host_ds_selector;
368 u16 host_fs_selector;
369 u16 host_gs_selector;
370 u16 host_tr_selector;
374 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
375 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
376 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
378 #define VMCS12_REVISION 0x11e57ed0
381 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
382 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
383 * current implementation, 4K are reserved to avoid future complications.
385 #define VMCS12_SIZE 0x1000
387 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
389 struct list_head list;
391 struct loaded_vmcs vmcs02;
395 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
396 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
399 /* Has the level1 guest done vmxon? */
403 /* The guest-physical address of the current VMCS L1 keeps for L2 */
405 /* The host-usable pointer to the above */
406 struct page *current_vmcs12_page;
407 struct vmcs12 *current_vmcs12;
408 struct vmcs *current_shadow_vmcs;
410 * Indicates if the shadow vmcs must be updated with the
411 * data hold by vmcs12
413 bool sync_shadow_vmcs;
415 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
416 struct list_head vmcs02_pool;
418 u64 vmcs01_tsc_offset;
419 /* L2 must run next, and mustn't decide to exit to L1. */
420 bool nested_run_pending;
422 * Guest pages referred to in vmcs02 with host-physical pointers, so
423 * we must keep them pinned while L2 runs.
425 struct page *apic_access_page;
426 struct page *virtual_apic_page;
427 struct page *pi_desc_page;
428 struct pi_desc *pi_desc;
432 struct hrtimer preemption_timer;
433 bool preemption_timer_expired;
435 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
441 u32 nested_vmx_procbased_ctls_low;
442 u32 nested_vmx_procbased_ctls_high;
443 u32 nested_vmx_true_procbased_ctls_low;
444 u32 nested_vmx_secondary_ctls_low;
445 u32 nested_vmx_secondary_ctls_high;
446 u32 nested_vmx_pinbased_ctls_low;
447 u32 nested_vmx_pinbased_ctls_high;
448 u32 nested_vmx_exit_ctls_low;
449 u32 nested_vmx_exit_ctls_high;
450 u32 nested_vmx_true_exit_ctls_low;
451 u32 nested_vmx_entry_ctls_low;
452 u32 nested_vmx_entry_ctls_high;
453 u32 nested_vmx_true_entry_ctls_low;
454 u32 nested_vmx_misc_low;
455 u32 nested_vmx_misc_high;
456 u32 nested_vmx_ept_caps;
457 u32 nested_vmx_vpid_caps;
460 #define POSTED_INTR_ON 0
461 #define POSTED_INTR_SN 1
463 /* Posted-Interrupt Descriptor */
465 u32 pir[8]; /* Posted interrupt requested */
468 /* bit 256 - Outstanding Notification */
470 /* bit 257 - Suppress Notification */
472 /* bit 271:258 - Reserved */
474 /* bit 279:272 - Notification Vector */
476 /* bit 287:280 - Reserved */
478 /* bit 319:288 - Notification Destination */
486 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
488 return test_and_set_bit(POSTED_INTR_ON,
489 (unsigned long *)&pi_desc->control);
492 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
494 return test_and_clear_bit(POSTED_INTR_ON,
495 (unsigned long *)&pi_desc->control);
498 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
500 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
503 static inline void pi_clear_sn(struct pi_desc *pi_desc)
505 return clear_bit(POSTED_INTR_SN,
506 (unsigned long *)&pi_desc->control);
509 static inline void pi_set_sn(struct pi_desc *pi_desc)
511 return set_bit(POSTED_INTR_SN,
512 (unsigned long *)&pi_desc->control);
515 static inline int pi_test_on(struct pi_desc *pi_desc)
517 return test_bit(POSTED_INTR_ON,
518 (unsigned long *)&pi_desc->control);
521 static inline int pi_test_sn(struct pi_desc *pi_desc)
523 return test_bit(POSTED_INTR_SN,
524 (unsigned long *)&pi_desc->control);
528 struct kvm_vcpu vcpu;
529 unsigned long host_rsp;
531 bool nmi_known_unmasked;
533 u32 idt_vectoring_info;
535 struct shared_msr_entry *guest_msrs;
538 unsigned long host_idt_base;
540 u64 msr_host_kernel_gs_base;
541 u64 msr_guest_kernel_gs_base;
543 u32 vm_entry_controls_shadow;
544 u32 vm_exit_controls_shadow;
546 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
547 * non-nested (L1) guest, it always points to vmcs01. For a nested
548 * guest (L2), it points to a different VMCS.
550 struct loaded_vmcs vmcs01;
551 struct loaded_vmcs *loaded_vmcs;
552 bool __launched; /* temporary, used in vmx_vcpu_run */
553 struct msr_autoload {
555 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
556 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
560 u16 fs_sel, gs_sel, ldt_sel;
564 int gs_ldt_reload_needed;
565 int fs_reload_needed;
566 u64 msr_host_bndcfgs;
567 unsigned long vmcs_host_cr4; /* May not match real cr4 */
572 struct kvm_segment segs[8];
575 u32 bitmask; /* 4 bits per segment (1 bit per field) */
576 struct kvm_save_segment {
584 bool emulation_required;
586 /* Support for vnmi-less CPUs */
587 int soft_vnmi_blocked;
589 s64 vnmi_blocked_time;
592 /* Posted interrupt descriptor */
593 struct pi_desc pi_desc;
595 /* Support for a guest hypervisor (nested VMX) */
596 struct nested_vmx nested;
598 /* Dynamic PLE window. */
600 bool ple_window_dirty;
602 /* Support for PML */
603 #define PML_ENTITY_NUM 512
606 /* apic deadline value in host tsc */
609 u64 current_tsc_ratio;
611 bool guest_pkru_valid;
615 u64 msr_ia32_feature_control;
618 enum segment_cache_field {
627 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
629 return container_of(vcpu, struct vcpu_vmx, vcpu);
632 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
634 return &(to_vmx(vcpu)->pi_desc);
637 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
638 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
639 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
640 [number##_HIGH] = VMCS12_OFFSET(name)+4
643 static unsigned long shadow_read_only_fields[] = {
645 * We do NOT shadow fields that are modified when L0
646 * traps and emulates any vmx instruction (e.g. VMPTRLD,
647 * VMXON...) executed by L1.
648 * For example, VM_INSTRUCTION_ERROR is read
649 * by L1 if a vmx instruction fails (part of the error path).
650 * Note the code assumes this logic. If for some reason
651 * we start shadowing these fields then we need to
652 * force a shadow sync when L0 emulates vmx instructions
653 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
654 * by nested_vmx_failValid)
658 VM_EXIT_INSTRUCTION_LEN,
659 IDT_VECTORING_INFO_FIELD,
660 IDT_VECTORING_ERROR_CODE,
661 VM_EXIT_INTR_ERROR_CODE,
663 GUEST_LINEAR_ADDRESS,
664 GUEST_PHYSICAL_ADDRESS
666 static int max_shadow_read_only_fields =
667 ARRAY_SIZE(shadow_read_only_fields);
669 static unsigned long shadow_read_write_fields[] = {
676 GUEST_INTERRUPTIBILITY_INFO,
689 CPU_BASED_VM_EXEC_CONTROL,
690 VM_ENTRY_EXCEPTION_ERROR_CODE,
691 VM_ENTRY_INTR_INFO_FIELD,
692 VM_ENTRY_INSTRUCTION_LEN,
693 VM_ENTRY_EXCEPTION_ERROR_CODE,
699 static int max_shadow_read_write_fields =
700 ARRAY_SIZE(shadow_read_write_fields);
702 static const unsigned short vmcs_field_to_offset_table[] = {
703 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
704 FIELD(POSTED_INTR_NV, posted_intr_nv),
705 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
706 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
707 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
708 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
709 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
710 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
711 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
712 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
713 FIELD(GUEST_INTR_STATUS, guest_intr_status),
714 FIELD(HOST_ES_SELECTOR, host_es_selector),
715 FIELD(HOST_CS_SELECTOR, host_cs_selector),
716 FIELD(HOST_SS_SELECTOR, host_ss_selector),
717 FIELD(HOST_DS_SELECTOR, host_ds_selector),
718 FIELD(HOST_FS_SELECTOR, host_fs_selector),
719 FIELD(HOST_GS_SELECTOR, host_gs_selector),
720 FIELD(HOST_TR_SELECTOR, host_tr_selector),
721 FIELD64(IO_BITMAP_A, io_bitmap_a),
722 FIELD64(IO_BITMAP_B, io_bitmap_b),
723 FIELD64(MSR_BITMAP, msr_bitmap),
724 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
725 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
726 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
727 FIELD64(TSC_OFFSET, tsc_offset),
728 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
729 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
730 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
731 FIELD64(EPT_POINTER, ept_pointer),
732 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
733 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
734 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
735 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
736 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
737 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
738 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
739 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
740 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
741 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
742 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
743 FIELD64(GUEST_PDPTR0, guest_pdptr0),
744 FIELD64(GUEST_PDPTR1, guest_pdptr1),
745 FIELD64(GUEST_PDPTR2, guest_pdptr2),
746 FIELD64(GUEST_PDPTR3, guest_pdptr3),
747 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
748 FIELD64(HOST_IA32_PAT, host_ia32_pat),
749 FIELD64(HOST_IA32_EFER, host_ia32_efer),
750 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
751 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
752 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
753 FIELD(EXCEPTION_BITMAP, exception_bitmap),
754 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
755 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
756 FIELD(CR3_TARGET_COUNT, cr3_target_count),
757 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
758 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
759 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
760 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
761 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
762 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
763 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
764 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
765 FIELD(TPR_THRESHOLD, tpr_threshold),
766 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
767 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
768 FIELD(VM_EXIT_REASON, vm_exit_reason),
769 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
770 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
771 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
772 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
773 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
774 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
775 FIELD(GUEST_ES_LIMIT, guest_es_limit),
776 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
777 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
778 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
779 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
780 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
781 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
782 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
783 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
784 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
785 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
786 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
787 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
788 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
789 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
790 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
791 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
792 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
793 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
794 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
795 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
796 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
797 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
798 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
799 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
800 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
801 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
802 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
803 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
804 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
805 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
806 FIELD(EXIT_QUALIFICATION, exit_qualification),
807 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
808 FIELD(GUEST_CR0, guest_cr0),
809 FIELD(GUEST_CR3, guest_cr3),
810 FIELD(GUEST_CR4, guest_cr4),
811 FIELD(GUEST_ES_BASE, guest_es_base),
812 FIELD(GUEST_CS_BASE, guest_cs_base),
813 FIELD(GUEST_SS_BASE, guest_ss_base),
814 FIELD(GUEST_DS_BASE, guest_ds_base),
815 FIELD(GUEST_FS_BASE, guest_fs_base),
816 FIELD(GUEST_GS_BASE, guest_gs_base),
817 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
818 FIELD(GUEST_TR_BASE, guest_tr_base),
819 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
820 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
821 FIELD(GUEST_DR7, guest_dr7),
822 FIELD(GUEST_RSP, guest_rsp),
823 FIELD(GUEST_RIP, guest_rip),
824 FIELD(GUEST_RFLAGS, guest_rflags),
825 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
826 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
827 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
828 FIELD(HOST_CR0, host_cr0),
829 FIELD(HOST_CR3, host_cr3),
830 FIELD(HOST_CR4, host_cr4),
831 FIELD(HOST_FS_BASE, host_fs_base),
832 FIELD(HOST_GS_BASE, host_gs_base),
833 FIELD(HOST_TR_BASE, host_tr_base),
834 FIELD(HOST_GDTR_BASE, host_gdtr_base),
835 FIELD(HOST_IDTR_BASE, host_idtr_base),
836 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
837 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
838 FIELD(HOST_RSP, host_rsp),
839 FIELD(HOST_RIP, host_rip),
842 static inline short vmcs_field_to_offset(unsigned long field)
844 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
846 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
847 vmcs_field_to_offset_table[field] == 0)
850 return vmcs_field_to_offset_table[field];
853 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
855 return to_vmx(vcpu)->nested.current_vmcs12;
858 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
860 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
861 if (is_error_page(page))
867 static void nested_release_page(struct page *page)
869 kvm_release_page_dirty(page);
872 static void nested_release_page_clean(struct page *page)
874 kvm_release_page_clean(page);
877 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
878 static u64 construct_eptp(unsigned long root_hpa);
879 static void kvm_cpu_vmxon(u64 addr);
880 static void kvm_cpu_vmxoff(void);
881 static bool vmx_xsaves_supported(void);
882 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
883 static void vmx_set_segment(struct kvm_vcpu *vcpu,
884 struct kvm_segment *var, int seg);
885 static void vmx_get_segment(struct kvm_vcpu *vcpu,
886 struct kvm_segment *var, int seg);
887 static bool guest_state_valid(struct kvm_vcpu *vcpu);
888 static u32 vmx_segment_access_rights(struct kvm_segment *var);
889 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
890 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
891 static int alloc_identity_pagetable(struct kvm *kvm);
893 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
894 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
896 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
897 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
899 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
900 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
903 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
904 * can find which vCPU should be waken up.
906 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
907 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
909 static unsigned long *vmx_io_bitmap_a;
910 static unsigned long *vmx_io_bitmap_b;
911 static unsigned long *vmx_msr_bitmap_legacy;
912 static unsigned long *vmx_msr_bitmap_longmode;
913 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
914 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
915 static unsigned long *vmx_msr_bitmap_nested;
916 static unsigned long *vmx_vmread_bitmap;
917 static unsigned long *vmx_vmwrite_bitmap;
919 static bool cpu_has_load_ia32_efer;
920 static bool cpu_has_load_perf_global_ctrl;
922 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
923 static DEFINE_SPINLOCK(vmx_vpid_lock);
925 static struct vmcs_config {
929 u32 pin_based_exec_ctrl;
930 u32 cpu_based_exec_ctrl;
931 u32 cpu_based_2nd_exec_ctrl;
936 static struct vmx_capability {
941 #define VMX_SEGMENT_FIELD(seg) \
942 [VCPU_SREG_##seg] = { \
943 .selector = GUEST_##seg##_SELECTOR, \
944 .base = GUEST_##seg##_BASE, \
945 .limit = GUEST_##seg##_LIMIT, \
946 .ar_bytes = GUEST_##seg##_AR_BYTES, \
949 static const struct kvm_vmx_segment_field {
954 } kvm_vmx_segment_fields[] = {
955 VMX_SEGMENT_FIELD(CS),
956 VMX_SEGMENT_FIELD(DS),
957 VMX_SEGMENT_FIELD(ES),
958 VMX_SEGMENT_FIELD(FS),
959 VMX_SEGMENT_FIELD(GS),
960 VMX_SEGMENT_FIELD(SS),
961 VMX_SEGMENT_FIELD(TR),
962 VMX_SEGMENT_FIELD(LDTR),
965 static u64 host_efer;
967 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
970 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
971 * away by decrementing the array size.
973 static const u32 vmx_msr_index[] = {
975 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
977 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
980 static inline bool is_exception_n(u32 intr_info, u8 vector)
982 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
983 INTR_INFO_VALID_MASK)) ==
984 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
987 static inline bool is_debug(u32 intr_info)
989 return is_exception_n(intr_info, DB_VECTOR);
992 static inline bool is_breakpoint(u32 intr_info)
994 return is_exception_n(intr_info, BP_VECTOR);
997 static inline bool is_page_fault(u32 intr_info)
999 return is_exception_n(intr_info, PF_VECTOR);
1002 static inline bool is_no_device(u32 intr_info)
1004 return is_exception_n(intr_info, NM_VECTOR);
1007 static inline bool is_invalid_opcode(u32 intr_info)
1009 return is_exception_n(intr_info, UD_VECTOR);
1012 static inline bool is_external_interrupt(u32 intr_info)
1014 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1015 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1018 static inline bool is_machine_check(u32 intr_info)
1020 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1021 INTR_INFO_VALID_MASK)) ==
1022 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1025 static inline bool cpu_has_vmx_msr_bitmap(void)
1027 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1030 static inline bool cpu_has_vmx_tpr_shadow(void)
1032 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1035 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1037 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1040 static inline bool cpu_has_secondary_exec_ctrls(void)
1042 return vmcs_config.cpu_based_exec_ctrl &
1043 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1046 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1048 return vmcs_config.cpu_based_2nd_exec_ctrl &
1049 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1052 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1054 return vmcs_config.cpu_based_2nd_exec_ctrl &
1055 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1058 static inline bool cpu_has_vmx_apic_register_virt(void)
1060 return vmcs_config.cpu_based_2nd_exec_ctrl &
1061 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1064 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1066 return vmcs_config.cpu_based_2nd_exec_ctrl &
1067 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1071 * Comment's format: document - errata name - stepping - processor name.
1073 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1075 static u32 vmx_preemption_cpu_tfms[] = {
1076 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1078 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1079 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1080 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1082 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1084 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1085 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1087 * 320767.pdf - AAP86 - B1 -
1088 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1091 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1093 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1095 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1097 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1098 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1099 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1103 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1105 u32 eax = cpuid_eax(0x00000001), i;
1107 /* Clear the reserved bits */
1108 eax &= ~(0x3U << 14 | 0xfU << 28);
1109 for (i = 0; i < sizeof(vmx_preemption_cpu_tfms)/sizeof(u32); i++)
1110 if (eax == vmx_preemption_cpu_tfms[i])
1116 static inline bool cpu_has_vmx_preemption_timer(void)
1118 if (cpu_has_broken_vmx_preemption_timer())
1121 return vmcs_config.pin_based_exec_ctrl &
1122 PIN_BASED_VMX_PREEMPTION_TIMER;
1125 static inline bool cpu_has_vmx_posted_intr(void)
1127 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1128 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1131 static inline bool cpu_has_vmx_apicv(void)
1133 return cpu_has_vmx_apic_register_virt() &&
1134 cpu_has_vmx_virtual_intr_delivery() &&
1135 cpu_has_vmx_posted_intr();
1138 static inline bool cpu_has_vmx_flexpriority(void)
1140 return cpu_has_vmx_tpr_shadow() &&
1141 cpu_has_vmx_virtualize_apic_accesses();
1144 static inline bool cpu_has_vmx_ept_execute_only(void)
1146 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1149 static inline bool cpu_has_vmx_ept_2m_page(void)
1151 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1154 static inline bool cpu_has_vmx_ept_1g_page(void)
1156 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1159 static inline bool cpu_has_vmx_ept_4levels(void)
1161 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1164 static inline bool cpu_has_vmx_ept_ad_bits(void)
1166 return vmx_capability.ept & VMX_EPT_AD_BIT;
1169 static inline bool cpu_has_vmx_invept_context(void)
1171 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1174 static inline bool cpu_has_vmx_invept_global(void)
1176 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1179 static inline bool cpu_has_vmx_invvpid_single(void)
1181 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1184 static inline bool cpu_has_vmx_invvpid_global(void)
1186 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1189 static inline bool cpu_has_vmx_ept(void)
1191 return vmcs_config.cpu_based_2nd_exec_ctrl &
1192 SECONDARY_EXEC_ENABLE_EPT;
1195 static inline bool cpu_has_vmx_unrestricted_guest(void)
1197 return vmcs_config.cpu_based_2nd_exec_ctrl &
1198 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1201 static inline bool cpu_has_vmx_ple(void)
1203 return vmcs_config.cpu_based_2nd_exec_ctrl &
1204 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1207 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1209 return flexpriority_enabled && lapic_in_kernel(vcpu);
1212 static inline bool cpu_has_vmx_vpid(void)
1214 return vmcs_config.cpu_based_2nd_exec_ctrl &
1215 SECONDARY_EXEC_ENABLE_VPID;
1218 static inline bool cpu_has_vmx_rdtscp(void)
1220 return vmcs_config.cpu_based_2nd_exec_ctrl &
1221 SECONDARY_EXEC_RDTSCP;
1224 static inline bool cpu_has_vmx_invpcid(void)
1226 return vmcs_config.cpu_based_2nd_exec_ctrl &
1227 SECONDARY_EXEC_ENABLE_INVPCID;
1230 static inline bool cpu_has_virtual_nmis(void)
1232 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1235 static inline bool cpu_has_vmx_wbinvd_exit(void)
1237 return vmcs_config.cpu_based_2nd_exec_ctrl &
1238 SECONDARY_EXEC_WBINVD_EXITING;
1241 static inline bool cpu_has_vmx_shadow_vmcs(void)
1244 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1245 /* check if the cpu supports writing r/o exit information fields */
1246 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1249 return vmcs_config.cpu_based_2nd_exec_ctrl &
1250 SECONDARY_EXEC_SHADOW_VMCS;
1253 static inline bool cpu_has_vmx_pml(void)
1255 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1258 static inline bool cpu_has_vmx_tsc_scaling(void)
1260 return vmcs_config.cpu_based_2nd_exec_ctrl &
1261 SECONDARY_EXEC_TSC_SCALING;
1264 static inline bool report_flexpriority(void)
1266 return flexpriority_enabled;
1269 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1271 return vmcs12->cpu_based_vm_exec_control & bit;
1274 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1276 return (vmcs12->cpu_based_vm_exec_control &
1277 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1278 (vmcs12->secondary_vm_exec_control & bit);
1281 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1283 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1286 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1288 return vmcs12->pin_based_vm_exec_control &
1289 PIN_BASED_VMX_PREEMPTION_TIMER;
1292 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1294 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1297 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1299 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1300 vmx_xsaves_supported();
1303 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1305 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1308 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1310 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1313 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1315 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1318 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1320 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1323 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1325 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1328 static inline bool is_exception(u32 intr_info)
1330 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1331 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1334 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1336 unsigned long exit_qualification);
1337 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1338 struct vmcs12 *vmcs12,
1339 u32 reason, unsigned long qualification);
1341 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1345 for (i = 0; i < vmx->nmsrs; ++i)
1346 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1351 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1357 } operand = { vpid, 0, gva };
1359 asm volatile (__ex(ASM_VMX_INVVPID)
1360 /* CF==1 or ZF==1 --> rc = -1 */
1361 "; ja 1f ; ud2 ; 1:"
1362 : : "a"(&operand), "c"(ext) : "cc", "memory");
1365 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1369 } operand = {eptp, gpa};
1371 asm volatile (__ex(ASM_VMX_INVEPT)
1372 /* CF==1 or ZF==1 --> rc = -1 */
1373 "; ja 1f ; ud2 ; 1:\n"
1374 : : "a" (&operand), "c" (ext) : "cc", "memory");
1377 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1381 i = __find_msr_index(vmx, msr);
1383 return &vmx->guest_msrs[i];
1387 static void vmcs_clear(struct vmcs *vmcs)
1389 u64 phys_addr = __pa(vmcs);
1392 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1393 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1396 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1400 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1402 vmcs_clear(loaded_vmcs->vmcs);
1403 loaded_vmcs->cpu = -1;
1404 loaded_vmcs->launched = 0;
1407 static void vmcs_load(struct vmcs *vmcs)
1409 u64 phys_addr = __pa(vmcs);
1412 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1413 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1416 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1420 #ifdef CONFIG_KEXEC_CORE
1422 * This bitmap is used to indicate whether the vmclear
1423 * operation is enabled on all cpus. All disabled by
1426 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1428 static inline void crash_enable_local_vmclear(int cpu)
1430 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1433 static inline void crash_disable_local_vmclear(int cpu)
1435 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1438 static inline int crash_local_vmclear_enabled(int cpu)
1440 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1443 static void crash_vmclear_local_loaded_vmcss(void)
1445 int cpu = raw_smp_processor_id();
1446 struct loaded_vmcs *v;
1448 if (!crash_local_vmclear_enabled(cpu))
1451 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1452 loaded_vmcss_on_cpu_link)
1453 vmcs_clear(v->vmcs);
1456 static inline void crash_enable_local_vmclear(int cpu) { }
1457 static inline void crash_disable_local_vmclear(int cpu) { }
1458 #endif /* CONFIG_KEXEC_CORE */
1460 static void __loaded_vmcs_clear(void *arg)
1462 struct loaded_vmcs *loaded_vmcs = arg;
1463 int cpu = raw_smp_processor_id();
1465 if (loaded_vmcs->cpu != cpu)
1466 return; /* vcpu migration can race with cpu offline */
1467 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1468 per_cpu(current_vmcs, cpu) = NULL;
1469 crash_disable_local_vmclear(cpu);
1470 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1473 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1474 * is before setting loaded_vmcs->vcpu to -1 which is done in
1475 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1476 * then adds the vmcs into percpu list before it is deleted.
1480 loaded_vmcs_init(loaded_vmcs);
1481 crash_enable_local_vmclear(cpu);
1484 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1486 int cpu = loaded_vmcs->cpu;
1489 smp_call_function_single(cpu,
1490 __loaded_vmcs_clear, loaded_vmcs, 1);
1493 static inline void vpid_sync_vcpu_single(int vpid)
1498 if (cpu_has_vmx_invvpid_single())
1499 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1502 static inline void vpid_sync_vcpu_global(void)
1504 if (cpu_has_vmx_invvpid_global())
1505 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1508 static inline void vpid_sync_context(int vpid)
1510 if (cpu_has_vmx_invvpid_single())
1511 vpid_sync_vcpu_single(vpid);
1513 vpid_sync_vcpu_global();
1516 static inline void ept_sync_global(void)
1518 if (cpu_has_vmx_invept_global())
1519 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1522 static inline void ept_sync_context(u64 eptp)
1525 if (cpu_has_vmx_invept_context())
1526 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1532 static __always_inline void vmcs_check16(unsigned long field)
1534 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1535 "16-bit accessor invalid for 64-bit field");
1536 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1537 "16-bit accessor invalid for 64-bit high field");
1538 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1539 "16-bit accessor invalid for 32-bit high field");
1540 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1541 "16-bit accessor invalid for natural width field");
1544 static __always_inline void vmcs_check32(unsigned long field)
1546 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1547 "32-bit accessor invalid for 16-bit field");
1548 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1549 "32-bit accessor invalid for natural width field");
1552 static __always_inline void vmcs_check64(unsigned long field)
1554 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1555 "64-bit accessor invalid for 16-bit field");
1556 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1557 "64-bit accessor invalid for 64-bit high field");
1558 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1559 "64-bit accessor invalid for 32-bit field");
1560 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1561 "64-bit accessor invalid for natural width field");
1564 static __always_inline void vmcs_checkl(unsigned long field)
1566 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1567 "Natural width accessor invalid for 16-bit field");
1568 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1569 "Natural width accessor invalid for 64-bit field");
1570 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1571 "Natural width accessor invalid for 64-bit high field");
1572 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1573 "Natural width accessor invalid for 32-bit field");
1576 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1578 unsigned long value;
1580 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1581 : "=a"(value) : "d"(field) : "cc");
1585 static __always_inline u16 vmcs_read16(unsigned long field)
1587 vmcs_check16(field);
1588 return __vmcs_readl(field);
1591 static __always_inline u32 vmcs_read32(unsigned long field)
1593 vmcs_check32(field);
1594 return __vmcs_readl(field);
1597 static __always_inline u64 vmcs_read64(unsigned long field)
1599 vmcs_check64(field);
1600 #ifdef CONFIG_X86_64
1601 return __vmcs_readl(field);
1603 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1607 static __always_inline unsigned long vmcs_readl(unsigned long field)
1610 return __vmcs_readl(field);
1613 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1615 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1616 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1620 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1624 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1625 : "=q"(error) : "a"(value), "d"(field) : "cc");
1626 if (unlikely(error))
1627 vmwrite_error(field, value);
1630 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1632 vmcs_check16(field);
1633 __vmcs_writel(field, value);
1636 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1638 vmcs_check32(field);
1639 __vmcs_writel(field, value);
1642 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1644 vmcs_check64(field);
1645 __vmcs_writel(field, value);
1646 #ifndef CONFIG_X86_64
1648 __vmcs_writel(field+1, value >> 32);
1652 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1655 __vmcs_writel(field, value);
1658 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1660 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1661 "vmcs_clear_bits does not support 64-bit fields");
1662 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1665 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1667 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1668 "vmcs_set_bits does not support 64-bit fields");
1669 __vmcs_writel(field, __vmcs_readl(field) | mask);
1672 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1674 vmcs_write32(VM_ENTRY_CONTROLS, val);
1675 vmx->vm_entry_controls_shadow = val;
1678 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1680 if (vmx->vm_entry_controls_shadow != val)
1681 vm_entry_controls_init(vmx, val);
1684 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1686 return vmx->vm_entry_controls_shadow;
1690 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1692 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1695 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1697 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1700 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1702 vmcs_write32(VM_EXIT_CONTROLS, val);
1703 vmx->vm_exit_controls_shadow = val;
1706 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1708 if (vmx->vm_exit_controls_shadow != val)
1709 vm_exit_controls_init(vmx, val);
1712 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1714 return vmx->vm_exit_controls_shadow;
1718 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1720 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1723 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1725 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1728 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1730 vmx->segment_cache.bitmask = 0;
1733 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1737 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1739 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1740 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1741 vmx->segment_cache.bitmask = 0;
1743 ret = vmx->segment_cache.bitmask & mask;
1744 vmx->segment_cache.bitmask |= mask;
1748 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1750 u16 *p = &vmx->segment_cache.seg[seg].selector;
1752 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1753 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1757 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1759 ulong *p = &vmx->segment_cache.seg[seg].base;
1761 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1762 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1766 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1768 u32 *p = &vmx->segment_cache.seg[seg].limit;
1770 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1771 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1775 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1777 u32 *p = &vmx->segment_cache.seg[seg].ar;
1779 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1780 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1784 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1788 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1789 (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1790 if ((vcpu->guest_debug &
1791 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1792 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1793 eb |= 1u << BP_VECTOR;
1794 if (to_vmx(vcpu)->rmode.vm86_active)
1797 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1798 if (vcpu->fpu_active)
1799 eb &= ~(1u << NM_VECTOR);
1801 /* When we are running a nested L2 guest and L1 specified for it a
1802 * certain exception bitmap, we must trap the same exceptions and pass
1803 * them to L1. When running L2, we will only handle the exceptions
1804 * specified above if L1 did not want them.
1806 if (is_guest_mode(vcpu))
1807 eb |= get_vmcs12(vcpu)->exception_bitmap;
1809 vmcs_write32(EXCEPTION_BITMAP, eb);
1812 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1813 unsigned long entry, unsigned long exit)
1815 vm_entry_controls_clearbit(vmx, entry);
1816 vm_exit_controls_clearbit(vmx, exit);
1819 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1822 struct msr_autoload *m = &vmx->msr_autoload;
1826 if (cpu_has_load_ia32_efer) {
1827 clear_atomic_switch_msr_special(vmx,
1828 VM_ENTRY_LOAD_IA32_EFER,
1829 VM_EXIT_LOAD_IA32_EFER);
1833 case MSR_CORE_PERF_GLOBAL_CTRL:
1834 if (cpu_has_load_perf_global_ctrl) {
1835 clear_atomic_switch_msr_special(vmx,
1836 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1837 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1843 for (i = 0; i < m->nr; ++i)
1844 if (m->guest[i].index == msr)
1850 m->guest[i] = m->guest[m->nr];
1851 m->host[i] = m->host[m->nr];
1852 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1853 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1856 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1857 unsigned long entry, unsigned long exit,
1858 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1859 u64 guest_val, u64 host_val)
1861 vmcs_write64(guest_val_vmcs, guest_val);
1862 vmcs_write64(host_val_vmcs, host_val);
1863 vm_entry_controls_setbit(vmx, entry);
1864 vm_exit_controls_setbit(vmx, exit);
1867 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1868 u64 guest_val, u64 host_val)
1871 struct msr_autoload *m = &vmx->msr_autoload;
1875 if (cpu_has_load_ia32_efer) {
1876 add_atomic_switch_msr_special(vmx,
1877 VM_ENTRY_LOAD_IA32_EFER,
1878 VM_EXIT_LOAD_IA32_EFER,
1881 guest_val, host_val);
1885 case MSR_CORE_PERF_GLOBAL_CTRL:
1886 if (cpu_has_load_perf_global_ctrl) {
1887 add_atomic_switch_msr_special(vmx,
1888 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1889 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1890 GUEST_IA32_PERF_GLOBAL_CTRL,
1891 HOST_IA32_PERF_GLOBAL_CTRL,
1892 guest_val, host_val);
1896 case MSR_IA32_PEBS_ENABLE:
1897 /* PEBS needs a quiescent period after being disabled (to write
1898 * a record). Disabling PEBS through VMX MSR swapping doesn't
1899 * provide that period, so a CPU could write host's record into
1902 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1905 for (i = 0; i < m->nr; ++i)
1906 if (m->guest[i].index == msr)
1909 if (i == NR_AUTOLOAD_MSRS) {
1910 printk_once(KERN_WARNING "Not enough msr switch entries. "
1911 "Can't add msr %x\n", msr);
1913 } else if (i == m->nr) {
1915 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1916 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1919 m->guest[i].index = msr;
1920 m->guest[i].value = guest_val;
1921 m->host[i].index = msr;
1922 m->host[i].value = host_val;
1925 static void reload_tss(void)
1928 * VT restores TR but not its size. Useless.
1930 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1931 struct desc_struct *descs;
1933 descs = (void *)gdt->address;
1934 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1938 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1940 u64 guest_efer = vmx->vcpu.arch.efer;
1941 u64 ignore_bits = 0;
1945 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
1946 * host CPUID is more efficient than testing guest CPUID
1947 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
1949 if (boot_cpu_has(X86_FEATURE_SMEP))
1950 guest_efer |= EFER_NX;
1951 else if (!(guest_efer & EFER_NX))
1952 ignore_bits |= EFER_NX;
1956 * LMA and LME handled by hardware; SCE meaningless outside long mode.
1958 ignore_bits |= EFER_SCE;
1959 #ifdef CONFIG_X86_64
1960 ignore_bits |= EFER_LMA | EFER_LME;
1961 /* SCE is meaningful only in long mode on Intel */
1962 if (guest_efer & EFER_LMA)
1963 ignore_bits &= ~(u64)EFER_SCE;
1966 clear_atomic_switch_msr(vmx, MSR_EFER);
1969 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1970 * On CPUs that support "load IA32_EFER", always switch EFER
1971 * atomically, since it's faster than switching it manually.
1973 if (cpu_has_load_ia32_efer ||
1974 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1975 if (!(guest_efer & EFER_LMA))
1976 guest_efer &= ~EFER_LME;
1977 if (guest_efer != host_efer)
1978 add_atomic_switch_msr(vmx, MSR_EFER,
1979 guest_efer, host_efer);
1982 guest_efer &= ~ignore_bits;
1983 guest_efer |= host_efer & ignore_bits;
1985 vmx->guest_msrs[efer_offset].data = guest_efer;
1986 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1992 static unsigned long segment_base(u16 selector)
1994 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1995 struct desc_struct *d;
1996 unsigned long table_base;
1999 if (!(selector & ~3))
2002 table_base = gdt->address;
2004 if (selector & 4) { /* from ldt */
2005 u16 ldt_selector = kvm_read_ldt();
2007 if (!(ldt_selector & ~3))
2010 table_base = segment_base(ldt_selector);
2012 d = (struct desc_struct *)(table_base + (selector & ~7));
2013 v = get_desc_base(d);
2014 #ifdef CONFIG_X86_64
2015 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
2016 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
2021 static inline unsigned long kvm_read_tr_base(void)
2024 asm("str %0" : "=g"(tr));
2025 return segment_base(tr);
2028 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2030 struct vcpu_vmx *vmx = to_vmx(vcpu);
2033 if (vmx->host_state.loaded)
2036 vmx->host_state.loaded = 1;
2038 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2039 * allow segment selectors with cpl > 0 or ti == 1.
2041 vmx->host_state.ldt_sel = kvm_read_ldt();
2042 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2043 savesegment(fs, vmx->host_state.fs_sel);
2044 if (!(vmx->host_state.fs_sel & 7)) {
2045 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2046 vmx->host_state.fs_reload_needed = 0;
2048 vmcs_write16(HOST_FS_SELECTOR, 0);
2049 vmx->host_state.fs_reload_needed = 1;
2051 savesegment(gs, vmx->host_state.gs_sel);
2052 if (!(vmx->host_state.gs_sel & 7))
2053 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2055 vmcs_write16(HOST_GS_SELECTOR, 0);
2056 vmx->host_state.gs_ldt_reload_needed = 1;
2059 #ifdef CONFIG_X86_64
2060 savesegment(ds, vmx->host_state.ds_sel);
2061 savesegment(es, vmx->host_state.es_sel);
2064 #ifdef CONFIG_X86_64
2065 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2066 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2068 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2069 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2072 #ifdef CONFIG_X86_64
2073 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2074 if (is_long_mode(&vmx->vcpu))
2075 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2077 if (boot_cpu_has(X86_FEATURE_MPX))
2078 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2079 for (i = 0; i < vmx->save_nmsrs; ++i)
2080 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2081 vmx->guest_msrs[i].data,
2082 vmx->guest_msrs[i].mask);
2085 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2087 if (!vmx->host_state.loaded)
2090 ++vmx->vcpu.stat.host_state_reload;
2091 vmx->host_state.loaded = 0;
2092 #ifdef CONFIG_X86_64
2093 if (is_long_mode(&vmx->vcpu))
2094 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2096 if (vmx->host_state.gs_ldt_reload_needed) {
2097 kvm_load_ldt(vmx->host_state.ldt_sel);
2098 #ifdef CONFIG_X86_64
2099 load_gs_index(vmx->host_state.gs_sel);
2101 loadsegment(gs, vmx->host_state.gs_sel);
2104 if (vmx->host_state.fs_reload_needed)
2105 loadsegment(fs, vmx->host_state.fs_sel);
2106 #ifdef CONFIG_X86_64
2107 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2108 loadsegment(ds, vmx->host_state.ds_sel);
2109 loadsegment(es, vmx->host_state.es_sel);
2113 #ifdef CONFIG_X86_64
2114 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2116 if (vmx->host_state.msr_host_bndcfgs)
2117 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2119 * If the FPU is not active (through the host task or
2120 * the guest vcpu), then restore the cr0.TS bit.
2122 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2124 load_gdt(this_cpu_ptr(&host_gdt));
2127 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2130 __vmx_load_host_state(vmx);
2134 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2136 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2137 struct pi_desc old, new;
2140 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2141 !irq_remapping_cap(IRQ_POSTING_CAP))
2145 old.control = new.control = pi_desc->control;
2148 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2149 * are two possible cases:
2150 * 1. After running 'pre_block', context switch
2151 * happened. For this case, 'sn' was set in
2152 * vmx_vcpu_put(), so we need to clear it here.
2153 * 2. After running 'pre_block', we were blocked,
2154 * and woken up by some other guy. For this case,
2155 * we don't need to do anything, 'pi_post_block'
2156 * will do everything for us. However, we cannot
2157 * check whether it is case #1 or case #2 here
2158 * (maybe, not needed), so we also clear sn here,
2159 * I think it is not a big deal.
2161 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2162 if (vcpu->cpu != cpu) {
2163 dest = cpu_physical_id(cpu);
2165 if (x2apic_enabled())
2168 new.ndst = (dest << 8) & 0xFF00;
2171 /* set 'NV' to 'notification vector' */
2172 new.nv = POSTED_INTR_VECTOR;
2175 /* Allow posting non-urgent interrupts */
2177 } while (cmpxchg(&pi_desc->control, old.control,
2178 new.control) != old.control);
2182 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2183 * vcpu mutex is already taken.
2185 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2187 struct vcpu_vmx *vmx = to_vmx(vcpu);
2188 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2191 kvm_cpu_vmxon(phys_addr);
2192 else if (vmx->loaded_vmcs->cpu != cpu)
2193 loaded_vmcs_clear(vmx->loaded_vmcs);
2195 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2196 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2197 vmcs_load(vmx->loaded_vmcs->vmcs);
2200 if (vmx->loaded_vmcs->cpu != cpu) {
2201 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2202 unsigned long sysenter_esp;
2204 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2205 local_irq_disable();
2206 crash_disable_local_vmclear(cpu);
2209 * Read loaded_vmcs->cpu should be before fetching
2210 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2211 * See the comments in __loaded_vmcs_clear().
2215 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2216 &per_cpu(loaded_vmcss_on_cpu, cpu));
2217 crash_enable_local_vmclear(cpu);
2221 * Linux uses per-cpu TSS and GDT, so set these when switching
2224 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2225 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
2227 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2228 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2230 vmx->loaded_vmcs->cpu = cpu;
2233 /* Setup TSC multiplier */
2234 if (kvm_has_tsc_control &&
2235 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2236 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2237 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2240 vmx_vcpu_pi_load(vcpu, cpu);
2241 vmx->host_pkru = read_pkru();
2244 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2246 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2248 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2249 !irq_remapping_cap(IRQ_POSTING_CAP))
2252 /* Set SN when the vCPU is preempted */
2253 if (vcpu->preempted)
2257 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2259 vmx_vcpu_pi_put(vcpu);
2261 __vmx_load_host_state(to_vmx(vcpu));
2262 if (!vmm_exclusive) {
2263 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2269 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2273 if (vcpu->fpu_active)
2275 vcpu->fpu_active = 1;
2276 cr0 = vmcs_readl(GUEST_CR0);
2277 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2278 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2279 vmcs_writel(GUEST_CR0, cr0);
2280 update_exception_bitmap(vcpu);
2281 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2282 if (is_guest_mode(vcpu))
2283 vcpu->arch.cr0_guest_owned_bits &=
2284 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2285 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2288 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2291 * Return the cr0 value that a nested guest would read. This is a combination
2292 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2293 * its hypervisor (cr0_read_shadow).
2295 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2297 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2298 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2300 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2302 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2303 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2306 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2308 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2309 * set this *before* calling this function.
2311 vmx_decache_cr0_guest_bits(vcpu);
2312 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2313 update_exception_bitmap(vcpu);
2314 vcpu->arch.cr0_guest_owned_bits = 0;
2315 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2316 if (is_guest_mode(vcpu)) {
2318 * L1's specified read shadow might not contain the TS bit,
2319 * so now that we turned on shadowing of this bit, we need to
2320 * set this bit of the shadow. Like in nested_vmx_run we need
2321 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2322 * up-to-date here because we just decached cr0.TS (and we'll
2323 * only update vmcs12->guest_cr0 on nested exit).
2325 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2326 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2327 (vcpu->arch.cr0 & X86_CR0_TS);
2328 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2330 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2333 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2335 unsigned long rflags, save_rflags;
2337 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2338 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2339 rflags = vmcs_readl(GUEST_RFLAGS);
2340 if (to_vmx(vcpu)->rmode.vm86_active) {
2341 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2342 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2343 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2345 to_vmx(vcpu)->rflags = rflags;
2347 return to_vmx(vcpu)->rflags;
2350 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2352 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2353 to_vmx(vcpu)->rflags = rflags;
2354 if (to_vmx(vcpu)->rmode.vm86_active) {
2355 to_vmx(vcpu)->rmode.save_rflags = rflags;
2356 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2358 vmcs_writel(GUEST_RFLAGS, rflags);
2361 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2363 return to_vmx(vcpu)->guest_pkru;
2366 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2368 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2371 if (interruptibility & GUEST_INTR_STATE_STI)
2372 ret |= KVM_X86_SHADOW_INT_STI;
2373 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2374 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2379 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2381 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2382 u32 interruptibility = interruptibility_old;
2384 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2386 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2387 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2388 else if (mask & KVM_X86_SHADOW_INT_STI)
2389 interruptibility |= GUEST_INTR_STATE_STI;
2391 if ((interruptibility != interruptibility_old))
2392 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2395 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2399 rip = kvm_rip_read(vcpu);
2400 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2401 kvm_rip_write(vcpu, rip);
2403 /* skipping an emulated instruction also counts */
2404 vmx_set_interrupt_shadow(vcpu, 0);
2408 * KVM wants to inject page-faults which it got to the guest. This function
2409 * checks whether in a nested guest, we need to inject them to L1 or L2.
2411 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2413 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2415 if (!(vmcs12->exception_bitmap & (1u << nr)))
2418 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2419 vmcs_read32(VM_EXIT_INTR_INFO),
2420 vmcs_readl(EXIT_QUALIFICATION));
2424 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2425 bool has_error_code, u32 error_code,
2428 struct vcpu_vmx *vmx = to_vmx(vcpu);
2429 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2431 if (!reinject && is_guest_mode(vcpu) &&
2432 nested_vmx_check_exception(vcpu, nr))
2435 if (has_error_code) {
2436 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2437 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2440 if (vmx->rmode.vm86_active) {
2442 if (kvm_exception_is_soft(nr))
2443 inc_eip = vcpu->arch.event_exit_inst_len;
2444 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2445 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2449 if (kvm_exception_is_soft(nr)) {
2450 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2451 vmx->vcpu.arch.event_exit_inst_len);
2452 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2454 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2456 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2459 static bool vmx_rdtscp_supported(void)
2461 return cpu_has_vmx_rdtscp();
2464 static bool vmx_invpcid_supported(void)
2466 return cpu_has_vmx_invpcid() && enable_ept;
2470 * Swap MSR entry in host/guest MSR entry array.
2472 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2474 struct shared_msr_entry tmp;
2476 tmp = vmx->guest_msrs[to];
2477 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2478 vmx->guest_msrs[from] = tmp;
2481 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2483 unsigned long *msr_bitmap;
2485 if (is_guest_mode(vcpu))
2486 msr_bitmap = vmx_msr_bitmap_nested;
2487 else if (cpu_has_secondary_exec_ctrls() &&
2488 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2489 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2490 if (is_long_mode(vcpu))
2491 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2493 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2495 if (is_long_mode(vcpu))
2496 msr_bitmap = vmx_msr_bitmap_longmode;
2498 msr_bitmap = vmx_msr_bitmap_legacy;
2501 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2505 * Set up the vmcs to automatically save and restore system
2506 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2507 * mode, as fiddling with msrs is very expensive.
2509 static void setup_msrs(struct vcpu_vmx *vmx)
2511 int save_nmsrs, index;
2514 #ifdef CONFIG_X86_64
2515 if (is_long_mode(&vmx->vcpu)) {
2516 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2518 move_msr_up(vmx, index, save_nmsrs++);
2519 index = __find_msr_index(vmx, MSR_LSTAR);
2521 move_msr_up(vmx, index, save_nmsrs++);
2522 index = __find_msr_index(vmx, MSR_CSTAR);
2524 move_msr_up(vmx, index, save_nmsrs++);
2525 index = __find_msr_index(vmx, MSR_TSC_AUX);
2526 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2527 move_msr_up(vmx, index, save_nmsrs++);
2529 * MSR_STAR is only needed on long mode guests, and only
2530 * if efer.sce is enabled.
2532 index = __find_msr_index(vmx, MSR_STAR);
2533 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2534 move_msr_up(vmx, index, save_nmsrs++);
2537 index = __find_msr_index(vmx, MSR_EFER);
2538 if (index >= 0 && update_transition_efer(vmx, index))
2539 move_msr_up(vmx, index, save_nmsrs++);
2541 vmx->save_nmsrs = save_nmsrs;
2543 if (cpu_has_vmx_msr_bitmap())
2544 vmx_set_msr_bitmap(&vmx->vcpu);
2548 * reads and returns guest's timestamp counter "register"
2549 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2550 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2552 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2554 u64 host_tsc, tsc_offset;
2557 tsc_offset = vmcs_read64(TSC_OFFSET);
2558 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2562 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2563 * counter, even if a nested guest (L2) is currently running.
2565 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2569 tsc_offset = is_guest_mode(vcpu) ?
2570 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2571 vmcs_read64(TSC_OFFSET);
2572 return host_tsc + tsc_offset;
2575 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2577 return vmcs_read64(TSC_OFFSET);
2581 * writes 'offset' into guest's timestamp counter offset register
2583 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2585 if (is_guest_mode(vcpu)) {
2587 * We're here if L1 chose not to trap WRMSR to TSC. According
2588 * to the spec, this should set L1's TSC; The offset that L1
2589 * set for L2 remains unchanged, and still needs to be added
2590 * to the newly set TSC to get L2's TSC.
2592 struct vmcs12 *vmcs12;
2593 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2594 /* recalculate vmcs02.TSC_OFFSET: */
2595 vmcs12 = get_vmcs12(vcpu);
2596 vmcs_write64(TSC_OFFSET, offset +
2597 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2598 vmcs12->tsc_offset : 0));
2600 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2601 vmcs_read64(TSC_OFFSET), offset);
2602 vmcs_write64(TSC_OFFSET, offset);
2606 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2608 u64 offset = vmcs_read64(TSC_OFFSET);
2610 vmcs_write64(TSC_OFFSET, offset + adjustment);
2611 if (is_guest_mode(vcpu)) {
2612 /* Even when running L2, the adjustment needs to apply to L1 */
2613 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2615 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2616 offset + adjustment);
2619 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2621 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2622 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2626 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2627 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2628 * all guests if the "nested" module option is off, and can also be disabled
2629 * for a single guest by disabling its VMX cpuid bit.
2631 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2633 return nested && guest_cpuid_has_vmx(vcpu);
2637 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2638 * returned for the various VMX controls MSRs when nested VMX is enabled.
2639 * The same values should also be used to verify that vmcs12 control fields are
2640 * valid during nested entry from L1 to L2.
2641 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2642 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2643 * bit in the high half is on if the corresponding bit in the control field
2644 * may be on. See also vmx_control_verify().
2646 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2649 * Note that as a general rule, the high half of the MSRs (bits in
2650 * the control fields which may be 1) should be initialized by the
2651 * intersection of the underlying hardware's MSR (i.e., features which
2652 * can be supported) and the list of features we want to expose -
2653 * because they are known to be properly supported in our code.
2654 * Also, usually, the low half of the MSRs (bits which must be 1) can
2655 * be set to 0, meaning that L1 may turn off any of these bits. The
2656 * reason is that if one of these bits is necessary, it will appear
2657 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2658 * fields of vmcs01 and vmcs02, will turn these bits off - and
2659 * nested_vmx_exit_handled() will not pass related exits to L1.
2660 * These rules have exceptions below.
2663 /* pin-based controls */
2664 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2665 vmx->nested.nested_vmx_pinbased_ctls_low,
2666 vmx->nested.nested_vmx_pinbased_ctls_high);
2667 vmx->nested.nested_vmx_pinbased_ctls_low |=
2668 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2669 vmx->nested.nested_vmx_pinbased_ctls_high &=
2670 PIN_BASED_EXT_INTR_MASK |
2671 PIN_BASED_NMI_EXITING |
2672 PIN_BASED_VIRTUAL_NMIS;
2673 vmx->nested.nested_vmx_pinbased_ctls_high |=
2674 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2675 PIN_BASED_VMX_PREEMPTION_TIMER;
2676 if (kvm_vcpu_apicv_active(&vmx->vcpu))
2677 vmx->nested.nested_vmx_pinbased_ctls_high |=
2678 PIN_BASED_POSTED_INTR;
2681 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2682 vmx->nested.nested_vmx_exit_ctls_low,
2683 vmx->nested.nested_vmx_exit_ctls_high);
2684 vmx->nested.nested_vmx_exit_ctls_low =
2685 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2687 vmx->nested.nested_vmx_exit_ctls_high &=
2688 #ifdef CONFIG_X86_64
2689 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2691 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2692 vmx->nested.nested_vmx_exit_ctls_high |=
2693 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2694 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2695 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2697 if (kvm_mpx_supported())
2698 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2700 /* We support free control of debug control saving. */
2701 vmx->nested.nested_vmx_true_exit_ctls_low =
2702 vmx->nested.nested_vmx_exit_ctls_low &
2703 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2705 /* entry controls */
2706 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2707 vmx->nested.nested_vmx_entry_ctls_low,
2708 vmx->nested.nested_vmx_entry_ctls_high);
2709 vmx->nested.nested_vmx_entry_ctls_low =
2710 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2711 vmx->nested.nested_vmx_entry_ctls_high &=
2712 #ifdef CONFIG_X86_64
2713 VM_ENTRY_IA32E_MODE |
2715 VM_ENTRY_LOAD_IA32_PAT;
2716 vmx->nested.nested_vmx_entry_ctls_high |=
2717 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2718 if (kvm_mpx_supported())
2719 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2721 /* We support free control of debug control loading. */
2722 vmx->nested.nested_vmx_true_entry_ctls_low =
2723 vmx->nested.nested_vmx_entry_ctls_low &
2724 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2726 /* cpu-based controls */
2727 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2728 vmx->nested.nested_vmx_procbased_ctls_low,
2729 vmx->nested.nested_vmx_procbased_ctls_high);
2730 vmx->nested.nested_vmx_procbased_ctls_low =
2731 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2732 vmx->nested.nested_vmx_procbased_ctls_high &=
2733 CPU_BASED_VIRTUAL_INTR_PENDING |
2734 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2735 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2736 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2737 CPU_BASED_CR3_STORE_EXITING |
2738 #ifdef CONFIG_X86_64
2739 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2741 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2742 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2743 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2744 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2745 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2747 * We can allow some features even when not supported by the
2748 * hardware. For example, L1 can specify an MSR bitmap - and we
2749 * can use it to avoid exits to L1 - even when L0 runs L2
2750 * without MSR bitmaps.
2752 vmx->nested.nested_vmx_procbased_ctls_high |=
2753 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2754 CPU_BASED_USE_MSR_BITMAPS;
2756 /* We support free control of CR3 access interception. */
2757 vmx->nested.nested_vmx_true_procbased_ctls_low =
2758 vmx->nested.nested_vmx_procbased_ctls_low &
2759 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2761 /* secondary cpu-based controls */
2762 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2763 vmx->nested.nested_vmx_secondary_ctls_low,
2764 vmx->nested.nested_vmx_secondary_ctls_high);
2765 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2766 vmx->nested.nested_vmx_secondary_ctls_high &=
2767 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2768 SECONDARY_EXEC_RDTSCP |
2769 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2770 SECONDARY_EXEC_ENABLE_VPID |
2771 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2772 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2773 SECONDARY_EXEC_WBINVD_EXITING |
2774 SECONDARY_EXEC_XSAVES |
2775 SECONDARY_EXEC_PCOMMIT;
2778 /* nested EPT: emulate EPT also to L1 */
2779 vmx->nested.nested_vmx_secondary_ctls_high |=
2780 SECONDARY_EXEC_ENABLE_EPT;
2781 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2782 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2784 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2786 * For nested guests, we don't do anything specific
2787 * for single context invalidation. Hence, only advertise
2788 * support for global context invalidation.
2790 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2792 vmx->nested.nested_vmx_ept_caps = 0;
2795 * Old versions of KVM use the single-context version without
2796 * checking for support, so declare that it is supported even
2797 * though it is treated as global context. The alternative is
2798 * not failing the single-context invvpid, and it is worse.
2801 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2802 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2803 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2805 vmx->nested.nested_vmx_vpid_caps = 0;
2807 if (enable_unrestricted_guest)
2808 vmx->nested.nested_vmx_secondary_ctls_high |=
2809 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2811 /* miscellaneous data */
2812 rdmsr(MSR_IA32_VMX_MISC,
2813 vmx->nested.nested_vmx_misc_low,
2814 vmx->nested.nested_vmx_misc_high);
2815 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2816 vmx->nested.nested_vmx_misc_low |=
2817 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2818 VMX_MISC_ACTIVITY_HLT;
2819 vmx->nested.nested_vmx_misc_high = 0;
2822 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2825 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2827 return ((control & high) | low) == control;
2830 static inline u64 vmx_control_msr(u32 low, u32 high)
2832 return low | ((u64)high << 32);
2835 /* Returns 0 on success, non-0 otherwise. */
2836 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2838 struct vcpu_vmx *vmx = to_vmx(vcpu);
2840 switch (msr_index) {
2841 case MSR_IA32_VMX_BASIC:
2843 * This MSR reports some information about VMX support. We
2844 * should return information about the VMX we emulate for the
2845 * guest, and the VMCS structure we give it - not about the
2846 * VMX support of the underlying hardware.
2848 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2849 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2850 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2852 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2853 case MSR_IA32_VMX_PINBASED_CTLS:
2854 *pdata = vmx_control_msr(
2855 vmx->nested.nested_vmx_pinbased_ctls_low,
2856 vmx->nested.nested_vmx_pinbased_ctls_high);
2858 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2859 *pdata = vmx_control_msr(
2860 vmx->nested.nested_vmx_true_procbased_ctls_low,
2861 vmx->nested.nested_vmx_procbased_ctls_high);
2863 case MSR_IA32_VMX_PROCBASED_CTLS:
2864 *pdata = vmx_control_msr(
2865 vmx->nested.nested_vmx_procbased_ctls_low,
2866 vmx->nested.nested_vmx_procbased_ctls_high);
2868 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2869 *pdata = vmx_control_msr(
2870 vmx->nested.nested_vmx_true_exit_ctls_low,
2871 vmx->nested.nested_vmx_exit_ctls_high);
2873 case MSR_IA32_VMX_EXIT_CTLS:
2874 *pdata = vmx_control_msr(
2875 vmx->nested.nested_vmx_exit_ctls_low,
2876 vmx->nested.nested_vmx_exit_ctls_high);
2878 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2879 *pdata = vmx_control_msr(
2880 vmx->nested.nested_vmx_true_entry_ctls_low,
2881 vmx->nested.nested_vmx_entry_ctls_high);
2883 case MSR_IA32_VMX_ENTRY_CTLS:
2884 *pdata = vmx_control_msr(
2885 vmx->nested.nested_vmx_entry_ctls_low,
2886 vmx->nested.nested_vmx_entry_ctls_high);
2888 case MSR_IA32_VMX_MISC:
2889 *pdata = vmx_control_msr(
2890 vmx->nested.nested_vmx_misc_low,
2891 vmx->nested.nested_vmx_misc_high);
2894 * These MSRs specify bits which the guest must keep fixed (on or off)
2895 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2896 * We picked the standard core2 setting.
2898 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2899 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2900 case MSR_IA32_VMX_CR0_FIXED0:
2901 *pdata = VMXON_CR0_ALWAYSON;
2903 case MSR_IA32_VMX_CR0_FIXED1:
2906 case MSR_IA32_VMX_CR4_FIXED0:
2907 *pdata = VMXON_CR4_ALWAYSON;
2909 case MSR_IA32_VMX_CR4_FIXED1:
2912 case MSR_IA32_VMX_VMCS_ENUM:
2913 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2915 case MSR_IA32_VMX_PROCBASED_CTLS2:
2916 *pdata = vmx_control_msr(
2917 vmx->nested.nested_vmx_secondary_ctls_low,
2918 vmx->nested.nested_vmx_secondary_ctls_high);
2920 case MSR_IA32_VMX_EPT_VPID_CAP:
2921 /* Currently, no nested vpid support */
2922 *pdata = vmx->nested.nested_vmx_ept_caps |
2923 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2933 * Reads an msr value (of 'msr_index') into 'pdata'.
2934 * Returns 0 on success, non-0 otherwise.
2935 * Assumes vcpu_load() was already called.
2937 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2939 struct shared_msr_entry *msr;
2941 switch (msr_info->index) {
2942 #ifdef CONFIG_X86_64
2944 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2947 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2949 case MSR_KERNEL_GS_BASE:
2950 vmx_load_host_state(to_vmx(vcpu));
2951 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2955 return kvm_get_msr_common(vcpu, msr_info);
2957 msr_info->data = guest_read_tsc(vcpu);
2959 case MSR_IA32_SYSENTER_CS:
2960 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2962 case MSR_IA32_SYSENTER_EIP:
2963 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2965 case MSR_IA32_SYSENTER_ESP:
2966 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2968 case MSR_IA32_BNDCFGS:
2969 if (!kvm_mpx_supported())
2971 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2973 case MSR_IA32_FEATURE_CONTROL:
2974 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
2976 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2977 if (!nested_vmx_allowed(vcpu))
2979 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2981 if (!vmx_xsaves_supported())
2983 msr_info->data = vcpu->arch.ia32_xss;
2986 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2988 /* Otherwise falls through */
2990 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2992 msr_info->data = msr->data;
2995 return kvm_get_msr_common(vcpu, msr_info);
3001 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3004 * Writes msr value into into the appropriate "register".
3005 * Returns 0 on success, non-0 otherwise.
3006 * Assumes vcpu_load() was already called.
3008 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3010 struct vcpu_vmx *vmx = to_vmx(vcpu);
3011 struct shared_msr_entry *msr;
3013 u32 msr_index = msr_info->index;
3014 u64 data = msr_info->data;
3016 switch (msr_index) {
3018 ret = kvm_set_msr_common(vcpu, msr_info);
3020 #ifdef CONFIG_X86_64
3022 vmx_segment_cache_clear(vmx);
3023 vmcs_writel(GUEST_FS_BASE, data);
3026 vmx_segment_cache_clear(vmx);
3027 vmcs_writel(GUEST_GS_BASE, data);
3029 case MSR_KERNEL_GS_BASE:
3030 vmx_load_host_state(vmx);
3031 vmx->msr_guest_kernel_gs_base = data;
3034 case MSR_IA32_SYSENTER_CS:
3035 vmcs_write32(GUEST_SYSENTER_CS, data);
3037 case MSR_IA32_SYSENTER_EIP:
3038 vmcs_writel(GUEST_SYSENTER_EIP, data);
3040 case MSR_IA32_SYSENTER_ESP:
3041 vmcs_writel(GUEST_SYSENTER_ESP, data);
3043 case MSR_IA32_BNDCFGS:
3044 if (!kvm_mpx_supported())
3046 vmcs_write64(GUEST_BNDCFGS, data);
3049 kvm_write_tsc(vcpu, msr_info);
3051 case MSR_IA32_CR_PAT:
3052 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3053 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3055 vmcs_write64(GUEST_IA32_PAT, data);
3056 vcpu->arch.pat = data;
3059 ret = kvm_set_msr_common(vcpu, msr_info);
3061 case MSR_IA32_TSC_ADJUST:
3062 ret = kvm_set_msr_common(vcpu, msr_info);
3064 case MSR_IA32_FEATURE_CONTROL:
3065 if (!nested_vmx_allowed(vcpu) ||
3066 (to_vmx(vcpu)->msr_ia32_feature_control &
3067 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3069 vmx->msr_ia32_feature_control = data;
3070 if (msr_info->host_initiated && data == 0)
3071 vmx_leave_nested(vcpu);
3073 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3074 return 1; /* they are read-only */
3076 if (!vmx_xsaves_supported())
3079 * The only supported bit as of Skylake is bit 8, but
3080 * it is not supported on KVM.
3084 vcpu->arch.ia32_xss = data;
3085 if (vcpu->arch.ia32_xss != host_xss)
3086 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3087 vcpu->arch.ia32_xss, host_xss);
3089 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3092 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3094 /* Check reserved bit, higher 32 bits should be zero */
3095 if ((data >> 32) != 0)
3097 /* Otherwise falls through */
3099 msr = find_msr_entry(vmx, msr_index);
3101 u64 old_msr_data = msr->data;
3103 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3105 ret = kvm_set_shared_msr(msr->index, msr->data,
3109 msr->data = old_msr_data;
3113 ret = kvm_set_msr_common(vcpu, msr_info);
3119 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3121 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3124 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3127 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3129 case VCPU_EXREG_PDPTR:
3131 ept_save_pdptrs(vcpu);
3138 static __init int cpu_has_kvm_support(void)
3140 return cpu_has_vmx();
3143 static __init int vmx_disabled_by_bios(void)
3147 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3148 if (msr & FEATURE_CONTROL_LOCKED) {
3149 /* launched w/ TXT and VMX disabled */
3150 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3153 /* launched w/o TXT and VMX only enabled w/ TXT */
3154 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3155 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3156 && !tboot_enabled()) {
3157 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3158 "activate TXT before enabling KVM\n");
3161 /* launched w/o TXT and VMX disabled */
3162 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3163 && !tboot_enabled())
3170 static void kvm_cpu_vmxon(u64 addr)
3172 intel_pt_handle_vmx(1);
3174 asm volatile (ASM_VMX_VMXON_RAX
3175 : : "a"(&addr), "m"(addr)
3179 static int hardware_enable(void)
3181 int cpu = raw_smp_processor_id();
3182 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3185 if (cr4_read_shadow() & X86_CR4_VMXE)
3188 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3189 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3190 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3193 * Now we can enable the vmclear operation in kdump
3194 * since the loaded_vmcss_on_cpu list on this cpu
3195 * has been initialized.
3197 * Though the cpu is not in VMX operation now, there
3198 * is no problem to enable the vmclear operation
3199 * for the loaded_vmcss_on_cpu list is empty!
3201 crash_enable_local_vmclear(cpu);
3203 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3205 test_bits = FEATURE_CONTROL_LOCKED;
3206 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3207 if (tboot_enabled())
3208 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3210 if ((old & test_bits) != test_bits) {
3211 /* enable and lock */
3212 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3214 cr4_set_bits(X86_CR4_VMXE);
3216 if (vmm_exclusive) {
3217 kvm_cpu_vmxon(phys_addr);
3221 native_store_gdt(this_cpu_ptr(&host_gdt));
3226 static void vmclear_local_loaded_vmcss(void)
3228 int cpu = raw_smp_processor_id();
3229 struct loaded_vmcs *v, *n;
3231 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3232 loaded_vmcss_on_cpu_link)
3233 __loaded_vmcs_clear(v);
3237 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3240 static void kvm_cpu_vmxoff(void)
3242 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3244 intel_pt_handle_vmx(0);
3247 static void hardware_disable(void)
3249 if (vmm_exclusive) {
3250 vmclear_local_loaded_vmcss();
3253 cr4_clear_bits(X86_CR4_VMXE);
3256 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3257 u32 msr, u32 *result)
3259 u32 vmx_msr_low, vmx_msr_high;
3260 u32 ctl = ctl_min | ctl_opt;
3262 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3264 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3265 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3267 /* Ensure minimum (required) set of control bits are supported. */
3275 static __init bool allow_1_setting(u32 msr, u32 ctl)
3277 u32 vmx_msr_low, vmx_msr_high;
3279 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3280 return vmx_msr_high & ctl;
3283 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3285 u32 vmx_msr_low, vmx_msr_high;
3286 u32 min, opt, min2, opt2;
3287 u32 _pin_based_exec_control = 0;
3288 u32 _cpu_based_exec_control = 0;
3289 u32 _cpu_based_2nd_exec_control = 0;
3290 u32 _vmexit_control = 0;
3291 u32 _vmentry_control = 0;
3293 min = CPU_BASED_HLT_EXITING |
3294 #ifdef CONFIG_X86_64
3295 CPU_BASED_CR8_LOAD_EXITING |
3296 CPU_BASED_CR8_STORE_EXITING |
3298 CPU_BASED_CR3_LOAD_EXITING |
3299 CPU_BASED_CR3_STORE_EXITING |
3300 CPU_BASED_USE_IO_BITMAPS |
3301 CPU_BASED_MOV_DR_EXITING |
3302 CPU_BASED_USE_TSC_OFFSETING |
3303 CPU_BASED_MWAIT_EXITING |
3304 CPU_BASED_MONITOR_EXITING |
3305 CPU_BASED_INVLPG_EXITING |
3306 CPU_BASED_RDPMC_EXITING;
3308 opt = CPU_BASED_TPR_SHADOW |
3309 CPU_BASED_USE_MSR_BITMAPS |
3310 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3311 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3312 &_cpu_based_exec_control) < 0)
3314 #ifdef CONFIG_X86_64
3315 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3316 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3317 ~CPU_BASED_CR8_STORE_EXITING;
3319 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3321 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3322 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3323 SECONDARY_EXEC_WBINVD_EXITING |
3324 SECONDARY_EXEC_ENABLE_VPID |
3325 SECONDARY_EXEC_ENABLE_EPT |
3326 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3327 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3328 SECONDARY_EXEC_RDTSCP |
3329 SECONDARY_EXEC_ENABLE_INVPCID |
3330 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3331 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3332 SECONDARY_EXEC_SHADOW_VMCS |
3333 SECONDARY_EXEC_XSAVES |
3334 SECONDARY_EXEC_ENABLE_PML |
3335 SECONDARY_EXEC_PCOMMIT |
3336 SECONDARY_EXEC_TSC_SCALING;
3337 if (adjust_vmx_controls(min2, opt2,
3338 MSR_IA32_VMX_PROCBASED_CTLS2,
3339 &_cpu_based_2nd_exec_control) < 0)
3342 #ifndef CONFIG_X86_64
3343 if (!(_cpu_based_2nd_exec_control &
3344 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3345 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3348 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3349 _cpu_based_2nd_exec_control &= ~(
3350 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3351 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3352 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3354 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3355 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3357 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3358 CPU_BASED_CR3_STORE_EXITING |
3359 CPU_BASED_INVLPG_EXITING);
3360 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3361 vmx_capability.ept, vmx_capability.vpid);
3364 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3365 #ifdef CONFIG_X86_64
3366 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3368 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3369 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3370 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3371 &_vmexit_control) < 0)
3374 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3375 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3376 PIN_BASED_VMX_PREEMPTION_TIMER;
3377 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3378 &_pin_based_exec_control) < 0)
3381 if (!(_cpu_based_2nd_exec_control &
3382 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3383 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3384 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3386 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3387 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3388 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3389 &_vmentry_control) < 0)
3392 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3394 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3395 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3398 #ifdef CONFIG_X86_64
3399 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3400 if (vmx_msr_high & (1u<<16))
3404 /* Require Write-Back (WB) memory type for VMCS accesses. */
3405 if (((vmx_msr_high >> 18) & 15) != 6)
3408 vmcs_conf->size = vmx_msr_high & 0x1fff;
3409 vmcs_conf->order = get_order(vmcs_config.size);
3410 vmcs_conf->revision_id = vmx_msr_low;
3412 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3413 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3414 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3415 vmcs_conf->vmexit_ctrl = _vmexit_control;
3416 vmcs_conf->vmentry_ctrl = _vmentry_control;
3418 cpu_has_load_ia32_efer =
3419 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3420 VM_ENTRY_LOAD_IA32_EFER)
3421 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3422 VM_EXIT_LOAD_IA32_EFER);
3424 cpu_has_load_perf_global_ctrl =
3425 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3426 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3427 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3428 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3431 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3432 * but due to errata below it can't be used. Workaround is to use
3433 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3435 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3440 * BC86,AAY89,BD102 (model 44)
3444 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3445 switch (boot_cpu_data.x86_model) {
3451 cpu_has_load_perf_global_ctrl = false;
3452 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3453 "does not work properly. Using workaround\n");
3460 if (boot_cpu_has(X86_FEATURE_XSAVES))
3461 rdmsrl(MSR_IA32_XSS, host_xss);
3466 static struct vmcs *alloc_vmcs_cpu(int cpu)
3468 int node = cpu_to_node(cpu);
3472 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3475 vmcs = page_address(pages);
3476 memset(vmcs, 0, vmcs_config.size);
3477 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3481 static struct vmcs *alloc_vmcs(void)
3483 return alloc_vmcs_cpu(raw_smp_processor_id());
3486 static void free_vmcs(struct vmcs *vmcs)
3488 free_pages((unsigned long)vmcs, vmcs_config.order);
3492 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3494 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3496 if (!loaded_vmcs->vmcs)
3498 loaded_vmcs_clear(loaded_vmcs);
3499 free_vmcs(loaded_vmcs->vmcs);
3500 loaded_vmcs->vmcs = NULL;
3503 static void free_kvm_area(void)
3507 for_each_possible_cpu(cpu) {
3508 free_vmcs(per_cpu(vmxarea, cpu));
3509 per_cpu(vmxarea, cpu) = NULL;
3513 static void init_vmcs_shadow_fields(void)
3517 /* No checks for read only fields yet */
3519 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3520 switch (shadow_read_write_fields[i]) {
3522 if (!kvm_mpx_supported())
3530 shadow_read_write_fields[j] =
3531 shadow_read_write_fields[i];
3534 max_shadow_read_write_fields = j;
3536 /* shadowed fields guest access without vmexit */
3537 for (i = 0; i < max_shadow_read_write_fields; i++) {
3538 clear_bit(shadow_read_write_fields[i],
3539 vmx_vmwrite_bitmap);
3540 clear_bit(shadow_read_write_fields[i],
3543 for (i = 0; i < max_shadow_read_only_fields; i++)
3544 clear_bit(shadow_read_only_fields[i],
3548 static __init int alloc_kvm_area(void)
3552 for_each_possible_cpu(cpu) {
3555 vmcs = alloc_vmcs_cpu(cpu);
3561 per_cpu(vmxarea, cpu) = vmcs;
3566 static bool emulation_required(struct kvm_vcpu *vcpu)
3568 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3571 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3572 struct kvm_segment *save)
3574 if (!emulate_invalid_guest_state) {
3576 * CS and SS RPL should be equal during guest entry according
3577 * to VMX spec, but in reality it is not always so. Since vcpu
3578 * is in the middle of the transition from real mode to
3579 * protected mode it is safe to assume that RPL 0 is a good
3582 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3583 save->selector &= ~SEGMENT_RPL_MASK;
3584 save->dpl = save->selector & SEGMENT_RPL_MASK;
3587 vmx_set_segment(vcpu, save, seg);
3590 static void enter_pmode(struct kvm_vcpu *vcpu)
3592 unsigned long flags;
3593 struct vcpu_vmx *vmx = to_vmx(vcpu);
3596 * Update real mode segment cache. It may be not up-to-date if sement
3597 * register was written while vcpu was in a guest mode.
3599 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3600 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3601 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3602 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3603 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3604 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3606 vmx->rmode.vm86_active = 0;
3608 vmx_segment_cache_clear(vmx);
3610 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3612 flags = vmcs_readl(GUEST_RFLAGS);
3613 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3614 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3615 vmcs_writel(GUEST_RFLAGS, flags);
3617 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3618 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3620 update_exception_bitmap(vcpu);
3622 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3623 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3624 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3625 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3626 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3627 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3630 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3632 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3633 struct kvm_segment var = *save;
3636 if (seg == VCPU_SREG_CS)
3639 if (!emulate_invalid_guest_state) {
3640 var.selector = var.base >> 4;
3641 var.base = var.base & 0xffff0;
3651 if (save->base & 0xf)
3652 printk_once(KERN_WARNING "kvm: segment base is not "
3653 "paragraph aligned when entering "
3654 "protected mode (seg=%d)", seg);
3657 vmcs_write16(sf->selector, var.selector);
3658 vmcs_write32(sf->base, var.base);
3659 vmcs_write32(sf->limit, var.limit);
3660 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3663 static void enter_rmode(struct kvm_vcpu *vcpu)
3665 unsigned long flags;
3666 struct vcpu_vmx *vmx = to_vmx(vcpu);
3668 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3669 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3670 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3671 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3672 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3673 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3674 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3676 vmx->rmode.vm86_active = 1;
3679 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3680 * vcpu. Warn the user that an update is overdue.
3682 if (!vcpu->kvm->arch.tss_addr)
3683 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3684 "called before entering vcpu\n");
3686 vmx_segment_cache_clear(vmx);
3688 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3689 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3690 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3692 flags = vmcs_readl(GUEST_RFLAGS);
3693 vmx->rmode.save_rflags = flags;
3695 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3697 vmcs_writel(GUEST_RFLAGS, flags);
3698 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3699 update_exception_bitmap(vcpu);
3701 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3702 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3703 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3704 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3705 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3706 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3708 kvm_mmu_reset_context(vcpu);
3711 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3713 struct vcpu_vmx *vmx = to_vmx(vcpu);
3714 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3720 * Force kernel_gs_base reloading before EFER changes, as control
3721 * of this msr depends on is_long_mode().
3723 vmx_load_host_state(to_vmx(vcpu));
3724 vcpu->arch.efer = efer;
3725 if (efer & EFER_LMA) {
3726 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3729 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3731 msr->data = efer & ~EFER_LME;
3736 #ifdef CONFIG_X86_64
3738 static void enter_lmode(struct kvm_vcpu *vcpu)
3742 vmx_segment_cache_clear(to_vmx(vcpu));
3744 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3745 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3746 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3748 vmcs_write32(GUEST_TR_AR_BYTES,
3749 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3750 | VMX_AR_TYPE_BUSY_64_TSS);
3752 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3755 static void exit_lmode(struct kvm_vcpu *vcpu)
3757 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3758 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3763 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3765 vpid_sync_context(vpid);
3767 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3769 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3773 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3775 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3778 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3780 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3782 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3783 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3786 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3788 if (enable_ept && is_paging(vcpu))
3789 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3790 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3793 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3795 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3797 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3798 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3801 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3803 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3805 if (!test_bit(VCPU_EXREG_PDPTR,
3806 (unsigned long *)&vcpu->arch.regs_dirty))
3809 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3810 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3811 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3812 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3813 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3817 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3819 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3821 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3822 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3823 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3824 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3825 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3828 __set_bit(VCPU_EXREG_PDPTR,
3829 (unsigned long *)&vcpu->arch.regs_avail);
3830 __set_bit(VCPU_EXREG_PDPTR,
3831 (unsigned long *)&vcpu->arch.regs_dirty);
3834 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3836 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3838 struct kvm_vcpu *vcpu)
3840 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3841 vmx_decache_cr3(vcpu);
3842 if (!(cr0 & X86_CR0_PG)) {
3843 /* From paging/starting to nonpaging */
3844 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3845 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3846 (CPU_BASED_CR3_LOAD_EXITING |
3847 CPU_BASED_CR3_STORE_EXITING));
3848 vcpu->arch.cr0 = cr0;
3849 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3850 } else if (!is_paging(vcpu)) {
3851 /* From nonpaging to paging */
3852 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3853 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3854 ~(CPU_BASED_CR3_LOAD_EXITING |
3855 CPU_BASED_CR3_STORE_EXITING));
3856 vcpu->arch.cr0 = cr0;
3857 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3860 if (!(cr0 & X86_CR0_WP))
3861 *hw_cr0 &= ~X86_CR0_WP;
3864 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3866 struct vcpu_vmx *vmx = to_vmx(vcpu);
3867 unsigned long hw_cr0;
3869 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3870 if (enable_unrestricted_guest)
3871 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3873 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3875 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3878 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3882 #ifdef CONFIG_X86_64
3883 if (vcpu->arch.efer & EFER_LME) {
3884 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3886 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3892 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3894 if (!vcpu->fpu_active)
3895 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3897 vmcs_writel(CR0_READ_SHADOW, cr0);
3898 vmcs_writel(GUEST_CR0, hw_cr0);
3899 vcpu->arch.cr0 = cr0;
3901 /* depends on vcpu->arch.cr0 to be set to a new value */
3902 vmx->emulation_required = emulation_required(vcpu);
3905 static u64 construct_eptp(unsigned long root_hpa)
3909 /* TODO write the value reading from MSR */
3910 eptp = VMX_EPT_DEFAULT_MT |
3911 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3912 if (enable_ept_ad_bits)
3913 eptp |= VMX_EPT_AD_ENABLE_BIT;
3914 eptp |= (root_hpa & PAGE_MASK);
3919 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3921 unsigned long guest_cr3;
3926 eptp = construct_eptp(cr3);
3927 vmcs_write64(EPT_POINTER, eptp);
3928 if (is_paging(vcpu) || is_guest_mode(vcpu))
3929 guest_cr3 = kvm_read_cr3(vcpu);
3931 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3932 ept_load_pdptrs(vcpu);
3935 vmx_flush_tlb(vcpu);
3936 vmcs_writel(GUEST_CR3, guest_cr3);
3939 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3942 * Pass through host's Machine Check Enable value to hw_cr4, which
3943 * is in force while we are in guest mode. Do not let guests control
3944 * this bit, even if host CR4.MCE == 0.
3946 unsigned long hw_cr4 =
3947 (cr4_read_shadow() & X86_CR4_MCE) |
3948 (cr4 & ~X86_CR4_MCE) |
3949 (to_vmx(vcpu)->rmode.vm86_active ?
3950 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3952 if (cr4 & X86_CR4_VMXE) {
3954 * To use VMXON (and later other VMX instructions), a guest
3955 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3956 * So basically the check on whether to allow nested VMX
3959 if (!nested_vmx_allowed(vcpu))
3962 if (to_vmx(vcpu)->nested.vmxon &&
3963 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3966 vcpu->arch.cr4 = cr4;
3968 if (!is_paging(vcpu)) {
3969 hw_cr4 &= ~X86_CR4_PAE;
3970 hw_cr4 |= X86_CR4_PSE;
3971 } else if (!(cr4 & X86_CR4_PAE)) {
3972 hw_cr4 &= ~X86_CR4_PAE;
3976 if (!enable_unrestricted_guest && !is_paging(vcpu))
3978 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3979 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3980 * to be manually disabled when guest switches to non-paging
3983 * If !enable_unrestricted_guest, the CPU is always running
3984 * with CR0.PG=1 and CR4 needs to be modified.
3985 * If enable_unrestricted_guest, the CPU automatically
3986 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3988 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3990 vmcs_writel(CR4_READ_SHADOW, cr4);
3991 vmcs_writel(GUEST_CR4, hw_cr4);
3995 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3996 struct kvm_segment *var, int seg)
3998 struct vcpu_vmx *vmx = to_vmx(vcpu);
4001 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4002 *var = vmx->rmode.segs[seg];
4003 if (seg == VCPU_SREG_TR
4004 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4006 var->base = vmx_read_guest_seg_base(vmx, seg);
4007 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4010 var->base = vmx_read_guest_seg_base(vmx, seg);
4011 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4012 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4013 ar = vmx_read_guest_seg_ar(vmx, seg);
4014 var->unusable = (ar >> 16) & 1;
4015 var->type = ar & 15;
4016 var->s = (ar >> 4) & 1;
4017 var->dpl = (ar >> 5) & 3;
4019 * Some userspaces do not preserve unusable property. Since usable
4020 * segment has to be present according to VMX spec we can use present
4021 * property to amend userspace bug by making unusable segment always
4022 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4023 * segment as unusable.
4025 var->present = !var->unusable;
4026 var->avl = (ar >> 12) & 1;
4027 var->l = (ar >> 13) & 1;
4028 var->db = (ar >> 14) & 1;
4029 var->g = (ar >> 15) & 1;
4032 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4034 struct kvm_segment s;
4036 if (to_vmx(vcpu)->rmode.vm86_active) {
4037 vmx_get_segment(vcpu, &s, seg);
4040 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4043 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4045 struct vcpu_vmx *vmx = to_vmx(vcpu);
4047 if (unlikely(vmx->rmode.vm86_active))
4050 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4051 return VMX_AR_DPL(ar);
4055 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4059 if (var->unusable || !var->present)
4062 ar = var->type & 15;
4063 ar |= (var->s & 1) << 4;
4064 ar |= (var->dpl & 3) << 5;
4065 ar |= (var->present & 1) << 7;
4066 ar |= (var->avl & 1) << 12;
4067 ar |= (var->l & 1) << 13;
4068 ar |= (var->db & 1) << 14;
4069 ar |= (var->g & 1) << 15;
4075 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4076 struct kvm_segment *var, int seg)
4078 struct vcpu_vmx *vmx = to_vmx(vcpu);
4079 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4081 vmx_segment_cache_clear(vmx);
4083 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4084 vmx->rmode.segs[seg] = *var;
4085 if (seg == VCPU_SREG_TR)
4086 vmcs_write16(sf->selector, var->selector);
4088 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4092 vmcs_writel(sf->base, var->base);
4093 vmcs_write32(sf->limit, var->limit);
4094 vmcs_write16(sf->selector, var->selector);
4097 * Fix the "Accessed" bit in AR field of segment registers for older
4099 * IA32 arch specifies that at the time of processor reset the
4100 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4101 * is setting it to 0 in the userland code. This causes invalid guest
4102 * state vmexit when "unrestricted guest" mode is turned on.
4103 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4104 * tree. Newer qemu binaries with that qemu fix would not need this
4107 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4108 var->type |= 0x1; /* Accessed */
4110 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4113 vmx->emulation_required = emulation_required(vcpu);
4116 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4118 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4120 *db = (ar >> 14) & 1;
4121 *l = (ar >> 13) & 1;
4124 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4126 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4127 dt->address = vmcs_readl(GUEST_IDTR_BASE);
4130 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4132 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4133 vmcs_writel(GUEST_IDTR_BASE, dt->address);
4136 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4138 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4139 dt->address = vmcs_readl(GUEST_GDTR_BASE);
4142 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4144 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4145 vmcs_writel(GUEST_GDTR_BASE, dt->address);
4148 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4150 struct kvm_segment var;
4153 vmx_get_segment(vcpu, &var, seg);
4155 if (seg == VCPU_SREG_CS)
4157 ar = vmx_segment_access_rights(&var);
4159 if (var.base != (var.selector << 4))
4161 if (var.limit != 0xffff)
4169 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4171 struct kvm_segment cs;
4172 unsigned int cs_rpl;
4174 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4175 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4179 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4183 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4184 if (cs.dpl > cs_rpl)
4187 if (cs.dpl != cs_rpl)
4193 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4197 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4199 struct kvm_segment ss;
4200 unsigned int ss_rpl;
4202 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4203 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4207 if (ss.type != 3 && ss.type != 7)
4211 if (ss.dpl != ss_rpl) /* DPL != RPL */
4219 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4221 struct kvm_segment var;
4224 vmx_get_segment(vcpu, &var, seg);
4225 rpl = var.selector & SEGMENT_RPL_MASK;
4233 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4234 if (var.dpl < rpl) /* DPL < RPL */
4238 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4244 static bool tr_valid(struct kvm_vcpu *vcpu)
4246 struct kvm_segment tr;
4248 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4252 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4254 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4262 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4264 struct kvm_segment ldtr;
4266 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4270 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4280 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4282 struct kvm_segment cs, ss;
4284 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4285 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4287 return ((cs.selector & SEGMENT_RPL_MASK) ==
4288 (ss.selector & SEGMENT_RPL_MASK));
4292 * Check if guest state is valid. Returns true if valid, false if
4294 * We assume that registers are always usable
4296 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4298 if (enable_unrestricted_guest)
4301 /* real mode guest state checks */
4302 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4303 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4305 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4307 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4309 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4311 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4313 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4316 /* protected mode guest state checks */
4317 if (!cs_ss_rpl_check(vcpu))
4319 if (!code_segment_valid(vcpu))
4321 if (!stack_segment_valid(vcpu))
4323 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4325 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4327 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4329 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4331 if (!tr_valid(vcpu))
4333 if (!ldtr_valid(vcpu))
4337 * - Add checks on RIP
4338 * - Add checks on RFLAGS
4344 static int init_rmode_tss(struct kvm *kvm)
4350 idx = srcu_read_lock(&kvm->srcu);
4351 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4352 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4355 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4356 r = kvm_write_guest_page(kvm, fn++, &data,
4357 TSS_IOPB_BASE_OFFSET, sizeof(u16));
4360 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4363 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4367 r = kvm_write_guest_page(kvm, fn, &data,
4368 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4371 srcu_read_unlock(&kvm->srcu, idx);
4375 static int init_rmode_identity_map(struct kvm *kvm)
4378 kvm_pfn_t identity_map_pfn;
4384 /* Protect kvm->arch.ept_identity_pagetable_done. */
4385 mutex_lock(&kvm->slots_lock);
4387 if (likely(kvm->arch.ept_identity_pagetable_done))
4390 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4392 r = alloc_identity_pagetable(kvm);
4396 idx = srcu_read_lock(&kvm->srcu);
4397 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4400 /* Set up identity-mapping pagetable for EPT in real mode */
4401 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4402 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4403 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4404 r = kvm_write_guest_page(kvm, identity_map_pfn,
4405 &tmp, i * sizeof(tmp), sizeof(tmp));
4409 kvm->arch.ept_identity_pagetable_done = true;
4412 srcu_read_unlock(&kvm->srcu, idx);
4415 mutex_unlock(&kvm->slots_lock);
4419 static void seg_setup(int seg)
4421 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4424 vmcs_write16(sf->selector, 0);
4425 vmcs_writel(sf->base, 0);
4426 vmcs_write32(sf->limit, 0xffff);
4428 if (seg == VCPU_SREG_CS)
4429 ar |= 0x08; /* code segment */
4431 vmcs_write32(sf->ar_bytes, ar);
4434 static int alloc_apic_access_page(struct kvm *kvm)
4439 mutex_lock(&kvm->slots_lock);
4440 if (kvm->arch.apic_access_page_done)
4442 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4443 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4447 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4448 if (is_error_page(page)) {
4454 * Do not pin the page in memory, so that memory hot-unplug
4455 * is able to migrate it.
4458 kvm->arch.apic_access_page_done = true;
4460 mutex_unlock(&kvm->slots_lock);
4464 static int alloc_identity_pagetable(struct kvm *kvm)
4466 /* Called with kvm->slots_lock held. */
4470 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4472 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4473 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4478 static int allocate_vpid(void)
4484 spin_lock(&vmx_vpid_lock);
4485 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4486 if (vpid < VMX_NR_VPIDS)
4487 __set_bit(vpid, vmx_vpid_bitmap);
4490 spin_unlock(&vmx_vpid_lock);
4494 static void free_vpid(int vpid)
4496 if (!enable_vpid || vpid == 0)
4498 spin_lock(&vmx_vpid_lock);
4499 __clear_bit(vpid, vmx_vpid_bitmap);
4500 spin_unlock(&vmx_vpid_lock);
4503 #define MSR_TYPE_R 1
4504 #define MSR_TYPE_W 2
4505 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4508 int f = sizeof(unsigned long);
4510 if (!cpu_has_vmx_msr_bitmap())
4514 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4515 * have the write-low and read-high bitmap offsets the wrong way round.
4516 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4518 if (msr <= 0x1fff) {
4519 if (type & MSR_TYPE_R)
4521 __clear_bit(msr, msr_bitmap + 0x000 / f);
4523 if (type & MSR_TYPE_W)
4525 __clear_bit(msr, msr_bitmap + 0x800 / f);
4527 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4529 if (type & MSR_TYPE_R)
4531 __clear_bit(msr, msr_bitmap + 0x400 / f);
4533 if (type & MSR_TYPE_W)
4535 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4540 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4543 int f = sizeof(unsigned long);
4545 if (!cpu_has_vmx_msr_bitmap())
4549 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4550 * have the write-low and read-high bitmap offsets the wrong way round.
4551 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4553 if (msr <= 0x1fff) {
4554 if (type & MSR_TYPE_R)
4556 __set_bit(msr, msr_bitmap + 0x000 / f);
4558 if (type & MSR_TYPE_W)
4560 __set_bit(msr, msr_bitmap + 0x800 / f);
4562 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4564 if (type & MSR_TYPE_R)
4566 __set_bit(msr, msr_bitmap + 0x400 / f);
4568 if (type & MSR_TYPE_W)
4570 __set_bit(msr, msr_bitmap + 0xc00 / f);
4576 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4577 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4579 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4580 unsigned long *msr_bitmap_nested,
4583 int f = sizeof(unsigned long);
4585 if (!cpu_has_vmx_msr_bitmap()) {
4591 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4592 * have the write-low and read-high bitmap offsets the wrong way round.
4593 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4595 if (msr <= 0x1fff) {
4596 if (type & MSR_TYPE_R &&
4597 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4599 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4601 if (type & MSR_TYPE_W &&
4602 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4604 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4606 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4608 if (type & MSR_TYPE_R &&
4609 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4611 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4613 if (type & MSR_TYPE_W &&
4614 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4616 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4621 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4624 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4625 msr, MSR_TYPE_R | MSR_TYPE_W);
4626 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4627 msr, MSR_TYPE_R | MSR_TYPE_W);
4630 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4632 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4634 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4638 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4640 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4642 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4646 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4648 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4650 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4654 static bool vmx_get_enable_apicv(void)
4656 return enable_apicv;
4659 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4661 struct vcpu_vmx *vmx = to_vmx(vcpu);
4666 if (vmx->nested.pi_desc &&
4667 vmx->nested.pi_pending) {
4668 vmx->nested.pi_pending = false;
4669 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4672 max_irr = find_last_bit(
4673 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4678 vapic_page = kmap(vmx->nested.virtual_apic_page);
4683 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4684 kunmap(vmx->nested.virtual_apic_page);
4686 status = vmcs_read16(GUEST_INTR_STATUS);
4687 if ((u8)max_irr > ((u8)status & 0xff)) {
4689 status |= (u8)max_irr;
4690 vmcs_write16(GUEST_INTR_STATUS, status);
4696 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4699 if (vcpu->mode == IN_GUEST_MODE) {
4700 struct vcpu_vmx *vmx = to_vmx(vcpu);
4703 * Currently, we don't support urgent interrupt,
4704 * all interrupts are recognized as non-urgent
4705 * interrupt, so we cannot post interrupts when
4708 * If the vcpu is in guest mode, it means it is
4709 * running instead of being scheduled out and
4710 * waiting in the run queue, and that's the only
4711 * case when 'SN' is set currently, warning if
4714 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4716 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4717 POSTED_INTR_VECTOR);
4724 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4727 struct vcpu_vmx *vmx = to_vmx(vcpu);
4729 if (is_guest_mode(vcpu) &&
4730 vector == vmx->nested.posted_intr_nv) {
4731 /* the PIR and ON have been set by L1. */
4732 kvm_vcpu_trigger_posted_interrupt(vcpu);
4734 * If a posted intr is not recognized by hardware,
4735 * we will accomplish it in the next vmentry.
4737 vmx->nested.pi_pending = true;
4738 kvm_make_request(KVM_REQ_EVENT, vcpu);
4744 * Send interrupt to vcpu via posted interrupt way.
4745 * 1. If target vcpu is running(non-root mode), send posted interrupt
4746 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4747 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4748 * interrupt from PIR in next vmentry.
4750 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4752 struct vcpu_vmx *vmx = to_vmx(vcpu);
4755 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4759 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4762 r = pi_test_and_set_on(&vmx->pi_desc);
4763 kvm_make_request(KVM_REQ_EVENT, vcpu);
4764 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4765 kvm_vcpu_kick(vcpu);
4768 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4770 struct vcpu_vmx *vmx = to_vmx(vcpu);
4772 if (!pi_test_and_clear_on(&vmx->pi_desc))
4775 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4779 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4780 * will not change in the lifetime of the guest.
4781 * Note that host-state that does change is set elsewhere. E.g., host-state
4782 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4784 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4791 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
4792 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4794 /* Save the most likely value for this task's CR4 in the VMCS. */
4795 cr4 = cr4_read_shadow();
4796 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4797 vmx->host_state.vmcs_host_cr4 = cr4;
4799 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4800 #ifdef CONFIG_X86_64
4802 * Load null selectors, so we can avoid reloading them in
4803 * __vmx_load_host_state(), in case userspace uses the null selectors
4804 * too (the expected case).
4806 vmcs_write16(HOST_DS_SELECTOR, 0);
4807 vmcs_write16(HOST_ES_SELECTOR, 0);
4809 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4810 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4812 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4813 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4815 native_store_idt(&dt);
4816 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
4817 vmx->host_idt_base = dt.address;
4819 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4821 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4822 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4823 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4824 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4826 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4827 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4828 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4832 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4834 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4836 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4837 if (is_guest_mode(&vmx->vcpu))
4838 vmx->vcpu.arch.cr4_guest_owned_bits &=
4839 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4840 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4843 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4845 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4847 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4848 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4849 /* Enable the preemption timer dynamically */
4850 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4851 return pin_based_exec_ctrl;
4854 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4856 struct vcpu_vmx *vmx = to_vmx(vcpu);
4858 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4859 if (cpu_has_secondary_exec_ctrls()) {
4860 if (kvm_vcpu_apicv_active(vcpu))
4861 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
4862 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4863 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4865 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
4866 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4867 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4870 if (cpu_has_vmx_msr_bitmap())
4871 vmx_set_msr_bitmap(vcpu);
4874 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4876 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4878 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4879 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4881 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4882 exec_control &= ~CPU_BASED_TPR_SHADOW;
4883 #ifdef CONFIG_X86_64
4884 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4885 CPU_BASED_CR8_LOAD_EXITING;
4889 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4890 CPU_BASED_CR3_LOAD_EXITING |
4891 CPU_BASED_INVLPG_EXITING;
4892 return exec_control;
4895 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4897 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4898 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4899 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4901 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4903 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4904 enable_unrestricted_guest = 0;
4905 /* Enable INVPCID for non-ept guests may cause performance regression. */
4906 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4908 if (!enable_unrestricted_guest)
4909 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4911 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4912 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4913 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4914 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4915 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4916 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4918 We can NOT enable shadow_vmcs here because we don't have yet
4921 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4924 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4926 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4927 exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4929 return exec_control;
4932 static void ept_set_mmio_spte_mask(void)
4935 * EPT Misconfigurations can be generated if the value of bits 2:0
4936 * of an EPT paging-structure entry is 110b (write/execute).
4937 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4940 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4943 #define VMX_XSS_EXIT_BITMAP 0
4945 * Sets up the vmcs for emulated real mode.
4947 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4949 #ifdef CONFIG_X86_64
4955 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4956 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4958 if (enable_shadow_vmcs) {
4959 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4960 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4962 if (cpu_has_vmx_msr_bitmap())
4963 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4965 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4968 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4969 vmx->hv_deadline_tsc = -1;
4971 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4973 if (cpu_has_secondary_exec_ctrls())
4974 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4975 vmx_secondary_exec_control(vmx));
4977 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4978 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4979 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4980 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4981 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4983 vmcs_write16(GUEST_INTR_STATUS, 0);
4985 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4986 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4990 vmcs_write32(PLE_GAP, ple_gap);
4991 vmx->ple_window = ple_window;
4992 vmx->ple_window_dirty = true;
4995 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4996 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4997 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4999 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5000 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
5001 vmx_set_constant_host_state(vmx);
5002 #ifdef CONFIG_X86_64
5003 rdmsrl(MSR_FS_BASE, a);
5004 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5005 rdmsrl(MSR_GS_BASE, a);
5006 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5008 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5009 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5012 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5013 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5014 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5015 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5016 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5018 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5019 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5021 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5022 u32 index = vmx_msr_index[i];
5023 u32 data_low, data_high;
5026 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5028 if (wrmsr_safe(index, data_low, data_high) < 0)
5030 vmx->guest_msrs[j].index = i;
5031 vmx->guest_msrs[j].data = 0;
5032 vmx->guest_msrs[j].mask = -1ull;
5037 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5039 /* 22.2.1, 20.8.1 */
5040 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5042 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
5043 set_cr4_guest_host_mask(vmx);
5045 if (vmx_xsaves_supported())
5046 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5051 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5053 struct vcpu_vmx *vmx = to_vmx(vcpu);
5054 struct msr_data apic_base_msr;
5057 vmx->rmode.vm86_active = 0;
5059 vmx->soft_vnmi_blocked = 0;
5061 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5062 kvm_set_cr8(vcpu, 0);
5065 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5066 MSR_IA32_APICBASE_ENABLE;
5067 if (kvm_vcpu_is_reset_bsp(vcpu))
5068 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5069 apic_base_msr.host_initiated = true;
5070 kvm_set_apic_base(vcpu, &apic_base_msr);
5073 vmx_segment_cache_clear(vmx);
5075 seg_setup(VCPU_SREG_CS);
5076 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5077 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5079 seg_setup(VCPU_SREG_DS);
5080 seg_setup(VCPU_SREG_ES);
5081 seg_setup(VCPU_SREG_FS);
5082 seg_setup(VCPU_SREG_GS);
5083 seg_setup(VCPU_SREG_SS);
5085 vmcs_write16(GUEST_TR_SELECTOR, 0);
5086 vmcs_writel(GUEST_TR_BASE, 0);
5087 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5088 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5090 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5091 vmcs_writel(GUEST_LDTR_BASE, 0);
5092 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5093 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5096 vmcs_write32(GUEST_SYSENTER_CS, 0);
5097 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5098 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5099 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5102 vmcs_writel(GUEST_RFLAGS, 0x02);
5103 kvm_rip_write(vcpu, 0xfff0);
5105 vmcs_writel(GUEST_GDTR_BASE, 0);
5106 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5108 vmcs_writel(GUEST_IDTR_BASE, 0);
5109 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5111 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5112 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5113 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5117 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5119 if (cpu_has_vmx_tpr_shadow() && !init_event) {
5120 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5121 if (cpu_need_tpr_shadow(vcpu))
5122 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5123 __pa(vcpu->arch.apic->regs));
5124 vmcs_write32(TPR_THRESHOLD, 0);
5127 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5129 if (kvm_vcpu_apicv_active(vcpu))
5130 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5133 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5135 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5136 vmx->vcpu.arch.cr0 = cr0;
5137 vmx_set_cr0(vcpu, cr0); /* enter rmode */
5138 vmx_set_cr4(vcpu, 0);
5139 vmx_set_efer(vcpu, 0);
5140 vmx_fpu_activate(vcpu);
5141 update_exception_bitmap(vcpu);
5143 vpid_sync_context(vmx->vpid);
5147 * In nested virtualization, check if L1 asked to exit on external interrupts.
5148 * For most existing hypervisors, this will always return true.
5150 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5152 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5153 PIN_BASED_EXT_INTR_MASK;
5157 * In nested virtualization, check if L1 has set
5158 * VM_EXIT_ACK_INTR_ON_EXIT
5160 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5162 return get_vmcs12(vcpu)->vm_exit_controls &
5163 VM_EXIT_ACK_INTR_ON_EXIT;
5166 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5168 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5169 PIN_BASED_NMI_EXITING;
5172 static void enable_irq_window(struct kvm_vcpu *vcpu)
5174 u32 cpu_based_vm_exec_control;
5176 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5177 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5178 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5181 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5183 u32 cpu_based_vm_exec_control;
5185 if (!cpu_has_virtual_nmis() ||
5186 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5187 enable_irq_window(vcpu);
5191 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5192 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5193 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5196 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5198 struct vcpu_vmx *vmx = to_vmx(vcpu);
5200 int irq = vcpu->arch.interrupt.nr;
5202 trace_kvm_inj_virq(irq);
5204 ++vcpu->stat.irq_injections;
5205 if (vmx->rmode.vm86_active) {
5207 if (vcpu->arch.interrupt.soft)
5208 inc_eip = vcpu->arch.event_exit_inst_len;
5209 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5210 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5213 intr = irq | INTR_INFO_VALID_MASK;
5214 if (vcpu->arch.interrupt.soft) {
5215 intr |= INTR_TYPE_SOFT_INTR;
5216 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5217 vmx->vcpu.arch.event_exit_inst_len);
5219 intr |= INTR_TYPE_EXT_INTR;
5220 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5223 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5225 struct vcpu_vmx *vmx = to_vmx(vcpu);
5227 if (is_guest_mode(vcpu))
5230 if (!cpu_has_virtual_nmis()) {
5232 * Tracking the NMI-blocked state in software is built upon
5233 * finding the next open IRQ window. This, in turn, depends on
5234 * well-behaving guests: They have to keep IRQs disabled at
5235 * least as long as the NMI handler runs. Otherwise we may
5236 * cause NMI nesting, maybe breaking the guest. But as this is
5237 * highly unlikely, we can live with the residual risk.
5239 vmx->soft_vnmi_blocked = 1;
5240 vmx->vnmi_blocked_time = 0;
5243 ++vcpu->stat.nmi_injections;
5244 vmx->nmi_known_unmasked = false;
5245 if (vmx->rmode.vm86_active) {
5246 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5247 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5250 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5251 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5254 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5256 if (!cpu_has_virtual_nmis())
5257 return to_vmx(vcpu)->soft_vnmi_blocked;
5258 if (to_vmx(vcpu)->nmi_known_unmasked)
5260 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5263 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5265 struct vcpu_vmx *vmx = to_vmx(vcpu);
5267 if (!cpu_has_virtual_nmis()) {
5268 if (vmx->soft_vnmi_blocked != masked) {
5269 vmx->soft_vnmi_blocked = masked;
5270 vmx->vnmi_blocked_time = 0;
5273 vmx->nmi_known_unmasked = !masked;
5275 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5276 GUEST_INTR_STATE_NMI);
5278 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5279 GUEST_INTR_STATE_NMI);
5283 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5285 if (to_vmx(vcpu)->nested.nested_run_pending)
5288 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5291 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5292 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5293 | GUEST_INTR_STATE_NMI));
5296 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5298 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5299 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5300 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5301 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5304 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5308 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5312 kvm->arch.tss_addr = addr;
5313 return init_rmode_tss(kvm);
5316 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5321 * Update instruction length as we may reinject the exception
5322 * from user space while in guest debugging mode.
5324 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5325 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5326 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5330 if (vcpu->guest_debug &
5331 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5348 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5349 int vec, u32 err_code)
5352 * Instruction with address size override prefix opcode 0x67
5353 * Cause the #SS fault with 0 error code in VM86 mode.
5355 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5356 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5357 if (vcpu->arch.halt_request) {
5358 vcpu->arch.halt_request = 0;
5359 return kvm_vcpu_halt(vcpu);
5367 * Forward all other exceptions that are valid in real mode.
5368 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5369 * the required debugging infrastructure rework.
5371 kvm_queue_exception(vcpu, vec);
5376 * Trigger machine check on the host. We assume all the MSRs are already set up
5377 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5378 * We pass a fake environment to the machine check handler because we want
5379 * the guest to be always treated like user space, no matter what context
5380 * it used internally.
5382 static void kvm_machine_check(void)
5384 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5385 struct pt_regs regs = {
5386 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5387 .flags = X86_EFLAGS_IF,
5390 do_machine_check(®s, 0);
5394 static int handle_machine_check(struct kvm_vcpu *vcpu)
5396 /* already handled by vcpu_run */
5400 static int handle_exception(struct kvm_vcpu *vcpu)
5402 struct vcpu_vmx *vmx = to_vmx(vcpu);
5403 struct kvm_run *kvm_run = vcpu->run;
5404 u32 intr_info, ex_no, error_code;
5405 unsigned long cr2, rip, dr6;
5407 enum emulation_result er;
5409 vect_info = vmx->idt_vectoring_info;
5410 intr_info = vmx->exit_intr_info;
5412 if (is_machine_check(intr_info))
5413 return handle_machine_check(vcpu);
5415 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5416 return 1; /* already handled by vmx_vcpu_run() */
5418 if (is_no_device(intr_info)) {
5419 vmx_fpu_activate(vcpu);
5423 if (is_invalid_opcode(intr_info)) {
5424 if (is_guest_mode(vcpu)) {
5425 kvm_queue_exception(vcpu, UD_VECTOR);
5428 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5429 if (er != EMULATE_DONE)
5430 kvm_queue_exception(vcpu, UD_VECTOR);
5435 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5436 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5439 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5440 * MMIO, it is better to report an internal error.
5441 * See the comments in vmx_handle_exit.
5443 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5444 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5445 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5446 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5447 vcpu->run->internal.ndata = 3;
5448 vcpu->run->internal.data[0] = vect_info;
5449 vcpu->run->internal.data[1] = intr_info;
5450 vcpu->run->internal.data[2] = error_code;
5454 if (is_page_fault(intr_info)) {
5455 /* EPT won't cause page fault directly */
5457 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5458 trace_kvm_page_fault(cr2, error_code);
5460 if (kvm_event_needs_reinjection(vcpu))
5461 kvm_mmu_unprotect_page_virt(vcpu, cr2);
5462 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5465 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5467 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5468 return handle_rmode_exception(vcpu, ex_no, error_code);
5472 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5475 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5476 if (!(vcpu->guest_debug &
5477 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5478 vcpu->arch.dr6 &= ~15;
5479 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5480 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5481 skip_emulated_instruction(vcpu);
5483 kvm_queue_exception(vcpu, DB_VECTOR);
5486 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5487 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5491 * Update instruction length as we may reinject #BP from
5492 * user space while in guest debugging mode. Reading it for
5493 * #DB as well causes no harm, it is not used in that case.
5495 vmx->vcpu.arch.event_exit_inst_len =
5496 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5497 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5498 rip = kvm_rip_read(vcpu);
5499 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5500 kvm_run->debug.arch.exception = ex_no;
5503 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5504 kvm_run->ex.exception = ex_no;
5505 kvm_run->ex.error_code = error_code;
5511 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5513 ++vcpu->stat.irq_exits;
5517 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5519 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5523 static int handle_io(struct kvm_vcpu *vcpu)
5525 unsigned long exit_qualification;
5526 int size, in, string;
5529 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5530 string = (exit_qualification & 16) != 0;
5531 in = (exit_qualification & 8) != 0;
5533 ++vcpu->stat.io_exits;
5536 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5538 port = exit_qualification >> 16;
5539 size = (exit_qualification & 7) + 1;
5540 skip_emulated_instruction(vcpu);
5542 return kvm_fast_pio_out(vcpu, size, port);
5546 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5549 * Patch in the VMCALL instruction:
5551 hypercall[0] = 0x0f;
5552 hypercall[1] = 0x01;
5553 hypercall[2] = 0xc1;
5556 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5558 unsigned long always_on = VMXON_CR0_ALWAYSON;
5559 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5561 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5562 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5563 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5564 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5565 return (val & always_on) == always_on;
5568 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5569 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5571 if (is_guest_mode(vcpu)) {
5572 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5573 unsigned long orig_val = val;
5576 * We get here when L2 changed cr0 in a way that did not change
5577 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5578 * but did change L0 shadowed bits. So we first calculate the
5579 * effective cr0 value that L1 would like to write into the
5580 * hardware. It consists of the L2-owned bits from the new
5581 * value combined with the L1-owned bits from L1's guest_cr0.
5583 val = (val & ~vmcs12->cr0_guest_host_mask) |
5584 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5586 if (!nested_cr0_valid(vcpu, val))
5589 if (kvm_set_cr0(vcpu, val))
5591 vmcs_writel(CR0_READ_SHADOW, orig_val);
5594 if (to_vmx(vcpu)->nested.vmxon &&
5595 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5597 return kvm_set_cr0(vcpu, val);
5601 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5603 if (is_guest_mode(vcpu)) {
5604 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5605 unsigned long orig_val = val;
5607 /* analogously to handle_set_cr0 */
5608 val = (val & ~vmcs12->cr4_guest_host_mask) |
5609 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5610 if (kvm_set_cr4(vcpu, val))
5612 vmcs_writel(CR4_READ_SHADOW, orig_val);
5615 return kvm_set_cr4(vcpu, val);
5618 /* called to set cr0 as appropriate for clts instruction exit. */
5619 static void handle_clts(struct kvm_vcpu *vcpu)
5621 if (is_guest_mode(vcpu)) {
5623 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5624 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5625 * just pretend it's off (also in arch.cr0 for fpu_activate).
5627 vmcs_writel(CR0_READ_SHADOW,
5628 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5629 vcpu->arch.cr0 &= ~X86_CR0_TS;
5631 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5634 static int handle_cr(struct kvm_vcpu *vcpu)
5636 unsigned long exit_qualification, val;
5641 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5642 cr = exit_qualification & 15;
5643 reg = (exit_qualification >> 8) & 15;
5644 switch ((exit_qualification >> 4) & 3) {
5645 case 0: /* mov to cr */
5646 val = kvm_register_readl(vcpu, reg);
5647 trace_kvm_cr_write(cr, val);
5650 err = handle_set_cr0(vcpu, val);
5651 kvm_complete_insn_gp(vcpu, err);
5654 err = kvm_set_cr3(vcpu, val);
5655 kvm_complete_insn_gp(vcpu, err);
5658 err = handle_set_cr4(vcpu, val);
5659 kvm_complete_insn_gp(vcpu, err);
5662 u8 cr8_prev = kvm_get_cr8(vcpu);
5664 err = kvm_set_cr8(vcpu, cr8);
5665 kvm_complete_insn_gp(vcpu, err);
5666 if (lapic_in_kernel(vcpu))
5668 if (cr8_prev <= cr8)
5670 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5677 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5678 skip_emulated_instruction(vcpu);
5679 vmx_fpu_activate(vcpu);
5681 case 1: /*mov from cr*/
5684 val = kvm_read_cr3(vcpu);
5685 kvm_register_write(vcpu, reg, val);
5686 trace_kvm_cr_read(cr, val);
5687 skip_emulated_instruction(vcpu);
5690 val = kvm_get_cr8(vcpu);
5691 kvm_register_write(vcpu, reg, val);
5692 trace_kvm_cr_read(cr, val);
5693 skip_emulated_instruction(vcpu);
5698 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5699 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5700 kvm_lmsw(vcpu, val);
5702 skip_emulated_instruction(vcpu);
5707 vcpu->run->exit_reason = 0;
5708 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5709 (int)(exit_qualification >> 4) & 3, cr);
5713 static int handle_dr(struct kvm_vcpu *vcpu)
5715 unsigned long exit_qualification;
5718 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5719 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5721 /* First, if DR does not exist, trigger UD */
5722 if (!kvm_require_dr(vcpu, dr))
5725 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5726 if (!kvm_require_cpl(vcpu, 0))
5728 dr7 = vmcs_readl(GUEST_DR7);
5731 * As the vm-exit takes precedence over the debug trap, we
5732 * need to emulate the latter, either for the host or the
5733 * guest debugging itself.
5735 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5736 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5737 vcpu->run->debug.arch.dr7 = dr7;
5738 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5739 vcpu->run->debug.arch.exception = DB_VECTOR;
5740 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5743 vcpu->arch.dr6 &= ~15;
5744 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5745 kvm_queue_exception(vcpu, DB_VECTOR);
5750 if (vcpu->guest_debug == 0) {
5751 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5752 CPU_BASED_MOV_DR_EXITING);
5755 * No more DR vmexits; force a reload of the debug registers
5756 * and reenter on this instruction. The next vmexit will
5757 * retrieve the full state of the debug registers.
5759 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5763 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5764 if (exit_qualification & TYPE_MOV_FROM_DR) {
5767 if (kvm_get_dr(vcpu, dr, &val))
5769 kvm_register_write(vcpu, reg, val);
5771 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5774 skip_emulated_instruction(vcpu);
5778 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5780 return vcpu->arch.dr6;
5783 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5787 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5789 get_debugreg(vcpu->arch.db[0], 0);
5790 get_debugreg(vcpu->arch.db[1], 1);
5791 get_debugreg(vcpu->arch.db[2], 2);
5792 get_debugreg(vcpu->arch.db[3], 3);
5793 get_debugreg(vcpu->arch.dr6, 6);
5794 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5796 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5797 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5800 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5802 vmcs_writel(GUEST_DR7, val);
5805 static int handle_cpuid(struct kvm_vcpu *vcpu)
5807 kvm_emulate_cpuid(vcpu);
5811 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5813 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5814 struct msr_data msr_info;
5816 msr_info.index = ecx;
5817 msr_info.host_initiated = false;
5818 if (vmx_get_msr(vcpu, &msr_info)) {
5819 trace_kvm_msr_read_ex(ecx);
5820 kvm_inject_gp(vcpu, 0);
5824 trace_kvm_msr_read(ecx, msr_info.data);
5826 /* FIXME: handling of bits 32:63 of rax, rdx */
5827 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5828 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5829 skip_emulated_instruction(vcpu);
5833 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5835 struct msr_data msr;
5836 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5837 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5838 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5842 msr.host_initiated = false;
5843 if (kvm_set_msr(vcpu, &msr) != 0) {
5844 trace_kvm_msr_write_ex(ecx, data);
5845 kvm_inject_gp(vcpu, 0);
5849 trace_kvm_msr_write(ecx, data);
5850 skip_emulated_instruction(vcpu);
5854 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5856 kvm_make_request(KVM_REQ_EVENT, vcpu);
5860 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5862 u32 cpu_based_vm_exec_control;
5864 /* clear pending irq */
5865 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5866 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5867 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5869 kvm_make_request(KVM_REQ_EVENT, vcpu);
5871 ++vcpu->stat.irq_window_exits;
5875 static int handle_halt(struct kvm_vcpu *vcpu)
5877 return kvm_emulate_halt(vcpu);
5880 static int handle_vmcall(struct kvm_vcpu *vcpu)
5882 return kvm_emulate_hypercall(vcpu);
5885 static int handle_invd(struct kvm_vcpu *vcpu)
5887 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5890 static int handle_invlpg(struct kvm_vcpu *vcpu)
5892 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5894 kvm_mmu_invlpg(vcpu, exit_qualification);
5895 skip_emulated_instruction(vcpu);
5899 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5903 err = kvm_rdpmc(vcpu);
5904 kvm_complete_insn_gp(vcpu, err);
5909 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5911 kvm_emulate_wbinvd(vcpu);
5915 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5917 u64 new_bv = kvm_read_edx_eax(vcpu);
5918 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5920 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5921 skip_emulated_instruction(vcpu);
5925 static int handle_xsaves(struct kvm_vcpu *vcpu)
5927 skip_emulated_instruction(vcpu);
5928 WARN(1, "this should never happen\n");
5932 static int handle_xrstors(struct kvm_vcpu *vcpu)
5934 skip_emulated_instruction(vcpu);
5935 WARN(1, "this should never happen\n");
5939 static int handle_apic_access(struct kvm_vcpu *vcpu)
5941 if (likely(fasteoi)) {
5942 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5943 int access_type, offset;
5945 access_type = exit_qualification & APIC_ACCESS_TYPE;
5946 offset = exit_qualification & APIC_ACCESS_OFFSET;
5948 * Sane guest uses MOV to write EOI, with written value
5949 * not cared. So make a short-circuit here by avoiding
5950 * heavy instruction emulation.
5952 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5953 (offset == APIC_EOI)) {
5954 kvm_lapic_set_eoi(vcpu);
5955 skip_emulated_instruction(vcpu);
5959 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5962 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5964 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5965 int vector = exit_qualification & 0xff;
5967 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5968 kvm_apic_set_eoi_accelerated(vcpu, vector);
5972 static int handle_apic_write(struct kvm_vcpu *vcpu)
5974 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5975 u32 offset = exit_qualification & 0xfff;
5977 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5978 kvm_apic_write_nodecode(vcpu, offset);
5982 static int handle_task_switch(struct kvm_vcpu *vcpu)
5984 struct vcpu_vmx *vmx = to_vmx(vcpu);
5985 unsigned long exit_qualification;
5986 bool has_error_code = false;
5989 int reason, type, idt_v, idt_index;
5991 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5992 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5993 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5995 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5997 reason = (u32)exit_qualification >> 30;
5998 if (reason == TASK_SWITCH_GATE && idt_v) {
6000 case INTR_TYPE_NMI_INTR:
6001 vcpu->arch.nmi_injected = false;
6002 vmx_set_nmi_mask(vcpu, true);
6004 case INTR_TYPE_EXT_INTR:
6005 case INTR_TYPE_SOFT_INTR:
6006 kvm_clear_interrupt_queue(vcpu);
6008 case INTR_TYPE_HARD_EXCEPTION:
6009 if (vmx->idt_vectoring_info &
6010 VECTORING_INFO_DELIVER_CODE_MASK) {
6011 has_error_code = true;
6013 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6016 case INTR_TYPE_SOFT_EXCEPTION:
6017 kvm_clear_exception_queue(vcpu);
6023 tss_selector = exit_qualification;
6025 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6026 type != INTR_TYPE_EXT_INTR &&
6027 type != INTR_TYPE_NMI_INTR))
6028 skip_emulated_instruction(vcpu);
6030 if (kvm_task_switch(vcpu, tss_selector,
6031 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6032 has_error_code, error_code) == EMULATE_FAIL) {
6033 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6034 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6035 vcpu->run->internal.ndata = 0;
6040 * TODO: What about debug traps on tss switch?
6041 * Are we supposed to inject them and update dr6?
6047 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6049 unsigned long exit_qualification;
6054 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6056 gla_validity = (exit_qualification >> 7) & 0x3;
6057 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
6058 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6059 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6060 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6061 vmcs_readl(GUEST_LINEAR_ADDRESS));
6062 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6063 (long unsigned int)exit_qualification);
6064 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6065 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6070 * EPT violation happened while executing iret from NMI,
6071 * "blocked by NMI" bit has to be set before next VM entry.
6072 * There are errata that may cause this bit to not be set:
6075 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6076 cpu_has_virtual_nmis() &&
6077 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6078 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6080 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6081 trace_kvm_page_fault(gpa, exit_qualification);
6083 /* It is a write fault? */
6084 error_code = exit_qualification & PFERR_WRITE_MASK;
6085 /* It is a fetch fault? */
6086 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
6087 /* ept page table is present? */
6088 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
6090 vcpu->arch.exit_qualification = exit_qualification;
6092 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6095 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6100 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6101 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6102 skip_emulated_instruction(vcpu);
6103 trace_kvm_fast_mmio(gpa);
6107 ret = handle_mmio_page_fault(vcpu, gpa, true);
6108 if (likely(ret == RET_MMIO_PF_EMULATE))
6109 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6112 if (unlikely(ret == RET_MMIO_PF_INVALID))
6113 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6115 if (unlikely(ret == RET_MMIO_PF_RETRY))
6118 /* It is the real ept misconfig */
6121 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6122 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6127 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6129 u32 cpu_based_vm_exec_control;
6131 /* clear pending NMI */
6132 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6133 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6134 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6135 ++vcpu->stat.nmi_window_exits;
6136 kvm_make_request(KVM_REQ_EVENT, vcpu);
6141 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6143 struct vcpu_vmx *vmx = to_vmx(vcpu);
6144 enum emulation_result err = EMULATE_DONE;
6147 bool intr_window_requested;
6148 unsigned count = 130;
6150 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6151 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6153 while (vmx->emulation_required && count-- != 0) {
6154 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6155 return handle_interrupt_window(&vmx->vcpu);
6157 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6160 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6162 if (err == EMULATE_USER_EXIT) {
6163 ++vcpu->stat.mmio_exits;
6168 if (err != EMULATE_DONE) {
6169 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6170 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6171 vcpu->run->internal.ndata = 0;
6175 if (vcpu->arch.halt_request) {
6176 vcpu->arch.halt_request = 0;
6177 ret = kvm_vcpu_halt(vcpu);
6181 if (signal_pending(current))
6191 static int __grow_ple_window(int val)
6193 if (ple_window_grow < 1)
6196 val = min(val, ple_window_actual_max);
6198 if (ple_window_grow < ple_window)
6199 val *= ple_window_grow;
6201 val += ple_window_grow;
6206 static int __shrink_ple_window(int val, int modifier, int minimum)
6211 if (modifier < ple_window)
6216 return max(val, minimum);
6219 static void grow_ple_window(struct kvm_vcpu *vcpu)
6221 struct vcpu_vmx *vmx = to_vmx(vcpu);
6222 int old = vmx->ple_window;
6224 vmx->ple_window = __grow_ple_window(old);
6226 if (vmx->ple_window != old)
6227 vmx->ple_window_dirty = true;
6229 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6232 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6234 struct vcpu_vmx *vmx = to_vmx(vcpu);
6235 int old = vmx->ple_window;
6237 vmx->ple_window = __shrink_ple_window(old,
6238 ple_window_shrink, ple_window);
6240 if (vmx->ple_window != old)
6241 vmx->ple_window_dirty = true;
6243 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6247 * ple_window_actual_max is computed to be one grow_ple_window() below
6248 * ple_window_max. (See __grow_ple_window for the reason.)
6249 * This prevents overflows, because ple_window_max is int.
6250 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6252 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6254 static void update_ple_window_actual_max(void)
6256 ple_window_actual_max =
6257 __shrink_ple_window(max(ple_window_max, ple_window),
6258 ple_window_grow, INT_MIN);
6262 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6264 static void wakeup_handler(void)
6266 struct kvm_vcpu *vcpu;
6267 int cpu = smp_processor_id();
6269 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6270 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6271 blocked_vcpu_list) {
6272 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6274 if (pi_test_on(pi_desc) == 1)
6275 kvm_vcpu_kick(vcpu);
6277 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6280 static __init int hardware_setup(void)
6282 int r = -ENOMEM, i, msr;
6284 rdmsrl_safe(MSR_EFER, &host_efer);
6286 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6287 kvm_define_shared_msr(i, vmx_msr_index[i]);
6289 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6290 if (!vmx_io_bitmap_a)
6293 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6294 if (!vmx_io_bitmap_b)
6297 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6298 if (!vmx_msr_bitmap_legacy)
6301 vmx_msr_bitmap_legacy_x2apic =
6302 (unsigned long *)__get_free_page(GFP_KERNEL);
6303 if (!vmx_msr_bitmap_legacy_x2apic)
6306 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6307 if (!vmx_msr_bitmap_longmode)
6310 vmx_msr_bitmap_longmode_x2apic =
6311 (unsigned long *)__get_free_page(GFP_KERNEL);
6312 if (!vmx_msr_bitmap_longmode_x2apic)
6316 vmx_msr_bitmap_nested =
6317 (unsigned long *)__get_free_page(GFP_KERNEL);
6318 if (!vmx_msr_bitmap_nested)
6322 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6323 if (!vmx_vmread_bitmap)
6326 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6327 if (!vmx_vmwrite_bitmap)
6330 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6331 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6334 * Allow direct access to the PC debug port (it is often used for I/O
6335 * delays, but the vmexits simply slow things down).
6337 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6338 clear_bit(0x80, vmx_io_bitmap_a);
6340 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6342 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6343 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6345 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6347 if (setup_vmcs_config(&vmcs_config) < 0) {
6352 if (boot_cpu_has(X86_FEATURE_NX))
6353 kvm_enable_efer_bits(EFER_NX);
6355 if (!cpu_has_vmx_vpid())
6357 if (!cpu_has_vmx_shadow_vmcs())
6358 enable_shadow_vmcs = 0;
6359 if (enable_shadow_vmcs)
6360 init_vmcs_shadow_fields();
6362 if (!cpu_has_vmx_ept() ||
6363 !cpu_has_vmx_ept_4levels()) {
6365 enable_unrestricted_guest = 0;
6366 enable_ept_ad_bits = 0;
6369 if (!cpu_has_vmx_ept_ad_bits())
6370 enable_ept_ad_bits = 0;
6372 if (!cpu_has_vmx_unrestricted_guest())
6373 enable_unrestricted_guest = 0;
6375 if (!cpu_has_vmx_flexpriority())
6376 flexpriority_enabled = 0;
6379 * set_apic_access_page_addr() is used to reload apic access
6380 * page upon invalidation. No need to do anything if not
6381 * using the APIC_ACCESS_ADDR VMCS field.
6383 if (!flexpriority_enabled)
6384 kvm_x86_ops->set_apic_access_page_addr = NULL;
6386 if (!cpu_has_vmx_tpr_shadow())
6387 kvm_x86_ops->update_cr8_intercept = NULL;
6389 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6390 kvm_disable_largepages();
6392 if (!cpu_has_vmx_ple())
6395 if (!cpu_has_vmx_apicv())
6398 if (cpu_has_vmx_tsc_scaling()) {
6399 kvm_has_tsc_control = true;
6400 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6401 kvm_tsc_scaling_ratio_frac_bits = 48;
6404 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6405 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6406 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6407 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6408 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6409 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6410 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6412 memcpy(vmx_msr_bitmap_legacy_x2apic,
6413 vmx_msr_bitmap_legacy, PAGE_SIZE);
6414 memcpy(vmx_msr_bitmap_longmode_x2apic,
6415 vmx_msr_bitmap_longmode, PAGE_SIZE);
6417 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6419 for (msr = 0x800; msr <= 0x8ff; msr++)
6420 vmx_disable_intercept_msr_read_x2apic(msr);
6422 /* According SDM, in x2apic mode, the whole id reg is used. But in
6423 * KVM, it only use the highest eight bits. Need to intercept it */
6424 vmx_enable_intercept_msr_read_x2apic(0x802);
6426 vmx_enable_intercept_msr_read_x2apic(0x839);
6428 vmx_disable_intercept_msr_write_x2apic(0x808);
6430 vmx_disable_intercept_msr_write_x2apic(0x80b);
6432 vmx_disable_intercept_msr_write_x2apic(0x83f);
6435 kvm_mmu_set_mask_ptes(0ull,
6436 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6437 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6438 0ull, VMX_EPT_EXECUTABLE_MASK);
6439 ept_set_mmio_spte_mask();
6444 update_ple_window_actual_max();
6447 * Only enable PML when hardware supports PML feature, and both EPT
6448 * and EPT A/D bit features are enabled -- PML depends on them to work.
6450 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6454 kvm_x86_ops->slot_enable_log_dirty = NULL;
6455 kvm_x86_ops->slot_disable_log_dirty = NULL;
6456 kvm_x86_ops->flush_log_dirty = NULL;
6457 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6460 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6463 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6464 cpu_preemption_timer_multi =
6465 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6467 kvm_x86_ops->set_hv_timer = NULL;
6468 kvm_x86_ops->cancel_hv_timer = NULL;
6471 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6473 return alloc_kvm_area();
6476 free_page((unsigned long)vmx_vmwrite_bitmap);
6478 free_page((unsigned long)vmx_vmread_bitmap);
6481 free_page((unsigned long)vmx_msr_bitmap_nested);
6483 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6485 free_page((unsigned long)vmx_msr_bitmap_longmode);
6487 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6489 free_page((unsigned long)vmx_msr_bitmap_legacy);
6491 free_page((unsigned long)vmx_io_bitmap_b);
6493 free_page((unsigned long)vmx_io_bitmap_a);
6498 static __exit void hardware_unsetup(void)
6500 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6501 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6502 free_page((unsigned long)vmx_msr_bitmap_legacy);
6503 free_page((unsigned long)vmx_msr_bitmap_longmode);
6504 free_page((unsigned long)vmx_io_bitmap_b);
6505 free_page((unsigned long)vmx_io_bitmap_a);
6506 free_page((unsigned long)vmx_vmwrite_bitmap);
6507 free_page((unsigned long)vmx_vmread_bitmap);
6509 free_page((unsigned long)vmx_msr_bitmap_nested);
6515 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6516 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6518 static int handle_pause(struct kvm_vcpu *vcpu)
6521 grow_ple_window(vcpu);
6523 skip_emulated_instruction(vcpu);
6524 kvm_vcpu_on_spin(vcpu);
6529 static int handle_nop(struct kvm_vcpu *vcpu)
6531 skip_emulated_instruction(vcpu);
6535 static int handle_mwait(struct kvm_vcpu *vcpu)
6537 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6538 return handle_nop(vcpu);
6541 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6546 static int handle_monitor(struct kvm_vcpu *vcpu)
6548 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6549 return handle_nop(vcpu);
6553 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6554 * We could reuse a single VMCS for all the L2 guests, but we also want the
6555 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6556 * allows keeping them loaded on the processor, and in the future will allow
6557 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6558 * every entry if they never change.
6559 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6560 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6562 * The following functions allocate and free a vmcs02 in this pool.
6565 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6566 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6568 struct vmcs02_list *item;
6569 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6570 if (item->vmptr == vmx->nested.current_vmptr) {
6571 list_move(&item->list, &vmx->nested.vmcs02_pool);
6572 return &item->vmcs02;
6575 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6576 /* Recycle the least recently used VMCS. */
6577 item = list_last_entry(&vmx->nested.vmcs02_pool,
6578 struct vmcs02_list, list);
6579 item->vmptr = vmx->nested.current_vmptr;
6580 list_move(&item->list, &vmx->nested.vmcs02_pool);
6581 return &item->vmcs02;
6584 /* Create a new VMCS */
6585 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6588 item->vmcs02.vmcs = alloc_vmcs();
6589 if (!item->vmcs02.vmcs) {
6593 loaded_vmcs_init(&item->vmcs02);
6594 item->vmptr = vmx->nested.current_vmptr;
6595 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6596 vmx->nested.vmcs02_num++;
6597 return &item->vmcs02;
6600 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6601 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6603 struct vmcs02_list *item;
6604 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6605 if (item->vmptr == vmptr) {
6606 free_loaded_vmcs(&item->vmcs02);
6607 list_del(&item->list);
6609 vmx->nested.vmcs02_num--;
6615 * Free all VMCSs saved for this vcpu, except the one pointed by
6616 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6617 * must be &vmx->vmcs01.
6619 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6621 struct vmcs02_list *item, *n;
6623 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6624 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6626 * Something will leak if the above WARN triggers. Better than
6629 if (vmx->loaded_vmcs == &item->vmcs02)
6632 free_loaded_vmcs(&item->vmcs02);
6633 list_del(&item->list);
6635 vmx->nested.vmcs02_num--;
6640 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6641 * set the success or error code of an emulated VMX instruction, as specified
6642 * by Vol 2B, VMX Instruction Reference, "Conventions".
6644 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6646 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6647 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6648 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6651 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6653 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6654 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6655 X86_EFLAGS_SF | X86_EFLAGS_OF))
6659 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6660 u32 vm_instruction_error)
6662 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6664 * failValid writes the error number to the current VMCS, which
6665 * can't be done there isn't a current VMCS.
6667 nested_vmx_failInvalid(vcpu);
6670 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6671 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6672 X86_EFLAGS_SF | X86_EFLAGS_OF))
6674 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6676 * We don't need to force a shadow sync because
6677 * VM_INSTRUCTION_ERROR is not shadowed
6681 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6683 /* TODO: not to reset guest simply here. */
6684 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6685 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6688 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6690 struct vcpu_vmx *vmx =
6691 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6693 vmx->nested.preemption_timer_expired = true;
6694 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6695 kvm_vcpu_kick(&vmx->vcpu);
6697 return HRTIMER_NORESTART;
6701 * Decode the memory-address operand of a vmx instruction, as recorded on an
6702 * exit caused by such an instruction (run by a guest hypervisor).
6703 * On success, returns 0. When the operand is invalid, returns 1 and throws
6706 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6707 unsigned long exit_qualification,
6708 u32 vmx_instruction_info, bool wr, gva_t *ret)
6712 struct kvm_segment s;
6715 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6716 * Execution", on an exit, vmx_instruction_info holds most of the
6717 * addressing components of the operand. Only the displacement part
6718 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6719 * For how an actual address is calculated from all these components,
6720 * refer to Vol. 1, "Operand Addressing".
6722 int scaling = vmx_instruction_info & 3;
6723 int addr_size = (vmx_instruction_info >> 7) & 7;
6724 bool is_reg = vmx_instruction_info & (1u << 10);
6725 int seg_reg = (vmx_instruction_info >> 15) & 7;
6726 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6727 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6728 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6729 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6732 kvm_queue_exception(vcpu, UD_VECTOR);
6736 /* Addr = segment_base + offset */
6737 /* offset = base + [index * scale] + displacement */
6738 off = exit_qualification; /* holds the displacement */
6740 off += kvm_register_read(vcpu, base_reg);
6742 off += kvm_register_read(vcpu, index_reg)<<scaling;
6743 vmx_get_segment(vcpu, &s, seg_reg);
6744 *ret = s.base + off;
6746 if (addr_size == 1) /* 32 bit */
6749 /* Checks for #GP/#SS exceptions. */
6751 if (is_protmode(vcpu)) {
6752 /* Protected mode: apply checks for segment validity in the
6754 * - segment type check (#GP(0) may be thrown)
6755 * - usability check (#GP(0)/#SS(0))
6756 * - limit check (#GP(0)/#SS(0))
6759 /* #GP(0) if the destination operand is located in a
6760 * read-only data segment or any code segment.
6762 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6764 /* #GP(0) if the source operand is located in an
6765 * execute-only code segment
6767 exn = ((s.type & 0xa) == 8);
6770 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6773 if (is_long_mode(vcpu)) {
6774 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6775 * non-canonical form. This is an only check for long mode.
6777 exn = is_noncanonical_address(*ret);
6778 } else if (is_protmode(vcpu)) {
6779 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6781 exn = (s.unusable != 0);
6782 /* Protected mode: #GP(0)/#SS(0) if the memory
6783 * operand is outside the segment limit.
6785 exn = exn || (off + sizeof(u64) > s.limit);
6788 kvm_queue_exception_e(vcpu,
6789 seg_reg == VCPU_SREG_SS ?
6790 SS_VECTOR : GP_VECTOR,
6799 * This function performs the various checks including
6800 * - if it's 4KB aligned
6801 * - No bits beyond the physical address width are set
6802 * - Returns 0 on success or else 1
6803 * (Intel SDM Section 30.3)
6805 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6810 struct x86_exception e;
6812 struct vcpu_vmx *vmx = to_vmx(vcpu);
6813 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6815 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6816 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6819 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6820 sizeof(vmptr), &e)) {
6821 kvm_inject_page_fault(vcpu, &e);
6825 switch (exit_reason) {
6826 case EXIT_REASON_VMON:
6829 * The first 4 bytes of VMXON region contain the supported
6830 * VMCS revision identifier
6832 * Note - IA32_VMX_BASIC[48] will never be 1
6833 * for the nested case;
6834 * which replaces physical address width with 32
6837 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6838 nested_vmx_failInvalid(vcpu);
6839 skip_emulated_instruction(vcpu);
6843 page = nested_get_page(vcpu, vmptr);
6845 *(u32 *)kmap(page) != VMCS12_REVISION) {
6846 nested_vmx_failInvalid(vcpu);
6848 skip_emulated_instruction(vcpu);
6852 vmx->nested.vmxon_ptr = vmptr;
6854 case EXIT_REASON_VMCLEAR:
6855 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6856 nested_vmx_failValid(vcpu,
6857 VMXERR_VMCLEAR_INVALID_ADDRESS);
6858 skip_emulated_instruction(vcpu);
6862 if (vmptr == vmx->nested.vmxon_ptr) {
6863 nested_vmx_failValid(vcpu,
6864 VMXERR_VMCLEAR_VMXON_POINTER);
6865 skip_emulated_instruction(vcpu);
6869 case EXIT_REASON_VMPTRLD:
6870 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6871 nested_vmx_failValid(vcpu,
6872 VMXERR_VMPTRLD_INVALID_ADDRESS);
6873 skip_emulated_instruction(vcpu);
6877 if (vmptr == vmx->nested.vmxon_ptr) {
6878 nested_vmx_failValid(vcpu,
6879 VMXERR_VMCLEAR_VMXON_POINTER);
6880 skip_emulated_instruction(vcpu);
6885 return 1; /* shouldn't happen */
6894 * Emulate the VMXON instruction.
6895 * Currently, we just remember that VMX is active, and do not save or even
6896 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6897 * do not currently need to store anything in that guest-allocated memory
6898 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6899 * argument is different from the VMXON pointer (which the spec says they do).
6901 static int handle_vmon(struct kvm_vcpu *vcpu)
6903 struct kvm_segment cs;
6904 struct vcpu_vmx *vmx = to_vmx(vcpu);
6905 struct vmcs *shadow_vmcs;
6906 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6907 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6909 /* The Intel VMX Instruction Reference lists a bunch of bits that
6910 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6911 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6912 * Otherwise, we should fail with #UD. We test these now:
6914 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6915 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6916 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6917 kvm_queue_exception(vcpu, UD_VECTOR);
6921 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6922 if (is_long_mode(vcpu) && !cs.l) {
6923 kvm_queue_exception(vcpu, UD_VECTOR);
6927 if (vmx_get_cpl(vcpu)) {
6928 kvm_inject_gp(vcpu, 0);
6932 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6935 if (vmx->nested.vmxon) {
6936 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6937 skip_emulated_instruction(vcpu);
6941 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6942 != VMXON_NEEDED_FEATURES) {
6943 kvm_inject_gp(vcpu, 0);
6947 if (enable_shadow_vmcs) {
6948 shadow_vmcs = alloc_vmcs();
6951 /* mark vmcs as shadow */
6952 shadow_vmcs->revision_id |= (1u << 31);
6953 /* init shadow vmcs */
6954 vmcs_clear(shadow_vmcs);
6955 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6958 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6959 vmx->nested.vmcs02_num = 0;
6961 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6963 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6965 vmx->nested.vmxon = true;
6967 skip_emulated_instruction(vcpu);
6968 nested_vmx_succeed(vcpu);
6973 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6974 * for running VMX instructions (except VMXON, whose prerequisites are
6975 * slightly different). It also specifies what exception to inject otherwise.
6977 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6979 struct kvm_segment cs;
6980 struct vcpu_vmx *vmx = to_vmx(vcpu);
6982 if (!vmx->nested.vmxon) {
6983 kvm_queue_exception(vcpu, UD_VECTOR);
6987 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6988 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6989 (is_long_mode(vcpu) && !cs.l)) {
6990 kvm_queue_exception(vcpu, UD_VECTOR);
6994 if (vmx_get_cpl(vcpu)) {
6995 kvm_inject_gp(vcpu, 0);
7002 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7004 if (vmx->nested.current_vmptr == -1ull)
7007 /* current_vmptr and current_vmcs12 are always set/reset together */
7008 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7011 if (enable_shadow_vmcs) {
7012 /* copy to memory all shadowed fields in case
7013 they were modified */
7014 copy_shadow_to_vmcs12(vmx);
7015 vmx->nested.sync_shadow_vmcs = false;
7016 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7017 SECONDARY_EXEC_SHADOW_VMCS);
7018 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7020 vmx->nested.posted_intr_nv = -1;
7021 kunmap(vmx->nested.current_vmcs12_page);
7022 nested_release_page(vmx->nested.current_vmcs12_page);
7023 vmx->nested.current_vmptr = -1ull;
7024 vmx->nested.current_vmcs12 = NULL;
7028 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7029 * just stops using VMX.
7031 static void free_nested(struct vcpu_vmx *vmx)
7033 if (!vmx->nested.vmxon)
7036 vmx->nested.vmxon = false;
7037 free_vpid(vmx->nested.vpid02);
7038 nested_release_vmcs12(vmx);
7039 if (enable_shadow_vmcs)
7040 free_vmcs(vmx->nested.current_shadow_vmcs);
7041 /* Unpin physical memory we referred to in current vmcs02 */
7042 if (vmx->nested.apic_access_page) {
7043 nested_release_page(vmx->nested.apic_access_page);
7044 vmx->nested.apic_access_page = NULL;
7046 if (vmx->nested.virtual_apic_page) {
7047 nested_release_page(vmx->nested.virtual_apic_page);
7048 vmx->nested.virtual_apic_page = NULL;
7050 if (vmx->nested.pi_desc_page) {
7051 kunmap(vmx->nested.pi_desc_page);
7052 nested_release_page(vmx->nested.pi_desc_page);
7053 vmx->nested.pi_desc_page = NULL;
7054 vmx->nested.pi_desc = NULL;
7057 nested_free_all_saved_vmcss(vmx);
7060 /* Emulate the VMXOFF instruction */
7061 static int handle_vmoff(struct kvm_vcpu *vcpu)
7063 if (!nested_vmx_check_permission(vcpu))
7065 free_nested(to_vmx(vcpu));
7066 skip_emulated_instruction(vcpu);
7067 nested_vmx_succeed(vcpu);
7071 /* Emulate the VMCLEAR instruction */
7072 static int handle_vmclear(struct kvm_vcpu *vcpu)
7074 struct vcpu_vmx *vmx = to_vmx(vcpu);
7076 struct vmcs12 *vmcs12;
7079 if (!nested_vmx_check_permission(vcpu))
7082 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7085 if (vmptr == vmx->nested.current_vmptr)
7086 nested_release_vmcs12(vmx);
7088 page = nested_get_page(vcpu, vmptr);
7091 * For accurate processor emulation, VMCLEAR beyond available
7092 * physical memory should do nothing at all. However, it is
7093 * possible that a nested vmx bug, not a guest hypervisor bug,
7094 * resulted in this case, so let's shut down before doing any
7097 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7100 vmcs12 = kmap(page);
7101 vmcs12->launch_state = 0;
7103 nested_release_page(page);
7105 nested_free_vmcs02(vmx, vmptr);
7107 skip_emulated_instruction(vcpu);
7108 nested_vmx_succeed(vcpu);
7112 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7114 /* Emulate the VMLAUNCH instruction */
7115 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7117 return nested_vmx_run(vcpu, true);
7120 /* Emulate the VMRESUME instruction */
7121 static int handle_vmresume(struct kvm_vcpu *vcpu)
7124 return nested_vmx_run(vcpu, false);
7127 enum vmcs_field_type {
7128 VMCS_FIELD_TYPE_U16 = 0,
7129 VMCS_FIELD_TYPE_U64 = 1,
7130 VMCS_FIELD_TYPE_U32 = 2,
7131 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7134 static inline int vmcs_field_type(unsigned long field)
7136 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
7137 return VMCS_FIELD_TYPE_U32;
7138 return (field >> 13) & 0x3 ;
7141 static inline int vmcs_field_readonly(unsigned long field)
7143 return (((field >> 10) & 0x3) == 1);
7147 * Read a vmcs12 field. Since these can have varying lengths and we return
7148 * one type, we chose the biggest type (u64) and zero-extend the return value
7149 * to that size. Note that the caller, handle_vmread, might need to use only
7150 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7151 * 64-bit fields are to be returned).
7153 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7154 unsigned long field, u64 *ret)
7156 short offset = vmcs_field_to_offset(field);
7162 p = ((char *)(get_vmcs12(vcpu))) + offset;
7164 switch (vmcs_field_type(field)) {
7165 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7166 *ret = *((natural_width *)p);
7168 case VMCS_FIELD_TYPE_U16:
7171 case VMCS_FIELD_TYPE_U32:
7174 case VMCS_FIELD_TYPE_U64:
7184 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7185 unsigned long field, u64 field_value){
7186 short offset = vmcs_field_to_offset(field);
7187 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7191 switch (vmcs_field_type(field)) {
7192 case VMCS_FIELD_TYPE_U16:
7193 *(u16 *)p = field_value;
7195 case VMCS_FIELD_TYPE_U32:
7196 *(u32 *)p = field_value;
7198 case VMCS_FIELD_TYPE_U64:
7199 *(u64 *)p = field_value;
7201 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7202 *(natural_width *)p = field_value;
7211 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7214 unsigned long field;
7216 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7217 const unsigned long *fields = shadow_read_write_fields;
7218 const int num_fields = max_shadow_read_write_fields;
7222 vmcs_load(shadow_vmcs);
7224 for (i = 0; i < num_fields; i++) {
7226 switch (vmcs_field_type(field)) {
7227 case VMCS_FIELD_TYPE_U16:
7228 field_value = vmcs_read16(field);
7230 case VMCS_FIELD_TYPE_U32:
7231 field_value = vmcs_read32(field);
7233 case VMCS_FIELD_TYPE_U64:
7234 field_value = vmcs_read64(field);
7236 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7237 field_value = vmcs_readl(field);
7243 vmcs12_write_any(&vmx->vcpu, field, field_value);
7246 vmcs_clear(shadow_vmcs);
7247 vmcs_load(vmx->loaded_vmcs->vmcs);
7252 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7254 const unsigned long *fields[] = {
7255 shadow_read_write_fields,
7256 shadow_read_only_fields
7258 const int max_fields[] = {
7259 max_shadow_read_write_fields,
7260 max_shadow_read_only_fields
7263 unsigned long field;
7264 u64 field_value = 0;
7265 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7267 vmcs_load(shadow_vmcs);
7269 for (q = 0; q < ARRAY_SIZE(fields); q++) {
7270 for (i = 0; i < max_fields[q]; i++) {
7271 field = fields[q][i];
7272 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7274 switch (vmcs_field_type(field)) {
7275 case VMCS_FIELD_TYPE_U16:
7276 vmcs_write16(field, (u16)field_value);
7278 case VMCS_FIELD_TYPE_U32:
7279 vmcs_write32(field, (u32)field_value);
7281 case VMCS_FIELD_TYPE_U64:
7282 vmcs_write64(field, (u64)field_value);
7284 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7285 vmcs_writel(field, (long)field_value);
7294 vmcs_clear(shadow_vmcs);
7295 vmcs_load(vmx->loaded_vmcs->vmcs);
7299 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7300 * used before) all generate the same failure when it is missing.
7302 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7304 struct vcpu_vmx *vmx = to_vmx(vcpu);
7305 if (vmx->nested.current_vmptr == -1ull) {
7306 nested_vmx_failInvalid(vcpu);
7307 skip_emulated_instruction(vcpu);
7313 static int handle_vmread(struct kvm_vcpu *vcpu)
7315 unsigned long field;
7317 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7318 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7321 if (!nested_vmx_check_permission(vcpu) ||
7322 !nested_vmx_check_vmcs12(vcpu))
7325 /* Decode instruction info and find the field to read */
7326 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7327 /* Read the field, zero-extended to a u64 field_value */
7328 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7329 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7330 skip_emulated_instruction(vcpu);
7334 * Now copy part of this value to register or memory, as requested.
7335 * Note that the number of bits actually copied is 32 or 64 depending
7336 * on the guest's mode (32 or 64 bit), not on the given field's length.
7338 if (vmx_instruction_info & (1u << 10)) {
7339 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7342 if (get_vmx_mem_address(vcpu, exit_qualification,
7343 vmx_instruction_info, true, &gva))
7345 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7346 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7347 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7350 nested_vmx_succeed(vcpu);
7351 skip_emulated_instruction(vcpu);
7356 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7358 unsigned long field;
7360 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7361 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7362 /* The value to write might be 32 or 64 bits, depending on L1's long
7363 * mode, and eventually we need to write that into a field of several
7364 * possible lengths. The code below first zero-extends the value to 64
7365 * bit (field_value), and then copies only the appropriate number of
7366 * bits into the vmcs12 field.
7368 u64 field_value = 0;
7369 struct x86_exception e;
7371 if (!nested_vmx_check_permission(vcpu) ||
7372 !nested_vmx_check_vmcs12(vcpu))
7375 if (vmx_instruction_info & (1u << 10))
7376 field_value = kvm_register_readl(vcpu,
7377 (((vmx_instruction_info) >> 3) & 0xf));
7379 if (get_vmx_mem_address(vcpu, exit_qualification,
7380 vmx_instruction_info, false, &gva))
7382 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7383 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7384 kvm_inject_page_fault(vcpu, &e);
7390 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7391 if (vmcs_field_readonly(field)) {
7392 nested_vmx_failValid(vcpu,
7393 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7394 skip_emulated_instruction(vcpu);
7398 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7399 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7400 skip_emulated_instruction(vcpu);
7404 nested_vmx_succeed(vcpu);
7405 skip_emulated_instruction(vcpu);
7409 /* Emulate the VMPTRLD instruction */
7410 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7412 struct vcpu_vmx *vmx = to_vmx(vcpu);
7415 if (!nested_vmx_check_permission(vcpu))
7418 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7421 if (vmx->nested.current_vmptr != vmptr) {
7422 struct vmcs12 *new_vmcs12;
7424 page = nested_get_page(vcpu, vmptr);
7426 nested_vmx_failInvalid(vcpu);
7427 skip_emulated_instruction(vcpu);
7430 new_vmcs12 = kmap(page);
7431 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7433 nested_release_page_clean(page);
7434 nested_vmx_failValid(vcpu,
7435 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7436 skip_emulated_instruction(vcpu);
7440 nested_release_vmcs12(vmx);
7441 vmx->nested.current_vmptr = vmptr;
7442 vmx->nested.current_vmcs12 = new_vmcs12;
7443 vmx->nested.current_vmcs12_page = page;
7444 if (enable_shadow_vmcs) {
7445 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7446 SECONDARY_EXEC_SHADOW_VMCS);
7447 vmcs_write64(VMCS_LINK_POINTER,
7448 __pa(vmx->nested.current_shadow_vmcs));
7449 vmx->nested.sync_shadow_vmcs = true;
7453 nested_vmx_succeed(vcpu);
7454 skip_emulated_instruction(vcpu);
7458 /* Emulate the VMPTRST instruction */
7459 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7461 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7462 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7464 struct x86_exception e;
7466 if (!nested_vmx_check_permission(vcpu))
7469 if (get_vmx_mem_address(vcpu, exit_qualification,
7470 vmx_instruction_info, true, &vmcs_gva))
7472 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7473 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7474 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7476 kvm_inject_page_fault(vcpu, &e);
7479 nested_vmx_succeed(vcpu);
7480 skip_emulated_instruction(vcpu);
7484 /* Emulate the INVEPT instruction */
7485 static int handle_invept(struct kvm_vcpu *vcpu)
7487 struct vcpu_vmx *vmx = to_vmx(vcpu);
7488 u32 vmx_instruction_info, types;
7491 struct x86_exception e;
7496 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7497 SECONDARY_EXEC_ENABLE_EPT) ||
7498 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7499 kvm_queue_exception(vcpu, UD_VECTOR);
7503 if (!nested_vmx_check_permission(vcpu))
7506 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7507 kvm_queue_exception(vcpu, UD_VECTOR);
7511 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7512 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7514 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7516 if (!(types & (1UL << type))) {
7517 nested_vmx_failValid(vcpu,
7518 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7519 skip_emulated_instruction(vcpu);
7523 /* According to the Intel VMX instruction reference, the memory
7524 * operand is read even if it isn't needed (e.g., for type==global)
7526 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7527 vmx_instruction_info, false, &gva))
7529 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7530 sizeof(operand), &e)) {
7531 kvm_inject_page_fault(vcpu, &e);
7536 case VMX_EPT_EXTENT_GLOBAL:
7537 kvm_mmu_sync_roots(vcpu);
7538 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7539 nested_vmx_succeed(vcpu);
7542 /* Trap single context invalidation invept calls */
7547 skip_emulated_instruction(vcpu);
7551 static int handle_invvpid(struct kvm_vcpu *vcpu)
7553 struct vcpu_vmx *vmx = to_vmx(vcpu);
7554 u32 vmx_instruction_info;
7555 unsigned long type, types;
7557 struct x86_exception e;
7560 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7561 SECONDARY_EXEC_ENABLE_VPID) ||
7562 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7563 kvm_queue_exception(vcpu, UD_VECTOR);
7567 if (!nested_vmx_check_permission(vcpu))
7570 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7571 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7573 types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7575 if (!(types & (1UL << type))) {
7576 nested_vmx_failValid(vcpu,
7577 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7578 skip_emulated_instruction(vcpu);
7582 /* according to the intel vmx instruction reference, the memory
7583 * operand is read even if it isn't needed (e.g., for type==global)
7585 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7586 vmx_instruction_info, false, &gva))
7588 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7590 kvm_inject_page_fault(vcpu, &e);
7595 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7597 * Old versions of KVM use the single-context version so we
7598 * have to support it; just treat it the same as all-context.
7600 case VMX_VPID_EXTENT_ALL_CONTEXT:
7601 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7602 nested_vmx_succeed(vcpu);
7605 /* Trap individual address invalidation invvpid calls */
7610 skip_emulated_instruction(vcpu);
7614 static int handle_pml_full(struct kvm_vcpu *vcpu)
7616 unsigned long exit_qualification;
7618 trace_kvm_pml_full(vcpu->vcpu_id);
7620 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7623 * PML buffer FULL happened while executing iret from NMI,
7624 * "blocked by NMI" bit has to be set before next VM entry.
7626 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7627 cpu_has_virtual_nmis() &&
7628 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7629 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7630 GUEST_INTR_STATE_NMI);
7633 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7634 * here.., and there's no userspace involvement needed for PML.
7639 static int handle_pcommit(struct kvm_vcpu *vcpu)
7641 /* we never catch pcommit instruct for L1 guest. */
7646 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7648 kvm_lapic_expired_hv_timer(vcpu);
7653 * The exit handlers return 1 if the exit was handled fully and guest execution
7654 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7655 * to be done to userspace and return 0.
7657 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7658 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7659 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
7660 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
7661 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
7662 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
7663 [EXIT_REASON_CR_ACCESS] = handle_cr,
7664 [EXIT_REASON_DR_ACCESS] = handle_dr,
7665 [EXIT_REASON_CPUID] = handle_cpuid,
7666 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7667 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7668 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7669 [EXIT_REASON_HLT] = handle_halt,
7670 [EXIT_REASON_INVD] = handle_invd,
7671 [EXIT_REASON_INVLPG] = handle_invlpg,
7672 [EXIT_REASON_RDPMC] = handle_rdpmc,
7673 [EXIT_REASON_VMCALL] = handle_vmcall,
7674 [EXIT_REASON_VMCLEAR] = handle_vmclear,
7675 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
7676 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
7677 [EXIT_REASON_VMPTRST] = handle_vmptrst,
7678 [EXIT_REASON_VMREAD] = handle_vmread,
7679 [EXIT_REASON_VMRESUME] = handle_vmresume,
7680 [EXIT_REASON_VMWRITE] = handle_vmwrite,
7681 [EXIT_REASON_VMOFF] = handle_vmoff,
7682 [EXIT_REASON_VMON] = handle_vmon,
7683 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7684 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
7685 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
7686 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
7687 [EXIT_REASON_WBINVD] = handle_wbinvd,
7688 [EXIT_REASON_XSETBV] = handle_xsetbv,
7689 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
7690 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
7691 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7692 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
7693 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
7694 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7695 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
7696 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
7697 [EXIT_REASON_INVEPT] = handle_invept,
7698 [EXIT_REASON_INVVPID] = handle_invvpid,
7699 [EXIT_REASON_XSAVES] = handle_xsaves,
7700 [EXIT_REASON_XRSTORS] = handle_xrstors,
7701 [EXIT_REASON_PML_FULL] = handle_pml_full,
7702 [EXIT_REASON_PCOMMIT] = handle_pcommit,
7703 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
7706 static const int kvm_vmx_max_exit_handlers =
7707 ARRAY_SIZE(kvm_vmx_exit_handlers);
7709 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7710 struct vmcs12 *vmcs12)
7712 unsigned long exit_qualification;
7713 gpa_t bitmap, last_bitmap;
7718 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7719 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7721 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7723 port = exit_qualification >> 16;
7724 size = (exit_qualification & 7) + 1;
7726 last_bitmap = (gpa_t)-1;
7731 bitmap = vmcs12->io_bitmap_a;
7732 else if (port < 0x10000)
7733 bitmap = vmcs12->io_bitmap_b;
7736 bitmap += (port & 0x7fff) / 8;
7738 if (last_bitmap != bitmap)
7739 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7741 if (b & (1 << (port & 7)))
7746 last_bitmap = bitmap;
7753 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7754 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7755 * disinterest in the current event (read or write a specific MSR) by using an
7756 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7758 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7759 struct vmcs12 *vmcs12, u32 exit_reason)
7761 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7764 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7768 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7769 * for the four combinations of read/write and low/high MSR numbers.
7770 * First we need to figure out which of the four to use:
7772 bitmap = vmcs12->msr_bitmap;
7773 if (exit_reason == EXIT_REASON_MSR_WRITE)
7775 if (msr_index >= 0xc0000000) {
7776 msr_index -= 0xc0000000;
7780 /* Then read the msr_index'th bit from this bitmap: */
7781 if (msr_index < 1024*8) {
7783 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7785 return 1 & (b >> (msr_index & 7));
7787 return true; /* let L1 handle the wrong parameter */
7791 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7792 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7793 * intercept (via guest_host_mask etc.) the current event.
7795 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7796 struct vmcs12 *vmcs12)
7798 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7799 int cr = exit_qualification & 15;
7800 int reg = (exit_qualification >> 8) & 15;
7801 unsigned long val = kvm_register_readl(vcpu, reg);
7803 switch ((exit_qualification >> 4) & 3) {
7804 case 0: /* mov to cr */
7807 if (vmcs12->cr0_guest_host_mask &
7808 (val ^ vmcs12->cr0_read_shadow))
7812 if ((vmcs12->cr3_target_count >= 1 &&
7813 vmcs12->cr3_target_value0 == val) ||
7814 (vmcs12->cr3_target_count >= 2 &&
7815 vmcs12->cr3_target_value1 == val) ||
7816 (vmcs12->cr3_target_count >= 3 &&
7817 vmcs12->cr3_target_value2 == val) ||
7818 (vmcs12->cr3_target_count >= 4 &&
7819 vmcs12->cr3_target_value3 == val))
7821 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7825 if (vmcs12->cr4_guest_host_mask &
7826 (vmcs12->cr4_read_shadow ^ val))
7830 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7836 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7837 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7840 case 1: /* mov from cr */
7843 if (vmcs12->cpu_based_vm_exec_control &
7844 CPU_BASED_CR3_STORE_EXITING)
7848 if (vmcs12->cpu_based_vm_exec_control &
7849 CPU_BASED_CR8_STORE_EXITING)
7856 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7857 * cr0. Other attempted changes are ignored, with no exit.
7859 if (vmcs12->cr0_guest_host_mask & 0xe &
7860 (val ^ vmcs12->cr0_read_shadow))
7862 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7863 !(vmcs12->cr0_read_shadow & 0x1) &&
7872 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7873 * should handle it ourselves in L0 (and then continue L2). Only call this
7874 * when in is_guest_mode (L2).
7876 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7878 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7879 struct vcpu_vmx *vmx = to_vmx(vcpu);
7880 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7881 u32 exit_reason = vmx->exit_reason;
7883 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7884 vmcs_readl(EXIT_QUALIFICATION),
7885 vmx->idt_vectoring_info,
7887 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7890 if (vmx->nested.nested_run_pending)
7893 if (unlikely(vmx->fail)) {
7894 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7895 vmcs_read32(VM_INSTRUCTION_ERROR));
7899 switch (exit_reason) {
7900 case EXIT_REASON_EXCEPTION_NMI:
7901 if (!is_exception(intr_info))
7903 else if (is_page_fault(intr_info))
7905 else if (is_no_device(intr_info) &&
7906 !(vmcs12->guest_cr0 & X86_CR0_TS))
7908 else if (is_debug(intr_info) &&
7910 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
7912 else if (is_breakpoint(intr_info) &&
7913 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
7915 return vmcs12->exception_bitmap &
7916 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7917 case EXIT_REASON_EXTERNAL_INTERRUPT:
7919 case EXIT_REASON_TRIPLE_FAULT:
7921 case EXIT_REASON_PENDING_INTERRUPT:
7922 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7923 case EXIT_REASON_NMI_WINDOW:
7924 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7925 case EXIT_REASON_TASK_SWITCH:
7927 case EXIT_REASON_CPUID:
7928 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7931 case EXIT_REASON_HLT:
7932 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7933 case EXIT_REASON_INVD:
7935 case EXIT_REASON_INVLPG:
7936 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7937 case EXIT_REASON_RDPMC:
7938 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7939 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7940 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7941 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7942 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7943 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7944 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7945 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7946 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7948 * VMX instructions trap unconditionally. This allows L1 to
7949 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7952 case EXIT_REASON_CR_ACCESS:
7953 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7954 case EXIT_REASON_DR_ACCESS:
7955 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7956 case EXIT_REASON_IO_INSTRUCTION:
7957 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7958 case EXIT_REASON_MSR_READ:
7959 case EXIT_REASON_MSR_WRITE:
7960 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7961 case EXIT_REASON_INVALID_STATE:
7963 case EXIT_REASON_MWAIT_INSTRUCTION:
7964 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7965 case EXIT_REASON_MONITOR_TRAP_FLAG:
7966 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7967 case EXIT_REASON_MONITOR_INSTRUCTION:
7968 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7969 case EXIT_REASON_PAUSE_INSTRUCTION:
7970 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7971 nested_cpu_has2(vmcs12,
7972 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7973 case EXIT_REASON_MCE_DURING_VMENTRY:
7975 case EXIT_REASON_TPR_BELOW_THRESHOLD:
7976 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7977 case EXIT_REASON_APIC_ACCESS:
7978 return nested_cpu_has2(vmcs12,
7979 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7980 case EXIT_REASON_APIC_WRITE:
7981 case EXIT_REASON_EOI_INDUCED:
7982 /* apic_write and eoi_induced should exit unconditionally. */
7984 case EXIT_REASON_EPT_VIOLATION:
7986 * L0 always deals with the EPT violation. If nested EPT is
7987 * used, and the nested mmu code discovers that the address is
7988 * missing in the guest EPT table (EPT12), the EPT violation
7989 * will be injected with nested_ept_inject_page_fault()
7992 case EXIT_REASON_EPT_MISCONFIG:
7994 * L2 never uses directly L1's EPT, but rather L0's own EPT
7995 * table (shadow on EPT) or a merged EPT table that L0 built
7996 * (EPT on EPT). So any problems with the structure of the
7997 * table is L0's fault.
8000 case EXIT_REASON_WBINVD:
8001 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8002 case EXIT_REASON_XSETBV:
8004 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8006 * This should never happen, since it is not possible to
8007 * set XSS to a non-zero value---neither in L1 nor in L2.
8008 * If if it were, XSS would have to be checked against
8009 * the XSS exit bitmap in vmcs12.
8011 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8012 case EXIT_REASON_PCOMMIT:
8013 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
8019 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8021 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8022 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8025 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
8027 struct page *pml_pg;
8029 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
8033 vmx->pml_pg = pml_pg;
8035 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
8036 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8041 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8044 __free_page(vmx->pml_pg);
8049 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8051 struct vcpu_vmx *vmx = to_vmx(vcpu);
8055 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8057 /* Do nothing if PML buffer is empty */
8058 if (pml_idx == (PML_ENTITY_NUM - 1))
8061 /* PML index always points to next available PML buffer entity */
8062 if (pml_idx >= PML_ENTITY_NUM)
8067 pml_buf = page_address(vmx->pml_pg);
8068 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8071 gpa = pml_buf[pml_idx];
8072 WARN_ON(gpa & (PAGE_SIZE - 1));
8073 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8076 /* reset PML index */
8077 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8081 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8082 * Called before reporting dirty_bitmap to userspace.
8084 static void kvm_flush_pml_buffers(struct kvm *kvm)
8087 struct kvm_vcpu *vcpu;
8089 * We only need to kick vcpu out of guest mode here, as PML buffer
8090 * is flushed at beginning of all VMEXITs, and it's obvious that only
8091 * vcpus running in guest are possible to have unflushed GPAs in PML
8094 kvm_for_each_vcpu(i, vcpu, kvm)
8095 kvm_vcpu_kick(vcpu);
8098 static void vmx_dump_sel(char *name, uint32_t sel)
8100 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8101 name, vmcs_read32(sel),
8102 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8103 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8104 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8107 static void vmx_dump_dtsel(char *name, uint32_t limit)
8109 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8110 name, vmcs_read32(limit),
8111 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8114 static void dump_vmcs(void)
8116 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8117 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8118 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8119 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8120 u32 secondary_exec_control = 0;
8121 unsigned long cr4 = vmcs_readl(GUEST_CR4);
8122 u64 efer = vmcs_read64(GUEST_IA32_EFER);
8125 if (cpu_has_secondary_exec_ctrls())
8126 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8128 pr_err("*** Guest State ***\n");
8129 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8130 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8131 vmcs_readl(CR0_GUEST_HOST_MASK));
8132 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8133 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8134 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8135 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8136 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8138 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8139 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8140 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8141 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8143 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8144 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8145 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8146 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8147 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8148 vmcs_readl(GUEST_SYSENTER_ESP),
8149 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8150 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8151 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8152 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8153 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8154 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8155 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8156 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8157 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8158 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8159 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8160 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8161 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8162 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8163 efer, vmcs_read64(GUEST_IA32_PAT));
8164 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8165 vmcs_read64(GUEST_IA32_DEBUGCTL),
8166 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8167 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8168 pr_err("PerfGlobCtl = 0x%016llx\n",
8169 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8170 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8171 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8172 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8173 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8174 vmcs_read32(GUEST_ACTIVITY_STATE));
8175 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8176 pr_err("InterruptStatus = %04x\n",
8177 vmcs_read16(GUEST_INTR_STATUS));
8179 pr_err("*** Host State ***\n");
8180 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8181 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8182 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8183 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8184 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8185 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8186 vmcs_read16(HOST_TR_SELECTOR));
8187 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8188 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8189 vmcs_readl(HOST_TR_BASE));
8190 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8191 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8192 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8193 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8194 vmcs_readl(HOST_CR4));
8195 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8196 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8197 vmcs_read32(HOST_IA32_SYSENTER_CS),
8198 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8199 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8200 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8201 vmcs_read64(HOST_IA32_EFER),
8202 vmcs_read64(HOST_IA32_PAT));
8203 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8204 pr_err("PerfGlobCtl = 0x%016llx\n",
8205 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8207 pr_err("*** Control State ***\n");
8208 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8209 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8210 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8211 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8212 vmcs_read32(EXCEPTION_BITMAP),
8213 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8214 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8215 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8216 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8217 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8218 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8219 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8220 vmcs_read32(VM_EXIT_INTR_INFO),
8221 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8222 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8223 pr_err(" reason=%08x qualification=%016lx\n",
8224 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8225 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8226 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8227 vmcs_read32(IDT_VECTORING_ERROR_CODE));
8228 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8229 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8230 pr_err("TSC Multiplier = 0x%016llx\n",
8231 vmcs_read64(TSC_MULTIPLIER));
8232 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8233 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8234 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8235 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8236 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8237 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8238 n = vmcs_read32(CR3_TARGET_COUNT);
8239 for (i = 0; i + 1 < n; i += 4)
8240 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8241 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8242 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8244 pr_err("CR3 target%u=%016lx\n",
8245 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8246 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8247 pr_err("PLE Gap=%08x Window=%08x\n",
8248 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8249 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8250 pr_err("Virtual processor ID = 0x%04x\n",
8251 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8255 * The guest has exited. See if we can fix it or if we need userspace
8258 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8260 struct vcpu_vmx *vmx = to_vmx(vcpu);
8261 u32 exit_reason = vmx->exit_reason;
8262 u32 vectoring_info = vmx->idt_vectoring_info;
8264 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8267 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8268 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8269 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8270 * mode as if vcpus is in root mode, the PML buffer must has been
8274 vmx_flush_pml_buffer(vcpu);
8276 /* If guest state is invalid, start emulating */
8277 if (vmx->emulation_required)
8278 return handle_invalid_guest_state(vcpu);
8280 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8281 nested_vmx_vmexit(vcpu, exit_reason,
8282 vmcs_read32(VM_EXIT_INTR_INFO),
8283 vmcs_readl(EXIT_QUALIFICATION));
8287 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8289 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8290 vcpu->run->fail_entry.hardware_entry_failure_reason
8295 if (unlikely(vmx->fail)) {
8296 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8297 vcpu->run->fail_entry.hardware_entry_failure_reason
8298 = vmcs_read32(VM_INSTRUCTION_ERROR);
8304 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8305 * delivery event since it indicates guest is accessing MMIO.
8306 * The vm-exit can be triggered again after return to guest that
8307 * will cause infinite loop.
8309 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8310 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8311 exit_reason != EXIT_REASON_EPT_VIOLATION &&
8312 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8313 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8314 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8315 vcpu->run->internal.ndata = 2;
8316 vcpu->run->internal.data[0] = vectoring_info;
8317 vcpu->run->internal.data[1] = exit_reason;
8321 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8322 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8323 get_vmcs12(vcpu))))) {
8324 if (vmx_interrupt_allowed(vcpu)) {
8325 vmx->soft_vnmi_blocked = 0;
8326 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8327 vcpu->arch.nmi_pending) {
8329 * This CPU don't support us in finding the end of an
8330 * NMI-blocked window if the guest runs with IRQs
8331 * disabled. So we pull the trigger after 1 s of
8332 * futile waiting, but inform the user about this.
8334 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8335 "state on VCPU %d after 1 s timeout\n",
8336 __func__, vcpu->vcpu_id);
8337 vmx->soft_vnmi_blocked = 0;
8341 if (exit_reason < kvm_vmx_max_exit_handlers
8342 && kvm_vmx_exit_handlers[exit_reason])
8343 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8345 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8346 kvm_queue_exception(vcpu, UD_VECTOR);
8351 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8353 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8355 if (is_guest_mode(vcpu) &&
8356 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8359 if (irr == -1 || tpr < irr) {
8360 vmcs_write32(TPR_THRESHOLD, 0);
8364 vmcs_write32(TPR_THRESHOLD, irr);
8367 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8369 u32 sec_exec_control;
8372 * There is not point to enable virtualize x2apic without enable
8375 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8376 !kvm_vcpu_apicv_active(vcpu))
8379 if (!cpu_need_tpr_shadow(vcpu))
8382 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8385 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8386 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8388 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8389 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8391 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8393 vmx_set_msr_bitmap(vcpu);
8396 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8398 struct vcpu_vmx *vmx = to_vmx(vcpu);
8401 * Currently we do not handle the nested case where L2 has an
8402 * APIC access page of its own; that page is still pinned.
8403 * Hence, we skip the case where the VCPU is in guest mode _and_
8404 * L1 prepared an APIC access page for L2.
8406 * For the case where L1 and L2 share the same APIC access page
8407 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8408 * in the vmcs12), this function will only update either the vmcs01
8409 * or the vmcs02. If the former, the vmcs02 will be updated by
8410 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8411 * the next L2->L1 exit.
8413 if (!is_guest_mode(vcpu) ||
8414 !nested_cpu_has2(vmx->nested.current_vmcs12,
8415 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8416 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8419 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8427 status = vmcs_read16(GUEST_INTR_STATUS);
8429 if (max_isr != old) {
8431 status |= max_isr << 8;
8432 vmcs_write16(GUEST_INTR_STATUS, status);
8436 static void vmx_set_rvi(int vector)
8444 status = vmcs_read16(GUEST_INTR_STATUS);
8445 old = (u8)status & 0xff;
8446 if ((u8)vector != old) {
8448 status |= (u8)vector;
8449 vmcs_write16(GUEST_INTR_STATUS, status);
8453 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8455 if (!is_guest_mode(vcpu)) {
8456 vmx_set_rvi(max_irr);
8464 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8467 if (nested_exit_on_intr(vcpu))
8471 * Else, fall back to pre-APICv interrupt injection since L2
8472 * is run without virtual interrupt delivery.
8474 if (!kvm_event_needs_reinjection(vcpu) &&
8475 vmx_interrupt_allowed(vcpu)) {
8476 kvm_queue_interrupt(vcpu, max_irr, false);
8477 vmx_inject_irq(vcpu);
8481 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8483 if (!kvm_vcpu_apicv_active(vcpu))
8486 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8487 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8488 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8489 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8492 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8496 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8497 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8500 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8501 exit_intr_info = vmx->exit_intr_info;
8503 /* Handle machine checks before interrupts are enabled */
8504 if (is_machine_check(exit_intr_info))
8505 kvm_machine_check();
8507 /* We need to handle NMIs before interrupts are enabled */
8508 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8509 (exit_intr_info & INTR_INFO_VALID_MASK)) {
8510 kvm_before_handle_nmi(&vmx->vcpu);
8512 kvm_after_handle_nmi(&vmx->vcpu);
8516 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8518 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8519 register void *__sp asm(_ASM_SP);
8522 * If external interrupt exists, IF bit is set in rflags/eflags on the
8523 * interrupt stack frame, and interrupt will be enabled on a return
8524 * from interrupt handler.
8526 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8527 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8528 unsigned int vector;
8529 unsigned long entry;
8531 struct vcpu_vmx *vmx = to_vmx(vcpu);
8532 #ifdef CONFIG_X86_64
8536 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8537 desc = (gate_desc *)vmx->host_idt_base + vector;
8538 entry = gate_offset(*desc);
8540 #ifdef CONFIG_X86_64
8541 "mov %%" _ASM_SP ", %[sp]\n\t"
8542 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8547 "orl $0x200, (%%" _ASM_SP ")\n\t"
8548 __ASM_SIZE(push) " $%c[cs]\n\t"
8549 "call *%[entry]\n\t"
8551 #ifdef CONFIG_X86_64
8557 [ss]"i"(__KERNEL_DS),
8558 [cs]"i"(__KERNEL_CS)
8564 static bool vmx_has_high_real_mode_segbase(void)
8566 return enable_unrestricted_guest || emulate_invalid_guest_state;
8569 static bool vmx_mpx_supported(void)
8571 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8572 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8575 static bool vmx_xsaves_supported(void)
8577 return vmcs_config.cpu_based_2nd_exec_ctrl &
8578 SECONDARY_EXEC_XSAVES;
8581 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8586 bool idtv_info_valid;
8588 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8590 if (cpu_has_virtual_nmis()) {
8591 if (vmx->nmi_known_unmasked)
8594 * Can't use vmx->exit_intr_info since we're not sure what
8595 * the exit reason is.
8597 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8598 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8599 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8601 * SDM 3: 27.7.1.2 (September 2008)
8602 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8603 * a guest IRET fault.
8604 * SDM 3: 23.2.2 (September 2008)
8605 * Bit 12 is undefined in any of the following cases:
8606 * If the VM exit sets the valid bit in the IDT-vectoring
8607 * information field.
8608 * If the VM exit is due to a double fault.
8610 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8611 vector != DF_VECTOR && !idtv_info_valid)
8612 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8613 GUEST_INTR_STATE_NMI);
8615 vmx->nmi_known_unmasked =
8616 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8617 & GUEST_INTR_STATE_NMI);
8618 } else if (unlikely(vmx->soft_vnmi_blocked))
8619 vmx->vnmi_blocked_time +=
8620 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8623 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8624 u32 idt_vectoring_info,
8625 int instr_len_field,
8626 int error_code_field)
8630 bool idtv_info_valid;
8632 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8634 vcpu->arch.nmi_injected = false;
8635 kvm_clear_exception_queue(vcpu);
8636 kvm_clear_interrupt_queue(vcpu);
8638 if (!idtv_info_valid)
8641 kvm_make_request(KVM_REQ_EVENT, vcpu);
8643 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8644 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8647 case INTR_TYPE_NMI_INTR:
8648 vcpu->arch.nmi_injected = true;
8650 * SDM 3: 27.7.1.2 (September 2008)
8651 * Clear bit "block by NMI" before VM entry if a NMI
8654 vmx_set_nmi_mask(vcpu, false);
8656 case INTR_TYPE_SOFT_EXCEPTION:
8657 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8659 case INTR_TYPE_HARD_EXCEPTION:
8660 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8661 u32 err = vmcs_read32(error_code_field);
8662 kvm_requeue_exception_e(vcpu, vector, err);
8664 kvm_requeue_exception(vcpu, vector);
8666 case INTR_TYPE_SOFT_INTR:
8667 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8669 case INTR_TYPE_EXT_INTR:
8670 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8677 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8679 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8680 VM_EXIT_INSTRUCTION_LEN,
8681 IDT_VECTORING_ERROR_CODE);
8684 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8686 __vmx_complete_interrupts(vcpu,
8687 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8688 VM_ENTRY_INSTRUCTION_LEN,
8689 VM_ENTRY_EXCEPTION_ERROR_CODE);
8691 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8694 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8697 struct perf_guest_switch_msr *msrs;
8699 msrs = perf_guest_get_msrs(&nr_msrs);
8704 for (i = 0; i < nr_msrs; i++)
8705 if (msrs[i].host == msrs[i].guest)
8706 clear_atomic_switch_msr(vmx, msrs[i].msr);
8708 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8712 void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8714 struct vcpu_vmx *vmx = to_vmx(vcpu);
8718 if (vmx->hv_deadline_tsc == -1)
8722 if (vmx->hv_deadline_tsc > tscl)
8723 /* sure to be 32 bit only because checked on set_hv_timer */
8724 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8725 cpu_preemption_timer_multi);
8729 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8732 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8734 struct vcpu_vmx *vmx = to_vmx(vcpu);
8735 unsigned long debugctlmsr, cr4;
8737 /* Record the guest's net vcpu time for enforced NMI injections. */
8738 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8739 vmx->entry_time = ktime_get();
8741 /* Don't enter VMX if guest state is invalid, let the exit handler
8742 start emulation until we arrive back to a valid state */
8743 if (vmx->emulation_required)
8746 if (vmx->ple_window_dirty) {
8747 vmx->ple_window_dirty = false;
8748 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8751 if (vmx->nested.sync_shadow_vmcs) {
8752 copy_vmcs12_to_shadow(vmx);
8753 vmx->nested.sync_shadow_vmcs = false;
8756 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8757 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8758 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8759 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8761 cr4 = cr4_read_shadow();
8762 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8763 vmcs_writel(HOST_CR4, cr4);
8764 vmx->host_state.vmcs_host_cr4 = cr4;
8767 /* When single-stepping over STI and MOV SS, we must clear the
8768 * corresponding interruptibility bits in the guest state. Otherwise
8769 * vmentry fails as it then expects bit 14 (BS) in pending debug
8770 * exceptions being set, but that's not correct for the guest debugging
8772 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8773 vmx_set_interrupt_shadow(vcpu, 0);
8775 if (vmx->guest_pkru_valid)
8776 __write_pkru(vmx->guest_pkru);
8778 atomic_switch_perf_msrs(vmx);
8779 debugctlmsr = get_debugctlmsr();
8781 vmx_arm_hv_timer(vcpu);
8783 vmx->__launched = vmx->loaded_vmcs->launched;
8785 /* Store host registers */
8786 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8787 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8788 "push %%" _ASM_CX " \n\t"
8789 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8791 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8792 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8794 /* Reload cr2 if changed */
8795 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8796 "mov %%cr2, %%" _ASM_DX " \n\t"
8797 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8799 "mov %%" _ASM_AX", %%cr2 \n\t"
8801 /* Check if vmlaunch of vmresume is needed */
8802 "cmpl $0, %c[launched](%0) \n\t"
8803 /* Load guest registers. Don't clobber flags. */
8804 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8805 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8806 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8807 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8808 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8809 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8810 #ifdef CONFIG_X86_64
8811 "mov %c[r8](%0), %%r8 \n\t"
8812 "mov %c[r9](%0), %%r9 \n\t"
8813 "mov %c[r10](%0), %%r10 \n\t"
8814 "mov %c[r11](%0), %%r11 \n\t"
8815 "mov %c[r12](%0), %%r12 \n\t"
8816 "mov %c[r13](%0), %%r13 \n\t"
8817 "mov %c[r14](%0), %%r14 \n\t"
8818 "mov %c[r15](%0), %%r15 \n\t"
8820 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8822 /* Enter guest mode */
8824 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8826 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8828 /* Save guest registers, load host registers, keep flags */
8829 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8831 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8832 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8833 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8834 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8835 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8836 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8837 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8838 #ifdef CONFIG_X86_64
8839 "mov %%r8, %c[r8](%0) \n\t"
8840 "mov %%r9, %c[r9](%0) \n\t"
8841 "mov %%r10, %c[r10](%0) \n\t"
8842 "mov %%r11, %c[r11](%0) \n\t"
8843 "mov %%r12, %c[r12](%0) \n\t"
8844 "mov %%r13, %c[r13](%0) \n\t"
8845 "mov %%r14, %c[r14](%0) \n\t"
8846 "mov %%r15, %c[r15](%0) \n\t"
8848 "mov %%cr2, %%" _ASM_AX " \n\t"
8849 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8851 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
8852 "setbe %c[fail](%0) \n\t"
8853 ".pushsection .rodata \n\t"
8854 ".global vmx_return \n\t"
8855 "vmx_return: " _ASM_PTR " 2b \n\t"
8857 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8858 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8859 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8860 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8861 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8862 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8863 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8864 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8865 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8866 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8867 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8868 #ifdef CONFIG_X86_64
8869 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8870 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8871 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8872 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8873 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8874 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8875 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8876 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8878 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8879 [wordsize]"i"(sizeof(ulong))
8881 #ifdef CONFIG_X86_64
8882 , "rax", "rbx", "rdi", "rsi"
8883 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8885 , "eax", "ebx", "edi", "esi"
8889 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8891 update_debugctlmsr(debugctlmsr);
8893 #ifndef CONFIG_X86_64
8895 * The sysexit path does not restore ds/es, so we must set them to
8896 * a reasonable value ourselves.
8898 * We can't defer this to vmx_load_host_state() since that function
8899 * may be executed in interrupt context, which saves and restore segments
8900 * around it, nullifying its effect.
8902 loadsegment(ds, __USER_DS);
8903 loadsegment(es, __USER_DS);
8906 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8907 | (1 << VCPU_EXREG_RFLAGS)
8908 | (1 << VCPU_EXREG_PDPTR)
8909 | (1 << VCPU_EXREG_SEGMENTS)
8910 | (1 << VCPU_EXREG_CR3));
8911 vcpu->arch.regs_dirty = 0;
8913 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8915 vmx->loaded_vmcs->launched = 1;
8917 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8920 * eager fpu is enabled if PKEY is supported and CR4 is switched
8921 * back on host, so it is safe to read guest PKRU from current
8924 if (boot_cpu_has(X86_FEATURE_OSPKE)) {
8925 vmx->guest_pkru = __read_pkru();
8926 if (vmx->guest_pkru != vmx->host_pkru) {
8927 vmx->guest_pkru_valid = true;
8928 __write_pkru(vmx->host_pkru);
8930 vmx->guest_pkru_valid = false;
8934 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8935 * we did not inject a still-pending event to L1 now because of
8936 * nested_run_pending, we need to re-enable this bit.
8938 if (vmx->nested.nested_run_pending)
8939 kvm_make_request(KVM_REQ_EVENT, vcpu);
8941 vmx->nested.nested_run_pending = 0;
8943 vmx_complete_atomic_exit(vmx);
8944 vmx_recover_nmi_blocking(vmx);
8945 vmx_complete_interrupts(vmx);
8948 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8950 struct vcpu_vmx *vmx = to_vmx(vcpu);
8953 if (vmx->loaded_vmcs == &vmx->vmcs01)
8957 vmx->loaded_vmcs = &vmx->vmcs01;
8959 vmx_vcpu_load(vcpu, cpu);
8964 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8966 struct vcpu_vmx *vmx = to_vmx(vcpu);
8969 vmx_destroy_pml_buffer(vmx);
8970 free_vpid(vmx->vpid);
8971 leave_guest_mode(vcpu);
8972 vmx_load_vmcs01(vcpu);
8974 free_loaded_vmcs(vmx->loaded_vmcs);
8975 kfree(vmx->guest_msrs);
8976 kvm_vcpu_uninit(vcpu);
8977 kmem_cache_free(kvm_vcpu_cache, vmx);
8980 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8983 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8987 return ERR_PTR(-ENOMEM);
8989 vmx->vpid = allocate_vpid();
8991 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8995 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8996 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9000 if (!vmx->guest_msrs) {
9004 vmx->loaded_vmcs = &vmx->vmcs01;
9005 vmx->loaded_vmcs->vmcs = alloc_vmcs();
9006 if (!vmx->loaded_vmcs->vmcs)
9009 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9010 loaded_vmcs_init(vmx->loaded_vmcs);
9015 vmx_vcpu_load(&vmx->vcpu, cpu);
9016 vmx->vcpu.cpu = cpu;
9017 err = vmx_vcpu_setup(vmx);
9018 vmx_vcpu_put(&vmx->vcpu);
9022 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9023 err = alloc_apic_access_page(kvm);
9029 if (!kvm->arch.ept_identity_map_addr)
9030 kvm->arch.ept_identity_map_addr =
9031 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9032 err = init_rmode_identity_map(kvm);
9038 nested_vmx_setup_ctls_msrs(vmx);
9039 vmx->nested.vpid02 = allocate_vpid();
9042 vmx->nested.posted_intr_nv = -1;
9043 vmx->nested.current_vmptr = -1ull;
9044 vmx->nested.current_vmcs12 = NULL;
9047 * If PML is turned on, failure on enabling PML just results in failure
9048 * of creating the vcpu, therefore we can simplify PML logic (by
9049 * avoiding dealing with cases, such as enabling PML partially on vcpus
9050 * for the guest, etc.
9053 err = vmx_create_pml_buffer(vmx);
9061 free_vpid(vmx->nested.vpid02);
9062 free_loaded_vmcs(vmx->loaded_vmcs);
9064 kfree(vmx->guest_msrs);
9066 kvm_vcpu_uninit(&vmx->vcpu);
9068 free_vpid(vmx->vpid);
9069 kmem_cache_free(kvm_vcpu_cache, vmx);
9070 return ERR_PTR(err);
9073 static void __init vmx_check_processor_compat(void *rtn)
9075 struct vmcs_config vmcs_conf;
9078 if (setup_vmcs_config(&vmcs_conf) < 0)
9080 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9081 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9082 smp_processor_id());
9087 static int get_ept_level(void)
9089 return VMX_EPT_DEFAULT_GAW + 1;
9092 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9097 /* For VT-d and EPT combination
9098 * 1. MMIO: always map as UC
9100 * a. VT-d without snooping control feature: can't guarantee the
9101 * result, try to trust guest.
9102 * b. VT-d with snooping control feature: snooping control feature of
9103 * VT-d engine can guarantee the cache correctness. Just set it
9104 * to WB to keep consistent with host. So the same as item 3.
9105 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9106 * consistent with host MTRR
9109 cache = MTRR_TYPE_UNCACHABLE;
9113 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9114 ipat = VMX_EPT_IPAT_BIT;
9115 cache = MTRR_TYPE_WRBACK;
9119 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9120 ipat = VMX_EPT_IPAT_BIT;
9121 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9122 cache = MTRR_TYPE_WRBACK;
9124 cache = MTRR_TYPE_UNCACHABLE;
9128 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9131 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9134 static int vmx_get_lpage_level(void)
9136 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9137 return PT_DIRECTORY_LEVEL;
9139 /* For shadow and EPT supported 1GB page */
9140 return PT_PDPE_LEVEL;
9143 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9146 * These bits in the secondary execution controls field
9147 * are dynamic, the others are mostly based on the hypervisor
9148 * architecture and the guest's CPUID. Do not touch the
9152 SECONDARY_EXEC_SHADOW_VMCS |
9153 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9154 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9156 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9158 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9159 (new_ctl & ~mask) | (cur_ctl & mask));
9162 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9164 struct kvm_cpuid_entry2 *best;
9165 struct vcpu_vmx *vmx = to_vmx(vcpu);
9166 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9168 if (vmx_rdtscp_supported()) {
9169 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9170 if (!rdtscp_enabled)
9171 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9175 vmx->nested.nested_vmx_secondary_ctls_high |=
9176 SECONDARY_EXEC_RDTSCP;
9178 vmx->nested.nested_vmx_secondary_ctls_high &=
9179 ~SECONDARY_EXEC_RDTSCP;
9183 /* Exposing INVPCID only when PCID is exposed */
9184 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9185 if (vmx_invpcid_supported() &&
9186 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9187 !guest_cpuid_has_pcid(vcpu))) {
9188 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9191 best->ebx &= ~bit(X86_FEATURE_INVPCID);
9194 if (cpu_has_secondary_exec_ctrls())
9195 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9197 if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
9198 if (guest_cpuid_has_pcommit(vcpu))
9199 vmx->nested.nested_vmx_secondary_ctls_high |=
9200 SECONDARY_EXEC_PCOMMIT;
9202 vmx->nested.nested_vmx_secondary_ctls_high &=
9203 ~SECONDARY_EXEC_PCOMMIT;
9207 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9209 if (func == 1 && nested)
9210 entry->ecx |= bit(X86_FEATURE_VMX);
9213 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9214 struct x86_exception *fault)
9216 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9219 if (fault->error_code & PFERR_RSVD_MASK)
9220 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9222 exit_reason = EXIT_REASON_EPT_VIOLATION;
9223 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9224 vmcs12->guest_physical_address = fault->address;
9227 /* Callbacks for nested_ept_init_mmu_context: */
9229 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9231 /* return the page table to be shadowed - in our case, EPT12 */
9232 return get_vmcs12(vcpu)->ept_pointer;
9235 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9237 WARN_ON(mmu_is_nested(vcpu));
9238 kvm_init_shadow_ept_mmu(vcpu,
9239 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9240 VMX_EPT_EXECUTE_ONLY_BIT);
9241 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9242 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9243 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9245 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
9248 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9250 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9253 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9256 bool inequality, bit;
9258 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9260 (error_code & vmcs12->page_fault_error_code_mask) !=
9261 vmcs12->page_fault_error_code_match;
9262 return inequality ^ bit;
9265 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9266 struct x86_exception *fault)
9268 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9270 WARN_ON(!is_guest_mode(vcpu));
9272 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9273 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9274 vmcs_read32(VM_EXIT_INTR_INFO),
9275 vmcs_readl(EXIT_QUALIFICATION));
9277 kvm_inject_page_fault(vcpu, fault);
9280 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9281 struct vmcs12 *vmcs12)
9283 struct vcpu_vmx *vmx = to_vmx(vcpu);
9284 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9286 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9287 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9288 vmcs12->apic_access_addr >> maxphyaddr)
9292 * Translate L1 physical address to host physical
9293 * address for vmcs02. Keep the page pinned, so this
9294 * physical address remains valid. We keep a reference
9295 * to it so we can release it later.
9297 if (vmx->nested.apic_access_page) /* shouldn't happen */
9298 nested_release_page(vmx->nested.apic_access_page);
9299 vmx->nested.apic_access_page =
9300 nested_get_page(vcpu, vmcs12->apic_access_addr);
9303 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9304 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9305 vmcs12->virtual_apic_page_addr >> maxphyaddr)
9308 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9309 nested_release_page(vmx->nested.virtual_apic_page);
9310 vmx->nested.virtual_apic_page =
9311 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9314 * Failing the vm entry is _not_ what the processor does
9315 * but it's basically the only possibility we have.
9316 * We could still enter the guest if CR8 load exits are
9317 * enabled, CR8 store exits are enabled, and virtualize APIC
9318 * access is disabled; in this case the processor would never
9319 * use the TPR shadow and we could simply clear the bit from
9320 * the execution control. But such a configuration is useless,
9321 * so let's keep the code simple.
9323 if (!vmx->nested.virtual_apic_page)
9327 if (nested_cpu_has_posted_intr(vmcs12)) {
9328 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9329 vmcs12->posted_intr_desc_addr >> maxphyaddr)
9332 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9333 kunmap(vmx->nested.pi_desc_page);
9334 nested_release_page(vmx->nested.pi_desc_page);
9336 vmx->nested.pi_desc_page =
9337 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9338 if (!vmx->nested.pi_desc_page)
9341 vmx->nested.pi_desc =
9342 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9343 if (!vmx->nested.pi_desc) {
9344 nested_release_page_clean(vmx->nested.pi_desc_page);
9347 vmx->nested.pi_desc =
9348 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9349 (unsigned long)(vmcs12->posted_intr_desc_addr &
9356 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9358 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9359 struct vcpu_vmx *vmx = to_vmx(vcpu);
9361 if (vcpu->arch.virtual_tsc_khz == 0)
9364 /* Make sure short timeouts reliably trigger an immediate vmexit.
9365 * hrtimer_start does not guarantee this. */
9366 if (preemption_timeout <= 1) {
9367 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9371 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9372 preemption_timeout *= 1000000;
9373 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9374 hrtimer_start(&vmx->nested.preemption_timer,
9375 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9378 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9379 struct vmcs12 *vmcs12)
9384 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9387 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9391 maxphyaddr = cpuid_maxphyaddr(vcpu);
9393 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9394 ((addr + PAGE_SIZE) >> maxphyaddr))
9401 * Merge L0's and L1's MSR bitmap, return false to indicate that
9402 * we do not use the hardware.
9404 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9405 struct vmcs12 *vmcs12)
9409 unsigned long *msr_bitmap;
9411 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9414 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9419 msr_bitmap = (unsigned long *)kmap(page);
9421 nested_release_page_clean(page);
9426 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9427 if (nested_cpu_has_apic_reg_virt(vmcs12))
9428 for (msr = 0x800; msr <= 0x8ff; msr++)
9429 nested_vmx_disable_intercept_for_msr(
9431 vmx_msr_bitmap_nested,
9433 /* TPR is allowed */
9434 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9435 vmx_msr_bitmap_nested,
9436 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9437 MSR_TYPE_R | MSR_TYPE_W);
9438 if (nested_cpu_has_vid(vmcs12)) {
9439 /* EOI and self-IPI are allowed */
9440 nested_vmx_disable_intercept_for_msr(
9442 vmx_msr_bitmap_nested,
9443 APIC_BASE_MSR + (APIC_EOI >> 4),
9445 nested_vmx_disable_intercept_for_msr(
9447 vmx_msr_bitmap_nested,
9448 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9453 * Enable reading intercept of all the x2apic
9454 * MSRs. We should not rely on vmcs12 to do any
9455 * optimizations here, it may have been modified
9458 for (msr = 0x800; msr <= 0x8ff; msr++)
9459 __vmx_enable_intercept_for_msr(
9460 vmx_msr_bitmap_nested,
9464 __vmx_enable_intercept_for_msr(
9465 vmx_msr_bitmap_nested,
9466 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9468 __vmx_enable_intercept_for_msr(
9469 vmx_msr_bitmap_nested,
9470 APIC_BASE_MSR + (APIC_EOI >> 4),
9472 __vmx_enable_intercept_for_msr(
9473 vmx_msr_bitmap_nested,
9474 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9478 nested_release_page_clean(page);
9483 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9484 struct vmcs12 *vmcs12)
9486 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9487 !nested_cpu_has_apic_reg_virt(vmcs12) &&
9488 !nested_cpu_has_vid(vmcs12) &&
9489 !nested_cpu_has_posted_intr(vmcs12))
9493 * If virtualize x2apic mode is enabled,
9494 * virtualize apic access must be disabled.
9496 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9497 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9501 * If virtual interrupt delivery is enabled,
9502 * we must exit on external interrupts.
9504 if (nested_cpu_has_vid(vmcs12) &&
9505 !nested_exit_on_intr(vcpu))
9509 * bits 15:8 should be zero in posted_intr_nv,
9510 * the descriptor address has been already checked
9511 * in nested_get_vmcs12_pages.
9513 if (nested_cpu_has_posted_intr(vmcs12) &&
9514 (!nested_cpu_has_vid(vmcs12) ||
9515 !nested_exit_intr_ack_set(vcpu) ||
9516 vmcs12->posted_intr_nv & 0xff00))
9519 /* tpr shadow is needed by all apicv features. */
9520 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9526 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9527 unsigned long count_field,
9528 unsigned long addr_field)
9533 if (vmcs12_read_any(vcpu, count_field, &count) ||
9534 vmcs12_read_any(vcpu, addr_field, &addr)) {
9540 maxphyaddr = cpuid_maxphyaddr(vcpu);
9541 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9542 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9543 pr_warn_ratelimited(
9544 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9545 addr_field, maxphyaddr, count, addr);
9551 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9552 struct vmcs12 *vmcs12)
9554 if (vmcs12->vm_exit_msr_load_count == 0 &&
9555 vmcs12->vm_exit_msr_store_count == 0 &&
9556 vmcs12->vm_entry_msr_load_count == 0)
9557 return 0; /* Fast path */
9558 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9559 VM_EXIT_MSR_LOAD_ADDR) ||
9560 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9561 VM_EXIT_MSR_STORE_ADDR) ||
9562 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9563 VM_ENTRY_MSR_LOAD_ADDR))
9568 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9569 struct vmx_msr_entry *e)
9571 /* x2APIC MSR accesses are not allowed */
9572 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9574 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9575 e->index == MSR_IA32_UCODE_REV)
9577 if (e->reserved != 0)
9582 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9583 struct vmx_msr_entry *e)
9585 if (e->index == MSR_FS_BASE ||
9586 e->index == MSR_GS_BASE ||
9587 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9588 nested_vmx_msr_check_common(vcpu, e))
9593 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9594 struct vmx_msr_entry *e)
9596 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9597 nested_vmx_msr_check_common(vcpu, e))
9603 * Load guest's/host's msr at nested entry/exit.
9604 * return 0 for success, entry index for failure.
9606 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9609 struct vmx_msr_entry e;
9610 struct msr_data msr;
9612 msr.host_initiated = false;
9613 for (i = 0; i < count; i++) {
9614 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9616 pr_warn_ratelimited(
9617 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9618 __func__, i, gpa + i * sizeof(e));
9621 if (nested_vmx_load_msr_check(vcpu, &e)) {
9622 pr_warn_ratelimited(
9623 "%s check failed (%u, 0x%x, 0x%x)\n",
9624 __func__, i, e.index, e.reserved);
9627 msr.index = e.index;
9629 if (kvm_set_msr(vcpu, &msr)) {
9630 pr_warn_ratelimited(
9631 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9632 __func__, i, e.index, e.value);
9641 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9644 struct vmx_msr_entry e;
9646 for (i = 0; i < count; i++) {
9647 struct msr_data msr_info;
9648 if (kvm_vcpu_read_guest(vcpu,
9649 gpa + i * sizeof(e),
9650 &e, 2 * sizeof(u32))) {
9651 pr_warn_ratelimited(
9652 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9653 __func__, i, gpa + i * sizeof(e));
9656 if (nested_vmx_store_msr_check(vcpu, &e)) {
9657 pr_warn_ratelimited(
9658 "%s check failed (%u, 0x%x, 0x%x)\n",
9659 __func__, i, e.index, e.reserved);
9662 msr_info.host_initiated = false;
9663 msr_info.index = e.index;
9664 if (kvm_get_msr(vcpu, &msr_info)) {
9665 pr_warn_ratelimited(
9666 "%s cannot read MSR (%u, 0x%x)\n",
9667 __func__, i, e.index);
9670 if (kvm_vcpu_write_guest(vcpu,
9671 gpa + i * sizeof(e) +
9672 offsetof(struct vmx_msr_entry, value),
9673 &msr_info.data, sizeof(msr_info.data))) {
9674 pr_warn_ratelimited(
9675 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9676 __func__, i, e.index, msr_info.data);
9684 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9685 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9686 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9687 * guest in a way that will both be appropriate to L1's requests, and our
9688 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9689 * function also has additional necessary side-effects, like setting various
9690 * vcpu->arch fields.
9692 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9694 struct vcpu_vmx *vmx = to_vmx(vcpu);
9697 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9698 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9699 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9700 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9701 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9702 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9703 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9704 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9705 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9706 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9707 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9708 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9709 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9710 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9711 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9712 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9713 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9714 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9715 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9716 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9717 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9718 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9719 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9720 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9721 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9722 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9723 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9724 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9725 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9726 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9727 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9728 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9729 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9730 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9731 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9732 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9734 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9735 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9736 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9738 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9739 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9741 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9742 vmcs12->vm_entry_intr_info_field);
9743 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9744 vmcs12->vm_entry_exception_error_code);
9745 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9746 vmcs12->vm_entry_instruction_len);
9747 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9748 vmcs12->guest_interruptibility_info);
9749 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9750 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9751 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9752 vmcs12->guest_pending_dbg_exceptions);
9753 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9754 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9756 if (nested_cpu_has_xsaves(vmcs12))
9757 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9758 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9760 exec_control = vmcs12->pin_based_vm_exec_control;
9761 exec_control |= vmcs_config.pin_based_exec_ctrl;
9762 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9764 if (nested_cpu_has_posted_intr(vmcs12)) {
9766 * Note that we use L0's vector here and in
9767 * vmx_deliver_nested_posted_interrupt.
9769 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9770 vmx->nested.pi_pending = false;
9771 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9772 vmcs_write64(POSTED_INTR_DESC_ADDR,
9773 page_to_phys(vmx->nested.pi_desc_page) +
9774 (unsigned long)(vmcs12->posted_intr_desc_addr &
9777 exec_control &= ~PIN_BASED_POSTED_INTR;
9779 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9781 vmx->nested.preemption_timer_expired = false;
9782 if (nested_cpu_has_preemption_timer(vmcs12))
9783 vmx_start_preemption_timer(vcpu);
9786 * Whether page-faults are trapped is determined by a combination of
9787 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9788 * If enable_ept, L0 doesn't care about page faults and we should
9789 * set all of these to L1's desires. However, if !enable_ept, L0 does
9790 * care about (at least some) page faults, and because it is not easy
9791 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9792 * to exit on each and every L2 page fault. This is done by setting
9793 * MASK=MATCH=0 and (see below) EB.PF=1.
9794 * Note that below we don't need special code to set EB.PF beyond the
9795 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9796 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9797 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9799 * A problem with this approach (when !enable_ept) is that L1 may be
9800 * injected with more page faults than it asked for. This could have
9801 * caused problems, but in practice existing hypervisors don't care.
9802 * To fix this, we will need to emulate the PFEC checking (on the L1
9803 * page tables), using walk_addr(), when injecting PFs to L1.
9805 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9806 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9807 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9808 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9810 if (cpu_has_secondary_exec_ctrls()) {
9811 exec_control = vmx_secondary_exec_control(vmx);
9813 /* Take the following fields only from vmcs12 */
9814 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9815 SECONDARY_EXEC_RDTSCP |
9816 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9817 SECONDARY_EXEC_APIC_REGISTER_VIRT |
9818 SECONDARY_EXEC_PCOMMIT);
9819 if (nested_cpu_has(vmcs12,
9820 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9821 exec_control |= vmcs12->secondary_vm_exec_control;
9823 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9825 * If translation failed, no matter: This feature asks
9826 * to exit when accessing the given address, and if it
9827 * can never be accessed, this feature won't do
9830 if (!vmx->nested.apic_access_page)
9832 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9834 vmcs_write64(APIC_ACCESS_ADDR,
9835 page_to_phys(vmx->nested.apic_access_page));
9836 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9837 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9839 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9840 kvm_vcpu_reload_apic_access_page(vcpu);
9843 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9844 vmcs_write64(EOI_EXIT_BITMAP0,
9845 vmcs12->eoi_exit_bitmap0);
9846 vmcs_write64(EOI_EXIT_BITMAP1,
9847 vmcs12->eoi_exit_bitmap1);
9848 vmcs_write64(EOI_EXIT_BITMAP2,
9849 vmcs12->eoi_exit_bitmap2);
9850 vmcs_write64(EOI_EXIT_BITMAP3,
9851 vmcs12->eoi_exit_bitmap3);
9852 vmcs_write16(GUEST_INTR_STATUS,
9853 vmcs12->guest_intr_status);
9856 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9861 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9862 * Some constant fields are set here by vmx_set_constant_host_state().
9863 * Other fields are different per CPU, and will be set later when
9864 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9866 vmx_set_constant_host_state(vmx);
9869 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9870 * entry, but only if the current (host) sp changed from the value
9871 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9872 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9873 * here we just force the write to happen on entry.
9877 exec_control = vmx_exec_control(vmx); /* L0's desires */
9878 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9879 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9880 exec_control &= ~CPU_BASED_TPR_SHADOW;
9881 exec_control |= vmcs12->cpu_based_vm_exec_control;
9883 if (exec_control & CPU_BASED_TPR_SHADOW) {
9884 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9885 page_to_phys(vmx->nested.virtual_apic_page));
9886 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9889 if (cpu_has_vmx_msr_bitmap() &&
9890 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9891 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9892 /* MSR_BITMAP will be set by following vmx_set_efer. */
9894 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9897 * Merging of IO bitmap not currently supported.
9898 * Rather, exit every time.
9900 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9901 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9903 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9905 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9906 * bitwise-or of what L1 wants to trap for L2, and what we want to
9907 * trap. Note that CR0.TS also needs updating - we do this later.
9909 update_exception_bitmap(vcpu);
9910 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9911 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9913 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9914 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9915 * bits are further modified by vmx_set_efer() below.
9917 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9919 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9920 * emulated by vmx_set_efer(), below.
9922 vm_entry_controls_init(vmx,
9923 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9924 ~VM_ENTRY_IA32E_MODE) |
9925 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9927 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9928 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9929 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9930 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9931 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9934 set_cr4_guest_host_mask(vmx);
9936 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9937 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9939 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9940 vmcs_write64(TSC_OFFSET,
9941 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9943 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9947 * There is no direct mapping between vpid02 and vpid12, the
9948 * vpid02 is per-vCPU for L0 and reused while the value of
9949 * vpid12 is changed w/ one invvpid during nested vmentry.
9950 * The vpid12 is allocated by L1 for L2, so it will not
9951 * influence global bitmap(for vpid01 and vpid02 allocation)
9952 * even if spawn a lot of nested vCPUs.
9954 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9955 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9956 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9957 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9958 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9961 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9962 vmx_flush_tlb(vcpu);
9967 if (nested_cpu_has_ept(vmcs12)) {
9968 kvm_mmu_unload(vcpu);
9969 nested_ept_init_mmu_context(vcpu);
9972 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9973 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9974 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9975 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9977 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9978 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9979 vmx_set_efer(vcpu, vcpu->arch.efer);
9982 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9983 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9984 * The CR0_READ_SHADOW is what L2 should have expected to read given
9985 * the specifications by L1; It's not enough to take
9986 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9987 * have more bits than L1 expected.
9989 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9990 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9992 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9993 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9995 /* shadow page tables on either EPT or shadow page tables */
9996 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9997 kvm_mmu_reset_context(vcpu);
10000 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10003 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10006 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10007 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10008 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10009 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10012 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10013 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10017 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10018 * for running an L2 nested guest.
10020 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10022 struct vmcs12 *vmcs12;
10023 struct vcpu_vmx *vmx = to_vmx(vcpu);
10025 struct loaded_vmcs *vmcs02;
10029 if (!nested_vmx_check_permission(vcpu) ||
10030 !nested_vmx_check_vmcs12(vcpu))
10033 skip_emulated_instruction(vcpu);
10034 vmcs12 = get_vmcs12(vcpu);
10036 if (enable_shadow_vmcs)
10037 copy_shadow_to_vmcs12(vmx);
10040 * The nested entry process starts with enforcing various prerequisites
10041 * on vmcs12 as required by the Intel SDM, and act appropriately when
10042 * they fail: As the SDM explains, some conditions should cause the
10043 * instruction to fail, while others will cause the instruction to seem
10044 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10045 * To speed up the normal (success) code path, we should avoid checking
10046 * for misconfigurations which will anyway be caught by the processor
10047 * when using the merged vmcs02.
10049 if (vmcs12->launch_state == launch) {
10050 nested_vmx_failValid(vcpu,
10051 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10052 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10056 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10057 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
10058 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10062 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
10063 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10067 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
10068 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10072 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
10073 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10077 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
10078 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10082 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10083 vmx->nested.nested_vmx_true_procbased_ctls_low,
10084 vmx->nested.nested_vmx_procbased_ctls_high) ||
10085 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10086 vmx->nested.nested_vmx_secondary_ctls_low,
10087 vmx->nested.nested_vmx_secondary_ctls_high) ||
10088 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10089 vmx->nested.nested_vmx_pinbased_ctls_low,
10090 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10091 !vmx_control_verify(vmcs12->vm_exit_controls,
10092 vmx->nested.nested_vmx_true_exit_ctls_low,
10093 vmx->nested.nested_vmx_exit_ctls_high) ||
10094 !vmx_control_verify(vmcs12->vm_entry_controls,
10095 vmx->nested.nested_vmx_true_entry_ctls_low,
10096 vmx->nested.nested_vmx_entry_ctls_high))
10098 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10102 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
10103 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10104 nested_vmx_failValid(vcpu,
10105 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
10109 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10110 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10111 nested_vmx_entry_failure(vcpu, vmcs12,
10112 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10115 if (vmcs12->vmcs_link_pointer != -1ull) {
10116 nested_vmx_entry_failure(vcpu, vmcs12,
10117 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
10122 * If the load IA32_EFER VM-entry control is 1, the following checks
10123 * are performed on the field for the IA32_EFER MSR:
10124 * - Bits reserved in the IA32_EFER MSR must be 0.
10125 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10126 * the IA-32e mode guest VM-exit control. It must also be identical
10127 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10130 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
10131 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10132 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10133 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10134 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10135 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
10136 nested_vmx_entry_failure(vcpu, vmcs12,
10137 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10143 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10144 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10145 * the values of the LMA and LME bits in the field must each be that of
10146 * the host address-space size VM-exit control.
10148 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10149 ia32e = (vmcs12->vm_exit_controls &
10150 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10151 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10152 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10153 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
10154 nested_vmx_entry_failure(vcpu, vmcs12,
10155 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10161 * We're finally done with prerequisite checking, and can start with
10162 * the nested entry.
10165 vmcs02 = nested_get_current_vmcs02(vmx);
10169 enter_guest_mode(vcpu);
10171 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
10173 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10174 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10177 vmx->loaded_vmcs = vmcs02;
10178 vmx_vcpu_put(vcpu);
10179 vmx_vcpu_load(vcpu, cpu);
10183 vmx_segment_cache_clear(vmx);
10185 prepare_vmcs02(vcpu, vmcs12);
10187 msr_entry_idx = nested_vmx_load_msr(vcpu,
10188 vmcs12->vm_entry_msr_load_addr,
10189 vmcs12->vm_entry_msr_load_count);
10190 if (msr_entry_idx) {
10191 leave_guest_mode(vcpu);
10192 vmx_load_vmcs01(vcpu);
10193 nested_vmx_entry_failure(vcpu, vmcs12,
10194 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10198 vmcs12->launch_state = 1;
10200 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10201 return kvm_vcpu_halt(vcpu);
10203 vmx->nested.nested_run_pending = 1;
10206 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10207 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10208 * returned as far as L1 is concerned. It will only return (and set
10209 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10215 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10216 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10217 * This function returns the new value we should put in vmcs12.guest_cr0.
10218 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10219 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10220 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10221 * didn't trap the bit, because if L1 did, so would L0).
10222 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10223 * been modified by L2, and L1 knows it. So just leave the old value of
10224 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10225 * isn't relevant, because if L0 traps this bit it can set it to anything.
10226 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10227 * changed these bits, and therefore they need to be updated, but L0
10228 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10229 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10231 static inline unsigned long
10232 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10235 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10236 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10237 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10238 vcpu->arch.cr0_guest_owned_bits));
10241 static inline unsigned long
10242 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10245 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10246 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10247 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10248 vcpu->arch.cr4_guest_owned_bits));
10251 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10252 struct vmcs12 *vmcs12)
10257 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10258 nr = vcpu->arch.exception.nr;
10259 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10261 if (kvm_exception_is_soft(nr)) {
10262 vmcs12->vm_exit_instruction_len =
10263 vcpu->arch.event_exit_inst_len;
10264 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10266 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10268 if (vcpu->arch.exception.has_error_code) {
10269 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10270 vmcs12->idt_vectoring_error_code =
10271 vcpu->arch.exception.error_code;
10274 vmcs12->idt_vectoring_info_field = idt_vectoring;
10275 } else if (vcpu->arch.nmi_injected) {
10276 vmcs12->idt_vectoring_info_field =
10277 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10278 } else if (vcpu->arch.interrupt.pending) {
10279 nr = vcpu->arch.interrupt.nr;
10280 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10282 if (vcpu->arch.interrupt.soft) {
10283 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10284 vmcs12->vm_entry_instruction_len =
10285 vcpu->arch.event_exit_inst_len;
10287 idt_vectoring |= INTR_TYPE_EXT_INTR;
10289 vmcs12->idt_vectoring_info_field = idt_vectoring;
10293 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10295 struct vcpu_vmx *vmx = to_vmx(vcpu);
10297 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10298 vmx->nested.preemption_timer_expired) {
10299 if (vmx->nested.nested_run_pending)
10301 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10305 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10306 if (vmx->nested.nested_run_pending ||
10307 vcpu->arch.interrupt.pending)
10309 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10310 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10311 INTR_INFO_VALID_MASK, 0);
10313 * The NMI-triggered VM exit counts as injection:
10314 * clear this one and block further NMIs.
10316 vcpu->arch.nmi_pending = 0;
10317 vmx_set_nmi_mask(vcpu, true);
10321 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10322 nested_exit_on_intr(vcpu)) {
10323 if (vmx->nested.nested_run_pending)
10325 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10329 return vmx_complete_nested_posted_interrupt(vcpu);
10332 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10334 ktime_t remaining =
10335 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10338 if (ktime_to_ns(remaining) <= 0)
10341 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10342 do_div(value, 1000000);
10343 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10347 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10348 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10349 * and this function updates it to reflect the changes to the guest state while
10350 * L2 was running (and perhaps made some exits which were handled directly by L0
10351 * without going back to L1), and to reflect the exit reason.
10352 * Note that we do not have to copy here all VMCS fields, just those that
10353 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10354 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10355 * which already writes to vmcs12 directly.
10357 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10358 u32 exit_reason, u32 exit_intr_info,
10359 unsigned long exit_qualification)
10361 /* update guest state fields: */
10362 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10363 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10365 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10366 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10367 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10369 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10370 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10371 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10372 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10373 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10374 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10375 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10376 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10377 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10378 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10379 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10380 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10381 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10382 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10383 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10384 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10385 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10386 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10387 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10388 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10389 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10390 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10391 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10392 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10393 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10394 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10395 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10396 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10397 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10398 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10399 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10400 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10401 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10402 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10403 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10404 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10406 vmcs12->guest_interruptibility_info =
10407 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10408 vmcs12->guest_pending_dbg_exceptions =
10409 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10410 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10411 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10413 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10415 if (nested_cpu_has_preemption_timer(vmcs12)) {
10416 if (vmcs12->vm_exit_controls &
10417 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10418 vmcs12->vmx_preemption_timer_value =
10419 vmx_get_preemption_timer_value(vcpu);
10420 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10424 * In some cases (usually, nested EPT), L2 is allowed to change its
10425 * own CR3 without exiting. If it has changed it, we must keep it.
10426 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10427 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10429 * Additionally, restore L2's PDPTR to vmcs12.
10432 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10433 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10434 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10435 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10436 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10439 if (nested_cpu_has_vid(vmcs12))
10440 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10442 vmcs12->vm_entry_controls =
10443 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10444 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10446 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10447 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10448 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10451 /* TODO: These cannot have changed unless we have MSR bitmaps and
10452 * the relevant bit asks not to trap the change */
10453 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10454 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10455 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10456 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10457 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10458 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10459 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10460 if (kvm_mpx_supported())
10461 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10462 if (nested_cpu_has_xsaves(vmcs12))
10463 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10465 /* update exit information fields: */
10467 vmcs12->vm_exit_reason = exit_reason;
10468 vmcs12->exit_qualification = exit_qualification;
10470 vmcs12->vm_exit_intr_info = exit_intr_info;
10471 if ((vmcs12->vm_exit_intr_info &
10472 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10473 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10474 vmcs12->vm_exit_intr_error_code =
10475 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10476 vmcs12->idt_vectoring_info_field = 0;
10477 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10478 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10480 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10481 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10482 * instead of reading the real value. */
10483 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10486 * Transfer the event that L0 or L1 may wanted to inject into
10487 * L2 to IDT_VECTORING_INFO_FIELD.
10489 vmcs12_save_pending_event(vcpu, vmcs12);
10493 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10494 * preserved above and would only end up incorrectly in L1.
10496 vcpu->arch.nmi_injected = false;
10497 kvm_clear_exception_queue(vcpu);
10498 kvm_clear_interrupt_queue(vcpu);
10502 * A part of what we need to when the nested L2 guest exits and we want to
10503 * run its L1 parent, is to reset L1's guest state to the host state specified
10505 * This function is to be called not only on normal nested exit, but also on
10506 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10507 * Failures During or After Loading Guest State").
10508 * This function should be called when the active VMCS is L1's (vmcs01).
10510 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10511 struct vmcs12 *vmcs12)
10513 struct kvm_segment seg;
10515 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10516 vcpu->arch.efer = vmcs12->host_ia32_efer;
10517 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10518 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10520 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10521 vmx_set_efer(vcpu, vcpu->arch.efer);
10523 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10524 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10525 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10527 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10528 * actually changed, because it depends on the current state of
10529 * fpu_active (which may have changed).
10530 * Note that vmx_set_cr0 refers to efer set above.
10532 vmx_set_cr0(vcpu, vmcs12->host_cr0);
10534 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10535 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10536 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10538 update_exception_bitmap(vcpu);
10539 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10540 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10543 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10544 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10546 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10547 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10549 nested_ept_uninit_mmu_context(vcpu);
10551 kvm_set_cr3(vcpu, vmcs12->host_cr3);
10552 kvm_mmu_reset_context(vcpu);
10555 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10559 * Trivially support vpid by letting L2s share their parent
10560 * L1's vpid. TODO: move to a more elaborate solution, giving
10561 * each L2 its own vpid and exposing the vpid feature to L1.
10563 vmx_flush_tlb(vcpu);
10567 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10568 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10569 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10570 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10571 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10573 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10574 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10575 vmcs_write64(GUEST_BNDCFGS, 0);
10577 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10578 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10579 vcpu->arch.pat = vmcs12->host_ia32_pat;
10581 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10582 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10583 vmcs12->host_ia32_perf_global_ctrl);
10585 /* Set L1 segment info according to Intel SDM
10586 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10587 seg = (struct kvm_segment) {
10589 .limit = 0xFFFFFFFF,
10590 .selector = vmcs12->host_cs_selector,
10596 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10600 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10601 seg = (struct kvm_segment) {
10603 .limit = 0xFFFFFFFF,
10610 seg.selector = vmcs12->host_ds_selector;
10611 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10612 seg.selector = vmcs12->host_es_selector;
10613 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10614 seg.selector = vmcs12->host_ss_selector;
10615 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10616 seg.selector = vmcs12->host_fs_selector;
10617 seg.base = vmcs12->host_fs_base;
10618 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10619 seg.selector = vmcs12->host_gs_selector;
10620 seg.base = vmcs12->host_gs_base;
10621 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10622 seg = (struct kvm_segment) {
10623 .base = vmcs12->host_tr_base,
10625 .selector = vmcs12->host_tr_selector,
10629 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10631 kvm_set_dr(vcpu, 7, 0x400);
10632 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10634 if (cpu_has_vmx_msr_bitmap())
10635 vmx_set_msr_bitmap(vcpu);
10637 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10638 vmcs12->vm_exit_msr_load_count))
10639 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10643 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10644 * and modify vmcs12 to make it see what it would expect to see there if
10645 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10647 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10648 u32 exit_intr_info,
10649 unsigned long exit_qualification)
10651 struct vcpu_vmx *vmx = to_vmx(vcpu);
10652 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10654 /* trying to cancel vmlaunch/vmresume is a bug */
10655 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10657 leave_guest_mode(vcpu);
10658 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10659 exit_qualification);
10661 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10662 vmcs12->vm_exit_msr_store_count))
10663 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10665 vmx_load_vmcs01(vcpu);
10667 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10668 && nested_exit_intr_ack_set(vcpu)) {
10669 int irq = kvm_cpu_get_interrupt(vcpu);
10671 vmcs12->vm_exit_intr_info = irq |
10672 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10675 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10676 vmcs12->exit_qualification,
10677 vmcs12->idt_vectoring_info_field,
10678 vmcs12->vm_exit_intr_info,
10679 vmcs12->vm_exit_intr_error_code,
10682 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10683 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10684 vmx_segment_cache_clear(vmx);
10686 /* if no vmcs02 cache requested, remove the one we used */
10687 if (VMCS02_POOL_SIZE == 0)
10688 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10690 load_vmcs12_host_state(vcpu, vmcs12);
10692 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10693 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10695 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10698 /* Unpin physical memory we referred to in vmcs02 */
10699 if (vmx->nested.apic_access_page) {
10700 nested_release_page(vmx->nested.apic_access_page);
10701 vmx->nested.apic_access_page = NULL;
10703 if (vmx->nested.virtual_apic_page) {
10704 nested_release_page(vmx->nested.virtual_apic_page);
10705 vmx->nested.virtual_apic_page = NULL;
10707 if (vmx->nested.pi_desc_page) {
10708 kunmap(vmx->nested.pi_desc_page);
10709 nested_release_page(vmx->nested.pi_desc_page);
10710 vmx->nested.pi_desc_page = NULL;
10711 vmx->nested.pi_desc = NULL;
10715 * We are now running in L2, mmu_notifier will force to reload the
10716 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10718 kvm_vcpu_reload_apic_access_page(vcpu);
10721 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10722 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10723 * success or failure flag accordingly.
10725 if (unlikely(vmx->fail)) {
10727 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10729 nested_vmx_succeed(vcpu);
10730 if (enable_shadow_vmcs)
10731 vmx->nested.sync_shadow_vmcs = true;
10733 /* in case we halted in L2 */
10734 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10738 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10740 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10742 if (is_guest_mode(vcpu))
10743 nested_vmx_vmexit(vcpu, -1, 0, 0);
10744 free_nested(to_vmx(vcpu));
10748 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10749 * 23.7 "VM-entry failures during or after loading guest state" (this also
10750 * lists the acceptable exit-reason and exit-qualification parameters).
10751 * It should only be called before L2 actually succeeded to run, and when
10752 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10754 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10755 struct vmcs12 *vmcs12,
10756 u32 reason, unsigned long qualification)
10758 load_vmcs12_host_state(vcpu, vmcs12);
10759 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10760 vmcs12->exit_qualification = qualification;
10761 nested_vmx_succeed(vcpu);
10762 if (enable_shadow_vmcs)
10763 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10766 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10767 struct x86_instruction_info *info,
10768 enum x86_intercept_stage stage)
10770 return X86EMUL_CONTINUE;
10773 #ifdef CONFIG_X86_64
10774 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
10775 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
10776 u64 divisor, u64 *result)
10778 u64 low = a << shift, high = a >> (64 - shift);
10780 /* To avoid the overflow on divq */
10781 if (high >= divisor)
10784 /* Low hold the result, high hold rem which is discarded */
10785 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
10786 "rm" (divisor), "0" (low), "1" (high));
10792 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
10794 struct vcpu_vmx *vmx = to_vmx(vcpu);
10795 u64 tscl = rdtsc(), delta_tsc;
10797 delta_tsc = guest_deadline_tsc - kvm_read_l1_tsc(vcpu, tscl);
10799 /* Convert to host delta tsc if tsc scaling is enabled */
10800 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
10801 u64_shl_div_u64(delta_tsc,
10802 kvm_tsc_scaling_ratio_frac_bits,
10803 vcpu->arch.tsc_scaling_ratio,
10808 * If the delta tsc can't fit in the 32 bit after the multi shift,
10809 * we can't use the preemption timer.
10810 * It's possible that it fits on later vmentries, but checking
10811 * on every vmentry is costly so we just use an hrtimer.
10813 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
10816 vmx->hv_deadline_tsc = tscl + delta_tsc;
10817 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10818 PIN_BASED_VMX_PREEMPTION_TIMER);
10822 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
10824 struct vcpu_vmx *vmx = to_vmx(vcpu);
10825 vmx->hv_deadline_tsc = -1;
10826 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10827 PIN_BASED_VMX_PREEMPTION_TIMER);
10831 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10834 shrink_ple_window(vcpu);
10837 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10838 struct kvm_memory_slot *slot)
10840 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10841 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10844 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10845 struct kvm_memory_slot *slot)
10847 kvm_mmu_slot_set_dirty(kvm, slot);
10850 static void vmx_flush_log_dirty(struct kvm *kvm)
10852 kvm_flush_pml_buffers(kvm);
10855 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10856 struct kvm_memory_slot *memslot,
10857 gfn_t offset, unsigned long mask)
10859 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10863 * This routine does the following things for vCPU which is going
10864 * to be blocked if VT-d PI is enabled.
10865 * - Store the vCPU to the wakeup list, so when interrupts happen
10866 * we can find the right vCPU to wake up.
10867 * - Change the Posted-interrupt descriptor as below:
10868 * 'NDST' <-- vcpu->pre_pcpu
10869 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10870 * - If 'ON' is set during this process, which means at least one
10871 * interrupt is posted for this vCPU, we cannot block it, in
10872 * this case, return 1, otherwise, return 0.
10875 static int pi_pre_block(struct kvm_vcpu *vcpu)
10877 unsigned long flags;
10879 struct pi_desc old, new;
10880 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10882 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10883 !irq_remapping_cap(IRQ_POSTING_CAP))
10886 vcpu->pre_pcpu = vcpu->cpu;
10887 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10888 vcpu->pre_pcpu), flags);
10889 list_add_tail(&vcpu->blocked_vcpu_list,
10890 &per_cpu(blocked_vcpu_on_cpu,
10892 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10893 vcpu->pre_pcpu), flags);
10896 old.control = new.control = pi_desc->control;
10899 * We should not block the vCPU if
10900 * an interrupt is posted for it.
10902 if (pi_test_on(pi_desc) == 1) {
10903 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10904 vcpu->pre_pcpu), flags);
10905 list_del(&vcpu->blocked_vcpu_list);
10906 spin_unlock_irqrestore(
10907 &per_cpu(blocked_vcpu_on_cpu_lock,
10908 vcpu->pre_pcpu), flags);
10909 vcpu->pre_pcpu = -1;
10914 WARN((pi_desc->sn == 1),
10915 "Warning: SN field of posted-interrupts "
10916 "is set before blocking\n");
10919 * Since vCPU can be preempted during this process,
10920 * vcpu->cpu could be different with pre_pcpu, we
10921 * need to set pre_pcpu as the destination of wakeup
10922 * notification event, then we can find the right vCPU
10923 * to wakeup in wakeup handler if interrupts happen
10924 * when the vCPU is in blocked state.
10926 dest = cpu_physical_id(vcpu->pre_pcpu);
10928 if (x2apic_enabled())
10931 new.ndst = (dest << 8) & 0xFF00;
10933 /* set 'NV' to 'wakeup vector' */
10934 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10935 } while (cmpxchg(&pi_desc->control, old.control,
10936 new.control) != old.control);
10941 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10943 if (pi_pre_block(vcpu))
10946 if (kvm_lapic_hv_timer_in_use(vcpu))
10947 kvm_lapic_switch_to_sw_timer(vcpu);
10952 static void pi_post_block(struct kvm_vcpu *vcpu)
10954 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10955 struct pi_desc old, new;
10957 unsigned long flags;
10959 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10960 !irq_remapping_cap(IRQ_POSTING_CAP))
10964 old.control = new.control = pi_desc->control;
10966 dest = cpu_physical_id(vcpu->cpu);
10968 if (x2apic_enabled())
10971 new.ndst = (dest << 8) & 0xFF00;
10973 /* Allow posting non-urgent interrupts */
10976 /* set 'NV' to 'notification vector' */
10977 new.nv = POSTED_INTR_VECTOR;
10978 } while (cmpxchg(&pi_desc->control, old.control,
10979 new.control) != old.control);
10981 if(vcpu->pre_pcpu != -1) {
10983 &per_cpu(blocked_vcpu_on_cpu_lock,
10984 vcpu->pre_pcpu), flags);
10985 list_del(&vcpu->blocked_vcpu_list);
10986 spin_unlock_irqrestore(
10987 &per_cpu(blocked_vcpu_on_cpu_lock,
10988 vcpu->pre_pcpu), flags);
10989 vcpu->pre_pcpu = -1;
10993 static void vmx_post_block(struct kvm_vcpu *vcpu)
10995 if (kvm_x86_ops->set_hv_timer)
10996 kvm_lapic_switch_to_hv_timer(vcpu);
10998 pi_post_block(vcpu);
11002 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11005 * @host_irq: host irq of the interrupt
11006 * @guest_irq: gsi of the interrupt
11007 * @set: set or unset PI
11008 * returns 0 on success, < 0 on failure
11010 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11011 uint32_t guest_irq, bool set)
11013 struct kvm_kernel_irq_routing_entry *e;
11014 struct kvm_irq_routing_table *irq_rt;
11015 struct kvm_lapic_irq irq;
11016 struct kvm_vcpu *vcpu;
11017 struct vcpu_data vcpu_info;
11018 int idx, ret = -EINVAL;
11020 if (!kvm_arch_has_assigned_device(kvm) ||
11021 !irq_remapping_cap(IRQ_POSTING_CAP))
11024 idx = srcu_read_lock(&kvm->irq_srcu);
11025 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11026 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11028 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11029 if (e->type != KVM_IRQ_ROUTING_MSI)
11032 * VT-d PI cannot support posting multicast/broadcast
11033 * interrupts to a vCPU, we still use interrupt remapping
11034 * for these kind of interrupts.
11036 * For lowest-priority interrupts, we only support
11037 * those with single CPU as the destination, e.g. user
11038 * configures the interrupts via /proc/irq or uses
11039 * irqbalance to make the interrupts single-CPU.
11041 * We will support full lowest-priority interrupt later.
11044 kvm_set_msi_irq(e, &irq);
11045 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11047 * Make sure the IRTE is in remapped mode if
11048 * we don't handle it in posted mode.
11050 ret = irq_set_vcpu_affinity(host_irq, NULL);
11053 "failed to back to remapped mode, irq: %u\n",
11061 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11062 vcpu_info.vector = irq.vector;
11064 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11065 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11068 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11070 /* suppress notification event before unposting */
11071 pi_set_sn(vcpu_to_pi_desc(vcpu));
11072 ret = irq_set_vcpu_affinity(host_irq, NULL);
11073 pi_clear_sn(vcpu_to_pi_desc(vcpu));
11077 printk(KERN_INFO "%s: failed to update PI IRTE\n",
11085 srcu_read_unlock(&kvm->irq_srcu, idx);
11089 static struct kvm_x86_ops vmx_x86_ops = {
11090 .cpu_has_kvm_support = cpu_has_kvm_support,
11091 .disabled_by_bios = vmx_disabled_by_bios,
11092 .hardware_setup = hardware_setup,
11093 .hardware_unsetup = hardware_unsetup,
11094 .check_processor_compatibility = vmx_check_processor_compat,
11095 .hardware_enable = hardware_enable,
11096 .hardware_disable = hardware_disable,
11097 .cpu_has_accelerated_tpr = report_flexpriority,
11098 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11100 .vcpu_create = vmx_create_vcpu,
11101 .vcpu_free = vmx_free_vcpu,
11102 .vcpu_reset = vmx_vcpu_reset,
11104 .prepare_guest_switch = vmx_save_host_state,
11105 .vcpu_load = vmx_vcpu_load,
11106 .vcpu_put = vmx_vcpu_put,
11108 .update_bp_intercept = update_exception_bitmap,
11109 .get_msr = vmx_get_msr,
11110 .set_msr = vmx_set_msr,
11111 .get_segment_base = vmx_get_segment_base,
11112 .get_segment = vmx_get_segment,
11113 .set_segment = vmx_set_segment,
11114 .get_cpl = vmx_get_cpl,
11115 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11116 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11117 .decache_cr3 = vmx_decache_cr3,
11118 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11119 .set_cr0 = vmx_set_cr0,
11120 .set_cr3 = vmx_set_cr3,
11121 .set_cr4 = vmx_set_cr4,
11122 .set_efer = vmx_set_efer,
11123 .get_idt = vmx_get_idt,
11124 .set_idt = vmx_set_idt,
11125 .get_gdt = vmx_get_gdt,
11126 .set_gdt = vmx_set_gdt,
11127 .get_dr6 = vmx_get_dr6,
11128 .set_dr6 = vmx_set_dr6,
11129 .set_dr7 = vmx_set_dr7,
11130 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11131 .cache_reg = vmx_cache_reg,
11132 .get_rflags = vmx_get_rflags,
11133 .set_rflags = vmx_set_rflags,
11135 .get_pkru = vmx_get_pkru,
11137 .fpu_activate = vmx_fpu_activate,
11138 .fpu_deactivate = vmx_fpu_deactivate,
11140 .tlb_flush = vmx_flush_tlb,
11142 .run = vmx_vcpu_run,
11143 .handle_exit = vmx_handle_exit,
11144 .skip_emulated_instruction = skip_emulated_instruction,
11145 .set_interrupt_shadow = vmx_set_interrupt_shadow,
11146 .get_interrupt_shadow = vmx_get_interrupt_shadow,
11147 .patch_hypercall = vmx_patch_hypercall,
11148 .set_irq = vmx_inject_irq,
11149 .set_nmi = vmx_inject_nmi,
11150 .queue_exception = vmx_queue_exception,
11151 .cancel_injection = vmx_cancel_injection,
11152 .interrupt_allowed = vmx_interrupt_allowed,
11153 .nmi_allowed = vmx_nmi_allowed,
11154 .get_nmi_mask = vmx_get_nmi_mask,
11155 .set_nmi_mask = vmx_set_nmi_mask,
11156 .enable_nmi_window = enable_nmi_window,
11157 .enable_irq_window = enable_irq_window,
11158 .update_cr8_intercept = update_cr8_intercept,
11159 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11160 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11161 .get_enable_apicv = vmx_get_enable_apicv,
11162 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11163 .load_eoi_exitmap = vmx_load_eoi_exitmap,
11164 .hwapic_irr_update = vmx_hwapic_irr_update,
11165 .hwapic_isr_update = vmx_hwapic_isr_update,
11166 .sync_pir_to_irr = vmx_sync_pir_to_irr,
11167 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11169 .set_tss_addr = vmx_set_tss_addr,
11170 .get_tdp_level = get_ept_level,
11171 .get_mt_mask = vmx_get_mt_mask,
11173 .get_exit_info = vmx_get_exit_info,
11175 .get_lpage_level = vmx_get_lpage_level,
11177 .cpuid_update = vmx_cpuid_update,
11179 .rdtscp_supported = vmx_rdtscp_supported,
11180 .invpcid_supported = vmx_invpcid_supported,
11182 .set_supported_cpuid = vmx_set_supported_cpuid,
11184 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11186 .read_tsc_offset = vmx_read_tsc_offset,
11187 .write_tsc_offset = vmx_write_tsc_offset,
11188 .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
11189 .read_l1_tsc = vmx_read_l1_tsc,
11191 .set_tdp_cr3 = vmx_set_cr3,
11193 .check_intercept = vmx_check_intercept,
11194 .handle_external_intr = vmx_handle_external_intr,
11195 .mpx_supported = vmx_mpx_supported,
11196 .xsaves_supported = vmx_xsaves_supported,
11198 .check_nested_events = vmx_check_nested_events,
11200 .sched_in = vmx_sched_in,
11202 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11203 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11204 .flush_log_dirty = vmx_flush_log_dirty,
11205 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11207 .pre_block = vmx_pre_block,
11208 .post_block = vmx_post_block,
11210 .pmu_ops = &intel_pmu_ops,
11212 .update_pi_irte = vmx_update_pi_irte,
11214 #ifdef CONFIG_X86_64
11215 .set_hv_timer = vmx_set_hv_timer,
11216 .cancel_hv_timer = vmx_cancel_hv_timer,
11220 static int __init vmx_init(void)
11222 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11223 __alignof__(struct vcpu_vmx), THIS_MODULE);
11227 #ifdef CONFIG_KEXEC_CORE
11228 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11229 crash_vmclear_local_loaded_vmcss);
11235 static void __exit vmx_exit(void)
11237 #ifdef CONFIG_KEXEC_CORE
11238 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11245 module_init(vmx_init)
11246 module_exit(vmx_exit)