arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/frame.h>
  37 #include <linux/nospec.h>
  38 #include "kvm_cache_regs.h"
  39 #include "x86.h"
  40
  41 #include <asm/cpu.h>
  42 #include <asm/io.h>
  43 #include <asm/desc.h>
  44 #include <asm/vmx.h>
  45 #include <asm/virtext.h>
  46 #include <asm/mce.h>
  47 #include <asm/fpu/internal.h>
  48 #include <asm/perf_event.h>
  49 #include <asm/debugreg.h>
  50 #include <asm/kexec.h>
  51 #include <asm/apic.h>
  52 #include <asm/irq_remapping.h>
  53 #include <asm/mmu_context.h>
  54 #include <asm/spec-ctrl.h>
  55 #include <asm/mshyperv.h>
  56
  57 #include "trace.h"
  58 #include "pmu.h"
  59 #include "vmx_evmcs.h"
  60
  61 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  62 #define __ex_clear(x, reg) \
  63         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  64
  65 MODULE_AUTHOR("Qumranet");
  66 MODULE_LICENSE("GPL");
  67
  68 static const struct x86_cpu_id vmx_cpu_id[] = {
  69         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  70         {}
  71 };
  72 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  73
  74 static bool __read_mostly nosmt;
  75 module_param(nosmt, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_vpid = 1;
  78 module_param_named(vpid, enable_vpid, bool, 0444);
  79
  80 static bool __read_mostly enable_vnmi = 1;
  81 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  82
  83 static bool __read_mostly flexpriority_enabled = 1;
  84 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  85
  86 static bool __read_mostly enable_ept = 1;
  87 module_param_named(ept, enable_ept, bool, S_IRUGO);
  88
  89 static bool __read_mostly enable_unrestricted_guest = 1;
  90 module_param_named(unrestricted_guest,
  91                         enable_unrestricted_guest, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_ept_ad_bits = 1;
  94 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  95
  96 static bool __read_mostly emulate_invalid_guest_state = true;
  97 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  98
  99 static bool __read_mostly fasteoi = 1;
 100 module_param(fasteoi, bool, S_IRUGO);
 101
 102 static bool __read_mostly enable_apicv = 1;
 103 module_param(enable_apicv, bool, S_IRUGO);
 104
 105 static bool __read_mostly enable_shadow_vmcs = 1;
 106 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
 107 /*
 108  * If nested=1, nested virtualization is supported, i.e., guests may use
 109  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 110  * use VMX instructions.
 111  */
 112 static bool __read_mostly nested = 0;
 113 module_param(nested, bool, S_IRUGO);
 114
 115 static u64 __read_mostly host_xss;
 116
 117 static bool __read_mostly enable_pml = 1;
 118 module_param_named(pml, enable_pml, bool, S_IRUGO);
 119
 120 #define MSR_TYPE_R      1
 121 #define MSR_TYPE_W      2
 122 #define MSR_TYPE_RW     3
 123
 124 #define MSR_BITMAP_MODE_X2APIC          1
 125 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 126 #define MSR_BITMAP_MODE_LM              4
 127
 128 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 129
 130 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 131 static int __read_mostly cpu_preemption_timer_multi;
 132 static bool __read_mostly enable_preemption_timer = 1;
 133 #ifdef CONFIG_X86_64
 134 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 135 #endif
 136
 137 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 138 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 139 #define KVM_VM_CR0_ALWAYS_ON                            \
 140         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 141          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 142 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 143         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 144          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 145
 146 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 147 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 148 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 149
 150 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 151
 152 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 153
 154 /*
 155  * Hyper-V requires all of these, so mark them as supported even though
 156  * they are just treated the same as all-context.
 157  */
 158 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 159         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 160         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 161         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 162         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 163
 164 /*
 165  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 166  * ple_gap:    upper bound on the amount of time between two successive
 167  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 168  *             According to test, this time is usually smaller than 128 cycles.
 169  * ple_window: upper bound on the amount of time a guest is allowed to execute
 170  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 171  *             less than 2^12 cycles
 172  * Time is measured based on a counter that runs at the same rate as the TSC,
 173  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 174  */
 175 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 176
 177 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 178 module_param(ple_window, uint, 0444);
 179
 180 /* Default doubles per-vcpu window every exit. */
 181 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 182 module_param(ple_window_grow, uint, 0444);
 183
 184 /* Default resets per-vcpu window every exit to ple_window. */
 185 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 186 module_param(ple_window_shrink, uint, 0444);
 187
 188 /* Default is to compute the maximum so we can never overflow. */
 189 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 190 module_param(ple_window_max, uint, 0444);
 191
 192 extern const ulong vmx_return;
 193
 194 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 195
 196 /* These MUST be in sync with vmentry_l1d_param order. */
 197 enum vmx_l1d_flush_state {
 198         VMENTER_L1D_FLUSH_NEVER,
 199         VMENTER_L1D_FLUSH_COND,
 200         VMENTER_L1D_FLUSH_ALWAYS,
 201 };
 202
 203 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush = VMENTER_L1D_FLUSH_COND;
 204
 205 static const struct {
 206         const char *option;
 207         enum vmx_l1d_flush_state cmd;
 208 } vmentry_l1d_param[] = {
 209         {"never",       VMENTER_L1D_FLUSH_NEVER},
 210         {"cond",        VMENTER_L1D_FLUSH_COND},
 211         {"always",      VMENTER_L1D_FLUSH_ALWAYS},
 212 };
 213
 214 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 215 {
 216         unsigned int i;
 217
 218         if (!s)
 219                 return -EINVAL;
 220
 221         for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 222                 if (!strcmp(s, vmentry_l1d_param[i].option)) {
 223                         vmentry_l1d_flush = vmentry_l1d_param[i].cmd;
 224                         return 0;
 225                 }
 226         }
 227
 228         return -EINVAL;
 229 }
 230
 231 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 232 {
 233         return sprintf(s, "%s\n", vmentry_l1d_param[vmentry_l1d_flush].option);
 234 }
 235
 236 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 237         .set = vmentry_l1d_flush_set,
 238         .get = vmentry_l1d_flush_get,
 239 };
 240 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, &vmentry_l1d_flush, S_IRUGO);
 241
 242 struct kvm_vmx {
 243         struct kvm kvm;
 244
 245         unsigned int tss_addr;
 246         bool ept_identity_pagetable_done;
 247         gpa_t ept_identity_map_addr;
 248 };
 249
 250 #define NR_AUTOLOAD_MSRS 8
 251
 252 struct vmcs {
 253         u32 revision_id;
 254         u32 abort;
 255         char data[0];
 256 };
 257
 258 /*
 259  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 260  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 261  * loaded on this CPU (so we can clear them if the CPU goes down).
 262  */
 263 struct loaded_vmcs {
 264         struct vmcs *vmcs;
 265         struct vmcs *shadow_vmcs;
 266         int cpu;
 267         bool launched;
 268         bool nmi_known_unmasked;
 269         unsigned long vmcs_host_cr3;    /* May not match real cr3 */
 270         unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 271         /* Support for vnmi-less CPUs */
 272         int soft_vnmi_blocked;
 273         ktime_t entry_time;
 274         s64 vnmi_blocked_time;
 275         unsigned long *msr_bitmap;
 276         struct list_head loaded_vmcss_on_cpu_link;
 277 };
 278
 279 struct shared_msr_entry {
 280         unsigned index;
 281         u64 data;
 282         u64 mask;
 283 };
 284
 285 /*
 286  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 287  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 288  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 289  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 290  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 291  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 292  * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
 293  * underlying hardware which will be used to run L2.
 294  * This structure is packed to ensure that its layout is identical across
 295  * machines (necessary for live migration).
 296  *
 297  * IMPORTANT: Changing the layout of existing fields in this structure
 298  * will break save/restore compatibility with older kvm releases. When
 299  * adding new fields, either use space in the reserved padding* arrays
 300  * or add the new fields to the end of the structure.
 301  */
 302 typedef u64 natural_width;
 303 struct __packed vmcs12 {
 304         /* According to the Intel spec, a VMCS region must start with the
 305          * following two fields. Then follow implementation-specific data.
 306          */
 307         u32 revision_id;
 308         u32 abort;
 309
 310         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 311         u32 padding[7]; /* room for future expansion */
 312
 313         u64 io_bitmap_a;
 314         u64 io_bitmap_b;
 315         u64 msr_bitmap;
 316         u64 vm_exit_msr_store_addr;
 317         u64 vm_exit_msr_load_addr;
 318         u64 vm_entry_msr_load_addr;
 319         u64 tsc_offset;
 320         u64 virtual_apic_page_addr;
 321         u64 apic_access_addr;
 322         u64 posted_intr_desc_addr;
 323         u64 ept_pointer;
 324         u64 eoi_exit_bitmap0;
 325         u64 eoi_exit_bitmap1;
 326         u64 eoi_exit_bitmap2;
 327         u64 eoi_exit_bitmap3;
 328         u64 xss_exit_bitmap;
 329         u64 guest_physical_address;
 330         u64 vmcs_link_pointer;
 331         u64 guest_ia32_debugctl;
 332         u64 guest_ia32_pat;
 333         u64 guest_ia32_efer;
 334         u64 guest_ia32_perf_global_ctrl;
 335         u64 guest_pdptr0;
 336         u64 guest_pdptr1;
 337         u64 guest_pdptr2;
 338         u64 guest_pdptr3;
 339         u64 guest_bndcfgs;
 340         u64 host_ia32_pat;
 341         u64 host_ia32_efer;
 342         u64 host_ia32_perf_global_ctrl;
 343         u64 vmread_bitmap;
 344         u64 vmwrite_bitmap;
 345         u64 vm_function_control;
 346         u64 eptp_list_address;
 347         u64 pml_address;
 348         u64 padding64[3]; /* room for future expansion */
 349         /*
 350          * To allow migration of L1 (complete with its L2 guests) between
 351          * machines of different natural widths (32 or 64 bit), we cannot have
 352          * unsigned long fields with no explict size. We use u64 (aliased
 353          * natural_width) instead. Luckily, x86 is little-endian.
 354          */
 355         natural_width cr0_guest_host_mask;
 356         natural_width cr4_guest_host_mask;
 357         natural_width cr0_read_shadow;
 358         natural_width cr4_read_shadow;
 359         natural_width cr3_target_value0;
 360         natural_width cr3_target_value1;
 361         natural_width cr3_target_value2;
 362         natural_width cr3_target_value3;
 363         natural_width exit_qualification;
 364         natural_width guest_linear_address;
 365         natural_width guest_cr0;
 366         natural_width guest_cr3;
 367         natural_width guest_cr4;
 368         natural_width guest_es_base;
 369         natural_width guest_cs_base;
 370         natural_width guest_ss_base;
 371         natural_width guest_ds_base;
 372         natural_width guest_fs_base;
 373         natural_width guest_gs_base;
 374         natural_width guest_ldtr_base;
 375         natural_width guest_tr_base;
 376         natural_width guest_gdtr_base;
 377         natural_width guest_idtr_base;
 378         natural_width guest_dr7;
 379         natural_width guest_rsp;
 380         natural_width guest_rip;
 381         natural_width guest_rflags;
 382         natural_width guest_pending_dbg_exceptions;
 383         natural_width guest_sysenter_esp;
 384         natural_width guest_sysenter_eip;
 385         natural_width host_cr0;
 386         natural_width host_cr3;
 387         natural_width host_cr4;
 388         natural_width host_fs_base;
 389         natural_width host_gs_base;
 390         natural_width host_tr_base;
 391         natural_width host_gdtr_base;
 392         natural_width host_idtr_base;
 393         natural_width host_ia32_sysenter_esp;
 394         natural_width host_ia32_sysenter_eip;
 395         natural_width host_rsp;
 396         natural_width host_rip;
 397         natural_width paddingl[8]; /* room for future expansion */
 398         u32 pin_based_vm_exec_control;
 399         u32 cpu_based_vm_exec_control;
 400         u32 exception_bitmap;
 401         u32 page_fault_error_code_mask;
 402         u32 page_fault_error_code_match;
 403         u32 cr3_target_count;
 404         u32 vm_exit_controls;
 405         u32 vm_exit_msr_store_count;
 406         u32 vm_exit_msr_load_count;
 407         u32 vm_entry_controls;
 408         u32 vm_entry_msr_load_count;
 409         u32 vm_entry_intr_info_field;
 410         u32 vm_entry_exception_error_code;
 411         u32 vm_entry_instruction_len;
 412         u32 tpr_threshold;
 413         u32 secondary_vm_exec_control;
 414         u32 vm_instruction_error;
 415         u32 vm_exit_reason;
 416         u32 vm_exit_intr_info;
 417         u32 vm_exit_intr_error_code;
 418         u32 idt_vectoring_info_field;
 419         u32 idt_vectoring_error_code;
 420         u32 vm_exit_instruction_len;
 421         u32 vmx_instruction_info;
 422         u32 guest_es_limit;
 423         u32 guest_cs_limit;
 424         u32 guest_ss_limit;
 425         u32 guest_ds_limit;
 426         u32 guest_fs_limit;
 427         u32 guest_gs_limit;
 428         u32 guest_ldtr_limit;
 429         u32 guest_tr_limit;
 430         u32 guest_gdtr_limit;
 431         u32 guest_idtr_limit;
 432         u32 guest_es_ar_bytes;
 433         u32 guest_cs_ar_bytes;
 434         u32 guest_ss_ar_bytes;
 435         u32 guest_ds_ar_bytes;
 436         u32 guest_fs_ar_bytes;
 437         u32 guest_gs_ar_bytes;
 438         u32 guest_ldtr_ar_bytes;
 439         u32 guest_tr_ar_bytes;
 440         u32 guest_interruptibility_info;
 441         u32 guest_activity_state;
 442         u32 guest_sysenter_cs;
 443         u32 host_ia32_sysenter_cs;
 444         u32 vmx_preemption_timer_value;
 445         u32 padding32[7]; /* room for future expansion */
 446         u16 virtual_processor_id;
 447         u16 posted_intr_nv;
 448         u16 guest_es_selector;
 449         u16 guest_cs_selector;
 450         u16 guest_ss_selector;
 451         u16 guest_ds_selector;
 452         u16 guest_fs_selector;
 453         u16 guest_gs_selector;
 454         u16 guest_ldtr_selector;
 455         u16 guest_tr_selector;
 456         u16 guest_intr_status;
 457         u16 host_es_selector;
 458         u16 host_cs_selector;
 459         u16 host_ss_selector;
 460         u16 host_ds_selector;
 461         u16 host_fs_selector;
 462         u16 host_gs_selector;
 463         u16 host_tr_selector;
 464         u16 guest_pml_index;
 465 };
 466
 467 /*
 468  * For save/restore compatibility, the vmcs12 field offsets must not change.
 469  */
 470 #define CHECK_OFFSET(field, loc)                                \
 471         BUILD_BUG_ON_MSG(offsetof(struct vmcs12, field) != (loc),       \
 472                 "Offset of " #field " in struct vmcs12 has changed.")
 473
 474 static inline void vmx_check_vmcs12_offsets(void) {
 475         CHECK_OFFSET(revision_id, 0);
 476         CHECK_OFFSET(abort, 4);
 477         CHECK_OFFSET(launch_state, 8);
 478         CHECK_OFFSET(io_bitmap_a, 40);
 479         CHECK_OFFSET(io_bitmap_b, 48);
 480         CHECK_OFFSET(msr_bitmap, 56);
 481         CHECK_OFFSET(vm_exit_msr_store_addr, 64);
 482         CHECK_OFFSET(vm_exit_msr_load_addr, 72);
 483         CHECK_OFFSET(vm_entry_msr_load_addr, 80);
 484         CHECK_OFFSET(tsc_offset, 88);
 485         CHECK_OFFSET(virtual_apic_page_addr, 96);
 486         CHECK_OFFSET(apic_access_addr, 104);
 487         CHECK_OFFSET(posted_intr_desc_addr, 112);
 488         CHECK_OFFSET(ept_pointer, 120);
 489         CHECK_OFFSET(eoi_exit_bitmap0, 128);
 490         CHECK_OFFSET(eoi_exit_bitmap1, 136);
 491         CHECK_OFFSET(eoi_exit_bitmap2, 144);
 492         CHECK_OFFSET(eoi_exit_bitmap3, 152);
 493         CHECK_OFFSET(xss_exit_bitmap, 160);
 494         CHECK_OFFSET(guest_physical_address, 168);
 495         CHECK_OFFSET(vmcs_link_pointer, 176);
 496         CHECK_OFFSET(guest_ia32_debugctl, 184);
 497         CHECK_OFFSET(guest_ia32_pat, 192);
 498         CHECK_OFFSET(guest_ia32_efer, 200);
 499         CHECK_OFFSET(guest_ia32_perf_global_ctrl, 208);
 500         CHECK_OFFSET(guest_pdptr0, 216);
 501         CHECK_OFFSET(guest_pdptr1, 224);
 502         CHECK_OFFSET(guest_pdptr2, 232);
 503         CHECK_OFFSET(guest_pdptr3, 240);
 504         CHECK_OFFSET(guest_bndcfgs, 248);
 505         CHECK_OFFSET(host_ia32_pat, 256);
 506         CHECK_OFFSET(host_ia32_efer, 264);
 507         CHECK_OFFSET(host_ia32_perf_global_ctrl, 272);
 508         CHECK_OFFSET(vmread_bitmap, 280);
 509         CHECK_OFFSET(vmwrite_bitmap, 288);
 510         CHECK_OFFSET(vm_function_control, 296);
 511         CHECK_OFFSET(eptp_list_address, 304);
 512         CHECK_OFFSET(pml_address, 312);
 513         CHECK_OFFSET(cr0_guest_host_mask, 344);
 514         CHECK_OFFSET(cr4_guest_host_mask, 352);
 515         CHECK_OFFSET(cr0_read_shadow, 360);
 516         CHECK_OFFSET(cr4_read_shadow, 368);
 517         CHECK_OFFSET(cr3_target_value0, 376);
 518         CHECK_OFFSET(cr3_target_value1, 384);
 519         CHECK_OFFSET(cr3_target_value2, 392);
 520         CHECK_OFFSET(cr3_target_value3, 400);
 521         CHECK_OFFSET(exit_qualification, 408);
 522         CHECK_OFFSET(guest_linear_address, 416);
 523         CHECK_OFFSET(guest_cr0, 424);
 524         CHECK_OFFSET(guest_cr3, 432);
 525         CHECK_OFFSET(guest_cr4, 440);
 526         CHECK_OFFSET(guest_es_base, 448);
 527         CHECK_OFFSET(guest_cs_base, 456);
 528         CHECK_OFFSET(guest_ss_base, 464);
 529         CHECK_OFFSET(guest_ds_base, 472);
 530         CHECK_OFFSET(guest_fs_base, 480);
 531         CHECK_OFFSET(guest_gs_base, 488);
 532         CHECK_OFFSET(guest_ldtr_base, 496);
 533         CHECK_OFFSET(guest_tr_base, 504);
 534         CHECK_OFFSET(guest_gdtr_base, 512);
 535         CHECK_OFFSET(guest_idtr_base, 520);
 536         CHECK_OFFSET(guest_dr7, 528);
 537         CHECK_OFFSET(guest_rsp, 536);
 538         CHECK_OFFSET(guest_rip, 544);
 539         CHECK_OFFSET(guest_rflags, 552);
 540         CHECK_OFFSET(guest_pending_dbg_exceptions, 560);
 541         CHECK_OFFSET(guest_sysenter_esp, 568);
 542         CHECK_OFFSET(guest_sysenter_eip, 576);
 543         CHECK_OFFSET(host_cr0, 584);
 544         CHECK_OFFSET(host_cr3, 592);
 545         CHECK_OFFSET(host_cr4, 600);
 546         CHECK_OFFSET(host_fs_base, 608);
 547         CHECK_OFFSET(host_gs_base, 616);
 548         CHECK_OFFSET(host_tr_base, 624);
 549         CHECK_OFFSET(host_gdtr_base, 632);
 550         CHECK_OFFSET(host_idtr_base, 640);
 551         CHECK_OFFSET(host_ia32_sysenter_esp, 648);
 552         CHECK_OFFSET(host_ia32_sysenter_eip, 656);
 553         CHECK_OFFSET(host_rsp, 664);
 554         CHECK_OFFSET(host_rip, 672);
 555         CHECK_OFFSET(pin_based_vm_exec_control, 744);
 556         CHECK_OFFSET(cpu_based_vm_exec_control, 748);
 557         CHECK_OFFSET(exception_bitmap, 752);
 558         CHECK_OFFSET(page_fault_error_code_mask, 756);
 559         CHECK_OFFSET(page_fault_error_code_match, 760);
 560         CHECK_OFFSET(cr3_target_count, 764);
 561         CHECK_OFFSET(vm_exit_controls, 768);
 562         CHECK_OFFSET(vm_exit_msr_store_count, 772);
 563         CHECK_OFFSET(vm_exit_msr_load_count, 776);
 564         CHECK_OFFSET(vm_entry_controls, 780);
 565         CHECK_OFFSET(vm_entry_msr_load_count, 784);
 566         CHECK_OFFSET(vm_entry_intr_info_field, 788);
 567         CHECK_OFFSET(vm_entry_exception_error_code, 792);
 568         CHECK_OFFSET(vm_entry_instruction_len, 796);
 569         CHECK_OFFSET(tpr_threshold, 800);
 570         CHECK_OFFSET(secondary_vm_exec_control, 804);
 571         CHECK_OFFSET(vm_instruction_error, 808);
 572         CHECK_OFFSET(vm_exit_reason, 812);
 573         CHECK_OFFSET(vm_exit_intr_info, 816);
 574         CHECK_OFFSET(vm_exit_intr_error_code, 820);
 575         CHECK_OFFSET(idt_vectoring_info_field, 824);
 576         CHECK_OFFSET(idt_vectoring_error_code, 828);
 577         CHECK_OFFSET(vm_exit_instruction_len, 832);
 578         CHECK_OFFSET(vmx_instruction_info, 836);
 579         CHECK_OFFSET(guest_es_limit, 840);
 580         CHECK_OFFSET(guest_cs_limit, 844);
 581         CHECK_OFFSET(guest_ss_limit, 848);
 582         CHECK_OFFSET(guest_ds_limit, 852);
 583         CHECK_OFFSET(guest_fs_limit, 856);
 584         CHECK_OFFSET(guest_gs_limit, 860);
 585         CHECK_OFFSET(guest_ldtr_limit, 864);
 586         CHECK_OFFSET(guest_tr_limit, 868);
 587         CHECK_OFFSET(guest_gdtr_limit, 872);
 588         CHECK_OFFSET(guest_idtr_limit, 876);
 589         CHECK_OFFSET(guest_es_ar_bytes, 880);
 590         CHECK_OFFSET(guest_cs_ar_bytes, 884);
 591         CHECK_OFFSET(guest_ss_ar_bytes, 888);
 592         CHECK_OFFSET(guest_ds_ar_bytes, 892);
 593         CHECK_OFFSET(guest_fs_ar_bytes, 896);
 594         CHECK_OFFSET(guest_gs_ar_bytes, 900);
 595         CHECK_OFFSET(guest_ldtr_ar_bytes, 904);
 596         CHECK_OFFSET(guest_tr_ar_bytes, 908);
 597         CHECK_OFFSET(guest_interruptibility_info, 912);
 598         CHECK_OFFSET(guest_activity_state, 916);
 599         CHECK_OFFSET(guest_sysenter_cs, 920);
 600         CHECK_OFFSET(host_ia32_sysenter_cs, 924);
 601         CHECK_OFFSET(vmx_preemption_timer_value, 928);
 602         CHECK_OFFSET(virtual_processor_id, 960);
 603         CHECK_OFFSET(posted_intr_nv, 962);
 604         CHECK_OFFSET(guest_es_selector, 964);
 605         CHECK_OFFSET(guest_cs_selector, 966);
 606         CHECK_OFFSET(guest_ss_selector, 968);
 607         CHECK_OFFSET(guest_ds_selector, 970);
 608         CHECK_OFFSET(guest_fs_selector, 972);
 609         CHECK_OFFSET(guest_gs_selector, 974);
 610         CHECK_OFFSET(guest_ldtr_selector, 976);
 611         CHECK_OFFSET(guest_tr_selector, 978);
 612         CHECK_OFFSET(guest_intr_status, 980);
 613         CHECK_OFFSET(host_es_selector, 982);
 614         CHECK_OFFSET(host_cs_selector, 984);
 615         CHECK_OFFSET(host_ss_selector, 986);
 616         CHECK_OFFSET(host_ds_selector, 988);
 617         CHECK_OFFSET(host_fs_selector, 990);
 618         CHECK_OFFSET(host_gs_selector, 992);
 619         CHECK_OFFSET(host_tr_selector, 994);
 620         CHECK_OFFSET(guest_pml_index, 996);
 621 }
 622
 623 /*
 624  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 625  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 626  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 627  *
 628  * IMPORTANT: Changing this value will break save/restore compatibility with
 629  * older kvm releases.
 630  */
 631 #define VMCS12_REVISION 0x11e57ed0
 632
 633 /*
 634  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 635  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 636  * current implementation, 4K are reserved to avoid future complications.
 637  */
 638 #define VMCS12_SIZE 0x1000
 639
 640 /*
 641  * VMCS12_MAX_FIELD_INDEX is the highest index value used in any
 642  * supported VMCS12 field encoding.
 643  */
 644 #define VMCS12_MAX_FIELD_INDEX 0x17
 645
 646 struct nested_vmx_msrs {
 647         /*
 648          * We only store the "true" versions of the VMX capability MSRs. We
 649          * generate the "non-true" versions by setting the must-be-1 bits
 650          * according to the SDM.
 651          */
 652         u32 procbased_ctls_low;
 653         u32 procbased_ctls_high;
 654         u32 secondary_ctls_low;
 655         u32 secondary_ctls_high;
 656         u32 pinbased_ctls_low;
 657         u32 pinbased_ctls_high;
 658         u32 exit_ctls_low;
 659         u32 exit_ctls_high;
 660         u32 entry_ctls_low;
 661         u32 entry_ctls_high;
 662         u32 misc_low;
 663         u32 misc_high;
 664         u32 ept_caps;
 665         u32 vpid_caps;
 666         u64 basic;
 667         u64 cr0_fixed0;
 668         u64 cr0_fixed1;
 669         u64 cr4_fixed0;
 670         u64 cr4_fixed1;
 671         u64 vmcs_enum;
 672         u64 vmfunc_controls;
 673 };
 674
 675 /*
 676  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 677  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 678  */
 679 struct nested_vmx {
 680         /* Has the level1 guest done vmxon? */
 681         bool vmxon;
 682         gpa_t vmxon_ptr;
 683         bool pml_full;
 684
 685         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 686         gpa_t current_vmptr;
 687         /*
 688          * Cache of the guest's VMCS, existing outside of guest memory.
 689          * Loaded from guest memory during VMPTRLD. Flushed to guest
 690          * memory during VMCLEAR and VMPTRLD.
 691          */
 692         struct vmcs12 *cached_vmcs12;
 693         /*
 694          * Indicates if the shadow vmcs must be updated with the
 695          * data hold by vmcs12
 696          */
 697         bool sync_shadow_vmcs;
 698         bool dirty_vmcs12;
 699
 700         bool change_vmcs01_virtual_apic_mode;
 701
 702         /* L2 must run next, and mustn't decide to exit to L1. */
 703         bool nested_run_pending;
 704
 705         struct loaded_vmcs vmcs02;
 706
 707         /*
 708          * Guest pages referred to in the vmcs02 with host-physical
 709          * pointers, so we must keep them pinned while L2 runs.
 710          */
 711         struct page *apic_access_page;
 712         struct page *virtual_apic_page;
 713         struct page *pi_desc_page;
 714         struct pi_desc *pi_desc;
 715         bool pi_pending;
 716         u16 posted_intr_nv;
 717
 718         struct hrtimer preemption_timer;
 719         bool preemption_timer_expired;
 720
 721         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 722         u64 vmcs01_debugctl;
 723
 724         u16 vpid02;
 725         u16 last_vpid;
 726
 727         struct nested_vmx_msrs msrs;
 728
 729         /* SMM related state */
 730         struct {
 731                 /* in VMX operation on SMM entry? */
 732                 bool vmxon;
 733                 /* in guest mode on SMM entry? */
 734                 bool guest_mode;
 735         } smm;
 736 };
 737
 738 #define POSTED_INTR_ON  0
 739 #define POSTED_INTR_SN  1
 740
 741 /* Posted-Interrupt Descriptor */
 742 struct pi_desc {
 743         u32 pir[8];     /* Posted interrupt requested */
 744         union {
 745                 struct {
 746                                 /* bit 256 - Outstanding Notification */
 747                         u16     on      : 1,
 748                                 /* bit 257 - Suppress Notification */
 749                                 sn      : 1,
 750                                 /* bit 271:258 - Reserved */
 751                                 rsvd_1  : 14;
 752                                 /* bit 279:272 - Notification Vector */
 753                         u8      nv;
 754                                 /* bit 287:280 - Reserved */
 755                         u8      rsvd_2;
 756                                 /* bit 319:288 - Notification Destination */
 757                         u32     ndst;
 758                 };
 759                 u64 control;
 760         };
 761         u32 rsvd[6];
 762 } __aligned(64);
 763
 764 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 765 {
 766         return test_and_set_bit(POSTED_INTR_ON,
 767                         (unsigned long *)&pi_desc->control);
 768 }
 769
 770 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 771 {
 772         return test_and_clear_bit(POSTED_INTR_ON,
 773                         (unsigned long *)&pi_desc->control);
 774 }
 775
 776 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 777 {
 778         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 779 }
 780
 781 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 782 {
 783         return clear_bit(POSTED_INTR_SN,
 784                         (unsigned long *)&pi_desc->control);
 785 }
 786
 787 static inline void pi_set_sn(struct pi_desc *pi_desc)
 788 {
 789         return set_bit(POSTED_INTR_SN,
 790                         (unsigned long *)&pi_desc->control);
 791 }
 792
 793 static inline void pi_clear_on(struct pi_desc *pi_desc)
 794 {
 795         clear_bit(POSTED_INTR_ON,
 796                   (unsigned long *)&pi_desc->control);
 797 }
 798
 799 static inline int pi_test_on(struct pi_desc *pi_desc)
 800 {
 801         return test_bit(POSTED_INTR_ON,
 802                         (unsigned long *)&pi_desc->control);
 803 }
 804
 805 static inline int pi_test_sn(struct pi_desc *pi_desc)
 806 {
 807         return test_bit(POSTED_INTR_SN,
 808                         (unsigned long *)&pi_desc->control);
 809 }
 810
 811 struct vmx_msrs {
 812         unsigned int            nr;
 813         struct vmx_msr_entry    val[NR_AUTOLOAD_MSRS];
 814 };
 815
 816 struct vcpu_vmx {
 817         struct kvm_vcpu       vcpu;
 818         unsigned long         host_rsp;
 819         u8                    fail;
 820         u8                    msr_bitmap_mode;
 821         u32                   exit_intr_info;
 822         u32                   idt_vectoring_info;
 823         ulong                 rflags;
 824         struct shared_msr_entry *guest_msrs;
 825         int                   nmsrs;
 826         int                   save_nmsrs;
 827         unsigned long         host_idt_base;
 828 #ifdef CONFIG_X86_64
 829         u64                   msr_host_kernel_gs_base;
 830         u64                   msr_guest_kernel_gs_base;
 831 #endif
 832
 833         u64                   arch_capabilities;
 834         u64                   spec_ctrl;
 835
 836         u32 vm_entry_controls_shadow;
 837         u32 vm_exit_controls_shadow;
 838         u32 secondary_exec_control;
 839
 840         /*
 841          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 842          * non-nested (L1) guest, it always points to vmcs01. For a nested
 843          * guest (L2), it points to a different VMCS.
 844          */
 845         struct loaded_vmcs    vmcs01;
 846         struct loaded_vmcs   *loaded_vmcs;
 847         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 848         struct msr_autoload {
 849                 struct vmx_msrs guest;
 850                 struct vmx_msrs host;
 851         } msr_autoload;
 852         struct {
 853                 int           loaded;
 854                 u16           fs_sel, gs_sel, ldt_sel;
 855 #ifdef CONFIG_X86_64
 856                 u16           ds_sel, es_sel;
 857 #endif
 858                 int           gs_ldt_reload_needed;
 859                 int           fs_reload_needed;
 860                 u64           msr_host_bndcfgs;
 861         } host_state;
 862         struct {
 863                 int vm86_active;
 864                 ulong save_rflags;
 865                 struct kvm_segment segs[8];
 866         } rmode;
 867         struct {
 868                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 869                 struct kvm_save_segment {
 870                         u16 selector;
 871                         unsigned long base;
 872                         u32 limit;
 873                         u32 ar;
 874                 } seg[8];
 875         } segment_cache;
 876         int vpid;
 877         bool emulation_required;
 878
 879         u32 exit_reason;
 880
 881         /* Posted interrupt descriptor */
 882         struct pi_desc pi_desc;
 883
 884         /* Support for a guest hypervisor (nested VMX) */
 885         struct nested_vmx nested;
 886
 887         /* Dynamic PLE window. */
 888         int ple_window;
 889         bool ple_window_dirty;
 890
 891         /* Support for PML */
 892 #define PML_ENTITY_NUM          512
 893         struct page *pml_pg;
 894
 895         /* apic deadline value in host tsc */
 896         u64 hv_deadline_tsc;
 897
 898         u64 current_tsc_ratio;
 899
 900         u32 host_pkru;
 901
 902         unsigned long host_debugctlmsr;
 903
 904         /*
 905          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 906          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 907          * in msr_ia32_feature_control_valid_bits.
 908          */
 909         u64 msr_ia32_feature_control;
 910         u64 msr_ia32_feature_control_valid_bits;
 911 };
 912
 913 enum segment_cache_field {
 914         SEG_FIELD_SEL = 0,
 915         SEG_FIELD_BASE = 1,
 916         SEG_FIELD_LIMIT = 2,
 917         SEG_FIELD_AR = 3,
 918
 919         SEG_FIELD_NR = 4
 920 };
 921
 922 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
 923 {
 924         return container_of(kvm, struct kvm_vmx, kvm);
 925 }
 926
 927 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 928 {
 929         return container_of(vcpu, struct vcpu_vmx, vcpu);
 930 }
 931
 932 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 933 {
 934         return &(to_vmx(vcpu)->pi_desc);
 935 }
 936
 937 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
 938 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 939 #define FIELD(number, name)     [ROL16(number, 6)] = VMCS12_OFFSET(name)
 940 #define FIELD64(number, name)                                           \
 941         FIELD(number, name),                                            \
 942         [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
 943
 944
 945 static u16 shadow_read_only_fields[] = {
 946 #define SHADOW_FIELD_RO(x) x,
 947 #include "vmx_shadow_fields.h"
 948 };
 949 static int max_shadow_read_only_fields =
 950         ARRAY_SIZE(shadow_read_only_fields);
 951
 952 static u16 shadow_read_write_fields[] = {
 953 #define SHADOW_FIELD_RW(x) x,
 954 #include "vmx_shadow_fields.h"
 955 };
 956 static int max_shadow_read_write_fields =
 957         ARRAY_SIZE(shadow_read_write_fields);
 958
 959 static const unsigned short vmcs_field_to_offset_table[] = {
 960         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 961         FIELD(POSTED_INTR_NV, posted_intr_nv),
 962         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 963         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 964         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 965         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 966         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 967         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 968         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 969         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 970         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 971         FIELD(GUEST_PML_INDEX, guest_pml_index),
 972         FIELD(HOST_ES_SELECTOR, host_es_selector),
 973         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 974         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 975         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 976         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 977         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 978         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 979         FIELD64(IO_BITMAP_A, io_bitmap_a),
 980         FIELD64(IO_BITMAP_B, io_bitmap_b),
 981         FIELD64(MSR_BITMAP, msr_bitmap),
 982         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 983         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 984         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 985         FIELD64(PML_ADDRESS, pml_address),
 986         FIELD64(TSC_OFFSET, tsc_offset),
 987         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 988         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 989         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 990         FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
 991         FIELD64(EPT_POINTER, ept_pointer),
 992         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 993         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 994         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 995         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 996         FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
 997         FIELD64(VMREAD_BITMAP, vmread_bitmap),
 998         FIELD64(VMWRITE_BITMAP, vmwrite_bitmap),
 999         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
1000         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
1001         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
1002         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
1003         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
1004         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
1005         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
1006         FIELD64(GUEST_PDPTR0, guest_pdptr0),
1007         FIELD64(GUEST_PDPTR1, guest_pdptr1),
1008         FIELD64(GUEST_PDPTR2, guest_pdptr2),
1009         FIELD64(GUEST_PDPTR3, guest_pdptr3),
1010         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
1011         FIELD64(HOST_IA32_PAT, host_ia32_pat),
1012         FIELD64(HOST_IA32_EFER, host_ia32_efer),
1013         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
1014         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
1015         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
1016         FIELD(EXCEPTION_BITMAP, exception_bitmap),
1017         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
1018         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
1019         FIELD(CR3_TARGET_COUNT, cr3_target_count),
1020         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
1021         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
1022         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
1023         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
1024         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
1025         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
1026         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
1027         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
1028         FIELD(TPR_THRESHOLD, tpr_threshold),
1029         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
1030         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
1031         FIELD(VM_EXIT_REASON, vm_exit_reason),
1032         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
1033         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
1034         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
1035         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
1036         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
1037         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
1038         FIELD(GUEST_ES_LIMIT, guest_es_limit),
1039         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
1040         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
1041         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
1042         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
1043         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
1044         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
1045         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
1046         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
1047         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
1048         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
1049         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
1050         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
1051         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
1052         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
1053         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
1054         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
1055         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
1056         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
1057         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
1058         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
1059         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
1060         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
1061         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
1062         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
1063         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
1064         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
1065         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
1066         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
1067         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
1068         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
1069         FIELD(EXIT_QUALIFICATION, exit_qualification),
1070         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
1071         FIELD(GUEST_CR0, guest_cr0),
1072         FIELD(GUEST_CR3, guest_cr3),
1073         FIELD(GUEST_CR4, guest_cr4),
1074         FIELD(GUEST_ES_BASE, guest_es_base),
1075         FIELD(GUEST_CS_BASE, guest_cs_base),
1076         FIELD(GUEST_SS_BASE, guest_ss_base),
1077         FIELD(GUEST_DS_BASE, guest_ds_base),
1078         FIELD(GUEST_FS_BASE, guest_fs_base),
1079         FIELD(GUEST_GS_BASE, guest_gs_base),
1080         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
1081         FIELD(GUEST_TR_BASE, guest_tr_base),
1082         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
1083         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
1084         FIELD(GUEST_DR7, guest_dr7),
1085         FIELD(GUEST_RSP, guest_rsp),
1086         FIELD(GUEST_RIP, guest_rip),
1087         FIELD(GUEST_RFLAGS, guest_rflags),
1088         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
1089         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
1090         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
1091         FIELD(HOST_CR0, host_cr0),
1092         FIELD(HOST_CR3, host_cr3),
1093         FIELD(HOST_CR4, host_cr4),
1094         FIELD(HOST_FS_BASE, host_fs_base),
1095         FIELD(HOST_GS_BASE, host_gs_base),
1096         FIELD(HOST_TR_BASE, host_tr_base),
1097         FIELD(HOST_GDTR_BASE, host_gdtr_base),
1098         FIELD(HOST_IDTR_BASE, host_idtr_base),
1099         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
1100         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
1101         FIELD(HOST_RSP, host_rsp),
1102         FIELD(HOST_RIP, host_rip),
1103 };
1104
1105 static inline short vmcs_field_to_offset(unsigned long field)
1106 {
1107         const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
1108         unsigned short offset;
1109         unsigned index;
1110
1111         if (field >> 15)
1112                 return -ENOENT;
1113
1114         index = ROL16(field, 6);
1115         if (index >= size)
1116                 return -ENOENT;
1117
1118         index = array_index_nospec(index, size);
1119         offset = vmcs_field_to_offset_table[index];
1120         if (offset == 0)
1121                 return -ENOENT;
1122         return offset;
1123 }
1124
1125 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
1126 {
1127         return to_vmx(vcpu)->nested.cached_vmcs12;
1128 }
1129
1130 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
1131 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
1132 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
1133 static bool vmx_xsaves_supported(void);
1134 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1135                             struct kvm_segment *var, int seg);
1136 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1137                             struct kvm_segment *var, int seg);
1138 static bool guest_state_valid(struct kvm_vcpu *vcpu);
1139 static u32 vmx_segment_access_rights(struct kvm_segment *var);
1140 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
1141 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
1142 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
1143 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
1144                                             u16 error_code);
1145 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
1146 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
1147                                                           u32 msr, int type);
1148
1149 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
1150 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
1151 /*
1152  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
1153  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
1154  */
1155 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
1156
1157 /*
1158  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
1159  * can find which vCPU should be waken up.
1160  */
1161 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
1162 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
1163
1164 enum {
1165         VMX_VMREAD_BITMAP,
1166         VMX_VMWRITE_BITMAP,
1167         VMX_BITMAP_NR
1168 };
1169
1170 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
1171
1172 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
1173 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
1174
1175 static bool cpu_has_load_ia32_efer;
1176 static bool cpu_has_load_perf_global_ctrl;
1177
1178 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
1179 static DEFINE_SPINLOCK(vmx_vpid_lock);
1180
1181 static struct vmcs_config {
1182         int size;
1183         int order;
1184         u32 basic_cap;
1185         u32 revision_id;
1186         u32 pin_based_exec_ctrl;
1187         u32 cpu_based_exec_ctrl;
1188         u32 cpu_based_2nd_exec_ctrl;
1189         u32 vmexit_ctrl;
1190         u32 vmentry_ctrl;
1191         struct nested_vmx_msrs nested;
1192 } vmcs_config;
1193
1194 static struct vmx_capability {
1195         u32 ept;
1196         u32 vpid;
1197 } vmx_capability;
1198
1199 #define VMX_SEGMENT_FIELD(seg)                                  \
1200         [VCPU_SREG_##seg] = {                                   \
1201                 .selector = GUEST_##seg##_SELECTOR,             \
1202                 .base = GUEST_##seg##_BASE,                     \
1203                 .limit = GUEST_##seg##_LIMIT,                   \
1204                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1205         }
1206
1207 static const struct kvm_vmx_segment_field {
1208         unsigned selector;
1209         unsigned base;
1210         unsigned limit;
1211         unsigned ar_bytes;
1212 } kvm_vmx_segment_fields[] = {
1213         VMX_SEGMENT_FIELD(CS),
1214         VMX_SEGMENT_FIELD(DS),
1215         VMX_SEGMENT_FIELD(ES),
1216         VMX_SEGMENT_FIELD(FS),
1217         VMX_SEGMENT_FIELD(GS),
1218         VMX_SEGMENT_FIELD(SS),
1219         VMX_SEGMENT_FIELD(TR),
1220         VMX_SEGMENT_FIELD(LDTR),
1221 };
1222
1223 static u64 host_efer;
1224
1225 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1226
1227 /*
1228  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1229  * away by decrementing the array size.
1230  */
1231 static const u32 vmx_msr_index[] = {
1232 #ifdef CONFIG_X86_64
1233         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1234 #endif
1235         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1236 };
1237
1238 DEFINE_STATIC_KEY_FALSE(enable_evmcs);
1239
1240 #define current_evmcs ((struct hv_enlightened_vmcs *)this_cpu_read(current_vmcs))
1241
1242 #define KVM_EVMCS_VERSION 1
1243
1244 #if IS_ENABLED(CONFIG_HYPERV)
1245 static bool __read_mostly enlightened_vmcs = true;
1246 module_param(enlightened_vmcs, bool, 0444);
1247
1248 static inline void evmcs_write64(unsigned long field, u64 value)
1249 {
1250         u16 clean_field;
1251         int offset = get_evmcs_offset(field, &clean_field);
1252
1253         if (offset < 0)
1254                 return;
1255
1256         *(u64 *)((char *)current_evmcs + offset) = value;
1257
1258         current_evmcs->hv_clean_fields &= ~clean_field;
1259 }
1260
1261 static inline void evmcs_write32(unsigned long field, u32 value)
1262 {
1263         u16 clean_field;
1264         int offset = get_evmcs_offset(field, &clean_field);
1265
1266         if (offset < 0)
1267                 return;
1268
1269         *(u32 *)((char *)current_evmcs + offset) = value;
1270         current_evmcs->hv_clean_fields &= ~clean_field;
1271 }
1272
1273 static inline void evmcs_write16(unsigned long field, u16 value)
1274 {
1275         u16 clean_field;
1276         int offset = get_evmcs_offset(field, &clean_field);
1277
1278         if (offset < 0)
1279                 return;
1280
1281         *(u16 *)((char *)current_evmcs + offset) = value;
1282         current_evmcs->hv_clean_fields &= ~clean_field;
1283 }
1284
1285 static inline u64 evmcs_read64(unsigned long field)
1286 {
1287         int offset = get_evmcs_offset(field, NULL);
1288
1289         if (offset < 0)
1290                 return 0;
1291
1292         return *(u64 *)((char *)current_evmcs + offset);
1293 }
1294
1295 static inline u32 evmcs_read32(unsigned long field)
1296 {
1297         int offset = get_evmcs_offset(field, NULL);
1298
1299         if (offset < 0)
1300                 return 0;
1301
1302         return *(u32 *)((char *)current_evmcs + offset);
1303 }
1304
1305 static inline u16 evmcs_read16(unsigned long field)
1306 {
1307         int offset = get_evmcs_offset(field, NULL);
1308
1309         if (offset < 0)
1310                 return 0;
1311
1312         return *(u16 *)((char *)current_evmcs + offset);
1313 }
1314
1315 static inline void evmcs_touch_msr_bitmap(void)
1316 {
1317         if (unlikely(!current_evmcs))
1318                 return;
1319
1320         if (current_evmcs->hv_enlightenments_control.msr_bitmap)
1321                 current_evmcs->hv_clean_fields &=
1322                         ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP;
1323 }
1324
1325 static void evmcs_load(u64 phys_addr)
1326 {
1327         struct hv_vp_assist_page *vp_ap =
1328                 hv_get_vp_assist_page(smp_processor_id());
1329
1330         vp_ap->current_nested_vmcs = phys_addr;
1331         vp_ap->enlighten_vmentry = 1;
1332 }
1333
1334 static void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf)
1335 {
1336         /*
1337          * Enlightened VMCSv1 doesn't support these:
1338          *
1339          *      POSTED_INTR_NV                  = 0x00000002,
1340          *      GUEST_INTR_STATUS               = 0x00000810,
1341          *      APIC_ACCESS_ADDR                = 0x00002014,
1342          *      POSTED_INTR_DESC_ADDR           = 0x00002016,
1343          *      EOI_EXIT_BITMAP0                = 0x0000201c,
1344          *      EOI_EXIT_BITMAP1                = 0x0000201e,
1345          *      EOI_EXIT_BITMAP2                = 0x00002020,
1346          *      EOI_EXIT_BITMAP3                = 0x00002022,
1347          */
1348         vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
1349         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1350                 ~SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1351         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1352                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1353         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1354                 ~SECONDARY_EXEC_APIC_REGISTER_VIRT;
1355
1356         /*
1357          *      GUEST_PML_INDEX                 = 0x00000812,
1358          *      PML_ADDRESS                     = 0x0000200e,
1359          */
1360         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_PML;
1361
1362         /*      VM_FUNCTION_CONTROL             = 0x00002018, */
1363         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_VMFUNC;
1364
1365         /*
1366          *      EPTP_LIST_ADDRESS               = 0x00002024,
1367          *      VMREAD_BITMAP                   = 0x00002026,
1368          *      VMWRITE_BITMAP                  = 0x00002028,
1369          */
1370         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_SHADOW_VMCS;
1371
1372         /*
1373          *      TSC_MULTIPLIER                  = 0x00002032,
1374          */
1375         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_TSC_SCALING;
1376
1377         /*
1378          *      PLE_GAP                         = 0x00004020,
1379          *      PLE_WINDOW                      = 0x00004022,
1380          */
1381         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1382
1383         /*
1384          *      VMX_PREEMPTION_TIMER_VALUE      = 0x0000482E,
1385          */
1386         vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
1387
1388         /*
1389          *      GUEST_IA32_PERF_GLOBAL_CTRL     = 0x00002808,
1390          *      HOST_IA32_PERF_GLOBAL_CTRL      = 0x00002c04,
1391          */
1392         vmcs_conf->vmexit_ctrl &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
1393         vmcs_conf->vmentry_ctrl &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
1394
1395         /*
1396          * Currently unsupported in KVM:
1397          *      GUEST_IA32_RTIT_CTL             = 0x00002814,
1398          */
1399 }
1400 #else /* !IS_ENABLED(CONFIG_HYPERV) */
1401 static inline void evmcs_write64(unsigned long field, u64 value) {}
1402 static inline void evmcs_write32(unsigned long field, u32 value) {}
1403 static inline void evmcs_write16(unsigned long field, u16 value) {}
1404 static inline u64 evmcs_read64(unsigned long field) { return 0; }
1405 static inline u32 evmcs_read32(unsigned long field) { return 0; }
1406 static inline u16 evmcs_read16(unsigned long field) { return 0; }
1407 static inline void evmcs_load(u64 phys_addr) {}
1408 static inline void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf) {}
1409 static inline void evmcs_touch_msr_bitmap(void) {}
1410 #endif /* IS_ENABLED(CONFIG_HYPERV) */
1411
1412 static inline bool is_exception_n(u32 intr_info, u8 vector)
1413 {
1414         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1415                              INTR_INFO_VALID_MASK)) ==
1416                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1417 }
1418
1419 static inline bool is_debug(u32 intr_info)
1420 {
1421         return is_exception_n(intr_info, DB_VECTOR);
1422 }
1423
1424 static inline bool is_breakpoint(u32 intr_info)
1425 {
1426         return is_exception_n(intr_info, BP_VECTOR);
1427 }
1428
1429 static inline bool is_page_fault(u32 intr_info)
1430 {
1431         return is_exception_n(intr_info, PF_VECTOR);
1432 }
1433
1434 static inline bool is_no_device(u32 intr_info)
1435 {
1436         return is_exception_n(intr_info, NM_VECTOR);
1437 }
1438
1439 static inline bool is_invalid_opcode(u32 intr_info)
1440 {
1441         return is_exception_n(intr_info, UD_VECTOR);
1442 }
1443
1444 static inline bool is_gp_fault(u32 intr_info)
1445 {
1446         return is_exception_n(intr_info, GP_VECTOR);
1447 }
1448
1449 static inline bool is_external_interrupt(u32 intr_info)
1450 {
1451         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1452                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1453 }
1454
1455 static inline bool is_machine_check(u32 intr_info)
1456 {
1457         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1458                              INTR_INFO_VALID_MASK)) ==
1459                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1460 }
1461
1462 /* Undocumented: icebp/int1 */
1463 static inline bool is_icebp(u32 intr_info)
1464 {
1465         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1466                 == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
1467 }
1468
1469 static inline bool cpu_has_vmx_msr_bitmap(void)
1470 {
1471         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1472 }
1473
1474 static inline bool cpu_has_vmx_tpr_shadow(void)
1475 {
1476         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1477 }
1478
1479 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1480 {
1481         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1482 }
1483
1484 static inline bool cpu_has_secondary_exec_ctrls(void)
1485 {
1486         return vmcs_config.cpu_based_exec_ctrl &
1487                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1488 }
1489
1490 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1491 {
1492         return vmcs_config.cpu_based_2nd_exec_ctrl &
1493                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1494 }
1495
1496 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1497 {
1498         return vmcs_config.cpu_based_2nd_exec_ctrl &
1499                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1500 }
1501
1502 static inline bool cpu_has_vmx_apic_register_virt(void)
1503 {
1504         return vmcs_config.cpu_based_2nd_exec_ctrl &
1505                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1506 }
1507
1508 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1509 {
1510         return vmcs_config.cpu_based_2nd_exec_ctrl &
1511                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1512 }
1513
1514 /*
1515  * Comment's format: document - errata name - stepping - processor name.
1516  * Refer from
1517  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1518  */
1519 static u32 vmx_preemption_cpu_tfms[] = {
1520 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1521 0x000206E6,
1522 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1523 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1524 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1525 0x00020652,
1526 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1527 0x00020655,
1528 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1529 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1530 /*
1531  * 320767.pdf - AAP86  - B1 -
1532  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1533  */
1534 0x000106E5,
1535 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1536 0x000106A0,
1537 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1538 0x000106A1,
1539 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1540 0x000106A4,
1541  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1542  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1543  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1544 0x000106A5,
1545 };
1546
1547 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1548 {
1549         u32 eax = cpuid_eax(0x00000001), i;
1550
1551         /* Clear the reserved bits */
1552         eax &= ~(0x3U << 14 | 0xfU << 28);
1553         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1554                 if (eax == vmx_preemption_cpu_tfms[i])
1555                         return true;
1556
1557         return false;
1558 }
1559
1560 static inline bool cpu_has_vmx_preemption_timer(void)
1561 {
1562         return vmcs_config.pin_based_exec_ctrl &
1563                 PIN_BASED_VMX_PREEMPTION_TIMER;
1564 }
1565
1566 static inline bool cpu_has_vmx_posted_intr(void)
1567 {
1568         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1569                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1570 }
1571
1572 static inline bool cpu_has_vmx_apicv(void)
1573 {
1574         return cpu_has_vmx_apic_register_virt() &&
1575                 cpu_has_vmx_virtual_intr_delivery() &&
1576                 cpu_has_vmx_posted_intr();
1577 }
1578
1579 static inline bool cpu_has_vmx_flexpriority(void)
1580 {
1581         return cpu_has_vmx_tpr_shadow() &&
1582                 cpu_has_vmx_virtualize_apic_accesses();
1583 }
1584
1585 static inline bool cpu_has_vmx_ept_execute_only(void)
1586 {
1587         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1588 }
1589
1590 static inline bool cpu_has_vmx_ept_2m_page(void)
1591 {
1592         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1593 }
1594
1595 static inline bool cpu_has_vmx_ept_1g_page(void)
1596 {
1597         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1598 }
1599
1600 static inline bool cpu_has_vmx_ept_4levels(void)
1601 {
1602         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1603 }
1604
1605 static inline bool cpu_has_vmx_ept_mt_wb(void)
1606 {
1607         return vmx_capability.ept & VMX_EPTP_WB_BIT;
1608 }
1609
1610 static inline bool cpu_has_vmx_ept_5levels(void)
1611 {
1612         return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1613 }
1614
1615 static inline bool cpu_has_vmx_ept_ad_bits(void)
1616 {
1617         return vmx_capability.ept & VMX_EPT_AD_BIT;
1618 }
1619
1620 static inline bool cpu_has_vmx_invept_context(void)
1621 {
1622         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1623 }
1624
1625 static inline bool cpu_has_vmx_invept_global(void)
1626 {
1627         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1628 }
1629
1630 static inline bool cpu_has_vmx_invvpid_individual_addr(void)
1631 {
1632         return vmx_capability.vpid & VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT;
1633 }
1634
1635 static inline bool cpu_has_vmx_invvpid_single(void)
1636 {
1637         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1638 }
1639
1640 static inline bool cpu_has_vmx_invvpid_global(void)
1641 {
1642         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1643 }
1644
1645 static inline bool cpu_has_vmx_invvpid(void)
1646 {
1647         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1648 }
1649
1650 static inline bool cpu_has_vmx_ept(void)
1651 {
1652         return vmcs_config.cpu_based_2nd_exec_ctrl &
1653                 SECONDARY_EXEC_ENABLE_EPT;
1654 }
1655
1656 static inline bool cpu_has_vmx_unrestricted_guest(void)
1657 {
1658         return vmcs_config.cpu_based_2nd_exec_ctrl &
1659                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1660 }
1661
1662 static inline bool cpu_has_vmx_ple(void)
1663 {
1664         return vmcs_config.cpu_based_2nd_exec_ctrl &
1665                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1666 }
1667
1668 static inline bool cpu_has_vmx_basic_inout(void)
1669 {
1670         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1671 }
1672
1673 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1674 {
1675         return flexpriority_enabled && lapic_in_kernel(vcpu);
1676 }
1677
1678 static inline bool cpu_has_vmx_vpid(void)
1679 {
1680         return vmcs_config.cpu_based_2nd_exec_ctrl &
1681                 SECONDARY_EXEC_ENABLE_VPID;
1682 }
1683
1684 static inline bool cpu_has_vmx_rdtscp(void)
1685 {
1686         return vmcs_config.cpu_based_2nd_exec_ctrl &
1687                 SECONDARY_EXEC_RDTSCP;
1688 }
1689
1690 static inline bool cpu_has_vmx_invpcid(void)
1691 {
1692         return vmcs_config.cpu_based_2nd_exec_ctrl &
1693                 SECONDARY_EXEC_ENABLE_INVPCID;
1694 }
1695
1696 static inline bool cpu_has_virtual_nmis(void)
1697 {
1698         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1699 }
1700
1701 static inline bool cpu_has_vmx_wbinvd_exit(void)
1702 {
1703         return vmcs_config.cpu_based_2nd_exec_ctrl &
1704                 SECONDARY_EXEC_WBINVD_EXITING;
1705 }
1706
1707 static inline bool cpu_has_vmx_shadow_vmcs(void)
1708 {
1709         u64 vmx_msr;
1710         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1711         /* check if the cpu supports writing r/o exit information fields */
1712         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1713                 return false;
1714
1715         return vmcs_config.cpu_based_2nd_exec_ctrl &
1716                 SECONDARY_EXEC_SHADOW_VMCS;
1717 }
1718
1719 static inline bool cpu_has_vmx_pml(void)
1720 {
1721         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1722 }
1723
1724 static inline bool cpu_has_vmx_tsc_scaling(void)
1725 {
1726         return vmcs_config.cpu_based_2nd_exec_ctrl &
1727                 SECONDARY_EXEC_TSC_SCALING;
1728 }
1729
1730 static inline bool cpu_has_vmx_vmfunc(void)
1731 {
1732         return vmcs_config.cpu_based_2nd_exec_ctrl &
1733                 SECONDARY_EXEC_ENABLE_VMFUNC;
1734 }
1735
1736 static bool vmx_umip_emulated(void)
1737 {
1738         return vmcs_config.cpu_based_2nd_exec_ctrl &
1739                 SECONDARY_EXEC_DESC;
1740 }
1741
1742 static inline bool report_flexpriority(void)
1743 {
1744         return flexpriority_enabled;
1745 }
1746
1747 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1748 {
1749         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low);
1750 }
1751
1752 /*
1753  * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE
1754  * to modify any valid field of the VMCS, or are the VM-exit
1755  * information fields read-only?
1756  */
1757 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu)
1758 {
1759         return to_vmx(vcpu)->nested.msrs.misc_low &
1760                 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS;
1761 }
1762
1763 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1764 {
1765         return vmcs12->cpu_based_vm_exec_control & bit;
1766 }
1767
1768 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1769 {
1770         return (vmcs12->cpu_based_vm_exec_control &
1771                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1772                 (vmcs12->secondary_vm_exec_control & bit);
1773 }
1774
1775 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1776 {
1777         return vmcs12->pin_based_vm_exec_control &
1778                 PIN_BASED_VMX_PREEMPTION_TIMER;
1779 }
1780
1781 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12)
1782 {
1783         return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING;
1784 }
1785
1786 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1787 {
1788         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1789 }
1790
1791 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1792 {
1793         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1794 }
1795
1796 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1797 {
1798         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
1799 }
1800
1801 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1802 {
1803         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1804 }
1805
1806 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1807 {
1808         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1809 }
1810
1811 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1812 {
1813         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1814 }
1815
1816 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1817 {
1818         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1819 }
1820
1821 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1822 {
1823         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1824 }
1825
1826 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1827 {
1828         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1829 }
1830
1831 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1832 {
1833         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1834 }
1835
1836 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1837 {
1838         return nested_cpu_has_vmfunc(vmcs12) &&
1839                 (vmcs12->vm_function_control &
1840                  VMX_VMFUNC_EPTP_SWITCHING);
1841 }
1842
1843 static inline bool is_nmi(u32 intr_info)
1844 {
1845         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1846                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1847 }
1848
1849 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1850                               u32 exit_intr_info,
1851                               unsigned long exit_qualification);
1852 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1853                         struct vmcs12 *vmcs12,
1854                         u32 reason, unsigned long qualification);
1855
1856 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1857 {
1858         int i;
1859
1860         for (i = 0; i < vmx->nmsrs; ++i)
1861                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1862                         return i;
1863         return -1;
1864 }
1865
1866 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1867 {
1868     struct {
1869         u64 vpid : 16;
1870         u64 rsvd : 48;
1871         u64 gva;
1872     } operand = { vpid, 0, gva };
1873
1874     asm volatile (__ex(ASM_VMX_INVVPID)
1875                   /* CF==1 or ZF==1 --> rc = -1 */
1876                   "; ja 1f ; ud2 ; 1:"
1877                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1878 }
1879
1880 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1881 {
1882         struct {
1883                 u64 eptp, gpa;
1884         } operand = {eptp, gpa};
1885
1886         asm volatile (__ex(ASM_VMX_INVEPT)
1887                         /* CF==1 or ZF==1 --> rc = -1 */
1888                         "; ja 1f ; ud2 ; 1:\n"
1889                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1890 }
1891
1892 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1893 {
1894         int i;
1895
1896         i = __find_msr_index(vmx, msr);
1897         if (i >= 0)
1898                 return &vmx->guest_msrs[i];
1899         return NULL;
1900 }
1901
1902 static void vmcs_clear(struct vmcs *vmcs)
1903 {
1904         u64 phys_addr = __pa(vmcs);
1905         u8 error;
1906
1907         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1908                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1909                       : "cc", "memory");
1910         if (error)
1911                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1912                        vmcs, phys_addr);
1913 }
1914
1915 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1916 {
1917         vmcs_clear(loaded_vmcs->vmcs);
1918         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1919                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1920         loaded_vmcs->cpu = -1;
1921         loaded_vmcs->launched = 0;
1922 }
1923
1924 static void vmcs_load(struct vmcs *vmcs)
1925 {
1926         u64 phys_addr = __pa(vmcs);
1927         u8 error;
1928
1929         if (static_branch_unlikely(&enable_evmcs))
1930                 return evmcs_load(phys_addr);
1931
1932         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1933                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1934                         : "cc", "memory");
1935         if (error)
1936                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1937                        vmcs, phys_addr);
1938 }
1939
1940 #ifdef CONFIG_KEXEC_CORE
1941 /*
1942  * This bitmap is used to indicate whether the vmclear
1943  * operation is enabled on all cpus. All disabled by
1944  * default.
1945  */
1946 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1947
1948 static inline void crash_enable_local_vmclear(int cpu)
1949 {
1950         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1951 }
1952
1953 static inline void crash_disable_local_vmclear(int cpu)
1954 {
1955         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1956 }
1957
1958 static inline int crash_local_vmclear_enabled(int cpu)
1959 {
1960         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1961 }
1962
1963 static void crash_vmclear_local_loaded_vmcss(void)
1964 {
1965         int cpu = raw_smp_processor_id();
1966         struct loaded_vmcs *v;
1967
1968         if (!crash_local_vmclear_enabled(cpu))
1969                 return;
1970
1971         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1972                             loaded_vmcss_on_cpu_link)
1973                 vmcs_clear(v->vmcs);
1974 }
1975 #else
1976 static inline void crash_enable_local_vmclear(int cpu) { }
1977 static inline void crash_disable_local_vmclear(int cpu) { }
1978 #endif /* CONFIG_KEXEC_CORE */
1979
1980 static void __loaded_vmcs_clear(void *arg)
1981 {
1982         struct loaded_vmcs *loaded_vmcs = arg;
1983         int cpu = raw_smp_processor_id();
1984
1985         if (loaded_vmcs->cpu != cpu)
1986                 return; /* vcpu migration can race with cpu offline */
1987         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1988                 per_cpu(current_vmcs, cpu) = NULL;
1989         crash_disable_local_vmclear(cpu);
1990         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1991
1992         /*
1993          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1994          * is before setting loaded_vmcs->vcpu to -1 which is done in
1995          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1996          * then adds the vmcs into percpu list before it is deleted.
1997          */
1998         smp_wmb();
1999
2000         loaded_vmcs_init(loaded_vmcs);
2001         crash_enable_local_vmclear(cpu);
2002 }
2003
2004 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
2005 {
2006         int cpu = loaded_vmcs->cpu;
2007
2008         if (cpu != -1)
2009                 smp_call_function_single(cpu,
2010                          __loaded_vmcs_clear, loaded_vmcs, 1);
2011 }
2012
2013 static inline void vpid_sync_vcpu_single(int vpid)
2014 {
2015         if (vpid == 0)
2016                 return;
2017
2018         if (cpu_has_vmx_invvpid_single())
2019                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
2020 }
2021
2022 static inline void vpid_sync_vcpu_global(void)
2023 {
2024         if (cpu_has_vmx_invvpid_global())
2025                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
2026 }
2027
2028 static inline void vpid_sync_context(int vpid)
2029 {
2030         if (cpu_has_vmx_invvpid_single())
2031                 vpid_sync_vcpu_single(vpid);
2032         else
2033                 vpid_sync_vcpu_global();
2034 }
2035
2036 static inline void ept_sync_global(void)
2037 {
2038         __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
2039 }
2040
2041 static inline void ept_sync_context(u64 eptp)
2042 {
2043         if (cpu_has_vmx_invept_context())
2044                 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
2045         else
2046                 ept_sync_global();
2047 }
2048
2049 static __always_inline void vmcs_check16(unsigned long field)
2050 {
2051         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2052                          "16-bit accessor invalid for 64-bit field");
2053         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2054                          "16-bit accessor invalid for 64-bit high field");
2055         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2056                          "16-bit accessor invalid for 32-bit high field");
2057         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2058                          "16-bit accessor invalid for natural width field");
2059 }
2060
2061 static __always_inline void vmcs_check32(unsigned long field)
2062 {
2063         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2064                          "32-bit accessor invalid for 16-bit field");
2065         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2066                          "32-bit accessor invalid for natural width field");
2067 }
2068
2069 static __always_inline void vmcs_check64(unsigned long field)
2070 {
2071         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2072                          "64-bit accessor invalid for 16-bit field");
2073         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2074                          "64-bit accessor invalid for 64-bit high field");
2075         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2076                          "64-bit accessor invalid for 32-bit field");
2077         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2078                          "64-bit accessor invalid for natural width field");
2079 }
2080
2081 static __always_inline void vmcs_checkl(unsigned long field)
2082 {
2083         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2084                          "Natural width accessor invalid for 16-bit field");
2085         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2086                          "Natural width accessor invalid for 64-bit field");
2087         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2088                          "Natural width accessor invalid for 64-bit high field");
2089         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2090                          "Natural width accessor invalid for 32-bit field");
2091 }
2092
2093 static __always_inline unsigned long __vmcs_readl(unsigned long field)
2094 {
2095         unsigned long value;
2096
2097         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
2098                       : "=a"(value) : "d"(field) : "cc");
2099         return value;
2100 }
2101
2102 static __always_inline u16 vmcs_read16(unsigned long field)
2103 {
2104         vmcs_check16(field);
2105         if (static_branch_unlikely(&enable_evmcs))
2106                 return evmcs_read16(field);
2107         return __vmcs_readl(field);
2108 }
2109
2110 static __always_inline u32 vmcs_read32(unsigned long field)
2111 {
2112         vmcs_check32(field);
2113         if (static_branch_unlikely(&enable_evmcs))
2114                 return evmcs_read32(field);
2115         return __vmcs_readl(field);
2116 }
2117
2118 static __always_inline u64 vmcs_read64(unsigned long field)
2119 {
2120         vmcs_check64(field);
2121         if (static_branch_unlikely(&enable_evmcs))
2122                 return evmcs_read64(field);
2123 #ifdef CONFIG_X86_64
2124         return __vmcs_readl(field);
2125 #else
2126         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
2127 #endif
2128 }
2129
2130 static __always_inline unsigned long vmcs_readl(unsigned long field)
2131 {
2132         vmcs_checkl(field);
2133         if (static_branch_unlikely(&enable_evmcs))
2134                 return evmcs_read64(field);
2135         return __vmcs_readl(field);
2136 }
2137
2138 static noinline void vmwrite_error(unsigned long field, unsigned long value)
2139 {
2140         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
2141                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
2142         dump_stack();
2143 }
2144
2145 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
2146 {
2147         u8 error;
2148
2149         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
2150                        : "=q"(error) : "a"(value), "d"(field) : "cc");
2151         if (unlikely(error))
2152                 vmwrite_error(field, value);
2153 }
2154
2155 static __always_inline void vmcs_write16(unsigned long field, u16 value)
2156 {
2157         vmcs_check16(field);
2158         if (static_branch_unlikely(&enable_evmcs))
2159                 return evmcs_write16(field, value);
2160
2161         __vmcs_writel(field, value);
2162 }
2163
2164 static __always_inline void vmcs_write32(unsigned long field, u32 value)
2165 {
2166         vmcs_check32(field);
2167         if (static_branch_unlikely(&enable_evmcs))
2168                 return evmcs_write32(field, value);
2169
2170         __vmcs_writel(field, value);
2171 }
2172
2173 static __always_inline void vmcs_write64(unsigned long field, u64 value)
2174 {
2175         vmcs_check64(field);
2176         if (static_branch_unlikely(&enable_evmcs))
2177                 return evmcs_write64(field, value);
2178
2179         __vmcs_writel(field, value);
2180 #ifndef CONFIG_X86_64
2181         asm volatile ("");
2182         __vmcs_writel(field+1, value >> 32);
2183 #endif
2184 }
2185
2186 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
2187 {
2188         vmcs_checkl(field);
2189         if (static_branch_unlikely(&enable_evmcs))
2190                 return evmcs_write64(field, value);
2191
2192         __vmcs_writel(field, value);
2193 }
2194
2195 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
2196 {
2197         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2198                          "vmcs_clear_bits does not support 64-bit fields");
2199         if (static_branch_unlikely(&enable_evmcs))
2200                 return evmcs_write32(field, evmcs_read32(field) & ~mask);
2201
2202         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
2203 }
2204
2205 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
2206 {
2207         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2208                          "vmcs_set_bits does not support 64-bit fields");
2209         if (static_branch_unlikely(&enable_evmcs))
2210                 return evmcs_write32(field, evmcs_read32(field) | mask);
2211
2212         __vmcs_writel(field, __vmcs_readl(field) | mask);
2213 }
2214
2215 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
2216 {
2217         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
2218 }
2219
2220 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
2221 {
2222         vmcs_write32(VM_ENTRY_CONTROLS, val);
2223         vmx->vm_entry_controls_shadow = val;
2224 }
2225
2226 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
2227 {
2228         if (vmx->vm_entry_controls_shadow != val)
2229                 vm_entry_controls_init(vmx, val);
2230 }
2231
2232 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
2233 {
2234         return vmx->vm_entry_controls_shadow;
2235 }
2236
2237
2238 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2239 {
2240         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
2241 }
2242
2243 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2244 {
2245         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
2246 }
2247
2248 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
2249 {
2250         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
2251 }
2252
2253 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
2254 {
2255         vmcs_write32(VM_EXIT_CONTROLS, val);
2256         vmx->vm_exit_controls_shadow = val;
2257 }
2258
2259 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
2260 {
2261         if (vmx->vm_exit_controls_shadow != val)
2262                 vm_exit_controls_init(vmx, val);
2263 }
2264
2265 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
2266 {
2267         return vmx->vm_exit_controls_shadow;
2268 }
2269
2270
2271 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2272 {
2273         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
2274 }
2275
2276 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2277 {
2278         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
2279 }
2280
2281 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
2282 {
2283         vmx->segment_cache.bitmask = 0;
2284 }
2285
2286 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
2287                                        unsigned field)
2288 {
2289         bool ret;
2290         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
2291
2292         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
2293                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
2294                 vmx->segment_cache.bitmask = 0;
2295         }
2296         ret = vmx->segment_cache.bitmask & mask;
2297         vmx->segment_cache.bitmask |= mask;
2298         return ret;
2299 }
2300
2301 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
2302 {
2303         u16 *p = &vmx->segment_cache.seg[seg].selector;
2304
2305         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
2306                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
2307         return *p;
2308 }
2309
2310 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
2311 {
2312         ulong *p = &vmx->segment_cache.seg[seg].base;
2313
2314         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
2315                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
2316         return *p;
2317 }
2318
2319 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
2320 {
2321         u32 *p = &vmx->segment_cache.seg[seg].limit;
2322
2323         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
2324                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
2325         return *p;
2326 }
2327
2328 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
2329 {
2330         u32 *p = &vmx->segment_cache.seg[seg].ar;
2331
2332         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
2333                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
2334         return *p;
2335 }
2336
2337 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
2338 {
2339         u32 eb;
2340
2341         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
2342              (1u << DB_VECTOR) | (1u << AC_VECTOR);
2343         /*
2344          * Guest access to VMware backdoor ports could legitimately
2345          * trigger #GP because of TSS I/O permission bitmap.
2346          * We intercept those #GP and allow access to them anyway
2347          * as VMware does.
2348          */
2349         if (enable_vmware_backdoor)
2350                 eb |= (1u << GP_VECTOR);
2351         if ((vcpu->guest_debug &
2352              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
2353             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
2354                 eb |= 1u << BP_VECTOR;
2355         if (to_vmx(vcpu)->rmode.vm86_active)
2356                 eb = ~0;
2357         if (enable_ept)
2358                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
2359
2360         /* When we are running a nested L2 guest and L1 specified for it a
2361          * certain exception bitmap, we must trap the same exceptions and pass
2362          * them to L1. When running L2, we will only handle the exceptions
2363          * specified above if L1 did not want them.
2364          */
2365         if (is_guest_mode(vcpu))
2366                 eb |= get_vmcs12(vcpu)->exception_bitmap;
2367
2368         vmcs_write32(EXCEPTION_BITMAP, eb);
2369 }
2370
2371 /*
2372  * Check if MSR is intercepted for currently loaded MSR bitmap.
2373  */
2374 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
2375 {
2376         unsigned long *msr_bitmap;
2377         int f = sizeof(unsigned long);
2378
2379         if (!cpu_has_vmx_msr_bitmap())
2380                 return true;
2381
2382         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
2383
2384         if (msr <= 0x1fff) {
2385                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2386         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2387                 msr &= 0x1fff;
2388                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2389         }
2390
2391         return true;
2392 }
2393
2394 /*
2395  * Check if MSR is intercepted for L01 MSR bitmap.
2396  */
2397 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
2398 {
2399         unsigned long *msr_bitmap;
2400         int f = sizeof(unsigned long);
2401
2402         if (!cpu_has_vmx_msr_bitmap())
2403                 return true;
2404
2405         msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
2406
2407         if (msr <= 0x1fff) {
2408                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2409         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2410                 msr &= 0x1fff;
2411                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2412         }
2413
2414         return true;
2415 }
2416
2417 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2418                 unsigned long entry, unsigned long exit)
2419 {
2420         vm_entry_controls_clearbit(vmx, entry);
2421         vm_exit_controls_clearbit(vmx, exit);
2422 }
2423
2424 static int find_msr(struct vmx_msrs *m, unsigned int msr)
2425 {
2426         unsigned int i;
2427
2428         for (i = 0; i < m->nr; ++i) {
2429                 if (m->val[i].index == msr)
2430                         return i;
2431         }
2432         return -ENOENT;
2433 }
2434
2435 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
2436 {
2437         int i;
2438         struct msr_autoload *m = &vmx->msr_autoload;
2439
2440         switch (msr) {
2441         case MSR_EFER:
2442                 if (cpu_has_load_ia32_efer) {
2443                         clear_atomic_switch_msr_special(vmx,
2444                                         VM_ENTRY_LOAD_IA32_EFER,
2445                                         VM_EXIT_LOAD_IA32_EFER);
2446                         return;
2447                 }
2448                 break;
2449         case MSR_CORE_PERF_GLOBAL_CTRL:
2450                 if (cpu_has_load_perf_global_ctrl) {
2451                         clear_atomic_switch_msr_special(vmx,
2452                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2453                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2454                         return;
2455                 }
2456                 break;
2457         }
2458         i = find_msr(&m->guest, msr);
2459         if (i < 0)
2460                 goto skip_guest;
2461         --m->guest.nr;
2462         m->guest.val[i] = m->guest.val[m->guest.nr];
2463         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
2464
2465 skip_guest:
2466         i = find_msr(&m->host, msr);
2467         if (i < 0)
2468                 return;
2469
2470         --m->host.nr;
2471         m->host.val[i] = m->host.val[m->host.nr];
2472         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
2473 }
2474
2475 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2476                 unsigned long entry, unsigned long exit,
2477                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
2478                 u64 guest_val, u64 host_val)
2479 {
2480         vmcs_write64(guest_val_vmcs, guest_val);
2481         vmcs_write64(host_val_vmcs, host_val);
2482         vm_entry_controls_setbit(vmx, entry);
2483         vm_exit_controls_setbit(vmx, exit);
2484 }
2485
2486 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
2487                                   u64 guest_val, u64 host_val)
2488 {
2489         int i, j;
2490         struct msr_autoload *m = &vmx->msr_autoload;
2491
2492         switch (msr) {
2493         case MSR_EFER:
2494                 if (cpu_has_load_ia32_efer) {
2495                         add_atomic_switch_msr_special(vmx,
2496                                         VM_ENTRY_LOAD_IA32_EFER,
2497                                         VM_EXIT_LOAD_IA32_EFER,
2498                                         GUEST_IA32_EFER,
2499                                         HOST_IA32_EFER,
2500                                         guest_val, host_val);
2501                         return;
2502                 }
2503                 break;
2504         case MSR_CORE_PERF_GLOBAL_CTRL:
2505                 if (cpu_has_load_perf_global_ctrl) {
2506                         add_atomic_switch_msr_special(vmx,
2507                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2508                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2509                                         GUEST_IA32_PERF_GLOBAL_CTRL,
2510                                         HOST_IA32_PERF_GLOBAL_CTRL,
2511                                         guest_val, host_val);
2512                         return;
2513                 }
2514                 break;
2515         case MSR_IA32_PEBS_ENABLE:
2516                 /* PEBS needs a quiescent period after being disabled (to write
2517                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
2518                  * provide that period, so a CPU could write host's record into
2519                  * guest's memory.
2520                  */
2521                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2522         }
2523
2524         i = find_msr(&m->guest, msr);
2525         j = find_msr(&m->host, msr);
2526         if (i == NR_AUTOLOAD_MSRS || j == NR_AUTOLOAD_MSRS) {
2527                 printk_once(KERN_WARNING "Not enough msr switch entries. "
2528                                 "Can't add msr %x\n", msr);
2529                 return;
2530         }
2531         if (i < 0) {
2532                 i = m->guest.nr++;
2533                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
2534         }
2535         if (j < 0) {
2536                 j = m->host.nr++;
2537                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
2538         }
2539         m->guest.val[i].index = msr;
2540         m->guest.val[i].value = guest_val;
2541         m->host.val[j].index = msr;
2542         m->host.val[j].value = host_val;
2543 }
2544
2545 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2546 {
2547         u64 guest_efer = vmx->vcpu.arch.efer;
2548         u64 ignore_bits = 0;
2549
2550         if (!enable_ept) {
2551                 /*
2552                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2553                  * host CPUID is more efficient than testing guest CPUID
2554                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2555                  */
2556                 if (boot_cpu_has(X86_FEATURE_SMEP))
2557                         guest_efer |= EFER_NX;
2558                 else if (!(guest_efer & EFER_NX))
2559                         ignore_bits |= EFER_NX;
2560         }
2561
2562         /*
2563          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2564          */
2565         ignore_bits |= EFER_SCE;
2566 #ifdef CONFIG_X86_64
2567         ignore_bits |= EFER_LMA | EFER_LME;
2568         /* SCE is meaningful only in long mode on Intel */
2569         if (guest_efer & EFER_LMA)
2570                 ignore_bits &= ~(u64)EFER_SCE;
2571 #endif
2572
2573         clear_atomic_switch_msr(vmx, MSR_EFER);
2574
2575         /*
2576          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2577          * On CPUs that support "load IA32_EFER", always switch EFER
2578          * atomically, since it's faster than switching it manually.
2579          */
2580         if (cpu_has_load_ia32_efer ||
2581             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2582                 if (!(guest_efer & EFER_LMA))
2583                         guest_efer &= ~EFER_LME;
2584                 if (guest_efer != host_efer)
2585                         add_atomic_switch_msr(vmx, MSR_EFER,
2586                                               guest_efer, host_efer);
2587                 return false;
2588         } else {
2589                 guest_efer &= ~ignore_bits;
2590                 guest_efer |= host_efer & ignore_bits;
2591
2592                 vmx->guest_msrs[efer_offset].data = guest_efer;
2593                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2594
2595                 return true;
2596         }
2597 }
2598
2599 #ifdef CONFIG_X86_32
2600 /*
2601  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2602  * VMCS rather than the segment table.  KVM uses this helper to figure
2603  * out the current bases to poke them into the VMCS before entry.
2604  */
2605 static unsigned long segment_base(u16 selector)
2606 {
2607         struct desc_struct *table;
2608         unsigned long v;
2609
2610         if (!(selector & ~SEGMENT_RPL_MASK))
2611                 return 0;
2612
2613         table = get_current_gdt_ro();
2614
2615         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2616                 u16 ldt_selector = kvm_read_ldt();
2617
2618                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2619                         return 0;
2620
2621                 table = (struct desc_struct *)segment_base(ldt_selector);
2622         }
2623         v = get_desc_base(&table[selector >> 3]);
2624         return v;
2625 }
2626 #endif
2627
2628 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2629 {
2630         struct vcpu_vmx *vmx = to_vmx(vcpu);
2631 #ifdef CONFIG_X86_64
2632         int cpu = raw_smp_processor_id();
2633 #endif
2634         int i;
2635
2636         if (vmx->host_state.loaded)
2637                 return;
2638
2639         vmx->host_state.loaded = 1;
2640         /*
2641          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2642          * allow segment selectors with cpl > 0 or ti == 1.
2643          */
2644         vmx->host_state.ldt_sel = kvm_read_ldt();
2645         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2646
2647 #ifdef CONFIG_X86_64
2648         save_fsgs_for_kvm();
2649         vmx->host_state.fs_sel = current->thread.fsindex;
2650         vmx->host_state.gs_sel = current->thread.gsindex;
2651 #else
2652         savesegment(fs, vmx->host_state.fs_sel);
2653         savesegment(gs, vmx->host_state.gs_sel);
2654 #endif
2655         if (!(vmx->host_state.fs_sel & 7)) {
2656                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2657                 vmx->host_state.fs_reload_needed = 0;
2658         } else {
2659                 vmcs_write16(HOST_FS_SELECTOR, 0);
2660                 vmx->host_state.fs_reload_needed = 1;
2661         }
2662         if (!(vmx->host_state.gs_sel & 7))
2663                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2664         else {
2665                 vmcs_write16(HOST_GS_SELECTOR, 0);
2666                 vmx->host_state.gs_ldt_reload_needed = 1;
2667         }
2668
2669 #ifdef CONFIG_X86_64
2670         savesegment(ds, vmx->host_state.ds_sel);
2671         savesegment(es, vmx->host_state.es_sel);
2672
2673         vmcs_writel(HOST_FS_BASE, current->thread.fsbase);
2674         vmcs_writel(HOST_GS_BASE, cpu_kernelmode_gs_base(cpu));
2675
2676         vmx->msr_host_kernel_gs_base = current->thread.gsbase;
2677         if (is_long_mode(&vmx->vcpu))
2678                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2679 #else
2680         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2681         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2682 #endif
2683         if (boot_cpu_has(X86_FEATURE_MPX))
2684                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2685         for (i = 0; i < vmx->save_nmsrs; ++i)
2686                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2687                                    vmx->guest_msrs[i].data,
2688                                    vmx->guest_msrs[i].mask);
2689 }
2690
2691 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2692 {
2693         if (!vmx->host_state.loaded)
2694                 return;
2695
2696         ++vmx->vcpu.stat.host_state_reload;
2697         vmx->host_state.loaded = 0;
2698 #ifdef CONFIG_X86_64
2699         if (is_long_mode(&vmx->vcpu))
2700                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2701 #endif
2702         if (vmx->host_state.gs_ldt_reload_needed) {
2703                 kvm_load_ldt(vmx->host_state.ldt_sel);
2704 #ifdef CONFIG_X86_64
2705                 load_gs_index(vmx->host_state.gs_sel);
2706 #else
2707                 loadsegment(gs, vmx->host_state.gs_sel);
2708 #endif
2709         }
2710         if (vmx->host_state.fs_reload_needed)
2711                 loadsegment(fs, vmx->host_state.fs_sel);
2712 #ifdef CONFIG_X86_64
2713         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2714                 loadsegment(ds, vmx->host_state.ds_sel);
2715                 loadsegment(es, vmx->host_state.es_sel);
2716         }
2717 #endif
2718         invalidate_tss_limit();
2719 #ifdef CONFIG_X86_64
2720         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2721 #endif
2722         if (vmx->host_state.msr_host_bndcfgs)
2723                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2724         load_fixmap_gdt(raw_smp_processor_id());
2725 }
2726
2727 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2728 {
2729         preempt_disable();
2730         __vmx_load_host_state(vmx);
2731         preempt_enable();
2732 }
2733
2734 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2735 {
2736         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2737         struct pi_desc old, new;
2738         unsigned int dest;
2739
2740         /*
2741          * In case of hot-plug or hot-unplug, we may have to undo
2742          * vmx_vcpu_pi_put even if there is no assigned device.  And we
2743          * always keep PI.NDST up to date for simplicity: it makes the
2744          * code easier, and CPU migration is not a fast path.
2745          */
2746         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2747                 return;
2748
2749         /*
2750          * First handle the simple case where no cmpxchg is necessary; just
2751          * allow posting non-urgent interrupts.
2752          *
2753          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2754          * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2755          * expects the VCPU to be on the blocked_vcpu_list that matches
2756          * PI.NDST.
2757          */
2758         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2759             vcpu->cpu == cpu) {
2760                 pi_clear_sn(pi_desc);
2761                 return;
2762         }
2763
2764         /* The full case.  */
2765         do {
2766                 old.control = new.control = pi_desc->control;
2767
2768                 dest = cpu_physical_id(cpu);
2769
2770                 if (x2apic_enabled())
2771                         new.ndst = dest;
2772                 else
2773                         new.ndst = (dest << 8) & 0xFF00;
2774
2775                 new.sn = 0;
2776         } while (cmpxchg64(&pi_desc->control, old.control,
2777                            new.control) != old.control);
2778 }
2779
2780 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2781 {
2782         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2783         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2784 }
2785
2786 /*
2787  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2788  * vcpu mutex is already taken.
2789  */
2790 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2791 {
2792         struct vcpu_vmx *vmx = to_vmx(vcpu);
2793         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2794
2795         if (!already_loaded) {
2796                 loaded_vmcs_clear(vmx->loaded_vmcs);
2797                 local_irq_disable();
2798                 crash_disable_local_vmclear(cpu);
2799
2800                 /*
2801                  * Read loaded_vmcs->cpu should be before fetching
2802                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2803                  * See the comments in __loaded_vmcs_clear().
2804                  */
2805                 smp_rmb();
2806
2807                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2808                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2809                 crash_enable_local_vmclear(cpu);
2810                 local_irq_enable();
2811         }
2812
2813         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2814                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2815                 vmcs_load(vmx->loaded_vmcs->vmcs);
2816                 indirect_branch_prediction_barrier();
2817         }
2818
2819         if (!already_loaded) {
2820                 void *gdt = get_current_gdt_ro();
2821                 unsigned long sysenter_esp;
2822
2823                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2824
2825                 /*
2826                  * Linux uses per-cpu TSS and GDT, so set these when switching
2827                  * processors.  See 22.2.4.
2828                  */
2829                 vmcs_writel(HOST_TR_BASE,
2830                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
2831                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
2832
2833                 /*
2834                  * VM exits change the host TR limit to 0x67 after a VM
2835                  * exit.  This is okay, since 0x67 covers everything except
2836                  * the IO bitmap and have have code to handle the IO bitmap
2837                  * being lost after a VM exit.
2838                  */
2839                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2840
2841                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2842                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2843
2844                 vmx->loaded_vmcs->cpu = cpu;
2845         }
2846
2847         /* Setup TSC multiplier */
2848         if (kvm_has_tsc_control &&
2849             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2850                 decache_tsc_multiplier(vmx);
2851
2852         vmx_vcpu_pi_load(vcpu, cpu);
2853         vmx->host_pkru = read_pkru();
2854         vmx->host_debugctlmsr = get_debugctlmsr();
2855 }
2856
2857 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2858 {
2859         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2860
2861         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2862                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2863                 !kvm_vcpu_apicv_active(vcpu))
2864                 return;
2865
2866         /* Set SN when the vCPU is preempted */
2867         if (vcpu->preempted)
2868                 pi_set_sn(pi_desc);
2869 }
2870
2871 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2872 {
2873         vmx_vcpu_pi_put(vcpu);
2874
2875         __vmx_load_host_state(to_vmx(vcpu));
2876 }
2877
2878 static bool emulation_required(struct kvm_vcpu *vcpu)
2879 {
2880         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2881 }
2882
2883 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2884
2885 /*
2886  * Return the cr0 value that a nested guest would read. This is a combination
2887  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2888  * its hypervisor (cr0_read_shadow).
2889  */
2890 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2891 {
2892         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2893                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2894 }
2895 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2896 {
2897         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2898                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2899 }
2900
2901 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2902 {
2903         unsigned long rflags, save_rflags;
2904
2905         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2906                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2907                 rflags = vmcs_readl(GUEST_RFLAGS);
2908                 if (to_vmx(vcpu)->rmode.vm86_active) {
2909                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2910                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2911                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2912                 }
2913                 to_vmx(vcpu)->rflags = rflags;
2914         }
2915         return to_vmx(vcpu)->rflags;
2916 }
2917
2918 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2919 {
2920         unsigned long old_rflags = vmx_get_rflags(vcpu);
2921
2922         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2923         to_vmx(vcpu)->rflags = rflags;
2924         if (to_vmx(vcpu)->rmode.vm86_active) {
2925                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2926                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2927         }
2928         vmcs_writel(GUEST_RFLAGS, rflags);
2929
2930         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2931                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2932 }
2933
2934 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2935 {
2936         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2937         int ret = 0;
2938
2939         if (interruptibility & GUEST_INTR_STATE_STI)
2940                 ret |= KVM_X86_SHADOW_INT_STI;
2941         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2942                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2943
2944         return ret;
2945 }
2946
2947 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2948 {
2949         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2950         u32 interruptibility = interruptibility_old;
2951
2952         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2953
2954         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2955                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2956         else if (mask & KVM_X86_SHADOW_INT_STI)
2957                 interruptibility |= GUEST_INTR_STATE_STI;
2958
2959         if ((interruptibility != interruptibility_old))
2960                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2961 }
2962
2963 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2964 {
2965         unsigned long rip;
2966
2967         rip = kvm_rip_read(vcpu);
2968         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2969         kvm_rip_write(vcpu, rip);
2970
2971         /* skipping an emulated instruction also counts */
2972         vmx_set_interrupt_shadow(vcpu, 0);
2973 }
2974
2975 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2976                                                unsigned long exit_qual)
2977 {
2978         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2979         unsigned int nr = vcpu->arch.exception.nr;
2980         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2981
2982         if (vcpu->arch.exception.has_error_code) {
2983                 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2984                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2985         }
2986
2987         if (kvm_exception_is_soft(nr))
2988                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2989         else
2990                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2991
2992         if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2993             vmx_get_nmi_mask(vcpu))
2994                 intr_info |= INTR_INFO_UNBLOCK_NMI;
2995
2996         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2997 }
2998
2999 /*
3000  * KVM wants to inject page-faults which it got to the guest. This function
3001  * checks whether in a nested guest, we need to inject them to L1 or L2.
3002  */
3003 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
3004 {
3005         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3006         unsigned int nr = vcpu->arch.exception.nr;
3007
3008         if (nr == PF_VECTOR) {
3009                 if (vcpu->arch.exception.nested_apf) {
3010                         *exit_qual = vcpu->arch.apf.nested_apf_token;
3011                         return 1;
3012                 }
3013                 /*
3014                  * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
3015                  * The fix is to add the ancillary datum (CR2 or DR6) to structs
3016                  * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
3017                  * can be written only when inject_pending_event runs.  This should be
3018                  * conditional on a new capability---if the capability is disabled,
3019                  * kvm_multiple_exception would write the ancillary information to
3020                  * CR2 or DR6, for backwards ABI-compatibility.
3021                  */
3022                 if (nested_vmx_is_page_fault_vmexit(vmcs12,
3023                                                     vcpu->arch.exception.error_code)) {
3024                         *exit_qual = vcpu->arch.cr2;
3025                         return 1;
3026                 }
3027         } else {
3028                 if (vmcs12->exception_bitmap & (1u << nr)) {
3029                         if (nr == DB_VECTOR)
3030                                 *exit_qual = vcpu->arch.dr6;
3031                         else
3032                                 *exit_qual = 0;
3033                         return 1;
3034                 }
3035         }
3036
3037         return 0;
3038 }
3039
3040 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
3041 {
3042         /*
3043          * Ensure that we clear the HLT state in the VMCS.  We don't need to
3044          * explicitly skip the instruction because if the HLT state is set,
3045          * then the instruction is already executing and RIP has already been
3046          * advanced.
3047          */
3048         if (kvm_hlt_in_guest(vcpu->kvm) &&
3049                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
3050                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3051 }
3052
3053 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
3054 {
3055         struct vcpu_vmx *vmx = to_vmx(vcpu);
3056         unsigned nr = vcpu->arch.exception.nr;
3057         bool has_error_code = vcpu->arch.exception.has_error_code;
3058         u32 error_code = vcpu->arch.exception.error_code;
3059         u32 intr_info = nr | INTR_INFO_VALID_MASK;
3060
3061         if (has_error_code) {
3062                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
3063                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3064         }
3065
3066         if (vmx->rmode.vm86_active) {
3067                 int inc_eip = 0;
3068                 if (kvm_exception_is_soft(nr))
3069                         inc_eip = vcpu->arch.event_exit_inst_len;
3070                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
3071                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3072                 return;
3073         }
3074
3075         WARN_ON_ONCE(vmx->emulation_required);
3076
3077         if (kvm_exception_is_soft(nr)) {
3078                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3079                              vmx->vcpu.arch.event_exit_inst_len);
3080                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3081         } else
3082                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3083
3084         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
3085
3086         vmx_clear_hlt(vcpu);
3087 }
3088
3089 static bool vmx_rdtscp_supported(void)
3090 {
3091         return cpu_has_vmx_rdtscp();
3092 }
3093
3094 static bool vmx_invpcid_supported(void)
3095 {
3096         return cpu_has_vmx_invpcid() && enable_ept;
3097 }
3098
3099 /*
3100  * Swap MSR entry in host/guest MSR entry array.
3101  */
3102 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
3103 {
3104         struct shared_msr_entry tmp;
3105
3106         tmp = vmx->guest_msrs[to];
3107         vmx->guest_msrs[to] = vmx->guest_msrs[from];
3108         vmx->guest_msrs[from] = tmp;
3109 }
3110
3111 /*
3112  * Set up the vmcs to automatically save and restore system
3113  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
3114  * mode, as fiddling with msrs is very expensive.
3115  */
3116 static void setup_msrs(struct vcpu_vmx *vmx)
3117 {
3118         int save_nmsrs, index;
3119
3120         save_nmsrs = 0;
3121 #ifdef CONFIG_X86_64
3122         if (is_long_mode(&vmx->vcpu)) {
3123                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
3124                 if (index >= 0)
3125                         move_msr_up(vmx, index, save_nmsrs++);
3126                 index = __find_msr_index(vmx, MSR_LSTAR);
3127                 if (index >= 0)
3128                         move_msr_up(vmx, index, save_nmsrs++);
3129                 index = __find_msr_index(vmx, MSR_CSTAR);
3130                 if (index >= 0)
3131                         move_msr_up(vmx, index, save_nmsrs++);
3132                 index = __find_msr_index(vmx, MSR_TSC_AUX);
3133                 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
3134                         move_msr_up(vmx, index, save_nmsrs++);
3135                 /*
3136                  * MSR_STAR is only needed on long mode guests, and only
3137                  * if efer.sce is enabled.
3138                  */
3139                 index = __find_msr_index(vmx, MSR_STAR);
3140                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
3141                         move_msr_up(vmx, index, save_nmsrs++);
3142         }
3143 #endif
3144         index = __find_msr_index(vmx, MSR_EFER);
3145         if (index >= 0 && update_transition_efer(vmx, index))
3146                 move_msr_up(vmx, index, save_nmsrs++);
3147
3148         vmx->save_nmsrs = save_nmsrs;
3149
3150         if (cpu_has_vmx_msr_bitmap())
3151                 vmx_update_msr_bitmap(&vmx->vcpu);
3152 }
3153
3154 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
3155 {
3156         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3157
3158         if (is_guest_mode(vcpu) &&
3159             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
3160                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
3161
3162         return vcpu->arch.tsc_offset;
3163 }
3164
3165 /*
3166  * writes 'offset' into guest's timestamp counter offset register
3167  */
3168 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
3169 {
3170         if (is_guest_mode(vcpu)) {
3171                 /*
3172                  * We're here if L1 chose not to trap WRMSR to TSC. According
3173                  * to the spec, this should set L1's TSC; The offset that L1
3174                  * set for L2 remains unchanged, and still needs to be added
3175                  * to the newly set TSC to get L2's TSC.
3176                  */
3177                 struct vmcs12 *vmcs12;
3178                 /* recalculate vmcs02.TSC_OFFSET: */
3179                 vmcs12 = get_vmcs12(vcpu);
3180                 vmcs_write64(TSC_OFFSET, offset +
3181                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
3182                          vmcs12->tsc_offset : 0));
3183         } else {
3184                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
3185                                            vmcs_read64(TSC_OFFSET), offset);
3186                 vmcs_write64(TSC_OFFSET, offset);
3187         }
3188 }
3189
3190 /*
3191  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
3192  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
3193  * all guests if the "nested" module option is off, and can also be disabled
3194  * for a single guest by disabling its VMX cpuid bit.
3195  */
3196 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
3197 {
3198         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
3199 }
3200
3201 /*
3202  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
3203  * returned for the various VMX controls MSRs when nested VMX is enabled.
3204  * The same values should also be used to verify that vmcs12 control fields are
3205  * valid during nested entry from L1 to L2.
3206  * Each of these control msrs has a low and high 32-bit half: A low bit is on
3207  * if the corresponding bit in the (32-bit) control field *must* be on, and a
3208  * bit in the high half is on if the corresponding bit in the control field
3209  * may be on. See also vmx_control_verify().
3210  */
3211 static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv)
3212 {
3213         if (!nested) {
3214                 memset(msrs, 0, sizeof(*msrs));
3215                 return;
3216         }
3217
3218         /*
3219          * Note that as a general rule, the high half of the MSRs (bits in
3220          * the control fields which may be 1) should be initialized by the
3221          * intersection of the underlying hardware's MSR (i.e., features which
3222          * can be supported) and the list of features we want to expose -
3223          * because they are known to be properly supported in our code.
3224          * Also, usually, the low half of the MSRs (bits which must be 1) can
3225          * be set to 0, meaning that L1 may turn off any of these bits. The
3226          * reason is that if one of these bits is necessary, it will appear
3227          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
3228          * fields of vmcs01 and vmcs02, will turn these bits off - and
3229          * nested_vmx_exit_reflected() will not pass related exits to L1.
3230          * These rules have exceptions below.
3231          */
3232
3233         /* pin-based controls */
3234         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
3235                 msrs->pinbased_ctls_low,
3236                 msrs->pinbased_ctls_high);
3237         msrs->pinbased_ctls_low |=
3238                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3239         msrs->pinbased_ctls_high &=
3240                 PIN_BASED_EXT_INTR_MASK |
3241                 PIN_BASED_NMI_EXITING |
3242                 PIN_BASED_VIRTUAL_NMIS |
3243                 (apicv ? PIN_BASED_POSTED_INTR : 0);
3244         msrs->pinbased_ctls_high |=
3245                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3246                 PIN_BASED_VMX_PREEMPTION_TIMER;
3247
3248         /* exit controls */
3249         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
3250                 msrs->exit_ctls_low,
3251                 msrs->exit_ctls_high);
3252         msrs->exit_ctls_low =
3253                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3254
3255         msrs->exit_ctls_high &=
3256 #ifdef CONFIG_X86_64
3257                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
3258 #endif
3259                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
3260         msrs->exit_ctls_high |=
3261                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
3262                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
3263                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
3264
3265         if (kvm_mpx_supported())
3266                 msrs->exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
3267
3268         /* We support free control of debug control saving. */
3269         msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
3270
3271         /* entry controls */
3272         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
3273                 msrs->entry_ctls_low,
3274                 msrs->entry_ctls_high);
3275         msrs->entry_ctls_low =
3276                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3277         msrs->entry_ctls_high &=
3278 #ifdef CONFIG_X86_64
3279                 VM_ENTRY_IA32E_MODE |
3280 #endif
3281                 VM_ENTRY_LOAD_IA32_PAT;
3282         msrs->entry_ctls_high |=
3283                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
3284         if (kvm_mpx_supported())
3285                 msrs->entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
3286
3287         /* We support free control of debug control loading. */
3288         msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
3289
3290         /* cpu-based controls */
3291         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
3292                 msrs->procbased_ctls_low,
3293                 msrs->procbased_ctls_high);
3294         msrs->procbased_ctls_low =
3295                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3296         msrs->procbased_ctls_high &=
3297                 CPU_BASED_VIRTUAL_INTR_PENDING |
3298                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
3299                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
3300                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
3301                 CPU_BASED_CR3_STORE_EXITING |
3302 #ifdef CONFIG_X86_64
3303                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
3304 #endif
3305                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
3306                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
3307                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
3308                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
3309                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3310         /*
3311          * We can allow some features even when not supported by the
3312          * hardware. For example, L1 can specify an MSR bitmap - and we
3313          * can use it to avoid exits to L1 - even when L0 runs L2
3314          * without MSR bitmaps.
3315          */
3316         msrs->procbased_ctls_high |=
3317                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3318                 CPU_BASED_USE_MSR_BITMAPS;
3319
3320         /* We support free control of CR3 access interception. */
3321         msrs->procbased_ctls_low &=
3322                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
3323
3324         /*
3325          * secondary cpu-based controls.  Do not include those that
3326          * depend on CPUID bits, they are added later by vmx_cpuid_update.
3327          */
3328         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
3329                 msrs->secondary_ctls_low,
3330                 msrs->secondary_ctls_high);
3331         msrs->secondary_ctls_low = 0;
3332         msrs->secondary_ctls_high &=
3333                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3334                 SECONDARY_EXEC_DESC |
3335                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3336                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3337                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3338                 SECONDARY_EXEC_WBINVD_EXITING;
3339
3340         if (enable_ept) {
3341                 /* nested EPT: emulate EPT also to L1 */
3342                 msrs->secondary_ctls_high |=
3343                         SECONDARY_EXEC_ENABLE_EPT;
3344                 msrs->ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
3345                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
3346                 if (cpu_has_vmx_ept_execute_only())
3347                         msrs->ept_caps |=
3348                                 VMX_EPT_EXECUTE_ONLY_BIT;
3349                 msrs->ept_caps &= vmx_capability.ept;
3350                 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
3351                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
3352                         VMX_EPT_1GB_PAGE_BIT;
3353                 if (enable_ept_ad_bits) {
3354                         msrs->secondary_ctls_high |=
3355                                 SECONDARY_EXEC_ENABLE_PML;
3356                         msrs->ept_caps |= VMX_EPT_AD_BIT;
3357                 }
3358         }
3359
3360         if (cpu_has_vmx_vmfunc()) {
3361                 msrs->secondary_ctls_high |=
3362                         SECONDARY_EXEC_ENABLE_VMFUNC;
3363                 /*
3364                  * Advertise EPTP switching unconditionally
3365                  * since we emulate it
3366                  */
3367                 if (enable_ept)
3368                         msrs->vmfunc_controls =
3369                                 VMX_VMFUNC_EPTP_SWITCHING;
3370         }
3371
3372         /*
3373          * Old versions of KVM use the single-context version without
3374          * checking for support, so declare that it is supported even
3375          * though it is treated as global context.  The alternative is
3376          * not failing the single-context invvpid, and it is worse.
3377          */
3378         if (enable_vpid) {
3379                 msrs->secondary_ctls_high |=
3380                         SECONDARY_EXEC_ENABLE_VPID;
3381                 msrs->vpid_caps = VMX_VPID_INVVPID_BIT |
3382                         VMX_VPID_EXTENT_SUPPORTED_MASK;
3383         }
3384
3385         if (enable_unrestricted_guest)
3386                 msrs->secondary_ctls_high |=
3387                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
3388
3389         /* miscellaneous data */
3390         rdmsr(MSR_IA32_VMX_MISC,
3391                 msrs->misc_low,
3392                 msrs->misc_high);
3393         msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA;
3394         msrs->misc_low |=
3395                 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
3396                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
3397                 VMX_MISC_ACTIVITY_HLT;
3398         msrs->misc_high = 0;
3399
3400         /*
3401          * This MSR reports some information about VMX support. We
3402          * should return information about the VMX we emulate for the
3403          * guest, and the VMCS structure we give it - not about the
3404          * VMX support of the underlying hardware.
3405          */
3406         msrs->basic =
3407                 VMCS12_REVISION |
3408                 VMX_BASIC_TRUE_CTLS |
3409                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
3410                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
3411
3412         if (cpu_has_vmx_basic_inout())
3413                 msrs->basic |= VMX_BASIC_INOUT;
3414
3415         /*
3416          * These MSRs specify bits which the guest must keep fixed on
3417          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
3418          * We picked the standard core2 setting.
3419          */
3420 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
3421 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
3422         msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON;
3423         msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
3424
3425         /* These MSRs specify bits which the guest must keep fixed off. */
3426         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
3427         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
3428
3429         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
3430         msrs->vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1;
3431 }
3432
3433 /*
3434  * if fixed0[i] == 1: val[i] must be 1
3435  * if fixed1[i] == 0: val[i] must be 0
3436  */
3437 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
3438 {
3439         return ((val & fixed1) | fixed0) == val;
3440 }
3441
3442 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
3443 {
3444         return fixed_bits_valid(control, low, high);
3445 }
3446
3447 static inline u64 vmx_control_msr(u32 low, u32 high)
3448 {
3449         return low | ((u64)high << 32);
3450 }
3451
3452 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
3453 {
3454         superset &= mask;
3455         subset &= mask;
3456
3457         return (superset | subset) == superset;
3458 }
3459
3460 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
3461 {
3462         const u64 feature_and_reserved =
3463                 /* feature (except bit 48; see below) */
3464                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
3465                 /* reserved */
3466                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
3467         u64 vmx_basic = vmx->nested.msrs.basic;
3468
3469         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
3470                 return -EINVAL;
3471
3472         /*
3473          * KVM does not emulate a version of VMX that constrains physical
3474          * addresses of VMX structures (e.g. VMCS) to 32-bits.
3475          */
3476         if (data & BIT_ULL(48))
3477                 return -EINVAL;
3478
3479         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
3480             vmx_basic_vmcs_revision_id(data))
3481                 return -EINVAL;
3482
3483         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
3484                 return -EINVAL;
3485
3486         vmx->nested.msrs.basic = data;
3487         return 0;
3488 }
3489
3490 static int
3491 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3492 {
3493         u64 supported;
3494         u32 *lowp, *highp;
3495
3496         switch (msr_index) {
3497         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3498                 lowp = &vmx->nested.msrs.pinbased_ctls_low;
3499                 highp = &vmx->nested.msrs.pinbased_ctls_high;
3500                 break;
3501         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3502                 lowp = &vmx->nested.msrs.procbased_ctls_low;
3503                 highp = &vmx->nested.msrs.procbased_ctls_high;
3504                 break;
3505         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3506                 lowp = &vmx->nested.msrs.exit_ctls_low;
3507                 highp = &vmx->nested.msrs.exit_ctls_high;
3508                 break;
3509         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3510                 lowp = &vmx->nested.msrs.entry_ctls_low;
3511                 highp = &vmx->nested.msrs.entry_ctls_high;
3512                 break;
3513         case MSR_IA32_VMX_PROCBASED_CTLS2:
3514                 lowp = &vmx->nested.msrs.secondary_ctls_low;
3515                 highp = &vmx->nested.msrs.secondary_ctls_high;
3516                 break;
3517         default:
3518                 BUG();
3519         }
3520
3521         supported = vmx_control_msr(*lowp, *highp);
3522
3523         /* Check must-be-1 bits are still 1. */
3524         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3525                 return -EINVAL;
3526
3527         /* Check must-be-0 bits are still 0. */
3528         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3529                 return -EINVAL;
3530
3531         *lowp = data;
3532         *highp = data >> 32;
3533         return 0;
3534 }
3535
3536 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3537 {
3538         const u64 feature_and_reserved_bits =
3539                 /* feature */
3540                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3541                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3542                 /* reserved */
3543                 GENMASK_ULL(13, 9) | BIT_ULL(31);
3544         u64 vmx_misc;
3545
3546         vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
3547                                    vmx->nested.msrs.misc_high);
3548
3549         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3550                 return -EINVAL;
3551
3552         if ((vmx->nested.msrs.pinbased_ctls_high &
3553              PIN_BASED_VMX_PREEMPTION_TIMER) &&
3554             vmx_misc_preemption_timer_rate(data) !=
3555             vmx_misc_preemption_timer_rate(vmx_misc))
3556                 return -EINVAL;
3557
3558         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3559                 return -EINVAL;
3560
3561         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3562                 return -EINVAL;
3563
3564         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3565                 return -EINVAL;
3566
3567         vmx->nested.msrs.misc_low = data;
3568         vmx->nested.msrs.misc_high = data >> 32;
3569
3570         /*
3571          * If L1 has read-only VM-exit information fields, use the
3572          * less permissive vmx_vmwrite_bitmap to specify write
3573          * permissions for the shadow VMCS.
3574          */
3575         if (enable_shadow_vmcs && !nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
3576                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
3577
3578         return 0;
3579 }
3580
3581 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3582 {
3583         u64 vmx_ept_vpid_cap;
3584
3585         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps,
3586                                            vmx->nested.msrs.vpid_caps);
3587
3588         /* Every bit is either reserved or a feature bit. */
3589         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3590                 return -EINVAL;
3591
3592         vmx->nested.msrs.ept_caps = data;
3593         vmx->nested.msrs.vpid_caps = data >> 32;
3594         return 0;
3595 }
3596
3597 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3598 {
3599         u64 *msr;
3600
3601         switch (msr_index) {
3602         case MSR_IA32_VMX_CR0_FIXED0:
3603                 msr = &vmx->nested.msrs.cr0_fixed0;
3604                 break;
3605         case MSR_IA32_VMX_CR4_FIXED0:
3606                 msr = &vmx->nested.msrs.cr4_fixed0;
3607                 break;
3608         default:
3609                 BUG();
3610         }
3611
3612         /*
3613          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3614          * must be 1 in the restored value.
3615          */
3616         if (!is_bitwise_subset(data, *msr, -1ULL))
3617                 return -EINVAL;
3618
3619         *msr = data;
3620         return 0;
3621 }
3622
3623 /*
3624  * Called when userspace is restoring VMX MSRs.
3625  *
3626  * Returns 0 on success, non-0 otherwise.
3627  */
3628 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3629 {
3630         struct vcpu_vmx *vmx = to_vmx(vcpu);
3631
3632         /*
3633          * Don't allow changes to the VMX capability MSRs while the vCPU
3634          * is in VMX operation.
3635          */
3636         if (vmx->nested.vmxon)
3637                 return -EBUSY;
3638
3639         switch (msr_index) {
3640         case MSR_IA32_VMX_BASIC:
3641                 return vmx_restore_vmx_basic(vmx, data);
3642         case MSR_IA32_VMX_PINBASED_CTLS:
3643         case MSR_IA32_VMX_PROCBASED_CTLS:
3644         case MSR_IA32_VMX_EXIT_CTLS:
3645         case MSR_IA32_VMX_ENTRY_CTLS:
3646                 /*
3647                  * The "non-true" VMX capability MSRs are generated from the
3648                  * "true" MSRs, so we do not support restoring them directly.
3649                  *
3650                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3651                  * should restore the "true" MSRs with the must-be-1 bits
3652                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3653                  * DEFAULT SETTINGS".
3654                  */
3655                 return -EINVAL;
3656         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3657         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3658         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3659         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3660         case MSR_IA32_VMX_PROCBASED_CTLS2:
3661                 return vmx_restore_control_msr(vmx, msr_index, data);
3662         case MSR_IA32_VMX_MISC:
3663                 return vmx_restore_vmx_misc(vmx, data);
3664         case MSR_IA32_VMX_CR0_FIXED0:
3665         case MSR_IA32_VMX_CR4_FIXED0:
3666                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3667         case MSR_IA32_VMX_CR0_FIXED1:
3668         case MSR_IA32_VMX_CR4_FIXED1:
3669                 /*
3670                  * These MSRs are generated based on the vCPU's CPUID, so we
3671                  * do not support restoring them directly.
3672                  */
3673                 return -EINVAL;
3674         case MSR_IA32_VMX_EPT_VPID_CAP:
3675                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3676         case MSR_IA32_VMX_VMCS_ENUM:
3677                 vmx->nested.msrs.vmcs_enum = data;
3678                 return 0;
3679         default:
3680                 /*
3681                  * The rest of the VMX capability MSRs do not support restore.
3682                  */
3683                 return -EINVAL;
3684         }
3685 }
3686
3687 /* Returns 0 on success, non-0 otherwise. */
3688 static int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata)
3689 {
3690         switch (msr_index) {
3691         case MSR_IA32_VMX_BASIC:
3692                 *pdata = msrs->basic;
3693                 break;
3694         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3695         case MSR_IA32_VMX_PINBASED_CTLS:
3696                 *pdata = vmx_control_msr(
3697                         msrs->pinbased_ctls_low,
3698                         msrs->pinbased_ctls_high);
3699                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3700                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3701                 break;
3702         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3703         case MSR_IA32_VMX_PROCBASED_CTLS:
3704                 *pdata = vmx_control_msr(
3705                         msrs->procbased_ctls_low,
3706                         msrs->procbased_ctls_high);
3707                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3708                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3709                 break;
3710         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3711         case MSR_IA32_VMX_EXIT_CTLS:
3712                 *pdata = vmx_control_msr(
3713                         msrs->exit_ctls_low,
3714                         msrs->exit_ctls_high);
3715                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3716                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3717                 break;
3718         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3719         case MSR_IA32_VMX_ENTRY_CTLS:
3720                 *pdata = vmx_control_msr(
3721                         msrs->entry_ctls_low,
3722                         msrs->entry_ctls_high);
3723                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3724                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3725                 break;
3726         case MSR_IA32_VMX_MISC:
3727                 *pdata = vmx_control_msr(
3728                         msrs->misc_low,
3729                         msrs->misc_high);
3730                 break;
3731         case MSR_IA32_VMX_CR0_FIXED0:
3732                 *pdata = msrs->cr0_fixed0;
3733                 break;
3734         case MSR_IA32_VMX_CR0_FIXED1:
3735                 *pdata = msrs->cr0_fixed1;
3736                 break;
3737         case MSR_IA32_VMX_CR4_FIXED0:
3738                 *pdata = msrs->cr4_fixed0;
3739                 break;
3740         case MSR_IA32_VMX_CR4_FIXED1:
3741                 *pdata = msrs->cr4_fixed1;
3742                 break;
3743         case MSR_IA32_VMX_VMCS_ENUM:
3744                 *pdata = msrs->vmcs_enum;
3745                 break;
3746         case MSR_IA32_VMX_PROCBASED_CTLS2:
3747                 *pdata = vmx_control_msr(
3748                         msrs->secondary_ctls_low,
3749                         msrs->secondary_ctls_high);
3750                 break;
3751         case MSR_IA32_VMX_EPT_VPID_CAP:
3752                 *pdata = msrs->ept_caps |
3753                         ((u64)msrs->vpid_caps << 32);
3754                 break;
3755         case MSR_IA32_VMX_VMFUNC:
3756                 *pdata = msrs->vmfunc_controls;
3757                 break;
3758         default:
3759                 return 1;
3760         }
3761
3762         return 0;
3763 }
3764
3765 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3766                                                  uint64_t val)
3767 {
3768         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3769
3770         return !(val & ~valid_bits);
3771 }
3772
3773 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
3774 {
3775         switch (msr->index) {
3776         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3777                 if (!nested)
3778                         return 1;
3779                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
3780         default:
3781                 return 1;
3782         }
3783
3784         return 0;
3785 }
3786
3787 /*
3788  * Reads an msr value (of 'msr_index') into 'pdata'.
3789  * Returns 0 on success, non-0 otherwise.
3790  * Assumes vcpu_load() was already called.
3791  */
3792 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3793 {
3794         struct vcpu_vmx *vmx = to_vmx(vcpu);
3795         struct shared_msr_entry *msr;
3796
3797         switch (msr_info->index) {
3798 #ifdef CONFIG_X86_64
3799         case MSR_FS_BASE:
3800                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3801                 break;
3802         case MSR_GS_BASE:
3803                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3804                 break;
3805         case MSR_KERNEL_GS_BASE:
3806                 vmx_load_host_state(vmx);
3807                 msr_info->data = vmx->msr_guest_kernel_gs_base;
3808                 break;
3809 #endif
3810         case MSR_EFER:
3811                 return kvm_get_msr_common(vcpu, msr_info);
3812         case MSR_IA32_SPEC_CTRL:
3813                 if (!msr_info->host_initiated &&
3814                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3815                         return 1;
3816
3817                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
3818                 break;
3819         case MSR_IA32_ARCH_CAPABILITIES:
3820                 if (!msr_info->host_initiated &&
3821                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3822                         return 1;
3823                 msr_info->data = to_vmx(vcpu)->arch_capabilities;
3824                 break;
3825         case MSR_IA32_SYSENTER_CS:
3826                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3827                 break;
3828         case MSR_IA32_SYSENTER_EIP:
3829                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3830                 break;
3831         case MSR_IA32_SYSENTER_ESP:
3832                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3833                 break;
3834         case MSR_IA32_BNDCFGS:
3835                 if (!kvm_mpx_supported() ||
3836                     (!msr_info->host_initiated &&
3837                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3838                         return 1;
3839                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3840                 break;
3841         case MSR_IA32_MCG_EXT_CTL:
3842                 if (!msr_info->host_initiated &&
3843                     !(vmx->msr_ia32_feature_control &
3844                       FEATURE_CONTROL_LMCE))
3845                         return 1;
3846                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3847                 break;
3848         case MSR_IA32_FEATURE_CONTROL:
3849                 msr_info->data = vmx->msr_ia32_feature_control;
3850                 break;
3851         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3852                 if (!nested_vmx_allowed(vcpu))
3853                         return 1;
3854                 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
3855                                        &msr_info->data);
3856         case MSR_IA32_XSS:
3857                 if (!vmx_xsaves_supported())
3858                         return 1;
3859                 msr_info->data = vcpu->arch.ia32_xss;
3860                 break;
3861         case MSR_TSC_AUX:
3862                 if (!msr_info->host_initiated &&
3863                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3864                         return 1;
3865                 /* Otherwise falls through */
3866         default:
3867                 msr = find_msr_entry(vmx, msr_info->index);
3868                 if (msr) {
3869                         msr_info->data = msr->data;
3870                         break;
3871                 }
3872                 return kvm_get_msr_common(vcpu, msr_info);
3873         }
3874
3875         return 0;
3876 }
3877
3878 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3879
3880 /*
3881  * Writes msr value into into the appropriate "register".
3882  * Returns 0 on success, non-0 otherwise.
3883  * Assumes vcpu_load() was already called.
3884  */
3885 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3886 {
3887         struct vcpu_vmx *vmx = to_vmx(vcpu);
3888         struct shared_msr_entry *msr;
3889         int ret = 0;
3890         u32 msr_index = msr_info->index;
3891         u64 data = msr_info->data;
3892
3893         switch (msr_index) {
3894         case MSR_EFER:
3895                 ret = kvm_set_msr_common(vcpu, msr_info);
3896                 break;
3897 #ifdef CONFIG_X86_64
3898         case MSR_FS_BASE:
3899                 vmx_segment_cache_clear(vmx);
3900                 vmcs_writel(GUEST_FS_BASE, data);
3901                 break;
3902         case MSR_GS_BASE:
3903                 vmx_segment_cache_clear(vmx);
3904                 vmcs_writel(GUEST_GS_BASE, data);
3905                 break;
3906         case MSR_KERNEL_GS_BASE:
3907                 vmx_load_host_state(vmx);
3908                 vmx->msr_guest_kernel_gs_base = data;
3909                 break;
3910 #endif
3911         case MSR_IA32_SYSENTER_CS:
3912                 vmcs_write32(GUEST_SYSENTER_CS, data);
3913                 break;
3914         case MSR_IA32_SYSENTER_EIP:
3915                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3916                 break;
3917         case MSR_IA32_SYSENTER_ESP:
3918                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3919                 break;
3920         case MSR_IA32_BNDCFGS:
3921                 if (!kvm_mpx_supported() ||
3922                     (!msr_info->host_initiated &&
3923                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3924                         return 1;
3925                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
3926                     (data & MSR_IA32_BNDCFGS_RSVD))
3927                         return 1;
3928                 vmcs_write64(GUEST_BNDCFGS, data);
3929                 break;
3930         case MSR_IA32_SPEC_CTRL:
3931                 if (!msr_info->host_initiated &&
3932                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3933                         return 1;
3934
3935                 /* The STIBP bit doesn't fault even if it's not advertised */
3936                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
3937                         return 1;
3938
3939                 vmx->spec_ctrl = data;
3940
3941                 if (!data)
3942                         break;
3943
3944                 /*
3945                  * For non-nested:
3946                  * When it's written (to non-zero) for the first time, pass
3947                  * it through.
3948                  *
3949                  * For nested:
3950                  * The handling of the MSR bitmap for L2 guests is done in
3951                  * nested_vmx_merge_msr_bitmap. We should not touch the
3952                  * vmcs02.msr_bitmap here since it gets completely overwritten
3953                  * in the merging. We update the vmcs01 here for L1 as well
3954                  * since it will end up touching the MSR anyway now.
3955                  */
3956                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
3957                                               MSR_IA32_SPEC_CTRL,
3958                                               MSR_TYPE_RW);
3959                 break;
3960         case MSR_IA32_PRED_CMD:
3961                 if (!msr_info->host_initiated &&
3962                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3963                         return 1;
3964
3965                 if (data & ~PRED_CMD_IBPB)
3966                         return 1;
3967
3968                 if (!data)
3969                         break;
3970
3971                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3972
3973                 /*
3974                  * For non-nested:
3975                  * When it's written (to non-zero) for the first time, pass
3976                  * it through.
3977                  *
3978                  * For nested:
3979                  * The handling of the MSR bitmap for L2 guests is done in
3980                  * nested_vmx_merge_msr_bitmap. We should not touch the
3981                  * vmcs02.msr_bitmap here since it gets completely overwritten
3982                  * in the merging.
3983                  */
3984                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
3985                                               MSR_TYPE_W);
3986                 break;
3987         case MSR_IA32_ARCH_CAPABILITIES:
3988                 if (!msr_info->host_initiated)
3989                         return 1;
3990                 vmx->arch_capabilities = data;
3991                 break;
3992         case MSR_IA32_CR_PAT:
3993                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3994                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3995                                 return 1;
3996                         vmcs_write64(GUEST_IA32_PAT, data);
3997                         vcpu->arch.pat = data;
3998                         break;
3999                 }
4000                 ret = kvm_set_msr_common(vcpu, msr_info);
4001                 break;
4002         case MSR_IA32_TSC_ADJUST:
4003                 ret = kvm_set_msr_common(vcpu, msr_info);
4004                 break;
4005         case MSR_IA32_MCG_EXT_CTL:
4006                 if ((!msr_info->host_initiated &&
4007                      !(to_vmx(vcpu)->msr_ia32_feature_control &
4008                        FEATURE_CONTROL_LMCE)) ||
4009                     (data & ~MCG_EXT_CTL_LMCE_EN))
4010                         return 1;
4011                 vcpu->arch.mcg_ext_ctl = data;
4012                 break;
4013         case MSR_IA32_FEATURE_CONTROL:
4014                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
4015                     (to_vmx(vcpu)->msr_ia32_feature_control &
4016                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
4017                         return 1;
4018                 vmx->msr_ia32_feature_control = data;
4019                 if (msr_info->host_initiated && data == 0)
4020                         vmx_leave_nested(vcpu);
4021                 break;
4022         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4023                 if (!msr_info->host_initiated)
4024                         return 1; /* they are read-only */
4025                 if (!nested_vmx_allowed(vcpu))
4026                         return 1;
4027                 return vmx_set_vmx_msr(vcpu, msr_index, data);
4028         case MSR_IA32_XSS:
4029                 if (!vmx_xsaves_supported())
4030                         return 1;
4031                 /*
4032                  * The only supported bit as of Skylake is bit 8, but
4033                  * it is not supported on KVM.
4034                  */
4035                 if (data != 0)
4036                         return 1;
4037                 vcpu->arch.ia32_xss = data;
4038                 if (vcpu->arch.ia32_xss != host_xss)
4039                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
4040                                 vcpu->arch.ia32_xss, host_xss);
4041                 else
4042                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
4043                 break;
4044         case MSR_TSC_AUX:
4045                 if (!msr_info->host_initiated &&
4046                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4047                         return 1;
4048                 /* Check reserved bit, higher 32 bits should be zero */
4049                 if ((data >> 32) != 0)
4050                         return 1;
4051                 /* Otherwise falls through */
4052         default:
4053                 msr = find_msr_entry(vmx, msr_index);
4054                 if (msr) {
4055                         u64 old_msr_data = msr->data;
4056                         msr->data = data;
4057                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
4058                                 preempt_disable();
4059                                 ret = kvm_set_shared_msr(msr->index, msr->data,
4060                                                          msr->mask);
4061                                 preempt_enable();
4062                                 if (ret)
4063                                         msr->data = old_msr_data;
4064                         }
4065                         break;
4066                 }
4067                 ret = kvm_set_msr_common(vcpu, msr_info);
4068         }
4069
4070         return ret;
4071 }
4072
4073 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
4074 {
4075         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
4076         switch (reg) {
4077         case VCPU_REGS_RSP:
4078                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
4079                 break;
4080         case VCPU_REGS_RIP:
4081                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
4082                 break;
4083         case VCPU_EXREG_PDPTR:
4084                 if (enable_ept)
4085                         ept_save_pdptrs(vcpu);
4086                 break;
4087         default:
4088                 break;
4089         }
4090 }
4091
4092 static __init int cpu_has_kvm_support(void)
4093 {
4094         return cpu_has_vmx();
4095 }
4096
4097 static __init int vmx_disabled_by_bios(void)
4098 {
4099         u64 msr;
4100
4101         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
4102         if (msr & FEATURE_CONTROL_LOCKED) {
4103                 /* launched w/ TXT and VMX disabled */
4104                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4105                         && tboot_enabled())
4106                         return 1;
4107                 /* launched w/o TXT and VMX only enabled w/ TXT */
4108                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4109                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4110                         && !tboot_enabled()) {
4111                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
4112                                 "activate TXT before enabling KVM\n");
4113                         return 1;
4114                 }
4115                 /* launched w/o TXT and VMX disabled */
4116                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4117                         && !tboot_enabled())
4118                         return 1;
4119         }
4120
4121         return 0;
4122 }
4123
4124 static void kvm_cpu_vmxon(u64 addr)
4125 {
4126         cr4_set_bits(X86_CR4_VMXE);
4127         intel_pt_handle_vmx(1);
4128
4129         asm volatile (ASM_VMX_VMXON_RAX
4130                         : : "a"(&addr), "m"(addr)
4131                         : "memory", "cc");
4132 }
4133
4134 static int hardware_enable(void)
4135 {
4136         int cpu = raw_smp_processor_id();
4137         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
4138         u64 old, test_bits;
4139
4140         if (cr4_read_shadow() & X86_CR4_VMXE)
4141                 return -EBUSY;
4142
4143         /*
4144          * This can happen if we hot-added a CPU but failed to allocate
4145          * VP assist page for it.
4146          */
4147         if (static_branch_unlikely(&enable_evmcs) &&
4148             !hv_get_vp_assist_page(cpu))
4149                 return -EFAULT;
4150
4151         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
4152         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
4153         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
4154
4155         /*
4156          * Now we can enable the vmclear operation in kdump
4157          * since the loaded_vmcss_on_cpu list on this cpu
4158          * has been initialized.
4159          *
4160          * Though the cpu is not in VMX operation now, there
4161          * is no problem to enable the vmclear operation
4162          * for the loaded_vmcss_on_cpu list is empty!
4163          */
4164         crash_enable_local_vmclear(cpu);
4165
4166         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
4167
4168         test_bits = FEATURE_CONTROL_LOCKED;
4169         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
4170         if (tboot_enabled())
4171                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
4172
4173         if ((old & test_bits) != test_bits) {
4174                 /* enable and lock */
4175                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
4176         }
4177         kvm_cpu_vmxon(phys_addr);
4178         if (enable_ept)
4179                 ept_sync_global();
4180
4181         return 0;
4182 }
4183
4184 static void vmclear_local_loaded_vmcss(void)
4185 {
4186         int cpu = raw_smp_processor_id();
4187         struct loaded_vmcs *v, *n;
4188
4189         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
4190                                  loaded_vmcss_on_cpu_link)
4191                 __loaded_vmcs_clear(v);
4192 }
4193
4194
4195 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
4196  * tricks.
4197  */
4198 static void kvm_cpu_vmxoff(void)
4199 {
4200         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
4201
4202         intel_pt_handle_vmx(0);
4203         cr4_clear_bits(X86_CR4_VMXE);
4204 }
4205
4206 static void hardware_disable(void)
4207 {
4208         vmclear_local_loaded_vmcss();
4209         kvm_cpu_vmxoff();
4210 }
4211
4212 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
4213                                       u32 msr, u32 *result)
4214 {
4215         u32 vmx_msr_low, vmx_msr_high;
4216         u32 ctl = ctl_min | ctl_opt;
4217
4218         rdmsr(msr, vmx_msr_low, vmx_msr_high);
4219
4220         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
4221         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
4222
4223         /* Ensure minimum (required) set of control bits are supported. */
4224         if (ctl_min & ~ctl)
4225                 return -EIO;
4226
4227         *result = ctl;
4228         return 0;
4229 }
4230
4231 static __init bool allow_1_setting(u32 msr, u32 ctl)
4232 {
4233         u32 vmx_msr_low, vmx_msr_high;
4234
4235         rdmsr(msr, vmx_msr_low, vmx_msr_high);
4236         return vmx_msr_high & ctl;
4237 }
4238
4239 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
4240 {
4241         u32 vmx_msr_low, vmx_msr_high;
4242         u32 min, opt, min2, opt2;
4243         u32 _pin_based_exec_control = 0;
4244         u32 _cpu_based_exec_control = 0;
4245         u32 _cpu_based_2nd_exec_control = 0;
4246         u32 _vmexit_control = 0;
4247         u32 _vmentry_control = 0;
4248
4249         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
4250         min = CPU_BASED_HLT_EXITING |
4251 #ifdef CONFIG_X86_64
4252               CPU_BASED_CR8_LOAD_EXITING |
4253               CPU_BASED_CR8_STORE_EXITING |
4254 #endif
4255               CPU_BASED_CR3_LOAD_EXITING |
4256               CPU_BASED_CR3_STORE_EXITING |
4257               CPU_BASED_UNCOND_IO_EXITING |
4258               CPU_BASED_MOV_DR_EXITING |
4259               CPU_BASED_USE_TSC_OFFSETING |
4260               CPU_BASED_MWAIT_EXITING |
4261               CPU_BASED_MONITOR_EXITING |
4262               CPU_BASED_INVLPG_EXITING |
4263               CPU_BASED_RDPMC_EXITING;
4264
4265         opt = CPU_BASED_TPR_SHADOW |
4266               CPU_BASED_USE_MSR_BITMAPS |
4267               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
4268         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
4269                                 &_cpu_based_exec_control) < 0)
4270                 return -EIO;
4271 #ifdef CONFIG_X86_64
4272         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4273                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
4274                                            ~CPU_BASED_CR8_STORE_EXITING;
4275 #endif
4276         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
4277                 min2 = 0;
4278                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4279                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4280                         SECONDARY_EXEC_WBINVD_EXITING |
4281                         SECONDARY_EXEC_ENABLE_VPID |
4282                         SECONDARY_EXEC_ENABLE_EPT |
4283                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
4284                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
4285                         SECONDARY_EXEC_DESC |
4286                         SECONDARY_EXEC_RDTSCP |
4287                         SECONDARY_EXEC_ENABLE_INVPCID |
4288                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4289                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4290                         SECONDARY_EXEC_SHADOW_VMCS |
4291                         SECONDARY_EXEC_XSAVES |
4292                         SECONDARY_EXEC_RDSEED_EXITING |
4293                         SECONDARY_EXEC_RDRAND_EXITING |
4294                         SECONDARY_EXEC_ENABLE_PML |
4295                         SECONDARY_EXEC_TSC_SCALING |
4296                         SECONDARY_EXEC_ENABLE_VMFUNC;
4297                 if (adjust_vmx_controls(min2, opt2,
4298                                         MSR_IA32_VMX_PROCBASED_CTLS2,
4299                                         &_cpu_based_2nd_exec_control) < 0)
4300                         return -EIO;
4301         }
4302 #ifndef CONFIG_X86_64
4303         if (!(_cpu_based_2nd_exec_control &
4304                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
4305                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
4306 #endif
4307
4308         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4309                 _cpu_based_2nd_exec_control &= ~(
4310                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4311                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4312                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4313
4314         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
4315                 &vmx_capability.ept, &vmx_capability.vpid);
4316
4317         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
4318                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
4319                    enabled */
4320                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
4321                                              CPU_BASED_CR3_STORE_EXITING |
4322                                              CPU_BASED_INVLPG_EXITING);
4323         } else if (vmx_capability.ept) {
4324                 vmx_capability.ept = 0;
4325                 pr_warn_once("EPT CAP should not exist if not support "
4326                                 "1-setting enable EPT VM-execution control\n");
4327         }
4328         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
4329                 vmx_capability.vpid) {
4330                 vmx_capability.vpid = 0;
4331                 pr_warn_once("VPID CAP should not exist if not support "
4332                                 "1-setting enable VPID VM-execution control\n");
4333         }
4334
4335         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
4336 #ifdef CONFIG_X86_64
4337         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
4338 #endif
4339         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
4340                 VM_EXIT_CLEAR_BNDCFGS;
4341         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
4342                                 &_vmexit_control) < 0)
4343                 return -EIO;
4344
4345         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
4346         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
4347                  PIN_BASED_VMX_PREEMPTION_TIMER;
4348         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
4349                                 &_pin_based_exec_control) < 0)
4350                 return -EIO;
4351
4352         if (cpu_has_broken_vmx_preemption_timer())
4353                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4354         if (!(_cpu_based_2nd_exec_control &
4355                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
4356                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
4357
4358         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
4359         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
4360         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
4361                                 &_vmentry_control) < 0)
4362                 return -EIO;
4363
4364         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
4365
4366         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
4367         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
4368                 return -EIO;
4369
4370 #ifdef CONFIG_X86_64
4371         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
4372         if (vmx_msr_high & (1u<<16))
4373                 return -EIO;
4374 #endif
4375
4376         /* Require Write-Back (WB) memory type for VMCS accesses. */
4377         if (((vmx_msr_high >> 18) & 15) != 6)
4378                 return -EIO;
4379
4380         vmcs_conf->size = vmx_msr_high & 0x1fff;
4381         vmcs_conf->order = get_order(vmcs_conf->size);
4382         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
4383
4384         /* KVM supports Enlightened VMCS v1 only */
4385         if (static_branch_unlikely(&enable_evmcs))
4386                 vmcs_conf->revision_id = KVM_EVMCS_VERSION;
4387         else
4388                 vmcs_conf->revision_id = vmx_msr_low;
4389
4390         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
4391         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
4392         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
4393         vmcs_conf->vmexit_ctrl         = _vmexit_control;
4394         vmcs_conf->vmentry_ctrl        = _vmentry_control;
4395
4396         if (static_branch_unlikely(&enable_evmcs))
4397                 evmcs_sanitize_exec_ctrls(vmcs_conf);
4398
4399         cpu_has_load_ia32_efer =
4400                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4401                                 VM_ENTRY_LOAD_IA32_EFER)
4402                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4403                                    VM_EXIT_LOAD_IA32_EFER);
4404
4405         cpu_has_load_perf_global_ctrl =
4406                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4407                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
4408                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4409                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
4410
4411         /*
4412          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
4413          * but due to errata below it can't be used. Workaround is to use
4414          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
4415          *
4416          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
4417          *
4418          * AAK155             (model 26)
4419          * AAP115             (model 30)
4420          * AAT100             (model 37)
4421          * BC86,AAY89,BD102   (model 44)
4422          * BA97               (model 46)
4423          *
4424          */
4425         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
4426                 switch (boot_cpu_data.x86_model) {
4427                 case 26:
4428                 case 30:
4429                 case 37:
4430                 case 44:
4431                 case 46:
4432                         cpu_has_load_perf_global_ctrl = false;
4433                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
4434                                         "does not work properly. Using workaround\n");
4435                         break;
4436                 default:
4437                         break;
4438                 }
4439         }
4440
4441         if (boot_cpu_has(X86_FEATURE_XSAVES))
4442                 rdmsrl(MSR_IA32_XSS, host_xss);
4443
4444         return 0;
4445 }
4446
4447 static struct vmcs *alloc_vmcs_cpu(int cpu)
4448 {
4449         int node = cpu_to_node(cpu);
4450         struct page *pages;
4451         struct vmcs *vmcs;
4452
4453         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
4454         if (!pages)
4455                 return NULL;
4456         vmcs = page_address(pages);
4457         memset(vmcs, 0, vmcs_config.size);
4458         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
4459         return vmcs;
4460 }
4461
4462 static void free_vmcs(struct vmcs *vmcs)
4463 {
4464         free_pages((unsigned long)vmcs, vmcs_config.order);
4465 }
4466
4467 /*
4468  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
4469  */
4470 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4471 {
4472         if (!loaded_vmcs->vmcs)
4473                 return;
4474         loaded_vmcs_clear(loaded_vmcs);
4475         free_vmcs(loaded_vmcs->vmcs);
4476         loaded_vmcs->vmcs = NULL;
4477         if (loaded_vmcs->msr_bitmap)
4478                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
4479         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
4480 }
4481
4482 static struct vmcs *alloc_vmcs(void)
4483 {
4484         return alloc_vmcs_cpu(raw_smp_processor_id());
4485 }
4486
4487 static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4488 {
4489         loaded_vmcs->vmcs = alloc_vmcs();
4490         if (!loaded_vmcs->vmcs)
4491                 return -ENOMEM;
4492
4493         loaded_vmcs->shadow_vmcs = NULL;
4494         loaded_vmcs_init(loaded_vmcs);
4495
4496         if (cpu_has_vmx_msr_bitmap()) {
4497                 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
4498                 if (!loaded_vmcs->msr_bitmap)
4499                         goto out_vmcs;
4500                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
4501
4502                 if (IS_ENABLED(CONFIG_HYPERV) &&
4503                     static_branch_unlikely(&enable_evmcs) &&
4504                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
4505                         struct hv_enlightened_vmcs *evmcs =
4506                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
4507
4508                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
4509                 }
4510         }
4511         return 0;
4512
4513 out_vmcs:
4514         free_loaded_vmcs(loaded_vmcs);
4515         return -ENOMEM;
4516 }
4517
4518 static void free_kvm_area(void)
4519 {
4520         int cpu;
4521
4522         for_each_possible_cpu(cpu) {
4523                 free_vmcs(per_cpu(vmxarea, cpu));
4524                 per_cpu(vmxarea, cpu) = NULL;
4525         }
4526 }
4527
4528 enum vmcs_field_width {
4529         VMCS_FIELD_WIDTH_U16 = 0,
4530         VMCS_FIELD_WIDTH_U64 = 1,
4531         VMCS_FIELD_WIDTH_U32 = 2,
4532         VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
4533 };
4534
4535 static inline int vmcs_field_width(unsigned long field)
4536 {
4537         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
4538                 return VMCS_FIELD_WIDTH_U32;
4539         return (field >> 13) & 0x3 ;
4540 }
4541
4542 static inline int vmcs_field_readonly(unsigned long field)
4543 {
4544         return (((field >> 10) & 0x3) == 1);
4545 }
4546
4547 static void init_vmcs_shadow_fields(void)
4548 {
4549         int i, j;
4550
4551         for (i = j = 0; i < max_shadow_read_only_fields; i++) {
4552                 u16 field = shadow_read_only_fields[i];
4553                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4554                     (i + 1 == max_shadow_read_only_fields ||
4555                      shadow_read_only_fields[i + 1] != field + 1))
4556                         pr_err("Missing field from shadow_read_only_field %x\n",
4557                                field + 1);
4558
4559                 clear_bit(field, vmx_vmread_bitmap);
4560 #ifdef CONFIG_X86_64
4561                 if (field & 1)
4562                         continue;
4563 #endif
4564                 if (j < i)
4565                         shadow_read_only_fields[j] = field;
4566                 j++;
4567         }
4568         max_shadow_read_only_fields = j;
4569
4570         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
4571                 u16 field = shadow_read_write_fields[i];
4572                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4573                     (i + 1 == max_shadow_read_write_fields ||
4574                      shadow_read_write_fields[i + 1] != field + 1))
4575                         pr_err("Missing field from shadow_read_write_field %x\n",
4576                                field + 1);
4577
4578                 /*
4579                  * PML and the preemption timer can be emulated, but the
4580                  * processor cannot vmwrite to fields that don't exist
4581                  * on bare metal.
4582                  */
4583                 switch (field) {
4584                 case GUEST_PML_INDEX:
4585                         if (!cpu_has_vmx_pml())
4586                                 continue;
4587                         break;
4588                 case VMX_PREEMPTION_TIMER_VALUE:
4589                         if (!cpu_has_vmx_preemption_timer())
4590                                 continue;
4591                         break;
4592                 case GUEST_INTR_STATUS:
4593                         if (!cpu_has_vmx_apicv())
4594                                 continue;
4595                         break;
4596                 default:
4597                         break;
4598                 }
4599
4600                 clear_bit(field, vmx_vmwrite_bitmap);
4601                 clear_bit(field, vmx_vmread_bitmap);
4602 #ifdef CONFIG_X86_64
4603                 if (field & 1)
4604                         continue;
4605 #endif
4606                 if (j < i)
4607                         shadow_read_write_fields[j] = field;
4608                 j++;
4609         }
4610         max_shadow_read_write_fields = j;
4611 }
4612
4613 static __init int alloc_kvm_area(void)
4614 {
4615         int cpu;
4616
4617         for_each_possible_cpu(cpu) {
4618                 struct vmcs *vmcs;
4619
4620                 vmcs = alloc_vmcs_cpu(cpu);
4621                 if (!vmcs) {
4622                         free_kvm_area();
4623                         return -ENOMEM;
4624                 }
4625
4626                 per_cpu(vmxarea, cpu) = vmcs;
4627         }
4628         return 0;
4629 }
4630
4631 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
4632                 struct kvm_segment *save)
4633 {
4634         if (!emulate_invalid_guest_state) {
4635                 /*
4636                  * CS and SS RPL should be equal during guest entry according
4637                  * to VMX spec, but in reality it is not always so. Since vcpu
4638                  * is in the middle of the transition from real mode to
4639                  * protected mode it is safe to assume that RPL 0 is a good
4640                  * default value.
4641                  */
4642                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4643                         save->selector &= ~SEGMENT_RPL_MASK;
4644                 save->dpl = save->selector & SEGMENT_RPL_MASK;
4645                 save->s = 1;
4646         }
4647         vmx_set_segment(vcpu, save, seg);
4648 }
4649
4650 static void enter_pmode(struct kvm_vcpu *vcpu)
4651 {
4652         unsigned long flags;
4653         struct vcpu_vmx *vmx = to_vmx(vcpu);
4654
4655         /*
4656          * Update real mode segment cache. It may be not up-to-date if sement
4657          * register was written while vcpu was in a guest mode.
4658          */
4659         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4660         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4661         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4662         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4663         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4664         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4665
4666         vmx->rmode.vm86_active = 0;
4667
4668         vmx_segment_cache_clear(vmx);
4669
4670         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4671
4672         flags = vmcs_readl(GUEST_RFLAGS);
4673         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
4674         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
4675         vmcs_writel(GUEST_RFLAGS, flags);
4676
4677         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
4678                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4679
4680         update_exception_bitmap(vcpu);
4681
4682         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4683         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4684         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4685         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4686         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4687         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4688 }
4689
4690 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4691 {
4692         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4693         struct kvm_segment var = *save;
4694
4695         var.dpl = 0x3;
4696         if (seg == VCPU_SREG_CS)
4697                 var.type = 0x3;
4698
4699         if (!emulate_invalid_guest_state) {
4700                 var.selector = var.base >> 4;
4701                 var.base = var.base & 0xffff0;
4702                 var.limit = 0xffff;
4703                 var.g = 0;
4704                 var.db = 0;
4705                 var.present = 1;
4706                 var.s = 1;
4707                 var.l = 0;
4708                 var.unusable = 0;
4709                 var.type = 0x3;
4710                 var.avl = 0;
4711                 if (save->base & 0xf)
4712                         printk_once(KERN_WARNING "kvm: segment base is not "
4713                                         "paragraph aligned when entering "
4714                                         "protected mode (seg=%d)", seg);
4715         }
4716
4717         vmcs_write16(sf->selector, var.selector);
4718         vmcs_writel(sf->base, var.base);
4719         vmcs_write32(sf->limit, var.limit);
4720         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
4721 }
4722
4723 static void enter_rmode(struct kvm_vcpu *vcpu)
4724 {
4725         unsigned long flags;
4726         struct vcpu_vmx *vmx = to_vmx(vcpu);
4727         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
4728
4729         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4730         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4731         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4732         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4733         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4734         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4735         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4736
4737         vmx->rmode.vm86_active = 1;
4738
4739         /*
4740          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4741          * vcpu. Warn the user that an update is overdue.
4742          */
4743         if (!kvm_vmx->tss_addr)
4744                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4745                              "called before entering vcpu\n");
4746
4747         vmx_segment_cache_clear(vmx);
4748
4749         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
4750         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4751         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4752
4753         flags = vmcs_readl(GUEST_RFLAGS);
4754         vmx->rmode.save_rflags = flags;
4755
4756         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4757
4758         vmcs_writel(GUEST_RFLAGS, flags);
4759         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4760         update_exception_bitmap(vcpu);
4761
4762         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4763         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4764         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4765         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4766         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4767         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4768
4769         kvm_mmu_reset_context(vcpu);
4770 }
4771
4772 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4773 {
4774         struct vcpu_vmx *vmx = to_vmx(vcpu);
4775         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4776
4777         if (!msr)
4778                 return;
4779
4780         /*
4781          * Force kernel_gs_base reloading before EFER changes, as control
4782          * of this msr depends on is_long_mode().
4783          */
4784         vmx_load_host_state(to_vmx(vcpu));
4785         vcpu->arch.efer = efer;
4786         if (efer & EFER_LMA) {
4787                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4788                 msr->data = efer;
4789         } else {
4790                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4791
4792                 msr->data = efer & ~EFER_LME;
4793         }
4794         setup_msrs(vmx);
4795 }
4796
4797 #ifdef CONFIG_X86_64
4798
4799 static void enter_lmode(struct kvm_vcpu *vcpu)
4800 {
4801         u32 guest_tr_ar;
4802
4803         vmx_segment_cache_clear(to_vmx(vcpu));
4804
4805         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4806         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4807                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4808                                      __func__);
4809                 vmcs_write32(GUEST_TR_AR_BYTES,
4810                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4811                              | VMX_AR_TYPE_BUSY_64_TSS);
4812         }
4813         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4814 }
4815
4816 static void exit_lmode(struct kvm_vcpu *vcpu)
4817 {
4818         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4819         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4820 }
4821
4822 #endif
4823
4824 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
4825                                 bool invalidate_gpa)
4826 {
4827         if (enable_ept && (invalidate_gpa || !enable_vpid)) {
4828                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4829                         return;
4830                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4831         } else {
4832                 vpid_sync_context(vpid);
4833         }
4834 }
4835
4836 static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
4837 {
4838         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
4839 }
4840
4841 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4842 {
4843         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4844
4845         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4846         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4847 }
4848
4849 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4850 {
4851         if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
4852                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4853         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4854 }
4855
4856 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4857 {
4858         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4859
4860         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4861         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4862 }
4863
4864 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4865 {
4866         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4867
4868         if (!test_bit(VCPU_EXREG_PDPTR,
4869                       (unsigned long *)&vcpu->arch.regs_dirty))
4870                 return;
4871
4872         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4873                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4874                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4875                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4876                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4877         }
4878 }
4879
4880 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4881 {
4882         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4883
4884         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4885                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4886                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4887                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4888                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4889         }
4890
4891         __set_bit(VCPU_EXREG_PDPTR,
4892                   (unsigned long *)&vcpu->arch.regs_avail);
4893         __set_bit(VCPU_EXREG_PDPTR,
4894                   (unsigned long *)&vcpu->arch.regs_dirty);
4895 }
4896
4897 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4898 {
4899         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
4900         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
4901         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4902
4903         if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
4904                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4905             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4906                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4907
4908         return fixed_bits_valid(val, fixed0, fixed1);
4909 }
4910
4911 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4912 {
4913         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
4914         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
4915
4916         return fixed_bits_valid(val, fixed0, fixed1);
4917 }
4918
4919 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4920 {
4921         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0;
4922         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1;
4923
4924         return fixed_bits_valid(val, fixed0, fixed1);
4925 }
4926
4927 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4928 #define nested_guest_cr4_valid  nested_cr4_valid
4929 #define nested_host_cr4_valid   nested_cr4_valid
4930
4931 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4932
4933 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4934                                         unsigned long cr0,
4935                                         struct kvm_vcpu *vcpu)
4936 {
4937         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4938                 vmx_decache_cr3(vcpu);
4939         if (!(cr0 & X86_CR0_PG)) {
4940                 /* From paging/starting to nonpaging */
4941                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4942                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4943                              (CPU_BASED_CR3_LOAD_EXITING |
4944                               CPU_BASED_CR3_STORE_EXITING));
4945                 vcpu->arch.cr0 = cr0;
4946                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4947         } else if (!is_paging(vcpu)) {
4948                 /* From nonpaging to paging */
4949                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4950                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4951                              ~(CPU_BASED_CR3_LOAD_EXITING |
4952                                CPU_BASED_CR3_STORE_EXITING));
4953                 vcpu->arch.cr0 = cr0;
4954                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4955         }
4956
4957         if (!(cr0 & X86_CR0_WP))
4958                 *hw_cr0 &= ~X86_CR0_WP;
4959 }
4960
4961 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4962 {
4963         struct vcpu_vmx *vmx = to_vmx(vcpu);
4964         unsigned long hw_cr0;
4965
4966         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4967         if (enable_unrestricted_guest)
4968                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4969         else {
4970                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4971
4972                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4973                         enter_pmode(vcpu);
4974
4975                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4976                         enter_rmode(vcpu);
4977         }
4978
4979 #ifdef CONFIG_X86_64
4980         if (vcpu->arch.efer & EFER_LME) {
4981                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4982                         enter_lmode(vcpu);
4983                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4984                         exit_lmode(vcpu);
4985         }
4986 #endif
4987
4988         if (enable_ept && !enable_unrestricted_guest)
4989                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4990
4991         vmcs_writel(CR0_READ_SHADOW, cr0);
4992         vmcs_writel(GUEST_CR0, hw_cr0);
4993         vcpu->arch.cr0 = cr0;
4994
4995         /* depends on vcpu->arch.cr0 to be set to a new value */
4996         vmx->emulation_required = emulation_required(vcpu);
4997 }
4998
4999 static int get_ept_level(struct kvm_vcpu *vcpu)
5000 {
5001         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
5002                 return 5;
5003         return 4;
5004 }
5005
5006 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
5007 {
5008         u64 eptp = VMX_EPTP_MT_WB;
5009
5010         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
5011
5012         if (enable_ept_ad_bits &&
5013             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
5014                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
5015         eptp |= (root_hpa & PAGE_MASK);
5016
5017         return eptp;
5018 }
5019
5020 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
5021 {
5022         unsigned long guest_cr3;
5023         u64 eptp;
5024
5025         guest_cr3 = cr3;
5026         if (enable_ept) {
5027                 eptp = construct_eptp(vcpu, cr3);
5028                 vmcs_write64(EPT_POINTER, eptp);
5029                 if (enable_unrestricted_guest || is_paging(vcpu) ||
5030                     is_guest_mode(vcpu))
5031                         guest_cr3 = kvm_read_cr3(vcpu);
5032                 else
5033                         guest_cr3 = to_kvm_vmx(vcpu->kvm)->ept_identity_map_addr;
5034                 ept_load_pdptrs(vcpu);
5035         }
5036
5037         vmx_flush_tlb(vcpu, true);
5038         vmcs_writel(GUEST_CR3, guest_cr3);
5039 }
5040
5041 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
5042 {
5043         /*
5044          * Pass through host's Machine Check Enable value to hw_cr4, which
5045          * is in force while we are in guest mode.  Do not let guests control
5046          * this bit, even if host CR4.MCE == 0.
5047          */
5048         unsigned long hw_cr4;
5049
5050         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
5051         if (enable_unrestricted_guest)
5052                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
5053         else if (to_vmx(vcpu)->rmode.vm86_active)
5054                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
5055         else
5056                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
5057
5058         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
5059                 if (cr4 & X86_CR4_UMIP) {
5060                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5061                                 SECONDARY_EXEC_DESC);
5062                         hw_cr4 &= ~X86_CR4_UMIP;
5063                 } else if (!is_guest_mode(vcpu) ||
5064                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
5065                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5066                                         SECONDARY_EXEC_DESC);
5067         }
5068
5069         if (cr4 & X86_CR4_VMXE) {
5070                 /*
5071                  * To use VMXON (and later other VMX instructions), a guest
5072                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
5073                  * So basically the check on whether to allow nested VMX
5074                  * is here.
5075                  */
5076                 if (!nested_vmx_allowed(vcpu))
5077                         return 1;
5078         }
5079
5080         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5081                 return 1;
5082
5083         vcpu->arch.cr4 = cr4;
5084
5085         if (!enable_unrestricted_guest) {
5086                 if (enable_ept) {
5087                         if (!is_paging(vcpu)) {
5088                                 hw_cr4 &= ~X86_CR4_PAE;
5089                                 hw_cr4 |= X86_CR4_PSE;
5090                         } else if (!(cr4 & X86_CR4_PAE)) {
5091                                 hw_cr4 &= ~X86_CR4_PAE;
5092                         }
5093                 }
5094
5095                 /*
5096                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
5097                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
5098                  * to be manually disabled when guest switches to non-paging
5099                  * mode.
5100                  *
5101                  * If !enable_unrestricted_guest, the CPU is always running
5102                  * with CR0.PG=1 and CR4 needs to be modified.
5103                  * If enable_unrestricted_guest, the CPU automatically
5104                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
5105                  */
5106                 if (!is_paging(vcpu))
5107                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
5108         }
5109
5110         vmcs_writel(CR4_READ_SHADOW, cr4);
5111         vmcs_writel(GUEST_CR4, hw_cr4);
5112         return 0;
5113 }
5114
5115 static void vmx_get_segment(struct kvm_vcpu *vcpu,
5116                             struct kvm_segment *var, int seg)
5117 {
5118         struct vcpu_vmx *vmx = to_vmx(vcpu);
5119         u32 ar;
5120
5121         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5122                 *var = vmx->rmode.segs[seg];
5123                 if (seg == VCPU_SREG_TR
5124                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
5125                         return;
5126                 var->base = vmx_read_guest_seg_base(vmx, seg);
5127                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
5128                 return;
5129         }
5130         var->base = vmx_read_guest_seg_base(vmx, seg);
5131         var->limit = vmx_read_guest_seg_limit(vmx, seg);
5132         var->selector = vmx_read_guest_seg_selector(vmx, seg);
5133         ar = vmx_read_guest_seg_ar(vmx, seg);
5134         var->unusable = (ar >> 16) & 1;
5135         var->type = ar & 15;
5136         var->s = (ar >> 4) & 1;
5137         var->dpl = (ar >> 5) & 3;
5138         /*
5139          * Some userspaces do not preserve unusable property. Since usable
5140          * segment has to be present according to VMX spec we can use present
5141          * property to amend userspace bug by making unusable segment always
5142          * nonpresent. vmx_segment_access_rights() already marks nonpresent
5143          * segment as unusable.
5144          */
5145         var->present = !var->unusable;
5146         var->avl = (ar >> 12) & 1;
5147         var->l = (ar >> 13) & 1;
5148         var->db = (ar >> 14) & 1;
5149         var->g = (ar >> 15) & 1;
5150 }
5151
5152 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
5153 {
5154         struct kvm_segment s;
5155
5156         if (to_vmx(vcpu)->rmode.vm86_active) {
5157                 vmx_get_segment(vcpu, &s, seg);
5158                 return s.base;
5159         }
5160         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
5161 }
5162
5163 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
5164 {
5165         struct vcpu_vmx *vmx = to_vmx(vcpu);
5166
5167         if (unlikely(vmx->rmode.vm86_active))
5168                 return 0;
5169         else {
5170                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
5171                 return VMX_AR_DPL(ar);
5172         }
5173 }
5174
5175 static u32 vmx_segment_access_rights(struct kvm_segment *var)
5176 {
5177         u32 ar;
5178
5179         if (var->unusable || !var->present)
5180                 ar = 1 << 16;
5181         else {
5182                 ar = var->type & 15;
5183                 ar |= (var->s & 1) << 4;
5184                 ar |= (var->dpl & 3) << 5;
5185                 ar |= (var->present & 1) << 7;
5186                 ar |= (var->avl & 1) << 12;
5187                 ar |= (var->l & 1) << 13;
5188                 ar |= (var->db & 1) << 14;
5189                 ar |= (var->g & 1) << 15;
5190         }
5191
5192         return ar;
5193 }
5194
5195 static void vmx_set_segment(struct kvm_vcpu *vcpu,
5196                             struct kvm_segment *var, int seg)
5197 {
5198         struct vcpu_vmx *vmx = to_vmx(vcpu);
5199         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5200
5201         vmx_segment_cache_clear(vmx);
5202
5203         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5204                 vmx->rmode.segs[seg] = *var;
5205                 if (seg == VCPU_SREG_TR)
5206                         vmcs_write16(sf->selector, var->selector);
5207                 else if (var->s)
5208                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
5209                 goto out;
5210         }
5211
5212         vmcs_writel(sf->base, var->base);
5213         vmcs_write32(sf->limit, var->limit);
5214         vmcs_write16(sf->selector, var->selector);
5215
5216         /*
5217          *   Fix the "Accessed" bit in AR field of segment registers for older
5218          * qemu binaries.
5219          *   IA32 arch specifies that at the time of processor reset the
5220          * "Accessed" bit in the AR field of segment registers is 1. And qemu
5221          * is setting it to 0 in the userland code. This causes invalid guest
5222          * state vmexit when "unrestricted guest" mode is turned on.
5223          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
5224          * tree. Newer qemu binaries with that qemu fix would not need this
5225          * kvm hack.
5226          */
5227         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
5228                 var->type |= 0x1; /* Accessed */
5229
5230         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
5231
5232 out:
5233         vmx->emulation_required = emulation_required(vcpu);
5234 }
5235
5236 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5237 {
5238         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
5239
5240         *db = (ar >> 14) & 1;
5241         *l = (ar >> 13) & 1;
5242 }
5243
5244 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5245 {
5246         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
5247         dt->address = vmcs_readl(GUEST_IDTR_BASE);
5248 }
5249
5250 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5251 {
5252         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
5253         vmcs_writel(GUEST_IDTR_BASE, dt->address);
5254 }
5255
5256 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5257 {
5258         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
5259         dt->address = vmcs_readl(GUEST_GDTR_BASE);
5260 }
5261
5262 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5263 {
5264         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
5265         vmcs_writel(GUEST_GDTR_BASE, dt->address);
5266 }
5267
5268 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
5269 {
5270         struct kvm_segment var;
5271         u32 ar;
5272
5273         vmx_get_segment(vcpu, &var, seg);
5274         var.dpl = 0x3;
5275         if (seg == VCPU_SREG_CS)
5276                 var.type = 0x3;
5277         ar = vmx_segment_access_rights(&var);
5278
5279         if (var.base != (var.selector << 4))
5280                 return false;
5281         if (var.limit != 0xffff)
5282                 return false;
5283         if (ar != 0xf3)
5284                 return false;
5285
5286         return true;
5287 }
5288
5289 static bool code_segment_valid(struct kvm_vcpu *vcpu)
5290 {
5291         struct kvm_segment cs;
5292         unsigned int cs_rpl;
5293
5294         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5295         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
5296
5297         if (cs.unusable)
5298                 return false;
5299         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
5300                 return false;
5301         if (!cs.s)
5302                 return false;
5303         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
5304                 if (cs.dpl > cs_rpl)
5305                         return false;
5306         } else {
5307                 if (cs.dpl != cs_rpl)
5308                         return false;
5309         }
5310         if (!cs.present)
5311                 return false;
5312
5313         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
5314         return true;
5315 }
5316
5317 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
5318 {
5319         struct kvm_segment ss;
5320         unsigned int ss_rpl;
5321
5322         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5323         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
5324
5325         if (ss.unusable)
5326                 return true;
5327         if (ss.type != 3 && ss.type != 7)
5328                 return false;
5329         if (!ss.s)
5330                 return false;
5331         if (ss.dpl != ss_rpl) /* DPL != RPL */
5332                 return false;
5333         if (!ss.present)
5334                 return false;
5335
5336         return true;
5337 }
5338
5339 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
5340 {
5341         struct kvm_segment var;
5342         unsigned int rpl;
5343
5344         vmx_get_segment(vcpu, &var, seg);
5345         rpl = var.selector & SEGMENT_RPL_MASK;
5346
5347         if (var.unusable)
5348                 return true;
5349         if (!var.s)
5350                 return false;
5351         if (!var.present)
5352                 return false;
5353         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
5354                 if (var.dpl < rpl) /* DPL < RPL */
5355                         return false;
5356         }
5357
5358         /* TODO: Add other members to kvm_segment_field to allow checking for other access
5359          * rights flags
5360          */
5361         return true;
5362 }
5363
5364 static bool tr_valid(struct kvm_vcpu *vcpu)
5365 {
5366         struct kvm_segment tr;
5367
5368         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
5369
5370         if (tr.unusable)
5371                 return false;
5372         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
5373                 return false;
5374         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
5375                 return false;
5376         if (!tr.present)
5377                 return false;
5378
5379         return true;
5380 }
5381
5382 static bool ldtr_valid(struct kvm_vcpu *vcpu)
5383 {
5384         struct kvm_segment ldtr;
5385
5386         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
5387
5388         if (ldtr.unusable)
5389                 return true;
5390         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
5391                 return false;
5392         if (ldtr.type != 2)
5393                 return false;
5394         if (!ldtr.present)
5395                 return false;
5396
5397         return true;
5398 }
5399
5400 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
5401 {
5402         struct kvm_segment cs, ss;
5403
5404         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5405         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5406
5407         return ((cs.selector & SEGMENT_RPL_MASK) ==
5408                  (ss.selector & SEGMENT_RPL_MASK));
5409 }
5410
5411 /*
5412  * Check if guest state is valid. Returns true if valid, false if
5413  * not.
5414  * We assume that registers are always usable
5415  */
5416 static bool guest_state_valid(struct kvm_vcpu *vcpu)
5417 {
5418         if (enable_unrestricted_guest)
5419                 return true;
5420
5421         /* real mode guest state checks */
5422         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5423                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
5424                         return false;
5425                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
5426                         return false;
5427                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
5428                         return false;
5429                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
5430                         return false;
5431                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
5432                         return false;
5433                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
5434                         return false;
5435         } else {
5436         /* protected mode guest state checks */
5437                 if (!cs_ss_rpl_check(vcpu))
5438                         return false;
5439                 if (!code_segment_valid(vcpu))
5440                         return false;
5441                 if (!stack_segment_valid(vcpu))
5442                         return false;
5443                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
5444                         return false;
5445                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
5446                         return false;
5447                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
5448                         return false;
5449                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
5450                         return false;
5451                 if (!tr_valid(vcpu))
5452                         return false;
5453                 if (!ldtr_valid(vcpu))
5454                         return false;
5455         }
5456         /* TODO:
5457          * - Add checks on RIP
5458          * - Add checks on RFLAGS
5459          */
5460
5461         return true;
5462 }
5463
5464 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
5465 {
5466         return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
5467 }
5468
5469 static int init_rmode_tss(struct kvm *kvm)
5470 {
5471         gfn_t fn;
5472         u16 data = 0;
5473         int idx, r;
5474
5475         idx = srcu_read_lock(&kvm->srcu);
5476         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
5477         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5478         if (r < 0)
5479                 goto out;
5480         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
5481         r = kvm_write_guest_page(kvm, fn++, &data,
5482                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
5483         if (r < 0)
5484                 goto out;
5485         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
5486         if (r < 0)
5487                 goto out;
5488         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5489         if (r < 0)
5490                 goto out;
5491         data = ~0;
5492         r = kvm_write_guest_page(kvm, fn, &data,
5493                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
5494                                  sizeof(u8));
5495 out:
5496         srcu_read_unlock(&kvm->srcu, idx);
5497         return r;
5498 }
5499
5500 static int init_rmode_identity_map(struct kvm *kvm)
5501 {
5502         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
5503         int i, idx, r = 0;
5504         kvm_pfn_t identity_map_pfn;
5505         u32 tmp;
5506
5507         /* Protect kvm_vmx->ept_identity_pagetable_done. */
5508         mutex_lock(&kvm->slots_lock);
5509
5510         if (likely(kvm_vmx->ept_identity_pagetable_done))
5511                 goto out2;
5512
5513         if (!kvm_vmx->ept_identity_map_addr)
5514                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
5515         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
5516
5517         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
5518                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
5519         if (r < 0)
5520                 goto out2;
5521
5522         idx = srcu_read_lock(&kvm->srcu);
5523         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
5524         if (r < 0)
5525                 goto out;
5526         /* Set up identity-mapping pagetable for EPT in real mode */
5527         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
5528                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
5529                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
5530                 r = kvm_write_guest_page(kvm, identity_map_pfn,
5531                                 &tmp, i * sizeof(tmp), sizeof(tmp));
5532                 if (r < 0)
5533                         goto out;
5534         }
5535         kvm_vmx->ept_identity_pagetable_done = true;
5536
5537 out:
5538         srcu_read_unlock(&kvm->srcu, idx);
5539
5540 out2:
5541         mutex_unlock(&kvm->slots_lock);
5542         return r;
5543 }
5544
5545 static void seg_setup(int seg)
5546 {
5547         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5548         unsigned int ar;
5549
5550         vmcs_write16(sf->selector, 0);
5551         vmcs_writel(sf->base, 0);
5552         vmcs_write32(sf->limit, 0xffff);
5553         ar = 0x93;
5554         if (seg == VCPU_SREG_CS)
5555                 ar |= 0x08; /* code segment */
5556
5557         vmcs_write32(sf->ar_bytes, ar);
5558 }
5559
5560 static int alloc_apic_access_page(struct kvm *kvm)
5561 {
5562         struct page *page;
5563         int r = 0;
5564
5565         mutex_lock(&kvm->slots_lock);
5566         if (kvm->arch.apic_access_page_done)
5567                 goto out;
5568         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
5569                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
5570         if (r)
5571                 goto out;
5572
5573         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
5574         if (is_error_page(page)) {
5575                 r = -EFAULT;
5576                 goto out;
5577         }
5578
5579         /*
5580          * Do not pin the page in memory, so that memory hot-unplug
5581          * is able to migrate it.
5582          */
5583         put_page(page);
5584         kvm->arch.apic_access_page_done = true;
5585 out:
5586         mutex_unlock(&kvm->slots_lock);
5587         return r;
5588 }
5589
5590 static int allocate_vpid(void)
5591 {
5592         int vpid;
5593
5594         if (!enable_vpid)
5595                 return 0;
5596         spin_lock(&vmx_vpid_lock);
5597         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
5598         if (vpid < VMX_NR_VPIDS)
5599                 __set_bit(vpid, vmx_vpid_bitmap);
5600         else
5601                 vpid = 0;
5602         spin_unlock(&vmx_vpid_lock);
5603         return vpid;
5604 }
5605
5606 static void free_vpid(int vpid)
5607 {
5608         if (!enable_vpid || vpid == 0)
5609                 return;
5610         spin_lock(&vmx_vpid_lock);
5611         __clear_bit(vpid, vmx_vpid_bitmap);
5612         spin_unlock(&vmx_vpid_lock);
5613 }
5614
5615 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
5616                                                           u32 msr, int type)
5617 {
5618         int f = sizeof(unsigned long);
5619
5620         if (!cpu_has_vmx_msr_bitmap())
5621                 return;
5622
5623         if (static_branch_unlikely(&enable_evmcs))
5624                 evmcs_touch_msr_bitmap();
5625
5626         /*
5627          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5628          * have the write-low and read-high bitmap offsets the wrong way round.
5629          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5630          */
5631         if (msr <= 0x1fff) {
5632                 if (type & MSR_TYPE_R)
5633                         /* read-low */
5634                         __clear_bit(msr, msr_bitmap + 0x000 / f);
5635
5636                 if (type & MSR_TYPE_W)
5637                         /* write-low */
5638                         __clear_bit(msr, msr_bitmap + 0x800 / f);
5639
5640         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5641                 msr &= 0x1fff;
5642                 if (type & MSR_TYPE_R)
5643                         /* read-high */
5644                         __clear_bit(msr, msr_bitmap + 0x400 / f);
5645
5646                 if (type & MSR_TYPE_W)
5647                         /* write-high */
5648                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
5649
5650         }
5651 }
5652
5653 static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
5654                                                          u32 msr, int type)
5655 {
5656         int f = sizeof(unsigned long);
5657
5658         if (!cpu_has_vmx_msr_bitmap())
5659                 return;
5660
5661         if (static_branch_unlikely(&enable_evmcs))
5662                 evmcs_touch_msr_bitmap();
5663
5664         /*
5665          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5666          * have the write-low and read-high bitmap offsets the wrong way round.
5667          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5668          */
5669         if (msr <= 0x1fff) {
5670                 if (type & MSR_TYPE_R)
5671                         /* read-low */
5672                         __set_bit(msr, msr_bitmap + 0x000 / f);
5673
5674                 if (type & MSR_TYPE_W)
5675                         /* write-low */
5676                         __set_bit(msr, msr_bitmap + 0x800 / f);
5677
5678         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5679                 msr &= 0x1fff;
5680                 if (type & MSR_TYPE_R)
5681                         /* read-high */
5682                         __set_bit(msr, msr_bitmap + 0x400 / f);
5683
5684                 if (type & MSR_TYPE_W)
5685                         /* write-high */
5686                         __set_bit(msr, msr_bitmap + 0xc00 / f);
5687
5688         }
5689 }
5690
5691 static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
5692                                                       u32 msr, int type, bool value)
5693 {
5694         if (value)
5695                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
5696         else
5697                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
5698 }
5699
5700 /*
5701  * If a msr is allowed by L0, we should check whether it is allowed by L1.
5702  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
5703  */
5704 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
5705                                                unsigned long *msr_bitmap_nested,
5706                                                u32 msr, int type)
5707 {
5708         int f = sizeof(unsigned long);
5709
5710         /*
5711          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5712          * have the write-low and read-high bitmap offsets the wrong way round.
5713          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5714          */
5715         if (msr <= 0x1fff) {
5716                 if (type & MSR_TYPE_R &&
5717                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
5718                         /* read-low */
5719                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
5720
5721                 if (type & MSR_TYPE_W &&
5722                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
5723                         /* write-low */
5724                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
5725
5726         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5727                 msr &= 0x1fff;
5728                 if (type & MSR_TYPE_R &&
5729                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
5730                         /* read-high */
5731                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
5732
5733                 if (type & MSR_TYPE_W &&
5734                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
5735                         /* write-high */
5736                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
5737
5738         }
5739 }
5740
5741 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5742 {
5743         u8 mode = 0;
5744
5745         if (cpu_has_secondary_exec_ctrls() &&
5746             (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
5747              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
5748                 mode |= MSR_BITMAP_MODE_X2APIC;
5749                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
5750                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
5751         }
5752
5753         if (is_long_mode(vcpu))
5754                 mode |= MSR_BITMAP_MODE_LM;
5755
5756         return mode;
5757 }
5758
5759 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
5760
5761 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
5762                                          u8 mode)
5763 {
5764         int msr;
5765
5766         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
5767                 unsigned word = msr / BITS_PER_LONG;
5768                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
5769                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
5770         }
5771
5772         if (mode & MSR_BITMAP_MODE_X2APIC) {
5773                 /*
5774                  * TPR reads and writes can be virtualized even if virtual interrupt
5775                  * delivery is not in use.
5776                  */
5777                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
5778                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
5779                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
5780                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
5781                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
5782                 }
5783         }
5784 }
5785
5786 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
5787 {
5788         struct vcpu_vmx *vmx = to_vmx(vcpu);
5789         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
5790         u8 mode = vmx_msr_bitmap_mode(vcpu);
5791         u8 changed = mode ^ vmx->msr_bitmap_mode;
5792
5793         if (!changed)
5794                 return;
5795
5796         vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW,
5797                                   !(mode & MSR_BITMAP_MODE_LM));
5798
5799         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
5800                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
5801
5802         vmx->msr_bitmap_mode = mode;
5803 }
5804
5805 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
5806 {
5807         return enable_apicv;
5808 }
5809
5810 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5811 {
5812         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5813         gfn_t gfn;
5814
5815         /*
5816          * Don't need to mark the APIC access page dirty; it is never
5817          * written to by the CPU during APIC virtualization.
5818          */
5819
5820         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5821                 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5822                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5823         }
5824
5825         if (nested_cpu_has_posted_intr(vmcs12)) {
5826                 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5827                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5828         }
5829 }
5830
5831
5832 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5833 {
5834         struct vcpu_vmx *vmx = to_vmx(vcpu);
5835         int max_irr;
5836         void *vapic_page;
5837         u16 status;
5838
5839         if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5840                 return;
5841
5842         vmx->nested.pi_pending = false;
5843         if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5844                 return;
5845
5846         max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5847         if (max_irr != 256) {
5848                 vapic_page = kmap(vmx->nested.virtual_apic_page);
5849                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
5850                         vapic_page, &max_irr);
5851                 kunmap(vmx->nested.virtual_apic_page);
5852
5853                 status = vmcs_read16(GUEST_INTR_STATUS);
5854                 if ((u8)max_irr > ((u8)status & 0xff)) {
5855                         status &= ~0xff;
5856                         status |= (u8)max_irr;
5857                         vmcs_write16(GUEST_INTR_STATUS, status);
5858                 }
5859         }
5860
5861         nested_mark_vmcs12_pages_dirty(vcpu);
5862 }
5863
5864 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5865                                                      bool nested)
5866 {
5867 #ifdef CONFIG_SMP
5868         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5869
5870         if (vcpu->mode == IN_GUEST_MODE) {
5871                 /*
5872                  * The vector of interrupt to be delivered to vcpu had
5873                  * been set in PIR before this function.
5874                  *
5875                  * Following cases will be reached in this block, and
5876                  * we always send a notification event in all cases as
5877                  * explained below.
5878                  *
5879                  * Case 1: vcpu keeps in non-root mode. Sending a
5880                  * notification event posts the interrupt to vcpu.
5881                  *
5882                  * Case 2: vcpu exits to root mode and is still
5883                  * runnable. PIR will be synced to vIRR before the
5884                  * next vcpu entry. Sending a notification event in
5885                  * this case has no effect, as vcpu is not in root
5886                  * mode.
5887                  *
5888                  * Case 3: vcpu exits to root mode and is blocked.
5889                  * vcpu_block() has already synced PIR to vIRR and
5890                  * never blocks vcpu if vIRR is not cleared. Therefore,
5891                  * a blocked vcpu here does not wait for any requested
5892                  * interrupts in PIR, and sending a notification event
5893                  * which has no effect is safe here.
5894                  */
5895
5896                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5897                 return true;
5898         }
5899 #endif
5900         return false;
5901 }
5902
5903 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5904                                                 int vector)
5905 {
5906         struct vcpu_vmx *vmx = to_vmx(vcpu);
5907
5908         if (is_guest_mode(vcpu) &&
5909             vector == vmx->nested.posted_intr_nv) {
5910                 /*
5911                  * If a posted intr is not recognized by hardware,
5912                  * we will accomplish it in the next vmentry.
5913                  */
5914                 vmx->nested.pi_pending = true;
5915                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5916                 /* the PIR and ON have been set by L1. */
5917                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
5918                         kvm_vcpu_kick(vcpu);
5919                 return 0;
5920         }
5921         return -1;
5922 }
5923 /*
5924  * Send interrupt to vcpu via posted interrupt way.
5925  * 1. If target vcpu is running(non-root mode), send posted interrupt
5926  * notification to vcpu and hardware will sync PIR to vIRR atomically.
5927  * 2. If target vcpu isn't running(root mode), kick it to pick up the
5928  * interrupt from PIR in next vmentry.
5929  */
5930 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5931 {
5932         struct vcpu_vmx *vmx = to_vmx(vcpu);
5933         int r;
5934
5935         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5936         if (!r)
5937                 return;
5938
5939         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5940                 return;
5941
5942         /* If a previous notification has sent the IPI, nothing to do.  */
5943         if (pi_test_and_set_on(&vmx->pi_desc))
5944                 return;
5945
5946         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5947                 kvm_vcpu_kick(vcpu);
5948 }
5949
5950 /*
5951  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5952  * will not change in the lifetime of the guest.
5953  * Note that host-state that does change is set elsewhere. E.g., host-state
5954  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5955  */
5956 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5957 {
5958         u32 low32, high32;
5959         unsigned long tmpl;
5960         struct desc_ptr dt;
5961         unsigned long cr0, cr3, cr4;
5962
5963         cr0 = read_cr0();
5964         WARN_ON(cr0 & X86_CR0_TS);
5965         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5966
5967         /*
5968          * Save the most likely value for this task's CR3 in the VMCS.
5969          * We can't use __get_current_cr3_fast() because we're not atomic.
5970          */
5971         cr3 = __read_cr3();
5972         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
5973         vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5974
5975         /* Save the most likely value for this task's CR4 in the VMCS. */
5976         cr4 = cr4_read_shadow();
5977         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5978         vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5979
5980         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5981 #ifdef CONFIG_X86_64
5982         /*
5983          * Load null selectors, so we can avoid reloading them in
5984          * __vmx_load_host_state(), in case userspace uses the null selectors
5985          * too (the expected case).
5986          */
5987         vmcs_write16(HOST_DS_SELECTOR, 0);
5988         vmcs_write16(HOST_ES_SELECTOR, 0);
5989 #else
5990         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5991         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5992 #endif
5993         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5994         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5995
5996         store_idt(&dt);
5997         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5998         vmx->host_idt_base = dt.address;
5999
6000         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
6001
6002         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
6003         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
6004         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
6005         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
6006
6007         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
6008                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
6009                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
6010         }
6011 }
6012
6013 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
6014 {
6015         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
6016         if (enable_ept)
6017                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
6018         if (is_guest_mode(&vmx->vcpu))
6019                 vmx->vcpu.arch.cr4_guest_owned_bits &=
6020                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
6021         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
6022 }
6023
6024 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
6025 {
6026         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
6027
6028         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
6029                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
6030
6031         if (!enable_vnmi)
6032                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
6033
6034         /* Enable the preemption timer dynamically */
6035         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
6036         return pin_based_exec_ctrl;
6037 }
6038
6039 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
6040 {
6041         struct vcpu_vmx *vmx = to_vmx(vcpu);
6042
6043         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6044         if (cpu_has_secondary_exec_ctrls()) {
6045                 if (kvm_vcpu_apicv_active(vcpu))
6046                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
6047                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
6048                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6049                 else
6050                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6051                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
6052                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6053         }
6054
6055         if (cpu_has_vmx_msr_bitmap())
6056                 vmx_update_msr_bitmap(vcpu);
6057 }
6058
6059 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
6060 {
6061         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
6062
6063         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
6064                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
6065
6066         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
6067                 exec_control &= ~CPU_BASED_TPR_SHADOW;
6068 #ifdef CONFIG_X86_64
6069                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
6070                                 CPU_BASED_CR8_LOAD_EXITING;
6071 #endif
6072         }
6073         if (!enable_ept)
6074                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
6075                                 CPU_BASED_CR3_LOAD_EXITING  |
6076                                 CPU_BASED_INVLPG_EXITING;
6077         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
6078                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
6079                                 CPU_BASED_MONITOR_EXITING);
6080         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
6081                 exec_control &= ~CPU_BASED_HLT_EXITING;
6082         return exec_control;
6083 }
6084
6085 static bool vmx_rdrand_supported(void)
6086 {
6087         return vmcs_config.cpu_based_2nd_exec_ctrl &
6088                 SECONDARY_EXEC_RDRAND_EXITING;
6089 }
6090
6091 static bool vmx_rdseed_supported(void)
6092 {
6093         return vmcs_config.cpu_based_2nd_exec_ctrl &
6094                 SECONDARY_EXEC_RDSEED_EXITING;
6095 }
6096
6097 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
6098 {
6099         struct kvm_vcpu *vcpu = &vmx->vcpu;
6100
6101         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
6102
6103         if (!cpu_need_virtualize_apic_accesses(vcpu))
6104                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6105         if (vmx->vpid == 0)
6106                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
6107         if (!enable_ept) {
6108                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
6109                 enable_unrestricted_guest = 0;
6110                 /* Enable INVPCID for non-ept guests may cause performance regression. */
6111                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6112         }
6113         if (!enable_unrestricted_guest)
6114                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
6115         if (kvm_pause_in_guest(vmx->vcpu.kvm))
6116                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
6117         if (!kvm_vcpu_apicv_active(vcpu))
6118                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
6119                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6120         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6121
6122         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
6123          * in vmx_set_cr4.  */
6124         exec_control &= ~SECONDARY_EXEC_DESC;
6125
6126         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
6127            (handle_vmptrld).
6128            We can NOT enable shadow_vmcs here because we don't have yet
6129            a current VMCS12
6130         */
6131         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6132
6133         if (!enable_pml)
6134                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
6135
6136         if (vmx_xsaves_supported()) {
6137                 /* Exposing XSAVES only when XSAVE is exposed */
6138                 bool xsaves_enabled =
6139                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
6140                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
6141
6142                 if (!xsaves_enabled)
6143                         exec_control &= ~SECONDARY_EXEC_XSAVES;
6144
6145                 if (nested) {
6146                         if (xsaves_enabled)
6147                                 vmx->nested.msrs.secondary_ctls_high |=
6148                                         SECONDARY_EXEC_XSAVES;
6149                         else
6150                                 vmx->nested.msrs.secondary_ctls_high &=
6151                                         ~SECONDARY_EXEC_XSAVES;
6152                 }
6153         }
6154
6155         if (vmx_rdtscp_supported()) {
6156                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
6157                 if (!rdtscp_enabled)
6158                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6159
6160                 if (nested) {
6161                         if (rdtscp_enabled)
6162                                 vmx->nested.msrs.secondary_ctls_high |=
6163                                         SECONDARY_EXEC_RDTSCP;
6164                         else
6165                                 vmx->nested.msrs.secondary_ctls_high &=
6166                                         ~SECONDARY_EXEC_RDTSCP;
6167                 }
6168         }
6169
6170         if (vmx_invpcid_supported()) {
6171                 /* Exposing INVPCID only when PCID is exposed */
6172                 bool invpcid_enabled =
6173                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
6174                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
6175
6176                 if (!invpcid_enabled) {
6177                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6178                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
6179                 }
6180
6181                 if (nested) {
6182                         if (invpcid_enabled)
6183                                 vmx->nested.msrs.secondary_ctls_high |=
6184                                         SECONDARY_EXEC_ENABLE_INVPCID;
6185                         else
6186                                 vmx->nested.msrs.secondary_ctls_high &=
6187                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
6188                 }
6189         }
6190
6191         if (vmx_rdrand_supported()) {
6192                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
6193                 if (rdrand_enabled)
6194                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
6195
6196                 if (nested) {
6197                         if (rdrand_enabled)
6198                                 vmx->nested.msrs.secondary_ctls_high |=
6199                                         SECONDARY_EXEC_RDRAND_EXITING;
6200                         else
6201                                 vmx->nested.msrs.secondary_ctls_high &=
6202                                         ~SECONDARY_EXEC_RDRAND_EXITING;
6203                 }
6204         }
6205
6206         if (vmx_rdseed_supported()) {
6207                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
6208                 if (rdseed_enabled)
6209                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
6210
6211                 if (nested) {
6212                         if (rdseed_enabled)
6213                                 vmx->nested.msrs.secondary_ctls_high |=
6214                                         SECONDARY_EXEC_RDSEED_EXITING;
6215                         else
6216                                 vmx->nested.msrs.secondary_ctls_high &=
6217                                         ~SECONDARY_EXEC_RDSEED_EXITING;
6218                 }
6219         }
6220
6221         vmx->secondary_exec_control = exec_control;
6222 }
6223
6224 static void ept_set_mmio_spte_mask(void)
6225 {
6226         /*
6227          * EPT Misconfigurations can be generated if the value of bits 2:0
6228          * of an EPT paging-structure entry is 110b (write/execute).
6229          */
6230         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
6231                                    VMX_EPT_MISCONFIG_WX_VALUE);
6232 }
6233
6234 #define VMX_XSS_EXIT_BITMAP 0
6235 /*
6236  * Sets up the vmcs for emulated real mode.
6237  */
6238 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
6239 {
6240 #ifdef CONFIG_X86_64
6241         unsigned long a;
6242 #endif
6243         int i;
6244
6245         if (enable_shadow_vmcs) {
6246                 /*
6247                  * At vCPU creation, "VMWRITE to any supported field
6248                  * in the VMCS" is supported, so use the more
6249                  * permissive vmx_vmread_bitmap to specify both read
6250                  * and write permissions for the shadow VMCS.
6251                  */
6252                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
6253                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmread_bitmap));
6254         }
6255         if (cpu_has_vmx_msr_bitmap())
6256                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
6257
6258         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
6259
6260         /* Control */
6261         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6262         vmx->hv_deadline_tsc = -1;
6263
6264         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6265
6266         if (cpu_has_secondary_exec_ctrls()) {
6267                 vmx_compute_secondary_exec_control(vmx);
6268                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6269                              vmx->secondary_exec_control);
6270         }
6271
6272         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
6273                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
6274                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
6275                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
6276                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
6277
6278                 vmcs_write16(GUEST_INTR_STATUS, 0);
6279
6280                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
6281                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
6282         }
6283
6284         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
6285                 vmcs_write32(PLE_GAP, ple_gap);
6286                 vmx->ple_window = ple_window;
6287                 vmx->ple_window_dirty = true;
6288         }
6289
6290         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
6291         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6292         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
6293
6294         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
6295         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
6296         vmx_set_constant_host_state(vmx);
6297 #ifdef CONFIG_X86_64
6298         rdmsrl(MSR_FS_BASE, a);
6299         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
6300         rdmsrl(MSR_GS_BASE, a);
6301         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
6302 #else
6303         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
6304         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6305 #endif
6306
6307         if (cpu_has_vmx_vmfunc())
6308                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
6309
6310         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
6311         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
6312         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
6313         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6314         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
6315
6316         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6317                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6318
6319         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6320                 u32 index = vmx_msr_index[i];
6321                 u32 data_low, data_high;
6322                 int j = vmx->nmsrs;
6323
6324                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6325                         continue;
6326                 if (wrmsr_safe(index, data_low, data_high) < 0)
6327                         continue;
6328                 vmx->guest_msrs[j].index = i;
6329                 vmx->guest_msrs[j].data = 0;
6330                 vmx->guest_msrs[j].mask = -1ull;
6331                 ++vmx->nmsrs;
6332         }
6333
6334         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
6335                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, vmx->arch_capabilities);
6336
6337         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6338
6339         /* 22.2.1, 20.8.1 */
6340         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
6341
6342         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
6343         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
6344
6345         set_cr4_guest_host_mask(vmx);
6346
6347         if (vmx_xsaves_supported())
6348                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
6349
6350         if (enable_pml) {
6351                 ASSERT(vmx->pml_pg);
6352                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
6353                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
6354         }
6355 }
6356
6357 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
6358 {
6359         struct vcpu_vmx *vmx = to_vmx(vcpu);
6360         struct msr_data apic_base_msr;
6361         u64 cr0;
6362
6363         vmx->rmode.vm86_active = 0;
6364         vmx->spec_ctrl = 0;
6365
6366         vcpu->arch.microcode_version = 0x100000000ULL;
6367         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
6368         kvm_set_cr8(vcpu, 0);
6369
6370         if (!init_event) {
6371                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
6372                                      MSR_IA32_APICBASE_ENABLE;
6373                 if (kvm_vcpu_is_reset_bsp(vcpu))
6374                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
6375                 apic_base_msr.host_initiated = true;
6376                 kvm_set_apic_base(vcpu, &apic_base_msr);
6377         }
6378
6379         vmx_segment_cache_clear(vmx);
6380
6381         seg_setup(VCPU_SREG_CS);
6382         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
6383         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
6384
6385         seg_setup(VCPU_SREG_DS);
6386         seg_setup(VCPU_SREG_ES);
6387         seg_setup(VCPU_SREG_FS);
6388         seg_setup(VCPU_SREG_GS);
6389         seg_setup(VCPU_SREG_SS);
6390
6391         vmcs_write16(GUEST_TR_SELECTOR, 0);
6392         vmcs_writel(GUEST_TR_BASE, 0);
6393         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
6394         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
6395
6396         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
6397         vmcs_writel(GUEST_LDTR_BASE, 0);
6398         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
6399         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
6400
6401         if (!init_event) {
6402                 vmcs_write32(GUEST_SYSENTER_CS, 0);
6403                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
6404                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
6405                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
6406         }
6407
6408         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6409         kvm_rip_write(vcpu, 0xfff0);
6410
6411         vmcs_writel(GUEST_GDTR_BASE, 0);
6412         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
6413
6414         vmcs_writel(GUEST_IDTR_BASE, 0);
6415         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
6416
6417         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
6418         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
6419         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
6420         if (kvm_mpx_supported())
6421                 vmcs_write64(GUEST_BNDCFGS, 0);
6422
6423         setup_msrs(vmx);
6424
6425         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
6426
6427         if (cpu_has_vmx_tpr_shadow() && !init_event) {
6428                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
6429                 if (cpu_need_tpr_shadow(vcpu))
6430                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
6431                                      __pa(vcpu->arch.apic->regs));
6432                 vmcs_write32(TPR_THRESHOLD, 0);
6433         }
6434
6435         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6436
6437         if (vmx->vpid != 0)
6438                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6439
6440         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
6441         vmx->vcpu.arch.cr0 = cr0;
6442         vmx_set_cr0(vcpu, cr0); /* enter rmode */
6443         vmx_set_cr4(vcpu, 0);
6444         vmx_set_efer(vcpu, 0);
6445
6446         update_exception_bitmap(vcpu);
6447
6448         vpid_sync_context(vmx->vpid);
6449         if (init_event)
6450                 vmx_clear_hlt(vcpu);
6451 }
6452
6453 /*
6454  * In nested virtualization, check if L1 asked to exit on external interrupts.
6455  * For most existing hypervisors, this will always return true.
6456  */
6457 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
6458 {
6459         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
6460                 PIN_BASED_EXT_INTR_MASK;
6461 }
6462
6463 /*
6464  * In nested virtualization, check if L1 has set
6465  * VM_EXIT_ACK_INTR_ON_EXIT
6466  */
6467 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
6468 {
6469         return get_vmcs12(vcpu)->vm_exit_controls &
6470                 VM_EXIT_ACK_INTR_ON_EXIT;
6471 }
6472
6473 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
6474 {
6475         return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu));
6476 }
6477
6478 static void enable_irq_window(struct kvm_vcpu *vcpu)
6479 {
6480         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6481                       CPU_BASED_VIRTUAL_INTR_PENDING);
6482 }
6483
6484 static void enable_nmi_window(struct kvm_vcpu *vcpu)
6485 {
6486         if (!enable_vnmi ||
6487             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
6488                 enable_irq_window(vcpu);
6489                 return;
6490         }
6491
6492         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6493                       CPU_BASED_VIRTUAL_NMI_PENDING);
6494 }
6495
6496 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
6497 {
6498         struct vcpu_vmx *vmx = to_vmx(vcpu);
6499         uint32_t intr;
6500         int irq = vcpu->arch.interrupt.nr;
6501
6502         trace_kvm_inj_virq(irq);
6503
6504         ++vcpu->stat.irq_injections;
6505         if (vmx->rmode.vm86_active) {
6506                 int inc_eip = 0;
6507                 if (vcpu->arch.interrupt.soft)
6508                         inc_eip = vcpu->arch.event_exit_inst_len;
6509                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
6510                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6511                 return;
6512         }
6513         intr = irq | INTR_INFO_VALID_MASK;
6514         if (vcpu->arch.interrupt.soft) {
6515                 intr |= INTR_TYPE_SOFT_INTR;
6516                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6517                              vmx->vcpu.arch.event_exit_inst_len);
6518         } else
6519                 intr |= INTR_TYPE_EXT_INTR;
6520         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
6521
6522         vmx_clear_hlt(vcpu);
6523 }
6524
6525 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
6526 {
6527         struct vcpu_vmx *vmx = to_vmx(vcpu);
6528
6529         if (!enable_vnmi) {
6530                 /*
6531                  * Tracking the NMI-blocked state in software is built upon
6532                  * finding the next open IRQ window. This, in turn, depends on
6533                  * well-behaving guests: They have to keep IRQs disabled at
6534                  * least as long as the NMI handler runs. Otherwise we may
6535                  * cause NMI nesting, maybe breaking the guest. But as this is
6536                  * highly unlikely, we can live with the residual risk.
6537                  */
6538                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
6539                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6540         }
6541
6542         ++vcpu->stat.nmi_injections;
6543         vmx->loaded_vmcs->nmi_known_unmasked = false;
6544
6545         if (vmx->rmode.vm86_active) {
6546                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
6547                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6548                 return;
6549         }
6550
6551         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6552                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
6553
6554         vmx_clear_hlt(vcpu);
6555 }
6556
6557 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
6558 {
6559         struct vcpu_vmx *vmx = to_vmx(vcpu);
6560         bool masked;
6561
6562         if (!enable_vnmi)
6563                 return vmx->loaded_vmcs->soft_vnmi_blocked;
6564         if (vmx->loaded_vmcs->nmi_known_unmasked)
6565                 return false;
6566         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
6567         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6568         return masked;
6569 }
6570
6571 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
6572 {
6573         struct vcpu_vmx *vmx = to_vmx(vcpu);
6574
6575         if (!enable_vnmi) {
6576                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
6577                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
6578                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
6579                 }
6580         } else {
6581                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6582                 if (masked)
6583                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6584                                       GUEST_INTR_STATE_NMI);
6585                 else
6586                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
6587                                         GUEST_INTR_STATE_NMI);
6588         }
6589 }
6590
6591 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
6592 {
6593         if (to_vmx(vcpu)->nested.nested_run_pending)
6594                 return 0;
6595
6596         if (!enable_vnmi &&
6597             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
6598                 return 0;
6599
6600         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6601                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
6602                    | GUEST_INTR_STATE_NMI));
6603 }
6604
6605 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
6606 {
6607         return (!to_vmx(vcpu)->nested.nested_run_pending &&
6608                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
6609                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6610                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
6611 }
6612
6613 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
6614 {
6615         int ret;
6616
6617         if (enable_unrestricted_guest)
6618                 return 0;
6619
6620         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
6621                                     PAGE_SIZE * 3);
6622         if (ret)
6623                 return ret;
6624         to_kvm_vmx(kvm)->tss_addr = addr;
6625         return init_rmode_tss(kvm);
6626 }
6627
6628 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
6629 {
6630         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
6631         return 0;
6632 }
6633
6634 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6635 {
6636         switch (vec) {
6637         case BP_VECTOR:
6638                 /*
6639                  * Update instruction length as we may reinject the exception
6640                  * from user space while in guest debugging mode.
6641                  */
6642                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
6643                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6644                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6645                         return false;
6646                 /* fall through */
6647         case DB_VECTOR:
6648                 if (vcpu->guest_debug &
6649                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6650                         return false;
6651                 /* fall through */
6652         case DE_VECTOR:
6653         case OF_VECTOR:
6654         case BR_VECTOR:
6655         case UD_VECTOR:
6656         case DF_VECTOR:
6657         case SS_VECTOR:
6658         case GP_VECTOR:
6659         case MF_VECTOR:
6660                 return true;
6661         break;
6662         }
6663         return false;
6664 }
6665
6666 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
6667                                   int vec, u32 err_code)
6668 {
6669         /*
6670          * Instruction with address size override prefix opcode 0x67
6671          * Cause the #SS fault with 0 error code in VM86 mode.
6672          */
6673         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
6674                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
6675                         if (vcpu->arch.halt_request) {
6676                                 vcpu->arch.halt_request = 0;
6677                                 return kvm_vcpu_halt(vcpu);
6678                         }
6679                         return 1;
6680                 }
6681                 return 0;
6682         }
6683
6684         /*
6685          * Forward all other exceptions that are valid in real mode.
6686          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
6687          *        the required debugging infrastructure rework.
6688          */
6689         kvm_queue_exception(vcpu, vec);
6690         return 1;
6691 }
6692
6693 /*
6694  * Trigger machine check on the host. We assume all the MSRs are already set up
6695  * by the CPU and that we still run on the same CPU as the MCE occurred on.
6696  * We pass a fake environment to the machine check handler because we want
6697  * the guest to be always treated like user space, no matter what context
6698  * it used internally.
6699  */
6700 static void kvm_machine_check(void)
6701 {
6702 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
6703         struct pt_regs regs = {
6704                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
6705                 .flags = X86_EFLAGS_IF,
6706         };
6707
6708         do_machine_check(&regs, 0);
6709 #endif
6710 }
6711
6712 static int handle_machine_check(struct kvm_vcpu *vcpu)
6713 {
6714         /* already handled by vcpu_run */
6715         return 1;
6716 }
6717
6718 static int handle_exception(struct kvm_vcpu *vcpu)
6719 {
6720         struct vcpu_vmx *vmx = to_vmx(vcpu);
6721         struct kvm_run *kvm_run = vcpu->run;
6722         u32 intr_info, ex_no, error_code;
6723         unsigned long cr2, rip, dr6;
6724         u32 vect_info;
6725         enum emulation_result er;
6726
6727         vect_info = vmx->idt_vectoring_info;
6728         intr_info = vmx->exit_intr_info;
6729
6730         if (is_machine_check(intr_info))
6731                 return handle_machine_check(vcpu);
6732
6733         if (is_nmi(intr_info))
6734                 return 1;  /* already handled by vmx_vcpu_run() */
6735
6736         if (is_invalid_opcode(intr_info))
6737                 return handle_ud(vcpu);
6738
6739         error_code = 0;
6740         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6741                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6742
6743         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
6744                 WARN_ON_ONCE(!enable_vmware_backdoor);
6745                 er = emulate_instruction(vcpu,
6746                         EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
6747                 if (er == EMULATE_USER_EXIT)
6748                         return 0;
6749                 else if (er != EMULATE_DONE)
6750                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
6751                 return 1;
6752         }
6753
6754         /*
6755          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
6756          * MMIO, it is better to report an internal error.
6757          * See the comments in vmx_handle_exit.
6758          */
6759         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
6760             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
6761                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6762                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
6763                 vcpu->run->internal.ndata = 3;
6764                 vcpu->run->internal.data[0] = vect_info;
6765                 vcpu->run->internal.data[1] = intr_info;
6766                 vcpu->run->internal.data[2] = error_code;
6767                 return 0;
6768         }
6769
6770         if (is_page_fault(intr_info)) {
6771                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
6772                 /* EPT won't cause page fault directly */
6773                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
6774                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6775         }
6776
6777         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
6778
6779         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
6780                 return handle_rmode_exception(vcpu, ex_no, error_code);
6781
6782         switch (ex_no) {
6783         case AC_VECTOR:
6784                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
6785                 return 1;
6786         case DB_VECTOR:
6787                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
6788                 if (!(vcpu->guest_debug &
6789                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
6790                         vcpu->arch.dr6 &= ~15;
6791                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
6792                         if (is_icebp(intr_info))
6793                                 skip_emulated_instruction(vcpu);
6794
6795                         kvm_queue_exception(vcpu, DB_VECTOR);
6796                         return 1;
6797                 }
6798                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
6799                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
6800                 /* fall through */
6801         case BP_VECTOR:
6802                 /*
6803                  * Update instruction length as we may reinject #BP from
6804                  * user space while in guest debugging mode. Reading it for
6805                  * #DB as well causes no harm, it is not used in that case.
6806                  */
6807                 vmx->vcpu.arch.event_exit_inst_len =
6808                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6809                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6810                 rip = kvm_rip_read(vcpu);
6811                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
6812                 kvm_run->debug.arch.exception = ex_no;
6813                 break;
6814         default:
6815                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
6816                 kvm_run->ex.exception = ex_no;
6817                 kvm_run->ex.error_code = error_code;
6818                 break;
6819         }
6820         return 0;
6821 }
6822
6823 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6824 {
6825         ++vcpu->stat.irq_exits;
6826         return 1;
6827 }
6828
6829 static int handle_triple_fault(struct kvm_vcpu *vcpu)
6830 {
6831         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6832         vcpu->mmio_needed = 0;
6833         return 0;
6834 }
6835
6836 static int handle_io(struct kvm_vcpu *vcpu)
6837 {
6838         unsigned long exit_qualification;
6839         int size, in, string;
6840         unsigned port;
6841
6842         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6843         string = (exit_qualification & 16) != 0;
6844
6845         ++vcpu->stat.io_exits;
6846
6847         if (string)
6848                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6849
6850         port = exit_qualification >> 16;
6851         size = (exit_qualification & 7) + 1;
6852         in = (exit_qualification & 8) != 0;
6853
6854         return kvm_fast_pio(vcpu, size, port, in);
6855 }
6856
6857 static void
6858 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
6859 {
6860         /*
6861          * Patch in the VMCALL instruction:
6862          */
6863         hypercall[0] = 0x0f;
6864         hypercall[1] = 0x01;
6865         hypercall[2] = 0xc1;
6866 }
6867
6868 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6869 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
6870 {
6871         if (is_guest_mode(vcpu)) {
6872                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6873                 unsigned long orig_val = val;
6874
6875                 /*
6876                  * We get here when L2 changed cr0 in a way that did not change
6877                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6878                  * but did change L0 shadowed bits. So we first calculate the
6879                  * effective cr0 value that L1 would like to write into the
6880                  * hardware. It consists of the L2-owned bits from the new
6881                  * value combined with the L1-owned bits from L1's guest_cr0.
6882                  */
6883                 val = (val & ~vmcs12->cr0_guest_host_mask) |
6884                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
6885
6886                 if (!nested_guest_cr0_valid(vcpu, val))
6887                         return 1;
6888
6889                 if (kvm_set_cr0(vcpu, val))
6890                         return 1;
6891                 vmcs_writel(CR0_READ_SHADOW, orig_val);
6892                 return 0;
6893         } else {
6894                 if (to_vmx(vcpu)->nested.vmxon &&
6895                     !nested_host_cr0_valid(vcpu, val))
6896                         return 1;
6897
6898                 return kvm_set_cr0(vcpu, val);
6899         }
6900 }
6901
6902 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
6903 {
6904         if (is_guest_mode(vcpu)) {
6905                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6906                 unsigned long orig_val = val;
6907
6908                 /* analogously to handle_set_cr0 */
6909                 val = (val & ~vmcs12->cr4_guest_host_mask) |
6910                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
6911                 if (kvm_set_cr4(vcpu, val))
6912                         return 1;
6913                 vmcs_writel(CR4_READ_SHADOW, orig_val);
6914                 return 0;
6915         } else
6916                 return kvm_set_cr4(vcpu, val);
6917 }
6918
6919 static int handle_desc(struct kvm_vcpu *vcpu)
6920 {
6921         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
6922         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6923 }
6924
6925 static int handle_cr(struct kvm_vcpu *vcpu)
6926 {
6927         unsigned long exit_qualification, val;
6928         int cr;
6929         int reg;
6930         int err;
6931         int ret;
6932
6933         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6934         cr = exit_qualification & 15;
6935         reg = (exit_qualification >> 8) & 15;
6936         switch ((exit_qualification >> 4) & 3) {
6937         case 0: /* mov to cr */
6938                 val = kvm_register_readl(vcpu, reg);
6939                 trace_kvm_cr_write(cr, val);
6940                 switch (cr) {
6941                 case 0:
6942                         err = handle_set_cr0(vcpu, val);
6943                         return kvm_complete_insn_gp(vcpu, err);
6944                 case 3:
6945                         WARN_ON_ONCE(enable_unrestricted_guest);
6946                         err = kvm_set_cr3(vcpu, val);
6947                         return kvm_complete_insn_gp(vcpu, err);
6948                 case 4:
6949                         err = handle_set_cr4(vcpu, val);
6950                         return kvm_complete_insn_gp(vcpu, err);
6951                 case 8: {
6952                                 u8 cr8_prev = kvm_get_cr8(vcpu);
6953                                 u8 cr8 = (u8)val;
6954                                 err = kvm_set_cr8(vcpu, cr8);
6955                                 ret = kvm_complete_insn_gp(vcpu, err);
6956                                 if (lapic_in_kernel(vcpu))
6957                                         return ret;
6958                                 if (cr8_prev <= cr8)
6959                                         return ret;
6960                                 /*
6961                                  * TODO: we might be squashing a
6962                                  * KVM_GUESTDBG_SINGLESTEP-triggered
6963                                  * KVM_EXIT_DEBUG here.
6964                                  */
6965                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
6966                                 return 0;
6967                         }
6968                 }
6969                 break;
6970         case 2: /* clts */
6971                 WARN_ONCE(1, "Guest should always own CR0.TS");
6972                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6973                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6974                 return kvm_skip_emulated_instruction(vcpu);
6975         case 1: /*mov from cr*/
6976                 switch (cr) {
6977                 case 3:
6978                         WARN_ON_ONCE(enable_unrestricted_guest);
6979                         val = kvm_read_cr3(vcpu);
6980                         kvm_register_write(vcpu, reg, val);
6981                         trace_kvm_cr_read(cr, val);
6982                         return kvm_skip_emulated_instruction(vcpu);
6983                 case 8:
6984                         val = kvm_get_cr8(vcpu);
6985                         kvm_register_write(vcpu, reg, val);
6986                         trace_kvm_cr_read(cr, val);
6987                         return kvm_skip_emulated_instruction(vcpu);
6988                 }
6989                 break;
6990         case 3: /* lmsw */
6991                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6992                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6993                 kvm_lmsw(vcpu, val);
6994
6995                 return kvm_skip_emulated_instruction(vcpu);
6996         default:
6997                 break;
6998         }
6999         vcpu->run->exit_reason = 0;
7000         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
7001                (int)(exit_qualification >> 4) & 3, cr);
7002         return 0;
7003 }
7004
7005 static int handle_dr(struct kvm_vcpu *vcpu)
7006 {
7007         unsigned long exit_qualification;
7008         int dr, dr7, reg;
7009
7010         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7011         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
7012
7013         /* First, if DR does not exist, trigger UD */
7014         if (!kvm_require_dr(vcpu, dr))
7015                 return 1;
7016
7017         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
7018         if (!kvm_require_cpl(vcpu, 0))
7019                 return 1;
7020         dr7 = vmcs_readl(GUEST_DR7);
7021         if (dr7 & DR7_GD) {
7022                 /*
7023                  * As the vm-exit takes precedence over the debug trap, we
7024                  * need to emulate the latter, either for the host or the
7025                  * guest debugging itself.
7026                  */
7027                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7028                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
7029                         vcpu->run->debug.arch.dr7 = dr7;
7030                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
7031                         vcpu->run->debug.arch.exception = DB_VECTOR;
7032                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
7033                         return 0;
7034                 } else {
7035                         vcpu->arch.dr6 &= ~15;
7036                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
7037                         kvm_queue_exception(vcpu, DB_VECTOR);
7038                         return 1;
7039                 }
7040         }
7041
7042         if (vcpu->guest_debug == 0) {
7043                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7044                                 CPU_BASED_MOV_DR_EXITING);
7045
7046                 /*
7047                  * No more DR vmexits; force a reload of the debug registers
7048                  * and reenter on this instruction.  The next vmexit will
7049                  * retrieve the full state of the debug registers.
7050                  */
7051                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
7052                 return 1;
7053         }
7054
7055         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
7056         if (exit_qualification & TYPE_MOV_FROM_DR) {
7057                 unsigned long val;
7058
7059                 if (kvm_get_dr(vcpu, dr, &val))
7060                         return 1;
7061                 kvm_register_write(vcpu, reg, val);
7062         } else
7063                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
7064                         return 1;
7065
7066         return kvm_skip_emulated_instruction(vcpu);
7067 }
7068
7069 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
7070 {
7071         return vcpu->arch.dr6;
7072 }
7073
7074 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
7075 {
7076 }
7077
7078 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
7079 {
7080         get_debugreg(vcpu->arch.db[0], 0);
7081         get_debugreg(vcpu->arch.db[1], 1);
7082         get_debugreg(vcpu->arch.db[2], 2);
7083         get_debugreg(vcpu->arch.db[3], 3);
7084         get_debugreg(vcpu->arch.dr6, 6);
7085         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
7086
7087         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
7088         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
7089 }
7090
7091 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
7092 {
7093         vmcs_writel(GUEST_DR7, val);
7094 }
7095
7096 static int handle_cpuid(struct kvm_vcpu *vcpu)
7097 {
7098         return kvm_emulate_cpuid(vcpu);
7099 }
7100
7101 static int handle_rdmsr(struct kvm_vcpu *vcpu)
7102 {
7103         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7104         struct msr_data msr_info;
7105
7106         msr_info.index = ecx;
7107         msr_info.host_initiated = false;
7108         if (vmx_get_msr(vcpu, &msr_info)) {
7109                 trace_kvm_msr_read_ex(ecx);
7110                 kvm_inject_gp(vcpu, 0);
7111                 return 1;
7112         }
7113
7114         trace_kvm_msr_read(ecx, msr_info.data);
7115
7116         /* FIXME: handling of bits 32:63 of rax, rdx */
7117         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
7118         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
7119         return kvm_skip_emulated_instruction(vcpu);
7120 }
7121
7122 static int handle_wrmsr(struct kvm_vcpu *vcpu)
7123 {
7124         struct msr_data msr;
7125         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7126         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
7127                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
7128
7129         msr.data = data;
7130         msr.index = ecx;
7131         msr.host_initiated = false;
7132         if (kvm_set_msr(vcpu, &msr) != 0) {
7133                 trace_kvm_msr_write_ex(ecx, data);
7134                 kvm_inject_gp(vcpu, 0);
7135                 return 1;
7136         }
7137
7138         trace_kvm_msr_write(ecx, data);
7139         return kvm_skip_emulated_instruction(vcpu);
7140 }
7141
7142 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
7143 {
7144         kvm_apic_update_ppr(vcpu);
7145         return 1;
7146 }
7147
7148 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
7149 {
7150         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7151                         CPU_BASED_VIRTUAL_INTR_PENDING);
7152
7153         kvm_make_request(KVM_REQ_EVENT, vcpu);
7154
7155         ++vcpu->stat.irq_window_exits;
7156         return 1;
7157 }
7158
7159 static int handle_halt(struct kvm_vcpu *vcpu)
7160 {
7161         return kvm_emulate_halt(vcpu);
7162 }
7163
7164 static int handle_vmcall(struct kvm_vcpu *vcpu)
7165 {
7166         return kvm_emulate_hypercall(vcpu);
7167 }
7168
7169 static int handle_invd(struct kvm_vcpu *vcpu)
7170 {
7171         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
7172 }
7173
7174 static int handle_invlpg(struct kvm_vcpu *vcpu)
7175 {
7176         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7177
7178         kvm_mmu_invlpg(vcpu, exit_qualification);
7179         return kvm_skip_emulated_instruction(vcpu);
7180 }
7181
7182 static int handle_rdpmc(struct kvm_vcpu *vcpu)
7183 {
7184         int err;
7185
7186         err = kvm_rdpmc(vcpu);
7187         return kvm_complete_insn_gp(vcpu, err);
7188 }
7189
7190 static int handle_wbinvd(struct kvm_vcpu *vcpu)
7191 {
7192         return kvm_emulate_wbinvd(vcpu);
7193 }
7194
7195 static int handle_xsetbv(struct kvm_vcpu *vcpu)
7196 {
7197         u64 new_bv = kvm_read_edx_eax(vcpu);
7198         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
7199
7200         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
7201                 return kvm_skip_emulated_instruction(vcpu);
7202         return 1;
7203 }
7204
7205 static int handle_xsaves(struct kvm_vcpu *vcpu)
7206 {
7207         kvm_skip_emulated_instruction(vcpu);
7208         WARN(1, "this should never happen\n");
7209         return 1;
7210 }
7211
7212 static int handle_xrstors(struct kvm_vcpu *vcpu)
7213 {
7214         kvm_skip_emulated_instruction(vcpu);
7215         WARN(1, "this should never happen\n");
7216         return 1;
7217 }
7218
7219 static int handle_apic_access(struct kvm_vcpu *vcpu)
7220 {
7221         if (likely(fasteoi)) {
7222                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7223                 int access_type, offset;
7224
7225                 access_type = exit_qualification & APIC_ACCESS_TYPE;
7226                 offset = exit_qualification & APIC_ACCESS_OFFSET;
7227                 /*
7228                  * Sane guest uses MOV to write EOI, with written value
7229                  * not cared. So make a short-circuit here by avoiding
7230                  * heavy instruction emulation.
7231                  */
7232                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
7233                     (offset == APIC_EOI)) {
7234                         kvm_lapic_set_eoi(vcpu);
7235                         return kvm_skip_emulated_instruction(vcpu);
7236                 }
7237         }
7238         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
7239 }
7240
7241 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
7242 {
7243         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7244         int vector = exit_qualification & 0xff;
7245
7246         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
7247         kvm_apic_set_eoi_accelerated(vcpu, vector);
7248         return 1;
7249 }
7250
7251 static int handle_apic_write(struct kvm_vcpu *vcpu)
7252 {
7253         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7254         u32 offset = exit_qualification & 0xfff;
7255
7256         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
7257         kvm_apic_write_nodecode(vcpu, offset);
7258         return 1;
7259 }
7260
7261 static int handle_task_switch(struct kvm_vcpu *vcpu)
7262 {
7263         struct vcpu_vmx *vmx = to_vmx(vcpu);
7264         unsigned long exit_qualification;
7265         bool has_error_code = false;
7266         u32 error_code = 0;
7267         u16 tss_selector;
7268         int reason, type, idt_v, idt_index;
7269
7270         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7271         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
7272         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
7273
7274         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7275
7276         reason = (u32)exit_qualification >> 30;
7277         if (reason == TASK_SWITCH_GATE && idt_v) {
7278                 switch (type) {
7279                 case INTR_TYPE_NMI_INTR:
7280                         vcpu->arch.nmi_injected = false;
7281                         vmx_set_nmi_mask(vcpu, true);
7282                         break;
7283                 case INTR_TYPE_EXT_INTR:
7284                 case INTR_TYPE_SOFT_INTR:
7285                         kvm_clear_interrupt_queue(vcpu);
7286                         break;
7287                 case INTR_TYPE_HARD_EXCEPTION:
7288                         if (vmx->idt_vectoring_info &
7289                             VECTORING_INFO_DELIVER_CODE_MASK) {
7290                                 has_error_code = true;
7291                                 error_code =
7292                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
7293                         }
7294                         /* fall through */
7295                 case INTR_TYPE_SOFT_EXCEPTION:
7296                         kvm_clear_exception_queue(vcpu);
7297                         break;
7298                 default:
7299                         break;
7300                 }
7301         }
7302         tss_selector = exit_qualification;
7303
7304         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
7305                        type != INTR_TYPE_EXT_INTR &&
7306                        type != INTR_TYPE_NMI_INTR))
7307                 skip_emulated_instruction(vcpu);
7308
7309         if (kvm_task_switch(vcpu, tss_selector,
7310                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
7311                             has_error_code, error_code) == EMULATE_FAIL) {
7312                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7313                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7314                 vcpu->run->internal.ndata = 0;
7315                 return 0;
7316         }
7317
7318         /*
7319          * TODO: What about debug traps on tss switch?
7320          *       Are we supposed to inject them and update dr6?
7321          */
7322
7323         return 1;
7324 }
7325
7326 static int handle_ept_violation(struct kvm_vcpu *vcpu)
7327 {
7328         unsigned long exit_qualification;
7329         gpa_t gpa;
7330         u64 error_code;
7331
7332         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7333
7334         /*
7335          * EPT violation happened while executing iret from NMI,
7336          * "blocked by NMI" bit has to be set before next VM entry.
7337          * There are errata that may cause this bit to not be set:
7338          * AAK134, BY25.
7339          */
7340         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7341                         enable_vnmi &&
7342                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7343                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
7344
7345         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7346         trace_kvm_page_fault(gpa, exit_qualification);
7347
7348         /* Is it a read fault? */
7349         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
7350                      ? PFERR_USER_MASK : 0;
7351         /* Is it a write fault? */
7352         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
7353                       ? PFERR_WRITE_MASK : 0;
7354         /* Is it a fetch fault? */
7355         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
7356                       ? PFERR_FETCH_MASK : 0;
7357         /* ept page table entry is present? */
7358         error_code |= (exit_qualification &
7359                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
7360                         EPT_VIOLATION_EXECUTABLE))
7361                       ? PFERR_PRESENT_MASK : 0;
7362
7363         error_code |= (exit_qualification & 0x100) != 0 ?
7364                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
7365
7366         vcpu->arch.exit_qualification = exit_qualification;
7367         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
7368 }
7369
7370 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
7371 {
7372         gpa_t gpa;
7373
7374         /*
7375          * A nested guest cannot optimize MMIO vmexits, because we have an
7376          * nGPA here instead of the required GPA.
7377          */
7378         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7379         if (!is_guest_mode(vcpu) &&
7380             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
7381                 trace_kvm_fast_mmio(gpa);
7382                 /*
7383                  * Doing kvm_skip_emulated_instruction() depends on undefined
7384                  * behavior: Intel's manual doesn't mandate
7385                  * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
7386                  * occurs and while on real hardware it was observed to be set,
7387                  * other hypervisors (namely Hyper-V) don't set it, we end up
7388                  * advancing IP with some random value. Disable fast mmio when
7389                  * running nested and keep it for real hardware in hope that
7390                  * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
7391                  */
7392                 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
7393                         return kvm_skip_emulated_instruction(vcpu);
7394                 else
7395                         return x86_emulate_instruction(vcpu, gpa, EMULTYPE_SKIP,
7396                                                        NULL, 0) == EMULATE_DONE;
7397         }
7398
7399         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
7400 }
7401
7402 static int handle_nmi_window(struct kvm_vcpu *vcpu)
7403 {
7404         WARN_ON_ONCE(!enable_vnmi);
7405         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7406                         CPU_BASED_VIRTUAL_NMI_PENDING);
7407         ++vcpu->stat.nmi_window_exits;
7408         kvm_make_request(KVM_REQ_EVENT, vcpu);
7409
7410         return 1;
7411 }
7412
7413 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
7414 {
7415         struct vcpu_vmx *vmx = to_vmx(vcpu);
7416         enum emulation_result err = EMULATE_DONE;
7417         int ret = 1;
7418         u32 cpu_exec_ctrl;
7419         bool intr_window_requested;
7420         unsigned count = 130;
7421
7422         /*
7423          * We should never reach the point where we are emulating L2
7424          * due to invalid guest state as that means we incorrectly
7425          * allowed a nested VMEntry with an invalid vmcs12.
7426          */
7427         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
7428
7429         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7430         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
7431
7432         while (vmx->emulation_required && count-- != 0) {
7433                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
7434                         return handle_interrupt_window(&vmx->vcpu);
7435
7436                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
7437                         return 1;
7438
7439                 err = emulate_instruction(vcpu, 0);
7440
7441                 if (err == EMULATE_USER_EXIT) {
7442                         ++vcpu->stat.mmio_exits;
7443                         ret = 0;
7444                         goto out;
7445                 }
7446
7447                 if (err != EMULATE_DONE)
7448                         goto emulation_error;
7449
7450                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
7451                     vcpu->arch.exception.pending)
7452                         goto emulation_error;
7453
7454                 if (vcpu->arch.halt_request) {
7455                         vcpu->arch.halt_request = 0;
7456                         ret = kvm_vcpu_halt(vcpu);
7457                         goto out;
7458                 }
7459
7460                 if (signal_pending(current))
7461                         goto out;
7462                 if (need_resched())
7463                         schedule();
7464         }
7465
7466 out:
7467         return ret;
7468
7469 emulation_error:
7470         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7471         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7472         vcpu->run->internal.ndata = 0;
7473         return 0;
7474 }
7475
7476 static void grow_ple_window(struct kvm_vcpu *vcpu)
7477 {
7478         struct vcpu_vmx *vmx = to_vmx(vcpu);
7479         int old = vmx->ple_window;
7480
7481         vmx->ple_window = __grow_ple_window(old, ple_window,
7482                                             ple_window_grow,
7483                                             ple_window_max);
7484
7485         if (vmx->ple_window != old)
7486                 vmx->ple_window_dirty = true;
7487
7488         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
7489 }
7490
7491 static void shrink_ple_window(struct kvm_vcpu *vcpu)
7492 {
7493         struct vcpu_vmx *vmx = to_vmx(vcpu);
7494         int old = vmx->ple_window;
7495
7496         vmx->ple_window = __shrink_ple_window(old, ple_window,
7497                                               ple_window_shrink,
7498                                               ple_window);
7499
7500         if (vmx->ple_window != old)
7501                 vmx->ple_window_dirty = true;
7502
7503         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
7504 }
7505
7506 /*
7507  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
7508  */
7509 static void wakeup_handler(void)
7510 {
7511         struct kvm_vcpu *vcpu;
7512         int cpu = smp_processor_id();
7513
7514         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7515         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
7516                         blocked_vcpu_list) {
7517                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7518
7519                 if (pi_test_on(pi_desc) == 1)
7520                         kvm_vcpu_kick(vcpu);
7521         }
7522         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7523 }
7524
7525 static void vmx_enable_tdp(void)
7526 {
7527         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
7528                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
7529                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
7530                 0ull, VMX_EPT_EXECUTABLE_MASK,
7531                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
7532                 VMX_EPT_RWX_MASK, 0ull);
7533
7534         ept_set_mmio_spte_mask();
7535         kvm_enable_tdp();
7536 }
7537
7538 static __init int hardware_setup(void)
7539 {
7540         int r = -ENOMEM, i;
7541
7542         rdmsrl_safe(MSR_EFER, &host_efer);
7543
7544         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7545                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7546
7547         for (i = 0; i < VMX_BITMAP_NR; i++) {
7548                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
7549                 if (!vmx_bitmap[i])
7550                         goto out;
7551         }
7552
7553         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
7554         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
7555
7556         if (setup_vmcs_config(&vmcs_config) < 0) {
7557                 r = -EIO;
7558                 goto out;
7559         }
7560
7561         if (boot_cpu_has(X86_FEATURE_NX))
7562                 kvm_enable_efer_bits(EFER_NX);
7563
7564         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7565                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7566                 enable_vpid = 0;
7567
7568         if (!cpu_has_vmx_ept() ||
7569             !cpu_has_vmx_ept_4levels() ||
7570             !cpu_has_vmx_ept_mt_wb() ||
7571             !cpu_has_vmx_invept_global())
7572                 enable_ept = 0;
7573
7574         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7575                 enable_ept_ad_bits = 0;
7576
7577         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7578                 enable_unrestricted_guest = 0;
7579
7580         if (!cpu_has_vmx_flexpriority())
7581                 flexpriority_enabled = 0;
7582
7583         if (!cpu_has_virtual_nmis())
7584                 enable_vnmi = 0;
7585
7586         /*
7587          * set_apic_access_page_addr() is used to reload apic access
7588          * page upon invalidation.  No need to do anything if not
7589          * using the APIC_ACCESS_ADDR VMCS field.
7590          */
7591         if (!flexpriority_enabled)
7592                 kvm_x86_ops->set_apic_access_page_addr = NULL;
7593
7594         if (!cpu_has_vmx_tpr_shadow())
7595                 kvm_x86_ops->update_cr8_intercept = NULL;
7596
7597         if (enable_ept && !cpu_has_vmx_ept_2m_page())
7598                 kvm_disable_largepages();
7599
7600         if (!cpu_has_vmx_ple()) {
7601                 ple_gap = 0;
7602                 ple_window = 0;
7603                 ple_window_grow = 0;
7604                 ple_window_max = 0;
7605                 ple_window_shrink = 0;
7606         }
7607
7608         if (!cpu_has_vmx_apicv()) {
7609                 enable_apicv = 0;
7610                 kvm_x86_ops->sync_pir_to_irr = NULL;
7611         }
7612
7613         if (cpu_has_vmx_tsc_scaling()) {
7614                 kvm_has_tsc_control = true;
7615                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7616                 kvm_tsc_scaling_ratio_frac_bits = 48;
7617         }
7618
7619         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7620
7621         if (enable_ept)
7622                 vmx_enable_tdp();
7623         else
7624                 kvm_disable_tdp();
7625
7626         /*
7627          * Only enable PML when hardware supports PML feature, and both EPT
7628          * and EPT A/D bit features are enabled -- PML depends on them to work.
7629          */
7630         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7631                 enable_pml = 0;
7632
7633         if (!enable_pml) {
7634                 kvm_x86_ops->slot_enable_log_dirty = NULL;
7635                 kvm_x86_ops->slot_disable_log_dirty = NULL;
7636                 kvm_x86_ops->flush_log_dirty = NULL;
7637                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7638         }
7639
7640         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7641                 u64 vmx_msr;
7642
7643                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7644                 cpu_preemption_timer_multi =
7645                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7646         } else {
7647                 kvm_x86_ops->set_hv_timer = NULL;
7648                 kvm_x86_ops->cancel_hv_timer = NULL;
7649         }
7650
7651         if (!cpu_has_vmx_shadow_vmcs())
7652                 enable_shadow_vmcs = 0;
7653         if (enable_shadow_vmcs)
7654                 init_vmcs_shadow_fields();
7655
7656         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7657         nested_vmx_setup_ctls_msrs(&vmcs_config.nested, enable_apicv);
7658
7659         kvm_mce_cap_supported |= MCG_LMCE_P;
7660
7661         return alloc_kvm_area();
7662
7663 out:
7664         for (i = 0; i < VMX_BITMAP_NR; i++)
7665                 free_page((unsigned long)vmx_bitmap[i]);
7666
7667     return r;
7668 }
7669
7670 static __exit void hardware_unsetup(void)
7671 {
7672         int i;
7673
7674         for (i = 0; i < VMX_BITMAP_NR; i++)
7675                 free_page((unsigned long)vmx_bitmap[i]);
7676
7677         free_kvm_area();
7678 }
7679
7680 /*
7681  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
7682  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
7683  */
7684 static int handle_pause(struct kvm_vcpu *vcpu)
7685 {
7686         if (!kvm_pause_in_guest(vcpu->kvm))
7687                 grow_ple_window(vcpu);
7688
7689         /*
7690          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
7691          * VM-execution control is ignored if CPL > 0. OTOH, KVM
7692          * never set PAUSE_EXITING and just set PLE if supported,
7693          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
7694          */
7695         kvm_vcpu_on_spin(vcpu, true);
7696         return kvm_skip_emulated_instruction(vcpu);
7697 }
7698
7699 static int handle_nop(struct kvm_vcpu *vcpu)
7700 {
7701         return kvm_skip_emulated_instruction(vcpu);
7702 }
7703
7704 static int handle_mwait(struct kvm_vcpu *vcpu)
7705 {
7706         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
7707         return handle_nop(vcpu);
7708 }
7709
7710 static int handle_invalid_op(struct kvm_vcpu *vcpu)
7711 {
7712         kvm_queue_exception(vcpu, UD_VECTOR);
7713         return 1;
7714 }
7715
7716 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
7717 {
7718         return 1;
7719 }
7720
7721 static int handle_monitor(struct kvm_vcpu *vcpu)
7722 {
7723         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
7724         return handle_nop(vcpu);
7725 }
7726
7727 /*
7728  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7729  * set the success or error code of an emulated VMX instruction, as specified
7730  * by Vol 2B, VMX Instruction Reference, "Conventions".
7731  */
7732 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
7733 {
7734         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
7735                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7736                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
7737 }
7738
7739 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
7740 {
7741         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7742                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
7743                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7744                         | X86_EFLAGS_CF);
7745 }
7746
7747 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
7748                                         u32 vm_instruction_error)
7749 {
7750         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
7751                 /*
7752                  * failValid writes the error number to the current VMCS, which
7753                  * can't be done there isn't a current VMCS.
7754                  */
7755                 nested_vmx_failInvalid(vcpu);
7756                 return;
7757         }
7758         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7759                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7760                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7761                         | X86_EFLAGS_ZF);
7762         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
7763         /*
7764          * We don't need to force a shadow sync because
7765          * VM_INSTRUCTION_ERROR is not shadowed
7766          */
7767 }
7768
7769 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
7770 {
7771         /* TODO: not to reset guest simply here. */
7772         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7773         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
7774 }
7775
7776 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
7777 {
7778         struct vcpu_vmx *vmx =
7779                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
7780
7781         vmx->nested.preemption_timer_expired = true;
7782         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
7783         kvm_vcpu_kick(&vmx->vcpu);
7784
7785         return HRTIMER_NORESTART;
7786 }
7787
7788 /*
7789  * Decode the memory-address operand of a vmx instruction, as recorded on an
7790  * exit caused by such an instruction (run by a guest hypervisor).
7791  * On success, returns 0. When the operand is invalid, returns 1 and throws
7792  * #UD or #GP.
7793  */
7794 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
7795                                  unsigned long exit_qualification,
7796                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
7797 {
7798         gva_t off;
7799         bool exn;
7800         struct kvm_segment s;
7801
7802         /*
7803          * According to Vol. 3B, "Information for VM Exits Due to Instruction
7804          * Execution", on an exit, vmx_instruction_info holds most of the
7805          * addressing components of the operand. Only the displacement part
7806          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7807          * For how an actual address is calculated from all these components,
7808          * refer to Vol. 1, "Operand Addressing".
7809          */
7810         int  scaling = vmx_instruction_info & 3;
7811         int  addr_size = (vmx_instruction_info >> 7) & 7;
7812         bool is_reg = vmx_instruction_info & (1u << 10);
7813         int  seg_reg = (vmx_instruction_info >> 15) & 7;
7814         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
7815         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
7816         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
7817         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
7818
7819         if (is_reg) {
7820                 kvm_queue_exception(vcpu, UD_VECTOR);
7821                 return 1;
7822         }
7823
7824         /* Addr = segment_base + offset */
7825         /* offset = base + [index * scale] + displacement */
7826         off = exit_qualification; /* holds the displacement */
7827         if (base_is_valid)
7828                 off += kvm_register_read(vcpu, base_reg);
7829         if (index_is_valid)
7830                 off += kvm_register_read(vcpu, index_reg)<<scaling;
7831         vmx_get_segment(vcpu, &s, seg_reg);
7832         *ret = s.base + off;
7833
7834         if (addr_size == 1) /* 32 bit */
7835                 *ret &= 0xffffffff;
7836
7837         /* Checks for #GP/#SS exceptions. */
7838         exn = false;
7839         if (is_long_mode(vcpu)) {
7840                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7841                  * non-canonical form. This is the only check on the memory
7842                  * destination for long mode!
7843                  */
7844                 exn = is_noncanonical_address(*ret, vcpu);
7845         } else if (is_protmode(vcpu)) {
7846                 /* Protected mode: apply checks for segment validity in the
7847                  * following order:
7848                  * - segment type check (#GP(0) may be thrown)
7849                  * - usability check (#GP(0)/#SS(0))
7850                  * - limit check (#GP(0)/#SS(0))
7851                  */
7852                 if (wr)
7853                         /* #GP(0) if the destination operand is located in a
7854                          * read-only data segment or any code segment.
7855                          */
7856                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
7857                 else
7858                         /* #GP(0) if the source operand is located in an
7859                          * execute-only code segment
7860                          */
7861                         exn = ((s.type & 0xa) == 8);
7862                 if (exn) {
7863                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7864                         return 1;
7865                 }
7866                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7867                  */
7868                 exn = (s.unusable != 0);
7869                 /* Protected mode: #GP(0)/#SS(0) if the memory
7870                  * operand is outside the segment limit.
7871                  */
7872                 exn = exn || (off + sizeof(u64) > s.limit);
7873         }
7874         if (exn) {
7875                 kvm_queue_exception_e(vcpu,
7876                                       seg_reg == VCPU_SREG_SS ?
7877                                                 SS_VECTOR : GP_VECTOR,
7878                                       0);
7879                 return 1;
7880         }
7881
7882         return 0;
7883 }
7884
7885 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7886 {
7887         gva_t gva;
7888         struct x86_exception e;
7889
7890         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7891                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7892                 return 1;
7893
7894         if (kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e)) {
7895                 kvm_inject_page_fault(vcpu, &e);
7896                 return 1;
7897         }
7898
7899         return 0;
7900 }
7901
7902 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7903 {
7904         struct vcpu_vmx *vmx = to_vmx(vcpu);
7905         struct vmcs *shadow_vmcs;
7906         int r;
7907
7908         r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
7909         if (r < 0)
7910                 goto out_vmcs02;
7911
7912         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7913         if (!vmx->nested.cached_vmcs12)
7914                 goto out_cached_vmcs12;
7915
7916         if (enable_shadow_vmcs) {
7917                 shadow_vmcs = alloc_vmcs();
7918                 if (!shadow_vmcs)
7919                         goto out_shadow_vmcs;
7920                 /* mark vmcs as shadow */
7921                 shadow_vmcs->revision_id |= (1u << 31);
7922                 /* init shadow vmcs */
7923                 vmcs_clear(shadow_vmcs);
7924                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7925         }
7926
7927         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7928                      HRTIMER_MODE_REL_PINNED);
7929         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7930
7931         vmx->nested.vmxon = true;
7932         return 0;
7933
7934 out_shadow_vmcs:
7935         kfree(vmx->nested.cached_vmcs12);
7936
7937 out_cached_vmcs12:
7938         free_loaded_vmcs(&vmx->nested.vmcs02);
7939
7940 out_vmcs02:
7941         return -ENOMEM;
7942 }
7943
7944 /*
7945  * Emulate the VMXON instruction.
7946  * Currently, we just remember that VMX is active, and do not save or even
7947  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7948  * do not currently need to store anything in that guest-allocated memory
7949  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7950  * argument is different from the VMXON pointer (which the spec says they do).
7951  */
7952 static int handle_vmon(struct kvm_vcpu *vcpu)
7953 {
7954         int ret;
7955         gpa_t vmptr;
7956         struct page *page;
7957         struct vcpu_vmx *vmx = to_vmx(vcpu);
7958         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7959                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7960
7961         /*
7962          * The Intel VMX Instruction Reference lists a bunch of bits that are
7963          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7964          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7965          * Otherwise, we should fail with #UD.  But most faulting conditions
7966          * have already been checked by hardware, prior to the VM-exit for
7967          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
7968          * that bit set to 1 in non-root mode.
7969          */
7970         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7971                 kvm_queue_exception(vcpu, UD_VECTOR);
7972                 return 1;
7973         }
7974
7975         /* CPL=0 must be checked manually. */
7976         if (vmx_get_cpl(vcpu)) {
7977                 kvm_queue_exception(vcpu, UD_VECTOR);
7978                 return 1;
7979         }
7980
7981         if (vmx->nested.vmxon) {
7982                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7983                 return kvm_skip_emulated_instruction(vcpu);
7984         }
7985
7986         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7987                         != VMXON_NEEDED_FEATURES) {
7988                 kvm_inject_gp(vcpu, 0);
7989                 return 1;
7990         }
7991
7992         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7993                 return 1;
7994
7995         /*
7996          * SDM 3: 24.11.5
7997          * The first 4 bytes of VMXON region contain the supported
7998          * VMCS revision identifier
7999          *
8000          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
8001          * which replaces physical address width with 32
8002          */
8003         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8004                 nested_vmx_failInvalid(vcpu);
8005                 return kvm_skip_emulated_instruction(vcpu);
8006         }
8007
8008         page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8009         if (is_error_page(page)) {
8010                 nested_vmx_failInvalid(vcpu);
8011                 return kvm_skip_emulated_instruction(vcpu);
8012         }
8013         if (*(u32 *)kmap(page) != VMCS12_REVISION) {
8014                 kunmap(page);
8015                 kvm_release_page_clean(page);
8016                 nested_vmx_failInvalid(vcpu);
8017                 return kvm_skip_emulated_instruction(vcpu);
8018         }
8019         kunmap(page);
8020         kvm_release_page_clean(page);
8021
8022         vmx->nested.vmxon_ptr = vmptr;
8023         ret = enter_vmx_operation(vcpu);
8024         if (ret)
8025                 return ret;
8026
8027         nested_vmx_succeed(vcpu);
8028         return kvm_skip_emulated_instruction(vcpu);
8029 }
8030
8031 /*
8032  * Intel's VMX Instruction Reference specifies a common set of prerequisites
8033  * for running VMX instructions (except VMXON, whose prerequisites are
8034  * slightly different). It also specifies what exception to inject otherwise.
8035  * Note that many of these exceptions have priority over VM exits, so they
8036  * don't have to be checked again here.
8037  */
8038 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
8039 {
8040         if (vmx_get_cpl(vcpu)) {
8041                 kvm_queue_exception(vcpu, UD_VECTOR);
8042                 return 0;
8043         }
8044
8045         if (!to_vmx(vcpu)->nested.vmxon) {
8046                 kvm_queue_exception(vcpu, UD_VECTOR);
8047                 return 0;
8048         }
8049         return 1;
8050 }
8051
8052 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
8053 {
8054         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
8055         vmcs_write64(VMCS_LINK_POINTER, -1ull);
8056 }
8057
8058 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
8059 {
8060         if (vmx->nested.current_vmptr == -1ull)
8061                 return;
8062
8063         if (enable_shadow_vmcs) {
8064                 /* copy to memory all shadowed fields in case
8065                    they were modified */
8066                 copy_shadow_to_vmcs12(vmx);
8067                 vmx->nested.sync_shadow_vmcs = false;
8068                 vmx_disable_shadow_vmcs(vmx);
8069         }
8070         vmx->nested.posted_intr_nv = -1;
8071
8072         /* Flush VMCS12 to guest memory */
8073         kvm_vcpu_write_guest_page(&vmx->vcpu,
8074                                   vmx->nested.current_vmptr >> PAGE_SHIFT,
8075                                   vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
8076
8077         vmx->nested.current_vmptr = -1ull;
8078 }
8079
8080 /*
8081  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
8082  * just stops using VMX.
8083  */
8084 static void free_nested(struct vcpu_vmx *vmx)
8085 {
8086         if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
8087                 return;
8088
8089         vmx->nested.vmxon = false;
8090         vmx->nested.smm.vmxon = false;
8091         free_vpid(vmx->nested.vpid02);
8092         vmx->nested.posted_intr_nv = -1;
8093         vmx->nested.current_vmptr = -1ull;
8094         if (enable_shadow_vmcs) {
8095                 vmx_disable_shadow_vmcs(vmx);
8096                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
8097                 free_vmcs(vmx->vmcs01.shadow_vmcs);
8098                 vmx->vmcs01.shadow_vmcs = NULL;
8099         }
8100         kfree(vmx->nested.cached_vmcs12);
8101         /* Unpin physical memory we referred to in the vmcs02 */
8102         if (vmx->nested.apic_access_page) {
8103                 kvm_release_page_dirty(vmx->nested.apic_access_page);
8104                 vmx->nested.apic_access_page = NULL;
8105         }
8106         if (vmx->nested.virtual_apic_page) {
8107                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
8108                 vmx->nested.virtual_apic_page = NULL;
8109         }
8110         if (vmx->nested.pi_desc_page) {
8111                 kunmap(vmx->nested.pi_desc_page);
8112                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
8113                 vmx->nested.pi_desc_page = NULL;
8114                 vmx->nested.pi_desc = NULL;
8115         }
8116
8117         free_loaded_vmcs(&vmx->nested.vmcs02);
8118 }
8119
8120 /* Emulate the VMXOFF instruction */
8121 static int handle_vmoff(struct kvm_vcpu *vcpu)
8122 {
8123         if (!nested_vmx_check_permission(vcpu))
8124                 return 1;
8125         free_nested(to_vmx(vcpu));
8126         nested_vmx_succeed(vcpu);
8127         return kvm_skip_emulated_instruction(vcpu);
8128 }
8129
8130 /* Emulate the VMCLEAR instruction */
8131 static int handle_vmclear(struct kvm_vcpu *vcpu)
8132 {
8133         struct vcpu_vmx *vmx = to_vmx(vcpu);
8134         u32 zero = 0;
8135         gpa_t vmptr;
8136
8137         if (!nested_vmx_check_permission(vcpu))
8138                 return 1;
8139
8140         if (nested_vmx_get_vmptr(vcpu, &vmptr))
8141                 return 1;
8142
8143         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8144                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
8145                 return kvm_skip_emulated_instruction(vcpu);
8146         }
8147
8148         if (vmptr == vmx->nested.vmxon_ptr) {
8149                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
8150                 return kvm_skip_emulated_instruction(vcpu);
8151         }
8152
8153         if (vmptr == vmx->nested.current_vmptr)
8154                 nested_release_vmcs12(vmx);
8155
8156         kvm_vcpu_write_guest(vcpu,
8157                         vmptr + offsetof(struct vmcs12, launch_state),
8158                         &zero, sizeof(zero));
8159
8160         nested_vmx_succeed(vcpu);
8161         return kvm_skip_emulated_instruction(vcpu);
8162 }
8163
8164 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
8165
8166 /* Emulate the VMLAUNCH instruction */
8167 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
8168 {
8169         return nested_vmx_run(vcpu, true);
8170 }
8171
8172 /* Emulate the VMRESUME instruction */
8173 static int handle_vmresume(struct kvm_vcpu *vcpu)
8174 {
8175
8176         return nested_vmx_run(vcpu, false);
8177 }
8178
8179 /*
8180  * Read a vmcs12 field. Since these can have varying lengths and we return
8181  * one type, we chose the biggest type (u64) and zero-extend the return value
8182  * to that size. Note that the caller, handle_vmread, might need to use only
8183  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
8184  * 64-bit fields are to be returned).
8185  */
8186 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
8187                                   unsigned long field, u64 *ret)
8188 {
8189         short offset = vmcs_field_to_offset(field);
8190         char *p;
8191
8192         if (offset < 0)
8193                 return offset;
8194
8195         p = ((char *)(get_vmcs12(vcpu))) + offset;
8196
8197         switch (vmcs_field_width(field)) {
8198         case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8199                 *ret = *((natural_width *)p);
8200                 return 0;
8201         case VMCS_FIELD_WIDTH_U16:
8202                 *ret = *((u16 *)p);
8203                 return 0;
8204         case VMCS_FIELD_WIDTH_U32:
8205                 *ret = *((u32 *)p);
8206                 return 0;
8207         case VMCS_FIELD_WIDTH_U64:
8208                 *ret = *((u64 *)p);
8209                 return 0;
8210         default:
8211                 WARN_ON(1);
8212                 return -ENOENT;
8213         }
8214 }
8215
8216
8217 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
8218                                    unsigned long field, u64 field_value){
8219         short offset = vmcs_field_to_offset(field);
8220         char *p = ((char *) get_vmcs12(vcpu)) + offset;
8221         if (offset < 0)
8222                 return offset;
8223
8224         switch (vmcs_field_width(field)) {
8225         case VMCS_FIELD_WIDTH_U16:
8226                 *(u16 *)p = field_value;
8227                 return 0;
8228         case VMCS_FIELD_WIDTH_U32:
8229                 *(u32 *)p = field_value;
8230                 return 0;
8231         case VMCS_FIELD_WIDTH_U64:
8232                 *(u64 *)p = field_value;
8233                 return 0;
8234         case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8235                 *(natural_width *)p = field_value;
8236                 return 0;
8237         default:
8238                 WARN_ON(1);
8239                 return -ENOENT;
8240         }
8241
8242 }
8243
8244 /*
8245  * Copy the writable VMCS shadow fields back to the VMCS12, in case
8246  * they have been modified by the L1 guest. Note that the "read-only"
8247  * VM-exit information fields are actually writable if the vCPU is
8248  * configured to support "VMWRITE to any supported field in the VMCS."
8249  */
8250 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
8251 {
8252         const u16 *fields[] = {
8253                 shadow_read_write_fields,
8254                 shadow_read_only_fields
8255         };
8256         const int max_fields[] = {
8257                 max_shadow_read_write_fields,
8258                 max_shadow_read_only_fields
8259         };
8260         int i, q;
8261         unsigned long field;
8262         u64 field_value;
8263         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8264
8265         preempt_disable();
8266
8267         vmcs_load(shadow_vmcs);
8268
8269         for (q = 0; q < ARRAY_SIZE(fields); q++) {
8270                 for (i = 0; i < max_fields[q]; i++) {
8271                         field = fields[q][i];
8272                         field_value = __vmcs_readl(field);
8273                         vmcs12_write_any(&vmx->vcpu, field, field_value);
8274                 }
8275                 /*
8276                  * Skip the VM-exit information fields if they are read-only.
8277                  */
8278                 if (!nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
8279                         break;
8280         }
8281
8282         vmcs_clear(shadow_vmcs);
8283         vmcs_load(vmx->loaded_vmcs->vmcs);
8284
8285         preempt_enable();
8286 }
8287
8288 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
8289 {
8290         const u16 *fields[] = {
8291                 shadow_read_write_fields,
8292                 shadow_read_only_fields
8293         };
8294         const int max_fields[] = {
8295                 max_shadow_read_write_fields,
8296                 max_shadow_read_only_fields
8297         };
8298         int i, q;
8299         unsigned long field;
8300         u64 field_value = 0;
8301         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8302
8303         vmcs_load(shadow_vmcs);
8304
8305         for (q = 0; q < ARRAY_SIZE(fields); q++) {
8306                 for (i = 0; i < max_fields[q]; i++) {
8307                         field = fields[q][i];
8308                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
8309                         __vmcs_writel(field, field_value);
8310                 }
8311         }
8312
8313         vmcs_clear(shadow_vmcs);
8314         vmcs_load(vmx->loaded_vmcs->vmcs);
8315 }
8316
8317 /*
8318  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
8319  * used before) all generate the same failure when it is missing.
8320  */
8321 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
8322 {
8323         struct vcpu_vmx *vmx = to_vmx(vcpu);
8324         if (vmx->nested.current_vmptr == -1ull) {
8325                 nested_vmx_failInvalid(vcpu);
8326                 return 0;
8327         }
8328         return 1;
8329 }
8330
8331 static int handle_vmread(struct kvm_vcpu *vcpu)
8332 {
8333         unsigned long field;
8334         u64 field_value;
8335         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8336         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8337         gva_t gva = 0;
8338
8339         if (!nested_vmx_check_permission(vcpu))
8340                 return 1;
8341
8342         if (!nested_vmx_check_vmcs12(vcpu))
8343                 return kvm_skip_emulated_instruction(vcpu);
8344
8345         /* Decode instruction info and find the field to read */
8346         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8347         /* Read the field, zero-extended to a u64 field_value */
8348         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
8349                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8350                 return kvm_skip_emulated_instruction(vcpu);
8351         }
8352         /*
8353          * Now copy part of this value to register or memory, as requested.
8354          * Note that the number of bits actually copied is 32 or 64 depending
8355          * on the guest's mode (32 or 64 bit), not on the given field's length.
8356          */
8357         if (vmx_instruction_info & (1u << 10)) {
8358                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
8359                         field_value);
8360         } else {
8361                 if (get_vmx_mem_address(vcpu, exit_qualification,
8362                                 vmx_instruction_info, true, &gva))
8363                         return 1;
8364                 /* _system ok, nested_vmx_check_permission has verified cpl=0 */
8365                 kvm_write_guest_virt_system(vcpu, gva, &field_value,
8366                                             (is_long_mode(vcpu) ? 8 : 4), NULL);
8367         }
8368
8369         nested_vmx_succeed(vcpu);
8370         return kvm_skip_emulated_instruction(vcpu);
8371 }
8372
8373
8374 static int handle_vmwrite(struct kvm_vcpu *vcpu)
8375 {
8376         unsigned long field;
8377         gva_t gva;
8378         struct vcpu_vmx *vmx = to_vmx(vcpu);
8379         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8380         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8381
8382         /* The value to write might be 32 or 64 bits, depending on L1's long
8383          * mode, and eventually we need to write that into a field of several
8384          * possible lengths. The code below first zero-extends the value to 64
8385          * bit (field_value), and then copies only the appropriate number of
8386          * bits into the vmcs12 field.
8387          */
8388         u64 field_value = 0;
8389         struct x86_exception e;
8390
8391         if (!nested_vmx_check_permission(vcpu))
8392                 return 1;
8393
8394         if (!nested_vmx_check_vmcs12(vcpu))
8395                 return kvm_skip_emulated_instruction(vcpu);
8396
8397         if (vmx_instruction_info & (1u << 10))
8398                 field_value = kvm_register_readl(vcpu,
8399                         (((vmx_instruction_info) >> 3) & 0xf));
8400         else {
8401                 if (get_vmx_mem_address(vcpu, exit_qualification,
8402                                 vmx_instruction_info, false, &gva))
8403                         return 1;
8404                 if (kvm_read_guest_virt(vcpu, gva, &field_value,
8405                                         (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
8406                         kvm_inject_page_fault(vcpu, &e);
8407                         return 1;
8408                 }
8409         }
8410
8411
8412         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8413         /*
8414          * If the vCPU supports "VMWRITE to any supported field in the
8415          * VMCS," then the "read-only" fields are actually read/write.
8416          */
8417         if (vmcs_field_readonly(field) &&
8418             !nested_cpu_has_vmwrite_any_field(vcpu)) {
8419                 nested_vmx_failValid(vcpu,
8420                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
8421                 return kvm_skip_emulated_instruction(vcpu);
8422         }
8423
8424         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
8425                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8426                 return kvm_skip_emulated_instruction(vcpu);
8427         }
8428
8429         switch (field) {
8430 #define SHADOW_FIELD_RW(x) case x:
8431 #include "vmx_shadow_fields.h"
8432                 /*
8433                  * The fields that can be updated by L1 without a vmexit are
8434                  * always updated in the vmcs02, the others go down the slow
8435                  * path of prepare_vmcs02.
8436                  */
8437                 break;
8438         default:
8439                 vmx->nested.dirty_vmcs12 = true;
8440                 break;
8441         }
8442
8443         nested_vmx_succeed(vcpu);
8444         return kvm_skip_emulated_instruction(vcpu);
8445 }
8446
8447 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
8448 {
8449         vmx->nested.current_vmptr = vmptr;
8450         if (enable_shadow_vmcs) {
8451                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
8452                               SECONDARY_EXEC_SHADOW_VMCS);
8453                 vmcs_write64(VMCS_LINK_POINTER,
8454                              __pa(vmx->vmcs01.shadow_vmcs));
8455                 vmx->nested.sync_shadow_vmcs = true;
8456         }
8457         vmx->nested.dirty_vmcs12 = true;
8458 }
8459
8460 /* Emulate the VMPTRLD instruction */
8461 static int handle_vmptrld(struct kvm_vcpu *vcpu)
8462 {
8463         struct vcpu_vmx *vmx = to_vmx(vcpu);
8464         gpa_t vmptr;
8465
8466         if (!nested_vmx_check_permission(vcpu))
8467                 return 1;
8468
8469         if (nested_vmx_get_vmptr(vcpu, &vmptr))
8470                 return 1;
8471
8472         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8473                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
8474                 return kvm_skip_emulated_instruction(vcpu);
8475         }
8476
8477         if (vmptr == vmx->nested.vmxon_ptr) {
8478                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
8479                 return kvm_skip_emulated_instruction(vcpu);
8480         }
8481
8482         if (vmx->nested.current_vmptr != vmptr) {
8483                 struct vmcs12 *new_vmcs12;
8484                 struct page *page;
8485                 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8486                 if (is_error_page(page)) {
8487                         nested_vmx_failInvalid(vcpu);
8488                         return kvm_skip_emulated_instruction(vcpu);
8489                 }
8490                 new_vmcs12 = kmap(page);
8491                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
8492                         kunmap(page);
8493                         kvm_release_page_clean(page);
8494                         nested_vmx_failValid(vcpu,
8495                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
8496                         return kvm_skip_emulated_instruction(vcpu);
8497                 }
8498
8499                 nested_release_vmcs12(vmx);
8500                 /*
8501                  * Load VMCS12 from guest memory since it is not already
8502                  * cached.
8503                  */
8504                 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
8505                 kunmap(page);
8506                 kvm_release_page_clean(page);
8507
8508                 set_current_vmptr(vmx, vmptr);
8509         }
8510
8511         nested_vmx_succeed(vcpu);
8512         return kvm_skip_emulated_instruction(vcpu);
8513 }
8514
8515 /* Emulate the VMPTRST instruction */
8516 static int handle_vmptrst(struct kvm_vcpu *vcpu)
8517 {
8518         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8519         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8520         gva_t vmcs_gva;
8521         struct x86_exception e;
8522
8523         if (!nested_vmx_check_permission(vcpu))
8524                 return 1;
8525
8526         if (get_vmx_mem_address(vcpu, exit_qualification,
8527                         vmx_instruction_info, true, &vmcs_gva))
8528                 return 1;
8529         /* *_system ok, nested_vmx_check_permission has verified cpl=0 */
8530         if (kvm_write_guest_virt_system(vcpu, vmcs_gva,
8531                                         (void *)&to_vmx(vcpu)->nested.current_vmptr,
8532                                         sizeof(u64), &e)) {
8533                 kvm_inject_page_fault(vcpu, &e);
8534                 return 1;
8535         }
8536         nested_vmx_succeed(vcpu);
8537         return kvm_skip_emulated_instruction(vcpu);
8538 }
8539
8540 /* Emulate the INVEPT instruction */
8541 static int handle_invept(struct kvm_vcpu *vcpu)
8542 {
8543         struct vcpu_vmx *vmx = to_vmx(vcpu);
8544         u32 vmx_instruction_info, types;
8545         unsigned long type;
8546         gva_t gva;
8547         struct x86_exception e;
8548         struct {
8549                 u64 eptp, gpa;
8550         } operand;
8551
8552         if (!(vmx->nested.msrs.secondary_ctls_high &
8553               SECONDARY_EXEC_ENABLE_EPT) ||
8554             !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) {
8555                 kvm_queue_exception(vcpu, UD_VECTOR);
8556                 return 1;
8557         }
8558
8559         if (!nested_vmx_check_permission(vcpu))
8560                 return 1;
8561
8562         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8563         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8564
8565         types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
8566
8567         if (type >= 32 || !(types & (1 << type))) {
8568                 nested_vmx_failValid(vcpu,
8569                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8570                 return kvm_skip_emulated_instruction(vcpu);
8571         }
8572
8573         /* According to the Intel VMX instruction reference, the memory
8574          * operand is read even if it isn't needed (e.g., for type==global)
8575          */
8576         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8577                         vmx_instruction_info, false, &gva))
8578                 return 1;
8579         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
8580                 kvm_inject_page_fault(vcpu, &e);
8581                 return 1;
8582         }
8583
8584         switch (type) {
8585         case VMX_EPT_EXTENT_GLOBAL:
8586         /*
8587          * TODO: track mappings and invalidate
8588          * single context requests appropriately
8589          */
8590         case VMX_EPT_EXTENT_CONTEXT:
8591                 kvm_mmu_sync_roots(vcpu);
8592                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
8593                 nested_vmx_succeed(vcpu);
8594                 break;
8595         default:
8596                 BUG_ON(1);
8597                 break;
8598         }
8599
8600         return kvm_skip_emulated_instruction(vcpu);
8601 }
8602
8603 static int handle_invvpid(struct kvm_vcpu *vcpu)
8604 {
8605         struct vcpu_vmx *vmx = to_vmx(vcpu);
8606         u32 vmx_instruction_info;
8607         unsigned long type, types;
8608         gva_t gva;
8609         struct x86_exception e;
8610         struct {
8611                 u64 vpid;
8612                 u64 gla;
8613         } operand;
8614
8615         if (!(vmx->nested.msrs.secondary_ctls_high &
8616               SECONDARY_EXEC_ENABLE_VPID) ||
8617                         !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) {
8618                 kvm_queue_exception(vcpu, UD_VECTOR);
8619                 return 1;
8620         }
8621
8622         if (!nested_vmx_check_permission(vcpu))
8623                 return 1;
8624
8625         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8626         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8627
8628         types = (vmx->nested.msrs.vpid_caps &
8629                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
8630
8631         if (type >= 32 || !(types & (1 << type))) {
8632                 nested_vmx_failValid(vcpu,
8633                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8634                 return kvm_skip_emulated_instruction(vcpu);
8635         }
8636
8637         /* according to the intel vmx instruction reference, the memory
8638          * operand is read even if it isn't needed (e.g., for type==global)
8639          */
8640         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8641                         vmx_instruction_info, false, &gva))
8642                 return 1;
8643         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
8644                 kvm_inject_page_fault(vcpu, &e);
8645                 return 1;
8646         }
8647         if (operand.vpid >> 16) {
8648                 nested_vmx_failValid(vcpu,
8649                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8650                 return kvm_skip_emulated_instruction(vcpu);
8651         }
8652
8653         switch (type) {
8654         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
8655                 if (!operand.vpid ||
8656                     is_noncanonical_address(operand.gla, vcpu)) {
8657                         nested_vmx_failValid(vcpu,
8658                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8659                         return kvm_skip_emulated_instruction(vcpu);
8660                 }
8661                 if (cpu_has_vmx_invvpid_individual_addr() &&
8662                     vmx->nested.vpid02) {
8663                         __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR,
8664                                 vmx->nested.vpid02, operand.gla);
8665                 } else
8666                         __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8667                 break;
8668         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
8669         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
8670                 if (!operand.vpid) {
8671                         nested_vmx_failValid(vcpu,
8672                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8673                         return kvm_skip_emulated_instruction(vcpu);
8674                 }
8675                 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8676                 break;
8677         case VMX_VPID_EXTENT_ALL_CONTEXT:
8678                 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8679                 break;
8680         default:
8681                 WARN_ON_ONCE(1);
8682                 return kvm_skip_emulated_instruction(vcpu);
8683         }
8684
8685         nested_vmx_succeed(vcpu);
8686
8687         return kvm_skip_emulated_instruction(vcpu);
8688 }
8689
8690 static int handle_pml_full(struct kvm_vcpu *vcpu)
8691 {
8692         unsigned long exit_qualification;
8693
8694         trace_kvm_pml_full(vcpu->vcpu_id);
8695
8696         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8697
8698         /*
8699          * PML buffer FULL happened while executing iret from NMI,
8700          * "blocked by NMI" bit has to be set before next VM entry.
8701          */
8702         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
8703                         enable_vnmi &&
8704                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
8705                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8706                                 GUEST_INTR_STATE_NMI);
8707
8708         /*
8709          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
8710          * here.., and there's no userspace involvement needed for PML.
8711          */
8712         return 1;
8713 }
8714
8715 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8716 {
8717         kvm_lapic_expired_hv_timer(vcpu);
8718         return 1;
8719 }
8720
8721 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
8722 {
8723         struct vcpu_vmx *vmx = to_vmx(vcpu);
8724         int maxphyaddr = cpuid_maxphyaddr(vcpu);
8725
8726         /* Check for memory type validity */
8727         switch (address & VMX_EPTP_MT_MASK) {
8728         case VMX_EPTP_MT_UC:
8729                 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT))
8730                         return false;
8731                 break;
8732         case VMX_EPTP_MT_WB:
8733                 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT))
8734                         return false;
8735                 break;
8736         default:
8737                 return false;
8738         }
8739
8740         /* only 4 levels page-walk length are valid */
8741         if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
8742                 return false;
8743
8744         /* Reserved bits should not be set */
8745         if (address >> maxphyaddr || ((address >> 7) & 0x1f))
8746                 return false;
8747
8748         /* AD, if set, should be supported */
8749         if (address & VMX_EPTP_AD_ENABLE_BIT) {
8750                 if (!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT))
8751                         return false;
8752         }
8753
8754         return true;
8755 }
8756
8757 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
8758                                      struct vmcs12 *vmcs12)
8759 {
8760         u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
8761         u64 address;
8762         bool accessed_dirty;
8763         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
8764
8765         if (!nested_cpu_has_eptp_switching(vmcs12) ||
8766             !nested_cpu_has_ept(vmcs12))
8767                 return 1;
8768
8769         if (index >= VMFUNC_EPTP_ENTRIES)
8770                 return 1;
8771
8772
8773         if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
8774                                      &address, index * 8, 8))
8775                 return 1;
8776
8777         accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
8778
8779         /*
8780          * If the (L2) guest does a vmfunc to the currently
8781          * active ept pointer, we don't have to do anything else
8782          */
8783         if (vmcs12->ept_pointer != address) {
8784                 if (!valid_ept_address(vcpu, address))
8785                         return 1;
8786
8787                 kvm_mmu_unload(vcpu);
8788                 mmu->ept_ad = accessed_dirty;
8789                 mmu->base_role.ad_disabled = !accessed_dirty;
8790                 vmcs12->ept_pointer = address;
8791                 /*
8792                  * TODO: Check what's the correct approach in case
8793                  * mmu reload fails. Currently, we just let the next
8794                  * reload potentially fail
8795                  */
8796                 kvm_mmu_reload(vcpu);
8797         }
8798
8799         return 0;
8800 }
8801
8802 static int handle_vmfunc(struct kvm_vcpu *vcpu)
8803 {
8804         struct vcpu_vmx *vmx = to_vmx(vcpu);
8805         struct vmcs12 *vmcs12;
8806         u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
8807
8808         /*
8809          * VMFUNC is only supported for nested guests, but we always enable the
8810          * secondary control for simplicity; for non-nested mode, fake that we
8811          * didn't by injecting #UD.
8812          */
8813         if (!is_guest_mode(vcpu)) {
8814                 kvm_queue_exception(vcpu, UD_VECTOR);
8815                 return 1;
8816         }
8817
8818         vmcs12 = get_vmcs12(vcpu);
8819         if ((vmcs12->vm_function_control & (1 << function)) == 0)
8820                 goto fail;
8821
8822         switch (function) {
8823         case 0:
8824                 if (nested_vmx_eptp_switching(vcpu, vmcs12))
8825                         goto fail;
8826                 break;
8827         default:
8828                 goto fail;
8829         }
8830         return kvm_skip_emulated_instruction(vcpu);
8831
8832 fail:
8833         nested_vmx_vmexit(vcpu, vmx->exit_reason,
8834                           vmcs_read32(VM_EXIT_INTR_INFO),
8835                           vmcs_readl(EXIT_QUALIFICATION));
8836         return 1;
8837 }
8838
8839 /*
8840  * The exit handlers return 1 if the exit was handled fully and guest execution
8841  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
8842  * to be done to userspace and return 0.
8843  */
8844 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
8845         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
8846         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
8847         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
8848         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
8849         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
8850         [EXIT_REASON_CR_ACCESS]               = handle_cr,
8851         [EXIT_REASON_DR_ACCESS]               = handle_dr,
8852         [EXIT_REASON_CPUID]                   = handle_cpuid,
8853         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
8854         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
8855         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
8856         [EXIT_REASON_HLT]                     = handle_halt,
8857         [EXIT_REASON_INVD]                    = handle_invd,
8858         [EXIT_REASON_INVLPG]                  = handle_invlpg,
8859         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
8860         [EXIT_REASON_VMCALL]                  = handle_vmcall,
8861         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
8862         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
8863         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
8864         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
8865         [EXIT_REASON_VMREAD]                  = handle_vmread,
8866         [EXIT_REASON_VMRESUME]                = handle_vmresume,
8867         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
8868         [EXIT_REASON_VMOFF]                   = handle_vmoff,
8869         [EXIT_REASON_VMON]                    = handle_vmon,
8870         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
8871         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
8872         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
8873         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
8874         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
8875         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
8876         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
8877         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
8878         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
8879         [EXIT_REASON_LDTR_TR]                 = handle_desc,
8880         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
8881         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
8882         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
8883         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
8884         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
8885         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
8886         [EXIT_REASON_INVEPT]                  = handle_invept,
8887         [EXIT_REASON_INVVPID]                 = handle_invvpid,
8888         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
8889         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
8890         [EXIT_REASON_XSAVES]                  = handle_xsaves,
8891         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
8892         [EXIT_REASON_PML_FULL]                = handle_pml_full,
8893         [EXIT_REASON_VMFUNC]                  = handle_vmfunc,
8894         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
8895 };
8896
8897 static const int kvm_vmx_max_exit_handlers =
8898         ARRAY_SIZE(kvm_vmx_exit_handlers);
8899
8900 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
8901                                        struct vmcs12 *vmcs12)
8902 {
8903         unsigned long exit_qualification;
8904         gpa_t bitmap, last_bitmap;
8905         unsigned int port;
8906         int size;
8907         u8 b;
8908
8909         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
8910                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
8911
8912         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8913
8914         port = exit_qualification >> 16;
8915         size = (exit_qualification & 7) + 1;
8916
8917         last_bitmap = (gpa_t)-1;
8918         b = -1;
8919
8920         while (size > 0) {
8921                 if (port < 0x8000)
8922                         bitmap = vmcs12->io_bitmap_a;
8923                 else if (port < 0x10000)
8924                         bitmap = vmcs12->io_bitmap_b;
8925                 else
8926                         return true;
8927                 bitmap += (port & 0x7fff) / 8;
8928
8929                 if (last_bitmap != bitmap)
8930                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8931                                 return true;
8932                 if (b & (1 << (port & 7)))
8933                         return true;
8934
8935                 port++;
8936                 size--;
8937                 last_bitmap = bitmap;
8938         }
8939
8940         return false;
8941 }
8942
8943 /*
8944  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8945  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8946  * disinterest in the current event (read or write a specific MSR) by using an
8947  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8948  */
8949 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8950         struct vmcs12 *vmcs12, u32 exit_reason)
8951 {
8952         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8953         gpa_t bitmap;
8954
8955         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8956                 return true;
8957
8958         /*
8959          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8960          * for the four combinations of read/write and low/high MSR numbers.
8961          * First we need to figure out which of the four to use:
8962          */
8963         bitmap = vmcs12->msr_bitmap;
8964         if (exit_reason == EXIT_REASON_MSR_WRITE)
8965                 bitmap += 2048;
8966         if (msr_index >= 0xc0000000) {
8967                 msr_index -= 0xc0000000;
8968                 bitmap += 1024;
8969         }
8970
8971         /* Then read the msr_index'th bit from this bitmap: */
8972         if (msr_index < 1024*8) {
8973                 unsigned char b;
8974                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8975                         return true;
8976                 return 1 & (b >> (msr_index & 7));
8977         } else
8978                 return true; /* let L1 handle the wrong parameter */
8979 }
8980
8981 /*
8982  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8983  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8984  * intercept (via guest_host_mask etc.) the current event.
8985  */
8986 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8987         struct vmcs12 *vmcs12)
8988 {
8989         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8990         int cr = exit_qualification & 15;
8991         int reg;
8992         unsigned long val;
8993
8994         switch ((exit_qualification >> 4) & 3) {
8995         case 0: /* mov to cr */
8996                 reg = (exit_qualification >> 8) & 15;
8997                 val = kvm_register_readl(vcpu, reg);
8998                 switch (cr) {
8999                 case 0:
9000                         if (vmcs12->cr0_guest_host_mask &
9001                             (val ^ vmcs12->cr0_read_shadow))
9002                                 return true;
9003                         break;
9004                 case 3:
9005                         if ((vmcs12->cr3_target_count >= 1 &&
9006                                         vmcs12->cr3_target_value0 == val) ||
9007                                 (vmcs12->cr3_target_count >= 2 &&
9008                                         vmcs12->cr3_target_value1 == val) ||
9009                                 (vmcs12->cr3_target_count >= 3 &&
9010                                         vmcs12->cr3_target_value2 == val) ||
9011                                 (vmcs12->cr3_target_count >= 4 &&
9012                                         vmcs12->cr3_target_value3 == val))
9013                                 return false;
9014                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
9015                                 return true;
9016                         break;
9017                 case 4:
9018                         if (vmcs12->cr4_guest_host_mask &
9019                             (vmcs12->cr4_read_shadow ^ val))
9020                                 return true;
9021                         break;
9022                 case 8:
9023                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
9024                                 return true;
9025                         break;
9026                 }
9027                 break;
9028         case 2: /* clts */
9029                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
9030                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
9031                         return true;
9032                 break;
9033         case 1: /* mov from cr */
9034                 switch (cr) {
9035                 case 3:
9036                         if (vmcs12->cpu_based_vm_exec_control &
9037                             CPU_BASED_CR3_STORE_EXITING)
9038                                 return true;
9039                         break;
9040                 case 8:
9041                         if (vmcs12->cpu_based_vm_exec_control &
9042                             CPU_BASED_CR8_STORE_EXITING)
9043                                 return true;
9044                         break;
9045                 }
9046                 break;
9047         case 3: /* lmsw */
9048                 /*
9049                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
9050                  * cr0. Other attempted changes are ignored, with no exit.
9051                  */
9052                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
9053                 if (vmcs12->cr0_guest_host_mask & 0xe &
9054                     (val ^ vmcs12->cr0_read_shadow))
9055                         return true;
9056                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
9057                     !(vmcs12->cr0_read_shadow & 0x1) &&
9058                     (val & 0x1))
9059                         return true;
9060                 break;
9061         }
9062         return false;
9063 }
9064
9065 /*
9066  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
9067  * should handle it ourselves in L0 (and then continue L2). Only call this
9068  * when in is_guest_mode (L2).
9069  */
9070 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
9071 {
9072         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9073         struct vcpu_vmx *vmx = to_vmx(vcpu);
9074         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9075
9076         if (vmx->nested.nested_run_pending)
9077                 return false;
9078
9079         if (unlikely(vmx->fail)) {
9080                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
9081                                     vmcs_read32(VM_INSTRUCTION_ERROR));
9082                 return true;
9083         }
9084
9085         /*
9086          * The host physical addresses of some pages of guest memory
9087          * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
9088          * Page). The CPU may write to these pages via their host
9089          * physical address while L2 is running, bypassing any
9090          * address-translation-based dirty tracking (e.g. EPT write
9091          * protection).
9092          *
9093          * Mark them dirty on every exit from L2 to prevent them from
9094          * getting out of sync with dirty tracking.
9095          */
9096         nested_mark_vmcs12_pages_dirty(vcpu);
9097
9098         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
9099                                 vmcs_readl(EXIT_QUALIFICATION),
9100                                 vmx->idt_vectoring_info,
9101                                 intr_info,
9102                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9103                                 KVM_ISA_VMX);
9104
9105         switch (exit_reason) {
9106         case EXIT_REASON_EXCEPTION_NMI:
9107                 if (is_nmi(intr_info))
9108                         return false;
9109                 else if (is_page_fault(intr_info))
9110                         return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
9111                 else if (is_no_device(intr_info) &&
9112                          !(vmcs12->guest_cr0 & X86_CR0_TS))
9113                         return false;
9114                 else if (is_debug(intr_info) &&
9115                          vcpu->guest_debug &
9116                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
9117                         return false;
9118                 else if (is_breakpoint(intr_info) &&
9119                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
9120                         return false;
9121                 return vmcs12->exception_bitmap &
9122                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
9123         case EXIT_REASON_EXTERNAL_INTERRUPT:
9124                 return false;
9125         case EXIT_REASON_TRIPLE_FAULT:
9126                 return true;
9127         case EXIT_REASON_PENDING_INTERRUPT:
9128                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
9129         case EXIT_REASON_NMI_WINDOW:
9130                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
9131         case EXIT_REASON_TASK_SWITCH:
9132                 return true;
9133         case EXIT_REASON_CPUID:
9134                 return true;
9135         case EXIT_REASON_HLT:
9136                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
9137         case EXIT_REASON_INVD:
9138                 return true;
9139         case EXIT_REASON_INVLPG:
9140                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9141         case EXIT_REASON_RDPMC:
9142                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
9143         case EXIT_REASON_RDRAND:
9144                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
9145         case EXIT_REASON_RDSEED:
9146                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
9147         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
9148                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
9149         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
9150         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
9151         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
9152         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
9153         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
9154         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
9155                 /*
9156                  * VMX instructions trap unconditionally. This allows L1 to
9157                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
9158                  */
9159                 return true;
9160         case EXIT_REASON_CR_ACCESS:
9161                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
9162         case EXIT_REASON_DR_ACCESS:
9163                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
9164         case EXIT_REASON_IO_INSTRUCTION:
9165                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
9166         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
9167                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
9168         case EXIT_REASON_MSR_READ:
9169         case EXIT_REASON_MSR_WRITE:
9170                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
9171         case EXIT_REASON_INVALID_STATE:
9172                 return true;
9173         case EXIT_REASON_MWAIT_INSTRUCTION:
9174                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
9175         case EXIT_REASON_MONITOR_TRAP_FLAG:
9176                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
9177         case EXIT_REASON_MONITOR_INSTRUCTION:
9178                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
9179         case EXIT_REASON_PAUSE_INSTRUCTION:
9180                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
9181                         nested_cpu_has2(vmcs12,
9182                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
9183         case EXIT_REASON_MCE_DURING_VMENTRY:
9184                 return false;
9185         case EXIT_REASON_TPR_BELOW_THRESHOLD:
9186                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
9187         case EXIT_REASON_APIC_ACCESS:
9188         case EXIT_REASON_APIC_WRITE:
9189         case EXIT_REASON_EOI_INDUCED:
9190                 /*
9191                  * The controls for "virtualize APIC accesses," "APIC-
9192                  * register virtualization," and "virtual-interrupt
9193                  * delivery" only come from vmcs12.
9194                  */
9195                 return true;
9196         case EXIT_REASON_EPT_VIOLATION:
9197                 /*
9198                  * L0 always deals with the EPT violation. If nested EPT is
9199                  * used, and the nested mmu code discovers that the address is
9200                  * missing in the guest EPT table (EPT12), the EPT violation
9201                  * will be injected with nested_ept_inject_page_fault()
9202                  */
9203                 return false;
9204         case EXIT_REASON_EPT_MISCONFIG:
9205                 /*
9206                  * L2 never uses directly L1's EPT, but rather L0's own EPT
9207                  * table (shadow on EPT) or a merged EPT table that L0 built
9208                  * (EPT on EPT). So any problems with the structure of the
9209                  * table is L0's fault.
9210                  */
9211                 return false;
9212         case EXIT_REASON_INVPCID:
9213                 return
9214                         nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
9215                         nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9216         case EXIT_REASON_WBINVD:
9217                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
9218         case EXIT_REASON_XSETBV:
9219                 return true;
9220         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
9221                 /*
9222                  * This should never happen, since it is not possible to
9223                  * set XSS to a non-zero value---neither in L1 nor in L2.
9224                  * If if it were, XSS would have to be checked against
9225                  * the XSS exit bitmap in vmcs12.
9226                  */
9227                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
9228         case EXIT_REASON_PREEMPTION_TIMER:
9229                 return false;
9230         case EXIT_REASON_PML_FULL:
9231                 /* We emulate PML support to L1. */
9232                 return false;
9233         case EXIT_REASON_VMFUNC:
9234                 /* VM functions are emulated through L2->L0 vmexits. */
9235                 return false;
9236         default:
9237                 return true;
9238         }
9239 }
9240
9241 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
9242 {
9243         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9244
9245         /*
9246          * At this point, the exit interruption info in exit_intr_info
9247          * is only valid for EXCEPTION_NMI exits.  For EXTERNAL_INTERRUPT
9248          * we need to query the in-kernel LAPIC.
9249          */
9250         WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
9251         if ((exit_intr_info &
9252              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9253             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
9254                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9255                 vmcs12->vm_exit_intr_error_code =
9256                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9257         }
9258
9259         nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
9260                           vmcs_readl(EXIT_QUALIFICATION));
9261         return 1;
9262 }
9263
9264 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
9265 {
9266         *info1 = vmcs_readl(EXIT_QUALIFICATION);
9267         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
9268 }
9269
9270 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
9271 {
9272         if (vmx->pml_pg) {
9273                 __free_page(vmx->pml_pg);
9274                 vmx->pml_pg = NULL;
9275         }
9276 }
9277
9278 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
9279 {
9280         struct vcpu_vmx *vmx = to_vmx(vcpu);
9281         u64 *pml_buf;
9282         u16 pml_idx;
9283
9284         pml_idx = vmcs_read16(GUEST_PML_INDEX);
9285
9286         /* Do nothing if PML buffer is empty */
9287         if (pml_idx == (PML_ENTITY_NUM - 1))
9288                 return;
9289
9290         /* PML index always points to next available PML buffer entity */
9291         if (pml_idx >= PML_ENTITY_NUM)
9292                 pml_idx = 0;
9293         else
9294                 pml_idx++;
9295
9296         pml_buf = page_address(vmx->pml_pg);
9297         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
9298                 u64 gpa;
9299
9300                 gpa = pml_buf[pml_idx];
9301                 WARN_ON(gpa & (PAGE_SIZE - 1));
9302                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
9303         }
9304
9305         /* reset PML index */
9306         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
9307 }
9308
9309 /*
9310  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
9311  * Called before reporting dirty_bitmap to userspace.
9312  */
9313 static void kvm_flush_pml_buffers(struct kvm *kvm)
9314 {
9315         int i;
9316         struct kvm_vcpu *vcpu;
9317         /*
9318          * We only need to kick vcpu out of guest mode here, as PML buffer
9319          * is flushed at beginning of all VMEXITs, and it's obvious that only
9320          * vcpus running in guest are possible to have unflushed GPAs in PML
9321          * buffer.
9322          */
9323         kvm_for_each_vcpu(i, vcpu, kvm)
9324                 kvm_vcpu_kick(vcpu);
9325 }
9326
9327 static void vmx_dump_sel(char *name, uint32_t sel)
9328 {
9329         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
9330                name, vmcs_read16(sel),
9331                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
9332                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
9333                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
9334 }
9335
9336 static void vmx_dump_dtsel(char *name, uint32_t limit)
9337 {
9338         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
9339                name, vmcs_read32(limit),
9340                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
9341 }
9342
9343 static void dump_vmcs(void)
9344 {
9345         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
9346         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
9347         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
9348         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
9349         u32 secondary_exec_control = 0;
9350         unsigned long cr4 = vmcs_readl(GUEST_CR4);
9351         u64 efer = vmcs_read64(GUEST_IA32_EFER);
9352         int i, n;
9353
9354         if (cpu_has_secondary_exec_ctrls())
9355                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9356
9357         pr_err("*** Guest State ***\n");
9358         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9359                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
9360                vmcs_readl(CR0_GUEST_HOST_MASK));
9361         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9362                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
9363         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
9364         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
9365             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
9366         {
9367                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
9368                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
9369                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
9370                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
9371         }
9372         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
9373                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
9374         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
9375                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
9376         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9377                vmcs_readl(GUEST_SYSENTER_ESP),
9378                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
9379         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
9380         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
9381         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
9382         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
9383         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
9384         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
9385         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
9386         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
9387         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
9388         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
9389         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
9390             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
9391                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
9392                        efer, vmcs_read64(GUEST_IA32_PAT));
9393         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
9394                vmcs_read64(GUEST_IA32_DEBUGCTL),
9395                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
9396         if (cpu_has_load_perf_global_ctrl &&
9397             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
9398                 pr_err("PerfGlobCtl = 0x%016llx\n",
9399                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
9400         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
9401                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
9402         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
9403                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
9404                vmcs_read32(GUEST_ACTIVITY_STATE));
9405         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
9406                 pr_err("InterruptStatus = %04x\n",
9407                        vmcs_read16(GUEST_INTR_STATUS));
9408
9409         pr_err("*** Host State ***\n");
9410         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
9411                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
9412         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
9413                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
9414                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
9415                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
9416                vmcs_read16(HOST_TR_SELECTOR));
9417         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
9418                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
9419                vmcs_readl(HOST_TR_BASE));
9420         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
9421                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
9422         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
9423                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
9424                vmcs_readl(HOST_CR4));
9425         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9426                vmcs_readl(HOST_IA32_SYSENTER_ESP),
9427                vmcs_read32(HOST_IA32_SYSENTER_CS),
9428                vmcs_readl(HOST_IA32_SYSENTER_EIP));
9429         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
9430                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
9431                        vmcs_read64(HOST_IA32_EFER),
9432                        vmcs_read64(HOST_IA32_PAT));
9433         if (cpu_has_load_perf_global_ctrl &&
9434             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9435                 pr_err("PerfGlobCtl = 0x%016llx\n",
9436                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
9437
9438         pr_err("*** Control State ***\n");
9439         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
9440                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
9441         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
9442         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
9443                vmcs_read32(EXCEPTION_BITMAP),
9444                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
9445                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
9446         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
9447                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9448                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
9449                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
9450         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
9451                vmcs_read32(VM_EXIT_INTR_INFO),
9452                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9453                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
9454         pr_err("        reason=%08x qualification=%016lx\n",
9455                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
9456         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
9457                vmcs_read32(IDT_VECTORING_INFO_FIELD),
9458                vmcs_read32(IDT_VECTORING_ERROR_CODE));
9459         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
9460         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
9461                 pr_err("TSC Multiplier = 0x%016llx\n",
9462                        vmcs_read64(TSC_MULTIPLIER));
9463         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
9464                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
9465         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
9466                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
9467         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
9468                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
9469         n = vmcs_read32(CR3_TARGET_COUNT);
9470         for (i = 0; i + 1 < n; i += 4)
9471                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
9472                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
9473                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
9474         if (i < n)
9475                 pr_err("CR3 target%u=%016lx\n",
9476                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
9477         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
9478                 pr_err("PLE Gap=%08x Window=%08x\n",
9479                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
9480         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
9481                 pr_err("Virtual processor ID = 0x%04x\n",
9482                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
9483 }
9484
9485 /*
9486  * The guest has exited.  See if we can fix it or if we need userspace
9487  * assistance.
9488  */
9489 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
9490 {
9491         struct vcpu_vmx *vmx = to_vmx(vcpu);
9492         u32 exit_reason = vmx->exit_reason;
9493         u32 vectoring_info = vmx->idt_vectoring_info;
9494
9495         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
9496
9497         /*
9498          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
9499          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
9500          * querying dirty_bitmap, we only need to kick all vcpus out of guest
9501          * mode as if vcpus is in root mode, the PML buffer must has been
9502          * flushed already.
9503          */
9504         if (enable_pml)
9505                 vmx_flush_pml_buffer(vcpu);
9506
9507         /* If guest state is invalid, start emulating */
9508         if (vmx->emulation_required)
9509                 return handle_invalid_guest_state(vcpu);
9510
9511         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
9512                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
9513
9514         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
9515                 dump_vmcs();
9516                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
9517                 vcpu->run->fail_entry.hardware_entry_failure_reason
9518                         = exit_reason;
9519                 return 0;
9520         }
9521
9522         if (unlikely(vmx->fail)) {
9523                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
9524                 vcpu->run->fail_entry.hardware_entry_failure_reason
9525                         = vmcs_read32(VM_INSTRUCTION_ERROR);
9526                 return 0;
9527         }
9528
9529         /*
9530          * Note:
9531          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
9532          * delivery event since it indicates guest is accessing MMIO.
9533          * The vm-exit can be triggered again after return to guest that
9534          * will cause infinite loop.
9535          */
9536         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
9537                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
9538                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
9539                         exit_reason != EXIT_REASON_PML_FULL &&
9540                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
9541                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9542                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
9543                 vcpu->run->internal.ndata = 3;
9544                 vcpu->run->internal.data[0] = vectoring_info;
9545                 vcpu->run->internal.data[1] = exit_reason;
9546                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
9547                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
9548                         vcpu->run->internal.ndata++;
9549                         vcpu->run->internal.data[3] =
9550                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
9551                 }
9552                 return 0;
9553         }
9554
9555         if (unlikely(!enable_vnmi &&
9556                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
9557                 if (vmx_interrupt_allowed(vcpu)) {
9558                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
9559                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
9560                            vcpu->arch.nmi_pending) {
9561                         /*
9562                          * This CPU don't support us in finding the end of an
9563                          * NMI-blocked window if the guest runs with IRQs
9564                          * disabled. So we pull the trigger after 1 s of
9565                          * futile waiting, but inform the user about this.
9566                          */
9567                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
9568                                "state on VCPU %d after 1 s timeout\n",
9569                                __func__, vcpu->vcpu_id);
9570                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
9571                 }
9572         }
9573
9574         if (exit_reason < kvm_vmx_max_exit_handlers
9575             && kvm_vmx_exit_handlers[exit_reason])
9576                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
9577         else {
9578                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
9579                                 exit_reason);
9580                 kvm_queue_exception(vcpu, UD_VECTOR);
9581                 return 1;
9582         }
9583 }
9584
9585 /*
9586  * Software based L1D cache flush which is used when microcode providing
9587  * the cache control MSR is not loaded.
9588  *
9589  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
9590  * flush it is required to read in 64 KiB because the replacement algorithm
9591  * is not exactly LRU. This could be sized at runtime via topology
9592  * information but as all relevant affected CPUs have 32KiB L1D cache size
9593  * there is no point in doing so.
9594  */
9595 #define L1D_CACHE_ORDER 4
9596 static void *vmx_l1d_flush_pages;
9597
9598 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
9599 {
9600         int size = PAGE_SIZE << L1D_CACHE_ORDER;
9601         bool always;
9602
9603         /*
9604          * If the mitigation mode is 'flush always', keep the flush bit
9605          * set, otherwise clear it. It gets set again either from
9606          * vcpu_run() or from one of the unsafe VMEXIT handlers.
9607          */
9608         always = vmentry_l1d_flush == VMENTER_L1D_FLUSH_ALWAYS;
9609         vcpu->arch.l1tf_flush_l1d = always;
9610
9611         vcpu->stat.l1d_flush++;
9612
9613         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
9614                 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
9615                 return;
9616         }
9617
9618         asm volatile(
9619                 /* First ensure the pages are in the TLB */
9620                 "xorl   %%eax, %%eax\n"
9621                 ".Lpopulate_tlb:\n\t"
9622                 "movzbl (%[empty_zp], %%" _ASM_AX "), %%ecx\n\t"
9623                 "addl   $4096, %%eax\n\t"
9624                 "cmpl   %%eax, %[size]\n\t"
9625                 "jne    .Lpopulate_tlb\n\t"
9626                 "xorl   %%eax, %%eax\n\t"
9627                 "cpuid\n\t"
9628                 /* Now fill the cache */
9629                 "xorl   %%eax, %%eax\n"
9630                 ".Lfill_cache:\n"
9631                 "movzbl (%[empty_zp], %%" _ASM_AX "), %%ecx\n\t"
9632                 "addl   $64, %%eax\n\t"
9633                 "cmpl   %%eax, %[size]\n\t"
9634                 "jne    .Lfill_cache\n\t"
9635                 "lfence\n"
9636                 :: [empty_zp] "r" (vmx_l1d_flush_pages),
9637                     [size] "r" (size)
9638                 : "eax", "ebx", "ecx", "edx");
9639 }
9640
9641 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
9642 {
9643         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9644
9645         if (is_guest_mode(vcpu) &&
9646                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9647                 return;
9648
9649         if (irr == -1 || tpr < irr) {
9650                 vmcs_write32(TPR_THRESHOLD, 0);
9651                 return;
9652         }
9653
9654         vmcs_write32(TPR_THRESHOLD, irr);
9655 }
9656
9657 static void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
9658 {
9659         u32 sec_exec_control;
9660
9661         if (!lapic_in_kernel(vcpu))
9662                 return;
9663
9664         /* Postpone execution until vmcs01 is the current VMCS. */
9665         if (is_guest_mode(vcpu)) {
9666                 to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
9667                 return;
9668         }
9669
9670         if (!cpu_need_tpr_shadow(vcpu))
9671                 return;
9672
9673         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9674         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9675                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
9676
9677         switch (kvm_get_apic_mode(vcpu)) {
9678         case LAPIC_MODE_INVALID:
9679                 WARN_ONCE(true, "Invalid local APIC state");
9680         case LAPIC_MODE_DISABLED:
9681                 break;
9682         case LAPIC_MODE_XAPIC:
9683                 if (flexpriority_enabled) {
9684                         sec_exec_control |=
9685                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9686                         vmx_flush_tlb(vcpu, true);
9687                 }
9688                 break;
9689         case LAPIC_MODE_X2APIC:
9690                 if (cpu_has_vmx_virtualize_x2apic_mode())
9691                         sec_exec_control |=
9692                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9693                 break;
9694         }
9695         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
9696
9697         vmx_update_msr_bitmap(vcpu);
9698 }
9699
9700 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
9701 {
9702         if (!is_guest_mode(vcpu)) {
9703                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9704                 vmx_flush_tlb(vcpu, true);
9705         }
9706 }
9707
9708 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
9709 {
9710         u16 status;
9711         u8 old;
9712
9713         if (max_isr == -1)
9714                 max_isr = 0;
9715
9716         status = vmcs_read16(GUEST_INTR_STATUS);
9717         old = status >> 8;
9718         if (max_isr != old) {
9719                 status &= 0xff;
9720                 status |= max_isr << 8;
9721                 vmcs_write16(GUEST_INTR_STATUS, status);
9722         }
9723 }
9724
9725 static void vmx_set_rvi(int vector)
9726 {
9727         u16 status;
9728         u8 old;
9729
9730         if (vector == -1)
9731                 vector = 0;
9732
9733         status = vmcs_read16(GUEST_INTR_STATUS);
9734         old = (u8)status & 0xff;
9735         if ((u8)vector != old) {
9736                 status &= ~0xff;
9737                 status |= (u8)vector;
9738                 vmcs_write16(GUEST_INTR_STATUS, status);
9739         }
9740 }
9741
9742 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
9743 {
9744         /*
9745          * When running L2, updating RVI is only relevant when
9746          * vmcs12 virtual-interrupt-delivery enabled.
9747          * However, it can be enabled only when L1 also
9748          * intercepts external-interrupts and in that case
9749          * we should not update vmcs02 RVI but instead intercept
9750          * interrupt. Therefore, do nothing when running L2.
9751          */
9752         if (!is_guest_mode(vcpu))
9753                 vmx_set_rvi(max_irr);
9754 }
9755
9756 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
9757 {
9758         struct vcpu_vmx *vmx = to_vmx(vcpu);
9759         int max_irr;
9760         bool max_irr_updated;
9761
9762         WARN_ON(!vcpu->arch.apicv_active);
9763         if (pi_test_on(&vmx->pi_desc)) {
9764                 pi_clear_on(&vmx->pi_desc);
9765                 /*
9766                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
9767                  * But on x86 this is just a compiler barrier anyway.
9768                  */
9769                 smp_mb__after_atomic();
9770                 max_irr_updated =
9771                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
9772
9773                 /*
9774                  * If we are running L2 and L1 has a new pending interrupt
9775                  * which can be injected, we should re-evaluate
9776                  * what should be done with this new L1 interrupt.
9777                  * If L1 intercepts external-interrupts, we should
9778                  * exit from L2 to L1. Otherwise, interrupt should be
9779                  * delivered directly to L2.
9780                  */
9781                 if (is_guest_mode(vcpu) && max_irr_updated) {
9782                         if (nested_exit_on_intr(vcpu))
9783                                 kvm_vcpu_exiting_guest_mode(vcpu);
9784                         else
9785                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9786                 }
9787         } else {
9788                 max_irr = kvm_lapic_find_highest_irr(vcpu);
9789         }
9790         vmx_hwapic_irr_update(vcpu, max_irr);
9791         return max_irr;
9792 }
9793
9794 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
9795 {
9796         if (!kvm_vcpu_apicv_active(vcpu))
9797                 return;
9798
9799         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
9800         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
9801         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
9802         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
9803 }
9804
9805 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
9806 {
9807         struct vcpu_vmx *vmx = to_vmx(vcpu);
9808
9809         pi_clear_on(&vmx->pi_desc);
9810         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
9811 }
9812
9813 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
9814 {
9815         u32 exit_intr_info = 0;
9816         u16 basic_exit_reason = (u16)vmx->exit_reason;
9817
9818         if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
9819               || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
9820                 return;
9821
9822         if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9823                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9824         vmx->exit_intr_info = exit_intr_info;
9825
9826         /* if exit due to PF check for async PF */
9827         if (is_page_fault(exit_intr_info))
9828                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
9829
9830         /* Handle machine checks before interrupts are enabled */
9831         if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
9832             is_machine_check(exit_intr_info))
9833                 kvm_machine_check();
9834
9835         /* We need to handle NMIs before interrupts are enabled */
9836         if (is_nmi(exit_intr_info)) {
9837                 kvm_before_interrupt(&vmx->vcpu);
9838                 asm("int $2");
9839                 kvm_after_interrupt(&vmx->vcpu);
9840         }
9841 }
9842
9843 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
9844 {
9845         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9846
9847         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
9848                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
9849                 unsigned int vector;
9850                 unsigned long entry;
9851                 gate_desc *desc;
9852                 struct vcpu_vmx *vmx = to_vmx(vcpu);
9853 #ifdef CONFIG_X86_64
9854                 unsigned long tmp;
9855 #endif
9856
9857                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
9858                 desc = (gate_desc *)vmx->host_idt_base + vector;
9859                 entry = gate_offset(desc);
9860                 asm volatile(
9861 #ifdef CONFIG_X86_64
9862                         "mov %%" _ASM_SP ", %[sp]\n\t"
9863                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
9864                         "push $%c[ss]\n\t"
9865                         "push %[sp]\n\t"
9866 #endif
9867                         "pushf\n\t"
9868                         __ASM_SIZE(push) " $%c[cs]\n\t"
9869                         CALL_NOSPEC
9870                         :
9871 #ifdef CONFIG_X86_64
9872                         [sp]"=&r"(tmp),
9873 #endif
9874                         ASM_CALL_CONSTRAINT
9875                         :
9876                         THUNK_TARGET(entry),
9877                         [ss]"i"(__KERNEL_DS),
9878                         [cs]"i"(__KERNEL_CS)
9879                         );
9880                 vcpu->arch.l1tf_flush_l1d = true;
9881         }
9882 }
9883 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
9884
9885 static bool vmx_has_emulated_msr(int index)
9886 {
9887         switch (index) {
9888         case MSR_IA32_SMBASE:
9889                 /*
9890                  * We cannot do SMM unless we can run the guest in big
9891                  * real mode.
9892                  */
9893                 return enable_unrestricted_guest || emulate_invalid_guest_state;
9894         case MSR_AMD64_VIRT_SPEC_CTRL:
9895                 /* This is AMD only.  */
9896                 return false;
9897         default:
9898                 return true;
9899         }
9900 }
9901
9902 static bool vmx_mpx_supported(void)
9903 {
9904         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
9905                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
9906 }
9907
9908 static bool vmx_xsaves_supported(void)
9909 {
9910         return vmcs_config.cpu_based_2nd_exec_ctrl &
9911                 SECONDARY_EXEC_XSAVES;
9912 }
9913
9914 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
9915 {
9916         u32 exit_intr_info;
9917         bool unblock_nmi;
9918         u8 vector;
9919         bool idtv_info_valid;
9920
9921         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9922
9923         if (enable_vnmi) {
9924                 if (vmx->loaded_vmcs->nmi_known_unmasked)
9925                         return;
9926                 /*
9927                  * Can't use vmx->exit_intr_info since we're not sure what
9928                  * the exit reason is.
9929                  */
9930                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9931                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
9932                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9933                 /*
9934                  * SDM 3: 27.7.1.2 (September 2008)
9935                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
9936                  * a guest IRET fault.
9937                  * SDM 3: 23.2.2 (September 2008)
9938                  * Bit 12 is undefined in any of the following cases:
9939                  *  If the VM exit sets the valid bit in the IDT-vectoring
9940                  *   information field.
9941                  *  If the VM exit is due to a double fault.
9942                  */
9943                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
9944                     vector != DF_VECTOR && !idtv_info_valid)
9945                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9946                                       GUEST_INTR_STATE_NMI);
9947                 else
9948                         vmx->loaded_vmcs->nmi_known_unmasked =
9949                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
9950                                   & GUEST_INTR_STATE_NMI);
9951         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
9952                 vmx->loaded_vmcs->vnmi_blocked_time +=
9953                         ktime_to_ns(ktime_sub(ktime_get(),
9954                                               vmx->loaded_vmcs->entry_time));
9955 }
9956
9957 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
9958                                       u32 idt_vectoring_info,
9959                                       int instr_len_field,
9960                                       int error_code_field)
9961 {
9962         u8 vector;
9963         int type;
9964         bool idtv_info_valid;
9965
9966         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9967
9968         vcpu->arch.nmi_injected = false;
9969         kvm_clear_exception_queue(vcpu);
9970         kvm_clear_interrupt_queue(vcpu);
9971
9972         if (!idtv_info_valid)
9973                 return;
9974
9975         kvm_make_request(KVM_REQ_EVENT, vcpu);
9976
9977         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
9978         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
9979
9980         switch (type) {
9981         case INTR_TYPE_NMI_INTR:
9982                 vcpu->arch.nmi_injected = true;
9983                 /*
9984                  * SDM 3: 27.7.1.2 (September 2008)
9985                  * Clear bit "block by NMI" before VM entry if a NMI
9986                  * delivery faulted.
9987                  */
9988                 vmx_set_nmi_mask(vcpu, false);
9989                 break;
9990         case INTR_TYPE_SOFT_EXCEPTION:
9991                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9992                 /* fall through */
9993         case INTR_TYPE_HARD_EXCEPTION:
9994                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
9995                         u32 err = vmcs_read32(error_code_field);
9996                         kvm_requeue_exception_e(vcpu, vector, err);
9997                 } else
9998                         kvm_requeue_exception(vcpu, vector);
9999                 break;
10000         case INTR_TYPE_SOFT_INTR:
10001                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
10002                 /* fall through */
10003         case INTR_TYPE_EXT_INTR:
10004                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
10005                 break;
10006         default:
10007                 break;
10008         }
10009 }
10010
10011 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
10012 {
10013         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
10014                                   VM_EXIT_INSTRUCTION_LEN,
10015                                   IDT_VECTORING_ERROR_CODE);
10016 }
10017
10018 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
10019 {
10020         __vmx_complete_interrupts(vcpu,
10021                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
10022                                   VM_ENTRY_INSTRUCTION_LEN,
10023                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
10024
10025         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10026 }
10027
10028 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
10029 {
10030         int i, nr_msrs;
10031         struct perf_guest_switch_msr *msrs;
10032
10033         msrs = perf_guest_get_msrs(&nr_msrs);
10034
10035         if (!msrs)
10036                 return;
10037
10038         for (i = 0; i < nr_msrs; i++)
10039                 if (msrs[i].host == msrs[i].guest)
10040                         clear_atomic_switch_msr(vmx, msrs[i].msr);
10041                 else
10042                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
10043                                         msrs[i].host);
10044 }
10045
10046 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
10047 {
10048         struct vcpu_vmx *vmx = to_vmx(vcpu);
10049         u64 tscl;
10050         u32 delta_tsc;
10051
10052         if (vmx->hv_deadline_tsc == -1)
10053                 return;
10054
10055         tscl = rdtsc();
10056         if (vmx->hv_deadline_tsc > tscl)
10057                 /* sure to be 32 bit only because checked on set_hv_timer */
10058                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
10059                         cpu_preemption_timer_multi);
10060         else
10061                 delta_tsc = 0;
10062
10063         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
10064 }
10065
10066 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
10067 {
10068         struct vcpu_vmx *vmx = to_vmx(vcpu);
10069         unsigned long cr3, cr4, evmcs_rsp;
10070
10071         /* Record the guest's net vcpu time for enforced NMI injections. */
10072         if (unlikely(!enable_vnmi &&
10073                      vmx->loaded_vmcs->soft_vnmi_blocked))
10074                 vmx->loaded_vmcs->entry_time = ktime_get();
10075
10076         /* Don't enter VMX if guest state is invalid, let the exit handler
10077            start emulation until we arrive back to a valid state */
10078         if (vmx->emulation_required)
10079                 return;
10080
10081         if (vmx->ple_window_dirty) {
10082                 vmx->ple_window_dirty = false;
10083                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
10084         }
10085
10086         if (vmx->nested.sync_shadow_vmcs) {
10087                 copy_vmcs12_to_shadow(vmx);
10088                 vmx->nested.sync_shadow_vmcs = false;
10089         }
10090
10091         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
10092                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
10093         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
10094                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
10095
10096         cr3 = __get_current_cr3_fast();
10097         if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) {
10098                 vmcs_writel(HOST_CR3, cr3);
10099                 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
10100         }
10101
10102         cr4 = cr4_read_shadow();
10103         if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) {
10104                 vmcs_writel(HOST_CR4, cr4);
10105                 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
10106         }
10107
10108         /* When single-stepping over STI and MOV SS, we must clear the
10109          * corresponding interruptibility bits in the guest state. Otherwise
10110          * vmentry fails as it then expects bit 14 (BS) in pending debug
10111          * exceptions being set, but that's not correct for the guest debugging
10112          * case. */
10113         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10114                 vmx_set_interrupt_shadow(vcpu, 0);
10115
10116         if (static_cpu_has(X86_FEATURE_PKU) &&
10117             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
10118             vcpu->arch.pkru != vmx->host_pkru)
10119                 __write_pkru(vcpu->arch.pkru);
10120
10121         atomic_switch_perf_msrs(vmx);
10122
10123         vmx_arm_hv_timer(vcpu);
10124
10125         /*
10126          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
10127          * it's non-zero. Since vmentry is serialising on affected CPUs, there
10128          * is no need to worry about the conditional branch over the wrmsr
10129          * being speculatively taken.
10130          */
10131         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
10132
10133         vmx->__launched = vmx->loaded_vmcs->launched;
10134
10135         evmcs_rsp = static_branch_unlikely(&enable_evmcs) ?
10136                 (unsigned long)&current_evmcs->host_rsp : 0;
10137
10138         if (static_branch_unlikely(&vmx_l1d_should_flush)) {
10139                 if (vcpu->arch.l1tf_flush_l1d)
10140                         vmx_l1d_flush(vcpu);
10141         }
10142
10143         asm(
10144                 /* Store host registers */
10145                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
10146                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
10147                 "push %%" _ASM_CX " \n\t"
10148                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10149                 "je 1f \n\t"
10150                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10151                 /* Avoid VMWRITE when Enlightened VMCS is in use */
10152                 "test %%" _ASM_SI ", %%" _ASM_SI " \n\t"
10153                 "jz 2f \n\t"
10154                 "mov %%" _ASM_SP ", (%%" _ASM_SI ") \n\t"
10155                 "jmp 1f \n\t"
10156                 "2: \n\t"
10157                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
10158                 "1: \n\t"
10159                 /* Reload cr2 if changed */
10160                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
10161                 "mov %%cr2, %%" _ASM_DX " \n\t"
10162                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
10163                 "je 3f \n\t"
10164                 "mov %%" _ASM_AX", %%cr2 \n\t"
10165                 "3: \n\t"
10166                 /* Check if vmlaunch of vmresume is needed */
10167                 "cmpl $0, %c[launched](%0) \n\t"
10168                 /* Load guest registers.  Don't clobber flags. */
10169                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
10170                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
10171                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
10172                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
10173                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
10174                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
10175 #ifdef CONFIG_X86_64
10176                 "mov %c[r8](%0),  %%r8  \n\t"
10177                 "mov %c[r9](%0),  %%r9  \n\t"
10178                 "mov %c[r10](%0), %%r10 \n\t"
10179                 "mov %c[r11](%0), %%r11 \n\t"
10180                 "mov %c[r12](%0), %%r12 \n\t"
10181                 "mov %c[r13](%0), %%r13 \n\t"
10182                 "mov %c[r14](%0), %%r14 \n\t"
10183                 "mov %c[r15](%0), %%r15 \n\t"
10184 #endif
10185                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
10186
10187                 /* Enter guest mode */
10188                 "jne 1f \n\t"
10189                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
10190                 "jmp 2f \n\t"
10191                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
10192                 "2: "
10193                 /* Save guest registers, load host registers, keep flags */
10194                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
10195                 "pop %0 \n\t"
10196                 "setbe %c[fail](%0)\n\t"
10197                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
10198                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
10199                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
10200                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
10201                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
10202                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
10203                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
10204 #ifdef CONFIG_X86_64
10205                 "mov %%r8,  %c[r8](%0) \n\t"
10206                 "mov %%r9,  %c[r9](%0) \n\t"
10207                 "mov %%r10, %c[r10](%0) \n\t"
10208                 "mov %%r11, %c[r11](%0) \n\t"
10209                 "mov %%r12, %c[r12](%0) \n\t"
10210                 "mov %%r13, %c[r13](%0) \n\t"
10211                 "mov %%r14, %c[r14](%0) \n\t"
10212                 "mov %%r15, %c[r15](%0) \n\t"
10213                 "xor %%r8d,  %%r8d \n\t"
10214                 "xor %%r9d,  %%r9d \n\t"
10215                 "xor %%r10d, %%r10d \n\t"
10216                 "xor %%r11d, %%r11d \n\t"
10217                 "xor %%r12d, %%r12d \n\t"
10218                 "xor %%r13d, %%r13d \n\t"
10219                 "xor %%r14d, %%r14d \n\t"
10220                 "xor %%r15d, %%r15d \n\t"
10221 #endif
10222                 "mov %%cr2, %%" _ASM_AX "   \n\t"
10223                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
10224
10225                 "xor %%eax, %%eax \n\t"
10226                 "xor %%ebx, %%ebx \n\t"
10227                 "xor %%esi, %%esi \n\t"
10228                 "xor %%edi, %%edi \n\t"
10229                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
10230                 ".pushsection .rodata \n\t"
10231                 ".global vmx_return \n\t"
10232                 "vmx_return: " _ASM_PTR " 2b \n\t"
10233                 ".popsection"
10234               : : "c"(vmx), "d"((unsigned long)HOST_RSP), "S"(evmcs_rsp),
10235                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
10236                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
10237                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
10238                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
10239                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
10240                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
10241                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
10242                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
10243                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
10244                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
10245 #ifdef CONFIG_X86_64
10246                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
10247                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
10248                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
10249                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
10250                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
10251                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
10252                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
10253                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
10254 #endif
10255                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
10256                 [wordsize]"i"(sizeof(ulong))
10257               : "cc", "memory"
10258 #ifdef CONFIG_X86_64
10259                 , "rax", "rbx", "rdi"
10260                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
10261 #else
10262                 , "eax", "ebx", "edi"
10263 #endif
10264               );
10265
10266         /*
10267          * We do not use IBRS in the kernel. If this vCPU has used the
10268          * SPEC_CTRL MSR it may have left it on; save the value and
10269          * turn it off. This is much more efficient than blindly adding
10270          * it to the atomic save/restore list. Especially as the former
10271          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
10272          *
10273          * For non-nested case:
10274          * If the L01 MSR bitmap does not intercept the MSR, then we need to
10275          * save it.
10276          *
10277          * For nested case:
10278          * If the L02 MSR bitmap does not intercept the MSR, then we need to
10279          * save it.
10280          */
10281         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
10282                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
10283
10284         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
10285
10286         /* Eliminate branch target predictions from guest mode */
10287         vmexit_fill_RSB();
10288
10289         /* All fields are clean at this point */
10290         if (static_branch_unlikely(&enable_evmcs))
10291                 current_evmcs->hv_clean_fields |=
10292                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
10293
10294         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
10295         if (vmx->host_debugctlmsr)
10296                 update_debugctlmsr(vmx->host_debugctlmsr);
10297
10298 #ifndef CONFIG_X86_64
10299         /*
10300          * The sysexit path does not restore ds/es, so we must set them to
10301          * a reasonable value ourselves.
10302          *
10303          * We can't defer this to vmx_load_host_state() since that function
10304          * may be executed in interrupt context, which saves and restore segments
10305          * around it, nullifying its effect.
10306          */
10307         loadsegment(ds, __USER_DS);
10308         loadsegment(es, __USER_DS);
10309 #endif
10310
10311         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
10312                                   | (1 << VCPU_EXREG_RFLAGS)
10313                                   | (1 << VCPU_EXREG_PDPTR)
10314                                   | (1 << VCPU_EXREG_SEGMENTS)
10315                                   | (1 << VCPU_EXREG_CR3));
10316         vcpu->arch.regs_dirty = 0;
10317
10318         /*
10319          * eager fpu is enabled if PKEY is supported and CR4 is switched
10320          * back on host, so it is safe to read guest PKRU from current
10321          * XSAVE.
10322          */
10323         if (static_cpu_has(X86_FEATURE_PKU) &&
10324             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
10325                 vcpu->arch.pkru = __read_pkru();
10326                 if (vcpu->arch.pkru != vmx->host_pkru)
10327                         __write_pkru(vmx->host_pkru);
10328         }
10329
10330         vmx->nested.nested_run_pending = 0;
10331         vmx->idt_vectoring_info = 0;
10332
10333         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
10334         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
10335                 return;
10336
10337         vmx->loaded_vmcs->launched = 1;
10338         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
10339
10340         vmx_complete_atomic_exit(vmx);
10341         vmx_recover_nmi_blocking(vmx);
10342         vmx_complete_interrupts(vmx);
10343 }
10344 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
10345
10346 static struct kvm *vmx_vm_alloc(void)
10347 {
10348         struct kvm_vmx *kvm_vmx = vzalloc(sizeof(struct kvm_vmx));
10349         return &kvm_vmx->kvm;
10350 }
10351
10352 static void vmx_vm_free(struct kvm *kvm)
10353 {
10354         vfree(to_kvm_vmx(kvm));
10355 }
10356
10357 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
10358 {
10359         struct vcpu_vmx *vmx = to_vmx(vcpu);
10360         int cpu;
10361
10362         if (vmx->loaded_vmcs == vmcs)
10363                 return;
10364
10365         cpu = get_cpu();
10366         vmx->loaded_vmcs = vmcs;
10367         vmx_vcpu_put(vcpu);
10368         vmx_vcpu_load(vcpu, cpu);
10369         put_cpu();
10370 }
10371
10372 /*
10373  * Ensure that the current vmcs of the logical processor is the
10374  * vmcs01 of the vcpu before calling free_nested().
10375  */
10376 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
10377 {
10378        struct vcpu_vmx *vmx = to_vmx(vcpu);
10379
10380        vcpu_load(vcpu);
10381        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10382        free_nested(vmx);
10383        vcpu_put(vcpu);
10384 }
10385
10386 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
10387 {
10388         struct vcpu_vmx *vmx = to_vmx(vcpu);
10389
10390         if (enable_pml)
10391                 vmx_destroy_pml_buffer(vmx);
10392         free_vpid(vmx->vpid);
10393         leave_guest_mode(vcpu);
10394         vmx_free_vcpu_nested(vcpu);
10395         free_loaded_vmcs(vmx->loaded_vmcs);
10396         kfree(vmx->guest_msrs);
10397         kvm_vcpu_uninit(vcpu);
10398         kmem_cache_free(kvm_vcpu_cache, vmx);
10399 }
10400
10401 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
10402 {
10403         int err;
10404         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
10405         unsigned long *msr_bitmap;
10406         int cpu;
10407
10408         if (!vmx)
10409                 return ERR_PTR(-ENOMEM);
10410
10411         vmx->vpid = allocate_vpid();
10412
10413         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
10414         if (err)
10415                 goto free_vcpu;
10416
10417         err = -ENOMEM;
10418
10419         /*
10420          * If PML is turned on, failure on enabling PML just results in failure
10421          * of creating the vcpu, therefore we can simplify PML logic (by
10422          * avoiding dealing with cases, such as enabling PML partially on vcpus
10423          * for the guest, etc.
10424          */
10425         if (enable_pml) {
10426                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
10427                 if (!vmx->pml_pg)
10428                         goto uninit_vcpu;
10429         }
10430
10431         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
10432         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
10433                      > PAGE_SIZE);
10434
10435         if (!vmx->guest_msrs)
10436                 goto free_pml;
10437
10438         err = alloc_loaded_vmcs(&vmx->vmcs01);
10439         if (err < 0)
10440                 goto free_msrs;
10441
10442         msr_bitmap = vmx->vmcs01.msr_bitmap;
10443         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
10444         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
10445         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
10446         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
10447         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
10448         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
10449         vmx->msr_bitmap_mode = 0;
10450
10451         vmx->loaded_vmcs = &vmx->vmcs01;
10452         cpu = get_cpu();
10453         vmx_vcpu_load(&vmx->vcpu, cpu);
10454         vmx->vcpu.cpu = cpu;
10455         vmx_vcpu_setup(vmx);
10456         vmx_vcpu_put(&vmx->vcpu);
10457         put_cpu();
10458         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
10459                 err = alloc_apic_access_page(kvm);
10460                 if (err)
10461                         goto free_vmcs;
10462         }
10463
10464         if (enable_ept && !enable_unrestricted_guest) {
10465                 err = init_rmode_identity_map(kvm);
10466                 if (err)
10467                         goto free_vmcs;
10468         }
10469
10470         if (nested) {
10471                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
10472                                            kvm_vcpu_apicv_active(&vmx->vcpu));
10473                 vmx->nested.vpid02 = allocate_vpid();
10474         }
10475
10476         vmx->nested.posted_intr_nv = -1;
10477         vmx->nested.current_vmptr = -1ull;
10478
10479         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
10480
10481         /*
10482          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
10483          * or POSTED_INTR_WAKEUP_VECTOR.
10484          */
10485         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
10486         vmx->pi_desc.sn = 1;
10487
10488         return &vmx->vcpu;
10489
10490 free_vmcs:
10491         free_vpid(vmx->nested.vpid02);
10492         free_loaded_vmcs(vmx->loaded_vmcs);
10493 free_msrs:
10494         kfree(vmx->guest_msrs);
10495 free_pml:
10496         vmx_destroy_pml_buffer(vmx);
10497 uninit_vcpu:
10498         kvm_vcpu_uninit(&vmx->vcpu);
10499 free_vcpu:
10500         free_vpid(vmx->vpid);
10501         kmem_cache_free(kvm_vcpu_cache, vmx);
10502         return ERR_PTR(err);
10503 }
10504
10505 #define L1TF_MSG "SMT enabled with L1TF CPU bug present. Refer to CVE-2018-3620 for details.\n"
10506
10507 static int vmx_vm_init(struct kvm *kvm)
10508 {
10509         if (!ple_gap)
10510                 kvm->arch.pause_in_guest = true;
10511
10512         if (boot_cpu_has(X86_BUG_L1TF) && cpu_smt_control == CPU_SMT_ENABLED) {
10513                 if (nosmt) {
10514                         pr_err(L1TF_MSG);
10515                         return -EOPNOTSUPP;
10516                 }
10517                 pr_warn(L1TF_MSG);
10518         }
10519         return 0;
10520 }
10521
10522 static void __init vmx_check_processor_compat(void *rtn)
10523 {
10524         struct vmcs_config vmcs_conf;
10525
10526         *(int *)rtn = 0;
10527         if (setup_vmcs_config(&vmcs_conf) < 0)
10528                 *(int *)rtn = -EIO;
10529         nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, enable_apicv);
10530         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
10531                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
10532                                 smp_processor_id());
10533                 *(int *)rtn = -EIO;
10534         }
10535 }
10536
10537 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
10538 {
10539         u8 cache;
10540         u64 ipat = 0;
10541
10542         /* For VT-d and EPT combination
10543          * 1. MMIO: always map as UC
10544          * 2. EPT with VT-d:
10545          *   a. VT-d without snooping control feature: can't guarantee the
10546          *      result, try to trust guest.
10547          *   b. VT-d with snooping control feature: snooping control feature of
10548          *      VT-d engine can guarantee the cache correctness. Just set it
10549          *      to WB to keep consistent with host. So the same as item 3.
10550          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
10551          *    consistent with host MTRR
10552          */
10553         if (is_mmio) {
10554                 cache = MTRR_TYPE_UNCACHABLE;
10555                 goto exit;
10556         }
10557
10558         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
10559                 ipat = VMX_EPT_IPAT_BIT;
10560                 cache = MTRR_TYPE_WRBACK;
10561                 goto exit;
10562         }
10563
10564         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
10565                 ipat = VMX_EPT_IPAT_BIT;
10566                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
10567                         cache = MTRR_TYPE_WRBACK;
10568                 else
10569                         cache = MTRR_TYPE_UNCACHABLE;
10570                 goto exit;
10571         }
10572
10573         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
10574
10575 exit:
10576         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
10577 }
10578
10579 static int vmx_get_lpage_level(void)
10580 {
10581         if (enable_ept && !cpu_has_vmx_ept_1g_page())
10582                 return PT_DIRECTORY_LEVEL;
10583         else
10584                 /* For shadow and EPT supported 1GB page */
10585                 return PT_PDPE_LEVEL;
10586 }
10587
10588 static void vmcs_set_secondary_exec_control(u32 new_ctl)
10589 {
10590         /*
10591          * These bits in the secondary execution controls field
10592          * are dynamic, the others are mostly based on the hypervisor
10593          * architecture and the guest's CPUID.  Do not touch the
10594          * dynamic bits.
10595          */
10596         u32 mask =
10597                 SECONDARY_EXEC_SHADOW_VMCS |
10598                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
10599                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10600                 SECONDARY_EXEC_DESC;
10601
10602         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
10603
10604         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
10605                      (new_ctl & ~mask) | (cur_ctl & mask));
10606 }
10607
10608 /*
10609  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
10610  * (indicating "allowed-1") if they are supported in the guest's CPUID.
10611  */
10612 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
10613 {
10614         struct vcpu_vmx *vmx = to_vmx(vcpu);
10615         struct kvm_cpuid_entry2 *entry;
10616
10617         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
10618         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
10619
10620 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
10621         if (entry && (entry->_reg & (_cpuid_mask)))                     \
10622                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
10623 } while (0)
10624
10625         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
10626         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
10627         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
10628         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
10629         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
10630         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
10631         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
10632         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
10633         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
10634         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
10635         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
10636         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
10637         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
10638         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
10639         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
10640
10641         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
10642         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
10643         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
10644         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
10645         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
10646         cr4_fixed1_update(X86_CR4_UMIP,       ecx, bit(X86_FEATURE_UMIP));
10647
10648 #undef cr4_fixed1_update
10649 }
10650
10651 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
10652 {
10653         struct vcpu_vmx *vmx = to_vmx(vcpu);
10654
10655         if (cpu_has_secondary_exec_ctrls()) {
10656                 vmx_compute_secondary_exec_control(vmx);
10657                 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
10658         }
10659
10660         if (nested_vmx_allowed(vcpu))
10661                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
10662                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
10663         else
10664                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
10665                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
10666
10667         if (nested_vmx_allowed(vcpu))
10668                 nested_vmx_cr_fixed1_bits_update(vcpu);
10669 }
10670
10671 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
10672 {
10673         if (func == 1 && nested)
10674                 entry->ecx |= bit(X86_FEATURE_VMX);
10675 }
10676
10677 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
10678                 struct x86_exception *fault)
10679 {
10680         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10681         struct vcpu_vmx *vmx = to_vmx(vcpu);
10682         u32 exit_reason;
10683         unsigned long exit_qualification = vcpu->arch.exit_qualification;
10684
10685         if (vmx->nested.pml_full) {
10686                 exit_reason = EXIT_REASON_PML_FULL;
10687                 vmx->nested.pml_full = false;
10688                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
10689         } else if (fault->error_code & PFERR_RSVD_MASK)
10690                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
10691         else
10692                 exit_reason = EXIT_REASON_EPT_VIOLATION;
10693
10694         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
10695         vmcs12->guest_physical_address = fault->address;
10696 }
10697
10698 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
10699 {
10700         return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
10701 }
10702
10703 /* Callbacks for nested_ept_init_mmu_context: */
10704
10705 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
10706 {
10707         /* return the page table to be shadowed - in our case, EPT12 */
10708         return get_vmcs12(vcpu)->ept_pointer;
10709 }
10710
10711 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
10712 {
10713         WARN_ON(mmu_is_nested(vcpu));
10714         if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
10715                 return 1;
10716
10717         kvm_mmu_unload(vcpu);
10718         kvm_init_shadow_ept_mmu(vcpu,
10719                         to_vmx(vcpu)->nested.msrs.ept_caps &
10720                         VMX_EPT_EXECUTE_ONLY_BIT,
10721                         nested_ept_ad_enabled(vcpu));
10722         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
10723         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
10724         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
10725
10726         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
10727         return 0;
10728 }
10729
10730 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
10731 {
10732         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
10733 }
10734
10735 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
10736                                             u16 error_code)
10737 {
10738         bool inequality, bit;
10739
10740         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
10741         inequality =
10742                 (error_code & vmcs12->page_fault_error_code_mask) !=
10743                  vmcs12->page_fault_error_code_match;
10744         return inequality ^ bit;
10745 }
10746
10747 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
10748                 struct x86_exception *fault)
10749 {
10750         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10751
10752         WARN_ON(!is_guest_mode(vcpu));
10753
10754         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
10755                 !to_vmx(vcpu)->nested.nested_run_pending) {
10756                 vmcs12->vm_exit_intr_error_code = fault->error_code;
10757                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10758                                   PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
10759                                   INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
10760                                   fault->address);
10761         } else {
10762                 kvm_inject_page_fault(vcpu, fault);
10763         }
10764 }
10765
10766 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10767                                                  struct vmcs12 *vmcs12);
10768
10769 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
10770                                         struct vmcs12 *vmcs12)
10771 {
10772         struct vcpu_vmx *vmx = to_vmx(vcpu);
10773         struct page *page;
10774         u64 hpa;
10775
10776         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10777                 /*
10778                  * Translate L1 physical address to host physical
10779                  * address for vmcs02. Keep the page pinned, so this
10780                  * physical address remains valid. We keep a reference
10781                  * to it so we can release it later.
10782                  */
10783                 if (vmx->nested.apic_access_page) { /* shouldn't happen */
10784                         kvm_release_page_dirty(vmx->nested.apic_access_page);
10785                         vmx->nested.apic_access_page = NULL;
10786                 }
10787                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
10788                 /*
10789                  * If translation failed, no matter: This feature asks
10790                  * to exit when accessing the given address, and if it
10791                  * can never be accessed, this feature won't do
10792                  * anything anyway.
10793                  */
10794                 if (!is_error_page(page)) {
10795                         vmx->nested.apic_access_page = page;
10796                         hpa = page_to_phys(vmx->nested.apic_access_page);
10797                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
10798                 } else {
10799                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
10800                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10801                 }
10802         }
10803
10804         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
10805                 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
10806                         kvm_release_page_dirty(vmx->nested.virtual_apic_page);
10807                         vmx->nested.virtual_apic_page = NULL;
10808                 }
10809                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
10810
10811                 /*
10812                  * If translation failed, VM entry will fail because
10813                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
10814                  * Failing the vm entry is _not_ what the processor
10815                  * does but it's basically the only possibility we
10816                  * have.  We could still enter the guest if CR8 load
10817                  * exits are enabled, CR8 store exits are enabled, and
10818                  * virtualize APIC access is disabled; in this case
10819                  * the processor would never use the TPR shadow and we
10820                  * could simply clear the bit from the execution
10821                  * control.  But such a configuration is useless, so
10822                  * let's keep the code simple.
10823                  */
10824                 if (!is_error_page(page)) {
10825                         vmx->nested.virtual_apic_page = page;
10826                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
10827                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
10828                 }
10829         }
10830
10831         if (nested_cpu_has_posted_intr(vmcs12)) {
10832                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
10833                         kunmap(vmx->nested.pi_desc_page);
10834                         kvm_release_page_dirty(vmx->nested.pi_desc_page);
10835                         vmx->nested.pi_desc_page = NULL;
10836                 }
10837                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
10838                 if (is_error_page(page))
10839                         return;
10840                 vmx->nested.pi_desc_page = page;
10841                 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
10842                 vmx->nested.pi_desc =
10843                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
10844                         (unsigned long)(vmcs12->posted_intr_desc_addr &
10845                         (PAGE_SIZE - 1)));
10846                 vmcs_write64(POSTED_INTR_DESC_ADDR,
10847                         page_to_phys(vmx->nested.pi_desc_page) +
10848                         (unsigned long)(vmcs12->posted_intr_desc_addr &
10849                         (PAGE_SIZE - 1)));
10850         }
10851         if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
10852                 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
10853                               CPU_BASED_USE_MSR_BITMAPS);
10854         else
10855                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
10856                                 CPU_BASED_USE_MSR_BITMAPS);
10857 }
10858
10859 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
10860 {
10861         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
10862         struct vcpu_vmx *vmx = to_vmx(vcpu);
10863
10864         if (vcpu->arch.virtual_tsc_khz == 0)
10865                 return;
10866
10867         /* Make sure short timeouts reliably trigger an immediate vmexit.
10868          * hrtimer_start does not guarantee this. */
10869         if (preemption_timeout <= 1) {
10870                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
10871                 return;
10872         }
10873
10874         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10875         preemption_timeout *= 1000000;
10876         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
10877         hrtimer_start(&vmx->nested.preemption_timer,
10878                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
10879 }
10880
10881 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
10882                                                struct vmcs12 *vmcs12)
10883 {
10884         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
10885                 return 0;
10886
10887         if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
10888             !page_address_valid(vcpu, vmcs12->io_bitmap_b))
10889                 return -EINVAL;
10890
10891         return 0;
10892 }
10893
10894 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
10895                                                 struct vmcs12 *vmcs12)
10896 {
10897         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10898                 return 0;
10899
10900         if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
10901                 return -EINVAL;
10902
10903         return 0;
10904 }
10905
10906 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
10907                                                 struct vmcs12 *vmcs12)
10908 {
10909         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10910                 return 0;
10911
10912         if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
10913                 return -EINVAL;
10914
10915         return 0;
10916 }
10917
10918 /*
10919  * Merge L0's and L1's MSR bitmap, return false to indicate that
10920  * we do not use the hardware.
10921  */
10922 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10923                                                  struct vmcs12 *vmcs12)
10924 {
10925         int msr;
10926         struct page *page;
10927         unsigned long *msr_bitmap_l1;
10928         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
10929         /*
10930          * pred_cmd & spec_ctrl are trying to verify two things:
10931          *
10932          * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
10933          *    ensures that we do not accidentally generate an L02 MSR bitmap
10934          *    from the L12 MSR bitmap that is too permissive.
10935          * 2. That L1 or L2s have actually used the MSR. This avoids
10936          *    unnecessarily merging of the bitmap if the MSR is unused. This
10937          *    works properly because we only update the L01 MSR bitmap lazily.
10938          *    So even if L0 should pass L1 these MSRs, the L01 bitmap is only
10939          *    updated to reflect this when L1 (or its L2s) actually write to
10940          *    the MSR.
10941          */
10942         bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
10943         bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
10944
10945         /* Nothing to do if the MSR bitmap is not in use.  */
10946         if (!cpu_has_vmx_msr_bitmap() ||
10947             !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10948                 return false;
10949
10950         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10951             !pred_cmd && !spec_ctrl)
10952                 return false;
10953
10954         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
10955         if (is_error_page(page))
10956                 return false;
10957
10958         msr_bitmap_l1 = (unsigned long *)kmap(page);
10959         if (nested_cpu_has_apic_reg_virt(vmcs12)) {
10960                 /*
10961                  * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it
10962                  * just lets the processor take the value from the virtual-APIC page;
10963                  * take those 256 bits directly from the L1 bitmap.
10964                  */
10965                 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10966                         unsigned word = msr / BITS_PER_LONG;
10967                         msr_bitmap_l0[word] = msr_bitmap_l1[word];
10968                         msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10969                 }
10970         } else {
10971                 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10972                         unsigned word = msr / BITS_PER_LONG;
10973                         msr_bitmap_l0[word] = ~0;
10974                         msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10975                 }
10976         }
10977
10978         nested_vmx_disable_intercept_for_msr(
10979                 msr_bitmap_l1, msr_bitmap_l0,
10980                 X2APIC_MSR(APIC_TASKPRI),
10981                 MSR_TYPE_W);
10982
10983         if (nested_cpu_has_vid(vmcs12)) {
10984                 nested_vmx_disable_intercept_for_msr(
10985                         msr_bitmap_l1, msr_bitmap_l0,
10986                         X2APIC_MSR(APIC_EOI),
10987                         MSR_TYPE_W);
10988                 nested_vmx_disable_intercept_for_msr(
10989                         msr_bitmap_l1, msr_bitmap_l0,
10990                         X2APIC_MSR(APIC_SELF_IPI),
10991                         MSR_TYPE_W);
10992         }
10993
10994         if (spec_ctrl)
10995                 nested_vmx_disable_intercept_for_msr(
10996                                         msr_bitmap_l1, msr_bitmap_l0,
10997                                         MSR_IA32_SPEC_CTRL,
10998                                         MSR_TYPE_R | MSR_TYPE_W);
10999
11000         if (pred_cmd)
11001                 nested_vmx_disable_intercept_for_msr(
11002                                         msr_bitmap_l1, msr_bitmap_l0,
11003                                         MSR_IA32_PRED_CMD,
11004                                         MSR_TYPE_W);
11005
11006         kunmap(page);
11007         kvm_release_page_clean(page);
11008
11009         return true;
11010 }
11011
11012 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu,
11013                                           struct vmcs12 *vmcs12)
11014 {
11015         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
11016             !page_address_valid(vcpu, vmcs12->apic_access_addr))
11017                 return -EINVAL;
11018         else
11019                 return 0;
11020 }
11021
11022 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
11023                                            struct vmcs12 *vmcs12)
11024 {
11025         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
11026             !nested_cpu_has_apic_reg_virt(vmcs12) &&
11027             !nested_cpu_has_vid(vmcs12) &&
11028             !nested_cpu_has_posted_intr(vmcs12))
11029                 return 0;
11030
11031         /*
11032          * If virtualize x2apic mode is enabled,
11033          * virtualize apic access must be disabled.
11034          */
11035         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
11036             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
11037                 return -EINVAL;
11038
11039         /*
11040          * If virtual interrupt delivery is enabled,
11041          * we must exit on external interrupts.
11042          */
11043         if (nested_cpu_has_vid(vmcs12) &&
11044            !nested_exit_on_intr(vcpu))
11045                 return -EINVAL;
11046
11047         /*
11048          * bits 15:8 should be zero in posted_intr_nv,
11049          * the descriptor address has been already checked
11050          * in nested_get_vmcs12_pages.
11051          */
11052         if (nested_cpu_has_posted_intr(vmcs12) &&
11053            (!nested_cpu_has_vid(vmcs12) ||
11054             !nested_exit_intr_ack_set(vcpu) ||
11055             vmcs12->posted_intr_nv & 0xff00))
11056                 return -EINVAL;
11057
11058         /* tpr shadow is needed by all apicv features. */
11059         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
11060                 return -EINVAL;
11061
11062         return 0;
11063 }
11064
11065 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
11066                                        unsigned long count_field,
11067                                        unsigned long addr_field)
11068 {
11069         int maxphyaddr;
11070         u64 count, addr;
11071
11072         if (vmcs12_read_any(vcpu, count_field, &count) ||
11073             vmcs12_read_any(vcpu, addr_field, &addr)) {
11074                 WARN_ON(1);
11075                 return -EINVAL;
11076         }
11077         if (count == 0)
11078                 return 0;
11079         maxphyaddr = cpuid_maxphyaddr(vcpu);
11080         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
11081             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
11082                 pr_debug_ratelimited(
11083                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
11084                         addr_field, maxphyaddr, count, addr);
11085                 return -EINVAL;
11086         }
11087         return 0;
11088 }
11089
11090 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
11091                                                 struct vmcs12 *vmcs12)
11092 {
11093         if (vmcs12->vm_exit_msr_load_count == 0 &&
11094             vmcs12->vm_exit_msr_store_count == 0 &&
11095             vmcs12->vm_entry_msr_load_count == 0)
11096                 return 0; /* Fast path */
11097         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
11098                                         VM_EXIT_MSR_LOAD_ADDR) ||
11099             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
11100                                         VM_EXIT_MSR_STORE_ADDR) ||
11101             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
11102                                         VM_ENTRY_MSR_LOAD_ADDR))
11103                 return -EINVAL;
11104         return 0;
11105 }
11106
11107 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
11108                                          struct vmcs12 *vmcs12)
11109 {
11110         u64 address = vmcs12->pml_address;
11111         int maxphyaddr = cpuid_maxphyaddr(vcpu);
11112
11113         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
11114                 if (!nested_cpu_has_ept(vmcs12) ||
11115                     !IS_ALIGNED(address, 4096)  ||
11116                     address >> maxphyaddr)
11117                         return -EINVAL;
11118         }
11119
11120         return 0;
11121 }
11122
11123 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
11124                                        struct vmx_msr_entry *e)
11125 {
11126         /* x2APIC MSR accesses are not allowed */
11127         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
11128                 return -EINVAL;
11129         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
11130             e->index == MSR_IA32_UCODE_REV)
11131                 return -EINVAL;
11132         if (e->reserved != 0)
11133                 return -EINVAL;
11134         return 0;
11135 }
11136
11137 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
11138                                      struct vmx_msr_entry *e)
11139 {
11140         if (e->index == MSR_FS_BASE ||
11141             e->index == MSR_GS_BASE ||
11142             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
11143             nested_vmx_msr_check_common(vcpu, e))
11144                 return -EINVAL;
11145         return 0;
11146 }
11147
11148 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
11149                                       struct vmx_msr_entry *e)
11150 {
11151         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
11152             nested_vmx_msr_check_common(vcpu, e))
11153                 return -EINVAL;
11154         return 0;
11155 }
11156
11157 /*
11158  * Load guest's/host's msr at nested entry/exit.
11159  * return 0 for success, entry index for failure.
11160  */
11161 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11162 {
11163         u32 i;
11164         struct vmx_msr_entry e;
11165         struct msr_data msr;
11166
11167         msr.host_initiated = false;
11168         for (i = 0; i < count; i++) {
11169                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
11170                                         &e, sizeof(e))) {
11171                         pr_debug_ratelimited(
11172                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11173                                 __func__, i, gpa + i * sizeof(e));
11174                         goto fail;
11175                 }
11176                 if (nested_vmx_load_msr_check(vcpu, &e)) {
11177                         pr_debug_ratelimited(
11178                                 "%s check failed (%u, 0x%x, 0x%x)\n",
11179                                 __func__, i, e.index, e.reserved);
11180                         goto fail;
11181                 }
11182                 msr.index = e.index;
11183                 msr.data = e.value;
11184                 if (kvm_set_msr(vcpu, &msr)) {
11185                         pr_debug_ratelimited(
11186                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11187                                 __func__, i, e.index, e.value);
11188                         goto fail;
11189                 }
11190         }
11191         return 0;
11192 fail:
11193         return i + 1;
11194 }
11195
11196 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11197 {
11198         u32 i;
11199         struct vmx_msr_entry e;
11200
11201         for (i = 0; i < count; i++) {
11202                 struct msr_data msr_info;
11203                 if (kvm_vcpu_read_guest(vcpu,
11204                                         gpa + i * sizeof(e),
11205                                         &e, 2 * sizeof(u32))) {
11206                         pr_debug_ratelimited(
11207                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11208                                 __func__, i, gpa + i * sizeof(e));
11209                         return -EINVAL;
11210                 }
11211                 if (nested_vmx_store_msr_check(vcpu, &e)) {
11212                         pr_debug_ratelimited(
11213                                 "%s check failed (%u, 0x%x, 0x%x)\n",
11214                                 __func__, i, e.index, e.reserved);
11215                         return -EINVAL;
11216                 }
11217                 msr_info.host_initiated = false;
11218                 msr_info.index = e.index;
11219                 if (kvm_get_msr(vcpu, &msr_info)) {
11220                         pr_debug_ratelimited(
11221                                 "%s cannot read MSR (%u, 0x%x)\n",
11222                                 __func__, i, e.index);
11223                         return -EINVAL;
11224                 }
11225                 if (kvm_vcpu_write_guest(vcpu,
11226                                          gpa + i * sizeof(e) +
11227                                              offsetof(struct vmx_msr_entry, value),
11228                                          &msr_info.data, sizeof(msr_info.data))) {
11229                         pr_debug_ratelimited(
11230                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11231                                 __func__, i, e.index, msr_info.data);
11232                         return -EINVAL;
11233                 }
11234         }
11235         return 0;
11236 }
11237
11238 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
11239 {
11240         unsigned long invalid_mask;
11241
11242         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
11243         return (val & invalid_mask) == 0;
11244 }
11245
11246 /*
11247  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
11248  * emulating VM entry into a guest with EPT enabled.
11249  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
11250  * is assigned to entry_failure_code on failure.
11251  */
11252 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
11253                                u32 *entry_failure_code)
11254 {
11255         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
11256                 if (!nested_cr3_valid(vcpu, cr3)) {
11257                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
11258                         return 1;
11259                 }
11260
11261                 /*
11262                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
11263                  * must not be dereferenced.
11264                  */
11265                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
11266                     !nested_ept) {
11267                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
11268                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
11269                                 return 1;
11270                         }
11271                 }
11272
11273                 vcpu->arch.cr3 = cr3;
11274                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
11275         }
11276
11277         kvm_mmu_reset_context(vcpu);
11278         return 0;
11279 }
11280
11281 static void prepare_vmcs02_full(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11282 {
11283         struct vcpu_vmx *vmx = to_vmx(vcpu);
11284
11285         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
11286         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
11287         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
11288         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
11289         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
11290         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
11291         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
11292         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
11293         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
11294         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
11295         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
11296         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
11297         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
11298         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
11299         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
11300         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
11301         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
11302         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
11303         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
11304         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
11305         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
11306         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
11307         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
11308         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
11309         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
11310         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
11311         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
11312         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
11313         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
11314         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
11315         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
11316
11317         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
11318         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
11319                 vmcs12->guest_pending_dbg_exceptions);
11320         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
11321         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
11322
11323         if (nested_cpu_has_xsaves(vmcs12))
11324                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
11325         vmcs_write64(VMCS_LINK_POINTER, -1ull);
11326
11327         if (cpu_has_vmx_posted_intr())
11328                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
11329
11330         /*
11331          * Whether page-faults are trapped is determined by a combination of
11332          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
11333          * If enable_ept, L0 doesn't care about page faults and we should
11334          * set all of these to L1's desires. However, if !enable_ept, L0 does
11335          * care about (at least some) page faults, and because it is not easy
11336          * (if at all possible?) to merge L0 and L1's desires, we simply ask
11337          * to exit on each and every L2 page fault. This is done by setting
11338          * MASK=MATCH=0 and (see below) EB.PF=1.
11339          * Note that below we don't need special code to set EB.PF beyond the
11340          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
11341          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
11342          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
11343          */
11344         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
11345                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
11346         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
11347                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
11348
11349         /* All VMFUNCs are currently emulated through L0 vmexits.  */
11350         if (cpu_has_vmx_vmfunc())
11351                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
11352
11353         if (cpu_has_vmx_apicv()) {
11354                 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
11355                 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
11356                 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
11357                 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
11358         }
11359
11360         /*
11361          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
11362          * Some constant fields are set here by vmx_set_constant_host_state().
11363          * Other fields are different per CPU, and will be set later when
11364          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
11365          */
11366         vmx_set_constant_host_state(vmx);
11367
11368         /*
11369          * Set the MSR load/store lists to match L0's settings.
11370          */
11371         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
11372         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
11373         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
11374         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
11375         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
11376
11377         set_cr4_guest_host_mask(vmx);
11378
11379         if (vmx_mpx_supported())
11380                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
11381
11382         if (enable_vpid) {
11383                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
11384                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
11385                 else
11386                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
11387         }
11388
11389         /*
11390          * L1 may access the L2's PDPTR, so save them to construct vmcs12
11391          */
11392         if (enable_ept) {
11393                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
11394                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
11395                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
11396                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
11397         }
11398
11399         if (cpu_has_vmx_msr_bitmap())
11400                 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
11401 }
11402
11403 /*
11404  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
11405  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
11406  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
11407  * guest in a way that will both be appropriate to L1's requests, and our
11408  * needs. In addition to modifying the active vmcs (which is vmcs02), this
11409  * function also has additional necessary side-effects, like setting various
11410  * vcpu->arch fields.
11411  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
11412  * is assigned to entry_failure_code on failure.
11413  */
11414 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11415                           u32 *entry_failure_code)
11416 {
11417         struct vcpu_vmx *vmx = to_vmx(vcpu);
11418         u32 exec_control, vmcs12_exec_ctrl;
11419
11420         if (vmx->nested.dirty_vmcs12) {
11421                 prepare_vmcs02_full(vcpu, vmcs12);
11422                 vmx->nested.dirty_vmcs12 = false;
11423         }
11424
11425         /*
11426          * First, the fields that are shadowed.  This must be kept in sync
11427          * with vmx_shadow_fields.h.
11428          */
11429
11430         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
11431         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
11432         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
11433         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
11434         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
11435
11436         /*
11437          * Not in vmcs02: GUEST_PML_INDEX, HOST_FS_SELECTOR, HOST_GS_SELECTOR,
11438          * HOST_FS_BASE, HOST_GS_BASE.
11439          */
11440
11441         if (vmx->nested.nested_run_pending &&
11442             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
11443                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
11444                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
11445         } else {
11446                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
11447                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
11448         }
11449         if (vmx->nested.nested_run_pending) {
11450                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
11451                              vmcs12->vm_entry_intr_info_field);
11452                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
11453                              vmcs12->vm_entry_exception_error_code);
11454                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
11455                              vmcs12->vm_entry_instruction_len);
11456                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
11457                              vmcs12->guest_interruptibility_info);
11458                 vmx->loaded_vmcs->nmi_known_unmasked =
11459                         !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
11460         } else {
11461                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
11462         }
11463         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
11464
11465         exec_control = vmcs12->pin_based_vm_exec_control;
11466
11467         /* Preemption timer setting is only taken from vmcs01.  */
11468         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
11469         exec_control |= vmcs_config.pin_based_exec_ctrl;
11470         if (vmx->hv_deadline_tsc == -1)
11471                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
11472
11473         /* Posted interrupts setting is only taken from vmcs12.  */
11474         if (nested_cpu_has_posted_intr(vmcs12)) {
11475                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
11476                 vmx->nested.pi_pending = false;
11477         } else {
11478                 exec_control &= ~PIN_BASED_POSTED_INTR;
11479         }
11480
11481         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
11482
11483         vmx->nested.preemption_timer_expired = false;
11484         if (nested_cpu_has_preemption_timer(vmcs12))
11485                 vmx_start_preemption_timer(vcpu);
11486
11487         if (cpu_has_secondary_exec_ctrls()) {
11488                 exec_control = vmx->secondary_exec_control;
11489
11490                 /* Take the following fields only from vmcs12 */
11491                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
11492                                   SECONDARY_EXEC_ENABLE_INVPCID |
11493                                   SECONDARY_EXEC_RDTSCP |
11494                                   SECONDARY_EXEC_XSAVES |
11495                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
11496                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
11497                                   SECONDARY_EXEC_ENABLE_VMFUNC);
11498                 if (nested_cpu_has(vmcs12,
11499                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
11500                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
11501                                 ~SECONDARY_EXEC_ENABLE_PML;
11502                         exec_control |= vmcs12_exec_ctrl;
11503                 }
11504
11505                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
11506                         vmcs_write16(GUEST_INTR_STATUS,
11507                                 vmcs12->guest_intr_status);
11508
11509                 /*
11510                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
11511                  * nested_get_vmcs12_pages will either fix it up or
11512                  * remove the VM execution control.
11513                  */
11514                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
11515                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
11516
11517                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
11518         }
11519
11520         /*
11521          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
11522          * entry, but only if the current (host) sp changed from the value
11523          * we wrote last (vmx->host_rsp). This cache is no longer relevant
11524          * if we switch vmcs, and rather than hold a separate cache per vmcs,
11525          * here we just force the write to happen on entry.
11526          */
11527         vmx->host_rsp = 0;
11528
11529         exec_control = vmx_exec_control(vmx); /* L0's desires */
11530         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
11531         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
11532         exec_control &= ~CPU_BASED_TPR_SHADOW;
11533         exec_control |= vmcs12->cpu_based_vm_exec_control;
11534
11535         /*
11536          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
11537          * nested_get_vmcs12_pages can't fix it up, the illegal value
11538          * will result in a VM entry failure.
11539          */
11540         if (exec_control & CPU_BASED_TPR_SHADOW) {
11541                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
11542                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
11543         } else {
11544 #ifdef CONFIG_X86_64
11545                 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
11546                                 CPU_BASED_CR8_STORE_EXITING;
11547 #endif
11548         }
11549
11550         /*
11551          * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
11552          * for I/O port accesses.
11553          */
11554         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
11555         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
11556
11557         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
11558
11559         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
11560          * bitwise-or of what L1 wants to trap for L2, and what we want to
11561          * trap. Note that CR0.TS also needs updating - we do this later.
11562          */
11563         update_exception_bitmap(vcpu);
11564         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
11565         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
11566
11567         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
11568          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
11569          * bits are further modified by vmx_set_efer() below.
11570          */
11571         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
11572
11573         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
11574          * emulated by vmx_set_efer(), below.
11575          */
11576         vm_entry_controls_init(vmx,
11577                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
11578                         ~VM_ENTRY_IA32E_MODE) |
11579                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
11580
11581         if (vmx->nested.nested_run_pending &&
11582             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
11583                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
11584                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
11585         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
11586                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
11587         }
11588
11589         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11590
11591         if (kvm_has_tsc_control)
11592                 decache_tsc_multiplier(vmx);
11593
11594         if (enable_vpid) {
11595                 /*
11596                  * There is no direct mapping between vpid02 and vpid12, the
11597                  * vpid02 is per-vCPU for L0 and reused while the value of
11598                  * vpid12 is changed w/ one invvpid during nested vmentry.
11599                  * The vpid12 is allocated by L1 for L2, so it will not
11600                  * influence global bitmap(for vpid01 and vpid02 allocation)
11601                  * even if spawn a lot of nested vCPUs.
11602                  */
11603                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
11604                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
11605                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
11606                                 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
11607                         }
11608                 } else {
11609                         vmx_flush_tlb(vcpu, true);
11610                 }
11611         }
11612
11613         if (enable_pml) {
11614                 /*
11615                  * Conceptually we want to copy the PML address and index from
11616                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
11617                  * since we always flush the log on each vmexit, this happens
11618                  * to be equivalent to simply resetting the fields in vmcs02.
11619                  */
11620                 ASSERT(vmx->pml_pg);
11621                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
11622                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
11623         }
11624
11625         if (nested_cpu_has_ept(vmcs12)) {
11626                 if (nested_ept_init_mmu_context(vcpu)) {
11627                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
11628                         return 1;
11629                 }
11630         } else if (nested_cpu_has2(vmcs12,
11631                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11632                 vmx_flush_tlb(vcpu, true);
11633         }
11634
11635         /*
11636          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
11637          * bits which we consider mandatory enabled.
11638          * The CR0_READ_SHADOW is what L2 should have expected to read given
11639          * the specifications by L1; It's not enough to take
11640          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
11641          * have more bits than L1 expected.
11642          */
11643         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
11644         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
11645
11646         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
11647         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
11648
11649         if (vmx->nested.nested_run_pending &&
11650             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
11651                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
11652         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
11653                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11654         else
11655                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11656         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
11657         vmx_set_efer(vcpu, vcpu->arch.efer);
11658
11659         /*
11660          * Guest state is invalid and unrestricted guest is disabled,
11661          * which means L1 attempted VMEntry to L2 with invalid state.
11662          * Fail the VMEntry.
11663          */
11664         if (vmx->emulation_required) {
11665                 *entry_failure_code = ENTRY_FAIL_DEFAULT;
11666                 return 1;
11667         }
11668
11669         /* Shadow page tables on either EPT or shadow page tables. */
11670         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
11671                                 entry_failure_code))
11672                 return 1;
11673
11674         if (!enable_ept)
11675                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
11676
11677         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
11678         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
11679         return 0;
11680 }
11681
11682 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12)
11683 {
11684         if (!nested_cpu_has_nmi_exiting(vmcs12) &&
11685             nested_cpu_has_virtual_nmis(vmcs12))
11686                 return -EINVAL;
11687
11688         if (!nested_cpu_has_virtual_nmis(vmcs12) &&
11689             nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING))
11690                 return -EINVAL;
11691
11692         return 0;
11693 }
11694
11695 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11696 {
11697         struct vcpu_vmx *vmx = to_vmx(vcpu);
11698
11699         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
11700             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
11701                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11702
11703         if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
11704                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11705
11706         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
11707                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11708
11709         if (nested_vmx_check_apic_access_controls(vcpu, vmcs12))
11710                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11711
11712         if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
11713                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11714
11715         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
11716                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11717
11718         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
11719                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11720
11721         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
11722                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11723
11724         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
11725                                 vmx->nested.msrs.procbased_ctls_low,
11726                                 vmx->nested.msrs.procbased_ctls_high) ||
11727             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
11728              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
11729                                  vmx->nested.msrs.secondary_ctls_low,
11730                                  vmx->nested.msrs.secondary_ctls_high)) ||
11731             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
11732                                 vmx->nested.msrs.pinbased_ctls_low,
11733                                 vmx->nested.msrs.pinbased_ctls_high) ||
11734             !vmx_control_verify(vmcs12->vm_exit_controls,
11735                                 vmx->nested.msrs.exit_ctls_low,
11736                                 vmx->nested.msrs.exit_ctls_high) ||
11737             !vmx_control_verify(vmcs12->vm_entry_controls,
11738                                 vmx->nested.msrs.entry_ctls_low,
11739                                 vmx->nested.msrs.entry_ctls_high))
11740                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11741
11742         if (nested_vmx_check_nmi_controls(vmcs12))
11743                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11744
11745         if (nested_cpu_has_vmfunc(vmcs12)) {
11746                 if (vmcs12->vm_function_control &
11747                     ~vmx->nested.msrs.vmfunc_controls)
11748                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11749
11750                 if (nested_cpu_has_eptp_switching(vmcs12)) {
11751                         if (!nested_cpu_has_ept(vmcs12) ||
11752                             !page_address_valid(vcpu, vmcs12->eptp_list_address))
11753                                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11754                 }
11755         }
11756
11757         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
11758                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11759
11760         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
11761             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
11762             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
11763                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
11764
11765         return 0;
11766 }
11767
11768 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11769                                   u32 *exit_qual)
11770 {
11771         bool ia32e;
11772
11773         *exit_qual = ENTRY_FAIL_DEFAULT;
11774
11775         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
11776             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
11777                 return 1;
11778
11779         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
11780             vmcs12->vmcs_link_pointer != -1ull) {
11781                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
11782                 return 1;
11783         }
11784
11785         /*
11786          * If the load IA32_EFER VM-entry control is 1, the following checks
11787          * are performed on the field for the IA32_EFER MSR:
11788          * - Bits reserved in the IA32_EFER MSR must be 0.
11789          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
11790          *   the IA-32e mode guest VM-exit control. It must also be identical
11791          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
11792          *   CR0.PG) is 1.
11793          */
11794         if (to_vmx(vcpu)->nested.nested_run_pending &&
11795             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
11796                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
11797                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
11798                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
11799                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
11800                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
11801                         return 1;
11802         }
11803
11804         /*
11805          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
11806          * IA32_EFER MSR must be 0 in the field for that register. In addition,
11807          * the values of the LMA and LME bits in the field must each be that of
11808          * the host address-space size VM-exit control.
11809          */
11810         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
11811                 ia32e = (vmcs12->vm_exit_controls &
11812                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
11813                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
11814                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
11815                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
11816                         return 1;
11817         }
11818
11819         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
11820                 (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) ||
11821                 (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))
11822                         return 1;
11823
11824         return 0;
11825 }
11826
11827 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu)
11828 {
11829         struct vcpu_vmx *vmx = to_vmx(vcpu);
11830         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11831         u32 msr_entry_idx;
11832         u32 exit_qual;
11833         int r;
11834
11835         enter_guest_mode(vcpu);
11836
11837         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
11838                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11839
11840         vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
11841         vmx_segment_cache_clear(vmx);
11842
11843         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
11844                 vcpu->arch.tsc_offset += vmcs12->tsc_offset;
11845
11846         r = EXIT_REASON_INVALID_STATE;
11847         if (prepare_vmcs02(vcpu, vmcs12, &exit_qual))
11848                 goto fail;
11849
11850         nested_get_vmcs12_pages(vcpu, vmcs12);
11851
11852         r = EXIT_REASON_MSR_LOAD_FAIL;
11853         msr_entry_idx = nested_vmx_load_msr(vcpu,
11854                                             vmcs12->vm_entry_msr_load_addr,
11855                                             vmcs12->vm_entry_msr_load_count);
11856         if (msr_entry_idx)
11857                 goto fail;
11858
11859         /*
11860          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
11861          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
11862          * returned as far as L1 is concerned. It will only return (and set
11863          * the success flag) when L2 exits (see nested_vmx_vmexit()).
11864          */
11865         return 0;
11866
11867 fail:
11868         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
11869                 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
11870         leave_guest_mode(vcpu);
11871         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11872         nested_vmx_entry_failure(vcpu, vmcs12, r, exit_qual);
11873         return 1;
11874 }
11875
11876 /*
11877  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
11878  * for running an L2 nested guest.
11879  */
11880 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
11881 {
11882         struct vmcs12 *vmcs12;
11883         struct vcpu_vmx *vmx = to_vmx(vcpu);
11884         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
11885         u32 exit_qual;
11886         int ret;
11887
11888         if (!nested_vmx_check_permission(vcpu))
11889                 return 1;
11890
11891         if (!nested_vmx_check_vmcs12(vcpu))
11892                 goto out;
11893
11894         vmcs12 = get_vmcs12(vcpu);
11895
11896         if (enable_shadow_vmcs)
11897                 copy_shadow_to_vmcs12(vmx);
11898
11899         /*
11900          * The nested entry process starts with enforcing various prerequisites
11901          * on vmcs12 as required by the Intel SDM, and act appropriately when
11902          * they fail: As the SDM explains, some conditions should cause the
11903          * instruction to fail, while others will cause the instruction to seem
11904          * to succeed, but return an EXIT_REASON_INVALID_STATE.
11905          * To speed up the normal (success) code path, we should avoid checking
11906          * for misconfigurations which will anyway be caught by the processor
11907          * when using the merged vmcs02.
11908          */
11909         if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
11910                 nested_vmx_failValid(vcpu,
11911                                      VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
11912                 goto out;
11913         }
11914
11915         if (vmcs12->launch_state == launch) {
11916                 nested_vmx_failValid(vcpu,
11917                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
11918                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
11919                 goto out;
11920         }
11921
11922         ret = check_vmentry_prereqs(vcpu, vmcs12);
11923         if (ret) {
11924                 nested_vmx_failValid(vcpu, ret);
11925                 goto out;
11926         }
11927
11928         /*
11929          * After this point, the trap flag no longer triggers a singlestep trap
11930          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
11931          * This is not 100% correct; for performance reasons, we delegate most
11932          * of the checks on host state to the processor.  If those fail,
11933          * the singlestep trap is missed.
11934          */
11935         skip_emulated_instruction(vcpu);
11936
11937         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
11938         if (ret) {
11939                 nested_vmx_entry_failure(vcpu, vmcs12,
11940                                          EXIT_REASON_INVALID_STATE, exit_qual);
11941                 return 1;
11942         }
11943
11944         /*
11945          * We're finally done with prerequisite checking, and can start with
11946          * the nested entry.
11947          */
11948
11949         vmx->nested.nested_run_pending = 1;
11950         ret = enter_vmx_non_root_mode(vcpu);
11951         if (ret) {
11952                 vmx->nested.nested_run_pending = 0;
11953                 return ret;
11954         }
11955
11956         /* Hide L1D cache contents from the nested guest.  */
11957         vmx->vcpu.arch.l1tf_flush_l1d = true;
11958
11959         /*
11960          * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken
11961          * by event injection, halt vcpu.
11962          */
11963         if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) &&
11964             !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK)) {
11965                 vmx->nested.nested_run_pending = 0;
11966                 return kvm_vcpu_halt(vcpu);
11967         }
11968         return 1;
11969
11970 out:
11971         return kvm_skip_emulated_instruction(vcpu);
11972 }
11973
11974 /*
11975  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11976  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11977  * This function returns the new value we should put in vmcs12.guest_cr0.
11978  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11979  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11980  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11981  *     didn't trap the bit, because if L1 did, so would L0).
11982  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11983  *     been modified by L2, and L1 knows it. So just leave the old value of
11984  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11985  *     isn't relevant, because if L0 traps this bit it can set it to anything.
11986  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11987  *     changed these bits, and therefore they need to be updated, but L0
11988  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11989  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11990  */
11991 static inline unsigned long
11992 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11993 {
11994         return
11995         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
11996         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
11997         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
11998                         vcpu->arch.cr0_guest_owned_bits));
11999 }
12000
12001 static inline unsigned long
12002 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12003 {
12004         return
12005         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
12006         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
12007         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
12008                         vcpu->arch.cr4_guest_owned_bits));
12009 }
12010
12011 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
12012                                        struct vmcs12 *vmcs12)
12013 {
12014         u32 idt_vectoring;
12015         unsigned int nr;
12016
12017         if (vcpu->arch.exception.injected) {
12018                 nr = vcpu->arch.exception.nr;
12019                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
12020
12021                 if (kvm_exception_is_soft(nr)) {
12022                         vmcs12->vm_exit_instruction_len =
12023                                 vcpu->arch.event_exit_inst_len;
12024                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
12025                 } else
12026                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
12027
12028                 if (vcpu->arch.exception.has_error_code) {
12029                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
12030                         vmcs12->idt_vectoring_error_code =
12031                                 vcpu->arch.exception.error_code;
12032                 }
12033
12034                 vmcs12->idt_vectoring_info_field = idt_vectoring;
12035         } else if (vcpu->arch.nmi_injected) {
12036                 vmcs12->idt_vectoring_info_field =
12037                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
12038         } else if (vcpu->arch.interrupt.injected) {
12039                 nr = vcpu->arch.interrupt.nr;
12040                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
12041
12042                 if (vcpu->arch.interrupt.soft) {
12043                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
12044                         vmcs12->vm_entry_instruction_len =
12045                                 vcpu->arch.event_exit_inst_len;
12046                 } else
12047                         idt_vectoring |= INTR_TYPE_EXT_INTR;
12048
12049                 vmcs12->idt_vectoring_info_field = idt_vectoring;
12050         }
12051 }
12052
12053 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
12054 {
12055         struct vcpu_vmx *vmx = to_vmx(vcpu);
12056         unsigned long exit_qual;
12057         bool block_nested_events =
12058             vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
12059
12060         if (vcpu->arch.exception.pending &&
12061                 nested_vmx_check_exception(vcpu, &exit_qual)) {
12062                 if (block_nested_events)
12063                         return -EBUSY;
12064                 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
12065                 return 0;
12066         }
12067
12068         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
12069             vmx->nested.preemption_timer_expired) {
12070                 if (block_nested_events)
12071                         return -EBUSY;
12072                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
12073                 return 0;
12074         }
12075
12076         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
12077                 if (block_nested_events)
12078                         return -EBUSY;
12079                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
12080                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
12081                                   INTR_INFO_VALID_MASK, 0);
12082                 /*
12083                  * The NMI-triggered VM exit counts as injection:
12084                  * clear this one and block further NMIs.
12085                  */
12086                 vcpu->arch.nmi_pending = 0;
12087                 vmx_set_nmi_mask(vcpu, true);
12088                 return 0;
12089         }
12090
12091         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
12092             nested_exit_on_intr(vcpu)) {
12093                 if (block_nested_events)
12094                         return -EBUSY;
12095                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
12096                 return 0;
12097         }
12098
12099         vmx_complete_nested_posted_interrupt(vcpu);
12100         return 0;
12101 }
12102
12103 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
12104 {
12105         ktime_t remaining =
12106                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
12107         u64 value;
12108
12109         if (ktime_to_ns(remaining) <= 0)
12110                 return 0;
12111
12112         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
12113         do_div(value, 1000000);
12114         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
12115 }
12116
12117 /*
12118  * Update the guest state fields of vmcs12 to reflect changes that
12119  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
12120  * VM-entry controls is also updated, since this is really a guest
12121  * state bit.)
12122  */
12123 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12124 {
12125         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
12126         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
12127
12128         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
12129         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
12130         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
12131
12132         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
12133         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
12134         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
12135         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
12136         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
12137         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
12138         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
12139         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
12140         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
12141         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
12142         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
12143         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
12144         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
12145         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
12146         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
12147         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
12148         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
12149         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
12150         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
12151         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
12152         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
12153         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
12154         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
12155         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
12156         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
12157         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
12158         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
12159         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
12160         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
12161         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
12162         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
12163         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
12164         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
12165         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
12166         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
12167         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
12168
12169         vmcs12->guest_interruptibility_info =
12170                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
12171         vmcs12->guest_pending_dbg_exceptions =
12172                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
12173         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
12174                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
12175         else
12176                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
12177
12178         if (nested_cpu_has_preemption_timer(vmcs12)) {
12179                 if (vmcs12->vm_exit_controls &
12180                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
12181                         vmcs12->vmx_preemption_timer_value =
12182                                 vmx_get_preemption_timer_value(vcpu);
12183                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
12184         }
12185
12186         /*
12187          * In some cases (usually, nested EPT), L2 is allowed to change its
12188          * own CR3 without exiting. If it has changed it, we must keep it.
12189          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
12190          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
12191          *
12192          * Additionally, restore L2's PDPTR to vmcs12.
12193          */
12194         if (enable_ept) {
12195                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
12196                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
12197                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
12198                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
12199                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
12200         }
12201
12202         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
12203
12204         if (nested_cpu_has_vid(vmcs12))
12205                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
12206
12207         vmcs12->vm_entry_controls =
12208                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
12209                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
12210
12211         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
12212                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
12213                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
12214         }
12215
12216         /* TODO: These cannot have changed unless we have MSR bitmaps and
12217          * the relevant bit asks not to trap the change */
12218         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
12219                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
12220         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
12221                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
12222         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
12223         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
12224         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
12225         if (kvm_mpx_supported())
12226                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
12227 }
12228
12229 /*
12230  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
12231  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
12232  * and this function updates it to reflect the changes to the guest state while
12233  * L2 was running (and perhaps made some exits which were handled directly by L0
12234  * without going back to L1), and to reflect the exit reason.
12235  * Note that we do not have to copy here all VMCS fields, just those that
12236  * could have changed by the L2 guest or the exit - i.e., the guest-state and
12237  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
12238  * which already writes to vmcs12 directly.
12239  */
12240 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
12241                            u32 exit_reason, u32 exit_intr_info,
12242                            unsigned long exit_qualification)
12243 {
12244         /* update guest state fields: */
12245         sync_vmcs12(vcpu, vmcs12);
12246
12247         /* update exit information fields: */
12248
12249         vmcs12->vm_exit_reason = exit_reason;
12250         vmcs12->exit_qualification = exit_qualification;
12251         vmcs12->vm_exit_intr_info = exit_intr_info;
12252
12253         vmcs12->idt_vectoring_info_field = 0;
12254         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
12255         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
12256
12257         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
12258                 vmcs12->launch_state = 1;
12259
12260                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
12261                  * instead of reading the real value. */
12262                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
12263
12264                 /*
12265                  * Transfer the event that L0 or L1 may wanted to inject into
12266                  * L2 to IDT_VECTORING_INFO_FIELD.
12267                  */
12268                 vmcs12_save_pending_event(vcpu, vmcs12);
12269         }
12270
12271         /*
12272          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
12273          * preserved above and would only end up incorrectly in L1.
12274          */
12275         vcpu->arch.nmi_injected = false;
12276         kvm_clear_exception_queue(vcpu);
12277         kvm_clear_interrupt_queue(vcpu);
12278 }
12279
12280 static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu,
12281                         struct vmcs12 *vmcs12)
12282 {
12283         u32 entry_failure_code;
12284
12285         nested_ept_uninit_mmu_context(vcpu);
12286
12287         /*
12288          * Only PDPTE load can fail as the value of cr3 was checked on entry and
12289          * couldn't have changed.
12290          */
12291         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
12292                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
12293
12294         if (!enable_ept)
12295                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
12296 }
12297
12298 /*
12299  * A part of what we need to when the nested L2 guest exits and we want to
12300  * run its L1 parent, is to reset L1's guest state to the host state specified
12301  * in vmcs12.
12302  * This function is to be called not only on normal nested exit, but also on
12303  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
12304  * Failures During or After Loading Guest State").
12305  * This function should be called when the active VMCS is L1's (vmcs01).
12306  */
12307 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
12308                                    struct vmcs12 *vmcs12)
12309 {
12310         struct kvm_segment seg;
12311
12312         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
12313                 vcpu->arch.efer = vmcs12->host_ia32_efer;
12314         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
12315                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
12316         else
12317                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
12318         vmx_set_efer(vcpu, vcpu->arch.efer);
12319
12320         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
12321         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
12322         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
12323         /*
12324          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
12325          * actually changed, because vmx_set_cr0 refers to efer set above.
12326          *
12327          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
12328          * (KVM doesn't change it);
12329          */
12330         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
12331         vmx_set_cr0(vcpu, vmcs12->host_cr0);
12332
12333         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
12334         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
12335         vmx_set_cr4(vcpu, vmcs12->host_cr4);
12336
12337         load_vmcs12_mmu_host_state(vcpu, vmcs12);
12338
12339         /*
12340          * If vmcs01 don't use VPID, CPU flushes TLB on every
12341          * VMEntry/VMExit. Thus, no need to flush TLB.
12342          *
12343          * If vmcs12 uses VPID, TLB entries populated by L2 are
12344          * tagged with vmx->nested.vpid02 while L1 entries are tagged
12345          * with vmx->vpid. Thus, no need to flush TLB.
12346          *
12347          * Therefore, flush TLB only in case vmcs01 uses VPID and
12348          * vmcs12 don't use VPID as in this case L1 & L2 TLB entries
12349          * are both tagged with vmx->vpid.
12350          */
12351         if (enable_vpid &&
12352             !(nested_cpu_has_vpid(vmcs12) && to_vmx(vcpu)->nested.vpid02)) {
12353                 vmx_flush_tlb(vcpu, true);
12354         }
12355
12356         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
12357         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
12358         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
12359         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
12360         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
12361         vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
12362         vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
12363
12364         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
12365         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
12366                 vmcs_write64(GUEST_BNDCFGS, 0);
12367
12368         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
12369                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
12370                 vcpu->arch.pat = vmcs12->host_ia32_pat;
12371         }
12372         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
12373                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
12374                         vmcs12->host_ia32_perf_global_ctrl);
12375
12376         /* Set L1 segment info according to Intel SDM
12377             27.5.2 Loading Host Segment and Descriptor-Table Registers */
12378         seg = (struct kvm_segment) {
12379                 .base = 0,
12380                 .limit = 0xFFFFFFFF,
12381                 .selector = vmcs12->host_cs_selector,
12382                 .type = 11,
12383                 .present = 1,
12384                 .s = 1,
12385                 .g = 1
12386         };
12387         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
12388                 seg.l = 1;
12389         else
12390                 seg.db = 1;
12391         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
12392         seg = (struct kvm_segment) {
12393                 .base = 0,
12394                 .limit = 0xFFFFFFFF,
12395                 .type = 3,
12396                 .present = 1,
12397                 .s = 1,
12398                 .db = 1,
12399                 .g = 1
12400         };
12401         seg.selector = vmcs12->host_ds_selector;
12402         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
12403         seg.selector = vmcs12->host_es_selector;
12404         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
12405         seg.selector = vmcs12->host_ss_selector;
12406         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
12407         seg.selector = vmcs12->host_fs_selector;
12408         seg.base = vmcs12->host_fs_base;
12409         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
12410         seg.selector = vmcs12->host_gs_selector;
12411         seg.base = vmcs12->host_gs_base;
12412         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
12413         seg = (struct kvm_segment) {
12414                 .base = vmcs12->host_tr_base,
12415                 .limit = 0x67,
12416                 .selector = vmcs12->host_tr_selector,
12417                 .type = 11,
12418                 .present = 1
12419         };
12420         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
12421
12422         kvm_set_dr(vcpu, 7, 0x400);
12423         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
12424
12425         if (cpu_has_vmx_msr_bitmap())
12426                 vmx_update_msr_bitmap(vcpu);
12427
12428         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
12429                                 vmcs12->vm_exit_msr_load_count))
12430                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
12431 }
12432
12433 /*
12434  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
12435  * and modify vmcs12 to make it see what it would expect to see there if
12436  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
12437  */
12438 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
12439                               u32 exit_intr_info,
12440                               unsigned long exit_qualification)
12441 {
12442         struct vcpu_vmx *vmx = to_vmx(vcpu);
12443         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12444
12445         /* trying to cancel vmlaunch/vmresume is a bug */
12446         WARN_ON_ONCE(vmx->nested.nested_run_pending);
12447
12448         /*
12449          * The only expected VM-instruction error is "VM entry with
12450          * invalid control field(s)." Anything else indicates a
12451          * problem with L0.
12452          */
12453         WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
12454                                    VMXERR_ENTRY_INVALID_CONTROL_FIELD));
12455
12456         leave_guest_mode(vcpu);
12457
12458         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
12459                 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
12460
12461         if (likely(!vmx->fail)) {
12462                 if (exit_reason == -1)
12463                         sync_vmcs12(vcpu, vmcs12);
12464                 else
12465                         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
12466                                        exit_qualification);
12467
12468                 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
12469                                          vmcs12->vm_exit_msr_store_count))
12470                         nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
12471         }
12472
12473         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
12474         vm_entry_controls_reset_shadow(vmx);
12475         vm_exit_controls_reset_shadow(vmx);
12476         vmx_segment_cache_clear(vmx);
12477
12478         /* Update any VMCS fields that might have changed while L2 ran */
12479         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
12480         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
12481         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
12482         if (vmx->hv_deadline_tsc == -1)
12483                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
12484                                 PIN_BASED_VMX_PREEMPTION_TIMER);
12485         else
12486                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
12487                               PIN_BASED_VMX_PREEMPTION_TIMER);
12488         if (kvm_has_tsc_control)
12489                 decache_tsc_multiplier(vmx);
12490
12491         if (vmx->nested.change_vmcs01_virtual_apic_mode) {
12492                 vmx->nested.change_vmcs01_virtual_apic_mode = false;
12493                 vmx_set_virtual_apic_mode(vcpu);
12494         } else if (!nested_cpu_has_ept(vmcs12) &&
12495                    nested_cpu_has2(vmcs12,
12496                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
12497                 vmx_flush_tlb(vcpu, true);
12498         }
12499
12500         /* This is needed for same reason as it was needed in prepare_vmcs02 */
12501         vmx->host_rsp = 0;
12502
12503         /* Unpin physical memory we referred to in vmcs02 */
12504         if (vmx->nested.apic_access_page) {
12505                 kvm_release_page_dirty(vmx->nested.apic_access_page);
12506                 vmx->nested.apic_access_page = NULL;
12507         }
12508         if (vmx->nested.virtual_apic_page) {
12509                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
12510                 vmx->nested.virtual_apic_page = NULL;
12511         }
12512         if (vmx->nested.pi_desc_page) {
12513                 kunmap(vmx->nested.pi_desc_page);
12514                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
12515                 vmx->nested.pi_desc_page = NULL;
12516                 vmx->nested.pi_desc = NULL;
12517         }
12518
12519         /*
12520          * We are now running in L2, mmu_notifier will force to reload the
12521          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
12522          */
12523         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
12524
12525         if (enable_shadow_vmcs && exit_reason != -1)
12526                 vmx->nested.sync_shadow_vmcs = true;
12527
12528         /* in case we halted in L2 */
12529         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
12530
12531         if (likely(!vmx->fail)) {
12532                 /*
12533                  * TODO: SDM says that with acknowledge interrupt on
12534                  * exit, bit 31 of the VM-exit interrupt information
12535                  * (valid interrupt) is always set to 1 on
12536                  * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
12537                  * need kvm_cpu_has_interrupt().  See the commit
12538                  * message for details.
12539                  */
12540                 if (nested_exit_intr_ack_set(vcpu) &&
12541                     exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
12542                     kvm_cpu_has_interrupt(vcpu)) {
12543                         int irq = kvm_cpu_get_interrupt(vcpu);
12544                         WARN_ON(irq < 0);
12545                         vmcs12->vm_exit_intr_info = irq |
12546                                 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
12547                 }
12548
12549                 if (exit_reason != -1)
12550                         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
12551                                                        vmcs12->exit_qualification,
12552                                                        vmcs12->idt_vectoring_info_field,
12553                                                        vmcs12->vm_exit_intr_info,
12554                                                        vmcs12->vm_exit_intr_error_code,
12555                                                        KVM_ISA_VMX);
12556
12557                 load_vmcs12_host_state(vcpu, vmcs12);
12558
12559                 return;
12560         }
12561
12562         /*
12563          * After an early L2 VM-entry failure, we're now back
12564          * in L1 which thinks it just finished a VMLAUNCH or
12565          * VMRESUME instruction, so we need to set the failure
12566          * flag and the VM-instruction error field of the VMCS
12567          * accordingly.
12568          */
12569         nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
12570
12571         load_vmcs12_mmu_host_state(vcpu, vmcs12);
12572
12573         /*
12574          * The emulated instruction was already skipped in
12575          * nested_vmx_run, but the updated RIP was never
12576          * written back to the vmcs01.
12577          */
12578         skip_emulated_instruction(vcpu);
12579         vmx->fail = 0;
12580 }
12581
12582 /*
12583  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
12584  */
12585 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
12586 {
12587         if (is_guest_mode(vcpu)) {
12588                 to_vmx(vcpu)->nested.nested_run_pending = 0;
12589                 nested_vmx_vmexit(vcpu, -1, 0, 0);
12590         }
12591         free_nested(to_vmx(vcpu));
12592 }
12593
12594 /*
12595  * L1's failure to enter L2 is a subset of a normal exit, as explained in
12596  * 23.7 "VM-entry failures during or after loading guest state" (this also
12597  * lists the acceptable exit-reason and exit-qualification parameters).
12598  * It should only be called before L2 actually succeeded to run, and when
12599  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
12600  */
12601 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
12602                         struct vmcs12 *vmcs12,
12603                         u32 reason, unsigned long qualification)
12604 {
12605         load_vmcs12_host_state(vcpu, vmcs12);
12606         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
12607         vmcs12->exit_qualification = qualification;
12608         nested_vmx_succeed(vcpu);
12609         if (enable_shadow_vmcs)
12610                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
12611 }
12612
12613 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
12614                                struct x86_instruction_info *info,
12615                                enum x86_intercept_stage stage)
12616 {
12617         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12618         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
12619
12620         /*
12621          * RDPID causes #UD if disabled through secondary execution controls.
12622          * Because it is marked as EmulateOnUD, we need to intercept it here.
12623          */
12624         if (info->intercept == x86_intercept_rdtscp &&
12625             !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
12626                 ctxt->exception.vector = UD_VECTOR;
12627                 ctxt->exception.error_code_valid = false;
12628                 return X86EMUL_PROPAGATE_FAULT;
12629         }
12630
12631         /* TODO: check more intercepts... */
12632         return X86EMUL_CONTINUE;
12633 }
12634
12635 #ifdef CONFIG_X86_64
12636 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
12637 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
12638                                   u64 divisor, u64 *result)
12639 {
12640         u64 low = a << shift, high = a >> (64 - shift);
12641
12642         /* To avoid the overflow on divq */
12643         if (high >= divisor)
12644                 return 1;
12645
12646         /* Low hold the result, high hold rem which is discarded */
12647         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
12648             "rm" (divisor), "0" (low), "1" (high));
12649         *result = low;
12650
12651         return 0;
12652 }
12653
12654 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
12655 {
12656         struct vcpu_vmx *vmx;
12657         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
12658
12659         if (kvm_mwait_in_guest(vcpu->kvm))
12660                 return -EOPNOTSUPP;
12661
12662         vmx = to_vmx(vcpu);
12663         tscl = rdtsc();
12664         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
12665         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
12666         lapic_timer_advance_cycles = nsec_to_cycles(vcpu, lapic_timer_advance_ns);
12667
12668         if (delta_tsc > lapic_timer_advance_cycles)
12669                 delta_tsc -= lapic_timer_advance_cycles;
12670         else
12671                 delta_tsc = 0;
12672
12673         /* Convert to host delta tsc if tsc scaling is enabled */
12674         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
12675                         u64_shl_div_u64(delta_tsc,
12676                                 kvm_tsc_scaling_ratio_frac_bits,
12677                                 vcpu->arch.tsc_scaling_ratio,
12678                                 &delta_tsc))
12679                 return -ERANGE;
12680
12681         /*
12682          * If the delta tsc can't fit in the 32 bit after the multi shift,
12683          * we can't use the preemption timer.
12684          * It's possible that it fits on later vmentries, but checking
12685          * on every vmentry is costly so we just use an hrtimer.
12686          */
12687         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
12688                 return -ERANGE;
12689
12690         vmx->hv_deadline_tsc = tscl + delta_tsc;
12691         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
12692                         PIN_BASED_VMX_PREEMPTION_TIMER);
12693
12694         return delta_tsc == 0;
12695 }
12696
12697 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
12698 {
12699         struct vcpu_vmx *vmx = to_vmx(vcpu);
12700         vmx->hv_deadline_tsc = -1;
12701         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
12702                         PIN_BASED_VMX_PREEMPTION_TIMER);
12703 }
12704 #endif
12705
12706 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
12707 {
12708         if (!kvm_pause_in_guest(vcpu->kvm))
12709                 shrink_ple_window(vcpu);
12710 }
12711
12712 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
12713                                      struct kvm_memory_slot *slot)
12714 {
12715         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
12716         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
12717 }
12718
12719 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
12720                                        struct kvm_memory_slot *slot)
12721 {
12722         kvm_mmu_slot_set_dirty(kvm, slot);
12723 }
12724
12725 static void vmx_flush_log_dirty(struct kvm *kvm)
12726 {
12727         kvm_flush_pml_buffers(kvm);
12728 }
12729
12730 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
12731 {
12732         struct vmcs12 *vmcs12;
12733         struct vcpu_vmx *vmx = to_vmx(vcpu);
12734         gpa_t gpa;
12735         struct page *page = NULL;
12736         u64 *pml_address;
12737
12738         if (is_guest_mode(vcpu)) {
12739                 WARN_ON_ONCE(vmx->nested.pml_full);
12740
12741                 /*
12742                  * Check if PML is enabled for the nested guest.
12743                  * Whether eptp bit 6 is set is already checked
12744                  * as part of A/D emulation.
12745                  */
12746                 vmcs12 = get_vmcs12(vcpu);
12747                 if (!nested_cpu_has_pml(vmcs12))
12748                         return 0;
12749
12750                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
12751                         vmx->nested.pml_full = true;
12752                         return 1;
12753                 }
12754
12755                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
12756
12757                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
12758                 if (is_error_page(page))
12759                         return 0;
12760
12761                 pml_address = kmap(page);
12762                 pml_address[vmcs12->guest_pml_index--] = gpa;
12763                 kunmap(page);
12764                 kvm_release_page_clean(page);
12765         }
12766
12767         return 0;
12768 }
12769
12770 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
12771                                            struct kvm_memory_slot *memslot,
12772                                            gfn_t offset, unsigned long mask)
12773 {
12774         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
12775 }
12776
12777 static void __pi_post_block(struct kvm_vcpu *vcpu)
12778 {
12779         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12780         struct pi_desc old, new;
12781         unsigned int dest;
12782
12783         do {
12784                 old.control = new.control = pi_desc->control;
12785                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
12786                      "Wakeup handler not enabled while the VCPU is blocked\n");
12787
12788                 dest = cpu_physical_id(vcpu->cpu);
12789
12790                 if (x2apic_enabled())
12791                         new.ndst = dest;
12792                 else
12793                         new.ndst = (dest << 8) & 0xFF00;
12794
12795                 /* set 'NV' to 'notification vector' */
12796                 new.nv = POSTED_INTR_VECTOR;
12797         } while (cmpxchg64(&pi_desc->control, old.control,
12798                            new.control) != old.control);
12799
12800         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
12801                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12802                 list_del(&vcpu->blocked_vcpu_list);
12803                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12804                 vcpu->pre_pcpu = -1;
12805         }
12806 }
12807
12808 /*
12809  * This routine does the following things for vCPU which is going
12810  * to be blocked if VT-d PI is enabled.
12811  * - Store the vCPU to the wakeup list, so when interrupts happen
12812  *   we can find the right vCPU to wake up.
12813  * - Change the Posted-interrupt descriptor as below:
12814  *      'NDST' <-- vcpu->pre_pcpu
12815  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
12816  * - If 'ON' is set during this process, which means at least one
12817  *   interrupt is posted for this vCPU, we cannot block it, in
12818  *   this case, return 1, otherwise, return 0.
12819  *
12820  */
12821 static int pi_pre_block(struct kvm_vcpu *vcpu)
12822 {
12823         unsigned int dest;
12824         struct pi_desc old, new;
12825         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12826
12827         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
12828                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
12829                 !kvm_vcpu_apicv_active(vcpu))
12830                 return 0;
12831
12832         WARN_ON(irqs_disabled());
12833         local_irq_disable();
12834         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
12835                 vcpu->pre_pcpu = vcpu->cpu;
12836                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12837                 list_add_tail(&vcpu->blocked_vcpu_list,
12838                               &per_cpu(blocked_vcpu_on_cpu,
12839                                        vcpu->pre_pcpu));
12840                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12841         }
12842
12843         do {
12844                 old.control = new.control = pi_desc->control;
12845
12846                 WARN((pi_desc->sn == 1),
12847                      "Warning: SN field of posted-interrupts "
12848                      "is set before blocking\n");
12849
12850                 /*
12851                  * Since vCPU can be preempted during this process,
12852                  * vcpu->cpu could be different with pre_pcpu, we
12853                  * need to set pre_pcpu as the destination of wakeup
12854                  * notification event, then we can find the right vCPU
12855                  * to wakeup in wakeup handler if interrupts happen
12856                  * when the vCPU is in blocked state.
12857                  */
12858                 dest = cpu_physical_id(vcpu->pre_pcpu);
12859
12860                 if (x2apic_enabled())
12861                         new.ndst = dest;
12862                 else
12863                         new.ndst = (dest << 8) & 0xFF00;
12864
12865                 /* set 'NV' to 'wakeup vector' */
12866                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
12867         } while (cmpxchg64(&pi_desc->control, old.control,
12868                            new.control) != old.control);
12869
12870         /* We should not block the vCPU if an interrupt is posted for it.  */
12871         if (pi_test_on(pi_desc) == 1)
12872                 __pi_post_block(vcpu);
12873
12874         local_irq_enable();
12875         return (vcpu->pre_pcpu == -1);
12876 }
12877
12878 static int vmx_pre_block(struct kvm_vcpu *vcpu)
12879 {
12880         if (pi_pre_block(vcpu))
12881                 return 1;
12882
12883         if (kvm_lapic_hv_timer_in_use(vcpu))
12884                 kvm_lapic_switch_to_sw_timer(vcpu);
12885
12886         return 0;
12887 }
12888
12889 static void pi_post_block(struct kvm_vcpu *vcpu)
12890 {
12891         if (vcpu->pre_pcpu == -1)
12892                 return;
12893
12894         WARN_ON(irqs_disabled());
12895         local_irq_disable();
12896         __pi_post_block(vcpu);
12897         local_irq_enable();
12898 }
12899
12900 static void vmx_post_block(struct kvm_vcpu *vcpu)
12901 {
12902         if (kvm_x86_ops->set_hv_timer)
12903                 kvm_lapic_switch_to_hv_timer(vcpu);
12904
12905         pi_post_block(vcpu);
12906 }
12907
12908 /*
12909  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
12910  *
12911  * @kvm: kvm
12912  * @host_irq: host irq of the interrupt
12913  * @guest_irq: gsi of the interrupt
12914  * @set: set or unset PI
12915  * returns 0 on success, < 0 on failure
12916  */
12917 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
12918                               uint32_t guest_irq, bool set)
12919 {
12920         struct kvm_kernel_irq_routing_entry *e;
12921         struct kvm_irq_routing_table *irq_rt;
12922         struct kvm_lapic_irq irq;
12923         struct kvm_vcpu *vcpu;
12924         struct vcpu_data vcpu_info;
12925         int idx, ret = 0;
12926
12927         if (!kvm_arch_has_assigned_device(kvm) ||
12928                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
12929                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
12930                 return 0;
12931
12932         idx = srcu_read_lock(&kvm->irq_srcu);
12933         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
12934         if (guest_irq >= irq_rt->nr_rt_entries ||
12935             hlist_empty(&irq_rt->map[guest_irq])) {
12936                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
12937                              guest_irq, irq_rt->nr_rt_entries);
12938                 goto out;
12939         }
12940
12941         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
12942                 if (e->type != KVM_IRQ_ROUTING_MSI)
12943                         continue;
12944                 /*
12945                  * VT-d PI cannot support posting multicast/broadcast
12946                  * interrupts to a vCPU, we still use interrupt remapping
12947                  * for these kind of interrupts.
12948                  *
12949                  * For lowest-priority interrupts, we only support
12950                  * those with single CPU as the destination, e.g. user
12951                  * configures the interrupts via /proc/irq or uses
12952                  * irqbalance to make the interrupts single-CPU.
12953                  *
12954                  * We will support full lowest-priority interrupt later.
12955                  */
12956
12957                 kvm_set_msi_irq(kvm, e, &irq);
12958                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
12959                         /*
12960                          * Make sure the IRTE is in remapped mode if
12961                          * we don't handle it in posted mode.
12962                          */
12963                         ret = irq_set_vcpu_affinity(host_irq, NULL);
12964                         if (ret < 0) {
12965                                 printk(KERN_INFO
12966                                    "failed to back to remapped mode, irq: %u\n",
12967                                    host_irq);
12968                                 goto out;
12969                         }
12970
12971                         continue;
12972                 }
12973
12974                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
12975                 vcpu_info.vector = irq.vector;
12976
12977                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
12978                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
12979
12980                 if (set)
12981                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
12982                 else
12983                         ret = irq_set_vcpu_affinity(host_irq, NULL);
12984
12985                 if (ret < 0) {
12986                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
12987                                         __func__);
12988                         goto out;
12989                 }
12990         }
12991
12992         ret = 0;
12993 out:
12994         srcu_read_unlock(&kvm->irq_srcu, idx);
12995         return ret;
12996 }
12997
12998 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
12999 {
13000         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
13001                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
13002                         FEATURE_CONTROL_LMCE;
13003         else
13004                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
13005                         ~FEATURE_CONTROL_LMCE;
13006 }
13007
13008 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
13009 {
13010         /* we need a nested vmexit to enter SMM, postpone if run is pending */
13011         if (to_vmx(vcpu)->nested.nested_run_pending)
13012                 return 0;
13013         return 1;
13014 }
13015
13016 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
13017 {
13018         struct vcpu_vmx *vmx = to_vmx(vcpu);
13019
13020         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
13021         if (vmx->nested.smm.guest_mode)
13022                 nested_vmx_vmexit(vcpu, -1, 0, 0);
13023
13024         vmx->nested.smm.vmxon = vmx->nested.vmxon;
13025         vmx->nested.vmxon = false;
13026         vmx_clear_hlt(vcpu);
13027         return 0;
13028 }
13029
13030 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
13031 {
13032         struct vcpu_vmx *vmx = to_vmx(vcpu);
13033         int ret;
13034
13035         if (vmx->nested.smm.vmxon) {
13036                 vmx->nested.vmxon = true;
13037                 vmx->nested.smm.vmxon = false;
13038         }
13039
13040         if (vmx->nested.smm.guest_mode) {
13041                 vcpu->arch.hflags &= ~HF_SMM_MASK;
13042                 ret = enter_vmx_non_root_mode(vcpu);
13043                 vcpu->arch.hflags |= HF_SMM_MASK;
13044                 if (ret)
13045                         return ret;
13046
13047                 vmx->nested.smm.guest_mode = false;
13048         }
13049         return 0;
13050 }
13051
13052 static int enable_smi_window(struct kvm_vcpu *vcpu)
13053 {
13054         return 0;
13055 }
13056
13057 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
13058         .cpu_has_kvm_support = cpu_has_kvm_support,
13059         .disabled_by_bios = vmx_disabled_by_bios,
13060         .hardware_setup = hardware_setup,
13061         .hardware_unsetup = hardware_unsetup,
13062         .check_processor_compatibility = vmx_check_processor_compat,
13063         .hardware_enable = hardware_enable,
13064         .hardware_disable = hardware_disable,
13065         .cpu_has_accelerated_tpr = report_flexpriority,
13066         .has_emulated_msr = vmx_has_emulated_msr,
13067
13068         .vm_init = vmx_vm_init,
13069         .vm_alloc = vmx_vm_alloc,
13070         .vm_free = vmx_vm_free,
13071
13072         .vcpu_create = vmx_create_vcpu,
13073         .vcpu_free = vmx_free_vcpu,
13074         .vcpu_reset = vmx_vcpu_reset,
13075
13076         .prepare_guest_switch = vmx_save_host_state,
13077         .vcpu_load = vmx_vcpu_load,
13078         .vcpu_put = vmx_vcpu_put,
13079
13080         .update_bp_intercept = update_exception_bitmap,
13081         .get_msr_feature = vmx_get_msr_feature,
13082         .get_msr = vmx_get_msr,
13083         .set_msr = vmx_set_msr,
13084         .get_segment_base = vmx_get_segment_base,
13085         .get_segment = vmx_get_segment,
13086         .set_segment = vmx_set_segment,
13087         .get_cpl = vmx_get_cpl,
13088         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
13089         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
13090         .decache_cr3 = vmx_decache_cr3,
13091         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
13092         .set_cr0 = vmx_set_cr0,
13093         .set_cr3 = vmx_set_cr3,
13094         .set_cr4 = vmx_set_cr4,
13095         .set_efer = vmx_set_efer,
13096         .get_idt = vmx_get_idt,
13097         .set_idt = vmx_set_idt,
13098         .get_gdt = vmx_get_gdt,
13099         .set_gdt = vmx_set_gdt,
13100         .get_dr6 = vmx_get_dr6,
13101         .set_dr6 = vmx_set_dr6,
13102         .set_dr7 = vmx_set_dr7,
13103         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
13104         .cache_reg = vmx_cache_reg,
13105         .get_rflags = vmx_get_rflags,
13106         .set_rflags = vmx_set_rflags,
13107
13108         .tlb_flush = vmx_flush_tlb,
13109
13110         .run = vmx_vcpu_run,
13111         .handle_exit = vmx_handle_exit,
13112         .skip_emulated_instruction = skip_emulated_instruction,
13113         .set_interrupt_shadow = vmx_set_interrupt_shadow,
13114         .get_interrupt_shadow = vmx_get_interrupt_shadow,
13115         .patch_hypercall = vmx_patch_hypercall,
13116         .set_irq = vmx_inject_irq,
13117         .set_nmi = vmx_inject_nmi,
13118         .queue_exception = vmx_queue_exception,
13119         .cancel_injection = vmx_cancel_injection,
13120         .interrupt_allowed = vmx_interrupt_allowed,
13121         .nmi_allowed = vmx_nmi_allowed,
13122         .get_nmi_mask = vmx_get_nmi_mask,
13123         .set_nmi_mask = vmx_set_nmi_mask,
13124         .enable_nmi_window = enable_nmi_window,
13125         .enable_irq_window = enable_irq_window,
13126         .update_cr8_intercept = update_cr8_intercept,
13127         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
13128         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
13129         .get_enable_apicv = vmx_get_enable_apicv,
13130         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
13131         .load_eoi_exitmap = vmx_load_eoi_exitmap,
13132         .apicv_post_state_restore = vmx_apicv_post_state_restore,
13133         .hwapic_irr_update = vmx_hwapic_irr_update,
13134         .hwapic_isr_update = vmx_hwapic_isr_update,
13135         .sync_pir_to_irr = vmx_sync_pir_to_irr,
13136         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
13137
13138         .set_tss_addr = vmx_set_tss_addr,
13139         .set_identity_map_addr = vmx_set_identity_map_addr,
13140         .get_tdp_level = get_ept_level,
13141         .get_mt_mask = vmx_get_mt_mask,
13142
13143         .get_exit_info = vmx_get_exit_info,
13144
13145         .get_lpage_level = vmx_get_lpage_level,
13146
13147         .cpuid_update = vmx_cpuid_update,
13148
13149         .rdtscp_supported = vmx_rdtscp_supported,
13150         .invpcid_supported = vmx_invpcid_supported,
13151
13152         .set_supported_cpuid = vmx_set_supported_cpuid,
13153
13154         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
13155
13156         .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
13157         .write_tsc_offset = vmx_write_tsc_offset,
13158
13159         .set_tdp_cr3 = vmx_set_cr3,
13160
13161         .check_intercept = vmx_check_intercept,
13162         .handle_external_intr = vmx_handle_external_intr,
13163         .mpx_supported = vmx_mpx_supported,
13164         .xsaves_supported = vmx_xsaves_supported,
13165         .umip_emulated = vmx_umip_emulated,
13166
13167         .check_nested_events = vmx_check_nested_events,
13168
13169         .sched_in = vmx_sched_in,
13170
13171         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
13172         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
13173         .flush_log_dirty = vmx_flush_log_dirty,
13174         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
13175         .write_log_dirty = vmx_write_pml_buffer,
13176
13177         .pre_block = vmx_pre_block,
13178         .post_block = vmx_post_block,
13179
13180         .pmu_ops = &intel_pmu_ops,
13181
13182         .update_pi_irte = vmx_update_pi_irte,
13183
13184 #ifdef CONFIG_X86_64
13185         .set_hv_timer = vmx_set_hv_timer,
13186         .cancel_hv_timer = vmx_cancel_hv_timer,
13187 #endif
13188
13189         .setup_mce = vmx_setup_mce,
13190
13191         .smi_allowed = vmx_smi_allowed,
13192         .pre_enter_smm = vmx_pre_enter_smm,
13193         .pre_leave_smm = vmx_pre_leave_smm,
13194         .enable_smi_window = enable_smi_window,
13195 };
13196
13197 static int __init vmx_setup_l1d_flush(void)
13198 {
13199         struct page *page;
13200
13201         if (vmentry_l1d_flush == VMENTER_L1D_FLUSH_NEVER ||
13202             !boot_cpu_has_bug(X86_BUG_L1TF))
13203                 return 0;
13204
13205         if (!boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
13206                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
13207                 if (!page)
13208                         return -ENOMEM;
13209                 vmx_l1d_flush_pages = page_address(page);
13210         }
13211
13212         static_branch_enable(&vmx_l1d_should_flush);
13213         return 0;
13214 }
13215
13216 static void vmx_free_l1d_flush_pages(void)
13217 {
13218         if (vmx_l1d_flush_pages) {
13219                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
13220                 vmx_l1d_flush_pages = NULL;
13221         }
13222 }
13223
13224 static int __init vmx_init(void)
13225 {
13226         int r;
13227
13228 #if IS_ENABLED(CONFIG_HYPERV)
13229         /*
13230          * Enlightened VMCS usage should be recommended and the host needs
13231          * to support eVMCS v1 or above. We can also disable eVMCS support
13232          * with module parameter.
13233          */
13234         if (enlightened_vmcs &&
13235             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
13236             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
13237             KVM_EVMCS_VERSION) {
13238                 int cpu;
13239
13240                 /* Check that we have assist pages on all online CPUs */
13241                 for_each_online_cpu(cpu) {
13242                         if (!hv_get_vp_assist_page(cpu)) {
13243                                 enlightened_vmcs = false;
13244                                 break;
13245                         }
13246                 }
13247
13248                 if (enlightened_vmcs) {
13249                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
13250                         static_branch_enable(&enable_evmcs);
13251                 }
13252         } else {
13253                 enlightened_vmcs = false;
13254         }
13255 #endif
13256
13257         r = vmx_setup_l1d_flush();
13258         if (r)
13259                 return r;
13260
13261         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
13262                      __alignof__(struct vcpu_vmx), THIS_MODULE);
13263         if (r) {
13264                 vmx_free_l1d_flush_pages();
13265                 return r;
13266         }
13267
13268 #ifdef CONFIG_KEXEC_CORE
13269         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
13270                            crash_vmclear_local_loaded_vmcss);
13271 #endif
13272         vmx_check_vmcs12_offsets();
13273
13274         return 0;
13275 }
13276
13277 static void __exit vmx_exit(void)
13278 {
13279 #ifdef CONFIG_KEXEC_CORE
13280         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
13281         synchronize_rcu();
13282 #endif
13283
13284         kvm_exit();
13285
13286 #if IS_ENABLED(CONFIG_HYPERV)
13287         if (static_branch_unlikely(&enable_evmcs)) {
13288                 int cpu;
13289                 struct hv_vp_assist_page *vp_ap;
13290                 /*
13291                  * Reset everything to support using non-enlightened VMCS
13292                  * access later (e.g. when we reload the module with
13293                  * enlightened_vmcs=0)
13294                  */
13295                 for_each_online_cpu(cpu) {
13296                         vp_ap = hv_get_vp_assist_page(cpu);
13297
13298                         if (!vp_ap)
13299                                 continue;
13300
13301                         vp_ap->current_nested_vmcs = 0;
13302                         vp_ap->enlighten_vmentry = 0;
13303                 }
13304
13305                 static_branch_disable(&enable_evmcs);
13306         }
13307 #endif
13308         vmx_free_l1d_flush_pages();
13309 }
13310
13311 module_init(vmx_init)
13312 module_exit(vmx_exit)