2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include <linux/nospec.h>
38 #include "kvm_cache_regs.h"
46 #include <asm/virtext.h>
48 #include <asm/fpu/internal.h>
49 #include <asm/perf_event.h>
50 #include <asm/debugreg.h>
51 #include <asm/kexec.h>
53 #include <asm/irq_remapping.h>
54 #include <asm/mmu_context.h>
55 #include <asm/spec-ctrl.h>
56 #include <asm/mshyperv.h>
60 #include "vmx_evmcs.h"
62 #define __ex(x) __kvm_handle_fault_on_reboot(x)
63 #define __ex_clear(x, reg) \
64 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
66 MODULE_AUTHOR("Qumranet");
67 MODULE_LICENSE("GPL");
69 static const struct x86_cpu_id vmx_cpu_id[] = {
70 X86_FEATURE_MATCH(X86_FEATURE_VMX),
73 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
75 static bool __read_mostly enable_vpid = 1;
76 module_param_named(vpid, enable_vpid, bool, 0444);
78 static bool __read_mostly enable_vnmi = 1;
79 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
81 static bool __read_mostly flexpriority_enabled = 1;
82 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
84 static bool __read_mostly enable_ept = 1;
85 module_param_named(ept, enable_ept, bool, S_IRUGO);
87 static bool __read_mostly enable_unrestricted_guest = 1;
88 module_param_named(unrestricted_guest,
89 enable_unrestricted_guest, bool, S_IRUGO);
91 static bool __read_mostly enable_ept_ad_bits = 1;
92 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
94 static bool __read_mostly emulate_invalid_guest_state = true;
95 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
97 static bool __read_mostly fasteoi = 1;
98 module_param(fasteoi, bool, S_IRUGO);
100 static bool __read_mostly enable_apicv = 1;
101 module_param(enable_apicv, bool, S_IRUGO);
103 static bool __read_mostly enable_shadow_vmcs = 1;
104 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
106 * If nested=1, nested virtualization is supported, i.e., guests may use
107 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
108 * use VMX instructions.
110 static bool __read_mostly nested = 0;
111 module_param(nested, bool, S_IRUGO);
113 static u64 __read_mostly host_xss;
115 static bool __read_mostly enable_pml = 1;
116 module_param_named(pml, enable_pml, bool, S_IRUGO);
120 #define MSR_TYPE_RW 3
122 #define MSR_BITMAP_MODE_X2APIC 1
123 #define MSR_BITMAP_MODE_X2APIC_APICV 2
124 #define MSR_BITMAP_MODE_LM 4
126 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
128 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
129 static int __read_mostly cpu_preemption_timer_multi;
130 static bool __read_mostly enable_preemption_timer = 1;
132 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
135 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
136 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
137 #define KVM_VM_CR0_ALWAYS_ON \
138 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
139 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
140 #define KVM_CR4_GUEST_OWNED_BITS \
141 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
142 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
144 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
145 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
146 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
148 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
150 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
153 * Hyper-V requires all of these, so mark them as supported even though
154 * they are just treated the same as all-context.
156 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
157 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
158 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
159 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
160 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
163 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
164 * ple_gap: upper bound on the amount of time between two successive
165 * executions of PAUSE in a loop. Also indicate if ple enabled.
166 * According to test, this time is usually smaller than 128 cycles.
167 * ple_window: upper bound on the amount of time a guest is allowed to execute
168 * in a PAUSE loop. Tests indicate that most spinlocks are held for
169 * less than 2^12 cycles
170 * Time is measured based on a counter that runs at the same rate as the TSC,
171 * refer SDM volume 3b section 21.6.13 & 22.1.3.
173 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
175 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
176 module_param(ple_window, uint, 0444);
178 /* Default doubles per-vcpu window every exit. */
179 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
180 module_param(ple_window_grow, uint, 0444);
182 /* Default resets per-vcpu window every exit to ple_window. */
183 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
184 module_param(ple_window_shrink, uint, 0444);
186 /* Default is to compute the maximum so we can never overflow. */
187 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
188 module_param(ple_window_max, uint, 0444);
190 extern const ulong vmx_return;
192 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
193 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
194 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
196 /* Storage for pre module init parameter parsing */
197 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
199 static const struct {
202 } vmentry_l1d_param[] = {
203 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
204 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
205 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
206 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
207 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
208 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
211 #define L1D_CACHE_ORDER 4
212 static void *vmx_l1d_flush_pages;
214 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
220 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
224 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
227 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
228 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
229 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
234 /* If set to auto use the default l1tf mitigation method */
235 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
236 switch (l1tf_mitigation) {
237 case L1TF_MITIGATION_OFF:
238 l1tf = VMENTER_L1D_FLUSH_NEVER;
240 case L1TF_MITIGATION_FLUSH_NOWARN:
241 case L1TF_MITIGATION_FLUSH:
242 case L1TF_MITIGATION_FLUSH_NOSMT:
243 l1tf = VMENTER_L1D_FLUSH_COND;
245 case L1TF_MITIGATION_FULL:
246 case L1TF_MITIGATION_FULL_FORCE:
247 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
250 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
251 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
254 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
255 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
256 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
259 vmx_l1d_flush_pages = page_address(page);
262 * Initialize each page with a different pattern in
263 * order to protect against KSM in the nested
264 * virtualization case.
266 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
267 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
272 l1tf_vmx_mitigation = l1tf;
274 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
275 static_branch_enable(&vmx_l1d_should_flush);
277 static_branch_disable(&vmx_l1d_should_flush);
279 if (l1tf == VMENTER_L1D_FLUSH_COND)
280 static_branch_enable(&vmx_l1d_flush_cond);
282 static_branch_disable(&vmx_l1d_flush_cond);
286 static int vmentry_l1d_flush_parse(const char *s)
291 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
292 if (vmentry_l1d_param[i].for_parse &&
293 sysfs_streq(s, vmentry_l1d_param[i].option))
300 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
304 l1tf = vmentry_l1d_flush_parse(s);
308 if (!boot_cpu_has(X86_BUG_L1TF))
312 * Has vmx_init() run already? If not then this is the pre init
313 * parameter parsing. In that case just store the value and let
314 * vmx_init() do the proper setup after enable_ept has been
317 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
318 vmentry_l1d_flush_param = l1tf;
322 mutex_lock(&vmx_l1d_flush_mutex);
323 ret = vmx_setup_l1d_flush(l1tf);
324 mutex_unlock(&vmx_l1d_flush_mutex);
328 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
330 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
331 return sprintf(s, "???\n");
333 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
336 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
337 .set = vmentry_l1d_flush_set,
338 .get = vmentry_l1d_flush_get,
340 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
342 enum ept_pointers_status {
343 EPT_POINTERS_CHECK = 0,
344 EPT_POINTERS_MATCH = 1,
345 EPT_POINTERS_MISMATCH = 2
351 unsigned int tss_addr;
352 bool ept_identity_pagetable_done;
353 gpa_t ept_identity_map_addr;
355 enum ept_pointers_status ept_pointers_match;
356 spinlock_t ept_pointer_lock;
359 #define NR_AUTOLOAD_MSRS 8
373 * vmcs_host_state tracks registers that are loaded from the VMCS on VMEXIT
374 * and whose values change infrequently, but are not constant. I.e. this is
375 * used as a write-through cache of the corresponding VMCS fields.
377 struct vmcs_host_state {
378 unsigned long cr3; /* May not match real cr3 */
379 unsigned long cr4; /* May not match real cr4 */
380 unsigned long gs_base;
381 unsigned long fs_base;
383 u16 fs_sel, gs_sel, ldt_sel;
390 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
391 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
392 * loaded on this CPU (so we can clear them if the CPU goes down).
396 struct vmcs *shadow_vmcs;
399 bool nmi_known_unmasked;
400 /* Support for vnmi-less CPUs */
401 int soft_vnmi_blocked;
403 s64 vnmi_blocked_time;
404 unsigned long *msr_bitmap;
405 struct list_head loaded_vmcss_on_cpu_link;
406 struct vmcs_host_state host_state;
409 struct shared_msr_entry {
416 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
417 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
418 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
419 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
420 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
421 * More than one of these structures may exist, if L1 runs multiple L2 guests.
422 * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
423 * underlying hardware which will be used to run L2.
424 * This structure is packed to ensure that its layout is identical across
425 * machines (necessary for live migration).
427 * IMPORTANT: Changing the layout of existing fields in this structure
428 * will break save/restore compatibility with older kvm releases. When
429 * adding new fields, either use space in the reserved padding* arrays
430 * or add the new fields to the end of the structure.
432 typedef u64 natural_width;
433 struct __packed vmcs12 {
434 /* According to the Intel spec, a VMCS region must start with the
435 * following two fields. Then follow implementation-specific data.
440 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
441 u32 padding[7]; /* room for future expansion */
446 u64 vm_exit_msr_store_addr;
447 u64 vm_exit_msr_load_addr;
448 u64 vm_entry_msr_load_addr;
450 u64 virtual_apic_page_addr;
451 u64 apic_access_addr;
452 u64 posted_intr_desc_addr;
454 u64 eoi_exit_bitmap0;
455 u64 eoi_exit_bitmap1;
456 u64 eoi_exit_bitmap2;
457 u64 eoi_exit_bitmap3;
459 u64 guest_physical_address;
460 u64 vmcs_link_pointer;
461 u64 guest_ia32_debugctl;
464 u64 guest_ia32_perf_global_ctrl;
472 u64 host_ia32_perf_global_ctrl;
475 u64 vm_function_control;
476 u64 eptp_list_address;
478 u64 padding64[3]; /* room for future expansion */
480 * To allow migration of L1 (complete with its L2 guests) between
481 * machines of different natural widths (32 or 64 bit), we cannot have
482 * unsigned long fields with no explict size. We use u64 (aliased
483 * natural_width) instead. Luckily, x86 is little-endian.
485 natural_width cr0_guest_host_mask;
486 natural_width cr4_guest_host_mask;
487 natural_width cr0_read_shadow;
488 natural_width cr4_read_shadow;
489 natural_width cr3_target_value0;
490 natural_width cr3_target_value1;
491 natural_width cr3_target_value2;
492 natural_width cr3_target_value3;
493 natural_width exit_qualification;
494 natural_width guest_linear_address;
495 natural_width guest_cr0;
496 natural_width guest_cr3;
497 natural_width guest_cr4;
498 natural_width guest_es_base;
499 natural_width guest_cs_base;
500 natural_width guest_ss_base;
501 natural_width guest_ds_base;
502 natural_width guest_fs_base;
503 natural_width guest_gs_base;
504 natural_width guest_ldtr_base;
505 natural_width guest_tr_base;
506 natural_width guest_gdtr_base;
507 natural_width guest_idtr_base;
508 natural_width guest_dr7;
509 natural_width guest_rsp;
510 natural_width guest_rip;
511 natural_width guest_rflags;
512 natural_width guest_pending_dbg_exceptions;
513 natural_width guest_sysenter_esp;
514 natural_width guest_sysenter_eip;
515 natural_width host_cr0;
516 natural_width host_cr3;
517 natural_width host_cr4;
518 natural_width host_fs_base;
519 natural_width host_gs_base;
520 natural_width host_tr_base;
521 natural_width host_gdtr_base;
522 natural_width host_idtr_base;
523 natural_width host_ia32_sysenter_esp;
524 natural_width host_ia32_sysenter_eip;
525 natural_width host_rsp;
526 natural_width host_rip;
527 natural_width paddingl[8]; /* room for future expansion */
528 u32 pin_based_vm_exec_control;
529 u32 cpu_based_vm_exec_control;
530 u32 exception_bitmap;
531 u32 page_fault_error_code_mask;
532 u32 page_fault_error_code_match;
533 u32 cr3_target_count;
534 u32 vm_exit_controls;
535 u32 vm_exit_msr_store_count;
536 u32 vm_exit_msr_load_count;
537 u32 vm_entry_controls;
538 u32 vm_entry_msr_load_count;
539 u32 vm_entry_intr_info_field;
540 u32 vm_entry_exception_error_code;
541 u32 vm_entry_instruction_len;
543 u32 secondary_vm_exec_control;
544 u32 vm_instruction_error;
546 u32 vm_exit_intr_info;
547 u32 vm_exit_intr_error_code;
548 u32 idt_vectoring_info_field;
549 u32 idt_vectoring_error_code;
550 u32 vm_exit_instruction_len;
551 u32 vmx_instruction_info;
558 u32 guest_ldtr_limit;
560 u32 guest_gdtr_limit;
561 u32 guest_idtr_limit;
562 u32 guest_es_ar_bytes;
563 u32 guest_cs_ar_bytes;
564 u32 guest_ss_ar_bytes;
565 u32 guest_ds_ar_bytes;
566 u32 guest_fs_ar_bytes;
567 u32 guest_gs_ar_bytes;
568 u32 guest_ldtr_ar_bytes;
569 u32 guest_tr_ar_bytes;
570 u32 guest_interruptibility_info;
571 u32 guest_activity_state;
572 u32 guest_sysenter_cs;
573 u32 host_ia32_sysenter_cs;
574 u32 vmx_preemption_timer_value;
575 u32 padding32[7]; /* room for future expansion */
576 u16 virtual_processor_id;
578 u16 guest_es_selector;
579 u16 guest_cs_selector;
580 u16 guest_ss_selector;
581 u16 guest_ds_selector;
582 u16 guest_fs_selector;
583 u16 guest_gs_selector;
584 u16 guest_ldtr_selector;
585 u16 guest_tr_selector;
586 u16 guest_intr_status;
587 u16 host_es_selector;
588 u16 host_cs_selector;
589 u16 host_ss_selector;
590 u16 host_ds_selector;
591 u16 host_fs_selector;
592 u16 host_gs_selector;
593 u16 host_tr_selector;
598 * For save/restore compatibility, the vmcs12 field offsets must not change.
600 #define CHECK_OFFSET(field, loc) \
601 BUILD_BUG_ON_MSG(offsetof(struct vmcs12, field) != (loc), \
602 "Offset of " #field " in struct vmcs12 has changed.")
604 static inline void vmx_check_vmcs12_offsets(void) {
605 CHECK_OFFSET(hdr, 0);
606 CHECK_OFFSET(abort, 4);
607 CHECK_OFFSET(launch_state, 8);
608 CHECK_OFFSET(io_bitmap_a, 40);
609 CHECK_OFFSET(io_bitmap_b, 48);
610 CHECK_OFFSET(msr_bitmap, 56);
611 CHECK_OFFSET(vm_exit_msr_store_addr, 64);
612 CHECK_OFFSET(vm_exit_msr_load_addr, 72);
613 CHECK_OFFSET(vm_entry_msr_load_addr, 80);
614 CHECK_OFFSET(tsc_offset, 88);
615 CHECK_OFFSET(virtual_apic_page_addr, 96);
616 CHECK_OFFSET(apic_access_addr, 104);
617 CHECK_OFFSET(posted_intr_desc_addr, 112);
618 CHECK_OFFSET(ept_pointer, 120);
619 CHECK_OFFSET(eoi_exit_bitmap0, 128);
620 CHECK_OFFSET(eoi_exit_bitmap1, 136);
621 CHECK_OFFSET(eoi_exit_bitmap2, 144);
622 CHECK_OFFSET(eoi_exit_bitmap3, 152);
623 CHECK_OFFSET(xss_exit_bitmap, 160);
624 CHECK_OFFSET(guest_physical_address, 168);
625 CHECK_OFFSET(vmcs_link_pointer, 176);
626 CHECK_OFFSET(guest_ia32_debugctl, 184);
627 CHECK_OFFSET(guest_ia32_pat, 192);
628 CHECK_OFFSET(guest_ia32_efer, 200);
629 CHECK_OFFSET(guest_ia32_perf_global_ctrl, 208);
630 CHECK_OFFSET(guest_pdptr0, 216);
631 CHECK_OFFSET(guest_pdptr1, 224);
632 CHECK_OFFSET(guest_pdptr2, 232);
633 CHECK_OFFSET(guest_pdptr3, 240);
634 CHECK_OFFSET(guest_bndcfgs, 248);
635 CHECK_OFFSET(host_ia32_pat, 256);
636 CHECK_OFFSET(host_ia32_efer, 264);
637 CHECK_OFFSET(host_ia32_perf_global_ctrl, 272);
638 CHECK_OFFSET(vmread_bitmap, 280);
639 CHECK_OFFSET(vmwrite_bitmap, 288);
640 CHECK_OFFSET(vm_function_control, 296);
641 CHECK_OFFSET(eptp_list_address, 304);
642 CHECK_OFFSET(pml_address, 312);
643 CHECK_OFFSET(cr0_guest_host_mask, 344);
644 CHECK_OFFSET(cr4_guest_host_mask, 352);
645 CHECK_OFFSET(cr0_read_shadow, 360);
646 CHECK_OFFSET(cr4_read_shadow, 368);
647 CHECK_OFFSET(cr3_target_value0, 376);
648 CHECK_OFFSET(cr3_target_value1, 384);
649 CHECK_OFFSET(cr3_target_value2, 392);
650 CHECK_OFFSET(cr3_target_value3, 400);
651 CHECK_OFFSET(exit_qualification, 408);
652 CHECK_OFFSET(guest_linear_address, 416);
653 CHECK_OFFSET(guest_cr0, 424);
654 CHECK_OFFSET(guest_cr3, 432);
655 CHECK_OFFSET(guest_cr4, 440);
656 CHECK_OFFSET(guest_es_base, 448);
657 CHECK_OFFSET(guest_cs_base, 456);
658 CHECK_OFFSET(guest_ss_base, 464);
659 CHECK_OFFSET(guest_ds_base, 472);
660 CHECK_OFFSET(guest_fs_base, 480);
661 CHECK_OFFSET(guest_gs_base, 488);
662 CHECK_OFFSET(guest_ldtr_base, 496);
663 CHECK_OFFSET(guest_tr_base, 504);
664 CHECK_OFFSET(guest_gdtr_base, 512);
665 CHECK_OFFSET(guest_idtr_base, 520);
666 CHECK_OFFSET(guest_dr7, 528);
667 CHECK_OFFSET(guest_rsp, 536);
668 CHECK_OFFSET(guest_rip, 544);
669 CHECK_OFFSET(guest_rflags, 552);
670 CHECK_OFFSET(guest_pending_dbg_exceptions, 560);
671 CHECK_OFFSET(guest_sysenter_esp, 568);
672 CHECK_OFFSET(guest_sysenter_eip, 576);
673 CHECK_OFFSET(host_cr0, 584);
674 CHECK_OFFSET(host_cr3, 592);
675 CHECK_OFFSET(host_cr4, 600);
676 CHECK_OFFSET(host_fs_base, 608);
677 CHECK_OFFSET(host_gs_base, 616);
678 CHECK_OFFSET(host_tr_base, 624);
679 CHECK_OFFSET(host_gdtr_base, 632);
680 CHECK_OFFSET(host_idtr_base, 640);
681 CHECK_OFFSET(host_ia32_sysenter_esp, 648);
682 CHECK_OFFSET(host_ia32_sysenter_eip, 656);
683 CHECK_OFFSET(host_rsp, 664);
684 CHECK_OFFSET(host_rip, 672);
685 CHECK_OFFSET(pin_based_vm_exec_control, 744);
686 CHECK_OFFSET(cpu_based_vm_exec_control, 748);
687 CHECK_OFFSET(exception_bitmap, 752);
688 CHECK_OFFSET(page_fault_error_code_mask, 756);
689 CHECK_OFFSET(page_fault_error_code_match, 760);
690 CHECK_OFFSET(cr3_target_count, 764);
691 CHECK_OFFSET(vm_exit_controls, 768);
692 CHECK_OFFSET(vm_exit_msr_store_count, 772);
693 CHECK_OFFSET(vm_exit_msr_load_count, 776);
694 CHECK_OFFSET(vm_entry_controls, 780);
695 CHECK_OFFSET(vm_entry_msr_load_count, 784);
696 CHECK_OFFSET(vm_entry_intr_info_field, 788);
697 CHECK_OFFSET(vm_entry_exception_error_code, 792);
698 CHECK_OFFSET(vm_entry_instruction_len, 796);
699 CHECK_OFFSET(tpr_threshold, 800);
700 CHECK_OFFSET(secondary_vm_exec_control, 804);
701 CHECK_OFFSET(vm_instruction_error, 808);
702 CHECK_OFFSET(vm_exit_reason, 812);
703 CHECK_OFFSET(vm_exit_intr_info, 816);
704 CHECK_OFFSET(vm_exit_intr_error_code, 820);
705 CHECK_OFFSET(idt_vectoring_info_field, 824);
706 CHECK_OFFSET(idt_vectoring_error_code, 828);
707 CHECK_OFFSET(vm_exit_instruction_len, 832);
708 CHECK_OFFSET(vmx_instruction_info, 836);
709 CHECK_OFFSET(guest_es_limit, 840);
710 CHECK_OFFSET(guest_cs_limit, 844);
711 CHECK_OFFSET(guest_ss_limit, 848);
712 CHECK_OFFSET(guest_ds_limit, 852);
713 CHECK_OFFSET(guest_fs_limit, 856);
714 CHECK_OFFSET(guest_gs_limit, 860);
715 CHECK_OFFSET(guest_ldtr_limit, 864);
716 CHECK_OFFSET(guest_tr_limit, 868);
717 CHECK_OFFSET(guest_gdtr_limit, 872);
718 CHECK_OFFSET(guest_idtr_limit, 876);
719 CHECK_OFFSET(guest_es_ar_bytes, 880);
720 CHECK_OFFSET(guest_cs_ar_bytes, 884);
721 CHECK_OFFSET(guest_ss_ar_bytes, 888);
722 CHECK_OFFSET(guest_ds_ar_bytes, 892);
723 CHECK_OFFSET(guest_fs_ar_bytes, 896);
724 CHECK_OFFSET(guest_gs_ar_bytes, 900);
725 CHECK_OFFSET(guest_ldtr_ar_bytes, 904);
726 CHECK_OFFSET(guest_tr_ar_bytes, 908);
727 CHECK_OFFSET(guest_interruptibility_info, 912);
728 CHECK_OFFSET(guest_activity_state, 916);
729 CHECK_OFFSET(guest_sysenter_cs, 920);
730 CHECK_OFFSET(host_ia32_sysenter_cs, 924);
731 CHECK_OFFSET(vmx_preemption_timer_value, 928);
732 CHECK_OFFSET(virtual_processor_id, 960);
733 CHECK_OFFSET(posted_intr_nv, 962);
734 CHECK_OFFSET(guest_es_selector, 964);
735 CHECK_OFFSET(guest_cs_selector, 966);
736 CHECK_OFFSET(guest_ss_selector, 968);
737 CHECK_OFFSET(guest_ds_selector, 970);
738 CHECK_OFFSET(guest_fs_selector, 972);
739 CHECK_OFFSET(guest_gs_selector, 974);
740 CHECK_OFFSET(guest_ldtr_selector, 976);
741 CHECK_OFFSET(guest_tr_selector, 978);
742 CHECK_OFFSET(guest_intr_status, 980);
743 CHECK_OFFSET(host_es_selector, 982);
744 CHECK_OFFSET(host_cs_selector, 984);
745 CHECK_OFFSET(host_ss_selector, 986);
746 CHECK_OFFSET(host_ds_selector, 988);
747 CHECK_OFFSET(host_fs_selector, 990);
748 CHECK_OFFSET(host_gs_selector, 992);
749 CHECK_OFFSET(host_tr_selector, 994);
750 CHECK_OFFSET(guest_pml_index, 996);
754 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
755 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
756 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
758 * IMPORTANT: Changing this value will break save/restore compatibility with
759 * older kvm releases.
761 #define VMCS12_REVISION 0x11e57ed0
764 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
765 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
766 * current implementation, 4K are reserved to avoid future complications.
768 #define VMCS12_SIZE 0x1000
771 * VMCS12_MAX_FIELD_INDEX is the highest index value used in any
772 * supported VMCS12 field encoding.
774 #define VMCS12_MAX_FIELD_INDEX 0x17
776 struct nested_vmx_msrs {
778 * We only store the "true" versions of the VMX capability MSRs. We
779 * generate the "non-true" versions by setting the must-be-1 bits
780 * according to the SDM.
782 u32 procbased_ctls_low;
783 u32 procbased_ctls_high;
784 u32 secondary_ctls_low;
785 u32 secondary_ctls_high;
786 u32 pinbased_ctls_low;
787 u32 pinbased_ctls_high;
806 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
807 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
810 /* Has the level1 guest done vmxon? */
815 /* The guest-physical address of the current VMCS L1 keeps for L2 */
818 * Cache of the guest's VMCS, existing outside of guest memory.
819 * Loaded from guest memory during VMPTRLD. Flushed to guest
820 * memory during VMCLEAR and VMPTRLD.
822 struct vmcs12 *cached_vmcs12;
824 * Cache of the guest's shadow VMCS, existing outside of guest
825 * memory. Loaded from guest memory during VM entry. Flushed
826 * to guest memory during VM exit.
828 struct vmcs12 *cached_shadow_vmcs12;
830 * Indicates if the shadow vmcs must be updated with the
831 * data hold by vmcs12
833 bool sync_shadow_vmcs;
836 bool change_vmcs01_virtual_apic_mode;
838 /* L2 must run next, and mustn't decide to exit to L1. */
839 bool nested_run_pending;
841 struct loaded_vmcs vmcs02;
844 * Guest pages referred to in the vmcs02 with host-physical
845 * pointers, so we must keep them pinned while L2 runs.
847 struct page *apic_access_page;
848 struct page *virtual_apic_page;
849 struct page *pi_desc_page;
850 struct pi_desc *pi_desc;
854 struct hrtimer preemption_timer;
855 bool preemption_timer_expired;
857 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
863 struct nested_vmx_msrs msrs;
865 /* SMM related state */
867 /* in VMX operation on SMM entry? */
869 /* in guest mode on SMM entry? */
874 #define POSTED_INTR_ON 0
875 #define POSTED_INTR_SN 1
877 /* Posted-Interrupt Descriptor */
879 u32 pir[8]; /* Posted interrupt requested */
882 /* bit 256 - Outstanding Notification */
884 /* bit 257 - Suppress Notification */
886 /* bit 271:258 - Reserved */
888 /* bit 279:272 - Notification Vector */
890 /* bit 287:280 - Reserved */
892 /* bit 319:288 - Notification Destination */
900 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
902 return test_and_set_bit(POSTED_INTR_ON,
903 (unsigned long *)&pi_desc->control);
906 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
908 return test_and_clear_bit(POSTED_INTR_ON,
909 (unsigned long *)&pi_desc->control);
912 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
914 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
917 static inline void pi_clear_sn(struct pi_desc *pi_desc)
919 return clear_bit(POSTED_INTR_SN,
920 (unsigned long *)&pi_desc->control);
923 static inline void pi_set_sn(struct pi_desc *pi_desc)
925 return set_bit(POSTED_INTR_SN,
926 (unsigned long *)&pi_desc->control);
929 static inline void pi_clear_on(struct pi_desc *pi_desc)
931 clear_bit(POSTED_INTR_ON,
932 (unsigned long *)&pi_desc->control);
935 static inline int pi_test_on(struct pi_desc *pi_desc)
937 return test_bit(POSTED_INTR_ON,
938 (unsigned long *)&pi_desc->control);
941 static inline int pi_test_sn(struct pi_desc *pi_desc)
943 return test_bit(POSTED_INTR_SN,
944 (unsigned long *)&pi_desc->control);
949 struct vmx_msr_entry val[NR_AUTOLOAD_MSRS];
953 struct kvm_vcpu vcpu;
954 unsigned long host_rsp;
958 u32 idt_vectoring_info;
960 struct shared_msr_entry *guest_msrs;
963 unsigned long host_idt_base;
965 u64 msr_host_kernel_gs_base;
966 u64 msr_guest_kernel_gs_base;
969 u64 arch_capabilities;
972 u32 vm_entry_controls_shadow;
973 u32 vm_exit_controls_shadow;
974 u32 secondary_exec_control;
977 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
978 * non-nested (L1) guest, it always points to vmcs01. For a nested
979 * guest (L2), it points to a different VMCS. loaded_cpu_state points
980 * to the VMCS whose state is loaded into the CPU registers that only
981 * need to be switched when transitioning to/from the kernel; a NULL
982 * value indicates that host state is loaded.
984 struct loaded_vmcs vmcs01;
985 struct loaded_vmcs *loaded_vmcs;
986 struct loaded_vmcs *loaded_cpu_state;
987 bool __launched; /* temporary, used in vmx_vcpu_run */
988 struct msr_autoload {
989 struct vmx_msrs guest;
990 struct vmx_msrs host;
996 struct kvm_segment segs[8];
999 u32 bitmask; /* 4 bits per segment (1 bit per field) */
1000 struct kvm_save_segment {
1008 bool emulation_required;
1012 /* Posted interrupt descriptor */
1013 struct pi_desc pi_desc;
1015 /* Support for a guest hypervisor (nested VMX) */
1016 struct nested_vmx nested;
1018 /* Dynamic PLE window. */
1020 bool ple_window_dirty;
1022 /* Support for PML */
1023 #define PML_ENTITY_NUM 512
1024 struct page *pml_pg;
1026 /* apic deadline value in host tsc */
1027 u64 hv_deadline_tsc;
1029 u64 current_tsc_ratio;
1033 unsigned long host_debugctlmsr;
1036 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
1037 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
1038 * in msr_ia32_feature_control_valid_bits.
1040 u64 msr_ia32_feature_control;
1041 u64 msr_ia32_feature_control_valid_bits;
1045 enum segment_cache_field {
1048 SEG_FIELD_LIMIT = 2,
1054 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
1056 return container_of(kvm, struct kvm_vmx, kvm);
1059 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
1061 return container_of(vcpu, struct vcpu_vmx, vcpu);
1064 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
1066 return &(to_vmx(vcpu)->pi_desc);
1069 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
1070 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
1071 #define FIELD(number, name) [ROL16(number, 6)] = VMCS12_OFFSET(name)
1072 #define FIELD64(number, name) \
1073 FIELD(number, name), \
1074 [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
1077 static u16 shadow_read_only_fields[] = {
1078 #define SHADOW_FIELD_RO(x) x,
1079 #include "vmx_shadow_fields.h"
1081 static int max_shadow_read_only_fields =
1082 ARRAY_SIZE(shadow_read_only_fields);
1084 static u16 shadow_read_write_fields[] = {
1085 #define SHADOW_FIELD_RW(x) x,
1086 #include "vmx_shadow_fields.h"
1088 static int max_shadow_read_write_fields =
1089 ARRAY_SIZE(shadow_read_write_fields);
1091 static const unsigned short vmcs_field_to_offset_table[] = {
1092 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
1093 FIELD(POSTED_INTR_NV, posted_intr_nv),
1094 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
1095 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
1096 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
1097 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
1098 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
1099 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
1100 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
1101 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
1102 FIELD(GUEST_INTR_STATUS, guest_intr_status),
1103 FIELD(GUEST_PML_INDEX, guest_pml_index),
1104 FIELD(HOST_ES_SELECTOR, host_es_selector),
1105 FIELD(HOST_CS_SELECTOR, host_cs_selector),
1106 FIELD(HOST_SS_SELECTOR, host_ss_selector),
1107 FIELD(HOST_DS_SELECTOR, host_ds_selector),
1108 FIELD(HOST_FS_SELECTOR, host_fs_selector),
1109 FIELD(HOST_GS_SELECTOR, host_gs_selector),
1110 FIELD(HOST_TR_SELECTOR, host_tr_selector),
1111 FIELD64(IO_BITMAP_A, io_bitmap_a),
1112 FIELD64(IO_BITMAP_B, io_bitmap_b),
1113 FIELD64(MSR_BITMAP, msr_bitmap),
1114 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
1115 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
1116 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
1117 FIELD64(PML_ADDRESS, pml_address),
1118 FIELD64(TSC_OFFSET, tsc_offset),
1119 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
1120 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
1121 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
1122 FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
1123 FIELD64(EPT_POINTER, ept_pointer),
1124 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
1125 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
1126 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
1127 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
1128 FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
1129 FIELD64(VMREAD_BITMAP, vmread_bitmap),
1130 FIELD64(VMWRITE_BITMAP, vmwrite_bitmap),
1131 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
1132 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
1133 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
1134 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
1135 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
1136 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
1137 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
1138 FIELD64(GUEST_PDPTR0, guest_pdptr0),
1139 FIELD64(GUEST_PDPTR1, guest_pdptr1),
1140 FIELD64(GUEST_PDPTR2, guest_pdptr2),
1141 FIELD64(GUEST_PDPTR3, guest_pdptr3),
1142 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
1143 FIELD64(HOST_IA32_PAT, host_ia32_pat),
1144 FIELD64(HOST_IA32_EFER, host_ia32_efer),
1145 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
1146 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
1147 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
1148 FIELD(EXCEPTION_BITMAP, exception_bitmap),
1149 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
1150 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
1151 FIELD(CR3_TARGET_COUNT, cr3_target_count),
1152 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
1153 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
1154 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
1155 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
1156 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
1157 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
1158 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
1159 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
1160 FIELD(TPR_THRESHOLD, tpr_threshold),
1161 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
1162 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
1163 FIELD(VM_EXIT_REASON, vm_exit_reason),
1164 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
1165 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
1166 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
1167 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
1168 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
1169 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
1170 FIELD(GUEST_ES_LIMIT, guest_es_limit),
1171 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
1172 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
1173 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
1174 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
1175 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
1176 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
1177 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
1178 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
1179 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
1180 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
1181 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
1182 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
1183 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
1184 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
1185 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
1186 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
1187 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
1188 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
1189 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
1190 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
1191 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
1192 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
1193 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
1194 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
1195 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
1196 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
1197 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
1198 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
1199 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
1200 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
1201 FIELD(EXIT_QUALIFICATION, exit_qualification),
1202 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
1203 FIELD(GUEST_CR0, guest_cr0),
1204 FIELD(GUEST_CR3, guest_cr3),
1205 FIELD(GUEST_CR4, guest_cr4),
1206 FIELD(GUEST_ES_BASE, guest_es_base),
1207 FIELD(GUEST_CS_BASE, guest_cs_base),
1208 FIELD(GUEST_SS_BASE, guest_ss_base),
1209 FIELD(GUEST_DS_BASE, guest_ds_base),
1210 FIELD(GUEST_FS_BASE, guest_fs_base),
1211 FIELD(GUEST_GS_BASE, guest_gs_base),
1212 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
1213 FIELD(GUEST_TR_BASE, guest_tr_base),
1214 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
1215 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
1216 FIELD(GUEST_DR7, guest_dr7),
1217 FIELD(GUEST_RSP, guest_rsp),
1218 FIELD(GUEST_RIP, guest_rip),
1219 FIELD(GUEST_RFLAGS, guest_rflags),
1220 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
1221 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
1222 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
1223 FIELD(HOST_CR0, host_cr0),
1224 FIELD(HOST_CR3, host_cr3),
1225 FIELD(HOST_CR4, host_cr4),
1226 FIELD(HOST_FS_BASE, host_fs_base),
1227 FIELD(HOST_GS_BASE, host_gs_base),
1228 FIELD(HOST_TR_BASE, host_tr_base),
1229 FIELD(HOST_GDTR_BASE, host_gdtr_base),
1230 FIELD(HOST_IDTR_BASE, host_idtr_base),
1231 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
1232 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
1233 FIELD(HOST_RSP, host_rsp),
1234 FIELD(HOST_RIP, host_rip),
1237 static inline short vmcs_field_to_offset(unsigned long field)
1239 const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
1240 unsigned short offset;
1246 index = ROL16(field, 6);
1250 index = array_index_nospec(index, size);
1251 offset = vmcs_field_to_offset_table[index];
1257 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
1259 return to_vmx(vcpu)->nested.cached_vmcs12;
1262 static inline struct vmcs12 *get_shadow_vmcs12(struct kvm_vcpu *vcpu)
1264 return to_vmx(vcpu)->nested.cached_shadow_vmcs12;
1267 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
1268 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
1269 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
1270 static bool vmx_xsaves_supported(void);
1271 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1272 struct kvm_segment *var, int seg);
1273 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1274 struct kvm_segment *var, int seg);
1275 static bool guest_state_valid(struct kvm_vcpu *vcpu);
1276 static u32 vmx_segment_access_rights(struct kvm_segment *var);
1277 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
1278 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
1279 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
1280 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
1282 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
1283 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
1286 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
1287 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
1289 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
1290 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
1292 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
1295 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
1296 * can find which vCPU should be waken up.
1298 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
1299 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
1307 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
1309 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
1310 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
1312 static bool cpu_has_load_ia32_efer;
1313 static bool cpu_has_load_perf_global_ctrl;
1315 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
1316 static DEFINE_SPINLOCK(vmx_vpid_lock);
1318 static struct vmcs_config {
1323 u32 pin_based_exec_ctrl;
1324 u32 cpu_based_exec_ctrl;
1325 u32 cpu_based_2nd_exec_ctrl;
1328 struct nested_vmx_msrs nested;
1331 static struct vmx_capability {
1336 #define VMX_SEGMENT_FIELD(seg) \
1337 [VCPU_SREG_##seg] = { \
1338 .selector = GUEST_##seg##_SELECTOR, \
1339 .base = GUEST_##seg##_BASE, \
1340 .limit = GUEST_##seg##_LIMIT, \
1341 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1344 static const struct kvm_vmx_segment_field {
1349 } kvm_vmx_segment_fields[] = {
1350 VMX_SEGMENT_FIELD(CS),
1351 VMX_SEGMENT_FIELD(DS),
1352 VMX_SEGMENT_FIELD(ES),
1353 VMX_SEGMENT_FIELD(FS),
1354 VMX_SEGMENT_FIELD(GS),
1355 VMX_SEGMENT_FIELD(SS),
1356 VMX_SEGMENT_FIELD(TR),
1357 VMX_SEGMENT_FIELD(LDTR),
1360 static u64 host_efer;
1362 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1365 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1366 * away by decrementing the array size.
1368 static const u32 vmx_msr_index[] = {
1369 #ifdef CONFIG_X86_64
1370 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1372 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1375 DEFINE_STATIC_KEY_FALSE(enable_evmcs);
1377 #define current_evmcs ((struct hv_enlightened_vmcs *)this_cpu_read(current_vmcs))
1379 #define KVM_EVMCS_VERSION 1
1381 #if IS_ENABLED(CONFIG_HYPERV)
1382 static bool __read_mostly enlightened_vmcs = true;
1383 module_param(enlightened_vmcs, bool, 0444);
1385 static inline void evmcs_write64(unsigned long field, u64 value)
1388 int offset = get_evmcs_offset(field, &clean_field);
1393 *(u64 *)((char *)current_evmcs + offset) = value;
1395 current_evmcs->hv_clean_fields &= ~clean_field;
1398 static inline void evmcs_write32(unsigned long field, u32 value)
1401 int offset = get_evmcs_offset(field, &clean_field);
1406 *(u32 *)((char *)current_evmcs + offset) = value;
1407 current_evmcs->hv_clean_fields &= ~clean_field;
1410 static inline void evmcs_write16(unsigned long field, u16 value)
1413 int offset = get_evmcs_offset(field, &clean_field);
1418 *(u16 *)((char *)current_evmcs + offset) = value;
1419 current_evmcs->hv_clean_fields &= ~clean_field;
1422 static inline u64 evmcs_read64(unsigned long field)
1424 int offset = get_evmcs_offset(field, NULL);
1429 return *(u64 *)((char *)current_evmcs + offset);
1432 static inline u32 evmcs_read32(unsigned long field)
1434 int offset = get_evmcs_offset(field, NULL);
1439 return *(u32 *)((char *)current_evmcs + offset);
1442 static inline u16 evmcs_read16(unsigned long field)
1444 int offset = get_evmcs_offset(field, NULL);
1449 return *(u16 *)((char *)current_evmcs + offset);
1452 static inline void evmcs_touch_msr_bitmap(void)
1454 if (unlikely(!current_evmcs))
1457 if (current_evmcs->hv_enlightenments_control.msr_bitmap)
1458 current_evmcs->hv_clean_fields &=
1459 ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP;
1462 static void evmcs_load(u64 phys_addr)
1464 struct hv_vp_assist_page *vp_ap =
1465 hv_get_vp_assist_page(smp_processor_id());
1467 vp_ap->current_nested_vmcs = phys_addr;
1468 vp_ap->enlighten_vmentry = 1;
1471 static void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf)
1474 * Enlightened VMCSv1 doesn't support these:
1476 * POSTED_INTR_NV = 0x00000002,
1477 * GUEST_INTR_STATUS = 0x00000810,
1478 * APIC_ACCESS_ADDR = 0x00002014,
1479 * POSTED_INTR_DESC_ADDR = 0x00002016,
1480 * EOI_EXIT_BITMAP0 = 0x0000201c,
1481 * EOI_EXIT_BITMAP1 = 0x0000201e,
1482 * EOI_EXIT_BITMAP2 = 0x00002020,
1483 * EOI_EXIT_BITMAP3 = 0x00002022,
1485 vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
1486 vmcs_conf->cpu_based_2nd_exec_ctrl &=
1487 ~SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1488 vmcs_conf->cpu_based_2nd_exec_ctrl &=
1489 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1490 vmcs_conf->cpu_based_2nd_exec_ctrl &=
1491 ~SECONDARY_EXEC_APIC_REGISTER_VIRT;
1494 * GUEST_PML_INDEX = 0x00000812,
1495 * PML_ADDRESS = 0x0000200e,
1497 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_PML;
1499 /* VM_FUNCTION_CONTROL = 0x00002018, */
1500 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_VMFUNC;
1503 * EPTP_LIST_ADDRESS = 0x00002024,
1504 * VMREAD_BITMAP = 0x00002026,
1505 * VMWRITE_BITMAP = 0x00002028,
1507 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_SHADOW_VMCS;
1510 * TSC_MULTIPLIER = 0x00002032,
1512 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_TSC_SCALING;
1515 * PLE_GAP = 0x00004020,
1516 * PLE_WINDOW = 0x00004022,
1518 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1521 * VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
1523 vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
1526 * GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
1527 * HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
1529 vmcs_conf->vmexit_ctrl &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
1530 vmcs_conf->vmentry_ctrl &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
1533 * Currently unsupported in KVM:
1534 * GUEST_IA32_RTIT_CTL = 0x00002814,
1538 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
1539 static void check_ept_pointer_match(struct kvm *kvm)
1541 struct kvm_vcpu *vcpu;
1542 u64 tmp_eptp = INVALID_PAGE;
1545 kvm_for_each_vcpu(i, vcpu, kvm) {
1546 if (!VALID_PAGE(tmp_eptp)) {
1547 tmp_eptp = to_vmx(vcpu)->ept_pointer;
1548 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
1549 to_kvm_vmx(kvm)->ept_pointers_match
1550 = EPT_POINTERS_MISMATCH;
1555 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
1558 static int vmx_hv_remote_flush_tlb(struct kvm *kvm)
1562 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
1564 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
1565 check_ept_pointer_match(kvm);
1567 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
1572 ret = hyperv_flush_guest_mapping(
1573 to_vmx(kvm_get_vcpu(kvm, 0))->ept_pointer);
1576 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
1579 #else /* !IS_ENABLED(CONFIG_HYPERV) */
1580 static inline void evmcs_write64(unsigned long field, u64 value) {}
1581 static inline void evmcs_write32(unsigned long field, u32 value) {}
1582 static inline void evmcs_write16(unsigned long field, u16 value) {}
1583 static inline u64 evmcs_read64(unsigned long field) { return 0; }
1584 static inline u32 evmcs_read32(unsigned long field) { return 0; }
1585 static inline u16 evmcs_read16(unsigned long field) { return 0; }
1586 static inline void evmcs_load(u64 phys_addr) {}
1587 static inline void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf) {}
1588 static inline void evmcs_touch_msr_bitmap(void) {}
1589 #endif /* IS_ENABLED(CONFIG_HYPERV) */
1591 static inline bool is_exception_n(u32 intr_info, u8 vector)
1593 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1594 INTR_INFO_VALID_MASK)) ==
1595 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1598 static inline bool is_debug(u32 intr_info)
1600 return is_exception_n(intr_info, DB_VECTOR);
1603 static inline bool is_breakpoint(u32 intr_info)
1605 return is_exception_n(intr_info, BP_VECTOR);
1608 static inline bool is_page_fault(u32 intr_info)
1610 return is_exception_n(intr_info, PF_VECTOR);
1613 static inline bool is_no_device(u32 intr_info)
1615 return is_exception_n(intr_info, NM_VECTOR);
1618 static inline bool is_invalid_opcode(u32 intr_info)
1620 return is_exception_n(intr_info, UD_VECTOR);
1623 static inline bool is_gp_fault(u32 intr_info)
1625 return is_exception_n(intr_info, GP_VECTOR);
1628 static inline bool is_external_interrupt(u32 intr_info)
1630 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1631 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1634 static inline bool is_machine_check(u32 intr_info)
1636 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1637 INTR_INFO_VALID_MASK)) ==
1638 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1641 /* Undocumented: icebp/int1 */
1642 static inline bool is_icebp(u32 intr_info)
1644 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1645 == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
1648 static inline bool cpu_has_vmx_msr_bitmap(void)
1650 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1653 static inline bool cpu_has_vmx_tpr_shadow(void)
1655 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1658 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1660 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1663 static inline bool cpu_has_secondary_exec_ctrls(void)
1665 return vmcs_config.cpu_based_exec_ctrl &
1666 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1669 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1671 return vmcs_config.cpu_based_2nd_exec_ctrl &
1672 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1675 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1677 return vmcs_config.cpu_based_2nd_exec_ctrl &
1678 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1681 static inline bool cpu_has_vmx_apic_register_virt(void)
1683 return vmcs_config.cpu_based_2nd_exec_ctrl &
1684 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1687 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1689 return vmcs_config.cpu_based_2nd_exec_ctrl &
1690 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1693 static inline bool cpu_has_vmx_encls_vmexit(void)
1695 return vmcs_config.cpu_based_2nd_exec_ctrl &
1696 SECONDARY_EXEC_ENCLS_EXITING;
1700 * Comment's format: document - errata name - stepping - processor name.
1702 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1704 static u32 vmx_preemption_cpu_tfms[] = {
1705 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1707 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1708 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1709 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1711 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1713 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1714 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1716 * 320767.pdf - AAP86 - B1 -
1717 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1720 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1722 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1724 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1726 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1727 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1728 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1732 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1734 u32 eax = cpuid_eax(0x00000001), i;
1736 /* Clear the reserved bits */
1737 eax &= ~(0x3U << 14 | 0xfU << 28);
1738 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1739 if (eax == vmx_preemption_cpu_tfms[i])
1745 static inline bool cpu_has_vmx_preemption_timer(void)
1747 return vmcs_config.pin_based_exec_ctrl &
1748 PIN_BASED_VMX_PREEMPTION_TIMER;
1751 static inline bool cpu_has_vmx_posted_intr(void)
1753 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1754 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1757 static inline bool cpu_has_vmx_apicv(void)
1759 return cpu_has_vmx_apic_register_virt() &&
1760 cpu_has_vmx_virtual_intr_delivery() &&
1761 cpu_has_vmx_posted_intr();
1764 static inline bool cpu_has_vmx_flexpriority(void)
1766 return cpu_has_vmx_tpr_shadow() &&
1767 cpu_has_vmx_virtualize_apic_accesses();
1770 static inline bool cpu_has_vmx_ept_execute_only(void)
1772 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1775 static inline bool cpu_has_vmx_ept_2m_page(void)
1777 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1780 static inline bool cpu_has_vmx_ept_1g_page(void)
1782 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1785 static inline bool cpu_has_vmx_ept_4levels(void)
1787 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1790 static inline bool cpu_has_vmx_ept_mt_wb(void)
1792 return vmx_capability.ept & VMX_EPTP_WB_BIT;
1795 static inline bool cpu_has_vmx_ept_5levels(void)
1797 return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1800 static inline bool cpu_has_vmx_ept_ad_bits(void)
1802 return vmx_capability.ept & VMX_EPT_AD_BIT;
1805 static inline bool cpu_has_vmx_invept_context(void)
1807 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1810 static inline bool cpu_has_vmx_invept_global(void)
1812 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1815 static inline bool cpu_has_vmx_invvpid_individual_addr(void)
1817 return vmx_capability.vpid & VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT;
1820 static inline bool cpu_has_vmx_invvpid_single(void)
1822 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1825 static inline bool cpu_has_vmx_invvpid_global(void)
1827 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1830 static inline bool cpu_has_vmx_invvpid(void)
1832 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1835 static inline bool cpu_has_vmx_ept(void)
1837 return vmcs_config.cpu_based_2nd_exec_ctrl &
1838 SECONDARY_EXEC_ENABLE_EPT;
1841 static inline bool cpu_has_vmx_unrestricted_guest(void)
1843 return vmcs_config.cpu_based_2nd_exec_ctrl &
1844 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1847 static inline bool cpu_has_vmx_ple(void)
1849 return vmcs_config.cpu_based_2nd_exec_ctrl &
1850 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1853 static inline bool cpu_has_vmx_basic_inout(void)
1855 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1858 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1860 return flexpriority_enabled && lapic_in_kernel(vcpu);
1863 static inline bool cpu_has_vmx_vpid(void)
1865 return vmcs_config.cpu_based_2nd_exec_ctrl &
1866 SECONDARY_EXEC_ENABLE_VPID;
1869 static inline bool cpu_has_vmx_rdtscp(void)
1871 return vmcs_config.cpu_based_2nd_exec_ctrl &
1872 SECONDARY_EXEC_RDTSCP;
1875 static inline bool cpu_has_vmx_invpcid(void)
1877 return vmcs_config.cpu_based_2nd_exec_ctrl &
1878 SECONDARY_EXEC_ENABLE_INVPCID;
1881 static inline bool cpu_has_virtual_nmis(void)
1883 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1886 static inline bool cpu_has_vmx_wbinvd_exit(void)
1888 return vmcs_config.cpu_based_2nd_exec_ctrl &
1889 SECONDARY_EXEC_WBINVD_EXITING;
1892 static inline bool cpu_has_vmx_shadow_vmcs(void)
1895 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1896 /* check if the cpu supports writing r/o exit information fields */
1897 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1900 return vmcs_config.cpu_based_2nd_exec_ctrl &
1901 SECONDARY_EXEC_SHADOW_VMCS;
1904 static inline bool cpu_has_vmx_pml(void)
1906 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1909 static inline bool cpu_has_vmx_tsc_scaling(void)
1911 return vmcs_config.cpu_based_2nd_exec_ctrl &
1912 SECONDARY_EXEC_TSC_SCALING;
1915 static inline bool cpu_has_vmx_vmfunc(void)
1917 return vmcs_config.cpu_based_2nd_exec_ctrl &
1918 SECONDARY_EXEC_ENABLE_VMFUNC;
1921 static bool vmx_umip_emulated(void)
1923 return vmcs_config.cpu_based_2nd_exec_ctrl &
1924 SECONDARY_EXEC_DESC;
1927 static inline bool report_flexpriority(void)
1929 return flexpriority_enabled;
1932 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1934 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low);
1938 * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE
1939 * to modify any valid field of the VMCS, or are the VM-exit
1940 * information fields read-only?
1942 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu)
1944 return to_vmx(vcpu)->nested.msrs.misc_low &
1945 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS;
1948 static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu)
1950 return to_vmx(vcpu)->nested.msrs.misc_low & VMX_MISC_ZERO_LEN_INS;
1953 static inline bool nested_cpu_supports_monitor_trap_flag(struct kvm_vcpu *vcpu)
1955 return to_vmx(vcpu)->nested.msrs.procbased_ctls_high &
1956 CPU_BASED_MONITOR_TRAP_FLAG;
1959 static inline bool nested_cpu_has_vmx_shadow_vmcs(struct kvm_vcpu *vcpu)
1961 return to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
1962 SECONDARY_EXEC_SHADOW_VMCS;
1965 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1967 return vmcs12->cpu_based_vm_exec_control & bit;
1970 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1972 return (vmcs12->cpu_based_vm_exec_control &
1973 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1974 (vmcs12->secondary_vm_exec_control & bit);
1977 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1979 return vmcs12->pin_based_vm_exec_control &
1980 PIN_BASED_VMX_PREEMPTION_TIMER;
1983 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12)
1985 return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING;
1988 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1990 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1993 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1995 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1998 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
2000 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
2003 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
2005 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
2008 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
2010 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
2013 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
2015 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
2018 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
2020 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
2023 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
2025 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2028 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
2030 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
2033 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
2035 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
2038 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
2040 return nested_cpu_has_vmfunc(vmcs12) &&
2041 (vmcs12->vm_function_control &
2042 VMX_VMFUNC_EPTP_SWITCHING);
2045 static inline bool nested_cpu_has_shadow_vmcs(struct vmcs12 *vmcs12)
2047 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS);
2050 static inline bool is_nmi(u32 intr_info)
2052 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
2053 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
2056 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
2058 unsigned long exit_qualification);
2059 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
2060 struct vmcs12 *vmcs12,
2061 u32 reason, unsigned long qualification);
2063 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
2067 for (i = 0; i < vmx->nmsrs; ++i)
2068 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
2073 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
2079 } operand = { vpid, 0, gva };
2082 asm volatile (__ex(ASM_VMX_INVVPID) CC_SET(na)
2083 : CC_OUT(na) (error) : "a"(&operand), "c"(ext)
2088 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
2092 } operand = {eptp, gpa};
2095 asm volatile (__ex(ASM_VMX_INVEPT) CC_SET(na)
2096 : CC_OUT(na) (error) : "a" (&operand), "c" (ext)
2101 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
2105 i = __find_msr_index(vmx, msr);
2107 return &vmx->guest_msrs[i];
2111 static void vmcs_clear(struct vmcs *vmcs)
2113 u64 phys_addr = __pa(vmcs);
2116 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) CC_SET(na)
2117 : CC_OUT(na) (error) : "a"(&phys_addr), "m"(phys_addr)
2119 if (unlikely(error))
2120 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
2124 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
2126 vmcs_clear(loaded_vmcs->vmcs);
2127 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
2128 vmcs_clear(loaded_vmcs->shadow_vmcs);
2129 loaded_vmcs->cpu = -1;
2130 loaded_vmcs->launched = 0;
2133 static void vmcs_load(struct vmcs *vmcs)
2135 u64 phys_addr = __pa(vmcs);
2138 if (static_branch_unlikely(&enable_evmcs))
2139 return evmcs_load(phys_addr);
2141 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) CC_SET(na)
2142 : CC_OUT(na) (error) : "a"(&phys_addr), "m"(phys_addr)
2144 if (unlikely(error))
2145 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
2149 #ifdef CONFIG_KEXEC_CORE
2151 * This bitmap is used to indicate whether the vmclear
2152 * operation is enabled on all cpus. All disabled by
2155 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
2157 static inline void crash_enable_local_vmclear(int cpu)
2159 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
2162 static inline void crash_disable_local_vmclear(int cpu)
2164 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
2167 static inline int crash_local_vmclear_enabled(int cpu)
2169 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
2172 static void crash_vmclear_local_loaded_vmcss(void)
2174 int cpu = raw_smp_processor_id();
2175 struct loaded_vmcs *v;
2177 if (!crash_local_vmclear_enabled(cpu))
2180 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
2181 loaded_vmcss_on_cpu_link)
2182 vmcs_clear(v->vmcs);
2185 static inline void crash_enable_local_vmclear(int cpu) { }
2186 static inline void crash_disable_local_vmclear(int cpu) { }
2187 #endif /* CONFIG_KEXEC_CORE */
2189 static void __loaded_vmcs_clear(void *arg)
2191 struct loaded_vmcs *loaded_vmcs = arg;
2192 int cpu = raw_smp_processor_id();
2194 if (loaded_vmcs->cpu != cpu)
2195 return; /* vcpu migration can race with cpu offline */
2196 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
2197 per_cpu(current_vmcs, cpu) = NULL;
2198 crash_disable_local_vmclear(cpu);
2199 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
2202 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
2203 * is before setting loaded_vmcs->vcpu to -1 which is done in
2204 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
2205 * then adds the vmcs into percpu list before it is deleted.
2209 loaded_vmcs_init(loaded_vmcs);
2210 crash_enable_local_vmclear(cpu);
2213 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
2215 int cpu = loaded_vmcs->cpu;
2218 smp_call_function_single(cpu,
2219 __loaded_vmcs_clear, loaded_vmcs, 1);
2222 static inline bool vpid_sync_vcpu_addr(int vpid, gva_t addr)
2227 if (cpu_has_vmx_invvpid_individual_addr()) {
2228 __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR, vpid, addr);
2235 static inline void vpid_sync_vcpu_single(int vpid)
2240 if (cpu_has_vmx_invvpid_single())
2241 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
2244 static inline void vpid_sync_vcpu_global(void)
2246 if (cpu_has_vmx_invvpid_global())
2247 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
2250 static inline void vpid_sync_context(int vpid)
2252 if (cpu_has_vmx_invvpid_single())
2253 vpid_sync_vcpu_single(vpid);
2255 vpid_sync_vcpu_global();
2258 static inline void ept_sync_global(void)
2260 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
2263 static inline void ept_sync_context(u64 eptp)
2265 if (cpu_has_vmx_invept_context())
2266 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
2271 static __always_inline void vmcs_check16(unsigned long field)
2273 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2274 "16-bit accessor invalid for 64-bit field");
2275 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2276 "16-bit accessor invalid for 64-bit high field");
2277 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2278 "16-bit accessor invalid for 32-bit high field");
2279 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2280 "16-bit accessor invalid for natural width field");
2283 static __always_inline void vmcs_check32(unsigned long field)
2285 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2286 "32-bit accessor invalid for 16-bit field");
2287 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2288 "32-bit accessor invalid for natural width field");
2291 static __always_inline void vmcs_check64(unsigned long field)
2293 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2294 "64-bit accessor invalid for 16-bit field");
2295 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2296 "64-bit accessor invalid for 64-bit high field");
2297 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2298 "64-bit accessor invalid for 32-bit field");
2299 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2300 "64-bit accessor invalid for natural width field");
2303 static __always_inline void vmcs_checkl(unsigned long field)
2305 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2306 "Natural width accessor invalid for 16-bit field");
2307 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2308 "Natural width accessor invalid for 64-bit field");
2309 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2310 "Natural width accessor invalid for 64-bit high field");
2311 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2312 "Natural width accessor invalid for 32-bit field");
2315 static __always_inline unsigned long __vmcs_readl(unsigned long field)
2317 unsigned long value;
2319 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
2320 : "=a"(value) : "d"(field) : "cc");
2324 static __always_inline u16 vmcs_read16(unsigned long field)
2326 vmcs_check16(field);
2327 if (static_branch_unlikely(&enable_evmcs))
2328 return evmcs_read16(field);
2329 return __vmcs_readl(field);
2332 static __always_inline u32 vmcs_read32(unsigned long field)
2334 vmcs_check32(field);
2335 if (static_branch_unlikely(&enable_evmcs))
2336 return evmcs_read32(field);
2337 return __vmcs_readl(field);
2340 static __always_inline u64 vmcs_read64(unsigned long field)
2342 vmcs_check64(field);
2343 if (static_branch_unlikely(&enable_evmcs))
2344 return evmcs_read64(field);
2345 #ifdef CONFIG_X86_64
2346 return __vmcs_readl(field);
2348 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
2352 static __always_inline unsigned long vmcs_readl(unsigned long field)
2355 if (static_branch_unlikely(&enable_evmcs))
2356 return evmcs_read64(field);
2357 return __vmcs_readl(field);
2360 static noinline void vmwrite_error(unsigned long field, unsigned long value)
2362 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
2363 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
2367 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
2371 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) CC_SET(na)
2372 : CC_OUT(na) (error) : "a"(value), "d"(field));
2373 if (unlikely(error))
2374 vmwrite_error(field, value);
2377 static __always_inline void vmcs_write16(unsigned long field, u16 value)
2379 vmcs_check16(field);
2380 if (static_branch_unlikely(&enable_evmcs))
2381 return evmcs_write16(field, value);
2383 __vmcs_writel(field, value);
2386 static __always_inline void vmcs_write32(unsigned long field, u32 value)
2388 vmcs_check32(field);
2389 if (static_branch_unlikely(&enable_evmcs))
2390 return evmcs_write32(field, value);
2392 __vmcs_writel(field, value);
2395 static __always_inline void vmcs_write64(unsigned long field, u64 value)
2397 vmcs_check64(field);
2398 if (static_branch_unlikely(&enable_evmcs))
2399 return evmcs_write64(field, value);
2401 __vmcs_writel(field, value);
2402 #ifndef CONFIG_X86_64
2404 __vmcs_writel(field+1, value >> 32);
2408 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
2411 if (static_branch_unlikely(&enable_evmcs))
2412 return evmcs_write64(field, value);
2414 __vmcs_writel(field, value);
2417 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
2419 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2420 "vmcs_clear_bits does not support 64-bit fields");
2421 if (static_branch_unlikely(&enable_evmcs))
2422 return evmcs_write32(field, evmcs_read32(field) & ~mask);
2424 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
2427 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
2429 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2430 "vmcs_set_bits does not support 64-bit fields");
2431 if (static_branch_unlikely(&enable_evmcs))
2432 return evmcs_write32(field, evmcs_read32(field) | mask);
2434 __vmcs_writel(field, __vmcs_readl(field) | mask);
2437 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
2439 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
2442 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
2444 vmcs_write32(VM_ENTRY_CONTROLS, val);
2445 vmx->vm_entry_controls_shadow = val;
2448 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
2450 if (vmx->vm_entry_controls_shadow != val)
2451 vm_entry_controls_init(vmx, val);
2454 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
2456 return vmx->vm_entry_controls_shadow;
2460 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2462 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
2465 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2467 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
2470 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
2472 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
2475 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
2477 vmcs_write32(VM_EXIT_CONTROLS, val);
2478 vmx->vm_exit_controls_shadow = val;
2481 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
2483 if (vmx->vm_exit_controls_shadow != val)
2484 vm_exit_controls_init(vmx, val);
2487 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
2489 return vmx->vm_exit_controls_shadow;
2493 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2495 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
2498 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2500 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
2503 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
2505 vmx->segment_cache.bitmask = 0;
2508 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
2512 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
2514 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
2515 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
2516 vmx->segment_cache.bitmask = 0;
2518 ret = vmx->segment_cache.bitmask & mask;
2519 vmx->segment_cache.bitmask |= mask;
2523 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
2525 u16 *p = &vmx->segment_cache.seg[seg].selector;
2527 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
2528 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
2532 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
2534 ulong *p = &vmx->segment_cache.seg[seg].base;
2536 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
2537 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
2541 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
2543 u32 *p = &vmx->segment_cache.seg[seg].limit;
2545 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
2546 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
2550 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
2552 u32 *p = &vmx->segment_cache.seg[seg].ar;
2554 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
2555 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
2559 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
2563 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
2564 (1u << DB_VECTOR) | (1u << AC_VECTOR);
2566 * Guest access to VMware backdoor ports could legitimately
2567 * trigger #GP because of TSS I/O permission bitmap.
2568 * We intercept those #GP and allow access to them anyway
2571 if (enable_vmware_backdoor)
2572 eb |= (1u << GP_VECTOR);
2573 if ((vcpu->guest_debug &
2574 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
2575 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
2576 eb |= 1u << BP_VECTOR;
2577 if (to_vmx(vcpu)->rmode.vm86_active)
2580 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
2582 /* When we are running a nested L2 guest and L1 specified for it a
2583 * certain exception bitmap, we must trap the same exceptions and pass
2584 * them to L1. When running L2, we will only handle the exceptions
2585 * specified above if L1 did not want them.
2587 if (is_guest_mode(vcpu))
2588 eb |= get_vmcs12(vcpu)->exception_bitmap;
2590 vmcs_write32(EXCEPTION_BITMAP, eb);
2594 * Check if MSR is intercepted for currently loaded MSR bitmap.
2596 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
2598 unsigned long *msr_bitmap;
2599 int f = sizeof(unsigned long);
2601 if (!cpu_has_vmx_msr_bitmap())
2604 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
2606 if (msr <= 0x1fff) {
2607 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2608 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2610 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2617 * Check if MSR is intercepted for L01 MSR bitmap.
2619 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
2621 unsigned long *msr_bitmap;
2622 int f = sizeof(unsigned long);
2624 if (!cpu_has_vmx_msr_bitmap())
2627 msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
2629 if (msr <= 0x1fff) {
2630 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2631 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2633 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2639 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2640 unsigned long entry, unsigned long exit)
2642 vm_entry_controls_clearbit(vmx, entry);
2643 vm_exit_controls_clearbit(vmx, exit);
2646 static int find_msr(struct vmx_msrs *m, unsigned int msr)
2650 for (i = 0; i < m->nr; ++i) {
2651 if (m->val[i].index == msr)
2657 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
2660 struct msr_autoload *m = &vmx->msr_autoload;
2664 if (cpu_has_load_ia32_efer) {
2665 clear_atomic_switch_msr_special(vmx,
2666 VM_ENTRY_LOAD_IA32_EFER,
2667 VM_EXIT_LOAD_IA32_EFER);
2671 case MSR_CORE_PERF_GLOBAL_CTRL:
2672 if (cpu_has_load_perf_global_ctrl) {
2673 clear_atomic_switch_msr_special(vmx,
2674 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2675 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2680 i = find_msr(&m->guest, msr);
2684 m->guest.val[i] = m->guest.val[m->guest.nr];
2685 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
2688 i = find_msr(&m->host, msr);
2693 m->host.val[i] = m->host.val[m->host.nr];
2694 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
2697 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2698 unsigned long entry, unsigned long exit,
2699 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
2700 u64 guest_val, u64 host_val)
2702 vmcs_write64(guest_val_vmcs, guest_val);
2703 vmcs_write64(host_val_vmcs, host_val);
2704 vm_entry_controls_setbit(vmx, entry);
2705 vm_exit_controls_setbit(vmx, exit);
2708 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
2709 u64 guest_val, u64 host_val, bool entry_only)
2712 struct msr_autoload *m = &vmx->msr_autoload;
2716 if (cpu_has_load_ia32_efer) {
2717 add_atomic_switch_msr_special(vmx,
2718 VM_ENTRY_LOAD_IA32_EFER,
2719 VM_EXIT_LOAD_IA32_EFER,
2722 guest_val, host_val);
2726 case MSR_CORE_PERF_GLOBAL_CTRL:
2727 if (cpu_has_load_perf_global_ctrl) {
2728 add_atomic_switch_msr_special(vmx,
2729 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2730 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2731 GUEST_IA32_PERF_GLOBAL_CTRL,
2732 HOST_IA32_PERF_GLOBAL_CTRL,
2733 guest_val, host_val);
2737 case MSR_IA32_PEBS_ENABLE:
2738 /* PEBS needs a quiescent period after being disabled (to write
2739 * a record). Disabling PEBS through VMX MSR swapping doesn't
2740 * provide that period, so a CPU could write host's record into
2743 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2746 i = find_msr(&m->guest, msr);
2748 j = find_msr(&m->host, msr);
2750 if (i == NR_AUTOLOAD_MSRS || j == NR_AUTOLOAD_MSRS) {
2751 printk_once(KERN_WARNING "Not enough msr switch entries. "
2752 "Can't add msr %x\n", msr);
2757 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
2759 m->guest.val[i].index = msr;
2760 m->guest.val[i].value = guest_val;
2767 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
2769 m->host.val[j].index = msr;
2770 m->host.val[j].value = host_val;
2773 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2775 u64 guest_efer = vmx->vcpu.arch.efer;
2776 u64 ignore_bits = 0;
2780 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2781 * host CPUID is more efficient than testing guest CPUID
2782 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2784 if (boot_cpu_has(X86_FEATURE_SMEP))
2785 guest_efer |= EFER_NX;
2786 else if (!(guest_efer & EFER_NX))
2787 ignore_bits |= EFER_NX;
2791 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2793 ignore_bits |= EFER_SCE;
2794 #ifdef CONFIG_X86_64
2795 ignore_bits |= EFER_LMA | EFER_LME;
2796 /* SCE is meaningful only in long mode on Intel */
2797 if (guest_efer & EFER_LMA)
2798 ignore_bits &= ~(u64)EFER_SCE;
2801 clear_atomic_switch_msr(vmx, MSR_EFER);
2804 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2805 * On CPUs that support "load IA32_EFER", always switch EFER
2806 * atomically, since it's faster than switching it manually.
2808 if (cpu_has_load_ia32_efer ||
2809 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2810 if (!(guest_efer & EFER_LMA))
2811 guest_efer &= ~EFER_LME;
2812 if (guest_efer != host_efer)
2813 add_atomic_switch_msr(vmx, MSR_EFER,
2814 guest_efer, host_efer, false);
2817 guest_efer &= ~ignore_bits;
2818 guest_efer |= host_efer & ignore_bits;
2820 vmx->guest_msrs[efer_offset].data = guest_efer;
2821 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2827 #ifdef CONFIG_X86_32
2829 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2830 * VMCS rather than the segment table. KVM uses this helper to figure
2831 * out the current bases to poke them into the VMCS before entry.
2833 static unsigned long segment_base(u16 selector)
2835 struct desc_struct *table;
2838 if (!(selector & ~SEGMENT_RPL_MASK))
2841 table = get_current_gdt_ro();
2843 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2844 u16 ldt_selector = kvm_read_ldt();
2846 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2849 table = (struct desc_struct *)segment_base(ldt_selector);
2851 v = get_desc_base(&table[selector >> 3]);
2856 static void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
2858 struct vcpu_vmx *vmx = to_vmx(vcpu);
2859 struct vmcs_host_state *host_state;
2860 #ifdef CONFIG_X86_64
2861 int cpu = raw_smp_processor_id();
2863 unsigned long fs_base, gs_base;
2867 if (vmx->loaded_cpu_state)
2870 vmx->loaded_cpu_state = vmx->loaded_vmcs;
2871 host_state = &vmx->loaded_cpu_state->host_state;
2874 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2875 * allow segment selectors with cpl > 0 or ti == 1.
2877 host_state->ldt_sel = kvm_read_ldt();
2879 #ifdef CONFIG_X86_64
2880 savesegment(ds, host_state->ds_sel);
2881 savesegment(es, host_state->es_sel);
2883 gs_base = cpu_kernelmode_gs_base(cpu);
2884 if (likely(is_64bit_mm(current->mm))) {
2885 save_fsgs_for_kvm();
2886 fs_sel = current->thread.fsindex;
2887 gs_sel = current->thread.gsindex;
2888 fs_base = current->thread.fsbase;
2889 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
2891 savesegment(fs, fs_sel);
2892 savesegment(gs, gs_sel);
2893 fs_base = read_msr(MSR_FS_BASE);
2894 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
2897 if (is_long_mode(&vmx->vcpu))
2898 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2900 savesegment(fs, fs_sel);
2901 savesegment(gs, gs_sel);
2902 fs_base = segment_base(fs_sel);
2903 gs_base = segment_base(gs_sel);
2906 if (unlikely(fs_sel != host_state->fs_sel)) {
2908 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
2910 vmcs_write16(HOST_FS_SELECTOR, 0);
2911 host_state->fs_sel = fs_sel;
2913 if (unlikely(gs_sel != host_state->gs_sel)) {
2915 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
2917 vmcs_write16(HOST_GS_SELECTOR, 0);
2918 host_state->gs_sel = gs_sel;
2920 if (unlikely(fs_base != host_state->fs_base)) {
2921 vmcs_writel(HOST_FS_BASE, fs_base);
2922 host_state->fs_base = fs_base;
2924 if (unlikely(gs_base != host_state->gs_base)) {
2925 vmcs_writel(HOST_GS_BASE, gs_base);
2926 host_state->gs_base = gs_base;
2929 for (i = 0; i < vmx->save_nmsrs; ++i)
2930 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2931 vmx->guest_msrs[i].data,
2932 vmx->guest_msrs[i].mask);
2935 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
2937 struct vmcs_host_state *host_state;
2939 if (!vmx->loaded_cpu_state)
2942 WARN_ON_ONCE(vmx->loaded_cpu_state != vmx->loaded_vmcs);
2943 host_state = &vmx->loaded_cpu_state->host_state;
2945 ++vmx->vcpu.stat.host_state_reload;
2946 vmx->loaded_cpu_state = NULL;
2948 #ifdef CONFIG_X86_64
2949 if (is_long_mode(&vmx->vcpu))
2950 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2952 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
2953 kvm_load_ldt(host_state->ldt_sel);
2954 #ifdef CONFIG_X86_64
2955 load_gs_index(host_state->gs_sel);
2957 loadsegment(gs, host_state->gs_sel);
2960 if (host_state->fs_sel & 7)
2961 loadsegment(fs, host_state->fs_sel);
2962 #ifdef CONFIG_X86_64
2963 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
2964 loadsegment(ds, host_state->ds_sel);
2965 loadsegment(es, host_state->es_sel);
2968 invalidate_tss_limit();
2969 #ifdef CONFIG_X86_64
2970 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2972 load_fixmap_gdt(raw_smp_processor_id());
2975 #ifdef CONFIG_X86_64
2976 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
2978 if (is_long_mode(&vmx->vcpu)) {
2980 if (vmx->loaded_cpu_state)
2981 rdmsrl(MSR_KERNEL_GS_BASE,
2982 vmx->msr_guest_kernel_gs_base);
2985 return vmx->msr_guest_kernel_gs_base;
2988 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
2990 if (is_long_mode(&vmx->vcpu)) {
2992 if (vmx->loaded_cpu_state)
2993 wrmsrl(MSR_KERNEL_GS_BASE, data);
2996 vmx->msr_guest_kernel_gs_base = data;
3000 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
3002 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
3003 struct pi_desc old, new;
3007 * In case of hot-plug or hot-unplug, we may have to undo
3008 * vmx_vcpu_pi_put even if there is no assigned device. And we
3009 * always keep PI.NDST up to date for simplicity: it makes the
3010 * code easier, and CPU migration is not a fast path.
3012 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
3016 * First handle the simple case where no cmpxchg is necessary; just
3017 * allow posting non-urgent interrupts.
3019 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
3020 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
3021 * expects the VCPU to be on the blocked_vcpu_list that matches
3024 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
3026 pi_clear_sn(pi_desc);
3030 /* The full case. */
3032 old.control = new.control = pi_desc->control;
3034 dest = cpu_physical_id(cpu);
3036 if (x2apic_enabled())
3039 new.ndst = (dest << 8) & 0xFF00;
3042 } while (cmpxchg64(&pi_desc->control, old.control,
3043 new.control) != old.control);
3046 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
3048 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
3049 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
3053 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
3054 * vcpu mutex is already taken.
3056 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3058 struct vcpu_vmx *vmx = to_vmx(vcpu);
3059 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
3061 if (!already_loaded) {
3062 loaded_vmcs_clear(vmx->loaded_vmcs);
3063 local_irq_disable();
3064 crash_disable_local_vmclear(cpu);
3067 * Read loaded_vmcs->cpu should be before fetching
3068 * loaded_vmcs->loaded_vmcss_on_cpu_link.
3069 * See the comments in __loaded_vmcs_clear().
3073 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
3074 &per_cpu(loaded_vmcss_on_cpu, cpu));
3075 crash_enable_local_vmclear(cpu);
3079 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
3080 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
3081 vmcs_load(vmx->loaded_vmcs->vmcs);
3082 indirect_branch_prediction_barrier();
3085 if (!already_loaded) {
3086 void *gdt = get_current_gdt_ro();
3087 unsigned long sysenter_esp;
3089 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3092 * Linux uses per-cpu TSS and GDT, so set these when switching
3093 * processors. See 22.2.4.
3095 vmcs_writel(HOST_TR_BASE,
3096 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
3097 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
3100 * VM exits change the host TR limit to 0x67 after a VM
3101 * exit. This is okay, since 0x67 covers everything except
3102 * the IO bitmap and have have code to handle the IO bitmap
3103 * being lost after a VM exit.
3105 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
3107 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
3108 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
3110 vmx->loaded_vmcs->cpu = cpu;
3113 /* Setup TSC multiplier */
3114 if (kvm_has_tsc_control &&
3115 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
3116 decache_tsc_multiplier(vmx);
3118 vmx_vcpu_pi_load(vcpu, cpu);
3119 vmx->host_pkru = read_pkru();
3120 vmx->host_debugctlmsr = get_debugctlmsr();
3123 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
3125 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
3127 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
3128 !irq_remapping_cap(IRQ_POSTING_CAP) ||
3129 !kvm_vcpu_apicv_active(vcpu))
3132 /* Set SN when the vCPU is preempted */
3133 if (vcpu->preempted)
3137 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
3139 vmx_vcpu_pi_put(vcpu);
3141 vmx_prepare_switch_to_host(to_vmx(vcpu));
3144 static bool emulation_required(struct kvm_vcpu *vcpu)
3146 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3149 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
3152 * Return the cr0 value that a nested guest would read. This is a combination
3153 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
3154 * its hypervisor (cr0_read_shadow).
3156 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
3158 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
3159 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
3161 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
3163 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
3164 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
3167 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
3169 unsigned long rflags, save_rflags;
3171 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
3172 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
3173 rflags = vmcs_readl(GUEST_RFLAGS);
3174 if (to_vmx(vcpu)->rmode.vm86_active) {
3175 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3176 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
3177 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3179 to_vmx(vcpu)->rflags = rflags;
3181 return to_vmx(vcpu)->rflags;
3184 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
3186 unsigned long old_rflags = vmx_get_rflags(vcpu);
3188 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
3189 to_vmx(vcpu)->rflags = rflags;
3190 if (to_vmx(vcpu)->rmode.vm86_active) {
3191 to_vmx(vcpu)->rmode.save_rflags = rflags;
3192 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3194 vmcs_writel(GUEST_RFLAGS, rflags);
3196 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
3197 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
3200 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
3202 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
3205 if (interruptibility & GUEST_INTR_STATE_STI)
3206 ret |= KVM_X86_SHADOW_INT_STI;
3207 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
3208 ret |= KVM_X86_SHADOW_INT_MOV_SS;
3213 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
3215 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
3216 u32 interruptibility = interruptibility_old;
3218 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
3220 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
3221 interruptibility |= GUEST_INTR_STATE_MOV_SS;
3222 else if (mask & KVM_X86_SHADOW_INT_STI)
3223 interruptibility |= GUEST_INTR_STATE_STI;
3225 if ((interruptibility != interruptibility_old))
3226 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
3229 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
3233 rip = kvm_rip_read(vcpu);
3234 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3235 kvm_rip_write(vcpu, rip);
3237 /* skipping an emulated instruction also counts */
3238 vmx_set_interrupt_shadow(vcpu, 0);
3241 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
3242 unsigned long exit_qual)
3244 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3245 unsigned int nr = vcpu->arch.exception.nr;
3246 u32 intr_info = nr | INTR_INFO_VALID_MASK;
3248 if (vcpu->arch.exception.has_error_code) {
3249 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
3250 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3253 if (kvm_exception_is_soft(nr))
3254 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3256 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3258 if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
3259 vmx_get_nmi_mask(vcpu))
3260 intr_info |= INTR_INFO_UNBLOCK_NMI;
3262 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
3266 * KVM wants to inject page-faults which it got to the guest. This function
3267 * checks whether in a nested guest, we need to inject them to L1 or L2.
3269 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
3271 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3272 unsigned int nr = vcpu->arch.exception.nr;
3274 if (nr == PF_VECTOR) {
3275 if (vcpu->arch.exception.nested_apf) {
3276 *exit_qual = vcpu->arch.apf.nested_apf_token;
3280 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
3281 * The fix is to add the ancillary datum (CR2 or DR6) to structs
3282 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
3283 * can be written only when inject_pending_event runs. This should be
3284 * conditional on a new capability---if the capability is disabled,
3285 * kvm_multiple_exception would write the ancillary information to
3286 * CR2 or DR6, for backwards ABI-compatibility.
3288 if (nested_vmx_is_page_fault_vmexit(vmcs12,
3289 vcpu->arch.exception.error_code)) {
3290 *exit_qual = vcpu->arch.cr2;
3294 if (vmcs12->exception_bitmap & (1u << nr)) {
3295 if (nr == DB_VECTOR)
3296 *exit_qual = vcpu->arch.dr6;
3306 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
3309 * Ensure that we clear the HLT state in the VMCS. We don't need to
3310 * explicitly skip the instruction because if the HLT state is set,
3311 * then the instruction is already executing and RIP has already been
3314 if (kvm_hlt_in_guest(vcpu->kvm) &&
3315 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
3316 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3319 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
3321 struct vcpu_vmx *vmx = to_vmx(vcpu);
3322 unsigned nr = vcpu->arch.exception.nr;
3323 bool has_error_code = vcpu->arch.exception.has_error_code;
3324 u32 error_code = vcpu->arch.exception.error_code;
3325 u32 intr_info = nr | INTR_INFO_VALID_MASK;
3327 if (has_error_code) {
3328 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
3329 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3332 if (vmx->rmode.vm86_active) {
3334 if (kvm_exception_is_soft(nr))
3335 inc_eip = vcpu->arch.event_exit_inst_len;
3336 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
3337 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3341 WARN_ON_ONCE(vmx->emulation_required);
3343 if (kvm_exception_is_soft(nr)) {
3344 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3345 vmx->vcpu.arch.event_exit_inst_len);
3346 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3348 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3350 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
3352 vmx_clear_hlt(vcpu);
3355 static bool vmx_rdtscp_supported(void)
3357 return cpu_has_vmx_rdtscp();
3360 static bool vmx_invpcid_supported(void)
3362 return cpu_has_vmx_invpcid();
3366 * Swap MSR entry in host/guest MSR entry array.
3368 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
3370 struct shared_msr_entry tmp;
3372 tmp = vmx->guest_msrs[to];
3373 vmx->guest_msrs[to] = vmx->guest_msrs[from];
3374 vmx->guest_msrs[from] = tmp;
3378 * Set up the vmcs to automatically save and restore system
3379 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
3380 * mode, as fiddling with msrs is very expensive.
3382 static void setup_msrs(struct vcpu_vmx *vmx)
3384 int save_nmsrs, index;
3387 #ifdef CONFIG_X86_64
3388 if (is_long_mode(&vmx->vcpu)) {
3389 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
3391 move_msr_up(vmx, index, save_nmsrs++);
3392 index = __find_msr_index(vmx, MSR_LSTAR);
3394 move_msr_up(vmx, index, save_nmsrs++);
3395 index = __find_msr_index(vmx, MSR_CSTAR);
3397 move_msr_up(vmx, index, save_nmsrs++);
3398 index = __find_msr_index(vmx, MSR_TSC_AUX);
3399 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
3400 move_msr_up(vmx, index, save_nmsrs++);
3402 * MSR_STAR is only needed on long mode guests, and only
3403 * if efer.sce is enabled.
3405 index = __find_msr_index(vmx, MSR_STAR);
3406 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
3407 move_msr_up(vmx, index, save_nmsrs++);
3410 index = __find_msr_index(vmx, MSR_EFER);
3411 if (index >= 0 && update_transition_efer(vmx, index))
3412 move_msr_up(vmx, index, save_nmsrs++);
3414 vmx->save_nmsrs = save_nmsrs;
3416 if (cpu_has_vmx_msr_bitmap())
3417 vmx_update_msr_bitmap(&vmx->vcpu);
3420 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
3422 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3424 if (is_guest_mode(vcpu) &&
3425 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
3426 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
3428 return vcpu->arch.tsc_offset;
3432 * writes 'offset' into guest's timestamp counter offset register
3434 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
3436 if (is_guest_mode(vcpu)) {
3438 * We're here if L1 chose not to trap WRMSR to TSC. According
3439 * to the spec, this should set L1's TSC; The offset that L1
3440 * set for L2 remains unchanged, and still needs to be added
3441 * to the newly set TSC to get L2's TSC.
3443 struct vmcs12 *vmcs12;
3444 /* recalculate vmcs02.TSC_OFFSET: */
3445 vmcs12 = get_vmcs12(vcpu);
3446 vmcs_write64(TSC_OFFSET, offset +
3447 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
3448 vmcs12->tsc_offset : 0));
3450 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
3451 vmcs_read64(TSC_OFFSET), offset);
3452 vmcs_write64(TSC_OFFSET, offset);
3457 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
3458 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
3459 * all guests if the "nested" module option is off, and can also be disabled
3460 * for a single guest by disabling its VMX cpuid bit.
3462 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
3464 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
3468 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
3469 * returned for the various VMX controls MSRs when nested VMX is enabled.
3470 * The same values should also be used to verify that vmcs12 control fields are
3471 * valid during nested entry from L1 to L2.
3472 * Each of these control msrs has a low and high 32-bit half: A low bit is on
3473 * if the corresponding bit in the (32-bit) control field *must* be on, and a
3474 * bit in the high half is on if the corresponding bit in the control field
3475 * may be on. See also vmx_control_verify().
3477 static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv)
3480 memset(msrs, 0, sizeof(*msrs));
3485 * Note that as a general rule, the high half of the MSRs (bits in
3486 * the control fields which may be 1) should be initialized by the
3487 * intersection of the underlying hardware's MSR (i.e., features which
3488 * can be supported) and the list of features we want to expose -
3489 * because they are known to be properly supported in our code.
3490 * Also, usually, the low half of the MSRs (bits which must be 1) can
3491 * be set to 0, meaning that L1 may turn off any of these bits. The
3492 * reason is that if one of these bits is necessary, it will appear
3493 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
3494 * fields of vmcs01 and vmcs02, will turn these bits off - and
3495 * nested_vmx_exit_reflected() will not pass related exits to L1.
3496 * These rules have exceptions below.
3499 /* pin-based controls */
3500 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
3501 msrs->pinbased_ctls_low,
3502 msrs->pinbased_ctls_high);
3503 msrs->pinbased_ctls_low |=
3504 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3505 msrs->pinbased_ctls_high &=
3506 PIN_BASED_EXT_INTR_MASK |
3507 PIN_BASED_NMI_EXITING |
3508 PIN_BASED_VIRTUAL_NMIS |
3509 (apicv ? PIN_BASED_POSTED_INTR : 0);
3510 msrs->pinbased_ctls_high |=
3511 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3512 PIN_BASED_VMX_PREEMPTION_TIMER;
3515 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
3516 msrs->exit_ctls_low,
3517 msrs->exit_ctls_high);
3518 msrs->exit_ctls_low =
3519 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3521 msrs->exit_ctls_high &=
3522 #ifdef CONFIG_X86_64
3523 VM_EXIT_HOST_ADDR_SPACE_SIZE |
3525 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
3526 msrs->exit_ctls_high |=
3527 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
3528 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
3529 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
3531 if (kvm_mpx_supported())
3532 msrs->exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
3534 /* We support free control of debug control saving. */
3535 msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
3537 /* entry controls */
3538 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
3539 msrs->entry_ctls_low,
3540 msrs->entry_ctls_high);
3541 msrs->entry_ctls_low =
3542 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3543 msrs->entry_ctls_high &=
3544 #ifdef CONFIG_X86_64
3545 VM_ENTRY_IA32E_MODE |
3547 VM_ENTRY_LOAD_IA32_PAT;
3548 msrs->entry_ctls_high |=
3549 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
3550 if (kvm_mpx_supported())
3551 msrs->entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
3553 /* We support free control of debug control loading. */
3554 msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
3556 /* cpu-based controls */
3557 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
3558 msrs->procbased_ctls_low,
3559 msrs->procbased_ctls_high);
3560 msrs->procbased_ctls_low =
3561 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3562 msrs->procbased_ctls_high &=
3563 CPU_BASED_VIRTUAL_INTR_PENDING |
3564 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
3565 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
3566 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
3567 CPU_BASED_CR3_STORE_EXITING |
3568 #ifdef CONFIG_X86_64
3569 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
3571 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
3572 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
3573 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
3574 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
3575 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3577 * We can allow some features even when not supported by the
3578 * hardware. For example, L1 can specify an MSR bitmap - and we
3579 * can use it to avoid exits to L1 - even when L0 runs L2
3580 * without MSR bitmaps.
3582 msrs->procbased_ctls_high |=
3583 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3584 CPU_BASED_USE_MSR_BITMAPS;
3586 /* We support free control of CR3 access interception. */
3587 msrs->procbased_ctls_low &=
3588 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
3591 * secondary cpu-based controls. Do not include those that
3592 * depend on CPUID bits, they are added later by vmx_cpuid_update.
3594 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
3595 msrs->secondary_ctls_low,
3596 msrs->secondary_ctls_high);
3597 msrs->secondary_ctls_low = 0;
3598 msrs->secondary_ctls_high &=
3599 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3600 SECONDARY_EXEC_DESC |
3601 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3602 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3603 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3604 SECONDARY_EXEC_WBINVD_EXITING;
3606 * We can emulate "VMCS shadowing," even if the hardware
3607 * doesn't support it.
3609 msrs->secondary_ctls_high |=
3610 SECONDARY_EXEC_SHADOW_VMCS;
3613 /* nested EPT: emulate EPT also to L1 */
3614 msrs->secondary_ctls_high |=
3615 SECONDARY_EXEC_ENABLE_EPT;
3616 msrs->ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
3617 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
3618 if (cpu_has_vmx_ept_execute_only())
3620 VMX_EPT_EXECUTE_ONLY_BIT;
3621 msrs->ept_caps &= vmx_capability.ept;
3622 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
3623 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
3624 VMX_EPT_1GB_PAGE_BIT;
3625 if (enable_ept_ad_bits) {
3626 msrs->secondary_ctls_high |=
3627 SECONDARY_EXEC_ENABLE_PML;
3628 msrs->ept_caps |= VMX_EPT_AD_BIT;
3632 if (cpu_has_vmx_vmfunc()) {
3633 msrs->secondary_ctls_high |=
3634 SECONDARY_EXEC_ENABLE_VMFUNC;
3636 * Advertise EPTP switching unconditionally
3637 * since we emulate it
3640 msrs->vmfunc_controls =
3641 VMX_VMFUNC_EPTP_SWITCHING;
3645 * Old versions of KVM use the single-context version without
3646 * checking for support, so declare that it is supported even
3647 * though it is treated as global context. The alternative is
3648 * not failing the single-context invvpid, and it is worse.
3651 msrs->secondary_ctls_high |=
3652 SECONDARY_EXEC_ENABLE_VPID;
3653 msrs->vpid_caps = VMX_VPID_INVVPID_BIT |
3654 VMX_VPID_EXTENT_SUPPORTED_MASK;
3657 if (enable_unrestricted_guest)
3658 msrs->secondary_ctls_high |=
3659 SECONDARY_EXEC_UNRESTRICTED_GUEST;
3661 /* miscellaneous data */
3662 rdmsr(MSR_IA32_VMX_MISC,
3665 msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA;
3667 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
3668 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
3669 VMX_MISC_ACTIVITY_HLT;
3670 msrs->misc_high = 0;
3673 * This MSR reports some information about VMX support. We
3674 * should return information about the VMX we emulate for the
3675 * guest, and the VMCS structure we give it - not about the
3676 * VMX support of the underlying hardware.
3680 VMX_BASIC_TRUE_CTLS |
3681 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
3682 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
3684 if (cpu_has_vmx_basic_inout())
3685 msrs->basic |= VMX_BASIC_INOUT;
3688 * These MSRs specify bits which the guest must keep fixed on
3689 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
3690 * We picked the standard core2 setting.
3692 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
3693 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
3694 msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON;
3695 msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
3697 /* These MSRs specify bits which the guest must keep fixed off. */
3698 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
3699 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
3701 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
3702 msrs->vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1;
3706 * if fixed0[i] == 1: val[i] must be 1
3707 * if fixed1[i] == 0: val[i] must be 0
3709 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
3711 return ((val & fixed1) | fixed0) == val;
3714 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
3716 return fixed_bits_valid(control, low, high);
3719 static inline u64 vmx_control_msr(u32 low, u32 high)
3721 return low | ((u64)high << 32);
3724 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
3729 return (superset | subset) == superset;
3732 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
3734 const u64 feature_and_reserved =
3735 /* feature (except bit 48; see below) */
3736 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
3738 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
3739 u64 vmx_basic = vmx->nested.msrs.basic;
3741 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
3745 * KVM does not emulate a version of VMX that constrains physical
3746 * addresses of VMX structures (e.g. VMCS) to 32-bits.
3748 if (data & BIT_ULL(48))
3751 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
3752 vmx_basic_vmcs_revision_id(data))
3755 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
3758 vmx->nested.msrs.basic = data;
3763 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3768 switch (msr_index) {
3769 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3770 lowp = &vmx->nested.msrs.pinbased_ctls_low;
3771 highp = &vmx->nested.msrs.pinbased_ctls_high;
3773 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3774 lowp = &vmx->nested.msrs.procbased_ctls_low;
3775 highp = &vmx->nested.msrs.procbased_ctls_high;
3777 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3778 lowp = &vmx->nested.msrs.exit_ctls_low;
3779 highp = &vmx->nested.msrs.exit_ctls_high;
3781 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3782 lowp = &vmx->nested.msrs.entry_ctls_low;
3783 highp = &vmx->nested.msrs.entry_ctls_high;
3785 case MSR_IA32_VMX_PROCBASED_CTLS2:
3786 lowp = &vmx->nested.msrs.secondary_ctls_low;
3787 highp = &vmx->nested.msrs.secondary_ctls_high;
3793 supported = vmx_control_msr(*lowp, *highp);
3795 /* Check must-be-1 bits are still 1. */
3796 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3799 /* Check must-be-0 bits are still 0. */
3800 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3804 *highp = data >> 32;
3808 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3810 const u64 feature_and_reserved_bits =
3812 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3813 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3815 GENMASK_ULL(13, 9) | BIT_ULL(31);
3818 vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
3819 vmx->nested.msrs.misc_high);
3821 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3824 if ((vmx->nested.msrs.pinbased_ctls_high &
3825 PIN_BASED_VMX_PREEMPTION_TIMER) &&
3826 vmx_misc_preemption_timer_rate(data) !=
3827 vmx_misc_preemption_timer_rate(vmx_misc))
3830 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3833 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3836 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3839 vmx->nested.msrs.misc_low = data;
3840 vmx->nested.msrs.misc_high = data >> 32;
3843 * If L1 has read-only VM-exit information fields, use the
3844 * less permissive vmx_vmwrite_bitmap to specify write
3845 * permissions for the shadow VMCS.
3847 if (enable_shadow_vmcs && !nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
3848 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
3853 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3855 u64 vmx_ept_vpid_cap;
3857 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps,
3858 vmx->nested.msrs.vpid_caps);
3860 /* Every bit is either reserved or a feature bit. */
3861 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3864 vmx->nested.msrs.ept_caps = data;
3865 vmx->nested.msrs.vpid_caps = data >> 32;
3869 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3873 switch (msr_index) {
3874 case MSR_IA32_VMX_CR0_FIXED0:
3875 msr = &vmx->nested.msrs.cr0_fixed0;
3877 case MSR_IA32_VMX_CR4_FIXED0:
3878 msr = &vmx->nested.msrs.cr4_fixed0;
3885 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3886 * must be 1 in the restored value.
3888 if (!is_bitwise_subset(data, *msr, -1ULL))
3896 * Called when userspace is restoring VMX MSRs.
3898 * Returns 0 on success, non-0 otherwise.
3900 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3902 struct vcpu_vmx *vmx = to_vmx(vcpu);
3905 * Don't allow changes to the VMX capability MSRs while the vCPU
3906 * is in VMX operation.
3908 if (vmx->nested.vmxon)
3911 switch (msr_index) {
3912 case MSR_IA32_VMX_BASIC:
3913 return vmx_restore_vmx_basic(vmx, data);
3914 case MSR_IA32_VMX_PINBASED_CTLS:
3915 case MSR_IA32_VMX_PROCBASED_CTLS:
3916 case MSR_IA32_VMX_EXIT_CTLS:
3917 case MSR_IA32_VMX_ENTRY_CTLS:
3919 * The "non-true" VMX capability MSRs are generated from the
3920 * "true" MSRs, so we do not support restoring them directly.
3922 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3923 * should restore the "true" MSRs with the must-be-1 bits
3924 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3925 * DEFAULT SETTINGS".
3928 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3929 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3930 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3931 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3932 case MSR_IA32_VMX_PROCBASED_CTLS2:
3933 return vmx_restore_control_msr(vmx, msr_index, data);
3934 case MSR_IA32_VMX_MISC:
3935 return vmx_restore_vmx_misc(vmx, data);
3936 case MSR_IA32_VMX_CR0_FIXED0:
3937 case MSR_IA32_VMX_CR4_FIXED0:
3938 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3939 case MSR_IA32_VMX_CR0_FIXED1:
3940 case MSR_IA32_VMX_CR4_FIXED1:
3942 * These MSRs are generated based on the vCPU's CPUID, so we
3943 * do not support restoring them directly.
3946 case MSR_IA32_VMX_EPT_VPID_CAP:
3947 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3948 case MSR_IA32_VMX_VMCS_ENUM:
3949 vmx->nested.msrs.vmcs_enum = data;
3953 * The rest of the VMX capability MSRs do not support restore.
3959 /* Returns 0 on success, non-0 otherwise. */
3960 static int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata)
3962 switch (msr_index) {
3963 case MSR_IA32_VMX_BASIC:
3964 *pdata = msrs->basic;
3966 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3967 case MSR_IA32_VMX_PINBASED_CTLS:
3968 *pdata = vmx_control_msr(
3969 msrs->pinbased_ctls_low,
3970 msrs->pinbased_ctls_high);
3971 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3972 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3974 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3975 case MSR_IA32_VMX_PROCBASED_CTLS:
3976 *pdata = vmx_control_msr(
3977 msrs->procbased_ctls_low,
3978 msrs->procbased_ctls_high);
3979 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3980 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3982 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3983 case MSR_IA32_VMX_EXIT_CTLS:
3984 *pdata = vmx_control_msr(
3985 msrs->exit_ctls_low,
3986 msrs->exit_ctls_high);
3987 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3988 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3990 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3991 case MSR_IA32_VMX_ENTRY_CTLS:
3992 *pdata = vmx_control_msr(
3993 msrs->entry_ctls_low,
3994 msrs->entry_ctls_high);
3995 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3996 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3998 case MSR_IA32_VMX_MISC:
3999 *pdata = vmx_control_msr(
4003 case MSR_IA32_VMX_CR0_FIXED0:
4004 *pdata = msrs->cr0_fixed0;
4006 case MSR_IA32_VMX_CR0_FIXED1:
4007 *pdata = msrs->cr0_fixed1;
4009 case MSR_IA32_VMX_CR4_FIXED0:
4010 *pdata = msrs->cr4_fixed0;
4012 case MSR_IA32_VMX_CR4_FIXED1:
4013 *pdata = msrs->cr4_fixed1;
4015 case MSR_IA32_VMX_VMCS_ENUM:
4016 *pdata = msrs->vmcs_enum;
4018 case MSR_IA32_VMX_PROCBASED_CTLS2:
4019 *pdata = vmx_control_msr(
4020 msrs->secondary_ctls_low,
4021 msrs->secondary_ctls_high);
4023 case MSR_IA32_VMX_EPT_VPID_CAP:
4024 *pdata = msrs->ept_caps |
4025 ((u64)msrs->vpid_caps << 32);
4027 case MSR_IA32_VMX_VMFUNC:
4028 *pdata = msrs->vmfunc_controls;
4037 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
4040 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
4042 return !(val & ~valid_bits);
4045 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
4047 switch (msr->index) {
4048 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4051 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
4060 * Reads an msr value (of 'msr_index') into 'pdata'.
4061 * Returns 0 on success, non-0 otherwise.
4062 * Assumes vcpu_load() was already called.
4064 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4066 struct vcpu_vmx *vmx = to_vmx(vcpu);
4067 struct shared_msr_entry *msr;
4069 switch (msr_info->index) {
4070 #ifdef CONFIG_X86_64
4072 msr_info->data = vmcs_readl(GUEST_FS_BASE);
4075 msr_info->data = vmcs_readl(GUEST_GS_BASE);
4077 case MSR_KERNEL_GS_BASE:
4078 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
4082 return kvm_get_msr_common(vcpu, msr_info);
4083 case MSR_IA32_SPEC_CTRL:
4084 if (!msr_info->host_initiated &&
4085 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
4088 msr_info->data = to_vmx(vcpu)->spec_ctrl;
4090 case MSR_IA32_ARCH_CAPABILITIES:
4091 if (!msr_info->host_initiated &&
4092 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
4094 msr_info->data = to_vmx(vcpu)->arch_capabilities;
4096 case MSR_IA32_SYSENTER_CS:
4097 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
4099 case MSR_IA32_SYSENTER_EIP:
4100 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
4102 case MSR_IA32_SYSENTER_ESP:
4103 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
4105 case MSR_IA32_BNDCFGS:
4106 if (!kvm_mpx_supported() ||
4107 (!msr_info->host_initiated &&
4108 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
4110 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
4112 case MSR_IA32_MCG_EXT_CTL:
4113 if (!msr_info->host_initiated &&
4114 !(vmx->msr_ia32_feature_control &
4115 FEATURE_CONTROL_LMCE))
4117 msr_info->data = vcpu->arch.mcg_ext_ctl;
4119 case MSR_IA32_FEATURE_CONTROL:
4120 msr_info->data = vmx->msr_ia32_feature_control;
4122 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4123 if (!nested_vmx_allowed(vcpu))
4125 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
4128 if (!vmx_xsaves_supported())
4130 msr_info->data = vcpu->arch.ia32_xss;
4133 if (!msr_info->host_initiated &&
4134 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4136 /* Otherwise falls through */
4138 msr = find_msr_entry(vmx, msr_info->index);
4140 msr_info->data = msr->data;
4143 return kvm_get_msr_common(vcpu, msr_info);
4149 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
4152 * Writes msr value into into the appropriate "register".
4153 * Returns 0 on success, non-0 otherwise.
4154 * Assumes vcpu_load() was already called.
4156 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4158 struct vcpu_vmx *vmx = to_vmx(vcpu);
4159 struct shared_msr_entry *msr;
4161 u32 msr_index = msr_info->index;
4162 u64 data = msr_info->data;
4164 switch (msr_index) {
4166 ret = kvm_set_msr_common(vcpu, msr_info);
4168 #ifdef CONFIG_X86_64
4170 vmx_segment_cache_clear(vmx);
4171 vmcs_writel(GUEST_FS_BASE, data);
4174 vmx_segment_cache_clear(vmx);
4175 vmcs_writel(GUEST_GS_BASE, data);
4177 case MSR_KERNEL_GS_BASE:
4178 vmx_write_guest_kernel_gs_base(vmx, data);
4181 case MSR_IA32_SYSENTER_CS:
4182 vmcs_write32(GUEST_SYSENTER_CS, data);
4184 case MSR_IA32_SYSENTER_EIP:
4185 vmcs_writel(GUEST_SYSENTER_EIP, data);
4187 case MSR_IA32_SYSENTER_ESP:
4188 vmcs_writel(GUEST_SYSENTER_ESP, data);
4190 case MSR_IA32_BNDCFGS:
4191 if (!kvm_mpx_supported() ||
4192 (!msr_info->host_initiated &&
4193 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
4195 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
4196 (data & MSR_IA32_BNDCFGS_RSVD))
4198 vmcs_write64(GUEST_BNDCFGS, data);
4200 case MSR_IA32_SPEC_CTRL:
4201 if (!msr_info->host_initiated &&
4202 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
4205 /* The STIBP bit doesn't fault even if it's not advertised */
4206 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4209 vmx->spec_ctrl = data;
4216 * When it's written (to non-zero) for the first time, pass
4220 * The handling of the MSR bitmap for L2 guests is done in
4221 * nested_vmx_merge_msr_bitmap. We should not touch the
4222 * vmcs02.msr_bitmap here since it gets completely overwritten
4223 * in the merging. We update the vmcs01 here for L1 as well
4224 * since it will end up touching the MSR anyway now.
4226 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
4230 case MSR_IA32_PRED_CMD:
4231 if (!msr_info->host_initiated &&
4232 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
4235 if (data & ~PRED_CMD_IBPB)
4241 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4245 * When it's written (to non-zero) for the first time, pass
4249 * The handling of the MSR bitmap for L2 guests is done in
4250 * nested_vmx_merge_msr_bitmap. We should not touch the
4251 * vmcs02.msr_bitmap here since it gets completely overwritten
4254 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
4257 case MSR_IA32_ARCH_CAPABILITIES:
4258 if (!msr_info->host_initiated)
4260 vmx->arch_capabilities = data;
4262 case MSR_IA32_CR_PAT:
4263 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4264 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4266 vmcs_write64(GUEST_IA32_PAT, data);
4267 vcpu->arch.pat = data;
4270 ret = kvm_set_msr_common(vcpu, msr_info);
4272 case MSR_IA32_TSC_ADJUST:
4273 ret = kvm_set_msr_common(vcpu, msr_info);
4275 case MSR_IA32_MCG_EXT_CTL:
4276 if ((!msr_info->host_initiated &&
4277 !(to_vmx(vcpu)->msr_ia32_feature_control &
4278 FEATURE_CONTROL_LMCE)) ||
4279 (data & ~MCG_EXT_CTL_LMCE_EN))
4281 vcpu->arch.mcg_ext_ctl = data;
4283 case MSR_IA32_FEATURE_CONTROL:
4284 if (!vmx_feature_control_msr_valid(vcpu, data) ||
4285 (to_vmx(vcpu)->msr_ia32_feature_control &
4286 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
4288 vmx->msr_ia32_feature_control = data;
4289 if (msr_info->host_initiated && data == 0)
4290 vmx_leave_nested(vcpu);
4292 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4293 if (!msr_info->host_initiated)
4294 return 1; /* they are read-only */
4295 if (!nested_vmx_allowed(vcpu))
4297 return vmx_set_vmx_msr(vcpu, msr_index, data);
4299 if (!vmx_xsaves_supported())
4302 * The only supported bit as of Skylake is bit 8, but
4303 * it is not supported on KVM.
4307 vcpu->arch.ia32_xss = data;
4308 if (vcpu->arch.ia32_xss != host_xss)
4309 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
4310 vcpu->arch.ia32_xss, host_xss, false);
4312 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
4315 if (!msr_info->host_initiated &&
4316 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4318 /* Check reserved bit, higher 32 bits should be zero */
4319 if ((data >> 32) != 0)
4321 /* Otherwise falls through */
4323 msr = find_msr_entry(vmx, msr_index);
4325 u64 old_msr_data = msr->data;
4327 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
4329 ret = kvm_set_shared_msr(msr->index, msr->data,
4333 msr->data = old_msr_data;
4337 ret = kvm_set_msr_common(vcpu, msr_info);
4343 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
4345 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
4348 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
4351 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
4353 case VCPU_EXREG_PDPTR:
4355 ept_save_pdptrs(vcpu);
4362 static __init int cpu_has_kvm_support(void)
4364 return cpu_has_vmx();
4367 static __init int vmx_disabled_by_bios(void)
4371 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
4372 if (msr & FEATURE_CONTROL_LOCKED) {
4373 /* launched w/ TXT and VMX disabled */
4374 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4377 /* launched w/o TXT and VMX only enabled w/ TXT */
4378 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4379 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4380 && !tboot_enabled()) {
4381 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
4382 "activate TXT before enabling KVM\n");
4385 /* launched w/o TXT and VMX disabled */
4386 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4387 && !tboot_enabled())
4394 static void kvm_cpu_vmxon(u64 addr)
4396 cr4_set_bits(X86_CR4_VMXE);
4397 intel_pt_handle_vmx(1);
4399 asm volatile (ASM_VMX_VMXON_RAX
4400 : : "a"(&addr), "m"(addr)
4404 static int hardware_enable(void)
4406 int cpu = raw_smp_processor_id();
4407 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
4410 if (cr4_read_shadow() & X86_CR4_VMXE)
4414 * This can happen if we hot-added a CPU but failed to allocate
4415 * VP assist page for it.
4417 if (static_branch_unlikely(&enable_evmcs) &&
4418 !hv_get_vp_assist_page(cpu))
4421 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
4422 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
4423 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
4426 * Now we can enable the vmclear operation in kdump
4427 * since the loaded_vmcss_on_cpu list on this cpu
4428 * has been initialized.
4430 * Though the cpu is not in VMX operation now, there
4431 * is no problem to enable the vmclear operation
4432 * for the loaded_vmcss_on_cpu list is empty!
4434 crash_enable_local_vmclear(cpu);
4436 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
4438 test_bits = FEATURE_CONTROL_LOCKED;
4439 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
4440 if (tboot_enabled())
4441 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
4443 if ((old & test_bits) != test_bits) {
4444 /* enable and lock */
4445 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
4447 kvm_cpu_vmxon(phys_addr);
4454 static void vmclear_local_loaded_vmcss(void)
4456 int cpu = raw_smp_processor_id();
4457 struct loaded_vmcs *v, *n;
4459 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
4460 loaded_vmcss_on_cpu_link)
4461 __loaded_vmcs_clear(v);
4465 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
4468 static void kvm_cpu_vmxoff(void)
4470 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
4472 intel_pt_handle_vmx(0);
4473 cr4_clear_bits(X86_CR4_VMXE);
4476 static void hardware_disable(void)
4478 vmclear_local_loaded_vmcss();
4482 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
4483 u32 msr, u32 *result)
4485 u32 vmx_msr_low, vmx_msr_high;
4486 u32 ctl = ctl_min | ctl_opt;
4488 rdmsr(msr, vmx_msr_low, vmx_msr_high);
4490 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
4491 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
4493 /* Ensure minimum (required) set of control bits are supported. */
4501 static __init bool allow_1_setting(u32 msr, u32 ctl)
4503 u32 vmx_msr_low, vmx_msr_high;
4505 rdmsr(msr, vmx_msr_low, vmx_msr_high);
4506 return vmx_msr_high & ctl;
4509 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
4511 u32 vmx_msr_low, vmx_msr_high;
4512 u32 min, opt, min2, opt2;
4513 u32 _pin_based_exec_control = 0;
4514 u32 _cpu_based_exec_control = 0;
4515 u32 _cpu_based_2nd_exec_control = 0;
4516 u32 _vmexit_control = 0;
4517 u32 _vmentry_control = 0;
4519 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
4520 min = CPU_BASED_HLT_EXITING |
4521 #ifdef CONFIG_X86_64
4522 CPU_BASED_CR8_LOAD_EXITING |
4523 CPU_BASED_CR8_STORE_EXITING |
4525 CPU_BASED_CR3_LOAD_EXITING |
4526 CPU_BASED_CR3_STORE_EXITING |
4527 CPU_BASED_UNCOND_IO_EXITING |
4528 CPU_BASED_MOV_DR_EXITING |
4529 CPU_BASED_USE_TSC_OFFSETING |
4530 CPU_BASED_MWAIT_EXITING |
4531 CPU_BASED_MONITOR_EXITING |
4532 CPU_BASED_INVLPG_EXITING |
4533 CPU_BASED_RDPMC_EXITING;
4535 opt = CPU_BASED_TPR_SHADOW |
4536 CPU_BASED_USE_MSR_BITMAPS |
4537 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
4538 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
4539 &_cpu_based_exec_control) < 0)
4541 #ifdef CONFIG_X86_64
4542 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4543 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
4544 ~CPU_BASED_CR8_STORE_EXITING;
4546 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
4548 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4549 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4550 SECONDARY_EXEC_WBINVD_EXITING |
4551 SECONDARY_EXEC_ENABLE_VPID |
4552 SECONDARY_EXEC_ENABLE_EPT |
4553 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4554 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
4555 SECONDARY_EXEC_DESC |
4556 SECONDARY_EXEC_RDTSCP |
4557 SECONDARY_EXEC_ENABLE_INVPCID |
4558 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4559 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4560 SECONDARY_EXEC_SHADOW_VMCS |
4561 SECONDARY_EXEC_XSAVES |
4562 SECONDARY_EXEC_RDSEED_EXITING |
4563 SECONDARY_EXEC_RDRAND_EXITING |
4564 SECONDARY_EXEC_ENABLE_PML |
4565 SECONDARY_EXEC_TSC_SCALING |
4566 SECONDARY_EXEC_ENABLE_VMFUNC |
4567 SECONDARY_EXEC_ENCLS_EXITING;
4568 if (adjust_vmx_controls(min2, opt2,
4569 MSR_IA32_VMX_PROCBASED_CTLS2,
4570 &_cpu_based_2nd_exec_control) < 0)
4573 #ifndef CONFIG_X86_64
4574 if (!(_cpu_based_2nd_exec_control &
4575 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
4576 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
4579 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4580 _cpu_based_2nd_exec_control &= ~(
4581 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4582 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4583 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4585 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
4586 &vmx_capability.ept, &vmx_capability.vpid);
4588 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
4589 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
4591 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
4592 CPU_BASED_CR3_STORE_EXITING |
4593 CPU_BASED_INVLPG_EXITING);
4594 } else if (vmx_capability.ept) {
4595 vmx_capability.ept = 0;
4596 pr_warn_once("EPT CAP should not exist if not support "
4597 "1-setting enable EPT VM-execution control\n");
4599 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
4600 vmx_capability.vpid) {
4601 vmx_capability.vpid = 0;
4602 pr_warn_once("VPID CAP should not exist if not support "
4603 "1-setting enable VPID VM-execution control\n");
4606 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
4607 #ifdef CONFIG_X86_64
4608 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
4610 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
4611 VM_EXIT_CLEAR_BNDCFGS;
4612 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
4613 &_vmexit_control) < 0)
4616 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
4617 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
4618 PIN_BASED_VMX_PREEMPTION_TIMER;
4619 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
4620 &_pin_based_exec_control) < 0)
4623 if (cpu_has_broken_vmx_preemption_timer())
4624 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4625 if (!(_cpu_based_2nd_exec_control &
4626 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
4627 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
4629 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
4630 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
4631 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
4632 &_vmentry_control) < 0)
4635 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
4637 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
4638 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
4641 #ifdef CONFIG_X86_64
4642 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
4643 if (vmx_msr_high & (1u<<16))
4647 /* Require Write-Back (WB) memory type for VMCS accesses. */
4648 if (((vmx_msr_high >> 18) & 15) != 6)
4651 vmcs_conf->size = vmx_msr_high & 0x1fff;
4652 vmcs_conf->order = get_order(vmcs_conf->size);
4653 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
4655 vmcs_conf->revision_id = vmx_msr_low;
4657 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
4658 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
4659 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
4660 vmcs_conf->vmexit_ctrl = _vmexit_control;
4661 vmcs_conf->vmentry_ctrl = _vmentry_control;
4663 if (static_branch_unlikely(&enable_evmcs))
4664 evmcs_sanitize_exec_ctrls(vmcs_conf);
4666 cpu_has_load_ia32_efer =
4667 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4668 VM_ENTRY_LOAD_IA32_EFER)
4669 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4670 VM_EXIT_LOAD_IA32_EFER);
4672 cpu_has_load_perf_global_ctrl =
4673 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4674 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
4675 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4676 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
4679 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
4680 * but due to errata below it can't be used. Workaround is to use
4681 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
4683 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
4688 * BC86,AAY89,BD102 (model 44)
4692 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
4693 switch (boot_cpu_data.x86_model) {
4699 cpu_has_load_perf_global_ctrl = false;
4700 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
4701 "does not work properly. Using workaround\n");
4708 if (boot_cpu_has(X86_FEATURE_XSAVES))
4709 rdmsrl(MSR_IA32_XSS, host_xss);
4714 static struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu)
4716 int node = cpu_to_node(cpu);
4720 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
4723 vmcs = page_address(pages);
4724 memset(vmcs, 0, vmcs_config.size);
4726 /* KVM supports Enlightened VMCS v1 only */
4727 if (static_branch_unlikely(&enable_evmcs))
4728 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
4730 vmcs->hdr.revision_id = vmcs_config.revision_id;
4733 vmcs->hdr.shadow_vmcs = 1;
4737 static void free_vmcs(struct vmcs *vmcs)
4739 free_pages((unsigned long)vmcs, vmcs_config.order);
4743 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
4745 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4747 if (!loaded_vmcs->vmcs)
4749 loaded_vmcs_clear(loaded_vmcs);
4750 free_vmcs(loaded_vmcs->vmcs);
4751 loaded_vmcs->vmcs = NULL;
4752 if (loaded_vmcs->msr_bitmap)
4753 free_page((unsigned long)loaded_vmcs->msr_bitmap);
4754 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
4757 static struct vmcs *alloc_vmcs(bool shadow)
4759 return alloc_vmcs_cpu(shadow, raw_smp_processor_id());
4762 static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4764 loaded_vmcs->vmcs = alloc_vmcs(false);
4765 if (!loaded_vmcs->vmcs)
4768 loaded_vmcs->shadow_vmcs = NULL;
4769 loaded_vmcs_init(loaded_vmcs);
4771 if (cpu_has_vmx_msr_bitmap()) {
4772 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
4773 if (!loaded_vmcs->msr_bitmap)
4775 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
4777 if (IS_ENABLED(CONFIG_HYPERV) &&
4778 static_branch_unlikely(&enable_evmcs) &&
4779 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
4780 struct hv_enlightened_vmcs *evmcs =
4781 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
4783 evmcs->hv_enlightenments_control.msr_bitmap = 1;
4787 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
4792 free_loaded_vmcs(loaded_vmcs);
4796 static void free_kvm_area(void)
4800 for_each_possible_cpu(cpu) {
4801 free_vmcs(per_cpu(vmxarea, cpu));
4802 per_cpu(vmxarea, cpu) = NULL;
4806 enum vmcs_field_width {
4807 VMCS_FIELD_WIDTH_U16 = 0,
4808 VMCS_FIELD_WIDTH_U64 = 1,
4809 VMCS_FIELD_WIDTH_U32 = 2,
4810 VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
4813 static inline int vmcs_field_width(unsigned long field)
4815 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
4816 return VMCS_FIELD_WIDTH_U32;
4817 return (field >> 13) & 0x3 ;
4820 static inline int vmcs_field_readonly(unsigned long field)
4822 return (((field >> 10) & 0x3) == 1);
4825 static void init_vmcs_shadow_fields(void)
4829 for (i = j = 0; i < max_shadow_read_only_fields; i++) {
4830 u16 field = shadow_read_only_fields[i];
4831 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4832 (i + 1 == max_shadow_read_only_fields ||
4833 shadow_read_only_fields[i + 1] != field + 1))
4834 pr_err("Missing field from shadow_read_only_field %x\n",
4837 clear_bit(field, vmx_vmread_bitmap);
4838 #ifdef CONFIG_X86_64
4843 shadow_read_only_fields[j] = field;
4846 max_shadow_read_only_fields = j;
4848 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
4849 u16 field = shadow_read_write_fields[i];
4850 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4851 (i + 1 == max_shadow_read_write_fields ||
4852 shadow_read_write_fields[i + 1] != field + 1))
4853 pr_err("Missing field from shadow_read_write_field %x\n",
4857 * PML and the preemption timer can be emulated, but the
4858 * processor cannot vmwrite to fields that don't exist
4862 case GUEST_PML_INDEX:
4863 if (!cpu_has_vmx_pml())
4866 case VMX_PREEMPTION_TIMER_VALUE:
4867 if (!cpu_has_vmx_preemption_timer())
4870 case GUEST_INTR_STATUS:
4871 if (!cpu_has_vmx_apicv())
4878 clear_bit(field, vmx_vmwrite_bitmap);
4879 clear_bit(field, vmx_vmread_bitmap);
4880 #ifdef CONFIG_X86_64
4885 shadow_read_write_fields[j] = field;
4888 max_shadow_read_write_fields = j;
4891 static __init int alloc_kvm_area(void)
4895 for_each_possible_cpu(cpu) {
4898 vmcs = alloc_vmcs_cpu(false, cpu);
4905 * When eVMCS is enabled, alloc_vmcs_cpu() sets
4906 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
4907 * revision_id reported by MSR_IA32_VMX_BASIC.
4909 * However, even though not explictly documented by
4910 * TLFS, VMXArea passed as VMXON argument should
4911 * still be marked with revision_id reported by
4914 if (static_branch_unlikely(&enable_evmcs))
4915 vmcs->hdr.revision_id = vmcs_config.revision_id;
4917 per_cpu(vmxarea, cpu) = vmcs;
4922 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
4923 struct kvm_segment *save)
4925 if (!emulate_invalid_guest_state) {
4927 * CS and SS RPL should be equal during guest entry according
4928 * to VMX spec, but in reality it is not always so. Since vcpu
4929 * is in the middle of the transition from real mode to
4930 * protected mode it is safe to assume that RPL 0 is a good
4933 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4934 save->selector &= ~SEGMENT_RPL_MASK;
4935 save->dpl = save->selector & SEGMENT_RPL_MASK;
4938 vmx_set_segment(vcpu, save, seg);
4941 static void enter_pmode(struct kvm_vcpu *vcpu)
4943 unsigned long flags;
4944 struct vcpu_vmx *vmx = to_vmx(vcpu);
4947 * Update real mode segment cache. It may be not up-to-date if sement
4948 * register was written while vcpu was in a guest mode.
4950 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4951 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4952 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4953 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4954 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4955 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4957 vmx->rmode.vm86_active = 0;
4959 vmx_segment_cache_clear(vmx);
4961 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4963 flags = vmcs_readl(GUEST_RFLAGS);
4964 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
4965 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
4966 vmcs_writel(GUEST_RFLAGS, flags);
4968 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
4969 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4971 update_exception_bitmap(vcpu);
4973 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4974 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4975 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4976 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4977 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4978 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4981 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4983 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4984 struct kvm_segment var = *save;
4987 if (seg == VCPU_SREG_CS)
4990 if (!emulate_invalid_guest_state) {
4991 var.selector = var.base >> 4;
4992 var.base = var.base & 0xffff0;
5002 if (save->base & 0xf)
5003 printk_once(KERN_WARNING "kvm: segment base is not "
5004 "paragraph aligned when entering "
5005 "protected mode (seg=%d)", seg);
5008 vmcs_write16(sf->selector, var.selector);
5009 vmcs_writel(sf->base, var.base);
5010 vmcs_write32(sf->limit, var.limit);
5011 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
5014 static void enter_rmode(struct kvm_vcpu *vcpu)
5016 unsigned long flags;
5017 struct vcpu_vmx *vmx = to_vmx(vcpu);
5018 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
5020 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
5021 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
5022 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
5023 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
5024 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
5025 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
5026 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
5028 vmx->rmode.vm86_active = 1;
5031 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
5032 * vcpu. Warn the user that an update is overdue.
5034 if (!kvm_vmx->tss_addr)
5035 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
5036 "called before entering vcpu\n");
5038 vmx_segment_cache_clear(vmx);
5040 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
5041 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
5042 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5044 flags = vmcs_readl(GUEST_RFLAGS);
5045 vmx->rmode.save_rflags = flags;
5047 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
5049 vmcs_writel(GUEST_RFLAGS, flags);
5050 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
5051 update_exception_bitmap(vcpu);
5053 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
5054 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
5055 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
5056 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
5057 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
5058 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
5060 kvm_mmu_reset_context(vcpu);
5063 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
5065 struct vcpu_vmx *vmx = to_vmx(vcpu);
5066 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
5072 * MSR_KERNEL_GS_BASE is not intercepted when the guest is in
5073 * 64-bit mode as a 64-bit kernel may frequently access the
5074 * MSR. This means we need to manually save/restore the MSR
5075 * when switching between guest and host state, but only if
5076 * the guest is in 64-bit mode. Sync our cached value if the
5077 * guest is transitioning to 32-bit mode and the CPU contains
5078 * guest state, i.e. the cache is stale.
5080 #ifdef CONFIG_X86_64
5081 if (!(efer & EFER_LMA))
5082 (void)vmx_read_guest_kernel_gs_base(vmx);
5084 vcpu->arch.efer = efer;
5085 if (efer & EFER_LMA) {
5086 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
5089 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
5091 msr->data = efer & ~EFER_LME;
5096 #ifdef CONFIG_X86_64
5098 static void enter_lmode(struct kvm_vcpu *vcpu)
5102 vmx_segment_cache_clear(to_vmx(vcpu));
5104 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
5105 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
5106 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
5108 vmcs_write32(GUEST_TR_AR_BYTES,
5109 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
5110 | VMX_AR_TYPE_BUSY_64_TSS);
5112 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
5115 static void exit_lmode(struct kvm_vcpu *vcpu)
5117 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
5118 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
5123 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
5124 bool invalidate_gpa)
5126 if (enable_ept && (invalidate_gpa || !enable_vpid)) {
5127 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
5129 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
5131 vpid_sync_context(vpid);
5135 static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5137 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
5140 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
5142 int vpid = to_vmx(vcpu)->vpid;
5144 if (!vpid_sync_vcpu_addr(vpid, addr))
5145 vpid_sync_context(vpid);
5148 * If VPIDs are not supported or enabled, then the above is a no-op.
5149 * But we don't really need a TLB flush in that case anyway, because
5150 * each VM entry/exit includes an implicit flush when VPID is 0.
5154 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
5156 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
5158 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
5159 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
5162 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
5164 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
5165 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
5166 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
5169 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
5171 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
5173 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
5174 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
5177 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
5179 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
5181 if (!test_bit(VCPU_EXREG_PDPTR,
5182 (unsigned long *)&vcpu->arch.regs_dirty))
5185 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
5186 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
5187 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
5188 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
5189 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
5193 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
5195 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
5197 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
5198 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
5199 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
5200 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
5201 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
5204 __set_bit(VCPU_EXREG_PDPTR,
5205 (unsigned long *)&vcpu->arch.regs_avail);
5206 __set_bit(VCPU_EXREG_PDPTR,
5207 (unsigned long *)&vcpu->arch.regs_dirty);
5210 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5212 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
5213 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
5214 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5216 if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
5217 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5218 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5219 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5221 return fixed_bits_valid(val, fixed0, fixed1);
5224 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5226 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
5227 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
5229 return fixed_bits_valid(val, fixed0, fixed1);
5232 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
5234 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0;
5235 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1;
5237 return fixed_bits_valid(val, fixed0, fixed1);
5240 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
5241 #define nested_guest_cr4_valid nested_cr4_valid
5242 #define nested_host_cr4_valid nested_cr4_valid
5244 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
5246 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
5248 struct kvm_vcpu *vcpu)
5250 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
5251 vmx_decache_cr3(vcpu);
5252 if (!(cr0 & X86_CR0_PG)) {
5253 /* From paging/starting to nonpaging */
5254 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
5255 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
5256 (CPU_BASED_CR3_LOAD_EXITING |
5257 CPU_BASED_CR3_STORE_EXITING));
5258 vcpu->arch.cr0 = cr0;
5259 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
5260 } else if (!is_paging(vcpu)) {
5261 /* From nonpaging to paging */
5262 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
5263 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
5264 ~(CPU_BASED_CR3_LOAD_EXITING |
5265 CPU_BASED_CR3_STORE_EXITING));
5266 vcpu->arch.cr0 = cr0;
5267 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
5270 if (!(cr0 & X86_CR0_WP))
5271 *hw_cr0 &= ~X86_CR0_WP;
5274 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
5276 struct vcpu_vmx *vmx = to_vmx(vcpu);
5277 unsigned long hw_cr0;
5279 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
5280 if (enable_unrestricted_guest)
5281 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
5283 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
5285 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
5288 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
5292 #ifdef CONFIG_X86_64
5293 if (vcpu->arch.efer & EFER_LME) {
5294 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
5296 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
5301 if (enable_ept && !enable_unrestricted_guest)
5302 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
5304 vmcs_writel(CR0_READ_SHADOW, cr0);
5305 vmcs_writel(GUEST_CR0, hw_cr0);
5306 vcpu->arch.cr0 = cr0;
5308 /* depends on vcpu->arch.cr0 to be set to a new value */
5309 vmx->emulation_required = emulation_required(vcpu);
5312 static int get_ept_level(struct kvm_vcpu *vcpu)
5314 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
5319 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
5321 u64 eptp = VMX_EPTP_MT_WB;
5323 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
5325 if (enable_ept_ad_bits &&
5326 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
5327 eptp |= VMX_EPTP_AD_ENABLE_BIT;
5328 eptp |= (root_hpa & PAGE_MASK);
5333 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
5335 struct kvm *kvm = vcpu->kvm;
5336 unsigned long guest_cr3;
5341 eptp = construct_eptp(vcpu, cr3);
5342 vmcs_write64(EPT_POINTER, eptp);
5344 if (kvm_x86_ops->tlb_remote_flush) {
5345 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
5346 to_vmx(vcpu)->ept_pointer = eptp;
5347 to_kvm_vmx(kvm)->ept_pointers_match
5348 = EPT_POINTERS_CHECK;
5349 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
5352 if (enable_unrestricted_guest || is_paging(vcpu) ||
5353 is_guest_mode(vcpu))
5354 guest_cr3 = kvm_read_cr3(vcpu);
5356 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
5357 ept_load_pdptrs(vcpu);
5360 vmcs_writel(GUEST_CR3, guest_cr3);
5363 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
5366 * Pass through host's Machine Check Enable value to hw_cr4, which
5367 * is in force while we are in guest mode. Do not let guests control
5368 * this bit, even if host CR4.MCE == 0.
5370 unsigned long hw_cr4;
5372 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
5373 if (enable_unrestricted_guest)
5374 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
5375 else if (to_vmx(vcpu)->rmode.vm86_active)
5376 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
5378 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
5380 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
5381 if (cr4 & X86_CR4_UMIP) {
5382 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5383 SECONDARY_EXEC_DESC);
5384 hw_cr4 &= ~X86_CR4_UMIP;
5385 } else if (!is_guest_mode(vcpu) ||
5386 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
5387 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5388 SECONDARY_EXEC_DESC);
5391 if (cr4 & X86_CR4_VMXE) {
5393 * To use VMXON (and later other VMX instructions), a guest
5394 * must first be able to turn on cr4.VMXE (see handle_vmon()).
5395 * So basically the check on whether to allow nested VMX
5398 if (!nested_vmx_allowed(vcpu))
5402 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5405 vcpu->arch.cr4 = cr4;
5407 if (!enable_unrestricted_guest) {
5409 if (!is_paging(vcpu)) {
5410 hw_cr4 &= ~X86_CR4_PAE;
5411 hw_cr4 |= X86_CR4_PSE;
5412 } else if (!(cr4 & X86_CR4_PAE)) {
5413 hw_cr4 &= ~X86_CR4_PAE;
5418 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
5419 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
5420 * to be manually disabled when guest switches to non-paging
5423 * If !enable_unrestricted_guest, the CPU is always running
5424 * with CR0.PG=1 and CR4 needs to be modified.
5425 * If enable_unrestricted_guest, the CPU automatically
5426 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
5428 if (!is_paging(vcpu))
5429 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
5432 vmcs_writel(CR4_READ_SHADOW, cr4);
5433 vmcs_writel(GUEST_CR4, hw_cr4);
5437 static void vmx_get_segment(struct kvm_vcpu *vcpu,
5438 struct kvm_segment *var, int seg)
5440 struct vcpu_vmx *vmx = to_vmx(vcpu);
5443 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5444 *var = vmx->rmode.segs[seg];
5445 if (seg == VCPU_SREG_TR
5446 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
5448 var->base = vmx_read_guest_seg_base(vmx, seg);
5449 var->selector = vmx_read_guest_seg_selector(vmx, seg);
5452 var->base = vmx_read_guest_seg_base(vmx, seg);
5453 var->limit = vmx_read_guest_seg_limit(vmx, seg);
5454 var->selector = vmx_read_guest_seg_selector(vmx, seg);
5455 ar = vmx_read_guest_seg_ar(vmx, seg);
5456 var->unusable = (ar >> 16) & 1;
5457 var->type = ar & 15;
5458 var->s = (ar >> 4) & 1;
5459 var->dpl = (ar >> 5) & 3;
5461 * Some userspaces do not preserve unusable property. Since usable
5462 * segment has to be present according to VMX spec we can use present
5463 * property to amend userspace bug by making unusable segment always
5464 * nonpresent. vmx_segment_access_rights() already marks nonpresent
5465 * segment as unusable.
5467 var->present = !var->unusable;
5468 var->avl = (ar >> 12) & 1;
5469 var->l = (ar >> 13) & 1;
5470 var->db = (ar >> 14) & 1;
5471 var->g = (ar >> 15) & 1;
5474 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
5476 struct kvm_segment s;
5478 if (to_vmx(vcpu)->rmode.vm86_active) {
5479 vmx_get_segment(vcpu, &s, seg);
5482 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
5485 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
5487 struct vcpu_vmx *vmx = to_vmx(vcpu);
5489 if (unlikely(vmx->rmode.vm86_active))
5492 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
5493 return VMX_AR_DPL(ar);
5497 static u32 vmx_segment_access_rights(struct kvm_segment *var)
5501 if (var->unusable || !var->present)
5504 ar = var->type & 15;
5505 ar |= (var->s & 1) << 4;
5506 ar |= (var->dpl & 3) << 5;
5507 ar |= (var->present & 1) << 7;
5508 ar |= (var->avl & 1) << 12;
5509 ar |= (var->l & 1) << 13;
5510 ar |= (var->db & 1) << 14;
5511 ar |= (var->g & 1) << 15;
5517 static void vmx_set_segment(struct kvm_vcpu *vcpu,
5518 struct kvm_segment *var, int seg)
5520 struct vcpu_vmx *vmx = to_vmx(vcpu);
5521 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5523 vmx_segment_cache_clear(vmx);
5525 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5526 vmx->rmode.segs[seg] = *var;
5527 if (seg == VCPU_SREG_TR)
5528 vmcs_write16(sf->selector, var->selector);
5530 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
5534 vmcs_writel(sf->base, var->base);
5535 vmcs_write32(sf->limit, var->limit);
5536 vmcs_write16(sf->selector, var->selector);
5539 * Fix the "Accessed" bit in AR field of segment registers for older
5541 * IA32 arch specifies that at the time of processor reset the
5542 * "Accessed" bit in the AR field of segment registers is 1. And qemu
5543 * is setting it to 0 in the userland code. This causes invalid guest
5544 * state vmexit when "unrestricted guest" mode is turned on.
5545 * Fix for this setup issue in cpu_reset is being pushed in the qemu
5546 * tree. Newer qemu binaries with that qemu fix would not need this
5549 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
5550 var->type |= 0x1; /* Accessed */
5552 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
5555 vmx->emulation_required = emulation_required(vcpu);
5558 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5560 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
5562 *db = (ar >> 14) & 1;
5563 *l = (ar >> 13) & 1;
5566 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5568 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
5569 dt->address = vmcs_readl(GUEST_IDTR_BASE);
5572 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5574 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
5575 vmcs_writel(GUEST_IDTR_BASE, dt->address);
5578 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5580 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
5581 dt->address = vmcs_readl(GUEST_GDTR_BASE);
5584 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5586 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
5587 vmcs_writel(GUEST_GDTR_BASE, dt->address);
5590 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
5592 struct kvm_segment var;
5595 vmx_get_segment(vcpu, &var, seg);
5597 if (seg == VCPU_SREG_CS)
5599 ar = vmx_segment_access_rights(&var);
5601 if (var.base != (var.selector << 4))
5603 if (var.limit != 0xffff)
5611 static bool code_segment_valid(struct kvm_vcpu *vcpu)
5613 struct kvm_segment cs;
5614 unsigned int cs_rpl;
5616 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5617 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
5621 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
5625 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
5626 if (cs.dpl > cs_rpl)
5629 if (cs.dpl != cs_rpl)
5635 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
5639 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
5641 struct kvm_segment ss;
5642 unsigned int ss_rpl;
5644 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5645 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
5649 if (ss.type != 3 && ss.type != 7)
5653 if (ss.dpl != ss_rpl) /* DPL != RPL */
5661 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
5663 struct kvm_segment var;
5666 vmx_get_segment(vcpu, &var, seg);
5667 rpl = var.selector & SEGMENT_RPL_MASK;
5675 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
5676 if (var.dpl < rpl) /* DPL < RPL */
5680 /* TODO: Add other members to kvm_segment_field to allow checking for other access
5686 static bool tr_valid(struct kvm_vcpu *vcpu)
5688 struct kvm_segment tr;
5690 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
5694 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
5696 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
5704 static bool ldtr_valid(struct kvm_vcpu *vcpu)
5706 struct kvm_segment ldtr;
5708 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
5712 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
5722 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
5724 struct kvm_segment cs, ss;
5726 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5727 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5729 return ((cs.selector & SEGMENT_RPL_MASK) ==
5730 (ss.selector & SEGMENT_RPL_MASK));
5734 * Check if guest state is valid. Returns true if valid, false if
5736 * We assume that registers are always usable
5738 static bool guest_state_valid(struct kvm_vcpu *vcpu)
5740 if (enable_unrestricted_guest)
5743 /* real mode guest state checks */
5744 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5745 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
5747 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
5749 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
5751 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
5753 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
5755 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
5758 /* protected mode guest state checks */
5759 if (!cs_ss_rpl_check(vcpu))
5761 if (!code_segment_valid(vcpu))
5763 if (!stack_segment_valid(vcpu))
5765 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
5767 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
5769 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
5771 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
5773 if (!tr_valid(vcpu))
5775 if (!ldtr_valid(vcpu))
5779 * - Add checks on RIP
5780 * - Add checks on RFLAGS
5786 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
5788 return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
5791 static int init_rmode_tss(struct kvm *kvm)
5797 idx = srcu_read_lock(&kvm->srcu);
5798 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
5799 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5802 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
5803 r = kvm_write_guest_page(kvm, fn++, &data,
5804 TSS_IOPB_BASE_OFFSET, sizeof(u16));
5807 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
5810 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5814 r = kvm_write_guest_page(kvm, fn, &data,
5815 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
5818 srcu_read_unlock(&kvm->srcu, idx);
5822 static int init_rmode_identity_map(struct kvm *kvm)
5824 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
5826 kvm_pfn_t identity_map_pfn;
5829 /* Protect kvm_vmx->ept_identity_pagetable_done. */
5830 mutex_lock(&kvm->slots_lock);
5832 if (likely(kvm_vmx->ept_identity_pagetable_done))
5835 if (!kvm_vmx->ept_identity_map_addr)
5836 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
5837 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
5839 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
5840 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
5844 idx = srcu_read_lock(&kvm->srcu);
5845 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
5848 /* Set up identity-mapping pagetable for EPT in real mode */
5849 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
5850 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
5851 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
5852 r = kvm_write_guest_page(kvm, identity_map_pfn,
5853 &tmp, i * sizeof(tmp), sizeof(tmp));
5857 kvm_vmx->ept_identity_pagetable_done = true;
5860 srcu_read_unlock(&kvm->srcu, idx);
5863 mutex_unlock(&kvm->slots_lock);
5867 static void seg_setup(int seg)
5869 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5872 vmcs_write16(sf->selector, 0);
5873 vmcs_writel(sf->base, 0);
5874 vmcs_write32(sf->limit, 0xffff);
5876 if (seg == VCPU_SREG_CS)
5877 ar |= 0x08; /* code segment */
5879 vmcs_write32(sf->ar_bytes, ar);
5882 static int alloc_apic_access_page(struct kvm *kvm)
5887 mutex_lock(&kvm->slots_lock);
5888 if (kvm->arch.apic_access_page_done)
5890 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
5891 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
5895 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
5896 if (is_error_page(page)) {
5902 * Do not pin the page in memory, so that memory hot-unplug
5903 * is able to migrate it.
5906 kvm->arch.apic_access_page_done = true;
5908 mutex_unlock(&kvm->slots_lock);
5912 static int allocate_vpid(void)
5918 spin_lock(&vmx_vpid_lock);
5919 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
5920 if (vpid < VMX_NR_VPIDS)
5921 __set_bit(vpid, vmx_vpid_bitmap);
5924 spin_unlock(&vmx_vpid_lock);
5928 static void free_vpid(int vpid)
5930 if (!enable_vpid || vpid == 0)
5932 spin_lock(&vmx_vpid_lock);
5933 __clear_bit(vpid, vmx_vpid_bitmap);
5934 spin_unlock(&vmx_vpid_lock);
5937 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
5940 int f = sizeof(unsigned long);
5942 if (!cpu_has_vmx_msr_bitmap())
5945 if (static_branch_unlikely(&enable_evmcs))
5946 evmcs_touch_msr_bitmap();
5949 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5950 * have the write-low and read-high bitmap offsets the wrong way round.
5951 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5953 if (msr <= 0x1fff) {
5954 if (type & MSR_TYPE_R)
5956 __clear_bit(msr, msr_bitmap + 0x000 / f);
5958 if (type & MSR_TYPE_W)
5960 __clear_bit(msr, msr_bitmap + 0x800 / f);
5962 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5964 if (type & MSR_TYPE_R)
5966 __clear_bit(msr, msr_bitmap + 0x400 / f);
5968 if (type & MSR_TYPE_W)
5970 __clear_bit(msr, msr_bitmap + 0xc00 / f);
5975 static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
5978 int f = sizeof(unsigned long);
5980 if (!cpu_has_vmx_msr_bitmap())
5983 if (static_branch_unlikely(&enable_evmcs))
5984 evmcs_touch_msr_bitmap();
5987 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5988 * have the write-low and read-high bitmap offsets the wrong way round.
5989 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5991 if (msr <= 0x1fff) {
5992 if (type & MSR_TYPE_R)
5994 __set_bit(msr, msr_bitmap + 0x000 / f);
5996 if (type & MSR_TYPE_W)
5998 __set_bit(msr, msr_bitmap + 0x800 / f);
6000 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
6002 if (type & MSR_TYPE_R)
6004 __set_bit(msr, msr_bitmap + 0x400 / f);
6006 if (type & MSR_TYPE_W)
6008 __set_bit(msr, msr_bitmap + 0xc00 / f);
6013 static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
6014 u32 msr, int type, bool value)
6017 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
6019 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
6023 * If a msr is allowed by L0, we should check whether it is allowed by L1.
6024 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
6026 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
6027 unsigned long *msr_bitmap_nested,
6030 int f = sizeof(unsigned long);
6033 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
6034 * have the write-low and read-high bitmap offsets the wrong way round.
6035 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
6037 if (msr <= 0x1fff) {
6038 if (type & MSR_TYPE_R &&
6039 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
6041 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
6043 if (type & MSR_TYPE_W &&
6044 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
6046 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
6048 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
6050 if (type & MSR_TYPE_R &&
6051 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
6053 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
6055 if (type & MSR_TYPE_W &&
6056 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
6058 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
6063 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
6067 if (cpu_has_secondary_exec_ctrls() &&
6068 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
6069 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
6070 mode |= MSR_BITMAP_MODE_X2APIC;
6071 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
6072 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
6075 if (is_long_mode(vcpu))
6076 mode |= MSR_BITMAP_MODE_LM;
6081 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
6083 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
6088 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
6089 unsigned word = msr / BITS_PER_LONG;
6090 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
6091 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
6094 if (mode & MSR_BITMAP_MODE_X2APIC) {
6096 * TPR reads and writes can be virtualized even if virtual interrupt
6097 * delivery is not in use.
6099 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
6100 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
6101 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
6102 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
6103 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
6108 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
6110 struct vcpu_vmx *vmx = to_vmx(vcpu);
6111 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
6112 u8 mode = vmx_msr_bitmap_mode(vcpu);
6113 u8 changed = mode ^ vmx->msr_bitmap_mode;
6118 vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW,
6119 !(mode & MSR_BITMAP_MODE_LM));
6121 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
6122 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
6124 vmx->msr_bitmap_mode = mode;
6127 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
6129 return enable_apicv;
6132 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
6134 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6138 * Don't need to mark the APIC access page dirty; it is never
6139 * written to by the CPU during APIC virtualization.
6142 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
6143 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
6144 kvm_vcpu_mark_page_dirty(vcpu, gfn);
6147 if (nested_cpu_has_posted_intr(vmcs12)) {
6148 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
6149 kvm_vcpu_mark_page_dirty(vcpu, gfn);
6154 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
6156 struct vcpu_vmx *vmx = to_vmx(vcpu);
6161 if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
6164 vmx->nested.pi_pending = false;
6165 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
6168 max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
6169 if (max_irr != 256) {
6170 vapic_page = kmap(vmx->nested.virtual_apic_page);
6171 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
6172 vapic_page, &max_irr);
6173 kunmap(vmx->nested.virtual_apic_page);
6175 status = vmcs_read16(GUEST_INTR_STATUS);
6176 if ((u8)max_irr > ((u8)status & 0xff)) {
6178 status |= (u8)max_irr;
6179 vmcs_write16(GUEST_INTR_STATUS, status);
6183 nested_mark_vmcs12_pages_dirty(vcpu);
6186 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
6190 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
6192 if (vcpu->mode == IN_GUEST_MODE) {
6194 * The vector of interrupt to be delivered to vcpu had
6195 * been set in PIR before this function.
6197 * Following cases will be reached in this block, and
6198 * we always send a notification event in all cases as
6201 * Case 1: vcpu keeps in non-root mode. Sending a
6202 * notification event posts the interrupt to vcpu.
6204 * Case 2: vcpu exits to root mode and is still
6205 * runnable. PIR will be synced to vIRR before the
6206 * next vcpu entry. Sending a notification event in
6207 * this case has no effect, as vcpu is not in root
6210 * Case 3: vcpu exits to root mode and is blocked.
6211 * vcpu_block() has already synced PIR to vIRR and
6212 * never blocks vcpu if vIRR is not cleared. Therefore,
6213 * a blocked vcpu here does not wait for any requested
6214 * interrupts in PIR, and sending a notification event
6215 * which has no effect is safe here.
6218 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
6225 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
6228 struct vcpu_vmx *vmx = to_vmx(vcpu);
6230 if (is_guest_mode(vcpu) &&
6231 vector == vmx->nested.posted_intr_nv) {
6233 * If a posted intr is not recognized by hardware,
6234 * we will accomplish it in the next vmentry.
6236 vmx->nested.pi_pending = true;
6237 kvm_make_request(KVM_REQ_EVENT, vcpu);
6238 /* the PIR and ON have been set by L1. */
6239 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
6240 kvm_vcpu_kick(vcpu);
6246 * Send interrupt to vcpu via posted interrupt way.
6247 * 1. If target vcpu is running(non-root mode), send posted interrupt
6248 * notification to vcpu and hardware will sync PIR to vIRR atomically.
6249 * 2. If target vcpu isn't running(root mode), kick it to pick up the
6250 * interrupt from PIR in next vmentry.
6252 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
6254 struct vcpu_vmx *vmx = to_vmx(vcpu);
6257 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
6261 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
6264 /* If a previous notification has sent the IPI, nothing to do. */
6265 if (pi_test_and_set_on(&vmx->pi_desc))
6268 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
6269 kvm_vcpu_kick(vcpu);
6273 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
6274 * will not change in the lifetime of the guest.
6275 * Note that host-state that does change is set elsewhere. E.g., host-state
6276 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
6278 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
6283 unsigned long cr0, cr3, cr4;
6286 WARN_ON(cr0 & X86_CR0_TS);
6287 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
6290 * Save the most likely value for this task's CR3 in the VMCS.
6291 * We can't use __get_current_cr3_fast() because we're not atomic.
6294 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
6295 vmx->loaded_vmcs->host_state.cr3 = cr3;
6297 /* Save the most likely value for this task's CR4 in the VMCS. */
6298 cr4 = cr4_read_shadow();
6299 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
6300 vmx->loaded_vmcs->host_state.cr4 = cr4;
6302 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
6303 #ifdef CONFIG_X86_64
6305 * Load null selectors, so we can avoid reloading them in
6306 * vmx_prepare_switch_to_host(), in case userspace uses
6307 * the null selectors too (the expected case).
6309 vmcs_write16(HOST_DS_SELECTOR, 0);
6310 vmcs_write16(HOST_ES_SELECTOR, 0);
6312 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
6313 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
6315 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
6316 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
6319 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6320 vmx->host_idt_base = dt.address;
6322 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
6324 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
6325 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
6326 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
6327 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
6329 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
6330 rdmsr(MSR_IA32_CR_PAT, low32, high32);
6331 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
6335 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
6337 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
6339 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
6340 if (is_guest_mode(&vmx->vcpu))
6341 vmx->vcpu.arch.cr4_guest_owned_bits &=
6342 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
6343 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
6346 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
6348 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
6350 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
6351 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
6354 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
6356 /* Enable the preemption timer dynamically */
6357 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
6358 return pin_based_exec_ctrl;
6361 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
6363 struct vcpu_vmx *vmx = to_vmx(vcpu);
6365 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6366 if (cpu_has_secondary_exec_ctrls()) {
6367 if (kvm_vcpu_apicv_active(vcpu))
6368 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
6369 SECONDARY_EXEC_APIC_REGISTER_VIRT |
6370 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6372 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6373 SECONDARY_EXEC_APIC_REGISTER_VIRT |
6374 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6377 if (cpu_has_vmx_msr_bitmap())
6378 vmx_update_msr_bitmap(vcpu);
6381 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
6383 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
6385 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
6386 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
6388 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
6389 exec_control &= ~CPU_BASED_TPR_SHADOW;
6390 #ifdef CONFIG_X86_64
6391 exec_control |= CPU_BASED_CR8_STORE_EXITING |
6392 CPU_BASED_CR8_LOAD_EXITING;
6396 exec_control |= CPU_BASED_CR3_STORE_EXITING |
6397 CPU_BASED_CR3_LOAD_EXITING |
6398 CPU_BASED_INVLPG_EXITING;
6399 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
6400 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
6401 CPU_BASED_MONITOR_EXITING);
6402 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
6403 exec_control &= ~CPU_BASED_HLT_EXITING;
6404 return exec_control;
6407 static bool vmx_rdrand_supported(void)
6409 return vmcs_config.cpu_based_2nd_exec_ctrl &
6410 SECONDARY_EXEC_RDRAND_EXITING;
6413 static bool vmx_rdseed_supported(void)
6415 return vmcs_config.cpu_based_2nd_exec_ctrl &
6416 SECONDARY_EXEC_RDSEED_EXITING;
6419 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
6421 struct kvm_vcpu *vcpu = &vmx->vcpu;
6423 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
6425 if (!cpu_need_virtualize_apic_accesses(vcpu))
6426 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6428 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
6430 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
6431 enable_unrestricted_guest = 0;
6433 if (!enable_unrestricted_guest)
6434 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
6435 if (kvm_pause_in_guest(vmx->vcpu.kvm))
6436 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
6437 if (!kvm_vcpu_apicv_active(vcpu))
6438 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
6439 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6440 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6442 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
6443 * in vmx_set_cr4. */
6444 exec_control &= ~SECONDARY_EXEC_DESC;
6446 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
6448 We can NOT enable shadow_vmcs here because we don't have yet
6451 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6454 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
6456 if (vmx_xsaves_supported()) {
6457 /* Exposing XSAVES only when XSAVE is exposed */
6458 bool xsaves_enabled =
6459 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
6460 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
6462 if (!xsaves_enabled)
6463 exec_control &= ~SECONDARY_EXEC_XSAVES;
6467 vmx->nested.msrs.secondary_ctls_high |=
6468 SECONDARY_EXEC_XSAVES;
6470 vmx->nested.msrs.secondary_ctls_high &=
6471 ~SECONDARY_EXEC_XSAVES;
6475 if (vmx_rdtscp_supported()) {
6476 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
6477 if (!rdtscp_enabled)
6478 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6482 vmx->nested.msrs.secondary_ctls_high |=
6483 SECONDARY_EXEC_RDTSCP;
6485 vmx->nested.msrs.secondary_ctls_high &=
6486 ~SECONDARY_EXEC_RDTSCP;
6490 if (vmx_invpcid_supported()) {
6491 /* Exposing INVPCID only when PCID is exposed */
6492 bool invpcid_enabled =
6493 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
6494 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
6496 if (!invpcid_enabled) {
6497 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6498 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
6502 if (invpcid_enabled)
6503 vmx->nested.msrs.secondary_ctls_high |=
6504 SECONDARY_EXEC_ENABLE_INVPCID;
6506 vmx->nested.msrs.secondary_ctls_high &=
6507 ~SECONDARY_EXEC_ENABLE_INVPCID;
6511 if (vmx_rdrand_supported()) {
6512 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
6514 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
6518 vmx->nested.msrs.secondary_ctls_high |=
6519 SECONDARY_EXEC_RDRAND_EXITING;
6521 vmx->nested.msrs.secondary_ctls_high &=
6522 ~SECONDARY_EXEC_RDRAND_EXITING;
6526 if (vmx_rdseed_supported()) {
6527 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
6529 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
6533 vmx->nested.msrs.secondary_ctls_high |=
6534 SECONDARY_EXEC_RDSEED_EXITING;
6536 vmx->nested.msrs.secondary_ctls_high &=
6537 ~SECONDARY_EXEC_RDSEED_EXITING;
6541 vmx->secondary_exec_control = exec_control;
6544 static void ept_set_mmio_spte_mask(void)
6547 * EPT Misconfigurations can be generated if the value of bits 2:0
6548 * of an EPT paging-structure entry is 110b (write/execute).
6550 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
6551 VMX_EPT_MISCONFIG_WX_VALUE);
6554 #define VMX_XSS_EXIT_BITMAP 0
6556 * Sets up the vmcs for emulated real mode.
6558 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
6562 if (enable_shadow_vmcs) {
6564 * At vCPU creation, "VMWRITE to any supported field
6565 * in the VMCS" is supported, so use the more
6566 * permissive vmx_vmread_bitmap to specify both read
6567 * and write permissions for the shadow VMCS.
6569 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
6570 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmread_bitmap));
6572 if (cpu_has_vmx_msr_bitmap())
6573 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
6575 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
6578 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6579 vmx->hv_deadline_tsc = -1;
6581 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6583 if (cpu_has_secondary_exec_ctrls()) {
6584 vmx_compute_secondary_exec_control(vmx);
6585 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6586 vmx->secondary_exec_control);
6589 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
6590 vmcs_write64(EOI_EXIT_BITMAP0, 0);
6591 vmcs_write64(EOI_EXIT_BITMAP1, 0);
6592 vmcs_write64(EOI_EXIT_BITMAP2, 0);
6593 vmcs_write64(EOI_EXIT_BITMAP3, 0);
6595 vmcs_write16(GUEST_INTR_STATUS, 0);
6597 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
6598 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
6601 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
6602 vmcs_write32(PLE_GAP, ple_gap);
6603 vmx->ple_window = ple_window;
6604 vmx->ple_window_dirty = true;
6607 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
6608 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6609 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
6611 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
6612 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
6613 vmx_set_constant_host_state(vmx);
6614 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
6615 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6617 if (cpu_has_vmx_vmfunc())
6618 vmcs_write64(VM_FUNCTION_CONTROL, 0);
6620 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
6621 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
6622 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
6623 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6624 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
6626 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6627 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6629 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6630 u32 index = vmx_msr_index[i];
6631 u32 data_low, data_high;
6634 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6636 if (wrmsr_safe(index, data_low, data_high) < 0)
6638 vmx->guest_msrs[j].index = i;
6639 vmx->guest_msrs[j].data = 0;
6640 vmx->guest_msrs[j].mask = -1ull;
6644 vmx->arch_capabilities = kvm_get_arch_capabilities();
6646 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6648 /* 22.2.1, 20.8.1 */
6649 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
6651 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
6652 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
6654 set_cr4_guest_host_mask(vmx);
6656 if (vmx_xsaves_supported())
6657 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
6660 ASSERT(vmx->pml_pg);
6661 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
6662 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
6665 if (cpu_has_vmx_encls_vmexit())
6666 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
6669 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
6671 struct vcpu_vmx *vmx = to_vmx(vcpu);
6672 struct msr_data apic_base_msr;
6675 vmx->rmode.vm86_active = 0;
6678 vcpu->arch.microcode_version = 0x100000000ULL;
6679 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
6680 kvm_set_cr8(vcpu, 0);
6683 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
6684 MSR_IA32_APICBASE_ENABLE;
6685 if (kvm_vcpu_is_reset_bsp(vcpu))
6686 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
6687 apic_base_msr.host_initiated = true;
6688 kvm_set_apic_base(vcpu, &apic_base_msr);
6691 vmx_segment_cache_clear(vmx);
6693 seg_setup(VCPU_SREG_CS);
6694 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
6695 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
6697 seg_setup(VCPU_SREG_DS);
6698 seg_setup(VCPU_SREG_ES);
6699 seg_setup(VCPU_SREG_FS);
6700 seg_setup(VCPU_SREG_GS);
6701 seg_setup(VCPU_SREG_SS);
6703 vmcs_write16(GUEST_TR_SELECTOR, 0);
6704 vmcs_writel(GUEST_TR_BASE, 0);
6705 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
6706 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
6708 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
6709 vmcs_writel(GUEST_LDTR_BASE, 0);
6710 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
6711 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
6714 vmcs_write32(GUEST_SYSENTER_CS, 0);
6715 vmcs_writel(GUEST_SYSENTER_ESP, 0);
6716 vmcs_writel(GUEST_SYSENTER_EIP, 0);
6717 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
6720 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6721 kvm_rip_write(vcpu, 0xfff0);
6723 vmcs_writel(GUEST_GDTR_BASE, 0);
6724 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
6726 vmcs_writel(GUEST_IDTR_BASE, 0);
6727 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
6729 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
6730 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
6731 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
6732 if (kvm_mpx_supported())
6733 vmcs_write64(GUEST_BNDCFGS, 0);
6737 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
6739 if (cpu_has_vmx_tpr_shadow() && !init_event) {
6740 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
6741 if (cpu_need_tpr_shadow(vcpu))
6742 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
6743 __pa(vcpu->arch.apic->regs));
6744 vmcs_write32(TPR_THRESHOLD, 0);
6747 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6750 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6752 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
6753 vmx->vcpu.arch.cr0 = cr0;
6754 vmx_set_cr0(vcpu, cr0); /* enter rmode */
6755 vmx_set_cr4(vcpu, 0);
6756 vmx_set_efer(vcpu, 0);
6758 update_exception_bitmap(vcpu);
6760 vpid_sync_context(vmx->vpid);
6762 vmx_clear_hlt(vcpu);
6766 * In nested virtualization, check if L1 asked to exit on external interrupts.
6767 * For most existing hypervisors, this will always return true.
6769 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
6771 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
6772 PIN_BASED_EXT_INTR_MASK;
6776 * In nested virtualization, check if L1 has set
6777 * VM_EXIT_ACK_INTR_ON_EXIT
6779 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
6781 return get_vmcs12(vcpu)->vm_exit_controls &
6782 VM_EXIT_ACK_INTR_ON_EXIT;
6785 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
6787 return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu));
6790 static void enable_irq_window(struct kvm_vcpu *vcpu)
6792 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6793 CPU_BASED_VIRTUAL_INTR_PENDING);
6796 static void enable_nmi_window(struct kvm_vcpu *vcpu)
6799 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
6800 enable_irq_window(vcpu);
6804 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6805 CPU_BASED_VIRTUAL_NMI_PENDING);
6808 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
6810 struct vcpu_vmx *vmx = to_vmx(vcpu);
6812 int irq = vcpu->arch.interrupt.nr;
6814 trace_kvm_inj_virq(irq);
6816 ++vcpu->stat.irq_injections;
6817 if (vmx->rmode.vm86_active) {
6819 if (vcpu->arch.interrupt.soft)
6820 inc_eip = vcpu->arch.event_exit_inst_len;
6821 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
6822 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6825 intr = irq | INTR_INFO_VALID_MASK;
6826 if (vcpu->arch.interrupt.soft) {
6827 intr |= INTR_TYPE_SOFT_INTR;
6828 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6829 vmx->vcpu.arch.event_exit_inst_len);
6831 intr |= INTR_TYPE_EXT_INTR;
6832 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
6834 vmx_clear_hlt(vcpu);
6837 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
6839 struct vcpu_vmx *vmx = to_vmx(vcpu);
6843 * Tracking the NMI-blocked state in software is built upon
6844 * finding the next open IRQ window. This, in turn, depends on
6845 * well-behaving guests: They have to keep IRQs disabled at
6846 * least as long as the NMI handler runs. Otherwise we may
6847 * cause NMI nesting, maybe breaking the guest. But as this is
6848 * highly unlikely, we can live with the residual risk.
6850 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
6851 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6854 ++vcpu->stat.nmi_injections;
6855 vmx->loaded_vmcs->nmi_known_unmasked = false;
6857 if (vmx->rmode.vm86_active) {
6858 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
6859 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6863 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6864 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
6866 vmx_clear_hlt(vcpu);
6869 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
6871 struct vcpu_vmx *vmx = to_vmx(vcpu);
6875 return vmx->loaded_vmcs->soft_vnmi_blocked;
6876 if (vmx->loaded_vmcs->nmi_known_unmasked)
6878 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
6879 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6883 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
6885 struct vcpu_vmx *vmx = to_vmx(vcpu);
6888 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
6889 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
6890 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6893 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6895 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6896 GUEST_INTR_STATE_NMI);
6898 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
6899 GUEST_INTR_STATE_NMI);
6903 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
6905 if (to_vmx(vcpu)->nested.nested_run_pending)
6909 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
6912 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6913 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
6914 | GUEST_INTR_STATE_NMI));
6917 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
6919 return (!to_vmx(vcpu)->nested.nested_run_pending &&
6920 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
6921 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6922 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
6925 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
6929 if (enable_unrestricted_guest)
6932 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
6936 to_kvm_vmx(kvm)->tss_addr = addr;
6937 return init_rmode_tss(kvm);
6940 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
6942 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
6946 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6951 * Update instruction length as we may reinject the exception
6952 * from user space while in guest debugging mode.
6954 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
6955 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6956 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6960 if (vcpu->guest_debug &
6961 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6978 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
6979 int vec, u32 err_code)
6982 * Instruction with address size override prefix opcode 0x67
6983 * Cause the #SS fault with 0 error code in VM86 mode.
6985 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
6986 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
6987 if (vcpu->arch.halt_request) {
6988 vcpu->arch.halt_request = 0;
6989 return kvm_vcpu_halt(vcpu);
6997 * Forward all other exceptions that are valid in real mode.
6998 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
6999 * the required debugging infrastructure rework.
7001 kvm_queue_exception(vcpu, vec);
7006 * Trigger machine check on the host. We assume all the MSRs are already set up
7007 * by the CPU and that we still run on the same CPU as the MCE occurred on.
7008 * We pass a fake environment to the machine check handler because we want
7009 * the guest to be always treated like user space, no matter what context
7010 * it used internally.
7012 static void kvm_machine_check(void)
7014 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
7015 struct pt_regs regs = {
7016 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
7017 .flags = X86_EFLAGS_IF,
7020 do_machine_check(®s, 0);
7024 static int handle_machine_check(struct kvm_vcpu *vcpu)
7026 /* already handled by vcpu_run */
7030 static int handle_exception(struct kvm_vcpu *vcpu)
7032 struct vcpu_vmx *vmx = to_vmx(vcpu);
7033 struct kvm_run *kvm_run = vcpu->run;
7034 u32 intr_info, ex_no, error_code;
7035 unsigned long cr2, rip, dr6;
7037 enum emulation_result er;
7039 vect_info = vmx->idt_vectoring_info;
7040 intr_info = vmx->exit_intr_info;
7042 if (is_machine_check(intr_info))
7043 return handle_machine_check(vcpu);
7045 if (is_nmi(intr_info))
7046 return 1; /* already handled by vmx_vcpu_run() */
7048 if (is_invalid_opcode(intr_info))
7049 return handle_ud(vcpu);
7052 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
7053 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7055 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
7056 WARN_ON_ONCE(!enable_vmware_backdoor);
7057 er = emulate_instruction(vcpu,
7058 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
7059 if (er == EMULATE_USER_EXIT)
7061 else if (er != EMULATE_DONE)
7062 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
7067 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
7068 * MMIO, it is better to report an internal error.
7069 * See the comments in vmx_handle_exit.
7071 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
7072 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
7073 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7074 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
7075 vcpu->run->internal.ndata = 3;
7076 vcpu->run->internal.data[0] = vect_info;
7077 vcpu->run->internal.data[1] = intr_info;
7078 vcpu->run->internal.data[2] = error_code;
7082 if (is_page_fault(intr_info)) {
7083 cr2 = vmcs_readl(EXIT_QUALIFICATION);
7084 /* EPT won't cause page fault directly */
7085 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
7086 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
7089 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
7091 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
7092 return handle_rmode_exception(vcpu, ex_no, error_code);
7096 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
7099 dr6 = vmcs_readl(EXIT_QUALIFICATION);
7100 if (!(vcpu->guest_debug &
7101 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
7102 vcpu->arch.dr6 &= ~15;
7103 vcpu->arch.dr6 |= dr6 | DR6_RTM;
7104 if (is_icebp(intr_info))
7105 skip_emulated_instruction(vcpu);
7107 kvm_queue_exception(vcpu, DB_VECTOR);
7110 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
7111 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
7115 * Update instruction length as we may reinject #BP from
7116 * user space while in guest debugging mode. Reading it for
7117 * #DB as well causes no harm, it is not used in that case.
7119 vmx->vcpu.arch.event_exit_inst_len =
7120 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7121 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7122 rip = kvm_rip_read(vcpu);
7123 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
7124 kvm_run->debug.arch.exception = ex_no;
7127 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
7128 kvm_run->ex.exception = ex_no;
7129 kvm_run->ex.error_code = error_code;
7135 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
7137 ++vcpu->stat.irq_exits;
7141 static int handle_triple_fault(struct kvm_vcpu *vcpu)
7143 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7144 vcpu->mmio_needed = 0;
7148 static int handle_io(struct kvm_vcpu *vcpu)
7150 unsigned long exit_qualification;
7151 int size, in, string;
7154 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7155 string = (exit_qualification & 16) != 0;
7157 ++vcpu->stat.io_exits;
7160 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
7162 port = exit_qualification >> 16;
7163 size = (exit_qualification & 7) + 1;
7164 in = (exit_qualification & 8) != 0;
7166 return kvm_fast_pio(vcpu, size, port, in);
7170 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
7173 * Patch in the VMCALL instruction:
7175 hypercall[0] = 0x0f;
7176 hypercall[1] = 0x01;
7177 hypercall[2] = 0xc1;
7180 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
7181 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
7183 if (is_guest_mode(vcpu)) {
7184 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7185 unsigned long orig_val = val;
7188 * We get here when L2 changed cr0 in a way that did not change
7189 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
7190 * but did change L0 shadowed bits. So we first calculate the
7191 * effective cr0 value that L1 would like to write into the
7192 * hardware. It consists of the L2-owned bits from the new
7193 * value combined with the L1-owned bits from L1's guest_cr0.
7195 val = (val & ~vmcs12->cr0_guest_host_mask) |
7196 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
7198 if (!nested_guest_cr0_valid(vcpu, val))
7201 if (kvm_set_cr0(vcpu, val))
7203 vmcs_writel(CR0_READ_SHADOW, orig_val);
7206 if (to_vmx(vcpu)->nested.vmxon &&
7207 !nested_host_cr0_valid(vcpu, val))
7210 return kvm_set_cr0(vcpu, val);
7214 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
7216 if (is_guest_mode(vcpu)) {
7217 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7218 unsigned long orig_val = val;
7220 /* analogously to handle_set_cr0 */
7221 val = (val & ~vmcs12->cr4_guest_host_mask) |
7222 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
7223 if (kvm_set_cr4(vcpu, val))
7225 vmcs_writel(CR4_READ_SHADOW, orig_val);
7228 return kvm_set_cr4(vcpu, val);
7231 static int handle_desc(struct kvm_vcpu *vcpu)
7233 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
7234 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
7237 static int handle_cr(struct kvm_vcpu *vcpu)
7239 unsigned long exit_qualification, val;
7245 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7246 cr = exit_qualification & 15;
7247 reg = (exit_qualification >> 8) & 15;
7248 switch ((exit_qualification >> 4) & 3) {
7249 case 0: /* mov to cr */
7250 val = kvm_register_readl(vcpu, reg);
7251 trace_kvm_cr_write(cr, val);
7254 err = handle_set_cr0(vcpu, val);
7255 return kvm_complete_insn_gp(vcpu, err);
7257 WARN_ON_ONCE(enable_unrestricted_guest);
7258 err = kvm_set_cr3(vcpu, val);
7259 return kvm_complete_insn_gp(vcpu, err);
7261 err = handle_set_cr4(vcpu, val);
7262 return kvm_complete_insn_gp(vcpu, err);
7264 u8 cr8_prev = kvm_get_cr8(vcpu);
7266 err = kvm_set_cr8(vcpu, cr8);
7267 ret = kvm_complete_insn_gp(vcpu, err);
7268 if (lapic_in_kernel(vcpu))
7270 if (cr8_prev <= cr8)
7273 * TODO: we might be squashing a
7274 * KVM_GUESTDBG_SINGLESTEP-triggered
7275 * KVM_EXIT_DEBUG here.
7277 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
7283 WARN_ONCE(1, "Guest should always own CR0.TS");
7284 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
7285 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
7286 return kvm_skip_emulated_instruction(vcpu);
7287 case 1: /*mov from cr*/
7290 WARN_ON_ONCE(enable_unrestricted_guest);
7291 val = kvm_read_cr3(vcpu);
7292 kvm_register_write(vcpu, reg, val);
7293 trace_kvm_cr_read(cr, val);
7294 return kvm_skip_emulated_instruction(vcpu);
7296 val = kvm_get_cr8(vcpu);
7297 kvm_register_write(vcpu, reg, val);
7298 trace_kvm_cr_read(cr, val);
7299 return kvm_skip_emulated_instruction(vcpu);
7303 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
7304 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
7305 kvm_lmsw(vcpu, val);
7307 return kvm_skip_emulated_instruction(vcpu);
7311 vcpu->run->exit_reason = 0;
7312 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
7313 (int)(exit_qualification >> 4) & 3, cr);
7317 static int handle_dr(struct kvm_vcpu *vcpu)
7319 unsigned long exit_qualification;
7322 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7323 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
7325 /* First, if DR does not exist, trigger UD */
7326 if (!kvm_require_dr(vcpu, dr))
7329 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
7330 if (!kvm_require_cpl(vcpu, 0))
7332 dr7 = vmcs_readl(GUEST_DR7);
7335 * As the vm-exit takes precedence over the debug trap, we
7336 * need to emulate the latter, either for the host or the
7337 * guest debugging itself.
7339 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7340 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
7341 vcpu->run->debug.arch.dr7 = dr7;
7342 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
7343 vcpu->run->debug.arch.exception = DB_VECTOR;
7344 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
7347 vcpu->arch.dr6 &= ~15;
7348 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
7349 kvm_queue_exception(vcpu, DB_VECTOR);
7354 if (vcpu->guest_debug == 0) {
7355 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7356 CPU_BASED_MOV_DR_EXITING);
7359 * No more DR vmexits; force a reload of the debug registers
7360 * and reenter on this instruction. The next vmexit will
7361 * retrieve the full state of the debug registers.
7363 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
7367 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
7368 if (exit_qualification & TYPE_MOV_FROM_DR) {
7371 if (kvm_get_dr(vcpu, dr, &val))
7373 kvm_register_write(vcpu, reg, val);
7375 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
7378 return kvm_skip_emulated_instruction(vcpu);
7381 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
7383 return vcpu->arch.dr6;
7386 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
7390 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
7392 get_debugreg(vcpu->arch.db[0], 0);
7393 get_debugreg(vcpu->arch.db[1], 1);
7394 get_debugreg(vcpu->arch.db[2], 2);
7395 get_debugreg(vcpu->arch.db[3], 3);
7396 get_debugreg(vcpu->arch.dr6, 6);
7397 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
7399 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
7400 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
7403 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
7405 vmcs_writel(GUEST_DR7, val);
7408 static int handle_cpuid(struct kvm_vcpu *vcpu)
7410 return kvm_emulate_cpuid(vcpu);
7413 static int handle_rdmsr(struct kvm_vcpu *vcpu)
7415 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7416 struct msr_data msr_info;
7418 msr_info.index = ecx;
7419 msr_info.host_initiated = false;
7420 if (vmx_get_msr(vcpu, &msr_info)) {
7421 trace_kvm_msr_read_ex(ecx);
7422 kvm_inject_gp(vcpu, 0);
7426 trace_kvm_msr_read(ecx, msr_info.data);
7428 /* FIXME: handling of bits 32:63 of rax, rdx */
7429 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
7430 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
7431 return kvm_skip_emulated_instruction(vcpu);
7434 static int handle_wrmsr(struct kvm_vcpu *vcpu)
7436 struct msr_data msr;
7437 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7438 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
7439 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
7443 msr.host_initiated = false;
7444 if (kvm_set_msr(vcpu, &msr) != 0) {
7445 trace_kvm_msr_write_ex(ecx, data);
7446 kvm_inject_gp(vcpu, 0);
7450 trace_kvm_msr_write(ecx, data);
7451 return kvm_skip_emulated_instruction(vcpu);
7454 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
7456 kvm_apic_update_ppr(vcpu);
7460 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
7462 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7463 CPU_BASED_VIRTUAL_INTR_PENDING);
7465 kvm_make_request(KVM_REQ_EVENT, vcpu);
7467 ++vcpu->stat.irq_window_exits;
7471 static int handle_halt(struct kvm_vcpu *vcpu)
7473 return kvm_emulate_halt(vcpu);
7476 static int handle_vmcall(struct kvm_vcpu *vcpu)
7478 return kvm_emulate_hypercall(vcpu);
7481 static int handle_invd(struct kvm_vcpu *vcpu)
7483 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
7486 static int handle_invlpg(struct kvm_vcpu *vcpu)
7488 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7490 kvm_mmu_invlpg(vcpu, exit_qualification);
7491 return kvm_skip_emulated_instruction(vcpu);
7494 static int handle_rdpmc(struct kvm_vcpu *vcpu)
7498 err = kvm_rdpmc(vcpu);
7499 return kvm_complete_insn_gp(vcpu, err);
7502 static int handle_wbinvd(struct kvm_vcpu *vcpu)
7504 return kvm_emulate_wbinvd(vcpu);
7507 static int handle_xsetbv(struct kvm_vcpu *vcpu)
7509 u64 new_bv = kvm_read_edx_eax(vcpu);
7510 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
7512 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
7513 return kvm_skip_emulated_instruction(vcpu);
7517 static int handle_xsaves(struct kvm_vcpu *vcpu)
7519 kvm_skip_emulated_instruction(vcpu);
7520 WARN(1, "this should never happen\n");
7524 static int handle_xrstors(struct kvm_vcpu *vcpu)
7526 kvm_skip_emulated_instruction(vcpu);
7527 WARN(1, "this should never happen\n");
7531 static int handle_apic_access(struct kvm_vcpu *vcpu)
7533 if (likely(fasteoi)) {
7534 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7535 int access_type, offset;
7537 access_type = exit_qualification & APIC_ACCESS_TYPE;
7538 offset = exit_qualification & APIC_ACCESS_OFFSET;
7540 * Sane guest uses MOV to write EOI, with written value
7541 * not cared. So make a short-circuit here by avoiding
7542 * heavy instruction emulation.
7544 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
7545 (offset == APIC_EOI)) {
7546 kvm_lapic_set_eoi(vcpu);
7547 return kvm_skip_emulated_instruction(vcpu);
7550 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
7553 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
7555 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7556 int vector = exit_qualification & 0xff;
7558 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
7559 kvm_apic_set_eoi_accelerated(vcpu, vector);
7563 static int handle_apic_write(struct kvm_vcpu *vcpu)
7565 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7566 u32 offset = exit_qualification & 0xfff;
7568 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
7569 kvm_apic_write_nodecode(vcpu, offset);
7573 static int handle_task_switch(struct kvm_vcpu *vcpu)
7575 struct vcpu_vmx *vmx = to_vmx(vcpu);
7576 unsigned long exit_qualification;
7577 bool has_error_code = false;
7580 int reason, type, idt_v, idt_index;
7582 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7583 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
7584 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
7586 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7588 reason = (u32)exit_qualification >> 30;
7589 if (reason == TASK_SWITCH_GATE && idt_v) {
7591 case INTR_TYPE_NMI_INTR:
7592 vcpu->arch.nmi_injected = false;
7593 vmx_set_nmi_mask(vcpu, true);
7595 case INTR_TYPE_EXT_INTR:
7596 case INTR_TYPE_SOFT_INTR:
7597 kvm_clear_interrupt_queue(vcpu);
7599 case INTR_TYPE_HARD_EXCEPTION:
7600 if (vmx->idt_vectoring_info &
7601 VECTORING_INFO_DELIVER_CODE_MASK) {
7602 has_error_code = true;
7604 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7607 case INTR_TYPE_SOFT_EXCEPTION:
7608 kvm_clear_exception_queue(vcpu);
7614 tss_selector = exit_qualification;
7616 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
7617 type != INTR_TYPE_EXT_INTR &&
7618 type != INTR_TYPE_NMI_INTR))
7619 skip_emulated_instruction(vcpu);
7621 if (kvm_task_switch(vcpu, tss_selector,
7622 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
7623 has_error_code, error_code) == EMULATE_FAIL) {
7624 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7625 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7626 vcpu->run->internal.ndata = 0;
7631 * TODO: What about debug traps on tss switch?
7632 * Are we supposed to inject them and update dr6?
7638 static int handle_ept_violation(struct kvm_vcpu *vcpu)
7640 unsigned long exit_qualification;
7644 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7647 * EPT violation happened while executing iret from NMI,
7648 * "blocked by NMI" bit has to be set before next VM entry.
7649 * There are errata that may cause this bit to not be set:
7652 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7654 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7655 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
7657 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7658 trace_kvm_page_fault(gpa, exit_qualification);
7660 /* Is it a read fault? */
7661 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
7662 ? PFERR_USER_MASK : 0;
7663 /* Is it a write fault? */
7664 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
7665 ? PFERR_WRITE_MASK : 0;
7666 /* Is it a fetch fault? */
7667 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
7668 ? PFERR_FETCH_MASK : 0;
7669 /* ept page table entry is present? */
7670 error_code |= (exit_qualification &
7671 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
7672 EPT_VIOLATION_EXECUTABLE))
7673 ? PFERR_PRESENT_MASK : 0;
7675 error_code |= (exit_qualification & 0x100) != 0 ?
7676 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
7678 vcpu->arch.exit_qualification = exit_qualification;
7679 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
7682 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
7687 * A nested guest cannot optimize MMIO vmexits, because we have an
7688 * nGPA here instead of the required GPA.
7690 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7691 if (!is_guest_mode(vcpu) &&
7692 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
7693 trace_kvm_fast_mmio(gpa);
7695 * Doing kvm_skip_emulated_instruction() depends on undefined
7696 * behavior: Intel's manual doesn't mandate
7697 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
7698 * occurs and while on real hardware it was observed to be set,
7699 * other hypervisors (namely Hyper-V) don't set it, we end up
7700 * advancing IP with some random value. Disable fast mmio when
7701 * running nested and keep it for real hardware in hope that
7702 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
7704 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
7705 return kvm_skip_emulated_instruction(vcpu);
7707 return x86_emulate_instruction(vcpu, gpa, EMULTYPE_SKIP,
7708 NULL, 0) == EMULATE_DONE;
7711 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
7714 static int handle_nmi_window(struct kvm_vcpu *vcpu)
7716 WARN_ON_ONCE(!enable_vnmi);
7717 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7718 CPU_BASED_VIRTUAL_NMI_PENDING);
7719 ++vcpu->stat.nmi_window_exits;
7720 kvm_make_request(KVM_REQ_EVENT, vcpu);
7725 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
7727 struct vcpu_vmx *vmx = to_vmx(vcpu);
7728 enum emulation_result err = EMULATE_DONE;
7731 bool intr_window_requested;
7732 unsigned count = 130;
7735 * We should never reach the point where we are emulating L2
7736 * due to invalid guest state as that means we incorrectly
7737 * allowed a nested VMEntry with an invalid vmcs12.
7739 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
7741 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7742 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
7744 while (vmx->emulation_required && count-- != 0) {
7745 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
7746 return handle_interrupt_window(&vmx->vcpu);
7748 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
7751 err = emulate_instruction(vcpu, 0);
7753 if (err == EMULATE_USER_EXIT) {
7754 ++vcpu->stat.mmio_exits;
7759 if (err != EMULATE_DONE)
7760 goto emulation_error;
7762 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
7763 vcpu->arch.exception.pending)
7764 goto emulation_error;
7766 if (vcpu->arch.halt_request) {
7767 vcpu->arch.halt_request = 0;
7768 ret = kvm_vcpu_halt(vcpu);
7772 if (signal_pending(current))
7782 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7783 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7784 vcpu->run->internal.ndata = 0;
7788 static void grow_ple_window(struct kvm_vcpu *vcpu)
7790 struct vcpu_vmx *vmx = to_vmx(vcpu);
7791 int old = vmx->ple_window;
7793 vmx->ple_window = __grow_ple_window(old, ple_window,
7797 if (vmx->ple_window != old)
7798 vmx->ple_window_dirty = true;
7800 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
7803 static void shrink_ple_window(struct kvm_vcpu *vcpu)
7805 struct vcpu_vmx *vmx = to_vmx(vcpu);
7806 int old = vmx->ple_window;
7808 vmx->ple_window = __shrink_ple_window(old, ple_window,
7812 if (vmx->ple_window != old)
7813 vmx->ple_window_dirty = true;
7815 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
7819 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
7821 static void wakeup_handler(void)
7823 struct kvm_vcpu *vcpu;
7824 int cpu = smp_processor_id();
7826 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7827 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
7828 blocked_vcpu_list) {
7829 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7831 if (pi_test_on(pi_desc) == 1)
7832 kvm_vcpu_kick(vcpu);
7834 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7837 static void vmx_enable_tdp(void)
7839 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
7840 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
7841 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
7842 0ull, VMX_EPT_EXECUTABLE_MASK,
7843 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
7844 VMX_EPT_RWX_MASK, 0ull);
7846 ept_set_mmio_spte_mask();
7850 static __init int hardware_setup(void)
7852 unsigned long host_bndcfgs;
7855 rdmsrl_safe(MSR_EFER, &host_efer);
7857 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7858 kvm_define_shared_msr(i, vmx_msr_index[i]);
7860 for (i = 0; i < VMX_BITMAP_NR; i++) {
7861 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
7866 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
7867 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
7869 if (setup_vmcs_config(&vmcs_config) < 0) {
7874 if (boot_cpu_has(X86_FEATURE_NX))
7875 kvm_enable_efer_bits(EFER_NX);
7877 if (boot_cpu_has(X86_FEATURE_MPX)) {
7878 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7879 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7882 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7883 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7886 if (!cpu_has_vmx_ept() ||
7887 !cpu_has_vmx_ept_4levels() ||
7888 !cpu_has_vmx_ept_mt_wb() ||
7889 !cpu_has_vmx_invept_global())
7892 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7893 enable_ept_ad_bits = 0;
7895 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7896 enable_unrestricted_guest = 0;
7898 if (!cpu_has_vmx_flexpriority())
7899 flexpriority_enabled = 0;
7901 if (!cpu_has_virtual_nmis())
7905 * set_apic_access_page_addr() is used to reload apic access
7906 * page upon invalidation. No need to do anything if not
7907 * using the APIC_ACCESS_ADDR VMCS field.
7909 if (!flexpriority_enabled)
7910 kvm_x86_ops->set_apic_access_page_addr = NULL;
7912 if (!cpu_has_vmx_tpr_shadow())
7913 kvm_x86_ops->update_cr8_intercept = NULL;
7915 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7916 kvm_disable_largepages();
7918 #if IS_ENABLED(CONFIG_HYPERV)
7919 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7921 kvm_x86_ops->tlb_remote_flush = vmx_hv_remote_flush_tlb;
7924 if (!cpu_has_vmx_ple()) {
7927 ple_window_grow = 0;
7929 ple_window_shrink = 0;
7932 if (!cpu_has_vmx_apicv()) {
7934 kvm_x86_ops->sync_pir_to_irr = NULL;
7937 if (cpu_has_vmx_tsc_scaling()) {
7938 kvm_has_tsc_control = true;
7939 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7940 kvm_tsc_scaling_ratio_frac_bits = 48;
7943 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7951 kvm_x86_ops->get_nested_state = NULL;
7952 kvm_x86_ops->set_nested_state = NULL;
7956 * Only enable PML when hardware supports PML feature, and both EPT
7957 * and EPT A/D bit features are enabled -- PML depends on them to work.
7959 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7963 kvm_x86_ops->slot_enable_log_dirty = NULL;
7964 kvm_x86_ops->slot_disable_log_dirty = NULL;
7965 kvm_x86_ops->flush_log_dirty = NULL;
7966 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7969 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7972 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7973 cpu_preemption_timer_multi =
7974 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7976 kvm_x86_ops->set_hv_timer = NULL;
7977 kvm_x86_ops->cancel_hv_timer = NULL;
7980 if (!cpu_has_vmx_shadow_vmcs())
7981 enable_shadow_vmcs = 0;
7982 if (enable_shadow_vmcs)
7983 init_vmcs_shadow_fields();
7985 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7986 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, enable_apicv);
7988 kvm_mce_cap_supported |= MCG_LMCE_P;
7990 return alloc_kvm_area();
7993 for (i = 0; i < VMX_BITMAP_NR; i++)
7994 free_page((unsigned long)vmx_bitmap[i]);
7999 static __exit void hardware_unsetup(void)
8003 for (i = 0; i < VMX_BITMAP_NR; i++)
8004 free_page((unsigned long)vmx_bitmap[i]);
8010 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
8011 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
8013 static int handle_pause(struct kvm_vcpu *vcpu)
8015 if (!kvm_pause_in_guest(vcpu->kvm))
8016 grow_ple_window(vcpu);
8019 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
8020 * VM-execution control is ignored if CPL > 0. OTOH, KVM
8021 * never set PAUSE_EXITING and just set PLE if supported,
8022 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
8024 kvm_vcpu_on_spin(vcpu, true);
8025 return kvm_skip_emulated_instruction(vcpu);
8028 static int handle_nop(struct kvm_vcpu *vcpu)
8030 return kvm_skip_emulated_instruction(vcpu);
8033 static int handle_mwait(struct kvm_vcpu *vcpu)
8035 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
8036 return handle_nop(vcpu);
8039 static int handle_invalid_op(struct kvm_vcpu *vcpu)
8041 kvm_queue_exception(vcpu, UD_VECTOR);
8045 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
8050 static int handle_monitor(struct kvm_vcpu *vcpu)
8052 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
8053 return handle_nop(vcpu);
8057 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
8058 * set the success or error code of an emulated VMX instruction, as specified
8059 * by Vol 2B, VMX Instruction Reference, "Conventions".
8061 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
8063 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
8064 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
8065 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
8068 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
8070 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
8071 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
8072 X86_EFLAGS_SF | X86_EFLAGS_OF))
8076 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
8077 u32 vm_instruction_error)
8079 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
8081 * failValid writes the error number to the current VMCS, which
8082 * can't be done there isn't a current VMCS.
8084 nested_vmx_failInvalid(vcpu);
8087 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
8088 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
8089 X86_EFLAGS_SF | X86_EFLAGS_OF))
8091 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
8093 * We don't need to force a shadow sync because
8094 * VM_INSTRUCTION_ERROR is not shadowed
8098 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
8100 /* TODO: not to reset guest simply here. */
8101 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8102 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
8105 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
8107 struct vcpu_vmx *vmx =
8108 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
8110 vmx->nested.preemption_timer_expired = true;
8111 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
8112 kvm_vcpu_kick(&vmx->vcpu);
8114 return HRTIMER_NORESTART;
8118 * Decode the memory-address operand of a vmx instruction, as recorded on an
8119 * exit caused by such an instruction (run by a guest hypervisor).
8120 * On success, returns 0. When the operand is invalid, returns 1 and throws
8123 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
8124 unsigned long exit_qualification,
8125 u32 vmx_instruction_info, bool wr, gva_t *ret)
8129 struct kvm_segment s;
8132 * According to Vol. 3B, "Information for VM Exits Due to Instruction
8133 * Execution", on an exit, vmx_instruction_info holds most of the
8134 * addressing components of the operand. Only the displacement part
8135 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
8136 * For how an actual address is calculated from all these components,
8137 * refer to Vol. 1, "Operand Addressing".
8139 int scaling = vmx_instruction_info & 3;
8140 int addr_size = (vmx_instruction_info >> 7) & 7;
8141 bool is_reg = vmx_instruction_info & (1u << 10);
8142 int seg_reg = (vmx_instruction_info >> 15) & 7;
8143 int index_reg = (vmx_instruction_info >> 18) & 0xf;
8144 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
8145 int base_reg = (vmx_instruction_info >> 23) & 0xf;
8146 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
8149 kvm_queue_exception(vcpu, UD_VECTOR);
8153 /* Addr = segment_base + offset */
8154 /* offset = base + [index * scale] + displacement */
8155 off = exit_qualification; /* holds the displacement */
8157 off += kvm_register_read(vcpu, base_reg);
8159 off += kvm_register_read(vcpu, index_reg)<<scaling;
8160 vmx_get_segment(vcpu, &s, seg_reg);
8161 *ret = s.base + off;
8163 if (addr_size == 1) /* 32 bit */
8166 /* Checks for #GP/#SS exceptions. */
8168 if (is_long_mode(vcpu)) {
8169 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
8170 * non-canonical form. This is the only check on the memory
8171 * destination for long mode!
8173 exn = is_noncanonical_address(*ret, vcpu);
8174 } else if (is_protmode(vcpu)) {
8175 /* Protected mode: apply checks for segment validity in the
8177 * - segment type check (#GP(0) may be thrown)
8178 * - usability check (#GP(0)/#SS(0))
8179 * - limit check (#GP(0)/#SS(0))
8182 /* #GP(0) if the destination operand is located in a
8183 * read-only data segment or any code segment.
8185 exn = ((s.type & 0xa) == 0 || (s.type & 8));
8187 /* #GP(0) if the source operand is located in an
8188 * execute-only code segment
8190 exn = ((s.type & 0xa) == 8);
8192 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8195 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
8197 exn = (s.unusable != 0);
8198 /* Protected mode: #GP(0)/#SS(0) if the memory
8199 * operand is outside the segment limit.
8201 exn = exn || (off + sizeof(u64) > s.limit);
8204 kvm_queue_exception_e(vcpu,
8205 seg_reg == VCPU_SREG_SS ?
8206 SS_VECTOR : GP_VECTOR,
8214 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
8217 struct x86_exception e;
8219 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8220 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
8223 if (kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e)) {
8224 kvm_inject_page_fault(vcpu, &e);
8232 * Allocate a shadow VMCS and associate it with the currently loaded
8233 * VMCS, unless such a shadow VMCS already exists. The newly allocated
8234 * VMCS is also VMCLEARed, so that it is ready for use.
8236 static struct vmcs *alloc_shadow_vmcs(struct kvm_vcpu *vcpu)
8238 struct vcpu_vmx *vmx = to_vmx(vcpu);
8239 struct loaded_vmcs *loaded_vmcs = vmx->loaded_vmcs;
8242 * We should allocate a shadow vmcs for vmcs01 only when L1
8243 * executes VMXON and free it when L1 executes VMXOFF.
8244 * As it is invalid to execute VMXON twice, we shouldn't reach
8245 * here when vmcs01 already have an allocated shadow vmcs.
8247 WARN_ON(loaded_vmcs == &vmx->vmcs01 && loaded_vmcs->shadow_vmcs);
8249 if (!loaded_vmcs->shadow_vmcs) {
8250 loaded_vmcs->shadow_vmcs = alloc_vmcs(true);
8251 if (loaded_vmcs->shadow_vmcs)
8252 vmcs_clear(loaded_vmcs->shadow_vmcs);
8254 return loaded_vmcs->shadow_vmcs;
8257 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
8259 struct vcpu_vmx *vmx = to_vmx(vcpu);
8262 r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
8266 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
8267 if (!vmx->nested.cached_vmcs12)
8268 goto out_cached_vmcs12;
8270 vmx->nested.cached_shadow_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
8271 if (!vmx->nested.cached_shadow_vmcs12)
8272 goto out_cached_shadow_vmcs12;
8274 if (enable_shadow_vmcs && !alloc_shadow_vmcs(vcpu))
8275 goto out_shadow_vmcs;
8277 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
8278 HRTIMER_MODE_REL_PINNED);
8279 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
8281 vmx->nested.vpid02 = allocate_vpid();
8283 vmx->nested.vmxon = true;
8287 kfree(vmx->nested.cached_shadow_vmcs12);
8289 out_cached_shadow_vmcs12:
8290 kfree(vmx->nested.cached_vmcs12);
8293 free_loaded_vmcs(&vmx->nested.vmcs02);
8300 * Emulate the VMXON instruction.
8301 * Currently, we just remember that VMX is active, and do not save or even
8302 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
8303 * do not currently need to store anything in that guest-allocated memory
8304 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
8305 * argument is different from the VMXON pointer (which the spec says they do).
8307 static int handle_vmon(struct kvm_vcpu *vcpu)
8312 struct vcpu_vmx *vmx = to_vmx(vcpu);
8313 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
8314 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
8317 * The Intel VMX Instruction Reference lists a bunch of bits that are
8318 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
8319 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
8320 * Otherwise, we should fail with #UD. But most faulting conditions
8321 * have already been checked by hardware, prior to the VM-exit for
8322 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
8323 * that bit set to 1 in non-root mode.
8325 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
8326 kvm_queue_exception(vcpu, UD_VECTOR);
8330 /* CPL=0 must be checked manually. */
8331 if (vmx_get_cpl(vcpu)) {
8332 kvm_inject_gp(vcpu, 0);
8336 if (vmx->nested.vmxon) {
8337 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
8338 return kvm_skip_emulated_instruction(vcpu);
8341 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
8342 != VMXON_NEEDED_FEATURES) {
8343 kvm_inject_gp(vcpu, 0);
8347 if (nested_vmx_get_vmptr(vcpu, &vmptr))
8352 * The first 4 bytes of VMXON region contain the supported
8353 * VMCS revision identifier
8355 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
8356 * which replaces physical address width with 32
8358 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8359 nested_vmx_failInvalid(vcpu);
8360 return kvm_skip_emulated_instruction(vcpu);
8363 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8364 if (is_error_page(page)) {
8365 nested_vmx_failInvalid(vcpu);
8366 return kvm_skip_emulated_instruction(vcpu);
8368 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
8370 kvm_release_page_clean(page);
8371 nested_vmx_failInvalid(vcpu);
8372 return kvm_skip_emulated_instruction(vcpu);
8375 kvm_release_page_clean(page);
8377 vmx->nested.vmxon_ptr = vmptr;
8378 ret = enter_vmx_operation(vcpu);
8382 nested_vmx_succeed(vcpu);
8383 return kvm_skip_emulated_instruction(vcpu);
8387 * Intel's VMX Instruction Reference specifies a common set of prerequisites
8388 * for running VMX instructions (except VMXON, whose prerequisites are
8389 * slightly different). It also specifies what exception to inject otherwise.
8390 * Note that many of these exceptions have priority over VM exits, so they
8391 * don't have to be checked again here.
8393 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
8395 if (!to_vmx(vcpu)->nested.vmxon) {
8396 kvm_queue_exception(vcpu, UD_VECTOR);
8400 if (vmx_get_cpl(vcpu)) {
8401 kvm_inject_gp(vcpu, 0);
8408 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
8410 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
8411 vmcs_write64(VMCS_LINK_POINTER, -1ull);
8414 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
8416 if (vmx->nested.current_vmptr == -1ull)
8419 if (enable_shadow_vmcs) {
8420 /* copy to memory all shadowed fields in case
8421 they were modified */
8422 copy_shadow_to_vmcs12(vmx);
8423 vmx->nested.sync_shadow_vmcs = false;
8424 vmx_disable_shadow_vmcs(vmx);
8426 vmx->nested.posted_intr_nv = -1;
8428 /* Flush VMCS12 to guest memory */
8429 kvm_vcpu_write_guest_page(&vmx->vcpu,
8430 vmx->nested.current_vmptr >> PAGE_SHIFT,
8431 vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
8433 vmx->nested.current_vmptr = -1ull;
8437 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
8438 * just stops using VMX.
8440 static void free_nested(struct vcpu_vmx *vmx)
8442 if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
8445 vmx->nested.vmxon = false;
8446 vmx->nested.smm.vmxon = false;
8447 free_vpid(vmx->nested.vpid02);
8448 vmx->nested.posted_intr_nv = -1;
8449 vmx->nested.current_vmptr = -1ull;
8450 if (enable_shadow_vmcs) {
8451 vmx_disable_shadow_vmcs(vmx);
8452 vmcs_clear(vmx->vmcs01.shadow_vmcs);
8453 free_vmcs(vmx->vmcs01.shadow_vmcs);
8454 vmx->vmcs01.shadow_vmcs = NULL;
8456 kfree(vmx->nested.cached_vmcs12);
8457 kfree(vmx->nested.cached_shadow_vmcs12);
8458 /* Unpin physical memory we referred to in the vmcs02 */
8459 if (vmx->nested.apic_access_page) {
8460 kvm_release_page_dirty(vmx->nested.apic_access_page);
8461 vmx->nested.apic_access_page = NULL;
8463 if (vmx->nested.virtual_apic_page) {
8464 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
8465 vmx->nested.virtual_apic_page = NULL;
8467 if (vmx->nested.pi_desc_page) {
8468 kunmap(vmx->nested.pi_desc_page);
8469 kvm_release_page_dirty(vmx->nested.pi_desc_page);
8470 vmx->nested.pi_desc_page = NULL;
8471 vmx->nested.pi_desc = NULL;
8474 free_loaded_vmcs(&vmx->nested.vmcs02);
8477 /* Emulate the VMXOFF instruction */
8478 static int handle_vmoff(struct kvm_vcpu *vcpu)
8480 if (!nested_vmx_check_permission(vcpu))
8482 free_nested(to_vmx(vcpu));
8483 nested_vmx_succeed(vcpu);
8484 return kvm_skip_emulated_instruction(vcpu);
8487 /* Emulate the VMCLEAR instruction */
8488 static int handle_vmclear(struct kvm_vcpu *vcpu)
8490 struct vcpu_vmx *vmx = to_vmx(vcpu);
8494 if (!nested_vmx_check_permission(vcpu))
8497 if (nested_vmx_get_vmptr(vcpu, &vmptr))
8500 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8501 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
8502 return kvm_skip_emulated_instruction(vcpu);
8505 if (vmptr == vmx->nested.vmxon_ptr) {
8506 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
8507 return kvm_skip_emulated_instruction(vcpu);
8510 if (vmptr == vmx->nested.current_vmptr)
8511 nested_release_vmcs12(vmx);
8513 kvm_vcpu_write_guest(vcpu,
8514 vmptr + offsetof(struct vmcs12, launch_state),
8515 &zero, sizeof(zero));
8517 nested_vmx_succeed(vcpu);
8518 return kvm_skip_emulated_instruction(vcpu);
8521 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
8523 /* Emulate the VMLAUNCH instruction */
8524 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
8526 return nested_vmx_run(vcpu, true);
8529 /* Emulate the VMRESUME instruction */
8530 static int handle_vmresume(struct kvm_vcpu *vcpu)
8533 return nested_vmx_run(vcpu, false);
8537 * Read a vmcs12 field. Since these can have varying lengths and we return
8538 * one type, we chose the biggest type (u64) and zero-extend the return value
8539 * to that size. Note that the caller, handle_vmread, might need to use only
8540 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
8541 * 64-bit fields are to be returned).
8543 static inline int vmcs12_read_any(struct vmcs12 *vmcs12,
8544 unsigned long field, u64 *ret)
8546 short offset = vmcs_field_to_offset(field);
8552 p = (char *)vmcs12 + offset;
8554 switch (vmcs_field_width(field)) {
8555 case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8556 *ret = *((natural_width *)p);
8558 case VMCS_FIELD_WIDTH_U16:
8561 case VMCS_FIELD_WIDTH_U32:
8564 case VMCS_FIELD_WIDTH_U64:
8574 static inline int vmcs12_write_any(struct vmcs12 *vmcs12,
8575 unsigned long field, u64 field_value){
8576 short offset = vmcs_field_to_offset(field);
8577 char *p = (char *)vmcs12 + offset;
8581 switch (vmcs_field_width(field)) {
8582 case VMCS_FIELD_WIDTH_U16:
8583 *(u16 *)p = field_value;
8585 case VMCS_FIELD_WIDTH_U32:
8586 *(u32 *)p = field_value;
8588 case VMCS_FIELD_WIDTH_U64:
8589 *(u64 *)p = field_value;
8591 case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8592 *(natural_width *)p = field_value;
8602 * Copy the writable VMCS shadow fields back to the VMCS12, in case
8603 * they have been modified by the L1 guest. Note that the "read-only"
8604 * VM-exit information fields are actually writable if the vCPU is
8605 * configured to support "VMWRITE to any supported field in the VMCS."
8607 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
8609 const u16 *fields[] = {
8610 shadow_read_write_fields,
8611 shadow_read_only_fields
8613 const int max_fields[] = {
8614 max_shadow_read_write_fields,
8615 max_shadow_read_only_fields
8618 unsigned long field;
8620 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8624 vmcs_load(shadow_vmcs);
8626 for (q = 0; q < ARRAY_SIZE(fields); q++) {
8627 for (i = 0; i < max_fields[q]; i++) {
8628 field = fields[q][i];
8629 field_value = __vmcs_readl(field);
8630 vmcs12_write_any(get_vmcs12(&vmx->vcpu), field, field_value);
8633 * Skip the VM-exit information fields if they are read-only.
8635 if (!nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
8639 vmcs_clear(shadow_vmcs);
8640 vmcs_load(vmx->loaded_vmcs->vmcs);
8645 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
8647 const u16 *fields[] = {
8648 shadow_read_write_fields,
8649 shadow_read_only_fields
8651 const int max_fields[] = {
8652 max_shadow_read_write_fields,
8653 max_shadow_read_only_fields
8656 unsigned long field;
8657 u64 field_value = 0;
8658 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8660 vmcs_load(shadow_vmcs);
8662 for (q = 0; q < ARRAY_SIZE(fields); q++) {
8663 for (i = 0; i < max_fields[q]; i++) {
8664 field = fields[q][i];
8665 vmcs12_read_any(get_vmcs12(&vmx->vcpu), field, &field_value);
8666 __vmcs_writel(field, field_value);
8670 vmcs_clear(shadow_vmcs);
8671 vmcs_load(vmx->loaded_vmcs->vmcs);
8675 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
8676 * used before) all generate the same failure when it is missing.
8678 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
8680 struct vcpu_vmx *vmx = to_vmx(vcpu);
8681 if (vmx->nested.current_vmptr == -1ull) {
8682 nested_vmx_failInvalid(vcpu);
8688 static int handle_vmread(struct kvm_vcpu *vcpu)
8690 unsigned long field;
8692 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8693 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8695 struct vmcs12 *vmcs12;
8697 if (!nested_vmx_check_permission(vcpu))
8700 if (!nested_vmx_check_vmcs12(vcpu))
8701 return kvm_skip_emulated_instruction(vcpu);
8703 if (!is_guest_mode(vcpu))
8704 vmcs12 = get_vmcs12(vcpu);
8707 * When vmcs->vmcs_link_pointer is -1ull, any VMREAD
8708 * to shadowed-field sets the ALU flags for VMfailInvalid.
8710 if (get_vmcs12(vcpu)->vmcs_link_pointer == -1ull) {
8711 nested_vmx_failInvalid(vcpu);
8712 return kvm_skip_emulated_instruction(vcpu);
8714 vmcs12 = get_shadow_vmcs12(vcpu);
8717 /* Decode instruction info and find the field to read */
8718 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8719 /* Read the field, zero-extended to a u64 field_value */
8720 if (vmcs12_read_any(vmcs12, field, &field_value) < 0) {
8721 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8722 return kvm_skip_emulated_instruction(vcpu);
8725 * Now copy part of this value to register or memory, as requested.
8726 * Note that the number of bits actually copied is 32 or 64 depending
8727 * on the guest's mode (32 or 64 bit), not on the given field's length.
8729 if (vmx_instruction_info & (1u << 10)) {
8730 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
8733 if (get_vmx_mem_address(vcpu, exit_qualification,
8734 vmx_instruction_info, true, &gva))
8736 /* _system ok, nested_vmx_check_permission has verified cpl=0 */
8737 kvm_write_guest_virt_system(vcpu, gva, &field_value,
8738 (is_long_mode(vcpu) ? 8 : 4), NULL);
8741 nested_vmx_succeed(vcpu);
8742 return kvm_skip_emulated_instruction(vcpu);
8746 static int handle_vmwrite(struct kvm_vcpu *vcpu)
8748 unsigned long field;
8750 struct vcpu_vmx *vmx = to_vmx(vcpu);
8751 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8752 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8754 /* The value to write might be 32 or 64 bits, depending on L1's long
8755 * mode, and eventually we need to write that into a field of several
8756 * possible lengths. The code below first zero-extends the value to 64
8757 * bit (field_value), and then copies only the appropriate number of
8758 * bits into the vmcs12 field.
8760 u64 field_value = 0;
8761 struct x86_exception e;
8762 struct vmcs12 *vmcs12;
8764 if (!nested_vmx_check_permission(vcpu))
8767 if (!nested_vmx_check_vmcs12(vcpu))
8768 return kvm_skip_emulated_instruction(vcpu);
8770 if (vmx_instruction_info & (1u << 10))
8771 field_value = kvm_register_readl(vcpu,
8772 (((vmx_instruction_info) >> 3) & 0xf));
8774 if (get_vmx_mem_address(vcpu, exit_qualification,
8775 vmx_instruction_info, false, &gva))
8777 if (kvm_read_guest_virt(vcpu, gva, &field_value,
8778 (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
8779 kvm_inject_page_fault(vcpu, &e);
8785 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8787 * If the vCPU supports "VMWRITE to any supported field in the
8788 * VMCS," then the "read-only" fields are actually read/write.
8790 if (vmcs_field_readonly(field) &&
8791 !nested_cpu_has_vmwrite_any_field(vcpu)) {
8792 nested_vmx_failValid(vcpu,
8793 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
8794 return kvm_skip_emulated_instruction(vcpu);
8797 if (!is_guest_mode(vcpu))
8798 vmcs12 = get_vmcs12(vcpu);
8801 * When vmcs->vmcs_link_pointer is -1ull, any VMWRITE
8802 * to shadowed-field sets the ALU flags for VMfailInvalid.
8804 if (get_vmcs12(vcpu)->vmcs_link_pointer == -1ull) {
8805 nested_vmx_failInvalid(vcpu);
8806 return kvm_skip_emulated_instruction(vcpu);
8808 vmcs12 = get_shadow_vmcs12(vcpu);
8812 if (vmcs12_write_any(vmcs12, field, field_value) < 0) {
8813 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8814 return kvm_skip_emulated_instruction(vcpu);
8818 * Do not track vmcs12 dirty-state if in guest-mode
8819 * as we actually dirty shadow vmcs12 instead of vmcs12.
8821 if (!is_guest_mode(vcpu)) {
8823 #define SHADOW_FIELD_RW(x) case x:
8824 #include "vmx_shadow_fields.h"
8826 * The fields that can be updated by L1 without a vmexit are
8827 * always updated in the vmcs02, the others go down the slow
8828 * path of prepare_vmcs02.
8832 vmx->nested.dirty_vmcs12 = true;
8837 nested_vmx_succeed(vcpu);
8838 return kvm_skip_emulated_instruction(vcpu);
8841 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
8843 vmx->nested.current_vmptr = vmptr;
8844 if (enable_shadow_vmcs) {
8845 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
8846 SECONDARY_EXEC_SHADOW_VMCS);
8847 vmcs_write64(VMCS_LINK_POINTER,
8848 __pa(vmx->vmcs01.shadow_vmcs));
8849 vmx->nested.sync_shadow_vmcs = true;
8851 vmx->nested.dirty_vmcs12 = true;
8854 /* Emulate the VMPTRLD instruction */
8855 static int handle_vmptrld(struct kvm_vcpu *vcpu)
8857 struct vcpu_vmx *vmx = to_vmx(vcpu);
8860 if (!nested_vmx_check_permission(vcpu))
8863 if (nested_vmx_get_vmptr(vcpu, &vmptr))
8866 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8867 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
8868 return kvm_skip_emulated_instruction(vcpu);
8871 if (vmptr == vmx->nested.vmxon_ptr) {
8872 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
8873 return kvm_skip_emulated_instruction(vcpu);
8876 if (vmx->nested.current_vmptr != vmptr) {
8877 struct vmcs12 *new_vmcs12;
8879 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8880 if (is_error_page(page)) {
8881 nested_vmx_failInvalid(vcpu);
8882 return kvm_skip_emulated_instruction(vcpu);
8884 new_vmcs12 = kmap(page);
8885 if (new_vmcs12->hdr.revision_id != VMCS12_REVISION ||
8886 (new_vmcs12->hdr.shadow_vmcs &&
8887 !nested_cpu_has_vmx_shadow_vmcs(vcpu))) {
8889 kvm_release_page_clean(page);
8890 nested_vmx_failValid(vcpu,
8891 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
8892 return kvm_skip_emulated_instruction(vcpu);
8895 nested_release_vmcs12(vmx);
8897 * Load VMCS12 from guest memory since it is not already
8900 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
8902 kvm_release_page_clean(page);
8904 set_current_vmptr(vmx, vmptr);
8907 nested_vmx_succeed(vcpu);
8908 return kvm_skip_emulated_instruction(vcpu);
8911 /* Emulate the VMPTRST instruction */
8912 static int handle_vmptrst(struct kvm_vcpu *vcpu)
8914 unsigned long exit_qual = vmcs_readl(EXIT_QUALIFICATION);
8915 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8916 gpa_t current_vmptr = to_vmx(vcpu)->nested.current_vmptr;
8917 struct x86_exception e;
8920 if (!nested_vmx_check_permission(vcpu))
8923 if (get_vmx_mem_address(vcpu, exit_qual, instr_info, true, &gva))
8925 /* *_system ok, nested_vmx_check_permission has verified cpl=0 */
8926 if (kvm_write_guest_virt_system(vcpu, gva, (void *)¤t_vmptr,
8927 sizeof(gpa_t), &e)) {
8928 kvm_inject_page_fault(vcpu, &e);
8931 nested_vmx_succeed(vcpu);
8932 return kvm_skip_emulated_instruction(vcpu);
8935 /* Emulate the INVEPT instruction */
8936 static int handle_invept(struct kvm_vcpu *vcpu)
8938 struct vcpu_vmx *vmx = to_vmx(vcpu);
8939 u32 vmx_instruction_info, types;
8942 struct x86_exception e;
8947 if (!(vmx->nested.msrs.secondary_ctls_high &
8948 SECONDARY_EXEC_ENABLE_EPT) ||
8949 !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) {
8950 kvm_queue_exception(vcpu, UD_VECTOR);
8954 if (!nested_vmx_check_permission(vcpu))
8957 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8958 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8960 types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
8962 if (type >= 32 || !(types & (1 << type))) {
8963 nested_vmx_failValid(vcpu,
8964 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8965 return kvm_skip_emulated_instruction(vcpu);
8968 /* According to the Intel VMX instruction reference, the memory
8969 * operand is read even if it isn't needed (e.g., for type==global)
8971 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8972 vmx_instruction_info, false, &gva))
8974 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
8975 kvm_inject_page_fault(vcpu, &e);
8980 case VMX_EPT_EXTENT_GLOBAL:
8982 * TODO: track mappings and invalidate
8983 * single context requests appropriately
8985 case VMX_EPT_EXTENT_CONTEXT:
8986 kvm_mmu_sync_roots(vcpu);
8987 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
8988 nested_vmx_succeed(vcpu);
8995 return kvm_skip_emulated_instruction(vcpu);
8998 static int handle_invvpid(struct kvm_vcpu *vcpu)
9000 struct vcpu_vmx *vmx = to_vmx(vcpu);
9001 u32 vmx_instruction_info;
9002 unsigned long type, types;
9004 struct x86_exception e;
9010 if (!(vmx->nested.msrs.secondary_ctls_high &
9011 SECONDARY_EXEC_ENABLE_VPID) ||
9012 !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) {
9013 kvm_queue_exception(vcpu, UD_VECTOR);
9017 if (!nested_vmx_check_permission(vcpu))
9020 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9021 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
9023 types = (vmx->nested.msrs.vpid_caps &
9024 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
9026 if (type >= 32 || !(types & (1 << type))) {
9027 nested_vmx_failValid(vcpu,
9028 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9029 return kvm_skip_emulated_instruction(vcpu);
9032 /* according to the intel vmx instruction reference, the memory
9033 * operand is read even if it isn't needed (e.g., for type==global)
9035 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
9036 vmx_instruction_info, false, &gva))
9038 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
9039 kvm_inject_page_fault(vcpu, &e);
9042 if (operand.vpid >> 16) {
9043 nested_vmx_failValid(vcpu,
9044 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9045 return kvm_skip_emulated_instruction(vcpu);
9049 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
9050 if (!operand.vpid ||
9051 is_noncanonical_address(operand.gla, vcpu)) {
9052 nested_vmx_failValid(vcpu,
9053 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9054 return kvm_skip_emulated_instruction(vcpu);
9056 if (cpu_has_vmx_invvpid_individual_addr() &&
9057 vmx->nested.vpid02) {
9058 __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR,
9059 vmx->nested.vpid02, operand.gla);
9061 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
9063 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
9064 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
9065 if (!operand.vpid) {
9066 nested_vmx_failValid(vcpu,
9067 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9068 return kvm_skip_emulated_instruction(vcpu);
9070 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
9072 case VMX_VPID_EXTENT_ALL_CONTEXT:
9073 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
9077 return kvm_skip_emulated_instruction(vcpu);
9080 nested_vmx_succeed(vcpu);
9082 return kvm_skip_emulated_instruction(vcpu);
9085 static int handle_invpcid(struct kvm_vcpu *vcpu)
9087 u32 vmx_instruction_info;
9091 struct x86_exception e;
9093 unsigned long roots_to_free = 0;
9099 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
9100 kvm_queue_exception(vcpu, UD_VECTOR);
9104 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9105 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
9108 kvm_inject_gp(vcpu, 0);
9112 /* According to the Intel instruction reference, the memory operand
9113 * is read even if it isn't needed (e.g., for type==all)
9115 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
9116 vmx_instruction_info, false, &gva))
9119 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
9120 kvm_inject_page_fault(vcpu, &e);
9124 if (operand.pcid >> 12 != 0) {
9125 kvm_inject_gp(vcpu, 0);
9129 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
9132 case INVPCID_TYPE_INDIV_ADDR:
9133 if ((!pcid_enabled && (operand.pcid != 0)) ||
9134 is_noncanonical_address(operand.gla, vcpu)) {
9135 kvm_inject_gp(vcpu, 0);
9138 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
9139 return kvm_skip_emulated_instruction(vcpu);
9141 case INVPCID_TYPE_SINGLE_CTXT:
9142 if (!pcid_enabled && (operand.pcid != 0)) {
9143 kvm_inject_gp(vcpu, 0);
9147 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
9148 kvm_mmu_sync_roots(vcpu);
9149 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
9152 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
9153 if (kvm_get_pcid(vcpu, vcpu->arch.mmu.prev_roots[i].cr3)
9155 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
9157 kvm_mmu_free_roots(vcpu, roots_to_free);
9159 * If neither the current cr3 nor any of the prev_roots use the
9160 * given PCID, then nothing needs to be done here because a
9161 * resync will happen anyway before switching to any other CR3.
9164 return kvm_skip_emulated_instruction(vcpu);
9166 case INVPCID_TYPE_ALL_NON_GLOBAL:
9168 * Currently, KVM doesn't mark global entries in the shadow
9169 * page tables, so a non-global flush just degenerates to a
9170 * global flush. If needed, we could optimize this later by
9171 * keeping track of global entries in shadow page tables.
9175 case INVPCID_TYPE_ALL_INCL_GLOBAL:
9176 kvm_mmu_unload(vcpu);
9177 return kvm_skip_emulated_instruction(vcpu);
9180 BUG(); /* We have already checked above that type <= 3 */
9184 static int handle_pml_full(struct kvm_vcpu *vcpu)
9186 unsigned long exit_qualification;
9188 trace_kvm_pml_full(vcpu->vcpu_id);
9190 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
9193 * PML buffer FULL happened while executing iret from NMI,
9194 * "blocked by NMI" bit has to be set before next VM entry.
9196 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
9198 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
9199 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9200 GUEST_INTR_STATE_NMI);
9203 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
9204 * here.., and there's no userspace involvement needed for PML.
9209 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
9211 kvm_lapic_expired_hv_timer(vcpu);
9215 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
9217 struct vcpu_vmx *vmx = to_vmx(vcpu);
9218 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9220 /* Check for memory type validity */
9221 switch (address & VMX_EPTP_MT_MASK) {
9222 case VMX_EPTP_MT_UC:
9223 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT))
9226 case VMX_EPTP_MT_WB:
9227 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT))
9234 /* only 4 levels page-walk length are valid */
9235 if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
9238 /* Reserved bits should not be set */
9239 if (address >> maxphyaddr || ((address >> 7) & 0x1f))
9242 /* AD, if set, should be supported */
9243 if (address & VMX_EPTP_AD_ENABLE_BIT) {
9244 if (!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT))
9251 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
9252 struct vmcs12 *vmcs12)
9254 u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
9256 bool accessed_dirty;
9257 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
9259 if (!nested_cpu_has_eptp_switching(vmcs12) ||
9260 !nested_cpu_has_ept(vmcs12))
9263 if (index >= VMFUNC_EPTP_ENTRIES)
9267 if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
9268 &address, index * 8, 8))
9271 accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
9274 * If the (L2) guest does a vmfunc to the currently
9275 * active ept pointer, we don't have to do anything else
9277 if (vmcs12->ept_pointer != address) {
9278 if (!valid_ept_address(vcpu, address))
9281 kvm_mmu_unload(vcpu);
9282 mmu->ept_ad = accessed_dirty;
9283 mmu->base_role.ad_disabled = !accessed_dirty;
9284 vmcs12->ept_pointer = address;
9286 * TODO: Check what's the correct approach in case
9287 * mmu reload fails. Currently, we just let the next
9288 * reload potentially fail
9290 kvm_mmu_reload(vcpu);
9296 static int handle_vmfunc(struct kvm_vcpu *vcpu)
9298 struct vcpu_vmx *vmx = to_vmx(vcpu);
9299 struct vmcs12 *vmcs12;
9300 u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
9303 * VMFUNC is only supported for nested guests, but we always enable the
9304 * secondary control for simplicity; for non-nested mode, fake that we
9305 * didn't by injecting #UD.
9307 if (!is_guest_mode(vcpu)) {
9308 kvm_queue_exception(vcpu, UD_VECTOR);
9312 vmcs12 = get_vmcs12(vcpu);
9313 if ((vmcs12->vm_function_control & (1 << function)) == 0)
9318 if (nested_vmx_eptp_switching(vcpu, vmcs12))
9324 return kvm_skip_emulated_instruction(vcpu);
9327 nested_vmx_vmexit(vcpu, vmx->exit_reason,
9328 vmcs_read32(VM_EXIT_INTR_INFO),
9329 vmcs_readl(EXIT_QUALIFICATION));
9333 static int handle_encls(struct kvm_vcpu *vcpu)
9336 * SGX virtualization is not yet supported. There is no software
9337 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
9338 * to prevent the guest from executing ENCLS.
9340 kvm_queue_exception(vcpu, UD_VECTOR);
9345 * The exit handlers return 1 if the exit was handled fully and guest execution
9346 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
9347 * to be done to userspace and return 0.
9349 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
9350 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
9351 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
9352 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
9353 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
9354 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
9355 [EXIT_REASON_CR_ACCESS] = handle_cr,
9356 [EXIT_REASON_DR_ACCESS] = handle_dr,
9357 [EXIT_REASON_CPUID] = handle_cpuid,
9358 [EXIT_REASON_MSR_READ] = handle_rdmsr,
9359 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
9360 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
9361 [EXIT_REASON_HLT] = handle_halt,
9362 [EXIT_REASON_INVD] = handle_invd,
9363 [EXIT_REASON_INVLPG] = handle_invlpg,
9364 [EXIT_REASON_RDPMC] = handle_rdpmc,
9365 [EXIT_REASON_VMCALL] = handle_vmcall,
9366 [EXIT_REASON_VMCLEAR] = handle_vmclear,
9367 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
9368 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
9369 [EXIT_REASON_VMPTRST] = handle_vmptrst,
9370 [EXIT_REASON_VMREAD] = handle_vmread,
9371 [EXIT_REASON_VMRESUME] = handle_vmresume,
9372 [EXIT_REASON_VMWRITE] = handle_vmwrite,
9373 [EXIT_REASON_VMOFF] = handle_vmoff,
9374 [EXIT_REASON_VMON] = handle_vmon,
9375 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
9376 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
9377 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
9378 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
9379 [EXIT_REASON_WBINVD] = handle_wbinvd,
9380 [EXIT_REASON_XSETBV] = handle_xsetbv,
9381 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
9382 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
9383 [EXIT_REASON_GDTR_IDTR] = handle_desc,
9384 [EXIT_REASON_LDTR_TR] = handle_desc,
9385 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
9386 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
9387 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
9388 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
9389 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
9390 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
9391 [EXIT_REASON_INVEPT] = handle_invept,
9392 [EXIT_REASON_INVVPID] = handle_invvpid,
9393 [EXIT_REASON_RDRAND] = handle_invalid_op,
9394 [EXIT_REASON_RDSEED] = handle_invalid_op,
9395 [EXIT_REASON_XSAVES] = handle_xsaves,
9396 [EXIT_REASON_XRSTORS] = handle_xrstors,
9397 [EXIT_REASON_PML_FULL] = handle_pml_full,
9398 [EXIT_REASON_INVPCID] = handle_invpcid,
9399 [EXIT_REASON_VMFUNC] = handle_vmfunc,
9400 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
9401 [EXIT_REASON_ENCLS] = handle_encls,
9404 static const int kvm_vmx_max_exit_handlers =
9405 ARRAY_SIZE(kvm_vmx_exit_handlers);
9407 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
9408 struct vmcs12 *vmcs12)
9410 unsigned long exit_qualification;
9411 gpa_t bitmap, last_bitmap;
9416 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9417 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
9419 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
9421 port = exit_qualification >> 16;
9422 size = (exit_qualification & 7) + 1;
9424 last_bitmap = (gpa_t)-1;
9429 bitmap = vmcs12->io_bitmap_a;
9430 else if (port < 0x10000)
9431 bitmap = vmcs12->io_bitmap_b;
9434 bitmap += (port & 0x7fff) / 8;
9436 if (last_bitmap != bitmap)
9437 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
9439 if (b & (1 << (port & 7)))
9444 last_bitmap = bitmap;
9451 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
9452 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
9453 * disinterest in the current event (read or write a specific MSR) by using an
9454 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
9456 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
9457 struct vmcs12 *vmcs12, u32 exit_reason)
9459 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
9462 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9466 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
9467 * for the four combinations of read/write and low/high MSR numbers.
9468 * First we need to figure out which of the four to use:
9470 bitmap = vmcs12->msr_bitmap;
9471 if (exit_reason == EXIT_REASON_MSR_WRITE)
9473 if (msr_index >= 0xc0000000) {
9474 msr_index -= 0xc0000000;
9478 /* Then read the msr_index'th bit from this bitmap: */
9479 if (msr_index < 1024*8) {
9481 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
9483 return 1 & (b >> (msr_index & 7));
9485 return true; /* let L1 handle the wrong parameter */
9489 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
9490 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
9491 * intercept (via guest_host_mask etc.) the current event.
9493 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
9494 struct vmcs12 *vmcs12)
9496 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
9497 int cr = exit_qualification & 15;
9501 switch ((exit_qualification >> 4) & 3) {
9502 case 0: /* mov to cr */
9503 reg = (exit_qualification >> 8) & 15;
9504 val = kvm_register_readl(vcpu, reg);
9507 if (vmcs12->cr0_guest_host_mask &
9508 (val ^ vmcs12->cr0_read_shadow))
9512 if ((vmcs12->cr3_target_count >= 1 &&
9513 vmcs12->cr3_target_value0 == val) ||
9514 (vmcs12->cr3_target_count >= 2 &&
9515 vmcs12->cr3_target_value1 == val) ||
9516 (vmcs12->cr3_target_count >= 3 &&
9517 vmcs12->cr3_target_value2 == val) ||
9518 (vmcs12->cr3_target_count >= 4 &&
9519 vmcs12->cr3_target_value3 == val))
9521 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
9525 if (vmcs12->cr4_guest_host_mask &
9526 (vmcs12->cr4_read_shadow ^ val))
9530 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
9536 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
9537 (vmcs12->cr0_read_shadow & X86_CR0_TS))
9540 case 1: /* mov from cr */
9543 if (vmcs12->cpu_based_vm_exec_control &
9544 CPU_BASED_CR3_STORE_EXITING)
9548 if (vmcs12->cpu_based_vm_exec_control &
9549 CPU_BASED_CR8_STORE_EXITING)
9556 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
9557 * cr0. Other attempted changes are ignored, with no exit.
9559 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
9560 if (vmcs12->cr0_guest_host_mask & 0xe &
9561 (val ^ vmcs12->cr0_read_shadow))
9563 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
9564 !(vmcs12->cr0_read_shadow & 0x1) &&
9572 static bool nested_vmx_exit_handled_vmcs_access(struct kvm_vcpu *vcpu,
9573 struct vmcs12 *vmcs12, gpa_t bitmap)
9575 u32 vmx_instruction_info;
9576 unsigned long field;
9579 if (!nested_cpu_has_shadow_vmcs(vmcs12))
9582 /* Decode instruction info and find the field to access */
9583 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9584 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
9586 /* Out-of-range fields always cause a VM exit from L2 to L1 */
9590 if (kvm_vcpu_read_guest(vcpu, bitmap + field/8, &b, 1))
9593 return 1 & (b >> (field & 7));
9597 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
9598 * should handle it ourselves in L0 (and then continue L2). Only call this
9599 * when in is_guest_mode (L2).
9601 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
9603 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9604 struct vcpu_vmx *vmx = to_vmx(vcpu);
9605 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9607 if (vmx->nested.nested_run_pending)
9610 if (unlikely(vmx->fail)) {
9611 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
9612 vmcs_read32(VM_INSTRUCTION_ERROR));
9617 * The host physical addresses of some pages of guest memory
9618 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
9619 * Page). The CPU may write to these pages via their host
9620 * physical address while L2 is running, bypassing any
9621 * address-translation-based dirty tracking (e.g. EPT write
9624 * Mark them dirty on every exit from L2 to prevent them from
9625 * getting out of sync with dirty tracking.
9627 nested_mark_vmcs12_pages_dirty(vcpu);
9629 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
9630 vmcs_readl(EXIT_QUALIFICATION),
9631 vmx->idt_vectoring_info,
9633 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9636 switch (exit_reason) {
9637 case EXIT_REASON_EXCEPTION_NMI:
9638 if (is_nmi(intr_info))
9640 else if (is_page_fault(intr_info))
9641 return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
9642 else if (is_no_device(intr_info) &&
9643 !(vmcs12->guest_cr0 & X86_CR0_TS))
9645 else if (is_debug(intr_info) &&
9647 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
9649 else if (is_breakpoint(intr_info) &&
9650 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
9652 return vmcs12->exception_bitmap &
9653 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
9654 case EXIT_REASON_EXTERNAL_INTERRUPT:
9656 case EXIT_REASON_TRIPLE_FAULT:
9658 case EXIT_REASON_PENDING_INTERRUPT:
9659 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
9660 case EXIT_REASON_NMI_WINDOW:
9661 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
9662 case EXIT_REASON_TASK_SWITCH:
9664 case EXIT_REASON_CPUID:
9666 case EXIT_REASON_HLT:
9667 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
9668 case EXIT_REASON_INVD:
9670 case EXIT_REASON_INVLPG:
9671 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9672 case EXIT_REASON_RDPMC:
9673 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
9674 case EXIT_REASON_RDRAND:
9675 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
9676 case EXIT_REASON_RDSEED:
9677 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
9678 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
9679 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
9680 case EXIT_REASON_VMREAD:
9681 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
9682 vmcs12->vmread_bitmap);
9683 case EXIT_REASON_VMWRITE:
9684 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
9685 vmcs12->vmwrite_bitmap);
9686 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
9687 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
9688 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMRESUME:
9689 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
9690 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
9692 * VMX instructions trap unconditionally. This allows L1 to
9693 * emulate them for its L2 guest, i.e., allows 3-level nesting!
9696 case EXIT_REASON_CR_ACCESS:
9697 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
9698 case EXIT_REASON_DR_ACCESS:
9699 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
9700 case EXIT_REASON_IO_INSTRUCTION:
9701 return nested_vmx_exit_handled_io(vcpu, vmcs12);
9702 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
9703 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
9704 case EXIT_REASON_MSR_READ:
9705 case EXIT_REASON_MSR_WRITE:
9706 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
9707 case EXIT_REASON_INVALID_STATE:
9709 case EXIT_REASON_MWAIT_INSTRUCTION:
9710 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
9711 case EXIT_REASON_MONITOR_TRAP_FLAG:
9712 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
9713 case EXIT_REASON_MONITOR_INSTRUCTION:
9714 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
9715 case EXIT_REASON_PAUSE_INSTRUCTION:
9716 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
9717 nested_cpu_has2(vmcs12,
9718 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
9719 case EXIT_REASON_MCE_DURING_VMENTRY:
9721 case EXIT_REASON_TPR_BELOW_THRESHOLD:
9722 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
9723 case EXIT_REASON_APIC_ACCESS:
9724 case EXIT_REASON_APIC_WRITE:
9725 case EXIT_REASON_EOI_INDUCED:
9727 * The controls for "virtualize APIC accesses," "APIC-
9728 * register virtualization," and "virtual-interrupt
9729 * delivery" only come from vmcs12.
9732 case EXIT_REASON_EPT_VIOLATION:
9734 * L0 always deals with the EPT violation. If nested EPT is
9735 * used, and the nested mmu code discovers that the address is
9736 * missing in the guest EPT table (EPT12), the EPT violation
9737 * will be injected with nested_ept_inject_page_fault()
9740 case EXIT_REASON_EPT_MISCONFIG:
9742 * L2 never uses directly L1's EPT, but rather L0's own EPT
9743 * table (shadow on EPT) or a merged EPT table that L0 built
9744 * (EPT on EPT). So any problems with the structure of the
9745 * table is L0's fault.
9748 case EXIT_REASON_INVPCID:
9750 nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
9751 nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9752 case EXIT_REASON_WBINVD:
9753 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
9754 case EXIT_REASON_XSETBV:
9756 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
9758 * This should never happen, since it is not possible to
9759 * set XSS to a non-zero value---neither in L1 nor in L2.
9760 * If if it were, XSS would have to be checked against
9761 * the XSS exit bitmap in vmcs12.
9763 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
9764 case EXIT_REASON_PREEMPTION_TIMER:
9766 case EXIT_REASON_PML_FULL:
9767 /* We emulate PML support to L1. */
9769 case EXIT_REASON_VMFUNC:
9770 /* VM functions are emulated through L2->L0 vmexits. */
9772 case EXIT_REASON_ENCLS:
9773 /* SGX is never exposed to L1 */
9780 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
9782 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9785 * At this point, the exit interruption info in exit_intr_info
9786 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
9787 * we need to query the in-kernel LAPIC.
9789 WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
9790 if ((exit_intr_info &
9791 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9792 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
9793 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9794 vmcs12->vm_exit_intr_error_code =
9795 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9798 nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
9799 vmcs_readl(EXIT_QUALIFICATION));
9803 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
9805 *info1 = vmcs_readl(EXIT_QUALIFICATION);
9806 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
9809 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
9812 __free_page(vmx->pml_pg);
9817 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
9819 struct vcpu_vmx *vmx = to_vmx(vcpu);
9823 pml_idx = vmcs_read16(GUEST_PML_INDEX);
9825 /* Do nothing if PML buffer is empty */
9826 if (pml_idx == (PML_ENTITY_NUM - 1))
9829 /* PML index always points to next available PML buffer entity */
9830 if (pml_idx >= PML_ENTITY_NUM)
9835 pml_buf = page_address(vmx->pml_pg);
9836 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
9839 gpa = pml_buf[pml_idx];
9840 WARN_ON(gpa & (PAGE_SIZE - 1));
9841 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
9844 /* reset PML index */
9845 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
9849 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
9850 * Called before reporting dirty_bitmap to userspace.
9852 static void kvm_flush_pml_buffers(struct kvm *kvm)
9855 struct kvm_vcpu *vcpu;
9857 * We only need to kick vcpu out of guest mode here, as PML buffer
9858 * is flushed at beginning of all VMEXITs, and it's obvious that only
9859 * vcpus running in guest are possible to have unflushed GPAs in PML
9862 kvm_for_each_vcpu(i, vcpu, kvm)
9863 kvm_vcpu_kick(vcpu);
9866 static void vmx_dump_sel(char *name, uint32_t sel)
9868 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
9869 name, vmcs_read16(sel),
9870 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
9871 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
9872 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
9875 static void vmx_dump_dtsel(char *name, uint32_t limit)
9877 pr_err("%s limit=0x%08x, base=0x%016lx\n",
9878 name, vmcs_read32(limit),
9879 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
9882 static void dump_vmcs(void)
9884 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
9885 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
9886 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
9887 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
9888 u32 secondary_exec_control = 0;
9889 unsigned long cr4 = vmcs_readl(GUEST_CR4);
9890 u64 efer = vmcs_read64(GUEST_IA32_EFER);
9893 if (cpu_has_secondary_exec_ctrls())
9894 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9896 pr_err("*** Guest State ***\n");
9897 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9898 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
9899 vmcs_readl(CR0_GUEST_HOST_MASK));
9900 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9901 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
9902 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
9903 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
9904 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
9906 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
9907 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
9908 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
9909 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
9911 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
9912 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
9913 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
9914 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
9915 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9916 vmcs_readl(GUEST_SYSENTER_ESP),
9917 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
9918 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
9919 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
9920 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
9921 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
9922 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
9923 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
9924 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
9925 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
9926 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
9927 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
9928 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
9929 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
9930 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
9931 efer, vmcs_read64(GUEST_IA32_PAT));
9932 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
9933 vmcs_read64(GUEST_IA32_DEBUGCTL),
9934 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
9935 if (cpu_has_load_perf_global_ctrl &&
9936 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
9937 pr_err("PerfGlobCtl = 0x%016llx\n",
9938 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
9939 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
9940 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
9941 pr_err("Interruptibility = %08x ActivityState = %08x\n",
9942 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
9943 vmcs_read32(GUEST_ACTIVITY_STATE));
9944 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
9945 pr_err("InterruptStatus = %04x\n",
9946 vmcs_read16(GUEST_INTR_STATUS));
9948 pr_err("*** Host State ***\n");
9949 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
9950 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
9951 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
9952 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
9953 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
9954 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
9955 vmcs_read16(HOST_TR_SELECTOR));
9956 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
9957 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
9958 vmcs_readl(HOST_TR_BASE));
9959 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
9960 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
9961 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
9962 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
9963 vmcs_readl(HOST_CR4));
9964 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9965 vmcs_readl(HOST_IA32_SYSENTER_ESP),
9966 vmcs_read32(HOST_IA32_SYSENTER_CS),
9967 vmcs_readl(HOST_IA32_SYSENTER_EIP));
9968 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
9969 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
9970 vmcs_read64(HOST_IA32_EFER),
9971 vmcs_read64(HOST_IA32_PAT));
9972 if (cpu_has_load_perf_global_ctrl &&
9973 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9974 pr_err("PerfGlobCtl = 0x%016llx\n",
9975 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
9977 pr_err("*** Control State ***\n");
9978 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
9979 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
9980 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
9981 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
9982 vmcs_read32(EXCEPTION_BITMAP),
9983 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
9984 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
9985 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
9986 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9987 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
9988 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
9989 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
9990 vmcs_read32(VM_EXIT_INTR_INFO),
9991 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9992 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
9993 pr_err(" reason=%08x qualification=%016lx\n",
9994 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
9995 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
9996 vmcs_read32(IDT_VECTORING_INFO_FIELD),
9997 vmcs_read32(IDT_VECTORING_ERROR_CODE));
9998 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
9999 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
10000 pr_err("TSC Multiplier = 0x%016llx\n",
10001 vmcs_read64(TSC_MULTIPLIER));
10002 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
10003 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
10004 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
10005 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
10006 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
10007 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
10008 n = vmcs_read32(CR3_TARGET_COUNT);
10009 for (i = 0; i + 1 < n; i += 4)
10010 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
10011 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
10012 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
10014 pr_err("CR3 target%u=%016lx\n",
10015 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
10016 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
10017 pr_err("PLE Gap=%08x Window=%08x\n",
10018 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
10019 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
10020 pr_err("Virtual processor ID = 0x%04x\n",
10021 vmcs_read16(VIRTUAL_PROCESSOR_ID));
10025 * The guest has exited. See if we can fix it or if we need userspace
10028 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
10030 struct vcpu_vmx *vmx = to_vmx(vcpu);
10031 u32 exit_reason = vmx->exit_reason;
10032 u32 vectoring_info = vmx->idt_vectoring_info;
10034 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
10037 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
10038 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
10039 * querying dirty_bitmap, we only need to kick all vcpus out of guest
10040 * mode as if vcpus is in root mode, the PML buffer must has been
10044 vmx_flush_pml_buffer(vcpu);
10046 /* If guest state is invalid, start emulating */
10047 if (vmx->emulation_required)
10048 return handle_invalid_guest_state(vcpu);
10050 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
10051 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
10053 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
10055 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
10056 vcpu->run->fail_entry.hardware_entry_failure_reason
10061 if (unlikely(vmx->fail)) {
10062 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
10063 vcpu->run->fail_entry.hardware_entry_failure_reason
10064 = vmcs_read32(VM_INSTRUCTION_ERROR);
10070 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
10071 * delivery event since it indicates guest is accessing MMIO.
10072 * The vm-exit can be triggered again after return to guest that
10073 * will cause infinite loop.
10075 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
10076 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
10077 exit_reason != EXIT_REASON_EPT_VIOLATION &&
10078 exit_reason != EXIT_REASON_PML_FULL &&
10079 exit_reason != EXIT_REASON_TASK_SWITCH)) {
10080 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
10081 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
10082 vcpu->run->internal.ndata = 3;
10083 vcpu->run->internal.data[0] = vectoring_info;
10084 vcpu->run->internal.data[1] = exit_reason;
10085 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
10086 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
10087 vcpu->run->internal.ndata++;
10088 vcpu->run->internal.data[3] =
10089 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
10094 if (unlikely(!enable_vnmi &&
10095 vmx->loaded_vmcs->soft_vnmi_blocked)) {
10096 if (vmx_interrupt_allowed(vcpu)) {
10097 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
10098 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
10099 vcpu->arch.nmi_pending) {
10101 * This CPU don't support us in finding the end of an
10102 * NMI-blocked window if the guest runs with IRQs
10103 * disabled. So we pull the trigger after 1 s of
10104 * futile waiting, but inform the user about this.
10106 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
10107 "state on VCPU %d after 1 s timeout\n",
10108 __func__, vcpu->vcpu_id);
10109 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
10113 if (exit_reason < kvm_vmx_max_exit_handlers
10114 && kvm_vmx_exit_handlers[exit_reason])
10115 return kvm_vmx_exit_handlers[exit_reason](vcpu);
10117 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
10119 kvm_queue_exception(vcpu, UD_VECTOR);
10125 * Software based L1D cache flush which is used when microcode providing
10126 * the cache control MSR is not loaded.
10128 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
10129 * flush it is required to read in 64 KiB because the replacement algorithm
10130 * is not exactly LRU. This could be sized at runtime via topology
10131 * information but as all relevant affected CPUs have 32KiB L1D cache size
10132 * there is no point in doing so.
10134 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
10136 int size = PAGE_SIZE << L1D_CACHE_ORDER;
10139 * This code is only executed when the the flush mode is 'cond' or
10142 if (static_branch_likely(&vmx_l1d_flush_cond)) {
10146 * Clear the per-vcpu flush bit, it gets set again
10147 * either from vcpu_run() or from one of the unsafe
10150 flush_l1d = vcpu->arch.l1tf_flush_l1d;
10151 vcpu->arch.l1tf_flush_l1d = false;
10154 * Clear the per-cpu flush bit, it gets set again from
10155 * the interrupt handlers.
10157 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
10158 kvm_clear_cpu_l1tf_flush_l1d();
10164 vcpu->stat.l1d_flush++;
10166 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
10167 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
10172 /* First ensure the pages are in the TLB */
10173 "xorl %%eax, %%eax\n"
10174 ".Lpopulate_tlb:\n\t"
10175 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
10176 "addl $4096, %%eax\n\t"
10177 "cmpl %%eax, %[size]\n\t"
10178 "jne .Lpopulate_tlb\n\t"
10179 "xorl %%eax, %%eax\n\t"
10181 /* Now fill the cache */
10182 "xorl %%eax, %%eax\n"
10184 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
10185 "addl $64, %%eax\n\t"
10186 "cmpl %%eax, %[size]\n\t"
10187 "jne .Lfill_cache\n\t"
10189 :: [flush_pages] "r" (vmx_l1d_flush_pages),
10191 : "eax", "ebx", "ecx", "edx");
10194 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
10196 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10198 if (is_guest_mode(vcpu) &&
10199 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10202 if (irr == -1 || tpr < irr) {
10203 vmcs_write32(TPR_THRESHOLD, 0);
10207 vmcs_write32(TPR_THRESHOLD, irr);
10210 static void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
10212 u32 sec_exec_control;
10214 if (!lapic_in_kernel(vcpu))
10217 /* Postpone execution until vmcs01 is the current VMCS. */
10218 if (is_guest_mode(vcpu)) {
10219 to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
10223 if (!cpu_need_tpr_shadow(vcpu))
10226 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
10227 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10228 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
10230 switch (kvm_get_apic_mode(vcpu)) {
10231 case LAPIC_MODE_INVALID:
10232 WARN_ONCE(true, "Invalid local APIC state");
10233 case LAPIC_MODE_DISABLED:
10235 case LAPIC_MODE_XAPIC:
10236 if (flexpriority_enabled) {
10237 sec_exec_control |=
10238 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
10239 vmx_flush_tlb(vcpu, true);
10242 case LAPIC_MODE_X2APIC:
10243 if (cpu_has_vmx_virtualize_x2apic_mode())
10244 sec_exec_control |=
10245 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
10248 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
10250 vmx_update_msr_bitmap(vcpu);
10253 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
10255 if (!is_guest_mode(vcpu)) {
10256 vmcs_write64(APIC_ACCESS_ADDR, hpa);
10257 vmx_flush_tlb(vcpu, true);
10261 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
10269 status = vmcs_read16(GUEST_INTR_STATUS);
10271 if (max_isr != old) {
10273 status |= max_isr << 8;
10274 vmcs_write16(GUEST_INTR_STATUS, status);
10278 static void vmx_set_rvi(int vector)
10286 status = vmcs_read16(GUEST_INTR_STATUS);
10287 old = (u8)status & 0xff;
10288 if ((u8)vector != old) {
10290 status |= (u8)vector;
10291 vmcs_write16(GUEST_INTR_STATUS, status);
10295 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
10298 * When running L2, updating RVI is only relevant when
10299 * vmcs12 virtual-interrupt-delivery enabled.
10300 * However, it can be enabled only when L1 also
10301 * intercepts external-interrupts and in that case
10302 * we should not update vmcs02 RVI but instead intercept
10303 * interrupt. Therefore, do nothing when running L2.
10305 if (!is_guest_mode(vcpu))
10306 vmx_set_rvi(max_irr);
10309 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
10311 struct vcpu_vmx *vmx = to_vmx(vcpu);
10313 bool max_irr_updated;
10315 WARN_ON(!vcpu->arch.apicv_active);
10316 if (pi_test_on(&vmx->pi_desc)) {
10317 pi_clear_on(&vmx->pi_desc);
10319 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
10320 * But on x86 this is just a compiler barrier anyway.
10322 smp_mb__after_atomic();
10324 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
10327 * If we are running L2 and L1 has a new pending interrupt
10328 * which can be injected, we should re-evaluate
10329 * what should be done with this new L1 interrupt.
10330 * If L1 intercepts external-interrupts, we should
10331 * exit from L2 to L1. Otherwise, interrupt should be
10332 * delivered directly to L2.
10334 if (is_guest_mode(vcpu) && max_irr_updated) {
10335 if (nested_exit_on_intr(vcpu))
10336 kvm_vcpu_exiting_guest_mode(vcpu);
10338 kvm_make_request(KVM_REQ_EVENT, vcpu);
10341 max_irr = kvm_lapic_find_highest_irr(vcpu);
10343 vmx_hwapic_irr_update(vcpu, max_irr);
10347 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
10349 if (!kvm_vcpu_apicv_active(vcpu))
10352 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
10353 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
10354 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
10355 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
10358 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
10360 struct vcpu_vmx *vmx = to_vmx(vcpu);
10362 pi_clear_on(&vmx->pi_desc);
10363 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
10366 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
10368 u32 exit_intr_info = 0;
10369 u16 basic_exit_reason = (u16)vmx->exit_reason;
10371 if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
10372 || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
10375 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
10376 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
10377 vmx->exit_intr_info = exit_intr_info;
10379 /* if exit due to PF check for async PF */
10380 if (is_page_fault(exit_intr_info))
10381 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
10383 /* Handle machine checks before interrupts are enabled */
10384 if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
10385 is_machine_check(exit_intr_info))
10386 kvm_machine_check();
10388 /* We need to handle NMIs before interrupts are enabled */
10389 if (is_nmi(exit_intr_info)) {
10390 kvm_before_interrupt(&vmx->vcpu);
10392 kvm_after_interrupt(&vmx->vcpu);
10396 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
10398 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
10400 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
10401 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
10402 unsigned int vector;
10403 unsigned long entry;
10405 struct vcpu_vmx *vmx = to_vmx(vcpu);
10406 #ifdef CONFIG_X86_64
10410 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
10411 desc = (gate_desc *)vmx->host_idt_base + vector;
10412 entry = gate_offset(desc);
10414 #ifdef CONFIG_X86_64
10415 "mov %%" _ASM_SP ", %[sp]\n\t"
10416 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
10421 __ASM_SIZE(push) " $%c[cs]\n\t"
10424 #ifdef CONFIG_X86_64
10427 ASM_CALL_CONSTRAINT
10429 THUNK_TARGET(entry),
10430 [ss]"i"(__KERNEL_DS),
10431 [cs]"i"(__KERNEL_CS)
10435 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
10437 static bool vmx_has_emulated_msr(int index)
10440 case MSR_IA32_SMBASE:
10442 * We cannot do SMM unless we can run the guest in big
10445 return enable_unrestricted_guest || emulate_invalid_guest_state;
10446 case MSR_AMD64_VIRT_SPEC_CTRL:
10447 /* This is AMD only. */
10454 static bool vmx_mpx_supported(void)
10456 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
10457 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
10460 static bool vmx_xsaves_supported(void)
10462 return vmcs_config.cpu_based_2nd_exec_ctrl &
10463 SECONDARY_EXEC_XSAVES;
10466 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
10468 u32 exit_intr_info;
10471 bool idtv_info_valid;
10473 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
10476 if (vmx->loaded_vmcs->nmi_known_unmasked)
10479 * Can't use vmx->exit_intr_info since we're not sure what
10480 * the exit reason is.
10482 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
10483 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
10484 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
10486 * SDM 3: 27.7.1.2 (September 2008)
10487 * Re-set bit "block by NMI" before VM entry if vmexit caused by
10488 * a guest IRET fault.
10489 * SDM 3: 23.2.2 (September 2008)
10490 * Bit 12 is undefined in any of the following cases:
10491 * If the VM exit sets the valid bit in the IDT-vectoring
10492 * information field.
10493 * If the VM exit is due to a double fault.
10495 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
10496 vector != DF_VECTOR && !idtv_info_valid)
10497 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
10498 GUEST_INTR_STATE_NMI);
10500 vmx->loaded_vmcs->nmi_known_unmasked =
10501 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
10502 & GUEST_INTR_STATE_NMI);
10503 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
10504 vmx->loaded_vmcs->vnmi_blocked_time +=
10505 ktime_to_ns(ktime_sub(ktime_get(),
10506 vmx->loaded_vmcs->entry_time));
10509 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
10510 u32 idt_vectoring_info,
10511 int instr_len_field,
10512 int error_code_field)
10516 bool idtv_info_valid;
10518 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
10520 vcpu->arch.nmi_injected = false;
10521 kvm_clear_exception_queue(vcpu);
10522 kvm_clear_interrupt_queue(vcpu);
10524 if (!idtv_info_valid)
10527 kvm_make_request(KVM_REQ_EVENT, vcpu);
10529 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
10530 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
10533 case INTR_TYPE_NMI_INTR:
10534 vcpu->arch.nmi_injected = true;
10536 * SDM 3: 27.7.1.2 (September 2008)
10537 * Clear bit "block by NMI" before VM entry if a NMI
10538 * delivery faulted.
10540 vmx_set_nmi_mask(vcpu, false);
10542 case INTR_TYPE_SOFT_EXCEPTION:
10543 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
10545 case INTR_TYPE_HARD_EXCEPTION:
10546 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
10547 u32 err = vmcs_read32(error_code_field);
10548 kvm_requeue_exception_e(vcpu, vector, err);
10550 kvm_requeue_exception(vcpu, vector);
10552 case INTR_TYPE_SOFT_INTR:
10553 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
10555 case INTR_TYPE_EXT_INTR:
10556 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
10563 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
10565 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
10566 VM_EXIT_INSTRUCTION_LEN,
10567 IDT_VECTORING_ERROR_CODE);
10570 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
10572 __vmx_complete_interrupts(vcpu,
10573 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
10574 VM_ENTRY_INSTRUCTION_LEN,
10575 VM_ENTRY_EXCEPTION_ERROR_CODE);
10577 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10580 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
10583 struct perf_guest_switch_msr *msrs;
10585 msrs = perf_guest_get_msrs(&nr_msrs);
10590 for (i = 0; i < nr_msrs; i++)
10591 if (msrs[i].host == msrs[i].guest)
10592 clear_atomic_switch_msr(vmx, msrs[i].msr);
10594 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
10595 msrs[i].host, false);
10598 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
10600 struct vcpu_vmx *vmx = to_vmx(vcpu);
10604 if (vmx->hv_deadline_tsc == -1)
10608 if (vmx->hv_deadline_tsc > tscl)
10609 /* sure to be 32 bit only because checked on set_hv_timer */
10610 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
10611 cpu_preemption_timer_multi);
10615 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
10618 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
10620 struct vcpu_vmx *vmx = to_vmx(vcpu);
10621 unsigned long cr3, cr4, evmcs_rsp;
10623 /* Record the guest's net vcpu time for enforced NMI injections. */
10624 if (unlikely(!enable_vnmi &&
10625 vmx->loaded_vmcs->soft_vnmi_blocked))
10626 vmx->loaded_vmcs->entry_time = ktime_get();
10628 /* Don't enter VMX if guest state is invalid, let the exit handler
10629 start emulation until we arrive back to a valid state */
10630 if (vmx->emulation_required)
10633 if (vmx->ple_window_dirty) {
10634 vmx->ple_window_dirty = false;
10635 vmcs_write32(PLE_WINDOW, vmx->ple_window);
10638 if (vmx->nested.sync_shadow_vmcs) {
10639 copy_vmcs12_to_shadow(vmx);
10640 vmx->nested.sync_shadow_vmcs = false;
10643 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
10644 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
10645 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
10646 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
10648 cr3 = __get_current_cr3_fast();
10649 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
10650 vmcs_writel(HOST_CR3, cr3);
10651 vmx->loaded_vmcs->host_state.cr3 = cr3;
10654 cr4 = cr4_read_shadow();
10655 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
10656 vmcs_writel(HOST_CR4, cr4);
10657 vmx->loaded_vmcs->host_state.cr4 = cr4;
10660 /* When single-stepping over STI and MOV SS, we must clear the
10661 * corresponding interruptibility bits in the guest state. Otherwise
10662 * vmentry fails as it then expects bit 14 (BS) in pending debug
10663 * exceptions being set, but that's not correct for the guest debugging
10665 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10666 vmx_set_interrupt_shadow(vcpu, 0);
10668 if (static_cpu_has(X86_FEATURE_PKU) &&
10669 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
10670 vcpu->arch.pkru != vmx->host_pkru)
10671 __write_pkru(vcpu->arch.pkru);
10673 atomic_switch_perf_msrs(vmx);
10675 vmx_arm_hv_timer(vcpu);
10678 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
10679 * it's non-zero. Since vmentry is serialising on affected CPUs, there
10680 * is no need to worry about the conditional branch over the wrmsr
10681 * being speculatively taken.
10683 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
10685 vmx->__launched = vmx->loaded_vmcs->launched;
10687 evmcs_rsp = static_branch_unlikely(&enable_evmcs) ?
10688 (unsigned long)¤t_evmcs->host_rsp : 0;
10690 if (static_branch_unlikely(&vmx_l1d_should_flush))
10691 vmx_l1d_flush(vcpu);
10694 /* Store host registers */
10695 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
10696 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
10697 "push %%" _ASM_CX " \n\t"
10698 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10700 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10701 /* Avoid VMWRITE when Enlightened VMCS is in use */
10702 "test %%" _ASM_SI ", %%" _ASM_SI " \n\t"
10704 "mov %%" _ASM_SP ", (%%" _ASM_SI ") \n\t"
10707 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
10709 /* Reload cr2 if changed */
10710 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
10711 "mov %%cr2, %%" _ASM_DX " \n\t"
10712 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
10714 "mov %%" _ASM_AX", %%cr2 \n\t"
10716 /* Check if vmlaunch of vmresume is needed */
10717 "cmpl $0, %c[launched](%0) \n\t"
10718 /* Load guest registers. Don't clobber flags. */
10719 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
10720 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
10721 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
10722 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
10723 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
10724 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
10725 #ifdef CONFIG_X86_64
10726 "mov %c[r8](%0), %%r8 \n\t"
10727 "mov %c[r9](%0), %%r9 \n\t"
10728 "mov %c[r10](%0), %%r10 \n\t"
10729 "mov %c[r11](%0), %%r11 \n\t"
10730 "mov %c[r12](%0), %%r12 \n\t"
10731 "mov %c[r13](%0), %%r13 \n\t"
10732 "mov %c[r14](%0), %%r14 \n\t"
10733 "mov %c[r15](%0), %%r15 \n\t"
10735 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
10737 /* Enter guest mode */
10739 __ex(ASM_VMX_VMLAUNCH) "\n\t"
10741 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
10743 /* Save guest registers, load host registers, keep flags */
10744 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
10746 "setbe %c[fail](%0)\n\t"
10747 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
10748 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
10749 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
10750 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
10751 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
10752 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
10753 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
10754 #ifdef CONFIG_X86_64
10755 "mov %%r8, %c[r8](%0) \n\t"
10756 "mov %%r9, %c[r9](%0) \n\t"
10757 "mov %%r10, %c[r10](%0) \n\t"
10758 "mov %%r11, %c[r11](%0) \n\t"
10759 "mov %%r12, %c[r12](%0) \n\t"
10760 "mov %%r13, %c[r13](%0) \n\t"
10761 "mov %%r14, %c[r14](%0) \n\t"
10762 "mov %%r15, %c[r15](%0) \n\t"
10763 "xor %%r8d, %%r8d \n\t"
10764 "xor %%r9d, %%r9d \n\t"
10765 "xor %%r10d, %%r10d \n\t"
10766 "xor %%r11d, %%r11d \n\t"
10767 "xor %%r12d, %%r12d \n\t"
10768 "xor %%r13d, %%r13d \n\t"
10769 "xor %%r14d, %%r14d \n\t"
10770 "xor %%r15d, %%r15d \n\t"
10772 "mov %%cr2, %%" _ASM_AX " \n\t"
10773 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
10775 "xor %%eax, %%eax \n\t"
10776 "xor %%ebx, %%ebx \n\t"
10777 "xor %%esi, %%esi \n\t"
10778 "xor %%edi, %%edi \n\t"
10779 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
10780 ".pushsection .rodata \n\t"
10781 ".global vmx_return \n\t"
10782 "vmx_return: " _ASM_PTR " 2b \n\t"
10784 : : "c"(vmx), "d"((unsigned long)HOST_RSP), "S"(evmcs_rsp),
10785 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
10786 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
10787 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
10788 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
10789 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
10790 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
10791 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
10792 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
10793 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
10794 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
10795 #ifdef CONFIG_X86_64
10796 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
10797 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
10798 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
10799 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
10800 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
10801 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
10802 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
10803 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
10805 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
10806 [wordsize]"i"(sizeof(ulong))
10808 #ifdef CONFIG_X86_64
10809 , "rax", "rbx", "rdi"
10810 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
10812 , "eax", "ebx", "edi"
10817 * We do not use IBRS in the kernel. If this vCPU has used the
10818 * SPEC_CTRL MSR it may have left it on; save the value and
10819 * turn it off. This is much more efficient than blindly adding
10820 * it to the atomic save/restore list. Especially as the former
10821 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
10823 * For non-nested case:
10824 * If the L01 MSR bitmap does not intercept the MSR, then we need to
10828 * If the L02 MSR bitmap does not intercept the MSR, then we need to
10831 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
10832 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
10834 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
10836 /* Eliminate branch target predictions from guest mode */
10839 /* All fields are clean at this point */
10840 if (static_branch_unlikely(&enable_evmcs))
10841 current_evmcs->hv_clean_fields |=
10842 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
10844 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
10845 if (vmx->host_debugctlmsr)
10846 update_debugctlmsr(vmx->host_debugctlmsr);
10848 #ifndef CONFIG_X86_64
10850 * The sysexit path does not restore ds/es, so we must set them to
10851 * a reasonable value ourselves.
10853 * We can't defer this to vmx_prepare_switch_to_host() since that
10854 * function may be executed in interrupt context, which saves and
10855 * restore segments around it, nullifying its effect.
10857 loadsegment(ds, __USER_DS);
10858 loadsegment(es, __USER_DS);
10861 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
10862 | (1 << VCPU_EXREG_RFLAGS)
10863 | (1 << VCPU_EXREG_PDPTR)
10864 | (1 << VCPU_EXREG_SEGMENTS)
10865 | (1 << VCPU_EXREG_CR3));
10866 vcpu->arch.regs_dirty = 0;
10869 * eager fpu is enabled if PKEY is supported and CR4 is switched
10870 * back on host, so it is safe to read guest PKRU from current
10873 if (static_cpu_has(X86_FEATURE_PKU) &&
10874 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
10875 vcpu->arch.pkru = __read_pkru();
10876 if (vcpu->arch.pkru != vmx->host_pkru)
10877 __write_pkru(vmx->host_pkru);
10880 vmx->nested.nested_run_pending = 0;
10881 vmx->idt_vectoring_info = 0;
10883 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
10884 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
10887 vmx->loaded_vmcs->launched = 1;
10888 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
10890 vmx_complete_atomic_exit(vmx);
10891 vmx_recover_nmi_blocking(vmx);
10892 vmx_complete_interrupts(vmx);
10894 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
10896 static struct kvm *vmx_vm_alloc(void)
10898 struct kvm_vmx *kvm_vmx = vzalloc(sizeof(struct kvm_vmx));
10899 return &kvm_vmx->kvm;
10902 static void vmx_vm_free(struct kvm *kvm)
10904 vfree(to_kvm_vmx(kvm));
10907 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
10909 struct vcpu_vmx *vmx = to_vmx(vcpu);
10912 if (vmx->loaded_vmcs == vmcs)
10916 vmx_vcpu_put(vcpu);
10917 vmx->loaded_vmcs = vmcs;
10918 vmx_vcpu_load(vcpu, cpu);
10923 * Ensure that the current vmcs of the logical processor is the
10924 * vmcs01 of the vcpu before calling free_nested().
10926 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
10928 struct vcpu_vmx *vmx = to_vmx(vcpu);
10931 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10936 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
10938 struct vcpu_vmx *vmx = to_vmx(vcpu);
10941 vmx_destroy_pml_buffer(vmx);
10942 free_vpid(vmx->vpid);
10943 leave_guest_mode(vcpu);
10944 vmx_free_vcpu_nested(vcpu);
10945 free_loaded_vmcs(vmx->loaded_vmcs);
10946 kfree(vmx->guest_msrs);
10947 kvm_vcpu_uninit(vcpu);
10948 kmem_cache_free(kvm_vcpu_cache, vmx);
10951 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
10954 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
10955 unsigned long *msr_bitmap;
10959 return ERR_PTR(-ENOMEM);
10961 vmx->vpid = allocate_vpid();
10963 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
10970 * If PML is turned on, failure on enabling PML just results in failure
10971 * of creating the vcpu, therefore we can simplify PML logic (by
10972 * avoiding dealing with cases, such as enabling PML partially on vcpus
10973 * for the guest, etc.
10976 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
10981 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
10982 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
10985 if (!vmx->guest_msrs)
10988 err = alloc_loaded_vmcs(&vmx->vmcs01);
10992 msr_bitmap = vmx->vmcs01.msr_bitmap;
10993 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
10994 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
10995 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
10996 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
10997 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
10998 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
10999 vmx->msr_bitmap_mode = 0;
11001 vmx->loaded_vmcs = &vmx->vmcs01;
11003 vmx_vcpu_load(&vmx->vcpu, cpu);
11004 vmx->vcpu.cpu = cpu;
11005 vmx_vcpu_setup(vmx);
11006 vmx_vcpu_put(&vmx->vcpu);
11008 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
11009 err = alloc_apic_access_page(kvm);
11014 if (enable_ept && !enable_unrestricted_guest) {
11015 err = init_rmode_identity_map(kvm);
11021 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
11022 kvm_vcpu_apicv_active(&vmx->vcpu));
11024 vmx->nested.posted_intr_nv = -1;
11025 vmx->nested.current_vmptr = -1ull;
11027 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
11030 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
11031 * or POSTED_INTR_WAKEUP_VECTOR.
11033 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
11034 vmx->pi_desc.sn = 1;
11039 free_loaded_vmcs(vmx->loaded_vmcs);
11041 kfree(vmx->guest_msrs);
11043 vmx_destroy_pml_buffer(vmx);
11045 kvm_vcpu_uninit(&vmx->vcpu);
11047 free_vpid(vmx->vpid);
11048 kmem_cache_free(kvm_vcpu_cache, vmx);
11049 return ERR_PTR(err);
11052 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
11053 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
11055 static int vmx_vm_init(struct kvm *kvm)
11057 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
11060 kvm->arch.pause_in_guest = true;
11062 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
11063 switch (l1tf_mitigation) {
11064 case L1TF_MITIGATION_OFF:
11065 case L1TF_MITIGATION_FLUSH_NOWARN:
11066 /* 'I explicitly don't care' is set */
11068 case L1TF_MITIGATION_FLUSH:
11069 case L1TF_MITIGATION_FLUSH_NOSMT:
11070 case L1TF_MITIGATION_FULL:
11072 * Warn upon starting the first VM in a potentially
11073 * insecure environment.
11075 if (cpu_smt_control == CPU_SMT_ENABLED)
11076 pr_warn_once(L1TF_MSG_SMT);
11077 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
11078 pr_warn_once(L1TF_MSG_L1D);
11080 case L1TF_MITIGATION_FULL_FORCE:
11081 /* Flush is enforced */
11088 static void __init vmx_check_processor_compat(void *rtn)
11090 struct vmcs_config vmcs_conf;
11093 if (setup_vmcs_config(&vmcs_conf) < 0)
11094 *(int *)rtn = -EIO;
11095 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, enable_apicv);
11096 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
11097 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
11098 smp_processor_id());
11099 *(int *)rtn = -EIO;
11103 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
11108 /* For VT-d and EPT combination
11109 * 1. MMIO: always map as UC
11110 * 2. EPT with VT-d:
11111 * a. VT-d without snooping control feature: can't guarantee the
11112 * result, try to trust guest.
11113 * b. VT-d with snooping control feature: snooping control feature of
11114 * VT-d engine can guarantee the cache correctness. Just set it
11115 * to WB to keep consistent with host. So the same as item 3.
11116 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
11117 * consistent with host MTRR
11120 cache = MTRR_TYPE_UNCACHABLE;
11124 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
11125 ipat = VMX_EPT_IPAT_BIT;
11126 cache = MTRR_TYPE_WRBACK;
11130 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
11131 ipat = VMX_EPT_IPAT_BIT;
11132 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
11133 cache = MTRR_TYPE_WRBACK;
11135 cache = MTRR_TYPE_UNCACHABLE;
11139 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
11142 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
11145 static int vmx_get_lpage_level(void)
11147 if (enable_ept && !cpu_has_vmx_ept_1g_page())
11148 return PT_DIRECTORY_LEVEL;
11150 /* For shadow and EPT supported 1GB page */
11151 return PT_PDPE_LEVEL;
11154 static void vmcs_set_secondary_exec_control(u32 new_ctl)
11157 * These bits in the secondary execution controls field
11158 * are dynamic, the others are mostly based on the hypervisor
11159 * architecture and the guest's CPUID. Do not touch the
11163 SECONDARY_EXEC_SHADOW_VMCS |
11164 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
11165 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
11166 SECONDARY_EXEC_DESC;
11168 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
11170 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
11171 (new_ctl & ~mask) | (cur_ctl & mask));
11175 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
11176 * (indicating "allowed-1") if they are supported in the guest's CPUID.
11178 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
11180 struct vcpu_vmx *vmx = to_vmx(vcpu);
11181 struct kvm_cpuid_entry2 *entry;
11183 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
11184 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
11186 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
11187 if (entry && (entry->_reg & (_cpuid_mask))) \
11188 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
11191 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
11192 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
11193 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
11194 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
11195 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
11196 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
11197 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
11198 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
11199 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
11200 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
11201 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
11202 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
11203 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
11204 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
11205 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
11207 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
11208 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
11209 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
11210 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
11211 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
11212 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
11214 #undef cr4_fixed1_update
11217 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
11219 struct vcpu_vmx *vmx = to_vmx(vcpu);
11221 if (cpu_has_secondary_exec_ctrls()) {
11222 vmx_compute_secondary_exec_control(vmx);
11223 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
11226 if (nested_vmx_allowed(vcpu))
11227 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11228 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
11230 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11231 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
11233 if (nested_vmx_allowed(vcpu))
11234 nested_vmx_cr_fixed1_bits_update(vcpu);
11237 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
11239 if (func == 1 && nested)
11240 entry->ecx |= bit(X86_FEATURE_VMX);
11243 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
11244 struct x86_exception *fault)
11246 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11247 struct vcpu_vmx *vmx = to_vmx(vcpu);
11249 unsigned long exit_qualification = vcpu->arch.exit_qualification;
11251 if (vmx->nested.pml_full) {
11252 exit_reason = EXIT_REASON_PML_FULL;
11253 vmx->nested.pml_full = false;
11254 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
11255 } else if (fault->error_code & PFERR_RSVD_MASK)
11256 exit_reason = EXIT_REASON_EPT_MISCONFIG;
11258 exit_reason = EXIT_REASON_EPT_VIOLATION;
11260 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
11261 vmcs12->guest_physical_address = fault->address;
11264 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
11266 return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
11269 /* Callbacks for nested_ept_init_mmu_context: */
11271 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
11273 /* return the page table to be shadowed - in our case, EPT12 */
11274 return get_vmcs12(vcpu)->ept_pointer;
11277 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
11279 WARN_ON(mmu_is_nested(vcpu));
11280 if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
11283 kvm_init_shadow_ept_mmu(vcpu,
11284 to_vmx(vcpu)->nested.msrs.ept_caps &
11285 VMX_EPT_EXECUTE_ONLY_BIT,
11286 nested_ept_ad_enabled(vcpu),
11287 nested_ept_get_cr3(vcpu));
11288 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
11289 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
11290 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
11292 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
11296 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
11298 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
11301 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
11304 bool inequality, bit;
11306 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
11308 (error_code & vmcs12->page_fault_error_code_mask) !=
11309 vmcs12->page_fault_error_code_match;
11310 return inequality ^ bit;
11313 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
11314 struct x86_exception *fault)
11316 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11318 WARN_ON(!is_guest_mode(vcpu));
11320 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
11321 !to_vmx(vcpu)->nested.nested_run_pending) {
11322 vmcs12->vm_exit_intr_error_code = fault->error_code;
11323 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
11324 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
11325 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
11328 kvm_inject_page_fault(vcpu, fault);
11332 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
11333 struct vmcs12 *vmcs12);
11335 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu)
11337 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11338 struct vcpu_vmx *vmx = to_vmx(vcpu);
11342 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11344 * Translate L1 physical address to host physical
11345 * address for vmcs02. Keep the page pinned, so this
11346 * physical address remains valid. We keep a reference
11347 * to it so we can release it later.
11349 if (vmx->nested.apic_access_page) { /* shouldn't happen */
11350 kvm_release_page_dirty(vmx->nested.apic_access_page);
11351 vmx->nested.apic_access_page = NULL;
11353 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
11355 * If translation failed, no matter: This feature asks
11356 * to exit when accessing the given address, and if it
11357 * can never be accessed, this feature won't do
11360 if (!is_error_page(page)) {
11361 vmx->nested.apic_access_page = page;
11362 hpa = page_to_phys(vmx->nested.apic_access_page);
11363 vmcs_write64(APIC_ACCESS_ADDR, hpa);
11365 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
11366 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
11370 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
11371 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
11372 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
11373 vmx->nested.virtual_apic_page = NULL;
11375 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
11378 * If translation failed, VM entry will fail because
11379 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
11380 * Failing the vm entry is _not_ what the processor
11381 * does but it's basically the only possibility we
11382 * have. We could still enter the guest if CR8 load
11383 * exits are enabled, CR8 store exits are enabled, and
11384 * virtualize APIC access is disabled; in this case
11385 * the processor would never use the TPR shadow and we
11386 * could simply clear the bit from the execution
11387 * control. But such a configuration is useless, so
11388 * let's keep the code simple.
11390 if (!is_error_page(page)) {
11391 vmx->nested.virtual_apic_page = page;
11392 hpa = page_to_phys(vmx->nested.virtual_apic_page);
11393 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
11397 if (nested_cpu_has_posted_intr(vmcs12)) {
11398 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
11399 kunmap(vmx->nested.pi_desc_page);
11400 kvm_release_page_dirty(vmx->nested.pi_desc_page);
11401 vmx->nested.pi_desc_page = NULL;
11403 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
11404 if (is_error_page(page))
11406 vmx->nested.pi_desc_page = page;
11407 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
11408 vmx->nested.pi_desc =
11409 (struct pi_desc *)((void *)vmx->nested.pi_desc +
11410 (unsigned long)(vmcs12->posted_intr_desc_addr &
11412 vmcs_write64(POSTED_INTR_DESC_ADDR,
11413 page_to_phys(vmx->nested.pi_desc_page) +
11414 (unsigned long)(vmcs12->posted_intr_desc_addr &
11417 if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
11418 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
11419 CPU_BASED_USE_MSR_BITMAPS);
11421 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
11422 CPU_BASED_USE_MSR_BITMAPS);
11425 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
11427 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
11428 struct vcpu_vmx *vmx = to_vmx(vcpu);
11430 if (vcpu->arch.virtual_tsc_khz == 0)
11433 /* Make sure short timeouts reliably trigger an immediate vmexit.
11434 * hrtimer_start does not guarantee this. */
11435 if (preemption_timeout <= 1) {
11436 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
11440 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
11441 preemption_timeout *= 1000000;
11442 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
11443 hrtimer_start(&vmx->nested.preemption_timer,
11444 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
11447 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
11448 struct vmcs12 *vmcs12)
11450 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
11453 if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
11454 !page_address_valid(vcpu, vmcs12->io_bitmap_b))
11460 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
11461 struct vmcs12 *vmcs12)
11463 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
11466 if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
11472 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
11473 struct vmcs12 *vmcs12)
11475 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
11478 if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
11485 * Merge L0's and L1's MSR bitmap, return false to indicate that
11486 * we do not use the hardware.
11488 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
11489 struct vmcs12 *vmcs12)
11493 unsigned long *msr_bitmap_l1;
11494 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
11496 * pred_cmd & spec_ctrl are trying to verify two things:
11498 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
11499 * ensures that we do not accidentally generate an L02 MSR bitmap
11500 * from the L12 MSR bitmap that is too permissive.
11501 * 2. That L1 or L2s have actually used the MSR. This avoids
11502 * unnecessarily merging of the bitmap if the MSR is unused. This
11503 * works properly because we only update the L01 MSR bitmap lazily.
11504 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only
11505 * updated to reflect this when L1 (or its L2s) actually write to
11508 bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
11509 bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
11511 /* Nothing to do if the MSR bitmap is not in use. */
11512 if (!cpu_has_vmx_msr_bitmap() ||
11513 !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
11516 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
11517 !pred_cmd && !spec_ctrl)
11520 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
11521 if (is_error_page(page))
11524 msr_bitmap_l1 = (unsigned long *)kmap(page);
11525 if (nested_cpu_has_apic_reg_virt(vmcs12)) {
11527 * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it
11528 * just lets the processor take the value from the virtual-APIC page;
11529 * take those 256 bits directly from the L1 bitmap.
11531 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
11532 unsigned word = msr / BITS_PER_LONG;
11533 msr_bitmap_l0[word] = msr_bitmap_l1[word];
11534 msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
11537 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
11538 unsigned word = msr / BITS_PER_LONG;
11539 msr_bitmap_l0[word] = ~0;
11540 msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
11544 nested_vmx_disable_intercept_for_msr(
11545 msr_bitmap_l1, msr_bitmap_l0,
11546 X2APIC_MSR(APIC_TASKPRI),
11549 if (nested_cpu_has_vid(vmcs12)) {
11550 nested_vmx_disable_intercept_for_msr(
11551 msr_bitmap_l1, msr_bitmap_l0,
11552 X2APIC_MSR(APIC_EOI),
11554 nested_vmx_disable_intercept_for_msr(
11555 msr_bitmap_l1, msr_bitmap_l0,
11556 X2APIC_MSR(APIC_SELF_IPI),
11561 nested_vmx_disable_intercept_for_msr(
11562 msr_bitmap_l1, msr_bitmap_l0,
11563 MSR_IA32_SPEC_CTRL,
11564 MSR_TYPE_R | MSR_TYPE_W);
11567 nested_vmx_disable_intercept_for_msr(
11568 msr_bitmap_l1, msr_bitmap_l0,
11573 kvm_release_page_clean(page);
11578 static void nested_cache_shadow_vmcs12(struct kvm_vcpu *vcpu,
11579 struct vmcs12 *vmcs12)
11581 struct vmcs12 *shadow;
11584 if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
11585 vmcs12->vmcs_link_pointer == -1ull)
11588 shadow = get_shadow_vmcs12(vcpu);
11589 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->vmcs_link_pointer);
11591 memcpy(shadow, kmap(page), VMCS12_SIZE);
11594 kvm_release_page_clean(page);
11597 static void nested_flush_cached_shadow_vmcs12(struct kvm_vcpu *vcpu,
11598 struct vmcs12 *vmcs12)
11600 struct vcpu_vmx *vmx = to_vmx(vcpu);
11602 if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
11603 vmcs12->vmcs_link_pointer == -1ull)
11606 kvm_write_guest(vmx->vcpu.kvm, vmcs12->vmcs_link_pointer,
11607 get_shadow_vmcs12(vcpu), VMCS12_SIZE);
11610 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu,
11611 struct vmcs12 *vmcs12)
11613 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
11614 !page_address_valid(vcpu, vmcs12->apic_access_addr))
11620 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
11621 struct vmcs12 *vmcs12)
11623 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
11624 !nested_cpu_has_apic_reg_virt(vmcs12) &&
11625 !nested_cpu_has_vid(vmcs12) &&
11626 !nested_cpu_has_posted_intr(vmcs12))
11630 * If virtualize x2apic mode is enabled,
11631 * virtualize apic access must be disabled.
11633 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
11634 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
11638 * If virtual interrupt delivery is enabled,
11639 * we must exit on external interrupts.
11641 if (nested_cpu_has_vid(vmcs12) &&
11642 !nested_exit_on_intr(vcpu))
11646 * bits 15:8 should be zero in posted_intr_nv,
11647 * the descriptor address has been already checked
11648 * in nested_get_vmcs12_pages.
11650 if (nested_cpu_has_posted_intr(vmcs12) &&
11651 (!nested_cpu_has_vid(vmcs12) ||
11652 !nested_exit_intr_ack_set(vcpu) ||
11653 vmcs12->posted_intr_nv & 0xff00))
11656 /* tpr shadow is needed by all apicv features. */
11657 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
11663 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
11664 unsigned long count_field,
11665 unsigned long addr_field)
11667 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11671 if (vmcs12_read_any(vmcs12, count_field, &count) ||
11672 vmcs12_read_any(vmcs12, addr_field, &addr)) {
11678 maxphyaddr = cpuid_maxphyaddr(vcpu);
11679 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
11680 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
11681 pr_debug_ratelimited(
11682 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
11683 addr_field, maxphyaddr, count, addr);
11689 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
11690 struct vmcs12 *vmcs12)
11692 if (vmcs12->vm_exit_msr_load_count == 0 &&
11693 vmcs12->vm_exit_msr_store_count == 0 &&
11694 vmcs12->vm_entry_msr_load_count == 0)
11695 return 0; /* Fast path */
11696 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
11697 VM_EXIT_MSR_LOAD_ADDR) ||
11698 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
11699 VM_EXIT_MSR_STORE_ADDR) ||
11700 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
11701 VM_ENTRY_MSR_LOAD_ADDR))
11706 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
11707 struct vmcs12 *vmcs12)
11709 u64 address = vmcs12->pml_address;
11710 int maxphyaddr = cpuid_maxphyaddr(vcpu);
11712 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
11713 if (!nested_cpu_has_ept(vmcs12) ||
11714 !IS_ALIGNED(address, 4096) ||
11715 address >> maxphyaddr)
11722 static int nested_vmx_check_shadow_vmcs_controls(struct kvm_vcpu *vcpu,
11723 struct vmcs12 *vmcs12)
11725 if (!nested_cpu_has_shadow_vmcs(vmcs12))
11728 if (!page_address_valid(vcpu, vmcs12->vmread_bitmap) ||
11729 !page_address_valid(vcpu, vmcs12->vmwrite_bitmap))
11735 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
11736 struct vmx_msr_entry *e)
11738 /* x2APIC MSR accesses are not allowed */
11739 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
11741 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
11742 e->index == MSR_IA32_UCODE_REV)
11744 if (e->reserved != 0)
11749 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
11750 struct vmx_msr_entry *e)
11752 if (e->index == MSR_FS_BASE ||
11753 e->index == MSR_GS_BASE ||
11754 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
11755 nested_vmx_msr_check_common(vcpu, e))
11760 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
11761 struct vmx_msr_entry *e)
11763 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
11764 nested_vmx_msr_check_common(vcpu, e))
11770 * Load guest's/host's msr at nested entry/exit.
11771 * return 0 for success, entry index for failure.
11773 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11776 struct vmx_msr_entry e;
11777 struct msr_data msr;
11779 msr.host_initiated = false;
11780 for (i = 0; i < count; i++) {
11781 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
11783 pr_debug_ratelimited(
11784 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11785 __func__, i, gpa + i * sizeof(e));
11788 if (nested_vmx_load_msr_check(vcpu, &e)) {
11789 pr_debug_ratelimited(
11790 "%s check failed (%u, 0x%x, 0x%x)\n",
11791 __func__, i, e.index, e.reserved);
11794 msr.index = e.index;
11795 msr.data = e.value;
11796 if (kvm_set_msr(vcpu, &msr)) {
11797 pr_debug_ratelimited(
11798 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11799 __func__, i, e.index, e.value);
11808 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11811 struct vmx_msr_entry e;
11813 for (i = 0; i < count; i++) {
11814 struct msr_data msr_info;
11815 if (kvm_vcpu_read_guest(vcpu,
11816 gpa + i * sizeof(e),
11817 &e, 2 * sizeof(u32))) {
11818 pr_debug_ratelimited(
11819 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11820 __func__, i, gpa + i * sizeof(e));
11823 if (nested_vmx_store_msr_check(vcpu, &e)) {
11824 pr_debug_ratelimited(
11825 "%s check failed (%u, 0x%x, 0x%x)\n",
11826 __func__, i, e.index, e.reserved);
11829 msr_info.host_initiated = false;
11830 msr_info.index = e.index;
11831 if (kvm_get_msr(vcpu, &msr_info)) {
11832 pr_debug_ratelimited(
11833 "%s cannot read MSR (%u, 0x%x)\n",
11834 __func__, i, e.index);
11837 if (kvm_vcpu_write_guest(vcpu,
11838 gpa + i * sizeof(e) +
11839 offsetof(struct vmx_msr_entry, value),
11840 &msr_info.data, sizeof(msr_info.data))) {
11841 pr_debug_ratelimited(
11842 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11843 __func__, i, e.index, msr_info.data);
11850 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
11852 unsigned long invalid_mask;
11854 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
11855 return (val & invalid_mask) == 0;
11859 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
11860 * emulating VM entry into a guest with EPT enabled.
11861 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
11862 * is assigned to entry_failure_code on failure.
11864 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
11865 u32 *entry_failure_code)
11867 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
11868 if (!nested_cr3_valid(vcpu, cr3)) {
11869 *entry_failure_code = ENTRY_FAIL_DEFAULT;
11874 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
11875 * must not be dereferenced.
11877 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
11879 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
11880 *entry_failure_code = ENTRY_FAIL_PDPTE;
11887 kvm_mmu_new_cr3(vcpu, cr3, false);
11889 vcpu->arch.cr3 = cr3;
11890 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
11892 kvm_init_mmu(vcpu, false);
11897 static void prepare_vmcs02_full(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11899 struct vcpu_vmx *vmx = to_vmx(vcpu);
11901 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
11902 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
11903 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
11904 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
11905 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
11906 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
11907 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
11908 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
11909 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
11910 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
11911 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
11912 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
11913 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
11914 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
11915 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
11916 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
11917 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
11918 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
11919 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
11920 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
11921 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
11922 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
11923 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
11924 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
11925 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
11926 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
11927 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
11928 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
11929 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
11930 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
11931 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
11933 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
11934 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
11935 vmcs12->guest_pending_dbg_exceptions);
11936 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
11937 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
11939 if (nested_cpu_has_xsaves(vmcs12))
11940 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
11941 vmcs_write64(VMCS_LINK_POINTER, -1ull);
11943 if (cpu_has_vmx_posted_intr())
11944 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
11947 * Whether page-faults are trapped is determined by a combination of
11948 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
11949 * If enable_ept, L0 doesn't care about page faults and we should
11950 * set all of these to L1's desires. However, if !enable_ept, L0 does
11951 * care about (at least some) page faults, and because it is not easy
11952 * (if at all possible?) to merge L0 and L1's desires, we simply ask
11953 * to exit on each and every L2 page fault. This is done by setting
11954 * MASK=MATCH=0 and (see below) EB.PF=1.
11955 * Note that below we don't need special code to set EB.PF beyond the
11956 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
11957 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
11958 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
11960 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
11961 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
11962 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
11963 enable_ept ? vmcs12->page_fault_error_code_match : 0);
11965 /* All VMFUNCs are currently emulated through L0 vmexits. */
11966 if (cpu_has_vmx_vmfunc())
11967 vmcs_write64(VM_FUNCTION_CONTROL, 0);
11969 if (cpu_has_vmx_apicv()) {
11970 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
11971 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
11972 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
11973 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
11977 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
11978 * Some constant fields are set here by vmx_set_constant_host_state().
11979 * Other fields are different per CPU, and will be set later when
11980 * vmx_vcpu_load() is called, and when vmx_prepare_switch_to_guest()
11983 vmx_set_constant_host_state(vmx);
11986 * Set the MSR load/store lists to match L0's settings.
11988 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
11989 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
11990 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
11991 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
11992 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
11994 set_cr4_guest_host_mask(vmx);
11996 if (vmx_mpx_supported())
11997 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
12000 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
12001 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
12003 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
12007 * L1 may access the L2's PDPTR, so save them to construct vmcs12
12010 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
12011 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
12012 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
12013 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
12016 if (cpu_has_vmx_msr_bitmap())
12017 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
12021 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
12022 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
12023 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
12024 * guest in a way that will both be appropriate to L1's requests, and our
12025 * needs. In addition to modifying the active vmcs (which is vmcs02), this
12026 * function also has additional necessary side-effects, like setting various
12027 * vcpu->arch fields.
12028 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
12029 * is assigned to entry_failure_code on failure.
12031 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
12032 u32 *entry_failure_code)
12034 struct vcpu_vmx *vmx = to_vmx(vcpu);
12035 u32 exec_control, vmcs12_exec_ctrl;
12037 if (vmx->nested.dirty_vmcs12) {
12038 prepare_vmcs02_full(vcpu, vmcs12);
12039 vmx->nested.dirty_vmcs12 = false;
12043 * First, the fields that are shadowed. This must be kept in sync
12044 * with vmx_shadow_fields.h.
12047 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
12048 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
12049 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
12050 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
12051 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
12053 if (vmx->nested.nested_run_pending &&
12054 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
12055 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
12056 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
12058 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
12059 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
12061 if (vmx->nested.nested_run_pending) {
12062 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
12063 vmcs12->vm_entry_intr_info_field);
12064 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
12065 vmcs12->vm_entry_exception_error_code);
12066 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
12067 vmcs12->vm_entry_instruction_len);
12068 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
12069 vmcs12->guest_interruptibility_info);
12070 vmx->loaded_vmcs->nmi_known_unmasked =
12071 !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
12073 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
12075 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
12077 exec_control = vmcs12->pin_based_vm_exec_control;
12079 /* Preemption timer setting is only taken from vmcs01. */
12080 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
12081 exec_control |= vmcs_config.pin_based_exec_ctrl;
12082 if (vmx->hv_deadline_tsc == -1)
12083 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
12085 /* Posted interrupts setting is only taken from vmcs12. */
12086 if (nested_cpu_has_posted_intr(vmcs12)) {
12087 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
12088 vmx->nested.pi_pending = false;
12090 exec_control &= ~PIN_BASED_POSTED_INTR;
12093 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
12095 vmx->nested.preemption_timer_expired = false;
12096 if (nested_cpu_has_preemption_timer(vmcs12))
12097 vmx_start_preemption_timer(vcpu);
12099 if (cpu_has_secondary_exec_ctrls()) {
12100 exec_control = vmx->secondary_exec_control;
12102 /* Take the following fields only from vmcs12 */
12103 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
12104 SECONDARY_EXEC_ENABLE_INVPCID |
12105 SECONDARY_EXEC_RDTSCP |
12106 SECONDARY_EXEC_XSAVES |
12107 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
12108 SECONDARY_EXEC_APIC_REGISTER_VIRT |
12109 SECONDARY_EXEC_ENABLE_VMFUNC);
12110 if (nested_cpu_has(vmcs12,
12111 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
12112 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
12113 ~SECONDARY_EXEC_ENABLE_PML;
12114 exec_control |= vmcs12_exec_ctrl;
12117 /* VMCS shadowing for L2 is emulated for now */
12118 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
12120 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
12121 vmcs_write16(GUEST_INTR_STATUS,
12122 vmcs12->guest_intr_status);
12125 * Write an illegal value to APIC_ACCESS_ADDR. Later,
12126 * nested_get_vmcs12_pages will either fix it up or
12127 * remove the VM execution control.
12129 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
12130 vmcs_write64(APIC_ACCESS_ADDR, -1ull);
12132 if (exec_control & SECONDARY_EXEC_ENCLS_EXITING)
12133 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
12135 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
12139 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
12140 * entry, but only if the current (host) sp changed from the value
12141 * we wrote last (vmx->host_rsp). This cache is no longer relevant
12142 * if we switch vmcs, and rather than hold a separate cache per vmcs,
12143 * here we just force the write to happen on entry.
12147 exec_control = vmx_exec_control(vmx); /* L0's desires */
12148 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
12149 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
12150 exec_control &= ~CPU_BASED_TPR_SHADOW;
12151 exec_control |= vmcs12->cpu_based_vm_exec_control;
12154 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
12155 * nested_get_vmcs12_pages can't fix it up, the illegal value
12156 * will result in a VM entry failure.
12158 if (exec_control & CPU_BASED_TPR_SHADOW) {
12159 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
12160 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
12162 #ifdef CONFIG_X86_64
12163 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
12164 CPU_BASED_CR8_STORE_EXITING;
12169 * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
12170 * for I/O port accesses.
12172 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
12173 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
12175 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
12177 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
12178 * bitwise-or of what L1 wants to trap for L2, and what we want to
12179 * trap. Note that CR0.TS also needs updating - we do this later.
12181 update_exception_bitmap(vcpu);
12182 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
12183 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
12185 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
12186 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
12187 * bits are further modified by vmx_set_efer() below.
12189 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
12191 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
12192 * emulated by vmx_set_efer(), below.
12194 vm_entry_controls_init(vmx,
12195 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
12196 ~VM_ENTRY_IA32E_MODE) |
12197 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
12199 if (vmx->nested.nested_run_pending &&
12200 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
12201 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
12202 vcpu->arch.pat = vmcs12->guest_ia32_pat;
12203 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
12204 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
12207 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
12209 if (kvm_has_tsc_control)
12210 decache_tsc_multiplier(vmx);
12214 * There is no direct mapping between vpid02 and vpid12, the
12215 * vpid02 is per-vCPU for L0 and reused while the value of
12216 * vpid12 is changed w/ one invvpid during nested vmentry.
12217 * The vpid12 is allocated by L1 for L2, so it will not
12218 * influence global bitmap(for vpid01 and vpid02 allocation)
12219 * even if spawn a lot of nested vCPUs.
12221 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
12222 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
12223 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
12224 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
12227 vmx_flush_tlb(vcpu, true);
12233 * Conceptually we want to copy the PML address and index from
12234 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
12235 * since we always flush the log on each vmexit, this happens
12236 * to be equivalent to simply resetting the fields in vmcs02.
12238 ASSERT(vmx->pml_pg);
12239 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
12240 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
12243 if (nested_cpu_has_ept(vmcs12)) {
12244 if (nested_ept_init_mmu_context(vcpu)) {
12245 *entry_failure_code = ENTRY_FAIL_DEFAULT;
12248 } else if (nested_cpu_has2(vmcs12,
12249 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
12250 vmx_flush_tlb(vcpu, true);
12254 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
12255 * bits which we consider mandatory enabled.
12256 * The CR0_READ_SHADOW is what L2 should have expected to read given
12257 * the specifications by L1; It's not enough to take
12258 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
12259 * have more bits than L1 expected.
12261 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
12262 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
12264 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
12265 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
12267 if (vmx->nested.nested_run_pending &&
12268 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
12269 vcpu->arch.efer = vmcs12->guest_ia32_efer;
12270 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
12271 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
12273 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
12274 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
12275 vmx_set_efer(vcpu, vcpu->arch.efer);
12278 * Guest state is invalid and unrestricted guest is disabled,
12279 * which means L1 attempted VMEntry to L2 with invalid state.
12280 * Fail the VMEntry.
12282 if (vmx->emulation_required) {
12283 *entry_failure_code = ENTRY_FAIL_DEFAULT;
12287 /* Shadow page tables on either EPT or shadow page tables. */
12288 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
12289 entry_failure_code))
12293 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
12295 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
12296 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
12300 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12)
12302 if (!nested_cpu_has_nmi_exiting(vmcs12) &&
12303 nested_cpu_has_virtual_nmis(vmcs12))
12306 if (!nested_cpu_has_virtual_nmis(vmcs12) &&
12307 nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING))
12313 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12315 struct vcpu_vmx *vmx = to_vmx(vcpu);
12317 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
12318 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
12319 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12321 if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
12322 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12324 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
12325 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12327 if (nested_vmx_check_apic_access_controls(vcpu, vmcs12))
12328 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12330 if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
12331 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12333 if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
12334 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12336 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
12337 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12339 if (nested_vmx_check_pml_controls(vcpu, vmcs12))
12340 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12342 if (nested_vmx_check_shadow_vmcs_controls(vcpu, vmcs12))
12343 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12345 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
12346 vmx->nested.msrs.procbased_ctls_low,
12347 vmx->nested.msrs.procbased_ctls_high) ||
12348 (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
12349 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
12350 vmx->nested.msrs.secondary_ctls_low,
12351 vmx->nested.msrs.secondary_ctls_high)) ||
12352 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
12353 vmx->nested.msrs.pinbased_ctls_low,
12354 vmx->nested.msrs.pinbased_ctls_high) ||
12355 !vmx_control_verify(vmcs12->vm_exit_controls,
12356 vmx->nested.msrs.exit_ctls_low,
12357 vmx->nested.msrs.exit_ctls_high) ||
12358 !vmx_control_verify(vmcs12->vm_entry_controls,
12359 vmx->nested.msrs.entry_ctls_low,
12360 vmx->nested.msrs.entry_ctls_high))
12361 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12363 if (nested_vmx_check_nmi_controls(vmcs12))
12364 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12366 if (nested_cpu_has_vmfunc(vmcs12)) {
12367 if (vmcs12->vm_function_control &
12368 ~vmx->nested.msrs.vmfunc_controls)
12369 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12371 if (nested_cpu_has_eptp_switching(vmcs12)) {
12372 if (!nested_cpu_has_ept(vmcs12) ||
12373 !page_address_valid(vcpu, vmcs12->eptp_list_address))
12374 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12378 if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
12379 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12381 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
12382 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
12383 !nested_cr3_valid(vcpu, vmcs12->host_cr3))
12384 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
12387 * From the Intel SDM, volume 3:
12388 * Fields relevant to VM-entry event injection must be set properly.
12389 * These fields are the VM-entry interruption-information field, the
12390 * VM-entry exception error code, and the VM-entry instruction length.
12392 if (vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) {
12393 u32 intr_info = vmcs12->vm_entry_intr_info_field;
12394 u8 vector = intr_info & INTR_INFO_VECTOR_MASK;
12395 u32 intr_type = intr_info & INTR_INFO_INTR_TYPE_MASK;
12396 bool has_error_code = intr_info & INTR_INFO_DELIVER_CODE_MASK;
12397 bool should_have_error_code;
12398 bool urg = nested_cpu_has2(vmcs12,
12399 SECONDARY_EXEC_UNRESTRICTED_GUEST);
12400 bool prot_mode = !urg || vmcs12->guest_cr0 & X86_CR0_PE;
12402 /* VM-entry interruption-info field: interruption type */
12403 if (intr_type == INTR_TYPE_RESERVED ||
12404 (intr_type == INTR_TYPE_OTHER_EVENT &&
12405 !nested_cpu_supports_monitor_trap_flag(vcpu)))
12406 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12408 /* VM-entry interruption-info field: vector */
12409 if ((intr_type == INTR_TYPE_NMI_INTR && vector != NMI_VECTOR) ||
12410 (intr_type == INTR_TYPE_HARD_EXCEPTION && vector > 31) ||
12411 (intr_type == INTR_TYPE_OTHER_EVENT && vector != 0))
12412 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12414 /* VM-entry interruption-info field: deliver error code */
12415 should_have_error_code =
12416 intr_type == INTR_TYPE_HARD_EXCEPTION && prot_mode &&
12417 x86_exception_has_error_code(vector);
12418 if (has_error_code != should_have_error_code)
12419 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12421 /* VM-entry exception error code */
12422 if (has_error_code &&
12423 vmcs12->vm_entry_exception_error_code & GENMASK(31, 15))
12424 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12426 /* VM-entry interruption-info field: reserved bits */
12427 if (intr_info & INTR_INFO_RESVD_BITS_MASK)
12428 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12430 /* VM-entry instruction length */
12431 switch (intr_type) {
12432 case INTR_TYPE_SOFT_EXCEPTION:
12433 case INTR_TYPE_SOFT_INTR:
12434 case INTR_TYPE_PRIV_SW_EXCEPTION:
12435 if ((vmcs12->vm_entry_instruction_len > 15) ||
12436 (vmcs12->vm_entry_instruction_len == 0 &&
12437 !nested_cpu_has_zero_length_injection(vcpu)))
12438 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12445 static int nested_vmx_check_vmcs_link_ptr(struct kvm_vcpu *vcpu,
12446 struct vmcs12 *vmcs12)
12450 struct vmcs12 *shadow;
12452 if (vmcs12->vmcs_link_pointer == -1ull)
12455 if (!page_address_valid(vcpu, vmcs12->vmcs_link_pointer))
12458 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->vmcs_link_pointer);
12459 if (is_error_page(page))
12463 shadow = kmap(page);
12464 if (shadow->hdr.revision_id != VMCS12_REVISION ||
12465 shadow->hdr.shadow_vmcs != nested_cpu_has_shadow_vmcs(vmcs12))
12468 kvm_release_page_clean(page);
12472 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
12477 *exit_qual = ENTRY_FAIL_DEFAULT;
12479 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
12480 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
12483 if (nested_vmx_check_vmcs_link_ptr(vcpu, vmcs12)) {
12484 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
12489 * If the load IA32_EFER VM-entry control is 1, the following checks
12490 * are performed on the field for the IA32_EFER MSR:
12491 * - Bits reserved in the IA32_EFER MSR must be 0.
12492 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
12493 * the IA-32e mode guest VM-exit control. It must also be identical
12494 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
12497 if (to_vmx(vcpu)->nested.nested_run_pending &&
12498 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
12499 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
12500 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
12501 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
12502 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
12503 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
12508 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
12509 * IA32_EFER MSR must be 0 in the field for that register. In addition,
12510 * the values of the LMA and LME bits in the field must each be that of
12511 * the host address-space size VM-exit control.
12513 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
12514 ia32e = (vmcs12->vm_exit_controls &
12515 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
12516 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
12517 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
12518 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
12522 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
12523 (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) ||
12524 (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))
12531 * If exit_qual is NULL, this is being called from state restore (either RSM
12532 * or KVM_SET_NESTED_STATE). Otherwise it's called from vmlaunch/vmresume.
12534 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, u32 *exit_qual)
12536 struct vcpu_vmx *vmx = to_vmx(vcpu);
12537 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12538 bool from_vmentry = !!exit_qual;
12539 u32 dummy_exit_qual;
12542 enter_guest_mode(vcpu);
12544 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
12545 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
12547 vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
12548 vmx_segment_cache_clear(vmx);
12550 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
12551 vcpu->arch.tsc_offset += vmcs12->tsc_offset;
12553 r = EXIT_REASON_INVALID_STATE;
12554 if (prepare_vmcs02(vcpu, vmcs12, from_vmentry ? exit_qual : &dummy_exit_qual))
12557 if (from_vmentry) {
12558 nested_get_vmcs12_pages(vcpu);
12560 r = EXIT_REASON_MSR_LOAD_FAIL;
12561 *exit_qual = nested_vmx_load_msr(vcpu,
12562 vmcs12->vm_entry_msr_load_addr,
12563 vmcs12->vm_entry_msr_load_count);
12568 * The MMU is not initialized to point at the right entities yet and
12569 * "get pages" would need to read data from the guest (i.e. we will
12570 * need to perform gpa to hpa translation). Request a call
12571 * to nested_get_vmcs12_pages before the next VM-entry. The MSRs
12572 * have already been set at vmentry time and should not be reset.
12574 kvm_make_request(KVM_REQ_GET_VMCS12_PAGES, vcpu);
12578 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
12579 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
12580 * returned as far as L1 is concerned. It will only return (and set
12581 * the success flag) when L2 exits (see nested_vmx_vmexit()).
12586 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
12587 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
12588 leave_guest_mode(vcpu);
12589 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
12594 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
12595 * for running an L2 nested guest.
12597 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
12599 struct vmcs12 *vmcs12;
12600 struct vcpu_vmx *vmx = to_vmx(vcpu);
12601 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
12605 if (!nested_vmx_check_permission(vcpu))
12608 if (!nested_vmx_check_vmcs12(vcpu))
12611 vmcs12 = get_vmcs12(vcpu);
12614 * Can't VMLAUNCH or VMRESUME a shadow VMCS. Despite the fact
12615 * that there *is* a valid VMCS pointer, RFLAGS.CF is set
12616 * rather than RFLAGS.ZF, and no error number is stored to the
12617 * VM-instruction error field.
12619 if (vmcs12->hdr.shadow_vmcs) {
12620 nested_vmx_failInvalid(vcpu);
12624 if (enable_shadow_vmcs)
12625 copy_shadow_to_vmcs12(vmx);
12628 * The nested entry process starts with enforcing various prerequisites
12629 * on vmcs12 as required by the Intel SDM, and act appropriately when
12630 * they fail: As the SDM explains, some conditions should cause the
12631 * instruction to fail, while others will cause the instruction to seem
12632 * to succeed, but return an EXIT_REASON_INVALID_STATE.
12633 * To speed up the normal (success) code path, we should avoid checking
12634 * for misconfigurations which will anyway be caught by the processor
12635 * when using the merged vmcs02.
12637 if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
12638 nested_vmx_failValid(vcpu,
12639 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
12643 if (vmcs12->launch_state == launch) {
12644 nested_vmx_failValid(vcpu,
12645 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
12646 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
12650 ret = check_vmentry_prereqs(vcpu, vmcs12);
12652 nested_vmx_failValid(vcpu, ret);
12657 * After this point, the trap flag no longer triggers a singlestep trap
12658 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
12659 * This is not 100% correct; for performance reasons, we delegate most
12660 * of the checks on host state to the processor. If those fail,
12661 * the singlestep trap is missed.
12663 skip_emulated_instruction(vcpu);
12665 ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
12667 nested_vmx_entry_failure(vcpu, vmcs12,
12668 EXIT_REASON_INVALID_STATE, exit_qual);
12673 * We're finally done with prerequisite checking, and can start with
12674 * the nested entry.
12677 vmx->nested.nested_run_pending = 1;
12678 ret = enter_vmx_non_root_mode(vcpu, &exit_qual);
12680 nested_vmx_entry_failure(vcpu, vmcs12, ret, exit_qual);
12681 vmx->nested.nested_run_pending = 0;
12685 /* Hide L1D cache contents from the nested guest. */
12686 vmx->vcpu.arch.l1tf_flush_l1d = true;
12689 * Must happen outside of enter_vmx_non_root_mode() as it will
12690 * also be used as part of restoring nVMX state for
12691 * snapshot restore (migration).
12693 * In this flow, it is assumed that vmcs12 cache was
12694 * trasferred as part of captured nVMX state and should
12695 * therefore not be read from guest memory (which may not
12696 * exist on destination host yet).
12698 nested_cache_shadow_vmcs12(vcpu, vmcs12);
12701 * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken
12702 * by event injection, halt vcpu.
12704 if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) &&
12705 !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK)) {
12706 vmx->nested.nested_run_pending = 0;
12707 return kvm_vcpu_halt(vcpu);
12712 return kvm_skip_emulated_instruction(vcpu);
12716 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
12717 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
12718 * This function returns the new value we should put in vmcs12.guest_cr0.
12719 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
12720 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
12721 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
12722 * didn't trap the bit, because if L1 did, so would L0).
12723 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
12724 * been modified by L2, and L1 knows it. So just leave the old value of
12725 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
12726 * isn't relevant, because if L0 traps this bit it can set it to anything.
12727 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
12728 * changed these bits, and therefore they need to be updated, but L0
12729 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
12730 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
12732 static inline unsigned long
12733 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12736 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
12737 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
12738 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
12739 vcpu->arch.cr0_guest_owned_bits));
12742 static inline unsigned long
12743 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12746 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
12747 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
12748 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
12749 vcpu->arch.cr4_guest_owned_bits));
12752 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
12753 struct vmcs12 *vmcs12)
12758 if (vcpu->arch.exception.injected) {
12759 nr = vcpu->arch.exception.nr;
12760 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
12762 if (kvm_exception_is_soft(nr)) {
12763 vmcs12->vm_exit_instruction_len =
12764 vcpu->arch.event_exit_inst_len;
12765 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
12767 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
12769 if (vcpu->arch.exception.has_error_code) {
12770 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
12771 vmcs12->idt_vectoring_error_code =
12772 vcpu->arch.exception.error_code;
12775 vmcs12->idt_vectoring_info_field = idt_vectoring;
12776 } else if (vcpu->arch.nmi_injected) {
12777 vmcs12->idt_vectoring_info_field =
12778 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
12779 } else if (vcpu->arch.interrupt.injected) {
12780 nr = vcpu->arch.interrupt.nr;
12781 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
12783 if (vcpu->arch.interrupt.soft) {
12784 idt_vectoring |= INTR_TYPE_SOFT_INTR;
12785 vmcs12->vm_entry_instruction_len =
12786 vcpu->arch.event_exit_inst_len;
12788 idt_vectoring |= INTR_TYPE_EXT_INTR;
12790 vmcs12->idt_vectoring_info_field = idt_vectoring;
12794 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
12796 struct vcpu_vmx *vmx = to_vmx(vcpu);
12797 unsigned long exit_qual;
12798 bool block_nested_events =
12799 vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
12801 if (vcpu->arch.exception.pending &&
12802 nested_vmx_check_exception(vcpu, &exit_qual)) {
12803 if (block_nested_events)
12805 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
12809 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
12810 vmx->nested.preemption_timer_expired) {
12811 if (block_nested_events)
12813 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
12817 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
12818 if (block_nested_events)
12820 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
12821 NMI_VECTOR | INTR_TYPE_NMI_INTR |
12822 INTR_INFO_VALID_MASK, 0);
12824 * The NMI-triggered VM exit counts as injection:
12825 * clear this one and block further NMIs.
12827 vcpu->arch.nmi_pending = 0;
12828 vmx_set_nmi_mask(vcpu, true);
12832 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
12833 nested_exit_on_intr(vcpu)) {
12834 if (block_nested_events)
12836 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
12840 vmx_complete_nested_posted_interrupt(vcpu);
12844 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
12846 ktime_t remaining =
12847 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
12850 if (ktime_to_ns(remaining) <= 0)
12853 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
12854 do_div(value, 1000000);
12855 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
12859 * Update the guest state fields of vmcs12 to reflect changes that
12860 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
12861 * VM-entry controls is also updated, since this is really a guest
12864 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12866 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
12867 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
12869 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
12870 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
12871 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
12873 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
12874 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
12875 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
12876 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
12877 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
12878 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
12879 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
12880 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
12881 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
12882 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
12883 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
12884 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
12885 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
12886 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
12887 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
12888 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
12889 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
12890 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
12891 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
12892 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
12893 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
12894 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
12895 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
12896 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
12897 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
12898 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
12899 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
12900 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
12901 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
12902 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
12903 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
12904 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
12905 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
12906 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
12907 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
12908 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
12910 vmcs12->guest_interruptibility_info =
12911 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
12912 vmcs12->guest_pending_dbg_exceptions =
12913 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
12914 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
12915 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
12917 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
12919 if (nested_cpu_has_preemption_timer(vmcs12)) {
12920 if (vmcs12->vm_exit_controls &
12921 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
12922 vmcs12->vmx_preemption_timer_value =
12923 vmx_get_preemption_timer_value(vcpu);
12924 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
12928 * In some cases (usually, nested EPT), L2 is allowed to change its
12929 * own CR3 without exiting. If it has changed it, we must keep it.
12930 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
12931 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
12933 * Additionally, restore L2's PDPTR to vmcs12.
12936 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
12937 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
12938 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
12939 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
12940 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
12943 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
12945 if (nested_cpu_has_vid(vmcs12))
12946 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
12948 vmcs12->vm_entry_controls =
12949 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
12950 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
12952 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
12953 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
12954 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
12957 /* TODO: These cannot have changed unless we have MSR bitmaps and
12958 * the relevant bit asks not to trap the change */
12959 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
12960 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
12961 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
12962 vmcs12->guest_ia32_efer = vcpu->arch.efer;
12963 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
12964 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
12965 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
12966 if (kvm_mpx_supported())
12967 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
12971 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
12972 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
12973 * and this function updates it to reflect the changes to the guest state while
12974 * L2 was running (and perhaps made some exits which were handled directly by L0
12975 * without going back to L1), and to reflect the exit reason.
12976 * Note that we do not have to copy here all VMCS fields, just those that
12977 * could have changed by the L2 guest or the exit - i.e., the guest-state and
12978 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
12979 * which already writes to vmcs12 directly.
12981 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
12982 u32 exit_reason, u32 exit_intr_info,
12983 unsigned long exit_qualification)
12985 /* update guest state fields: */
12986 sync_vmcs12(vcpu, vmcs12);
12988 /* update exit information fields: */
12990 vmcs12->vm_exit_reason = exit_reason;
12991 vmcs12->exit_qualification = exit_qualification;
12992 vmcs12->vm_exit_intr_info = exit_intr_info;
12994 vmcs12->idt_vectoring_info_field = 0;
12995 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
12996 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
12998 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
12999 vmcs12->launch_state = 1;
13001 /* vm_entry_intr_info_field is cleared on exit. Emulate this
13002 * instead of reading the real value. */
13003 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
13006 * Transfer the event that L0 or L1 may wanted to inject into
13007 * L2 to IDT_VECTORING_INFO_FIELD.
13009 vmcs12_save_pending_event(vcpu, vmcs12);
13013 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
13014 * preserved above and would only end up incorrectly in L1.
13016 vcpu->arch.nmi_injected = false;
13017 kvm_clear_exception_queue(vcpu);
13018 kvm_clear_interrupt_queue(vcpu);
13021 static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu,
13022 struct vmcs12 *vmcs12)
13024 u32 entry_failure_code;
13026 nested_ept_uninit_mmu_context(vcpu);
13029 * Only PDPTE load can fail as the value of cr3 was checked on entry and
13030 * couldn't have changed.
13032 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
13033 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
13036 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
13040 * A part of what we need to when the nested L2 guest exits and we want to
13041 * run its L1 parent, is to reset L1's guest state to the host state specified
13043 * This function is to be called not only on normal nested exit, but also on
13044 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
13045 * Failures During or After Loading Guest State").
13046 * This function should be called when the active VMCS is L1's (vmcs01).
13048 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
13049 struct vmcs12 *vmcs12)
13051 struct kvm_segment seg;
13053 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
13054 vcpu->arch.efer = vmcs12->host_ia32_efer;
13055 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
13056 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
13058 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
13059 vmx_set_efer(vcpu, vcpu->arch.efer);
13061 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
13062 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
13063 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
13065 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
13066 * actually changed, because vmx_set_cr0 refers to efer set above.
13068 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
13069 * (KVM doesn't change it);
13071 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
13072 vmx_set_cr0(vcpu, vmcs12->host_cr0);
13074 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
13075 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
13076 vmx_set_cr4(vcpu, vmcs12->host_cr4);
13078 load_vmcs12_mmu_host_state(vcpu, vmcs12);
13081 * If vmcs01 don't use VPID, CPU flushes TLB on every
13082 * VMEntry/VMExit. Thus, no need to flush TLB.
13084 * If vmcs12 uses VPID, TLB entries populated by L2 are
13085 * tagged with vmx->nested.vpid02 while L1 entries are tagged
13086 * with vmx->vpid. Thus, no need to flush TLB.
13088 * Therefore, flush TLB only in case vmcs01 uses VPID and
13089 * vmcs12 don't use VPID as in this case L1 & L2 TLB entries
13090 * are both tagged with vmx->vpid.
13093 !(nested_cpu_has_vpid(vmcs12) && to_vmx(vcpu)->nested.vpid02)) {
13094 vmx_flush_tlb(vcpu, true);
13097 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
13098 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
13099 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
13100 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
13101 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
13102 vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
13103 vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
13105 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
13106 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
13107 vmcs_write64(GUEST_BNDCFGS, 0);
13109 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
13110 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
13111 vcpu->arch.pat = vmcs12->host_ia32_pat;
13113 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
13114 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
13115 vmcs12->host_ia32_perf_global_ctrl);
13117 /* Set L1 segment info according to Intel SDM
13118 27.5.2 Loading Host Segment and Descriptor-Table Registers */
13119 seg = (struct kvm_segment) {
13121 .limit = 0xFFFFFFFF,
13122 .selector = vmcs12->host_cs_selector,
13128 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
13132 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
13133 seg = (struct kvm_segment) {
13135 .limit = 0xFFFFFFFF,
13142 seg.selector = vmcs12->host_ds_selector;
13143 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
13144 seg.selector = vmcs12->host_es_selector;
13145 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
13146 seg.selector = vmcs12->host_ss_selector;
13147 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
13148 seg.selector = vmcs12->host_fs_selector;
13149 seg.base = vmcs12->host_fs_base;
13150 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
13151 seg.selector = vmcs12->host_gs_selector;
13152 seg.base = vmcs12->host_gs_base;
13153 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
13154 seg = (struct kvm_segment) {
13155 .base = vmcs12->host_tr_base,
13157 .selector = vmcs12->host_tr_selector,
13161 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
13163 kvm_set_dr(vcpu, 7, 0x400);
13164 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
13166 if (cpu_has_vmx_msr_bitmap())
13167 vmx_update_msr_bitmap(vcpu);
13169 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
13170 vmcs12->vm_exit_msr_load_count))
13171 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
13175 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
13176 * and modify vmcs12 to make it see what it would expect to see there if
13177 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
13179 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
13180 u32 exit_intr_info,
13181 unsigned long exit_qualification)
13183 struct vcpu_vmx *vmx = to_vmx(vcpu);
13184 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
13186 /* trying to cancel vmlaunch/vmresume is a bug */
13187 WARN_ON_ONCE(vmx->nested.nested_run_pending);
13190 * The only expected VM-instruction error is "VM entry with
13191 * invalid control field(s)." Anything else indicates a
13194 WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
13195 VMXERR_ENTRY_INVALID_CONTROL_FIELD));
13197 leave_guest_mode(vcpu);
13199 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
13200 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
13202 if (likely(!vmx->fail)) {
13203 if (exit_reason == -1)
13204 sync_vmcs12(vcpu, vmcs12);
13206 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
13207 exit_qualification);
13210 * Must happen outside of sync_vmcs12() as it will
13211 * also be used to capture vmcs12 cache as part of
13212 * capturing nVMX state for snapshot (migration).
13214 * Otherwise, this flush will dirty guest memory at a
13215 * point it is already assumed by user-space to be
13218 nested_flush_cached_shadow_vmcs12(vcpu, vmcs12);
13220 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
13221 vmcs12->vm_exit_msr_store_count))
13222 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
13225 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
13226 vm_entry_controls_reset_shadow(vmx);
13227 vm_exit_controls_reset_shadow(vmx);
13228 vmx_segment_cache_clear(vmx);
13230 /* Update any VMCS fields that might have changed while L2 ran */
13231 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
13232 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
13233 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
13234 if (vmx->hv_deadline_tsc == -1)
13235 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
13236 PIN_BASED_VMX_PREEMPTION_TIMER);
13238 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
13239 PIN_BASED_VMX_PREEMPTION_TIMER);
13240 if (kvm_has_tsc_control)
13241 decache_tsc_multiplier(vmx);
13243 if (vmx->nested.change_vmcs01_virtual_apic_mode) {
13244 vmx->nested.change_vmcs01_virtual_apic_mode = false;
13245 vmx_set_virtual_apic_mode(vcpu);
13246 } else if (!nested_cpu_has_ept(vmcs12) &&
13247 nested_cpu_has2(vmcs12,
13248 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
13249 vmx_flush_tlb(vcpu, true);
13252 /* This is needed for same reason as it was needed in prepare_vmcs02 */
13255 /* Unpin physical memory we referred to in vmcs02 */
13256 if (vmx->nested.apic_access_page) {
13257 kvm_release_page_dirty(vmx->nested.apic_access_page);
13258 vmx->nested.apic_access_page = NULL;
13260 if (vmx->nested.virtual_apic_page) {
13261 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
13262 vmx->nested.virtual_apic_page = NULL;
13264 if (vmx->nested.pi_desc_page) {
13265 kunmap(vmx->nested.pi_desc_page);
13266 kvm_release_page_dirty(vmx->nested.pi_desc_page);
13267 vmx->nested.pi_desc_page = NULL;
13268 vmx->nested.pi_desc = NULL;
13272 * We are now running in L2, mmu_notifier will force to reload the
13273 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
13275 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
13277 if (enable_shadow_vmcs && exit_reason != -1)
13278 vmx->nested.sync_shadow_vmcs = true;
13280 /* in case we halted in L2 */
13281 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
13283 if (likely(!vmx->fail)) {
13285 * TODO: SDM says that with acknowledge interrupt on
13286 * exit, bit 31 of the VM-exit interrupt information
13287 * (valid interrupt) is always set to 1 on
13288 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
13289 * need kvm_cpu_has_interrupt(). See the commit
13290 * message for details.
13292 if (nested_exit_intr_ack_set(vcpu) &&
13293 exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
13294 kvm_cpu_has_interrupt(vcpu)) {
13295 int irq = kvm_cpu_get_interrupt(vcpu);
13297 vmcs12->vm_exit_intr_info = irq |
13298 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
13301 if (exit_reason != -1)
13302 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
13303 vmcs12->exit_qualification,
13304 vmcs12->idt_vectoring_info_field,
13305 vmcs12->vm_exit_intr_info,
13306 vmcs12->vm_exit_intr_error_code,
13309 load_vmcs12_host_state(vcpu, vmcs12);
13315 * After an early L2 VM-entry failure, we're now back
13316 * in L1 which thinks it just finished a VMLAUNCH or
13317 * VMRESUME instruction, so we need to set the failure
13318 * flag and the VM-instruction error field of the VMCS
13321 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
13323 load_vmcs12_mmu_host_state(vcpu, vmcs12);
13326 * The emulated instruction was already skipped in
13327 * nested_vmx_run, but the updated RIP was never
13328 * written back to the vmcs01.
13330 skip_emulated_instruction(vcpu);
13335 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
13337 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
13339 if (is_guest_mode(vcpu)) {
13340 to_vmx(vcpu)->nested.nested_run_pending = 0;
13341 nested_vmx_vmexit(vcpu, -1, 0, 0);
13343 free_nested(to_vmx(vcpu));
13347 * L1's failure to enter L2 is a subset of a normal exit, as explained in
13348 * 23.7 "VM-entry failures during or after loading guest state" (this also
13349 * lists the acceptable exit-reason and exit-qualification parameters).
13350 * It should only be called before L2 actually succeeded to run, and when
13351 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
13353 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
13354 struct vmcs12 *vmcs12,
13355 u32 reason, unsigned long qualification)
13357 load_vmcs12_host_state(vcpu, vmcs12);
13358 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
13359 vmcs12->exit_qualification = qualification;
13360 nested_vmx_succeed(vcpu);
13361 if (enable_shadow_vmcs)
13362 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
13365 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
13366 struct x86_instruction_info *info,
13367 enum x86_intercept_stage stage)
13369 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
13370 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
13373 * RDPID causes #UD if disabled through secondary execution controls.
13374 * Because it is marked as EmulateOnUD, we need to intercept it here.
13376 if (info->intercept == x86_intercept_rdtscp &&
13377 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
13378 ctxt->exception.vector = UD_VECTOR;
13379 ctxt->exception.error_code_valid = false;
13380 return X86EMUL_PROPAGATE_FAULT;
13383 /* TODO: check more intercepts... */
13384 return X86EMUL_CONTINUE;
13387 #ifdef CONFIG_X86_64
13388 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
13389 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
13390 u64 divisor, u64 *result)
13392 u64 low = a << shift, high = a >> (64 - shift);
13394 /* To avoid the overflow on divq */
13395 if (high >= divisor)
13398 /* Low hold the result, high hold rem which is discarded */
13399 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
13400 "rm" (divisor), "0" (low), "1" (high));
13406 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
13408 struct vcpu_vmx *vmx;
13409 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
13411 if (kvm_mwait_in_guest(vcpu->kvm))
13412 return -EOPNOTSUPP;
13414 vmx = to_vmx(vcpu);
13416 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
13417 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
13418 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, lapic_timer_advance_ns);
13420 if (delta_tsc > lapic_timer_advance_cycles)
13421 delta_tsc -= lapic_timer_advance_cycles;
13425 /* Convert to host delta tsc if tsc scaling is enabled */
13426 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
13427 u64_shl_div_u64(delta_tsc,
13428 kvm_tsc_scaling_ratio_frac_bits,
13429 vcpu->arch.tsc_scaling_ratio,
13434 * If the delta tsc can't fit in the 32 bit after the multi shift,
13435 * we can't use the preemption timer.
13436 * It's possible that it fits on later vmentries, but checking
13437 * on every vmentry is costly so we just use an hrtimer.
13439 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
13442 vmx->hv_deadline_tsc = tscl + delta_tsc;
13443 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
13444 PIN_BASED_VMX_PREEMPTION_TIMER);
13446 return delta_tsc == 0;
13449 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
13451 struct vcpu_vmx *vmx = to_vmx(vcpu);
13452 vmx->hv_deadline_tsc = -1;
13453 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
13454 PIN_BASED_VMX_PREEMPTION_TIMER);
13458 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
13460 if (!kvm_pause_in_guest(vcpu->kvm))
13461 shrink_ple_window(vcpu);
13464 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
13465 struct kvm_memory_slot *slot)
13467 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
13468 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
13471 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
13472 struct kvm_memory_slot *slot)
13474 kvm_mmu_slot_set_dirty(kvm, slot);
13477 static void vmx_flush_log_dirty(struct kvm *kvm)
13479 kvm_flush_pml_buffers(kvm);
13482 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
13484 struct vmcs12 *vmcs12;
13485 struct vcpu_vmx *vmx = to_vmx(vcpu);
13487 struct page *page = NULL;
13490 if (is_guest_mode(vcpu)) {
13491 WARN_ON_ONCE(vmx->nested.pml_full);
13494 * Check if PML is enabled for the nested guest.
13495 * Whether eptp bit 6 is set is already checked
13496 * as part of A/D emulation.
13498 vmcs12 = get_vmcs12(vcpu);
13499 if (!nested_cpu_has_pml(vmcs12))
13502 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
13503 vmx->nested.pml_full = true;
13507 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
13509 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
13510 if (is_error_page(page))
13513 pml_address = kmap(page);
13514 pml_address[vmcs12->guest_pml_index--] = gpa;
13516 kvm_release_page_clean(page);
13522 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
13523 struct kvm_memory_slot *memslot,
13524 gfn_t offset, unsigned long mask)
13526 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
13529 static void __pi_post_block(struct kvm_vcpu *vcpu)
13531 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
13532 struct pi_desc old, new;
13536 old.control = new.control = pi_desc->control;
13537 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
13538 "Wakeup handler not enabled while the VCPU is blocked\n");
13540 dest = cpu_physical_id(vcpu->cpu);
13542 if (x2apic_enabled())
13545 new.ndst = (dest << 8) & 0xFF00;
13547 /* set 'NV' to 'notification vector' */
13548 new.nv = POSTED_INTR_VECTOR;
13549 } while (cmpxchg64(&pi_desc->control, old.control,
13550 new.control) != old.control);
13552 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
13553 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13554 list_del(&vcpu->blocked_vcpu_list);
13555 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13556 vcpu->pre_pcpu = -1;
13561 * This routine does the following things for vCPU which is going
13562 * to be blocked if VT-d PI is enabled.
13563 * - Store the vCPU to the wakeup list, so when interrupts happen
13564 * we can find the right vCPU to wake up.
13565 * - Change the Posted-interrupt descriptor as below:
13566 * 'NDST' <-- vcpu->pre_pcpu
13567 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
13568 * - If 'ON' is set during this process, which means at least one
13569 * interrupt is posted for this vCPU, we cannot block it, in
13570 * this case, return 1, otherwise, return 0.
13573 static int pi_pre_block(struct kvm_vcpu *vcpu)
13576 struct pi_desc old, new;
13577 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
13579 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
13580 !irq_remapping_cap(IRQ_POSTING_CAP) ||
13581 !kvm_vcpu_apicv_active(vcpu))
13584 WARN_ON(irqs_disabled());
13585 local_irq_disable();
13586 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
13587 vcpu->pre_pcpu = vcpu->cpu;
13588 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13589 list_add_tail(&vcpu->blocked_vcpu_list,
13590 &per_cpu(blocked_vcpu_on_cpu,
13592 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13596 old.control = new.control = pi_desc->control;
13598 WARN((pi_desc->sn == 1),
13599 "Warning: SN field of posted-interrupts "
13600 "is set before blocking\n");
13603 * Since vCPU can be preempted during this process,
13604 * vcpu->cpu could be different with pre_pcpu, we
13605 * need to set pre_pcpu as the destination of wakeup
13606 * notification event, then we can find the right vCPU
13607 * to wakeup in wakeup handler if interrupts happen
13608 * when the vCPU is in blocked state.
13610 dest = cpu_physical_id(vcpu->pre_pcpu);
13612 if (x2apic_enabled())
13615 new.ndst = (dest << 8) & 0xFF00;
13617 /* set 'NV' to 'wakeup vector' */
13618 new.nv = POSTED_INTR_WAKEUP_VECTOR;
13619 } while (cmpxchg64(&pi_desc->control, old.control,
13620 new.control) != old.control);
13622 /* We should not block the vCPU if an interrupt is posted for it. */
13623 if (pi_test_on(pi_desc) == 1)
13624 __pi_post_block(vcpu);
13626 local_irq_enable();
13627 return (vcpu->pre_pcpu == -1);
13630 static int vmx_pre_block(struct kvm_vcpu *vcpu)
13632 if (pi_pre_block(vcpu))
13635 if (kvm_lapic_hv_timer_in_use(vcpu))
13636 kvm_lapic_switch_to_sw_timer(vcpu);
13641 static void pi_post_block(struct kvm_vcpu *vcpu)
13643 if (vcpu->pre_pcpu == -1)
13646 WARN_ON(irqs_disabled());
13647 local_irq_disable();
13648 __pi_post_block(vcpu);
13649 local_irq_enable();
13652 static void vmx_post_block(struct kvm_vcpu *vcpu)
13654 if (kvm_x86_ops->set_hv_timer)
13655 kvm_lapic_switch_to_hv_timer(vcpu);
13657 pi_post_block(vcpu);
13661 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
13664 * @host_irq: host irq of the interrupt
13665 * @guest_irq: gsi of the interrupt
13666 * @set: set or unset PI
13667 * returns 0 on success, < 0 on failure
13669 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
13670 uint32_t guest_irq, bool set)
13672 struct kvm_kernel_irq_routing_entry *e;
13673 struct kvm_irq_routing_table *irq_rt;
13674 struct kvm_lapic_irq irq;
13675 struct kvm_vcpu *vcpu;
13676 struct vcpu_data vcpu_info;
13679 if (!kvm_arch_has_assigned_device(kvm) ||
13680 !irq_remapping_cap(IRQ_POSTING_CAP) ||
13681 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
13684 idx = srcu_read_lock(&kvm->irq_srcu);
13685 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
13686 if (guest_irq >= irq_rt->nr_rt_entries ||
13687 hlist_empty(&irq_rt->map[guest_irq])) {
13688 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
13689 guest_irq, irq_rt->nr_rt_entries);
13693 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
13694 if (e->type != KVM_IRQ_ROUTING_MSI)
13697 * VT-d PI cannot support posting multicast/broadcast
13698 * interrupts to a vCPU, we still use interrupt remapping
13699 * for these kind of interrupts.
13701 * For lowest-priority interrupts, we only support
13702 * those with single CPU as the destination, e.g. user
13703 * configures the interrupts via /proc/irq or uses
13704 * irqbalance to make the interrupts single-CPU.
13706 * We will support full lowest-priority interrupt later.
13709 kvm_set_msi_irq(kvm, e, &irq);
13710 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
13712 * Make sure the IRTE is in remapped mode if
13713 * we don't handle it in posted mode.
13715 ret = irq_set_vcpu_affinity(host_irq, NULL);
13718 "failed to back to remapped mode, irq: %u\n",
13726 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
13727 vcpu_info.vector = irq.vector;
13729 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
13730 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
13733 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
13735 ret = irq_set_vcpu_affinity(host_irq, NULL);
13738 printk(KERN_INFO "%s: failed to update PI IRTE\n",
13746 srcu_read_unlock(&kvm->irq_srcu, idx);
13750 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
13752 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
13753 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
13754 FEATURE_CONTROL_LMCE;
13756 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
13757 ~FEATURE_CONTROL_LMCE;
13760 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
13762 /* we need a nested vmexit to enter SMM, postpone if run is pending */
13763 if (to_vmx(vcpu)->nested.nested_run_pending)
13768 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
13770 struct vcpu_vmx *vmx = to_vmx(vcpu);
13772 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
13773 if (vmx->nested.smm.guest_mode)
13774 nested_vmx_vmexit(vcpu, -1, 0, 0);
13776 vmx->nested.smm.vmxon = vmx->nested.vmxon;
13777 vmx->nested.vmxon = false;
13778 vmx_clear_hlt(vcpu);
13782 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
13784 struct vcpu_vmx *vmx = to_vmx(vcpu);
13787 if (vmx->nested.smm.vmxon) {
13788 vmx->nested.vmxon = true;
13789 vmx->nested.smm.vmxon = false;
13792 if (vmx->nested.smm.guest_mode) {
13793 vcpu->arch.hflags &= ~HF_SMM_MASK;
13794 ret = enter_vmx_non_root_mode(vcpu, NULL);
13795 vcpu->arch.hflags |= HF_SMM_MASK;
13799 vmx->nested.smm.guest_mode = false;
13804 static int enable_smi_window(struct kvm_vcpu *vcpu)
13809 static int vmx_get_nested_state(struct kvm_vcpu *vcpu,
13810 struct kvm_nested_state __user *user_kvm_nested_state,
13811 u32 user_data_size)
13813 struct vcpu_vmx *vmx;
13814 struct vmcs12 *vmcs12;
13815 struct kvm_nested_state kvm_state = {
13818 .size = sizeof(kvm_state),
13819 .vmx.vmxon_pa = -1ull,
13820 .vmx.vmcs_pa = -1ull,
13824 return kvm_state.size + 2 * VMCS12_SIZE;
13826 vmx = to_vmx(vcpu);
13827 vmcs12 = get_vmcs12(vcpu);
13828 if (nested_vmx_allowed(vcpu) &&
13829 (vmx->nested.vmxon || vmx->nested.smm.vmxon)) {
13830 kvm_state.vmx.vmxon_pa = vmx->nested.vmxon_ptr;
13831 kvm_state.vmx.vmcs_pa = vmx->nested.current_vmptr;
13833 if (vmx->nested.current_vmptr != -1ull) {
13834 kvm_state.size += VMCS12_SIZE;
13836 if (is_guest_mode(vcpu) &&
13837 nested_cpu_has_shadow_vmcs(vmcs12) &&
13838 vmcs12->vmcs_link_pointer != -1ull)
13839 kvm_state.size += VMCS12_SIZE;
13842 if (vmx->nested.smm.vmxon)
13843 kvm_state.vmx.smm.flags |= KVM_STATE_NESTED_SMM_VMXON;
13845 if (vmx->nested.smm.guest_mode)
13846 kvm_state.vmx.smm.flags |= KVM_STATE_NESTED_SMM_GUEST_MODE;
13848 if (is_guest_mode(vcpu)) {
13849 kvm_state.flags |= KVM_STATE_NESTED_GUEST_MODE;
13851 if (vmx->nested.nested_run_pending)
13852 kvm_state.flags |= KVM_STATE_NESTED_RUN_PENDING;
13856 if (user_data_size < kvm_state.size)
13859 if (copy_to_user(user_kvm_nested_state, &kvm_state, sizeof(kvm_state)))
13862 if (vmx->nested.current_vmptr == -1ull)
13866 * When running L2, the authoritative vmcs12 state is in the
13867 * vmcs02. When running L1, the authoritative vmcs12 state is
13868 * in the shadow vmcs linked to vmcs01, unless
13869 * sync_shadow_vmcs is set, in which case, the authoritative
13870 * vmcs12 state is in the vmcs12 already.
13872 if (is_guest_mode(vcpu))
13873 sync_vmcs12(vcpu, vmcs12);
13874 else if (enable_shadow_vmcs && !vmx->nested.sync_shadow_vmcs)
13875 copy_shadow_to_vmcs12(vmx);
13877 if (copy_to_user(user_kvm_nested_state->data, vmcs12, sizeof(*vmcs12)))
13880 if (nested_cpu_has_shadow_vmcs(vmcs12) &&
13881 vmcs12->vmcs_link_pointer != -1ull) {
13882 if (copy_to_user(user_kvm_nested_state->data + VMCS12_SIZE,
13883 get_shadow_vmcs12(vcpu), sizeof(*vmcs12)))
13888 return kvm_state.size;
13891 static int vmx_set_nested_state(struct kvm_vcpu *vcpu,
13892 struct kvm_nested_state __user *user_kvm_nested_state,
13893 struct kvm_nested_state *kvm_state)
13895 struct vcpu_vmx *vmx = to_vmx(vcpu);
13896 struct vmcs12 *vmcs12;
13900 if (kvm_state->format != 0)
13903 if (!nested_vmx_allowed(vcpu))
13904 return kvm_state->vmx.vmxon_pa == -1ull ? 0 : -EINVAL;
13906 if (kvm_state->vmx.vmxon_pa == -1ull) {
13907 if (kvm_state->vmx.smm.flags)
13910 if (kvm_state->vmx.vmcs_pa != -1ull)
13913 vmx_leave_nested(vcpu);
13917 if (!page_address_valid(vcpu, kvm_state->vmx.vmxon_pa))
13920 if (kvm_state->size < sizeof(kvm_state) + sizeof(*vmcs12))
13923 if (kvm_state->vmx.vmcs_pa == kvm_state->vmx.vmxon_pa ||
13924 !page_address_valid(vcpu, kvm_state->vmx.vmcs_pa))
13927 if ((kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
13928 (kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
13931 if (kvm_state->vmx.smm.flags &
13932 ~(KVM_STATE_NESTED_SMM_GUEST_MODE | KVM_STATE_NESTED_SMM_VMXON))
13935 if ((kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
13936 !(kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON))
13939 vmx_leave_nested(vcpu);
13940 if (kvm_state->vmx.vmxon_pa == -1ull)
13943 vmx->nested.vmxon_ptr = kvm_state->vmx.vmxon_pa;
13944 ret = enter_vmx_operation(vcpu);
13948 set_current_vmptr(vmx, kvm_state->vmx.vmcs_pa);
13950 if (kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON) {
13951 vmx->nested.smm.vmxon = true;
13952 vmx->nested.vmxon = false;
13954 if (kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE)
13955 vmx->nested.smm.guest_mode = true;
13958 vmcs12 = get_vmcs12(vcpu);
13959 if (copy_from_user(vmcs12, user_kvm_nested_state->data, sizeof(*vmcs12)))
13962 if (vmcs12->hdr.revision_id != VMCS12_REVISION)
13965 if (!(kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
13968 vmx->nested.nested_run_pending =
13969 !!(kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING);
13971 if (nested_cpu_has_shadow_vmcs(vmcs12) &&
13972 vmcs12->vmcs_link_pointer != -1ull) {
13973 struct vmcs12 *shadow_vmcs12 = get_shadow_vmcs12(vcpu);
13974 if (kvm_state->size < sizeof(kvm_state) + 2 * sizeof(*vmcs12))
13977 if (copy_from_user(shadow_vmcs12,
13978 user_kvm_nested_state->data + VMCS12_SIZE,
13982 if (shadow_vmcs12->hdr.revision_id != VMCS12_REVISION ||
13983 !shadow_vmcs12->hdr.shadow_vmcs)
13987 if (check_vmentry_prereqs(vcpu, vmcs12) ||
13988 check_vmentry_postreqs(vcpu, vmcs12, &exit_qual))
13991 if (kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING)
13992 vmx->nested.nested_run_pending = 1;
13994 vmx->nested.dirty_vmcs12 = true;
13995 ret = enter_vmx_non_root_mode(vcpu, NULL);
14002 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
14003 .cpu_has_kvm_support = cpu_has_kvm_support,
14004 .disabled_by_bios = vmx_disabled_by_bios,
14005 .hardware_setup = hardware_setup,
14006 .hardware_unsetup = hardware_unsetup,
14007 .check_processor_compatibility = vmx_check_processor_compat,
14008 .hardware_enable = hardware_enable,
14009 .hardware_disable = hardware_disable,
14010 .cpu_has_accelerated_tpr = report_flexpriority,
14011 .has_emulated_msr = vmx_has_emulated_msr,
14013 .vm_init = vmx_vm_init,
14014 .vm_alloc = vmx_vm_alloc,
14015 .vm_free = vmx_vm_free,
14017 .vcpu_create = vmx_create_vcpu,
14018 .vcpu_free = vmx_free_vcpu,
14019 .vcpu_reset = vmx_vcpu_reset,
14021 .prepare_guest_switch = vmx_prepare_switch_to_guest,
14022 .vcpu_load = vmx_vcpu_load,
14023 .vcpu_put = vmx_vcpu_put,
14025 .update_bp_intercept = update_exception_bitmap,
14026 .get_msr_feature = vmx_get_msr_feature,
14027 .get_msr = vmx_get_msr,
14028 .set_msr = vmx_set_msr,
14029 .get_segment_base = vmx_get_segment_base,
14030 .get_segment = vmx_get_segment,
14031 .set_segment = vmx_set_segment,
14032 .get_cpl = vmx_get_cpl,
14033 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
14034 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
14035 .decache_cr3 = vmx_decache_cr3,
14036 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
14037 .set_cr0 = vmx_set_cr0,
14038 .set_cr3 = vmx_set_cr3,
14039 .set_cr4 = vmx_set_cr4,
14040 .set_efer = vmx_set_efer,
14041 .get_idt = vmx_get_idt,
14042 .set_idt = vmx_set_idt,
14043 .get_gdt = vmx_get_gdt,
14044 .set_gdt = vmx_set_gdt,
14045 .get_dr6 = vmx_get_dr6,
14046 .set_dr6 = vmx_set_dr6,
14047 .set_dr7 = vmx_set_dr7,
14048 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
14049 .cache_reg = vmx_cache_reg,
14050 .get_rflags = vmx_get_rflags,
14051 .set_rflags = vmx_set_rflags,
14053 .tlb_flush = vmx_flush_tlb,
14054 .tlb_flush_gva = vmx_flush_tlb_gva,
14056 .run = vmx_vcpu_run,
14057 .handle_exit = vmx_handle_exit,
14058 .skip_emulated_instruction = skip_emulated_instruction,
14059 .set_interrupt_shadow = vmx_set_interrupt_shadow,
14060 .get_interrupt_shadow = vmx_get_interrupt_shadow,
14061 .patch_hypercall = vmx_patch_hypercall,
14062 .set_irq = vmx_inject_irq,
14063 .set_nmi = vmx_inject_nmi,
14064 .queue_exception = vmx_queue_exception,
14065 .cancel_injection = vmx_cancel_injection,
14066 .interrupt_allowed = vmx_interrupt_allowed,
14067 .nmi_allowed = vmx_nmi_allowed,
14068 .get_nmi_mask = vmx_get_nmi_mask,
14069 .set_nmi_mask = vmx_set_nmi_mask,
14070 .enable_nmi_window = enable_nmi_window,
14071 .enable_irq_window = enable_irq_window,
14072 .update_cr8_intercept = update_cr8_intercept,
14073 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
14074 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
14075 .get_enable_apicv = vmx_get_enable_apicv,
14076 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
14077 .load_eoi_exitmap = vmx_load_eoi_exitmap,
14078 .apicv_post_state_restore = vmx_apicv_post_state_restore,
14079 .hwapic_irr_update = vmx_hwapic_irr_update,
14080 .hwapic_isr_update = vmx_hwapic_isr_update,
14081 .sync_pir_to_irr = vmx_sync_pir_to_irr,
14082 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
14084 .set_tss_addr = vmx_set_tss_addr,
14085 .set_identity_map_addr = vmx_set_identity_map_addr,
14086 .get_tdp_level = get_ept_level,
14087 .get_mt_mask = vmx_get_mt_mask,
14089 .get_exit_info = vmx_get_exit_info,
14091 .get_lpage_level = vmx_get_lpage_level,
14093 .cpuid_update = vmx_cpuid_update,
14095 .rdtscp_supported = vmx_rdtscp_supported,
14096 .invpcid_supported = vmx_invpcid_supported,
14098 .set_supported_cpuid = vmx_set_supported_cpuid,
14100 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
14102 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
14103 .write_tsc_offset = vmx_write_tsc_offset,
14105 .set_tdp_cr3 = vmx_set_cr3,
14107 .check_intercept = vmx_check_intercept,
14108 .handle_external_intr = vmx_handle_external_intr,
14109 .mpx_supported = vmx_mpx_supported,
14110 .xsaves_supported = vmx_xsaves_supported,
14111 .umip_emulated = vmx_umip_emulated,
14113 .check_nested_events = vmx_check_nested_events,
14115 .sched_in = vmx_sched_in,
14117 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
14118 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
14119 .flush_log_dirty = vmx_flush_log_dirty,
14120 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
14121 .write_log_dirty = vmx_write_pml_buffer,
14123 .pre_block = vmx_pre_block,
14124 .post_block = vmx_post_block,
14126 .pmu_ops = &intel_pmu_ops,
14128 .update_pi_irte = vmx_update_pi_irte,
14130 #ifdef CONFIG_X86_64
14131 .set_hv_timer = vmx_set_hv_timer,
14132 .cancel_hv_timer = vmx_cancel_hv_timer,
14135 .setup_mce = vmx_setup_mce,
14137 .get_nested_state = vmx_get_nested_state,
14138 .set_nested_state = vmx_set_nested_state,
14139 .get_vmcs12_pages = nested_get_vmcs12_pages,
14141 .smi_allowed = vmx_smi_allowed,
14142 .pre_enter_smm = vmx_pre_enter_smm,
14143 .pre_leave_smm = vmx_pre_leave_smm,
14144 .enable_smi_window = enable_smi_window,
14147 static void vmx_cleanup_l1d_flush(void)
14149 if (vmx_l1d_flush_pages) {
14150 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
14151 vmx_l1d_flush_pages = NULL;
14153 /* Restore state so sysfs ignores VMX */
14154 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
14157 static void vmx_exit(void)
14159 #ifdef CONFIG_KEXEC_CORE
14160 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
14166 #if IS_ENABLED(CONFIG_HYPERV)
14167 if (static_branch_unlikely(&enable_evmcs)) {
14169 struct hv_vp_assist_page *vp_ap;
14171 * Reset everything to support using non-enlightened VMCS
14172 * access later (e.g. when we reload the module with
14173 * enlightened_vmcs=0)
14175 for_each_online_cpu(cpu) {
14176 vp_ap = hv_get_vp_assist_page(cpu);
14181 vp_ap->current_nested_vmcs = 0;
14182 vp_ap->enlighten_vmentry = 0;
14185 static_branch_disable(&enable_evmcs);
14188 vmx_cleanup_l1d_flush();
14190 module_exit(vmx_exit);
14192 static int __init vmx_init(void)
14196 #if IS_ENABLED(CONFIG_HYPERV)
14198 * Enlightened VMCS usage should be recommended and the host needs
14199 * to support eVMCS v1 or above. We can also disable eVMCS support
14200 * with module parameter.
14202 if (enlightened_vmcs &&
14203 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
14204 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
14205 KVM_EVMCS_VERSION) {
14208 /* Check that we have assist pages on all online CPUs */
14209 for_each_online_cpu(cpu) {
14210 if (!hv_get_vp_assist_page(cpu)) {
14211 enlightened_vmcs = false;
14216 if (enlightened_vmcs) {
14217 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
14218 static_branch_enable(&enable_evmcs);
14221 enlightened_vmcs = false;
14225 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
14226 __alignof__(struct vcpu_vmx), THIS_MODULE);
14231 * Must be called after kvm_init() so enable_ept is properly set
14232 * up. Hand the parameter mitigation value in which was stored in
14233 * the pre module init parser. If no parameter was given, it will
14234 * contain 'auto' which will be turned into the default 'cond'
14237 if (boot_cpu_has(X86_BUG_L1TF)) {
14238 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
14245 #ifdef CONFIG_KEXEC_CORE
14246 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
14247 crash_vmclear_local_loaded_vmcss);
14249 vmx_check_vmcs12_offsets();
14253 module_init(vmx_init);