arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/frame.h>
  37 #include <linux/nospec.h>
  38 #include "kvm_cache_regs.h"
  39 #include "x86.h"
  40
  41 #include <asm/asm.h>
  42 #include <asm/cpu.h>
  43 #include <asm/io.h>
  44 #include <asm/desc.h>
  45 #include <asm/vmx.h>
  46 #include <asm/virtext.h>
  47 #include <asm/mce.h>
  48 #include <asm/fpu/internal.h>
  49 #include <asm/perf_event.h>
  50 #include <asm/debugreg.h>
  51 #include <asm/kexec.h>
  52 #include <asm/apic.h>
  53 #include <asm/irq_remapping.h>
  54 #include <asm/mmu_context.h>
  55 #include <asm/spec-ctrl.h>
  56 #include <asm/mshyperv.h>
  57
  58 #include "trace.h"
  59 #include "pmu.h"
  60 #include "vmx_evmcs.h"
  61
  62 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  63 #define __ex_clear(x, reg) \
  64         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  65
  66 MODULE_AUTHOR("Qumranet");
  67 MODULE_LICENSE("GPL");
  68
  69 static const struct x86_cpu_id vmx_cpu_id[] = {
  70         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  71         {}
  72 };
  73 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  74
  75 static bool __read_mostly enable_vpid = 1;
  76 module_param_named(vpid, enable_vpid, bool, 0444);
  77
  78 static bool __read_mostly enable_vnmi = 1;
  79 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
  80
  81 static bool __read_mostly flexpriority_enabled = 1;
  82 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  83
  84 static bool __read_mostly enable_ept = 1;
  85 module_param_named(ept, enable_ept, bool, S_IRUGO);
  86
  87 static bool __read_mostly enable_unrestricted_guest = 1;
  88 module_param_named(unrestricted_guest,
  89                         enable_unrestricted_guest, bool, S_IRUGO);
  90
  91 static bool __read_mostly enable_ept_ad_bits = 1;
  92 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  93
  94 static bool __read_mostly emulate_invalid_guest_state = true;
  95 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  96
  97 static bool __read_mostly fasteoi = 1;
  98 module_param(fasteoi, bool, S_IRUGO);
  99
 100 static bool __read_mostly enable_apicv = 1;
 101 module_param(enable_apicv, bool, S_IRUGO);
 102
 103 static bool __read_mostly enable_shadow_vmcs = 1;
 104 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
 105 /*
 106  * If nested=1, nested virtualization is supported, i.e., guests may use
 107  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 108  * use VMX instructions.
 109  */
 110 static bool __read_mostly nested = 0;
 111 module_param(nested, bool, S_IRUGO);
 112
 113 static bool __read_mostly nested_early_check = 0;
 114 module_param(nested_early_check, bool, S_IRUGO);
 115
 116 static u64 __read_mostly host_xss;
 117
 118 static bool __read_mostly enable_pml = 1;
 119 module_param_named(pml, enable_pml, bool, S_IRUGO);
 120
 121 #define MSR_TYPE_R      1
 122 #define MSR_TYPE_W      2
 123 #define MSR_TYPE_RW     3
 124
 125 #define MSR_BITMAP_MODE_X2APIC          1
 126 #define MSR_BITMAP_MODE_X2APIC_APICV    2
 127
 128 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 129
 130 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 131 static int __read_mostly cpu_preemption_timer_multi;
 132 static bool __read_mostly enable_preemption_timer = 1;
 133 #ifdef CONFIG_X86_64
 134 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 135 #endif
 136
 137 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
 138 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
 139 #define KVM_VM_CR0_ALWAYS_ON                            \
 140         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST |      \
 141          X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
 142 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 143         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 144          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 145
 146 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
 147 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 148 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 149
 150 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 151
 152 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 153
 154 /*
 155  * Hyper-V requires all of these, so mark them as supported even though
 156  * they are just treated the same as all-context.
 157  */
 158 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 159         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 160         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 161         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 162         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 163
 164 /*
 165  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 166  * ple_gap:    upper bound on the amount of time between two successive
 167  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 168  *             According to test, this time is usually smaller than 128 cycles.
 169  * ple_window: upper bound on the amount of time a guest is allowed to execute
 170  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 171  *             less than 2^12 cycles
 172  * Time is measured based on a counter that runs at the same rate as the TSC,
 173  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 174  */
 175 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
 176
 177 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 178 module_param(ple_window, uint, 0444);
 179
 180 /* Default doubles per-vcpu window every exit. */
 181 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 182 module_param(ple_window_grow, uint, 0444);
 183
 184 /* Default resets per-vcpu window every exit to ple_window. */
 185 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 186 module_param(ple_window_shrink, uint, 0444);
 187
 188 /* Default is to compute the maximum so we can never overflow. */
 189 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 190 module_param(ple_window_max, uint, 0444);
 191
 192 extern const ulong vmx_return;
 193 extern const ulong vmx_early_consistency_check_return;
 194
 195 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
 196 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
 197 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
 198
 199 /* Storage for pre module init parameter parsing */
 200 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
 201
 202 static const struct {
 203         const char *option;
 204         bool for_parse;
 205 } vmentry_l1d_param[] = {
 206         [VMENTER_L1D_FLUSH_AUTO]         = {"auto", true},
 207         [VMENTER_L1D_FLUSH_NEVER]        = {"never", true},
 208         [VMENTER_L1D_FLUSH_COND]         = {"cond", true},
 209         [VMENTER_L1D_FLUSH_ALWAYS]       = {"always", true},
 210         [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
 211         [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
 212 };
 213
 214 #define L1D_CACHE_ORDER 4
 215 static void *vmx_l1d_flush_pages;
 216
 217 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
 218 {
 219         struct page *page;
 220         unsigned int i;
 221
 222         if (!enable_ept) {
 223                 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
 224                 return 0;
 225         }
 226
 227         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
 228                 u64 msr;
 229
 230                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
 231                 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
 232                         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
 233                         return 0;
 234                 }
 235         }
 236
 237         /* If set to auto use the default l1tf mitigation method */
 238         if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
 239                 switch (l1tf_mitigation) {
 240                 case L1TF_MITIGATION_OFF:
 241                         l1tf = VMENTER_L1D_FLUSH_NEVER;
 242                         break;
 243                 case L1TF_MITIGATION_FLUSH_NOWARN:
 244                 case L1TF_MITIGATION_FLUSH:
 245                 case L1TF_MITIGATION_FLUSH_NOSMT:
 246                         l1tf = VMENTER_L1D_FLUSH_COND;
 247                         break;
 248                 case L1TF_MITIGATION_FULL:
 249                 case L1TF_MITIGATION_FULL_FORCE:
 250                         l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 251                         break;
 252                 }
 253         } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
 254                 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
 255         }
 256
 257         if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
 258             !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
 259                 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
 260                 if (!page)
 261                         return -ENOMEM;
 262                 vmx_l1d_flush_pages = page_address(page);
 263
 264                 /*
 265                  * Initialize each page with a different pattern in
 266                  * order to protect against KSM in the nested
 267                  * virtualization case.
 268                  */
 269                 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
 270                         memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
 271                                PAGE_SIZE);
 272                 }
 273         }
 274
 275         l1tf_vmx_mitigation = l1tf;
 276
 277         if (l1tf != VMENTER_L1D_FLUSH_NEVER)
 278                 static_branch_enable(&vmx_l1d_should_flush);
 279         else
 280                 static_branch_disable(&vmx_l1d_should_flush);
 281
 282         if (l1tf == VMENTER_L1D_FLUSH_COND)
 283                 static_branch_enable(&vmx_l1d_flush_cond);
 284         else
 285                 static_branch_disable(&vmx_l1d_flush_cond);
 286         return 0;
 287 }
 288
 289 static int vmentry_l1d_flush_parse(const char *s)
 290 {
 291         unsigned int i;
 292
 293         if (s) {
 294                 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
 295                         if (vmentry_l1d_param[i].for_parse &&
 296                             sysfs_streq(s, vmentry_l1d_param[i].option))
 297                                 return i;
 298                 }
 299         }
 300         return -EINVAL;
 301 }
 302
 303 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
 304 {
 305         int l1tf, ret;
 306
 307         l1tf = vmentry_l1d_flush_parse(s);
 308         if (l1tf < 0)
 309                 return l1tf;
 310
 311         if (!boot_cpu_has(X86_BUG_L1TF))
 312                 return 0;
 313
 314         /*
 315          * Has vmx_init() run already? If not then this is the pre init
 316          * parameter parsing. In that case just store the value and let
 317          * vmx_init() do the proper setup after enable_ept has been
 318          * established.
 319          */
 320         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
 321                 vmentry_l1d_flush_param = l1tf;
 322                 return 0;
 323         }
 324
 325         mutex_lock(&vmx_l1d_flush_mutex);
 326         ret = vmx_setup_l1d_flush(l1tf);
 327         mutex_unlock(&vmx_l1d_flush_mutex);
 328         return ret;
 329 }
 330
 331 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
 332 {
 333         if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
 334                 return sprintf(s, "???\n");
 335
 336         return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
 337 }
 338
 339 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
 340         .set = vmentry_l1d_flush_set,
 341         .get = vmentry_l1d_flush_get,
 342 };
 343 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
 344
 345 enum ept_pointers_status {
 346         EPT_POINTERS_CHECK = 0,
 347         EPT_POINTERS_MATCH = 1,
 348         EPT_POINTERS_MISMATCH = 2
 349 };
 350
 351 struct kvm_vmx {
 352         struct kvm kvm;
 353
 354         unsigned int tss_addr;
 355         bool ept_identity_pagetable_done;
 356         gpa_t ept_identity_map_addr;
 357
 358         enum ept_pointers_status ept_pointers_match;
 359         spinlock_t ept_pointer_lock;
 360 };
 361
 362 #define NR_AUTOLOAD_MSRS 8
 363
 364 struct vmcs_hdr {
 365         u32 revision_id:31;
 366         u32 shadow_vmcs:1;
 367 };
 368
 369 struct vmcs {
 370         struct vmcs_hdr hdr;
 371         u32 abort;
 372         char data[0];
 373 };
 374
 375 /*
 376  * vmcs_host_state tracks registers that are loaded from the VMCS on VMEXIT
 377  * and whose values change infrequently, but are not constant.  I.e. this is
 378  * used as a write-through cache of the corresponding VMCS fields.
 379  */
 380 struct vmcs_host_state {
 381         unsigned long cr3;      /* May not match real cr3 */
 382         unsigned long cr4;      /* May not match real cr4 */
 383         unsigned long gs_base;
 384         unsigned long fs_base;
 385
 386         u16           fs_sel, gs_sel, ldt_sel;
 387 #ifdef CONFIG_X86_64
 388         u16           ds_sel, es_sel;
 389 #endif
 390 };
 391
 392 /*
 393  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 394  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 395  * loaded on this CPU (so we can clear them if the CPU goes down).
 396  */
 397 struct loaded_vmcs {
 398         struct vmcs *vmcs;
 399         struct vmcs *shadow_vmcs;
 400         int cpu;
 401         bool launched;
 402         bool nmi_known_unmasked;
 403         bool hv_timer_armed;
 404         /* Support for vnmi-less CPUs */
 405         int soft_vnmi_blocked;
 406         ktime_t entry_time;
 407         s64 vnmi_blocked_time;
 408         unsigned long *msr_bitmap;
 409         struct list_head loaded_vmcss_on_cpu_link;
 410         struct vmcs_host_state host_state;
 411 };
 412
 413 struct shared_msr_entry {
 414         unsigned index;
 415         u64 data;
 416         u64 mask;
 417 };
 418
 419 /*
 420  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 421  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 422  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 423  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 424  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 425  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 426  * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
 427  * underlying hardware which will be used to run L2.
 428  * This structure is packed to ensure that its layout is identical across
 429  * machines (necessary for live migration).
 430  *
 431  * IMPORTANT: Changing the layout of existing fields in this structure
 432  * will break save/restore compatibility with older kvm releases. When
 433  * adding new fields, either use space in the reserved padding* arrays
 434  * or add the new fields to the end of the structure.
 435  */
 436 typedef u64 natural_width;
 437 struct __packed vmcs12 {
 438         /* According to the Intel spec, a VMCS region must start with the
 439          * following two fields. Then follow implementation-specific data.
 440          */
 441         struct vmcs_hdr hdr;
 442         u32 abort;
 443
 444         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 445         u32 padding[7]; /* room for future expansion */
 446
 447         u64 io_bitmap_a;
 448         u64 io_bitmap_b;
 449         u64 msr_bitmap;
 450         u64 vm_exit_msr_store_addr;
 451         u64 vm_exit_msr_load_addr;
 452         u64 vm_entry_msr_load_addr;
 453         u64 tsc_offset;
 454         u64 virtual_apic_page_addr;
 455         u64 apic_access_addr;
 456         u64 posted_intr_desc_addr;
 457         u64 ept_pointer;
 458         u64 eoi_exit_bitmap0;
 459         u64 eoi_exit_bitmap1;
 460         u64 eoi_exit_bitmap2;
 461         u64 eoi_exit_bitmap3;
 462         u64 xss_exit_bitmap;
 463         u64 guest_physical_address;
 464         u64 vmcs_link_pointer;
 465         u64 guest_ia32_debugctl;
 466         u64 guest_ia32_pat;
 467         u64 guest_ia32_efer;
 468         u64 guest_ia32_perf_global_ctrl;
 469         u64 guest_pdptr0;
 470         u64 guest_pdptr1;
 471         u64 guest_pdptr2;
 472         u64 guest_pdptr3;
 473         u64 guest_bndcfgs;
 474         u64 host_ia32_pat;
 475         u64 host_ia32_efer;
 476         u64 host_ia32_perf_global_ctrl;
 477         u64 vmread_bitmap;
 478         u64 vmwrite_bitmap;
 479         u64 vm_function_control;
 480         u64 eptp_list_address;
 481         u64 pml_address;
 482         u64 padding64[3]; /* room for future expansion */
 483         /*
 484          * To allow migration of L1 (complete with its L2 guests) between
 485          * machines of different natural widths (32 or 64 bit), we cannot have
 486          * unsigned long fields with no explict size. We use u64 (aliased
 487          * natural_width) instead. Luckily, x86 is little-endian.
 488          */
 489         natural_width cr0_guest_host_mask;
 490         natural_width cr4_guest_host_mask;
 491         natural_width cr0_read_shadow;
 492         natural_width cr4_read_shadow;
 493         natural_width cr3_target_value0;
 494         natural_width cr3_target_value1;
 495         natural_width cr3_target_value2;
 496         natural_width cr3_target_value3;
 497         natural_width exit_qualification;
 498         natural_width guest_linear_address;
 499         natural_width guest_cr0;
 500         natural_width guest_cr3;
 501         natural_width guest_cr4;
 502         natural_width guest_es_base;
 503         natural_width guest_cs_base;
 504         natural_width guest_ss_base;
 505         natural_width guest_ds_base;
 506         natural_width guest_fs_base;
 507         natural_width guest_gs_base;
 508         natural_width guest_ldtr_base;
 509         natural_width guest_tr_base;
 510         natural_width guest_gdtr_base;
 511         natural_width guest_idtr_base;
 512         natural_width guest_dr7;
 513         natural_width guest_rsp;
 514         natural_width guest_rip;
 515         natural_width guest_rflags;
 516         natural_width guest_pending_dbg_exceptions;
 517         natural_width guest_sysenter_esp;
 518         natural_width guest_sysenter_eip;
 519         natural_width host_cr0;
 520         natural_width host_cr3;
 521         natural_width host_cr4;
 522         natural_width host_fs_base;
 523         natural_width host_gs_base;
 524         natural_width host_tr_base;
 525         natural_width host_gdtr_base;
 526         natural_width host_idtr_base;
 527         natural_width host_ia32_sysenter_esp;
 528         natural_width host_ia32_sysenter_eip;
 529         natural_width host_rsp;
 530         natural_width host_rip;
 531         natural_width paddingl[8]; /* room for future expansion */
 532         u32 pin_based_vm_exec_control;
 533         u32 cpu_based_vm_exec_control;
 534         u32 exception_bitmap;
 535         u32 page_fault_error_code_mask;
 536         u32 page_fault_error_code_match;
 537         u32 cr3_target_count;
 538         u32 vm_exit_controls;
 539         u32 vm_exit_msr_store_count;
 540         u32 vm_exit_msr_load_count;
 541         u32 vm_entry_controls;
 542         u32 vm_entry_msr_load_count;
 543         u32 vm_entry_intr_info_field;
 544         u32 vm_entry_exception_error_code;
 545         u32 vm_entry_instruction_len;
 546         u32 tpr_threshold;
 547         u32 secondary_vm_exec_control;
 548         u32 vm_instruction_error;
 549         u32 vm_exit_reason;
 550         u32 vm_exit_intr_info;
 551         u32 vm_exit_intr_error_code;
 552         u32 idt_vectoring_info_field;
 553         u32 idt_vectoring_error_code;
 554         u32 vm_exit_instruction_len;
 555         u32 vmx_instruction_info;
 556         u32 guest_es_limit;
 557         u32 guest_cs_limit;
 558         u32 guest_ss_limit;
 559         u32 guest_ds_limit;
 560         u32 guest_fs_limit;
 561         u32 guest_gs_limit;
 562         u32 guest_ldtr_limit;
 563         u32 guest_tr_limit;
 564         u32 guest_gdtr_limit;
 565         u32 guest_idtr_limit;
 566         u32 guest_es_ar_bytes;
 567         u32 guest_cs_ar_bytes;
 568         u32 guest_ss_ar_bytes;
 569         u32 guest_ds_ar_bytes;
 570         u32 guest_fs_ar_bytes;
 571         u32 guest_gs_ar_bytes;
 572         u32 guest_ldtr_ar_bytes;
 573         u32 guest_tr_ar_bytes;
 574         u32 guest_interruptibility_info;
 575         u32 guest_activity_state;
 576         u32 guest_sysenter_cs;
 577         u32 host_ia32_sysenter_cs;
 578         u32 vmx_preemption_timer_value;
 579         u32 padding32[7]; /* room for future expansion */
 580         u16 virtual_processor_id;
 581         u16 posted_intr_nv;
 582         u16 guest_es_selector;
 583         u16 guest_cs_selector;
 584         u16 guest_ss_selector;
 585         u16 guest_ds_selector;
 586         u16 guest_fs_selector;
 587         u16 guest_gs_selector;
 588         u16 guest_ldtr_selector;
 589         u16 guest_tr_selector;
 590         u16 guest_intr_status;
 591         u16 host_es_selector;
 592         u16 host_cs_selector;
 593         u16 host_ss_selector;
 594         u16 host_ds_selector;
 595         u16 host_fs_selector;
 596         u16 host_gs_selector;
 597         u16 host_tr_selector;
 598         u16 guest_pml_index;
 599 };
 600
 601 /*
 602  * For save/restore compatibility, the vmcs12 field offsets must not change.
 603  */
 604 #define CHECK_OFFSET(field, loc)                                \
 605         BUILD_BUG_ON_MSG(offsetof(struct vmcs12, field) != (loc),       \
 606                 "Offset of " #field " in struct vmcs12 has changed.")
 607
 608 static inline void vmx_check_vmcs12_offsets(void) {
 609         CHECK_OFFSET(hdr, 0);
 610         CHECK_OFFSET(abort, 4);
 611         CHECK_OFFSET(launch_state, 8);
 612         CHECK_OFFSET(io_bitmap_a, 40);
 613         CHECK_OFFSET(io_bitmap_b, 48);
 614         CHECK_OFFSET(msr_bitmap, 56);
 615         CHECK_OFFSET(vm_exit_msr_store_addr, 64);
 616         CHECK_OFFSET(vm_exit_msr_load_addr, 72);
 617         CHECK_OFFSET(vm_entry_msr_load_addr, 80);
 618         CHECK_OFFSET(tsc_offset, 88);
 619         CHECK_OFFSET(virtual_apic_page_addr, 96);
 620         CHECK_OFFSET(apic_access_addr, 104);
 621         CHECK_OFFSET(posted_intr_desc_addr, 112);
 622         CHECK_OFFSET(ept_pointer, 120);
 623         CHECK_OFFSET(eoi_exit_bitmap0, 128);
 624         CHECK_OFFSET(eoi_exit_bitmap1, 136);
 625         CHECK_OFFSET(eoi_exit_bitmap2, 144);
 626         CHECK_OFFSET(eoi_exit_bitmap3, 152);
 627         CHECK_OFFSET(xss_exit_bitmap, 160);
 628         CHECK_OFFSET(guest_physical_address, 168);
 629         CHECK_OFFSET(vmcs_link_pointer, 176);
 630         CHECK_OFFSET(guest_ia32_debugctl, 184);
 631         CHECK_OFFSET(guest_ia32_pat, 192);
 632         CHECK_OFFSET(guest_ia32_efer, 200);
 633         CHECK_OFFSET(guest_ia32_perf_global_ctrl, 208);
 634         CHECK_OFFSET(guest_pdptr0, 216);
 635         CHECK_OFFSET(guest_pdptr1, 224);
 636         CHECK_OFFSET(guest_pdptr2, 232);
 637         CHECK_OFFSET(guest_pdptr3, 240);
 638         CHECK_OFFSET(guest_bndcfgs, 248);
 639         CHECK_OFFSET(host_ia32_pat, 256);
 640         CHECK_OFFSET(host_ia32_efer, 264);
 641         CHECK_OFFSET(host_ia32_perf_global_ctrl, 272);
 642         CHECK_OFFSET(vmread_bitmap, 280);
 643         CHECK_OFFSET(vmwrite_bitmap, 288);
 644         CHECK_OFFSET(vm_function_control, 296);
 645         CHECK_OFFSET(eptp_list_address, 304);
 646         CHECK_OFFSET(pml_address, 312);
 647         CHECK_OFFSET(cr0_guest_host_mask, 344);
 648         CHECK_OFFSET(cr4_guest_host_mask, 352);
 649         CHECK_OFFSET(cr0_read_shadow, 360);
 650         CHECK_OFFSET(cr4_read_shadow, 368);
 651         CHECK_OFFSET(cr3_target_value0, 376);
 652         CHECK_OFFSET(cr3_target_value1, 384);
 653         CHECK_OFFSET(cr3_target_value2, 392);
 654         CHECK_OFFSET(cr3_target_value3, 400);
 655         CHECK_OFFSET(exit_qualification, 408);
 656         CHECK_OFFSET(guest_linear_address, 416);
 657         CHECK_OFFSET(guest_cr0, 424);
 658         CHECK_OFFSET(guest_cr3, 432);
 659         CHECK_OFFSET(guest_cr4, 440);
 660         CHECK_OFFSET(guest_es_base, 448);
 661         CHECK_OFFSET(guest_cs_base, 456);
 662         CHECK_OFFSET(guest_ss_base, 464);
 663         CHECK_OFFSET(guest_ds_base, 472);
 664         CHECK_OFFSET(guest_fs_base, 480);
 665         CHECK_OFFSET(guest_gs_base, 488);
 666         CHECK_OFFSET(guest_ldtr_base, 496);
 667         CHECK_OFFSET(guest_tr_base, 504);
 668         CHECK_OFFSET(guest_gdtr_base, 512);
 669         CHECK_OFFSET(guest_idtr_base, 520);
 670         CHECK_OFFSET(guest_dr7, 528);
 671         CHECK_OFFSET(guest_rsp, 536);
 672         CHECK_OFFSET(guest_rip, 544);
 673         CHECK_OFFSET(guest_rflags, 552);
 674         CHECK_OFFSET(guest_pending_dbg_exceptions, 560);
 675         CHECK_OFFSET(guest_sysenter_esp, 568);
 676         CHECK_OFFSET(guest_sysenter_eip, 576);
 677         CHECK_OFFSET(host_cr0, 584);
 678         CHECK_OFFSET(host_cr3, 592);
 679         CHECK_OFFSET(host_cr4, 600);
 680         CHECK_OFFSET(host_fs_base, 608);
 681         CHECK_OFFSET(host_gs_base, 616);
 682         CHECK_OFFSET(host_tr_base, 624);
 683         CHECK_OFFSET(host_gdtr_base, 632);
 684         CHECK_OFFSET(host_idtr_base, 640);
 685         CHECK_OFFSET(host_ia32_sysenter_esp, 648);
 686         CHECK_OFFSET(host_ia32_sysenter_eip, 656);
 687         CHECK_OFFSET(host_rsp, 664);
 688         CHECK_OFFSET(host_rip, 672);
 689         CHECK_OFFSET(pin_based_vm_exec_control, 744);
 690         CHECK_OFFSET(cpu_based_vm_exec_control, 748);
 691         CHECK_OFFSET(exception_bitmap, 752);
 692         CHECK_OFFSET(page_fault_error_code_mask, 756);
 693         CHECK_OFFSET(page_fault_error_code_match, 760);
 694         CHECK_OFFSET(cr3_target_count, 764);
 695         CHECK_OFFSET(vm_exit_controls, 768);
 696         CHECK_OFFSET(vm_exit_msr_store_count, 772);
 697         CHECK_OFFSET(vm_exit_msr_load_count, 776);
 698         CHECK_OFFSET(vm_entry_controls, 780);
 699         CHECK_OFFSET(vm_entry_msr_load_count, 784);
 700         CHECK_OFFSET(vm_entry_intr_info_field, 788);
 701         CHECK_OFFSET(vm_entry_exception_error_code, 792);
 702         CHECK_OFFSET(vm_entry_instruction_len, 796);
 703         CHECK_OFFSET(tpr_threshold, 800);
 704         CHECK_OFFSET(secondary_vm_exec_control, 804);
 705         CHECK_OFFSET(vm_instruction_error, 808);
 706         CHECK_OFFSET(vm_exit_reason, 812);
 707         CHECK_OFFSET(vm_exit_intr_info, 816);
 708         CHECK_OFFSET(vm_exit_intr_error_code, 820);
 709         CHECK_OFFSET(idt_vectoring_info_field, 824);
 710         CHECK_OFFSET(idt_vectoring_error_code, 828);
 711         CHECK_OFFSET(vm_exit_instruction_len, 832);
 712         CHECK_OFFSET(vmx_instruction_info, 836);
 713         CHECK_OFFSET(guest_es_limit, 840);
 714         CHECK_OFFSET(guest_cs_limit, 844);
 715         CHECK_OFFSET(guest_ss_limit, 848);
 716         CHECK_OFFSET(guest_ds_limit, 852);
 717         CHECK_OFFSET(guest_fs_limit, 856);
 718         CHECK_OFFSET(guest_gs_limit, 860);
 719         CHECK_OFFSET(guest_ldtr_limit, 864);
 720         CHECK_OFFSET(guest_tr_limit, 868);
 721         CHECK_OFFSET(guest_gdtr_limit, 872);
 722         CHECK_OFFSET(guest_idtr_limit, 876);
 723         CHECK_OFFSET(guest_es_ar_bytes, 880);
 724         CHECK_OFFSET(guest_cs_ar_bytes, 884);
 725         CHECK_OFFSET(guest_ss_ar_bytes, 888);
 726         CHECK_OFFSET(guest_ds_ar_bytes, 892);
 727         CHECK_OFFSET(guest_fs_ar_bytes, 896);
 728         CHECK_OFFSET(guest_gs_ar_bytes, 900);
 729         CHECK_OFFSET(guest_ldtr_ar_bytes, 904);
 730         CHECK_OFFSET(guest_tr_ar_bytes, 908);
 731         CHECK_OFFSET(guest_interruptibility_info, 912);
 732         CHECK_OFFSET(guest_activity_state, 916);
 733         CHECK_OFFSET(guest_sysenter_cs, 920);
 734         CHECK_OFFSET(host_ia32_sysenter_cs, 924);
 735         CHECK_OFFSET(vmx_preemption_timer_value, 928);
 736         CHECK_OFFSET(virtual_processor_id, 960);
 737         CHECK_OFFSET(posted_intr_nv, 962);
 738         CHECK_OFFSET(guest_es_selector, 964);
 739         CHECK_OFFSET(guest_cs_selector, 966);
 740         CHECK_OFFSET(guest_ss_selector, 968);
 741         CHECK_OFFSET(guest_ds_selector, 970);
 742         CHECK_OFFSET(guest_fs_selector, 972);
 743         CHECK_OFFSET(guest_gs_selector, 974);
 744         CHECK_OFFSET(guest_ldtr_selector, 976);
 745         CHECK_OFFSET(guest_tr_selector, 978);
 746         CHECK_OFFSET(guest_intr_status, 980);
 747         CHECK_OFFSET(host_es_selector, 982);
 748         CHECK_OFFSET(host_cs_selector, 984);
 749         CHECK_OFFSET(host_ss_selector, 986);
 750         CHECK_OFFSET(host_ds_selector, 988);
 751         CHECK_OFFSET(host_fs_selector, 990);
 752         CHECK_OFFSET(host_gs_selector, 992);
 753         CHECK_OFFSET(host_tr_selector, 994);
 754         CHECK_OFFSET(guest_pml_index, 996);
 755 }
 756
 757 /*
 758  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 759  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 760  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 761  *
 762  * IMPORTANT: Changing this value will break save/restore compatibility with
 763  * older kvm releases.
 764  */
 765 #define VMCS12_REVISION 0x11e57ed0
 766
 767 /*
 768  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 769  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 770  * current implementation, 4K are reserved to avoid future complications.
 771  */
 772 #define VMCS12_SIZE 0x1000
 773
 774 /*
 775  * VMCS12_MAX_FIELD_INDEX is the highest index value used in any
 776  * supported VMCS12 field encoding.
 777  */
 778 #define VMCS12_MAX_FIELD_INDEX 0x17
 779
 780 struct nested_vmx_msrs {
 781         /*
 782          * We only store the "true" versions of the VMX capability MSRs. We
 783          * generate the "non-true" versions by setting the must-be-1 bits
 784          * according to the SDM.
 785          */
 786         u32 procbased_ctls_low;
 787         u32 procbased_ctls_high;
 788         u32 secondary_ctls_low;
 789         u32 secondary_ctls_high;
 790         u32 pinbased_ctls_low;
 791         u32 pinbased_ctls_high;
 792         u32 exit_ctls_low;
 793         u32 exit_ctls_high;
 794         u32 entry_ctls_low;
 795         u32 entry_ctls_high;
 796         u32 misc_low;
 797         u32 misc_high;
 798         u32 ept_caps;
 799         u32 vpid_caps;
 800         u64 basic;
 801         u64 cr0_fixed0;
 802         u64 cr0_fixed1;
 803         u64 cr4_fixed0;
 804         u64 cr4_fixed1;
 805         u64 vmcs_enum;
 806         u64 vmfunc_controls;
 807 };
 808
 809 /*
 810  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 811  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 812  */
 813 struct nested_vmx {
 814         /* Has the level1 guest done vmxon? */
 815         bool vmxon;
 816         gpa_t vmxon_ptr;
 817         bool pml_full;
 818
 819         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 820         gpa_t current_vmptr;
 821         /*
 822          * Cache of the guest's VMCS, existing outside of guest memory.
 823          * Loaded from guest memory during VMPTRLD. Flushed to guest
 824          * memory during VMCLEAR and VMPTRLD.
 825          */
 826         struct vmcs12 *cached_vmcs12;
 827         /*
 828          * Cache of the guest's shadow VMCS, existing outside of guest
 829          * memory. Loaded from guest memory during VM entry. Flushed
 830          * to guest memory during VM exit.
 831          */
 832         struct vmcs12 *cached_shadow_vmcs12;
 833         /*
 834          * Indicates if the shadow vmcs must be updated with the
 835          * data hold by vmcs12
 836          */
 837         bool sync_shadow_vmcs;
 838         bool dirty_vmcs12;
 839
 840         /*
 841          * vmcs02 has been initialized, i.e. state that is constant for
 842          * vmcs02 has been written to the backing VMCS.  Initialization
 843          * is delayed until L1 actually attempts to run a nested VM.
 844          */
 845         bool vmcs02_initialized;
 846
 847         bool change_vmcs01_virtual_apic_mode;
 848
 849         /* L2 must run next, and mustn't decide to exit to L1. */
 850         bool nested_run_pending;
 851
 852         struct loaded_vmcs vmcs02;
 853
 854         /*
 855          * Guest pages referred to in the vmcs02 with host-physical
 856          * pointers, so we must keep them pinned while L2 runs.
 857          */
 858         struct page *apic_access_page;
 859         struct page *virtual_apic_page;
 860         struct page *pi_desc_page;
 861         struct pi_desc *pi_desc;
 862         bool pi_pending;
 863         u16 posted_intr_nv;
 864
 865         struct hrtimer preemption_timer;
 866         bool preemption_timer_expired;
 867
 868         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 869         u64 vmcs01_debugctl;
 870         u64 vmcs01_guest_bndcfgs;
 871
 872         u16 vpid02;
 873         u16 last_vpid;
 874
 875         struct nested_vmx_msrs msrs;
 876
 877         /* SMM related state */
 878         struct {
 879                 /* in VMX operation on SMM entry? */
 880                 bool vmxon;
 881                 /* in guest mode on SMM entry? */
 882                 bool guest_mode;
 883         } smm;
 884 };
 885
 886 #define POSTED_INTR_ON  0
 887 #define POSTED_INTR_SN  1
 888
 889 /* Posted-Interrupt Descriptor */
 890 struct pi_desc {
 891         u32 pir[8];     /* Posted interrupt requested */
 892         union {
 893                 struct {
 894                                 /* bit 256 - Outstanding Notification */
 895                         u16     on      : 1,
 896                                 /* bit 257 - Suppress Notification */
 897                                 sn      : 1,
 898                                 /* bit 271:258 - Reserved */
 899                                 rsvd_1  : 14;
 900                                 /* bit 279:272 - Notification Vector */
 901                         u8      nv;
 902                                 /* bit 287:280 - Reserved */
 903                         u8      rsvd_2;
 904                                 /* bit 319:288 - Notification Destination */
 905                         u32     ndst;
 906                 };
 907                 u64 control;
 908         };
 909         u32 rsvd[6];
 910 } __aligned(64);
 911
 912 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 913 {
 914         return test_and_set_bit(POSTED_INTR_ON,
 915                         (unsigned long *)&pi_desc->control);
 916 }
 917
 918 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 919 {
 920         return test_and_clear_bit(POSTED_INTR_ON,
 921                         (unsigned long *)&pi_desc->control);
 922 }
 923
 924 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 925 {
 926         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 927 }
 928
 929 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 930 {
 931         return clear_bit(POSTED_INTR_SN,
 932                         (unsigned long *)&pi_desc->control);
 933 }
 934
 935 static inline void pi_set_sn(struct pi_desc *pi_desc)
 936 {
 937         return set_bit(POSTED_INTR_SN,
 938                         (unsigned long *)&pi_desc->control);
 939 }
 940
 941 static inline void pi_clear_on(struct pi_desc *pi_desc)
 942 {
 943         clear_bit(POSTED_INTR_ON,
 944                   (unsigned long *)&pi_desc->control);
 945 }
 946
 947 static inline int pi_test_on(struct pi_desc *pi_desc)
 948 {
 949         return test_bit(POSTED_INTR_ON,
 950                         (unsigned long *)&pi_desc->control);
 951 }
 952
 953 static inline int pi_test_sn(struct pi_desc *pi_desc)
 954 {
 955         return test_bit(POSTED_INTR_SN,
 956                         (unsigned long *)&pi_desc->control);
 957 }
 958
 959 struct vmx_msrs {
 960         unsigned int            nr;
 961         struct vmx_msr_entry    val[NR_AUTOLOAD_MSRS];
 962 };
 963
 964 struct vcpu_vmx {
 965         struct kvm_vcpu       vcpu;
 966         unsigned long         host_rsp;
 967         u8                    fail;
 968         u8                    msr_bitmap_mode;
 969         u32                   exit_intr_info;
 970         u32                   idt_vectoring_info;
 971         ulong                 rflags;
 972         struct shared_msr_entry *guest_msrs;
 973         int                   nmsrs;
 974         int                   save_nmsrs;
 975         unsigned long         host_idt_base;
 976 #ifdef CONFIG_X86_64
 977         u64                   msr_host_kernel_gs_base;
 978         u64                   msr_guest_kernel_gs_base;
 979 #endif
 980
 981         u64                   arch_capabilities;
 982         u64                   spec_ctrl;
 983
 984         u32 vm_entry_controls_shadow;
 985         u32 vm_exit_controls_shadow;
 986         u32 secondary_exec_control;
 987
 988         /*
 989          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 990          * non-nested (L1) guest, it always points to vmcs01. For a nested
 991          * guest (L2), it points to a different VMCS.  loaded_cpu_state points
 992          * to the VMCS whose state is loaded into the CPU registers that only
 993          * need to be switched when transitioning to/from the kernel; a NULL
 994          * value indicates that host state is loaded.
 995          */
 996         struct loaded_vmcs    vmcs01;
 997         struct loaded_vmcs   *loaded_vmcs;
 998         struct loaded_vmcs   *loaded_cpu_state;
 999         bool                  __launched; /* temporary, used in vmx_vcpu_run */
1000         struct msr_autoload {
1001                 struct vmx_msrs guest;
1002                 struct vmx_msrs host;
1003         } msr_autoload;
1004
1005         struct {
1006                 int vm86_active;
1007                 ulong save_rflags;
1008                 struct kvm_segment segs[8];
1009         } rmode;
1010         struct {
1011                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
1012                 struct kvm_save_segment {
1013                         u16 selector;
1014                         unsigned long base;
1015                         u32 limit;
1016                         u32 ar;
1017                 } seg[8];
1018         } segment_cache;
1019         int vpid;
1020         bool emulation_required;
1021
1022         u32 exit_reason;
1023
1024         /* Posted interrupt descriptor */
1025         struct pi_desc pi_desc;
1026
1027         /* Support for a guest hypervisor (nested VMX) */
1028         struct nested_vmx nested;
1029
1030         /* Dynamic PLE window. */
1031         int ple_window;
1032         bool ple_window_dirty;
1033
1034         bool req_immediate_exit;
1035
1036         /* Support for PML */
1037 #define PML_ENTITY_NUM          512
1038         struct page *pml_pg;
1039
1040         /* apic deadline value in host tsc */
1041         u64 hv_deadline_tsc;
1042
1043         u64 current_tsc_ratio;
1044
1045         u32 host_pkru;
1046
1047         unsigned long host_debugctlmsr;
1048
1049         /*
1050          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
1051          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
1052          * in msr_ia32_feature_control_valid_bits.
1053          */
1054         u64 msr_ia32_feature_control;
1055         u64 msr_ia32_feature_control_valid_bits;
1056         u64 ept_pointer;
1057 };
1058
1059 enum segment_cache_field {
1060         SEG_FIELD_SEL = 0,
1061         SEG_FIELD_BASE = 1,
1062         SEG_FIELD_LIMIT = 2,
1063         SEG_FIELD_AR = 3,
1064
1065         SEG_FIELD_NR = 4
1066 };
1067
1068 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
1069 {
1070         return container_of(kvm, struct kvm_vmx, kvm);
1071 }
1072
1073 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
1074 {
1075         return container_of(vcpu, struct vcpu_vmx, vcpu);
1076 }
1077
1078 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
1079 {
1080         return &(to_vmx(vcpu)->pi_desc);
1081 }
1082
1083 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
1084 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
1085 #define FIELD(number, name)     [ROL16(number, 6)] = VMCS12_OFFSET(name)
1086 #define FIELD64(number, name)                                           \
1087         FIELD(number, name),                                            \
1088         [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
1089
1090
1091 static u16 shadow_read_only_fields[] = {
1092 #define SHADOW_FIELD_RO(x) x,
1093 #include "vmx_shadow_fields.h"
1094 };
1095 static int max_shadow_read_only_fields =
1096         ARRAY_SIZE(shadow_read_only_fields);
1097
1098 static u16 shadow_read_write_fields[] = {
1099 #define SHADOW_FIELD_RW(x) x,
1100 #include "vmx_shadow_fields.h"
1101 };
1102 static int max_shadow_read_write_fields =
1103         ARRAY_SIZE(shadow_read_write_fields);
1104
1105 static const unsigned short vmcs_field_to_offset_table[] = {
1106         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
1107         FIELD(POSTED_INTR_NV, posted_intr_nv),
1108         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
1109         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
1110         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
1111         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
1112         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
1113         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
1114         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
1115         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
1116         FIELD(GUEST_INTR_STATUS, guest_intr_status),
1117         FIELD(GUEST_PML_INDEX, guest_pml_index),
1118         FIELD(HOST_ES_SELECTOR, host_es_selector),
1119         FIELD(HOST_CS_SELECTOR, host_cs_selector),
1120         FIELD(HOST_SS_SELECTOR, host_ss_selector),
1121         FIELD(HOST_DS_SELECTOR, host_ds_selector),
1122         FIELD(HOST_FS_SELECTOR, host_fs_selector),
1123         FIELD(HOST_GS_SELECTOR, host_gs_selector),
1124         FIELD(HOST_TR_SELECTOR, host_tr_selector),
1125         FIELD64(IO_BITMAP_A, io_bitmap_a),
1126         FIELD64(IO_BITMAP_B, io_bitmap_b),
1127         FIELD64(MSR_BITMAP, msr_bitmap),
1128         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
1129         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
1130         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
1131         FIELD64(PML_ADDRESS, pml_address),
1132         FIELD64(TSC_OFFSET, tsc_offset),
1133         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
1134         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
1135         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
1136         FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
1137         FIELD64(EPT_POINTER, ept_pointer),
1138         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
1139         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
1140         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
1141         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
1142         FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
1143         FIELD64(VMREAD_BITMAP, vmread_bitmap),
1144         FIELD64(VMWRITE_BITMAP, vmwrite_bitmap),
1145         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
1146         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
1147         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
1148         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
1149         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
1150         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
1151         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
1152         FIELD64(GUEST_PDPTR0, guest_pdptr0),
1153         FIELD64(GUEST_PDPTR1, guest_pdptr1),
1154         FIELD64(GUEST_PDPTR2, guest_pdptr2),
1155         FIELD64(GUEST_PDPTR3, guest_pdptr3),
1156         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
1157         FIELD64(HOST_IA32_PAT, host_ia32_pat),
1158         FIELD64(HOST_IA32_EFER, host_ia32_efer),
1159         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
1160         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
1161         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
1162         FIELD(EXCEPTION_BITMAP, exception_bitmap),
1163         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
1164         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
1165         FIELD(CR3_TARGET_COUNT, cr3_target_count),
1166         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
1167         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
1168         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
1169         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
1170         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
1171         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
1172         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
1173         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
1174         FIELD(TPR_THRESHOLD, tpr_threshold),
1175         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
1176         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
1177         FIELD(VM_EXIT_REASON, vm_exit_reason),
1178         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
1179         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
1180         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
1181         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
1182         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
1183         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
1184         FIELD(GUEST_ES_LIMIT, guest_es_limit),
1185         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
1186         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
1187         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
1188         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
1189         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
1190         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
1191         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
1192         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
1193         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
1194         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
1195         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
1196         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
1197         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
1198         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
1199         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
1200         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
1201         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
1202         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
1203         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
1204         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
1205         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
1206         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
1207         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
1208         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
1209         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
1210         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
1211         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
1212         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
1213         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
1214         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
1215         FIELD(EXIT_QUALIFICATION, exit_qualification),
1216         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
1217         FIELD(GUEST_CR0, guest_cr0),
1218         FIELD(GUEST_CR3, guest_cr3),
1219         FIELD(GUEST_CR4, guest_cr4),
1220         FIELD(GUEST_ES_BASE, guest_es_base),
1221         FIELD(GUEST_CS_BASE, guest_cs_base),
1222         FIELD(GUEST_SS_BASE, guest_ss_base),
1223         FIELD(GUEST_DS_BASE, guest_ds_base),
1224         FIELD(GUEST_FS_BASE, guest_fs_base),
1225         FIELD(GUEST_GS_BASE, guest_gs_base),
1226         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
1227         FIELD(GUEST_TR_BASE, guest_tr_base),
1228         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
1229         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
1230         FIELD(GUEST_DR7, guest_dr7),
1231         FIELD(GUEST_RSP, guest_rsp),
1232         FIELD(GUEST_RIP, guest_rip),
1233         FIELD(GUEST_RFLAGS, guest_rflags),
1234         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
1235         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
1236         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
1237         FIELD(HOST_CR0, host_cr0),
1238         FIELD(HOST_CR3, host_cr3),
1239         FIELD(HOST_CR4, host_cr4),
1240         FIELD(HOST_FS_BASE, host_fs_base),
1241         FIELD(HOST_GS_BASE, host_gs_base),
1242         FIELD(HOST_TR_BASE, host_tr_base),
1243         FIELD(HOST_GDTR_BASE, host_gdtr_base),
1244         FIELD(HOST_IDTR_BASE, host_idtr_base),
1245         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
1246         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
1247         FIELD(HOST_RSP, host_rsp),
1248         FIELD(HOST_RIP, host_rip),
1249 };
1250
1251 static inline short vmcs_field_to_offset(unsigned long field)
1252 {
1253         const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
1254         unsigned short offset;
1255         unsigned index;
1256
1257         if (field >> 15)
1258                 return -ENOENT;
1259
1260         index = ROL16(field, 6);
1261         if (index >= size)
1262                 return -ENOENT;
1263
1264         index = array_index_nospec(index, size);
1265         offset = vmcs_field_to_offset_table[index];
1266         if (offset == 0)
1267                 return -ENOENT;
1268         return offset;
1269 }
1270
1271 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
1272 {
1273         return to_vmx(vcpu)->nested.cached_vmcs12;
1274 }
1275
1276 static inline struct vmcs12 *get_shadow_vmcs12(struct kvm_vcpu *vcpu)
1277 {
1278         return to_vmx(vcpu)->nested.cached_shadow_vmcs12;
1279 }
1280
1281 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
1282 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
1283 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
1284 static bool vmx_xsaves_supported(void);
1285 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1286                             struct kvm_segment *var, int seg);
1287 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1288                             struct kvm_segment *var, int seg);
1289 static bool guest_state_valid(struct kvm_vcpu *vcpu);
1290 static u32 vmx_segment_access_rights(struct kvm_segment *var);
1291 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
1292 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
1293 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
1294 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
1295                                             u16 error_code);
1296 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
1297 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
1298                                                           u32 msr, int type);
1299
1300 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
1301 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
1302 /*
1303  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
1304  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
1305  */
1306 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
1307
1308 /*
1309  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
1310  * can find which vCPU should be waken up.
1311  */
1312 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
1313 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
1314
1315 enum {
1316         VMX_VMREAD_BITMAP,
1317         VMX_VMWRITE_BITMAP,
1318         VMX_BITMAP_NR
1319 };
1320
1321 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
1322
1323 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
1324 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
1325
1326 static bool cpu_has_load_ia32_efer;
1327 static bool cpu_has_load_perf_global_ctrl;
1328
1329 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
1330 static DEFINE_SPINLOCK(vmx_vpid_lock);
1331
1332 static struct vmcs_config {
1333         int size;
1334         int order;
1335         u32 basic_cap;
1336         u32 revision_id;
1337         u32 pin_based_exec_ctrl;
1338         u32 cpu_based_exec_ctrl;
1339         u32 cpu_based_2nd_exec_ctrl;
1340         u32 vmexit_ctrl;
1341         u32 vmentry_ctrl;
1342         struct nested_vmx_msrs nested;
1343 } vmcs_config;
1344
1345 static struct vmx_capability {
1346         u32 ept;
1347         u32 vpid;
1348 } vmx_capability;
1349
1350 #define VMX_SEGMENT_FIELD(seg)                                  \
1351         [VCPU_SREG_##seg] = {                                   \
1352                 .selector = GUEST_##seg##_SELECTOR,             \
1353                 .base = GUEST_##seg##_BASE,                     \
1354                 .limit = GUEST_##seg##_LIMIT,                   \
1355                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1356         }
1357
1358 static const struct kvm_vmx_segment_field {
1359         unsigned selector;
1360         unsigned base;
1361         unsigned limit;
1362         unsigned ar_bytes;
1363 } kvm_vmx_segment_fields[] = {
1364         VMX_SEGMENT_FIELD(CS),
1365         VMX_SEGMENT_FIELD(DS),
1366         VMX_SEGMENT_FIELD(ES),
1367         VMX_SEGMENT_FIELD(FS),
1368         VMX_SEGMENT_FIELD(GS),
1369         VMX_SEGMENT_FIELD(SS),
1370         VMX_SEGMENT_FIELD(TR),
1371         VMX_SEGMENT_FIELD(LDTR),
1372 };
1373
1374 static u64 host_efer;
1375
1376 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1377
1378 /*
1379  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1380  * away by decrementing the array size.
1381  */
1382 static const u32 vmx_msr_index[] = {
1383 #ifdef CONFIG_X86_64
1384         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1385 #endif
1386         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1387 };
1388
1389 DEFINE_STATIC_KEY_FALSE(enable_evmcs);
1390
1391 #define current_evmcs ((struct hv_enlightened_vmcs *)this_cpu_read(current_vmcs))
1392
1393 #define KVM_EVMCS_VERSION 1
1394
1395 #if IS_ENABLED(CONFIG_HYPERV)
1396 static bool __read_mostly enlightened_vmcs = true;
1397 module_param(enlightened_vmcs, bool, 0444);
1398
1399 static inline void evmcs_write64(unsigned long field, u64 value)
1400 {
1401         u16 clean_field;
1402         int offset = get_evmcs_offset(field, &clean_field);
1403
1404         if (offset < 0)
1405                 return;
1406
1407         *(u64 *)((char *)current_evmcs + offset) = value;
1408
1409         current_evmcs->hv_clean_fields &= ~clean_field;
1410 }
1411
1412 static inline void evmcs_write32(unsigned long field, u32 value)
1413 {
1414         u16 clean_field;
1415         int offset = get_evmcs_offset(field, &clean_field);
1416
1417         if (offset < 0)
1418                 return;
1419
1420         *(u32 *)((char *)current_evmcs + offset) = value;
1421         current_evmcs->hv_clean_fields &= ~clean_field;
1422 }
1423
1424 static inline void evmcs_write16(unsigned long field, u16 value)
1425 {
1426         u16 clean_field;
1427         int offset = get_evmcs_offset(field, &clean_field);
1428
1429         if (offset < 0)
1430                 return;
1431
1432         *(u16 *)((char *)current_evmcs + offset) = value;
1433         current_evmcs->hv_clean_fields &= ~clean_field;
1434 }
1435
1436 static inline u64 evmcs_read64(unsigned long field)
1437 {
1438         int offset = get_evmcs_offset(field, NULL);
1439
1440         if (offset < 0)
1441                 return 0;
1442
1443         return *(u64 *)((char *)current_evmcs + offset);
1444 }
1445
1446 static inline u32 evmcs_read32(unsigned long field)
1447 {
1448         int offset = get_evmcs_offset(field, NULL);
1449
1450         if (offset < 0)
1451                 return 0;
1452
1453         return *(u32 *)((char *)current_evmcs + offset);
1454 }
1455
1456 static inline u16 evmcs_read16(unsigned long field)
1457 {
1458         int offset = get_evmcs_offset(field, NULL);
1459
1460         if (offset < 0)
1461                 return 0;
1462
1463         return *(u16 *)((char *)current_evmcs + offset);
1464 }
1465
1466 static inline void evmcs_touch_msr_bitmap(void)
1467 {
1468         if (unlikely(!current_evmcs))
1469                 return;
1470
1471         if (current_evmcs->hv_enlightenments_control.msr_bitmap)
1472                 current_evmcs->hv_clean_fields &=
1473                         ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP;
1474 }
1475
1476 static void evmcs_load(u64 phys_addr)
1477 {
1478         struct hv_vp_assist_page *vp_ap =
1479                 hv_get_vp_assist_page(smp_processor_id());
1480
1481         vp_ap->current_nested_vmcs = phys_addr;
1482         vp_ap->enlighten_vmentry = 1;
1483 }
1484
1485 static void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf)
1486 {
1487         /*
1488          * Enlightened VMCSv1 doesn't support these:
1489          *
1490          *      POSTED_INTR_NV                  = 0x00000002,
1491          *      GUEST_INTR_STATUS               = 0x00000810,
1492          *      APIC_ACCESS_ADDR                = 0x00002014,
1493          *      POSTED_INTR_DESC_ADDR           = 0x00002016,
1494          *      EOI_EXIT_BITMAP0                = 0x0000201c,
1495          *      EOI_EXIT_BITMAP1                = 0x0000201e,
1496          *      EOI_EXIT_BITMAP2                = 0x00002020,
1497          *      EOI_EXIT_BITMAP3                = 0x00002022,
1498          */
1499         vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
1500         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1501                 ~SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1502         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1503                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1504         vmcs_conf->cpu_based_2nd_exec_ctrl &=
1505                 ~SECONDARY_EXEC_APIC_REGISTER_VIRT;
1506
1507         /*
1508          *      GUEST_PML_INDEX                 = 0x00000812,
1509          *      PML_ADDRESS                     = 0x0000200e,
1510          */
1511         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_PML;
1512
1513         /*      VM_FUNCTION_CONTROL             = 0x00002018, */
1514         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_VMFUNC;
1515
1516         /*
1517          *      EPTP_LIST_ADDRESS               = 0x00002024,
1518          *      VMREAD_BITMAP                   = 0x00002026,
1519          *      VMWRITE_BITMAP                  = 0x00002028,
1520          */
1521         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_SHADOW_VMCS;
1522
1523         /*
1524          *      TSC_MULTIPLIER                  = 0x00002032,
1525          */
1526         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_TSC_SCALING;
1527
1528         /*
1529          *      PLE_GAP                         = 0x00004020,
1530          *      PLE_WINDOW                      = 0x00004022,
1531          */
1532         vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1533
1534         /*
1535          *      VMX_PREEMPTION_TIMER_VALUE      = 0x0000482E,
1536          */
1537         vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
1538
1539         /*
1540          *      GUEST_IA32_PERF_GLOBAL_CTRL     = 0x00002808,
1541          *      HOST_IA32_PERF_GLOBAL_CTRL      = 0x00002c04,
1542          */
1543         vmcs_conf->vmexit_ctrl &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
1544         vmcs_conf->vmentry_ctrl &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
1545
1546         /*
1547          * Currently unsupported in KVM:
1548          *      GUEST_IA32_RTIT_CTL             = 0x00002814,
1549          */
1550 }
1551
1552 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
1553 static void check_ept_pointer_match(struct kvm *kvm)
1554 {
1555         struct kvm_vcpu *vcpu;
1556         u64 tmp_eptp = INVALID_PAGE;
1557         int i;
1558
1559         kvm_for_each_vcpu(i, vcpu, kvm) {
1560                 if (!VALID_PAGE(tmp_eptp)) {
1561                         tmp_eptp = to_vmx(vcpu)->ept_pointer;
1562                 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
1563                         to_kvm_vmx(kvm)->ept_pointers_match
1564                                 = EPT_POINTERS_MISMATCH;
1565                         return;
1566                 }
1567         }
1568
1569         to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
1570 }
1571
1572 static int vmx_hv_remote_flush_tlb(struct kvm *kvm)
1573 {
1574         int ret;
1575
1576         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
1577
1578         if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
1579                 check_ept_pointer_match(kvm);
1580
1581         if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
1582                 ret = -ENOTSUPP;
1583                 goto out;
1584         }
1585
1586         ret = hyperv_flush_guest_mapping(
1587                         to_vmx(kvm_get_vcpu(kvm, 0))->ept_pointer);
1588
1589 out:
1590         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
1591         return ret;
1592 }
1593 #else /* !IS_ENABLED(CONFIG_HYPERV) */
1594 static inline void evmcs_write64(unsigned long field, u64 value) {}
1595 static inline void evmcs_write32(unsigned long field, u32 value) {}
1596 static inline void evmcs_write16(unsigned long field, u16 value) {}
1597 static inline u64 evmcs_read64(unsigned long field) { return 0; }
1598 static inline u32 evmcs_read32(unsigned long field) { return 0; }
1599 static inline u16 evmcs_read16(unsigned long field) { return 0; }
1600 static inline void evmcs_load(u64 phys_addr) {}
1601 static inline void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf) {}
1602 static inline void evmcs_touch_msr_bitmap(void) {}
1603 #endif /* IS_ENABLED(CONFIG_HYPERV) */
1604
1605 static inline bool is_exception_n(u32 intr_info, u8 vector)
1606 {
1607         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1608                              INTR_INFO_VALID_MASK)) ==
1609                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1610 }
1611
1612 static inline bool is_debug(u32 intr_info)
1613 {
1614         return is_exception_n(intr_info, DB_VECTOR);
1615 }
1616
1617 static inline bool is_breakpoint(u32 intr_info)
1618 {
1619         return is_exception_n(intr_info, BP_VECTOR);
1620 }
1621
1622 static inline bool is_page_fault(u32 intr_info)
1623 {
1624         return is_exception_n(intr_info, PF_VECTOR);
1625 }
1626
1627 static inline bool is_invalid_opcode(u32 intr_info)
1628 {
1629         return is_exception_n(intr_info, UD_VECTOR);
1630 }
1631
1632 static inline bool is_gp_fault(u32 intr_info)
1633 {
1634         return is_exception_n(intr_info, GP_VECTOR);
1635 }
1636
1637 static inline bool is_machine_check(u32 intr_info)
1638 {
1639         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1640                              INTR_INFO_VALID_MASK)) ==
1641                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1642 }
1643
1644 /* Undocumented: icebp/int1 */
1645 static inline bool is_icebp(u32 intr_info)
1646 {
1647         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1648                 == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
1649 }
1650
1651 static inline bool cpu_has_vmx_msr_bitmap(void)
1652 {
1653         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1654 }
1655
1656 static inline bool cpu_has_vmx_tpr_shadow(void)
1657 {
1658         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1659 }
1660
1661 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1662 {
1663         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1664 }
1665
1666 static inline bool cpu_has_secondary_exec_ctrls(void)
1667 {
1668         return vmcs_config.cpu_based_exec_ctrl &
1669                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1670 }
1671
1672 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1673 {
1674         return vmcs_config.cpu_based_2nd_exec_ctrl &
1675                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1676 }
1677
1678 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1679 {
1680         return vmcs_config.cpu_based_2nd_exec_ctrl &
1681                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1682 }
1683
1684 static inline bool cpu_has_vmx_apic_register_virt(void)
1685 {
1686         return vmcs_config.cpu_based_2nd_exec_ctrl &
1687                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1688 }
1689
1690 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1691 {
1692         return vmcs_config.cpu_based_2nd_exec_ctrl &
1693                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1694 }
1695
1696 static inline bool cpu_has_vmx_encls_vmexit(void)
1697 {
1698         return vmcs_config.cpu_based_2nd_exec_ctrl &
1699                 SECONDARY_EXEC_ENCLS_EXITING;
1700 }
1701
1702 /*
1703  * Comment's format: document - errata name - stepping - processor name.
1704  * Refer from
1705  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1706  */
1707 static u32 vmx_preemption_cpu_tfms[] = {
1708 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1709 0x000206E6,
1710 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1711 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1712 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1713 0x00020652,
1714 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1715 0x00020655,
1716 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1717 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1718 /*
1719  * 320767.pdf - AAP86  - B1 -
1720  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1721  */
1722 0x000106E5,
1723 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1724 0x000106A0,
1725 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1726 0x000106A1,
1727 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1728 0x000106A4,
1729  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1730  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1731  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1732 0x000106A5,
1733 };
1734
1735 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1736 {
1737         u32 eax = cpuid_eax(0x00000001), i;
1738
1739         /* Clear the reserved bits */
1740         eax &= ~(0x3U << 14 | 0xfU << 28);
1741         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1742                 if (eax == vmx_preemption_cpu_tfms[i])
1743                         return true;
1744
1745         return false;
1746 }
1747
1748 static inline bool cpu_has_vmx_preemption_timer(void)
1749 {
1750         return vmcs_config.pin_based_exec_ctrl &
1751                 PIN_BASED_VMX_PREEMPTION_TIMER;
1752 }
1753
1754 static inline bool cpu_has_vmx_posted_intr(void)
1755 {
1756         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1757                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1758 }
1759
1760 static inline bool cpu_has_vmx_apicv(void)
1761 {
1762         return cpu_has_vmx_apic_register_virt() &&
1763                 cpu_has_vmx_virtual_intr_delivery() &&
1764                 cpu_has_vmx_posted_intr();
1765 }
1766
1767 static inline bool cpu_has_vmx_flexpriority(void)
1768 {
1769         return cpu_has_vmx_tpr_shadow() &&
1770                 cpu_has_vmx_virtualize_apic_accesses();
1771 }
1772
1773 static inline bool cpu_has_vmx_ept_execute_only(void)
1774 {
1775         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1776 }
1777
1778 static inline bool cpu_has_vmx_ept_2m_page(void)
1779 {
1780         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1781 }
1782
1783 static inline bool cpu_has_vmx_ept_1g_page(void)
1784 {
1785         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1786 }
1787
1788 static inline bool cpu_has_vmx_ept_4levels(void)
1789 {
1790         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1791 }
1792
1793 static inline bool cpu_has_vmx_ept_mt_wb(void)
1794 {
1795         return vmx_capability.ept & VMX_EPTP_WB_BIT;
1796 }
1797
1798 static inline bool cpu_has_vmx_ept_5levels(void)
1799 {
1800         return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1801 }
1802
1803 static inline bool cpu_has_vmx_ept_ad_bits(void)
1804 {
1805         return vmx_capability.ept & VMX_EPT_AD_BIT;
1806 }
1807
1808 static inline bool cpu_has_vmx_invept_context(void)
1809 {
1810         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1811 }
1812
1813 static inline bool cpu_has_vmx_invept_global(void)
1814 {
1815         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1816 }
1817
1818 static inline bool cpu_has_vmx_invvpid_individual_addr(void)
1819 {
1820         return vmx_capability.vpid & VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT;
1821 }
1822
1823 static inline bool cpu_has_vmx_invvpid_single(void)
1824 {
1825         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1826 }
1827
1828 static inline bool cpu_has_vmx_invvpid_global(void)
1829 {
1830         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1831 }
1832
1833 static inline bool cpu_has_vmx_invvpid(void)
1834 {
1835         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1836 }
1837
1838 static inline bool cpu_has_vmx_ept(void)
1839 {
1840         return vmcs_config.cpu_based_2nd_exec_ctrl &
1841                 SECONDARY_EXEC_ENABLE_EPT;
1842 }
1843
1844 static inline bool cpu_has_vmx_unrestricted_guest(void)
1845 {
1846         return vmcs_config.cpu_based_2nd_exec_ctrl &
1847                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1848 }
1849
1850 static inline bool cpu_has_vmx_ple(void)
1851 {
1852         return vmcs_config.cpu_based_2nd_exec_ctrl &
1853                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1854 }
1855
1856 static inline bool cpu_has_vmx_basic_inout(void)
1857 {
1858         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1859 }
1860
1861 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1862 {
1863         return flexpriority_enabled && lapic_in_kernel(vcpu);
1864 }
1865
1866 static inline bool cpu_has_vmx_vpid(void)
1867 {
1868         return vmcs_config.cpu_based_2nd_exec_ctrl &
1869                 SECONDARY_EXEC_ENABLE_VPID;
1870 }
1871
1872 static inline bool cpu_has_vmx_rdtscp(void)
1873 {
1874         return vmcs_config.cpu_based_2nd_exec_ctrl &
1875                 SECONDARY_EXEC_RDTSCP;
1876 }
1877
1878 static inline bool cpu_has_vmx_invpcid(void)
1879 {
1880         return vmcs_config.cpu_based_2nd_exec_ctrl &
1881                 SECONDARY_EXEC_ENABLE_INVPCID;
1882 }
1883
1884 static inline bool cpu_has_virtual_nmis(void)
1885 {
1886         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1887 }
1888
1889 static inline bool cpu_has_vmx_wbinvd_exit(void)
1890 {
1891         return vmcs_config.cpu_based_2nd_exec_ctrl &
1892                 SECONDARY_EXEC_WBINVD_EXITING;
1893 }
1894
1895 static inline bool cpu_has_vmx_shadow_vmcs(void)
1896 {
1897         u64 vmx_msr;
1898         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1899         /* check if the cpu supports writing r/o exit information fields */
1900         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1901                 return false;
1902
1903         return vmcs_config.cpu_based_2nd_exec_ctrl &
1904                 SECONDARY_EXEC_SHADOW_VMCS;
1905 }
1906
1907 static inline bool cpu_has_vmx_pml(void)
1908 {
1909         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1910 }
1911
1912 static inline bool cpu_has_vmx_tsc_scaling(void)
1913 {
1914         return vmcs_config.cpu_based_2nd_exec_ctrl &
1915                 SECONDARY_EXEC_TSC_SCALING;
1916 }
1917
1918 static inline bool cpu_has_vmx_vmfunc(void)
1919 {
1920         return vmcs_config.cpu_based_2nd_exec_ctrl &
1921                 SECONDARY_EXEC_ENABLE_VMFUNC;
1922 }
1923
1924 static bool vmx_umip_emulated(void)
1925 {
1926         return vmcs_config.cpu_based_2nd_exec_ctrl &
1927                 SECONDARY_EXEC_DESC;
1928 }
1929
1930 static inline bool report_flexpriority(void)
1931 {
1932         return flexpriority_enabled;
1933 }
1934
1935 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1936 {
1937         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low);
1938 }
1939
1940 /*
1941  * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE
1942  * to modify any valid field of the VMCS, or are the VM-exit
1943  * information fields read-only?
1944  */
1945 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu)
1946 {
1947         return to_vmx(vcpu)->nested.msrs.misc_low &
1948                 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS;
1949 }
1950
1951 static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu)
1952 {
1953         return to_vmx(vcpu)->nested.msrs.misc_low & VMX_MISC_ZERO_LEN_INS;
1954 }
1955
1956 static inline bool nested_cpu_supports_monitor_trap_flag(struct kvm_vcpu *vcpu)
1957 {
1958         return to_vmx(vcpu)->nested.msrs.procbased_ctls_high &
1959                         CPU_BASED_MONITOR_TRAP_FLAG;
1960 }
1961
1962 static inline bool nested_cpu_has_vmx_shadow_vmcs(struct kvm_vcpu *vcpu)
1963 {
1964         return to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
1965                 SECONDARY_EXEC_SHADOW_VMCS;
1966 }
1967
1968 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1969 {
1970         return vmcs12->cpu_based_vm_exec_control & bit;
1971 }
1972
1973 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1974 {
1975         return (vmcs12->cpu_based_vm_exec_control &
1976                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1977                 (vmcs12->secondary_vm_exec_control & bit);
1978 }
1979
1980 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1981 {
1982         return vmcs12->pin_based_vm_exec_control &
1983                 PIN_BASED_VMX_PREEMPTION_TIMER;
1984 }
1985
1986 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12)
1987 {
1988         return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING;
1989 }
1990
1991 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1992 {
1993         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1994 }
1995
1996 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1997 {
1998         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1999 }
2000
2001 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
2002 {
2003         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
2004 }
2005
2006 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
2007 {
2008         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
2009 }
2010
2011 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
2012 {
2013         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
2014 }
2015
2016 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
2017 {
2018         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
2019 }
2020
2021 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
2022 {
2023         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
2024 }
2025
2026 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
2027 {
2028         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2029 }
2030
2031 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
2032 {
2033         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
2034 }
2035
2036 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
2037 {
2038         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
2039 }
2040
2041 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
2042 {
2043         return nested_cpu_has_vmfunc(vmcs12) &&
2044                 (vmcs12->vm_function_control &
2045                  VMX_VMFUNC_EPTP_SWITCHING);
2046 }
2047
2048 static inline bool nested_cpu_has_shadow_vmcs(struct vmcs12 *vmcs12)
2049 {
2050         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS);
2051 }
2052
2053 static inline bool is_nmi(u32 intr_info)
2054 {
2055         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
2056                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
2057 }
2058
2059 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
2060                               u32 exit_intr_info,
2061                               unsigned long exit_qualification);
2062
2063 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
2064 {
2065         int i;
2066
2067         for (i = 0; i < vmx->nmsrs; ++i)
2068                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
2069                         return i;
2070         return -1;
2071 }
2072
2073 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
2074 {
2075     struct {
2076         u64 vpid : 16;
2077         u64 rsvd : 48;
2078         u64 gva;
2079     } operand = { vpid, 0, gva };
2080     bool error;
2081
2082     asm volatile (__ex(ASM_VMX_INVVPID) CC_SET(na)
2083                   : CC_OUT(na) (error) : "a"(&operand), "c"(ext)
2084                   : "memory");
2085     BUG_ON(error);
2086 }
2087
2088 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
2089 {
2090         struct {
2091                 u64 eptp, gpa;
2092         } operand = {eptp, gpa};
2093         bool error;
2094
2095         asm volatile (__ex(ASM_VMX_INVEPT) CC_SET(na)
2096                       : CC_OUT(na) (error) : "a" (&operand), "c" (ext)
2097                       : "memory");
2098         BUG_ON(error);
2099 }
2100
2101 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
2102 {
2103         int i;
2104
2105         i = __find_msr_index(vmx, msr);
2106         if (i >= 0)
2107                 return &vmx->guest_msrs[i];
2108         return NULL;
2109 }
2110
2111 static void vmcs_clear(struct vmcs *vmcs)
2112 {
2113         u64 phys_addr = __pa(vmcs);
2114         bool error;
2115
2116         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) CC_SET(na)
2117                       : CC_OUT(na) (error) : "a"(&phys_addr), "m"(phys_addr)
2118                       : "memory");
2119         if (unlikely(error))
2120                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
2121                        vmcs, phys_addr);
2122 }
2123
2124 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
2125 {
2126         vmcs_clear(loaded_vmcs->vmcs);
2127         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
2128                 vmcs_clear(loaded_vmcs->shadow_vmcs);
2129         loaded_vmcs->cpu = -1;
2130         loaded_vmcs->launched = 0;
2131 }
2132
2133 static void vmcs_load(struct vmcs *vmcs)
2134 {
2135         u64 phys_addr = __pa(vmcs);
2136         bool error;
2137
2138         if (static_branch_unlikely(&enable_evmcs))
2139                 return evmcs_load(phys_addr);
2140
2141         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) CC_SET(na)
2142                       : CC_OUT(na) (error) : "a"(&phys_addr), "m"(phys_addr)
2143                       : "memory");
2144         if (unlikely(error))
2145                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
2146                        vmcs, phys_addr);
2147 }
2148
2149 #ifdef CONFIG_KEXEC_CORE
2150 /*
2151  * This bitmap is used to indicate whether the vmclear
2152  * operation is enabled on all cpus. All disabled by
2153  * default.
2154  */
2155 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
2156
2157 static inline void crash_enable_local_vmclear(int cpu)
2158 {
2159         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
2160 }
2161
2162 static inline void crash_disable_local_vmclear(int cpu)
2163 {
2164         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
2165 }
2166
2167 static inline int crash_local_vmclear_enabled(int cpu)
2168 {
2169         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
2170 }
2171
2172 static void crash_vmclear_local_loaded_vmcss(void)
2173 {
2174         int cpu = raw_smp_processor_id();
2175         struct loaded_vmcs *v;
2176
2177         if (!crash_local_vmclear_enabled(cpu))
2178                 return;
2179
2180         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
2181                             loaded_vmcss_on_cpu_link)
2182                 vmcs_clear(v->vmcs);
2183 }
2184 #else
2185 static inline void crash_enable_local_vmclear(int cpu) { }
2186 static inline void crash_disable_local_vmclear(int cpu) { }
2187 #endif /* CONFIG_KEXEC_CORE */
2188
2189 static void __loaded_vmcs_clear(void *arg)
2190 {
2191         struct loaded_vmcs *loaded_vmcs = arg;
2192         int cpu = raw_smp_processor_id();
2193
2194         if (loaded_vmcs->cpu != cpu)
2195                 return; /* vcpu migration can race with cpu offline */
2196         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
2197                 per_cpu(current_vmcs, cpu) = NULL;
2198         crash_disable_local_vmclear(cpu);
2199         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
2200
2201         /*
2202          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
2203          * is before setting loaded_vmcs->vcpu to -1 which is done in
2204          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
2205          * then adds the vmcs into percpu list before it is deleted.
2206          */
2207         smp_wmb();
2208
2209         loaded_vmcs_init(loaded_vmcs);
2210         crash_enable_local_vmclear(cpu);
2211 }
2212
2213 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
2214 {
2215         int cpu = loaded_vmcs->cpu;
2216
2217         if (cpu != -1)
2218                 smp_call_function_single(cpu,
2219                          __loaded_vmcs_clear, loaded_vmcs, 1);
2220 }
2221
2222 static inline bool vpid_sync_vcpu_addr(int vpid, gva_t addr)
2223 {
2224         if (vpid == 0)
2225                 return true;
2226
2227         if (cpu_has_vmx_invvpid_individual_addr()) {
2228                 __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR, vpid, addr);
2229                 return true;
2230         }
2231
2232         return false;
2233 }
2234
2235 static inline void vpid_sync_vcpu_single(int vpid)
2236 {
2237         if (vpid == 0)
2238                 return;
2239
2240         if (cpu_has_vmx_invvpid_single())
2241                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
2242 }
2243
2244 static inline void vpid_sync_vcpu_global(void)
2245 {
2246         if (cpu_has_vmx_invvpid_global())
2247                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
2248 }
2249
2250 static inline void vpid_sync_context(int vpid)
2251 {
2252         if (cpu_has_vmx_invvpid_single())
2253                 vpid_sync_vcpu_single(vpid);
2254         else
2255                 vpid_sync_vcpu_global();
2256 }
2257
2258 static inline void ept_sync_global(void)
2259 {
2260         __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
2261 }
2262
2263 static inline void ept_sync_context(u64 eptp)
2264 {
2265         if (cpu_has_vmx_invept_context())
2266                 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
2267         else
2268                 ept_sync_global();
2269 }
2270
2271 static __always_inline void vmcs_check16(unsigned long field)
2272 {
2273         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2274                          "16-bit accessor invalid for 64-bit field");
2275         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2276                          "16-bit accessor invalid for 64-bit high field");
2277         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2278                          "16-bit accessor invalid for 32-bit high field");
2279         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2280                          "16-bit accessor invalid for natural width field");
2281 }
2282
2283 static __always_inline void vmcs_check32(unsigned long field)
2284 {
2285         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2286                          "32-bit accessor invalid for 16-bit field");
2287         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2288                          "32-bit accessor invalid for natural width field");
2289 }
2290
2291 static __always_inline void vmcs_check64(unsigned long field)
2292 {
2293         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2294                          "64-bit accessor invalid for 16-bit field");
2295         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2296                          "64-bit accessor invalid for 64-bit high field");
2297         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2298                          "64-bit accessor invalid for 32-bit field");
2299         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2300                          "64-bit accessor invalid for natural width field");
2301 }
2302
2303 static __always_inline void vmcs_checkl(unsigned long field)
2304 {
2305         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2306                          "Natural width accessor invalid for 16-bit field");
2307         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2308                          "Natural width accessor invalid for 64-bit field");
2309         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2310                          "Natural width accessor invalid for 64-bit high field");
2311         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2312                          "Natural width accessor invalid for 32-bit field");
2313 }
2314
2315 static __always_inline unsigned long __vmcs_readl(unsigned long field)
2316 {
2317         unsigned long value;
2318
2319         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
2320                       : "=a"(value) : "d"(field) : "cc");
2321         return value;
2322 }
2323
2324 static __always_inline u16 vmcs_read16(unsigned long field)
2325 {
2326         vmcs_check16(field);
2327         if (static_branch_unlikely(&enable_evmcs))
2328                 return evmcs_read16(field);
2329         return __vmcs_readl(field);
2330 }
2331
2332 static __always_inline u32 vmcs_read32(unsigned long field)
2333 {
2334         vmcs_check32(field);
2335         if (static_branch_unlikely(&enable_evmcs))
2336                 return evmcs_read32(field);
2337         return __vmcs_readl(field);
2338 }
2339
2340 static __always_inline u64 vmcs_read64(unsigned long field)
2341 {
2342         vmcs_check64(field);
2343         if (static_branch_unlikely(&enable_evmcs))
2344                 return evmcs_read64(field);
2345 #ifdef CONFIG_X86_64
2346         return __vmcs_readl(field);
2347 #else
2348         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
2349 #endif
2350 }
2351
2352 static __always_inline unsigned long vmcs_readl(unsigned long field)
2353 {
2354         vmcs_checkl(field);
2355         if (static_branch_unlikely(&enable_evmcs))
2356                 return evmcs_read64(field);
2357         return __vmcs_readl(field);
2358 }
2359
2360 static noinline void vmwrite_error(unsigned long field, unsigned long value)
2361 {
2362         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
2363                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
2364         dump_stack();
2365 }
2366
2367 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
2368 {
2369         bool error;
2370
2371         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) CC_SET(na)
2372                       : CC_OUT(na) (error) : "a"(value), "d"(field));
2373         if (unlikely(error))
2374                 vmwrite_error(field, value);
2375 }
2376
2377 static __always_inline void vmcs_write16(unsigned long field, u16 value)
2378 {
2379         vmcs_check16(field);
2380         if (static_branch_unlikely(&enable_evmcs))
2381                 return evmcs_write16(field, value);
2382
2383         __vmcs_writel(field, value);
2384 }
2385
2386 static __always_inline void vmcs_write32(unsigned long field, u32 value)
2387 {
2388         vmcs_check32(field);
2389         if (static_branch_unlikely(&enable_evmcs))
2390                 return evmcs_write32(field, value);
2391
2392         __vmcs_writel(field, value);
2393 }
2394
2395 static __always_inline void vmcs_write64(unsigned long field, u64 value)
2396 {
2397         vmcs_check64(field);
2398         if (static_branch_unlikely(&enable_evmcs))
2399                 return evmcs_write64(field, value);
2400
2401         __vmcs_writel(field, value);
2402 #ifndef CONFIG_X86_64
2403         asm volatile ("");
2404         __vmcs_writel(field+1, value >> 32);
2405 #endif
2406 }
2407
2408 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
2409 {
2410         vmcs_checkl(field);
2411         if (static_branch_unlikely(&enable_evmcs))
2412                 return evmcs_write64(field, value);
2413
2414         __vmcs_writel(field, value);
2415 }
2416
2417 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
2418 {
2419         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2420                          "vmcs_clear_bits does not support 64-bit fields");
2421         if (static_branch_unlikely(&enable_evmcs))
2422                 return evmcs_write32(field, evmcs_read32(field) & ~mask);
2423
2424         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
2425 }
2426
2427 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
2428 {
2429         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2430                          "vmcs_set_bits does not support 64-bit fields");
2431         if (static_branch_unlikely(&enable_evmcs))
2432                 return evmcs_write32(field, evmcs_read32(field) | mask);
2433
2434         __vmcs_writel(field, __vmcs_readl(field) | mask);
2435 }
2436
2437 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
2438 {
2439         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
2440 }
2441
2442 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
2443 {
2444         vmcs_write32(VM_ENTRY_CONTROLS, val);
2445         vmx->vm_entry_controls_shadow = val;
2446 }
2447
2448 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
2449 {
2450         if (vmx->vm_entry_controls_shadow != val)
2451                 vm_entry_controls_init(vmx, val);
2452 }
2453
2454 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
2455 {
2456         return vmx->vm_entry_controls_shadow;
2457 }
2458
2459
2460 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2461 {
2462         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
2463 }
2464
2465 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2466 {
2467         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
2468 }
2469
2470 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
2471 {
2472         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
2473 }
2474
2475 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
2476 {
2477         vmcs_write32(VM_EXIT_CONTROLS, val);
2478         vmx->vm_exit_controls_shadow = val;
2479 }
2480
2481 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
2482 {
2483         if (vmx->vm_exit_controls_shadow != val)
2484                 vm_exit_controls_init(vmx, val);
2485 }
2486
2487 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
2488 {
2489         return vmx->vm_exit_controls_shadow;
2490 }
2491
2492
2493 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2494 {
2495         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
2496 }
2497
2498 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2499 {
2500         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
2501 }
2502
2503 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
2504 {
2505         vmx->segment_cache.bitmask = 0;
2506 }
2507
2508 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
2509                                        unsigned field)
2510 {
2511         bool ret;
2512         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
2513
2514         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
2515                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
2516                 vmx->segment_cache.bitmask = 0;
2517         }
2518         ret = vmx->segment_cache.bitmask & mask;
2519         vmx->segment_cache.bitmask |= mask;
2520         return ret;
2521 }
2522
2523 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
2524 {
2525         u16 *p = &vmx->segment_cache.seg[seg].selector;
2526
2527         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
2528                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
2529         return *p;
2530 }
2531
2532 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
2533 {
2534         ulong *p = &vmx->segment_cache.seg[seg].base;
2535
2536         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
2537                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
2538         return *p;
2539 }
2540
2541 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
2542 {
2543         u32 *p = &vmx->segment_cache.seg[seg].limit;
2544
2545         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
2546                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
2547         return *p;
2548 }
2549
2550 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
2551 {
2552         u32 *p = &vmx->segment_cache.seg[seg].ar;
2553
2554         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
2555                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
2556         return *p;
2557 }
2558
2559 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
2560 {
2561         u32 eb;
2562
2563         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
2564              (1u << DB_VECTOR) | (1u << AC_VECTOR);
2565         /*
2566          * Guest access to VMware backdoor ports could legitimately
2567          * trigger #GP because of TSS I/O permission bitmap.
2568          * We intercept those #GP and allow access to them anyway
2569          * as VMware does.
2570          */
2571         if (enable_vmware_backdoor)
2572                 eb |= (1u << GP_VECTOR);
2573         if ((vcpu->guest_debug &
2574              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
2575             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
2576                 eb |= 1u << BP_VECTOR;
2577         if (to_vmx(vcpu)->rmode.vm86_active)
2578                 eb = ~0;
2579         if (enable_ept)
2580                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
2581
2582         /* When we are running a nested L2 guest and L1 specified for it a
2583          * certain exception bitmap, we must trap the same exceptions and pass
2584          * them to L1. When running L2, we will only handle the exceptions
2585          * specified above if L1 did not want them.
2586          */
2587         if (is_guest_mode(vcpu))
2588                 eb |= get_vmcs12(vcpu)->exception_bitmap;
2589
2590         vmcs_write32(EXCEPTION_BITMAP, eb);
2591 }
2592
2593 /*
2594  * Check if MSR is intercepted for currently loaded MSR bitmap.
2595  */
2596 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
2597 {
2598         unsigned long *msr_bitmap;
2599         int f = sizeof(unsigned long);
2600
2601         if (!cpu_has_vmx_msr_bitmap())
2602                 return true;
2603
2604         msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
2605
2606         if (msr <= 0x1fff) {
2607                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2608         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2609                 msr &= 0x1fff;
2610                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2611         }
2612
2613         return true;
2614 }
2615
2616 /*
2617  * Check if MSR is intercepted for L01 MSR bitmap.
2618  */
2619 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
2620 {
2621         unsigned long *msr_bitmap;
2622         int f = sizeof(unsigned long);
2623
2624         if (!cpu_has_vmx_msr_bitmap())
2625                 return true;
2626
2627         msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
2628
2629         if (msr <= 0x1fff) {
2630                 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2631         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2632                 msr &= 0x1fff;
2633                 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2634         }
2635
2636         return true;
2637 }
2638
2639 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2640                 unsigned long entry, unsigned long exit)
2641 {
2642         vm_entry_controls_clearbit(vmx, entry);
2643         vm_exit_controls_clearbit(vmx, exit);
2644 }
2645
2646 static int find_msr(struct vmx_msrs *m, unsigned int msr)
2647 {
2648         unsigned int i;
2649
2650         for (i = 0; i < m->nr; ++i) {
2651                 if (m->val[i].index == msr)
2652                         return i;
2653         }
2654         return -ENOENT;
2655 }
2656
2657 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
2658 {
2659         int i;
2660         struct msr_autoload *m = &vmx->msr_autoload;
2661
2662         switch (msr) {
2663         case MSR_EFER:
2664                 if (cpu_has_load_ia32_efer) {
2665                         clear_atomic_switch_msr_special(vmx,
2666                                         VM_ENTRY_LOAD_IA32_EFER,
2667                                         VM_EXIT_LOAD_IA32_EFER);
2668                         return;
2669                 }
2670                 break;
2671         case MSR_CORE_PERF_GLOBAL_CTRL:
2672                 if (cpu_has_load_perf_global_ctrl) {
2673                         clear_atomic_switch_msr_special(vmx,
2674                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2675                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2676                         return;
2677                 }
2678                 break;
2679         }
2680         i = find_msr(&m->guest, msr);
2681         if (i < 0)
2682                 goto skip_guest;
2683         --m->guest.nr;
2684         m->guest.val[i] = m->guest.val[m->guest.nr];
2685         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
2686
2687 skip_guest:
2688         i = find_msr(&m->host, msr);
2689         if (i < 0)
2690                 return;
2691
2692         --m->host.nr;
2693         m->host.val[i] = m->host.val[m->host.nr];
2694         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
2695 }
2696
2697 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2698                 unsigned long entry, unsigned long exit,
2699                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
2700                 u64 guest_val, u64 host_val)
2701 {
2702         vmcs_write64(guest_val_vmcs, guest_val);
2703         if (host_val_vmcs != HOST_IA32_EFER)
2704                 vmcs_write64(host_val_vmcs, host_val);
2705         vm_entry_controls_setbit(vmx, entry);
2706         vm_exit_controls_setbit(vmx, exit);
2707 }
2708
2709 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
2710                                   u64 guest_val, u64 host_val, bool entry_only)
2711 {
2712         int i, j = 0;
2713         struct msr_autoload *m = &vmx->msr_autoload;
2714
2715         switch (msr) {
2716         case MSR_EFER:
2717                 if (cpu_has_load_ia32_efer) {
2718                         add_atomic_switch_msr_special(vmx,
2719                                         VM_ENTRY_LOAD_IA32_EFER,
2720                                         VM_EXIT_LOAD_IA32_EFER,
2721                                         GUEST_IA32_EFER,
2722                                         HOST_IA32_EFER,
2723                                         guest_val, host_val);
2724                         return;
2725                 }
2726                 break;
2727         case MSR_CORE_PERF_GLOBAL_CTRL:
2728                 if (cpu_has_load_perf_global_ctrl) {
2729                         add_atomic_switch_msr_special(vmx,
2730                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2731                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2732                                         GUEST_IA32_PERF_GLOBAL_CTRL,
2733                                         HOST_IA32_PERF_GLOBAL_CTRL,
2734                                         guest_val, host_val);
2735                         return;
2736                 }
2737                 break;
2738         case MSR_IA32_PEBS_ENABLE:
2739                 /* PEBS needs a quiescent period after being disabled (to write
2740                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
2741                  * provide that period, so a CPU could write host's record into
2742                  * guest's memory.
2743                  */
2744                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2745         }
2746
2747         i = find_msr(&m->guest, msr);
2748         if (!entry_only)
2749                 j = find_msr(&m->host, msr);
2750
2751         if (i == NR_AUTOLOAD_MSRS || j == NR_AUTOLOAD_MSRS) {
2752                 printk_once(KERN_WARNING "Not enough msr switch entries. "
2753                                 "Can't add msr %x\n", msr);
2754                 return;
2755         }
2756         if (i < 0) {
2757                 i = m->guest.nr++;
2758                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
2759         }
2760         m->guest.val[i].index = msr;
2761         m->guest.val[i].value = guest_val;
2762
2763         if (entry_only)
2764                 return;
2765
2766         if (j < 0) {
2767                 j = m->host.nr++;
2768                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
2769         }
2770         m->host.val[j].index = msr;
2771         m->host.val[j].value = host_val;
2772 }
2773
2774 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2775 {
2776         u64 guest_efer = vmx->vcpu.arch.efer;
2777         u64 ignore_bits = 0;
2778
2779         if (!enable_ept) {
2780                 /*
2781                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2782                  * host CPUID is more efficient than testing guest CPUID
2783                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2784                  */
2785                 if (boot_cpu_has(X86_FEATURE_SMEP))
2786                         guest_efer |= EFER_NX;
2787                 else if (!(guest_efer & EFER_NX))
2788                         ignore_bits |= EFER_NX;
2789         }
2790
2791         /*
2792          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2793          */
2794         ignore_bits |= EFER_SCE;
2795 #ifdef CONFIG_X86_64
2796         ignore_bits |= EFER_LMA | EFER_LME;
2797         /* SCE is meaningful only in long mode on Intel */
2798         if (guest_efer & EFER_LMA)
2799                 ignore_bits &= ~(u64)EFER_SCE;
2800 #endif
2801
2802         /*
2803          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2804          * On CPUs that support "load IA32_EFER", always switch EFER
2805          * atomically, since it's faster than switching it manually.
2806          */
2807         if (cpu_has_load_ia32_efer ||
2808             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2809                 if (!(guest_efer & EFER_LMA))
2810                         guest_efer &= ~EFER_LME;
2811                 if (guest_efer != host_efer)
2812                         add_atomic_switch_msr(vmx, MSR_EFER,
2813                                               guest_efer, host_efer, false);
2814                 else
2815                         clear_atomic_switch_msr(vmx, MSR_EFER);
2816                 return false;
2817         } else {
2818                 clear_atomic_switch_msr(vmx, MSR_EFER);
2819
2820                 guest_efer &= ~ignore_bits;
2821                 guest_efer |= host_efer & ignore_bits;
2822
2823                 vmx->guest_msrs[efer_offset].data = guest_efer;
2824                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2825
2826                 return true;
2827         }
2828 }
2829
2830 #ifdef CONFIG_X86_32
2831 /*
2832  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2833  * VMCS rather than the segment table.  KVM uses this helper to figure
2834  * out the current bases to poke them into the VMCS before entry.
2835  */
2836 static unsigned long segment_base(u16 selector)
2837 {
2838         struct desc_struct *table;
2839         unsigned long v;
2840
2841         if (!(selector & ~SEGMENT_RPL_MASK))
2842                 return 0;
2843
2844         table = get_current_gdt_ro();
2845
2846         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2847                 u16 ldt_selector = kvm_read_ldt();
2848
2849                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2850                         return 0;
2851
2852                 table = (struct desc_struct *)segment_base(ldt_selector);
2853         }
2854         v = get_desc_base(&table[selector >> 3]);
2855         return v;
2856 }
2857 #endif
2858
2859 static void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
2860 {
2861         struct vcpu_vmx *vmx = to_vmx(vcpu);
2862         struct vmcs_host_state *host_state;
2863 #ifdef CONFIG_X86_64
2864         int cpu = raw_smp_processor_id();
2865 #endif
2866         unsigned long fs_base, gs_base;
2867         u16 fs_sel, gs_sel;
2868         int i;
2869
2870         vmx->req_immediate_exit = false;
2871
2872         if (vmx->loaded_cpu_state)
2873                 return;
2874
2875         vmx->loaded_cpu_state = vmx->loaded_vmcs;
2876         host_state = &vmx->loaded_cpu_state->host_state;
2877
2878         /*
2879          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2880          * allow segment selectors with cpl > 0 or ti == 1.
2881          */
2882         host_state->ldt_sel = kvm_read_ldt();
2883
2884 #ifdef CONFIG_X86_64
2885         savesegment(ds, host_state->ds_sel);
2886         savesegment(es, host_state->es_sel);
2887
2888         gs_base = cpu_kernelmode_gs_base(cpu);
2889         if (likely(is_64bit_mm(current->mm))) {
2890                 save_fsgs_for_kvm();
2891                 fs_sel = current->thread.fsindex;
2892                 gs_sel = current->thread.gsindex;
2893                 fs_base = current->thread.fsbase;
2894                 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
2895         } else {
2896                 savesegment(fs, fs_sel);
2897                 savesegment(gs, gs_sel);
2898                 fs_base = read_msr(MSR_FS_BASE);
2899                 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
2900         }
2901
2902         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2903 #else
2904         savesegment(fs, fs_sel);
2905         savesegment(gs, gs_sel);
2906         fs_base = segment_base(fs_sel);
2907         gs_base = segment_base(gs_sel);
2908 #endif
2909
2910         if (unlikely(fs_sel != host_state->fs_sel)) {
2911                 if (!(fs_sel & 7))
2912                         vmcs_write16(HOST_FS_SELECTOR, fs_sel);
2913                 else
2914                         vmcs_write16(HOST_FS_SELECTOR, 0);
2915                 host_state->fs_sel = fs_sel;
2916         }
2917         if (unlikely(gs_sel != host_state->gs_sel)) {
2918                 if (!(gs_sel & 7))
2919                         vmcs_write16(HOST_GS_SELECTOR, gs_sel);
2920                 else
2921                         vmcs_write16(HOST_GS_SELECTOR, 0);
2922                 host_state->gs_sel = gs_sel;
2923         }
2924         if (unlikely(fs_base != host_state->fs_base)) {
2925                 vmcs_writel(HOST_FS_BASE, fs_base);
2926                 host_state->fs_base = fs_base;
2927         }
2928         if (unlikely(gs_base != host_state->gs_base)) {
2929                 vmcs_writel(HOST_GS_BASE, gs_base);
2930                 host_state->gs_base = gs_base;
2931         }
2932
2933         for (i = 0; i < vmx->save_nmsrs; ++i)
2934                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2935                                    vmx->guest_msrs[i].data,
2936                                    vmx->guest_msrs[i].mask);
2937 }
2938
2939 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
2940 {
2941         struct vmcs_host_state *host_state;
2942
2943         if (!vmx->loaded_cpu_state)
2944                 return;
2945
2946         WARN_ON_ONCE(vmx->loaded_cpu_state != vmx->loaded_vmcs);
2947         host_state = &vmx->loaded_cpu_state->host_state;
2948
2949         ++vmx->vcpu.stat.host_state_reload;
2950         vmx->loaded_cpu_state = NULL;
2951
2952 #ifdef CONFIG_X86_64
2953         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2954 #endif
2955         if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
2956                 kvm_load_ldt(host_state->ldt_sel);
2957 #ifdef CONFIG_X86_64
2958                 load_gs_index(host_state->gs_sel);
2959 #else
2960                 loadsegment(gs, host_state->gs_sel);
2961 #endif
2962         }
2963         if (host_state->fs_sel & 7)
2964                 loadsegment(fs, host_state->fs_sel);
2965 #ifdef CONFIG_X86_64
2966         if (unlikely(host_state->ds_sel | host_state->es_sel)) {
2967                 loadsegment(ds, host_state->ds_sel);
2968                 loadsegment(es, host_state->es_sel);
2969         }
2970 #endif
2971         invalidate_tss_limit();
2972 #ifdef CONFIG_X86_64
2973         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2974 #endif
2975         load_fixmap_gdt(raw_smp_processor_id());
2976 }
2977
2978 #ifdef CONFIG_X86_64
2979 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
2980 {
2981         preempt_disable();
2982         if (vmx->loaded_cpu_state)
2983                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2984         preempt_enable();
2985         return vmx->msr_guest_kernel_gs_base;
2986 }
2987
2988 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
2989 {
2990         preempt_disable();
2991         if (vmx->loaded_cpu_state)
2992                 wrmsrl(MSR_KERNEL_GS_BASE, data);
2993         preempt_enable();
2994         vmx->msr_guest_kernel_gs_base = data;
2995 }
2996 #endif
2997
2998 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2999 {
3000         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
3001         struct pi_desc old, new;
3002         unsigned int dest;
3003
3004         /*
3005          * In case of hot-plug or hot-unplug, we may have to undo
3006          * vmx_vcpu_pi_put even if there is no assigned device.  And we
3007          * always keep PI.NDST up to date for simplicity: it makes the
3008          * code easier, and CPU migration is not a fast path.
3009          */
3010         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
3011                 return;
3012
3013         /*
3014          * First handle the simple case where no cmpxchg is necessary; just
3015          * allow posting non-urgent interrupts.
3016          *
3017          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
3018          * PI.NDST: pi_post_block will do it for us and the wakeup_handler
3019          * expects the VCPU to be on the blocked_vcpu_list that matches
3020          * PI.NDST.
3021          */
3022         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
3023             vcpu->cpu == cpu) {
3024                 pi_clear_sn(pi_desc);
3025                 return;
3026         }
3027
3028         /* The full case.  */
3029         do {
3030                 old.control = new.control = pi_desc->control;
3031
3032                 dest = cpu_physical_id(cpu);
3033
3034                 if (x2apic_enabled())
3035                         new.ndst = dest;
3036                 else
3037                         new.ndst = (dest << 8) & 0xFF00;
3038
3039                 new.sn = 0;
3040         } while (cmpxchg64(&pi_desc->control, old.control,
3041                            new.control) != old.control);
3042 }
3043
3044 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
3045 {
3046         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
3047         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
3048 }
3049
3050 /*
3051  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
3052  * vcpu mutex is already taken.
3053  */
3054 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3055 {
3056         struct vcpu_vmx *vmx = to_vmx(vcpu);
3057         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
3058
3059         if (!already_loaded) {
3060                 loaded_vmcs_clear(vmx->loaded_vmcs);
3061                 local_irq_disable();
3062                 crash_disable_local_vmclear(cpu);
3063
3064                 /*
3065                  * Read loaded_vmcs->cpu should be before fetching
3066                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
3067                  * See the comments in __loaded_vmcs_clear().
3068                  */
3069                 smp_rmb();
3070
3071                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
3072                          &per_cpu(loaded_vmcss_on_cpu, cpu));
3073                 crash_enable_local_vmclear(cpu);
3074                 local_irq_enable();
3075         }
3076
3077         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
3078                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
3079                 vmcs_load(vmx->loaded_vmcs->vmcs);
3080                 indirect_branch_prediction_barrier();
3081         }
3082
3083         if (!already_loaded) {
3084                 void *gdt = get_current_gdt_ro();
3085                 unsigned long sysenter_esp;
3086
3087                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3088
3089                 /*
3090                  * Linux uses per-cpu TSS and GDT, so set these when switching
3091                  * processors.  See 22.2.4.
3092                  */
3093                 vmcs_writel(HOST_TR_BASE,
3094                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
3095                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
3096
3097                 /*
3098                  * VM exits change the host TR limit to 0x67 after a VM
3099                  * exit.  This is okay, since 0x67 covers everything except
3100                  * the IO bitmap and have have code to handle the IO bitmap
3101                  * being lost after a VM exit.
3102                  */
3103                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
3104
3105                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
3106                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
3107
3108                 vmx->loaded_vmcs->cpu = cpu;
3109         }
3110
3111         /* Setup TSC multiplier */
3112         if (kvm_has_tsc_control &&
3113             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
3114                 decache_tsc_multiplier(vmx);
3115
3116         vmx_vcpu_pi_load(vcpu, cpu);
3117         vmx->host_pkru = read_pkru();
3118         vmx->host_debugctlmsr = get_debugctlmsr();
3119 }
3120
3121 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
3122 {
3123         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
3124
3125         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
3126                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
3127                 !kvm_vcpu_apicv_active(vcpu))
3128                 return;
3129
3130         /* Set SN when the vCPU is preempted */
3131         if (vcpu->preempted)
3132                 pi_set_sn(pi_desc);
3133 }
3134
3135 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
3136 {
3137         vmx_vcpu_pi_put(vcpu);
3138
3139         vmx_prepare_switch_to_host(to_vmx(vcpu));
3140 }
3141
3142 static bool emulation_required(struct kvm_vcpu *vcpu)
3143 {
3144         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3145 }
3146
3147 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
3148
3149 /*
3150  * Return the cr0 value that a nested guest would read. This is a combination
3151  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
3152  * its hypervisor (cr0_read_shadow).
3153  */
3154 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
3155 {
3156         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
3157                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
3158 }
3159 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
3160 {
3161         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
3162                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
3163 }
3164
3165 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
3166 {
3167         unsigned long rflags, save_rflags;
3168
3169         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
3170                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
3171                 rflags = vmcs_readl(GUEST_RFLAGS);
3172                 if (to_vmx(vcpu)->rmode.vm86_active) {
3173                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3174                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
3175                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3176                 }
3177                 to_vmx(vcpu)->rflags = rflags;
3178         }
3179         return to_vmx(vcpu)->rflags;
3180 }
3181
3182 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
3183 {
3184         unsigned long old_rflags = vmx_get_rflags(vcpu);
3185
3186         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
3187         to_vmx(vcpu)->rflags = rflags;
3188         if (to_vmx(vcpu)->rmode.vm86_active) {
3189                 to_vmx(vcpu)->rmode.save_rflags = rflags;
3190                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3191         }
3192         vmcs_writel(GUEST_RFLAGS, rflags);
3193
3194         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
3195                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
3196 }
3197
3198 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
3199 {
3200         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
3201         int ret = 0;
3202
3203         if (interruptibility & GUEST_INTR_STATE_STI)
3204                 ret |= KVM_X86_SHADOW_INT_STI;
3205         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
3206                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
3207
3208         return ret;
3209 }
3210
3211 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
3212 {
3213         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
3214         u32 interruptibility = interruptibility_old;
3215
3216         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
3217
3218         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
3219                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
3220         else if (mask & KVM_X86_SHADOW_INT_STI)
3221                 interruptibility |= GUEST_INTR_STATE_STI;
3222
3223         if ((interruptibility != interruptibility_old))
3224                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
3225 }
3226
3227 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
3228 {
3229         unsigned long rip;
3230
3231         rip = kvm_rip_read(vcpu);
3232         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3233         kvm_rip_write(vcpu, rip);
3234
3235         /* skipping an emulated instruction also counts */
3236         vmx_set_interrupt_shadow(vcpu, 0);
3237 }
3238
3239 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
3240                                                unsigned long exit_qual)
3241 {
3242         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3243         unsigned int nr = vcpu->arch.exception.nr;
3244         u32 intr_info = nr | INTR_INFO_VALID_MASK;
3245
3246         if (vcpu->arch.exception.has_error_code) {
3247                 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
3248                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3249         }
3250
3251         if (kvm_exception_is_soft(nr))
3252                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3253         else
3254                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3255
3256         if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
3257             vmx_get_nmi_mask(vcpu))
3258                 intr_info |= INTR_INFO_UNBLOCK_NMI;
3259
3260         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
3261 }
3262
3263 /*
3264  * KVM wants to inject page-faults which it got to the guest. This function
3265  * checks whether in a nested guest, we need to inject them to L1 or L2.
3266  */
3267 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
3268 {
3269         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3270         unsigned int nr = vcpu->arch.exception.nr;
3271
3272         if (nr == PF_VECTOR) {
3273                 if (vcpu->arch.exception.nested_apf) {
3274                         *exit_qual = vcpu->arch.apf.nested_apf_token;
3275                         return 1;
3276                 }
3277                 /*
3278                  * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
3279                  * The fix is to add the ancillary datum (CR2 or DR6) to structs
3280                  * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
3281                  * can be written only when inject_pending_event runs.  This should be
3282                  * conditional on a new capability---if the capability is disabled,
3283                  * kvm_multiple_exception would write the ancillary information to
3284                  * CR2 or DR6, for backwards ABI-compatibility.
3285                  */
3286                 if (nested_vmx_is_page_fault_vmexit(vmcs12,
3287                                                     vcpu->arch.exception.error_code)) {
3288                         *exit_qual = vcpu->arch.cr2;
3289                         return 1;
3290                 }
3291         } else {
3292                 if (vmcs12->exception_bitmap & (1u << nr)) {
3293                         if (nr == DB_VECTOR) {
3294                                 *exit_qual = vcpu->arch.dr6;
3295                                 *exit_qual &= ~(DR6_FIXED_1 | DR6_BT);
3296                                 *exit_qual ^= DR6_RTM;
3297                         } else {
3298                                 *exit_qual = 0;
3299                         }
3300                         return 1;
3301                 }
3302         }
3303
3304         return 0;
3305 }
3306
3307 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
3308 {
3309         /*
3310          * Ensure that we clear the HLT state in the VMCS.  We don't need to
3311          * explicitly skip the instruction because if the HLT state is set,
3312          * then the instruction is already executing and RIP has already been
3313          * advanced.
3314          */
3315         if (kvm_hlt_in_guest(vcpu->kvm) &&
3316                         vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
3317                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3318 }
3319
3320 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
3321 {
3322         struct vcpu_vmx *vmx = to_vmx(vcpu);
3323         unsigned nr = vcpu->arch.exception.nr;
3324         bool has_error_code = vcpu->arch.exception.has_error_code;
3325         u32 error_code = vcpu->arch.exception.error_code;
3326         u32 intr_info = nr | INTR_INFO_VALID_MASK;
3327
3328         if (has_error_code) {
3329                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
3330                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3331         }
3332
3333         if (vmx->rmode.vm86_active) {
3334                 int inc_eip = 0;
3335                 if (kvm_exception_is_soft(nr))
3336                         inc_eip = vcpu->arch.event_exit_inst_len;
3337                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
3338                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3339                 return;
3340         }
3341
3342         WARN_ON_ONCE(vmx->emulation_required);
3343
3344         if (kvm_exception_is_soft(nr)) {
3345                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3346                              vmx->vcpu.arch.event_exit_inst_len);
3347                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3348         } else
3349                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3350
3351         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
3352
3353         vmx_clear_hlt(vcpu);
3354 }
3355
3356 static bool vmx_rdtscp_supported(void)
3357 {
3358         return cpu_has_vmx_rdtscp();
3359 }
3360
3361 static bool vmx_invpcid_supported(void)
3362 {
3363         return cpu_has_vmx_invpcid();
3364 }
3365
3366 /*
3367  * Swap MSR entry in host/guest MSR entry array.
3368  */
3369 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
3370 {
3371         struct shared_msr_entry tmp;
3372
3373         tmp = vmx->guest_msrs[to];
3374         vmx->guest_msrs[to] = vmx->guest_msrs[from];
3375         vmx->guest_msrs[from] = tmp;
3376 }
3377
3378 /*
3379  * Set up the vmcs to automatically save and restore system
3380  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
3381  * mode, as fiddling with msrs is very expensive.
3382  */
3383 static void setup_msrs(struct vcpu_vmx *vmx)
3384 {
3385         int save_nmsrs, index;
3386
3387         save_nmsrs = 0;
3388 #ifdef CONFIG_X86_64
3389         if (is_long_mode(&vmx->vcpu)) {
3390                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
3391                 if (index >= 0)
3392                         move_msr_up(vmx, index, save_nmsrs++);
3393                 index = __find_msr_index(vmx, MSR_LSTAR);
3394                 if (index >= 0)
3395                         move_msr_up(vmx, index, save_nmsrs++);
3396                 index = __find_msr_index(vmx, MSR_CSTAR);
3397                 if (index >= 0)
3398                         move_msr_up(vmx, index, save_nmsrs++);
3399                 index = __find_msr_index(vmx, MSR_TSC_AUX);
3400                 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
3401                         move_msr_up(vmx, index, save_nmsrs++);
3402                 /*
3403                  * MSR_STAR is only needed on long mode guests, and only
3404                  * if efer.sce is enabled.
3405                  */
3406                 index = __find_msr_index(vmx, MSR_STAR);
3407                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
3408                         move_msr_up(vmx, index, save_nmsrs++);
3409         }
3410 #endif
3411         index = __find_msr_index(vmx, MSR_EFER);
3412         if (index >= 0 && update_transition_efer(vmx, index))
3413                 move_msr_up(vmx, index, save_nmsrs++);
3414
3415         vmx->save_nmsrs = save_nmsrs;
3416
3417         if (cpu_has_vmx_msr_bitmap())
3418                 vmx_update_msr_bitmap(&vmx->vcpu);
3419 }
3420
3421 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
3422 {
3423         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3424
3425         if (is_guest_mode(vcpu) &&
3426             (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
3427                 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
3428
3429         return vcpu->arch.tsc_offset;
3430 }
3431
3432 /*
3433  * writes 'offset' into guest's timestamp counter offset register
3434  */
3435 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
3436 {
3437         if (is_guest_mode(vcpu)) {
3438                 /*
3439                  * We're here if L1 chose not to trap WRMSR to TSC. According
3440                  * to the spec, this should set L1's TSC; The offset that L1
3441                  * set for L2 remains unchanged, and still needs to be added
3442                  * to the newly set TSC to get L2's TSC.
3443                  */
3444                 struct vmcs12 *vmcs12;
3445                 /* recalculate vmcs02.TSC_OFFSET: */
3446                 vmcs12 = get_vmcs12(vcpu);
3447                 vmcs_write64(TSC_OFFSET, offset +
3448                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
3449                          vmcs12->tsc_offset : 0));
3450         } else {
3451                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
3452                                            vmcs_read64(TSC_OFFSET), offset);
3453                 vmcs_write64(TSC_OFFSET, offset);
3454         }
3455 }
3456
3457 /*
3458  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
3459  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
3460  * all guests if the "nested" module option is off, and can also be disabled
3461  * for a single guest by disabling its VMX cpuid bit.
3462  */
3463 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
3464 {
3465         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
3466 }
3467
3468 /*
3469  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
3470  * returned for the various VMX controls MSRs when nested VMX is enabled.
3471  * The same values should also be used to verify that vmcs12 control fields are
3472  * valid during nested entry from L1 to L2.
3473  * Each of these control msrs has a low and high 32-bit half: A low bit is on
3474  * if the corresponding bit in the (32-bit) control field *must* be on, and a
3475  * bit in the high half is on if the corresponding bit in the control field
3476  * may be on. See also vmx_control_verify().
3477  */
3478 static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv)
3479 {
3480         if (!nested) {
3481                 memset(msrs, 0, sizeof(*msrs));
3482                 return;
3483         }
3484
3485         /*
3486          * Note that as a general rule, the high half of the MSRs (bits in
3487          * the control fields which may be 1) should be initialized by the
3488          * intersection of the underlying hardware's MSR (i.e., features which
3489          * can be supported) and the list of features we want to expose -
3490          * because they are known to be properly supported in our code.
3491          * Also, usually, the low half of the MSRs (bits which must be 1) can
3492          * be set to 0, meaning that L1 may turn off any of these bits. The
3493          * reason is that if one of these bits is necessary, it will appear
3494          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
3495          * fields of vmcs01 and vmcs02, will turn these bits off - and
3496          * nested_vmx_exit_reflected() will not pass related exits to L1.
3497          * These rules have exceptions below.
3498          */
3499
3500         /* pin-based controls */
3501         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
3502                 msrs->pinbased_ctls_low,
3503                 msrs->pinbased_ctls_high);
3504         msrs->pinbased_ctls_low |=
3505                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3506         msrs->pinbased_ctls_high &=
3507                 PIN_BASED_EXT_INTR_MASK |
3508                 PIN_BASED_NMI_EXITING |
3509                 PIN_BASED_VIRTUAL_NMIS |
3510                 (apicv ? PIN_BASED_POSTED_INTR : 0);
3511         msrs->pinbased_ctls_high |=
3512                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3513                 PIN_BASED_VMX_PREEMPTION_TIMER;
3514
3515         /* exit controls */
3516         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
3517                 msrs->exit_ctls_low,
3518                 msrs->exit_ctls_high);
3519         msrs->exit_ctls_low =
3520                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3521
3522         msrs->exit_ctls_high &=
3523 #ifdef CONFIG_X86_64
3524                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
3525 #endif
3526                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
3527         msrs->exit_ctls_high |=
3528                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
3529                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
3530                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
3531
3532         /* We support free control of debug control saving. */
3533         msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
3534
3535         /* entry controls */
3536         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
3537                 msrs->entry_ctls_low,
3538                 msrs->entry_ctls_high);
3539         msrs->entry_ctls_low =
3540                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3541         msrs->entry_ctls_high &=
3542 #ifdef CONFIG_X86_64
3543                 VM_ENTRY_IA32E_MODE |
3544 #endif
3545                 VM_ENTRY_LOAD_IA32_PAT;
3546         msrs->entry_ctls_high |=
3547                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
3548
3549         /* We support free control of debug control loading. */
3550         msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
3551
3552         /* cpu-based controls */
3553         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
3554                 msrs->procbased_ctls_low,
3555                 msrs->procbased_ctls_high);
3556         msrs->procbased_ctls_low =
3557                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3558         msrs->procbased_ctls_high &=
3559                 CPU_BASED_VIRTUAL_INTR_PENDING |
3560                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
3561                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
3562                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
3563                 CPU_BASED_CR3_STORE_EXITING |
3564 #ifdef CONFIG_X86_64
3565                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
3566 #endif
3567                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
3568                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
3569                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
3570                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
3571                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3572         /*
3573          * We can allow some features even when not supported by the
3574          * hardware. For example, L1 can specify an MSR bitmap - and we
3575          * can use it to avoid exits to L1 - even when L0 runs L2
3576          * without MSR bitmaps.
3577          */
3578         msrs->procbased_ctls_high |=
3579                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3580                 CPU_BASED_USE_MSR_BITMAPS;
3581
3582         /* We support free control of CR3 access interception. */
3583         msrs->procbased_ctls_low &=
3584                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
3585
3586         /*
3587          * secondary cpu-based controls.  Do not include those that
3588          * depend on CPUID bits, they are added later by vmx_cpuid_update.
3589          */
3590         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
3591                 msrs->secondary_ctls_low,
3592                 msrs->secondary_ctls_high);
3593         msrs->secondary_ctls_low = 0;
3594         msrs->secondary_ctls_high &=
3595                 SECONDARY_EXEC_DESC |
3596                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3597                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3598                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3599                 SECONDARY_EXEC_WBINVD_EXITING;
3600
3601         /*
3602          * We can emulate "VMCS shadowing," even if the hardware
3603          * doesn't support it.
3604          */
3605         msrs->secondary_ctls_high |=
3606                 SECONDARY_EXEC_SHADOW_VMCS;
3607
3608         if (enable_ept) {
3609                 /* nested EPT: emulate EPT also to L1 */
3610                 msrs->secondary_ctls_high |=
3611                         SECONDARY_EXEC_ENABLE_EPT;
3612                 msrs->ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
3613                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
3614                 if (cpu_has_vmx_ept_execute_only())
3615                         msrs->ept_caps |=
3616                                 VMX_EPT_EXECUTE_ONLY_BIT;
3617                 msrs->ept_caps &= vmx_capability.ept;
3618                 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
3619                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
3620                         VMX_EPT_1GB_PAGE_BIT;
3621                 if (enable_ept_ad_bits) {
3622                         msrs->secondary_ctls_high |=
3623                                 SECONDARY_EXEC_ENABLE_PML;
3624                         msrs->ept_caps |= VMX_EPT_AD_BIT;
3625                 }
3626         }
3627
3628         if (cpu_has_vmx_vmfunc()) {
3629                 msrs->secondary_ctls_high |=
3630                         SECONDARY_EXEC_ENABLE_VMFUNC;
3631                 /*
3632                  * Advertise EPTP switching unconditionally
3633                  * since we emulate it
3634                  */
3635                 if (enable_ept)
3636                         msrs->vmfunc_controls =
3637                                 VMX_VMFUNC_EPTP_SWITCHING;
3638         }
3639
3640         /*
3641          * Old versions of KVM use the single-context version without
3642          * checking for support, so declare that it is supported even
3643          * though it is treated as global context.  The alternative is
3644          * not failing the single-context invvpid, and it is worse.
3645          */
3646         if (enable_vpid) {
3647                 msrs->secondary_ctls_high |=
3648                         SECONDARY_EXEC_ENABLE_VPID;
3649                 msrs->vpid_caps = VMX_VPID_INVVPID_BIT |
3650                         VMX_VPID_EXTENT_SUPPORTED_MASK;
3651         }
3652
3653         if (enable_unrestricted_guest)
3654                 msrs->secondary_ctls_high |=
3655                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
3656
3657         if (flexpriority_enabled)
3658                 msrs->secondary_ctls_high |=
3659                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3660
3661         /* miscellaneous data */
3662         rdmsr(MSR_IA32_VMX_MISC,
3663                 msrs->misc_low,
3664                 msrs->misc_high);
3665         msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA;
3666         msrs->misc_low |=
3667                 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
3668                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
3669                 VMX_MISC_ACTIVITY_HLT;
3670         msrs->misc_high = 0;
3671
3672         /*
3673          * This MSR reports some information about VMX support. We
3674          * should return information about the VMX we emulate for the
3675          * guest, and the VMCS structure we give it - not about the
3676          * VMX support of the underlying hardware.
3677          */
3678         msrs->basic =
3679                 VMCS12_REVISION |
3680                 VMX_BASIC_TRUE_CTLS |
3681                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
3682                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
3683
3684         if (cpu_has_vmx_basic_inout())
3685                 msrs->basic |= VMX_BASIC_INOUT;
3686
3687         /*
3688          * These MSRs specify bits which the guest must keep fixed on
3689          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
3690          * We picked the standard core2 setting.
3691          */
3692 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
3693 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
3694         msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON;
3695         msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
3696
3697         /* These MSRs specify bits which the guest must keep fixed off. */
3698         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
3699         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
3700
3701         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
3702         msrs->vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1;
3703 }
3704
3705 /*
3706  * if fixed0[i] == 1: val[i] must be 1
3707  * if fixed1[i] == 0: val[i] must be 0
3708  */
3709 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
3710 {
3711         return ((val & fixed1) | fixed0) == val;
3712 }
3713
3714 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
3715 {
3716         return fixed_bits_valid(control, low, high);
3717 }
3718
3719 static inline u64 vmx_control_msr(u32 low, u32 high)
3720 {
3721         return low | ((u64)high << 32);
3722 }
3723
3724 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
3725 {
3726         superset &= mask;
3727         subset &= mask;
3728
3729         return (superset | subset) == superset;
3730 }
3731
3732 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
3733 {
3734         const u64 feature_and_reserved =
3735                 /* feature (except bit 48; see below) */
3736                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
3737                 /* reserved */
3738                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
3739         u64 vmx_basic = vmx->nested.msrs.basic;
3740
3741         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
3742                 return -EINVAL;
3743
3744         /*
3745          * KVM does not emulate a version of VMX that constrains physical
3746          * addresses of VMX structures (e.g. VMCS) to 32-bits.
3747          */
3748         if (data & BIT_ULL(48))
3749                 return -EINVAL;
3750
3751         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
3752             vmx_basic_vmcs_revision_id(data))
3753                 return -EINVAL;
3754
3755         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
3756                 return -EINVAL;
3757
3758         vmx->nested.msrs.basic = data;
3759         return 0;
3760 }
3761
3762 static int
3763 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3764 {
3765         u64 supported;
3766         u32 *lowp, *highp;
3767
3768         switch (msr_index) {
3769         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3770                 lowp = &vmx->nested.msrs.pinbased_ctls_low;
3771                 highp = &vmx->nested.msrs.pinbased_ctls_high;
3772                 break;
3773         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3774                 lowp = &vmx->nested.msrs.procbased_ctls_low;
3775                 highp = &vmx->nested.msrs.procbased_ctls_high;
3776                 break;
3777         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3778                 lowp = &vmx->nested.msrs.exit_ctls_low;
3779                 highp = &vmx->nested.msrs.exit_ctls_high;
3780                 break;
3781         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3782                 lowp = &vmx->nested.msrs.entry_ctls_low;
3783                 highp = &vmx->nested.msrs.entry_ctls_high;
3784                 break;
3785         case MSR_IA32_VMX_PROCBASED_CTLS2:
3786                 lowp = &vmx->nested.msrs.secondary_ctls_low;
3787                 highp = &vmx->nested.msrs.secondary_ctls_high;
3788                 break;
3789         default:
3790                 BUG();
3791         }
3792
3793         supported = vmx_control_msr(*lowp, *highp);
3794
3795         /* Check must-be-1 bits are still 1. */
3796         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3797                 return -EINVAL;
3798
3799         /* Check must-be-0 bits are still 0. */
3800         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3801                 return -EINVAL;
3802
3803         *lowp = data;
3804         *highp = data >> 32;
3805         return 0;
3806 }
3807
3808 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3809 {
3810         const u64 feature_and_reserved_bits =
3811                 /* feature */
3812                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3813                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3814                 /* reserved */
3815                 GENMASK_ULL(13, 9) | BIT_ULL(31);
3816         u64 vmx_misc;
3817
3818         vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
3819                                    vmx->nested.msrs.misc_high);
3820
3821         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3822                 return -EINVAL;
3823
3824         if ((vmx->nested.msrs.pinbased_ctls_high &
3825              PIN_BASED_VMX_PREEMPTION_TIMER) &&
3826             vmx_misc_preemption_timer_rate(data) !=
3827             vmx_misc_preemption_timer_rate(vmx_misc))
3828                 return -EINVAL;
3829
3830         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3831                 return -EINVAL;
3832
3833         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3834                 return -EINVAL;
3835
3836         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3837                 return -EINVAL;
3838
3839         vmx->nested.msrs.misc_low = data;
3840         vmx->nested.msrs.misc_high = data >> 32;
3841
3842         /*
3843          * If L1 has read-only VM-exit information fields, use the
3844          * less permissive vmx_vmwrite_bitmap to specify write
3845          * permissions for the shadow VMCS.
3846          */
3847         if (enable_shadow_vmcs && !nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
3848                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
3849
3850         return 0;
3851 }
3852
3853 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3854 {
3855         u64 vmx_ept_vpid_cap;
3856
3857         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps,
3858                                            vmx->nested.msrs.vpid_caps);
3859
3860         /* Every bit is either reserved or a feature bit. */
3861         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3862                 return -EINVAL;
3863
3864         vmx->nested.msrs.ept_caps = data;
3865         vmx->nested.msrs.vpid_caps = data >> 32;
3866         return 0;
3867 }
3868
3869 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3870 {
3871         u64 *msr;
3872
3873         switch (msr_index) {
3874         case MSR_IA32_VMX_CR0_FIXED0:
3875                 msr = &vmx->nested.msrs.cr0_fixed0;
3876                 break;
3877         case MSR_IA32_VMX_CR4_FIXED0:
3878                 msr = &vmx->nested.msrs.cr4_fixed0;
3879                 break;
3880         default:
3881                 BUG();
3882         }
3883
3884         /*
3885          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3886          * must be 1 in the restored value.
3887          */
3888         if (!is_bitwise_subset(data, *msr, -1ULL))
3889                 return -EINVAL;
3890
3891         *msr = data;
3892         return 0;
3893 }
3894
3895 /*
3896  * Called when userspace is restoring VMX MSRs.
3897  *
3898  * Returns 0 on success, non-0 otherwise.
3899  */
3900 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3901 {
3902         struct vcpu_vmx *vmx = to_vmx(vcpu);
3903
3904         /*
3905          * Don't allow changes to the VMX capability MSRs while the vCPU
3906          * is in VMX operation.
3907          */
3908         if (vmx->nested.vmxon)
3909                 return -EBUSY;
3910
3911         switch (msr_index) {
3912         case MSR_IA32_VMX_BASIC:
3913                 return vmx_restore_vmx_basic(vmx, data);
3914         case MSR_IA32_VMX_PINBASED_CTLS:
3915         case MSR_IA32_VMX_PROCBASED_CTLS:
3916         case MSR_IA32_VMX_EXIT_CTLS:
3917         case MSR_IA32_VMX_ENTRY_CTLS:
3918                 /*
3919                  * The "non-true" VMX capability MSRs are generated from the
3920                  * "true" MSRs, so we do not support restoring them directly.
3921                  *
3922                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3923                  * should restore the "true" MSRs with the must-be-1 bits
3924                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3925                  * DEFAULT SETTINGS".
3926                  */
3927                 return -EINVAL;
3928         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3929         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3930         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3931         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3932         case MSR_IA32_VMX_PROCBASED_CTLS2:
3933                 return vmx_restore_control_msr(vmx, msr_index, data);
3934         case MSR_IA32_VMX_MISC:
3935                 return vmx_restore_vmx_misc(vmx, data);
3936         case MSR_IA32_VMX_CR0_FIXED0:
3937         case MSR_IA32_VMX_CR4_FIXED0:
3938                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3939         case MSR_IA32_VMX_CR0_FIXED1:
3940         case MSR_IA32_VMX_CR4_FIXED1:
3941                 /*
3942                  * These MSRs are generated based on the vCPU's CPUID, so we
3943                  * do not support restoring them directly.
3944                  */
3945                 return -EINVAL;
3946         case MSR_IA32_VMX_EPT_VPID_CAP:
3947                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3948         case MSR_IA32_VMX_VMCS_ENUM:
3949                 vmx->nested.msrs.vmcs_enum = data;
3950                 return 0;
3951         default:
3952                 /*
3953                  * The rest of the VMX capability MSRs do not support restore.
3954                  */
3955                 return -EINVAL;
3956         }
3957 }
3958
3959 /* Returns 0 on success, non-0 otherwise. */
3960 static int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata)
3961 {
3962         switch (msr_index) {
3963         case MSR_IA32_VMX_BASIC:
3964                 *pdata = msrs->basic;
3965                 break;
3966         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3967         case MSR_IA32_VMX_PINBASED_CTLS:
3968                 *pdata = vmx_control_msr(
3969                         msrs->pinbased_ctls_low,
3970                         msrs->pinbased_ctls_high);
3971                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3972                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3973                 break;
3974         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3975         case MSR_IA32_VMX_PROCBASED_CTLS:
3976                 *pdata = vmx_control_msr(
3977                         msrs->procbased_ctls_low,
3978                         msrs->procbased_ctls_high);
3979                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3980                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3981                 break;
3982         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3983         case MSR_IA32_VMX_EXIT_CTLS:
3984                 *pdata = vmx_control_msr(
3985                         msrs->exit_ctls_low,
3986                         msrs->exit_ctls_high);
3987                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3988                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3989                 break;
3990         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3991         case MSR_IA32_VMX_ENTRY_CTLS:
3992                 *pdata = vmx_control_msr(
3993                         msrs->entry_ctls_low,
3994                         msrs->entry_ctls_high);
3995                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3996                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3997                 break;
3998         case MSR_IA32_VMX_MISC:
3999                 *pdata = vmx_control_msr(
4000                         msrs->misc_low,
4001                         msrs->misc_high);
4002                 break;
4003         case MSR_IA32_VMX_CR0_FIXED0:
4004                 *pdata = msrs->cr0_fixed0;
4005                 break;
4006         case MSR_IA32_VMX_CR0_FIXED1:
4007                 *pdata = msrs->cr0_fixed1;
4008                 break;
4009         case MSR_IA32_VMX_CR4_FIXED0:
4010                 *pdata = msrs->cr4_fixed0;
4011                 break;
4012         case MSR_IA32_VMX_CR4_FIXED1:
4013                 *pdata = msrs->cr4_fixed1;
4014                 break;
4015         case MSR_IA32_VMX_VMCS_ENUM:
4016                 *pdata = msrs->vmcs_enum;
4017                 break;
4018         case MSR_IA32_VMX_PROCBASED_CTLS2:
4019                 *pdata = vmx_control_msr(
4020                         msrs->secondary_ctls_low,
4021                         msrs->secondary_ctls_high);
4022                 break;
4023         case MSR_IA32_VMX_EPT_VPID_CAP:
4024                 *pdata = msrs->ept_caps |
4025                         ((u64)msrs->vpid_caps << 32);
4026                 break;
4027         case MSR_IA32_VMX_VMFUNC:
4028                 *pdata = msrs->vmfunc_controls;
4029                 break;
4030         default:
4031                 return 1;
4032         }
4033
4034         return 0;
4035 }
4036
4037 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
4038                                                  uint64_t val)
4039 {
4040         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
4041
4042         return !(val & ~valid_bits);
4043 }
4044
4045 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
4046 {
4047         switch (msr->index) {
4048         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4049                 if (!nested)
4050                         return 1;
4051                 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
4052         default:
4053                 return 1;
4054         }
4055
4056         return 0;
4057 }
4058
4059 /*
4060  * Reads an msr value (of 'msr_index') into 'pdata'.
4061  * Returns 0 on success, non-0 otherwise.
4062  * Assumes vcpu_load() was already called.
4063  */
4064 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4065 {
4066         struct vcpu_vmx *vmx = to_vmx(vcpu);
4067         struct shared_msr_entry *msr;
4068
4069         switch (msr_info->index) {
4070 #ifdef CONFIG_X86_64
4071         case MSR_FS_BASE:
4072                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
4073                 break;
4074         case MSR_GS_BASE:
4075                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
4076                 break;
4077         case MSR_KERNEL_GS_BASE:
4078                 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
4079                 break;
4080 #endif
4081         case MSR_EFER:
4082                 return kvm_get_msr_common(vcpu, msr_info);
4083         case MSR_IA32_SPEC_CTRL:
4084                 if (!msr_info->host_initiated &&
4085                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
4086                         return 1;
4087
4088                 msr_info->data = to_vmx(vcpu)->spec_ctrl;
4089                 break;
4090         case MSR_IA32_ARCH_CAPABILITIES:
4091                 if (!msr_info->host_initiated &&
4092                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
4093                         return 1;
4094                 msr_info->data = to_vmx(vcpu)->arch_capabilities;
4095                 break;
4096         case MSR_IA32_SYSENTER_CS:
4097                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
4098                 break;
4099         case MSR_IA32_SYSENTER_EIP:
4100                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
4101                 break;
4102         case MSR_IA32_SYSENTER_ESP:
4103                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
4104                 break;
4105         case MSR_IA32_BNDCFGS:
4106                 if (!kvm_mpx_supported() ||
4107                     (!msr_info->host_initiated &&
4108                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
4109                         return 1;
4110                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
4111                 break;
4112         case MSR_IA32_MCG_EXT_CTL:
4113                 if (!msr_info->host_initiated &&
4114                     !(vmx->msr_ia32_feature_control &
4115                       FEATURE_CONTROL_LMCE))
4116                         return 1;
4117                 msr_info->data = vcpu->arch.mcg_ext_ctl;
4118                 break;
4119         case MSR_IA32_FEATURE_CONTROL:
4120                 msr_info->data = vmx->msr_ia32_feature_control;
4121                 break;
4122         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4123                 if (!nested_vmx_allowed(vcpu))
4124                         return 1;
4125                 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
4126                                        &msr_info->data);
4127         case MSR_IA32_XSS:
4128                 if (!vmx_xsaves_supported())
4129                         return 1;
4130                 msr_info->data = vcpu->arch.ia32_xss;
4131                 break;
4132         case MSR_TSC_AUX:
4133                 if (!msr_info->host_initiated &&
4134                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4135                         return 1;
4136                 /* Otherwise falls through */
4137         default:
4138                 msr = find_msr_entry(vmx, msr_info->index);
4139                 if (msr) {
4140                         msr_info->data = msr->data;
4141                         break;
4142                 }
4143                 return kvm_get_msr_common(vcpu, msr_info);
4144         }
4145
4146         return 0;
4147 }
4148
4149 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
4150
4151 /*
4152  * Writes msr value into into the appropriate "register".
4153  * Returns 0 on success, non-0 otherwise.
4154  * Assumes vcpu_load() was already called.
4155  */
4156 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4157 {
4158         struct vcpu_vmx *vmx = to_vmx(vcpu);
4159         struct shared_msr_entry *msr;
4160         int ret = 0;
4161         u32 msr_index = msr_info->index;
4162         u64 data = msr_info->data;
4163
4164         switch (msr_index) {
4165         case MSR_EFER:
4166                 ret = kvm_set_msr_common(vcpu, msr_info);
4167                 break;
4168 #ifdef CONFIG_X86_64
4169         case MSR_FS_BASE:
4170                 vmx_segment_cache_clear(vmx);
4171                 vmcs_writel(GUEST_FS_BASE, data);
4172                 break;
4173         case MSR_GS_BASE:
4174                 vmx_segment_cache_clear(vmx);
4175                 vmcs_writel(GUEST_GS_BASE, data);
4176                 break;
4177         case MSR_KERNEL_GS_BASE:
4178                 vmx_write_guest_kernel_gs_base(vmx, data);
4179                 break;
4180 #endif
4181         case MSR_IA32_SYSENTER_CS:
4182                 vmcs_write32(GUEST_SYSENTER_CS, data);
4183                 break;
4184         case MSR_IA32_SYSENTER_EIP:
4185                 vmcs_writel(GUEST_SYSENTER_EIP, data);
4186                 break;
4187         case MSR_IA32_SYSENTER_ESP:
4188                 vmcs_writel(GUEST_SYSENTER_ESP, data);
4189                 break;
4190         case MSR_IA32_BNDCFGS:
4191                 if (!kvm_mpx_supported() ||
4192                     (!msr_info->host_initiated &&
4193                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
4194                         return 1;
4195                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
4196                     (data & MSR_IA32_BNDCFGS_RSVD))
4197                         return 1;
4198                 vmcs_write64(GUEST_BNDCFGS, data);
4199                 break;
4200         case MSR_IA32_SPEC_CTRL:
4201                 if (!msr_info->host_initiated &&
4202                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
4203                         return 1;
4204
4205                 /* The STIBP bit doesn't fault even if it's not advertised */
4206                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4207                         return 1;
4208
4209                 vmx->spec_ctrl = data;
4210
4211                 if (!data)
4212                         break;
4213
4214                 /*
4215                  * For non-nested:
4216                  * When it's written (to non-zero) for the first time, pass
4217                  * it through.
4218                  *
4219                  * For nested:
4220                  * The handling of the MSR bitmap for L2 guests is done in
4221                  * nested_vmx_merge_msr_bitmap. We should not touch the
4222                  * vmcs02.msr_bitmap here since it gets completely overwritten
4223                  * in the merging. We update the vmcs01 here for L1 as well
4224                  * since it will end up touching the MSR anyway now.
4225                  */
4226                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
4227                                               MSR_IA32_SPEC_CTRL,
4228                                               MSR_TYPE_RW);
4229                 break;
4230         case MSR_IA32_PRED_CMD:
4231                 if (!msr_info->host_initiated &&
4232                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
4233                         return 1;
4234
4235                 if (data & ~PRED_CMD_IBPB)
4236                         return 1;
4237
4238                 if (!data)
4239                         break;
4240
4241                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4242
4243                 /*
4244                  * For non-nested:
4245                  * When it's written (to non-zero) for the first time, pass
4246                  * it through.
4247                  *
4248                  * For nested:
4249                  * The handling of the MSR bitmap for L2 guests is done in
4250                  * nested_vmx_merge_msr_bitmap. We should not touch the
4251                  * vmcs02.msr_bitmap here since it gets completely overwritten
4252                  * in the merging.
4253                  */
4254                 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
4255                                               MSR_TYPE_W);
4256                 break;
4257         case MSR_IA32_ARCH_CAPABILITIES:
4258                 if (!msr_info->host_initiated)
4259                         return 1;
4260                 vmx->arch_capabilities = data;
4261                 break;
4262         case MSR_IA32_CR_PAT:
4263                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4264                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4265                                 return 1;
4266                         vmcs_write64(GUEST_IA32_PAT, data);
4267                         vcpu->arch.pat = data;
4268                         break;
4269                 }
4270                 ret = kvm_set_msr_common(vcpu, msr_info);
4271                 break;
4272         case MSR_IA32_TSC_ADJUST:
4273                 ret = kvm_set_msr_common(vcpu, msr_info);
4274                 break;
4275         case MSR_IA32_MCG_EXT_CTL:
4276                 if ((!msr_info->host_initiated &&
4277                      !(to_vmx(vcpu)->msr_ia32_feature_control &
4278                        FEATURE_CONTROL_LMCE)) ||
4279                     (data & ~MCG_EXT_CTL_LMCE_EN))
4280                         return 1;
4281                 vcpu->arch.mcg_ext_ctl = data;
4282                 break;
4283         case MSR_IA32_FEATURE_CONTROL:
4284                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
4285                     (to_vmx(vcpu)->msr_ia32_feature_control &
4286                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
4287                         return 1;
4288                 vmx->msr_ia32_feature_control = data;
4289                 if (msr_info->host_initiated && data == 0)
4290                         vmx_leave_nested(vcpu);
4291                 break;
4292         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4293                 if (!msr_info->host_initiated)
4294                         return 1; /* they are read-only */
4295                 if (!nested_vmx_allowed(vcpu))
4296                         return 1;
4297                 return vmx_set_vmx_msr(vcpu, msr_index, data);
4298         case MSR_IA32_XSS:
4299                 if (!vmx_xsaves_supported())
4300                         return 1;
4301                 /*
4302                  * The only supported bit as of Skylake is bit 8, but
4303                  * it is not supported on KVM.
4304                  */
4305                 if (data != 0)
4306                         return 1;
4307                 vcpu->arch.ia32_xss = data;
4308                 if (vcpu->arch.ia32_xss != host_xss)
4309                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
4310                                 vcpu->arch.ia32_xss, host_xss, false);
4311                 else
4312                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
4313                 break;
4314         case MSR_TSC_AUX:
4315                 if (!msr_info->host_initiated &&
4316                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4317                         return 1;
4318                 /* Check reserved bit, higher 32 bits should be zero */
4319                 if ((data >> 32) != 0)
4320                         return 1;
4321                 /* Otherwise falls through */
4322         default:
4323                 msr = find_msr_entry(vmx, msr_index);
4324                 if (msr) {
4325                         u64 old_msr_data = msr->data;
4326                         msr->data = data;
4327                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
4328                                 preempt_disable();
4329                                 ret = kvm_set_shared_msr(msr->index, msr->data,
4330                                                          msr->mask);
4331                                 preempt_enable();
4332                                 if (ret)
4333                                         msr->data = old_msr_data;
4334                         }
4335                         break;
4336                 }
4337                 ret = kvm_set_msr_common(vcpu, msr_info);
4338         }
4339
4340         return ret;
4341 }
4342
4343 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
4344 {
4345         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
4346         switch (reg) {
4347         case VCPU_REGS_RSP:
4348                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
4349                 break;
4350         case VCPU_REGS_RIP:
4351                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
4352                 break;
4353         case VCPU_EXREG_PDPTR:
4354                 if (enable_ept)
4355                         ept_save_pdptrs(vcpu);
4356                 break;
4357         default:
4358                 break;
4359         }
4360 }
4361
4362 static __init int cpu_has_kvm_support(void)
4363 {
4364         return cpu_has_vmx();
4365 }
4366
4367 static __init int vmx_disabled_by_bios(void)
4368 {
4369         u64 msr;
4370
4371         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
4372         if (msr & FEATURE_CONTROL_LOCKED) {
4373                 /* launched w/ TXT and VMX disabled */
4374                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4375                         && tboot_enabled())
4376                         return 1;
4377                 /* launched w/o TXT and VMX only enabled w/ TXT */
4378                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4379                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4380                         && !tboot_enabled()) {
4381                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
4382                                 "activate TXT before enabling KVM\n");
4383                         return 1;
4384                 }
4385                 /* launched w/o TXT and VMX disabled */
4386                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4387                         && !tboot_enabled())
4388                         return 1;
4389         }
4390
4391         return 0;
4392 }
4393
4394 static void kvm_cpu_vmxon(u64 addr)
4395 {
4396         cr4_set_bits(X86_CR4_VMXE);
4397         intel_pt_handle_vmx(1);
4398
4399         asm volatile (ASM_VMX_VMXON_RAX
4400                         : : "a"(&addr), "m"(addr)
4401                         : "memory", "cc");
4402 }
4403
4404 static int hardware_enable(void)
4405 {
4406         int cpu = raw_smp_processor_id();
4407         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
4408         u64 old, test_bits;
4409
4410         if (cr4_read_shadow() & X86_CR4_VMXE)
4411                 return -EBUSY;
4412
4413         /*
4414          * This can happen if we hot-added a CPU but failed to allocate
4415          * VP assist page for it.
4416          */
4417         if (static_branch_unlikely(&enable_evmcs) &&
4418             !hv_get_vp_assist_page(cpu))
4419                 return -EFAULT;
4420
4421         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
4422         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
4423         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
4424
4425         /*
4426          * Now we can enable the vmclear operation in kdump
4427          * since the loaded_vmcss_on_cpu list on this cpu
4428          * has been initialized.
4429          *
4430          * Though the cpu is not in VMX operation now, there
4431          * is no problem to enable the vmclear operation
4432          * for the loaded_vmcss_on_cpu list is empty!
4433          */
4434         crash_enable_local_vmclear(cpu);
4435
4436         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
4437
4438         test_bits = FEATURE_CONTROL_LOCKED;
4439         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
4440         if (tboot_enabled())
4441                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
4442
4443         if ((old & test_bits) != test_bits) {
4444                 /* enable and lock */
4445                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
4446         }
4447         kvm_cpu_vmxon(phys_addr);
4448         if (enable_ept)
4449                 ept_sync_global();
4450
4451         return 0;
4452 }
4453
4454 static void vmclear_local_loaded_vmcss(void)
4455 {
4456         int cpu = raw_smp_processor_id();
4457         struct loaded_vmcs *v, *n;
4458
4459         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
4460                                  loaded_vmcss_on_cpu_link)
4461                 __loaded_vmcs_clear(v);
4462 }
4463
4464
4465 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
4466  * tricks.
4467  */
4468 static void kvm_cpu_vmxoff(void)
4469 {
4470         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
4471
4472         intel_pt_handle_vmx(0);
4473         cr4_clear_bits(X86_CR4_VMXE);
4474 }
4475
4476 static void hardware_disable(void)
4477 {
4478         vmclear_local_loaded_vmcss();
4479         kvm_cpu_vmxoff();
4480 }
4481
4482 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
4483                                       u32 msr, u32 *result)
4484 {
4485         u32 vmx_msr_low, vmx_msr_high;
4486         u32 ctl = ctl_min | ctl_opt;
4487
4488         rdmsr(msr, vmx_msr_low, vmx_msr_high);
4489
4490         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
4491         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
4492
4493         /* Ensure minimum (required) set of control bits are supported. */
4494         if (ctl_min & ~ctl)
4495                 return -EIO;
4496
4497         *result = ctl;
4498         return 0;
4499 }
4500
4501 static __init bool allow_1_setting(u32 msr, u32 ctl)
4502 {
4503         u32 vmx_msr_low, vmx_msr_high;
4504
4505         rdmsr(msr, vmx_msr_low, vmx_msr_high);
4506         return vmx_msr_high & ctl;
4507 }
4508
4509 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
4510 {
4511         u32 vmx_msr_low, vmx_msr_high;
4512         u32 min, opt, min2, opt2;
4513         u32 _pin_based_exec_control = 0;
4514         u32 _cpu_based_exec_control = 0;
4515         u32 _cpu_based_2nd_exec_control = 0;
4516         u32 _vmexit_control = 0;
4517         u32 _vmentry_control = 0;
4518
4519         memset(vmcs_conf, 0, sizeof(*vmcs_conf));
4520         min = CPU_BASED_HLT_EXITING |
4521 #ifdef CONFIG_X86_64
4522               CPU_BASED_CR8_LOAD_EXITING |
4523               CPU_BASED_CR8_STORE_EXITING |
4524 #endif
4525               CPU_BASED_CR3_LOAD_EXITING |
4526               CPU_BASED_CR3_STORE_EXITING |
4527               CPU_BASED_UNCOND_IO_EXITING |
4528               CPU_BASED_MOV_DR_EXITING |
4529               CPU_BASED_USE_TSC_OFFSETING |
4530               CPU_BASED_MWAIT_EXITING |
4531               CPU_BASED_MONITOR_EXITING |
4532               CPU_BASED_INVLPG_EXITING |
4533               CPU_BASED_RDPMC_EXITING;
4534
4535         opt = CPU_BASED_TPR_SHADOW |
4536               CPU_BASED_USE_MSR_BITMAPS |
4537               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
4538         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
4539                                 &_cpu_based_exec_control) < 0)
4540                 return -EIO;
4541 #ifdef CONFIG_X86_64
4542         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4543                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
4544                                            ~CPU_BASED_CR8_STORE_EXITING;
4545 #endif
4546         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
4547                 min2 = 0;
4548                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4549                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4550                         SECONDARY_EXEC_WBINVD_EXITING |
4551                         SECONDARY_EXEC_ENABLE_VPID |
4552                         SECONDARY_EXEC_ENABLE_EPT |
4553                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
4554                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
4555                         SECONDARY_EXEC_DESC |
4556                         SECONDARY_EXEC_RDTSCP |
4557                         SECONDARY_EXEC_ENABLE_INVPCID |
4558                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4559                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4560                         SECONDARY_EXEC_SHADOW_VMCS |
4561                         SECONDARY_EXEC_XSAVES |
4562                         SECONDARY_EXEC_RDSEED_EXITING |
4563                         SECONDARY_EXEC_RDRAND_EXITING |
4564                         SECONDARY_EXEC_ENABLE_PML |
4565                         SECONDARY_EXEC_TSC_SCALING |
4566                         SECONDARY_EXEC_ENABLE_VMFUNC |
4567                         SECONDARY_EXEC_ENCLS_EXITING;
4568                 if (adjust_vmx_controls(min2, opt2,
4569                                         MSR_IA32_VMX_PROCBASED_CTLS2,
4570                                         &_cpu_based_2nd_exec_control) < 0)
4571                         return -EIO;
4572         }
4573 #ifndef CONFIG_X86_64
4574         if (!(_cpu_based_2nd_exec_control &
4575                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
4576                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
4577 #endif
4578
4579         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4580                 _cpu_based_2nd_exec_control &= ~(
4581                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4582                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4583                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4584
4585         rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
4586                 &vmx_capability.ept, &vmx_capability.vpid);
4587
4588         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
4589                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
4590                    enabled */
4591                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
4592                                              CPU_BASED_CR3_STORE_EXITING |
4593                                              CPU_BASED_INVLPG_EXITING);
4594         } else if (vmx_capability.ept) {
4595                 vmx_capability.ept = 0;
4596                 pr_warn_once("EPT CAP should not exist if not support "
4597                                 "1-setting enable EPT VM-execution control\n");
4598         }
4599         if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
4600                 vmx_capability.vpid) {
4601                 vmx_capability.vpid = 0;
4602                 pr_warn_once("VPID CAP should not exist if not support "
4603                                 "1-setting enable VPID VM-execution control\n");
4604         }
4605
4606         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
4607 #ifdef CONFIG_X86_64
4608         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
4609 #endif
4610         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
4611                 VM_EXIT_CLEAR_BNDCFGS;
4612         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
4613                                 &_vmexit_control) < 0)
4614                 return -EIO;
4615
4616         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
4617         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
4618                  PIN_BASED_VMX_PREEMPTION_TIMER;
4619         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
4620                                 &_pin_based_exec_control) < 0)
4621                 return -EIO;
4622
4623         if (cpu_has_broken_vmx_preemption_timer())
4624                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4625         if (!(_cpu_based_2nd_exec_control &
4626                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
4627                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
4628
4629         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
4630         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
4631         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
4632                                 &_vmentry_control) < 0)
4633                 return -EIO;
4634
4635         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
4636
4637         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
4638         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
4639                 return -EIO;
4640
4641 #ifdef CONFIG_X86_64
4642         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
4643         if (vmx_msr_high & (1u<<16))
4644                 return -EIO;
4645 #endif
4646
4647         /* Require Write-Back (WB) memory type for VMCS accesses. */
4648         if (((vmx_msr_high >> 18) & 15) != 6)
4649                 return -EIO;
4650
4651         vmcs_conf->size = vmx_msr_high & 0x1fff;
4652         vmcs_conf->order = get_order(vmcs_conf->size);
4653         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
4654
4655         vmcs_conf->revision_id = vmx_msr_low;
4656
4657         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
4658         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
4659         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
4660         vmcs_conf->vmexit_ctrl         = _vmexit_control;
4661         vmcs_conf->vmentry_ctrl        = _vmentry_control;
4662
4663         if (static_branch_unlikely(&enable_evmcs))
4664                 evmcs_sanitize_exec_ctrls(vmcs_conf);
4665
4666         cpu_has_load_ia32_efer =
4667                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4668                                 VM_ENTRY_LOAD_IA32_EFER)
4669                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4670                                    VM_EXIT_LOAD_IA32_EFER);
4671
4672         cpu_has_load_perf_global_ctrl =
4673                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4674                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
4675                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4676                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
4677
4678         /*
4679          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
4680          * but due to errata below it can't be used. Workaround is to use
4681          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
4682          *
4683          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
4684          *
4685          * AAK155             (model 26)
4686          * AAP115             (model 30)
4687          * AAT100             (model 37)
4688          * BC86,AAY89,BD102   (model 44)
4689          * BA97               (model 46)
4690          *
4691          */
4692         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
4693                 switch (boot_cpu_data.x86_model) {
4694                 case 26:
4695                 case 30:
4696                 case 37:
4697                 case 44:
4698                 case 46:
4699                         cpu_has_load_perf_global_ctrl = false;
4700                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
4701                                         "does not work properly. Using workaround\n");
4702                         break;
4703                 default:
4704                         break;
4705                 }
4706         }
4707
4708         if (boot_cpu_has(X86_FEATURE_XSAVES))
4709                 rdmsrl(MSR_IA32_XSS, host_xss);
4710
4711         return 0;
4712 }
4713
4714 static struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu)
4715 {
4716         int node = cpu_to_node(cpu);
4717         struct page *pages;
4718         struct vmcs *vmcs;
4719
4720         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
4721         if (!pages)
4722                 return NULL;
4723         vmcs = page_address(pages);
4724         memset(vmcs, 0, vmcs_config.size);
4725
4726         /* KVM supports Enlightened VMCS v1 only */
4727         if (static_branch_unlikely(&enable_evmcs))
4728                 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
4729         else
4730                 vmcs->hdr.revision_id = vmcs_config.revision_id;
4731
4732         if (shadow)
4733                 vmcs->hdr.shadow_vmcs = 1;
4734         return vmcs;
4735 }
4736
4737 static void free_vmcs(struct vmcs *vmcs)
4738 {
4739         free_pages((unsigned long)vmcs, vmcs_config.order);
4740 }
4741
4742 /*
4743  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
4744  */
4745 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4746 {
4747         if (!loaded_vmcs->vmcs)
4748                 return;
4749         loaded_vmcs_clear(loaded_vmcs);
4750         free_vmcs(loaded_vmcs->vmcs);
4751         loaded_vmcs->vmcs = NULL;
4752         if (loaded_vmcs->msr_bitmap)
4753                 free_page((unsigned long)loaded_vmcs->msr_bitmap);
4754         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
4755 }
4756
4757 static struct vmcs *alloc_vmcs(bool shadow)
4758 {
4759         return alloc_vmcs_cpu(shadow, raw_smp_processor_id());
4760 }
4761
4762 static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4763 {
4764         loaded_vmcs->vmcs = alloc_vmcs(false);
4765         if (!loaded_vmcs->vmcs)
4766                 return -ENOMEM;
4767
4768         loaded_vmcs->shadow_vmcs = NULL;
4769         loaded_vmcs_init(loaded_vmcs);
4770
4771         if (cpu_has_vmx_msr_bitmap()) {
4772                 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
4773                 if (!loaded_vmcs->msr_bitmap)
4774                         goto out_vmcs;
4775                 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
4776
4777                 if (IS_ENABLED(CONFIG_HYPERV) &&
4778                     static_branch_unlikely(&enable_evmcs) &&
4779                     (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
4780                         struct hv_enlightened_vmcs *evmcs =
4781                                 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
4782
4783                         evmcs->hv_enlightenments_control.msr_bitmap = 1;
4784                 }
4785         }
4786
4787         memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
4788
4789         return 0;
4790
4791 out_vmcs:
4792         free_loaded_vmcs(loaded_vmcs);
4793         return -ENOMEM;
4794 }
4795
4796 static void free_kvm_area(void)
4797 {
4798         int cpu;
4799
4800         for_each_possible_cpu(cpu) {
4801                 free_vmcs(per_cpu(vmxarea, cpu));
4802                 per_cpu(vmxarea, cpu) = NULL;
4803         }
4804 }
4805
4806 enum vmcs_field_width {
4807         VMCS_FIELD_WIDTH_U16 = 0,
4808         VMCS_FIELD_WIDTH_U64 = 1,
4809         VMCS_FIELD_WIDTH_U32 = 2,
4810         VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
4811 };
4812
4813 static inline int vmcs_field_width(unsigned long field)
4814 {
4815         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
4816                 return VMCS_FIELD_WIDTH_U32;
4817         return (field >> 13) & 0x3 ;
4818 }
4819
4820 static inline int vmcs_field_readonly(unsigned long field)
4821 {
4822         return (((field >> 10) & 0x3) == 1);
4823 }
4824
4825 static void init_vmcs_shadow_fields(void)
4826 {
4827         int i, j;
4828
4829         for (i = j = 0; i < max_shadow_read_only_fields; i++) {
4830                 u16 field = shadow_read_only_fields[i];
4831                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4832                     (i + 1 == max_shadow_read_only_fields ||
4833                      shadow_read_only_fields[i + 1] != field + 1))
4834                         pr_err("Missing field from shadow_read_only_field %x\n",
4835                                field + 1);
4836
4837                 clear_bit(field, vmx_vmread_bitmap);
4838 #ifdef CONFIG_X86_64
4839                 if (field & 1)
4840                         continue;
4841 #endif
4842                 if (j < i)
4843                         shadow_read_only_fields[j] = field;
4844                 j++;
4845         }
4846         max_shadow_read_only_fields = j;
4847
4848         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
4849                 u16 field = shadow_read_write_fields[i];
4850                 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4851                     (i + 1 == max_shadow_read_write_fields ||
4852                      shadow_read_write_fields[i + 1] != field + 1))
4853                         pr_err("Missing field from shadow_read_write_field %x\n",
4854                                field + 1);
4855
4856                 /*
4857                  * PML and the preemption timer can be emulated, but the
4858                  * processor cannot vmwrite to fields that don't exist
4859                  * on bare metal.
4860                  */
4861                 switch (field) {
4862                 case GUEST_PML_INDEX:
4863                         if (!cpu_has_vmx_pml())
4864                                 continue;
4865                         break;
4866                 case VMX_PREEMPTION_TIMER_VALUE:
4867                         if (!cpu_has_vmx_preemption_timer())
4868                                 continue;
4869                         break;
4870                 case GUEST_INTR_STATUS:
4871                         if (!cpu_has_vmx_apicv())
4872                                 continue;
4873                         break;
4874                 default:
4875                         break;
4876                 }
4877
4878                 clear_bit(field, vmx_vmwrite_bitmap);
4879                 clear_bit(field, vmx_vmread_bitmap);
4880 #ifdef CONFIG_X86_64
4881                 if (field & 1)
4882                         continue;
4883 #endif
4884                 if (j < i)
4885                         shadow_read_write_fields[j] = field;
4886                 j++;
4887         }
4888         max_shadow_read_write_fields = j;
4889 }
4890
4891 static __init int alloc_kvm_area(void)
4892 {
4893         int cpu;
4894
4895         for_each_possible_cpu(cpu) {
4896                 struct vmcs *vmcs;
4897
4898                 vmcs = alloc_vmcs_cpu(false, cpu);
4899                 if (!vmcs) {
4900                         free_kvm_area();
4901                         return -ENOMEM;
4902                 }
4903
4904                 /*
4905                  * When eVMCS is enabled, alloc_vmcs_cpu() sets
4906                  * vmcs->revision_id to KVM_EVMCS_VERSION instead of
4907                  * revision_id reported by MSR_IA32_VMX_BASIC.
4908                  *
4909                  * However, even though not explictly documented by
4910                  * TLFS, VMXArea passed as VMXON argument should
4911                  * still be marked with revision_id reported by
4912                  * physical CPU.
4913                  */
4914                 if (static_branch_unlikely(&enable_evmcs))
4915                         vmcs->hdr.revision_id = vmcs_config.revision_id;
4916
4917                 per_cpu(vmxarea, cpu) = vmcs;
4918         }
4919         return 0;
4920 }
4921
4922 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
4923                 struct kvm_segment *save)
4924 {
4925         if (!emulate_invalid_guest_state) {
4926                 /*
4927                  * CS and SS RPL should be equal during guest entry according
4928                  * to VMX spec, but in reality it is not always so. Since vcpu
4929                  * is in the middle of the transition from real mode to
4930                  * protected mode it is safe to assume that RPL 0 is a good
4931                  * default value.
4932                  */
4933                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4934                         save->selector &= ~SEGMENT_RPL_MASK;
4935                 save->dpl = save->selector & SEGMENT_RPL_MASK;
4936                 save->s = 1;
4937         }
4938         vmx_set_segment(vcpu, save, seg);
4939 }
4940
4941 static void enter_pmode(struct kvm_vcpu *vcpu)
4942 {
4943         unsigned long flags;
4944         struct vcpu_vmx *vmx = to_vmx(vcpu);
4945
4946         /*
4947          * Update real mode segment cache. It may be not up-to-date if sement
4948          * register was written while vcpu was in a guest mode.
4949          */
4950         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4951         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4952         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4953         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4954         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4955         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4956
4957         vmx->rmode.vm86_active = 0;
4958
4959         vmx_segment_cache_clear(vmx);
4960
4961         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4962
4963         flags = vmcs_readl(GUEST_RFLAGS);
4964         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
4965         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
4966         vmcs_writel(GUEST_RFLAGS, flags);
4967
4968         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
4969                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4970
4971         update_exception_bitmap(vcpu);
4972
4973         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4974         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4975         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4976         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4977         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4978         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4979 }
4980
4981 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4982 {
4983         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4984         struct kvm_segment var = *save;
4985
4986         var.dpl = 0x3;
4987         if (seg == VCPU_SREG_CS)
4988                 var.type = 0x3;
4989
4990         if (!emulate_invalid_guest_state) {
4991                 var.selector = var.base >> 4;
4992                 var.base = var.base & 0xffff0;
4993                 var.limit = 0xffff;
4994                 var.g = 0;
4995                 var.db = 0;
4996                 var.present = 1;
4997                 var.s = 1;
4998                 var.l = 0;
4999                 var.unusable = 0;
5000                 var.type = 0x3;
5001                 var.avl = 0;
5002                 if (save->base & 0xf)
5003                         printk_once(KERN_WARNING "kvm: segment base is not "
5004                                         "paragraph aligned when entering "
5005                                         "protected mode (seg=%d)", seg);
5006         }
5007
5008         vmcs_write16(sf->selector, var.selector);
5009         vmcs_writel(sf->base, var.base);
5010         vmcs_write32(sf->limit, var.limit);
5011         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
5012 }
5013
5014 static void enter_rmode(struct kvm_vcpu *vcpu)
5015 {
5016         unsigned long flags;
5017         struct vcpu_vmx *vmx = to_vmx(vcpu);
5018         struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
5019
5020         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
5021         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
5022         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
5023         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
5024         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
5025         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
5026         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
5027
5028         vmx->rmode.vm86_active = 1;
5029
5030         /*
5031          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
5032          * vcpu. Warn the user that an update is overdue.
5033          */
5034         if (!kvm_vmx->tss_addr)
5035                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
5036                              "called before entering vcpu\n");
5037
5038         vmx_segment_cache_clear(vmx);
5039
5040         vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
5041         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
5042         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5043
5044         flags = vmcs_readl(GUEST_RFLAGS);
5045         vmx->rmode.save_rflags = flags;
5046
5047         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
5048
5049         vmcs_writel(GUEST_RFLAGS, flags);
5050         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
5051         update_exception_bitmap(vcpu);
5052
5053         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
5054         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
5055         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
5056         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
5057         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
5058         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
5059
5060         kvm_mmu_reset_context(vcpu);
5061 }
5062
5063 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
5064 {
5065         struct vcpu_vmx *vmx = to_vmx(vcpu);
5066         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
5067
5068         if (!msr)
5069                 return;
5070
5071         vcpu->arch.efer = efer;
5072         if (efer & EFER_LMA) {
5073                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
5074                 msr->data = efer;
5075         } else {
5076                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
5077
5078                 msr->data = efer & ~EFER_LME;
5079         }
5080         setup_msrs(vmx);
5081 }
5082
5083 #ifdef CONFIG_X86_64
5084
5085 static void enter_lmode(struct kvm_vcpu *vcpu)
5086 {
5087         u32 guest_tr_ar;
5088
5089         vmx_segment_cache_clear(to_vmx(vcpu));
5090
5091         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
5092         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
5093                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
5094                                      __func__);
5095                 vmcs_write32(GUEST_TR_AR_BYTES,
5096                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
5097                              | VMX_AR_TYPE_BUSY_64_TSS);
5098         }
5099         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
5100 }
5101
5102 static void exit_lmode(struct kvm_vcpu *vcpu)
5103 {
5104         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
5105         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
5106 }
5107
5108 #endif
5109
5110 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
5111                                 bool invalidate_gpa)
5112 {
5113         if (enable_ept && (invalidate_gpa || !enable_vpid)) {
5114                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
5115                         return;
5116                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
5117         } else {
5118                 vpid_sync_context(vpid);
5119         }
5120 }
5121
5122 static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5123 {
5124         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
5125 }
5126
5127 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
5128 {
5129         int vpid = to_vmx(vcpu)->vpid;
5130
5131         if (!vpid_sync_vcpu_addr(vpid, addr))
5132                 vpid_sync_context(vpid);
5133
5134         /*
5135          * If VPIDs are not supported or enabled, then the above is a no-op.
5136          * But we don't really need a TLB flush in that case anyway, because
5137          * each VM entry/exit includes an implicit flush when VPID is 0.
5138          */
5139 }
5140
5141 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
5142 {
5143         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
5144
5145         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
5146         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
5147 }
5148
5149 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
5150 {
5151         if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
5152                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
5153         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
5154 }
5155
5156 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
5157 {
5158         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
5159
5160         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
5161         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
5162 }
5163
5164 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
5165 {
5166         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
5167
5168         if (!test_bit(VCPU_EXREG_PDPTR,
5169                       (unsigned long *)&vcpu->arch.regs_dirty))
5170                 return;
5171
5172         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
5173                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
5174                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
5175                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
5176                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
5177         }
5178 }
5179
5180 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
5181 {
5182         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
5183
5184         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
5185                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
5186                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
5187                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
5188                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
5189         }
5190
5191         __set_bit(VCPU_EXREG_PDPTR,
5192                   (unsigned long *)&vcpu->arch.regs_avail);
5193         __set_bit(VCPU_EXREG_PDPTR,
5194                   (unsigned long *)&vcpu->arch.regs_dirty);
5195 }
5196
5197 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5198 {
5199         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
5200         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
5201         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5202
5203         if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
5204                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5205             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5206                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5207
5208         return fixed_bits_valid(val, fixed0, fixed1);
5209 }
5210
5211 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5212 {
5213         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
5214         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
5215
5216         return fixed_bits_valid(val, fixed0, fixed1);
5217 }
5218
5219 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
5220 {
5221         u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0;
5222         u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1;
5223
5224         return fixed_bits_valid(val, fixed0, fixed1);
5225 }
5226
5227 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
5228 #define nested_guest_cr4_valid  nested_cr4_valid
5229 #define nested_host_cr4_valid   nested_cr4_valid
5230
5231 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
5232
5233 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
5234                                         unsigned long cr0,
5235                                         struct kvm_vcpu *vcpu)
5236 {
5237         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
5238                 vmx_decache_cr3(vcpu);
5239         if (!(cr0 & X86_CR0_PG)) {
5240                 /* From paging/starting to nonpaging */
5241                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
5242                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
5243                              (CPU_BASED_CR3_LOAD_EXITING |
5244                               CPU_BASED_CR3_STORE_EXITING));
5245                 vcpu->arch.cr0 = cr0;
5246                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
5247         } else if (!is_paging(vcpu)) {
5248                 /* From nonpaging to paging */
5249                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
5250                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
5251                              ~(CPU_BASED_CR3_LOAD_EXITING |
5252                                CPU_BASED_CR3_STORE_EXITING));
5253                 vcpu->arch.cr0 = cr0;
5254                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
5255         }
5256
5257         if (!(cr0 & X86_CR0_WP))
5258                 *hw_cr0 &= ~X86_CR0_WP;
5259 }
5260
5261 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
5262 {
5263         struct vcpu_vmx *vmx = to_vmx(vcpu);
5264         unsigned long hw_cr0;
5265
5266         hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
5267         if (enable_unrestricted_guest)
5268                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
5269         else {
5270                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
5271
5272                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
5273                         enter_pmode(vcpu);
5274
5275                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
5276                         enter_rmode(vcpu);
5277         }
5278
5279 #ifdef CONFIG_X86_64
5280         if (vcpu->arch.efer & EFER_LME) {
5281                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
5282                         enter_lmode(vcpu);
5283                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
5284                         exit_lmode(vcpu);
5285         }
5286 #endif
5287
5288         if (enable_ept && !enable_unrestricted_guest)
5289                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
5290
5291         vmcs_writel(CR0_READ_SHADOW, cr0);
5292         vmcs_writel(GUEST_CR0, hw_cr0);
5293         vcpu->arch.cr0 = cr0;
5294
5295         /* depends on vcpu->arch.cr0 to be set to a new value */
5296         vmx->emulation_required = emulation_required(vcpu);
5297 }
5298
5299 static int get_ept_level(struct kvm_vcpu *vcpu)
5300 {
5301         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
5302                 return 5;
5303         return 4;
5304 }
5305
5306 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
5307 {
5308         u64 eptp = VMX_EPTP_MT_WB;
5309
5310         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
5311
5312         if (enable_ept_ad_bits &&
5313             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
5314                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
5315         eptp |= (root_hpa & PAGE_MASK);
5316
5317         return eptp;
5318 }
5319
5320 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
5321 {
5322         struct kvm *kvm = vcpu->kvm;
5323         unsigned long guest_cr3;
5324         u64 eptp;
5325
5326         guest_cr3 = cr3;
5327         if (enable_ept) {
5328                 eptp = construct_eptp(vcpu, cr3);
5329                 vmcs_write64(EPT_POINTER, eptp);
5330
5331                 if (kvm_x86_ops->tlb_remote_flush) {
5332                         spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
5333                         to_vmx(vcpu)->ept_pointer = eptp;
5334                         to_kvm_vmx(kvm)->ept_pointers_match
5335                                 = EPT_POINTERS_CHECK;
5336                         spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
5337                 }
5338
5339                 if (enable_unrestricted_guest || is_paging(vcpu) ||
5340                     is_guest_mode(vcpu))
5341                         guest_cr3 = kvm_read_cr3(vcpu);
5342                 else
5343                         guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
5344                 ept_load_pdptrs(vcpu);
5345         }
5346
5347         vmcs_writel(GUEST_CR3, guest_cr3);
5348 }
5349
5350 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
5351 {
5352         /*
5353          * Pass through host's Machine Check Enable value to hw_cr4, which
5354          * is in force while we are in guest mode.  Do not let guests control
5355          * this bit, even if host CR4.MCE == 0.
5356          */
5357         unsigned long hw_cr4;
5358
5359         hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
5360         if (enable_unrestricted_guest)
5361                 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
5362         else if (to_vmx(vcpu)->rmode.vm86_active)
5363                 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
5364         else
5365                 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
5366
5367         if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
5368                 if (cr4 & X86_CR4_UMIP) {
5369                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5370                                 SECONDARY_EXEC_DESC);
5371                         hw_cr4 &= ~X86_CR4_UMIP;
5372                 } else if (!is_guest_mode(vcpu) ||
5373                         !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
5374                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5375                                         SECONDARY_EXEC_DESC);
5376         }
5377
5378         if (cr4 & X86_CR4_VMXE) {
5379                 /*
5380                  * To use VMXON (and later other VMX instructions), a guest
5381                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
5382                  * So basically the check on whether to allow nested VMX
5383                  * is here.  We operate under the default treatment of SMM,
5384                  * so VMX cannot be enabled under SMM.
5385                  */
5386                 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
5387                         return 1;
5388         }
5389
5390         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5391                 return 1;
5392
5393         vcpu->arch.cr4 = cr4;
5394
5395         if (!enable_unrestricted_guest) {
5396                 if (enable_ept) {
5397                         if (!is_paging(vcpu)) {
5398                                 hw_cr4 &= ~X86_CR4_PAE;
5399                                 hw_cr4 |= X86_CR4_PSE;
5400                         } else if (!(cr4 & X86_CR4_PAE)) {
5401                                 hw_cr4 &= ~X86_CR4_PAE;
5402                         }
5403                 }
5404
5405                 /*
5406                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
5407                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
5408                  * to be manually disabled when guest switches to non-paging
5409                  * mode.
5410                  *
5411                  * If !enable_unrestricted_guest, the CPU is always running
5412                  * with CR0.PG=1 and CR4 needs to be modified.
5413                  * If enable_unrestricted_guest, the CPU automatically
5414                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
5415                  */
5416                 if (!is_paging(vcpu))
5417                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
5418         }
5419
5420         vmcs_writel(CR4_READ_SHADOW, cr4);
5421         vmcs_writel(GUEST_CR4, hw_cr4);
5422         return 0;
5423 }
5424
5425 static void vmx_get_segment(struct kvm_vcpu *vcpu,
5426                             struct kvm_segment *var, int seg)
5427 {
5428         struct vcpu_vmx *vmx = to_vmx(vcpu);
5429         u32 ar;
5430
5431         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5432                 *var = vmx->rmode.segs[seg];
5433                 if (seg == VCPU_SREG_TR
5434                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
5435                         return;
5436                 var->base = vmx_read_guest_seg_base(vmx, seg);
5437                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
5438                 return;
5439         }
5440         var->base = vmx_read_guest_seg_base(vmx, seg);
5441         var->limit = vmx_read_guest_seg_limit(vmx, seg);
5442         var->selector = vmx_read_guest_seg_selector(vmx, seg);
5443         ar = vmx_read_guest_seg_ar(vmx, seg);
5444         var->unusable = (ar >> 16) & 1;
5445         var->type = ar & 15;
5446         var->s = (ar >> 4) & 1;
5447         var->dpl = (ar >> 5) & 3;
5448         /*
5449          * Some userspaces do not preserve unusable property. Since usable
5450          * segment has to be present according to VMX spec we can use present
5451          * property to amend userspace bug by making unusable segment always
5452          * nonpresent. vmx_segment_access_rights() already marks nonpresent
5453          * segment as unusable.
5454          */
5455         var->present = !var->unusable;
5456         var->avl = (ar >> 12) & 1;
5457         var->l = (ar >> 13) & 1;
5458         var->db = (ar >> 14) & 1;
5459         var->g = (ar >> 15) & 1;
5460 }
5461
5462 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
5463 {
5464         struct kvm_segment s;
5465
5466         if (to_vmx(vcpu)->rmode.vm86_active) {
5467                 vmx_get_segment(vcpu, &s, seg);
5468                 return s.base;
5469         }
5470         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
5471 }
5472
5473 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
5474 {
5475         struct vcpu_vmx *vmx = to_vmx(vcpu);
5476
5477         if (unlikely(vmx->rmode.vm86_active))
5478                 return 0;
5479         else {
5480                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
5481                 return VMX_AR_DPL(ar);
5482         }
5483 }
5484
5485 static u32 vmx_segment_access_rights(struct kvm_segment *var)
5486 {
5487         u32 ar;
5488
5489         if (var->unusable || !var->present)
5490                 ar = 1 << 16;
5491         else {
5492                 ar = var->type & 15;
5493                 ar |= (var->s & 1) << 4;
5494                 ar |= (var->dpl & 3) << 5;
5495                 ar |= (var->present & 1) << 7;
5496                 ar |= (var->avl & 1) << 12;
5497                 ar |= (var->l & 1) << 13;
5498                 ar |= (var->db & 1) << 14;
5499                 ar |= (var->g & 1) << 15;
5500         }
5501
5502         return ar;
5503 }
5504
5505 static void vmx_set_segment(struct kvm_vcpu *vcpu,
5506                             struct kvm_segment *var, int seg)
5507 {
5508         struct vcpu_vmx *vmx = to_vmx(vcpu);
5509         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5510
5511         vmx_segment_cache_clear(vmx);
5512
5513         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5514                 vmx->rmode.segs[seg] = *var;
5515                 if (seg == VCPU_SREG_TR)
5516                         vmcs_write16(sf->selector, var->selector);
5517                 else if (var->s)
5518                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
5519                 goto out;
5520         }
5521
5522         vmcs_writel(sf->base, var->base);
5523         vmcs_write32(sf->limit, var->limit);
5524         vmcs_write16(sf->selector, var->selector);
5525
5526         /*
5527          *   Fix the "Accessed" bit in AR field of segment registers for older
5528          * qemu binaries.
5529          *   IA32 arch specifies that at the time of processor reset the
5530          * "Accessed" bit in the AR field of segment registers is 1. And qemu
5531          * is setting it to 0 in the userland code. This causes invalid guest
5532          * state vmexit when "unrestricted guest" mode is turned on.
5533          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
5534          * tree. Newer qemu binaries with that qemu fix would not need this
5535          * kvm hack.
5536          */
5537         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
5538                 var->type |= 0x1; /* Accessed */
5539
5540         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
5541
5542 out:
5543         vmx->emulation_required = emulation_required(vcpu);
5544 }
5545
5546 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5547 {
5548         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
5549
5550         *db = (ar >> 14) & 1;
5551         *l = (ar >> 13) & 1;
5552 }
5553
5554 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5555 {
5556         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
5557         dt->address = vmcs_readl(GUEST_IDTR_BASE);
5558 }
5559
5560 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5561 {
5562         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
5563         vmcs_writel(GUEST_IDTR_BASE, dt->address);
5564 }
5565
5566 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5567 {
5568         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
5569         dt->address = vmcs_readl(GUEST_GDTR_BASE);
5570 }
5571
5572 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5573 {
5574         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
5575         vmcs_writel(GUEST_GDTR_BASE, dt->address);
5576 }
5577
5578 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
5579 {
5580         struct kvm_segment var;
5581         u32 ar;
5582
5583         vmx_get_segment(vcpu, &var, seg);
5584         var.dpl = 0x3;
5585         if (seg == VCPU_SREG_CS)
5586                 var.type = 0x3;
5587         ar = vmx_segment_access_rights(&var);
5588
5589         if (var.base != (var.selector << 4))
5590                 return false;
5591         if (var.limit != 0xffff)
5592                 return false;
5593         if (ar != 0xf3)
5594                 return false;
5595
5596         return true;
5597 }
5598
5599 static bool code_segment_valid(struct kvm_vcpu *vcpu)
5600 {
5601         struct kvm_segment cs;
5602         unsigned int cs_rpl;
5603
5604         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5605         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
5606
5607         if (cs.unusable)
5608                 return false;
5609         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
5610                 return false;
5611         if (!cs.s)
5612                 return false;
5613         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
5614                 if (cs.dpl > cs_rpl)
5615                         return false;
5616         } else {
5617                 if (cs.dpl != cs_rpl)
5618                         return false;
5619         }
5620         if (!cs.present)
5621                 return false;
5622
5623         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
5624         return true;
5625 }
5626
5627 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
5628 {
5629         struct kvm_segment ss;
5630         unsigned int ss_rpl;
5631
5632         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5633         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
5634
5635         if (ss.unusable)
5636                 return true;
5637         if (ss.type != 3 && ss.type != 7)
5638                 return false;
5639         if (!ss.s)
5640                 return false;
5641         if (ss.dpl != ss_rpl) /* DPL != RPL */
5642                 return false;
5643         if (!ss.present)
5644                 return false;
5645
5646         return true;
5647 }
5648
5649 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
5650 {
5651         struct kvm_segment var;
5652         unsigned int rpl;
5653
5654         vmx_get_segment(vcpu, &var, seg);
5655         rpl = var.selector & SEGMENT_RPL_MASK;
5656
5657         if (var.unusable)
5658                 return true;
5659         if (!var.s)
5660                 return false;
5661         if (!var.present)
5662                 return false;
5663         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
5664                 if (var.dpl < rpl) /* DPL < RPL */
5665                         return false;
5666         }
5667
5668         /* TODO: Add other members to kvm_segment_field to allow checking for other access
5669          * rights flags
5670          */
5671         return true;
5672 }
5673
5674 static bool tr_valid(struct kvm_vcpu *vcpu)
5675 {
5676         struct kvm_segment tr;
5677
5678         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
5679
5680         if (tr.unusable)
5681                 return false;
5682         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
5683                 return false;
5684         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
5685                 return false;
5686         if (!tr.present)
5687                 return false;
5688
5689         return true;
5690 }
5691
5692 static bool ldtr_valid(struct kvm_vcpu *vcpu)
5693 {
5694         struct kvm_segment ldtr;
5695
5696         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
5697
5698         if (ldtr.unusable)
5699                 return true;
5700         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
5701                 return false;
5702         if (ldtr.type != 2)
5703                 return false;
5704         if (!ldtr.present)
5705                 return false;
5706
5707         return true;
5708 }
5709
5710 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
5711 {
5712         struct kvm_segment cs, ss;
5713
5714         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5715         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5716
5717         return ((cs.selector & SEGMENT_RPL_MASK) ==
5718                  (ss.selector & SEGMENT_RPL_MASK));
5719 }
5720
5721 /*
5722  * Check if guest state is valid. Returns true if valid, false if
5723  * not.
5724  * We assume that registers are always usable
5725  */
5726 static bool guest_state_valid(struct kvm_vcpu *vcpu)
5727 {
5728         if (enable_unrestricted_guest)
5729                 return true;
5730
5731         /* real mode guest state checks */
5732         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5733                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
5734                         return false;
5735                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
5736                         return false;
5737                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
5738                         return false;
5739                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
5740                         return false;
5741                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
5742                         return false;
5743                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
5744                         return false;
5745         } else {
5746         /* protected mode guest state checks */
5747                 if (!cs_ss_rpl_check(vcpu))
5748                         return false;
5749                 if (!code_segment_valid(vcpu))
5750                         return false;
5751                 if (!stack_segment_valid(vcpu))
5752                         return false;
5753                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
5754                         return false;
5755                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
5756                         return false;
5757                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
5758                         return false;
5759                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
5760                         return false;
5761                 if (!tr_valid(vcpu))
5762                         return false;
5763                 if (!ldtr_valid(vcpu))
5764                         return false;
5765         }
5766         /* TODO:
5767          * - Add checks on RIP
5768          * - Add checks on RFLAGS
5769          */
5770
5771         return true;
5772 }
5773
5774 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
5775 {
5776         return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
5777 }
5778
5779 static int init_rmode_tss(struct kvm *kvm)
5780 {
5781         gfn_t fn;
5782         u16 data = 0;
5783         int idx, r;
5784
5785         idx = srcu_read_lock(&kvm->srcu);
5786         fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
5787         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5788         if (r < 0)
5789                 goto out;
5790         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
5791         r = kvm_write_guest_page(kvm, fn++, &data,
5792                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
5793         if (r < 0)
5794                 goto out;
5795         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
5796         if (r < 0)
5797                 goto out;
5798         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5799         if (r < 0)
5800                 goto out;
5801         data = ~0;
5802         r = kvm_write_guest_page(kvm, fn, &data,
5803                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
5804                                  sizeof(u8));
5805 out:
5806         srcu_read_unlock(&kvm->srcu, idx);
5807         return r;
5808 }
5809
5810 static int init_rmode_identity_map(struct kvm *kvm)
5811 {
5812         struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
5813         int i, idx, r = 0;
5814         kvm_pfn_t identity_map_pfn;
5815         u32 tmp;
5816
5817         /* Protect kvm_vmx->ept_identity_pagetable_done. */
5818         mutex_lock(&kvm->slots_lock);
5819
5820         if (likely(kvm_vmx->ept_identity_pagetable_done))
5821                 goto out2;
5822
5823         if (!kvm_vmx->ept_identity_map_addr)
5824                 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
5825         identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
5826
5827         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
5828                                     kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
5829         if (r < 0)
5830                 goto out2;
5831
5832         idx = srcu_read_lock(&kvm->srcu);
5833         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
5834         if (r < 0)
5835                 goto out;
5836         /* Set up identity-mapping pagetable for EPT in real mode */
5837         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
5838                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
5839                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
5840                 r = kvm_write_guest_page(kvm, identity_map_pfn,
5841                                 &tmp, i * sizeof(tmp), sizeof(tmp));
5842                 if (r < 0)
5843                         goto out;
5844         }
5845         kvm_vmx->ept_identity_pagetable_done = true;
5846
5847 out:
5848         srcu_read_unlock(&kvm->srcu, idx);
5849
5850 out2:
5851         mutex_unlock(&kvm->slots_lock);
5852         return r;
5853 }
5854
5855 static void seg_setup(int seg)
5856 {
5857         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5858         unsigned int ar;
5859
5860         vmcs_write16(sf->selector, 0);
5861         vmcs_writel(sf->base, 0);
5862         vmcs_write32(sf->limit, 0xffff);
5863         ar = 0x93;
5864         if (seg == VCPU_SREG_CS)
5865                 ar |= 0x08; /* code segment */
5866
5867         vmcs_write32(sf->ar_bytes, ar);
5868 }
5869
5870 static int alloc_apic_access_page(struct kvm *kvm)
5871 {
5872         struct page *page;
5873         int r = 0;
5874
5875         mutex_lock(&kvm->slots_lock);
5876         if (kvm->arch.apic_access_page_done)
5877                 goto out;
5878         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
5879                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
5880         if (r)
5881                 goto out;
5882
5883         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
5884         if (is_error_page(page)) {
5885                 r = -EFAULT;
5886                 goto out;
5887         }
5888
5889         /*
5890          * Do not pin the page in memory, so that memory hot-unplug
5891          * is able to migrate it.
5892          */
5893         put_page(page);
5894         kvm->arch.apic_access_page_done = true;
5895 out:
5896         mutex_unlock(&kvm->slots_lock);
5897         return r;
5898 }
5899
5900 static int allocate_vpid(void)
5901 {
5902         int vpid;
5903
5904         if (!enable_vpid)
5905                 return 0;
5906         spin_lock(&vmx_vpid_lock);
5907         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
5908         if (vpid < VMX_NR_VPIDS)
5909                 __set_bit(vpid, vmx_vpid_bitmap);
5910         else
5911                 vpid = 0;
5912         spin_unlock(&vmx_vpid_lock);
5913         return vpid;
5914 }
5915
5916 static void free_vpid(int vpid)
5917 {
5918         if (!enable_vpid || vpid == 0)
5919                 return;
5920         spin_lock(&vmx_vpid_lock);
5921         __clear_bit(vpid, vmx_vpid_bitmap);
5922         spin_unlock(&vmx_vpid_lock);
5923 }
5924
5925 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
5926                                                           u32 msr, int type)
5927 {
5928         int f = sizeof(unsigned long);
5929
5930         if (!cpu_has_vmx_msr_bitmap())
5931                 return;
5932
5933         if (static_branch_unlikely(&enable_evmcs))
5934                 evmcs_touch_msr_bitmap();
5935
5936         /*
5937          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5938          * have the write-low and read-high bitmap offsets the wrong way round.
5939          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5940          */
5941         if (msr <= 0x1fff) {
5942                 if (type & MSR_TYPE_R)
5943                         /* read-low */
5944                         __clear_bit(msr, msr_bitmap + 0x000 / f);
5945
5946                 if (type & MSR_TYPE_W)
5947                         /* write-low */
5948                         __clear_bit(msr, msr_bitmap + 0x800 / f);
5949
5950         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5951                 msr &= 0x1fff;
5952                 if (type & MSR_TYPE_R)
5953                         /* read-high */
5954                         __clear_bit(msr, msr_bitmap + 0x400 / f);
5955
5956                 if (type & MSR_TYPE_W)
5957                         /* write-high */
5958                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
5959
5960         }
5961 }
5962
5963 static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
5964                                                          u32 msr, int type)
5965 {
5966         int f = sizeof(unsigned long);
5967
5968         if (!cpu_has_vmx_msr_bitmap())
5969                 return;
5970
5971         if (static_branch_unlikely(&enable_evmcs))
5972                 evmcs_touch_msr_bitmap();
5973
5974         /*
5975          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5976          * have the write-low and read-high bitmap offsets the wrong way round.
5977          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5978          */
5979         if (msr <= 0x1fff) {
5980                 if (type & MSR_TYPE_R)
5981                         /* read-low */
5982                         __set_bit(msr, msr_bitmap + 0x000 / f);
5983
5984                 if (type & MSR_TYPE_W)
5985                         /* write-low */
5986                         __set_bit(msr, msr_bitmap + 0x800 / f);
5987
5988         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5989                 msr &= 0x1fff;
5990                 if (type & MSR_TYPE_R)
5991                         /* read-high */
5992                         __set_bit(msr, msr_bitmap + 0x400 / f);
5993
5994                 if (type & MSR_TYPE_W)
5995                         /* write-high */
5996                         __set_bit(msr, msr_bitmap + 0xc00 / f);
5997
5998         }
5999 }
6000
6001 static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
6002                                                       u32 msr, int type, bool value)
6003 {
6004         if (value)
6005                 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
6006         else
6007                 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
6008 }
6009
6010 /*
6011  * If a msr is allowed by L0, we should check whether it is allowed by L1.
6012  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
6013  */
6014 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
6015                                                unsigned long *msr_bitmap_nested,
6016                                                u32 msr, int type)
6017 {
6018         int f = sizeof(unsigned long);
6019
6020         /*
6021          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
6022          * have the write-low and read-high bitmap offsets the wrong way round.
6023          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
6024          */
6025         if (msr <= 0x1fff) {
6026                 if (type & MSR_TYPE_R &&
6027                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
6028                         /* read-low */
6029                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
6030
6031                 if (type & MSR_TYPE_W &&
6032                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
6033                         /* write-low */
6034                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
6035
6036         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
6037                 msr &= 0x1fff;
6038                 if (type & MSR_TYPE_R &&
6039                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
6040                         /* read-high */
6041                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
6042
6043                 if (type & MSR_TYPE_W &&
6044                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
6045                         /* write-high */
6046                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
6047
6048         }
6049 }
6050
6051 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
6052 {
6053         u8 mode = 0;
6054
6055         if (cpu_has_secondary_exec_ctrls() &&
6056             (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
6057              SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
6058                 mode |= MSR_BITMAP_MODE_X2APIC;
6059                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
6060                         mode |= MSR_BITMAP_MODE_X2APIC_APICV;
6061         }
6062
6063         return mode;
6064 }
6065
6066 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
6067
6068 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
6069                                          u8 mode)
6070 {
6071         int msr;
6072
6073         for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
6074                 unsigned word = msr / BITS_PER_LONG;
6075                 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
6076                 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
6077         }
6078
6079         if (mode & MSR_BITMAP_MODE_X2APIC) {
6080                 /*
6081                  * TPR reads and writes can be virtualized even if virtual interrupt
6082                  * delivery is not in use.
6083                  */
6084                 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
6085                 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
6086                         vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
6087                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
6088                         vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
6089                 }
6090         }
6091 }
6092
6093 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
6094 {
6095         struct vcpu_vmx *vmx = to_vmx(vcpu);
6096         unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
6097         u8 mode = vmx_msr_bitmap_mode(vcpu);
6098         u8 changed = mode ^ vmx->msr_bitmap_mode;
6099
6100         if (!changed)
6101                 return;
6102
6103         if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
6104                 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
6105
6106         vmx->msr_bitmap_mode = mode;
6107 }
6108
6109 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
6110 {
6111         return enable_apicv;
6112 }
6113
6114 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
6115 {
6116         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6117         gfn_t gfn;
6118
6119         /*
6120          * Don't need to mark the APIC access page dirty; it is never
6121          * written to by the CPU during APIC virtualization.
6122          */
6123
6124         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
6125                 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
6126                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
6127         }
6128
6129         if (nested_cpu_has_posted_intr(vmcs12)) {
6130                 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
6131                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
6132         }
6133 }
6134
6135
6136 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
6137 {
6138         struct vcpu_vmx *vmx = to_vmx(vcpu);
6139         int max_irr;
6140         void *vapic_page;
6141         u16 status;
6142
6143         if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
6144                 return;
6145
6146         vmx->nested.pi_pending = false;
6147         if (!pi_test_and_clear_on(vmx->nested.pi_desc))
6148                 return;
6149
6150         max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
6151         if (max_irr != 256) {
6152                 vapic_page = kmap(vmx->nested.virtual_apic_page);
6153                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
6154                         vapic_page, &max_irr);
6155                 kunmap(vmx->nested.virtual_apic_page);
6156
6157                 status = vmcs_read16(GUEST_INTR_STATUS);
6158                 if ((u8)max_irr > ((u8)status & 0xff)) {
6159                         status &= ~0xff;
6160                         status |= (u8)max_irr;
6161                         vmcs_write16(GUEST_INTR_STATUS, status);
6162                 }
6163         }
6164
6165         nested_mark_vmcs12_pages_dirty(vcpu);
6166 }
6167
6168 static u8 vmx_get_rvi(void)
6169 {
6170         return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
6171 }
6172
6173 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
6174 {
6175         struct vcpu_vmx *vmx = to_vmx(vcpu);
6176         void *vapic_page;
6177         u32 vppr;
6178         int rvi;
6179
6180         if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
6181                 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
6182                 WARN_ON_ONCE(!vmx->nested.virtual_apic_page))
6183                 return false;
6184
6185         rvi = vmx_get_rvi();
6186
6187         vapic_page = kmap(vmx->nested.virtual_apic_page);
6188         vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
6189         kunmap(vmx->nested.virtual_apic_page);
6190
6191         return ((rvi & 0xf0) > (vppr & 0xf0));
6192 }
6193
6194 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
6195                                                      bool nested)
6196 {
6197 #ifdef CONFIG_SMP
6198         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
6199
6200         if (vcpu->mode == IN_GUEST_MODE) {
6201                 /*
6202                  * The vector of interrupt to be delivered to vcpu had
6203                  * been set in PIR before this function.
6204                  *
6205                  * Following cases will be reached in this block, and
6206                  * we always send a notification event in all cases as
6207                  * explained below.
6208                  *
6209                  * Case 1: vcpu keeps in non-root mode. Sending a
6210                  * notification event posts the interrupt to vcpu.
6211                  *
6212                  * Case 2: vcpu exits to root mode and is still
6213                  * runnable. PIR will be synced to vIRR before the
6214                  * next vcpu entry. Sending a notification event in
6215                  * this case has no effect, as vcpu is not in root
6216                  * mode.
6217                  *
6218                  * Case 3: vcpu exits to root mode and is blocked.
6219                  * vcpu_block() has already synced PIR to vIRR and
6220                  * never blocks vcpu if vIRR is not cleared. Therefore,
6221                  * a blocked vcpu here does not wait for any requested
6222                  * interrupts in PIR, and sending a notification event
6223                  * which has no effect is safe here.
6224                  */
6225
6226                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
6227                 return true;
6228         }
6229 #endif
6230         return false;
6231 }
6232
6233 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
6234                                                 int vector)
6235 {
6236         struct vcpu_vmx *vmx = to_vmx(vcpu);
6237
6238         if (is_guest_mode(vcpu) &&
6239             vector == vmx->nested.posted_intr_nv) {
6240                 /*
6241                  * If a posted intr is not recognized by hardware,
6242                  * we will accomplish it in the next vmentry.
6243                  */
6244                 vmx->nested.pi_pending = true;
6245                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6246                 /* the PIR and ON have been set by L1. */
6247                 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
6248                         kvm_vcpu_kick(vcpu);
6249                 return 0;
6250         }
6251         return -1;
6252 }
6253 /*
6254  * Send interrupt to vcpu via posted interrupt way.
6255  * 1. If target vcpu is running(non-root mode), send posted interrupt
6256  * notification to vcpu and hardware will sync PIR to vIRR atomically.
6257  * 2. If target vcpu isn't running(root mode), kick it to pick up the
6258  * interrupt from PIR in next vmentry.
6259  */
6260 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
6261 {
6262         struct vcpu_vmx *vmx = to_vmx(vcpu);
6263         int r;
6264
6265         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
6266         if (!r)
6267                 return;
6268
6269         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
6270                 return;
6271
6272         /* If a previous notification has sent the IPI, nothing to do.  */
6273         if (pi_test_and_set_on(&vmx->pi_desc))
6274                 return;
6275
6276         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
6277                 kvm_vcpu_kick(vcpu);
6278 }
6279
6280 /*
6281  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
6282  * will not change in the lifetime of the guest.
6283  * Note that host-state that does change is set elsewhere. E.g., host-state
6284  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
6285  */
6286 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
6287 {
6288         u32 low32, high32;
6289         unsigned long tmpl;
6290         struct desc_ptr dt;
6291         unsigned long cr0, cr3, cr4;
6292
6293         cr0 = read_cr0();
6294         WARN_ON(cr0 & X86_CR0_TS);
6295         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
6296
6297         /*
6298          * Save the most likely value for this task's CR3 in the VMCS.
6299          * We can't use __get_current_cr3_fast() because we're not atomic.
6300          */
6301         cr3 = __read_cr3();
6302         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
6303         vmx->loaded_vmcs->host_state.cr3 = cr3;
6304
6305         /* Save the most likely value for this task's CR4 in the VMCS. */
6306         cr4 = cr4_read_shadow();
6307         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
6308         vmx->loaded_vmcs->host_state.cr4 = cr4;
6309
6310         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
6311 #ifdef CONFIG_X86_64
6312         /*
6313          * Load null selectors, so we can avoid reloading them in
6314          * vmx_prepare_switch_to_host(), in case userspace uses
6315          * the null selectors too (the expected case).
6316          */
6317         vmcs_write16(HOST_DS_SELECTOR, 0);
6318         vmcs_write16(HOST_ES_SELECTOR, 0);
6319 #else
6320         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
6321         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
6322 #endif
6323         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
6324         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
6325
6326         store_idt(&dt);
6327         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
6328         vmx->host_idt_base = dt.address;
6329
6330         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
6331
6332         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
6333         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
6334         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
6335         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
6336
6337         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
6338                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
6339                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
6340         }
6341
6342         if (cpu_has_load_ia32_efer)
6343                 vmcs_write64(HOST_IA32_EFER, host_efer);
6344 }
6345
6346 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
6347 {
6348         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
6349         if (enable_ept)
6350                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
6351         if (is_guest_mode(&vmx->vcpu))
6352                 vmx->vcpu.arch.cr4_guest_owned_bits &=
6353                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
6354         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
6355 }
6356
6357 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
6358 {
6359         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
6360
6361         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
6362                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
6363
6364         if (!enable_vnmi)
6365                 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
6366
6367         /* Enable the preemption timer dynamically */
6368         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
6369         return pin_based_exec_ctrl;
6370 }
6371
6372 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
6373 {
6374         struct vcpu_vmx *vmx = to_vmx(vcpu);
6375
6376         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6377         if (cpu_has_secondary_exec_ctrls()) {
6378                 if (kvm_vcpu_apicv_active(vcpu))
6379                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
6380                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
6381                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6382                 else
6383                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6384                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
6385                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6386         }
6387
6388         if (cpu_has_vmx_msr_bitmap())
6389                 vmx_update_msr_bitmap(vcpu);
6390 }
6391
6392 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
6393 {
6394         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
6395
6396         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
6397                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
6398
6399         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
6400                 exec_control &= ~CPU_BASED_TPR_SHADOW;
6401 #ifdef CONFIG_X86_64
6402                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
6403                                 CPU_BASED_CR8_LOAD_EXITING;
6404 #endif
6405         }
6406         if (!enable_ept)
6407                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
6408                                 CPU_BASED_CR3_LOAD_EXITING  |
6409                                 CPU_BASED_INVLPG_EXITING;
6410         if (kvm_mwait_in_guest(vmx->vcpu.kvm))
6411                 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
6412                                 CPU_BASED_MONITOR_EXITING);
6413         if (kvm_hlt_in_guest(vmx->vcpu.kvm))
6414                 exec_control &= ~CPU_BASED_HLT_EXITING;
6415         return exec_control;
6416 }
6417
6418 static bool vmx_rdrand_supported(void)
6419 {
6420         return vmcs_config.cpu_based_2nd_exec_ctrl &
6421                 SECONDARY_EXEC_RDRAND_EXITING;
6422 }
6423
6424 static bool vmx_rdseed_supported(void)
6425 {
6426         return vmcs_config.cpu_based_2nd_exec_ctrl &
6427                 SECONDARY_EXEC_RDSEED_EXITING;
6428 }
6429
6430 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
6431 {
6432         struct kvm_vcpu *vcpu = &vmx->vcpu;
6433
6434         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
6435
6436         if (!cpu_need_virtualize_apic_accesses(vcpu))
6437                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6438         if (vmx->vpid == 0)
6439                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
6440         if (!enable_ept) {
6441                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
6442                 enable_unrestricted_guest = 0;
6443         }
6444         if (!enable_unrestricted_guest)
6445                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
6446         if (kvm_pause_in_guest(vmx->vcpu.kvm))
6447                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
6448         if (!kvm_vcpu_apicv_active(vcpu))
6449                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
6450                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6451         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6452
6453         /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
6454          * in vmx_set_cr4.  */
6455         exec_control &= ~SECONDARY_EXEC_DESC;
6456
6457         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
6458            (handle_vmptrld).
6459            We can NOT enable shadow_vmcs here because we don't have yet
6460            a current VMCS12
6461         */
6462         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6463
6464         if (!enable_pml)
6465                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
6466
6467         if (vmx_xsaves_supported()) {
6468                 /* Exposing XSAVES only when XSAVE is exposed */
6469                 bool xsaves_enabled =
6470                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
6471                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
6472
6473                 if (!xsaves_enabled)
6474                         exec_control &= ~SECONDARY_EXEC_XSAVES;
6475
6476                 if (nested) {
6477                         if (xsaves_enabled)
6478                                 vmx->nested.msrs.secondary_ctls_high |=
6479                                         SECONDARY_EXEC_XSAVES;
6480                         else
6481                                 vmx->nested.msrs.secondary_ctls_high &=
6482                                         ~SECONDARY_EXEC_XSAVES;
6483                 }
6484         }
6485
6486         if (vmx_rdtscp_supported()) {
6487                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
6488                 if (!rdtscp_enabled)
6489                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6490
6491                 if (nested) {
6492                         if (rdtscp_enabled)
6493                                 vmx->nested.msrs.secondary_ctls_high |=
6494                                         SECONDARY_EXEC_RDTSCP;
6495                         else
6496                                 vmx->nested.msrs.secondary_ctls_high &=
6497                                         ~SECONDARY_EXEC_RDTSCP;
6498                 }
6499         }
6500
6501         if (vmx_invpcid_supported()) {
6502                 /* Exposing INVPCID only when PCID is exposed */
6503                 bool invpcid_enabled =
6504                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
6505                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
6506
6507                 if (!invpcid_enabled) {
6508                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6509                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
6510                 }
6511
6512                 if (nested) {
6513                         if (invpcid_enabled)
6514                                 vmx->nested.msrs.secondary_ctls_high |=
6515                                         SECONDARY_EXEC_ENABLE_INVPCID;
6516                         else
6517                                 vmx->nested.msrs.secondary_ctls_high &=
6518                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
6519                 }
6520         }
6521
6522         if (vmx_rdrand_supported()) {
6523                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
6524                 if (rdrand_enabled)
6525                         exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
6526
6527                 if (nested) {
6528                         if (rdrand_enabled)
6529                                 vmx->nested.msrs.secondary_ctls_high |=
6530                                         SECONDARY_EXEC_RDRAND_EXITING;
6531                         else
6532                                 vmx->nested.msrs.secondary_ctls_high &=
6533                                         ~SECONDARY_EXEC_RDRAND_EXITING;
6534                 }
6535         }
6536
6537         if (vmx_rdseed_supported()) {
6538                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
6539                 if (rdseed_enabled)
6540                         exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
6541
6542                 if (nested) {
6543                         if (rdseed_enabled)
6544                                 vmx->nested.msrs.secondary_ctls_high |=
6545                                         SECONDARY_EXEC_RDSEED_EXITING;
6546                         else
6547                                 vmx->nested.msrs.secondary_ctls_high &=
6548                                         ~SECONDARY_EXEC_RDSEED_EXITING;
6549                 }
6550         }
6551
6552         vmx->secondary_exec_control = exec_control;
6553 }
6554
6555 static void ept_set_mmio_spte_mask(void)
6556 {
6557         /*
6558          * EPT Misconfigurations can be generated if the value of bits 2:0
6559          * of an EPT paging-structure entry is 110b (write/execute).
6560          */
6561         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
6562                                    VMX_EPT_MISCONFIG_WX_VALUE);
6563 }
6564
6565 #define VMX_XSS_EXIT_BITMAP 0
6566 /*
6567  * Sets up the vmcs for emulated real mode.
6568  */
6569 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
6570 {
6571         int i;
6572
6573         if (enable_shadow_vmcs) {
6574                 /*
6575                  * At vCPU creation, "VMWRITE to any supported field
6576                  * in the VMCS" is supported, so use the more
6577                  * permissive vmx_vmread_bitmap to specify both read
6578                  * and write permissions for the shadow VMCS.
6579                  */
6580                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
6581                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmread_bitmap));
6582         }
6583         if (cpu_has_vmx_msr_bitmap())
6584                 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
6585
6586         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
6587
6588         /* Control */
6589         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6590         vmx->hv_deadline_tsc = -1;
6591
6592         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6593
6594         if (cpu_has_secondary_exec_ctrls()) {
6595                 vmx_compute_secondary_exec_control(vmx);
6596                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6597                              vmx->secondary_exec_control);
6598         }
6599
6600         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
6601                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
6602                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
6603                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
6604                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
6605
6606                 vmcs_write16(GUEST_INTR_STATUS, 0);
6607
6608                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
6609                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
6610         }
6611
6612         if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
6613                 vmcs_write32(PLE_GAP, ple_gap);
6614                 vmx->ple_window = ple_window;
6615                 vmx->ple_window_dirty = true;
6616         }
6617
6618         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
6619         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6620         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
6621
6622         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
6623         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
6624         vmx_set_constant_host_state(vmx);
6625         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
6626         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6627
6628         if (cpu_has_vmx_vmfunc())
6629                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
6630
6631         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
6632         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
6633         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
6634         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6635         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
6636
6637         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6638                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6639
6640         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6641                 u32 index = vmx_msr_index[i];
6642                 u32 data_low, data_high;
6643                 int j = vmx->nmsrs;
6644
6645                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6646                         continue;
6647                 if (wrmsr_safe(index, data_low, data_high) < 0)
6648                         continue;
6649                 vmx->guest_msrs[j].index = i;
6650                 vmx->guest_msrs[j].data = 0;
6651                 vmx->guest_msrs[j].mask = -1ull;
6652                 ++vmx->nmsrs;
6653         }
6654
6655         vmx->arch_capabilities = kvm_get_arch_capabilities();
6656
6657         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6658
6659         /* 22.2.1, 20.8.1 */
6660         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
6661
6662         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
6663         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
6664
6665         set_cr4_guest_host_mask(vmx);
6666
6667         if (vmx_xsaves_supported())
6668                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
6669
6670         if (enable_pml) {
6671                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
6672                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
6673         }
6674
6675         if (cpu_has_vmx_encls_vmexit())
6676                 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
6677 }
6678
6679 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
6680 {
6681         struct vcpu_vmx *vmx = to_vmx(vcpu);
6682         struct msr_data apic_base_msr;
6683         u64 cr0;
6684
6685         vmx->rmode.vm86_active = 0;
6686         vmx->spec_ctrl = 0;
6687
6688         vcpu->arch.microcode_version = 0x100000000ULL;
6689         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
6690         kvm_set_cr8(vcpu, 0);
6691
6692         if (!init_event) {
6693                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
6694                                      MSR_IA32_APICBASE_ENABLE;
6695                 if (kvm_vcpu_is_reset_bsp(vcpu))
6696                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
6697                 apic_base_msr.host_initiated = true;
6698                 kvm_set_apic_base(vcpu, &apic_base_msr);
6699         }
6700
6701         vmx_segment_cache_clear(vmx);
6702
6703         seg_setup(VCPU_SREG_CS);
6704         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
6705         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
6706
6707         seg_setup(VCPU_SREG_DS);
6708         seg_setup(VCPU_SREG_ES);
6709         seg_setup(VCPU_SREG_FS);
6710         seg_setup(VCPU_SREG_GS);
6711         seg_setup(VCPU_SREG_SS);
6712
6713         vmcs_write16(GUEST_TR_SELECTOR, 0);
6714         vmcs_writel(GUEST_TR_BASE, 0);
6715         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
6716         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
6717
6718         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
6719         vmcs_writel(GUEST_LDTR_BASE, 0);
6720         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
6721         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
6722
6723         if (!init_event) {
6724                 vmcs_write32(GUEST_SYSENTER_CS, 0);
6725                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
6726                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
6727                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
6728         }
6729
6730         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6731         kvm_rip_write(vcpu, 0xfff0);
6732
6733         vmcs_writel(GUEST_GDTR_BASE, 0);
6734         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
6735
6736         vmcs_writel(GUEST_IDTR_BASE, 0);
6737         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
6738
6739         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
6740         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
6741         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
6742         if (kvm_mpx_supported())
6743                 vmcs_write64(GUEST_BNDCFGS, 0);
6744
6745         setup_msrs(vmx);
6746
6747         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
6748
6749         if (cpu_has_vmx_tpr_shadow() && !init_event) {
6750                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
6751                 if (cpu_need_tpr_shadow(vcpu))
6752                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
6753                                      __pa(vcpu->arch.apic->regs));
6754                 vmcs_write32(TPR_THRESHOLD, 0);
6755         }
6756
6757         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6758
6759         if (vmx->vpid != 0)
6760                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6761
6762         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
6763         vmx->vcpu.arch.cr0 = cr0;
6764         vmx_set_cr0(vcpu, cr0); /* enter rmode */
6765         vmx_set_cr4(vcpu, 0);
6766         vmx_set_efer(vcpu, 0);
6767
6768         update_exception_bitmap(vcpu);
6769
6770         vpid_sync_context(vmx->vpid);
6771         if (init_event)
6772                 vmx_clear_hlt(vcpu);
6773 }
6774
6775 /*
6776  * In nested virtualization, check if L1 asked to exit on external interrupts.
6777  * For most existing hypervisors, this will always return true.
6778  */
6779 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
6780 {
6781         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
6782                 PIN_BASED_EXT_INTR_MASK;
6783 }
6784
6785 /*
6786  * In nested virtualization, check if L1 has set
6787  * VM_EXIT_ACK_INTR_ON_EXIT
6788  */
6789 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
6790 {
6791         return get_vmcs12(vcpu)->vm_exit_controls &
6792                 VM_EXIT_ACK_INTR_ON_EXIT;
6793 }
6794
6795 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
6796 {
6797         return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu));
6798 }
6799
6800 static void enable_irq_window(struct kvm_vcpu *vcpu)
6801 {
6802         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6803                       CPU_BASED_VIRTUAL_INTR_PENDING);
6804 }
6805
6806 static void enable_nmi_window(struct kvm_vcpu *vcpu)
6807 {
6808         if (!enable_vnmi ||
6809             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
6810                 enable_irq_window(vcpu);
6811                 return;
6812         }
6813
6814         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6815                       CPU_BASED_VIRTUAL_NMI_PENDING);
6816 }
6817
6818 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
6819 {
6820         struct vcpu_vmx *vmx = to_vmx(vcpu);
6821         uint32_t intr;
6822         int irq = vcpu->arch.interrupt.nr;
6823
6824         trace_kvm_inj_virq(irq);
6825
6826         ++vcpu->stat.irq_injections;
6827         if (vmx->rmode.vm86_active) {
6828                 int inc_eip = 0;
6829                 if (vcpu->arch.interrupt.soft)
6830                         inc_eip = vcpu->arch.event_exit_inst_len;
6831                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
6832                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6833                 return;
6834         }
6835         intr = irq | INTR_INFO_VALID_MASK;
6836         if (vcpu->arch.interrupt.soft) {
6837                 intr |= INTR_TYPE_SOFT_INTR;
6838                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6839                              vmx->vcpu.arch.event_exit_inst_len);
6840         } else
6841                 intr |= INTR_TYPE_EXT_INTR;
6842         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
6843
6844         vmx_clear_hlt(vcpu);
6845 }
6846
6847 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
6848 {
6849         struct vcpu_vmx *vmx = to_vmx(vcpu);
6850
6851         if (!enable_vnmi) {
6852                 /*
6853                  * Tracking the NMI-blocked state in software is built upon
6854                  * finding the next open IRQ window. This, in turn, depends on
6855                  * well-behaving guests: They have to keep IRQs disabled at
6856                  * least as long as the NMI handler runs. Otherwise we may
6857                  * cause NMI nesting, maybe breaking the guest. But as this is
6858                  * highly unlikely, we can live with the residual risk.
6859                  */
6860                 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
6861                 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6862         }
6863
6864         ++vcpu->stat.nmi_injections;
6865         vmx->loaded_vmcs->nmi_known_unmasked = false;
6866
6867         if (vmx->rmode.vm86_active) {
6868                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
6869                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6870                 return;
6871         }
6872
6873         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6874                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
6875
6876         vmx_clear_hlt(vcpu);
6877 }
6878
6879 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
6880 {
6881         struct vcpu_vmx *vmx = to_vmx(vcpu);
6882         bool masked;
6883
6884         if (!enable_vnmi)
6885                 return vmx->loaded_vmcs->soft_vnmi_blocked;
6886         if (vmx->loaded_vmcs->nmi_known_unmasked)
6887                 return false;
6888         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
6889         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6890         return masked;
6891 }
6892
6893 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
6894 {
6895         struct vcpu_vmx *vmx = to_vmx(vcpu);
6896
6897         if (!enable_vnmi) {
6898                 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
6899                         vmx->loaded_vmcs->soft_vnmi_blocked = masked;
6900                         vmx->loaded_vmcs->vnmi_blocked_time = 0;
6901                 }
6902         } else {
6903                 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6904                 if (masked)
6905                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6906                                       GUEST_INTR_STATE_NMI);
6907                 else
6908                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
6909                                         GUEST_INTR_STATE_NMI);
6910         }
6911 }
6912
6913 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
6914 {
6915         if (to_vmx(vcpu)->nested.nested_run_pending)
6916                 return 0;
6917
6918         if (!enable_vnmi &&
6919             to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
6920                 return 0;
6921
6922         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6923                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
6924                    | GUEST_INTR_STATE_NMI));
6925 }
6926
6927 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
6928 {
6929         return (!to_vmx(vcpu)->nested.nested_run_pending &&
6930                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
6931                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6932                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
6933 }
6934
6935 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
6936 {
6937         int ret;
6938
6939         if (enable_unrestricted_guest)
6940                 return 0;
6941
6942         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
6943                                     PAGE_SIZE * 3);
6944         if (ret)
6945                 return ret;
6946         to_kvm_vmx(kvm)->tss_addr = addr;
6947         return init_rmode_tss(kvm);
6948 }
6949
6950 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
6951 {
6952         to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
6953         return 0;
6954 }
6955
6956 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6957 {
6958         switch (vec) {
6959         case BP_VECTOR:
6960                 /*
6961                  * Update instruction length as we may reinject the exception
6962                  * from user space while in guest debugging mode.
6963                  */
6964                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
6965                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6966                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6967                         return false;
6968                 /* fall through */
6969         case DB_VECTOR:
6970                 if (vcpu->guest_debug &
6971                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6972                         return false;
6973                 /* fall through */
6974         case DE_VECTOR:
6975         case OF_VECTOR:
6976         case BR_VECTOR:
6977         case UD_VECTOR:
6978         case DF_VECTOR:
6979         case SS_VECTOR:
6980         case GP_VECTOR:
6981         case MF_VECTOR:
6982                 return true;
6983         break;
6984         }
6985         return false;
6986 }
6987
6988 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
6989                                   int vec, u32 err_code)
6990 {
6991         /*
6992          * Instruction with address size override prefix opcode 0x67
6993          * Cause the #SS fault with 0 error code in VM86 mode.
6994          */
6995         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
6996                 if (kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE) {
6997                         if (vcpu->arch.halt_request) {
6998                                 vcpu->arch.halt_request = 0;
6999                                 return kvm_vcpu_halt(vcpu);
7000                         }
7001                         return 1;
7002                 }
7003                 return 0;
7004         }
7005
7006         /*
7007          * Forward all other exceptions that are valid in real mode.
7008          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
7009          *        the required debugging infrastructure rework.
7010          */
7011         kvm_queue_exception(vcpu, vec);
7012         return 1;
7013 }
7014
7015 /*
7016  * Trigger machine check on the host. We assume all the MSRs are already set up
7017  * by the CPU and that we still run on the same CPU as the MCE occurred on.
7018  * We pass a fake environment to the machine check handler because we want
7019  * the guest to be always treated like user space, no matter what context
7020  * it used internally.
7021  */
7022 static void kvm_machine_check(void)
7023 {
7024 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
7025         struct pt_regs regs = {
7026                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
7027                 .flags = X86_EFLAGS_IF,
7028         };
7029
7030         do_machine_check(&regs, 0);
7031 #endif
7032 }
7033
7034 static int handle_machine_check(struct kvm_vcpu *vcpu)
7035 {
7036         /* already handled by vcpu_run */
7037         return 1;
7038 }
7039
7040 static int handle_exception(struct kvm_vcpu *vcpu)
7041 {
7042         struct vcpu_vmx *vmx = to_vmx(vcpu);
7043         struct kvm_run *kvm_run = vcpu->run;
7044         u32 intr_info, ex_no, error_code;
7045         unsigned long cr2, rip, dr6;
7046         u32 vect_info;
7047         enum emulation_result er;
7048
7049         vect_info = vmx->idt_vectoring_info;
7050         intr_info = vmx->exit_intr_info;
7051
7052         if (is_machine_check(intr_info))
7053                 return handle_machine_check(vcpu);
7054
7055         if (is_nmi(intr_info))
7056                 return 1;  /* already handled by vmx_vcpu_run() */
7057
7058         if (is_invalid_opcode(intr_info))
7059                 return handle_ud(vcpu);
7060
7061         error_code = 0;
7062         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
7063                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7064
7065         if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
7066                 WARN_ON_ONCE(!enable_vmware_backdoor);
7067                 er = kvm_emulate_instruction(vcpu,
7068                         EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
7069                 if (er == EMULATE_USER_EXIT)
7070                         return 0;
7071                 else if (er != EMULATE_DONE)
7072                         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
7073                 return 1;
7074         }
7075
7076         /*
7077          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
7078          * MMIO, it is better to report an internal error.
7079          * See the comments in vmx_handle_exit.
7080          */
7081         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
7082             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
7083                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7084                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
7085                 vcpu->run->internal.ndata = 3;
7086                 vcpu->run->internal.data[0] = vect_info;
7087                 vcpu->run->internal.data[1] = intr_info;
7088                 vcpu->run->internal.data[2] = error_code;
7089                 return 0;
7090         }
7091
7092         if (is_page_fault(intr_info)) {
7093                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
7094                 /* EPT won't cause page fault directly */
7095                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
7096                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
7097         }
7098
7099         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
7100
7101         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
7102                 return handle_rmode_exception(vcpu, ex_no, error_code);
7103
7104         switch (ex_no) {
7105         case AC_VECTOR:
7106                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
7107                 return 1;
7108         case DB_VECTOR:
7109                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
7110                 if (!(vcpu->guest_debug &
7111                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
7112                         vcpu->arch.dr6 &= ~15;
7113                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
7114                         if (is_icebp(intr_info))
7115                                 skip_emulated_instruction(vcpu);
7116
7117                         kvm_queue_exception(vcpu, DB_VECTOR);
7118                         return 1;
7119                 }
7120                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
7121                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
7122                 /* fall through */
7123         case BP_VECTOR:
7124                 /*
7125                  * Update instruction length as we may reinject #BP from
7126                  * user space while in guest debugging mode. Reading it for
7127                  * #DB as well causes no harm, it is not used in that case.
7128                  */
7129                 vmx->vcpu.arch.event_exit_inst_len =
7130                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7131                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7132                 rip = kvm_rip_read(vcpu);
7133                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
7134                 kvm_run->debug.arch.exception = ex_no;
7135                 break;
7136         default:
7137                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
7138                 kvm_run->ex.exception = ex_no;
7139                 kvm_run->ex.error_code = error_code;
7140                 break;
7141         }
7142         return 0;
7143 }
7144
7145 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
7146 {
7147         ++vcpu->stat.irq_exits;
7148         return 1;
7149 }
7150
7151 static int handle_triple_fault(struct kvm_vcpu *vcpu)
7152 {
7153         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7154         vcpu->mmio_needed = 0;
7155         return 0;
7156 }
7157
7158 static int handle_io(struct kvm_vcpu *vcpu)
7159 {
7160         unsigned long exit_qualification;
7161         int size, in, string;
7162         unsigned port;
7163
7164         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7165         string = (exit_qualification & 16) != 0;
7166
7167         ++vcpu->stat.io_exits;
7168
7169         if (string)
7170                 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
7171
7172         port = exit_qualification >> 16;
7173         size = (exit_qualification & 7) + 1;
7174         in = (exit_qualification & 8) != 0;
7175
7176         return kvm_fast_pio(vcpu, size, port, in);
7177 }
7178
7179 static void
7180 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
7181 {
7182         /*
7183          * Patch in the VMCALL instruction:
7184          */
7185         hypercall[0] = 0x0f;
7186         hypercall[1] = 0x01;
7187         hypercall[2] = 0xc1;
7188 }
7189
7190 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
7191 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
7192 {
7193         if (is_guest_mode(vcpu)) {
7194                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7195                 unsigned long orig_val = val;
7196
7197                 /*
7198                  * We get here when L2 changed cr0 in a way that did not change
7199                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
7200                  * but did change L0 shadowed bits. So we first calculate the
7201                  * effective cr0 value that L1 would like to write into the
7202                  * hardware. It consists of the L2-owned bits from the new
7203                  * value combined with the L1-owned bits from L1's guest_cr0.
7204                  */
7205                 val = (val & ~vmcs12->cr0_guest_host_mask) |
7206                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
7207
7208                 if (!nested_guest_cr0_valid(vcpu, val))
7209                         return 1;
7210
7211                 if (kvm_set_cr0(vcpu, val))
7212                         return 1;
7213                 vmcs_writel(CR0_READ_SHADOW, orig_val);
7214                 return 0;
7215         } else {
7216                 if (to_vmx(vcpu)->nested.vmxon &&
7217                     !nested_host_cr0_valid(vcpu, val))
7218                         return 1;
7219
7220                 return kvm_set_cr0(vcpu, val);
7221         }
7222 }
7223
7224 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
7225 {
7226         if (is_guest_mode(vcpu)) {
7227                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7228                 unsigned long orig_val = val;
7229
7230                 /* analogously to handle_set_cr0 */
7231                 val = (val & ~vmcs12->cr4_guest_host_mask) |
7232                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
7233                 if (kvm_set_cr4(vcpu, val))
7234                         return 1;
7235                 vmcs_writel(CR4_READ_SHADOW, orig_val);
7236                 return 0;
7237         } else
7238                 return kvm_set_cr4(vcpu, val);
7239 }
7240
7241 static int handle_desc(struct kvm_vcpu *vcpu)
7242 {
7243         WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
7244         return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
7245 }
7246
7247 static int handle_cr(struct kvm_vcpu *vcpu)
7248 {
7249         unsigned long exit_qualification, val;
7250         int cr;
7251         int reg;
7252         int err;
7253         int ret;
7254
7255         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7256         cr = exit_qualification & 15;
7257         reg = (exit_qualification >> 8) & 15;
7258         switch ((exit_qualification >> 4) & 3) {
7259         case 0: /* mov to cr */
7260                 val = kvm_register_readl(vcpu, reg);
7261                 trace_kvm_cr_write(cr, val);
7262                 switch (cr) {
7263                 case 0:
7264                         err = handle_set_cr0(vcpu, val);
7265                         return kvm_complete_insn_gp(vcpu, err);
7266                 case 3:
7267                         WARN_ON_ONCE(enable_unrestricted_guest);
7268                         err = kvm_set_cr3(vcpu, val);
7269                         return kvm_complete_insn_gp(vcpu, err);
7270                 case 4:
7271                         err = handle_set_cr4(vcpu, val);
7272                         return kvm_complete_insn_gp(vcpu, err);
7273                 case 8: {
7274                                 u8 cr8_prev = kvm_get_cr8(vcpu);
7275                                 u8 cr8 = (u8)val;
7276                                 err = kvm_set_cr8(vcpu, cr8);
7277                                 ret = kvm_complete_insn_gp(vcpu, err);
7278                                 if (lapic_in_kernel(vcpu))
7279                                         return ret;
7280                                 if (cr8_prev <= cr8)
7281                                         return ret;
7282                                 /*
7283                                  * TODO: we might be squashing a
7284                                  * KVM_GUESTDBG_SINGLESTEP-triggered
7285                                  * KVM_EXIT_DEBUG here.
7286                                  */
7287                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
7288                                 return 0;
7289                         }
7290                 }
7291                 break;
7292         case 2: /* clts */
7293                 WARN_ONCE(1, "Guest should always own CR0.TS");
7294                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
7295                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
7296                 return kvm_skip_emulated_instruction(vcpu);
7297         case 1: /*mov from cr*/
7298                 switch (cr) {
7299                 case 3:
7300                         WARN_ON_ONCE(enable_unrestricted_guest);
7301                         val = kvm_read_cr3(vcpu);
7302                         kvm_register_write(vcpu, reg, val);
7303                         trace_kvm_cr_read(cr, val);
7304                         return kvm_skip_emulated_instruction(vcpu);
7305                 case 8:
7306                         val = kvm_get_cr8(vcpu);
7307                         kvm_register_write(vcpu, reg, val);
7308                         trace_kvm_cr_read(cr, val);
7309                         return kvm_skip_emulated_instruction(vcpu);
7310                 }
7311                 break;
7312         case 3: /* lmsw */
7313                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
7314                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
7315                 kvm_lmsw(vcpu, val);
7316
7317                 return kvm_skip_emulated_instruction(vcpu);
7318         default:
7319                 break;
7320         }
7321         vcpu->run->exit_reason = 0;
7322         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
7323                (int)(exit_qualification >> 4) & 3, cr);
7324         return 0;
7325 }
7326
7327 static int handle_dr(struct kvm_vcpu *vcpu)
7328 {
7329         unsigned long exit_qualification;
7330         int dr, dr7, reg;
7331
7332         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7333         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
7334
7335         /* First, if DR does not exist, trigger UD */
7336         if (!kvm_require_dr(vcpu, dr))
7337                 return 1;
7338
7339         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
7340         if (!kvm_require_cpl(vcpu, 0))
7341                 return 1;
7342         dr7 = vmcs_readl(GUEST_DR7);
7343         if (dr7 & DR7_GD) {
7344                 /*
7345                  * As the vm-exit takes precedence over the debug trap, we
7346                  * need to emulate the latter, either for the host or the
7347                  * guest debugging itself.
7348                  */
7349                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7350                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
7351                         vcpu->run->debug.arch.dr7 = dr7;
7352                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
7353                         vcpu->run->debug.arch.exception = DB_VECTOR;
7354                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
7355                         return 0;
7356                 } else {
7357                         vcpu->arch.dr6 &= ~15;
7358                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
7359                         kvm_queue_exception(vcpu, DB_VECTOR);
7360                         return 1;
7361                 }
7362         }
7363
7364         if (vcpu->guest_debug == 0) {
7365                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7366                                 CPU_BASED_MOV_DR_EXITING);
7367
7368                 /*
7369                  * No more DR vmexits; force a reload of the debug registers
7370                  * and reenter on this instruction.  The next vmexit will
7371                  * retrieve the full state of the debug registers.
7372                  */
7373                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
7374                 return 1;
7375         }
7376
7377         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
7378         if (exit_qualification & TYPE_MOV_FROM_DR) {
7379                 unsigned long val;
7380
7381                 if (kvm_get_dr(vcpu, dr, &val))
7382                         return 1;
7383                 kvm_register_write(vcpu, reg, val);
7384         } else
7385                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
7386                         return 1;
7387
7388         return kvm_skip_emulated_instruction(vcpu);
7389 }
7390
7391 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
7392 {
7393         return vcpu->arch.dr6;
7394 }
7395
7396 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
7397 {
7398 }
7399
7400 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
7401 {
7402         get_debugreg(vcpu->arch.db[0], 0);
7403         get_debugreg(vcpu->arch.db[1], 1);
7404         get_debugreg(vcpu->arch.db[2], 2);
7405         get_debugreg(vcpu->arch.db[3], 3);
7406         get_debugreg(vcpu->arch.dr6, 6);
7407         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
7408
7409         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
7410         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
7411 }
7412
7413 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
7414 {
7415         vmcs_writel(GUEST_DR7, val);
7416 }
7417
7418 static int handle_cpuid(struct kvm_vcpu *vcpu)
7419 {
7420         return kvm_emulate_cpuid(vcpu);
7421 }
7422
7423 static int handle_rdmsr(struct kvm_vcpu *vcpu)
7424 {
7425         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7426         struct msr_data msr_info;
7427
7428         msr_info.index = ecx;
7429         msr_info.host_initiated = false;
7430         if (vmx_get_msr(vcpu, &msr_info)) {
7431                 trace_kvm_msr_read_ex(ecx);
7432                 kvm_inject_gp(vcpu, 0);
7433                 return 1;
7434         }
7435
7436         trace_kvm_msr_read(ecx, msr_info.data);
7437
7438         /* FIXME: handling of bits 32:63 of rax, rdx */
7439         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
7440         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
7441         return kvm_skip_emulated_instruction(vcpu);
7442 }
7443
7444 static int handle_wrmsr(struct kvm_vcpu *vcpu)
7445 {
7446         struct msr_data msr;
7447         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7448         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
7449                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
7450
7451         msr.data = data;
7452         msr.index = ecx;
7453         msr.host_initiated = false;
7454         if (kvm_set_msr(vcpu, &msr) != 0) {
7455                 trace_kvm_msr_write_ex(ecx, data);
7456                 kvm_inject_gp(vcpu, 0);
7457                 return 1;
7458         }
7459
7460         trace_kvm_msr_write(ecx, data);
7461         return kvm_skip_emulated_instruction(vcpu);
7462 }
7463
7464 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
7465 {
7466         kvm_apic_update_ppr(vcpu);
7467         return 1;
7468 }
7469
7470 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
7471 {
7472         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7473                         CPU_BASED_VIRTUAL_INTR_PENDING);
7474
7475         kvm_make_request(KVM_REQ_EVENT, vcpu);
7476
7477         ++vcpu->stat.irq_window_exits;
7478         return 1;
7479 }
7480
7481 static int handle_halt(struct kvm_vcpu *vcpu)
7482 {
7483         return kvm_emulate_halt(vcpu);
7484 }
7485
7486 static int handle_vmcall(struct kvm_vcpu *vcpu)
7487 {
7488         return kvm_emulate_hypercall(vcpu);
7489 }
7490
7491 static int handle_invd(struct kvm_vcpu *vcpu)
7492 {
7493         return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
7494 }
7495
7496 static int handle_invlpg(struct kvm_vcpu *vcpu)
7497 {
7498         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7499
7500         kvm_mmu_invlpg(vcpu, exit_qualification);
7501         return kvm_skip_emulated_instruction(vcpu);
7502 }
7503
7504 static int handle_rdpmc(struct kvm_vcpu *vcpu)
7505 {
7506         int err;
7507
7508         err = kvm_rdpmc(vcpu);
7509         return kvm_complete_insn_gp(vcpu, err);
7510 }
7511
7512 static int handle_wbinvd(struct kvm_vcpu *vcpu)
7513 {
7514         return kvm_emulate_wbinvd(vcpu);
7515 }
7516
7517 static int handle_xsetbv(struct kvm_vcpu *vcpu)
7518 {
7519         u64 new_bv = kvm_read_edx_eax(vcpu);
7520         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
7521
7522         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
7523                 return kvm_skip_emulated_instruction(vcpu);
7524         return 1;
7525 }
7526
7527 static int handle_xsaves(struct kvm_vcpu *vcpu)
7528 {
7529         kvm_skip_emulated_instruction(vcpu);
7530         WARN(1, "this should never happen\n");
7531         return 1;
7532 }
7533
7534 static int handle_xrstors(struct kvm_vcpu *vcpu)
7535 {
7536         kvm_skip_emulated_instruction(vcpu);
7537         WARN(1, "this should never happen\n");
7538         return 1;
7539 }
7540
7541 static int handle_apic_access(struct kvm_vcpu *vcpu)
7542 {
7543         if (likely(fasteoi)) {
7544                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7545                 int access_type, offset;
7546
7547                 access_type = exit_qualification & APIC_ACCESS_TYPE;
7548                 offset = exit_qualification & APIC_ACCESS_OFFSET;
7549                 /*
7550                  * Sane guest uses MOV to write EOI, with written value
7551                  * not cared. So make a short-circuit here by avoiding
7552                  * heavy instruction emulation.
7553                  */
7554                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
7555                     (offset == APIC_EOI)) {
7556                         kvm_lapic_set_eoi(vcpu);
7557                         return kvm_skip_emulated_instruction(vcpu);
7558                 }
7559         }
7560         return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
7561 }
7562
7563 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
7564 {
7565         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7566         int vector = exit_qualification & 0xff;
7567
7568         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
7569         kvm_apic_set_eoi_accelerated(vcpu, vector);
7570         return 1;
7571 }
7572
7573 static int handle_apic_write(struct kvm_vcpu *vcpu)
7574 {
7575         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7576         u32 offset = exit_qualification & 0xfff;
7577
7578         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
7579         kvm_apic_write_nodecode(vcpu, offset);
7580         return 1;
7581 }
7582
7583 static int handle_task_switch(struct kvm_vcpu *vcpu)
7584 {
7585         struct vcpu_vmx *vmx = to_vmx(vcpu);
7586         unsigned long exit_qualification;
7587         bool has_error_code = false;
7588         u32 error_code = 0;
7589         u16 tss_selector;
7590         int reason, type, idt_v, idt_index;
7591
7592         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7593         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
7594         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
7595
7596         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7597
7598         reason = (u32)exit_qualification >> 30;
7599         if (reason == TASK_SWITCH_GATE && idt_v) {
7600                 switch (type) {
7601                 case INTR_TYPE_NMI_INTR:
7602                         vcpu->arch.nmi_injected = false;
7603                         vmx_set_nmi_mask(vcpu, true);
7604                         break;
7605                 case INTR_TYPE_EXT_INTR:
7606                 case INTR_TYPE_SOFT_INTR:
7607                         kvm_clear_interrupt_queue(vcpu);
7608                         break;
7609                 case INTR_TYPE_HARD_EXCEPTION:
7610                         if (vmx->idt_vectoring_info &
7611                             VECTORING_INFO_DELIVER_CODE_MASK) {
7612                                 has_error_code = true;
7613                                 error_code =
7614                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
7615                         }
7616                         /* fall through */
7617                 case INTR_TYPE_SOFT_EXCEPTION:
7618                         kvm_clear_exception_queue(vcpu);
7619                         break;
7620                 default:
7621                         break;
7622                 }
7623         }
7624         tss_selector = exit_qualification;
7625
7626         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
7627                        type != INTR_TYPE_EXT_INTR &&
7628                        type != INTR_TYPE_NMI_INTR))
7629                 skip_emulated_instruction(vcpu);
7630
7631         if (kvm_task_switch(vcpu, tss_selector,
7632                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
7633                             has_error_code, error_code) == EMULATE_FAIL) {
7634                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7635                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7636                 vcpu->run->internal.ndata = 0;
7637                 return 0;
7638         }
7639
7640         /*
7641          * TODO: What about debug traps on tss switch?
7642          *       Are we supposed to inject them and update dr6?
7643          */
7644
7645         return 1;
7646 }
7647
7648 static int handle_ept_violation(struct kvm_vcpu *vcpu)
7649 {
7650         unsigned long exit_qualification;
7651         gpa_t gpa;
7652         u64 error_code;
7653
7654         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7655
7656         /*
7657          * EPT violation happened while executing iret from NMI,
7658          * "blocked by NMI" bit has to be set before next VM entry.
7659          * There are errata that may cause this bit to not be set:
7660          * AAK134, BY25.
7661          */
7662         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7663                         enable_vnmi &&
7664                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7665                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
7666
7667         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7668         trace_kvm_page_fault(gpa, exit_qualification);
7669
7670         /* Is it a read fault? */
7671         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
7672                      ? PFERR_USER_MASK : 0;
7673         /* Is it a write fault? */
7674         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
7675                       ? PFERR_WRITE_MASK : 0;
7676         /* Is it a fetch fault? */
7677         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
7678                       ? PFERR_FETCH_MASK : 0;
7679         /* ept page table entry is present? */
7680         error_code |= (exit_qualification &
7681                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
7682                         EPT_VIOLATION_EXECUTABLE))
7683                       ? PFERR_PRESENT_MASK : 0;
7684
7685         error_code |= (exit_qualification & 0x100) != 0 ?
7686                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
7687
7688         vcpu->arch.exit_qualification = exit_qualification;
7689         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
7690 }
7691
7692 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
7693 {
7694         gpa_t gpa;
7695
7696         /*
7697          * A nested guest cannot optimize MMIO vmexits, because we have an
7698          * nGPA here instead of the required GPA.
7699          */
7700         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7701         if (!is_guest_mode(vcpu) &&
7702             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
7703                 trace_kvm_fast_mmio(gpa);
7704                 /*
7705                  * Doing kvm_skip_emulated_instruction() depends on undefined
7706                  * behavior: Intel's manual doesn't mandate
7707                  * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
7708                  * occurs and while on real hardware it was observed to be set,
7709                  * other hypervisors (namely Hyper-V) don't set it, we end up
7710                  * advancing IP with some random value. Disable fast mmio when
7711                  * running nested and keep it for real hardware in hope that
7712                  * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
7713                  */
7714                 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
7715                         return kvm_skip_emulated_instruction(vcpu);
7716                 else
7717                         return kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) ==
7718                                                                 EMULATE_DONE;
7719         }
7720
7721         return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
7722 }
7723
7724 static int handle_nmi_window(struct kvm_vcpu *vcpu)
7725 {
7726         WARN_ON_ONCE(!enable_vnmi);
7727         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7728                         CPU_BASED_VIRTUAL_NMI_PENDING);
7729         ++vcpu->stat.nmi_window_exits;
7730         kvm_make_request(KVM_REQ_EVENT, vcpu);
7731
7732         return 1;
7733 }
7734
7735 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
7736 {
7737         struct vcpu_vmx *vmx = to_vmx(vcpu);
7738         enum emulation_result err = EMULATE_DONE;
7739         int ret = 1;
7740         u32 cpu_exec_ctrl;
7741         bool intr_window_requested;
7742         unsigned count = 130;
7743
7744         /*
7745          * We should never reach the point where we are emulating L2
7746          * due to invalid guest state as that means we incorrectly
7747          * allowed a nested VMEntry with an invalid vmcs12.
7748          */
7749         WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
7750
7751         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7752         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
7753
7754         while (vmx->emulation_required && count-- != 0) {
7755                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
7756                         return handle_interrupt_window(&vmx->vcpu);
7757
7758                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
7759                         return 1;
7760
7761                 err = kvm_emulate_instruction(vcpu, 0);
7762
7763                 if (err == EMULATE_USER_EXIT) {
7764                         ++vcpu->stat.mmio_exits;
7765                         ret = 0;
7766                         goto out;
7767                 }
7768
7769                 if (err != EMULATE_DONE)
7770                         goto emulation_error;
7771
7772                 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
7773                     vcpu->arch.exception.pending)
7774                         goto emulation_error;
7775
7776                 if (vcpu->arch.halt_request) {
7777                         vcpu->arch.halt_request = 0;
7778                         ret = kvm_vcpu_halt(vcpu);
7779                         goto out;
7780                 }
7781
7782                 if (signal_pending(current))
7783                         goto out;
7784                 if (need_resched())
7785                         schedule();
7786         }
7787
7788 out:
7789         return ret;
7790
7791 emulation_error:
7792         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7793         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7794         vcpu->run->internal.ndata = 0;
7795         return 0;
7796 }
7797
7798 static void grow_ple_window(struct kvm_vcpu *vcpu)
7799 {
7800         struct vcpu_vmx *vmx = to_vmx(vcpu);
7801         int old = vmx->ple_window;
7802
7803         vmx->ple_window = __grow_ple_window(old, ple_window,
7804                                             ple_window_grow,
7805                                             ple_window_max);
7806
7807         if (vmx->ple_window != old)
7808                 vmx->ple_window_dirty = true;
7809
7810         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
7811 }
7812
7813 static void shrink_ple_window(struct kvm_vcpu *vcpu)
7814 {
7815         struct vcpu_vmx *vmx = to_vmx(vcpu);
7816         int old = vmx->ple_window;
7817
7818         vmx->ple_window = __shrink_ple_window(old, ple_window,
7819                                               ple_window_shrink,
7820                                               ple_window);
7821
7822         if (vmx->ple_window != old)
7823                 vmx->ple_window_dirty = true;
7824
7825         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
7826 }
7827
7828 /*
7829  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
7830  */
7831 static void wakeup_handler(void)
7832 {
7833         struct kvm_vcpu *vcpu;
7834         int cpu = smp_processor_id();
7835
7836         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7837         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
7838                         blocked_vcpu_list) {
7839                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7840
7841                 if (pi_test_on(pi_desc) == 1)
7842                         kvm_vcpu_kick(vcpu);
7843         }
7844         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7845 }
7846
7847 static void vmx_enable_tdp(void)
7848 {
7849         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
7850                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
7851                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
7852                 0ull, VMX_EPT_EXECUTABLE_MASK,
7853                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
7854                 VMX_EPT_RWX_MASK, 0ull);
7855
7856         ept_set_mmio_spte_mask();
7857         kvm_enable_tdp();
7858 }
7859
7860 static __init int hardware_setup(void)
7861 {
7862         unsigned long host_bndcfgs;
7863         int r = -ENOMEM, i;
7864
7865         rdmsrl_safe(MSR_EFER, &host_efer);
7866
7867         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7868                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7869
7870         for (i = 0; i < VMX_BITMAP_NR; i++) {
7871                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
7872                 if (!vmx_bitmap[i])
7873                         goto out;
7874         }
7875
7876         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
7877         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
7878
7879         if (setup_vmcs_config(&vmcs_config) < 0) {
7880                 r = -EIO;
7881                 goto out;
7882         }
7883
7884         if (boot_cpu_has(X86_FEATURE_NX))
7885                 kvm_enable_efer_bits(EFER_NX);
7886
7887         if (boot_cpu_has(X86_FEATURE_MPX)) {
7888                 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7889                 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7890         }
7891
7892         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7893                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7894                 enable_vpid = 0;
7895
7896         if (!cpu_has_vmx_ept() ||
7897             !cpu_has_vmx_ept_4levels() ||
7898             !cpu_has_vmx_ept_mt_wb() ||
7899             !cpu_has_vmx_invept_global())
7900                 enable_ept = 0;
7901
7902         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7903                 enable_ept_ad_bits = 0;
7904
7905         if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7906                 enable_unrestricted_guest = 0;
7907
7908         if (!cpu_has_vmx_flexpriority())
7909                 flexpriority_enabled = 0;
7910
7911         if (!cpu_has_virtual_nmis())
7912                 enable_vnmi = 0;
7913
7914         /*
7915          * set_apic_access_page_addr() is used to reload apic access
7916          * page upon invalidation.  No need to do anything if not
7917          * using the APIC_ACCESS_ADDR VMCS field.
7918          */
7919         if (!flexpriority_enabled)
7920                 kvm_x86_ops->set_apic_access_page_addr = NULL;
7921
7922         if (!cpu_has_vmx_tpr_shadow())
7923                 kvm_x86_ops->update_cr8_intercept = NULL;
7924
7925         if (enable_ept && !cpu_has_vmx_ept_2m_page())
7926                 kvm_disable_largepages();
7927
7928 #if IS_ENABLED(CONFIG_HYPERV)
7929         if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7930             && enable_ept)
7931                 kvm_x86_ops->tlb_remote_flush = vmx_hv_remote_flush_tlb;
7932 #endif
7933
7934         if (!cpu_has_vmx_ple()) {
7935                 ple_gap = 0;
7936                 ple_window = 0;
7937                 ple_window_grow = 0;
7938                 ple_window_max = 0;
7939                 ple_window_shrink = 0;
7940         }
7941
7942         if (!cpu_has_vmx_apicv()) {
7943                 enable_apicv = 0;
7944                 kvm_x86_ops->sync_pir_to_irr = NULL;
7945         }
7946
7947         if (cpu_has_vmx_tsc_scaling()) {
7948                 kvm_has_tsc_control = true;
7949                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7950                 kvm_tsc_scaling_ratio_frac_bits = 48;
7951         }
7952
7953         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7954
7955         if (enable_ept)
7956                 vmx_enable_tdp();
7957         else
7958                 kvm_disable_tdp();
7959
7960         if (!nested) {
7961                 kvm_x86_ops->get_nested_state = NULL;
7962                 kvm_x86_ops->set_nested_state = NULL;
7963         }
7964
7965         /*
7966          * Only enable PML when hardware supports PML feature, and both EPT
7967          * and EPT A/D bit features are enabled -- PML depends on them to work.
7968          */
7969         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7970                 enable_pml = 0;
7971
7972         if (!enable_pml) {
7973                 kvm_x86_ops->slot_enable_log_dirty = NULL;
7974                 kvm_x86_ops->slot_disable_log_dirty = NULL;
7975                 kvm_x86_ops->flush_log_dirty = NULL;
7976                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7977         }
7978
7979         if (!cpu_has_vmx_preemption_timer())
7980                 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7981
7982         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7983                 u64 vmx_msr;
7984
7985                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7986                 cpu_preemption_timer_multi =
7987                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7988         } else {
7989                 kvm_x86_ops->set_hv_timer = NULL;
7990                 kvm_x86_ops->cancel_hv_timer = NULL;
7991         }
7992
7993         if (!cpu_has_vmx_shadow_vmcs())
7994                 enable_shadow_vmcs = 0;
7995         if (enable_shadow_vmcs)
7996                 init_vmcs_shadow_fields();
7997
7998         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7999         nested_vmx_setup_ctls_msrs(&vmcs_config.nested, enable_apicv);
8000
8001         kvm_mce_cap_supported |= MCG_LMCE_P;
8002
8003         return alloc_kvm_area();
8004
8005 out:
8006         for (i = 0; i < VMX_BITMAP_NR; i++)
8007                 free_page((unsigned long)vmx_bitmap[i]);
8008
8009     return r;
8010 }
8011
8012 static __exit void hardware_unsetup(void)
8013 {
8014         int i;
8015
8016         for (i = 0; i < VMX_BITMAP_NR; i++)
8017                 free_page((unsigned long)vmx_bitmap[i]);
8018
8019         free_kvm_area();
8020 }
8021
8022 /*
8023  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
8024  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
8025  */
8026 static int handle_pause(struct kvm_vcpu *vcpu)
8027 {
8028         if (!kvm_pause_in_guest(vcpu->kvm))
8029                 grow_ple_window(vcpu);
8030
8031         /*
8032          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
8033          * VM-execution control is ignored if CPL > 0. OTOH, KVM
8034          * never set PAUSE_EXITING and just set PLE if supported,
8035          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
8036          */
8037         kvm_vcpu_on_spin(vcpu, true);
8038         return kvm_skip_emulated_instruction(vcpu);
8039 }
8040
8041 static int handle_nop(struct kvm_vcpu *vcpu)
8042 {
8043         return kvm_skip_emulated_instruction(vcpu);
8044 }
8045
8046 static int handle_mwait(struct kvm_vcpu *vcpu)
8047 {
8048         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
8049         return handle_nop(vcpu);
8050 }
8051
8052 static int handle_invalid_op(struct kvm_vcpu *vcpu)
8053 {
8054         kvm_queue_exception(vcpu, UD_VECTOR);
8055         return 1;
8056 }
8057
8058 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
8059 {
8060         return 1;
8061 }
8062
8063 static int handle_monitor(struct kvm_vcpu *vcpu)
8064 {
8065         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
8066         return handle_nop(vcpu);
8067 }
8068
8069 /*
8070  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
8071  * set the success or error code of an emulated VMX instruction (as specified
8072  * by Vol 2B, VMX Instruction Reference, "Conventions"), and skip the emulated
8073  * instruction.
8074  */
8075 static int nested_vmx_succeed(struct kvm_vcpu *vcpu)
8076 {
8077         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
8078                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
8079                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
8080         return kvm_skip_emulated_instruction(vcpu);
8081 }
8082
8083 static int nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
8084 {
8085         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
8086                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
8087                             X86_EFLAGS_SF | X86_EFLAGS_OF))
8088                         | X86_EFLAGS_CF);
8089         return kvm_skip_emulated_instruction(vcpu);
8090 }
8091
8092 static int nested_vmx_failValid(struct kvm_vcpu *vcpu,
8093                                 u32 vm_instruction_error)
8094 {
8095         /*
8096          * failValid writes the error number to the current VMCS, which
8097          * can't be done if there isn't a current VMCS.
8098          */
8099         if (to_vmx(vcpu)->nested.current_vmptr == -1ull)
8100                 return nested_vmx_failInvalid(vcpu);
8101
8102         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
8103                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
8104                             X86_EFLAGS_SF | X86_EFLAGS_OF))
8105                         | X86_EFLAGS_ZF);
8106         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
8107         /*
8108          * We don't need to force a shadow sync because
8109          * VM_INSTRUCTION_ERROR is not shadowed
8110          */
8111         return kvm_skip_emulated_instruction(vcpu);
8112 }
8113
8114 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
8115 {
8116         /* TODO: not to reset guest simply here. */
8117         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8118         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
8119 }
8120
8121 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
8122 {
8123         struct vcpu_vmx *vmx =
8124                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
8125
8126         vmx->nested.preemption_timer_expired = true;
8127         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
8128         kvm_vcpu_kick(&vmx->vcpu);
8129
8130         return HRTIMER_NORESTART;
8131 }
8132
8133 /*
8134  * Decode the memory-address operand of a vmx instruction, as recorded on an
8135  * exit caused by such an instruction (run by a guest hypervisor).
8136  * On success, returns 0. When the operand is invalid, returns 1 and throws
8137  * #UD or #GP.
8138  */
8139 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
8140                                  unsigned long exit_qualification,
8141                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
8142 {
8143         gva_t off;
8144         bool exn;
8145         struct kvm_segment s;
8146
8147         /*
8148          * According to Vol. 3B, "Information for VM Exits Due to Instruction
8149          * Execution", on an exit, vmx_instruction_info holds most of the
8150          * addressing components of the operand. Only the displacement part
8151          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
8152          * For how an actual address is calculated from all these components,
8153          * refer to Vol. 1, "Operand Addressing".
8154          */
8155         int  scaling = vmx_instruction_info & 3;
8156         int  addr_size = (vmx_instruction_info >> 7) & 7;
8157         bool is_reg = vmx_instruction_info & (1u << 10);
8158         int  seg_reg = (vmx_instruction_info >> 15) & 7;
8159         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
8160         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
8161         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
8162         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
8163
8164         if (is_reg) {
8165                 kvm_queue_exception(vcpu, UD_VECTOR);
8166                 return 1;
8167         }
8168
8169         /* Addr = segment_base + offset */
8170         /* offset = base + [index * scale] + displacement */
8171         off = exit_qualification; /* holds the displacement */
8172         if (base_is_valid)
8173                 off += kvm_register_read(vcpu, base_reg);
8174         if (index_is_valid)
8175                 off += kvm_register_read(vcpu, index_reg)<<scaling;
8176         vmx_get_segment(vcpu, &s, seg_reg);
8177         *ret = s.base + off;
8178
8179         if (addr_size == 1) /* 32 bit */
8180                 *ret &= 0xffffffff;
8181
8182         /* Checks for #GP/#SS exceptions. */
8183         exn = false;
8184         if (is_long_mode(vcpu)) {
8185                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
8186                  * non-canonical form. This is the only check on the memory
8187                  * destination for long mode!
8188                  */
8189                 exn = is_noncanonical_address(*ret, vcpu);
8190         } else if (is_protmode(vcpu)) {
8191                 /* Protected mode: apply checks for segment validity in the
8192                  * following order:
8193                  * - segment type check (#GP(0) may be thrown)
8194                  * - usability check (#GP(0)/#SS(0))
8195                  * - limit check (#GP(0)/#SS(0))
8196                  */
8197                 if (wr)
8198                         /* #GP(0) if the destination operand is located in a
8199                          * read-only data segment or any code segment.
8200                          */
8201                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
8202                 else
8203                         /* #GP(0) if the source operand is located in an
8204                          * execute-only code segment
8205                          */
8206                         exn = ((s.type & 0xa) == 8);
8207                 if (exn) {
8208                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8209                         return 1;
8210                 }
8211                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
8212                  */
8213                 exn = (s.unusable != 0);
8214                 /* Protected mode: #GP(0)/#SS(0) if the memory
8215                  * operand is outside the segment limit.
8216                  */
8217                 exn = exn || (off + sizeof(u64) > s.limit);
8218         }
8219         if (exn) {
8220                 kvm_queue_exception_e(vcpu,
8221                                       seg_reg == VCPU_SREG_SS ?
8222                                                 SS_VECTOR : GP_VECTOR,
8223                                       0);
8224                 return 1;
8225         }
8226
8227         return 0;
8228 }
8229
8230 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
8231 {
8232         gva_t gva;
8233         struct x86_exception e;
8234
8235         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8236                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
8237                 return 1;
8238
8239         if (kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e)) {
8240                 kvm_inject_page_fault(vcpu, &e);
8241                 return 1;
8242         }
8243
8244         return 0;
8245 }
8246
8247 /*
8248  * Allocate a shadow VMCS and associate it with the currently loaded
8249  * VMCS, unless such a shadow VMCS already exists. The newly allocated
8250  * VMCS is also VMCLEARed, so that it is ready for use.
8251  */
8252 static struct vmcs *alloc_shadow_vmcs(struct kvm_vcpu *vcpu)
8253 {
8254         struct vcpu_vmx *vmx = to_vmx(vcpu);
8255         struct loaded_vmcs *loaded_vmcs = vmx->loaded_vmcs;
8256
8257         /*
8258          * We should allocate a shadow vmcs for vmcs01 only when L1
8259          * executes VMXON and free it when L1 executes VMXOFF.
8260          * As it is invalid to execute VMXON twice, we shouldn't reach
8261          * here when vmcs01 already have an allocated shadow vmcs.
8262          */
8263         WARN_ON(loaded_vmcs == &vmx->vmcs01 && loaded_vmcs->shadow_vmcs);
8264
8265         if (!loaded_vmcs->shadow_vmcs) {
8266                 loaded_vmcs->shadow_vmcs = alloc_vmcs(true);
8267                 if (loaded_vmcs->shadow_vmcs)
8268                         vmcs_clear(loaded_vmcs->shadow_vmcs);
8269         }
8270         return loaded_vmcs->shadow_vmcs;
8271 }
8272
8273 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
8274 {
8275         struct vcpu_vmx *vmx = to_vmx(vcpu);
8276         int r;
8277
8278         r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
8279         if (r < 0)
8280                 goto out_vmcs02;
8281
8282         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
8283         if (!vmx->nested.cached_vmcs12)
8284                 goto out_cached_vmcs12;
8285
8286         vmx->nested.cached_shadow_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
8287         if (!vmx->nested.cached_shadow_vmcs12)
8288                 goto out_cached_shadow_vmcs12;
8289
8290         if (enable_shadow_vmcs && !alloc_shadow_vmcs(vcpu))
8291                 goto out_shadow_vmcs;
8292
8293         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
8294                      HRTIMER_MODE_REL_PINNED);
8295         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
8296
8297         vmx->nested.vpid02 = allocate_vpid();
8298
8299         vmx->nested.vmcs02_initialized = false;
8300         vmx->nested.vmxon = true;
8301         return 0;
8302
8303 out_shadow_vmcs:
8304         kfree(vmx->nested.cached_shadow_vmcs12);
8305
8306 out_cached_shadow_vmcs12:
8307         kfree(vmx->nested.cached_vmcs12);
8308
8309 out_cached_vmcs12:
8310         free_loaded_vmcs(&vmx->nested.vmcs02);
8311
8312 out_vmcs02:
8313         return -ENOMEM;
8314 }
8315
8316 /*
8317  * Emulate the VMXON instruction.
8318  * Currently, we just remember that VMX is active, and do not save or even
8319  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
8320  * do not currently need to store anything in that guest-allocated memory
8321  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
8322  * argument is different from the VMXON pointer (which the spec says they do).
8323  */
8324 static int handle_vmon(struct kvm_vcpu *vcpu)
8325 {
8326         int ret;
8327         gpa_t vmptr;
8328         struct page *page;
8329         struct vcpu_vmx *vmx = to_vmx(vcpu);
8330         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
8331                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
8332
8333         /*
8334          * The Intel VMX Instruction Reference lists a bunch of bits that are
8335          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
8336          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
8337          * Otherwise, we should fail with #UD.  But most faulting conditions
8338          * have already been checked by hardware, prior to the VM-exit for
8339          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
8340          * that bit set to 1 in non-root mode.
8341          */
8342         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
8343                 kvm_queue_exception(vcpu, UD_VECTOR);
8344                 return 1;
8345         }
8346
8347         /* CPL=0 must be checked manually. */
8348         if (vmx_get_cpl(vcpu)) {
8349                 kvm_inject_gp(vcpu, 0);
8350                 return 1;
8351         }
8352
8353         if (vmx->nested.vmxon)
8354                 return nested_vmx_failValid(vcpu,
8355                         VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
8356
8357         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
8358                         != VMXON_NEEDED_FEATURES) {
8359                 kvm_inject_gp(vcpu, 0);
8360                 return 1;
8361         }
8362
8363         if (nested_vmx_get_vmptr(vcpu, &vmptr))
8364                 return 1;
8365
8366         /*
8367          * SDM 3: 24.11.5
8368          * The first 4 bytes of VMXON region contain the supported
8369          * VMCS revision identifier
8370          *
8371          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
8372          * which replaces physical address width with 32
8373          */
8374         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu)))
8375                 return nested_vmx_failInvalid(vcpu);
8376
8377         page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8378         if (is_error_page(page))
8379                 return nested_vmx_failInvalid(vcpu);
8380
8381         if (*(u32 *)kmap(page) != VMCS12_REVISION) {
8382                 kunmap(page);
8383                 kvm_release_page_clean(page);
8384                 return nested_vmx_failInvalid(vcpu);
8385         }
8386         kunmap(page);
8387         kvm_release_page_clean(page);
8388
8389         vmx->nested.vmxon_ptr = vmptr;
8390         ret = enter_vmx_operation(vcpu);
8391         if (ret)
8392                 return ret;
8393
8394         return nested_vmx_succeed(vcpu);
8395 }
8396
8397 /*
8398  * Intel's VMX Instruction Reference specifies a common set of prerequisites
8399  * for running VMX instructions (except VMXON, whose prerequisites are
8400  * slightly different). It also specifies what exception to inject otherwise.
8401  * Note that many of these exceptions have priority over VM exits, so they
8402  * don't have to be checked again here.
8403  */
8404 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
8405 {
8406         if (!to_vmx(vcpu)->nested.vmxon) {
8407                 kvm_queue_exception(vcpu, UD_VECTOR);
8408                 return 0;
8409         }
8410
8411         if (vmx_get_cpl(vcpu)) {
8412                 kvm_inject_gp(vcpu, 0);
8413                 return 0;
8414         }
8415
8416         return 1;
8417 }
8418
8419 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
8420 {
8421         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
8422         vmcs_write64(VMCS_LINK_POINTER, -1ull);
8423 }
8424
8425 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
8426 {
8427         if (vmx->nested.current_vmptr == -1ull)
8428                 return;
8429
8430         if (enable_shadow_vmcs) {
8431                 /* copy to memory all shadowed fields in case
8432                    they were modified */
8433                 copy_shadow_to_vmcs12(vmx);
8434                 vmx->nested.sync_shadow_vmcs = false;
8435                 vmx_disable_shadow_vmcs(vmx);
8436         }
8437         vmx->nested.posted_intr_nv = -1;
8438
8439         /* Flush VMCS12 to guest memory */
8440         kvm_vcpu_write_guest_page(&vmx->vcpu,
8441                                   vmx->nested.current_vmptr >> PAGE_SHIFT,
8442                                   vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
8443
8444         vmx->nested.current_vmptr = -1ull;
8445 }
8446
8447 /*
8448  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
8449  * just stops using VMX.
8450  */
8451 static void free_nested(struct vcpu_vmx *vmx)
8452 {
8453         if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
8454                 return;
8455
8456         vmx->nested.vmxon = false;
8457         vmx->nested.smm.vmxon = false;
8458         free_vpid(vmx->nested.vpid02);
8459         vmx->nested.posted_intr_nv = -1;
8460         vmx->nested.current_vmptr = -1ull;
8461         if (enable_shadow_vmcs) {
8462                 vmx_disable_shadow_vmcs(vmx);
8463                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
8464                 free_vmcs(vmx->vmcs01.shadow_vmcs);
8465                 vmx->vmcs01.shadow_vmcs = NULL;
8466         }
8467         kfree(vmx->nested.cached_vmcs12);
8468         kfree(vmx->nested.cached_shadow_vmcs12);
8469         /* Unpin physical memory we referred to in the vmcs02 */
8470         if (vmx->nested.apic_access_page) {
8471                 kvm_release_page_dirty(vmx->nested.apic_access_page);
8472                 vmx->nested.apic_access_page = NULL;
8473         }
8474         if (vmx->nested.virtual_apic_page) {
8475                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
8476                 vmx->nested.virtual_apic_page = NULL;
8477         }
8478         if (vmx->nested.pi_desc_page) {
8479                 kunmap(vmx->nested.pi_desc_page);
8480                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
8481                 vmx->nested.pi_desc_page = NULL;
8482                 vmx->nested.pi_desc = NULL;
8483         }
8484
8485         free_loaded_vmcs(&vmx->nested.vmcs02);
8486 }
8487
8488 /* Emulate the VMXOFF instruction */
8489 static int handle_vmoff(struct kvm_vcpu *vcpu)
8490 {
8491         if (!nested_vmx_check_permission(vcpu))
8492                 return 1;
8493         free_nested(to_vmx(vcpu));
8494         return nested_vmx_succeed(vcpu);
8495 }
8496
8497 /* Emulate the VMCLEAR instruction */
8498 static int handle_vmclear(struct kvm_vcpu *vcpu)
8499 {
8500         struct vcpu_vmx *vmx = to_vmx(vcpu);
8501         u32 zero = 0;
8502         gpa_t vmptr;
8503
8504         if (!nested_vmx_check_permission(vcpu))
8505                 return 1;
8506
8507         if (nested_vmx_get_vmptr(vcpu, &vmptr))
8508                 return 1;
8509
8510         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu)))
8511                 return nested_vmx_failValid(vcpu,
8512                         VMXERR_VMCLEAR_INVALID_ADDRESS);
8513
8514         if (vmptr == vmx->nested.vmxon_ptr)
8515                 return nested_vmx_failValid(vcpu,
8516                         VMXERR_VMCLEAR_VMXON_POINTER);
8517
8518         if (vmptr == vmx->nested.current_vmptr)
8519                 nested_release_vmcs12(vmx);
8520
8521         kvm_vcpu_write_guest(vcpu,
8522                         vmptr + offsetof(struct vmcs12, launch_state),
8523                         &zero, sizeof(zero));
8524
8525         return nested_vmx_succeed(vcpu);
8526 }
8527
8528 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
8529
8530 /* Emulate the VMLAUNCH instruction */
8531 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
8532 {
8533         return nested_vmx_run(vcpu, true);
8534 }
8535
8536 /* Emulate the VMRESUME instruction */
8537 static int handle_vmresume(struct kvm_vcpu *vcpu)
8538 {
8539
8540         return nested_vmx_run(vcpu, false);
8541 }
8542
8543 /*
8544  * Read a vmcs12 field. Since these can have varying lengths and we return
8545  * one type, we chose the biggest type (u64) and zero-extend the return value
8546  * to that size. Note that the caller, handle_vmread, might need to use only
8547  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
8548  * 64-bit fields are to be returned).
8549  */
8550 static inline int vmcs12_read_any(struct vmcs12 *vmcs12,
8551                                   unsigned long field, u64 *ret)
8552 {
8553         short offset = vmcs_field_to_offset(field);
8554         char *p;
8555
8556         if (offset < 0)
8557                 return offset;
8558
8559         p = (char *)vmcs12 + offset;
8560
8561         switch (vmcs_field_width(field)) {
8562         case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8563                 *ret = *((natural_width *)p);
8564                 return 0;
8565         case VMCS_FIELD_WIDTH_U16:
8566                 *ret = *((u16 *)p);
8567                 return 0;
8568         case VMCS_FIELD_WIDTH_U32:
8569                 *ret = *((u32 *)p);
8570                 return 0;
8571         case VMCS_FIELD_WIDTH_U64:
8572                 *ret = *((u64 *)p);
8573                 return 0;
8574         default:
8575                 WARN_ON(1);
8576                 return -ENOENT;
8577         }
8578 }
8579
8580
8581 static inline int vmcs12_write_any(struct vmcs12 *vmcs12,
8582                                    unsigned long field, u64 field_value){
8583         short offset = vmcs_field_to_offset(field);
8584         char *p = (char *)vmcs12 + offset;
8585         if (offset < 0)
8586                 return offset;
8587
8588         switch (vmcs_field_width(field)) {
8589         case VMCS_FIELD_WIDTH_U16:
8590                 *(u16 *)p = field_value;
8591                 return 0;
8592         case VMCS_FIELD_WIDTH_U32:
8593                 *(u32 *)p = field_value;
8594                 return 0;
8595         case VMCS_FIELD_WIDTH_U64:
8596                 *(u64 *)p = field_value;
8597                 return 0;
8598         case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8599                 *(natural_width *)p = field_value;
8600                 return 0;
8601         default:
8602                 WARN_ON(1);
8603                 return -ENOENT;
8604         }
8605
8606 }
8607
8608 /*
8609  * Copy the writable VMCS shadow fields back to the VMCS12, in case
8610  * they have been modified by the L1 guest. Note that the "read-only"
8611  * VM-exit information fields are actually writable if the vCPU is
8612  * configured to support "VMWRITE to any supported field in the VMCS."
8613  */
8614 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
8615 {
8616         const u16 *fields[] = {
8617                 shadow_read_write_fields,
8618                 shadow_read_only_fields
8619         };
8620         const int max_fields[] = {
8621                 max_shadow_read_write_fields,
8622                 max_shadow_read_only_fields
8623         };
8624         int i, q;
8625         unsigned long field;
8626         u64 field_value;
8627         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8628
8629         preempt_disable();
8630
8631         vmcs_load(shadow_vmcs);
8632
8633         for (q = 0; q < ARRAY_SIZE(fields); q++) {
8634                 for (i = 0; i < max_fields[q]; i++) {
8635                         field = fields[q][i];
8636                         field_value = __vmcs_readl(field);
8637                         vmcs12_write_any(get_vmcs12(&vmx->vcpu), field, field_value);
8638                 }
8639                 /*
8640                  * Skip the VM-exit information fields if they are read-only.
8641                  */
8642                 if (!nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
8643                         break;
8644         }
8645
8646         vmcs_clear(shadow_vmcs);
8647         vmcs_load(vmx->loaded_vmcs->vmcs);
8648
8649         preempt_enable();
8650 }
8651
8652 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
8653 {
8654         const u16 *fields[] = {
8655                 shadow_read_write_fields,
8656                 shadow_read_only_fields
8657         };
8658         const int max_fields[] = {
8659                 max_shadow_read_write_fields,
8660                 max_shadow_read_only_fields
8661         };
8662         int i, q;
8663         unsigned long field;
8664         u64 field_value = 0;
8665         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8666
8667         vmcs_load(shadow_vmcs);
8668
8669         for (q = 0; q < ARRAY_SIZE(fields); q++) {
8670                 for (i = 0; i < max_fields[q]; i++) {
8671                         field = fields[q][i];
8672                         vmcs12_read_any(get_vmcs12(&vmx->vcpu), field, &field_value);
8673                         __vmcs_writel(field, field_value);
8674                 }
8675         }
8676
8677         vmcs_clear(shadow_vmcs);
8678         vmcs_load(vmx->loaded_vmcs->vmcs);
8679 }
8680
8681 static int handle_vmread(struct kvm_vcpu *vcpu)
8682 {
8683         unsigned long field;
8684         u64 field_value;
8685         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8686         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8687         gva_t gva = 0;
8688         struct vmcs12 *vmcs12;
8689
8690         if (!nested_vmx_check_permission(vcpu))
8691                 return 1;
8692
8693         if (to_vmx(vcpu)->nested.current_vmptr == -1ull)
8694                 return nested_vmx_failInvalid(vcpu);
8695
8696         if (!is_guest_mode(vcpu))
8697                 vmcs12 = get_vmcs12(vcpu);
8698         else {
8699                 /*
8700                  * When vmcs->vmcs_link_pointer is -1ull, any VMREAD
8701                  * to shadowed-field sets the ALU flags for VMfailInvalid.
8702                  */
8703                 if (get_vmcs12(vcpu)->vmcs_link_pointer == -1ull)
8704                         return nested_vmx_failInvalid(vcpu);
8705                 vmcs12 = get_shadow_vmcs12(vcpu);
8706         }
8707
8708         /* Decode instruction info and find the field to read */
8709         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8710         /* Read the field, zero-extended to a u64 field_value */
8711         if (vmcs12_read_any(vmcs12, field, &field_value) < 0)
8712                 return nested_vmx_failValid(vcpu,
8713                         VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8714
8715         /*
8716          * Now copy part of this value to register or memory, as requested.
8717          * Note that the number of bits actually copied is 32 or 64 depending
8718          * on the guest's mode (32 or 64 bit), not on the given field's length.
8719          */
8720         if (vmx_instruction_info & (1u << 10)) {
8721                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
8722                         field_value);
8723         } else {
8724                 if (get_vmx_mem_address(vcpu, exit_qualification,
8725                                 vmx_instruction_info, true, &gva))
8726                         return 1;
8727                 /* _system ok, nested_vmx_check_permission has verified cpl=0 */
8728                 kvm_write_guest_virt_system(vcpu, gva, &field_value,
8729                                             (is_long_mode(vcpu) ? 8 : 4), NULL);
8730         }
8731
8732         return nested_vmx_succeed(vcpu);
8733 }
8734
8735
8736 static int handle_vmwrite(struct kvm_vcpu *vcpu)
8737 {
8738         unsigned long field;
8739         gva_t gva;
8740         struct vcpu_vmx *vmx = to_vmx(vcpu);
8741         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8742         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8743
8744         /* The value to write might be 32 or 64 bits, depending on L1's long
8745          * mode, and eventually we need to write that into a field of several
8746          * possible lengths. The code below first zero-extends the value to 64
8747          * bit (field_value), and then copies only the appropriate number of
8748          * bits into the vmcs12 field.
8749          */
8750         u64 field_value = 0;
8751         struct x86_exception e;
8752         struct vmcs12 *vmcs12;
8753
8754         if (!nested_vmx_check_permission(vcpu))
8755                 return 1;
8756
8757         if (vmx->nested.current_vmptr == -1ull)
8758                 return nested_vmx_failInvalid(vcpu);
8759
8760         if (vmx_instruction_info & (1u << 10))
8761                 field_value = kvm_register_readl(vcpu,
8762                         (((vmx_instruction_info) >> 3) & 0xf));
8763         else {
8764                 if (get_vmx_mem_address(vcpu, exit_qualification,
8765                                 vmx_instruction_info, false, &gva))
8766                         return 1;
8767                 if (kvm_read_guest_virt(vcpu, gva, &field_value,
8768                                         (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
8769                         kvm_inject_page_fault(vcpu, &e);
8770                         return 1;
8771                 }
8772         }
8773
8774
8775         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8776         /*
8777          * If the vCPU supports "VMWRITE to any supported field in the
8778          * VMCS," then the "read-only" fields are actually read/write.
8779          */
8780         if (vmcs_field_readonly(field) &&
8781             !nested_cpu_has_vmwrite_any_field(vcpu))
8782                 return nested_vmx_failValid(vcpu,
8783                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
8784
8785         if (!is_guest_mode(vcpu))
8786                 vmcs12 = get_vmcs12(vcpu);
8787         else {
8788                 /*
8789                  * When vmcs->vmcs_link_pointer is -1ull, any VMWRITE
8790                  * to shadowed-field sets the ALU flags for VMfailInvalid.
8791                  */
8792                 if (get_vmcs12(vcpu)->vmcs_link_pointer == -1ull)
8793                         return nested_vmx_failInvalid(vcpu);
8794                 vmcs12 = get_shadow_vmcs12(vcpu);
8795         }
8796
8797         if (vmcs12_write_any(vmcs12, field, field_value) < 0)
8798                 return nested_vmx_failValid(vcpu,
8799                         VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8800
8801         /*
8802          * Do not track vmcs12 dirty-state if in guest-mode
8803          * as we actually dirty shadow vmcs12 instead of vmcs12.
8804          */
8805         if (!is_guest_mode(vcpu)) {
8806                 switch (field) {
8807 #define SHADOW_FIELD_RW(x) case x:
8808 #include "vmx_shadow_fields.h"
8809                         /*
8810                          * The fields that can be updated by L1 without a vmexit are
8811                          * always updated in the vmcs02, the others go down the slow
8812                          * path of prepare_vmcs02.
8813                          */
8814                         break;
8815                 default:
8816                         vmx->nested.dirty_vmcs12 = true;
8817                         break;
8818                 }
8819         }
8820
8821         return nested_vmx_succeed(vcpu);
8822 }
8823
8824 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
8825 {
8826         vmx->nested.current_vmptr = vmptr;
8827         if (enable_shadow_vmcs) {
8828                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
8829                               SECONDARY_EXEC_SHADOW_VMCS);
8830                 vmcs_write64(VMCS_LINK_POINTER,
8831                              __pa(vmx->vmcs01.shadow_vmcs));
8832                 vmx->nested.sync_shadow_vmcs = true;
8833         }
8834         vmx->nested.dirty_vmcs12 = true;
8835 }
8836
8837 /* Emulate the VMPTRLD instruction */
8838 static int handle_vmptrld(struct kvm_vcpu *vcpu)
8839 {
8840         struct vcpu_vmx *vmx = to_vmx(vcpu);
8841         gpa_t vmptr;
8842
8843         if (!nested_vmx_check_permission(vcpu))
8844                 return 1;
8845
8846         if (nested_vmx_get_vmptr(vcpu, &vmptr))
8847                 return 1;
8848
8849         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu)))
8850                 return nested_vmx_failValid(vcpu,
8851                         VMXERR_VMPTRLD_INVALID_ADDRESS);
8852
8853         if (vmptr == vmx->nested.vmxon_ptr)
8854                 return nested_vmx_failValid(vcpu,
8855                         VMXERR_VMPTRLD_VMXON_POINTER);
8856
8857         if (vmx->nested.current_vmptr != vmptr) {
8858                 struct vmcs12 *new_vmcs12;
8859                 struct page *page;
8860                 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8861                 if (is_error_page(page))
8862                         return nested_vmx_failInvalid(vcpu);
8863
8864                 new_vmcs12 = kmap(page);
8865                 if (new_vmcs12->hdr.revision_id != VMCS12_REVISION ||
8866                     (new_vmcs12->hdr.shadow_vmcs &&
8867                      !nested_cpu_has_vmx_shadow_vmcs(vcpu))) {
8868                         kunmap(page);
8869                         kvm_release_page_clean(page);
8870                         return nested_vmx_failValid(vcpu,
8871                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
8872                 }
8873
8874                 nested_release_vmcs12(vmx);
8875                 /*
8876                  * Load VMCS12 from guest memory since it is not already
8877                  * cached.
8878                  */
8879                 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
8880                 kunmap(page);
8881                 kvm_release_page_clean(page);
8882
8883                 set_current_vmptr(vmx, vmptr);
8884         }
8885
8886         return nested_vmx_succeed(vcpu);
8887 }
8888
8889 /* Emulate the VMPTRST instruction */
8890 static int handle_vmptrst(struct kvm_vcpu *vcpu)
8891 {
8892         unsigned long exit_qual = vmcs_readl(EXIT_QUALIFICATION);
8893         u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8894         gpa_t current_vmptr = to_vmx(vcpu)->nested.current_vmptr;
8895         struct x86_exception e;
8896         gva_t gva;
8897
8898         if (!nested_vmx_check_permission(vcpu))
8899                 return 1;
8900
8901         if (get_vmx_mem_address(vcpu, exit_qual, instr_info, true, &gva))
8902                 return 1;
8903         /* *_system ok, nested_vmx_check_permission has verified cpl=0 */
8904         if (kvm_write_guest_virt_system(vcpu, gva, (void *)&current_vmptr,
8905                                         sizeof(gpa_t), &e)) {
8906                 kvm_inject_page_fault(vcpu, &e);
8907                 return 1;
8908         }
8909         return nested_vmx_succeed(vcpu);
8910 }
8911
8912 /* Emulate the INVEPT instruction */
8913 static int handle_invept(struct kvm_vcpu *vcpu)
8914 {
8915         struct vcpu_vmx *vmx = to_vmx(vcpu);
8916         u32 vmx_instruction_info, types;
8917         unsigned long type;
8918         gva_t gva;
8919         struct x86_exception e;
8920         struct {
8921                 u64 eptp, gpa;
8922         } operand;
8923
8924         if (!(vmx->nested.msrs.secondary_ctls_high &
8925               SECONDARY_EXEC_ENABLE_EPT) ||
8926             !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) {
8927                 kvm_queue_exception(vcpu, UD_VECTOR);
8928                 return 1;
8929         }
8930
8931         if (!nested_vmx_check_permission(vcpu))
8932                 return 1;
8933
8934         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8935         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8936
8937         types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
8938
8939         if (type >= 32 || !(types & (1 << type)))
8940                 return nested_vmx_failValid(vcpu,
8941                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8942
8943         /* According to the Intel VMX instruction reference, the memory
8944          * operand is read even if it isn't needed (e.g., for type==global)
8945          */
8946         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8947                         vmx_instruction_info, false, &gva))
8948                 return 1;
8949         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
8950                 kvm_inject_page_fault(vcpu, &e);
8951                 return 1;
8952         }
8953
8954         switch (type) {
8955         case VMX_EPT_EXTENT_GLOBAL:
8956         /*
8957          * TODO: track mappings and invalidate
8958          * single context requests appropriately
8959          */
8960         case VMX_EPT_EXTENT_CONTEXT:
8961                 kvm_mmu_sync_roots(vcpu);
8962                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
8963                 break;
8964         default:
8965                 BUG_ON(1);
8966                 break;
8967         }
8968
8969         return nested_vmx_succeed(vcpu);
8970 }
8971
8972 static u16 nested_get_vpid02(struct kvm_vcpu *vcpu)
8973 {
8974         struct vcpu_vmx *vmx = to_vmx(vcpu);
8975
8976         return vmx->nested.vpid02 ? vmx->nested.vpid02 : vmx->vpid;
8977 }
8978
8979 static int handle_invvpid(struct kvm_vcpu *vcpu)
8980 {
8981         struct vcpu_vmx *vmx = to_vmx(vcpu);
8982         u32 vmx_instruction_info;
8983         unsigned long type, types;
8984         gva_t gva;
8985         struct x86_exception e;
8986         struct {
8987                 u64 vpid;
8988                 u64 gla;
8989         } operand;
8990         u16 vpid02;
8991
8992         if (!(vmx->nested.msrs.secondary_ctls_high &
8993               SECONDARY_EXEC_ENABLE_VPID) ||
8994                         !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) {
8995                 kvm_queue_exception(vcpu, UD_VECTOR);
8996                 return 1;
8997         }
8998
8999         if (!nested_vmx_check_permission(vcpu))
9000                 return 1;
9001
9002         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9003         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
9004
9005         types = (vmx->nested.msrs.vpid_caps &
9006                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
9007
9008         if (type >= 32 || !(types & (1 << type)))
9009                 return nested_vmx_failValid(vcpu,
9010                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9011
9012         /* according to the intel vmx instruction reference, the memory
9013          * operand is read even if it isn't needed (e.g., for type==global)
9014          */
9015         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
9016                         vmx_instruction_info, false, &gva))
9017                 return 1;
9018         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
9019                 kvm_inject_page_fault(vcpu, &e);
9020                 return 1;
9021         }
9022         if (operand.vpid >> 16)
9023                 return nested_vmx_failValid(vcpu,
9024                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9025
9026         vpid02 = nested_get_vpid02(vcpu);
9027         switch (type) {
9028         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
9029                 if (!operand.vpid ||
9030                     is_noncanonical_address(operand.gla, vcpu))
9031                         return nested_vmx_failValid(vcpu,
9032                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9033                 if (cpu_has_vmx_invvpid_individual_addr()) {
9034                         __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR,
9035                                 vpid02, operand.gla);
9036                 } else
9037                         __vmx_flush_tlb(vcpu, vpid02, false);
9038                 break;
9039         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
9040         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
9041                 if (!operand.vpid)
9042                         return nested_vmx_failValid(vcpu,
9043                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
9044                 __vmx_flush_tlb(vcpu, vpid02, false);
9045                 break;
9046         case VMX_VPID_EXTENT_ALL_CONTEXT:
9047                 __vmx_flush_tlb(vcpu, vpid02, false);
9048                 break;
9049         default:
9050                 WARN_ON_ONCE(1);
9051                 return kvm_skip_emulated_instruction(vcpu);
9052         }
9053
9054         return nested_vmx_succeed(vcpu);
9055 }
9056
9057 static int handle_invpcid(struct kvm_vcpu *vcpu)
9058 {
9059         u32 vmx_instruction_info;
9060         unsigned long type;
9061         bool pcid_enabled;
9062         gva_t gva;
9063         struct x86_exception e;
9064         unsigned i;
9065         unsigned long roots_to_free = 0;
9066         struct {
9067                 u64 pcid;
9068                 u64 gla;
9069         } operand;
9070
9071         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
9072                 kvm_queue_exception(vcpu, UD_VECTOR);
9073                 return 1;
9074         }
9075
9076         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9077         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
9078
9079         if (type > 3) {
9080                 kvm_inject_gp(vcpu, 0);
9081                 return 1;
9082         }
9083
9084         /* According to the Intel instruction reference, the memory operand
9085          * is read even if it isn't needed (e.g., for type==all)
9086          */
9087         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
9088                                 vmx_instruction_info, false, &gva))
9089                 return 1;
9090
9091         if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
9092                 kvm_inject_page_fault(vcpu, &e);
9093                 return 1;
9094         }
9095
9096         if (operand.pcid >> 12 != 0) {
9097                 kvm_inject_gp(vcpu, 0);
9098                 return 1;
9099         }
9100
9101         pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
9102
9103         switch (type) {
9104         case INVPCID_TYPE_INDIV_ADDR:
9105                 if ((!pcid_enabled && (operand.pcid != 0)) ||
9106                     is_noncanonical_address(operand.gla, vcpu)) {
9107                         kvm_inject_gp(vcpu, 0);
9108                         return 1;
9109                 }
9110                 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
9111                 return kvm_skip_emulated_instruction(vcpu);
9112
9113         case INVPCID_TYPE_SINGLE_CTXT:
9114                 if (!pcid_enabled && (operand.pcid != 0)) {
9115                         kvm_inject_gp(vcpu, 0);
9116                         return 1;
9117                 }
9118
9119                 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
9120                         kvm_mmu_sync_roots(vcpu);
9121                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
9122                 }
9123
9124                 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
9125                         if (kvm_get_pcid(vcpu, vcpu->arch.mmu.prev_roots[i].cr3)
9126                             == operand.pcid)
9127                                 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
9128
9129                 kvm_mmu_free_roots(vcpu, roots_to_free);
9130                 /*
9131                  * If neither the current cr3 nor any of the prev_roots use the
9132                  * given PCID, then nothing needs to be done here because a
9133                  * resync will happen anyway before switching to any other CR3.
9134                  */
9135
9136                 return kvm_skip_emulated_instruction(vcpu);
9137
9138         case INVPCID_TYPE_ALL_NON_GLOBAL:
9139                 /*
9140                  * Currently, KVM doesn't mark global entries in the shadow
9141                  * page tables, so a non-global flush just degenerates to a
9142                  * global flush. If needed, we could optimize this later by
9143                  * keeping track of global entries in shadow page tables.
9144                  */
9145
9146                 /* fall-through */
9147         case INVPCID_TYPE_ALL_INCL_GLOBAL:
9148                 kvm_mmu_unload(vcpu);
9149                 return kvm_skip_emulated_instruction(vcpu);
9150
9151         default:
9152                 BUG(); /* We have already checked above that type <= 3 */
9153         }
9154 }
9155
9156 static int handle_pml_full(struct kvm_vcpu *vcpu)
9157 {
9158         unsigned long exit_qualification;
9159
9160         trace_kvm_pml_full(vcpu->vcpu_id);
9161
9162         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
9163
9164         /*
9165          * PML buffer FULL happened while executing iret from NMI,
9166          * "blocked by NMI" bit has to be set before next VM entry.
9167          */
9168         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
9169                         enable_vnmi &&
9170                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
9171                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9172                                 GUEST_INTR_STATE_NMI);
9173
9174         /*
9175          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
9176          * here.., and there's no userspace involvement needed for PML.
9177          */
9178         return 1;
9179 }
9180
9181 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
9182 {
9183         if (!to_vmx(vcpu)->req_immediate_exit)
9184                 kvm_lapic_expired_hv_timer(vcpu);
9185         return 1;
9186 }
9187
9188 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
9189 {
9190         struct vcpu_vmx *vmx = to_vmx(vcpu);
9191         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9192
9193         /* Check for memory type validity */
9194         switch (address & VMX_EPTP_MT_MASK) {
9195         case VMX_EPTP_MT_UC:
9196                 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT))
9197                         return false;
9198                 break;
9199         case VMX_EPTP_MT_WB:
9200                 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT))
9201                         return false;
9202                 break;
9203         default:
9204                 return false;
9205         }
9206
9207         /* only 4 levels page-walk length are valid */
9208         if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
9209                 return false;
9210
9211         /* Reserved bits should not be set */
9212         if (address >> maxphyaddr || ((address >> 7) & 0x1f))
9213                 return false;
9214
9215         /* AD, if set, should be supported */
9216         if (address & VMX_EPTP_AD_ENABLE_BIT) {
9217                 if (!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT))
9218                         return false;
9219         }
9220
9221         return true;
9222 }
9223
9224 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
9225                                      struct vmcs12 *vmcs12)
9226 {
9227         u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
9228         u64 address;
9229         bool accessed_dirty;
9230         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
9231
9232         if (!nested_cpu_has_eptp_switching(vmcs12) ||
9233             !nested_cpu_has_ept(vmcs12))
9234                 return 1;
9235
9236         if (index >= VMFUNC_EPTP_ENTRIES)
9237                 return 1;
9238
9239
9240         if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
9241                                      &address, index * 8, 8))
9242                 return 1;
9243
9244         accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
9245
9246         /*
9247          * If the (L2) guest does a vmfunc to the currently
9248          * active ept pointer, we don't have to do anything else
9249          */
9250         if (vmcs12->ept_pointer != address) {
9251                 if (!valid_ept_address(vcpu, address))
9252                         return 1;
9253
9254                 kvm_mmu_unload(vcpu);
9255                 mmu->ept_ad = accessed_dirty;
9256                 mmu->base_role.ad_disabled = !accessed_dirty;
9257                 vmcs12->ept_pointer = address;
9258                 /*
9259                  * TODO: Check what's the correct approach in case
9260                  * mmu reload fails. Currently, we just let the next
9261                  * reload potentially fail
9262                  */
9263                 kvm_mmu_reload(vcpu);
9264         }
9265
9266         return 0;
9267 }
9268
9269 static int handle_vmfunc(struct kvm_vcpu *vcpu)
9270 {
9271         struct vcpu_vmx *vmx = to_vmx(vcpu);
9272         struct vmcs12 *vmcs12;
9273         u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
9274
9275         /*
9276          * VMFUNC is only supported for nested guests, but we always enable the
9277          * secondary control for simplicity; for non-nested mode, fake that we
9278          * didn't by injecting #UD.
9279          */
9280         if (!is_guest_mode(vcpu)) {
9281                 kvm_queue_exception(vcpu, UD_VECTOR);
9282                 return 1;
9283         }
9284
9285         vmcs12 = get_vmcs12(vcpu);
9286         if ((vmcs12->vm_function_control & (1 << function)) == 0)
9287                 goto fail;
9288
9289         switch (function) {
9290         case 0:
9291                 if (nested_vmx_eptp_switching(vcpu, vmcs12))
9292                         goto fail;
9293                 break;
9294         default:
9295                 goto fail;
9296         }
9297         return kvm_skip_emulated_instruction(vcpu);
9298
9299 fail:
9300         nested_vmx_vmexit(vcpu, vmx->exit_reason,
9301                           vmcs_read32(VM_EXIT_INTR_INFO),
9302                           vmcs_readl(EXIT_QUALIFICATION));
9303         return 1;
9304 }
9305
9306 static int handle_encls(struct kvm_vcpu *vcpu)
9307 {
9308         /*
9309          * SGX virtualization is not yet supported.  There is no software
9310          * enable bit for SGX, so we have to trap ENCLS and inject a #UD
9311          * to prevent the guest from executing ENCLS.
9312          */
9313         kvm_queue_exception(vcpu, UD_VECTOR);
9314         return 1;
9315 }
9316
9317 /*
9318  * The exit handlers return 1 if the exit was handled fully and guest execution
9319  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
9320  * to be done to userspace and return 0.
9321  */
9322 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
9323         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
9324         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
9325         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
9326         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
9327         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
9328         [EXIT_REASON_CR_ACCESS]               = handle_cr,
9329         [EXIT_REASON_DR_ACCESS]               = handle_dr,
9330         [EXIT_REASON_CPUID]                   = handle_cpuid,
9331         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
9332         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
9333         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
9334         [EXIT_REASON_HLT]                     = handle_halt,
9335         [EXIT_REASON_INVD]                    = handle_invd,
9336         [EXIT_REASON_INVLPG]                  = handle_invlpg,
9337         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
9338         [EXIT_REASON_VMCALL]                  = handle_vmcall,
9339         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
9340         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
9341         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
9342         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
9343         [EXIT_REASON_VMREAD]                  = handle_vmread,
9344         [EXIT_REASON_VMRESUME]                = handle_vmresume,
9345         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
9346         [EXIT_REASON_VMOFF]                   = handle_vmoff,
9347         [EXIT_REASON_VMON]                    = handle_vmon,
9348         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
9349         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
9350         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
9351         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
9352         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
9353         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
9354         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
9355         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
9356         [EXIT_REASON_GDTR_IDTR]               = handle_desc,
9357         [EXIT_REASON_LDTR_TR]                 = handle_desc,
9358         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
9359         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
9360         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
9361         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
9362         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
9363         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
9364         [EXIT_REASON_INVEPT]                  = handle_invept,
9365         [EXIT_REASON_INVVPID]                 = handle_invvpid,
9366         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
9367         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
9368         [EXIT_REASON_XSAVES]                  = handle_xsaves,
9369         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
9370         [EXIT_REASON_PML_FULL]                = handle_pml_full,
9371         [EXIT_REASON_INVPCID]                 = handle_invpcid,
9372         [EXIT_REASON_VMFUNC]                  = handle_vmfunc,
9373         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
9374         [EXIT_REASON_ENCLS]                   = handle_encls,
9375 };
9376
9377 static const int kvm_vmx_max_exit_handlers =
9378         ARRAY_SIZE(kvm_vmx_exit_handlers);
9379
9380 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
9381                                        struct vmcs12 *vmcs12)
9382 {
9383         unsigned long exit_qualification;
9384         gpa_t bitmap, last_bitmap;
9385         unsigned int port;
9386         int size;
9387         u8 b;
9388
9389         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9390                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
9391
9392         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
9393
9394         port = exit_qualification >> 16;
9395         size = (exit_qualification & 7) + 1;
9396
9397         last_bitmap = (gpa_t)-1;
9398         b = -1;
9399
9400         while (size > 0) {
9401                 if (port < 0x8000)
9402                         bitmap = vmcs12->io_bitmap_a;
9403                 else if (port < 0x10000)
9404                         bitmap = vmcs12->io_bitmap_b;
9405                 else
9406                         return true;
9407                 bitmap += (port & 0x7fff) / 8;
9408
9409                 if (last_bitmap != bitmap)
9410                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
9411                                 return true;
9412                 if (b & (1 << (port & 7)))
9413                         return true;
9414
9415                 port++;
9416                 size--;
9417                 last_bitmap = bitmap;
9418         }
9419
9420         return false;
9421 }
9422
9423 /*
9424  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
9425  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
9426  * disinterest in the current event (read or write a specific MSR) by using an
9427  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
9428  */
9429 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
9430         struct vmcs12 *vmcs12, u32 exit_reason)
9431 {
9432         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
9433         gpa_t bitmap;
9434
9435         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9436                 return true;
9437
9438         /*
9439          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
9440          * for the four combinations of read/write and low/high MSR numbers.
9441          * First we need to figure out which of the four to use:
9442          */
9443         bitmap = vmcs12->msr_bitmap;
9444         if (exit_reason == EXIT_REASON_MSR_WRITE)
9445                 bitmap += 2048;
9446         if (msr_index >= 0xc0000000) {
9447                 msr_index -= 0xc0000000;
9448                 bitmap += 1024;
9449         }
9450
9451         /* Then read the msr_index'th bit from this bitmap: */
9452         if (msr_index < 1024*8) {
9453                 unsigned char b;
9454                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
9455                         return true;
9456                 return 1 & (b >> (msr_index & 7));
9457         } else
9458                 return true; /* let L1 handle the wrong parameter */
9459 }
9460
9461 /*
9462  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
9463  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
9464  * intercept (via guest_host_mask etc.) the current event.
9465  */
9466 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
9467         struct vmcs12 *vmcs12)
9468 {
9469         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
9470         int cr = exit_qualification & 15;
9471         int reg;
9472         unsigned long val;
9473
9474         switch ((exit_qualification >> 4) & 3) {
9475         case 0: /* mov to cr */
9476                 reg = (exit_qualification >> 8) & 15;
9477                 val = kvm_register_readl(vcpu, reg);
9478                 switch (cr) {
9479                 case 0:
9480                         if (vmcs12->cr0_guest_host_mask &
9481                             (val ^ vmcs12->cr0_read_shadow))
9482                                 return true;
9483                         break;
9484                 case 3:
9485                         if ((vmcs12->cr3_target_count >= 1 &&
9486                                         vmcs12->cr3_target_value0 == val) ||
9487                                 (vmcs12->cr3_target_count >= 2 &&
9488                                         vmcs12->cr3_target_value1 == val) ||
9489                                 (vmcs12->cr3_target_count >= 3 &&
9490                                         vmcs12->cr3_target_value2 == val) ||
9491                                 (vmcs12->cr3_target_count >= 4 &&
9492                                         vmcs12->cr3_target_value3 == val))
9493                                 return false;
9494                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
9495                                 return true;
9496                         break;
9497                 case 4:
9498                         if (vmcs12->cr4_guest_host_mask &
9499                             (vmcs12->cr4_read_shadow ^ val))
9500                                 return true;
9501                         break;
9502                 case 8:
9503                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
9504                                 return true;
9505                         break;
9506                 }
9507                 break;
9508         case 2: /* clts */
9509                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
9510                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
9511                         return true;
9512                 break;
9513         case 1: /* mov from cr */
9514                 switch (cr) {
9515                 case 3:
9516                         if (vmcs12->cpu_based_vm_exec_control &
9517                             CPU_BASED_CR3_STORE_EXITING)
9518                                 return true;
9519                         break;
9520                 case 8:
9521                         if (vmcs12->cpu_based_vm_exec_control &
9522                             CPU_BASED_CR8_STORE_EXITING)
9523                                 return true;
9524                         break;
9525                 }
9526                 break;
9527         case 3: /* lmsw */
9528                 /*
9529                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
9530                  * cr0. Other attempted changes are ignored, with no exit.
9531                  */
9532                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
9533                 if (vmcs12->cr0_guest_host_mask & 0xe &
9534                     (val ^ vmcs12->cr0_read_shadow))
9535                         return true;
9536                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
9537                     !(vmcs12->cr0_read_shadow & 0x1) &&
9538                     (val & 0x1))
9539                         return true;
9540                 break;
9541         }
9542         return false;
9543 }
9544
9545 static bool nested_vmx_exit_handled_vmcs_access(struct kvm_vcpu *vcpu,
9546         struct vmcs12 *vmcs12, gpa_t bitmap)
9547 {
9548         u32 vmx_instruction_info;
9549         unsigned long field;
9550         u8 b;
9551
9552         if (!nested_cpu_has_shadow_vmcs(vmcs12))
9553                 return true;
9554
9555         /* Decode instruction info and find the field to access */
9556         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9557         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
9558
9559         /* Out-of-range fields always cause a VM exit from L2 to L1 */
9560         if (field >> 15)
9561                 return true;
9562
9563         if (kvm_vcpu_read_guest(vcpu, bitmap + field/8, &b, 1))
9564                 return true;
9565
9566         return 1 & (b >> (field & 7));
9567 }
9568
9569 /*
9570  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
9571  * should handle it ourselves in L0 (and then continue L2). Only call this
9572  * when in is_guest_mode (L2).
9573  */
9574 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
9575 {
9576         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9577         struct vcpu_vmx *vmx = to_vmx(vcpu);
9578         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9579
9580         if (vmx->nested.nested_run_pending)
9581                 return false;
9582
9583         if (unlikely(vmx->fail)) {
9584                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
9585                                     vmcs_read32(VM_INSTRUCTION_ERROR));
9586                 return true;
9587         }
9588
9589         /*
9590          * The host physical addresses of some pages of guest memory
9591          * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
9592          * Page). The CPU may write to these pages via their host
9593          * physical address while L2 is running, bypassing any
9594          * address-translation-based dirty tracking (e.g. EPT write
9595          * protection).
9596          *
9597          * Mark them dirty on every exit from L2 to prevent them from
9598          * getting out of sync with dirty tracking.
9599          */
9600         nested_mark_vmcs12_pages_dirty(vcpu);
9601
9602         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
9603                                 vmcs_readl(EXIT_QUALIFICATION),
9604                                 vmx->idt_vectoring_info,
9605                                 intr_info,
9606                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9607                                 KVM_ISA_VMX);
9608
9609         switch (exit_reason) {
9610         case EXIT_REASON_EXCEPTION_NMI:
9611                 if (is_nmi(intr_info))
9612                         return false;
9613                 else if (is_page_fault(intr_info))
9614                         return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
9615                 else if (is_debug(intr_info) &&
9616                          vcpu->guest_debug &
9617                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
9618                         return false;
9619                 else if (is_breakpoint(intr_info) &&
9620                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
9621                         return false;
9622                 return vmcs12->exception_bitmap &
9623                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
9624         case EXIT_REASON_EXTERNAL_INTERRUPT:
9625                 return false;
9626         case EXIT_REASON_TRIPLE_FAULT:
9627                 return true;
9628         case EXIT_REASON_PENDING_INTERRUPT:
9629                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
9630         case EXIT_REASON_NMI_WINDOW:
9631                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
9632         case EXIT_REASON_TASK_SWITCH:
9633                 return true;
9634         case EXIT_REASON_CPUID:
9635                 return true;
9636         case EXIT_REASON_HLT:
9637                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
9638         case EXIT_REASON_INVD:
9639                 return true;
9640         case EXIT_REASON_INVLPG:
9641                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9642         case EXIT_REASON_RDPMC:
9643                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
9644         case EXIT_REASON_RDRAND:
9645                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
9646         case EXIT_REASON_RDSEED:
9647                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
9648         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
9649                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
9650         case EXIT_REASON_VMREAD:
9651                 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
9652                         vmcs12->vmread_bitmap);
9653         case EXIT_REASON_VMWRITE:
9654                 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12,
9655                         vmcs12->vmwrite_bitmap);
9656         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
9657         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
9658         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMRESUME:
9659         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
9660         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
9661                 /*
9662                  * VMX instructions trap unconditionally. This allows L1 to
9663                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
9664                  */
9665                 return true;
9666         case EXIT_REASON_CR_ACCESS:
9667                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
9668         case EXIT_REASON_DR_ACCESS:
9669                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
9670         case EXIT_REASON_IO_INSTRUCTION:
9671                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
9672         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
9673                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
9674         case EXIT_REASON_MSR_READ:
9675         case EXIT_REASON_MSR_WRITE:
9676                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
9677         case EXIT_REASON_INVALID_STATE:
9678                 return true;
9679         case EXIT_REASON_MWAIT_INSTRUCTION:
9680                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
9681         case EXIT_REASON_MONITOR_TRAP_FLAG:
9682                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
9683         case EXIT_REASON_MONITOR_INSTRUCTION:
9684                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
9685         case EXIT_REASON_PAUSE_INSTRUCTION:
9686                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
9687                         nested_cpu_has2(vmcs12,
9688                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
9689         case EXIT_REASON_MCE_DURING_VMENTRY:
9690                 return false;
9691         case EXIT_REASON_TPR_BELOW_THRESHOLD:
9692                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
9693         case EXIT_REASON_APIC_ACCESS:
9694         case EXIT_REASON_APIC_WRITE:
9695         case EXIT_REASON_EOI_INDUCED:
9696                 /*
9697                  * The controls for "virtualize APIC accesses," "APIC-
9698                  * register virtualization," and "virtual-interrupt
9699                  * delivery" only come from vmcs12.
9700                  */
9701                 return true;
9702         case EXIT_REASON_EPT_VIOLATION:
9703                 /*
9704                  * L0 always deals with the EPT violation. If nested EPT is
9705                  * used, and the nested mmu code discovers that the address is
9706                  * missing in the guest EPT table (EPT12), the EPT violation
9707                  * will be injected with nested_ept_inject_page_fault()
9708                  */
9709                 return false;
9710         case EXIT_REASON_EPT_MISCONFIG:
9711                 /*
9712                  * L2 never uses directly L1's EPT, but rather L0's own EPT
9713                  * table (shadow on EPT) or a merged EPT table that L0 built
9714                  * (EPT on EPT). So any problems with the structure of the
9715                  * table is L0's fault.
9716                  */
9717                 return false;
9718         case EXIT_REASON_INVPCID:
9719                 return
9720                         nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
9721                         nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9722         case EXIT_REASON_WBINVD:
9723                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
9724         case EXIT_REASON_XSETBV:
9725                 return true;
9726         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
9727                 /*
9728                  * This should never happen, since it is not possible to
9729                  * set XSS to a non-zero value---neither in L1 nor in L2.
9730                  * If if it were, XSS would have to be checked against
9731                  * the XSS exit bitmap in vmcs12.
9732                  */
9733                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
9734         case EXIT_REASON_PREEMPTION_TIMER:
9735                 return false;
9736         case EXIT_REASON_PML_FULL:
9737                 /* We emulate PML support to L1. */
9738                 return false;
9739         case EXIT_REASON_VMFUNC:
9740                 /* VM functions are emulated through L2->L0 vmexits. */
9741                 return false;
9742         case EXIT_REASON_ENCLS:
9743                 /* SGX is never exposed to L1 */
9744                 return false;
9745         default:
9746                 return true;
9747         }
9748 }
9749
9750 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
9751 {
9752         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9753
9754         /*
9755          * At this point, the exit interruption info in exit_intr_info
9756          * is only valid for EXCEPTION_NMI exits.  For EXTERNAL_INTERRUPT
9757          * we need to query the in-kernel LAPIC.
9758          */
9759         WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
9760         if ((exit_intr_info &
9761              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9762             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
9763                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9764                 vmcs12->vm_exit_intr_error_code =
9765                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9766         }
9767
9768         nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
9769                           vmcs_readl(EXIT_QUALIFICATION));
9770         return 1;
9771 }
9772
9773 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
9774 {
9775         *info1 = vmcs_readl(EXIT_QUALIFICATION);
9776         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
9777 }
9778
9779 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
9780 {
9781         if (vmx->pml_pg) {
9782                 __free_page(vmx->pml_pg);
9783                 vmx->pml_pg = NULL;
9784         }
9785 }
9786
9787 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
9788 {
9789         struct vcpu_vmx *vmx = to_vmx(vcpu);
9790         u64 *pml_buf;
9791         u16 pml_idx;
9792
9793         pml_idx = vmcs_read16(GUEST_PML_INDEX);
9794
9795         /* Do nothing if PML buffer is empty */
9796         if (pml_idx == (PML_ENTITY_NUM - 1))
9797                 return;
9798
9799         /* PML index always points to next available PML buffer entity */
9800         if (pml_idx >= PML_ENTITY_NUM)
9801                 pml_idx = 0;
9802         else
9803                 pml_idx++;
9804
9805         pml_buf = page_address(vmx->pml_pg);
9806         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
9807                 u64 gpa;
9808
9809                 gpa = pml_buf[pml_idx];
9810                 WARN_ON(gpa & (PAGE_SIZE - 1));
9811                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
9812         }
9813
9814         /* reset PML index */
9815         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
9816 }
9817
9818 /*
9819  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
9820  * Called before reporting dirty_bitmap to userspace.
9821  */
9822 static void kvm_flush_pml_buffers(struct kvm *kvm)
9823 {
9824         int i;
9825         struct kvm_vcpu *vcpu;
9826         /*
9827          * We only need to kick vcpu out of guest mode here, as PML buffer
9828          * is flushed at beginning of all VMEXITs, and it's obvious that only
9829          * vcpus running in guest are possible to have unflushed GPAs in PML
9830          * buffer.
9831          */
9832         kvm_for_each_vcpu(i, vcpu, kvm)
9833                 kvm_vcpu_kick(vcpu);
9834 }
9835
9836 static void vmx_dump_sel(char *name, uint32_t sel)
9837 {
9838         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
9839                name, vmcs_read16(sel),
9840                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
9841                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
9842                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
9843 }
9844
9845 static void vmx_dump_dtsel(char *name, uint32_t limit)
9846 {
9847         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
9848                name, vmcs_read32(limit),
9849                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
9850 }
9851
9852 static void dump_vmcs(void)
9853 {
9854         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
9855         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
9856         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
9857         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
9858         u32 secondary_exec_control = 0;
9859         unsigned long cr4 = vmcs_readl(GUEST_CR4);
9860         u64 efer = vmcs_read64(GUEST_IA32_EFER);
9861         int i, n;
9862
9863         if (cpu_has_secondary_exec_ctrls())
9864                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9865
9866         pr_err("*** Guest State ***\n");
9867         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9868                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
9869                vmcs_readl(CR0_GUEST_HOST_MASK));
9870         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9871                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
9872         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
9873         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
9874             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
9875         {
9876                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
9877                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
9878                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
9879                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
9880         }
9881         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
9882                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
9883         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
9884                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
9885         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9886                vmcs_readl(GUEST_SYSENTER_ESP),
9887                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
9888         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
9889         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
9890         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
9891         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
9892         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
9893         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
9894         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
9895         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
9896         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
9897         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
9898         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
9899             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
9900                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
9901                        efer, vmcs_read64(GUEST_IA32_PAT));
9902         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
9903                vmcs_read64(GUEST_IA32_DEBUGCTL),
9904                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
9905         if (cpu_has_load_perf_global_ctrl &&
9906             vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
9907                 pr_err("PerfGlobCtl = 0x%016llx\n",
9908                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
9909         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
9910                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
9911         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
9912                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
9913                vmcs_read32(GUEST_ACTIVITY_STATE));
9914         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
9915                 pr_err("InterruptStatus = %04x\n",
9916                        vmcs_read16(GUEST_INTR_STATUS));
9917
9918         pr_err("*** Host State ***\n");
9919         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
9920                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
9921         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
9922                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
9923                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
9924                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
9925                vmcs_read16(HOST_TR_SELECTOR));
9926         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
9927                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
9928                vmcs_readl(HOST_TR_BASE));
9929         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
9930                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
9931         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
9932                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
9933                vmcs_readl(HOST_CR4));
9934         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9935                vmcs_readl(HOST_IA32_SYSENTER_ESP),
9936                vmcs_read32(HOST_IA32_SYSENTER_CS),
9937                vmcs_readl(HOST_IA32_SYSENTER_EIP));
9938         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
9939                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
9940                        vmcs_read64(HOST_IA32_EFER),
9941                        vmcs_read64(HOST_IA32_PAT));
9942         if (cpu_has_load_perf_global_ctrl &&
9943             vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9944                 pr_err("PerfGlobCtl = 0x%016llx\n",
9945                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
9946
9947         pr_err("*** Control State ***\n");
9948         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
9949                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
9950         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
9951         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
9952                vmcs_read32(EXCEPTION_BITMAP),
9953                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
9954                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
9955         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
9956                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9957                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
9958                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
9959         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
9960                vmcs_read32(VM_EXIT_INTR_INFO),
9961                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9962                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
9963         pr_err("        reason=%08x qualification=%016lx\n",
9964                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
9965         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
9966                vmcs_read32(IDT_VECTORING_INFO_FIELD),
9967                vmcs_read32(IDT_VECTORING_ERROR_CODE));
9968         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
9969         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
9970                 pr_err("TSC Multiplier = 0x%016llx\n",
9971                        vmcs_read64(TSC_MULTIPLIER));
9972         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
9973                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
9974         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
9975                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
9976         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
9977                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
9978         n = vmcs_read32(CR3_TARGET_COUNT);
9979         for (i = 0; i + 1 < n; i += 4)
9980                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
9981                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
9982                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
9983         if (i < n)
9984                 pr_err("CR3 target%u=%016lx\n",
9985                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
9986         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
9987                 pr_err("PLE Gap=%08x Window=%08x\n",
9988                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
9989         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
9990                 pr_err("Virtual processor ID = 0x%04x\n",
9991                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
9992 }
9993
9994 /*
9995  * The guest has exited.  See if we can fix it or if we need userspace
9996  * assistance.
9997  */
9998 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
9999 {
10000         struct vcpu_vmx *vmx = to_vmx(vcpu);
10001         u32 exit_reason = vmx->exit_reason;
10002         u32 vectoring_info = vmx->idt_vectoring_info;
10003
10004         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
10005
10006         /*
10007          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
10008          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
10009          * querying dirty_bitmap, we only need to kick all vcpus out of guest
10010          * mode as if vcpus is in root mode, the PML buffer must has been
10011          * flushed already.
10012          */
10013         if (enable_pml)
10014                 vmx_flush_pml_buffer(vcpu);
10015
10016         /* If guest state is invalid, start emulating */
10017         if (vmx->emulation_required)
10018                 return handle_invalid_guest_state(vcpu);
10019
10020         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
10021                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
10022
10023         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
10024                 dump_vmcs();
10025                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
10026                 vcpu->run->fail_entry.hardware_entry_failure_reason
10027                         = exit_reason;
10028                 return 0;
10029         }
10030
10031         if (unlikely(vmx->fail)) {
10032                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
10033                 vcpu->run->fail_entry.hardware_entry_failure_reason
10034                         = vmcs_read32(VM_INSTRUCTION_ERROR);
10035                 return 0;
10036         }
10037
10038         /*
10039          * Note:
10040          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
10041          * delivery event since it indicates guest is accessing MMIO.
10042          * The vm-exit can be triggered again after return to guest that
10043          * will cause infinite loop.
10044          */
10045         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
10046                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
10047                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
10048                         exit_reason != EXIT_REASON_PML_FULL &&
10049                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
10050                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
10051                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
10052                 vcpu->run->internal.ndata = 3;
10053                 vcpu->run->internal.data[0] = vectoring_info;
10054                 vcpu->run->internal.data[1] = exit_reason;
10055                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
10056                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
10057                         vcpu->run->internal.ndata++;
10058                         vcpu->run->internal.data[3] =
10059                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
10060                 }
10061                 return 0;
10062         }
10063
10064         if (unlikely(!enable_vnmi &&
10065                      vmx->loaded_vmcs->soft_vnmi_blocked)) {
10066                 if (vmx_interrupt_allowed(vcpu)) {
10067                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
10068                 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
10069                            vcpu->arch.nmi_pending) {
10070                         /*
10071                          * This CPU don't support us in finding the end of an
10072                          * NMI-blocked window if the guest runs with IRQs
10073                          * disabled. So we pull the trigger after 1 s of
10074                          * futile waiting, but inform the user about this.
10075                          */
10076                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
10077                                "state on VCPU %d after 1 s timeout\n",
10078                                __func__, vcpu->vcpu_id);
10079                         vmx->loaded_vmcs->soft_vnmi_blocked = 0;
10080                 }
10081         }
10082
10083         if (exit_reason < kvm_vmx_max_exit_handlers
10084             && kvm_vmx_exit_handlers[exit_reason])
10085                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
10086         else {
10087                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
10088                                 exit_reason);
10089                 kvm_queue_exception(vcpu, UD_VECTOR);
10090                 return 1;
10091         }
10092 }
10093
10094 /*
10095  * Software based L1D cache flush which is used when microcode providing
10096  * the cache control MSR is not loaded.
10097  *
10098  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
10099  * flush it is required to read in 64 KiB because the replacement algorithm
10100  * is not exactly LRU. This could be sized at runtime via topology
10101  * information but as all relevant affected CPUs have 32KiB L1D cache size
10102  * there is no point in doing so.
10103  */
10104 static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
10105 {
10106         int size = PAGE_SIZE << L1D_CACHE_ORDER;
10107
10108         /*
10109          * This code is only executed when the the flush mode is 'cond' or
10110          * 'always'
10111          */
10112         if (static_branch_likely(&vmx_l1d_flush_cond)) {
10113                 bool flush_l1d;
10114
10115                 /*
10116                  * Clear the per-vcpu flush bit, it gets set again
10117                  * either from vcpu_run() or from one of the unsafe
10118                  * VMEXIT handlers.
10119                  */
10120                 flush_l1d = vcpu->arch.l1tf_flush_l1d;
10121                 vcpu->arch.l1tf_flush_l1d = false;
10122
10123                 /*
10124                  * Clear the per-cpu flush bit, it gets set again from
10125                  * the interrupt handlers.
10126                  */
10127                 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
10128                 kvm_clear_cpu_l1tf_flush_l1d();
10129
10130                 if (!flush_l1d)
10131                         return;
10132         }
10133
10134         vcpu->stat.l1d_flush++;
10135
10136         if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
10137                 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
10138                 return;
10139         }
10140
10141         asm volatile(
10142                 /* First ensure the pages are in the TLB */
10143                 "xorl   %%eax, %%eax\n"
10144                 ".Lpopulate_tlb:\n\t"
10145                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
10146                 "addl   $4096, %%eax\n\t"
10147                 "cmpl   %%eax, %[size]\n\t"
10148                 "jne    .Lpopulate_tlb\n\t"
10149                 "xorl   %%eax, %%eax\n\t"
10150                 "cpuid\n\t"
10151                 /* Now fill the cache */
10152                 "xorl   %%eax, %%eax\n"
10153                 ".Lfill_cache:\n"
10154                 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
10155                 "addl   $64, %%eax\n\t"
10156                 "cmpl   %%eax, %[size]\n\t"
10157                 "jne    .Lfill_cache\n\t"
10158                 "lfence\n"
10159                 :: [flush_pages] "r" (vmx_l1d_flush_pages),
10160                     [size] "r" (size)
10161                 : "eax", "ebx", "ecx", "edx");
10162 }
10163
10164 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
10165 {
10166         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10167
10168         if (is_guest_mode(vcpu) &&
10169                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10170                 return;
10171
10172         if (irr == -1 || tpr < irr) {
10173                 vmcs_write32(TPR_THRESHOLD, 0);
10174                 return;
10175         }
10176
10177         vmcs_write32(TPR_THRESHOLD, irr);
10178 }
10179
10180 static void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
10181 {
10182         u32 sec_exec_control;
10183
10184         if (!lapic_in_kernel(vcpu))
10185                 return;
10186
10187         if (!flexpriority_enabled &&
10188             !cpu_has_vmx_virtualize_x2apic_mode())
10189                 return;
10190
10191         /* Postpone execution until vmcs01 is the current VMCS. */
10192         if (is_guest_mode(vcpu)) {
10193                 to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
10194                 return;
10195         }
10196
10197         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
10198         sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10199                               SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
10200
10201         switch (kvm_get_apic_mode(vcpu)) {
10202         case LAPIC_MODE_INVALID:
10203                 WARN_ONCE(true, "Invalid local APIC state");
10204         case LAPIC_MODE_DISABLED:
10205                 break;
10206         case LAPIC_MODE_XAPIC:
10207                 if (flexpriority_enabled) {
10208                         sec_exec_control |=
10209                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
10210                         vmx_flush_tlb(vcpu, true);
10211                 }
10212                 break;
10213         case LAPIC_MODE_X2APIC:
10214                 if (cpu_has_vmx_virtualize_x2apic_mode())
10215                         sec_exec_control |=
10216                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
10217                 break;
10218         }
10219         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
10220
10221         vmx_update_msr_bitmap(vcpu);
10222 }
10223
10224 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
10225 {
10226         if (!is_guest_mode(vcpu)) {
10227                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
10228                 vmx_flush_tlb(vcpu, true);
10229         }
10230 }
10231
10232 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
10233 {
10234         u16 status;
10235         u8 old;
10236
10237         if (max_isr == -1)
10238                 max_isr = 0;
10239
10240         status = vmcs_read16(GUEST_INTR_STATUS);
10241         old = status >> 8;
10242         if (max_isr != old) {
10243                 status &= 0xff;
10244                 status |= max_isr << 8;
10245                 vmcs_write16(GUEST_INTR_STATUS, status);
10246         }
10247 }
10248
10249 static void vmx_set_rvi(int vector)
10250 {
10251         u16 status;
10252         u8 old;
10253
10254         if (vector == -1)
10255                 vector = 0;
10256
10257         status = vmcs_read16(GUEST_INTR_STATUS);
10258         old = (u8)status & 0xff;
10259         if ((u8)vector != old) {
10260                 status &= ~0xff;
10261                 status |= (u8)vector;
10262                 vmcs_write16(GUEST_INTR_STATUS, status);
10263         }
10264 }
10265
10266 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
10267 {
10268         /*
10269          * When running L2, updating RVI is only relevant when
10270          * vmcs12 virtual-interrupt-delivery enabled.
10271          * However, it can be enabled only when L1 also
10272          * intercepts external-interrupts and in that case
10273          * we should not update vmcs02 RVI but instead intercept
10274          * interrupt. Therefore, do nothing when running L2.
10275          */
10276         if (!is_guest_mode(vcpu))
10277                 vmx_set_rvi(max_irr);
10278 }
10279
10280 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
10281 {
10282         struct vcpu_vmx *vmx = to_vmx(vcpu);
10283         int max_irr;
10284         bool max_irr_updated;
10285
10286         WARN_ON(!vcpu->arch.apicv_active);
10287         if (pi_test_on(&vmx->pi_desc)) {
10288                 pi_clear_on(&vmx->pi_desc);
10289                 /*
10290                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
10291                  * But on x86 this is just a compiler barrier anyway.
10292                  */
10293                 smp_mb__after_atomic();
10294                 max_irr_updated =
10295                         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
10296
10297                 /*
10298                  * If we are running L2 and L1 has a new pending interrupt
10299                  * which can be injected, we should re-evaluate
10300                  * what should be done with this new L1 interrupt.
10301                  * If L1 intercepts external-interrupts, we should
10302                  * exit from L2 to L1. Otherwise, interrupt should be
10303                  * delivered directly to L2.
10304                  */
10305                 if (is_guest_mode(vcpu) && max_irr_updated) {
10306                         if (nested_exit_on_intr(vcpu))
10307                                 kvm_vcpu_exiting_guest_mode(vcpu);
10308                         else
10309                                 kvm_make_request(KVM_REQ_EVENT, vcpu);
10310                 }
10311         } else {
10312                 max_irr = kvm_lapic_find_highest_irr(vcpu);
10313         }
10314         vmx_hwapic_irr_update(vcpu, max_irr);
10315         return max_irr;
10316 }
10317
10318 static u8 vmx_has_apicv_interrupt(struct kvm_vcpu *vcpu)
10319 {
10320         u8 rvi = vmx_get_rvi();
10321         u8 vppr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_PROCPRI);
10322
10323         return ((rvi & 0xf0) > (vppr & 0xf0));
10324 }
10325
10326 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
10327 {
10328         if (!kvm_vcpu_apicv_active(vcpu))
10329                 return;
10330
10331         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
10332         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
10333         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
10334         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
10335 }
10336
10337 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
10338 {
10339         struct vcpu_vmx *vmx = to_vmx(vcpu);
10340
10341         pi_clear_on(&vmx->pi_desc);
10342         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
10343 }
10344
10345 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
10346 {
10347         u32 exit_intr_info = 0;
10348         u16 basic_exit_reason = (u16)vmx->exit_reason;
10349
10350         if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
10351               || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
10352                 return;
10353
10354         if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
10355                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
10356         vmx->exit_intr_info = exit_intr_info;
10357
10358         /* if exit due to PF check for async PF */
10359         if (is_page_fault(exit_intr_info))
10360                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
10361
10362         /* Handle machine checks before interrupts are enabled */
10363         if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
10364             is_machine_check(exit_intr_info))
10365                 kvm_machine_check();
10366
10367         /* We need to handle NMIs before interrupts are enabled */
10368         if (is_nmi(exit_intr_info)) {
10369                 kvm_before_interrupt(&vmx->vcpu);
10370                 asm("int $2");
10371                 kvm_after_interrupt(&vmx->vcpu);
10372         }
10373 }
10374
10375 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
10376 {
10377         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
10378
10379         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
10380                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
10381                 unsigned int vector;
10382                 unsigned long entry;
10383                 gate_desc *desc;
10384                 struct vcpu_vmx *vmx = to_vmx(vcpu);
10385 #ifdef CONFIG_X86_64
10386                 unsigned long tmp;
10387 #endif
10388
10389                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
10390                 desc = (gate_desc *)vmx->host_idt_base + vector;
10391                 entry = gate_offset(desc);
10392                 asm volatile(
10393 #ifdef CONFIG_X86_64
10394                         "mov %%" _ASM_SP ", %[sp]\n\t"
10395                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
10396                         "push $%c[ss]\n\t"
10397                         "push %[sp]\n\t"
10398 #endif
10399                         "pushf\n\t"
10400                         __ASM_SIZE(push) " $%c[cs]\n\t"
10401                         CALL_NOSPEC
10402                         :
10403 #ifdef CONFIG_X86_64
10404                         [sp]"=&r"(tmp),
10405 #endif
10406                         ASM_CALL_CONSTRAINT
10407                         :
10408                         THUNK_TARGET(entry),
10409                         [ss]"i"(__KERNEL_DS),
10410                         [cs]"i"(__KERNEL_CS)
10411                         );
10412         }
10413 }
10414 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
10415
10416 static bool vmx_has_emulated_msr(int index)
10417 {
10418         switch (index) {
10419         case MSR_IA32_SMBASE:
10420                 /*
10421                  * We cannot do SMM unless we can run the guest in big
10422                  * real mode.
10423                  */
10424                 return enable_unrestricted_guest || emulate_invalid_guest_state;
10425         case MSR_AMD64_VIRT_SPEC_CTRL:
10426                 /* This is AMD only.  */
10427                 return false;
10428         default:
10429                 return true;
10430         }
10431 }
10432
10433 static bool vmx_mpx_supported(void)
10434 {
10435         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
10436                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
10437 }
10438
10439 static bool vmx_xsaves_supported(void)
10440 {
10441         return vmcs_config.cpu_based_2nd_exec_ctrl &
10442                 SECONDARY_EXEC_XSAVES;
10443 }
10444
10445 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
10446 {
10447         u32 exit_intr_info;
10448         bool unblock_nmi;
10449         u8 vector;
10450         bool idtv_info_valid;
10451
10452         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
10453
10454         if (enable_vnmi) {
10455                 if (vmx->loaded_vmcs->nmi_known_unmasked)
10456                         return;
10457                 /*
10458                  * Can't use vmx->exit_intr_info since we're not sure what
10459                  * the exit reason is.
10460                  */
10461                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
10462                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
10463                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
10464                 /*
10465                  * SDM 3: 27.7.1.2 (September 2008)
10466                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
10467                  * a guest IRET fault.
10468                  * SDM 3: 23.2.2 (September 2008)
10469                  * Bit 12 is undefined in any of the following cases:
10470                  *  If the VM exit sets the valid bit in the IDT-vectoring
10471                  *   information field.
10472                  *  If the VM exit is due to a double fault.
10473                  */
10474                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
10475                     vector != DF_VECTOR && !idtv_info_valid)
10476                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
10477                                       GUEST_INTR_STATE_NMI);
10478                 else
10479                         vmx->loaded_vmcs->nmi_known_unmasked =
10480                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
10481                                   & GUEST_INTR_STATE_NMI);
10482         } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
10483                 vmx->loaded_vmcs->vnmi_blocked_time +=
10484                         ktime_to_ns(ktime_sub(ktime_get(),
10485                                               vmx->loaded_vmcs->entry_time));
10486 }
10487
10488 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
10489                                       u32 idt_vectoring_info,
10490                                       int instr_len_field,
10491                                       int error_code_field)
10492 {
10493         u8 vector;
10494         int type;
10495         bool idtv_info_valid;
10496
10497         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
10498
10499         vcpu->arch.nmi_injected = false;
10500         kvm_clear_exception_queue(vcpu);
10501         kvm_clear_interrupt_queue(vcpu);
10502
10503         if (!idtv_info_valid)
10504                 return;
10505
10506         kvm_make_request(KVM_REQ_EVENT, vcpu);
10507
10508         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
10509         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
10510
10511         switch (type) {
10512         case INTR_TYPE_NMI_INTR:
10513                 vcpu->arch.nmi_injected = true;
10514                 /*
10515                  * SDM 3: 27.7.1.2 (September 2008)
10516                  * Clear bit "block by NMI" before VM entry if a NMI
10517                  * delivery faulted.
10518                  */
10519                 vmx_set_nmi_mask(vcpu, false);
10520                 break;
10521         case INTR_TYPE_SOFT_EXCEPTION:
10522                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
10523                 /* fall through */
10524         case INTR_TYPE_HARD_EXCEPTION:
10525                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
10526                         u32 err = vmcs_read32(error_code_field);
10527                         kvm_requeue_exception_e(vcpu, vector, err);
10528                 } else
10529                         kvm_requeue_exception(vcpu, vector);
10530                 break;
10531         case INTR_TYPE_SOFT_INTR:
10532                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
10533                 /* fall through */
10534         case INTR_TYPE_EXT_INTR:
10535                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
10536                 break;
10537         default:
10538                 break;
10539         }
10540 }
10541
10542 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
10543 {
10544         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
10545                                   VM_EXIT_INSTRUCTION_LEN,
10546                                   IDT_VECTORING_ERROR_CODE);
10547 }
10548
10549 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
10550 {
10551         __vmx_complete_interrupts(vcpu,
10552                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
10553                                   VM_ENTRY_INSTRUCTION_LEN,
10554                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
10555
10556         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10557 }
10558
10559 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
10560 {
10561         int i, nr_msrs;
10562         struct perf_guest_switch_msr *msrs;
10563
10564         msrs = perf_guest_get_msrs(&nr_msrs);
10565
10566         if (!msrs)
10567                 return;
10568
10569         for (i = 0; i < nr_msrs; i++)
10570                 if (msrs[i].host == msrs[i].guest)
10571                         clear_atomic_switch_msr(vmx, msrs[i].msr);
10572                 else
10573                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
10574                                         msrs[i].host, false);
10575 }
10576
10577 static void vmx_arm_hv_timer(struct vcpu_vmx *vmx, u32 val)
10578 {
10579         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, val);
10580         if (!vmx->loaded_vmcs->hv_timer_armed)
10581                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10582                               PIN_BASED_VMX_PREEMPTION_TIMER);
10583         vmx->loaded_vmcs->hv_timer_armed = true;
10584 }
10585
10586 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
10587 {
10588         struct vcpu_vmx *vmx = to_vmx(vcpu);
10589         u64 tscl;
10590         u32 delta_tsc;
10591
10592         if (vmx->req_immediate_exit) {
10593                 vmx_arm_hv_timer(vmx, 0);
10594                 return;
10595         }
10596
10597         if (vmx->hv_deadline_tsc != -1) {
10598                 tscl = rdtsc();
10599                 if (vmx->hv_deadline_tsc > tscl)
10600                         /* set_hv_timer ensures the delta fits in 32-bits */
10601                         delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
10602                                 cpu_preemption_timer_multi);
10603                 else
10604                         delta_tsc = 0;
10605
10606                 vmx_arm_hv_timer(vmx, delta_tsc);
10607                 return;
10608         }
10609
10610         if (vmx->loaded_vmcs->hv_timer_armed)
10611                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10612                                 PIN_BASED_VMX_PREEMPTION_TIMER);
10613         vmx->loaded_vmcs->hv_timer_armed = false;
10614 }
10615
10616 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
10617 {
10618         struct vcpu_vmx *vmx = to_vmx(vcpu);
10619         unsigned long cr3, cr4, evmcs_rsp;
10620
10621         /* Record the guest's net vcpu time for enforced NMI injections. */
10622         if (unlikely(!enable_vnmi &&
10623                      vmx->loaded_vmcs->soft_vnmi_blocked))
10624                 vmx->loaded_vmcs->entry_time = ktime_get();
10625
10626         /* Don't enter VMX if guest state is invalid, let the exit handler
10627            start emulation until we arrive back to a valid state */
10628         if (vmx->emulation_required)
10629                 return;
10630
10631         if (vmx->ple_window_dirty) {
10632                 vmx->ple_window_dirty = false;
10633                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
10634         }
10635
10636         if (vmx->nested.sync_shadow_vmcs) {
10637                 copy_vmcs12_to_shadow(vmx);
10638                 vmx->nested.sync_shadow_vmcs = false;
10639         }
10640
10641         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
10642                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
10643         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
10644                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
10645
10646         cr3 = __get_current_cr3_fast();
10647         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
10648                 vmcs_writel(HOST_CR3, cr3);
10649                 vmx->loaded_vmcs->host_state.cr3 = cr3;
10650         }
10651
10652         cr4 = cr4_read_shadow();
10653         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
10654                 vmcs_writel(HOST_CR4, cr4);
10655                 vmx->loaded_vmcs->host_state.cr4 = cr4;
10656         }
10657
10658         /* When single-stepping over STI and MOV SS, we must clear the
10659          * corresponding interruptibility bits in the guest state. Otherwise
10660          * vmentry fails as it then expects bit 14 (BS) in pending debug
10661          * exceptions being set, but that's not correct for the guest debugging
10662          * case. */
10663         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10664                 vmx_set_interrupt_shadow(vcpu, 0);
10665
10666         if (static_cpu_has(X86_FEATURE_PKU) &&
10667             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
10668             vcpu->arch.pkru != vmx->host_pkru)
10669                 __write_pkru(vcpu->arch.pkru);
10670
10671         atomic_switch_perf_msrs(vmx);
10672
10673         vmx_update_hv_timer(vcpu);
10674
10675         /*
10676          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
10677          * it's non-zero. Since vmentry is serialising on affected CPUs, there
10678          * is no need to worry about the conditional branch over the wrmsr
10679          * being speculatively taken.
10680          */
10681         x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
10682
10683         vmx->__launched = vmx->loaded_vmcs->launched;
10684
10685         evmcs_rsp = static_branch_unlikely(&enable_evmcs) ?
10686                 (unsigned long)&current_evmcs->host_rsp : 0;
10687
10688         if (static_branch_unlikely(&vmx_l1d_should_flush))
10689                 vmx_l1d_flush(vcpu);
10690
10691         asm(
10692                 /* Store host registers */
10693                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
10694                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
10695                 "push %%" _ASM_CX " \n\t"
10696                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10697                 "je 1f \n\t"
10698                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10699                 /* Avoid VMWRITE when Enlightened VMCS is in use */
10700                 "test %%" _ASM_SI ", %%" _ASM_SI " \n\t"
10701                 "jz 2f \n\t"
10702                 "mov %%" _ASM_SP ", (%%" _ASM_SI ") \n\t"
10703                 "jmp 1f \n\t"
10704                 "2: \n\t"
10705                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
10706                 "1: \n\t"
10707                 /* Reload cr2 if changed */
10708                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
10709                 "mov %%cr2, %%" _ASM_DX " \n\t"
10710                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
10711                 "je 3f \n\t"
10712                 "mov %%" _ASM_AX", %%cr2 \n\t"
10713                 "3: \n\t"
10714                 /* Check if vmlaunch of vmresume is needed */
10715                 "cmpl $0, %c[launched](%0) \n\t"
10716                 /* Load guest registers.  Don't clobber flags. */
10717                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
10718                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
10719                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
10720                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
10721                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
10722                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
10723 #ifdef CONFIG_X86_64
10724                 "mov %c[r8](%0),  %%r8  \n\t"
10725                 "mov %c[r9](%0),  %%r9  \n\t"
10726                 "mov %c[r10](%0), %%r10 \n\t"
10727                 "mov %c[r11](%0), %%r11 \n\t"
10728                 "mov %c[r12](%0), %%r12 \n\t"
10729                 "mov %c[r13](%0), %%r13 \n\t"
10730                 "mov %c[r14](%0), %%r14 \n\t"
10731                 "mov %c[r15](%0), %%r15 \n\t"
10732 #endif
10733                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
10734
10735                 /* Enter guest mode */
10736                 "jne 1f \n\t"
10737                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
10738                 "jmp 2f \n\t"
10739                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
10740                 "2: "
10741                 /* Save guest registers, load host registers, keep flags */
10742                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
10743                 "pop %0 \n\t"
10744                 "setbe %c[fail](%0)\n\t"
10745                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
10746                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
10747                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
10748                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
10749                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
10750                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
10751                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
10752 #ifdef CONFIG_X86_64
10753                 "mov %%r8,  %c[r8](%0) \n\t"
10754                 "mov %%r9,  %c[r9](%0) \n\t"
10755                 "mov %%r10, %c[r10](%0) \n\t"
10756                 "mov %%r11, %c[r11](%0) \n\t"
10757                 "mov %%r12, %c[r12](%0) \n\t"
10758                 "mov %%r13, %c[r13](%0) \n\t"
10759                 "mov %%r14, %c[r14](%0) \n\t"
10760                 "mov %%r15, %c[r15](%0) \n\t"
10761                 "xor %%r8d,  %%r8d \n\t"
10762                 "xor %%r9d,  %%r9d \n\t"
10763                 "xor %%r10d, %%r10d \n\t"
10764                 "xor %%r11d, %%r11d \n\t"
10765                 "xor %%r12d, %%r12d \n\t"
10766                 "xor %%r13d, %%r13d \n\t"
10767                 "xor %%r14d, %%r14d \n\t"
10768                 "xor %%r15d, %%r15d \n\t"
10769 #endif
10770                 "mov %%cr2, %%" _ASM_AX "   \n\t"
10771                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
10772
10773                 "xor %%eax, %%eax \n\t"
10774                 "xor %%ebx, %%ebx \n\t"
10775                 "xor %%esi, %%esi \n\t"
10776                 "xor %%edi, %%edi \n\t"
10777                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
10778                 ".pushsection .rodata \n\t"
10779                 ".global vmx_return \n\t"
10780                 "vmx_return: " _ASM_PTR " 2b \n\t"
10781                 ".popsection"
10782               : : "c"(vmx), "d"((unsigned long)HOST_RSP), "S"(evmcs_rsp),
10783                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
10784                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
10785                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
10786                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
10787                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
10788                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
10789                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
10790                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
10791                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
10792                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
10793 #ifdef CONFIG_X86_64
10794                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
10795                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
10796                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
10797                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
10798                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
10799                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
10800                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
10801                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
10802 #endif
10803                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
10804                 [wordsize]"i"(sizeof(ulong))
10805               : "cc", "memory"
10806 #ifdef CONFIG_X86_64
10807                 , "rax", "rbx", "rdi"
10808                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
10809 #else
10810                 , "eax", "ebx", "edi"
10811 #endif
10812               );
10813
10814         /*
10815          * We do not use IBRS in the kernel. If this vCPU has used the
10816          * SPEC_CTRL MSR it may have left it on; save the value and
10817          * turn it off. This is much more efficient than blindly adding
10818          * it to the atomic save/restore list. Especially as the former
10819          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
10820          *
10821          * For non-nested case:
10822          * If the L01 MSR bitmap does not intercept the MSR, then we need to
10823          * save it.
10824          *
10825          * For nested case:
10826          * If the L02 MSR bitmap does not intercept the MSR, then we need to
10827          * save it.
10828          */
10829         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
10830                 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
10831
10832         x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
10833
10834         /* Eliminate branch target predictions from guest mode */
10835         vmexit_fill_RSB();
10836
10837         /* All fields are clean at this point */
10838         if (static_branch_unlikely(&enable_evmcs))
10839                 current_evmcs->hv_clean_fields |=
10840                         HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
10841
10842         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
10843         if (vmx->host_debugctlmsr)
10844                 update_debugctlmsr(vmx->host_debugctlmsr);
10845
10846 #ifndef CONFIG_X86_64
10847         /*
10848          * The sysexit path does not restore ds/es, so we must set them to
10849          * a reasonable value ourselves.
10850          *
10851          * We can't defer this to vmx_prepare_switch_to_host() since that
10852          * function may be executed in interrupt context, which saves and
10853          * restore segments around it, nullifying its effect.
10854          */
10855         loadsegment(ds, __USER_DS);
10856         loadsegment(es, __USER_DS);
10857 #endif
10858
10859         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
10860                                   | (1 << VCPU_EXREG_RFLAGS)
10861                                   | (1 << VCPU_EXREG_PDPTR)
10862                                   | (1 << VCPU_EXREG_SEGMENTS)
10863                                   | (1 << VCPU_EXREG_CR3));
10864         vcpu->arch.regs_dirty = 0;
10865
10866         /*
10867          * eager fpu is enabled if PKEY is supported and CR4 is switched
10868          * back on host, so it is safe to read guest PKRU from current
10869          * XSAVE.
10870          */
10871         if (static_cpu_has(X86_FEATURE_PKU) &&
10872             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
10873                 vcpu->arch.pkru = __read_pkru();
10874                 if (vcpu->arch.pkru != vmx->host_pkru)
10875                         __write_pkru(vmx->host_pkru);
10876         }
10877
10878         vmx->nested.nested_run_pending = 0;
10879         vmx->idt_vectoring_info = 0;
10880
10881         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
10882         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
10883                 return;
10884
10885         vmx->loaded_vmcs->launched = 1;
10886         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
10887
10888         vmx_complete_atomic_exit(vmx);
10889         vmx_recover_nmi_blocking(vmx);
10890         vmx_complete_interrupts(vmx);
10891 }
10892 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
10893
10894 static struct kvm *vmx_vm_alloc(void)
10895 {
10896         struct kvm_vmx *kvm_vmx = vzalloc(sizeof(struct kvm_vmx));
10897         return &kvm_vmx->kvm;
10898 }
10899
10900 static void vmx_vm_free(struct kvm *kvm)
10901 {
10902         vfree(to_kvm_vmx(kvm));
10903 }
10904
10905 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
10906 {
10907         struct vcpu_vmx *vmx = to_vmx(vcpu);
10908         int cpu;
10909
10910         if (vmx->loaded_vmcs == vmcs)
10911                 return;
10912
10913         cpu = get_cpu();
10914         vmx_vcpu_put(vcpu);
10915         vmx->loaded_vmcs = vmcs;
10916         vmx_vcpu_load(vcpu, cpu);
10917         put_cpu();
10918
10919         vm_entry_controls_reset_shadow(vmx);
10920         vm_exit_controls_reset_shadow(vmx);
10921         vmx_segment_cache_clear(vmx);
10922 }
10923
10924 /*
10925  * Ensure that the current vmcs of the logical processor is the
10926  * vmcs01 of the vcpu before calling free_nested().
10927  */
10928 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
10929 {
10930        struct vcpu_vmx *vmx = to_vmx(vcpu);
10931
10932        vcpu_load(vcpu);
10933        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10934        free_nested(vmx);
10935        vcpu_put(vcpu);
10936 }
10937
10938 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
10939 {
10940         struct vcpu_vmx *vmx = to_vmx(vcpu);
10941
10942         if (enable_pml)
10943                 vmx_destroy_pml_buffer(vmx);
10944         free_vpid(vmx->vpid);
10945         leave_guest_mode(vcpu);
10946         vmx_free_vcpu_nested(vcpu);
10947         free_loaded_vmcs(vmx->loaded_vmcs);
10948         kfree(vmx->guest_msrs);
10949         kvm_vcpu_uninit(vcpu);
10950         kmem_cache_free(kvm_vcpu_cache, vmx);
10951 }
10952
10953 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
10954 {
10955         int err;
10956         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
10957         unsigned long *msr_bitmap;
10958         int cpu;
10959
10960         if (!vmx)
10961                 return ERR_PTR(-ENOMEM);
10962
10963         vmx->vpid = allocate_vpid();
10964
10965         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
10966         if (err)
10967                 goto free_vcpu;
10968
10969         err = -ENOMEM;
10970
10971         /*
10972          * If PML is turned on, failure on enabling PML just results in failure
10973          * of creating the vcpu, therefore we can simplify PML logic (by
10974          * avoiding dealing with cases, such as enabling PML partially on vcpus
10975          * for the guest, etc.
10976          */
10977         if (enable_pml) {
10978                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
10979                 if (!vmx->pml_pg)
10980                         goto uninit_vcpu;
10981         }
10982
10983         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
10984         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
10985                      > PAGE_SIZE);
10986
10987         if (!vmx->guest_msrs)
10988                 goto free_pml;
10989
10990         err = alloc_loaded_vmcs(&vmx->vmcs01);
10991         if (err < 0)
10992                 goto free_msrs;
10993
10994         msr_bitmap = vmx->vmcs01.msr_bitmap;
10995         vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
10996         vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
10997         vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
10998         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
10999         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
11000         vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
11001         vmx->msr_bitmap_mode = 0;
11002
11003         vmx->loaded_vmcs = &vmx->vmcs01;
11004         cpu = get_cpu();
11005         vmx_vcpu_load(&vmx->vcpu, cpu);
11006         vmx->vcpu.cpu = cpu;
11007         vmx_vcpu_setup(vmx);
11008         vmx_vcpu_put(&vmx->vcpu);
11009         put_cpu();
11010         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
11011                 err = alloc_apic_access_page(kvm);
11012                 if (err)
11013                         goto free_vmcs;
11014         }
11015
11016         if (enable_ept && !enable_unrestricted_guest) {
11017                 err = init_rmode_identity_map(kvm);
11018                 if (err)
11019                         goto free_vmcs;
11020         }
11021
11022         if (nested)
11023                 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
11024                                            kvm_vcpu_apicv_active(&vmx->vcpu));
11025
11026         vmx->nested.posted_intr_nv = -1;
11027         vmx->nested.current_vmptr = -1ull;
11028
11029         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
11030
11031         /*
11032          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
11033          * or POSTED_INTR_WAKEUP_VECTOR.
11034          */
11035         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
11036         vmx->pi_desc.sn = 1;
11037
11038         return &vmx->vcpu;
11039
11040 free_vmcs:
11041         free_loaded_vmcs(vmx->loaded_vmcs);
11042 free_msrs:
11043         kfree(vmx->guest_msrs);
11044 free_pml:
11045         vmx_destroy_pml_buffer(vmx);
11046 uninit_vcpu:
11047         kvm_vcpu_uninit(&vmx->vcpu);
11048 free_vcpu:
11049         free_vpid(vmx->vpid);
11050         kmem_cache_free(kvm_vcpu_cache, vmx);
11051         return ERR_PTR(err);
11052 }
11053
11054 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
11055 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
11056
11057 static int vmx_vm_init(struct kvm *kvm)
11058 {
11059         spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
11060
11061         if (!ple_gap)
11062                 kvm->arch.pause_in_guest = true;
11063
11064         if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
11065                 switch (l1tf_mitigation) {
11066                 case L1TF_MITIGATION_OFF:
11067                 case L1TF_MITIGATION_FLUSH_NOWARN:
11068                         /* 'I explicitly don't care' is set */
11069                         break;
11070                 case L1TF_MITIGATION_FLUSH:
11071                 case L1TF_MITIGATION_FLUSH_NOSMT:
11072                 case L1TF_MITIGATION_FULL:
11073                         /*
11074                          * Warn upon starting the first VM in a potentially
11075                          * insecure environment.
11076                          */
11077                         if (cpu_smt_control == CPU_SMT_ENABLED)
11078                                 pr_warn_once(L1TF_MSG_SMT);
11079                         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
11080                                 pr_warn_once(L1TF_MSG_L1D);
11081                         break;
11082                 case L1TF_MITIGATION_FULL_FORCE:
11083                         /* Flush is enforced */
11084                         break;
11085                 }
11086         }
11087         return 0;
11088 }
11089
11090 static void __init vmx_check_processor_compat(void *rtn)
11091 {
11092         struct vmcs_config vmcs_conf;
11093
11094         *(int *)rtn = 0;
11095         if (setup_vmcs_config(&vmcs_conf) < 0)
11096                 *(int *)rtn = -EIO;
11097         nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, enable_apicv);
11098         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
11099                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
11100                                 smp_processor_id());
11101                 *(int *)rtn = -EIO;
11102         }
11103 }
11104
11105 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
11106 {
11107         u8 cache;
11108         u64 ipat = 0;
11109
11110         /* For VT-d and EPT combination
11111          * 1. MMIO: always map as UC
11112          * 2. EPT with VT-d:
11113          *   a. VT-d without snooping control feature: can't guarantee the
11114          *      result, try to trust guest.
11115          *   b. VT-d with snooping control feature: snooping control feature of
11116          *      VT-d engine can guarantee the cache correctness. Just set it
11117          *      to WB to keep consistent with host. So the same as item 3.
11118          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
11119          *    consistent with host MTRR
11120          */
11121         if (is_mmio) {
11122                 cache = MTRR_TYPE_UNCACHABLE;
11123                 goto exit;
11124         }
11125
11126         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
11127                 ipat = VMX_EPT_IPAT_BIT;
11128                 cache = MTRR_TYPE_WRBACK;
11129                 goto exit;
11130         }
11131
11132         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
11133                 ipat = VMX_EPT_IPAT_BIT;
11134                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
11135                         cache = MTRR_TYPE_WRBACK;
11136                 else
11137                         cache = MTRR_TYPE_UNCACHABLE;
11138                 goto exit;
11139         }
11140
11141         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
11142
11143 exit:
11144         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
11145 }
11146
11147 static int vmx_get_lpage_level(void)
11148 {
11149         if (enable_ept && !cpu_has_vmx_ept_1g_page())
11150                 return PT_DIRECTORY_LEVEL;
11151         else
11152                 /* For shadow and EPT supported 1GB page */
11153                 return PT_PDPE_LEVEL;
11154 }
11155
11156 static void vmcs_set_secondary_exec_control(u32 new_ctl)
11157 {
11158         /*
11159          * These bits in the secondary execution controls field
11160          * are dynamic, the others are mostly based on the hypervisor
11161          * architecture and the guest's CPUID.  Do not touch the
11162          * dynamic bits.
11163          */
11164         u32 mask =
11165                 SECONDARY_EXEC_SHADOW_VMCS |
11166                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
11167                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
11168                 SECONDARY_EXEC_DESC;
11169
11170         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
11171
11172         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
11173                      (new_ctl & ~mask) | (cur_ctl & mask));
11174 }
11175
11176 /*
11177  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
11178  * (indicating "allowed-1") if they are supported in the guest's CPUID.
11179  */
11180 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
11181 {
11182         struct vcpu_vmx *vmx = to_vmx(vcpu);
11183         struct kvm_cpuid_entry2 *entry;
11184
11185         vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
11186         vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
11187
11188 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
11189         if (entry && (entry->_reg & (_cpuid_mask)))                     \
11190                 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);     \
11191 } while (0)
11192
11193         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
11194         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
11195         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
11196         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
11197         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
11198         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
11199         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
11200         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
11201         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
11202         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
11203         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
11204         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
11205         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
11206         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
11207         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
11208
11209         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
11210         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
11211         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
11212         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
11213         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
11214         cr4_fixed1_update(X86_CR4_UMIP,       ecx, bit(X86_FEATURE_UMIP));
11215
11216 #undef cr4_fixed1_update
11217 }
11218
11219 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
11220 {
11221         struct vcpu_vmx *vmx = to_vmx(vcpu);
11222
11223         if (kvm_mpx_supported()) {
11224                 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
11225
11226                 if (mpx_enabled) {
11227                         vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
11228                         vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
11229                 } else {
11230                         vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
11231                         vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
11232                 }
11233         }
11234 }
11235
11236 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
11237 {
11238         struct vcpu_vmx *vmx = to_vmx(vcpu);
11239
11240         if (cpu_has_secondary_exec_ctrls()) {
11241                 vmx_compute_secondary_exec_control(vmx);
11242                 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
11243         }
11244
11245         if (nested_vmx_allowed(vcpu))
11246                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11247                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
11248         else
11249                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11250                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
11251
11252         if (nested_vmx_allowed(vcpu)) {
11253                 nested_vmx_cr_fixed1_bits_update(vcpu);
11254                 nested_vmx_entry_exit_ctls_update(vcpu);
11255         }
11256 }
11257
11258 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
11259 {
11260         if (func == 1 && nested)
11261                 entry->ecx |= bit(X86_FEATURE_VMX);
11262 }
11263
11264 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
11265                 struct x86_exception *fault)
11266 {
11267         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11268         struct vcpu_vmx *vmx = to_vmx(vcpu);
11269         u32 exit_reason;
11270         unsigned long exit_qualification = vcpu->arch.exit_qualification;
11271
11272         if (vmx->nested.pml_full) {
11273                 exit_reason = EXIT_REASON_PML_FULL;
11274                 vmx->nested.pml_full = false;
11275                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
11276         } else if (fault->error_code & PFERR_RSVD_MASK)
11277                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
11278         else
11279                 exit_reason = EXIT_REASON_EPT_VIOLATION;
11280
11281         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
11282         vmcs12->guest_physical_address = fault->address;
11283 }
11284
11285 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
11286 {
11287         return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
11288 }
11289
11290 /* Callbacks for nested_ept_init_mmu_context: */
11291
11292 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
11293 {
11294         /* return the page table to be shadowed - in our case, EPT12 */
11295         return get_vmcs12(vcpu)->ept_pointer;
11296 }
11297
11298 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
11299 {
11300         WARN_ON(mmu_is_nested(vcpu));
11301
11302         kvm_init_shadow_ept_mmu(vcpu,
11303                         to_vmx(vcpu)->nested.msrs.ept_caps &
11304                         VMX_EPT_EXECUTE_ONLY_BIT,
11305                         nested_ept_ad_enabled(vcpu),
11306                         nested_ept_get_cr3(vcpu));
11307         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
11308         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
11309         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
11310
11311         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
11312 }
11313
11314 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
11315 {
11316         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
11317 }
11318
11319 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
11320                                             u16 error_code)
11321 {
11322         bool inequality, bit;
11323
11324         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
11325         inequality =
11326                 (error_code & vmcs12->page_fault_error_code_mask) !=
11327                  vmcs12->page_fault_error_code_match;
11328         return inequality ^ bit;
11329 }
11330
11331 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
11332                 struct x86_exception *fault)
11333 {
11334         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11335
11336         WARN_ON(!is_guest_mode(vcpu));
11337
11338         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
11339                 !to_vmx(vcpu)->nested.nested_run_pending) {
11340                 vmcs12->vm_exit_intr_error_code = fault->error_code;
11341                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
11342                                   PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
11343                                   INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
11344                                   fault->address);
11345         } else {
11346                 kvm_inject_page_fault(vcpu, fault);
11347         }
11348 }
11349
11350 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
11351                                                  struct vmcs12 *vmcs12);
11352
11353 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu)
11354 {
11355         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11356         struct vcpu_vmx *vmx = to_vmx(vcpu);
11357         struct page *page;
11358         u64 hpa;
11359
11360         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11361                 /*
11362                  * Translate L1 physical address to host physical
11363                  * address for vmcs02. Keep the page pinned, so this
11364                  * physical address remains valid. We keep a reference
11365                  * to it so we can release it later.
11366                  */
11367                 if (vmx->nested.apic_access_page) { /* shouldn't happen */
11368                         kvm_release_page_dirty(vmx->nested.apic_access_page);
11369                         vmx->nested.apic_access_page = NULL;
11370                 }
11371                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
11372                 /*
11373                  * If translation failed, no matter: This feature asks
11374                  * to exit when accessing the given address, and if it
11375                  * can never be accessed, this feature won't do
11376                  * anything anyway.
11377                  */
11378                 if (!is_error_page(page)) {
11379                         vmx->nested.apic_access_page = page;
11380                         hpa = page_to_phys(vmx->nested.apic_access_page);
11381                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
11382                 } else {
11383                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
11384                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
11385                 }
11386         }
11387
11388         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
11389                 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
11390                         kvm_release_page_dirty(vmx->nested.virtual_apic_page);
11391                         vmx->nested.virtual_apic_page = NULL;
11392                 }
11393                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
11394
11395                 /*
11396                  * If translation failed, VM entry will fail because
11397                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
11398                  * Failing the vm entry is _not_ what the processor
11399                  * does but it's basically the only possibility we
11400                  * have.  We could still enter the guest if CR8 load
11401                  * exits are enabled, CR8 store exits are enabled, and
11402                  * virtualize APIC access is disabled; in this case
11403                  * the processor would never use the TPR shadow and we
11404                  * could simply clear the bit from the execution
11405                  * control.  But such a configuration is useless, so
11406                  * let's keep the code simple.
11407                  */
11408                 if (!is_error_page(page)) {
11409                         vmx->nested.virtual_apic_page = page;
11410                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
11411                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
11412                 }
11413         }
11414
11415         if (nested_cpu_has_posted_intr(vmcs12)) {
11416                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
11417                         kunmap(vmx->nested.pi_desc_page);
11418                         kvm_release_page_dirty(vmx->nested.pi_desc_page);
11419                         vmx->nested.pi_desc_page = NULL;
11420                 }
11421                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
11422                 if (is_error_page(page))
11423                         return;
11424                 vmx->nested.pi_desc_page = page;
11425                 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
11426                 vmx->nested.pi_desc =
11427                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
11428                         (unsigned long)(vmcs12->posted_intr_desc_addr &
11429                         (PAGE_SIZE - 1)));
11430                 vmcs_write64(POSTED_INTR_DESC_ADDR,
11431                         page_to_phys(vmx->nested.pi_desc_page) +
11432                         (unsigned long)(vmcs12->posted_intr_desc_addr &
11433                         (PAGE_SIZE - 1)));
11434         }
11435         if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
11436                 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
11437                               CPU_BASED_USE_MSR_BITMAPS);
11438         else
11439                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
11440                                 CPU_BASED_USE_MSR_BITMAPS);
11441 }
11442
11443 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
11444 {
11445         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
11446         struct vcpu_vmx *vmx = to_vmx(vcpu);
11447
11448         /*
11449          * A timer value of zero is architecturally guaranteed to cause
11450          * a VMExit prior to executing any instructions in the guest.
11451          */
11452         if (preemption_timeout == 0) {
11453                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
11454                 return;
11455         }
11456
11457         if (vcpu->arch.virtual_tsc_khz == 0)
11458                 return;
11459
11460         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
11461         preemption_timeout *= 1000000;
11462         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
11463         hrtimer_start(&vmx->nested.preemption_timer,
11464                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
11465 }
11466
11467 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
11468                                                struct vmcs12 *vmcs12)
11469 {
11470         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
11471                 return 0;
11472
11473         if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
11474             !page_address_valid(vcpu, vmcs12->io_bitmap_b))
11475                 return -EINVAL;
11476
11477         return 0;
11478 }
11479
11480 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
11481                                                 struct vmcs12 *vmcs12)
11482 {
11483         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
11484                 return 0;
11485
11486         if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
11487                 return -EINVAL;
11488
11489         return 0;
11490 }
11491
11492 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
11493                                                 struct vmcs12 *vmcs12)
11494 {
11495         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
11496                 return 0;
11497
11498         if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
11499                 return -EINVAL;
11500
11501         return 0;
11502 }
11503
11504 /*
11505  * Merge L0's and L1's MSR bitmap, return false to indicate that
11506  * we do not use the hardware.
11507  */
11508 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
11509                                                  struct vmcs12 *vmcs12)
11510 {
11511         int msr;
11512         struct page *page;
11513         unsigned long *msr_bitmap_l1;
11514         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
11515         /*
11516          * pred_cmd & spec_ctrl are trying to verify two things:
11517          *
11518          * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
11519          *    ensures that we do not accidentally generate an L02 MSR bitmap
11520          *    from the L12 MSR bitmap that is too permissive.
11521          * 2. That L1 or L2s have actually used the MSR. This avoids
11522          *    unnecessarily merging of the bitmap if the MSR is unused. This
11523          *    works properly because we only update the L01 MSR bitmap lazily.
11524          *    So even if L0 should pass L1 these MSRs, the L01 bitmap is only
11525          *    updated to reflect this when L1 (or its L2s) actually write to
11526          *    the MSR.
11527          */
11528         bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
11529         bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
11530
11531         /* Nothing to do if the MSR bitmap is not in use.  */
11532         if (!cpu_has_vmx_msr_bitmap() ||
11533             !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
11534                 return false;
11535
11536         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
11537             !pred_cmd && !spec_ctrl)
11538                 return false;
11539
11540         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
11541         if (is_error_page(page))
11542                 return false;
11543
11544         msr_bitmap_l1 = (unsigned long *)kmap(page);
11545         if (nested_cpu_has_apic_reg_virt(vmcs12)) {
11546                 /*
11547                  * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it
11548                  * just lets the processor take the value from the virtual-APIC page;
11549                  * take those 256 bits directly from the L1 bitmap.
11550                  */
11551                 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
11552                         unsigned word = msr / BITS_PER_LONG;
11553                         msr_bitmap_l0[word] = msr_bitmap_l1[word];
11554                         msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
11555                 }
11556         } else {
11557                 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
11558                         unsigned word = msr / BITS_PER_LONG;
11559                         msr_bitmap_l0[word] = ~0;
11560                         msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
11561                 }
11562         }
11563
11564         nested_vmx_disable_intercept_for_msr(
11565                 msr_bitmap_l1, msr_bitmap_l0,
11566                 X2APIC_MSR(APIC_TASKPRI),
11567                 MSR_TYPE_W);
11568
11569         if (nested_cpu_has_vid(vmcs12)) {
11570                 nested_vmx_disable_intercept_for_msr(
11571                         msr_bitmap_l1, msr_bitmap_l0,
11572                         X2APIC_MSR(APIC_EOI),
11573                         MSR_TYPE_W);
11574                 nested_vmx_disable_intercept_for_msr(
11575                         msr_bitmap_l1, msr_bitmap_l0,
11576                         X2APIC_MSR(APIC_SELF_IPI),
11577                         MSR_TYPE_W);
11578         }
11579
11580         if (spec_ctrl)
11581                 nested_vmx_disable_intercept_for_msr(
11582                                         msr_bitmap_l1, msr_bitmap_l0,
11583                                         MSR_IA32_SPEC_CTRL,
11584                                         MSR_TYPE_R | MSR_TYPE_W);
11585
11586         if (pred_cmd)
11587                 nested_vmx_disable_intercept_for_msr(
11588                                         msr_bitmap_l1, msr_bitmap_l0,
11589                                         MSR_IA32_PRED_CMD,
11590                                         MSR_TYPE_W);
11591
11592         kunmap(page);
11593         kvm_release_page_clean(page);
11594
11595         return true;
11596 }
11597
11598 static void nested_cache_shadow_vmcs12(struct kvm_vcpu *vcpu,
11599                                        struct vmcs12 *vmcs12)
11600 {
11601         struct vmcs12 *shadow;
11602         struct page *page;
11603
11604         if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
11605             vmcs12->vmcs_link_pointer == -1ull)
11606                 return;
11607
11608         shadow = get_shadow_vmcs12(vcpu);
11609         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->vmcs_link_pointer);
11610
11611         memcpy(shadow, kmap(page), VMCS12_SIZE);
11612
11613         kunmap(page);
11614         kvm_release_page_clean(page);
11615 }
11616
11617 static void nested_flush_cached_shadow_vmcs12(struct kvm_vcpu *vcpu,
11618                                               struct vmcs12 *vmcs12)
11619 {
11620         struct vcpu_vmx *vmx = to_vmx(vcpu);
11621
11622         if (!nested_cpu_has_shadow_vmcs(vmcs12) ||
11623             vmcs12->vmcs_link_pointer == -1ull)
11624                 return;
11625
11626         kvm_write_guest(vmx->vcpu.kvm, vmcs12->vmcs_link_pointer,
11627                         get_shadow_vmcs12(vcpu), VMCS12_SIZE);
11628 }
11629
11630 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu,
11631                                           struct vmcs12 *vmcs12)
11632 {
11633         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
11634             !page_address_valid(vcpu, vmcs12->apic_access_addr))
11635                 return -EINVAL;
11636         else
11637                 return 0;
11638 }
11639
11640 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
11641                                            struct vmcs12 *vmcs12)
11642 {
11643         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
11644             !nested_cpu_has_apic_reg_virt(vmcs12) &&
11645             !nested_cpu_has_vid(vmcs12) &&
11646             !nested_cpu_has_posted_intr(vmcs12))
11647                 return 0;
11648
11649         /*
11650          * If virtualize x2apic mode is enabled,
11651          * virtualize apic access must be disabled.
11652          */
11653         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
11654             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
11655                 return -EINVAL;
11656
11657         /*
11658          * If virtual interrupt delivery is enabled,
11659          * we must exit on external interrupts.
11660          */
11661         if (nested_cpu_has_vid(vmcs12) &&
11662            !nested_exit_on_intr(vcpu))
11663                 return -EINVAL;
11664
11665         /*
11666          * bits 15:8 should be zero in posted_intr_nv,
11667          * the descriptor address has been already checked
11668          * in nested_get_vmcs12_pages.
11669          *
11670          * bits 5:0 of posted_intr_desc_addr should be zero.
11671          */
11672         if (nested_cpu_has_posted_intr(vmcs12) &&
11673            (!nested_cpu_has_vid(vmcs12) ||
11674             !nested_exit_intr_ack_set(vcpu) ||
11675             (vmcs12->posted_intr_nv & 0xff00) ||
11676             (vmcs12->posted_intr_desc_addr & 0x3f) ||
11677             (!page_address_valid(vcpu, vmcs12->posted_intr_desc_addr))))
11678                 return -EINVAL;
11679
11680         /* tpr shadow is needed by all apicv features. */
11681         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
11682                 return -EINVAL;
11683
11684         return 0;
11685 }
11686
11687 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
11688                                        unsigned long count_field,
11689                                        unsigned long addr_field)
11690 {
11691         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11692         int maxphyaddr;
11693         u64 count, addr;
11694
11695         if (vmcs12_read_any(vmcs12, count_field, &count) ||
11696             vmcs12_read_any(vmcs12, addr_field, &addr)) {
11697                 WARN_ON(1);
11698                 return -EINVAL;
11699         }
11700         if (count == 0)
11701                 return 0;
11702         maxphyaddr = cpuid_maxphyaddr(vcpu);
11703         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
11704             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
11705                 pr_debug_ratelimited(
11706                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
11707                         addr_field, maxphyaddr, count, addr);
11708                 return -EINVAL;
11709         }
11710         return 0;
11711 }
11712
11713 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
11714                                                 struct vmcs12 *vmcs12)
11715 {
11716         if (vmcs12->vm_exit_msr_load_count == 0 &&
11717             vmcs12->vm_exit_msr_store_count == 0 &&
11718             vmcs12->vm_entry_msr_load_count == 0)
11719                 return 0; /* Fast path */
11720         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
11721                                         VM_EXIT_MSR_LOAD_ADDR) ||
11722             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
11723                                         VM_EXIT_MSR_STORE_ADDR) ||
11724             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
11725                                         VM_ENTRY_MSR_LOAD_ADDR))
11726                 return -EINVAL;
11727         return 0;
11728 }
11729
11730 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
11731                                          struct vmcs12 *vmcs12)
11732 {
11733         if (!nested_cpu_has_pml(vmcs12))
11734                 return 0;
11735
11736         if (!nested_cpu_has_ept(vmcs12) ||
11737             !page_address_valid(vcpu, vmcs12->pml_address))
11738                 return -EINVAL;
11739
11740         return 0;
11741 }
11742
11743 static int nested_vmx_check_shadow_vmcs_controls(struct kvm_vcpu *vcpu,
11744                                                  struct vmcs12 *vmcs12)
11745 {
11746         if (!nested_cpu_has_shadow_vmcs(vmcs12))
11747                 return 0;
11748
11749         if (!page_address_valid(vcpu, vmcs12->vmread_bitmap) ||
11750             !page_address_valid(vcpu, vmcs12->vmwrite_bitmap))
11751                 return -EINVAL;
11752
11753         return 0;
11754 }
11755
11756 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
11757                                        struct vmx_msr_entry *e)
11758 {
11759         /* x2APIC MSR accesses are not allowed */
11760         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
11761                 return -EINVAL;
11762         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
11763             e->index == MSR_IA32_UCODE_REV)
11764                 return -EINVAL;
11765         if (e->reserved != 0)
11766                 return -EINVAL;
11767         return 0;
11768 }
11769
11770 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
11771                                      struct vmx_msr_entry *e)
11772 {
11773         if (e->index == MSR_FS_BASE ||
11774             e->index == MSR_GS_BASE ||
11775             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
11776             nested_vmx_msr_check_common(vcpu, e))
11777                 return -EINVAL;
11778         return 0;
11779 }
11780
11781 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
11782                                       struct vmx_msr_entry *e)
11783 {
11784         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
11785             nested_vmx_msr_check_common(vcpu, e))
11786                 return -EINVAL;
11787         return 0;
11788 }
11789
11790 /*
11791  * Load guest's/host's msr at nested entry/exit.
11792  * return 0 for success, entry index for failure.
11793  */
11794 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11795 {
11796         u32 i;
11797         struct vmx_msr_entry e;
11798         struct msr_data msr;
11799
11800         msr.host_initiated = false;
11801         for (i = 0; i < count; i++) {
11802                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
11803                                         &e, sizeof(e))) {
11804                         pr_debug_ratelimited(
11805                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11806                                 __func__, i, gpa + i * sizeof(e));
11807                         goto fail;
11808                 }
11809                 if (nested_vmx_load_msr_check(vcpu, &e)) {
11810                         pr_debug_ratelimited(
11811                                 "%s check failed (%u, 0x%x, 0x%x)\n",
11812                                 __func__, i, e.index, e.reserved);
11813                         goto fail;
11814                 }
11815                 msr.index = e.index;
11816                 msr.data = e.value;
11817                 if (kvm_set_msr(vcpu, &msr)) {
11818                         pr_debug_ratelimited(
11819                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11820                                 __func__, i, e.index, e.value);
11821                         goto fail;
11822                 }
11823         }
11824         return 0;
11825 fail:
11826         return i + 1;
11827 }
11828
11829 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11830 {
11831         u32 i;
11832         struct vmx_msr_entry e;
11833
11834         for (i = 0; i < count; i++) {
11835                 struct msr_data msr_info;
11836                 if (kvm_vcpu_read_guest(vcpu,
11837                                         gpa + i * sizeof(e),
11838                                         &e, 2 * sizeof(u32))) {
11839                         pr_debug_ratelimited(
11840                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11841                                 __func__, i, gpa + i * sizeof(e));
11842                         return -EINVAL;
11843                 }
11844                 if (nested_vmx_store_msr_check(vcpu, &e)) {
11845                         pr_debug_ratelimited(
11846                                 "%s check failed (%u, 0x%x, 0x%x)\n",
11847                                 __func__, i, e.index, e.reserved);
11848                         return -EINVAL;
11849                 }
11850                 msr_info.host_initiated = false;
11851                 msr_info.index = e.index;
11852                 if (kvm_get_msr(vcpu, &msr_info)) {
11853                         pr_debug_ratelimited(
11854                                 "%s cannot read MSR (%u, 0x%x)\n",
11855                                 __func__, i, e.index);
11856                         return -EINVAL;
11857                 }
11858                 if (kvm_vcpu_write_guest(vcpu,
11859                                          gpa + i * sizeof(e) +
11860                                              offsetof(struct vmx_msr_entry, value),
11861                                          &msr_info.data, sizeof(msr_info.data))) {
11862                         pr_debug_ratelimited(
11863                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11864                                 __func__, i, e.index, msr_info.data);
11865                         return -EINVAL;
11866                 }
11867         }
11868         return 0;
11869 }
11870
11871 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
11872 {
11873         unsigned long invalid_mask;
11874
11875         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
11876         return (val & invalid_mask) == 0;
11877 }
11878
11879 /*
11880  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
11881  * emulating VM entry into a guest with EPT enabled.
11882  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
11883  * is assigned to entry_failure_code on failure.
11884  */
11885 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
11886                                u32 *entry_failure_code)
11887 {
11888         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
11889                 if (!nested_cr3_valid(vcpu, cr3)) {
11890                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
11891                         return 1;
11892                 }
11893
11894                 /*
11895                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
11896                  * must not be dereferenced.
11897                  */
11898                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
11899                     !nested_ept) {
11900                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
11901                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
11902                                 return 1;
11903                         }
11904                 }
11905         }
11906
11907         if (!nested_ept)
11908                 kvm_mmu_new_cr3(vcpu, cr3, false);
11909
11910         vcpu->arch.cr3 = cr3;
11911         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
11912
11913         kvm_init_mmu(vcpu, false);
11914
11915         return 0;
11916 }
11917
11918 /*
11919  * Returns if KVM is able to config CPU to tag TLB entries
11920  * populated by L2 differently than TLB entries populated
11921  * by L1.
11922  *
11923  * If L1 uses EPT, then TLB entries are tagged with different EPTP.
11924  *
11925  * If L1 uses VPID and we allocated a vpid02, TLB entries are tagged
11926  * with different VPID (L1 entries are tagged with vmx->vpid
11927  * while L2 entries are tagged with vmx->nested.vpid02).
11928  */
11929 static bool nested_has_guest_tlb_tag(struct kvm_vcpu *vcpu)
11930 {
11931         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11932
11933         return nested_cpu_has_ept(vmcs12) ||
11934                (nested_cpu_has_vpid(vmcs12) && to_vmx(vcpu)->nested.vpid02);
11935 }
11936
11937 static u64 nested_vmx_calc_efer(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
11938 {
11939         if (vmx->nested.nested_run_pending &&
11940             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
11941                 return vmcs12->guest_ia32_efer;
11942         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
11943                 return vmx->vcpu.arch.efer | (EFER_LMA | EFER_LME);
11944         else
11945                 return vmx->vcpu.arch.efer & ~(EFER_LMA | EFER_LME);
11946 }
11947
11948 static void prepare_vmcs02_constant_state(struct vcpu_vmx *vmx)
11949 {
11950         /*
11951          * If vmcs02 hasn't been initialized, set the constant vmcs02 state
11952          * according to L0's settings (vmcs12 is irrelevant here).  Host
11953          * fields that come from L0 and are not constant, e.g. HOST_CR3,
11954          * will be set as needed prior to VMLAUNCH/VMRESUME.
11955          */
11956         if (vmx->nested.vmcs02_initialized)
11957                 return;
11958         vmx->nested.vmcs02_initialized = true;
11959
11960         /*
11961          * We don't care what the EPTP value is we just need to guarantee
11962          * it's valid so we don't get a false positive when doing early
11963          * consistency checks.
11964          */
11965         if (enable_ept && nested_early_check)
11966                 vmcs_write64(EPT_POINTER, construct_eptp(&vmx->vcpu, 0));
11967
11968         /* All VMFUNCs are currently emulated through L0 vmexits.  */
11969         if (cpu_has_vmx_vmfunc())
11970                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
11971
11972         if (cpu_has_vmx_posted_intr())
11973                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
11974
11975         if (cpu_has_vmx_msr_bitmap())
11976                 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
11977
11978         if (enable_pml)
11979                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
11980
11981         /*
11982          * Set the MSR load/store lists to match L0's settings.  Only the
11983          * addresses are constant (for vmcs02), the counts can change based
11984          * on L2's behavior, e.g. switching to/from long mode.
11985          */
11986         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
11987         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
11988         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
11989
11990         vmx_set_constant_host_state(vmx);
11991 }
11992
11993 static void prepare_vmcs02_early_full(struct vcpu_vmx *vmx,
11994                                       struct vmcs12 *vmcs12)
11995 {
11996         prepare_vmcs02_constant_state(vmx);
11997
11998         vmcs_write64(VMCS_LINK_POINTER, -1ull);
11999
12000         if (enable_vpid) {
12001                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
12002                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
12003                 else
12004                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
12005         }
12006 }
12007
12008 static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
12009 {
12010         u32 exec_control, vmcs12_exec_ctrl;
12011         u64 guest_efer = nested_vmx_calc_efer(vmx, vmcs12);
12012
12013         if (vmx->nested.dirty_vmcs12)
12014                 prepare_vmcs02_early_full(vmx, vmcs12);
12015
12016         /*
12017          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
12018          * entry, but only if the current (host) sp changed from the value
12019          * we wrote last (vmx->host_rsp).  This cache is no longer relevant
12020          * if we switch vmcs, and rather than hold a separate cache per vmcs,
12021          * here we just force the write to happen on entry.  host_rsp will
12022          * also be written unconditionally by nested_vmx_check_vmentry_hw()
12023          * if we are doing early consistency checks via hardware.
12024          */
12025         vmx->host_rsp = 0;
12026
12027         /*
12028          * PIN CONTROLS
12029          */
12030         exec_control = vmcs12->pin_based_vm_exec_control;
12031
12032         /* Preemption timer setting is computed directly in vmx_vcpu_run.  */
12033         exec_control |= vmcs_config.pin_based_exec_ctrl;
12034         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
12035         vmx->loaded_vmcs->hv_timer_armed = false;
12036
12037         /* Posted interrupts setting is only taken from vmcs12.  */
12038         if (nested_cpu_has_posted_intr(vmcs12)) {
12039                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
12040                 vmx->nested.pi_pending = false;
12041         } else {
12042                 exec_control &= ~PIN_BASED_POSTED_INTR;
12043         }
12044         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
12045
12046         /*
12047          * EXEC CONTROLS
12048          */
12049         exec_control = vmx_exec_control(vmx); /* L0's desires */
12050         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
12051         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
12052         exec_control &= ~CPU_BASED_TPR_SHADOW;
12053         exec_control |= vmcs12->cpu_based_vm_exec_control;
12054
12055         /*
12056          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
12057          * nested_get_vmcs12_pages can't fix it up, the illegal value
12058          * will result in a VM entry failure.
12059          */
12060         if (exec_control & CPU_BASED_TPR_SHADOW) {
12061                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
12062                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
12063         } else {
12064 #ifdef CONFIG_X86_64
12065                 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
12066                                 CPU_BASED_CR8_STORE_EXITING;
12067 #endif
12068         }
12069
12070         /*
12071          * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
12072          * for I/O port accesses.
12073          */
12074         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
12075         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
12076         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
12077
12078         /*
12079          * SECONDARY EXEC CONTROLS
12080          */
12081         if (cpu_has_secondary_exec_ctrls()) {
12082                 exec_control = vmx->secondary_exec_control;
12083
12084                 /* Take the following fields only from vmcs12 */
12085                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
12086                                   SECONDARY_EXEC_ENABLE_INVPCID |
12087                                   SECONDARY_EXEC_RDTSCP |
12088                                   SECONDARY_EXEC_XSAVES |
12089                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
12090                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
12091                                   SECONDARY_EXEC_ENABLE_VMFUNC);
12092                 if (nested_cpu_has(vmcs12,
12093                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
12094                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
12095                                 ~SECONDARY_EXEC_ENABLE_PML;
12096                         exec_control |= vmcs12_exec_ctrl;
12097                 }
12098
12099                 /* VMCS shadowing for L2 is emulated for now */
12100                 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
12101
12102                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
12103                         vmcs_write16(GUEST_INTR_STATUS,
12104                                 vmcs12->guest_intr_status);
12105
12106                 /*
12107                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
12108                  * nested_get_vmcs12_pages will either fix it up or
12109                  * remove the VM execution control.
12110                  */
12111                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
12112                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
12113
12114                 if (exec_control & SECONDARY_EXEC_ENCLS_EXITING)
12115                         vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
12116
12117                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
12118         }
12119
12120         /*
12121          * ENTRY CONTROLS
12122          *
12123          * vmcs12's VM_{ENTRY,EXIT}_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE
12124          * are emulated by vmx_set_efer() in prepare_vmcs02(), but speculate
12125          * on the related bits (if supported by the CPU) in the hope that
12126          * we can avoid VMWrites during vmx_set_efer().
12127          */
12128         exec_control = (vmcs12->vm_entry_controls | vmcs_config.vmentry_ctrl) &
12129                         ~VM_ENTRY_IA32E_MODE & ~VM_ENTRY_LOAD_IA32_EFER;
12130         if (cpu_has_load_ia32_efer) {
12131                 if (guest_efer & EFER_LMA)
12132                         exec_control |= VM_ENTRY_IA32E_MODE;
12133                 if (guest_efer != host_efer)
12134                         exec_control |= VM_ENTRY_LOAD_IA32_EFER;
12135         }
12136         vm_entry_controls_init(vmx, exec_control);
12137
12138         /*
12139          * EXIT CONTROLS
12140          *
12141          * L2->L1 exit controls are emulated - the hardware exit is to L0 so
12142          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
12143          * bits may be modified by vmx_set_efer() in prepare_vmcs02().
12144          */
12145         exec_control = vmcs_config.vmexit_ctrl;
12146         if (cpu_has_load_ia32_efer && guest_efer != host_efer)
12147                 exec_control |= VM_EXIT_LOAD_IA32_EFER;
12148         vm_exit_controls_init(vmx, exec_control);
12149
12150         /*
12151          * Conceptually we want to copy the PML address and index from
12152          * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
12153          * since we always flush the log on each vmexit and never change
12154          * the PML address (once set), this happens to be equivalent to
12155          * simply resetting the index in vmcs02.
12156          */
12157         if (enable_pml)
12158                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
12159
12160         /*
12161          * Interrupt/Exception Fields
12162          */
12163         if (vmx->nested.nested_run_pending) {
12164                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
12165                              vmcs12->vm_entry_intr_info_field);
12166                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
12167                              vmcs12->vm_entry_exception_error_code);
12168                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
12169                              vmcs12->vm_entry_instruction_len);
12170                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
12171                              vmcs12->guest_interruptibility_info);
12172                 vmx->loaded_vmcs->nmi_known_unmasked =
12173                         !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
12174         } else {
12175                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
12176         }
12177 }
12178
12179 static void prepare_vmcs02_full(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
12180 {
12181         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
12182         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
12183         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
12184         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
12185         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
12186         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
12187         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
12188         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
12189         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
12190         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
12191         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
12192         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
12193         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
12194         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
12195         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
12196         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
12197         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
12198         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
12199         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
12200         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
12201         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
12202         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
12203         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
12204         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
12205         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
12206         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
12207         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
12208         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
12209         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
12210         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
12211         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
12212
12213         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
12214         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
12215                 vmcs12->guest_pending_dbg_exceptions);
12216         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
12217         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
12218
12219         if (nested_cpu_has_xsaves(vmcs12))
12220                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
12221
12222         /*
12223          * Whether page-faults are trapped is determined by a combination of
12224          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
12225          * If enable_ept, L0 doesn't care about page faults and we should
12226          * set all of these to L1's desires. However, if !enable_ept, L0 does
12227          * care about (at least some) page faults, and because it is not easy
12228          * (if at all possible?) to merge L0 and L1's desires, we simply ask
12229          * to exit on each and every L2 page fault. This is done by setting
12230          * MASK=MATCH=0 and (see below) EB.PF=1.
12231          * Note that below we don't need special code to set EB.PF beyond the
12232          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
12233          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
12234          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
12235          */
12236         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
12237                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
12238         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
12239                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
12240
12241         if (cpu_has_vmx_apicv()) {
12242                 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
12243                 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
12244                 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
12245                 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
12246         }
12247
12248         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
12249         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
12250
12251         set_cr4_guest_host_mask(vmx);
12252
12253         if (kvm_mpx_supported()) {
12254                 if (vmx->nested.nested_run_pending &&
12255                         (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
12256                         vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
12257                 else
12258                         vmcs_write64(GUEST_BNDCFGS, vmx->nested.vmcs01_guest_bndcfgs);
12259         }
12260
12261         /*
12262          * L1 may access the L2's PDPTR, so save them to construct vmcs12
12263          */
12264         if (enable_ept) {
12265                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
12266                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
12267                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
12268                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
12269         }
12270 }
12271
12272 /*
12273  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
12274  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
12275  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
12276  * guest in a way that will both be appropriate to L1's requests, and our
12277  * needs. In addition to modifying the active vmcs (which is vmcs02), this
12278  * function also has additional necessary side-effects, like setting various
12279  * vcpu->arch fields.
12280  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
12281  * is assigned to entry_failure_code on failure.
12282  */
12283 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
12284                           u32 *entry_failure_code)
12285 {
12286         struct vcpu_vmx *vmx = to_vmx(vcpu);
12287
12288         if (vmx->nested.dirty_vmcs12) {
12289                 prepare_vmcs02_full(vmx, vmcs12);
12290                 vmx->nested.dirty_vmcs12 = false;
12291         }
12292
12293         /*
12294          * First, the fields that are shadowed.  This must be kept in sync
12295          * with vmx_shadow_fields.h.
12296          */
12297
12298         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
12299         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
12300         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
12301         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
12302         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
12303
12304         if (vmx->nested.nested_run_pending &&
12305             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
12306                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
12307                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
12308         } else {
12309                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
12310                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
12311         }
12312         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
12313
12314         vmx->nested.preemption_timer_expired = false;
12315         if (nested_cpu_has_preemption_timer(vmcs12))
12316                 vmx_start_preemption_timer(vcpu);
12317
12318         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
12319          * bitwise-or of what L1 wants to trap for L2, and what we want to
12320          * trap. Note that CR0.TS also needs updating - we do this later.
12321          */
12322         update_exception_bitmap(vcpu);
12323         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
12324         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
12325
12326         if (vmx->nested.nested_run_pending &&
12327             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
12328                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
12329                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
12330         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
12331                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
12332         }
12333
12334         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
12335
12336         if (kvm_has_tsc_control)
12337                 decache_tsc_multiplier(vmx);
12338
12339         if (enable_vpid) {
12340                 /*
12341                  * There is no direct mapping between vpid02 and vpid12, the
12342                  * vpid02 is per-vCPU for L0 and reused while the value of
12343                  * vpid12 is changed w/ one invvpid during nested vmentry.
12344                  * The vpid12 is allocated by L1 for L2, so it will not
12345                  * influence global bitmap(for vpid01 and vpid02 allocation)
12346                  * even if spawn a lot of nested vCPUs.
12347                  */
12348                 if (nested_cpu_has_vpid(vmcs12) && nested_has_guest_tlb_tag(vcpu)) {
12349                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
12350                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
12351                                 __vmx_flush_tlb(vcpu, nested_get_vpid02(vcpu), false);
12352                         }
12353                 } else {
12354                         /*
12355                          * If L1 use EPT, then L0 needs to execute INVEPT on
12356                          * EPTP02 instead of EPTP01. Therefore, delay TLB
12357                          * flush until vmcs02->eptp is fully updated by
12358                          * KVM_REQ_LOAD_CR3. Note that this assumes
12359                          * KVM_REQ_TLB_FLUSH is evaluated after
12360                          * KVM_REQ_LOAD_CR3 in vcpu_enter_guest().
12361                          */
12362                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
12363                 }
12364         }
12365
12366         if (nested_cpu_has_ept(vmcs12))
12367                 nested_ept_init_mmu_context(vcpu);
12368         else if (nested_cpu_has2(vmcs12,
12369                                  SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
12370                 vmx_flush_tlb(vcpu, true);
12371
12372         /*
12373          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
12374          * bits which we consider mandatory enabled.
12375          * The CR0_READ_SHADOW is what L2 should have expected to read given
12376          * the specifications by L1; It's not enough to take
12377          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
12378          * have more bits than L1 expected.
12379          */
12380         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
12381         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
12382
12383         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
12384         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
12385
12386         vcpu->arch.efer = nested_vmx_calc_efer(vmx, vmcs12);
12387         /* Note: may modify VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
12388         vmx_set_efer(vcpu, vcpu->arch.efer);
12389
12390         /*
12391          * Guest state is invalid and unrestricted guest is disabled,
12392          * which means L1 attempted VMEntry to L2 with invalid state.
12393          * Fail the VMEntry.
12394          */
12395         if (vmx->emulation_required) {
12396                 *entry_failure_code = ENTRY_FAIL_DEFAULT;
12397                 return 1;
12398         }
12399
12400         /* Shadow page tables on either EPT or shadow page tables. */
12401         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
12402                                 entry_failure_code))
12403                 return 1;
12404
12405         if (!enable_ept)
12406                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
12407
12408         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
12409         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
12410         return 0;
12411 }
12412
12413 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12)
12414 {
12415         if (!nested_cpu_has_nmi_exiting(vmcs12) &&
12416             nested_cpu_has_virtual_nmis(vmcs12))
12417                 return -EINVAL;
12418
12419         if (!nested_cpu_has_virtual_nmis(vmcs12) &&
12420             nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING))
12421                 return -EINVAL;
12422
12423         return 0;
12424 }
12425
12426 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12427 {
12428         struct vcpu_vmx *vmx = to_vmx(vcpu);
12429         bool ia32e;
12430
12431         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
12432             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
12433                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12434
12435         if (nested_cpu_has_vpid(vmcs12) && !vmcs12->virtual_processor_id)
12436                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12437
12438         if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
12439                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12440
12441         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
12442                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12443
12444         if (nested_vmx_check_apic_access_controls(vcpu, vmcs12))
12445                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12446
12447         if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
12448                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12449
12450         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
12451                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12452
12453         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
12454                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12455
12456         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
12457                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12458
12459         if (nested_vmx_check_shadow_vmcs_controls(vcpu, vmcs12))
12460                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12461
12462         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
12463                                 vmx->nested.msrs.procbased_ctls_low,
12464                                 vmx->nested.msrs.procbased_ctls_high) ||
12465             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
12466              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
12467                                  vmx->nested.msrs.secondary_ctls_low,
12468                                  vmx->nested.msrs.secondary_ctls_high)) ||
12469             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
12470                                 vmx->nested.msrs.pinbased_ctls_low,
12471                                 vmx->nested.msrs.pinbased_ctls_high) ||
12472             !vmx_control_verify(vmcs12->vm_exit_controls,
12473                                 vmx->nested.msrs.exit_ctls_low,
12474                                 vmx->nested.msrs.exit_ctls_high) ||
12475             !vmx_control_verify(vmcs12->vm_entry_controls,
12476                                 vmx->nested.msrs.entry_ctls_low,
12477                                 vmx->nested.msrs.entry_ctls_high))
12478                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12479
12480         if (nested_vmx_check_nmi_controls(vmcs12))
12481                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12482
12483         if (nested_cpu_has_vmfunc(vmcs12)) {
12484                 if (vmcs12->vm_function_control &
12485                     ~vmx->nested.msrs.vmfunc_controls)
12486                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12487
12488                 if (nested_cpu_has_eptp_switching(vmcs12)) {
12489                         if (!nested_cpu_has_ept(vmcs12) ||
12490                             !page_address_valid(vcpu, vmcs12->eptp_list_address))
12491                                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12492                 }
12493         }
12494
12495         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
12496                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12497
12498         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
12499             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
12500             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
12501                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
12502
12503         /*
12504          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
12505          * IA32_EFER MSR must be 0 in the field for that register. In addition,
12506          * the values of the LMA and LME bits in the field must each be that of
12507          * the host address-space size VM-exit control.
12508          */
12509         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
12510                 ia32e = (vmcs12->vm_exit_controls &
12511                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
12512                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
12513                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
12514                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
12515                         return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
12516         }
12517
12518         /*
12519          * From the Intel SDM, volume 3:
12520          * Fields relevant to VM-entry event injection must be set properly.
12521          * These fields are the VM-entry interruption-information field, the
12522          * VM-entry exception error code, and the VM-entry instruction length.
12523          */
12524         if (vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) {
12525                 u32 intr_info = vmcs12->vm_entry_intr_info_field;
12526                 u8 vector = intr_info & INTR_INFO_VECTOR_MASK;
12527                 u32 intr_type = intr_info & INTR_INFO_INTR_TYPE_MASK;
12528                 bool has_error_code = intr_info & INTR_INFO_DELIVER_CODE_MASK;
12529                 bool should_have_error_code;
12530                 bool urg = nested_cpu_has2(vmcs12,
12531                                            SECONDARY_EXEC_UNRESTRICTED_GUEST);
12532                 bool prot_mode = !urg || vmcs12->guest_cr0 & X86_CR0_PE;
12533
12534                 /* VM-entry interruption-info field: interruption type */
12535                 if (intr_type == INTR_TYPE_RESERVED ||
12536                     (intr_type == INTR_TYPE_OTHER_EVENT &&
12537                      !nested_cpu_supports_monitor_trap_flag(vcpu)))
12538                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12539
12540                 /* VM-entry interruption-info field: vector */
12541                 if ((intr_type == INTR_TYPE_NMI_INTR && vector != NMI_VECTOR) ||
12542                     (intr_type == INTR_TYPE_HARD_EXCEPTION && vector > 31) ||
12543                     (intr_type == INTR_TYPE_OTHER_EVENT && vector != 0))
12544                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12545
12546                 /* VM-entry interruption-info field: deliver error code */
12547                 should_have_error_code =
12548                         intr_type == INTR_TYPE_HARD_EXCEPTION && prot_mode &&
12549                         x86_exception_has_error_code(vector);
12550                 if (has_error_code != should_have_error_code)
12551                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12552
12553                 /* VM-entry exception error code */
12554                 if (has_error_code &&
12555                     vmcs12->vm_entry_exception_error_code & GENMASK(31, 15))
12556                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12557
12558                 /* VM-entry interruption-info field: reserved bits */
12559                 if (intr_info & INTR_INFO_RESVD_BITS_MASK)
12560                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12561
12562                 /* VM-entry instruction length */
12563                 switch (intr_type) {
12564                 case INTR_TYPE_SOFT_EXCEPTION:
12565                 case INTR_TYPE_SOFT_INTR:
12566                 case INTR_TYPE_PRIV_SW_EXCEPTION:
12567                         if ((vmcs12->vm_entry_instruction_len > 15) ||
12568                             (vmcs12->vm_entry_instruction_len == 0 &&
12569                              !nested_cpu_has_zero_length_injection(vcpu)))
12570                                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12571                 }
12572         }
12573
12574         if (nested_cpu_has_ept(vmcs12) &&
12575             !valid_ept_address(vcpu, vmcs12->ept_pointer))
12576                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
12577
12578         return 0;
12579 }
12580
12581 static int nested_vmx_check_vmcs_link_ptr(struct kvm_vcpu *vcpu,
12582                                           struct vmcs12 *vmcs12)
12583 {
12584         int r;
12585         struct page *page;
12586         struct vmcs12 *shadow;
12587
12588         if (vmcs12->vmcs_link_pointer == -1ull)
12589                 return 0;
12590
12591         if (!page_address_valid(vcpu, vmcs12->vmcs_link_pointer))
12592                 return -EINVAL;
12593
12594         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->vmcs_link_pointer);
12595         if (is_error_page(page))
12596                 return -EINVAL;
12597
12598         r = 0;
12599         shadow = kmap(page);
12600         if (shadow->hdr.revision_id != VMCS12_REVISION ||
12601             shadow->hdr.shadow_vmcs != nested_cpu_has_shadow_vmcs(vmcs12))
12602                 r = -EINVAL;
12603         kunmap(page);
12604         kvm_release_page_clean(page);
12605         return r;
12606 }
12607
12608 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
12609                                   u32 *exit_qual)
12610 {
12611         bool ia32e;
12612
12613         *exit_qual = ENTRY_FAIL_DEFAULT;
12614
12615         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
12616             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
12617                 return 1;
12618
12619         if (nested_vmx_check_vmcs_link_ptr(vcpu, vmcs12)) {
12620                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
12621                 return 1;
12622         }
12623
12624         /*
12625          * If the load IA32_EFER VM-entry control is 1, the following checks
12626          * are performed on the field for the IA32_EFER MSR:
12627          * - Bits reserved in the IA32_EFER MSR must be 0.
12628          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
12629          *   the IA-32e mode guest VM-exit control. It must also be identical
12630          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
12631          *   CR0.PG) is 1.
12632          */
12633         if (to_vmx(vcpu)->nested.nested_run_pending &&
12634             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
12635                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
12636                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
12637                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
12638                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
12639                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
12640                         return 1;
12641         }
12642
12643         if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
12644                 (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) ||
12645                 (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))
12646                         return 1;
12647
12648         return 0;
12649 }
12650
12651 static int __noclone nested_vmx_check_vmentry_hw(struct kvm_vcpu *vcpu)
12652 {
12653         struct vcpu_vmx *vmx = to_vmx(vcpu);
12654         unsigned long cr3, cr4;
12655
12656         if (!nested_early_check)
12657                 return 0;
12658
12659         if (vmx->msr_autoload.host.nr)
12660                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
12661         if (vmx->msr_autoload.guest.nr)
12662                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
12663
12664         preempt_disable();
12665
12666         vmx_prepare_switch_to_guest(vcpu);
12667
12668         /*
12669          * Induce a consistency check VMExit by clearing bit 1 in GUEST_RFLAGS,
12670          * which is reserved to '1' by hardware.  GUEST_RFLAGS is guaranteed to
12671          * be written (by preparve_vmcs02()) before the "real" VMEnter, i.e.
12672          * there is no need to preserve other bits or save/restore the field.
12673          */
12674         vmcs_writel(GUEST_RFLAGS, 0);
12675
12676         vmcs_writel(HOST_RIP, vmx_early_consistency_check_return);
12677
12678         cr3 = __get_current_cr3_fast();
12679         if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
12680                 vmcs_writel(HOST_CR3, cr3);
12681                 vmx->loaded_vmcs->host_state.cr3 = cr3;
12682         }
12683
12684         cr4 = cr4_read_shadow();
12685         if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
12686                 vmcs_writel(HOST_CR4, cr4);
12687                 vmx->loaded_vmcs->host_state.cr4 = cr4;
12688         }
12689
12690         vmx->__launched = vmx->loaded_vmcs->launched;
12691
12692         asm(
12693                 /* Set HOST_RSP */
12694                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
12695                 "mov %%" _ASM_SP ", %c[host_rsp](%0)\n\t"
12696
12697                 /* Check if vmlaunch of vmresume is needed */
12698                 "cmpl $0, %c[launched](%0)\n\t"
12699                 "je 1f\n\t"
12700                 __ex(ASM_VMX_VMRESUME) "\n\t"
12701                 "jmp 2f\n\t"
12702                 "1: " __ex(ASM_VMX_VMLAUNCH) "\n\t"
12703                 "jmp 2f\n\t"
12704                 "2: "
12705
12706                 /* Set vmx->fail accordingly */
12707                 "setbe %c[fail](%0)\n\t"
12708
12709                 ".pushsection .rodata\n\t"
12710                 ".global vmx_early_consistency_check_return\n\t"
12711                 "vmx_early_consistency_check_return: " _ASM_PTR " 2b\n\t"
12712                 ".popsection"
12713               :
12714               : "c"(vmx), "d"((unsigned long)HOST_RSP),
12715                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
12716                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
12717                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp))
12718               : "rax", "cc", "memory"
12719         );
12720
12721         vmcs_writel(HOST_RIP, vmx_return);
12722
12723         preempt_enable();
12724
12725         if (vmx->msr_autoload.host.nr)
12726                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
12727         if (vmx->msr_autoload.guest.nr)
12728                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
12729
12730         if (vmx->fail) {
12731                 WARN_ON_ONCE(vmcs_read32(VM_INSTRUCTION_ERROR) !=
12732                              VMXERR_ENTRY_INVALID_CONTROL_FIELD);
12733                 vmx->fail = 0;
12734                 return 1;
12735         }
12736
12737         /*
12738          * VMExit clears RFLAGS.IF and DR7, even on a consistency check.
12739          */
12740         local_irq_enable();
12741         if (hw_breakpoint_active())
12742                 set_debugreg(__this_cpu_read(cpu_dr7), 7);
12743
12744         /*
12745          * A non-failing VMEntry means we somehow entered guest mode with
12746          * an illegal RIP, and that's just the tip of the iceberg.  There
12747          * is no telling what memory has been modified or what state has
12748          * been exposed to unknown code.  Hitting this all but guarantees
12749          * a (very critical) hardware issue.
12750          */
12751         WARN_ON(!(vmcs_read32(VM_EXIT_REASON) &
12752                 VMX_EXIT_REASONS_FAILED_VMENTRY));
12753
12754         return 0;
12755 }
12756 STACK_FRAME_NON_STANDARD(nested_vmx_check_vmentry_hw);
12757
12758 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
12759                                    struct vmcs12 *vmcs12);
12760
12761 /*
12762  * If from_vmentry is false, this is being called from state restore (either RSM
12763  * or KVM_SET_NESTED_STATE).  Otherwise it's called from vmlaunch/vmresume.
12764 + *
12765 + * Returns:
12766 + *   0 - success, i.e. proceed with actual VMEnter
12767 + *   1 - consistency check VMExit
12768 + *  -1 - consistency check VMFail
12769  */
12770 static int nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,
12771                                           bool from_vmentry)
12772 {
12773         struct vcpu_vmx *vmx = to_vmx(vcpu);
12774         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12775         bool evaluate_pending_interrupts;
12776         u32 exit_reason = EXIT_REASON_INVALID_STATE;
12777         u32 exit_qual;
12778
12779         evaluate_pending_interrupts = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
12780                 (CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_VIRTUAL_NMI_PENDING);
12781         if (likely(!evaluate_pending_interrupts) && kvm_vcpu_apicv_active(vcpu))
12782                 evaluate_pending_interrupts |= vmx_has_apicv_interrupt(vcpu);
12783
12784         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
12785                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
12786         if (kvm_mpx_supported() &&
12787                 !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
12788                 vmx->nested.vmcs01_guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
12789
12790         vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
12791
12792         prepare_vmcs02_early(vmx, vmcs12);
12793
12794         if (from_vmentry) {
12795                 nested_get_vmcs12_pages(vcpu);
12796
12797                 if (nested_vmx_check_vmentry_hw(vcpu)) {
12798                         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
12799                         return -1;
12800                 }
12801
12802                 if (check_vmentry_postreqs(vcpu, vmcs12, &exit_qual))
12803                         goto vmentry_fail_vmexit;
12804         }
12805
12806         enter_guest_mode(vcpu);
12807         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
12808                 vcpu->arch.tsc_offset += vmcs12->tsc_offset;
12809
12810         if (prepare_vmcs02(vcpu, vmcs12, &exit_qual))
12811                 goto vmentry_fail_vmexit_guest_mode;
12812
12813         if (from_vmentry) {
12814                 exit_reason = EXIT_REASON_MSR_LOAD_FAIL;
12815                 exit_qual = nested_vmx_load_msr(vcpu,
12816                                                 vmcs12->vm_entry_msr_load_addr,
12817                                                 vmcs12->vm_entry_msr_load_count);
12818                 if (exit_qual)
12819                         goto vmentry_fail_vmexit_guest_mode;
12820         } else {
12821                 /*
12822                  * The MMU is not initialized to point at the right entities yet and
12823                  * "get pages" would need to read data from the guest (i.e. we will
12824                  * need to perform gpa to hpa translation). Request a call
12825                  * to nested_get_vmcs12_pages before the next VM-entry.  The MSRs
12826                  * have already been set at vmentry time and should not be reset.
12827                  */
12828                 kvm_make_request(KVM_REQ_GET_VMCS12_PAGES, vcpu);
12829         }
12830
12831         /*
12832          * If L1 had a pending IRQ/NMI until it executed
12833          * VMLAUNCH/VMRESUME which wasn't delivered because it was
12834          * disallowed (e.g. interrupts disabled), L0 needs to
12835          * evaluate if this pending event should cause an exit from L2
12836          * to L1 or delivered directly to L2 (e.g. In case L1 don't
12837          * intercept EXTERNAL_INTERRUPT).
12838          *
12839          * Usually this would be handled by the processor noticing an
12840          * IRQ/NMI window request, or checking RVI during evaluation of
12841          * pending virtual interrupts.  However, this setting was done
12842          * on VMCS01 and now VMCS02 is active instead. Thus, we force L0
12843          * to perform pending event evaluation by requesting a KVM_REQ_EVENT.
12844          */
12845         if (unlikely(evaluate_pending_interrupts))
12846                 kvm_make_request(KVM_REQ_EVENT, vcpu);
12847
12848         /*
12849          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
12850          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
12851          * returned as far as L1 is concerned. It will only return (and set
12852          * the success flag) when L2 exits (see nested_vmx_vmexit()).
12853          */
12854         return 0;
12855
12856         /*
12857          * A failed consistency check that leads to a VMExit during L1's
12858          * VMEnter to L2 is a variation of a normal VMexit, as explained in
12859          * 26.7 "VM-entry failures during or after loading guest state".
12860          */
12861 vmentry_fail_vmexit_guest_mode:
12862         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
12863                 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
12864         leave_guest_mode(vcpu);
12865
12866 vmentry_fail_vmexit:
12867         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
12868
12869         if (!from_vmentry)
12870                 return 1;
12871
12872         load_vmcs12_host_state(vcpu, vmcs12);
12873         vmcs12->vm_exit_reason = exit_reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
12874         vmcs12->exit_qualification = exit_qual;
12875         if (enable_shadow_vmcs)
12876                 vmx->nested.sync_shadow_vmcs = true;
12877         return 1;
12878 }
12879
12880 /*
12881  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
12882  * for running an L2 nested guest.
12883  */
12884 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
12885 {
12886         struct vmcs12 *vmcs12;
12887         struct vcpu_vmx *vmx = to_vmx(vcpu);
12888         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
12889         int ret;
12890
12891         if (!nested_vmx_check_permission(vcpu))
12892                 return 1;
12893
12894         if (vmx->nested.current_vmptr == -1ull)
12895                 return nested_vmx_failInvalid(vcpu);
12896
12897         vmcs12 = get_vmcs12(vcpu);
12898
12899         /*
12900          * Can't VMLAUNCH or VMRESUME a shadow VMCS. Despite the fact
12901          * that there *is* a valid VMCS pointer, RFLAGS.CF is set
12902          * rather than RFLAGS.ZF, and no error number is stored to the
12903          * VM-instruction error field.
12904          */
12905         if (vmcs12->hdr.shadow_vmcs)
12906                 return nested_vmx_failInvalid(vcpu);
12907
12908         if (enable_shadow_vmcs)
12909                 copy_shadow_to_vmcs12(vmx);
12910
12911         /*
12912          * The nested entry process starts with enforcing various prerequisites
12913          * on vmcs12 as required by the Intel SDM, and act appropriately when
12914          * they fail: As the SDM explains, some conditions should cause the
12915          * instruction to fail, while others will cause the instruction to seem
12916          * to succeed, but return an EXIT_REASON_INVALID_STATE.
12917          * To speed up the normal (success) code path, we should avoid checking
12918          * for misconfigurations which will anyway be caught by the processor
12919          * when using the merged vmcs02.
12920          */
12921         if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS)
12922                 return nested_vmx_failValid(vcpu,
12923                         VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
12924
12925         if (vmcs12->launch_state == launch)
12926                 return nested_vmx_failValid(vcpu,
12927                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
12928                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
12929
12930         ret = check_vmentry_prereqs(vcpu, vmcs12);
12931         if (ret)
12932                 return nested_vmx_failValid(vcpu, ret);
12933
12934         /*
12935          * We're finally done with prerequisite checking, and can start with
12936          * the nested entry.
12937          */
12938         vmx->nested.nested_run_pending = 1;
12939         ret = nested_vmx_enter_non_root_mode(vcpu, true);
12940         vmx->nested.nested_run_pending = !ret;
12941         if (ret > 0)
12942                 return 1;
12943         else if (ret)
12944                 return nested_vmx_failValid(vcpu,
12945                         VMXERR_ENTRY_INVALID_CONTROL_FIELD);
12946
12947         /* Hide L1D cache contents from the nested guest.  */
12948         vmx->vcpu.arch.l1tf_flush_l1d = true;
12949
12950         /*
12951          * Must happen outside of nested_vmx_enter_non_root_mode() as it will
12952          * also be used as part of restoring nVMX state for
12953          * snapshot restore (migration).
12954          *
12955          * In this flow, it is assumed that vmcs12 cache was
12956          * trasferred as part of captured nVMX state and should
12957          * therefore not be read from guest memory (which may not
12958          * exist on destination host yet).
12959          */
12960         nested_cache_shadow_vmcs12(vcpu, vmcs12);
12961
12962         /*
12963          * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken
12964          * by event injection, halt vcpu.
12965          */
12966         if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) &&
12967             !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK)) {
12968                 vmx->nested.nested_run_pending = 0;
12969                 return kvm_vcpu_halt(vcpu);
12970         }
12971         return 1;
12972 }
12973
12974 /*
12975  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
12976  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
12977  * This function returns the new value we should put in vmcs12.guest_cr0.
12978  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
12979  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
12980  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
12981  *     didn't trap the bit, because if L1 did, so would L0).
12982  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
12983  *     been modified by L2, and L1 knows it. So just leave the old value of
12984  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
12985  *     isn't relevant, because if L0 traps this bit it can set it to anything.
12986  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
12987  *     changed these bits, and therefore they need to be updated, but L0
12988  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
12989  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
12990  */
12991 static inline unsigned long
12992 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12993 {
12994         return
12995         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
12996         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
12997         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
12998                         vcpu->arch.cr0_guest_owned_bits));
12999 }
13000
13001 static inline unsigned long
13002 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
13003 {
13004         return
13005         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
13006         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
13007         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
13008                         vcpu->arch.cr4_guest_owned_bits));
13009 }
13010
13011 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
13012                                        struct vmcs12 *vmcs12)
13013 {
13014         u32 idt_vectoring;
13015         unsigned int nr;
13016
13017         if (vcpu->arch.exception.injected) {
13018                 nr = vcpu->arch.exception.nr;
13019                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
13020
13021                 if (kvm_exception_is_soft(nr)) {
13022                         vmcs12->vm_exit_instruction_len =
13023                                 vcpu->arch.event_exit_inst_len;
13024                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
13025                 } else
13026                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
13027
13028                 if (vcpu->arch.exception.has_error_code) {
13029                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
13030                         vmcs12->idt_vectoring_error_code =
13031                                 vcpu->arch.exception.error_code;
13032                 }
13033
13034                 vmcs12->idt_vectoring_info_field = idt_vectoring;
13035         } else if (vcpu->arch.nmi_injected) {
13036                 vmcs12->idt_vectoring_info_field =
13037                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
13038         } else if (vcpu->arch.interrupt.injected) {
13039                 nr = vcpu->arch.interrupt.nr;
13040                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
13041
13042                 if (vcpu->arch.interrupt.soft) {
13043                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
13044                         vmcs12->vm_entry_instruction_len =
13045                                 vcpu->arch.event_exit_inst_len;
13046                 } else
13047                         idt_vectoring |= INTR_TYPE_EXT_INTR;
13048
13049                 vmcs12->idt_vectoring_info_field = idt_vectoring;
13050         }
13051 }
13052
13053 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
13054 {
13055         struct vcpu_vmx *vmx = to_vmx(vcpu);
13056         unsigned long exit_qual;
13057         bool block_nested_events =
13058             vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
13059
13060         if (vcpu->arch.exception.pending &&
13061                 nested_vmx_check_exception(vcpu, &exit_qual)) {
13062                 if (block_nested_events)
13063                         return -EBUSY;
13064                 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
13065                 return 0;
13066         }
13067
13068         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
13069             vmx->nested.preemption_timer_expired) {
13070                 if (block_nested_events)
13071                         return -EBUSY;
13072                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
13073                 return 0;
13074         }
13075
13076         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
13077                 if (block_nested_events)
13078                         return -EBUSY;
13079                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
13080                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
13081                                   INTR_INFO_VALID_MASK, 0);
13082                 /*
13083                  * The NMI-triggered VM exit counts as injection:
13084                  * clear this one and block further NMIs.
13085                  */
13086                 vcpu->arch.nmi_pending = 0;
13087                 vmx_set_nmi_mask(vcpu, true);
13088                 return 0;
13089         }
13090
13091         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
13092             nested_exit_on_intr(vcpu)) {
13093                 if (block_nested_events)
13094                         return -EBUSY;
13095                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
13096                 return 0;
13097         }
13098
13099         vmx_complete_nested_posted_interrupt(vcpu);
13100         return 0;
13101 }
13102
13103 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
13104 {
13105         to_vmx(vcpu)->req_immediate_exit = true;
13106 }
13107
13108 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
13109 {
13110         ktime_t remaining =
13111                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
13112         u64 value;
13113
13114         if (ktime_to_ns(remaining) <= 0)
13115                 return 0;
13116
13117         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
13118         do_div(value, 1000000);
13119         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
13120 }
13121
13122 /*
13123  * Update the guest state fields of vmcs12 to reflect changes that
13124  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
13125  * VM-entry controls is also updated, since this is really a guest
13126  * state bit.)
13127  */
13128 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
13129 {
13130         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
13131         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
13132
13133         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
13134         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
13135         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
13136
13137         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
13138         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
13139         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
13140         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
13141         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
13142         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
13143         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
13144         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
13145         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
13146         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
13147         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
13148         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
13149         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
13150         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
13151         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
13152         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
13153         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
13154         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
13155         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
13156         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
13157         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
13158         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
13159         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
13160         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
13161         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
13162         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
13163         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
13164         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
13165         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
13166         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
13167         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
13168         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
13169         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
13170         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
13171         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
13172         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
13173
13174         vmcs12->guest_interruptibility_info =
13175                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
13176         vmcs12->guest_pending_dbg_exceptions =
13177                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
13178         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
13179                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
13180         else
13181                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
13182
13183         if (nested_cpu_has_preemption_timer(vmcs12)) {
13184                 if (vmcs12->vm_exit_controls &
13185                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
13186                         vmcs12->vmx_preemption_timer_value =
13187                                 vmx_get_preemption_timer_value(vcpu);
13188                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
13189         }
13190
13191         /*
13192          * In some cases (usually, nested EPT), L2 is allowed to change its
13193          * own CR3 without exiting. If it has changed it, we must keep it.
13194          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
13195          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
13196          *
13197          * Additionally, restore L2's PDPTR to vmcs12.
13198          */
13199         if (enable_ept) {
13200                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
13201                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
13202                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
13203                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
13204                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
13205         }
13206
13207         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
13208
13209         if (nested_cpu_has_vid(vmcs12))
13210                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
13211
13212         vmcs12->vm_entry_controls =
13213                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
13214                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
13215
13216         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
13217                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
13218                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
13219         }
13220
13221         /* TODO: These cannot have changed unless we have MSR bitmaps and
13222          * the relevant bit asks not to trap the change */
13223         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
13224                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
13225         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
13226                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
13227         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
13228         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
13229         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
13230         if (kvm_mpx_supported())
13231                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
13232 }
13233
13234 /*
13235  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
13236  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
13237  * and this function updates it to reflect the changes to the guest state while
13238  * L2 was running (and perhaps made some exits which were handled directly by L0
13239  * without going back to L1), and to reflect the exit reason.
13240  * Note that we do not have to copy here all VMCS fields, just those that
13241  * could have changed by the L2 guest or the exit - i.e., the guest-state and
13242  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
13243  * which already writes to vmcs12 directly.
13244  */
13245 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
13246                            u32 exit_reason, u32 exit_intr_info,
13247                            unsigned long exit_qualification)
13248 {
13249         /* update guest state fields: */
13250         sync_vmcs12(vcpu, vmcs12);
13251
13252         /* update exit information fields: */
13253
13254         vmcs12->vm_exit_reason = exit_reason;
13255         vmcs12->exit_qualification = exit_qualification;
13256         vmcs12->vm_exit_intr_info = exit_intr_info;
13257
13258         vmcs12->idt_vectoring_info_field = 0;
13259         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
13260         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
13261
13262         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
13263                 vmcs12->launch_state = 1;
13264
13265                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
13266                  * instead of reading the real value. */
13267                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
13268
13269                 /*
13270                  * Transfer the event that L0 or L1 may wanted to inject into
13271                  * L2 to IDT_VECTORING_INFO_FIELD.
13272                  */
13273                 vmcs12_save_pending_event(vcpu, vmcs12);
13274         }
13275
13276         /*
13277          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
13278          * preserved above and would only end up incorrectly in L1.
13279          */
13280         vcpu->arch.nmi_injected = false;
13281         kvm_clear_exception_queue(vcpu);
13282         kvm_clear_interrupt_queue(vcpu);
13283 }
13284
13285 /*
13286  * A part of what we need to when the nested L2 guest exits and we want to
13287  * run its L1 parent, is to reset L1's guest state to the host state specified
13288  * in vmcs12.
13289  * This function is to be called not only on normal nested exit, but also on
13290  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
13291  * Failures During or After Loading Guest State").
13292  * This function should be called when the active VMCS is L1's (vmcs01).
13293  */
13294 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
13295                                    struct vmcs12 *vmcs12)
13296 {
13297         struct kvm_segment seg;
13298         u32 entry_failure_code;
13299
13300         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
13301                 vcpu->arch.efer = vmcs12->host_ia32_efer;
13302         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
13303                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
13304         else
13305                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
13306         vmx_set_efer(vcpu, vcpu->arch.efer);
13307
13308         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
13309         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
13310         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
13311         vmx_set_interrupt_shadow(vcpu, 0);
13312
13313         /*
13314          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
13315          * actually changed, because vmx_set_cr0 refers to efer set above.
13316          *
13317          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
13318          * (KVM doesn't change it);
13319          */
13320         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
13321         vmx_set_cr0(vcpu, vmcs12->host_cr0);
13322
13323         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
13324         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
13325         vmx_set_cr4(vcpu, vmcs12->host_cr4);
13326
13327         nested_ept_uninit_mmu_context(vcpu);
13328
13329         /*
13330          * Only PDPTE load can fail as the value of cr3 was checked on entry and
13331          * couldn't have changed.
13332          */
13333         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
13334                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
13335
13336         if (!enable_ept)
13337                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
13338
13339         /*
13340          * If vmcs01 doesn't use VPID, CPU flushes TLB on every
13341          * VMEntry/VMExit. Thus, no need to flush TLB.
13342          *
13343          * If vmcs12 doesn't use VPID, L1 expects TLB to be
13344          * flushed on every VMEntry/VMExit.
13345          *
13346          * Otherwise, we can preserve TLB entries as long as we are
13347          * able to tag L1 TLB entries differently than L2 TLB entries.
13348          *
13349          * If vmcs12 uses EPT, we need to execute this flush on EPTP01
13350          * and therefore we request the TLB flush to happen only after VMCS EPTP
13351          * has been set by KVM_REQ_LOAD_CR3.
13352          */
13353         if (enable_vpid &&
13354             (!nested_cpu_has_vpid(vmcs12) || !nested_has_guest_tlb_tag(vcpu))) {
13355                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
13356         }
13357
13358         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
13359         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
13360         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
13361         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
13362         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
13363         vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
13364         vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
13365
13366         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
13367         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
13368                 vmcs_write64(GUEST_BNDCFGS, 0);
13369
13370         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
13371                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
13372                 vcpu->arch.pat = vmcs12->host_ia32_pat;
13373         }
13374         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
13375                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
13376                         vmcs12->host_ia32_perf_global_ctrl);
13377
13378         /* Set L1 segment info according to Intel SDM
13379             27.5.2 Loading Host Segment and Descriptor-Table Registers */
13380         seg = (struct kvm_segment) {
13381                 .base = 0,
13382                 .limit = 0xFFFFFFFF,
13383                 .selector = vmcs12->host_cs_selector,
13384                 .type = 11,
13385                 .present = 1,
13386                 .s = 1,
13387                 .g = 1
13388         };
13389         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
13390                 seg.l = 1;
13391         else
13392                 seg.db = 1;
13393         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
13394         seg = (struct kvm_segment) {
13395                 .base = 0,
13396                 .limit = 0xFFFFFFFF,
13397                 .type = 3,
13398                 .present = 1,
13399                 .s = 1,
13400                 .db = 1,
13401                 .g = 1
13402         };
13403         seg.selector = vmcs12->host_ds_selector;
13404         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
13405         seg.selector = vmcs12->host_es_selector;
13406         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
13407         seg.selector = vmcs12->host_ss_selector;
13408         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
13409         seg.selector = vmcs12->host_fs_selector;
13410         seg.base = vmcs12->host_fs_base;
13411         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
13412         seg.selector = vmcs12->host_gs_selector;
13413         seg.base = vmcs12->host_gs_base;
13414         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
13415         seg = (struct kvm_segment) {
13416                 .base = vmcs12->host_tr_base,
13417                 .limit = 0x67,
13418                 .selector = vmcs12->host_tr_selector,
13419                 .type = 11,
13420                 .present = 1
13421         };
13422         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
13423
13424         kvm_set_dr(vcpu, 7, 0x400);
13425         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
13426
13427         if (cpu_has_vmx_msr_bitmap())
13428                 vmx_update_msr_bitmap(vcpu);
13429
13430         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
13431                                 vmcs12->vm_exit_msr_load_count))
13432                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
13433 }
13434
13435 static inline u64 nested_vmx_get_vmcs01_guest_efer(struct vcpu_vmx *vmx)
13436 {
13437         struct shared_msr_entry *efer_msr;
13438         unsigned int i;
13439
13440         if (vm_entry_controls_get(vmx) & VM_ENTRY_LOAD_IA32_EFER)
13441                 return vmcs_read64(GUEST_IA32_EFER);
13442
13443         if (cpu_has_load_ia32_efer)
13444                 return host_efer;
13445
13446         for (i = 0; i < vmx->msr_autoload.guest.nr; ++i) {
13447                 if (vmx->msr_autoload.guest.val[i].index == MSR_EFER)
13448                         return vmx->msr_autoload.guest.val[i].value;
13449         }
13450
13451         efer_msr = find_msr_entry(vmx, MSR_EFER);
13452         if (efer_msr)
13453                 return efer_msr->data;
13454
13455         return host_efer;
13456 }
13457
13458 static void nested_vmx_restore_host_state(struct kvm_vcpu *vcpu)
13459 {
13460         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
13461         struct vcpu_vmx *vmx = to_vmx(vcpu);
13462         struct vmx_msr_entry g, h;
13463         struct msr_data msr;
13464         gpa_t gpa;
13465         u32 i, j;
13466
13467         vcpu->arch.pat = vmcs_read64(GUEST_IA32_PAT);
13468
13469         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
13470                 /*
13471                  * L1's host DR7 is lost if KVM_GUESTDBG_USE_HW_BP is set
13472                  * as vmcs01.GUEST_DR7 contains a userspace defined value
13473                  * and vcpu->arch.dr7 is not squirreled away before the
13474                  * nested VMENTER (not worth adding a variable in nested_vmx).
13475                  */
13476                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
13477                         kvm_set_dr(vcpu, 7, DR7_FIXED_1);
13478                 else
13479                         WARN_ON(kvm_set_dr(vcpu, 7, vmcs_readl(GUEST_DR7)));
13480         }
13481
13482         /*
13483          * Note that calling vmx_set_{efer,cr0,cr4} is important as they
13484          * handle a variety of side effects to KVM's software model.
13485          */
13486         vmx_set_efer(vcpu, nested_vmx_get_vmcs01_guest_efer(vmx));
13487
13488         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
13489         vmx_set_cr0(vcpu, vmcs_readl(CR0_READ_SHADOW));
13490
13491         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
13492         vmx_set_cr4(vcpu, vmcs_readl(CR4_READ_SHADOW));
13493
13494         nested_ept_uninit_mmu_context(vcpu);
13495         vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
13496         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
13497
13498         /*
13499          * Use ept_save_pdptrs(vcpu) to load the MMU's cached PDPTRs
13500          * from vmcs01 (if necessary).  The PDPTRs are not loaded on
13501          * VMFail, like everything else we just need to ensure our
13502          * software model is up-to-date.
13503          */
13504         ept_save_pdptrs(vcpu);
13505
13506         kvm_mmu_reset_context(vcpu);
13507
13508         if (cpu_has_vmx_msr_bitmap())
13509                 vmx_update_msr_bitmap(vcpu);
13510
13511         /*
13512          * This nasty bit of open coding is a compromise between blindly
13513          * loading L1's MSRs using the exit load lists (incorrect emulation
13514          * of VMFail), leaving the nested VM's MSRs in the software model
13515          * (incorrect behavior) and snapshotting the modified MSRs (too
13516          * expensive since the lists are unbound by hardware).  For each
13517          * MSR that was (prematurely) loaded from the nested VMEntry load
13518          * list, reload it from the exit load list if it exists and differs
13519          * from the guest value.  The intent is to stuff host state as
13520          * silently as possible, not to fully process the exit load list.
13521          */
13522         msr.host_initiated = false;
13523         for (i = 0; i < vmcs12->vm_entry_msr_load_count; i++) {
13524                 gpa = vmcs12->vm_entry_msr_load_addr + (i * sizeof(g));
13525                 if (kvm_vcpu_read_guest(vcpu, gpa, &g, sizeof(g))) {
13526                         pr_debug_ratelimited(
13527                                 "%s read MSR index failed (%u, 0x%08llx)\n",
13528                                 __func__, i, gpa);
13529                         goto vmabort;
13530                 }
13531
13532                 for (j = 0; j < vmcs12->vm_exit_msr_load_count; j++) {
13533                         gpa = vmcs12->vm_exit_msr_load_addr + (j * sizeof(h));
13534                         if (kvm_vcpu_read_guest(vcpu, gpa, &h, sizeof(h))) {
13535                                 pr_debug_ratelimited(
13536                                         "%s read MSR failed (%u, 0x%08llx)\n",
13537                                         __func__, j, gpa);
13538                                 goto vmabort;
13539                         }
13540                         if (h.index != g.index)
13541                                 continue;
13542                         if (h.value == g.value)
13543                                 break;
13544
13545                         if (nested_vmx_load_msr_check(vcpu, &h)) {
13546                                 pr_debug_ratelimited(
13547                                         "%s check failed (%u, 0x%x, 0x%x)\n",
13548                                         __func__, j, h.index, h.reserved);
13549                                 goto vmabort;
13550                         }
13551
13552                         msr.index = h.index;
13553                         msr.data = h.value;
13554                         if (kvm_set_msr(vcpu, &msr)) {
13555                                 pr_debug_ratelimited(
13556                                         "%s WRMSR failed (%u, 0x%x, 0x%llx)\n",
13557                                         __func__, j, h.index, h.value);
13558                                 goto vmabort;
13559                         }
13560                 }
13561         }
13562
13563         return;
13564
13565 vmabort:
13566         nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
13567 }
13568
13569 /*
13570  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
13571  * and modify vmcs12 to make it see what it would expect to see there if
13572  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
13573  */
13574 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
13575                               u32 exit_intr_info,
13576                               unsigned long exit_qualification)
13577 {
13578         struct vcpu_vmx *vmx = to_vmx(vcpu);
13579         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
13580
13581         /* trying to cancel vmlaunch/vmresume is a bug */
13582         WARN_ON_ONCE(vmx->nested.nested_run_pending);
13583
13584         /*
13585          * The only expected VM-instruction error is "VM entry with
13586          * invalid control field(s)." Anything else indicates a
13587          * problem with L0.
13588          */
13589         WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
13590                                    VMXERR_ENTRY_INVALID_CONTROL_FIELD));
13591
13592         leave_guest_mode(vcpu);
13593
13594         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
13595                 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
13596
13597         if (likely(!vmx->fail)) {
13598                 if (exit_reason == -1)
13599                         sync_vmcs12(vcpu, vmcs12);
13600                 else
13601                         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
13602                                        exit_qualification);
13603
13604                 /*
13605                  * Must happen outside of sync_vmcs12() as it will
13606                  * also be used to capture vmcs12 cache as part of
13607                  * capturing nVMX state for snapshot (migration).
13608                  *
13609                  * Otherwise, this flush will dirty guest memory at a
13610                  * point it is already assumed by user-space to be
13611                  * immutable.
13612                  */
13613                 nested_flush_cached_shadow_vmcs12(vcpu, vmcs12);
13614
13615                 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
13616                                          vmcs12->vm_exit_msr_store_count))
13617                         nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
13618         }
13619
13620         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
13621
13622         /* Update any VMCS fields that might have changed while L2 ran */
13623         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
13624         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
13625         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
13626
13627         if (kvm_has_tsc_control)
13628                 decache_tsc_multiplier(vmx);
13629
13630         if (vmx->nested.change_vmcs01_virtual_apic_mode) {
13631                 vmx->nested.change_vmcs01_virtual_apic_mode = false;
13632                 vmx_set_virtual_apic_mode(vcpu);
13633         } else if (!nested_cpu_has_ept(vmcs12) &&
13634                    nested_cpu_has2(vmcs12,
13635                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
13636                 vmx_flush_tlb(vcpu, true);
13637         }
13638
13639         /* This is needed for same reason as it was needed in prepare_vmcs02 */
13640         vmx->host_rsp = 0;
13641
13642         /* Unpin physical memory we referred to in vmcs02 */
13643         if (vmx->nested.apic_access_page) {
13644                 kvm_release_page_dirty(vmx->nested.apic_access_page);
13645                 vmx->nested.apic_access_page = NULL;
13646         }
13647         if (vmx->nested.virtual_apic_page) {
13648                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
13649                 vmx->nested.virtual_apic_page = NULL;
13650         }
13651         if (vmx->nested.pi_desc_page) {
13652                 kunmap(vmx->nested.pi_desc_page);
13653                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
13654                 vmx->nested.pi_desc_page = NULL;
13655                 vmx->nested.pi_desc = NULL;
13656         }
13657
13658         /*
13659          * We are now running in L2, mmu_notifier will force to reload the
13660          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
13661          */
13662         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
13663
13664         if (enable_shadow_vmcs && exit_reason != -1)
13665                 vmx->nested.sync_shadow_vmcs = true;
13666
13667         /* in case we halted in L2 */
13668         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
13669
13670         if (likely(!vmx->fail)) {
13671                 /*
13672                  * TODO: SDM says that with acknowledge interrupt on
13673                  * exit, bit 31 of the VM-exit interrupt information
13674                  * (valid interrupt) is always set to 1 on
13675                  * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
13676                  * need kvm_cpu_has_interrupt().  See the commit
13677                  * message for details.
13678                  */
13679                 if (nested_exit_intr_ack_set(vcpu) &&
13680                     exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
13681                     kvm_cpu_has_interrupt(vcpu)) {
13682                         int irq = kvm_cpu_get_interrupt(vcpu);
13683                         WARN_ON(irq < 0);
13684                         vmcs12->vm_exit_intr_info = irq |
13685                                 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
13686                 }
13687
13688                 if (exit_reason != -1)
13689                         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
13690                                                        vmcs12->exit_qualification,
13691                                                        vmcs12->idt_vectoring_info_field,
13692                                                        vmcs12->vm_exit_intr_info,
13693                                                        vmcs12->vm_exit_intr_error_code,
13694                                                        KVM_ISA_VMX);
13695
13696                 load_vmcs12_host_state(vcpu, vmcs12);
13697
13698                 return;
13699         }
13700
13701         /*
13702          * After an early L2 VM-entry failure, we're now back
13703          * in L1 which thinks it just finished a VMLAUNCH or
13704          * VMRESUME instruction, so we need to set the failure
13705          * flag and the VM-instruction error field of the VMCS
13706          * accordingly, and skip the emulated instruction.
13707          */
13708         (void)nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
13709
13710         /*
13711          * Restore L1's host state to KVM's software model.  We're here
13712          * because a consistency check was caught by hardware, which
13713          * means some amount of guest state has been propagated to KVM's
13714          * model and needs to be unwound to the host's state.
13715          */
13716         nested_vmx_restore_host_state(vcpu);
13717
13718         vmx->fail = 0;
13719 }
13720
13721 /*
13722  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
13723  */
13724 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
13725 {
13726         if (is_guest_mode(vcpu)) {
13727                 to_vmx(vcpu)->nested.nested_run_pending = 0;
13728                 nested_vmx_vmexit(vcpu, -1, 0, 0);
13729         }
13730         free_nested(to_vmx(vcpu));
13731 }
13732
13733 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
13734                                struct x86_instruction_info *info,
13735                                enum x86_intercept_stage stage)
13736 {
13737         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
13738         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
13739
13740         /*
13741          * RDPID causes #UD if disabled through secondary execution controls.
13742          * Because it is marked as EmulateOnUD, we need to intercept it here.
13743          */
13744         if (info->intercept == x86_intercept_rdtscp &&
13745             !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
13746                 ctxt->exception.vector = UD_VECTOR;
13747                 ctxt->exception.error_code_valid = false;
13748                 return X86EMUL_PROPAGATE_FAULT;
13749         }
13750
13751         /* TODO: check more intercepts... */
13752         return X86EMUL_CONTINUE;
13753 }
13754
13755 #ifdef CONFIG_X86_64
13756 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
13757 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
13758                                   u64 divisor, u64 *result)
13759 {
13760         u64 low = a << shift, high = a >> (64 - shift);
13761
13762         /* To avoid the overflow on divq */
13763         if (high >= divisor)
13764                 return 1;
13765
13766         /* Low hold the result, high hold rem which is discarded */
13767         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
13768             "rm" (divisor), "0" (low), "1" (high));
13769         *result = low;
13770
13771         return 0;
13772 }
13773
13774 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
13775 {
13776         struct vcpu_vmx *vmx;
13777         u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
13778
13779         if (kvm_mwait_in_guest(vcpu->kvm))
13780                 return -EOPNOTSUPP;
13781
13782         vmx = to_vmx(vcpu);
13783         tscl = rdtsc();
13784         guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
13785         delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
13786         lapic_timer_advance_cycles = nsec_to_cycles(vcpu, lapic_timer_advance_ns);
13787
13788         if (delta_tsc > lapic_timer_advance_cycles)
13789                 delta_tsc -= lapic_timer_advance_cycles;
13790         else
13791                 delta_tsc = 0;
13792
13793         /* Convert to host delta tsc if tsc scaling is enabled */
13794         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
13795                         u64_shl_div_u64(delta_tsc,
13796                                 kvm_tsc_scaling_ratio_frac_bits,
13797                                 vcpu->arch.tsc_scaling_ratio,
13798                                 &delta_tsc))
13799                 return -ERANGE;
13800
13801         /*
13802          * If the delta tsc can't fit in the 32 bit after the multi shift,
13803          * we can't use the preemption timer.
13804          * It's possible that it fits on later vmentries, but checking
13805          * on every vmentry is costly so we just use an hrtimer.
13806          */
13807         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
13808                 return -ERANGE;
13809
13810         vmx->hv_deadline_tsc = tscl + delta_tsc;
13811         return delta_tsc == 0;
13812 }
13813
13814 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
13815 {
13816         to_vmx(vcpu)->hv_deadline_tsc = -1;
13817 }
13818 #endif
13819
13820 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
13821 {
13822         if (!kvm_pause_in_guest(vcpu->kvm))
13823                 shrink_ple_window(vcpu);
13824 }
13825
13826 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
13827                                      struct kvm_memory_slot *slot)
13828 {
13829         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
13830         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
13831 }
13832
13833 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
13834                                        struct kvm_memory_slot *slot)
13835 {
13836         kvm_mmu_slot_set_dirty(kvm, slot);
13837 }
13838
13839 static void vmx_flush_log_dirty(struct kvm *kvm)
13840 {
13841         kvm_flush_pml_buffers(kvm);
13842 }
13843
13844 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
13845 {
13846         struct vmcs12 *vmcs12;
13847         struct vcpu_vmx *vmx = to_vmx(vcpu);
13848         gpa_t gpa;
13849         struct page *page = NULL;
13850         u64 *pml_address;
13851
13852         if (is_guest_mode(vcpu)) {
13853                 WARN_ON_ONCE(vmx->nested.pml_full);
13854
13855                 /*
13856                  * Check if PML is enabled for the nested guest.
13857                  * Whether eptp bit 6 is set is already checked
13858                  * as part of A/D emulation.
13859                  */
13860                 vmcs12 = get_vmcs12(vcpu);
13861                 if (!nested_cpu_has_pml(vmcs12))
13862                         return 0;
13863
13864                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
13865                         vmx->nested.pml_full = true;
13866                         return 1;
13867                 }
13868
13869                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
13870
13871                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
13872                 if (is_error_page(page))
13873                         return 0;
13874
13875                 pml_address = kmap(page);
13876                 pml_address[vmcs12->guest_pml_index--] = gpa;
13877                 kunmap(page);
13878                 kvm_release_page_clean(page);
13879         }
13880
13881         return 0;
13882 }
13883
13884 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
13885                                            struct kvm_memory_slot *memslot,
13886                                            gfn_t offset, unsigned long mask)
13887 {
13888         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
13889 }
13890
13891 static void __pi_post_block(struct kvm_vcpu *vcpu)
13892 {
13893         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
13894         struct pi_desc old, new;
13895         unsigned int dest;
13896
13897         do {
13898                 old.control = new.control = pi_desc->control;
13899                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
13900                      "Wakeup handler not enabled while the VCPU is blocked\n");
13901
13902                 dest = cpu_physical_id(vcpu->cpu);
13903
13904                 if (x2apic_enabled())
13905                         new.ndst = dest;
13906                 else
13907                         new.ndst = (dest << 8) & 0xFF00;
13908
13909                 /* set 'NV' to 'notification vector' */
13910                 new.nv = POSTED_INTR_VECTOR;
13911         } while (cmpxchg64(&pi_desc->control, old.control,
13912                            new.control) != old.control);
13913
13914         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
13915                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13916                 list_del(&vcpu->blocked_vcpu_list);
13917                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13918                 vcpu->pre_pcpu = -1;
13919         }
13920 }
13921
13922 /*
13923  * This routine does the following things for vCPU which is going
13924  * to be blocked if VT-d PI is enabled.
13925  * - Store the vCPU to the wakeup list, so when interrupts happen
13926  *   we can find the right vCPU to wake up.
13927  * - Change the Posted-interrupt descriptor as below:
13928  *      'NDST' <-- vcpu->pre_pcpu
13929  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
13930  * - If 'ON' is set during this process, which means at least one
13931  *   interrupt is posted for this vCPU, we cannot block it, in
13932  *   this case, return 1, otherwise, return 0.
13933  *
13934  */
13935 static int pi_pre_block(struct kvm_vcpu *vcpu)
13936 {
13937         unsigned int dest;
13938         struct pi_desc old, new;
13939         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
13940
13941         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
13942                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
13943                 !kvm_vcpu_apicv_active(vcpu))
13944                 return 0;
13945
13946         WARN_ON(irqs_disabled());
13947         local_irq_disable();
13948         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
13949                 vcpu->pre_pcpu = vcpu->cpu;
13950                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13951                 list_add_tail(&vcpu->blocked_vcpu_list,
13952                               &per_cpu(blocked_vcpu_on_cpu,
13953                                        vcpu->pre_pcpu));
13954                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
13955         }
13956
13957         do {
13958                 old.control = new.control = pi_desc->control;
13959
13960                 WARN((pi_desc->sn == 1),
13961                      "Warning: SN field of posted-interrupts "
13962                      "is set before blocking\n");
13963
13964                 /*
13965                  * Since vCPU can be preempted during this process,
13966                  * vcpu->cpu could be different with pre_pcpu, we
13967                  * need to set pre_pcpu as the destination of wakeup
13968                  * notification event, then we can find the right vCPU
13969                  * to wakeup in wakeup handler if interrupts happen
13970                  * when the vCPU is in blocked state.
13971                  */
13972                 dest = cpu_physical_id(vcpu->pre_pcpu);
13973
13974                 if (x2apic_enabled())
13975                         new.ndst = dest;
13976                 else
13977                         new.ndst = (dest << 8) & 0xFF00;
13978
13979                 /* set 'NV' to 'wakeup vector' */
13980                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
13981         } while (cmpxchg64(&pi_desc->control, old.control,
13982                            new.control) != old.control);
13983
13984         /* We should not block the vCPU if an interrupt is posted for it.  */
13985         if (pi_test_on(pi_desc) == 1)
13986                 __pi_post_block(vcpu);
13987
13988         local_irq_enable();
13989         return (vcpu->pre_pcpu == -1);
13990 }
13991
13992 static int vmx_pre_block(struct kvm_vcpu *vcpu)
13993 {
13994         if (pi_pre_block(vcpu))
13995                 return 1;
13996
13997         if (kvm_lapic_hv_timer_in_use(vcpu))
13998                 kvm_lapic_switch_to_sw_timer(vcpu);
13999
14000         return 0;
14001 }
14002
14003 static void pi_post_block(struct kvm_vcpu *vcpu)
14004 {
14005         if (vcpu->pre_pcpu == -1)
14006                 return;
14007
14008         WARN_ON(irqs_disabled());
14009         local_irq_disable();
14010         __pi_post_block(vcpu);
14011         local_irq_enable();
14012 }
14013
14014 static void vmx_post_block(struct kvm_vcpu *vcpu)
14015 {
14016         if (kvm_x86_ops->set_hv_timer)
14017                 kvm_lapic_switch_to_hv_timer(vcpu);
14018
14019         pi_post_block(vcpu);
14020 }
14021
14022 /*
14023  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
14024  *
14025  * @kvm: kvm
14026  * @host_irq: host irq of the interrupt
14027  * @guest_irq: gsi of the interrupt
14028  * @set: set or unset PI
14029  * returns 0 on success, < 0 on failure
14030  */
14031 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
14032                               uint32_t guest_irq, bool set)
14033 {
14034         struct kvm_kernel_irq_routing_entry *e;
14035         struct kvm_irq_routing_table *irq_rt;
14036         struct kvm_lapic_irq irq;
14037         struct kvm_vcpu *vcpu;
14038         struct vcpu_data vcpu_info;
14039         int idx, ret = 0;
14040
14041         if (!kvm_arch_has_assigned_device(kvm) ||
14042                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
14043                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
14044                 return 0;
14045
14046         idx = srcu_read_lock(&kvm->irq_srcu);
14047         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
14048         if (guest_irq >= irq_rt->nr_rt_entries ||
14049             hlist_empty(&irq_rt->map[guest_irq])) {
14050                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
14051                              guest_irq, irq_rt->nr_rt_entries);
14052                 goto out;
14053         }
14054
14055         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
14056                 if (e->type != KVM_IRQ_ROUTING_MSI)
14057                         continue;
14058                 /*
14059                  * VT-d PI cannot support posting multicast/broadcast
14060                  * interrupts to a vCPU, we still use interrupt remapping
14061                  * for these kind of interrupts.
14062                  *
14063                  * For lowest-priority interrupts, we only support
14064                  * those with single CPU as the destination, e.g. user
14065                  * configures the interrupts via /proc/irq or uses
14066                  * irqbalance to make the interrupts single-CPU.
14067                  *
14068                  * We will support full lowest-priority interrupt later.
14069                  */
14070
14071                 kvm_set_msi_irq(kvm, e, &irq);
14072                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
14073                         /*
14074                          * Make sure the IRTE is in remapped mode if
14075                          * we don't handle it in posted mode.
14076                          */
14077                         ret = irq_set_vcpu_affinity(host_irq, NULL);
14078                         if (ret < 0) {
14079                                 printk(KERN_INFO
14080                                    "failed to back to remapped mode, irq: %u\n",
14081                                    host_irq);
14082                                 goto out;
14083                         }
14084
14085                         continue;
14086                 }
14087
14088                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
14089                 vcpu_info.vector = irq.vector;
14090
14091                 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
14092                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
14093
14094                 if (set)
14095                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
14096                 else
14097                         ret = irq_set_vcpu_affinity(host_irq, NULL);
14098
14099                 if (ret < 0) {
14100                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
14101                                         __func__);
14102                         goto out;
14103                 }
14104         }
14105
14106         ret = 0;
14107 out:
14108         srcu_read_unlock(&kvm->irq_srcu, idx);
14109         return ret;
14110 }
14111
14112 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
14113 {
14114         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
14115                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
14116                         FEATURE_CONTROL_LMCE;
14117         else
14118                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
14119                         ~FEATURE_CONTROL_LMCE;
14120 }
14121
14122 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
14123 {
14124         /* we need a nested vmexit to enter SMM, postpone if run is pending */
14125         if (to_vmx(vcpu)->nested.nested_run_pending)
14126                 return 0;
14127         return 1;
14128 }
14129
14130 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
14131 {
14132         struct vcpu_vmx *vmx = to_vmx(vcpu);
14133
14134         vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
14135         if (vmx->nested.smm.guest_mode)
14136                 nested_vmx_vmexit(vcpu, -1, 0, 0);
14137
14138         vmx->nested.smm.vmxon = vmx->nested.vmxon;
14139         vmx->nested.vmxon = false;
14140         vmx_clear_hlt(vcpu);
14141         return 0;
14142 }
14143
14144 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
14145 {
14146         struct vcpu_vmx *vmx = to_vmx(vcpu);
14147         int ret;
14148
14149         if (vmx->nested.smm.vmxon) {
14150                 vmx->nested.vmxon = true;
14151                 vmx->nested.smm.vmxon = false;
14152         }
14153
14154         if (vmx->nested.smm.guest_mode) {
14155                 vcpu->arch.hflags &= ~HF_SMM_MASK;
14156                 ret = nested_vmx_enter_non_root_mode(vcpu, false);
14157                 vcpu->arch.hflags |= HF_SMM_MASK;
14158                 if (ret)
14159                         return ret;
14160
14161                 vmx->nested.smm.guest_mode = false;
14162         }
14163         return 0;
14164 }
14165
14166 static int enable_smi_window(struct kvm_vcpu *vcpu)
14167 {
14168         return 0;
14169 }
14170
14171 static int vmx_get_nested_state(struct kvm_vcpu *vcpu,
14172                                 struct kvm_nested_state __user *user_kvm_nested_state,
14173                                 u32 user_data_size)
14174 {
14175         struct vcpu_vmx *vmx;
14176         struct vmcs12 *vmcs12;
14177         struct kvm_nested_state kvm_state = {
14178                 .flags = 0,
14179                 .format = 0,
14180                 .size = sizeof(kvm_state),
14181                 .vmx.vmxon_pa = -1ull,
14182                 .vmx.vmcs_pa = -1ull,
14183         };
14184
14185         if (!vcpu)
14186                 return kvm_state.size + 2 * VMCS12_SIZE;
14187
14188         vmx = to_vmx(vcpu);
14189         vmcs12 = get_vmcs12(vcpu);
14190         if (nested_vmx_allowed(vcpu) &&
14191             (vmx->nested.vmxon || vmx->nested.smm.vmxon)) {
14192                 kvm_state.vmx.vmxon_pa = vmx->nested.vmxon_ptr;
14193                 kvm_state.vmx.vmcs_pa = vmx->nested.current_vmptr;
14194
14195                 if (vmx->nested.current_vmptr != -1ull) {
14196                         kvm_state.size += VMCS12_SIZE;
14197
14198                         if (is_guest_mode(vcpu) &&
14199                             nested_cpu_has_shadow_vmcs(vmcs12) &&
14200                             vmcs12->vmcs_link_pointer != -1ull)
14201                                 kvm_state.size += VMCS12_SIZE;
14202                 }
14203
14204                 if (vmx->nested.smm.vmxon)
14205                         kvm_state.vmx.smm.flags |= KVM_STATE_NESTED_SMM_VMXON;
14206
14207                 if (vmx->nested.smm.guest_mode)
14208                         kvm_state.vmx.smm.flags |= KVM_STATE_NESTED_SMM_GUEST_MODE;
14209
14210                 if (is_guest_mode(vcpu)) {
14211                         kvm_state.flags |= KVM_STATE_NESTED_GUEST_MODE;
14212
14213                         if (vmx->nested.nested_run_pending)
14214                                 kvm_state.flags |= KVM_STATE_NESTED_RUN_PENDING;
14215                 }
14216         }
14217
14218         if (user_data_size < kvm_state.size)
14219                 goto out;
14220
14221         if (copy_to_user(user_kvm_nested_state, &kvm_state, sizeof(kvm_state)))
14222                 return -EFAULT;
14223
14224         if (vmx->nested.current_vmptr == -1ull)
14225                 goto out;
14226
14227         /*
14228          * When running L2, the authoritative vmcs12 state is in the
14229          * vmcs02. When running L1, the authoritative vmcs12 state is
14230          * in the shadow vmcs linked to vmcs01, unless
14231          * sync_shadow_vmcs is set, in which case, the authoritative
14232          * vmcs12 state is in the vmcs12 already.
14233          */
14234         if (is_guest_mode(vcpu))
14235                 sync_vmcs12(vcpu, vmcs12);
14236         else if (enable_shadow_vmcs && !vmx->nested.sync_shadow_vmcs)
14237                 copy_shadow_to_vmcs12(vmx);
14238
14239         if (copy_to_user(user_kvm_nested_state->data, vmcs12, sizeof(*vmcs12)))
14240                 return -EFAULT;
14241
14242         if (nested_cpu_has_shadow_vmcs(vmcs12) &&
14243             vmcs12->vmcs_link_pointer != -1ull) {
14244                 if (copy_to_user(user_kvm_nested_state->data + VMCS12_SIZE,
14245                                  get_shadow_vmcs12(vcpu), sizeof(*vmcs12)))
14246                         return -EFAULT;
14247         }
14248
14249 out:
14250         return kvm_state.size;
14251 }
14252
14253 static int vmx_set_nested_state(struct kvm_vcpu *vcpu,
14254                                 struct kvm_nested_state __user *user_kvm_nested_state,
14255                                 struct kvm_nested_state *kvm_state)
14256 {
14257         struct vcpu_vmx *vmx = to_vmx(vcpu);
14258         struct vmcs12 *vmcs12;
14259         u32 exit_qual;
14260         int ret;
14261
14262         if (kvm_state->format != 0)
14263                 return -EINVAL;
14264
14265         if (!nested_vmx_allowed(vcpu))
14266                 return kvm_state->vmx.vmxon_pa == -1ull ? 0 : -EINVAL;
14267
14268         if (kvm_state->vmx.vmxon_pa == -1ull) {
14269                 if (kvm_state->vmx.smm.flags)
14270                         return -EINVAL;
14271
14272                 if (kvm_state->vmx.vmcs_pa != -1ull)
14273                         return -EINVAL;
14274
14275                 vmx_leave_nested(vcpu);
14276                 return 0;
14277         }
14278
14279         if (!page_address_valid(vcpu, kvm_state->vmx.vmxon_pa))
14280                 return -EINVAL;
14281
14282         if (kvm_state->size < sizeof(kvm_state) + sizeof(*vmcs12))
14283                 return -EINVAL;
14284
14285         if (kvm_state->vmx.vmcs_pa == kvm_state->vmx.vmxon_pa ||
14286             !page_address_valid(vcpu, kvm_state->vmx.vmcs_pa))
14287                 return -EINVAL;
14288
14289         if ((kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
14290             (kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
14291                 return -EINVAL;
14292
14293         if (kvm_state->vmx.smm.flags &
14294             ~(KVM_STATE_NESTED_SMM_GUEST_MODE | KVM_STATE_NESTED_SMM_VMXON))
14295                 return -EINVAL;
14296
14297         /*
14298          * SMM temporarily disables VMX, so we cannot be in guest mode,
14299          * nor can VMLAUNCH/VMRESUME be pending.  Outside SMM, SMM flags
14300          * must be zero.
14301          */
14302         if (is_smm(vcpu) ? kvm_state->flags : kvm_state->vmx.smm.flags)
14303                 return -EINVAL;
14304
14305         if ((kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) &&
14306             !(kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON))
14307                 return -EINVAL;
14308
14309         vmx_leave_nested(vcpu);
14310         if (kvm_state->vmx.vmxon_pa == -1ull)
14311                 return 0;
14312
14313         vmx->nested.vmxon_ptr = kvm_state->vmx.vmxon_pa;
14314         ret = enter_vmx_operation(vcpu);
14315         if (ret)
14316                 return ret;
14317
14318         set_current_vmptr(vmx, kvm_state->vmx.vmcs_pa);
14319
14320         if (kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON) {
14321                 vmx->nested.smm.vmxon = true;
14322                 vmx->nested.vmxon = false;
14323
14324                 if (kvm_state->vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE)
14325                         vmx->nested.smm.guest_mode = true;
14326         }
14327
14328         vmcs12 = get_vmcs12(vcpu);
14329         if (copy_from_user(vmcs12, user_kvm_nested_state->data, sizeof(*vmcs12)))
14330                 return -EFAULT;
14331
14332         if (vmcs12->hdr.revision_id != VMCS12_REVISION)
14333                 return -EINVAL;
14334
14335         if (!(kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE))
14336                 return 0;
14337
14338         vmx->nested.nested_run_pending =
14339                 !!(kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING);
14340
14341         if (nested_cpu_has_shadow_vmcs(vmcs12) &&
14342             vmcs12->vmcs_link_pointer != -1ull) {
14343                 struct vmcs12 *shadow_vmcs12 = get_shadow_vmcs12(vcpu);
14344                 if (kvm_state->size < sizeof(kvm_state) + 2 * sizeof(*vmcs12))
14345                         return -EINVAL;
14346
14347                 if (copy_from_user(shadow_vmcs12,
14348                                    user_kvm_nested_state->data + VMCS12_SIZE,
14349                                    sizeof(*vmcs12)))
14350                         return -EFAULT;
14351
14352                 if (shadow_vmcs12->hdr.revision_id != VMCS12_REVISION ||
14353                     !shadow_vmcs12->hdr.shadow_vmcs)
14354                         return -EINVAL;
14355         }
14356
14357         if (check_vmentry_prereqs(vcpu, vmcs12) ||
14358             check_vmentry_postreqs(vcpu, vmcs12, &exit_qual))
14359                 return -EINVAL;
14360
14361         vmx->nested.dirty_vmcs12 = true;
14362         ret = nested_vmx_enter_non_root_mode(vcpu, false);
14363         if (ret)
14364                 return -EINVAL;
14365
14366         return 0;
14367 }
14368
14369 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
14370         .cpu_has_kvm_support = cpu_has_kvm_support,
14371         .disabled_by_bios = vmx_disabled_by_bios,
14372         .hardware_setup = hardware_setup,
14373         .hardware_unsetup = hardware_unsetup,
14374         .check_processor_compatibility = vmx_check_processor_compat,
14375         .hardware_enable = hardware_enable,
14376         .hardware_disable = hardware_disable,
14377         .cpu_has_accelerated_tpr = report_flexpriority,
14378         .has_emulated_msr = vmx_has_emulated_msr,
14379
14380         .vm_init = vmx_vm_init,
14381         .vm_alloc = vmx_vm_alloc,
14382         .vm_free = vmx_vm_free,
14383
14384         .vcpu_create = vmx_create_vcpu,
14385         .vcpu_free = vmx_free_vcpu,
14386         .vcpu_reset = vmx_vcpu_reset,
14387
14388         .prepare_guest_switch = vmx_prepare_switch_to_guest,
14389         .vcpu_load = vmx_vcpu_load,
14390         .vcpu_put = vmx_vcpu_put,
14391
14392         .update_bp_intercept = update_exception_bitmap,
14393         .get_msr_feature = vmx_get_msr_feature,
14394         .get_msr = vmx_get_msr,
14395         .set_msr = vmx_set_msr,
14396         .get_segment_base = vmx_get_segment_base,
14397         .get_segment = vmx_get_segment,
14398         .set_segment = vmx_set_segment,
14399         .get_cpl = vmx_get_cpl,
14400         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
14401         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
14402         .decache_cr3 = vmx_decache_cr3,
14403         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
14404         .set_cr0 = vmx_set_cr0,
14405         .set_cr3 = vmx_set_cr3,
14406         .set_cr4 = vmx_set_cr4,
14407         .set_efer = vmx_set_efer,
14408         .get_idt = vmx_get_idt,
14409         .set_idt = vmx_set_idt,
14410         .get_gdt = vmx_get_gdt,
14411         .set_gdt = vmx_set_gdt,
14412         .get_dr6 = vmx_get_dr6,
14413         .set_dr6 = vmx_set_dr6,
14414         .set_dr7 = vmx_set_dr7,
14415         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
14416         .cache_reg = vmx_cache_reg,
14417         .get_rflags = vmx_get_rflags,
14418         .set_rflags = vmx_set_rflags,
14419
14420         .tlb_flush = vmx_flush_tlb,
14421         .tlb_flush_gva = vmx_flush_tlb_gva,
14422
14423         .run = vmx_vcpu_run,
14424         .handle_exit = vmx_handle_exit,
14425         .skip_emulated_instruction = skip_emulated_instruction,
14426         .set_interrupt_shadow = vmx_set_interrupt_shadow,
14427         .get_interrupt_shadow = vmx_get_interrupt_shadow,
14428         .patch_hypercall = vmx_patch_hypercall,
14429         .set_irq = vmx_inject_irq,
14430         .set_nmi = vmx_inject_nmi,
14431         .queue_exception = vmx_queue_exception,
14432         .cancel_injection = vmx_cancel_injection,
14433         .interrupt_allowed = vmx_interrupt_allowed,
14434         .nmi_allowed = vmx_nmi_allowed,
14435         .get_nmi_mask = vmx_get_nmi_mask,
14436         .set_nmi_mask = vmx_set_nmi_mask,
14437         .enable_nmi_window = enable_nmi_window,
14438         .enable_irq_window = enable_irq_window,
14439         .update_cr8_intercept = update_cr8_intercept,
14440         .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
14441         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
14442         .get_enable_apicv = vmx_get_enable_apicv,
14443         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
14444         .load_eoi_exitmap = vmx_load_eoi_exitmap,
14445         .apicv_post_state_restore = vmx_apicv_post_state_restore,
14446         .hwapic_irr_update = vmx_hwapic_irr_update,
14447         .hwapic_isr_update = vmx_hwapic_isr_update,
14448         .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
14449         .sync_pir_to_irr = vmx_sync_pir_to_irr,
14450         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
14451
14452         .set_tss_addr = vmx_set_tss_addr,
14453         .set_identity_map_addr = vmx_set_identity_map_addr,
14454         .get_tdp_level = get_ept_level,
14455         .get_mt_mask = vmx_get_mt_mask,
14456
14457         .get_exit_info = vmx_get_exit_info,
14458
14459         .get_lpage_level = vmx_get_lpage_level,
14460
14461         .cpuid_update = vmx_cpuid_update,
14462
14463         .rdtscp_supported = vmx_rdtscp_supported,
14464         .invpcid_supported = vmx_invpcid_supported,
14465
14466         .set_supported_cpuid = vmx_set_supported_cpuid,
14467
14468         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
14469
14470         .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
14471         .write_tsc_offset = vmx_write_tsc_offset,
14472
14473         .set_tdp_cr3 = vmx_set_cr3,
14474
14475         .check_intercept = vmx_check_intercept,
14476         .handle_external_intr = vmx_handle_external_intr,
14477         .mpx_supported = vmx_mpx_supported,
14478         .xsaves_supported = vmx_xsaves_supported,
14479         .umip_emulated = vmx_umip_emulated,
14480
14481         .check_nested_events = vmx_check_nested_events,
14482         .request_immediate_exit = vmx_request_immediate_exit,
14483
14484         .sched_in = vmx_sched_in,
14485
14486         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
14487         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
14488         .flush_log_dirty = vmx_flush_log_dirty,
14489         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
14490         .write_log_dirty = vmx_write_pml_buffer,
14491
14492         .pre_block = vmx_pre_block,
14493         .post_block = vmx_post_block,
14494
14495         .pmu_ops = &intel_pmu_ops,
14496
14497         .update_pi_irte = vmx_update_pi_irte,
14498
14499 #ifdef CONFIG_X86_64
14500         .set_hv_timer = vmx_set_hv_timer,
14501         .cancel_hv_timer = vmx_cancel_hv_timer,
14502 #endif
14503
14504         .setup_mce = vmx_setup_mce,
14505
14506         .get_nested_state = vmx_get_nested_state,
14507         .set_nested_state = vmx_set_nested_state,
14508         .get_vmcs12_pages = nested_get_vmcs12_pages,
14509
14510         .smi_allowed = vmx_smi_allowed,
14511         .pre_enter_smm = vmx_pre_enter_smm,
14512         .pre_leave_smm = vmx_pre_leave_smm,
14513         .enable_smi_window = enable_smi_window,
14514 };
14515
14516 static void vmx_cleanup_l1d_flush(void)
14517 {
14518         if (vmx_l1d_flush_pages) {
14519                 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
14520                 vmx_l1d_flush_pages = NULL;
14521         }
14522         /* Restore state so sysfs ignores VMX */
14523         l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
14524 }
14525
14526 static void vmx_exit(void)
14527 {
14528 #ifdef CONFIG_KEXEC_CORE
14529         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
14530         synchronize_rcu();
14531 #endif
14532
14533         kvm_exit();
14534
14535 #if IS_ENABLED(CONFIG_HYPERV)
14536         if (static_branch_unlikely(&enable_evmcs)) {
14537                 int cpu;
14538                 struct hv_vp_assist_page *vp_ap;
14539                 /*
14540                  * Reset everything to support using non-enlightened VMCS
14541                  * access later (e.g. when we reload the module with
14542                  * enlightened_vmcs=0)
14543                  */
14544                 for_each_online_cpu(cpu) {
14545                         vp_ap = hv_get_vp_assist_page(cpu);
14546
14547                         if (!vp_ap)
14548                                 continue;
14549
14550                         vp_ap->current_nested_vmcs = 0;
14551                         vp_ap->enlighten_vmentry = 0;
14552                 }
14553
14554                 static_branch_disable(&enable_evmcs);
14555         }
14556 #endif
14557         vmx_cleanup_l1d_flush();
14558 }
14559 module_exit(vmx_exit);
14560
14561 static int __init vmx_init(void)
14562 {
14563         int r;
14564
14565 #if IS_ENABLED(CONFIG_HYPERV)
14566         /*
14567          * Enlightened VMCS usage should be recommended and the host needs
14568          * to support eVMCS v1 or above. We can also disable eVMCS support
14569          * with module parameter.
14570          */
14571         if (enlightened_vmcs &&
14572             ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
14573             (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
14574             KVM_EVMCS_VERSION) {
14575                 int cpu;
14576
14577                 /* Check that we have assist pages on all online CPUs */
14578                 for_each_online_cpu(cpu) {
14579                         if (!hv_get_vp_assist_page(cpu)) {
14580                                 enlightened_vmcs = false;
14581                                 break;
14582                         }
14583                 }
14584
14585                 if (enlightened_vmcs) {
14586                         pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
14587                         static_branch_enable(&enable_evmcs);
14588                 }
14589         } else {
14590                 enlightened_vmcs = false;
14591         }
14592 #endif
14593
14594         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
14595                      __alignof__(struct vcpu_vmx), THIS_MODULE);
14596         if (r)
14597                 return r;
14598
14599         /*
14600          * Must be called after kvm_init() so enable_ept is properly set
14601          * up. Hand the parameter mitigation value in which was stored in
14602          * the pre module init parser. If no parameter was given, it will
14603          * contain 'auto' which will be turned into the default 'cond'
14604          * mitigation mode.
14605          */
14606         if (boot_cpu_has(X86_BUG_L1TF)) {
14607                 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
14608                 if (r) {
14609                         vmx_exit();
14610                         return r;
14611                 }
14612         }
14613
14614 #ifdef CONFIG_KEXEC_CORE
14615         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
14616                            crash_vmclear_local_loaded_vmcss);
14617 #endif
14618         vmx_check_vmcs12_offsets();
14619
14620         return 0;
14621 }
14622 module_init(vmx_init);