2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include <linux/nospec.h>
38 #include "kvm_cache_regs.h"
45 #include <asm/virtext.h>
47 #include <asm/fpu/internal.h>
48 #include <asm/perf_event.h>
49 #include <asm/debugreg.h>
50 #include <asm/kexec.h>
52 #include <asm/irq_remapping.h>
53 #include <asm/mmu_context.h>
54 #include <asm/spec-ctrl.h>
55 #include <asm/mshyperv.h>
59 #include "vmx_evmcs.h"
61 #define __ex(x) __kvm_handle_fault_on_reboot(x)
62 #define __ex_clear(x, reg) \
63 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
65 MODULE_AUTHOR("Qumranet");
66 MODULE_LICENSE("GPL");
68 static const struct x86_cpu_id vmx_cpu_id[] = {
69 X86_FEATURE_MATCH(X86_FEATURE_VMX),
72 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
74 static bool __read_mostly enable_vpid = 1;
75 module_param_named(vpid, enable_vpid, bool, 0444);
77 static bool __read_mostly enable_vnmi = 1;
78 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
80 static bool __read_mostly flexpriority_enabled = 1;
81 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
83 static bool __read_mostly enable_ept = 1;
84 module_param_named(ept, enable_ept, bool, S_IRUGO);
86 static bool __read_mostly enable_unrestricted_guest = 1;
87 module_param_named(unrestricted_guest,
88 enable_unrestricted_guest, bool, S_IRUGO);
90 static bool __read_mostly enable_ept_ad_bits = 1;
91 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
93 static bool __read_mostly emulate_invalid_guest_state = true;
94 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
96 static bool __read_mostly fasteoi = 1;
97 module_param(fasteoi, bool, S_IRUGO);
99 static bool __read_mostly enable_apicv = 1;
100 module_param(enable_apicv, bool, S_IRUGO);
102 static bool __read_mostly enable_shadow_vmcs = 1;
103 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
105 * If nested=1, nested virtualization is supported, i.e., guests may use
106 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
107 * use VMX instructions.
109 static bool __read_mostly nested = 0;
110 module_param(nested, bool, S_IRUGO);
112 static u64 __read_mostly host_xss;
114 static bool __read_mostly enable_pml = 1;
115 module_param_named(pml, enable_pml, bool, S_IRUGO);
119 #define MSR_TYPE_RW 3
121 #define MSR_BITMAP_MODE_X2APIC 1
122 #define MSR_BITMAP_MODE_X2APIC_APICV 2
123 #define MSR_BITMAP_MODE_LM 4
125 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
127 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
128 static int __read_mostly cpu_preemption_timer_multi;
129 static bool __read_mostly enable_preemption_timer = 1;
131 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
134 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
135 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
136 #define KVM_VM_CR0_ALWAYS_ON \
137 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
138 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
139 #define KVM_CR4_GUEST_OWNED_BITS \
140 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
141 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
143 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
144 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
145 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
147 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
149 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
152 * Hyper-V requires all of these, so mark them as supported even though
153 * they are just treated the same as all-context.
155 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
156 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
157 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
158 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
159 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
162 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
163 * ple_gap: upper bound on the amount of time between two successive
164 * executions of PAUSE in a loop. Also indicate if ple enabled.
165 * According to test, this time is usually smaller than 128 cycles.
166 * ple_window: upper bound on the amount of time a guest is allowed to execute
167 * in a PAUSE loop. Tests indicate that most spinlocks are held for
168 * less than 2^12 cycles
169 * Time is measured based on a counter that runs at the same rate as the TSC,
170 * refer SDM volume 3b section 21.6.13 & 22.1.3.
172 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
174 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
175 module_param(ple_window, uint, 0444);
177 /* Default doubles per-vcpu window every exit. */
178 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
179 module_param(ple_window_grow, uint, 0444);
181 /* Default resets per-vcpu window every exit to ple_window. */
182 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
183 module_param(ple_window_shrink, uint, 0444);
185 /* Default is to compute the maximum so we can never overflow. */
186 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
187 module_param(ple_window_max, uint, 0444);
189 extern const ulong vmx_return;
194 unsigned int tss_addr;
195 bool ept_identity_pagetable_done;
196 gpa_t ept_identity_map_addr;
199 #define NR_AUTOLOAD_MSRS 8
208 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
209 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
210 * loaded on this CPU (so we can clear them if the CPU goes down).
214 struct vmcs *shadow_vmcs;
217 bool nmi_known_unmasked;
218 unsigned long vmcs_host_cr3; /* May not match real cr3 */
219 unsigned long vmcs_host_cr4; /* May not match real cr4 */
220 /* Support for vnmi-less CPUs */
221 int soft_vnmi_blocked;
223 s64 vnmi_blocked_time;
224 unsigned long *msr_bitmap;
225 struct list_head loaded_vmcss_on_cpu_link;
228 struct shared_msr_entry {
235 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
236 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
237 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
238 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
239 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
240 * More than one of these structures may exist, if L1 runs multiple L2 guests.
241 * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
242 * underlying hardware which will be used to run L2.
243 * This structure is packed to ensure that its layout is identical across
244 * machines (necessary for live migration).
246 * IMPORTANT: Changing the layout of existing fields in this structure
247 * will break save/restore compatibility with older kvm releases. When
248 * adding new fields, either use space in the reserved padding* arrays
249 * or add the new fields to the end of the structure.
251 typedef u64 natural_width;
252 struct __packed vmcs12 {
253 /* According to the Intel spec, a VMCS region must start with the
254 * following two fields. Then follow implementation-specific data.
259 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
260 u32 padding[7]; /* room for future expansion */
265 u64 vm_exit_msr_store_addr;
266 u64 vm_exit_msr_load_addr;
267 u64 vm_entry_msr_load_addr;
269 u64 virtual_apic_page_addr;
270 u64 apic_access_addr;
271 u64 posted_intr_desc_addr;
273 u64 eoi_exit_bitmap0;
274 u64 eoi_exit_bitmap1;
275 u64 eoi_exit_bitmap2;
276 u64 eoi_exit_bitmap3;
278 u64 guest_physical_address;
279 u64 vmcs_link_pointer;
280 u64 guest_ia32_debugctl;
283 u64 guest_ia32_perf_global_ctrl;
291 u64 host_ia32_perf_global_ctrl;
294 u64 vm_function_control;
295 u64 eptp_list_address;
297 u64 padding64[3]; /* room for future expansion */
299 * To allow migration of L1 (complete with its L2 guests) between
300 * machines of different natural widths (32 or 64 bit), we cannot have
301 * unsigned long fields with no explict size. We use u64 (aliased
302 * natural_width) instead. Luckily, x86 is little-endian.
304 natural_width cr0_guest_host_mask;
305 natural_width cr4_guest_host_mask;
306 natural_width cr0_read_shadow;
307 natural_width cr4_read_shadow;
308 natural_width cr3_target_value0;
309 natural_width cr3_target_value1;
310 natural_width cr3_target_value2;
311 natural_width cr3_target_value3;
312 natural_width exit_qualification;
313 natural_width guest_linear_address;
314 natural_width guest_cr0;
315 natural_width guest_cr3;
316 natural_width guest_cr4;
317 natural_width guest_es_base;
318 natural_width guest_cs_base;
319 natural_width guest_ss_base;
320 natural_width guest_ds_base;
321 natural_width guest_fs_base;
322 natural_width guest_gs_base;
323 natural_width guest_ldtr_base;
324 natural_width guest_tr_base;
325 natural_width guest_gdtr_base;
326 natural_width guest_idtr_base;
327 natural_width guest_dr7;
328 natural_width guest_rsp;
329 natural_width guest_rip;
330 natural_width guest_rflags;
331 natural_width guest_pending_dbg_exceptions;
332 natural_width guest_sysenter_esp;
333 natural_width guest_sysenter_eip;
334 natural_width host_cr0;
335 natural_width host_cr3;
336 natural_width host_cr4;
337 natural_width host_fs_base;
338 natural_width host_gs_base;
339 natural_width host_tr_base;
340 natural_width host_gdtr_base;
341 natural_width host_idtr_base;
342 natural_width host_ia32_sysenter_esp;
343 natural_width host_ia32_sysenter_eip;
344 natural_width host_rsp;
345 natural_width host_rip;
346 natural_width paddingl[8]; /* room for future expansion */
347 u32 pin_based_vm_exec_control;
348 u32 cpu_based_vm_exec_control;
349 u32 exception_bitmap;
350 u32 page_fault_error_code_mask;
351 u32 page_fault_error_code_match;
352 u32 cr3_target_count;
353 u32 vm_exit_controls;
354 u32 vm_exit_msr_store_count;
355 u32 vm_exit_msr_load_count;
356 u32 vm_entry_controls;
357 u32 vm_entry_msr_load_count;
358 u32 vm_entry_intr_info_field;
359 u32 vm_entry_exception_error_code;
360 u32 vm_entry_instruction_len;
362 u32 secondary_vm_exec_control;
363 u32 vm_instruction_error;
365 u32 vm_exit_intr_info;
366 u32 vm_exit_intr_error_code;
367 u32 idt_vectoring_info_field;
368 u32 idt_vectoring_error_code;
369 u32 vm_exit_instruction_len;
370 u32 vmx_instruction_info;
377 u32 guest_ldtr_limit;
379 u32 guest_gdtr_limit;
380 u32 guest_idtr_limit;
381 u32 guest_es_ar_bytes;
382 u32 guest_cs_ar_bytes;
383 u32 guest_ss_ar_bytes;
384 u32 guest_ds_ar_bytes;
385 u32 guest_fs_ar_bytes;
386 u32 guest_gs_ar_bytes;
387 u32 guest_ldtr_ar_bytes;
388 u32 guest_tr_ar_bytes;
389 u32 guest_interruptibility_info;
390 u32 guest_activity_state;
391 u32 guest_sysenter_cs;
392 u32 host_ia32_sysenter_cs;
393 u32 vmx_preemption_timer_value;
394 u32 padding32[7]; /* room for future expansion */
395 u16 virtual_processor_id;
397 u16 guest_es_selector;
398 u16 guest_cs_selector;
399 u16 guest_ss_selector;
400 u16 guest_ds_selector;
401 u16 guest_fs_selector;
402 u16 guest_gs_selector;
403 u16 guest_ldtr_selector;
404 u16 guest_tr_selector;
405 u16 guest_intr_status;
406 u16 host_es_selector;
407 u16 host_cs_selector;
408 u16 host_ss_selector;
409 u16 host_ds_selector;
410 u16 host_fs_selector;
411 u16 host_gs_selector;
412 u16 host_tr_selector;
417 * For save/restore compatibility, the vmcs12 field offsets must not change.
419 #define CHECK_OFFSET(field, loc) \
420 BUILD_BUG_ON_MSG(offsetof(struct vmcs12, field) != (loc), \
421 "Offset of " #field " in struct vmcs12 has changed.")
423 static inline void vmx_check_vmcs12_offsets(void) {
424 CHECK_OFFSET(revision_id, 0);
425 CHECK_OFFSET(abort, 4);
426 CHECK_OFFSET(launch_state, 8);
427 CHECK_OFFSET(io_bitmap_a, 40);
428 CHECK_OFFSET(io_bitmap_b, 48);
429 CHECK_OFFSET(msr_bitmap, 56);
430 CHECK_OFFSET(vm_exit_msr_store_addr, 64);
431 CHECK_OFFSET(vm_exit_msr_load_addr, 72);
432 CHECK_OFFSET(vm_entry_msr_load_addr, 80);
433 CHECK_OFFSET(tsc_offset, 88);
434 CHECK_OFFSET(virtual_apic_page_addr, 96);
435 CHECK_OFFSET(apic_access_addr, 104);
436 CHECK_OFFSET(posted_intr_desc_addr, 112);
437 CHECK_OFFSET(ept_pointer, 120);
438 CHECK_OFFSET(eoi_exit_bitmap0, 128);
439 CHECK_OFFSET(eoi_exit_bitmap1, 136);
440 CHECK_OFFSET(eoi_exit_bitmap2, 144);
441 CHECK_OFFSET(eoi_exit_bitmap3, 152);
442 CHECK_OFFSET(xss_exit_bitmap, 160);
443 CHECK_OFFSET(guest_physical_address, 168);
444 CHECK_OFFSET(vmcs_link_pointer, 176);
445 CHECK_OFFSET(guest_ia32_debugctl, 184);
446 CHECK_OFFSET(guest_ia32_pat, 192);
447 CHECK_OFFSET(guest_ia32_efer, 200);
448 CHECK_OFFSET(guest_ia32_perf_global_ctrl, 208);
449 CHECK_OFFSET(guest_pdptr0, 216);
450 CHECK_OFFSET(guest_pdptr1, 224);
451 CHECK_OFFSET(guest_pdptr2, 232);
452 CHECK_OFFSET(guest_pdptr3, 240);
453 CHECK_OFFSET(guest_bndcfgs, 248);
454 CHECK_OFFSET(host_ia32_pat, 256);
455 CHECK_OFFSET(host_ia32_efer, 264);
456 CHECK_OFFSET(host_ia32_perf_global_ctrl, 272);
457 CHECK_OFFSET(vmread_bitmap, 280);
458 CHECK_OFFSET(vmwrite_bitmap, 288);
459 CHECK_OFFSET(vm_function_control, 296);
460 CHECK_OFFSET(eptp_list_address, 304);
461 CHECK_OFFSET(pml_address, 312);
462 CHECK_OFFSET(cr0_guest_host_mask, 344);
463 CHECK_OFFSET(cr4_guest_host_mask, 352);
464 CHECK_OFFSET(cr0_read_shadow, 360);
465 CHECK_OFFSET(cr4_read_shadow, 368);
466 CHECK_OFFSET(cr3_target_value0, 376);
467 CHECK_OFFSET(cr3_target_value1, 384);
468 CHECK_OFFSET(cr3_target_value2, 392);
469 CHECK_OFFSET(cr3_target_value3, 400);
470 CHECK_OFFSET(exit_qualification, 408);
471 CHECK_OFFSET(guest_linear_address, 416);
472 CHECK_OFFSET(guest_cr0, 424);
473 CHECK_OFFSET(guest_cr3, 432);
474 CHECK_OFFSET(guest_cr4, 440);
475 CHECK_OFFSET(guest_es_base, 448);
476 CHECK_OFFSET(guest_cs_base, 456);
477 CHECK_OFFSET(guest_ss_base, 464);
478 CHECK_OFFSET(guest_ds_base, 472);
479 CHECK_OFFSET(guest_fs_base, 480);
480 CHECK_OFFSET(guest_gs_base, 488);
481 CHECK_OFFSET(guest_ldtr_base, 496);
482 CHECK_OFFSET(guest_tr_base, 504);
483 CHECK_OFFSET(guest_gdtr_base, 512);
484 CHECK_OFFSET(guest_idtr_base, 520);
485 CHECK_OFFSET(guest_dr7, 528);
486 CHECK_OFFSET(guest_rsp, 536);
487 CHECK_OFFSET(guest_rip, 544);
488 CHECK_OFFSET(guest_rflags, 552);
489 CHECK_OFFSET(guest_pending_dbg_exceptions, 560);
490 CHECK_OFFSET(guest_sysenter_esp, 568);
491 CHECK_OFFSET(guest_sysenter_eip, 576);
492 CHECK_OFFSET(host_cr0, 584);
493 CHECK_OFFSET(host_cr3, 592);
494 CHECK_OFFSET(host_cr4, 600);
495 CHECK_OFFSET(host_fs_base, 608);
496 CHECK_OFFSET(host_gs_base, 616);
497 CHECK_OFFSET(host_tr_base, 624);
498 CHECK_OFFSET(host_gdtr_base, 632);
499 CHECK_OFFSET(host_idtr_base, 640);
500 CHECK_OFFSET(host_ia32_sysenter_esp, 648);
501 CHECK_OFFSET(host_ia32_sysenter_eip, 656);
502 CHECK_OFFSET(host_rsp, 664);
503 CHECK_OFFSET(host_rip, 672);
504 CHECK_OFFSET(pin_based_vm_exec_control, 744);
505 CHECK_OFFSET(cpu_based_vm_exec_control, 748);
506 CHECK_OFFSET(exception_bitmap, 752);
507 CHECK_OFFSET(page_fault_error_code_mask, 756);
508 CHECK_OFFSET(page_fault_error_code_match, 760);
509 CHECK_OFFSET(cr3_target_count, 764);
510 CHECK_OFFSET(vm_exit_controls, 768);
511 CHECK_OFFSET(vm_exit_msr_store_count, 772);
512 CHECK_OFFSET(vm_exit_msr_load_count, 776);
513 CHECK_OFFSET(vm_entry_controls, 780);
514 CHECK_OFFSET(vm_entry_msr_load_count, 784);
515 CHECK_OFFSET(vm_entry_intr_info_field, 788);
516 CHECK_OFFSET(vm_entry_exception_error_code, 792);
517 CHECK_OFFSET(vm_entry_instruction_len, 796);
518 CHECK_OFFSET(tpr_threshold, 800);
519 CHECK_OFFSET(secondary_vm_exec_control, 804);
520 CHECK_OFFSET(vm_instruction_error, 808);
521 CHECK_OFFSET(vm_exit_reason, 812);
522 CHECK_OFFSET(vm_exit_intr_info, 816);
523 CHECK_OFFSET(vm_exit_intr_error_code, 820);
524 CHECK_OFFSET(idt_vectoring_info_field, 824);
525 CHECK_OFFSET(idt_vectoring_error_code, 828);
526 CHECK_OFFSET(vm_exit_instruction_len, 832);
527 CHECK_OFFSET(vmx_instruction_info, 836);
528 CHECK_OFFSET(guest_es_limit, 840);
529 CHECK_OFFSET(guest_cs_limit, 844);
530 CHECK_OFFSET(guest_ss_limit, 848);
531 CHECK_OFFSET(guest_ds_limit, 852);
532 CHECK_OFFSET(guest_fs_limit, 856);
533 CHECK_OFFSET(guest_gs_limit, 860);
534 CHECK_OFFSET(guest_ldtr_limit, 864);
535 CHECK_OFFSET(guest_tr_limit, 868);
536 CHECK_OFFSET(guest_gdtr_limit, 872);
537 CHECK_OFFSET(guest_idtr_limit, 876);
538 CHECK_OFFSET(guest_es_ar_bytes, 880);
539 CHECK_OFFSET(guest_cs_ar_bytes, 884);
540 CHECK_OFFSET(guest_ss_ar_bytes, 888);
541 CHECK_OFFSET(guest_ds_ar_bytes, 892);
542 CHECK_OFFSET(guest_fs_ar_bytes, 896);
543 CHECK_OFFSET(guest_gs_ar_bytes, 900);
544 CHECK_OFFSET(guest_ldtr_ar_bytes, 904);
545 CHECK_OFFSET(guest_tr_ar_bytes, 908);
546 CHECK_OFFSET(guest_interruptibility_info, 912);
547 CHECK_OFFSET(guest_activity_state, 916);
548 CHECK_OFFSET(guest_sysenter_cs, 920);
549 CHECK_OFFSET(host_ia32_sysenter_cs, 924);
550 CHECK_OFFSET(vmx_preemption_timer_value, 928);
551 CHECK_OFFSET(virtual_processor_id, 960);
552 CHECK_OFFSET(posted_intr_nv, 962);
553 CHECK_OFFSET(guest_es_selector, 964);
554 CHECK_OFFSET(guest_cs_selector, 966);
555 CHECK_OFFSET(guest_ss_selector, 968);
556 CHECK_OFFSET(guest_ds_selector, 970);
557 CHECK_OFFSET(guest_fs_selector, 972);
558 CHECK_OFFSET(guest_gs_selector, 974);
559 CHECK_OFFSET(guest_ldtr_selector, 976);
560 CHECK_OFFSET(guest_tr_selector, 978);
561 CHECK_OFFSET(guest_intr_status, 980);
562 CHECK_OFFSET(host_es_selector, 982);
563 CHECK_OFFSET(host_cs_selector, 984);
564 CHECK_OFFSET(host_ss_selector, 986);
565 CHECK_OFFSET(host_ds_selector, 988);
566 CHECK_OFFSET(host_fs_selector, 990);
567 CHECK_OFFSET(host_gs_selector, 992);
568 CHECK_OFFSET(host_tr_selector, 994);
569 CHECK_OFFSET(guest_pml_index, 996);
573 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
574 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
575 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
577 * IMPORTANT: Changing this value will break save/restore compatibility with
578 * older kvm releases.
580 #define VMCS12_REVISION 0x11e57ed0
583 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
584 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
585 * current implementation, 4K are reserved to avoid future complications.
587 #define VMCS12_SIZE 0x1000
590 * VMCS12_MAX_FIELD_INDEX is the highest index value used in any
591 * supported VMCS12 field encoding.
593 #define VMCS12_MAX_FIELD_INDEX 0x17
595 struct nested_vmx_msrs {
597 * We only store the "true" versions of the VMX capability MSRs. We
598 * generate the "non-true" versions by setting the must-be-1 bits
599 * according to the SDM.
601 u32 procbased_ctls_low;
602 u32 procbased_ctls_high;
603 u32 secondary_ctls_low;
604 u32 secondary_ctls_high;
605 u32 pinbased_ctls_low;
606 u32 pinbased_ctls_high;
625 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
626 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
629 /* Has the level1 guest done vmxon? */
634 /* The guest-physical address of the current VMCS L1 keeps for L2 */
637 * Cache of the guest's VMCS, existing outside of guest memory.
638 * Loaded from guest memory during VMPTRLD. Flushed to guest
639 * memory during VMCLEAR and VMPTRLD.
641 struct vmcs12 *cached_vmcs12;
643 * Indicates if the shadow vmcs must be updated with the
644 * data hold by vmcs12
646 bool sync_shadow_vmcs;
649 bool change_vmcs01_virtual_apic_mode;
651 /* L2 must run next, and mustn't decide to exit to L1. */
652 bool nested_run_pending;
654 struct loaded_vmcs vmcs02;
657 * Guest pages referred to in the vmcs02 with host-physical
658 * pointers, so we must keep them pinned while L2 runs.
660 struct page *apic_access_page;
661 struct page *virtual_apic_page;
662 struct page *pi_desc_page;
663 struct pi_desc *pi_desc;
667 struct hrtimer preemption_timer;
668 bool preemption_timer_expired;
670 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
676 struct nested_vmx_msrs msrs;
678 /* SMM related state */
680 /* in VMX operation on SMM entry? */
682 /* in guest mode on SMM entry? */
687 #define POSTED_INTR_ON 0
688 #define POSTED_INTR_SN 1
690 /* Posted-Interrupt Descriptor */
692 u32 pir[8]; /* Posted interrupt requested */
695 /* bit 256 - Outstanding Notification */
697 /* bit 257 - Suppress Notification */
699 /* bit 271:258 - Reserved */
701 /* bit 279:272 - Notification Vector */
703 /* bit 287:280 - Reserved */
705 /* bit 319:288 - Notification Destination */
713 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
715 return test_and_set_bit(POSTED_INTR_ON,
716 (unsigned long *)&pi_desc->control);
719 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
721 return test_and_clear_bit(POSTED_INTR_ON,
722 (unsigned long *)&pi_desc->control);
725 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
727 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
730 static inline void pi_clear_sn(struct pi_desc *pi_desc)
732 return clear_bit(POSTED_INTR_SN,
733 (unsigned long *)&pi_desc->control);
736 static inline void pi_set_sn(struct pi_desc *pi_desc)
738 return set_bit(POSTED_INTR_SN,
739 (unsigned long *)&pi_desc->control);
742 static inline void pi_clear_on(struct pi_desc *pi_desc)
744 clear_bit(POSTED_INTR_ON,
745 (unsigned long *)&pi_desc->control);
748 static inline int pi_test_on(struct pi_desc *pi_desc)
750 return test_bit(POSTED_INTR_ON,
751 (unsigned long *)&pi_desc->control);
754 static inline int pi_test_sn(struct pi_desc *pi_desc)
756 return test_bit(POSTED_INTR_SN,
757 (unsigned long *)&pi_desc->control);
761 struct kvm_vcpu vcpu;
762 unsigned long host_rsp;
766 u32 idt_vectoring_info;
768 struct shared_msr_entry *guest_msrs;
771 unsigned long host_idt_base;
773 u64 msr_host_kernel_gs_base;
774 u64 msr_guest_kernel_gs_base;
777 u64 arch_capabilities;
780 u32 vm_entry_controls_shadow;
781 u32 vm_exit_controls_shadow;
782 u32 secondary_exec_control;
785 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
786 * non-nested (L1) guest, it always points to vmcs01. For a nested
787 * guest (L2), it points to a different VMCS.
789 struct loaded_vmcs vmcs01;
790 struct loaded_vmcs *loaded_vmcs;
791 bool __launched; /* temporary, used in vmx_vcpu_run */
792 struct msr_autoload {
794 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
795 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
799 u16 fs_sel, gs_sel, ldt_sel;
803 int gs_ldt_reload_needed;
804 int fs_reload_needed;
805 u64 msr_host_bndcfgs;
810 struct kvm_segment segs[8];
813 u32 bitmask; /* 4 bits per segment (1 bit per field) */
814 struct kvm_save_segment {
822 bool emulation_required;
826 /* Posted interrupt descriptor */
827 struct pi_desc pi_desc;
829 /* Support for a guest hypervisor (nested VMX) */
830 struct nested_vmx nested;
832 /* Dynamic PLE window. */
834 bool ple_window_dirty;
836 /* Support for PML */
837 #define PML_ENTITY_NUM 512
840 /* apic deadline value in host tsc */
843 u64 current_tsc_ratio;
847 unsigned long host_debugctlmsr;
850 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
851 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
852 * in msr_ia32_feature_control_valid_bits.
854 u64 msr_ia32_feature_control;
855 u64 msr_ia32_feature_control_valid_bits;
858 enum segment_cache_field {
867 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
869 return container_of(kvm, struct kvm_vmx, kvm);
872 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
874 return container_of(vcpu, struct vcpu_vmx, vcpu);
877 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
879 return &(to_vmx(vcpu)->pi_desc);
882 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
883 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
884 #define FIELD(number, name) [ROL16(number, 6)] = VMCS12_OFFSET(name)
885 #define FIELD64(number, name) \
886 FIELD(number, name), \
887 [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
890 static u16 shadow_read_only_fields[] = {
891 #define SHADOW_FIELD_RO(x) x,
892 #include "vmx_shadow_fields.h"
894 static int max_shadow_read_only_fields =
895 ARRAY_SIZE(shadow_read_only_fields);
897 static u16 shadow_read_write_fields[] = {
898 #define SHADOW_FIELD_RW(x) x,
899 #include "vmx_shadow_fields.h"
901 static int max_shadow_read_write_fields =
902 ARRAY_SIZE(shadow_read_write_fields);
904 static const unsigned short vmcs_field_to_offset_table[] = {
905 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
906 FIELD(POSTED_INTR_NV, posted_intr_nv),
907 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
908 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
909 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
910 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
911 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
912 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
913 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
914 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
915 FIELD(GUEST_INTR_STATUS, guest_intr_status),
916 FIELD(GUEST_PML_INDEX, guest_pml_index),
917 FIELD(HOST_ES_SELECTOR, host_es_selector),
918 FIELD(HOST_CS_SELECTOR, host_cs_selector),
919 FIELD(HOST_SS_SELECTOR, host_ss_selector),
920 FIELD(HOST_DS_SELECTOR, host_ds_selector),
921 FIELD(HOST_FS_SELECTOR, host_fs_selector),
922 FIELD(HOST_GS_SELECTOR, host_gs_selector),
923 FIELD(HOST_TR_SELECTOR, host_tr_selector),
924 FIELD64(IO_BITMAP_A, io_bitmap_a),
925 FIELD64(IO_BITMAP_B, io_bitmap_b),
926 FIELD64(MSR_BITMAP, msr_bitmap),
927 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
928 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
929 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
930 FIELD64(PML_ADDRESS, pml_address),
931 FIELD64(TSC_OFFSET, tsc_offset),
932 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
933 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
934 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
935 FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
936 FIELD64(EPT_POINTER, ept_pointer),
937 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
938 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
939 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
940 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
941 FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
942 FIELD64(VMREAD_BITMAP, vmread_bitmap),
943 FIELD64(VMWRITE_BITMAP, vmwrite_bitmap),
944 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
945 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
946 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
947 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
948 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
949 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
950 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
951 FIELD64(GUEST_PDPTR0, guest_pdptr0),
952 FIELD64(GUEST_PDPTR1, guest_pdptr1),
953 FIELD64(GUEST_PDPTR2, guest_pdptr2),
954 FIELD64(GUEST_PDPTR3, guest_pdptr3),
955 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
956 FIELD64(HOST_IA32_PAT, host_ia32_pat),
957 FIELD64(HOST_IA32_EFER, host_ia32_efer),
958 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
959 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
960 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
961 FIELD(EXCEPTION_BITMAP, exception_bitmap),
962 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
963 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
964 FIELD(CR3_TARGET_COUNT, cr3_target_count),
965 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
966 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
967 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
968 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
969 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
970 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
971 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
972 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
973 FIELD(TPR_THRESHOLD, tpr_threshold),
974 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
975 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
976 FIELD(VM_EXIT_REASON, vm_exit_reason),
977 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
978 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
979 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
980 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
981 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
982 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
983 FIELD(GUEST_ES_LIMIT, guest_es_limit),
984 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
985 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
986 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
987 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
988 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
989 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
990 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
991 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
992 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
993 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
994 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
995 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
996 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
997 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
998 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
999 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
1000 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
1001 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
1002 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
1003 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
1004 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
1005 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
1006 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
1007 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
1008 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
1009 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
1010 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
1011 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
1012 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
1013 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
1014 FIELD(EXIT_QUALIFICATION, exit_qualification),
1015 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
1016 FIELD(GUEST_CR0, guest_cr0),
1017 FIELD(GUEST_CR3, guest_cr3),
1018 FIELD(GUEST_CR4, guest_cr4),
1019 FIELD(GUEST_ES_BASE, guest_es_base),
1020 FIELD(GUEST_CS_BASE, guest_cs_base),
1021 FIELD(GUEST_SS_BASE, guest_ss_base),
1022 FIELD(GUEST_DS_BASE, guest_ds_base),
1023 FIELD(GUEST_FS_BASE, guest_fs_base),
1024 FIELD(GUEST_GS_BASE, guest_gs_base),
1025 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
1026 FIELD(GUEST_TR_BASE, guest_tr_base),
1027 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
1028 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
1029 FIELD(GUEST_DR7, guest_dr7),
1030 FIELD(GUEST_RSP, guest_rsp),
1031 FIELD(GUEST_RIP, guest_rip),
1032 FIELD(GUEST_RFLAGS, guest_rflags),
1033 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
1034 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
1035 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
1036 FIELD(HOST_CR0, host_cr0),
1037 FIELD(HOST_CR3, host_cr3),
1038 FIELD(HOST_CR4, host_cr4),
1039 FIELD(HOST_FS_BASE, host_fs_base),
1040 FIELD(HOST_GS_BASE, host_gs_base),
1041 FIELD(HOST_TR_BASE, host_tr_base),
1042 FIELD(HOST_GDTR_BASE, host_gdtr_base),
1043 FIELD(HOST_IDTR_BASE, host_idtr_base),
1044 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
1045 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
1046 FIELD(HOST_RSP, host_rsp),
1047 FIELD(HOST_RIP, host_rip),
1050 static inline short vmcs_field_to_offset(unsigned long field)
1052 const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
1053 unsigned short offset;
1059 index = ROL16(field, 6);
1063 index = array_index_nospec(index, size);
1064 offset = vmcs_field_to_offset_table[index];
1070 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
1072 return to_vmx(vcpu)->nested.cached_vmcs12;
1075 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
1076 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
1077 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
1078 static bool vmx_xsaves_supported(void);
1079 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1080 struct kvm_segment *var, int seg);
1081 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1082 struct kvm_segment *var, int seg);
1083 static bool guest_state_valid(struct kvm_vcpu *vcpu);
1084 static u32 vmx_segment_access_rights(struct kvm_segment *var);
1085 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
1086 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
1087 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
1088 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
1090 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
1091 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
1094 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
1095 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
1097 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
1098 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
1100 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
1103 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
1104 * can find which vCPU should be waken up.
1106 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
1107 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
1115 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
1117 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
1118 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
1120 static bool cpu_has_load_ia32_efer;
1121 static bool cpu_has_load_perf_global_ctrl;
1123 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
1124 static DEFINE_SPINLOCK(vmx_vpid_lock);
1126 static struct vmcs_config {
1131 u32 pin_based_exec_ctrl;
1132 u32 cpu_based_exec_ctrl;
1133 u32 cpu_based_2nd_exec_ctrl;
1136 struct nested_vmx_msrs nested;
1139 static struct vmx_capability {
1144 #define VMX_SEGMENT_FIELD(seg) \
1145 [VCPU_SREG_##seg] = { \
1146 .selector = GUEST_##seg##_SELECTOR, \
1147 .base = GUEST_##seg##_BASE, \
1148 .limit = GUEST_##seg##_LIMIT, \
1149 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1152 static const struct kvm_vmx_segment_field {
1157 } kvm_vmx_segment_fields[] = {
1158 VMX_SEGMENT_FIELD(CS),
1159 VMX_SEGMENT_FIELD(DS),
1160 VMX_SEGMENT_FIELD(ES),
1161 VMX_SEGMENT_FIELD(FS),
1162 VMX_SEGMENT_FIELD(GS),
1163 VMX_SEGMENT_FIELD(SS),
1164 VMX_SEGMENT_FIELD(TR),
1165 VMX_SEGMENT_FIELD(LDTR),
1168 static u64 host_efer;
1170 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1173 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1174 * away by decrementing the array size.
1176 static const u32 vmx_msr_index[] = {
1177 #ifdef CONFIG_X86_64
1178 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1180 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1183 DEFINE_STATIC_KEY_FALSE(enable_evmcs);
1185 #define current_evmcs ((struct hv_enlightened_vmcs *)this_cpu_read(current_vmcs))
1187 #define KVM_EVMCS_VERSION 1
1189 #if IS_ENABLED(CONFIG_HYPERV)
1190 static bool __read_mostly enlightened_vmcs = true;
1191 module_param(enlightened_vmcs, bool, 0444);
1193 static inline void evmcs_write64(unsigned long field, u64 value)
1196 int offset = get_evmcs_offset(field, &clean_field);
1201 *(u64 *)((char *)current_evmcs + offset) = value;
1203 current_evmcs->hv_clean_fields &= ~clean_field;
1206 static inline void evmcs_write32(unsigned long field, u32 value)
1209 int offset = get_evmcs_offset(field, &clean_field);
1214 *(u32 *)((char *)current_evmcs + offset) = value;
1215 current_evmcs->hv_clean_fields &= ~clean_field;
1218 static inline void evmcs_write16(unsigned long field, u16 value)
1221 int offset = get_evmcs_offset(field, &clean_field);
1226 *(u16 *)((char *)current_evmcs + offset) = value;
1227 current_evmcs->hv_clean_fields &= ~clean_field;
1230 static inline u64 evmcs_read64(unsigned long field)
1232 int offset = get_evmcs_offset(field, NULL);
1237 return *(u64 *)((char *)current_evmcs + offset);
1240 static inline u32 evmcs_read32(unsigned long field)
1242 int offset = get_evmcs_offset(field, NULL);
1247 return *(u32 *)((char *)current_evmcs + offset);
1250 static inline u16 evmcs_read16(unsigned long field)
1252 int offset = get_evmcs_offset(field, NULL);
1257 return *(u16 *)((char *)current_evmcs + offset);
1260 static inline void evmcs_touch_msr_bitmap(void)
1262 if (unlikely(!current_evmcs))
1265 if (current_evmcs->hv_enlightenments_control.msr_bitmap)
1266 current_evmcs->hv_clean_fields &=
1267 ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP;
1270 static void evmcs_load(u64 phys_addr)
1272 struct hv_vp_assist_page *vp_ap =
1273 hv_get_vp_assist_page(smp_processor_id());
1275 vp_ap->current_nested_vmcs = phys_addr;
1276 vp_ap->enlighten_vmentry = 1;
1279 static void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf)
1282 * Enlightened VMCSv1 doesn't support these:
1284 * POSTED_INTR_NV = 0x00000002,
1285 * GUEST_INTR_STATUS = 0x00000810,
1286 * APIC_ACCESS_ADDR = 0x00002014,
1287 * POSTED_INTR_DESC_ADDR = 0x00002016,
1288 * EOI_EXIT_BITMAP0 = 0x0000201c,
1289 * EOI_EXIT_BITMAP1 = 0x0000201e,
1290 * EOI_EXIT_BITMAP2 = 0x00002020,
1291 * EOI_EXIT_BITMAP3 = 0x00002022,
1293 vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
1294 vmcs_conf->cpu_based_2nd_exec_ctrl &=
1295 ~SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1296 vmcs_conf->cpu_based_2nd_exec_ctrl &=
1297 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1298 vmcs_conf->cpu_based_2nd_exec_ctrl &=
1299 ~SECONDARY_EXEC_APIC_REGISTER_VIRT;
1302 * GUEST_PML_INDEX = 0x00000812,
1303 * PML_ADDRESS = 0x0000200e,
1305 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_PML;
1307 /* VM_FUNCTION_CONTROL = 0x00002018, */
1308 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_ENABLE_VMFUNC;
1311 * EPTP_LIST_ADDRESS = 0x00002024,
1312 * VMREAD_BITMAP = 0x00002026,
1313 * VMWRITE_BITMAP = 0x00002028,
1315 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_SHADOW_VMCS;
1318 * TSC_MULTIPLIER = 0x00002032,
1320 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_TSC_SCALING;
1323 * PLE_GAP = 0x00004020,
1324 * PLE_WINDOW = 0x00004022,
1326 vmcs_conf->cpu_based_2nd_exec_ctrl &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1329 * VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
1331 vmcs_conf->pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
1334 * GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
1335 * HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
1337 vmcs_conf->vmexit_ctrl &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
1338 vmcs_conf->vmentry_ctrl &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
1341 * Currently unsupported in KVM:
1342 * GUEST_IA32_RTIT_CTL = 0x00002814,
1345 #else /* !IS_ENABLED(CONFIG_HYPERV) */
1346 static inline void evmcs_write64(unsigned long field, u64 value) {}
1347 static inline void evmcs_write32(unsigned long field, u32 value) {}
1348 static inline void evmcs_write16(unsigned long field, u16 value) {}
1349 static inline u64 evmcs_read64(unsigned long field) { return 0; }
1350 static inline u32 evmcs_read32(unsigned long field) { return 0; }
1351 static inline u16 evmcs_read16(unsigned long field) { return 0; }
1352 static inline void evmcs_load(u64 phys_addr) {}
1353 static inline void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf) {}
1354 static inline void evmcs_touch_msr_bitmap(void) {}
1355 #endif /* IS_ENABLED(CONFIG_HYPERV) */
1357 static inline bool is_exception_n(u32 intr_info, u8 vector)
1359 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1360 INTR_INFO_VALID_MASK)) ==
1361 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1364 static inline bool is_debug(u32 intr_info)
1366 return is_exception_n(intr_info, DB_VECTOR);
1369 static inline bool is_breakpoint(u32 intr_info)
1371 return is_exception_n(intr_info, BP_VECTOR);
1374 static inline bool is_page_fault(u32 intr_info)
1376 return is_exception_n(intr_info, PF_VECTOR);
1379 static inline bool is_no_device(u32 intr_info)
1381 return is_exception_n(intr_info, NM_VECTOR);
1384 static inline bool is_invalid_opcode(u32 intr_info)
1386 return is_exception_n(intr_info, UD_VECTOR);
1389 static inline bool is_gp_fault(u32 intr_info)
1391 return is_exception_n(intr_info, GP_VECTOR);
1394 static inline bool is_external_interrupt(u32 intr_info)
1396 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1397 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1400 static inline bool is_machine_check(u32 intr_info)
1402 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1403 INTR_INFO_VALID_MASK)) ==
1404 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1407 /* Undocumented: icebp/int1 */
1408 static inline bool is_icebp(u32 intr_info)
1410 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1411 == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
1414 static inline bool cpu_has_vmx_msr_bitmap(void)
1416 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1419 static inline bool cpu_has_vmx_tpr_shadow(void)
1421 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1424 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1426 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1429 static inline bool cpu_has_secondary_exec_ctrls(void)
1431 return vmcs_config.cpu_based_exec_ctrl &
1432 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1435 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1437 return vmcs_config.cpu_based_2nd_exec_ctrl &
1438 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1441 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1443 return vmcs_config.cpu_based_2nd_exec_ctrl &
1444 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1447 static inline bool cpu_has_vmx_apic_register_virt(void)
1449 return vmcs_config.cpu_based_2nd_exec_ctrl &
1450 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1453 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1455 return vmcs_config.cpu_based_2nd_exec_ctrl &
1456 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1460 * Comment's format: document - errata name - stepping - processor name.
1462 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1464 static u32 vmx_preemption_cpu_tfms[] = {
1465 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1467 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1468 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1469 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1471 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1473 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1474 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1476 * 320767.pdf - AAP86 - B1 -
1477 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1480 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1482 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1484 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1486 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1487 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1488 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1492 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1494 u32 eax = cpuid_eax(0x00000001), i;
1496 /* Clear the reserved bits */
1497 eax &= ~(0x3U << 14 | 0xfU << 28);
1498 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1499 if (eax == vmx_preemption_cpu_tfms[i])
1505 static inline bool cpu_has_vmx_preemption_timer(void)
1507 return vmcs_config.pin_based_exec_ctrl &
1508 PIN_BASED_VMX_PREEMPTION_TIMER;
1511 static inline bool cpu_has_vmx_posted_intr(void)
1513 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1514 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1517 static inline bool cpu_has_vmx_apicv(void)
1519 return cpu_has_vmx_apic_register_virt() &&
1520 cpu_has_vmx_virtual_intr_delivery() &&
1521 cpu_has_vmx_posted_intr();
1524 static inline bool cpu_has_vmx_flexpriority(void)
1526 return cpu_has_vmx_tpr_shadow() &&
1527 cpu_has_vmx_virtualize_apic_accesses();
1530 static inline bool cpu_has_vmx_ept_execute_only(void)
1532 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1535 static inline bool cpu_has_vmx_ept_2m_page(void)
1537 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1540 static inline bool cpu_has_vmx_ept_1g_page(void)
1542 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1545 static inline bool cpu_has_vmx_ept_4levels(void)
1547 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1550 static inline bool cpu_has_vmx_ept_mt_wb(void)
1552 return vmx_capability.ept & VMX_EPTP_WB_BIT;
1555 static inline bool cpu_has_vmx_ept_5levels(void)
1557 return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1560 static inline bool cpu_has_vmx_ept_ad_bits(void)
1562 return vmx_capability.ept & VMX_EPT_AD_BIT;
1565 static inline bool cpu_has_vmx_invept_context(void)
1567 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1570 static inline bool cpu_has_vmx_invept_global(void)
1572 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1575 static inline bool cpu_has_vmx_invvpid_individual_addr(void)
1577 return vmx_capability.vpid & VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT;
1580 static inline bool cpu_has_vmx_invvpid_single(void)
1582 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1585 static inline bool cpu_has_vmx_invvpid_global(void)
1587 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1590 static inline bool cpu_has_vmx_invvpid(void)
1592 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1595 static inline bool cpu_has_vmx_ept(void)
1597 return vmcs_config.cpu_based_2nd_exec_ctrl &
1598 SECONDARY_EXEC_ENABLE_EPT;
1601 static inline bool cpu_has_vmx_unrestricted_guest(void)
1603 return vmcs_config.cpu_based_2nd_exec_ctrl &
1604 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1607 static inline bool cpu_has_vmx_ple(void)
1609 return vmcs_config.cpu_based_2nd_exec_ctrl &
1610 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1613 static inline bool cpu_has_vmx_basic_inout(void)
1615 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1618 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1620 return flexpriority_enabled && lapic_in_kernel(vcpu);
1623 static inline bool cpu_has_vmx_vpid(void)
1625 return vmcs_config.cpu_based_2nd_exec_ctrl &
1626 SECONDARY_EXEC_ENABLE_VPID;
1629 static inline bool cpu_has_vmx_rdtscp(void)
1631 return vmcs_config.cpu_based_2nd_exec_ctrl &
1632 SECONDARY_EXEC_RDTSCP;
1635 static inline bool cpu_has_vmx_invpcid(void)
1637 return vmcs_config.cpu_based_2nd_exec_ctrl &
1638 SECONDARY_EXEC_ENABLE_INVPCID;
1641 static inline bool cpu_has_virtual_nmis(void)
1643 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1646 static inline bool cpu_has_vmx_wbinvd_exit(void)
1648 return vmcs_config.cpu_based_2nd_exec_ctrl &
1649 SECONDARY_EXEC_WBINVD_EXITING;
1652 static inline bool cpu_has_vmx_shadow_vmcs(void)
1655 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1656 /* check if the cpu supports writing r/o exit information fields */
1657 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1660 return vmcs_config.cpu_based_2nd_exec_ctrl &
1661 SECONDARY_EXEC_SHADOW_VMCS;
1664 static inline bool cpu_has_vmx_pml(void)
1666 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1669 static inline bool cpu_has_vmx_tsc_scaling(void)
1671 return vmcs_config.cpu_based_2nd_exec_ctrl &
1672 SECONDARY_EXEC_TSC_SCALING;
1675 static inline bool cpu_has_vmx_vmfunc(void)
1677 return vmcs_config.cpu_based_2nd_exec_ctrl &
1678 SECONDARY_EXEC_ENABLE_VMFUNC;
1681 static bool vmx_umip_emulated(void)
1683 return vmcs_config.cpu_based_2nd_exec_ctrl &
1684 SECONDARY_EXEC_DESC;
1687 static inline bool report_flexpriority(void)
1689 return flexpriority_enabled;
1692 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1694 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low);
1698 * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE
1699 * to modify any valid field of the VMCS, or are the VM-exit
1700 * information fields read-only?
1702 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu)
1704 return to_vmx(vcpu)->nested.msrs.misc_low &
1705 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS;
1708 static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu)
1710 return to_vmx(vcpu)->nested.msrs.misc_low & VMX_MISC_ZERO_LEN_INS;
1713 static inline bool nested_cpu_supports_monitor_trap_flag(struct kvm_vcpu *vcpu)
1715 return to_vmx(vcpu)->nested.msrs.procbased_ctls_high &
1716 CPU_BASED_MONITOR_TRAP_FLAG;
1719 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1721 return vmcs12->cpu_based_vm_exec_control & bit;
1724 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1726 return (vmcs12->cpu_based_vm_exec_control &
1727 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1728 (vmcs12->secondary_vm_exec_control & bit);
1731 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1733 return vmcs12->pin_based_vm_exec_control &
1734 PIN_BASED_VMX_PREEMPTION_TIMER;
1737 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12)
1739 return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING;
1742 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1744 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1747 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1749 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1752 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1754 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
1757 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1759 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1762 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1764 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1767 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1769 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1772 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1774 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1777 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1779 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1782 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1784 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1787 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1789 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1792 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1794 return nested_cpu_has_vmfunc(vmcs12) &&
1795 (vmcs12->vm_function_control &
1796 VMX_VMFUNC_EPTP_SWITCHING);
1799 static inline bool is_nmi(u32 intr_info)
1801 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1802 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1805 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1807 unsigned long exit_qualification);
1808 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1809 struct vmcs12 *vmcs12,
1810 u32 reason, unsigned long qualification);
1812 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1816 for (i = 0; i < vmx->nmsrs; ++i)
1817 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1822 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1828 } operand = { vpid, 0, gva };
1830 asm volatile (__ex(ASM_VMX_INVVPID)
1831 /* CF==1 or ZF==1 --> rc = -1 */
1832 "; ja 1f ; ud2 ; 1:"
1833 : : "a"(&operand), "c"(ext) : "cc", "memory");
1836 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1840 } operand = {eptp, gpa};
1842 asm volatile (__ex(ASM_VMX_INVEPT)
1843 /* CF==1 or ZF==1 --> rc = -1 */
1844 "; ja 1f ; ud2 ; 1:\n"
1845 : : "a" (&operand), "c" (ext) : "cc", "memory");
1848 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1852 i = __find_msr_index(vmx, msr);
1854 return &vmx->guest_msrs[i];
1858 static void vmcs_clear(struct vmcs *vmcs)
1860 u64 phys_addr = __pa(vmcs);
1863 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1864 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1867 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1871 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1873 vmcs_clear(loaded_vmcs->vmcs);
1874 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1875 vmcs_clear(loaded_vmcs->shadow_vmcs);
1876 loaded_vmcs->cpu = -1;
1877 loaded_vmcs->launched = 0;
1880 static void vmcs_load(struct vmcs *vmcs)
1882 u64 phys_addr = __pa(vmcs);
1885 if (static_branch_unlikely(&enable_evmcs))
1886 return evmcs_load(phys_addr);
1888 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1889 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1892 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1896 #ifdef CONFIG_KEXEC_CORE
1898 * This bitmap is used to indicate whether the vmclear
1899 * operation is enabled on all cpus. All disabled by
1902 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1904 static inline void crash_enable_local_vmclear(int cpu)
1906 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1909 static inline void crash_disable_local_vmclear(int cpu)
1911 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1914 static inline int crash_local_vmclear_enabled(int cpu)
1916 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1919 static void crash_vmclear_local_loaded_vmcss(void)
1921 int cpu = raw_smp_processor_id();
1922 struct loaded_vmcs *v;
1924 if (!crash_local_vmclear_enabled(cpu))
1927 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1928 loaded_vmcss_on_cpu_link)
1929 vmcs_clear(v->vmcs);
1932 static inline void crash_enable_local_vmclear(int cpu) { }
1933 static inline void crash_disable_local_vmclear(int cpu) { }
1934 #endif /* CONFIG_KEXEC_CORE */
1936 static void __loaded_vmcs_clear(void *arg)
1938 struct loaded_vmcs *loaded_vmcs = arg;
1939 int cpu = raw_smp_processor_id();
1941 if (loaded_vmcs->cpu != cpu)
1942 return; /* vcpu migration can race with cpu offline */
1943 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1944 per_cpu(current_vmcs, cpu) = NULL;
1945 crash_disable_local_vmclear(cpu);
1946 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1949 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1950 * is before setting loaded_vmcs->vcpu to -1 which is done in
1951 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1952 * then adds the vmcs into percpu list before it is deleted.
1956 loaded_vmcs_init(loaded_vmcs);
1957 crash_enable_local_vmclear(cpu);
1960 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1962 int cpu = loaded_vmcs->cpu;
1965 smp_call_function_single(cpu,
1966 __loaded_vmcs_clear, loaded_vmcs, 1);
1969 static inline void vpid_sync_vcpu_single(int vpid)
1974 if (cpu_has_vmx_invvpid_single())
1975 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1978 static inline void vpid_sync_vcpu_global(void)
1980 if (cpu_has_vmx_invvpid_global())
1981 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1984 static inline void vpid_sync_context(int vpid)
1986 if (cpu_has_vmx_invvpid_single())
1987 vpid_sync_vcpu_single(vpid);
1989 vpid_sync_vcpu_global();
1992 static inline void ept_sync_global(void)
1994 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1997 static inline void ept_sync_context(u64 eptp)
1999 if (cpu_has_vmx_invept_context())
2000 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
2005 static __always_inline void vmcs_check16(unsigned long field)
2007 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2008 "16-bit accessor invalid for 64-bit field");
2009 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2010 "16-bit accessor invalid for 64-bit high field");
2011 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2012 "16-bit accessor invalid for 32-bit high field");
2013 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2014 "16-bit accessor invalid for natural width field");
2017 static __always_inline void vmcs_check32(unsigned long field)
2019 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2020 "32-bit accessor invalid for 16-bit field");
2021 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2022 "32-bit accessor invalid for natural width field");
2025 static __always_inline void vmcs_check64(unsigned long field)
2027 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2028 "64-bit accessor invalid for 16-bit field");
2029 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2030 "64-bit accessor invalid for 64-bit high field");
2031 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2032 "64-bit accessor invalid for 32-bit field");
2033 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
2034 "64-bit accessor invalid for natural width field");
2037 static __always_inline void vmcs_checkl(unsigned long field)
2039 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
2040 "Natural width accessor invalid for 16-bit field");
2041 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
2042 "Natural width accessor invalid for 64-bit field");
2043 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
2044 "Natural width accessor invalid for 64-bit high field");
2045 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
2046 "Natural width accessor invalid for 32-bit field");
2049 static __always_inline unsigned long __vmcs_readl(unsigned long field)
2051 unsigned long value;
2053 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
2054 : "=a"(value) : "d"(field) : "cc");
2058 static __always_inline u16 vmcs_read16(unsigned long field)
2060 vmcs_check16(field);
2061 if (static_branch_unlikely(&enable_evmcs))
2062 return evmcs_read16(field);
2063 return __vmcs_readl(field);
2066 static __always_inline u32 vmcs_read32(unsigned long field)
2068 vmcs_check32(field);
2069 if (static_branch_unlikely(&enable_evmcs))
2070 return evmcs_read32(field);
2071 return __vmcs_readl(field);
2074 static __always_inline u64 vmcs_read64(unsigned long field)
2076 vmcs_check64(field);
2077 if (static_branch_unlikely(&enable_evmcs))
2078 return evmcs_read64(field);
2079 #ifdef CONFIG_X86_64
2080 return __vmcs_readl(field);
2082 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
2086 static __always_inline unsigned long vmcs_readl(unsigned long field)
2089 if (static_branch_unlikely(&enable_evmcs))
2090 return evmcs_read64(field);
2091 return __vmcs_readl(field);
2094 static noinline void vmwrite_error(unsigned long field, unsigned long value)
2096 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
2097 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
2101 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
2105 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
2106 : "=q"(error) : "a"(value), "d"(field) : "cc");
2107 if (unlikely(error))
2108 vmwrite_error(field, value);
2111 static __always_inline void vmcs_write16(unsigned long field, u16 value)
2113 vmcs_check16(field);
2114 if (static_branch_unlikely(&enable_evmcs))
2115 return evmcs_write16(field, value);
2117 __vmcs_writel(field, value);
2120 static __always_inline void vmcs_write32(unsigned long field, u32 value)
2122 vmcs_check32(field);
2123 if (static_branch_unlikely(&enable_evmcs))
2124 return evmcs_write32(field, value);
2126 __vmcs_writel(field, value);
2129 static __always_inline void vmcs_write64(unsigned long field, u64 value)
2131 vmcs_check64(field);
2132 if (static_branch_unlikely(&enable_evmcs))
2133 return evmcs_write64(field, value);
2135 __vmcs_writel(field, value);
2136 #ifndef CONFIG_X86_64
2138 __vmcs_writel(field+1, value >> 32);
2142 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
2145 if (static_branch_unlikely(&enable_evmcs))
2146 return evmcs_write64(field, value);
2148 __vmcs_writel(field, value);
2151 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
2153 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2154 "vmcs_clear_bits does not support 64-bit fields");
2155 if (static_branch_unlikely(&enable_evmcs))
2156 return evmcs_write32(field, evmcs_read32(field) & ~mask);
2158 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
2161 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
2163 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
2164 "vmcs_set_bits does not support 64-bit fields");
2165 if (static_branch_unlikely(&enable_evmcs))
2166 return evmcs_write32(field, evmcs_read32(field) | mask);
2168 __vmcs_writel(field, __vmcs_readl(field) | mask);
2171 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
2173 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
2176 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
2178 vmcs_write32(VM_ENTRY_CONTROLS, val);
2179 vmx->vm_entry_controls_shadow = val;
2182 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
2184 if (vmx->vm_entry_controls_shadow != val)
2185 vm_entry_controls_init(vmx, val);
2188 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
2190 return vmx->vm_entry_controls_shadow;
2194 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2196 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
2199 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2201 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
2204 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
2206 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
2209 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
2211 vmcs_write32(VM_EXIT_CONTROLS, val);
2212 vmx->vm_exit_controls_shadow = val;
2215 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
2217 if (vmx->vm_exit_controls_shadow != val)
2218 vm_exit_controls_init(vmx, val);
2221 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
2223 return vmx->vm_exit_controls_shadow;
2227 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
2229 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
2232 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
2234 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
2237 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
2239 vmx->segment_cache.bitmask = 0;
2242 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
2246 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
2248 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
2249 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
2250 vmx->segment_cache.bitmask = 0;
2252 ret = vmx->segment_cache.bitmask & mask;
2253 vmx->segment_cache.bitmask |= mask;
2257 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
2259 u16 *p = &vmx->segment_cache.seg[seg].selector;
2261 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
2262 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
2266 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
2268 ulong *p = &vmx->segment_cache.seg[seg].base;
2270 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
2271 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
2275 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
2277 u32 *p = &vmx->segment_cache.seg[seg].limit;
2279 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
2280 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
2284 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
2286 u32 *p = &vmx->segment_cache.seg[seg].ar;
2288 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
2289 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
2293 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
2297 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
2298 (1u << DB_VECTOR) | (1u << AC_VECTOR);
2300 * Guest access to VMware backdoor ports could legitimately
2301 * trigger #GP because of TSS I/O permission bitmap.
2302 * We intercept those #GP and allow access to them anyway
2305 if (enable_vmware_backdoor)
2306 eb |= (1u << GP_VECTOR);
2307 if ((vcpu->guest_debug &
2308 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
2309 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
2310 eb |= 1u << BP_VECTOR;
2311 if (to_vmx(vcpu)->rmode.vm86_active)
2314 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
2316 /* When we are running a nested L2 guest and L1 specified for it a
2317 * certain exception bitmap, we must trap the same exceptions and pass
2318 * them to L1. When running L2, we will only handle the exceptions
2319 * specified above if L1 did not want them.
2321 if (is_guest_mode(vcpu))
2322 eb |= get_vmcs12(vcpu)->exception_bitmap;
2324 vmcs_write32(EXCEPTION_BITMAP, eb);
2328 * Check if MSR is intercepted for currently loaded MSR bitmap.
2330 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
2332 unsigned long *msr_bitmap;
2333 int f = sizeof(unsigned long);
2335 if (!cpu_has_vmx_msr_bitmap())
2338 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
2340 if (msr <= 0x1fff) {
2341 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2342 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2344 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2351 * Check if MSR is intercepted for L01 MSR bitmap.
2353 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
2355 unsigned long *msr_bitmap;
2356 int f = sizeof(unsigned long);
2358 if (!cpu_has_vmx_msr_bitmap())
2361 msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
2363 if (msr <= 0x1fff) {
2364 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2365 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2367 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2373 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2374 unsigned long entry, unsigned long exit)
2376 vm_entry_controls_clearbit(vmx, entry);
2377 vm_exit_controls_clearbit(vmx, exit);
2380 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
2383 struct msr_autoload *m = &vmx->msr_autoload;
2387 if (cpu_has_load_ia32_efer) {
2388 clear_atomic_switch_msr_special(vmx,
2389 VM_ENTRY_LOAD_IA32_EFER,
2390 VM_EXIT_LOAD_IA32_EFER);
2394 case MSR_CORE_PERF_GLOBAL_CTRL:
2395 if (cpu_has_load_perf_global_ctrl) {
2396 clear_atomic_switch_msr_special(vmx,
2397 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2398 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2404 for (i = 0; i < m->nr; ++i)
2405 if (m->guest[i].index == msr)
2411 m->guest[i] = m->guest[m->nr];
2412 m->host[i] = m->host[m->nr];
2413 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2414 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2417 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2418 unsigned long entry, unsigned long exit,
2419 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
2420 u64 guest_val, u64 host_val)
2422 vmcs_write64(guest_val_vmcs, guest_val);
2423 vmcs_write64(host_val_vmcs, host_val);
2424 vm_entry_controls_setbit(vmx, entry);
2425 vm_exit_controls_setbit(vmx, exit);
2428 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
2429 u64 guest_val, u64 host_val)
2432 struct msr_autoload *m = &vmx->msr_autoload;
2436 if (cpu_has_load_ia32_efer) {
2437 add_atomic_switch_msr_special(vmx,
2438 VM_ENTRY_LOAD_IA32_EFER,
2439 VM_EXIT_LOAD_IA32_EFER,
2442 guest_val, host_val);
2446 case MSR_CORE_PERF_GLOBAL_CTRL:
2447 if (cpu_has_load_perf_global_ctrl) {
2448 add_atomic_switch_msr_special(vmx,
2449 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2450 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2451 GUEST_IA32_PERF_GLOBAL_CTRL,
2452 HOST_IA32_PERF_GLOBAL_CTRL,
2453 guest_val, host_val);
2457 case MSR_IA32_PEBS_ENABLE:
2458 /* PEBS needs a quiescent period after being disabled (to write
2459 * a record). Disabling PEBS through VMX MSR swapping doesn't
2460 * provide that period, so a CPU could write host's record into
2463 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2466 for (i = 0; i < m->nr; ++i)
2467 if (m->guest[i].index == msr)
2470 if (i == NR_AUTOLOAD_MSRS) {
2471 printk_once(KERN_WARNING "Not enough msr switch entries. "
2472 "Can't add msr %x\n", msr);
2474 } else if (i == m->nr) {
2476 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2477 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2480 m->guest[i].index = msr;
2481 m->guest[i].value = guest_val;
2482 m->host[i].index = msr;
2483 m->host[i].value = host_val;
2486 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2488 u64 guest_efer = vmx->vcpu.arch.efer;
2489 u64 ignore_bits = 0;
2493 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2494 * host CPUID is more efficient than testing guest CPUID
2495 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2497 if (boot_cpu_has(X86_FEATURE_SMEP))
2498 guest_efer |= EFER_NX;
2499 else if (!(guest_efer & EFER_NX))
2500 ignore_bits |= EFER_NX;
2504 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2506 ignore_bits |= EFER_SCE;
2507 #ifdef CONFIG_X86_64
2508 ignore_bits |= EFER_LMA | EFER_LME;
2509 /* SCE is meaningful only in long mode on Intel */
2510 if (guest_efer & EFER_LMA)
2511 ignore_bits &= ~(u64)EFER_SCE;
2514 clear_atomic_switch_msr(vmx, MSR_EFER);
2517 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2518 * On CPUs that support "load IA32_EFER", always switch EFER
2519 * atomically, since it's faster than switching it manually.
2521 if (cpu_has_load_ia32_efer ||
2522 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2523 if (!(guest_efer & EFER_LMA))
2524 guest_efer &= ~EFER_LME;
2525 if (guest_efer != host_efer)
2526 add_atomic_switch_msr(vmx, MSR_EFER,
2527 guest_efer, host_efer);
2530 guest_efer &= ~ignore_bits;
2531 guest_efer |= host_efer & ignore_bits;
2533 vmx->guest_msrs[efer_offset].data = guest_efer;
2534 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2540 #ifdef CONFIG_X86_32
2542 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2543 * VMCS rather than the segment table. KVM uses this helper to figure
2544 * out the current bases to poke them into the VMCS before entry.
2546 static unsigned long segment_base(u16 selector)
2548 struct desc_struct *table;
2551 if (!(selector & ~SEGMENT_RPL_MASK))
2554 table = get_current_gdt_ro();
2556 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2557 u16 ldt_selector = kvm_read_ldt();
2559 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2562 table = (struct desc_struct *)segment_base(ldt_selector);
2564 v = get_desc_base(&table[selector >> 3]);
2569 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2571 struct vcpu_vmx *vmx = to_vmx(vcpu);
2572 #ifdef CONFIG_X86_64
2573 int cpu = raw_smp_processor_id();
2574 unsigned long fs_base, kernel_gs_base;
2578 if (vmx->host_state.loaded)
2581 vmx->host_state.loaded = 1;
2583 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2584 * allow segment selectors with cpl > 0 or ti == 1.
2586 vmx->host_state.ldt_sel = kvm_read_ldt();
2587 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2589 #ifdef CONFIG_X86_64
2590 if (likely(is_64bit_mm(current->mm))) {
2591 save_fsgs_for_kvm();
2592 vmx->host_state.fs_sel = current->thread.fsindex;
2593 vmx->host_state.gs_sel = current->thread.gsindex;
2594 fs_base = current->thread.fsbase;
2595 kernel_gs_base = current->thread.gsbase;
2598 savesegment(fs, vmx->host_state.fs_sel);
2599 savesegment(gs, vmx->host_state.gs_sel);
2600 #ifdef CONFIG_X86_64
2601 fs_base = read_msr(MSR_FS_BASE);
2602 kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
2605 if (!(vmx->host_state.fs_sel & 7)) {
2606 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2607 vmx->host_state.fs_reload_needed = 0;
2609 vmcs_write16(HOST_FS_SELECTOR, 0);
2610 vmx->host_state.fs_reload_needed = 1;
2612 if (!(vmx->host_state.gs_sel & 7))
2613 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2615 vmcs_write16(HOST_GS_SELECTOR, 0);
2616 vmx->host_state.gs_ldt_reload_needed = 1;
2619 #ifdef CONFIG_X86_64
2620 savesegment(ds, vmx->host_state.ds_sel);
2621 savesegment(es, vmx->host_state.es_sel);
2623 vmcs_writel(HOST_FS_BASE, fs_base);
2624 vmcs_writel(HOST_GS_BASE, cpu_kernelmode_gs_base(cpu));
2626 vmx->msr_host_kernel_gs_base = kernel_gs_base;
2627 if (is_long_mode(&vmx->vcpu))
2628 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2630 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2631 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2633 if (boot_cpu_has(X86_FEATURE_MPX))
2634 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2635 for (i = 0; i < vmx->save_nmsrs; ++i)
2636 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2637 vmx->guest_msrs[i].data,
2638 vmx->guest_msrs[i].mask);
2641 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2643 if (!vmx->host_state.loaded)
2646 ++vmx->vcpu.stat.host_state_reload;
2647 vmx->host_state.loaded = 0;
2648 #ifdef CONFIG_X86_64
2649 if (is_long_mode(&vmx->vcpu))
2650 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2652 if (vmx->host_state.gs_ldt_reload_needed) {
2653 kvm_load_ldt(vmx->host_state.ldt_sel);
2654 #ifdef CONFIG_X86_64
2655 load_gs_index(vmx->host_state.gs_sel);
2657 loadsegment(gs, vmx->host_state.gs_sel);
2660 if (vmx->host_state.fs_reload_needed)
2661 loadsegment(fs, vmx->host_state.fs_sel);
2662 #ifdef CONFIG_X86_64
2663 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2664 loadsegment(ds, vmx->host_state.ds_sel);
2665 loadsegment(es, vmx->host_state.es_sel);
2668 invalidate_tss_limit();
2669 #ifdef CONFIG_X86_64
2670 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2672 if (vmx->host_state.msr_host_bndcfgs)
2673 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2674 load_fixmap_gdt(raw_smp_processor_id());
2677 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2680 __vmx_load_host_state(vmx);
2684 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2686 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2687 struct pi_desc old, new;
2691 * In case of hot-plug or hot-unplug, we may have to undo
2692 * vmx_vcpu_pi_put even if there is no assigned device. And we
2693 * always keep PI.NDST up to date for simplicity: it makes the
2694 * code easier, and CPU migration is not a fast path.
2696 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2700 * First handle the simple case where no cmpxchg is necessary; just
2701 * allow posting non-urgent interrupts.
2703 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2704 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2705 * expects the VCPU to be on the blocked_vcpu_list that matches
2708 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2710 pi_clear_sn(pi_desc);
2714 /* The full case. */
2716 old.control = new.control = pi_desc->control;
2718 dest = cpu_physical_id(cpu);
2720 if (x2apic_enabled())
2723 new.ndst = (dest << 8) & 0xFF00;
2726 } while (cmpxchg64(&pi_desc->control, old.control,
2727 new.control) != old.control);
2730 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2732 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2733 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2737 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2738 * vcpu mutex is already taken.
2740 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2742 struct vcpu_vmx *vmx = to_vmx(vcpu);
2743 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2745 if (!already_loaded) {
2746 loaded_vmcs_clear(vmx->loaded_vmcs);
2747 local_irq_disable();
2748 crash_disable_local_vmclear(cpu);
2751 * Read loaded_vmcs->cpu should be before fetching
2752 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2753 * See the comments in __loaded_vmcs_clear().
2757 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2758 &per_cpu(loaded_vmcss_on_cpu, cpu));
2759 crash_enable_local_vmclear(cpu);
2763 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2764 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2765 vmcs_load(vmx->loaded_vmcs->vmcs);
2766 indirect_branch_prediction_barrier();
2769 if (!already_loaded) {
2770 void *gdt = get_current_gdt_ro();
2771 unsigned long sysenter_esp;
2773 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2776 * Linux uses per-cpu TSS and GDT, so set these when switching
2777 * processors. See 22.2.4.
2779 vmcs_writel(HOST_TR_BASE,
2780 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
2781 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
2784 * VM exits change the host TR limit to 0x67 after a VM
2785 * exit. This is okay, since 0x67 covers everything except
2786 * the IO bitmap and have have code to handle the IO bitmap
2787 * being lost after a VM exit.
2789 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2791 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2792 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2794 vmx->loaded_vmcs->cpu = cpu;
2797 /* Setup TSC multiplier */
2798 if (kvm_has_tsc_control &&
2799 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2800 decache_tsc_multiplier(vmx);
2802 vmx_vcpu_pi_load(vcpu, cpu);
2803 vmx->host_pkru = read_pkru();
2804 vmx->host_debugctlmsr = get_debugctlmsr();
2807 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2809 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2811 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2812 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2813 !kvm_vcpu_apicv_active(vcpu))
2816 /* Set SN when the vCPU is preempted */
2817 if (vcpu->preempted)
2821 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2823 vmx_vcpu_pi_put(vcpu);
2825 __vmx_load_host_state(to_vmx(vcpu));
2828 static bool emulation_required(struct kvm_vcpu *vcpu)
2830 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2833 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2836 * Return the cr0 value that a nested guest would read. This is a combination
2837 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2838 * its hypervisor (cr0_read_shadow).
2840 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2842 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2843 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2845 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2847 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2848 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2851 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2853 unsigned long rflags, save_rflags;
2855 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2856 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2857 rflags = vmcs_readl(GUEST_RFLAGS);
2858 if (to_vmx(vcpu)->rmode.vm86_active) {
2859 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2860 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2861 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2863 to_vmx(vcpu)->rflags = rflags;
2865 return to_vmx(vcpu)->rflags;
2868 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2870 unsigned long old_rflags = vmx_get_rflags(vcpu);
2872 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2873 to_vmx(vcpu)->rflags = rflags;
2874 if (to_vmx(vcpu)->rmode.vm86_active) {
2875 to_vmx(vcpu)->rmode.save_rflags = rflags;
2876 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2878 vmcs_writel(GUEST_RFLAGS, rflags);
2880 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2881 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2884 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2886 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2889 if (interruptibility & GUEST_INTR_STATE_STI)
2890 ret |= KVM_X86_SHADOW_INT_STI;
2891 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2892 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2897 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2899 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2900 u32 interruptibility = interruptibility_old;
2902 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2904 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2905 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2906 else if (mask & KVM_X86_SHADOW_INT_STI)
2907 interruptibility |= GUEST_INTR_STATE_STI;
2909 if ((interruptibility != interruptibility_old))
2910 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2913 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2917 rip = kvm_rip_read(vcpu);
2918 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2919 kvm_rip_write(vcpu, rip);
2921 /* skipping an emulated instruction also counts */
2922 vmx_set_interrupt_shadow(vcpu, 0);
2925 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2926 unsigned long exit_qual)
2928 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2929 unsigned int nr = vcpu->arch.exception.nr;
2930 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2932 if (vcpu->arch.exception.has_error_code) {
2933 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2934 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2937 if (kvm_exception_is_soft(nr))
2938 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2940 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2942 if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2943 vmx_get_nmi_mask(vcpu))
2944 intr_info |= INTR_INFO_UNBLOCK_NMI;
2946 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2950 * KVM wants to inject page-faults which it got to the guest. This function
2951 * checks whether in a nested guest, we need to inject them to L1 or L2.
2953 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
2955 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2956 unsigned int nr = vcpu->arch.exception.nr;
2958 if (nr == PF_VECTOR) {
2959 if (vcpu->arch.exception.nested_apf) {
2960 *exit_qual = vcpu->arch.apf.nested_apf_token;
2964 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2965 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2966 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2967 * can be written only when inject_pending_event runs. This should be
2968 * conditional on a new capability---if the capability is disabled,
2969 * kvm_multiple_exception would write the ancillary information to
2970 * CR2 or DR6, for backwards ABI-compatibility.
2972 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2973 vcpu->arch.exception.error_code)) {
2974 *exit_qual = vcpu->arch.cr2;
2978 if (vmcs12->exception_bitmap & (1u << nr)) {
2979 if (nr == DB_VECTOR)
2980 *exit_qual = vcpu->arch.dr6;
2990 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
2993 * Ensure that we clear the HLT state in the VMCS. We don't need to
2994 * explicitly skip the instruction because if the HLT state is set,
2995 * then the instruction is already executing and RIP has already been
2998 if (kvm_hlt_in_guest(vcpu->kvm) &&
2999 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
3000 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3003 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
3005 struct vcpu_vmx *vmx = to_vmx(vcpu);
3006 unsigned nr = vcpu->arch.exception.nr;
3007 bool has_error_code = vcpu->arch.exception.has_error_code;
3008 u32 error_code = vcpu->arch.exception.error_code;
3009 u32 intr_info = nr | INTR_INFO_VALID_MASK;
3011 if (has_error_code) {
3012 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
3013 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
3016 if (vmx->rmode.vm86_active) {
3018 if (kvm_exception_is_soft(nr))
3019 inc_eip = vcpu->arch.event_exit_inst_len;
3020 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
3021 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3025 WARN_ON_ONCE(vmx->emulation_required);
3027 if (kvm_exception_is_soft(nr)) {
3028 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3029 vmx->vcpu.arch.event_exit_inst_len);
3030 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
3032 intr_info |= INTR_TYPE_HARD_EXCEPTION;
3034 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
3036 vmx_clear_hlt(vcpu);
3039 static bool vmx_rdtscp_supported(void)
3041 return cpu_has_vmx_rdtscp();
3044 static bool vmx_invpcid_supported(void)
3046 return cpu_has_vmx_invpcid() && enable_ept;
3050 * Swap MSR entry in host/guest MSR entry array.
3052 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
3054 struct shared_msr_entry tmp;
3056 tmp = vmx->guest_msrs[to];
3057 vmx->guest_msrs[to] = vmx->guest_msrs[from];
3058 vmx->guest_msrs[from] = tmp;
3062 * Set up the vmcs to automatically save and restore system
3063 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
3064 * mode, as fiddling with msrs is very expensive.
3066 static void setup_msrs(struct vcpu_vmx *vmx)
3068 int save_nmsrs, index;
3071 #ifdef CONFIG_X86_64
3072 if (is_long_mode(&vmx->vcpu)) {
3073 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
3075 move_msr_up(vmx, index, save_nmsrs++);
3076 index = __find_msr_index(vmx, MSR_LSTAR);
3078 move_msr_up(vmx, index, save_nmsrs++);
3079 index = __find_msr_index(vmx, MSR_CSTAR);
3081 move_msr_up(vmx, index, save_nmsrs++);
3082 index = __find_msr_index(vmx, MSR_TSC_AUX);
3083 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
3084 move_msr_up(vmx, index, save_nmsrs++);
3086 * MSR_STAR is only needed on long mode guests, and only
3087 * if efer.sce is enabled.
3089 index = __find_msr_index(vmx, MSR_STAR);
3090 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
3091 move_msr_up(vmx, index, save_nmsrs++);
3094 index = __find_msr_index(vmx, MSR_EFER);
3095 if (index >= 0 && update_transition_efer(vmx, index))
3096 move_msr_up(vmx, index, save_nmsrs++);
3098 vmx->save_nmsrs = save_nmsrs;
3100 if (cpu_has_vmx_msr_bitmap())
3101 vmx_update_msr_bitmap(&vmx->vcpu);
3104 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
3106 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
3108 if (is_guest_mode(vcpu) &&
3109 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
3110 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
3112 return vcpu->arch.tsc_offset;
3116 * writes 'offset' into guest's timestamp counter offset register
3118 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
3120 if (is_guest_mode(vcpu)) {
3122 * We're here if L1 chose not to trap WRMSR to TSC. According
3123 * to the spec, this should set L1's TSC; The offset that L1
3124 * set for L2 remains unchanged, and still needs to be added
3125 * to the newly set TSC to get L2's TSC.
3127 struct vmcs12 *vmcs12;
3128 /* recalculate vmcs02.TSC_OFFSET: */
3129 vmcs12 = get_vmcs12(vcpu);
3130 vmcs_write64(TSC_OFFSET, offset +
3131 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
3132 vmcs12->tsc_offset : 0));
3134 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
3135 vmcs_read64(TSC_OFFSET), offset);
3136 vmcs_write64(TSC_OFFSET, offset);
3141 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
3142 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
3143 * all guests if the "nested" module option is off, and can also be disabled
3144 * for a single guest by disabling its VMX cpuid bit.
3146 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
3148 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
3152 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
3153 * returned for the various VMX controls MSRs when nested VMX is enabled.
3154 * The same values should also be used to verify that vmcs12 control fields are
3155 * valid during nested entry from L1 to L2.
3156 * Each of these control msrs has a low and high 32-bit half: A low bit is on
3157 * if the corresponding bit in the (32-bit) control field *must* be on, and a
3158 * bit in the high half is on if the corresponding bit in the control field
3159 * may be on. See also vmx_control_verify().
3161 static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv)
3164 memset(msrs, 0, sizeof(*msrs));
3169 * Note that as a general rule, the high half of the MSRs (bits in
3170 * the control fields which may be 1) should be initialized by the
3171 * intersection of the underlying hardware's MSR (i.e., features which
3172 * can be supported) and the list of features we want to expose -
3173 * because they are known to be properly supported in our code.
3174 * Also, usually, the low half of the MSRs (bits which must be 1) can
3175 * be set to 0, meaning that L1 may turn off any of these bits. The
3176 * reason is that if one of these bits is necessary, it will appear
3177 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
3178 * fields of vmcs01 and vmcs02, will turn these bits off - and
3179 * nested_vmx_exit_reflected() will not pass related exits to L1.
3180 * These rules have exceptions below.
3183 /* pin-based controls */
3184 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
3185 msrs->pinbased_ctls_low,
3186 msrs->pinbased_ctls_high);
3187 msrs->pinbased_ctls_low |=
3188 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3189 msrs->pinbased_ctls_high &=
3190 PIN_BASED_EXT_INTR_MASK |
3191 PIN_BASED_NMI_EXITING |
3192 PIN_BASED_VIRTUAL_NMIS |
3193 (apicv ? PIN_BASED_POSTED_INTR : 0);
3194 msrs->pinbased_ctls_high |=
3195 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3196 PIN_BASED_VMX_PREEMPTION_TIMER;
3199 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
3200 msrs->exit_ctls_low,
3201 msrs->exit_ctls_high);
3202 msrs->exit_ctls_low =
3203 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3205 msrs->exit_ctls_high &=
3206 #ifdef CONFIG_X86_64
3207 VM_EXIT_HOST_ADDR_SPACE_SIZE |
3209 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
3210 msrs->exit_ctls_high |=
3211 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
3212 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
3213 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
3215 if (kvm_mpx_supported())
3216 msrs->exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
3218 /* We support free control of debug control saving. */
3219 msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
3221 /* entry controls */
3222 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
3223 msrs->entry_ctls_low,
3224 msrs->entry_ctls_high);
3225 msrs->entry_ctls_low =
3226 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3227 msrs->entry_ctls_high &=
3228 #ifdef CONFIG_X86_64
3229 VM_ENTRY_IA32E_MODE |
3231 VM_ENTRY_LOAD_IA32_PAT;
3232 msrs->entry_ctls_high |=
3233 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
3234 if (kvm_mpx_supported())
3235 msrs->entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
3237 /* We support free control of debug control loading. */
3238 msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
3240 /* cpu-based controls */
3241 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
3242 msrs->procbased_ctls_low,
3243 msrs->procbased_ctls_high);
3244 msrs->procbased_ctls_low =
3245 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3246 msrs->procbased_ctls_high &=
3247 CPU_BASED_VIRTUAL_INTR_PENDING |
3248 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
3249 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
3250 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
3251 CPU_BASED_CR3_STORE_EXITING |
3252 #ifdef CONFIG_X86_64
3253 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
3255 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
3256 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
3257 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
3258 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
3259 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3261 * We can allow some features even when not supported by the
3262 * hardware. For example, L1 can specify an MSR bitmap - and we
3263 * can use it to avoid exits to L1 - even when L0 runs L2
3264 * without MSR bitmaps.
3266 msrs->procbased_ctls_high |=
3267 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
3268 CPU_BASED_USE_MSR_BITMAPS;
3270 /* We support free control of CR3 access interception. */
3271 msrs->procbased_ctls_low &=
3272 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
3275 * secondary cpu-based controls. Do not include those that
3276 * depend on CPUID bits, they are added later by vmx_cpuid_update.
3278 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
3279 msrs->secondary_ctls_low,
3280 msrs->secondary_ctls_high);
3281 msrs->secondary_ctls_low = 0;
3282 msrs->secondary_ctls_high &=
3283 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3284 SECONDARY_EXEC_DESC |
3285 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3286 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3287 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3288 SECONDARY_EXEC_WBINVD_EXITING;
3291 /* nested EPT: emulate EPT also to L1 */
3292 msrs->secondary_ctls_high |=
3293 SECONDARY_EXEC_ENABLE_EPT;
3294 msrs->ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
3295 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
3296 if (cpu_has_vmx_ept_execute_only())
3298 VMX_EPT_EXECUTE_ONLY_BIT;
3299 msrs->ept_caps &= vmx_capability.ept;
3300 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
3301 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
3302 VMX_EPT_1GB_PAGE_BIT;
3303 if (enable_ept_ad_bits) {
3304 msrs->secondary_ctls_high |=
3305 SECONDARY_EXEC_ENABLE_PML;
3306 msrs->ept_caps |= VMX_EPT_AD_BIT;
3310 if (cpu_has_vmx_vmfunc()) {
3311 msrs->secondary_ctls_high |=
3312 SECONDARY_EXEC_ENABLE_VMFUNC;
3314 * Advertise EPTP switching unconditionally
3315 * since we emulate it
3318 msrs->vmfunc_controls =
3319 VMX_VMFUNC_EPTP_SWITCHING;
3323 * Old versions of KVM use the single-context version without
3324 * checking for support, so declare that it is supported even
3325 * though it is treated as global context. The alternative is
3326 * not failing the single-context invvpid, and it is worse.
3329 msrs->secondary_ctls_high |=
3330 SECONDARY_EXEC_ENABLE_VPID;
3331 msrs->vpid_caps = VMX_VPID_INVVPID_BIT |
3332 VMX_VPID_EXTENT_SUPPORTED_MASK;
3335 if (enable_unrestricted_guest)
3336 msrs->secondary_ctls_high |=
3337 SECONDARY_EXEC_UNRESTRICTED_GUEST;
3339 /* miscellaneous data */
3340 rdmsr(MSR_IA32_VMX_MISC,
3343 msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA;
3345 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS |
3346 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
3347 VMX_MISC_ACTIVITY_HLT;
3348 msrs->misc_high = 0;
3351 * This MSR reports some information about VMX support. We
3352 * should return information about the VMX we emulate for the
3353 * guest, and the VMCS structure we give it - not about the
3354 * VMX support of the underlying hardware.
3358 VMX_BASIC_TRUE_CTLS |
3359 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
3360 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
3362 if (cpu_has_vmx_basic_inout())
3363 msrs->basic |= VMX_BASIC_INOUT;
3366 * These MSRs specify bits which the guest must keep fixed on
3367 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
3368 * We picked the standard core2 setting.
3370 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
3371 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
3372 msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON;
3373 msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
3375 /* These MSRs specify bits which the guest must keep fixed off. */
3376 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
3377 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
3379 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
3380 msrs->vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1;
3384 * if fixed0[i] == 1: val[i] must be 1
3385 * if fixed1[i] == 0: val[i] must be 0
3387 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
3389 return ((val & fixed1) | fixed0) == val;
3392 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
3394 return fixed_bits_valid(control, low, high);
3397 static inline u64 vmx_control_msr(u32 low, u32 high)
3399 return low | ((u64)high << 32);
3402 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
3407 return (superset | subset) == superset;
3410 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
3412 const u64 feature_and_reserved =
3413 /* feature (except bit 48; see below) */
3414 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
3416 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
3417 u64 vmx_basic = vmx->nested.msrs.basic;
3419 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
3423 * KVM does not emulate a version of VMX that constrains physical
3424 * addresses of VMX structures (e.g. VMCS) to 32-bits.
3426 if (data & BIT_ULL(48))
3429 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
3430 vmx_basic_vmcs_revision_id(data))
3433 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
3436 vmx->nested.msrs.basic = data;
3441 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3446 switch (msr_index) {
3447 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3448 lowp = &vmx->nested.msrs.pinbased_ctls_low;
3449 highp = &vmx->nested.msrs.pinbased_ctls_high;
3451 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3452 lowp = &vmx->nested.msrs.procbased_ctls_low;
3453 highp = &vmx->nested.msrs.procbased_ctls_high;
3455 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3456 lowp = &vmx->nested.msrs.exit_ctls_low;
3457 highp = &vmx->nested.msrs.exit_ctls_high;
3459 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3460 lowp = &vmx->nested.msrs.entry_ctls_low;
3461 highp = &vmx->nested.msrs.entry_ctls_high;
3463 case MSR_IA32_VMX_PROCBASED_CTLS2:
3464 lowp = &vmx->nested.msrs.secondary_ctls_low;
3465 highp = &vmx->nested.msrs.secondary_ctls_high;
3471 supported = vmx_control_msr(*lowp, *highp);
3473 /* Check must-be-1 bits are still 1. */
3474 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3477 /* Check must-be-0 bits are still 0. */
3478 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3482 *highp = data >> 32;
3486 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3488 const u64 feature_and_reserved_bits =
3490 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3491 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3493 GENMASK_ULL(13, 9) | BIT_ULL(31);
3496 vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low,
3497 vmx->nested.msrs.misc_high);
3499 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3502 if ((vmx->nested.msrs.pinbased_ctls_high &
3503 PIN_BASED_VMX_PREEMPTION_TIMER) &&
3504 vmx_misc_preemption_timer_rate(data) !=
3505 vmx_misc_preemption_timer_rate(vmx_misc))
3508 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3511 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3514 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3517 vmx->nested.msrs.misc_low = data;
3518 vmx->nested.msrs.misc_high = data >> 32;
3521 * If L1 has read-only VM-exit information fields, use the
3522 * less permissive vmx_vmwrite_bitmap to specify write
3523 * permissions for the shadow VMCS.
3525 if (enable_shadow_vmcs && !nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
3526 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
3531 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3533 u64 vmx_ept_vpid_cap;
3535 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps,
3536 vmx->nested.msrs.vpid_caps);
3538 /* Every bit is either reserved or a feature bit. */
3539 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3542 vmx->nested.msrs.ept_caps = data;
3543 vmx->nested.msrs.vpid_caps = data >> 32;
3547 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3551 switch (msr_index) {
3552 case MSR_IA32_VMX_CR0_FIXED0:
3553 msr = &vmx->nested.msrs.cr0_fixed0;
3555 case MSR_IA32_VMX_CR4_FIXED0:
3556 msr = &vmx->nested.msrs.cr4_fixed0;
3563 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3564 * must be 1 in the restored value.
3566 if (!is_bitwise_subset(data, *msr, -1ULL))
3574 * Called when userspace is restoring VMX MSRs.
3576 * Returns 0 on success, non-0 otherwise.
3578 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3580 struct vcpu_vmx *vmx = to_vmx(vcpu);
3583 * Don't allow changes to the VMX capability MSRs while the vCPU
3584 * is in VMX operation.
3586 if (vmx->nested.vmxon)
3589 switch (msr_index) {
3590 case MSR_IA32_VMX_BASIC:
3591 return vmx_restore_vmx_basic(vmx, data);
3592 case MSR_IA32_VMX_PINBASED_CTLS:
3593 case MSR_IA32_VMX_PROCBASED_CTLS:
3594 case MSR_IA32_VMX_EXIT_CTLS:
3595 case MSR_IA32_VMX_ENTRY_CTLS:
3597 * The "non-true" VMX capability MSRs are generated from the
3598 * "true" MSRs, so we do not support restoring them directly.
3600 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3601 * should restore the "true" MSRs with the must-be-1 bits
3602 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3603 * DEFAULT SETTINGS".
3606 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3607 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3608 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3609 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3610 case MSR_IA32_VMX_PROCBASED_CTLS2:
3611 return vmx_restore_control_msr(vmx, msr_index, data);
3612 case MSR_IA32_VMX_MISC:
3613 return vmx_restore_vmx_misc(vmx, data);
3614 case MSR_IA32_VMX_CR0_FIXED0:
3615 case MSR_IA32_VMX_CR4_FIXED0:
3616 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3617 case MSR_IA32_VMX_CR0_FIXED1:
3618 case MSR_IA32_VMX_CR4_FIXED1:
3620 * These MSRs are generated based on the vCPU's CPUID, so we
3621 * do not support restoring them directly.
3624 case MSR_IA32_VMX_EPT_VPID_CAP:
3625 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3626 case MSR_IA32_VMX_VMCS_ENUM:
3627 vmx->nested.msrs.vmcs_enum = data;
3631 * The rest of the VMX capability MSRs do not support restore.
3637 /* Returns 0 on success, non-0 otherwise. */
3638 static int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata)
3640 switch (msr_index) {
3641 case MSR_IA32_VMX_BASIC:
3642 *pdata = msrs->basic;
3644 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3645 case MSR_IA32_VMX_PINBASED_CTLS:
3646 *pdata = vmx_control_msr(
3647 msrs->pinbased_ctls_low,
3648 msrs->pinbased_ctls_high);
3649 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3650 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3652 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3653 case MSR_IA32_VMX_PROCBASED_CTLS:
3654 *pdata = vmx_control_msr(
3655 msrs->procbased_ctls_low,
3656 msrs->procbased_ctls_high);
3657 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3658 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3660 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3661 case MSR_IA32_VMX_EXIT_CTLS:
3662 *pdata = vmx_control_msr(
3663 msrs->exit_ctls_low,
3664 msrs->exit_ctls_high);
3665 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3666 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3668 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3669 case MSR_IA32_VMX_ENTRY_CTLS:
3670 *pdata = vmx_control_msr(
3671 msrs->entry_ctls_low,
3672 msrs->entry_ctls_high);
3673 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3674 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3676 case MSR_IA32_VMX_MISC:
3677 *pdata = vmx_control_msr(
3681 case MSR_IA32_VMX_CR0_FIXED0:
3682 *pdata = msrs->cr0_fixed0;
3684 case MSR_IA32_VMX_CR0_FIXED1:
3685 *pdata = msrs->cr0_fixed1;
3687 case MSR_IA32_VMX_CR4_FIXED0:
3688 *pdata = msrs->cr4_fixed0;
3690 case MSR_IA32_VMX_CR4_FIXED1:
3691 *pdata = msrs->cr4_fixed1;
3693 case MSR_IA32_VMX_VMCS_ENUM:
3694 *pdata = msrs->vmcs_enum;
3696 case MSR_IA32_VMX_PROCBASED_CTLS2:
3697 *pdata = vmx_control_msr(
3698 msrs->secondary_ctls_low,
3699 msrs->secondary_ctls_high);
3701 case MSR_IA32_VMX_EPT_VPID_CAP:
3702 *pdata = msrs->ept_caps |
3703 ((u64)msrs->vpid_caps << 32);
3705 case MSR_IA32_VMX_VMFUNC:
3706 *pdata = msrs->vmfunc_controls;
3715 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3718 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3720 return !(val & ~valid_bits);
3723 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
3725 switch (msr->index) {
3726 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3729 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
3738 * Reads an msr value (of 'msr_index') into 'pdata'.
3739 * Returns 0 on success, non-0 otherwise.
3740 * Assumes vcpu_load() was already called.
3742 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3744 struct vcpu_vmx *vmx = to_vmx(vcpu);
3745 struct shared_msr_entry *msr;
3747 switch (msr_info->index) {
3748 #ifdef CONFIG_X86_64
3750 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3753 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3755 case MSR_KERNEL_GS_BASE:
3756 vmx_load_host_state(vmx);
3757 msr_info->data = vmx->msr_guest_kernel_gs_base;
3761 return kvm_get_msr_common(vcpu, msr_info);
3762 case MSR_IA32_SPEC_CTRL:
3763 if (!msr_info->host_initiated &&
3764 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3767 msr_info->data = to_vmx(vcpu)->spec_ctrl;
3769 case MSR_IA32_ARCH_CAPABILITIES:
3770 if (!msr_info->host_initiated &&
3771 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3773 msr_info->data = to_vmx(vcpu)->arch_capabilities;
3775 case MSR_IA32_SYSENTER_CS:
3776 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3778 case MSR_IA32_SYSENTER_EIP:
3779 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3781 case MSR_IA32_SYSENTER_ESP:
3782 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3784 case MSR_IA32_BNDCFGS:
3785 if (!kvm_mpx_supported() ||
3786 (!msr_info->host_initiated &&
3787 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3789 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3791 case MSR_IA32_MCG_EXT_CTL:
3792 if (!msr_info->host_initiated &&
3793 !(vmx->msr_ia32_feature_control &
3794 FEATURE_CONTROL_LMCE))
3796 msr_info->data = vcpu->arch.mcg_ext_ctl;
3798 case MSR_IA32_FEATURE_CONTROL:
3799 msr_info->data = vmx->msr_ia32_feature_control;
3801 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3802 if (!nested_vmx_allowed(vcpu))
3804 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
3807 if (!vmx_xsaves_supported())
3809 msr_info->data = vcpu->arch.ia32_xss;
3812 if (!msr_info->host_initiated &&
3813 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3815 /* Otherwise falls through */
3817 msr = find_msr_entry(vmx, msr_info->index);
3819 msr_info->data = msr->data;
3822 return kvm_get_msr_common(vcpu, msr_info);
3828 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3831 * Writes msr value into into the appropriate "register".
3832 * Returns 0 on success, non-0 otherwise.
3833 * Assumes vcpu_load() was already called.
3835 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3837 struct vcpu_vmx *vmx = to_vmx(vcpu);
3838 struct shared_msr_entry *msr;
3840 u32 msr_index = msr_info->index;
3841 u64 data = msr_info->data;
3843 switch (msr_index) {
3845 ret = kvm_set_msr_common(vcpu, msr_info);
3847 #ifdef CONFIG_X86_64
3849 vmx_segment_cache_clear(vmx);
3850 vmcs_writel(GUEST_FS_BASE, data);
3853 vmx_segment_cache_clear(vmx);
3854 vmcs_writel(GUEST_GS_BASE, data);
3856 case MSR_KERNEL_GS_BASE:
3857 vmx_load_host_state(vmx);
3858 vmx->msr_guest_kernel_gs_base = data;
3861 case MSR_IA32_SYSENTER_CS:
3862 vmcs_write32(GUEST_SYSENTER_CS, data);
3864 case MSR_IA32_SYSENTER_EIP:
3865 vmcs_writel(GUEST_SYSENTER_EIP, data);
3867 case MSR_IA32_SYSENTER_ESP:
3868 vmcs_writel(GUEST_SYSENTER_ESP, data);
3870 case MSR_IA32_BNDCFGS:
3871 if (!kvm_mpx_supported() ||
3872 (!msr_info->host_initiated &&
3873 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3875 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
3876 (data & MSR_IA32_BNDCFGS_RSVD))
3878 vmcs_write64(GUEST_BNDCFGS, data);
3880 case MSR_IA32_SPEC_CTRL:
3881 if (!msr_info->host_initiated &&
3882 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3885 /* The STIBP bit doesn't fault even if it's not advertised */
3886 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
3889 vmx->spec_ctrl = data;
3896 * When it's written (to non-zero) for the first time, pass
3900 * The handling of the MSR bitmap for L2 guests is done in
3901 * nested_vmx_merge_msr_bitmap. We should not touch the
3902 * vmcs02.msr_bitmap here since it gets completely overwritten
3903 * in the merging. We update the vmcs01 here for L1 as well
3904 * since it will end up touching the MSR anyway now.
3906 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
3910 case MSR_IA32_PRED_CMD:
3911 if (!msr_info->host_initiated &&
3912 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3915 if (data & ~PRED_CMD_IBPB)
3921 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3925 * When it's written (to non-zero) for the first time, pass
3929 * The handling of the MSR bitmap for L2 guests is done in
3930 * nested_vmx_merge_msr_bitmap. We should not touch the
3931 * vmcs02.msr_bitmap here since it gets completely overwritten
3934 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
3937 case MSR_IA32_ARCH_CAPABILITIES:
3938 if (!msr_info->host_initiated)
3940 vmx->arch_capabilities = data;
3942 case MSR_IA32_CR_PAT:
3943 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3944 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3946 vmcs_write64(GUEST_IA32_PAT, data);
3947 vcpu->arch.pat = data;
3950 ret = kvm_set_msr_common(vcpu, msr_info);
3952 case MSR_IA32_TSC_ADJUST:
3953 ret = kvm_set_msr_common(vcpu, msr_info);
3955 case MSR_IA32_MCG_EXT_CTL:
3956 if ((!msr_info->host_initiated &&
3957 !(to_vmx(vcpu)->msr_ia32_feature_control &
3958 FEATURE_CONTROL_LMCE)) ||
3959 (data & ~MCG_EXT_CTL_LMCE_EN))
3961 vcpu->arch.mcg_ext_ctl = data;
3963 case MSR_IA32_FEATURE_CONTROL:
3964 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3965 (to_vmx(vcpu)->msr_ia32_feature_control &
3966 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3968 vmx->msr_ia32_feature_control = data;
3969 if (msr_info->host_initiated && data == 0)
3970 vmx_leave_nested(vcpu);
3972 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3973 if (!msr_info->host_initiated)
3974 return 1; /* they are read-only */
3975 if (!nested_vmx_allowed(vcpu))
3977 return vmx_set_vmx_msr(vcpu, msr_index, data);
3979 if (!vmx_xsaves_supported())
3982 * The only supported bit as of Skylake is bit 8, but
3983 * it is not supported on KVM.
3987 vcpu->arch.ia32_xss = data;
3988 if (vcpu->arch.ia32_xss != host_xss)
3989 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3990 vcpu->arch.ia32_xss, host_xss);
3992 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3995 if (!msr_info->host_initiated &&
3996 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3998 /* Check reserved bit, higher 32 bits should be zero */
3999 if ((data >> 32) != 0)
4001 /* Otherwise falls through */
4003 msr = find_msr_entry(vmx, msr_index);
4005 u64 old_msr_data = msr->data;
4007 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
4009 ret = kvm_set_shared_msr(msr->index, msr->data,
4013 msr->data = old_msr_data;
4017 ret = kvm_set_msr_common(vcpu, msr_info);
4023 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
4025 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
4028 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
4031 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
4033 case VCPU_EXREG_PDPTR:
4035 ept_save_pdptrs(vcpu);
4042 static __init int cpu_has_kvm_support(void)
4044 return cpu_has_vmx();
4047 static __init int vmx_disabled_by_bios(void)
4051 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
4052 if (msr & FEATURE_CONTROL_LOCKED) {
4053 /* launched w/ TXT and VMX disabled */
4054 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4057 /* launched w/o TXT and VMX only enabled w/ TXT */
4058 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4059 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
4060 && !tboot_enabled()) {
4061 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
4062 "activate TXT before enabling KVM\n");
4065 /* launched w/o TXT and VMX disabled */
4066 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
4067 && !tboot_enabled())
4074 static void kvm_cpu_vmxon(u64 addr)
4076 cr4_set_bits(X86_CR4_VMXE);
4077 intel_pt_handle_vmx(1);
4079 asm volatile (ASM_VMX_VMXON_RAX
4080 : : "a"(&addr), "m"(addr)
4084 static int hardware_enable(void)
4086 int cpu = raw_smp_processor_id();
4087 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
4090 if (cr4_read_shadow() & X86_CR4_VMXE)
4094 * This can happen if we hot-added a CPU but failed to allocate
4095 * VP assist page for it.
4097 if (static_branch_unlikely(&enable_evmcs) &&
4098 !hv_get_vp_assist_page(cpu))
4101 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
4102 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
4103 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
4106 * Now we can enable the vmclear operation in kdump
4107 * since the loaded_vmcss_on_cpu list on this cpu
4108 * has been initialized.
4110 * Though the cpu is not in VMX operation now, there
4111 * is no problem to enable the vmclear operation
4112 * for the loaded_vmcss_on_cpu list is empty!
4114 crash_enable_local_vmclear(cpu);
4116 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
4118 test_bits = FEATURE_CONTROL_LOCKED;
4119 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
4120 if (tboot_enabled())
4121 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
4123 if ((old & test_bits) != test_bits) {
4124 /* enable and lock */
4125 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
4127 kvm_cpu_vmxon(phys_addr);
4134 static void vmclear_local_loaded_vmcss(void)
4136 int cpu = raw_smp_processor_id();
4137 struct loaded_vmcs *v, *n;
4139 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
4140 loaded_vmcss_on_cpu_link)
4141 __loaded_vmcs_clear(v);
4145 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
4148 static void kvm_cpu_vmxoff(void)
4150 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
4152 intel_pt_handle_vmx(0);
4153 cr4_clear_bits(X86_CR4_VMXE);
4156 static void hardware_disable(void)
4158 vmclear_local_loaded_vmcss();
4162 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
4163 u32 msr, u32 *result)
4165 u32 vmx_msr_low, vmx_msr_high;
4166 u32 ctl = ctl_min | ctl_opt;
4168 rdmsr(msr, vmx_msr_low, vmx_msr_high);
4170 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
4171 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
4173 /* Ensure minimum (required) set of control bits are supported. */
4181 static __init bool allow_1_setting(u32 msr, u32 ctl)
4183 u32 vmx_msr_low, vmx_msr_high;
4185 rdmsr(msr, vmx_msr_low, vmx_msr_high);
4186 return vmx_msr_high & ctl;
4189 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
4191 u32 vmx_msr_low, vmx_msr_high;
4192 u32 min, opt, min2, opt2;
4193 u32 _pin_based_exec_control = 0;
4194 u32 _cpu_based_exec_control = 0;
4195 u32 _cpu_based_2nd_exec_control = 0;
4196 u32 _vmexit_control = 0;
4197 u32 _vmentry_control = 0;
4199 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
4200 min = CPU_BASED_HLT_EXITING |
4201 #ifdef CONFIG_X86_64
4202 CPU_BASED_CR8_LOAD_EXITING |
4203 CPU_BASED_CR8_STORE_EXITING |
4205 CPU_BASED_CR3_LOAD_EXITING |
4206 CPU_BASED_CR3_STORE_EXITING |
4207 CPU_BASED_UNCOND_IO_EXITING |
4208 CPU_BASED_MOV_DR_EXITING |
4209 CPU_BASED_USE_TSC_OFFSETING |
4210 CPU_BASED_MWAIT_EXITING |
4211 CPU_BASED_MONITOR_EXITING |
4212 CPU_BASED_INVLPG_EXITING |
4213 CPU_BASED_RDPMC_EXITING;
4215 opt = CPU_BASED_TPR_SHADOW |
4216 CPU_BASED_USE_MSR_BITMAPS |
4217 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
4218 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
4219 &_cpu_based_exec_control) < 0)
4221 #ifdef CONFIG_X86_64
4222 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4223 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
4224 ~CPU_BASED_CR8_STORE_EXITING;
4226 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
4228 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4229 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4230 SECONDARY_EXEC_WBINVD_EXITING |
4231 SECONDARY_EXEC_ENABLE_VPID |
4232 SECONDARY_EXEC_ENABLE_EPT |
4233 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4234 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
4235 SECONDARY_EXEC_DESC |
4236 SECONDARY_EXEC_RDTSCP |
4237 SECONDARY_EXEC_ENABLE_INVPCID |
4238 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4239 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4240 SECONDARY_EXEC_SHADOW_VMCS |
4241 SECONDARY_EXEC_XSAVES |
4242 SECONDARY_EXEC_RDSEED_EXITING |
4243 SECONDARY_EXEC_RDRAND_EXITING |
4244 SECONDARY_EXEC_ENABLE_PML |
4245 SECONDARY_EXEC_TSC_SCALING |
4246 SECONDARY_EXEC_ENABLE_VMFUNC;
4247 if (adjust_vmx_controls(min2, opt2,
4248 MSR_IA32_VMX_PROCBASED_CTLS2,
4249 &_cpu_based_2nd_exec_control) < 0)
4252 #ifndef CONFIG_X86_64
4253 if (!(_cpu_based_2nd_exec_control &
4254 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
4255 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
4258 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
4259 _cpu_based_2nd_exec_control &= ~(
4260 SECONDARY_EXEC_APIC_REGISTER_VIRT |
4261 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4262 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4264 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
4265 &vmx_capability.ept, &vmx_capability.vpid);
4267 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
4268 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
4270 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
4271 CPU_BASED_CR3_STORE_EXITING |
4272 CPU_BASED_INVLPG_EXITING);
4273 } else if (vmx_capability.ept) {
4274 vmx_capability.ept = 0;
4275 pr_warn_once("EPT CAP should not exist if not support "
4276 "1-setting enable EPT VM-execution control\n");
4278 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
4279 vmx_capability.vpid) {
4280 vmx_capability.vpid = 0;
4281 pr_warn_once("VPID CAP should not exist if not support "
4282 "1-setting enable VPID VM-execution control\n");
4285 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
4286 #ifdef CONFIG_X86_64
4287 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
4289 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
4290 VM_EXIT_CLEAR_BNDCFGS;
4291 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
4292 &_vmexit_control) < 0)
4295 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
4296 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
4297 PIN_BASED_VMX_PREEMPTION_TIMER;
4298 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
4299 &_pin_based_exec_control) < 0)
4302 if (cpu_has_broken_vmx_preemption_timer())
4303 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4304 if (!(_cpu_based_2nd_exec_control &
4305 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
4306 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
4308 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
4309 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
4310 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
4311 &_vmentry_control) < 0)
4314 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
4316 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
4317 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
4320 #ifdef CONFIG_X86_64
4321 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
4322 if (vmx_msr_high & (1u<<16))
4326 /* Require Write-Back (WB) memory type for VMCS accesses. */
4327 if (((vmx_msr_high >> 18) & 15) != 6)
4330 vmcs_conf->size = vmx_msr_high & 0x1fff;
4331 vmcs_conf->order = get_order(vmcs_conf->size);
4332 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
4334 vmcs_conf->revision_id = vmx_msr_low;
4336 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
4337 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
4338 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
4339 vmcs_conf->vmexit_ctrl = _vmexit_control;
4340 vmcs_conf->vmentry_ctrl = _vmentry_control;
4342 if (static_branch_unlikely(&enable_evmcs))
4343 evmcs_sanitize_exec_ctrls(vmcs_conf);
4345 cpu_has_load_ia32_efer =
4346 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4347 VM_ENTRY_LOAD_IA32_EFER)
4348 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4349 VM_EXIT_LOAD_IA32_EFER);
4351 cpu_has_load_perf_global_ctrl =
4352 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
4353 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
4354 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
4355 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
4358 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
4359 * but due to errata below it can't be used. Workaround is to use
4360 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
4362 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
4367 * BC86,AAY89,BD102 (model 44)
4371 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
4372 switch (boot_cpu_data.x86_model) {
4378 cpu_has_load_perf_global_ctrl = false;
4379 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
4380 "does not work properly. Using workaround\n");
4387 if (boot_cpu_has(X86_FEATURE_XSAVES))
4388 rdmsrl(MSR_IA32_XSS, host_xss);
4393 static struct vmcs *alloc_vmcs_cpu(int cpu)
4395 int node = cpu_to_node(cpu);
4399 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
4402 vmcs = page_address(pages);
4403 memset(vmcs, 0, vmcs_config.size);
4405 /* KVM supports Enlightened VMCS v1 only */
4406 if (static_branch_unlikely(&enable_evmcs))
4407 vmcs->revision_id = KVM_EVMCS_VERSION;
4409 vmcs->revision_id = vmcs_config.revision_id;
4414 static void free_vmcs(struct vmcs *vmcs)
4416 free_pages((unsigned long)vmcs, vmcs_config.order);
4420 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
4422 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4424 if (!loaded_vmcs->vmcs)
4426 loaded_vmcs_clear(loaded_vmcs);
4427 free_vmcs(loaded_vmcs->vmcs);
4428 loaded_vmcs->vmcs = NULL;
4429 if (loaded_vmcs->msr_bitmap)
4430 free_page((unsigned long)loaded_vmcs->msr_bitmap);
4431 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
4434 static struct vmcs *alloc_vmcs(void)
4436 return alloc_vmcs_cpu(raw_smp_processor_id());
4439 static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
4441 loaded_vmcs->vmcs = alloc_vmcs();
4442 if (!loaded_vmcs->vmcs)
4445 loaded_vmcs->shadow_vmcs = NULL;
4446 loaded_vmcs_init(loaded_vmcs);
4448 if (cpu_has_vmx_msr_bitmap()) {
4449 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
4450 if (!loaded_vmcs->msr_bitmap)
4452 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
4454 if (IS_ENABLED(CONFIG_HYPERV) &&
4455 static_branch_unlikely(&enable_evmcs) &&
4456 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
4457 struct hv_enlightened_vmcs *evmcs =
4458 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
4460 evmcs->hv_enlightenments_control.msr_bitmap = 1;
4466 free_loaded_vmcs(loaded_vmcs);
4470 static void free_kvm_area(void)
4474 for_each_possible_cpu(cpu) {
4475 free_vmcs(per_cpu(vmxarea, cpu));
4476 per_cpu(vmxarea, cpu) = NULL;
4480 enum vmcs_field_width {
4481 VMCS_FIELD_WIDTH_U16 = 0,
4482 VMCS_FIELD_WIDTH_U64 = 1,
4483 VMCS_FIELD_WIDTH_U32 = 2,
4484 VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
4487 static inline int vmcs_field_width(unsigned long field)
4489 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
4490 return VMCS_FIELD_WIDTH_U32;
4491 return (field >> 13) & 0x3 ;
4494 static inline int vmcs_field_readonly(unsigned long field)
4496 return (((field >> 10) & 0x3) == 1);
4499 static void init_vmcs_shadow_fields(void)
4503 for (i = j = 0; i < max_shadow_read_only_fields; i++) {
4504 u16 field = shadow_read_only_fields[i];
4505 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4506 (i + 1 == max_shadow_read_only_fields ||
4507 shadow_read_only_fields[i + 1] != field + 1))
4508 pr_err("Missing field from shadow_read_only_field %x\n",
4511 clear_bit(field, vmx_vmread_bitmap);
4512 #ifdef CONFIG_X86_64
4517 shadow_read_only_fields[j] = field;
4520 max_shadow_read_only_fields = j;
4522 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
4523 u16 field = shadow_read_write_fields[i];
4524 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 &&
4525 (i + 1 == max_shadow_read_write_fields ||
4526 shadow_read_write_fields[i + 1] != field + 1))
4527 pr_err("Missing field from shadow_read_write_field %x\n",
4531 * PML and the preemption timer can be emulated, but the
4532 * processor cannot vmwrite to fields that don't exist
4536 case GUEST_PML_INDEX:
4537 if (!cpu_has_vmx_pml())
4540 case VMX_PREEMPTION_TIMER_VALUE:
4541 if (!cpu_has_vmx_preemption_timer())
4544 case GUEST_INTR_STATUS:
4545 if (!cpu_has_vmx_apicv())
4552 clear_bit(field, vmx_vmwrite_bitmap);
4553 clear_bit(field, vmx_vmread_bitmap);
4554 #ifdef CONFIG_X86_64
4559 shadow_read_write_fields[j] = field;
4562 max_shadow_read_write_fields = j;
4565 static __init int alloc_kvm_area(void)
4569 for_each_possible_cpu(cpu) {
4572 vmcs = alloc_vmcs_cpu(cpu);
4579 * When eVMCS is enabled, alloc_vmcs_cpu() sets
4580 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
4581 * revision_id reported by MSR_IA32_VMX_BASIC.
4583 * However, even though not explictly documented by
4584 * TLFS, VMXArea passed as VMXON argument should
4585 * still be marked with revision_id reported by
4588 if (static_branch_unlikely(&enable_evmcs))
4589 vmcs->revision_id = vmcs_config.revision_id;
4591 per_cpu(vmxarea, cpu) = vmcs;
4596 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
4597 struct kvm_segment *save)
4599 if (!emulate_invalid_guest_state) {
4601 * CS and SS RPL should be equal during guest entry according
4602 * to VMX spec, but in reality it is not always so. Since vcpu
4603 * is in the middle of the transition from real mode to
4604 * protected mode it is safe to assume that RPL 0 is a good
4607 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4608 save->selector &= ~SEGMENT_RPL_MASK;
4609 save->dpl = save->selector & SEGMENT_RPL_MASK;
4612 vmx_set_segment(vcpu, save, seg);
4615 static void enter_pmode(struct kvm_vcpu *vcpu)
4617 unsigned long flags;
4618 struct vcpu_vmx *vmx = to_vmx(vcpu);
4621 * Update real mode segment cache. It may be not up-to-date if sement
4622 * register was written while vcpu was in a guest mode.
4624 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4625 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4626 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4627 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4628 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4629 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4631 vmx->rmode.vm86_active = 0;
4633 vmx_segment_cache_clear(vmx);
4635 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4637 flags = vmcs_readl(GUEST_RFLAGS);
4638 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
4639 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
4640 vmcs_writel(GUEST_RFLAGS, flags);
4642 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
4643 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4645 update_exception_bitmap(vcpu);
4647 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4648 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4649 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4650 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4651 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4652 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4655 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4657 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4658 struct kvm_segment var = *save;
4661 if (seg == VCPU_SREG_CS)
4664 if (!emulate_invalid_guest_state) {
4665 var.selector = var.base >> 4;
4666 var.base = var.base & 0xffff0;
4676 if (save->base & 0xf)
4677 printk_once(KERN_WARNING "kvm: segment base is not "
4678 "paragraph aligned when entering "
4679 "protected mode (seg=%d)", seg);
4682 vmcs_write16(sf->selector, var.selector);
4683 vmcs_writel(sf->base, var.base);
4684 vmcs_write32(sf->limit, var.limit);
4685 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
4688 static void enter_rmode(struct kvm_vcpu *vcpu)
4690 unsigned long flags;
4691 struct vcpu_vmx *vmx = to_vmx(vcpu);
4692 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
4694 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4695 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4696 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4697 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4698 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4699 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4700 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4702 vmx->rmode.vm86_active = 1;
4705 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4706 * vcpu. Warn the user that an update is overdue.
4708 if (!kvm_vmx->tss_addr)
4709 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4710 "called before entering vcpu\n");
4712 vmx_segment_cache_clear(vmx);
4714 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
4715 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4716 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4718 flags = vmcs_readl(GUEST_RFLAGS);
4719 vmx->rmode.save_rflags = flags;
4721 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4723 vmcs_writel(GUEST_RFLAGS, flags);
4724 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4725 update_exception_bitmap(vcpu);
4727 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4728 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4729 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4730 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4731 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4732 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4734 kvm_mmu_reset_context(vcpu);
4737 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4739 struct vcpu_vmx *vmx = to_vmx(vcpu);
4740 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4746 * Force kernel_gs_base reloading before EFER changes, as control
4747 * of this msr depends on is_long_mode().
4749 vmx_load_host_state(to_vmx(vcpu));
4750 vcpu->arch.efer = efer;
4751 if (efer & EFER_LMA) {
4752 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4755 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4757 msr->data = efer & ~EFER_LME;
4762 #ifdef CONFIG_X86_64
4764 static void enter_lmode(struct kvm_vcpu *vcpu)
4768 vmx_segment_cache_clear(to_vmx(vcpu));
4770 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4771 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4772 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4774 vmcs_write32(GUEST_TR_AR_BYTES,
4775 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4776 | VMX_AR_TYPE_BUSY_64_TSS);
4778 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4781 static void exit_lmode(struct kvm_vcpu *vcpu)
4783 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4784 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4789 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
4790 bool invalidate_gpa)
4792 if (enable_ept && (invalidate_gpa || !enable_vpid)) {
4793 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4795 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4797 vpid_sync_context(vpid);
4801 static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
4803 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
4806 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4808 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4810 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4811 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4814 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4816 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
4817 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4818 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4821 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4823 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4825 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4826 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4829 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4831 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4833 if (!test_bit(VCPU_EXREG_PDPTR,
4834 (unsigned long *)&vcpu->arch.regs_dirty))
4837 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4838 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4839 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4840 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4841 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4845 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4847 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4849 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4850 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4851 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4852 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4853 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4856 __set_bit(VCPU_EXREG_PDPTR,
4857 (unsigned long *)&vcpu->arch.regs_avail);
4858 __set_bit(VCPU_EXREG_PDPTR,
4859 (unsigned long *)&vcpu->arch.regs_dirty);
4862 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4864 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
4865 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
4866 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4868 if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
4869 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4870 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4871 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4873 return fixed_bits_valid(val, fixed0, fixed1);
4876 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4878 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
4879 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
4881 return fixed_bits_valid(val, fixed0, fixed1);
4884 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4886 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0;
4887 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1;
4889 return fixed_bits_valid(val, fixed0, fixed1);
4892 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4893 #define nested_guest_cr4_valid nested_cr4_valid
4894 #define nested_host_cr4_valid nested_cr4_valid
4896 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4898 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4900 struct kvm_vcpu *vcpu)
4902 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4903 vmx_decache_cr3(vcpu);
4904 if (!(cr0 & X86_CR0_PG)) {
4905 /* From paging/starting to nonpaging */
4906 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4907 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4908 (CPU_BASED_CR3_LOAD_EXITING |
4909 CPU_BASED_CR3_STORE_EXITING));
4910 vcpu->arch.cr0 = cr0;
4911 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4912 } else if (!is_paging(vcpu)) {
4913 /* From nonpaging to paging */
4914 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4915 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4916 ~(CPU_BASED_CR3_LOAD_EXITING |
4917 CPU_BASED_CR3_STORE_EXITING));
4918 vcpu->arch.cr0 = cr0;
4919 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4922 if (!(cr0 & X86_CR0_WP))
4923 *hw_cr0 &= ~X86_CR0_WP;
4926 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4928 struct vcpu_vmx *vmx = to_vmx(vcpu);
4929 unsigned long hw_cr0;
4931 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4932 if (enable_unrestricted_guest)
4933 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4935 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4937 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4940 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4944 #ifdef CONFIG_X86_64
4945 if (vcpu->arch.efer & EFER_LME) {
4946 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4948 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4953 if (enable_ept && !enable_unrestricted_guest)
4954 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4956 vmcs_writel(CR0_READ_SHADOW, cr0);
4957 vmcs_writel(GUEST_CR0, hw_cr0);
4958 vcpu->arch.cr0 = cr0;
4960 /* depends on vcpu->arch.cr0 to be set to a new value */
4961 vmx->emulation_required = emulation_required(vcpu);
4964 static int get_ept_level(struct kvm_vcpu *vcpu)
4966 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
4971 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4973 u64 eptp = VMX_EPTP_MT_WB;
4975 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
4977 if (enable_ept_ad_bits &&
4978 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4979 eptp |= VMX_EPTP_AD_ENABLE_BIT;
4980 eptp |= (root_hpa & PAGE_MASK);
4985 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4987 unsigned long guest_cr3;
4992 eptp = construct_eptp(vcpu, cr3);
4993 vmcs_write64(EPT_POINTER, eptp);
4994 if (enable_unrestricted_guest || is_paging(vcpu) ||
4995 is_guest_mode(vcpu))
4996 guest_cr3 = kvm_read_cr3(vcpu);
4998 guest_cr3 = to_kvm_vmx(vcpu->kvm)->ept_identity_map_addr;
4999 ept_load_pdptrs(vcpu);
5002 vmx_flush_tlb(vcpu, true);
5003 vmcs_writel(GUEST_CR3, guest_cr3);
5006 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
5009 * Pass through host's Machine Check Enable value to hw_cr4, which
5010 * is in force while we are in guest mode. Do not let guests control
5011 * this bit, even if host CR4.MCE == 0.
5013 unsigned long hw_cr4;
5015 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
5016 if (enable_unrestricted_guest)
5017 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
5018 else if (to_vmx(vcpu)->rmode.vm86_active)
5019 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
5021 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
5023 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
5024 if (cr4 & X86_CR4_UMIP) {
5025 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5026 SECONDARY_EXEC_DESC);
5027 hw_cr4 &= ~X86_CR4_UMIP;
5028 } else if (!is_guest_mode(vcpu) ||
5029 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
5030 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5031 SECONDARY_EXEC_DESC);
5034 if (cr4 & X86_CR4_VMXE) {
5036 * To use VMXON (and later other VMX instructions), a guest
5037 * must first be able to turn on cr4.VMXE (see handle_vmon()).
5038 * So basically the check on whether to allow nested VMX
5041 if (!nested_vmx_allowed(vcpu))
5045 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5048 vcpu->arch.cr4 = cr4;
5050 if (!enable_unrestricted_guest) {
5052 if (!is_paging(vcpu)) {
5053 hw_cr4 &= ~X86_CR4_PAE;
5054 hw_cr4 |= X86_CR4_PSE;
5055 } else if (!(cr4 & X86_CR4_PAE)) {
5056 hw_cr4 &= ~X86_CR4_PAE;
5061 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
5062 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
5063 * to be manually disabled when guest switches to non-paging
5066 * If !enable_unrestricted_guest, the CPU is always running
5067 * with CR0.PG=1 and CR4 needs to be modified.
5068 * If enable_unrestricted_guest, the CPU automatically
5069 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
5071 if (!is_paging(vcpu))
5072 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
5075 vmcs_writel(CR4_READ_SHADOW, cr4);
5076 vmcs_writel(GUEST_CR4, hw_cr4);
5080 static void vmx_get_segment(struct kvm_vcpu *vcpu,
5081 struct kvm_segment *var, int seg)
5083 struct vcpu_vmx *vmx = to_vmx(vcpu);
5086 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5087 *var = vmx->rmode.segs[seg];
5088 if (seg == VCPU_SREG_TR
5089 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
5091 var->base = vmx_read_guest_seg_base(vmx, seg);
5092 var->selector = vmx_read_guest_seg_selector(vmx, seg);
5095 var->base = vmx_read_guest_seg_base(vmx, seg);
5096 var->limit = vmx_read_guest_seg_limit(vmx, seg);
5097 var->selector = vmx_read_guest_seg_selector(vmx, seg);
5098 ar = vmx_read_guest_seg_ar(vmx, seg);
5099 var->unusable = (ar >> 16) & 1;
5100 var->type = ar & 15;
5101 var->s = (ar >> 4) & 1;
5102 var->dpl = (ar >> 5) & 3;
5104 * Some userspaces do not preserve unusable property. Since usable
5105 * segment has to be present according to VMX spec we can use present
5106 * property to amend userspace bug by making unusable segment always
5107 * nonpresent. vmx_segment_access_rights() already marks nonpresent
5108 * segment as unusable.
5110 var->present = !var->unusable;
5111 var->avl = (ar >> 12) & 1;
5112 var->l = (ar >> 13) & 1;
5113 var->db = (ar >> 14) & 1;
5114 var->g = (ar >> 15) & 1;
5117 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
5119 struct kvm_segment s;
5121 if (to_vmx(vcpu)->rmode.vm86_active) {
5122 vmx_get_segment(vcpu, &s, seg);
5125 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
5128 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
5130 struct vcpu_vmx *vmx = to_vmx(vcpu);
5132 if (unlikely(vmx->rmode.vm86_active))
5135 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
5136 return VMX_AR_DPL(ar);
5140 static u32 vmx_segment_access_rights(struct kvm_segment *var)
5144 if (var->unusable || !var->present)
5147 ar = var->type & 15;
5148 ar |= (var->s & 1) << 4;
5149 ar |= (var->dpl & 3) << 5;
5150 ar |= (var->present & 1) << 7;
5151 ar |= (var->avl & 1) << 12;
5152 ar |= (var->l & 1) << 13;
5153 ar |= (var->db & 1) << 14;
5154 ar |= (var->g & 1) << 15;
5160 static void vmx_set_segment(struct kvm_vcpu *vcpu,
5161 struct kvm_segment *var, int seg)
5163 struct vcpu_vmx *vmx = to_vmx(vcpu);
5164 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5166 vmx_segment_cache_clear(vmx);
5168 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
5169 vmx->rmode.segs[seg] = *var;
5170 if (seg == VCPU_SREG_TR)
5171 vmcs_write16(sf->selector, var->selector);
5173 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
5177 vmcs_writel(sf->base, var->base);
5178 vmcs_write32(sf->limit, var->limit);
5179 vmcs_write16(sf->selector, var->selector);
5182 * Fix the "Accessed" bit in AR field of segment registers for older
5184 * IA32 arch specifies that at the time of processor reset the
5185 * "Accessed" bit in the AR field of segment registers is 1. And qemu
5186 * is setting it to 0 in the userland code. This causes invalid guest
5187 * state vmexit when "unrestricted guest" mode is turned on.
5188 * Fix for this setup issue in cpu_reset is being pushed in the qemu
5189 * tree. Newer qemu binaries with that qemu fix would not need this
5192 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
5193 var->type |= 0x1; /* Accessed */
5195 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
5198 vmx->emulation_required = emulation_required(vcpu);
5201 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5203 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
5205 *db = (ar >> 14) & 1;
5206 *l = (ar >> 13) & 1;
5209 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5211 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
5212 dt->address = vmcs_readl(GUEST_IDTR_BASE);
5215 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5217 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
5218 vmcs_writel(GUEST_IDTR_BASE, dt->address);
5221 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5223 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
5224 dt->address = vmcs_readl(GUEST_GDTR_BASE);
5227 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
5229 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
5230 vmcs_writel(GUEST_GDTR_BASE, dt->address);
5233 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
5235 struct kvm_segment var;
5238 vmx_get_segment(vcpu, &var, seg);
5240 if (seg == VCPU_SREG_CS)
5242 ar = vmx_segment_access_rights(&var);
5244 if (var.base != (var.selector << 4))
5246 if (var.limit != 0xffff)
5254 static bool code_segment_valid(struct kvm_vcpu *vcpu)
5256 struct kvm_segment cs;
5257 unsigned int cs_rpl;
5259 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5260 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
5264 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
5268 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
5269 if (cs.dpl > cs_rpl)
5272 if (cs.dpl != cs_rpl)
5278 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
5282 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
5284 struct kvm_segment ss;
5285 unsigned int ss_rpl;
5287 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5288 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
5292 if (ss.type != 3 && ss.type != 7)
5296 if (ss.dpl != ss_rpl) /* DPL != RPL */
5304 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
5306 struct kvm_segment var;
5309 vmx_get_segment(vcpu, &var, seg);
5310 rpl = var.selector & SEGMENT_RPL_MASK;
5318 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
5319 if (var.dpl < rpl) /* DPL < RPL */
5323 /* TODO: Add other members to kvm_segment_field to allow checking for other access
5329 static bool tr_valid(struct kvm_vcpu *vcpu)
5331 struct kvm_segment tr;
5333 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
5337 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
5339 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
5347 static bool ldtr_valid(struct kvm_vcpu *vcpu)
5349 struct kvm_segment ldtr;
5351 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
5355 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
5365 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
5367 struct kvm_segment cs, ss;
5369 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5370 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
5372 return ((cs.selector & SEGMENT_RPL_MASK) ==
5373 (ss.selector & SEGMENT_RPL_MASK));
5377 * Check if guest state is valid. Returns true if valid, false if
5379 * We assume that registers are always usable
5381 static bool guest_state_valid(struct kvm_vcpu *vcpu)
5383 if (enable_unrestricted_guest)
5386 /* real mode guest state checks */
5387 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5388 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
5390 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
5392 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
5394 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
5396 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
5398 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
5401 /* protected mode guest state checks */
5402 if (!cs_ss_rpl_check(vcpu))
5404 if (!code_segment_valid(vcpu))
5406 if (!stack_segment_valid(vcpu))
5408 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
5410 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
5412 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
5414 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
5416 if (!tr_valid(vcpu))
5418 if (!ldtr_valid(vcpu))
5422 * - Add checks on RIP
5423 * - Add checks on RFLAGS
5429 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
5431 return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
5434 static int init_rmode_tss(struct kvm *kvm)
5440 idx = srcu_read_lock(&kvm->srcu);
5441 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
5442 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5445 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
5446 r = kvm_write_guest_page(kvm, fn++, &data,
5447 TSS_IOPB_BASE_OFFSET, sizeof(u16));
5450 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
5453 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
5457 r = kvm_write_guest_page(kvm, fn, &data,
5458 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
5461 srcu_read_unlock(&kvm->srcu, idx);
5465 static int init_rmode_identity_map(struct kvm *kvm)
5467 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
5469 kvm_pfn_t identity_map_pfn;
5472 /* Protect kvm_vmx->ept_identity_pagetable_done. */
5473 mutex_lock(&kvm->slots_lock);
5475 if (likely(kvm_vmx->ept_identity_pagetable_done))
5478 if (!kvm_vmx->ept_identity_map_addr)
5479 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
5480 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
5482 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
5483 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
5487 idx = srcu_read_lock(&kvm->srcu);
5488 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
5491 /* Set up identity-mapping pagetable for EPT in real mode */
5492 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
5493 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
5494 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
5495 r = kvm_write_guest_page(kvm, identity_map_pfn,
5496 &tmp, i * sizeof(tmp), sizeof(tmp));
5500 kvm_vmx->ept_identity_pagetable_done = true;
5503 srcu_read_unlock(&kvm->srcu, idx);
5506 mutex_unlock(&kvm->slots_lock);
5510 static void seg_setup(int seg)
5512 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
5515 vmcs_write16(sf->selector, 0);
5516 vmcs_writel(sf->base, 0);
5517 vmcs_write32(sf->limit, 0xffff);
5519 if (seg == VCPU_SREG_CS)
5520 ar |= 0x08; /* code segment */
5522 vmcs_write32(sf->ar_bytes, ar);
5525 static int alloc_apic_access_page(struct kvm *kvm)
5530 mutex_lock(&kvm->slots_lock);
5531 if (kvm->arch.apic_access_page_done)
5533 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
5534 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
5538 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
5539 if (is_error_page(page)) {
5545 * Do not pin the page in memory, so that memory hot-unplug
5546 * is able to migrate it.
5549 kvm->arch.apic_access_page_done = true;
5551 mutex_unlock(&kvm->slots_lock);
5555 static int allocate_vpid(void)
5561 spin_lock(&vmx_vpid_lock);
5562 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
5563 if (vpid < VMX_NR_VPIDS)
5564 __set_bit(vpid, vmx_vpid_bitmap);
5567 spin_unlock(&vmx_vpid_lock);
5571 static void free_vpid(int vpid)
5573 if (!enable_vpid || vpid == 0)
5575 spin_lock(&vmx_vpid_lock);
5576 __clear_bit(vpid, vmx_vpid_bitmap);
5577 spin_unlock(&vmx_vpid_lock);
5580 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
5583 int f = sizeof(unsigned long);
5585 if (!cpu_has_vmx_msr_bitmap())
5588 if (static_branch_unlikely(&enable_evmcs))
5589 evmcs_touch_msr_bitmap();
5592 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5593 * have the write-low and read-high bitmap offsets the wrong way round.
5594 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5596 if (msr <= 0x1fff) {
5597 if (type & MSR_TYPE_R)
5599 __clear_bit(msr, msr_bitmap + 0x000 / f);
5601 if (type & MSR_TYPE_W)
5603 __clear_bit(msr, msr_bitmap + 0x800 / f);
5605 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5607 if (type & MSR_TYPE_R)
5609 __clear_bit(msr, msr_bitmap + 0x400 / f);
5611 if (type & MSR_TYPE_W)
5613 __clear_bit(msr, msr_bitmap + 0xc00 / f);
5618 static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
5621 int f = sizeof(unsigned long);
5623 if (!cpu_has_vmx_msr_bitmap())
5626 if (static_branch_unlikely(&enable_evmcs))
5627 evmcs_touch_msr_bitmap();
5630 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5631 * have the write-low and read-high bitmap offsets the wrong way round.
5632 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5634 if (msr <= 0x1fff) {
5635 if (type & MSR_TYPE_R)
5637 __set_bit(msr, msr_bitmap + 0x000 / f);
5639 if (type & MSR_TYPE_W)
5641 __set_bit(msr, msr_bitmap + 0x800 / f);
5643 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5645 if (type & MSR_TYPE_R)
5647 __set_bit(msr, msr_bitmap + 0x400 / f);
5649 if (type & MSR_TYPE_W)
5651 __set_bit(msr, msr_bitmap + 0xc00 / f);
5656 static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
5657 u32 msr, int type, bool value)
5660 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
5662 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
5666 * If a msr is allowed by L0, we should check whether it is allowed by L1.
5667 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
5669 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
5670 unsigned long *msr_bitmap_nested,
5673 int f = sizeof(unsigned long);
5676 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5677 * have the write-low and read-high bitmap offsets the wrong way round.
5678 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5680 if (msr <= 0x1fff) {
5681 if (type & MSR_TYPE_R &&
5682 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
5684 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
5686 if (type & MSR_TYPE_W &&
5687 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
5689 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
5691 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5693 if (type & MSR_TYPE_R &&
5694 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
5696 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
5698 if (type & MSR_TYPE_W &&
5699 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
5701 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
5706 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5710 if (cpu_has_secondary_exec_ctrls() &&
5711 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
5712 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
5713 mode |= MSR_BITMAP_MODE_X2APIC;
5714 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
5715 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
5718 if (is_long_mode(vcpu))
5719 mode |= MSR_BITMAP_MODE_LM;
5724 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
5726 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
5731 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
5732 unsigned word = msr / BITS_PER_LONG;
5733 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
5734 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
5737 if (mode & MSR_BITMAP_MODE_X2APIC) {
5739 * TPR reads and writes can be virtualized even if virtual interrupt
5740 * delivery is not in use.
5742 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
5743 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
5744 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
5745 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
5746 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
5751 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
5753 struct vcpu_vmx *vmx = to_vmx(vcpu);
5754 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
5755 u8 mode = vmx_msr_bitmap_mode(vcpu);
5756 u8 changed = mode ^ vmx->msr_bitmap_mode;
5761 vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW,
5762 !(mode & MSR_BITMAP_MODE_LM));
5764 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
5765 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
5767 vmx->msr_bitmap_mode = mode;
5770 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
5772 return enable_apicv;
5775 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5777 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5781 * Don't need to mark the APIC access page dirty; it is never
5782 * written to by the CPU during APIC virtualization.
5785 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5786 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5787 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5790 if (nested_cpu_has_posted_intr(vmcs12)) {
5791 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5792 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5797 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5799 struct vcpu_vmx *vmx = to_vmx(vcpu);
5804 if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5807 vmx->nested.pi_pending = false;
5808 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5811 max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5812 if (max_irr != 256) {
5813 vapic_page = kmap(vmx->nested.virtual_apic_page);
5814 __kvm_apic_update_irr(vmx->nested.pi_desc->pir,
5815 vapic_page, &max_irr);
5816 kunmap(vmx->nested.virtual_apic_page);
5818 status = vmcs_read16(GUEST_INTR_STATUS);
5819 if ((u8)max_irr > ((u8)status & 0xff)) {
5821 status |= (u8)max_irr;
5822 vmcs_write16(GUEST_INTR_STATUS, status);
5826 nested_mark_vmcs12_pages_dirty(vcpu);
5829 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5833 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5835 if (vcpu->mode == IN_GUEST_MODE) {
5837 * The vector of interrupt to be delivered to vcpu had
5838 * been set in PIR before this function.
5840 * Following cases will be reached in this block, and
5841 * we always send a notification event in all cases as
5844 * Case 1: vcpu keeps in non-root mode. Sending a
5845 * notification event posts the interrupt to vcpu.
5847 * Case 2: vcpu exits to root mode and is still
5848 * runnable. PIR will be synced to vIRR before the
5849 * next vcpu entry. Sending a notification event in
5850 * this case has no effect, as vcpu is not in root
5853 * Case 3: vcpu exits to root mode and is blocked.
5854 * vcpu_block() has already synced PIR to vIRR and
5855 * never blocks vcpu if vIRR is not cleared. Therefore,
5856 * a blocked vcpu here does not wait for any requested
5857 * interrupts in PIR, and sending a notification event
5858 * which has no effect is safe here.
5861 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5868 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5871 struct vcpu_vmx *vmx = to_vmx(vcpu);
5873 if (is_guest_mode(vcpu) &&
5874 vector == vmx->nested.posted_intr_nv) {
5876 * If a posted intr is not recognized by hardware,
5877 * we will accomplish it in the next vmentry.
5879 vmx->nested.pi_pending = true;
5880 kvm_make_request(KVM_REQ_EVENT, vcpu);
5881 /* the PIR and ON have been set by L1. */
5882 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
5883 kvm_vcpu_kick(vcpu);
5889 * Send interrupt to vcpu via posted interrupt way.
5890 * 1. If target vcpu is running(non-root mode), send posted interrupt
5891 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5892 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5893 * interrupt from PIR in next vmentry.
5895 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5897 struct vcpu_vmx *vmx = to_vmx(vcpu);
5900 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5904 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5907 /* If a previous notification has sent the IPI, nothing to do. */
5908 if (pi_test_and_set_on(&vmx->pi_desc))
5911 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5912 kvm_vcpu_kick(vcpu);
5916 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5917 * will not change in the lifetime of the guest.
5918 * Note that host-state that does change is set elsewhere. E.g., host-state
5919 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5921 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5926 unsigned long cr0, cr3, cr4;
5929 WARN_ON(cr0 & X86_CR0_TS);
5930 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
5933 * Save the most likely value for this task's CR3 in the VMCS.
5934 * We can't use __get_current_cr3_fast() because we're not atomic.
5937 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
5938 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5940 /* Save the most likely value for this task's CR4 in the VMCS. */
5941 cr4 = cr4_read_shadow();
5942 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5943 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5945 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
5946 #ifdef CONFIG_X86_64
5948 * Load null selectors, so we can avoid reloading them in
5949 * __vmx_load_host_state(), in case userspace uses the null selectors
5950 * too (the expected case).
5952 vmcs_write16(HOST_DS_SELECTOR, 0);
5953 vmcs_write16(HOST_ES_SELECTOR, 0);
5955 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5956 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5958 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5959 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5962 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
5963 vmx->host_idt_base = dt.address;
5965 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5967 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5968 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5969 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5970 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5972 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5973 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5974 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5978 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5980 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5982 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5983 if (is_guest_mode(&vmx->vcpu))
5984 vmx->vcpu.arch.cr4_guest_owned_bits &=
5985 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5986 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5989 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5991 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5993 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5994 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5997 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
5999 /* Enable the preemption timer dynamically */
6000 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
6001 return pin_based_exec_ctrl;
6004 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
6006 struct vcpu_vmx *vmx = to_vmx(vcpu);
6008 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6009 if (cpu_has_secondary_exec_ctrls()) {
6010 if (kvm_vcpu_apicv_active(vcpu))
6011 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
6012 SECONDARY_EXEC_APIC_REGISTER_VIRT |
6013 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6015 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6016 SECONDARY_EXEC_APIC_REGISTER_VIRT |
6017 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6020 if (cpu_has_vmx_msr_bitmap())
6021 vmx_update_msr_bitmap(vcpu);
6024 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
6026 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
6028 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
6029 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
6031 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
6032 exec_control &= ~CPU_BASED_TPR_SHADOW;
6033 #ifdef CONFIG_X86_64
6034 exec_control |= CPU_BASED_CR8_STORE_EXITING |
6035 CPU_BASED_CR8_LOAD_EXITING;
6039 exec_control |= CPU_BASED_CR3_STORE_EXITING |
6040 CPU_BASED_CR3_LOAD_EXITING |
6041 CPU_BASED_INVLPG_EXITING;
6042 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
6043 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
6044 CPU_BASED_MONITOR_EXITING);
6045 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
6046 exec_control &= ~CPU_BASED_HLT_EXITING;
6047 return exec_control;
6050 static bool vmx_rdrand_supported(void)
6052 return vmcs_config.cpu_based_2nd_exec_ctrl &
6053 SECONDARY_EXEC_RDRAND_EXITING;
6056 static bool vmx_rdseed_supported(void)
6058 return vmcs_config.cpu_based_2nd_exec_ctrl &
6059 SECONDARY_EXEC_RDSEED_EXITING;
6062 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
6064 struct kvm_vcpu *vcpu = &vmx->vcpu;
6066 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
6068 if (!cpu_need_virtualize_apic_accesses(vcpu))
6069 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6071 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
6073 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
6074 enable_unrestricted_guest = 0;
6075 /* Enable INVPCID for non-ept guests may cause performance regression. */
6076 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6078 if (!enable_unrestricted_guest)
6079 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
6080 if (kvm_pause_in_guest(vmx->vcpu.kvm))
6081 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
6082 if (!kvm_vcpu_apicv_active(vcpu))
6083 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
6084 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
6085 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6087 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
6088 * in vmx_set_cr4. */
6089 exec_control &= ~SECONDARY_EXEC_DESC;
6091 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
6093 We can NOT enable shadow_vmcs here because we don't have yet
6096 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6099 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
6101 if (vmx_xsaves_supported()) {
6102 /* Exposing XSAVES only when XSAVE is exposed */
6103 bool xsaves_enabled =
6104 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
6105 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
6107 if (!xsaves_enabled)
6108 exec_control &= ~SECONDARY_EXEC_XSAVES;
6112 vmx->nested.msrs.secondary_ctls_high |=
6113 SECONDARY_EXEC_XSAVES;
6115 vmx->nested.msrs.secondary_ctls_high &=
6116 ~SECONDARY_EXEC_XSAVES;
6120 if (vmx_rdtscp_supported()) {
6121 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
6122 if (!rdtscp_enabled)
6123 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6127 vmx->nested.msrs.secondary_ctls_high |=
6128 SECONDARY_EXEC_RDTSCP;
6130 vmx->nested.msrs.secondary_ctls_high &=
6131 ~SECONDARY_EXEC_RDTSCP;
6135 if (vmx_invpcid_supported()) {
6136 /* Exposing INVPCID only when PCID is exposed */
6137 bool invpcid_enabled =
6138 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
6139 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
6141 if (!invpcid_enabled) {
6142 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6143 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
6147 if (invpcid_enabled)
6148 vmx->nested.msrs.secondary_ctls_high |=
6149 SECONDARY_EXEC_ENABLE_INVPCID;
6151 vmx->nested.msrs.secondary_ctls_high &=
6152 ~SECONDARY_EXEC_ENABLE_INVPCID;
6156 if (vmx_rdrand_supported()) {
6157 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
6159 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
6163 vmx->nested.msrs.secondary_ctls_high |=
6164 SECONDARY_EXEC_RDRAND_EXITING;
6166 vmx->nested.msrs.secondary_ctls_high &=
6167 ~SECONDARY_EXEC_RDRAND_EXITING;
6171 if (vmx_rdseed_supported()) {
6172 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
6174 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
6178 vmx->nested.msrs.secondary_ctls_high |=
6179 SECONDARY_EXEC_RDSEED_EXITING;
6181 vmx->nested.msrs.secondary_ctls_high &=
6182 ~SECONDARY_EXEC_RDSEED_EXITING;
6186 vmx->secondary_exec_control = exec_control;
6189 static void ept_set_mmio_spte_mask(void)
6192 * EPT Misconfigurations can be generated if the value of bits 2:0
6193 * of an EPT paging-structure entry is 110b (write/execute).
6195 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
6196 VMX_EPT_MISCONFIG_WX_VALUE);
6199 #define VMX_XSS_EXIT_BITMAP 0
6201 * Sets up the vmcs for emulated real mode.
6203 static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
6205 #ifdef CONFIG_X86_64
6210 if (enable_shadow_vmcs) {
6212 * At vCPU creation, "VMWRITE to any supported field
6213 * in the VMCS" is supported, so use the more
6214 * permissive vmx_vmread_bitmap to specify both read
6215 * and write permissions for the shadow VMCS.
6217 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
6218 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmread_bitmap));
6220 if (cpu_has_vmx_msr_bitmap())
6221 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
6223 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
6226 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6227 vmx->hv_deadline_tsc = -1;
6229 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6231 if (cpu_has_secondary_exec_ctrls()) {
6232 vmx_compute_secondary_exec_control(vmx);
6233 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6234 vmx->secondary_exec_control);
6237 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
6238 vmcs_write64(EOI_EXIT_BITMAP0, 0);
6239 vmcs_write64(EOI_EXIT_BITMAP1, 0);
6240 vmcs_write64(EOI_EXIT_BITMAP2, 0);
6241 vmcs_write64(EOI_EXIT_BITMAP3, 0);
6243 vmcs_write16(GUEST_INTR_STATUS, 0);
6245 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
6246 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
6249 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
6250 vmcs_write32(PLE_GAP, ple_gap);
6251 vmx->ple_window = ple_window;
6252 vmx->ple_window_dirty = true;
6255 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
6256 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6257 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
6259 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
6260 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
6261 vmx_set_constant_host_state(vmx);
6262 #ifdef CONFIG_X86_64
6263 rdmsrl(MSR_FS_BASE, a);
6264 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
6265 rdmsrl(MSR_GS_BASE, a);
6266 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
6268 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
6269 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6272 if (cpu_has_vmx_vmfunc())
6273 vmcs_write64(VM_FUNCTION_CONTROL, 0);
6275 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
6276 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
6277 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
6278 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6279 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6281 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6282 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6284 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6285 u32 index = vmx_msr_index[i];
6286 u32 data_low, data_high;
6289 if (rdmsr_safe(index, &data_low, &data_high) < 0)
6291 if (wrmsr_safe(index, data_low, data_high) < 0)
6293 vmx->guest_msrs[j].index = i;
6294 vmx->guest_msrs[j].data = 0;
6295 vmx->guest_msrs[j].mask = -1ull;
6299 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
6300 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, vmx->arch_capabilities);
6302 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6304 /* 22.2.1, 20.8.1 */
6305 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
6307 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
6308 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
6310 set_cr4_guest_host_mask(vmx);
6312 if (vmx_xsaves_supported())
6313 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
6316 ASSERT(vmx->pml_pg);
6317 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
6318 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
6322 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
6324 struct vcpu_vmx *vmx = to_vmx(vcpu);
6325 struct msr_data apic_base_msr;
6328 vmx->rmode.vm86_active = 0;
6331 vcpu->arch.microcode_version = 0x100000000ULL;
6332 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
6333 kvm_set_cr8(vcpu, 0);
6336 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
6337 MSR_IA32_APICBASE_ENABLE;
6338 if (kvm_vcpu_is_reset_bsp(vcpu))
6339 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
6340 apic_base_msr.host_initiated = true;
6341 kvm_set_apic_base(vcpu, &apic_base_msr);
6344 vmx_segment_cache_clear(vmx);
6346 seg_setup(VCPU_SREG_CS);
6347 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
6348 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
6350 seg_setup(VCPU_SREG_DS);
6351 seg_setup(VCPU_SREG_ES);
6352 seg_setup(VCPU_SREG_FS);
6353 seg_setup(VCPU_SREG_GS);
6354 seg_setup(VCPU_SREG_SS);
6356 vmcs_write16(GUEST_TR_SELECTOR, 0);
6357 vmcs_writel(GUEST_TR_BASE, 0);
6358 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
6359 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
6361 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
6362 vmcs_writel(GUEST_LDTR_BASE, 0);
6363 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
6364 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
6367 vmcs_write32(GUEST_SYSENTER_CS, 0);
6368 vmcs_writel(GUEST_SYSENTER_ESP, 0);
6369 vmcs_writel(GUEST_SYSENTER_EIP, 0);
6370 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
6373 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6374 kvm_rip_write(vcpu, 0xfff0);
6376 vmcs_writel(GUEST_GDTR_BASE, 0);
6377 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
6379 vmcs_writel(GUEST_IDTR_BASE, 0);
6380 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
6382 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
6383 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
6384 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
6385 if (kvm_mpx_supported())
6386 vmcs_write64(GUEST_BNDCFGS, 0);
6390 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
6392 if (cpu_has_vmx_tpr_shadow() && !init_event) {
6393 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
6394 if (cpu_need_tpr_shadow(vcpu))
6395 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
6396 __pa(vcpu->arch.apic->regs));
6397 vmcs_write32(TPR_THRESHOLD, 0);
6400 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6403 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6405 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
6406 vmx->vcpu.arch.cr0 = cr0;
6407 vmx_set_cr0(vcpu, cr0); /* enter rmode */
6408 vmx_set_cr4(vcpu, 0);
6409 vmx_set_efer(vcpu, 0);
6411 update_exception_bitmap(vcpu);
6413 vpid_sync_context(vmx->vpid);
6415 vmx_clear_hlt(vcpu);
6419 * In nested virtualization, check if L1 asked to exit on external interrupts.
6420 * For most existing hypervisors, this will always return true.
6422 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
6424 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
6425 PIN_BASED_EXT_INTR_MASK;
6429 * In nested virtualization, check if L1 has set
6430 * VM_EXIT_ACK_INTR_ON_EXIT
6432 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
6434 return get_vmcs12(vcpu)->vm_exit_controls &
6435 VM_EXIT_ACK_INTR_ON_EXIT;
6438 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
6440 return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu));
6443 static void enable_irq_window(struct kvm_vcpu *vcpu)
6445 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6446 CPU_BASED_VIRTUAL_INTR_PENDING);
6449 static void enable_nmi_window(struct kvm_vcpu *vcpu)
6452 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
6453 enable_irq_window(vcpu);
6457 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
6458 CPU_BASED_VIRTUAL_NMI_PENDING);
6461 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
6463 struct vcpu_vmx *vmx = to_vmx(vcpu);
6465 int irq = vcpu->arch.interrupt.nr;
6467 trace_kvm_inj_virq(irq);
6469 ++vcpu->stat.irq_injections;
6470 if (vmx->rmode.vm86_active) {
6472 if (vcpu->arch.interrupt.soft)
6473 inc_eip = vcpu->arch.event_exit_inst_len;
6474 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
6475 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6478 intr = irq | INTR_INFO_VALID_MASK;
6479 if (vcpu->arch.interrupt.soft) {
6480 intr |= INTR_TYPE_SOFT_INTR;
6481 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6482 vmx->vcpu.arch.event_exit_inst_len);
6484 intr |= INTR_TYPE_EXT_INTR;
6485 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
6487 vmx_clear_hlt(vcpu);
6490 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
6492 struct vcpu_vmx *vmx = to_vmx(vcpu);
6496 * Tracking the NMI-blocked state in software is built upon
6497 * finding the next open IRQ window. This, in turn, depends on
6498 * well-behaving guests: They have to keep IRQs disabled at
6499 * least as long as the NMI handler runs. Otherwise we may
6500 * cause NMI nesting, maybe breaking the guest. But as this is
6501 * highly unlikely, we can live with the residual risk.
6503 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
6504 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6507 ++vcpu->stat.nmi_injections;
6508 vmx->loaded_vmcs->nmi_known_unmasked = false;
6510 if (vmx->rmode.vm86_active) {
6511 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
6512 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6516 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6517 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
6519 vmx_clear_hlt(vcpu);
6522 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
6524 struct vcpu_vmx *vmx = to_vmx(vcpu);
6528 return vmx->loaded_vmcs->soft_vnmi_blocked;
6529 if (vmx->loaded_vmcs->nmi_known_unmasked)
6531 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
6532 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6536 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
6538 struct vcpu_vmx *vmx = to_vmx(vcpu);
6541 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
6542 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
6543 vmx->loaded_vmcs->vnmi_blocked_time = 0;
6546 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
6548 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6549 GUEST_INTR_STATE_NMI);
6551 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
6552 GUEST_INTR_STATE_NMI);
6556 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
6558 if (to_vmx(vcpu)->nested.nested_run_pending)
6562 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
6565 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6566 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
6567 | GUEST_INTR_STATE_NMI));
6570 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
6572 return (!to_vmx(vcpu)->nested.nested_run_pending &&
6573 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
6574 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6575 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
6578 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
6582 if (enable_unrestricted_guest)
6585 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
6589 to_kvm_vmx(kvm)->tss_addr = addr;
6590 return init_rmode_tss(kvm);
6593 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
6595 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
6599 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6604 * Update instruction length as we may reinject the exception
6605 * from user space while in guest debugging mode.
6607 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
6608 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6609 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6613 if (vcpu->guest_debug &
6614 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6631 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
6632 int vec, u32 err_code)
6635 * Instruction with address size override prefix opcode 0x67
6636 * Cause the #SS fault with 0 error code in VM86 mode.
6638 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
6639 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
6640 if (vcpu->arch.halt_request) {
6641 vcpu->arch.halt_request = 0;
6642 return kvm_vcpu_halt(vcpu);
6650 * Forward all other exceptions that are valid in real mode.
6651 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
6652 * the required debugging infrastructure rework.
6654 kvm_queue_exception(vcpu, vec);
6659 * Trigger machine check on the host. We assume all the MSRs are already set up
6660 * by the CPU and that we still run on the same CPU as the MCE occurred on.
6661 * We pass a fake environment to the machine check handler because we want
6662 * the guest to be always treated like user space, no matter what context
6663 * it used internally.
6665 static void kvm_machine_check(void)
6667 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
6668 struct pt_regs regs = {
6669 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
6670 .flags = X86_EFLAGS_IF,
6673 do_machine_check(®s, 0);
6677 static int handle_machine_check(struct kvm_vcpu *vcpu)
6679 /* already handled by vcpu_run */
6683 static int handle_exception(struct kvm_vcpu *vcpu)
6685 struct vcpu_vmx *vmx = to_vmx(vcpu);
6686 struct kvm_run *kvm_run = vcpu->run;
6687 u32 intr_info, ex_no, error_code;
6688 unsigned long cr2, rip, dr6;
6690 enum emulation_result er;
6692 vect_info = vmx->idt_vectoring_info;
6693 intr_info = vmx->exit_intr_info;
6695 if (is_machine_check(intr_info))
6696 return handle_machine_check(vcpu);
6698 if (is_nmi(intr_info))
6699 return 1; /* already handled by vmx_vcpu_run() */
6701 if (is_invalid_opcode(intr_info))
6702 return handle_ud(vcpu);
6705 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6706 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6708 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
6709 WARN_ON_ONCE(!enable_vmware_backdoor);
6710 er = emulate_instruction(vcpu,
6711 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
6712 if (er == EMULATE_USER_EXIT)
6714 else if (er != EMULATE_DONE)
6715 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
6720 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
6721 * MMIO, it is better to report an internal error.
6722 * See the comments in vmx_handle_exit.
6724 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
6725 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
6726 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6727 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
6728 vcpu->run->internal.ndata = 3;
6729 vcpu->run->internal.data[0] = vect_info;
6730 vcpu->run->internal.data[1] = intr_info;
6731 vcpu->run->internal.data[2] = error_code;
6735 if (is_page_fault(intr_info)) {
6736 cr2 = vmcs_readl(EXIT_QUALIFICATION);
6737 /* EPT won't cause page fault directly */
6738 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
6739 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6742 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
6744 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
6745 return handle_rmode_exception(vcpu, ex_no, error_code);
6749 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
6752 dr6 = vmcs_readl(EXIT_QUALIFICATION);
6753 if (!(vcpu->guest_debug &
6754 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
6755 vcpu->arch.dr6 &= ~15;
6756 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6757 if (is_icebp(intr_info))
6758 skip_emulated_instruction(vcpu);
6760 kvm_queue_exception(vcpu, DB_VECTOR);
6763 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
6764 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
6768 * Update instruction length as we may reinject #BP from
6769 * user space while in guest debugging mode. Reading it for
6770 * #DB as well causes no harm, it is not used in that case.
6772 vmx->vcpu.arch.event_exit_inst_len =
6773 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6774 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6775 rip = kvm_rip_read(vcpu);
6776 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
6777 kvm_run->debug.arch.exception = ex_no;
6780 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
6781 kvm_run->ex.exception = ex_no;
6782 kvm_run->ex.error_code = error_code;
6788 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6790 ++vcpu->stat.irq_exits;
6794 static int handle_triple_fault(struct kvm_vcpu *vcpu)
6796 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6797 vcpu->mmio_needed = 0;
6801 static int handle_io(struct kvm_vcpu *vcpu)
6803 unsigned long exit_qualification;
6804 int size, in, string;
6807 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6808 string = (exit_qualification & 16) != 0;
6810 ++vcpu->stat.io_exits;
6813 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6815 port = exit_qualification >> 16;
6816 size = (exit_qualification & 7) + 1;
6817 in = (exit_qualification & 8) != 0;
6819 return kvm_fast_pio(vcpu, size, port, in);
6823 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
6826 * Patch in the VMCALL instruction:
6828 hypercall[0] = 0x0f;
6829 hypercall[1] = 0x01;
6830 hypercall[2] = 0xc1;
6833 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6834 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
6836 if (is_guest_mode(vcpu)) {
6837 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6838 unsigned long orig_val = val;
6841 * We get here when L2 changed cr0 in a way that did not change
6842 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6843 * but did change L0 shadowed bits. So we first calculate the
6844 * effective cr0 value that L1 would like to write into the
6845 * hardware. It consists of the L2-owned bits from the new
6846 * value combined with the L1-owned bits from L1's guest_cr0.
6848 val = (val & ~vmcs12->cr0_guest_host_mask) |
6849 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
6851 if (!nested_guest_cr0_valid(vcpu, val))
6854 if (kvm_set_cr0(vcpu, val))
6856 vmcs_writel(CR0_READ_SHADOW, orig_val);
6859 if (to_vmx(vcpu)->nested.vmxon &&
6860 !nested_host_cr0_valid(vcpu, val))
6863 return kvm_set_cr0(vcpu, val);
6867 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
6869 if (is_guest_mode(vcpu)) {
6870 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6871 unsigned long orig_val = val;
6873 /* analogously to handle_set_cr0 */
6874 val = (val & ~vmcs12->cr4_guest_host_mask) |
6875 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
6876 if (kvm_set_cr4(vcpu, val))
6878 vmcs_writel(CR4_READ_SHADOW, orig_val);
6881 return kvm_set_cr4(vcpu, val);
6884 static int handle_desc(struct kvm_vcpu *vcpu)
6886 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
6887 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6890 static int handle_cr(struct kvm_vcpu *vcpu)
6892 unsigned long exit_qualification, val;
6898 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6899 cr = exit_qualification & 15;
6900 reg = (exit_qualification >> 8) & 15;
6901 switch ((exit_qualification >> 4) & 3) {
6902 case 0: /* mov to cr */
6903 val = kvm_register_readl(vcpu, reg);
6904 trace_kvm_cr_write(cr, val);
6907 err = handle_set_cr0(vcpu, val);
6908 return kvm_complete_insn_gp(vcpu, err);
6910 WARN_ON_ONCE(enable_unrestricted_guest);
6911 err = kvm_set_cr3(vcpu, val);
6912 return kvm_complete_insn_gp(vcpu, err);
6914 err = handle_set_cr4(vcpu, val);
6915 return kvm_complete_insn_gp(vcpu, err);
6917 u8 cr8_prev = kvm_get_cr8(vcpu);
6919 err = kvm_set_cr8(vcpu, cr8);
6920 ret = kvm_complete_insn_gp(vcpu, err);
6921 if (lapic_in_kernel(vcpu))
6923 if (cr8_prev <= cr8)
6926 * TODO: we might be squashing a
6927 * KVM_GUESTDBG_SINGLESTEP-triggered
6928 * KVM_EXIT_DEBUG here.
6930 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
6936 WARN_ONCE(1, "Guest should always own CR0.TS");
6937 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6938 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6939 return kvm_skip_emulated_instruction(vcpu);
6940 case 1: /*mov from cr*/
6943 WARN_ON_ONCE(enable_unrestricted_guest);
6944 val = kvm_read_cr3(vcpu);
6945 kvm_register_write(vcpu, reg, val);
6946 trace_kvm_cr_read(cr, val);
6947 return kvm_skip_emulated_instruction(vcpu);
6949 val = kvm_get_cr8(vcpu);
6950 kvm_register_write(vcpu, reg, val);
6951 trace_kvm_cr_read(cr, val);
6952 return kvm_skip_emulated_instruction(vcpu);
6956 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6957 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6958 kvm_lmsw(vcpu, val);
6960 return kvm_skip_emulated_instruction(vcpu);
6964 vcpu->run->exit_reason = 0;
6965 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6966 (int)(exit_qualification >> 4) & 3, cr);
6970 static int handle_dr(struct kvm_vcpu *vcpu)
6972 unsigned long exit_qualification;
6975 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6976 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6978 /* First, if DR does not exist, trigger UD */
6979 if (!kvm_require_dr(vcpu, dr))
6982 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6983 if (!kvm_require_cpl(vcpu, 0))
6985 dr7 = vmcs_readl(GUEST_DR7);
6988 * As the vm-exit takes precedence over the debug trap, we
6989 * need to emulate the latter, either for the host or the
6990 * guest debugging itself.
6992 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6993 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6994 vcpu->run->debug.arch.dr7 = dr7;
6995 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6996 vcpu->run->debug.arch.exception = DB_VECTOR;
6997 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
7000 vcpu->arch.dr6 &= ~15;
7001 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
7002 kvm_queue_exception(vcpu, DB_VECTOR);
7007 if (vcpu->guest_debug == 0) {
7008 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7009 CPU_BASED_MOV_DR_EXITING);
7012 * No more DR vmexits; force a reload of the debug registers
7013 * and reenter on this instruction. The next vmexit will
7014 * retrieve the full state of the debug registers.
7016 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
7020 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
7021 if (exit_qualification & TYPE_MOV_FROM_DR) {
7024 if (kvm_get_dr(vcpu, dr, &val))
7026 kvm_register_write(vcpu, reg, val);
7028 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
7031 return kvm_skip_emulated_instruction(vcpu);
7034 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
7036 return vcpu->arch.dr6;
7039 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
7043 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
7045 get_debugreg(vcpu->arch.db[0], 0);
7046 get_debugreg(vcpu->arch.db[1], 1);
7047 get_debugreg(vcpu->arch.db[2], 2);
7048 get_debugreg(vcpu->arch.db[3], 3);
7049 get_debugreg(vcpu->arch.dr6, 6);
7050 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
7052 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
7053 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
7056 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
7058 vmcs_writel(GUEST_DR7, val);
7061 static int handle_cpuid(struct kvm_vcpu *vcpu)
7063 return kvm_emulate_cpuid(vcpu);
7066 static int handle_rdmsr(struct kvm_vcpu *vcpu)
7068 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7069 struct msr_data msr_info;
7071 msr_info.index = ecx;
7072 msr_info.host_initiated = false;
7073 if (vmx_get_msr(vcpu, &msr_info)) {
7074 trace_kvm_msr_read_ex(ecx);
7075 kvm_inject_gp(vcpu, 0);
7079 trace_kvm_msr_read(ecx, msr_info.data);
7081 /* FIXME: handling of bits 32:63 of rax, rdx */
7082 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
7083 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
7084 return kvm_skip_emulated_instruction(vcpu);
7087 static int handle_wrmsr(struct kvm_vcpu *vcpu)
7089 struct msr_data msr;
7090 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
7091 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
7092 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
7096 msr.host_initiated = false;
7097 if (kvm_set_msr(vcpu, &msr) != 0) {
7098 trace_kvm_msr_write_ex(ecx, data);
7099 kvm_inject_gp(vcpu, 0);
7103 trace_kvm_msr_write(ecx, data);
7104 return kvm_skip_emulated_instruction(vcpu);
7107 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
7109 kvm_apic_update_ppr(vcpu);
7113 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
7115 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7116 CPU_BASED_VIRTUAL_INTR_PENDING);
7118 kvm_make_request(KVM_REQ_EVENT, vcpu);
7120 ++vcpu->stat.irq_window_exits;
7124 static int handle_halt(struct kvm_vcpu *vcpu)
7126 return kvm_emulate_halt(vcpu);
7129 static int handle_vmcall(struct kvm_vcpu *vcpu)
7131 return kvm_emulate_hypercall(vcpu);
7134 static int handle_invd(struct kvm_vcpu *vcpu)
7136 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
7139 static int handle_invlpg(struct kvm_vcpu *vcpu)
7141 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7143 kvm_mmu_invlpg(vcpu, exit_qualification);
7144 return kvm_skip_emulated_instruction(vcpu);
7147 static int handle_rdpmc(struct kvm_vcpu *vcpu)
7151 err = kvm_rdpmc(vcpu);
7152 return kvm_complete_insn_gp(vcpu, err);
7155 static int handle_wbinvd(struct kvm_vcpu *vcpu)
7157 return kvm_emulate_wbinvd(vcpu);
7160 static int handle_xsetbv(struct kvm_vcpu *vcpu)
7162 u64 new_bv = kvm_read_edx_eax(vcpu);
7163 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
7165 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
7166 return kvm_skip_emulated_instruction(vcpu);
7170 static int handle_xsaves(struct kvm_vcpu *vcpu)
7172 kvm_skip_emulated_instruction(vcpu);
7173 WARN(1, "this should never happen\n");
7177 static int handle_xrstors(struct kvm_vcpu *vcpu)
7179 kvm_skip_emulated_instruction(vcpu);
7180 WARN(1, "this should never happen\n");
7184 static int handle_apic_access(struct kvm_vcpu *vcpu)
7186 if (likely(fasteoi)) {
7187 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7188 int access_type, offset;
7190 access_type = exit_qualification & APIC_ACCESS_TYPE;
7191 offset = exit_qualification & APIC_ACCESS_OFFSET;
7193 * Sane guest uses MOV to write EOI, with written value
7194 * not cared. So make a short-circuit here by avoiding
7195 * heavy instruction emulation.
7197 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
7198 (offset == APIC_EOI)) {
7199 kvm_lapic_set_eoi(vcpu);
7200 return kvm_skip_emulated_instruction(vcpu);
7203 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
7206 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
7208 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7209 int vector = exit_qualification & 0xff;
7211 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
7212 kvm_apic_set_eoi_accelerated(vcpu, vector);
7216 static int handle_apic_write(struct kvm_vcpu *vcpu)
7218 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7219 u32 offset = exit_qualification & 0xfff;
7221 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
7222 kvm_apic_write_nodecode(vcpu, offset);
7226 static int handle_task_switch(struct kvm_vcpu *vcpu)
7228 struct vcpu_vmx *vmx = to_vmx(vcpu);
7229 unsigned long exit_qualification;
7230 bool has_error_code = false;
7233 int reason, type, idt_v, idt_index;
7235 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7236 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
7237 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
7239 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7241 reason = (u32)exit_qualification >> 30;
7242 if (reason == TASK_SWITCH_GATE && idt_v) {
7244 case INTR_TYPE_NMI_INTR:
7245 vcpu->arch.nmi_injected = false;
7246 vmx_set_nmi_mask(vcpu, true);
7248 case INTR_TYPE_EXT_INTR:
7249 case INTR_TYPE_SOFT_INTR:
7250 kvm_clear_interrupt_queue(vcpu);
7252 case INTR_TYPE_HARD_EXCEPTION:
7253 if (vmx->idt_vectoring_info &
7254 VECTORING_INFO_DELIVER_CODE_MASK) {
7255 has_error_code = true;
7257 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7260 case INTR_TYPE_SOFT_EXCEPTION:
7261 kvm_clear_exception_queue(vcpu);
7267 tss_selector = exit_qualification;
7269 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
7270 type != INTR_TYPE_EXT_INTR &&
7271 type != INTR_TYPE_NMI_INTR))
7272 skip_emulated_instruction(vcpu);
7274 if (kvm_task_switch(vcpu, tss_selector,
7275 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
7276 has_error_code, error_code) == EMULATE_FAIL) {
7277 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7278 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7279 vcpu->run->internal.ndata = 0;
7284 * TODO: What about debug traps on tss switch?
7285 * Are we supposed to inject them and update dr6?
7291 static int handle_ept_violation(struct kvm_vcpu *vcpu)
7293 unsigned long exit_qualification;
7297 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7300 * EPT violation happened while executing iret from NMI,
7301 * "blocked by NMI" bit has to be set before next VM entry.
7302 * There are errata that may cause this bit to not be set:
7305 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7307 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7308 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
7310 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7311 trace_kvm_page_fault(gpa, exit_qualification);
7313 /* Is it a read fault? */
7314 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
7315 ? PFERR_USER_MASK : 0;
7316 /* Is it a write fault? */
7317 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
7318 ? PFERR_WRITE_MASK : 0;
7319 /* Is it a fetch fault? */
7320 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
7321 ? PFERR_FETCH_MASK : 0;
7322 /* ept page table entry is present? */
7323 error_code |= (exit_qualification &
7324 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
7325 EPT_VIOLATION_EXECUTABLE))
7326 ? PFERR_PRESENT_MASK : 0;
7328 error_code |= (exit_qualification & 0x100) != 0 ?
7329 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
7331 vcpu->arch.exit_qualification = exit_qualification;
7332 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
7335 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
7340 * A nested guest cannot optimize MMIO vmexits, because we have an
7341 * nGPA here instead of the required GPA.
7343 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
7344 if (!is_guest_mode(vcpu) &&
7345 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
7346 trace_kvm_fast_mmio(gpa);
7348 * Doing kvm_skip_emulated_instruction() depends on undefined
7349 * behavior: Intel's manual doesn't mandate
7350 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
7351 * occurs and while on real hardware it was observed to be set,
7352 * other hypervisors (namely Hyper-V) don't set it, we end up
7353 * advancing IP with some random value. Disable fast mmio when
7354 * running nested and keep it for real hardware in hope that
7355 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
7357 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
7358 return kvm_skip_emulated_instruction(vcpu);
7360 return x86_emulate_instruction(vcpu, gpa, EMULTYPE_SKIP,
7361 NULL, 0) == EMULATE_DONE;
7364 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
7367 static int handle_nmi_window(struct kvm_vcpu *vcpu)
7369 WARN_ON_ONCE(!enable_vnmi);
7370 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
7371 CPU_BASED_VIRTUAL_NMI_PENDING);
7372 ++vcpu->stat.nmi_window_exits;
7373 kvm_make_request(KVM_REQ_EVENT, vcpu);
7378 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
7380 struct vcpu_vmx *vmx = to_vmx(vcpu);
7381 enum emulation_result err = EMULATE_DONE;
7384 bool intr_window_requested;
7385 unsigned count = 130;
7388 * We should never reach the point where we are emulating L2
7389 * due to invalid guest state as that means we incorrectly
7390 * allowed a nested VMEntry with an invalid vmcs12.
7392 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
7394 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7395 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
7397 while (vmx->emulation_required && count-- != 0) {
7398 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
7399 return handle_interrupt_window(&vmx->vcpu);
7401 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
7404 err = emulate_instruction(vcpu, 0);
7406 if (err == EMULATE_USER_EXIT) {
7407 ++vcpu->stat.mmio_exits;
7412 if (err != EMULATE_DONE)
7413 goto emulation_error;
7415 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
7416 vcpu->arch.exception.pending)
7417 goto emulation_error;
7419 if (vcpu->arch.halt_request) {
7420 vcpu->arch.halt_request = 0;
7421 ret = kvm_vcpu_halt(vcpu);
7425 if (signal_pending(current))
7435 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7436 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7437 vcpu->run->internal.ndata = 0;
7441 static void grow_ple_window(struct kvm_vcpu *vcpu)
7443 struct vcpu_vmx *vmx = to_vmx(vcpu);
7444 int old = vmx->ple_window;
7446 vmx->ple_window = __grow_ple_window(old, ple_window,
7450 if (vmx->ple_window != old)
7451 vmx->ple_window_dirty = true;
7453 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
7456 static void shrink_ple_window(struct kvm_vcpu *vcpu)
7458 struct vcpu_vmx *vmx = to_vmx(vcpu);
7459 int old = vmx->ple_window;
7461 vmx->ple_window = __shrink_ple_window(old, ple_window,
7465 if (vmx->ple_window != old)
7466 vmx->ple_window_dirty = true;
7468 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
7472 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
7474 static void wakeup_handler(void)
7476 struct kvm_vcpu *vcpu;
7477 int cpu = smp_processor_id();
7479 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7480 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
7481 blocked_vcpu_list) {
7482 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
7484 if (pi_test_on(pi_desc) == 1)
7485 kvm_vcpu_kick(vcpu);
7487 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
7490 static void vmx_enable_tdp(void)
7492 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
7493 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
7494 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
7495 0ull, VMX_EPT_EXECUTABLE_MASK,
7496 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
7497 VMX_EPT_RWX_MASK, 0ull);
7499 ept_set_mmio_spte_mask();
7503 static __init int hardware_setup(void)
7507 rdmsrl_safe(MSR_EFER, &host_efer);
7509 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7510 kvm_define_shared_msr(i, vmx_msr_index[i]);
7512 for (i = 0; i < VMX_BITMAP_NR; i++) {
7513 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
7518 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
7519 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
7521 if (setup_vmcs_config(&vmcs_config) < 0) {
7526 if (boot_cpu_has(X86_FEATURE_NX))
7527 kvm_enable_efer_bits(EFER_NX);
7529 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7530 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7533 if (!cpu_has_vmx_ept() ||
7534 !cpu_has_vmx_ept_4levels() ||
7535 !cpu_has_vmx_ept_mt_wb() ||
7536 !cpu_has_vmx_invept_global())
7539 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7540 enable_ept_ad_bits = 0;
7542 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7543 enable_unrestricted_guest = 0;
7545 if (!cpu_has_vmx_flexpriority())
7546 flexpriority_enabled = 0;
7548 if (!cpu_has_virtual_nmis())
7552 * set_apic_access_page_addr() is used to reload apic access
7553 * page upon invalidation. No need to do anything if not
7554 * using the APIC_ACCESS_ADDR VMCS field.
7556 if (!flexpriority_enabled)
7557 kvm_x86_ops->set_apic_access_page_addr = NULL;
7559 if (!cpu_has_vmx_tpr_shadow())
7560 kvm_x86_ops->update_cr8_intercept = NULL;
7562 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7563 kvm_disable_largepages();
7565 if (!cpu_has_vmx_ple()) {
7568 ple_window_grow = 0;
7570 ple_window_shrink = 0;
7573 if (!cpu_has_vmx_apicv()) {
7575 kvm_x86_ops->sync_pir_to_irr = NULL;
7578 if (cpu_has_vmx_tsc_scaling()) {
7579 kvm_has_tsc_control = true;
7580 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7581 kvm_tsc_scaling_ratio_frac_bits = 48;
7584 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7592 * Only enable PML when hardware supports PML feature, and both EPT
7593 * and EPT A/D bit features are enabled -- PML depends on them to work.
7595 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7599 kvm_x86_ops->slot_enable_log_dirty = NULL;
7600 kvm_x86_ops->slot_disable_log_dirty = NULL;
7601 kvm_x86_ops->flush_log_dirty = NULL;
7602 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7605 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7608 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7609 cpu_preemption_timer_multi =
7610 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7612 kvm_x86_ops->set_hv_timer = NULL;
7613 kvm_x86_ops->cancel_hv_timer = NULL;
7616 if (!cpu_has_vmx_shadow_vmcs())
7617 enable_shadow_vmcs = 0;
7618 if (enable_shadow_vmcs)
7619 init_vmcs_shadow_fields();
7621 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7622 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, enable_apicv);
7624 kvm_mce_cap_supported |= MCG_LMCE_P;
7626 return alloc_kvm_area();
7629 for (i = 0; i < VMX_BITMAP_NR; i++)
7630 free_page((unsigned long)vmx_bitmap[i]);
7635 static __exit void hardware_unsetup(void)
7639 for (i = 0; i < VMX_BITMAP_NR; i++)
7640 free_page((unsigned long)vmx_bitmap[i]);
7646 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
7647 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
7649 static int handle_pause(struct kvm_vcpu *vcpu)
7651 if (!kvm_pause_in_guest(vcpu->kvm))
7652 grow_ple_window(vcpu);
7655 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
7656 * VM-execution control is ignored if CPL > 0. OTOH, KVM
7657 * never set PAUSE_EXITING and just set PLE if supported,
7658 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
7660 kvm_vcpu_on_spin(vcpu, true);
7661 return kvm_skip_emulated_instruction(vcpu);
7664 static int handle_nop(struct kvm_vcpu *vcpu)
7666 return kvm_skip_emulated_instruction(vcpu);
7669 static int handle_mwait(struct kvm_vcpu *vcpu)
7671 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
7672 return handle_nop(vcpu);
7675 static int handle_invalid_op(struct kvm_vcpu *vcpu)
7677 kvm_queue_exception(vcpu, UD_VECTOR);
7681 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
7686 static int handle_monitor(struct kvm_vcpu *vcpu)
7688 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
7689 return handle_nop(vcpu);
7693 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7694 * set the success or error code of an emulated VMX instruction, as specified
7695 * by Vol 2B, VMX Instruction Reference, "Conventions".
7697 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
7699 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
7700 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7701 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
7704 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
7706 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7707 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
7708 X86_EFLAGS_SF | X86_EFLAGS_OF))
7712 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
7713 u32 vm_instruction_error)
7715 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
7717 * failValid writes the error number to the current VMCS, which
7718 * can't be done there isn't a current VMCS.
7720 nested_vmx_failInvalid(vcpu);
7723 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7724 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7725 X86_EFLAGS_SF | X86_EFLAGS_OF))
7727 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
7729 * We don't need to force a shadow sync because
7730 * VM_INSTRUCTION_ERROR is not shadowed
7734 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
7736 /* TODO: not to reset guest simply here. */
7737 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7738 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
7741 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
7743 struct vcpu_vmx *vmx =
7744 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
7746 vmx->nested.preemption_timer_expired = true;
7747 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
7748 kvm_vcpu_kick(&vmx->vcpu);
7750 return HRTIMER_NORESTART;
7754 * Decode the memory-address operand of a vmx instruction, as recorded on an
7755 * exit caused by such an instruction (run by a guest hypervisor).
7756 * On success, returns 0. When the operand is invalid, returns 1 and throws
7759 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
7760 unsigned long exit_qualification,
7761 u32 vmx_instruction_info, bool wr, gva_t *ret)
7765 struct kvm_segment s;
7768 * According to Vol. 3B, "Information for VM Exits Due to Instruction
7769 * Execution", on an exit, vmx_instruction_info holds most of the
7770 * addressing components of the operand. Only the displacement part
7771 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7772 * For how an actual address is calculated from all these components,
7773 * refer to Vol. 1, "Operand Addressing".
7775 int scaling = vmx_instruction_info & 3;
7776 int addr_size = (vmx_instruction_info >> 7) & 7;
7777 bool is_reg = vmx_instruction_info & (1u << 10);
7778 int seg_reg = (vmx_instruction_info >> 15) & 7;
7779 int index_reg = (vmx_instruction_info >> 18) & 0xf;
7780 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
7781 int base_reg = (vmx_instruction_info >> 23) & 0xf;
7782 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
7785 kvm_queue_exception(vcpu, UD_VECTOR);
7789 /* Addr = segment_base + offset */
7790 /* offset = base + [index * scale] + displacement */
7791 off = exit_qualification; /* holds the displacement */
7793 off += kvm_register_read(vcpu, base_reg);
7795 off += kvm_register_read(vcpu, index_reg)<<scaling;
7796 vmx_get_segment(vcpu, &s, seg_reg);
7797 *ret = s.base + off;
7799 if (addr_size == 1) /* 32 bit */
7802 /* Checks for #GP/#SS exceptions. */
7804 if (is_long_mode(vcpu)) {
7805 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7806 * non-canonical form. This is the only check on the memory
7807 * destination for long mode!
7809 exn = is_noncanonical_address(*ret, vcpu);
7810 } else if (is_protmode(vcpu)) {
7811 /* Protected mode: apply checks for segment validity in the
7813 * - segment type check (#GP(0) may be thrown)
7814 * - usability check (#GP(0)/#SS(0))
7815 * - limit check (#GP(0)/#SS(0))
7818 /* #GP(0) if the destination operand is located in a
7819 * read-only data segment or any code segment.
7821 exn = ((s.type & 0xa) == 0 || (s.type & 8));
7823 /* #GP(0) if the source operand is located in an
7824 * execute-only code segment
7826 exn = ((s.type & 0xa) == 8);
7828 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7831 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7833 exn = (s.unusable != 0);
7834 /* Protected mode: #GP(0)/#SS(0) if the memory
7835 * operand is outside the segment limit.
7837 exn = exn || (off + sizeof(u64) > s.limit);
7840 kvm_queue_exception_e(vcpu,
7841 seg_reg == VCPU_SREG_SS ?
7842 SS_VECTOR : GP_VECTOR,
7850 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7853 struct x86_exception e;
7855 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7856 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7859 if (kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e)) {
7860 kvm_inject_page_fault(vcpu, &e);
7867 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7869 struct vcpu_vmx *vmx = to_vmx(vcpu);
7870 struct vmcs *shadow_vmcs;
7873 r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
7877 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7878 if (!vmx->nested.cached_vmcs12)
7879 goto out_cached_vmcs12;
7881 if (enable_shadow_vmcs) {
7882 shadow_vmcs = alloc_vmcs();
7884 goto out_shadow_vmcs;
7885 /* mark vmcs as shadow */
7886 shadow_vmcs->revision_id |= (1u << 31);
7887 /* init shadow vmcs */
7888 vmcs_clear(shadow_vmcs);
7889 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7892 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7893 HRTIMER_MODE_REL_PINNED);
7894 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7896 vmx->nested.vmxon = true;
7900 kfree(vmx->nested.cached_vmcs12);
7903 free_loaded_vmcs(&vmx->nested.vmcs02);
7910 * Emulate the VMXON instruction.
7911 * Currently, we just remember that VMX is active, and do not save or even
7912 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7913 * do not currently need to store anything in that guest-allocated memory
7914 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7915 * argument is different from the VMXON pointer (which the spec says they do).
7917 static int handle_vmon(struct kvm_vcpu *vcpu)
7922 struct vcpu_vmx *vmx = to_vmx(vcpu);
7923 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7924 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7927 * The Intel VMX Instruction Reference lists a bunch of bits that are
7928 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7929 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7930 * Otherwise, we should fail with #UD. But most faulting conditions
7931 * have already been checked by hardware, prior to the VM-exit for
7932 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7933 * that bit set to 1 in non-root mode.
7935 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7936 kvm_queue_exception(vcpu, UD_VECTOR);
7940 /* CPL=0 must be checked manually. */
7941 if (vmx_get_cpl(vcpu)) {
7942 kvm_queue_exception(vcpu, UD_VECTOR);
7946 if (vmx->nested.vmxon) {
7947 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7948 return kvm_skip_emulated_instruction(vcpu);
7951 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7952 != VMXON_NEEDED_FEATURES) {
7953 kvm_inject_gp(vcpu, 0);
7957 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7962 * The first 4 bytes of VMXON region contain the supported
7963 * VMCS revision identifier
7965 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7966 * which replaces physical address width with 32
7968 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7969 nested_vmx_failInvalid(vcpu);
7970 return kvm_skip_emulated_instruction(vcpu);
7973 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7974 if (is_error_page(page)) {
7975 nested_vmx_failInvalid(vcpu);
7976 return kvm_skip_emulated_instruction(vcpu);
7978 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7980 kvm_release_page_clean(page);
7981 nested_vmx_failInvalid(vcpu);
7982 return kvm_skip_emulated_instruction(vcpu);
7985 kvm_release_page_clean(page);
7987 vmx->nested.vmxon_ptr = vmptr;
7988 ret = enter_vmx_operation(vcpu);
7992 nested_vmx_succeed(vcpu);
7993 return kvm_skip_emulated_instruction(vcpu);
7997 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7998 * for running VMX instructions (except VMXON, whose prerequisites are
7999 * slightly different). It also specifies what exception to inject otherwise.
8000 * Note that many of these exceptions have priority over VM exits, so they
8001 * don't have to be checked again here.
8003 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
8005 if (vmx_get_cpl(vcpu)) {
8006 kvm_queue_exception(vcpu, UD_VECTOR);
8010 if (!to_vmx(vcpu)->nested.vmxon) {
8011 kvm_queue_exception(vcpu, UD_VECTOR);
8017 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
8019 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
8020 vmcs_write64(VMCS_LINK_POINTER, -1ull);
8023 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
8025 if (vmx->nested.current_vmptr == -1ull)
8028 if (enable_shadow_vmcs) {
8029 /* copy to memory all shadowed fields in case
8030 they were modified */
8031 copy_shadow_to_vmcs12(vmx);
8032 vmx->nested.sync_shadow_vmcs = false;
8033 vmx_disable_shadow_vmcs(vmx);
8035 vmx->nested.posted_intr_nv = -1;
8037 /* Flush VMCS12 to guest memory */
8038 kvm_vcpu_write_guest_page(&vmx->vcpu,
8039 vmx->nested.current_vmptr >> PAGE_SHIFT,
8040 vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
8042 vmx->nested.current_vmptr = -1ull;
8046 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
8047 * just stops using VMX.
8049 static void free_nested(struct vcpu_vmx *vmx)
8051 if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon)
8054 vmx->nested.vmxon = false;
8055 vmx->nested.smm.vmxon = false;
8056 free_vpid(vmx->nested.vpid02);
8057 vmx->nested.posted_intr_nv = -1;
8058 vmx->nested.current_vmptr = -1ull;
8059 if (enable_shadow_vmcs) {
8060 vmx_disable_shadow_vmcs(vmx);
8061 vmcs_clear(vmx->vmcs01.shadow_vmcs);
8062 free_vmcs(vmx->vmcs01.shadow_vmcs);
8063 vmx->vmcs01.shadow_vmcs = NULL;
8065 kfree(vmx->nested.cached_vmcs12);
8066 /* Unpin physical memory we referred to in the vmcs02 */
8067 if (vmx->nested.apic_access_page) {
8068 kvm_release_page_dirty(vmx->nested.apic_access_page);
8069 vmx->nested.apic_access_page = NULL;
8071 if (vmx->nested.virtual_apic_page) {
8072 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
8073 vmx->nested.virtual_apic_page = NULL;
8075 if (vmx->nested.pi_desc_page) {
8076 kunmap(vmx->nested.pi_desc_page);
8077 kvm_release_page_dirty(vmx->nested.pi_desc_page);
8078 vmx->nested.pi_desc_page = NULL;
8079 vmx->nested.pi_desc = NULL;
8082 free_loaded_vmcs(&vmx->nested.vmcs02);
8085 /* Emulate the VMXOFF instruction */
8086 static int handle_vmoff(struct kvm_vcpu *vcpu)
8088 if (!nested_vmx_check_permission(vcpu))
8090 free_nested(to_vmx(vcpu));
8091 nested_vmx_succeed(vcpu);
8092 return kvm_skip_emulated_instruction(vcpu);
8095 /* Emulate the VMCLEAR instruction */
8096 static int handle_vmclear(struct kvm_vcpu *vcpu)
8098 struct vcpu_vmx *vmx = to_vmx(vcpu);
8102 if (!nested_vmx_check_permission(vcpu))
8105 if (nested_vmx_get_vmptr(vcpu, &vmptr))
8108 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8109 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
8110 return kvm_skip_emulated_instruction(vcpu);
8113 if (vmptr == vmx->nested.vmxon_ptr) {
8114 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
8115 return kvm_skip_emulated_instruction(vcpu);
8118 if (vmptr == vmx->nested.current_vmptr)
8119 nested_release_vmcs12(vmx);
8121 kvm_vcpu_write_guest(vcpu,
8122 vmptr + offsetof(struct vmcs12, launch_state),
8123 &zero, sizeof(zero));
8125 nested_vmx_succeed(vcpu);
8126 return kvm_skip_emulated_instruction(vcpu);
8129 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
8131 /* Emulate the VMLAUNCH instruction */
8132 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
8134 return nested_vmx_run(vcpu, true);
8137 /* Emulate the VMRESUME instruction */
8138 static int handle_vmresume(struct kvm_vcpu *vcpu)
8141 return nested_vmx_run(vcpu, false);
8145 * Read a vmcs12 field. Since these can have varying lengths and we return
8146 * one type, we chose the biggest type (u64) and zero-extend the return value
8147 * to that size. Note that the caller, handle_vmread, might need to use only
8148 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
8149 * 64-bit fields are to be returned).
8151 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
8152 unsigned long field, u64 *ret)
8154 short offset = vmcs_field_to_offset(field);
8160 p = ((char *)(get_vmcs12(vcpu))) + offset;
8162 switch (vmcs_field_width(field)) {
8163 case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8164 *ret = *((natural_width *)p);
8166 case VMCS_FIELD_WIDTH_U16:
8169 case VMCS_FIELD_WIDTH_U32:
8172 case VMCS_FIELD_WIDTH_U64:
8182 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
8183 unsigned long field, u64 field_value){
8184 short offset = vmcs_field_to_offset(field);
8185 char *p = ((char *) get_vmcs12(vcpu)) + offset;
8189 switch (vmcs_field_width(field)) {
8190 case VMCS_FIELD_WIDTH_U16:
8191 *(u16 *)p = field_value;
8193 case VMCS_FIELD_WIDTH_U32:
8194 *(u32 *)p = field_value;
8196 case VMCS_FIELD_WIDTH_U64:
8197 *(u64 *)p = field_value;
8199 case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
8200 *(natural_width *)p = field_value;
8210 * Copy the writable VMCS shadow fields back to the VMCS12, in case
8211 * they have been modified by the L1 guest. Note that the "read-only"
8212 * VM-exit information fields are actually writable if the vCPU is
8213 * configured to support "VMWRITE to any supported field in the VMCS."
8215 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
8217 const u16 *fields[] = {
8218 shadow_read_write_fields,
8219 shadow_read_only_fields
8221 const int max_fields[] = {
8222 max_shadow_read_write_fields,
8223 max_shadow_read_only_fields
8226 unsigned long field;
8228 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8232 vmcs_load(shadow_vmcs);
8234 for (q = 0; q < ARRAY_SIZE(fields); q++) {
8235 for (i = 0; i < max_fields[q]; i++) {
8236 field = fields[q][i];
8237 field_value = __vmcs_readl(field);
8238 vmcs12_write_any(&vmx->vcpu, field, field_value);
8241 * Skip the VM-exit information fields if they are read-only.
8243 if (!nested_cpu_has_vmwrite_any_field(&vmx->vcpu))
8247 vmcs_clear(shadow_vmcs);
8248 vmcs_load(vmx->loaded_vmcs->vmcs);
8253 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
8255 const u16 *fields[] = {
8256 shadow_read_write_fields,
8257 shadow_read_only_fields
8259 const int max_fields[] = {
8260 max_shadow_read_write_fields,
8261 max_shadow_read_only_fields
8264 unsigned long field;
8265 u64 field_value = 0;
8266 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
8268 vmcs_load(shadow_vmcs);
8270 for (q = 0; q < ARRAY_SIZE(fields); q++) {
8271 for (i = 0; i < max_fields[q]; i++) {
8272 field = fields[q][i];
8273 vmcs12_read_any(&vmx->vcpu, field, &field_value);
8274 __vmcs_writel(field, field_value);
8278 vmcs_clear(shadow_vmcs);
8279 vmcs_load(vmx->loaded_vmcs->vmcs);
8283 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
8284 * used before) all generate the same failure when it is missing.
8286 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
8288 struct vcpu_vmx *vmx = to_vmx(vcpu);
8289 if (vmx->nested.current_vmptr == -1ull) {
8290 nested_vmx_failInvalid(vcpu);
8296 static int handle_vmread(struct kvm_vcpu *vcpu)
8298 unsigned long field;
8300 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8301 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8304 if (!nested_vmx_check_permission(vcpu))
8307 if (!nested_vmx_check_vmcs12(vcpu))
8308 return kvm_skip_emulated_instruction(vcpu);
8310 /* Decode instruction info and find the field to read */
8311 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8312 /* Read the field, zero-extended to a u64 field_value */
8313 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
8314 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8315 return kvm_skip_emulated_instruction(vcpu);
8318 * Now copy part of this value to register or memory, as requested.
8319 * Note that the number of bits actually copied is 32 or 64 depending
8320 * on the guest's mode (32 or 64 bit), not on the given field's length.
8322 if (vmx_instruction_info & (1u << 10)) {
8323 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
8326 if (get_vmx_mem_address(vcpu, exit_qualification,
8327 vmx_instruction_info, true, &gva))
8329 /* _system ok, nested_vmx_check_permission has verified cpl=0 */
8330 kvm_write_guest_virt_system(vcpu, gva, &field_value,
8331 (is_long_mode(vcpu) ? 8 : 4), NULL);
8334 nested_vmx_succeed(vcpu);
8335 return kvm_skip_emulated_instruction(vcpu);
8339 static int handle_vmwrite(struct kvm_vcpu *vcpu)
8341 unsigned long field;
8343 struct vcpu_vmx *vmx = to_vmx(vcpu);
8344 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8345 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8347 /* The value to write might be 32 or 64 bits, depending on L1's long
8348 * mode, and eventually we need to write that into a field of several
8349 * possible lengths. The code below first zero-extends the value to 64
8350 * bit (field_value), and then copies only the appropriate number of
8351 * bits into the vmcs12 field.
8353 u64 field_value = 0;
8354 struct x86_exception e;
8356 if (!nested_vmx_check_permission(vcpu))
8359 if (!nested_vmx_check_vmcs12(vcpu))
8360 return kvm_skip_emulated_instruction(vcpu);
8362 if (vmx_instruction_info & (1u << 10))
8363 field_value = kvm_register_readl(vcpu,
8364 (((vmx_instruction_info) >> 3) & 0xf));
8366 if (get_vmx_mem_address(vcpu, exit_qualification,
8367 vmx_instruction_info, false, &gva))
8369 if (kvm_read_guest_virt(vcpu, gva, &field_value,
8370 (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
8371 kvm_inject_page_fault(vcpu, &e);
8377 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
8379 * If the vCPU supports "VMWRITE to any supported field in the
8380 * VMCS," then the "read-only" fields are actually read/write.
8382 if (vmcs_field_readonly(field) &&
8383 !nested_cpu_has_vmwrite_any_field(vcpu)) {
8384 nested_vmx_failValid(vcpu,
8385 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
8386 return kvm_skip_emulated_instruction(vcpu);
8389 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
8390 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
8391 return kvm_skip_emulated_instruction(vcpu);
8395 #define SHADOW_FIELD_RW(x) case x:
8396 #include "vmx_shadow_fields.h"
8398 * The fields that can be updated by L1 without a vmexit are
8399 * always updated in the vmcs02, the others go down the slow
8400 * path of prepare_vmcs02.
8404 vmx->nested.dirty_vmcs12 = true;
8408 nested_vmx_succeed(vcpu);
8409 return kvm_skip_emulated_instruction(vcpu);
8412 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
8414 vmx->nested.current_vmptr = vmptr;
8415 if (enable_shadow_vmcs) {
8416 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
8417 SECONDARY_EXEC_SHADOW_VMCS);
8418 vmcs_write64(VMCS_LINK_POINTER,
8419 __pa(vmx->vmcs01.shadow_vmcs));
8420 vmx->nested.sync_shadow_vmcs = true;
8422 vmx->nested.dirty_vmcs12 = true;
8425 /* Emulate the VMPTRLD instruction */
8426 static int handle_vmptrld(struct kvm_vcpu *vcpu)
8428 struct vcpu_vmx *vmx = to_vmx(vcpu);
8431 if (!nested_vmx_check_permission(vcpu))
8434 if (nested_vmx_get_vmptr(vcpu, &vmptr))
8437 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
8438 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
8439 return kvm_skip_emulated_instruction(vcpu);
8442 if (vmptr == vmx->nested.vmxon_ptr) {
8443 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
8444 return kvm_skip_emulated_instruction(vcpu);
8447 if (vmx->nested.current_vmptr != vmptr) {
8448 struct vmcs12 *new_vmcs12;
8450 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
8451 if (is_error_page(page)) {
8452 nested_vmx_failInvalid(vcpu);
8453 return kvm_skip_emulated_instruction(vcpu);
8455 new_vmcs12 = kmap(page);
8456 if (new_vmcs12->revision_id != VMCS12_REVISION) {
8458 kvm_release_page_clean(page);
8459 nested_vmx_failValid(vcpu,
8460 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
8461 return kvm_skip_emulated_instruction(vcpu);
8464 nested_release_vmcs12(vmx);
8466 * Load VMCS12 from guest memory since it is not already
8469 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
8471 kvm_release_page_clean(page);
8473 set_current_vmptr(vmx, vmptr);
8476 nested_vmx_succeed(vcpu);
8477 return kvm_skip_emulated_instruction(vcpu);
8480 /* Emulate the VMPTRST instruction */
8481 static int handle_vmptrst(struct kvm_vcpu *vcpu)
8483 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8484 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8486 struct x86_exception e;
8488 if (!nested_vmx_check_permission(vcpu))
8491 if (get_vmx_mem_address(vcpu, exit_qualification,
8492 vmx_instruction_info, true, &vmcs_gva))
8494 /* *_system ok, nested_vmx_check_permission has verified cpl=0 */
8495 if (kvm_write_guest_virt_system(vcpu, vmcs_gva,
8496 (void *)&to_vmx(vcpu)->nested.current_vmptr,
8498 kvm_inject_page_fault(vcpu, &e);
8501 nested_vmx_succeed(vcpu);
8502 return kvm_skip_emulated_instruction(vcpu);
8505 /* Emulate the INVEPT instruction */
8506 static int handle_invept(struct kvm_vcpu *vcpu)
8508 struct vcpu_vmx *vmx = to_vmx(vcpu);
8509 u32 vmx_instruction_info, types;
8512 struct x86_exception e;
8517 if (!(vmx->nested.msrs.secondary_ctls_high &
8518 SECONDARY_EXEC_ENABLE_EPT) ||
8519 !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) {
8520 kvm_queue_exception(vcpu, UD_VECTOR);
8524 if (!nested_vmx_check_permission(vcpu))
8527 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8528 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8530 types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
8532 if (type >= 32 || !(types & (1 << type))) {
8533 nested_vmx_failValid(vcpu,
8534 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8535 return kvm_skip_emulated_instruction(vcpu);
8538 /* According to the Intel VMX instruction reference, the memory
8539 * operand is read even if it isn't needed (e.g., for type==global)
8541 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8542 vmx_instruction_info, false, &gva))
8544 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
8545 kvm_inject_page_fault(vcpu, &e);
8550 case VMX_EPT_EXTENT_GLOBAL:
8552 * TODO: track mappings and invalidate
8553 * single context requests appropriately
8555 case VMX_EPT_EXTENT_CONTEXT:
8556 kvm_mmu_sync_roots(vcpu);
8557 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
8558 nested_vmx_succeed(vcpu);
8565 return kvm_skip_emulated_instruction(vcpu);
8568 static int handle_invvpid(struct kvm_vcpu *vcpu)
8570 struct vcpu_vmx *vmx = to_vmx(vcpu);
8571 u32 vmx_instruction_info;
8572 unsigned long type, types;
8574 struct x86_exception e;
8580 if (!(vmx->nested.msrs.secondary_ctls_high &
8581 SECONDARY_EXEC_ENABLE_VPID) ||
8582 !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) {
8583 kvm_queue_exception(vcpu, UD_VECTOR);
8587 if (!nested_vmx_check_permission(vcpu))
8590 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8591 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8593 types = (vmx->nested.msrs.vpid_caps &
8594 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
8596 if (type >= 32 || !(types & (1 << type))) {
8597 nested_vmx_failValid(vcpu,
8598 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8599 return kvm_skip_emulated_instruction(vcpu);
8602 /* according to the intel vmx instruction reference, the memory
8603 * operand is read even if it isn't needed (e.g., for type==global)
8605 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8606 vmx_instruction_info, false, &gva))
8608 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
8609 kvm_inject_page_fault(vcpu, &e);
8612 if (operand.vpid >> 16) {
8613 nested_vmx_failValid(vcpu,
8614 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8615 return kvm_skip_emulated_instruction(vcpu);
8619 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
8620 if (!operand.vpid ||
8621 is_noncanonical_address(operand.gla, vcpu)) {
8622 nested_vmx_failValid(vcpu,
8623 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8624 return kvm_skip_emulated_instruction(vcpu);
8626 if (cpu_has_vmx_invvpid_individual_addr() &&
8627 vmx->nested.vpid02) {
8628 __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR,
8629 vmx->nested.vpid02, operand.gla);
8631 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8633 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
8634 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
8635 if (!operand.vpid) {
8636 nested_vmx_failValid(vcpu,
8637 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8638 return kvm_skip_emulated_instruction(vcpu);
8640 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8642 case VMX_VPID_EXTENT_ALL_CONTEXT:
8643 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
8647 return kvm_skip_emulated_instruction(vcpu);
8650 nested_vmx_succeed(vcpu);
8652 return kvm_skip_emulated_instruction(vcpu);
8655 static int handle_pml_full(struct kvm_vcpu *vcpu)
8657 unsigned long exit_qualification;
8659 trace_kvm_pml_full(vcpu->vcpu_id);
8661 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8664 * PML buffer FULL happened while executing iret from NMI,
8665 * "blocked by NMI" bit has to be set before next VM entry.
8667 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
8669 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
8670 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8671 GUEST_INTR_STATE_NMI);
8674 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
8675 * here.., and there's no userspace involvement needed for PML.
8680 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8682 kvm_lapic_expired_hv_timer(vcpu);
8686 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
8688 struct vcpu_vmx *vmx = to_vmx(vcpu);
8689 int maxphyaddr = cpuid_maxphyaddr(vcpu);
8691 /* Check for memory type validity */
8692 switch (address & VMX_EPTP_MT_MASK) {
8693 case VMX_EPTP_MT_UC:
8694 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT))
8697 case VMX_EPTP_MT_WB:
8698 if (!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT))
8705 /* only 4 levels page-walk length are valid */
8706 if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
8709 /* Reserved bits should not be set */
8710 if (address >> maxphyaddr || ((address >> 7) & 0x1f))
8713 /* AD, if set, should be supported */
8714 if (address & VMX_EPTP_AD_ENABLE_BIT) {
8715 if (!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT))
8722 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
8723 struct vmcs12 *vmcs12)
8725 u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
8727 bool accessed_dirty;
8728 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
8730 if (!nested_cpu_has_eptp_switching(vmcs12) ||
8731 !nested_cpu_has_ept(vmcs12))
8734 if (index >= VMFUNC_EPTP_ENTRIES)
8738 if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
8739 &address, index * 8, 8))
8742 accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
8745 * If the (L2) guest does a vmfunc to the currently
8746 * active ept pointer, we don't have to do anything else
8748 if (vmcs12->ept_pointer != address) {
8749 if (!valid_ept_address(vcpu, address))
8752 kvm_mmu_unload(vcpu);
8753 mmu->ept_ad = accessed_dirty;
8754 mmu->base_role.ad_disabled = !accessed_dirty;
8755 vmcs12->ept_pointer = address;
8757 * TODO: Check what's the correct approach in case
8758 * mmu reload fails. Currently, we just let the next
8759 * reload potentially fail
8761 kvm_mmu_reload(vcpu);
8767 static int handle_vmfunc(struct kvm_vcpu *vcpu)
8769 struct vcpu_vmx *vmx = to_vmx(vcpu);
8770 struct vmcs12 *vmcs12;
8771 u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
8774 * VMFUNC is only supported for nested guests, but we always enable the
8775 * secondary control for simplicity; for non-nested mode, fake that we
8776 * didn't by injecting #UD.
8778 if (!is_guest_mode(vcpu)) {
8779 kvm_queue_exception(vcpu, UD_VECTOR);
8783 vmcs12 = get_vmcs12(vcpu);
8784 if ((vmcs12->vm_function_control & (1 << function)) == 0)
8789 if (nested_vmx_eptp_switching(vcpu, vmcs12))
8795 return kvm_skip_emulated_instruction(vcpu);
8798 nested_vmx_vmexit(vcpu, vmx->exit_reason,
8799 vmcs_read32(VM_EXIT_INTR_INFO),
8800 vmcs_readl(EXIT_QUALIFICATION));
8805 * The exit handlers return 1 if the exit was handled fully and guest execution
8806 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
8807 * to be done to userspace and return 0.
8809 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
8810 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
8811 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
8812 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
8813 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
8814 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
8815 [EXIT_REASON_CR_ACCESS] = handle_cr,
8816 [EXIT_REASON_DR_ACCESS] = handle_dr,
8817 [EXIT_REASON_CPUID] = handle_cpuid,
8818 [EXIT_REASON_MSR_READ] = handle_rdmsr,
8819 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
8820 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
8821 [EXIT_REASON_HLT] = handle_halt,
8822 [EXIT_REASON_INVD] = handle_invd,
8823 [EXIT_REASON_INVLPG] = handle_invlpg,
8824 [EXIT_REASON_RDPMC] = handle_rdpmc,
8825 [EXIT_REASON_VMCALL] = handle_vmcall,
8826 [EXIT_REASON_VMCLEAR] = handle_vmclear,
8827 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
8828 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
8829 [EXIT_REASON_VMPTRST] = handle_vmptrst,
8830 [EXIT_REASON_VMREAD] = handle_vmread,
8831 [EXIT_REASON_VMRESUME] = handle_vmresume,
8832 [EXIT_REASON_VMWRITE] = handle_vmwrite,
8833 [EXIT_REASON_VMOFF] = handle_vmoff,
8834 [EXIT_REASON_VMON] = handle_vmon,
8835 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
8836 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
8837 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
8838 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
8839 [EXIT_REASON_WBINVD] = handle_wbinvd,
8840 [EXIT_REASON_XSETBV] = handle_xsetbv,
8841 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
8842 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
8843 [EXIT_REASON_GDTR_IDTR] = handle_desc,
8844 [EXIT_REASON_LDTR_TR] = handle_desc,
8845 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
8846 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
8847 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
8848 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
8849 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
8850 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
8851 [EXIT_REASON_INVEPT] = handle_invept,
8852 [EXIT_REASON_INVVPID] = handle_invvpid,
8853 [EXIT_REASON_RDRAND] = handle_invalid_op,
8854 [EXIT_REASON_RDSEED] = handle_invalid_op,
8855 [EXIT_REASON_XSAVES] = handle_xsaves,
8856 [EXIT_REASON_XRSTORS] = handle_xrstors,
8857 [EXIT_REASON_PML_FULL] = handle_pml_full,
8858 [EXIT_REASON_VMFUNC] = handle_vmfunc,
8859 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
8862 static const int kvm_vmx_max_exit_handlers =
8863 ARRAY_SIZE(kvm_vmx_exit_handlers);
8865 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
8866 struct vmcs12 *vmcs12)
8868 unsigned long exit_qualification;
8869 gpa_t bitmap, last_bitmap;
8874 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
8875 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
8877 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8879 port = exit_qualification >> 16;
8880 size = (exit_qualification & 7) + 1;
8882 last_bitmap = (gpa_t)-1;
8887 bitmap = vmcs12->io_bitmap_a;
8888 else if (port < 0x10000)
8889 bitmap = vmcs12->io_bitmap_b;
8892 bitmap += (port & 0x7fff) / 8;
8894 if (last_bitmap != bitmap)
8895 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8897 if (b & (1 << (port & 7)))
8902 last_bitmap = bitmap;
8909 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8910 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8911 * disinterest in the current event (read or write a specific MSR) by using an
8912 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8914 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8915 struct vmcs12 *vmcs12, u32 exit_reason)
8917 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8920 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8924 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8925 * for the four combinations of read/write and low/high MSR numbers.
8926 * First we need to figure out which of the four to use:
8928 bitmap = vmcs12->msr_bitmap;
8929 if (exit_reason == EXIT_REASON_MSR_WRITE)
8931 if (msr_index >= 0xc0000000) {
8932 msr_index -= 0xc0000000;
8936 /* Then read the msr_index'th bit from this bitmap: */
8937 if (msr_index < 1024*8) {
8939 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8941 return 1 & (b >> (msr_index & 7));
8943 return true; /* let L1 handle the wrong parameter */
8947 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8948 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8949 * intercept (via guest_host_mask etc.) the current event.
8951 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8952 struct vmcs12 *vmcs12)
8954 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8955 int cr = exit_qualification & 15;
8959 switch ((exit_qualification >> 4) & 3) {
8960 case 0: /* mov to cr */
8961 reg = (exit_qualification >> 8) & 15;
8962 val = kvm_register_readl(vcpu, reg);
8965 if (vmcs12->cr0_guest_host_mask &
8966 (val ^ vmcs12->cr0_read_shadow))
8970 if ((vmcs12->cr3_target_count >= 1 &&
8971 vmcs12->cr3_target_value0 == val) ||
8972 (vmcs12->cr3_target_count >= 2 &&
8973 vmcs12->cr3_target_value1 == val) ||
8974 (vmcs12->cr3_target_count >= 3 &&
8975 vmcs12->cr3_target_value2 == val) ||
8976 (vmcs12->cr3_target_count >= 4 &&
8977 vmcs12->cr3_target_value3 == val))
8979 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8983 if (vmcs12->cr4_guest_host_mask &
8984 (vmcs12->cr4_read_shadow ^ val))
8988 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8994 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8995 (vmcs12->cr0_read_shadow & X86_CR0_TS))
8998 case 1: /* mov from cr */
9001 if (vmcs12->cpu_based_vm_exec_control &
9002 CPU_BASED_CR3_STORE_EXITING)
9006 if (vmcs12->cpu_based_vm_exec_control &
9007 CPU_BASED_CR8_STORE_EXITING)
9014 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
9015 * cr0. Other attempted changes are ignored, with no exit.
9017 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
9018 if (vmcs12->cr0_guest_host_mask & 0xe &
9019 (val ^ vmcs12->cr0_read_shadow))
9021 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
9022 !(vmcs12->cr0_read_shadow & 0x1) &&
9031 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
9032 * should handle it ourselves in L0 (and then continue L2). Only call this
9033 * when in is_guest_mode (L2).
9035 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
9037 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9038 struct vcpu_vmx *vmx = to_vmx(vcpu);
9039 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9041 if (vmx->nested.nested_run_pending)
9044 if (unlikely(vmx->fail)) {
9045 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
9046 vmcs_read32(VM_INSTRUCTION_ERROR));
9051 * The host physical addresses of some pages of guest memory
9052 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
9053 * Page). The CPU may write to these pages via their host
9054 * physical address while L2 is running, bypassing any
9055 * address-translation-based dirty tracking (e.g. EPT write
9058 * Mark them dirty on every exit from L2 to prevent them from
9059 * getting out of sync with dirty tracking.
9061 nested_mark_vmcs12_pages_dirty(vcpu);
9063 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
9064 vmcs_readl(EXIT_QUALIFICATION),
9065 vmx->idt_vectoring_info,
9067 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9070 switch (exit_reason) {
9071 case EXIT_REASON_EXCEPTION_NMI:
9072 if (is_nmi(intr_info))
9074 else if (is_page_fault(intr_info))
9075 return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
9076 else if (is_no_device(intr_info) &&
9077 !(vmcs12->guest_cr0 & X86_CR0_TS))
9079 else if (is_debug(intr_info) &&
9081 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
9083 else if (is_breakpoint(intr_info) &&
9084 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
9086 return vmcs12->exception_bitmap &
9087 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
9088 case EXIT_REASON_EXTERNAL_INTERRUPT:
9090 case EXIT_REASON_TRIPLE_FAULT:
9092 case EXIT_REASON_PENDING_INTERRUPT:
9093 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
9094 case EXIT_REASON_NMI_WINDOW:
9095 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
9096 case EXIT_REASON_TASK_SWITCH:
9098 case EXIT_REASON_CPUID:
9100 case EXIT_REASON_HLT:
9101 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
9102 case EXIT_REASON_INVD:
9104 case EXIT_REASON_INVLPG:
9105 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9106 case EXIT_REASON_RDPMC:
9107 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
9108 case EXIT_REASON_RDRAND:
9109 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING);
9110 case EXIT_REASON_RDSEED:
9111 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING);
9112 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
9113 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
9114 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
9115 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
9116 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
9117 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
9118 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
9119 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
9121 * VMX instructions trap unconditionally. This allows L1 to
9122 * emulate them for its L2 guest, i.e., allows 3-level nesting!
9125 case EXIT_REASON_CR_ACCESS:
9126 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
9127 case EXIT_REASON_DR_ACCESS:
9128 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
9129 case EXIT_REASON_IO_INSTRUCTION:
9130 return nested_vmx_exit_handled_io(vcpu, vmcs12);
9131 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
9132 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
9133 case EXIT_REASON_MSR_READ:
9134 case EXIT_REASON_MSR_WRITE:
9135 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
9136 case EXIT_REASON_INVALID_STATE:
9138 case EXIT_REASON_MWAIT_INSTRUCTION:
9139 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
9140 case EXIT_REASON_MONITOR_TRAP_FLAG:
9141 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
9142 case EXIT_REASON_MONITOR_INSTRUCTION:
9143 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
9144 case EXIT_REASON_PAUSE_INSTRUCTION:
9145 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
9146 nested_cpu_has2(vmcs12,
9147 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
9148 case EXIT_REASON_MCE_DURING_VMENTRY:
9150 case EXIT_REASON_TPR_BELOW_THRESHOLD:
9151 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
9152 case EXIT_REASON_APIC_ACCESS:
9153 case EXIT_REASON_APIC_WRITE:
9154 case EXIT_REASON_EOI_INDUCED:
9156 * The controls for "virtualize APIC accesses," "APIC-
9157 * register virtualization," and "virtual-interrupt
9158 * delivery" only come from vmcs12.
9161 case EXIT_REASON_EPT_VIOLATION:
9163 * L0 always deals with the EPT violation. If nested EPT is
9164 * used, and the nested mmu code discovers that the address is
9165 * missing in the guest EPT table (EPT12), the EPT violation
9166 * will be injected with nested_ept_inject_page_fault()
9169 case EXIT_REASON_EPT_MISCONFIG:
9171 * L2 never uses directly L1's EPT, but rather L0's own EPT
9172 * table (shadow on EPT) or a merged EPT table that L0 built
9173 * (EPT on EPT). So any problems with the structure of the
9174 * table is L0's fault.
9177 case EXIT_REASON_INVPCID:
9179 nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
9180 nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
9181 case EXIT_REASON_WBINVD:
9182 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
9183 case EXIT_REASON_XSETBV:
9185 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
9187 * This should never happen, since it is not possible to
9188 * set XSS to a non-zero value---neither in L1 nor in L2.
9189 * If if it were, XSS would have to be checked against
9190 * the XSS exit bitmap in vmcs12.
9192 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
9193 case EXIT_REASON_PREEMPTION_TIMER:
9195 case EXIT_REASON_PML_FULL:
9196 /* We emulate PML support to L1. */
9198 case EXIT_REASON_VMFUNC:
9199 /* VM functions are emulated through L2->L0 vmexits. */
9206 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
9208 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9211 * At this point, the exit interruption info in exit_intr_info
9212 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
9213 * we need to query the in-kernel LAPIC.
9215 WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
9216 if ((exit_intr_info &
9217 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9218 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
9219 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9220 vmcs12->vm_exit_intr_error_code =
9221 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9224 nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
9225 vmcs_readl(EXIT_QUALIFICATION));
9229 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
9231 *info1 = vmcs_readl(EXIT_QUALIFICATION);
9232 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
9235 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
9238 __free_page(vmx->pml_pg);
9243 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
9245 struct vcpu_vmx *vmx = to_vmx(vcpu);
9249 pml_idx = vmcs_read16(GUEST_PML_INDEX);
9251 /* Do nothing if PML buffer is empty */
9252 if (pml_idx == (PML_ENTITY_NUM - 1))
9255 /* PML index always points to next available PML buffer entity */
9256 if (pml_idx >= PML_ENTITY_NUM)
9261 pml_buf = page_address(vmx->pml_pg);
9262 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
9265 gpa = pml_buf[pml_idx];
9266 WARN_ON(gpa & (PAGE_SIZE - 1));
9267 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
9270 /* reset PML index */
9271 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
9275 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
9276 * Called before reporting dirty_bitmap to userspace.
9278 static void kvm_flush_pml_buffers(struct kvm *kvm)
9281 struct kvm_vcpu *vcpu;
9283 * We only need to kick vcpu out of guest mode here, as PML buffer
9284 * is flushed at beginning of all VMEXITs, and it's obvious that only
9285 * vcpus running in guest are possible to have unflushed GPAs in PML
9288 kvm_for_each_vcpu(i, vcpu, kvm)
9289 kvm_vcpu_kick(vcpu);
9292 static void vmx_dump_sel(char *name, uint32_t sel)
9294 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
9295 name, vmcs_read16(sel),
9296 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
9297 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
9298 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
9301 static void vmx_dump_dtsel(char *name, uint32_t limit)
9303 pr_err("%s limit=0x%08x, base=0x%016lx\n",
9304 name, vmcs_read32(limit),
9305 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
9308 static void dump_vmcs(void)
9310 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
9311 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
9312 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
9313 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
9314 u32 secondary_exec_control = 0;
9315 unsigned long cr4 = vmcs_readl(GUEST_CR4);
9316 u64 efer = vmcs_read64(GUEST_IA32_EFER);
9319 if (cpu_has_secondary_exec_ctrls())
9320 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9322 pr_err("*** Guest State ***\n");
9323 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9324 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
9325 vmcs_readl(CR0_GUEST_HOST_MASK));
9326 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9327 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
9328 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
9329 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
9330 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
9332 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
9333 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
9334 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
9335 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
9337 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
9338 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
9339 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
9340 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
9341 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9342 vmcs_readl(GUEST_SYSENTER_ESP),
9343 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
9344 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
9345 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
9346 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
9347 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
9348 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
9349 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
9350 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
9351 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
9352 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
9353 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
9354 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
9355 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
9356 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
9357 efer, vmcs_read64(GUEST_IA32_PAT));
9358 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
9359 vmcs_read64(GUEST_IA32_DEBUGCTL),
9360 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
9361 if (cpu_has_load_perf_global_ctrl &&
9362 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
9363 pr_err("PerfGlobCtl = 0x%016llx\n",
9364 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
9365 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
9366 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
9367 pr_err("Interruptibility = %08x ActivityState = %08x\n",
9368 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
9369 vmcs_read32(GUEST_ACTIVITY_STATE));
9370 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
9371 pr_err("InterruptStatus = %04x\n",
9372 vmcs_read16(GUEST_INTR_STATUS));
9374 pr_err("*** Host State ***\n");
9375 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
9376 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
9377 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
9378 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
9379 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
9380 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
9381 vmcs_read16(HOST_TR_SELECTOR));
9382 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
9383 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
9384 vmcs_readl(HOST_TR_BASE));
9385 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
9386 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
9387 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
9388 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
9389 vmcs_readl(HOST_CR4));
9390 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9391 vmcs_readl(HOST_IA32_SYSENTER_ESP),
9392 vmcs_read32(HOST_IA32_SYSENTER_CS),
9393 vmcs_readl(HOST_IA32_SYSENTER_EIP));
9394 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
9395 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
9396 vmcs_read64(HOST_IA32_EFER),
9397 vmcs_read64(HOST_IA32_PAT));
9398 if (cpu_has_load_perf_global_ctrl &&
9399 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9400 pr_err("PerfGlobCtl = 0x%016llx\n",
9401 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
9403 pr_err("*** Control State ***\n");
9404 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
9405 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
9406 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
9407 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
9408 vmcs_read32(EXCEPTION_BITMAP),
9409 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
9410 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
9411 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
9412 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9413 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
9414 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
9415 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
9416 vmcs_read32(VM_EXIT_INTR_INFO),
9417 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
9418 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
9419 pr_err(" reason=%08x qualification=%016lx\n",
9420 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
9421 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
9422 vmcs_read32(IDT_VECTORING_INFO_FIELD),
9423 vmcs_read32(IDT_VECTORING_ERROR_CODE));
9424 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
9425 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
9426 pr_err("TSC Multiplier = 0x%016llx\n",
9427 vmcs_read64(TSC_MULTIPLIER));
9428 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
9429 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
9430 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
9431 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
9432 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
9433 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
9434 n = vmcs_read32(CR3_TARGET_COUNT);
9435 for (i = 0; i + 1 < n; i += 4)
9436 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
9437 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
9438 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
9440 pr_err("CR3 target%u=%016lx\n",
9441 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
9442 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
9443 pr_err("PLE Gap=%08x Window=%08x\n",
9444 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
9445 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
9446 pr_err("Virtual processor ID = 0x%04x\n",
9447 vmcs_read16(VIRTUAL_PROCESSOR_ID));
9451 * The guest has exited. See if we can fix it or if we need userspace
9454 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
9456 struct vcpu_vmx *vmx = to_vmx(vcpu);
9457 u32 exit_reason = vmx->exit_reason;
9458 u32 vectoring_info = vmx->idt_vectoring_info;
9460 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
9463 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
9464 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
9465 * querying dirty_bitmap, we only need to kick all vcpus out of guest
9466 * mode as if vcpus is in root mode, the PML buffer must has been
9470 vmx_flush_pml_buffer(vcpu);
9472 /* If guest state is invalid, start emulating */
9473 if (vmx->emulation_required)
9474 return handle_invalid_guest_state(vcpu);
9476 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
9477 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
9479 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
9481 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
9482 vcpu->run->fail_entry.hardware_entry_failure_reason
9487 if (unlikely(vmx->fail)) {
9488 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
9489 vcpu->run->fail_entry.hardware_entry_failure_reason
9490 = vmcs_read32(VM_INSTRUCTION_ERROR);
9496 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
9497 * delivery event since it indicates guest is accessing MMIO.
9498 * The vm-exit can be triggered again after return to guest that
9499 * will cause infinite loop.
9501 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
9502 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
9503 exit_reason != EXIT_REASON_EPT_VIOLATION &&
9504 exit_reason != EXIT_REASON_PML_FULL &&
9505 exit_reason != EXIT_REASON_TASK_SWITCH)) {
9506 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9507 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
9508 vcpu->run->internal.ndata = 3;
9509 vcpu->run->internal.data[0] = vectoring_info;
9510 vcpu->run->internal.data[1] = exit_reason;
9511 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
9512 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
9513 vcpu->run->internal.ndata++;
9514 vcpu->run->internal.data[3] =
9515 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
9520 if (unlikely(!enable_vnmi &&
9521 vmx->loaded_vmcs->soft_vnmi_blocked)) {
9522 if (vmx_interrupt_allowed(vcpu)) {
9523 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
9524 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
9525 vcpu->arch.nmi_pending) {
9527 * This CPU don't support us in finding the end of an
9528 * NMI-blocked window if the guest runs with IRQs
9529 * disabled. So we pull the trigger after 1 s of
9530 * futile waiting, but inform the user about this.
9532 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
9533 "state on VCPU %d after 1 s timeout\n",
9534 __func__, vcpu->vcpu_id);
9535 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
9539 if (exit_reason < kvm_vmx_max_exit_handlers
9540 && kvm_vmx_exit_handlers[exit_reason])
9541 return kvm_vmx_exit_handlers[exit_reason](vcpu);
9543 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
9545 kvm_queue_exception(vcpu, UD_VECTOR);
9550 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
9552 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9554 if (is_guest_mode(vcpu) &&
9555 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9558 if (irr == -1 || tpr < irr) {
9559 vmcs_write32(TPR_THRESHOLD, 0);
9563 vmcs_write32(TPR_THRESHOLD, irr);
9566 static void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
9568 u32 sec_exec_control;
9570 if (!lapic_in_kernel(vcpu))
9573 /* Postpone execution until vmcs01 is the current VMCS. */
9574 if (is_guest_mode(vcpu)) {
9575 to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
9579 if (!cpu_need_tpr_shadow(vcpu))
9582 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9583 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9584 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
9586 switch (kvm_get_apic_mode(vcpu)) {
9587 case LAPIC_MODE_INVALID:
9588 WARN_ONCE(true, "Invalid local APIC state");
9589 case LAPIC_MODE_DISABLED:
9591 case LAPIC_MODE_XAPIC:
9592 if (flexpriority_enabled) {
9594 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9595 vmx_flush_tlb(vcpu, true);
9598 case LAPIC_MODE_X2APIC:
9599 if (cpu_has_vmx_virtualize_x2apic_mode())
9601 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9604 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
9606 vmx_update_msr_bitmap(vcpu);
9609 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
9611 if (!is_guest_mode(vcpu)) {
9612 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9613 vmx_flush_tlb(vcpu, true);
9617 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
9625 status = vmcs_read16(GUEST_INTR_STATUS);
9627 if (max_isr != old) {
9629 status |= max_isr << 8;
9630 vmcs_write16(GUEST_INTR_STATUS, status);
9634 static void vmx_set_rvi(int vector)
9642 status = vmcs_read16(GUEST_INTR_STATUS);
9643 old = (u8)status & 0xff;
9644 if ((u8)vector != old) {
9646 status |= (u8)vector;
9647 vmcs_write16(GUEST_INTR_STATUS, status);
9651 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
9654 * When running L2, updating RVI is only relevant when
9655 * vmcs12 virtual-interrupt-delivery enabled.
9656 * However, it can be enabled only when L1 also
9657 * intercepts external-interrupts and in that case
9658 * we should not update vmcs02 RVI but instead intercept
9659 * interrupt. Therefore, do nothing when running L2.
9661 if (!is_guest_mode(vcpu))
9662 vmx_set_rvi(max_irr);
9665 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
9667 struct vcpu_vmx *vmx = to_vmx(vcpu);
9669 bool max_irr_updated;
9671 WARN_ON(!vcpu->arch.apicv_active);
9672 if (pi_test_on(&vmx->pi_desc)) {
9673 pi_clear_on(&vmx->pi_desc);
9675 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
9676 * But on x86 this is just a compiler barrier anyway.
9678 smp_mb__after_atomic();
9680 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
9683 * If we are running L2 and L1 has a new pending interrupt
9684 * which can be injected, we should re-evaluate
9685 * what should be done with this new L1 interrupt.
9686 * If L1 intercepts external-interrupts, we should
9687 * exit from L2 to L1. Otherwise, interrupt should be
9688 * delivered directly to L2.
9690 if (is_guest_mode(vcpu) && max_irr_updated) {
9691 if (nested_exit_on_intr(vcpu))
9692 kvm_vcpu_exiting_guest_mode(vcpu);
9694 kvm_make_request(KVM_REQ_EVENT, vcpu);
9697 max_irr = kvm_lapic_find_highest_irr(vcpu);
9699 vmx_hwapic_irr_update(vcpu, max_irr);
9703 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
9705 if (!kvm_vcpu_apicv_active(vcpu))
9708 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
9709 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
9710 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
9711 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
9714 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
9716 struct vcpu_vmx *vmx = to_vmx(vcpu);
9718 pi_clear_on(&vmx->pi_desc);
9719 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
9722 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
9724 u32 exit_intr_info = 0;
9725 u16 basic_exit_reason = (u16)vmx->exit_reason;
9727 if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
9728 || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
9731 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9732 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9733 vmx->exit_intr_info = exit_intr_info;
9735 /* if exit due to PF check for async PF */
9736 if (is_page_fault(exit_intr_info))
9737 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
9739 /* Handle machine checks before interrupts are enabled */
9740 if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
9741 is_machine_check(exit_intr_info))
9742 kvm_machine_check();
9744 /* We need to handle NMIs before interrupts are enabled */
9745 if (is_nmi(exit_intr_info)) {
9746 kvm_before_interrupt(&vmx->vcpu);
9748 kvm_after_interrupt(&vmx->vcpu);
9752 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
9754 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9756 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
9757 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
9758 unsigned int vector;
9759 unsigned long entry;
9761 struct vcpu_vmx *vmx = to_vmx(vcpu);
9762 #ifdef CONFIG_X86_64
9766 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9767 desc = (gate_desc *)vmx->host_idt_base + vector;
9768 entry = gate_offset(desc);
9770 #ifdef CONFIG_X86_64
9771 "mov %%" _ASM_SP ", %[sp]\n\t"
9772 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
9777 __ASM_SIZE(push) " $%c[cs]\n\t"
9780 #ifdef CONFIG_X86_64
9785 THUNK_TARGET(entry),
9786 [ss]"i"(__KERNEL_DS),
9787 [cs]"i"(__KERNEL_CS)
9791 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
9793 static bool vmx_has_emulated_msr(int index)
9796 case MSR_IA32_SMBASE:
9798 * We cannot do SMM unless we can run the guest in big
9801 return enable_unrestricted_guest || emulate_invalid_guest_state;
9802 case MSR_AMD64_VIRT_SPEC_CTRL:
9803 /* This is AMD only. */
9810 static bool vmx_mpx_supported(void)
9812 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
9813 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
9816 static bool vmx_xsaves_supported(void)
9818 return vmcs_config.cpu_based_2nd_exec_ctrl &
9819 SECONDARY_EXEC_XSAVES;
9822 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
9827 bool idtv_info_valid;
9829 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9832 if (vmx->loaded_vmcs->nmi_known_unmasked)
9835 * Can't use vmx->exit_intr_info since we're not sure what
9836 * the exit reason is.
9838 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9839 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
9840 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9842 * SDM 3: 27.7.1.2 (September 2008)
9843 * Re-set bit "block by NMI" before VM entry if vmexit caused by
9844 * a guest IRET fault.
9845 * SDM 3: 23.2.2 (September 2008)
9846 * Bit 12 is undefined in any of the following cases:
9847 * If the VM exit sets the valid bit in the IDT-vectoring
9848 * information field.
9849 * If the VM exit is due to a double fault.
9851 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
9852 vector != DF_VECTOR && !idtv_info_valid)
9853 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9854 GUEST_INTR_STATE_NMI);
9856 vmx->loaded_vmcs->nmi_known_unmasked =
9857 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
9858 & GUEST_INTR_STATE_NMI);
9859 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
9860 vmx->loaded_vmcs->vnmi_blocked_time +=
9861 ktime_to_ns(ktime_sub(ktime_get(),
9862 vmx->loaded_vmcs->entry_time));
9865 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
9866 u32 idt_vectoring_info,
9867 int instr_len_field,
9868 int error_code_field)
9872 bool idtv_info_valid;
9874 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9876 vcpu->arch.nmi_injected = false;
9877 kvm_clear_exception_queue(vcpu);
9878 kvm_clear_interrupt_queue(vcpu);
9880 if (!idtv_info_valid)
9883 kvm_make_request(KVM_REQ_EVENT, vcpu);
9885 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
9886 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
9889 case INTR_TYPE_NMI_INTR:
9890 vcpu->arch.nmi_injected = true;
9892 * SDM 3: 27.7.1.2 (September 2008)
9893 * Clear bit "block by NMI" before VM entry if a NMI
9896 vmx_set_nmi_mask(vcpu, false);
9898 case INTR_TYPE_SOFT_EXCEPTION:
9899 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9901 case INTR_TYPE_HARD_EXCEPTION:
9902 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
9903 u32 err = vmcs_read32(error_code_field);
9904 kvm_requeue_exception_e(vcpu, vector, err);
9906 kvm_requeue_exception(vcpu, vector);
9908 case INTR_TYPE_SOFT_INTR:
9909 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9911 case INTR_TYPE_EXT_INTR:
9912 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
9919 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
9921 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
9922 VM_EXIT_INSTRUCTION_LEN,
9923 IDT_VECTORING_ERROR_CODE);
9926 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
9928 __vmx_complete_interrupts(vcpu,
9929 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9930 VM_ENTRY_INSTRUCTION_LEN,
9931 VM_ENTRY_EXCEPTION_ERROR_CODE);
9933 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9936 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
9939 struct perf_guest_switch_msr *msrs;
9941 msrs = perf_guest_get_msrs(&nr_msrs);
9946 for (i = 0; i < nr_msrs; i++)
9947 if (msrs[i].host == msrs[i].guest)
9948 clear_atomic_switch_msr(vmx, msrs[i].msr);
9950 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
9954 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
9956 struct vcpu_vmx *vmx = to_vmx(vcpu);
9960 if (vmx->hv_deadline_tsc == -1)
9964 if (vmx->hv_deadline_tsc > tscl)
9965 /* sure to be 32 bit only because checked on set_hv_timer */
9966 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
9967 cpu_preemption_timer_multi);
9971 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9974 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
9976 struct vcpu_vmx *vmx = to_vmx(vcpu);
9977 unsigned long cr3, cr4, evmcs_rsp;
9979 /* Record the guest's net vcpu time for enforced NMI injections. */
9980 if (unlikely(!enable_vnmi &&
9981 vmx->loaded_vmcs->soft_vnmi_blocked))
9982 vmx->loaded_vmcs->entry_time = ktime_get();
9984 /* Don't enter VMX if guest state is invalid, let the exit handler
9985 start emulation until we arrive back to a valid state */
9986 if (vmx->emulation_required)
9989 if (vmx->ple_window_dirty) {
9990 vmx->ple_window_dirty = false;
9991 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9994 if (vmx->nested.sync_shadow_vmcs) {
9995 copy_vmcs12_to_shadow(vmx);
9996 vmx->nested.sync_shadow_vmcs = false;
9999 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
10000 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
10001 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
10002 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
10004 cr3 = __get_current_cr3_fast();
10005 if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) {
10006 vmcs_writel(HOST_CR3, cr3);
10007 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
10010 cr4 = cr4_read_shadow();
10011 if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) {
10012 vmcs_writel(HOST_CR4, cr4);
10013 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
10016 /* When single-stepping over STI and MOV SS, we must clear the
10017 * corresponding interruptibility bits in the guest state. Otherwise
10018 * vmentry fails as it then expects bit 14 (BS) in pending debug
10019 * exceptions being set, but that's not correct for the guest debugging
10021 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10022 vmx_set_interrupt_shadow(vcpu, 0);
10024 if (static_cpu_has(X86_FEATURE_PKU) &&
10025 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
10026 vcpu->arch.pkru != vmx->host_pkru)
10027 __write_pkru(vcpu->arch.pkru);
10029 atomic_switch_perf_msrs(vmx);
10031 vmx_arm_hv_timer(vcpu);
10034 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
10035 * it's non-zero. Since vmentry is serialising on affected CPUs, there
10036 * is no need to worry about the conditional branch over the wrmsr
10037 * being speculatively taken.
10039 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
10041 vmx->__launched = vmx->loaded_vmcs->launched;
10043 evmcs_rsp = static_branch_unlikely(&enable_evmcs) ?
10044 (unsigned long)¤t_evmcs->host_rsp : 0;
10047 /* Store host registers */
10048 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
10049 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
10050 "push %%" _ASM_CX " \n\t"
10051 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10053 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
10054 /* Avoid VMWRITE when Enlightened VMCS is in use */
10055 "test %%" _ASM_SI ", %%" _ASM_SI " \n\t"
10057 "mov %%" _ASM_SP ", (%%" _ASM_SI ") \n\t"
10060 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
10062 /* Reload cr2 if changed */
10063 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
10064 "mov %%cr2, %%" _ASM_DX " \n\t"
10065 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
10067 "mov %%" _ASM_AX", %%cr2 \n\t"
10069 /* Check if vmlaunch of vmresume is needed */
10070 "cmpl $0, %c[launched](%0) \n\t"
10071 /* Load guest registers. Don't clobber flags. */
10072 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
10073 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
10074 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
10075 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
10076 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
10077 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
10078 #ifdef CONFIG_X86_64
10079 "mov %c[r8](%0), %%r8 \n\t"
10080 "mov %c[r9](%0), %%r9 \n\t"
10081 "mov %c[r10](%0), %%r10 \n\t"
10082 "mov %c[r11](%0), %%r11 \n\t"
10083 "mov %c[r12](%0), %%r12 \n\t"
10084 "mov %c[r13](%0), %%r13 \n\t"
10085 "mov %c[r14](%0), %%r14 \n\t"
10086 "mov %c[r15](%0), %%r15 \n\t"
10088 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
10090 /* Enter guest mode */
10092 __ex(ASM_VMX_VMLAUNCH) "\n\t"
10094 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
10096 /* Save guest registers, load host registers, keep flags */
10097 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
10099 "setbe %c[fail](%0)\n\t"
10100 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
10101 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
10102 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
10103 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
10104 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
10105 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
10106 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
10107 #ifdef CONFIG_X86_64
10108 "mov %%r8, %c[r8](%0) \n\t"
10109 "mov %%r9, %c[r9](%0) \n\t"
10110 "mov %%r10, %c[r10](%0) \n\t"
10111 "mov %%r11, %c[r11](%0) \n\t"
10112 "mov %%r12, %c[r12](%0) \n\t"
10113 "mov %%r13, %c[r13](%0) \n\t"
10114 "mov %%r14, %c[r14](%0) \n\t"
10115 "mov %%r15, %c[r15](%0) \n\t"
10116 "xor %%r8d, %%r8d \n\t"
10117 "xor %%r9d, %%r9d \n\t"
10118 "xor %%r10d, %%r10d \n\t"
10119 "xor %%r11d, %%r11d \n\t"
10120 "xor %%r12d, %%r12d \n\t"
10121 "xor %%r13d, %%r13d \n\t"
10122 "xor %%r14d, %%r14d \n\t"
10123 "xor %%r15d, %%r15d \n\t"
10125 "mov %%cr2, %%" _ASM_AX " \n\t"
10126 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
10128 "xor %%eax, %%eax \n\t"
10129 "xor %%ebx, %%ebx \n\t"
10130 "xor %%esi, %%esi \n\t"
10131 "xor %%edi, %%edi \n\t"
10132 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
10133 ".pushsection .rodata \n\t"
10134 ".global vmx_return \n\t"
10135 "vmx_return: " _ASM_PTR " 2b \n\t"
10137 : : "c"(vmx), "d"((unsigned long)HOST_RSP), "S"(evmcs_rsp),
10138 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
10139 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
10140 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
10141 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
10142 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
10143 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
10144 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
10145 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
10146 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
10147 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
10148 #ifdef CONFIG_X86_64
10149 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
10150 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
10151 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
10152 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
10153 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
10154 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
10155 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
10156 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
10158 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
10159 [wordsize]"i"(sizeof(ulong))
10161 #ifdef CONFIG_X86_64
10162 , "rax", "rbx", "rdi"
10163 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
10165 , "eax", "ebx", "edi"
10170 * We do not use IBRS in the kernel. If this vCPU has used the
10171 * SPEC_CTRL MSR it may have left it on; save the value and
10172 * turn it off. This is much more efficient than blindly adding
10173 * it to the atomic save/restore list. Especially as the former
10174 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
10176 * For non-nested case:
10177 * If the L01 MSR bitmap does not intercept the MSR, then we need to
10181 * If the L02 MSR bitmap does not intercept the MSR, then we need to
10184 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
10185 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
10187 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
10189 /* Eliminate branch target predictions from guest mode */
10192 /* All fields are clean at this point */
10193 if (static_branch_unlikely(&enable_evmcs))
10194 current_evmcs->hv_clean_fields |=
10195 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
10197 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
10198 if (vmx->host_debugctlmsr)
10199 update_debugctlmsr(vmx->host_debugctlmsr);
10201 #ifndef CONFIG_X86_64
10203 * The sysexit path does not restore ds/es, so we must set them to
10204 * a reasonable value ourselves.
10206 * We can't defer this to vmx_load_host_state() since that function
10207 * may be executed in interrupt context, which saves and restore segments
10208 * around it, nullifying its effect.
10210 loadsegment(ds, __USER_DS);
10211 loadsegment(es, __USER_DS);
10214 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
10215 | (1 << VCPU_EXREG_RFLAGS)
10216 | (1 << VCPU_EXREG_PDPTR)
10217 | (1 << VCPU_EXREG_SEGMENTS)
10218 | (1 << VCPU_EXREG_CR3));
10219 vcpu->arch.regs_dirty = 0;
10222 * eager fpu is enabled if PKEY is supported and CR4 is switched
10223 * back on host, so it is safe to read guest PKRU from current
10226 if (static_cpu_has(X86_FEATURE_PKU) &&
10227 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
10228 vcpu->arch.pkru = __read_pkru();
10229 if (vcpu->arch.pkru != vmx->host_pkru)
10230 __write_pkru(vmx->host_pkru);
10233 vmx->nested.nested_run_pending = 0;
10234 vmx->idt_vectoring_info = 0;
10236 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
10237 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
10240 vmx->loaded_vmcs->launched = 1;
10241 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
10243 vmx_complete_atomic_exit(vmx);
10244 vmx_recover_nmi_blocking(vmx);
10245 vmx_complete_interrupts(vmx);
10247 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
10249 static struct kvm *vmx_vm_alloc(void)
10251 struct kvm_vmx *kvm_vmx = vzalloc(sizeof(struct kvm_vmx));
10252 return &kvm_vmx->kvm;
10255 static void vmx_vm_free(struct kvm *kvm)
10257 vfree(to_kvm_vmx(kvm));
10260 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
10262 struct vcpu_vmx *vmx = to_vmx(vcpu);
10265 if (vmx->loaded_vmcs == vmcs)
10269 vmx->loaded_vmcs = vmcs;
10270 vmx_vcpu_put(vcpu);
10271 vmx_vcpu_load(vcpu, cpu);
10276 * Ensure that the current vmcs of the logical processor is the
10277 * vmcs01 of the vcpu before calling free_nested().
10279 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
10281 struct vcpu_vmx *vmx = to_vmx(vcpu);
10284 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10289 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
10291 struct vcpu_vmx *vmx = to_vmx(vcpu);
10294 vmx_destroy_pml_buffer(vmx);
10295 free_vpid(vmx->vpid);
10296 leave_guest_mode(vcpu);
10297 vmx_free_vcpu_nested(vcpu);
10298 free_loaded_vmcs(vmx->loaded_vmcs);
10299 kfree(vmx->guest_msrs);
10300 kvm_vcpu_uninit(vcpu);
10301 kmem_cache_free(kvm_vcpu_cache, vmx);
10304 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
10307 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
10308 unsigned long *msr_bitmap;
10312 return ERR_PTR(-ENOMEM);
10314 vmx->vpid = allocate_vpid();
10316 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
10323 * If PML is turned on, failure on enabling PML just results in failure
10324 * of creating the vcpu, therefore we can simplify PML logic (by
10325 * avoiding dealing with cases, such as enabling PML partially on vcpus
10326 * for the guest, etc.
10329 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
10334 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
10335 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
10338 if (!vmx->guest_msrs)
10341 err = alloc_loaded_vmcs(&vmx->vmcs01);
10345 msr_bitmap = vmx->vmcs01.msr_bitmap;
10346 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
10347 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
10348 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
10349 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
10350 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
10351 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
10352 vmx->msr_bitmap_mode = 0;
10354 vmx->loaded_vmcs = &vmx->vmcs01;
10356 vmx_vcpu_load(&vmx->vcpu, cpu);
10357 vmx->vcpu.cpu = cpu;
10358 vmx_vcpu_setup(vmx);
10359 vmx_vcpu_put(&vmx->vcpu);
10361 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
10362 err = alloc_apic_access_page(kvm);
10367 if (enable_ept && !enable_unrestricted_guest) {
10368 err = init_rmode_identity_map(kvm);
10374 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
10375 kvm_vcpu_apicv_active(&vmx->vcpu));
10376 vmx->nested.vpid02 = allocate_vpid();
10379 vmx->nested.posted_intr_nv = -1;
10380 vmx->nested.current_vmptr = -1ull;
10382 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
10385 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
10386 * or POSTED_INTR_WAKEUP_VECTOR.
10388 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
10389 vmx->pi_desc.sn = 1;
10394 free_vpid(vmx->nested.vpid02);
10395 free_loaded_vmcs(vmx->loaded_vmcs);
10397 kfree(vmx->guest_msrs);
10399 vmx_destroy_pml_buffer(vmx);
10401 kvm_vcpu_uninit(&vmx->vcpu);
10403 free_vpid(vmx->vpid);
10404 kmem_cache_free(kvm_vcpu_cache, vmx);
10405 return ERR_PTR(err);
10408 static int vmx_vm_init(struct kvm *kvm)
10411 kvm->arch.pause_in_guest = true;
10415 static void __init vmx_check_processor_compat(void *rtn)
10417 struct vmcs_config vmcs_conf;
10420 if (setup_vmcs_config(&vmcs_conf) < 0)
10421 *(int *)rtn = -EIO;
10422 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, enable_apicv);
10423 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
10424 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
10425 smp_processor_id());
10426 *(int *)rtn = -EIO;
10430 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
10435 /* For VT-d and EPT combination
10436 * 1. MMIO: always map as UC
10437 * 2. EPT with VT-d:
10438 * a. VT-d without snooping control feature: can't guarantee the
10439 * result, try to trust guest.
10440 * b. VT-d with snooping control feature: snooping control feature of
10441 * VT-d engine can guarantee the cache correctness. Just set it
10442 * to WB to keep consistent with host. So the same as item 3.
10443 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
10444 * consistent with host MTRR
10447 cache = MTRR_TYPE_UNCACHABLE;
10451 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
10452 ipat = VMX_EPT_IPAT_BIT;
10453 cache = MTRR_TYPE_WRBACK;
10457 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
10458 ipat = VMX_EPT_IPAT_BIT;
10459 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
10460 cache = MTRR_TYPE_WRBACK;
10462 cache = MTRR_TYPE_UNCACHABLE;
10466 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
10469 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
10472 static int vmx_get_lpage_level(void)
10474 if (enable_ept && !cpu_has_vmx_ept_1g_page())
10475 return PT_DIRECTORY_LEVEL;
10477 /* For shadow and EPT supported 1GB page */
10478 return PT_PDPE_LEVEL;
10481 static void vmcs_set_secondary_exec_control(u32 new_ctl)
10484 * These bits in the secondary execution controls field
10485 * are dynamic, the others are mostly based on the hypervisor
10486 * architecture and the guest's CPUID. Do not touch the
10490 SECONDARY_EXEC_SHADOW_VMCS |
10491 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
10492 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10493 SECONDARY_EXEC_DESC;
10495 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
10497 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
10498 (new_ctl & ~mask) | (cur_ctl & mask));
10502 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
10503 * (indicating "allowed-1") if they are supported in the guest's CPUID.
10505 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
10507 struct vcpu_vmx *vmx = to_vmx(vcpu);
10508 struct kvm_cpuid_entry2 *entry;
10510 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
10511 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
10513 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
10514 if (entry && (entry->_reg & (_cpuid_mask))) \
10515 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
10518 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
10519 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
10520 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
10521 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
10522 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
10523 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
10524 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
10525 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
10526 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
10527 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
10528 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
10529 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
10530 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
10531 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
10532 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
10534 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
10535 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
10536 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
10537 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
10538 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
10539 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
10541 #undef cr4_fixed1_update
10544 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
10546 struct vcpu_vmx *vmx = to_vmx(vcpu);
10548 if (cpu_has_secondary_exec_ctrls()) {
10549 vmx_compute_secondary_exec_control(vmx);
10550 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
10553 if (nested_vmx_allowed(vcpu))
10554 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
10555 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
10557 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
10558 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
10560 if (nested_vmx_allowed(vcpu))
10561 nested_vmx_cr_fixed1_bits_update(vcpu);
10564 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
10566 if (func == 1 && nested)
10567 entry->ecx |= bit(X86_FEATURE_VMX);
10570 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
10571 struct x86_exception *fault)
10573 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10574 struct vcpu_vmx *vmx = to_vmx(vcpu);
10576 unsigned long exit_qualification = vcpu->arch.exit_qualification;
10578 if (vmx->nested.pml_full) {
10579 exit_reason = EXIT_REASON_PML_FULL;
10580 vmx->nested.pml_full = false;
10581 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
10582 } else if (fault->error_code & PFERR_RSVD_MASK)
10583 exit_reason = EXIT_REASON_EPT_MISCONFIG;
10585 exit_reason = EXIT_REASON_EPT_VIOLATION;
10587 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
10588 vmcs12->guest_physical_address = fault->address;
10591 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
10593 return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
10596 /* Callbacks for nested_ept_init_mmu_context: */
10598 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
10600 /* return the page table to be shadowed - in our case, EPT12 */
10601 return get_vmcs12(vcpu)->ept_pointer;
10604 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
10606 WARN_ON(mmu_is_nested(vcpu));
10607 if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
10610 kvm_mmu_unload(vcpu);
10611 kvm_init_shadow_ept_mmu(vcpu,
10612 to_vmx(vcpu)->nested.msrs.ept_caps &
10613 VMX_EPT_EXECUTE_ONLY_BIT,
10614 nested_ept_ad_enabled(vcpu));
10615 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
10616 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
10617 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
10619 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
10623 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
10625 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
10628 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
10631 bool inequality, bit;
10633 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
10635 (error_code & vmcs12->page_fault_error_code_mask) !=
10636 vmcs12->page_fault_error_code_match;
10637 return inequality ^ bit;
10640 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
10641 struct x86_exception *fault)
10643 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10645 WARN_ON(!is_guest_mode(vcpu));
10647 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
10648 !to_vmx(vcpu)->nested.nested_run_pending) {
10649 vmcs12->vm_exit_intr_error_code = fault->error_code;
10650 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10651 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
10652 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
10655 kvm_inject_page_fault(vcpu, fault);
10659 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10660 struct vmcs12 *vmcs12);
10662 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
10663 struct vmcs12 *vmcs12)
10665 struct vcpu_vmx *vmx = to_vmx(vcpu);
10669 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10671 * Translate L1 physical address to host physical
10672 * address for vmcs02. Keep the page pinned, so this
10673 * physical address remains valid. We keep a reference
10674 * to it so we can release it later.
10676 if (vmx->nested.apic_access_page) { /* shouldn't happen */
10677 kvm_release_page_dirty(vmx->nested.apic_access_page);
10678 vmx->nested.apic_access_page = NULL;
10680 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
10682 * If translation failed, no matter: This feature asks
10683 * to exit when accessing the given address, and if it
10684 * can never be accessed, this feature won't do
10687 if (!is_error_page(page)) {
10688 vmx->nested.apic_access_page = page;
10689 hpa = page_to_phys(vmx->nested.apic_access_page);
10690 vmcs_write64(APIC_ACCESS_ADDR, hpa);
10692 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
10693 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10697 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
10698 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
10699 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
10700 vmx->nested.virtual_apic_page = NULL;
10702 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
10705 * If translation failed, VM entry will fail because
10706 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
10707 * Failing the vm entry is _not_ what the processor
10708 * does but it's basically the only possibility we
10709 * have. We could still enter the guest if CR8 load
10710 * exits are enabled, CR8 store exits are enabled, and
10711 * virtualize APIC access is disabled; in this case
10712 * the processor would never use the TPR shadow and we
10713 * could simply clear the bit from the execution
10714 * control. But such a configuration is useless, so
10715 * let's keep the code simple.
10717 if (!is_error_page(page)) {
10718 vmx->nested.virtual_apic_page = page;
10719 hpa = page_to_phys(vmx->nested.virtual_apic_page);
10720 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
10724 if (nested_cpu_has_posted_intr(vmcs12)) {
10725 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
10726 kunmap(vmx->nested.pi_desc_page);
10727 kvm_release_page_dirty(vmx->nested.pi_desc_page);
10728 vmx->nested.pi_desc_page = NULL;
10730 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
10731 if (is_error_page(page))
10733 vmx->nested.pi_desc_page = page;
10734 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
10735 vmx->nested.pi_desc =
10736 (struct pi_desc *)((void *)vmx->nested.pi_desc +
10737 (unsigned long)(vmcs12->posted_intr_desc_addr &
10739 vmcs_write64(POSTED_INTR_DESC_ADDR,
10740 page_to_phys(vmx->nested.pi_desc_page) +
10741 (unsigned long)(vmcs12->posted_intr_desc_addr &
10744 if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
10745 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
10746 CPU_BASED_USE_MSR_BITMAPS);
10748 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
10749 CPU_BASED_USE_MSR_BITMAPS);
10752 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
10754 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
10755 struct vcpu_vmx *vmx = to_vmx(vcpu);
10757 if (vcpu->arch.virtual_tsc_khz == 0)
10760 /* Make sure short timeouts reliably trigger an immediate vmexit.
10761 * hrtimer_start does not guarantee this. */
10762 if (preemption_timeout <= 1) {
10763 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
10767 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10768 preemption_timeout *= 1000000;
10769 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
10770 hrtimer_start(&vmx->nested.preemption_timer,
10771 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
10774 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
10775 struct vmcs12 *vmcs12)
10777 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
10780 if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
10781 !page_address_valid(vcpu, vmcs12->io_bitmap_b))
10787 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
10788 struct vmcs12 *vmcs12)
10790 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10793 if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
10799 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
10800 struct vmcs12 *vmcs12)
10802 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10805 if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
10812 * Merge L0's and L1's MSR bitmap, return false to indicate that
10813 * we do not use the hardware.
10815 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
10816 struct vmcs12 *vmcs12)
10820 unsigned long *msr_bitmap_l1;
10821 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
10823 * pred_cmd & spec_ctrl are trying to verify two things:
10825 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
10826 * ensures that we do not accidentally generate an L02 MSR bitmap
10827 * from the L12 MSR bitmap that is too permissive.
10828 * 2. That L1 or L2s have actually used the MSR. This avoids
10829 * unnecessarily merging of the bitmap if the MSR is unused. This
10830 * works properly because we only update the L01 MSR bitmap lazily.
10831 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only
10832 * updated to reflect this when L1 (or its L2s) actually write to
10835 bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
10836 bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
10838 /* Nothing to do if the MSR bitmap is not in use. */
10839 if (!cpu_has_vmx_msr_bitmap() ||
10840 !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10843 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10844 !pred_cmd && !spec_ctrl)
10847 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
10848 if (is_error_page(page))
10851 msr_bitmap_l1 = (unsigned long *)kmap(page);
10852 if (nested_cpu_has_apic_reg_virt(vmcs12)) {
10854 * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it
10855 * just lets the processor take the value from the virtual-APIC page;
10856 * take those 256 bits directly from the L1 bitmap.
10858 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10859 unsigned word = msr / BITS_PER_LONG;
10860 msr_bitmap_l0[word] = msr_bitmap_l1[word];
10861 msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10864 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
10865 unsigned word = msr / BITS_PER_LONG;
10866 msr_bitmap_l0[word] = ~0;
10867 msr_bitmap_l0[word + (0x800 / sizeof(long))] = ~0;
10871 nested_vmx_disable_intercept_for_msr(
10872 msr_bitmap_l1, msr_bitmap_l0,
10873 X2APIC_MSR(APIC_TASKPRI),
10876 if (nested_cpu_has_vid(vmcs12)) {
10877 nested_vmx_disable_intercept_for_msr(
10878 msr_bitmap_l1, msr_bitmap_l0,
10879 X2APIC_MSR(APIC_EOI),
10881 nested_vmx_disable_intercept_for_msr(
10882 msr_bitmap_l1, msr_bitmap_l0,
10883 X2APIC_MSR(APIC_SELF_IPI),
10888 nested_vmx_disable_intercept_for_msr(
10889 msr_bitmap_l1, msr_bitmap_l0,
10890 MSR_IA32_SPEC_CTRL,
10891 MSR_TYPE_R | MSR_TYPE_W);
10894 nested_vmx_disable_intercept_for_msr(
10895 msr_bitmap_l1, msr_bitmap_l0,
10900 kvm_release_page_clean(page);
10905 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu,
10906 struct vmcs12 *vmcs12)
10908 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
10909 !page_address_valid(vcpu, vmcs12->apic_access_addr))
10915 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
10916 struct vmcs12 *vmcs12)
10918 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10919 !nested_cpu_has_apic_reg_virt(vmcs12) &&
10920 !nested_cpu_has_vid(vmcs12) &&
10921 !nested_cpu_has_posted_intr(vmcs12))
10925 * If virtualize x2apic mode is enabled,
10926 * virtualize apic access must be disabled.
10928 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10929 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
10933 * If virtual interrupt delivery is enabled,
10934 * we must exit on external interrupts.
10936 if (nested_cpu_has_vid(vmcs12) &&
10937 !nested_exit_on_intr(vcpu))
10941 * bits 15:8 should be zero in posted_intr_nv,
10942 * the descriptor address has been already checked
10943 * in nested_get_vmcs12_pages.
10945 if (nested_cpu_has_posted_intr(vmcs12) &&
10946 (!nested_cpu_has_vid(vmcs12) ||
10947 !nested_exit_intr_ack_set(vcpu) ||
10948 vmcs12->posted_intr_nv & 0xff00))
10951 /* tpr shadow is needed by all apicv features. */
10952 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10958 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
10959 unsigned long count_field,
10960 unsigned long addr_field)
10965 if (vmcs12_read_any(vcpu, count_field, &count) ||
10966 vmcs12_read_any(vcpu, addr_field, &addr)) {
10972 maxphyaddr = cpuid_maxphyaddr(vcpu);
10973 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
10974 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
10975 pr_debug_ratelimited(
10976 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10977 addr_field, maxphyaddr, count, addr);
10983 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
10984 struct vmcs12 *vmcs12)
10986 if (vmcs12->vm_exit_msr_load_count == 0 &&
10987 vmcs12->vm_exit_msr_store_count == 0 &&
10988 vmcs12->vm_entry_msr_load_count == 0)
10989 return 0; /* Fast path */
10990 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
10991 VM_EXIT_MSR_LOAD_ADDR) ||
10992 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
10993 VM_EXIT_MSR_STORE_ADDR) ||
10994 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
10995 VM_ENTRY_MSR_LOAD_ADDR))
11000 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
11001 struct vmcs12 *vmcs12)
11003 u64 address = vmcs12->pml_address;
11004 int maxphyaddr = cpuid_maxphyaddr(vcpu);
11006 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
11007 if (!nested_cpu_has_ept(vmcs12) ||
11008 !IS_ALIGNED(address, 4096) ||
11009 address >> maxphyaddr)
11016 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
11017 struct vmx_msr_entry *e)
11019 /* x2APIC MSR accesses are not allowed */
11020 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
11022 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
11023 e->index == MSR_IA32_UCODE_REV)
11025 if (e->reserved != 0)
11030 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
11031 struct vmx_msr_entry *e)
11033 if (e->index == MSR_FS_BASE ||
11034 e->index == MSR_GS_BASE ||
11035 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
11036 nested_vmx_msr_check_common(vcpu, e))
11041 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
11042 struct vmx_msr_entry *e)
11044 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
11045 nested_vmx_msr_check_common(vcpu, e))
11051 * Load guest's/host's msr at nested entry/exit.
11052 * return 0 for success, entry index for failure.
11054 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11057 struct vmx_msr_entry e;
11058 struct msr_data msr;
11060 msr.host_initiated = false;
11061 for (i = 0; i < count; i++) {
11062 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
11064 pr_debug_ratelimited(
11065 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11066 __func__, i, gpa + i * sizeof(e));
11069 if (nested_vmx_load_msr_check(vcpu, &e)) {
11070 pr_debug_ratelimited(
11071 "%s check failed (%u, 0x%x, 0x%x)\n",
11072 __func__, i, e.index, e.reserved);
11075 msr.index = e.index;
11076 msr.data = e.value;
11077 if (kvm_set_msr(vcpu, &msr)) {
11078 pr_debug_ratelimited(
11079 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11080 __func__, i, e.index, e.value);
11089 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
11092 struct vmx_msr_entry e;
11094 for (i = 0; i < count; i++) {
11095 struct msr_data msr_info;
11096 if (kvm_vcpu_read_guest(vcpu,
11097 gpa + i * sizeof(e),
11098 &e, 2 * sizeof(u32))) {
11099 pr_debug_ratelimited(
11100 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11101 __func__, i, gpa + i * sizeof(e));
11104 if (nested_vmx_store_msr_check(vcpu, &e)) {
11105 pr_debug_ratelimited(
11106 "%s check failed (%u, 0x%x, 0x%x)\n",
11107 __func__, i, e.index, e.reserved);
11110 msr_info.host_initiated = false;
11111 msr_info.index = e.index;
11112 if (kvm_get_msr(vcpu, &msr_info)) {
11113 pr_debug_ratelimited(
11114 "%s cannot read MSR (%u, 0x%x)\n",
11115 __func__, i, e.index);
11118 if (kvm_vcpu_write_guest(vcpu,
11119 gpa + i * sizeof(e) +
11120 offsetof(struct vmx_msr_entry, value),
11121 &msr_info.data, sizeof(msr_info.data))) {
11122 pr_debug_ratelimited(
11123 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11124 __func__, i, e.index, msr_info.data);
11131 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
11133 unsigned long invalid_mask;
11135 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
11136 return (val & invalid_mask) == 0;
11140 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
11141 * emulating VM entry into a guest with EPT enabled.
11142 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
11143 * is assigned to entry_failure_code on failure.
11145 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
11146 u32 *entry_failure_code)
11148 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
11149 if (!nested_cr3_valid(vcpu, cr3)) {
11150 *entry_failure_code = ENTRY_FAIL_DEFAULT;
11155 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
11156 * must not be dereferenced.
11158 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
11160 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
11161 *entry_failure_code = ENTRY_FAIL_PDPTE;
11166 vcpu->arch.cr3 = cr3;
11167 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
11170 kvm_mmu_reset_context(vcpu);
11174 static void prepare_vmcs02_full(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11176 struct vcpu_vmx *vmx = to_vmx(vcpu);
11178 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
11179 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
11180 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
11181 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
11182 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
11183 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
11184 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
11185 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
11186 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
11187 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
11188 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
11189 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
11190 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
11191 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
11192 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
11193 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
11194 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
11195 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
11196 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
11197 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
11198 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
11199 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
11200 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
11201 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
11202 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
11203 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
11204 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
11205 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
11206 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
11207 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
11208 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
11210 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
11211 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
11212 vmcs12->guest_pending_dbg_exceptions);
11213 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
11214 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
11216 if (nested_cpu_has_xsaves(vmcs12))
11217 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
11218 vmcs_write64(VMCS_LINK_POINTER, -1ull);
11220 if (cpu_has_vmx_posted_intr())
11221 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
11224 * Whether page-faults are trapped is determined by a combination of
11225 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
11226 * If enable_ept, L0 doesn't care about page faults and we should
11227 * set all of these to L1's desires. However, if !enable_ept, L0 does
11228 * care about (at least some) page faults, and because it is not easy
11229 * (if at all possible?) to merge L0 and L1's desires, we simply ask
11230 * to exit on each and every L2 page fault. This is done by setting
11231 * MASK=MATCH=0 and (see below) EB.PF=1.
11232 * Note that below we don't need special code to set EB.PF beyond the
11233 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
11234 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
11235 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
11237 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
11238 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
11239 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
11240 enable_ept ? vmcs12->page_fault_error_code_match : 0);
11242 /* All VMFUNCs are currently emulated through L0 vmexits. */
11243 if (cpu_has_vmx_vmfunc())
11244 vmcs_write64(VM_FUNCTION_CONTROL, 0);
11246 if (cpu_has_vmx_apicv()) {
11247 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0);
11248 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1);
11249 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2);
11250 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3);
11254 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
11255 * Some constant fields are set here by vmx_set_constant_host_state().
11256 * Other fields are different per CPU, and will be set later when
11257 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
11259 vmx_set_constant_host_state(vmx);
11262 * Set the MSR load/store lists to match L0's settings.
11264 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
11265 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11266 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
11267 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11268 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
11270 set_cr4_guest_host_mask(vmx);
11272 if (vmx_mpx_supported())
11273 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
11276 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
11277 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
11279 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
11283 * L1 may access the L2's PDPTR, so save them to construct vmcs12
11286 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
11287 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
11288 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
11289 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
11292 if (cpu_has_vmx_msr_bitmap())
11293 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
11297 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
11298 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
11299 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
11300 * guest in a way that will both be appropriate to L1's requests, and our
11301 * needs. In addition to modifying the active vmcs (which is vmcs02), this
11302 * function also has additional necessary side-effects, like setting various
11303 * vcpu->arch fields.
11304 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
11305 * is assigned to entry_failure_code on failure.
11307 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11308 u32 *entry_failure_code)
11310 struct vcpu_vmx *vmx = to_vmx(vcpu);
11311 u32 exec_control, vmcs12_exec_ctrl;
11313 if (vmx->nested.dirty_vmcs12) {
11314 prepare_vmcs02_full(vcpu, vmcs12);
11315 vmx->nested.dirty_vmcs12 = false;
11319 * First, the fields that are shadowed. This must be kept in sync
11320 * with vmx_shadow_fields.h.
11323 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
11324 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
11325 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
11326 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
11327 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
11330 * Not in vmcs02: GUEST_PML_INDEX, HOST_FS_SELECTOR, HOST_GS_SELECTOR,
11331 * HOST_FS_BASE, HOST_GS_BASE.
11334 if (vmx->nested.nested_run_pending &&
11335 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
11336 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
11337 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
11339 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
11340 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
11342 if (vmx->nested.nested_run_pending) {
11343 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
11344 vmcs12->vm_entry_intr_info_field);
11345 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
11346 vmcs12->vm_entry_exception_error_code);
11347 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
11348 vmcs12->vm_entry_instruction_len);
11349 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
11350 vmcs12->guest_interruptibility_info);
11351 vmx->loaded_vmcs->nmi_known_unmasked =
11352 !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
11354 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
11356 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
11358 exec_control = vmcs12->pin_based_vm_exec_control;
11360 /* Preemption timer setting is only taken from vmcs01. */
11361 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
11362 exec_control |= vmcs_config.pin_based_exec_ctrl;
11363 if (vmx->hv_deadline_tsc == -1)
11364 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
11366 /* Posted interrupts setting is only taken from vmcs12. */
11367 if (nested_cpu_has_posted_intr(vmcs12)) {
11368 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
11369 vmx->nested.pi_pending = false;
11371 exec_control &= ~PIN_BASED_POSTED_INTR;
11374 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
11376 vmx->nested.preemption_timer_expired = false;
11377 if (nested_cpu_has_preemption_timer(vmcs12))
11378 vmx_start_preemption_timer(vcpu);
11380 if (cpu_has_secondary_exec_ctrls()) {
11381 exec_control = vmx->secondary_exec_control;
11383 /* Take the following fields only from vmcs12 */
11384 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
11385 SECONDARY_EXEC_ENABLE_INVPCID |
11386 SECONDARY_EXEC_RDTSCP |
11387 SECONDARY_EXEC_XSAVES |
11388 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
11389 SECONDARY_EXEC_APIC_REGISTER_VIRT |
11390 SECONDARY_EXEC_ENABLE_VMFUNC);
11391 if (nested_cpu_has(vmcs12,
11392 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
11393 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
11394 ~SECONDARY_EXEC_ENABLE_PML;
11395 exec_control |= vmcs12_exec_ctrl;
11398 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
11399 vmcs_write16(GUEST_INTR_STATUS,
11400 vmcs12->guest_intr_status);
11403 * Write an illegal value to APIC_ACCESS_ADDR. Later,
11404 * nested_get_vmcs12_pages will either fix it up or
11405 * remove the VM execution control.
11407 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
11408 vmcs_write64(APIC_ACCESS_ADDR, -1ull);
11410 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
11414 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
11415 * entry, but only if the current (host) sp changed from the value
11416 * we wrote last (vmx->host_rsp). This cache is no longer relevant
11417 * if we switch vmcs, and rather than hold a separate cache per vmcs,
11418 * here we just force the write to happen on entry.
11422 exec_control = vmx_exec_control(vmx); /* L0's desires */
11423 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
11424 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
11425 exec_control &= ~CPU_BASED_TPR_SHADOW;
11426 exec_control |= vmcs12->cpu_based_vm_exec_control;
11429 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
11430 * nested_get_vmcs12_pages can't fix it up, the illegal value
11431 * will result in a VM entry failure.
11433 if (exec_control & CPU_BASED_TPR_SHADOW) {
11434 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
11435 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
11437 #ifdef CONFIG_X86_64
11438 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
11439 CPU_BASED_CR8_STORE_EXITING;
11444 * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
11445 * for I/O port accesses.
11447 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
11448 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
11450 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
11452 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
11453 * bitwise-or of what L1 wants to trap for L2, and what we want to
11454 * trap. Note that CR0.TS also needs updating - we do this later.
11456 update_exception_bitmap(vcpu);
11457 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
11458 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
11460 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
11461 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
11462 * bits are further modified by vmx_set_efer() below.
11464 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
11466 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
11467 * emulated by vmx_set_efer(), below.
11469 vm_entry_controls_init(vmx,
11470 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
11471 ~VM_ENTRY_IA32E_MODE) |
11472 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
11474 if (vmx->nested.nested_run_pending &&
11475 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
11476 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
11477 vcpu->arch.pat = vmcs12->guest_ia32_pat;
11478 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
11479 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
11482 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11484 if (kvm_has_tsc_control)
11485 decache_tsc_multiplier(vmx);
11489 * There is no direct mapping between vpid02 and vpid12, the
11490 * vpid02 is per-vCPU for L0 and reused while the value of
11491 * vpid12 is changed w/ one invvpid during nested vmentry.
11492 * The vpid12 is allocated by L1 for L2, so it will not
11493 * influence global bitmap(for vpid01 and vpid02 allocation)
11494 * even if spawn a lot of nested vCPUs.
11496 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
11497 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
11498 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
11499 __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true);
11502 vmx_flush_tlb(vcpu, true);
11508 * Conceptually we want to copy the PML address and index from
11509 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
11510 * since we always flush the log on each vmexit, this happens
11511 * to be equivalent to simply resetting the fields in vmcs02.
11513 ASSERT(vmx->pml_pg);
11514 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
11515 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
11518 if (nested_cpu_has_ept(vmcs12)) {
11519 if (nested_ept_init_mmu_context(vcpu)) {
11520 *entry_failure_code = ENTRY_FAIL_DEFAULT;
11523 } else if (nested_cpu_has2(vmcs12,
11524 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11525 vmx_flush_tlb(vcpu, true);
11529 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
11530 * bits which we consider mandatory enabled.
11531 * The CR0_READ_SHADOW is what L2 should have expected to read given
11532 * the specifications by L1; It's not enough to take
11533 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
11534 * have more bits than L1 expected.
11536 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
11537 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
11539 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
11540 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
11542 if (vmx->nested.nested_run_pending &&
11543 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
11544 vcpu->arch.efer = vmcs12->guest_ia32_efer;
11545 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
11546 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11548 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11549 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
11550 vmx_set_efer(vcpu, vcpu->arch.efer);
11553 * Guest state is invalid and unrestricted guest is disabled,
11554 * which means L1 attempted VMEntry to L2 with invalid state.
11555 * Fail the VMEntry.
11557 if (vmx->emulation_required) {
11558 *entry_failure_code = ENTRY_FAIL_DEFAULT;
11562 /* Shadow page tables on either EPT or shadow page tables. */
11563 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
11564 entry_failure_code))
11568 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
11570 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
11571 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
11575 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12)
11577 if (!nested_cpu_has_nmi_exiting(vmcs12) &&
11578 nested_cpu_has_virtual_nmis(vmcs12))
11581 if (!nested_cpu_has_virtual_nmis(vmcs12) &&
11582 nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING))
11588 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11590 struct vcpu_vmx *vmx = to_vmx(vcpu);
11592 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
11593 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
11594 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11596 if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
11597 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11599 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
11600 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11602 if (nested_vmx_check_apic_access_controls(vcpu, vmcs12))
11603 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11605 if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
11606 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11608 if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
11609 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11611 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
11612 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11614 if (nested_vmx_check_pml_controls(vcpu, vmcs12))
11615 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11617 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
11618 vmx->nested.msrs.procbased_ctls_low,
11619 vmx->nested.msrs.procbased_ctls_high) ||
11620 (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
11621 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
11622 vmx->nested.msrs.secondary_ctls_low,
11623 vmx->nested.msrs.secondary_ctls_high)) ||
11624 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
11625 vmx->nested.msrs.pinbased_ctls_low,
11626 vmx->nested.msrs.pinbased_ctls_high) ||
11627 !vmx_control_verify(vmcs12->vm_exit_controls,
11628 vmx->nested.msrs.exit_ctls_low,
11629 vmx->nested.msrs.exit_ctls_high) ||
11630 !vmx_control_verify(vmcs12->vm_entry_controls,
11631 vmx->nested.msrs.entry_ctls_low,
11632 vmx->nested.msrs.entry_ctls_high))
11633 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11635 if (nested_vmx_check_nmi_controls(vmcs12))
11636 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11638 if (nested_cpu_has_vmfunc(vmcs12)) {
11639 if (vmcs12->vm_function_control &
11640 ~vmx->nested.msrs.vmfunc_controls)
11641 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11643 if (nested_cpu_has_eptp_switching(vmcs12)) {
11644 if (!nested_cpu_has_ept(vmcs12) ||
11645 !page_address_valid(vcpu, vmcs12->eptp_list_address))
11646 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11650 if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
11651 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11653 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
11654 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
11655 !nested_cr3_valid(vcpu, vmcs12->host_cr3))
11656 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
11659 * From the Intel SDM, volume 3:
11660 * Fields relevant to VM-entry event injection must be set properly.
11661 * These fields are the VM-entry interruption-information field, the
11662 * VM-entry exception error code, and the VM-entry instruction length.
11664 if (vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) {
11665 u32 intr_info = vmcs12->vm_entry_intr_info_field;
11666 u8 vector = intr_info & INTR_INFO_VECTOR_MASK;
11667 u32 intr_type = intr_info & INTR_INFO_INTR_TYPE_MASK;
11668 bool has_error_code = intr_info & INTR_INFO_DELIVER_CODE_MASK;
11669 bool should_have_error_code;
11670 bool urg = nested_cpu_has2(vmcs12,
11671 SECONDARY_EXEC_UNRESTRICTED_GUEST);
11672 bool prot_mode = !urg || vmcs12->guest_cr0 & X86_CR0_PE;
11674 /* VM-entry interruption-info field: interruption type */
11675 if (intr_type == INTR_TYPE_RESERVED ||
11676 (intr_type == INTR_TYPE_OTHER_EVENT &&
11677 !nested_cpu_supports_monitor_trap_flag(vcpu)))
11678 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11680 /* VM-entry interruption-info field: vector */
11681 if ((intr_type == INTR_TYPE_NMI_INTR && vector != NMI_VECTOR) ||
11682 (intr_type == INTR_TYPE_HARD_EXCEPTION && vector > 31) ||
11683 (intr_type == INTR_TYPE_OTHER_EVENT && vector != 0))
11684 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11686 /* VM-entry interruption-info field: deliver error code */
11687 should_have_error_code =
11688 intr_type == INTR_TYPE_HARD_EXCEPTION && prot_mode &&
11689 x86_exception_has_error_code(vector);
11690 if (has_error_code != should_have_error_code)
11691 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11693 /* VM-entry exception error code */
11694 if (has_error_code &&
11695 vmcs12->vm_entry_exception_error_code & GENMASK(31, 15))
11696 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11698 /* VM-entry interruption-info field: reserved bits */
11699 if (intr_info & INTR_INFO_RESVD_BITS_MASK)
11700 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11702 /* VM-entry instruction length */
11703 switch (intr_type) {
11704 case INTR_TYPE_SOFT_EXCEPTION:
11705 case INTR_TYPE_SOFT_INTR:
11706 case INTR_TYPE_PRIV_SW_EXCEPTION:
11707 if ((vmcs12->vm_entry_instruction_len > 15) ||
11708 (vmcs12->vm_entry_instruction_len == 0 &&
11709 !nested_cpu_has_zero_length_injection(vcpu)))
11710 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
11717 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11722 *exit_qual = ENTRY_FAIL_DEFAULT;
11724 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
11725 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
11728 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
11729 vmcs12->vmcs_link_pointer != -1ull) {
11730 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
11735 * If the load IA32_EFER VM-entry control is 1, the following checks
11736 * are performed on the field for the IA32_EFER MSR:
11737 * - Bits reserved in the IA32_EFER MSR must be 0.
11738 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
11739 * the IA-32e mode guest VM-exit control. It must also be identical
11740 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
11743 if (to_vmx(vcpu)->nested.nested_run_pending &&
11744 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
11745 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
11746 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
11747 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
11748 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
11749 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
11754 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
11755 * IA32_EFER MSR must be 0 in the field for that register. In addition,
11756 * the values of the LMA and LME bits in the field must each be that of
11757 * the host address-space size VM-exit control.
11759 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
11760 ia32e = (vmcs12->vm_exit_controls &
11761 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
11762 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
11763 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
11764 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
11768 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) &&
11769 (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) ||
11770 (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))
11776 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu)
11778 struct vcpu_vmx *vmx = to_vmx(vcpu);
11779 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11783 enter_guest_mode(vcpu);
11785 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
11786 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11788 vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
11789 vmx_segment_cache_clear(vmx);
11791 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
11792 vcpu->arch.tsc_offset += vmcs12->tsc_offset;
11794 r = EXIT_REASON_INVALID_STATE;
11795 if (prepare_vmcs02(vcpu, vmcs12, &exit_qual))
11798 nested_get_vmcs12_pages(vcpu, vmcs12);
11800 r = EXIT_REASON_MSR_LOAD_FAIL;
11801 exit_qual = nested_vmx_load_msr(vcpu,
11802 vmcs12->vm_entry_msr_load_addr,
11803 vmcs12->vm_entry_msr_load_count);
11808 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
11809 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
11810 * returned as far as L1 is concerned. It will only return (and set
11811 * the success flag) when L2 exits (see nested_vmx_vmexit()).
11816 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
11817 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
11818 leave_guest_mode(vcpu);
11819 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11820 nested_vmx_entry_failure(vcpu, vmcs12, r, exit_qual);
11825 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
11826 * for running an L2 nested guest.
11828 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
11830 struct vmcs12 *vmcs12;
11831 struct vcpu_vmx *vmx = to_vmx(vcpu);
11832 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
11836 if (!nested_vmx_check_permission(vcpu))
11839 if (!nested_vmx_check_vmcs12(vcpu))
11842 vmcs12 = get_vmcs12(vcpu);
11844 if (enable_shadow_vmcs)
11845 copy_shadow_to_vmcs12(vmx);
11848 * The nested entry process starts with enforcing various prerequisites
11849 * on vmcs12 as required by the Intel SDM, and act appropriately when
11850 * they fail: As the SDM explains, some conditions should cause the
11851 * instruction to fail, while others will cause the instruction to seem
11852 * to succeed, but return an EXIT_REASON_INVALID_STATE.
11853 * To speed up the normal (success) code path, we should avoid checking
11854 * for misconfigurations which will anyway be caught by the processor
11855 * when using the merged vmcs02.
11857 if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
11858 nested_vmx_failValid(vcpu,
11859 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
11863 if (vmcs12->launch_state == launch) {
11864 nested_vmx_failValid(vcpu,
11865 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
11866 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
11870 ret = check_vmentry_prereqs(vcpu, vmcs12);
11872 nested_vmx_failValid(vcpu, ret);
11877 * After this point, the trap flag no longer triggers a singlestep trap
11878 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
11879 * This is not 100% correct; for performance reasons, we delegate most
11880 * of the checks on host state to the processor. If those fail,
11881 * the singlestep trap is missed.
11883 skip_emulated_instruction(vcpu);
11885 ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
11887 nested_vmx_entry_failure(vcpu, vmcs12,
11888 EXIT_REASON_INVALID_STATE, exit_qual);
11893 * We're finally done with prerequisite checking, and can start with
11894 * the nested entry.
11897 vmx->nested.nested_run_pending = 1;
11898 ret = enter_vmx_non_root_mode(vcpu);
11900 vmx->nested.nested_run_pending = 0;
11905 * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken
11906 * by event injection, halt vcpu.
11908 if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) &&
11909 !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK)) {
11910 vmx->nested.nested_run_pending = 0;
11911 return kvm_vcpu_halt(vcpu);
11916 return kvm_skip_emulated_instruction(vcpu);
11920 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11921 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11922 * This function returns the new value we should put in vmcs12.guest_cr0.
11923 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11924 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11925 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11926 * didn't trap the bit, because if L1 did, so would L0).
11927 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11928 * been modified by L2, and L1 knows it. So just leave the old value of
11929 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11930 * isn't relevant, because if L0 traps this bit it can set it to anything.
11931 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11932 * changed these bits, and therefore they need to be updated, but L0
11933 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11934 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11936 static inline unsigned long
11937 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11940 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
11941 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
11942 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
11943 vcpu->arch.cr0_guest_owned_bits));
11946 static inline unsigned long
11947 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11950 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
11951 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
11952 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
11953 vcpu->arch.cr4_guest_owned_bits));
11956 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
11957 struct vmcs12 *vmcs12)
11962 if (vcpu->arch.exception.injected) {
11963 nr = vcpu->arch.exception.nr;
11964 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11966 if (kvm_exception_is_soft(nr)) {
11967 vmcs12->vm_exit_instruction_len =
11968 vcpu->arch.event_exit_inst_len;
11969 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
11971 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
11973 if (vcpu->arch.exception.has_error_code) {
11974 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
11975 vmcs12->idt_vectoring_error_code =
11976 vcpu->arch.exception.error_code;
11979 vmcs12->idt_vectoring_info_field = idt_vectoring;
11980 } else if (vcpu->arch.nmi_injected) {
11981 vmcs12->idt_vectoring_info_field =
11982 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
11983 } else if (vcpu->arch.interrupt.injected) {
11984 nr = vcpu->arch.interrupt.nr;
11985 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11987 if (vcpu->arch.interrupt.soft) {
11988 idt_vectoring |= INTR_TYPE_SOFT_INTR;
11989 vmcs12->vm_entry_instruction_len =
11990 vcpu->arch.event_exit_inst_len;
11992 idt_vectoring |= INTR_TYPE_EXT_INTR;
11994 vmcs12->idt_vectoring_info_field = idt_vectoring;
11998 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
12000 struct vcpu_vmx *vmx = to_vmx(vcpu);
12001 unsigned long exit_qual;
12002 bool block_nested_events =
12003 vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
12005 if (vcpu->arch.exception.pending &&
12006 nested_vmx_check_exception(vcpu, &exit_qual)) {
12007 if (block_nested_events)
12009 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
12013 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
12014 vmx->nested.preemption_timer_expired) {
12015 if (block_nested_events)
12017 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
12021 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
12022 if (block_nested_events)
12024 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
12025 NMI_VECTOR | INTR_TYPE_NMI_INTR |
12026 INTR_INFO_VALID_MASK, 0);
12028 * The NMI-triggered VM exit counts as injection:
12029 * clear this one and block further NMIs.
12031 vcpu->arch.nmi_pending = 0;
12032 vmx_set_nmi_mask(vcpu, true);
12036 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
12037 nested_exit_on_intr(vcpu)) {
12038 if (block_nested_events)
12040 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
12044 vmx_complete_nested_posted_interrupt(vcpu);
12048 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
12050 ktime_t remaining =
12051 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
12054 if (ktime_to_ns(remaining) <= 0)
12057 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
12058 do_div(value, 1000000);
12059 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
12063 * Update the guest state fields of vmcs12 to reflect changes that
12064 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
12065 * VM-entry controls is also updated, since this is really a guest
12068 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
12070 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
12071 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
12073 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
12074 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
12075 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
12077 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
12078 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
12079 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
12080 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
12081 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
12082 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
12083 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
12084 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
12085 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
12086 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
12087 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
12088 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
12089 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
12090 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
12091 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
12092 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
12093 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
12094 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
12095 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
12096 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
12097 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
12098 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
12099 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
12100 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
12101 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
12102 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
12103 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
12104 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
12105 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
12106 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
12107 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
12108 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
12109 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
12110 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
12111 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
12112 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
12114 vmcs12->guest_interruptibility_info =
12115 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
12116 vmcs12->guest_pending_dbg_exceptions =
12117 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
12118 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
12119 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
12121 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
12123 if (nested_cpu_has_preemption_timer(vmcs12)) {
12124 if (vmcs12->vm_exit_controls &
12125 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
12126 vmcs12->vmx_preemption_timer_value =
12127 vmx_get_preemption_timer_value(vcpu);
12128 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
12132 * In some cases (usually, nested EPT), L2 is allowed to change its
12133 * own CR3 without exiting. If it has changed it, we must keep it.
12134 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
12135 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
12137 * Additionally, restore L2's PDPTR to vmcs12.
12140 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
12141 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
12142 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
12143 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
12144 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
12147 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
12149 if (nested_cpu_has_vid(vmcs12))
12150 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
12152 vmcs12->vm_entry_controls =
12153 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
12154 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
12156 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
12157 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
12158 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
12161 /* TODO: These cannot have changed unless we have MSR bitmaps and
12162 * the relevant bit asks not to trap the change */
12163 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
12164 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
12165 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
12166 vmcs12->guest_ia32_efer = vcpu->arch.efer;
12167 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
12168 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
12169 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
12170 if (kvm_mpx_supported())
12171 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
12175 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
12176 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
12177 * and this function updates it to reflect the changes to the guest state while
12178 * L2 was running (and perhaps made some exits which were handled directly by L0
12179 * without going back to L1), and to reflect the exit reason.
12180 * Note that we do not have to copy here all VMCS fields, just those that
12181 * could have changed by the L2 guest or the exit - i.e., the guest-state and
12182 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
12183 * which already writes to vmcs12 directly.
12185 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
12186 u32 exit_reason, u32 exit_intr_info,
12187 unsigned long exit_qualification)
12189 /* update guest state fields: */
12190 sync_vmcs12(vcpu, vmcs12);
12192 /* update exit information fields: */
12194 vmcs12->vm_exit_reason = exit_reason;
12195 vmcs12->exit_qualification = exit_qualification;
12196 vmcs12->vm_exit_intr_info = exit_intr_info;
12198 vmcs12->idt_vectoring_info_field = 0;
12199 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
12200 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
12202 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
12203 vmcs12->launch_state = 1;
12205 /* vm_entry_intr_info_field is cleared on exit. Emulate this
12206 * instead of reading the real value. */
12207 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
12210 * Transfer the event that L0 or L1 may wanted to inject into
12211 * L2 to IDT_VECTORING_INFO_FIELD.
12213 vmcs12_save_pending_event(vcpu, vmcs12);
12217 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
12218 * preserved above and would only end up incorrectly in L1.
12220 vcpu->arch.nmi_injected = false;
12221 kvm_clear_exception_queue(vcpu);
12222 kvm_clear_interrupt_queue(vcpu);
12225 static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu,
12226 struct vmcs12 *vmcs12)
12228 u32 entry_failure_code;
12230 nested_ept_uninit_mmu_context(vcpu);
12233 * Only PDPTE load can fail as the value of cr3 was checked on entry and
12234 * couldn't have changed.
12236 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
12237 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
12240 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
12244 * A part of what we need to when the nested L2 guest exits and we want to
12245 * run its L1 parent, is to reset L1's guest state to the host state specified
12247 * This function is to be called not only on normal nested exit, but also on
12248 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
12249 * Failures During or After Loading Guest State").
12250 * This function should be called when the active VMCS is L1's (vmcs01).
12252 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
12253 struct vmcs12 *vmcs12)
12255 struct kvm_segment seg;
12257 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
12258 vcpu->arch.efer = vmcs12->host_ia32_efer;
12259 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
12260 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
12262 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
12263 vmx_set_efer(vcpu, vcpu->arch.efer);
12265 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
12266 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
12267 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
12269 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
12270 * actually changed, because vmx_set_cr0 refers to efer set above.
12272 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
12273 * (KVM doesn't change it);
12275 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
12276 vmx_set_cr0(vcpu, vmcs12->host_cr0);
12278 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
12279 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
12280 vmx_set_cr4(vcpu, vmcs12->host_cr4);
12282 load_vmcs12_mmu_host_state(vcpu, vmcs12);
12285 * If vmcs01 don't use VPID, CPU flushes TLB on every
12286 * VMEntry/VMExit. Thus, no need to flush TLB.
12288 * If vmcs12 uses VPID, TLB entries populated by L2 are
12289 * tagged with vmx->nested.vpid02 while L1 entries are tagged
12290 * with vmx->vpid. Thus, no need to flush TLB.
12292 * Therefore, flush TLB only in case vmcs01 uses VPID and
12293 * vmcs12 don't use VPID as in this case L1 & L2 TLB entries
12294 * are both tagged with vmx->vpid.
12297 !(nested_cpu_has_vpid(vmcs12) && to_vmx(vcpu)->nested.vpid02)) {
12298 vmx_flush_tlb(vcpu, true);
12301 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
12302 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
12303 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
12304 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
12305 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
12306 vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
12307 vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
12309 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
12310 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
12311 vmcs_write64(GUEST_BNDCFGS, 0);
12313 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
12314 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
12315 vcpu->arch.pat = vmcs12->host_ia32_pat;
12317 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
12318 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
12319 vmcs12->host_ia32_perf_global_ctrl);
12321 /* Set L1 segment info according to Intel SDM
12322 27.5.2 Loading Host Segment and Descriptor-Table Registers */
12323 seg = (struct kvm_segment) {
12325 .limit = 0xFFFFFFFF,
12326 .selector = vmcs12->host_cs_selector,
12332 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
12336 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
12337 seg = (struct kvm_segment) {
12339 .limit = 0xFFFFFFFF,
12346 seg.selector = vmcs12->host_ds_selector;
12347 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
12348 seg.selector = vmcs12->host_es_selector;
12349 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
12350 seg.selector = vmcs12->host_ss_selector;
12351 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
12352 seg.selector = vmcs12->host_fs_selector;
12353 seg.base = vmcs12->host_fs_base;
12354 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
12355 seg.selector = vmcs12->host_gs_selector;
12356 seg.base = vmcs12->host_gs_base;
12357 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
12358 seg = (struct kvm_segment) {
12359 .base = vmcs12->host_tr_base,
12361 .selector = vmcs12->host_tr_selector,
12365 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
12367 kvm_set_dr(vcpu, 7, 0x400);
12368 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
12370 if (cpu_has_vmx_msr_bitmap())
12371 vmx_update_msr_bitmap(vcpu);
12373 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
12374 vmcs12->vm_exit_msr_load_count))
12375 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
12379 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
12380 * and modify vmcs12 to make it see what it would expect to see there if
12381 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
12383 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
12384 u32 exit_intr_info,
12385 unsigned long exit_qualification)
12387 struct vcpu_vmx *vmx = to_vmx(vcpu);
12388 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12390 /* trying to cancel vmlaunch/vmresume is a bug */
12391 WARN_ON_ONCE(vmx->nested.nested_run_pending);
12394 * The only expected VM-instruction error is "VM entry with
12395 * invalid control field(s)." Anything else indicates a
12398 WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
12399 VMXERR_ENTRY_INVALID_CONTROL_FIELD));
12401 leave_guest_mode(vcpu);
12403 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
12404 vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
12406 if (likely(!vmx->fail)) {
12407 if (exit_reason == -1)
12408 sync_vmcs12(vcpu, vmcs12);
12410 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
12411 exit_qualification);
12413 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
12414 vmcs12->vm_exit_msr_store_count))
12415 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
12418 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
12419 vm_entry_controls_reset_shadow(vmx);
12420 vm_exit_controls_reset_shadow(vmx);
12421 vmx_segment_cache_clear(vmx);
12423 /* Update any VMCS fields that might have changed while L2 ran */
12424 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
12425 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
12426 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
12427 if (vmx->hv_deadline_tsc == -1)
12428 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
12429 PIN_BASED_VMX_PREEMPTION_TIMER);
12431 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
12432 PIN_BASED_VMX_PREEMPTION_TIMER);
12433 if (kvm_has_tsc_control)
12434 decache_tsc_multiplier(vmx);
12436 if (vmx->nested.change_vmcs01_virtual_apic_mode) {
12437 vmx->nested.change_vmcs01_virtual_apic_mode = false;
12438 vmx_set_virtual_apic_mode(vcpu);
12439 } else if (!nested_cpu_has_ept(vmcs12) &&
12440 nested_cpu_has2(vmcs12,
12441 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
12442 vmx_flush_tlb(vcpu, true);
12445 /* This is needed for same reason as it was needed in prepare_vmcs02 */
12448 /* Unpin physical memory we referred to in vmcs02 */
12449 if (vmx->nested.apic_access_page) {
12450 kvm_release_page_dirty(vmx->nested.apic_access_page);
12451 vmx->nested.apic_access_page = NULL;
12453 if (vmx->nested.virtual_apic_page) {
12454 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
12455 vmx->nested.virtual_apic_page = NULL;
12457 if (vmx->nested.pi_desc_page) {
12458 kunmap(vmx->nested.pi_desc_page);
12459 kvm_release_page_dirty(vmx->nested.pi_desc_page);
12460 vmx->nested.pi_desc_page = NULL;
12461 vmx->nested.pi_desc = NULL;
12465 * We are now running in L2, mmu_notifier will force to reload the
12466 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
12468 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
12470 if (enable_shadow_vmcs && exit_reason != -1)
12471 vmx->nested.sync_shadow_vmcs = true;
12473 /* in case we halted in L2 */
12474 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
12476 if (likely(!vmx->fail)) {
12478 * TODO: SDM says that with acknowledge interrupt on
12479 * exit, bit 31 of the VM-exit interrupt information
12480 * (valid interrupt) is always set to 1 on
12481 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
12482 * need kvm_cpu_has_interrupt(). See the commit
12483 * message for details.
12485 if (nested_exit_intr_ack_set(vcpu) &&
12486 exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
12487 kvm_cpu_has_interrupt(vcpu)) {
12488 int irq = kvm_cpu_get_interrupt(vcpu);
12490 vmcs12->vm_exit_intr_info = irq |
12491 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
12494 if (exit_reason != -1)
12495 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
12496 vmcs12->exit_qualification,
12497 vmcs12->idt_vectoring_info_field,
12498 vmcs12->vm_exit_intr_info,
12499 vmcs12->vm_exit_intr_error_code,
12502 load_vmcs12_host_state(vcpu, vmcs12);
12508 * After an early L2 VM-entry failure, we're now back
12509 * in L1 which thinks it just finished a VMLAUNCH or
12510 * VMRESUME instruction, so we need to set the failure
12511 * flag and the VM-instruction error field of the VMCS
12514 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
12516 load_vmcs12_mmu_host_state(vcpu, vmcs12);
12519 * The emulated instruction was already skipped in
12520 * nested_vmx_run, but the updated RIP was never
12521 * written back to the vmcs01.
12523 skip_emulated_instruction(vcpu);
12528 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
12530 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
12532 if (is_guest_mode(vcpu)) {
12533 to_vmx(vcpu)->nested.nested_run_pending = 0;
12534 nested_vmx_vmexit(vcpu, -1, 0, 0);
12536 free_nested(to_vmx(vcpu));
12540 * L1's failure to enter L2 is a subset of a normal exit, as explained in
12541 * 23.7 "VM-entry failures during or after loading guest state" (this also
12542 * lists the acceptable exit-reason and exit-qualification parameters).
12543 * It should only be called before L2 actually succeeded to run, and when
12544 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
12546 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
12547 struct vmcs12 *vmcs12,
12548 u32 reason, unsigned long qualification)
12550 load_vmcs12_host_state(vcpu, vmcs12);
12551 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
12552 vmcs12->exit_qualification = qualification;
12553 nested_vmx_succeed(vcpu);
12554 if (enable_shadow_vmcs)
12555 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
12558 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
12559 struct x86_instruction_info *info,
12560 enum x86_intercept_stage stage)
12562 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
12563 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
12566 * RDPID causes #UD if disabled through secondary execution controls.
12567 * Because it is marked as EmulateOnUD, we need to intercept it here.
12569 if (info->intercept == x86_intercept_rdtscp &&
12570 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
12571 ctxt->exception.vector = UD_VECTOR;
12572 ctxt->exception.error_code_valid = false;
12573 return X86EMUL_PROPAGATE_FAULT;
12576 /* TODO: check more intercepts... */
12577 return X86EMUL_CONTINUE;
12580 #ifdef CONFIG_X86_64
12581 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
12582 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
12583 u64 divisor, u64 *result)
12585 u64 low = a << shift, high = a >> (64 - shift);
12587 /* To avoid the overflow on divq */
12588 if (high >= divisor)
12591 /* Low hold the result, high hold rem which is discarded */
12592 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
12593 "rm" (divisor), "0" (low), "1" (high));
12599 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
12601 struct vcpu_vmx *vmx;
12602 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
12604 if (kvm_mwait_in_guest(vcpu->kvm))
12605 return -EOPNOTSUPP;
12607 vmx = to_vmx(vcpu);
12609 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
12610 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
12611 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, lapic_timer_advance_ns);
12613 if (delta_tsc > lapic_timer_advance_cycles)
12614 delta_tsc -= lapic_timer_advance_cycles;
12618 /* Convert to host delta tsc if tsc scaling is enabled */
12619 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
12620 u64_shl_div_u64(delta_tsc,
12621 kvm_tsc_scaling_ratio_frac_bits,
12622 vcpu->arch.tsc_scaling_ratio,
12627 * If the delta tsc can't fit in the 32 bit after the multi shift,
12628 * we can't use the preemption timer.
12629 * It's possible that it fits on later vmentries, but checking
12630 * on every vmentry is costly so we just use an hrtimer.
12632 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
12635 vmx->hv_deadline_tsc = tscl + delta_tsc;
12636 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
12637 PIN_BASED_VMX_PREEMPTION_TIMER);
12639 return delta_tsc == 0;
12642 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
12644 struct vcpu_vmx *vmx = to_vmx(vcpu);
12645 vmx->hv_deadline_tsc = -1;
12646 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
12647 PIN_BASED_VMX_PREEMPTION_TIMER);
12651 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
12653 if (!kvm_pause_in_guest(vcpu->kvm))
12654 shrink_ple_window(vcpu);
12657 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
12658 struct kvm_memory_slot *slot)
12660 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
12661 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
12664 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
12665 struct kvm_memory_slot *slot)
12667 kvm_mmu_slot_set_dirty(kvm, slot);
12670 static void vmx_flush_log_dirty(struct kvm *kvm)
12672 kvm_flush_pml_buffers(kvm);
12675 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
12677 struct vmcs12 *vmcs12;
12678 struct vcpu_vmx *vmx = to_vmx(vcpu);
12680 struct page *page = NULL;
12683 if (is_guest_mode(vcpu)) {
12684 WARN_ON_ONCE(vmx->nested.pml_full);
12687 * Check if PML is enabled for the nested guest.
12688 * Whether eptp bit 6 is set is already checked
12689 * as part of A/D emulation.
12691 vmcs12 = get_vmcs12(vcpu);
12692 if (!nested_cpu_has_pml(vmcs12))
12695 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
12696 vmx->nested.pml_full = true;
12700 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
12702 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
12703 if (is_error_page(page))
12706 pml_address = kmap(page);
12707 pml_address[vmcs12->guest_pml_index--] = gpa;
12709 kvm_release_page_clean(page);
12715 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
12716 struct kvm_memory_slot *memslot,
12717 gfn_t offset, unsigned long mask)
12719 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
12722 static void __pi_post_block(struct kvm_vcpu *vcpu)
12724 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12725 struct pi_desc old, new;
12729 old.control = new.control = pi_desc->control;
12730 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
12731 "Wakeup handler not enabled while the VCPU is blocked\n");
12733 dest = cpu_physical_id(vcpu->cpu);
12735 if (x2apic_enabled())
12738 new.ndst = (dest << 8) & 0xFF00;
12740 /* set 'NV' to 'notification vector' */
12741 new.nv = POSTED_INTR_VECTOR;
12742 } while (cmpxchg64(&pi_desc->control, old.control,
12743 new.control) != old.control);
12745 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
12746 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12747 list_del(&vcpu->blocked_vcpu_list);
12748 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12749 vcpu->pre_pcpu = -1;
12754 * This routine does the following things for vCPU which is going
12755 * to be blocked if VT-d PI is enabled.
12756 * - Store the vCPU to the wakeup list, so when interrupts happen
12757 * we can find the right vCPU to wake up.
12758 * - Change the Posted-interrupt descriptor as below:
12759 * 'NDST' <-- vcpu->pre_pcpu
12760 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
12761 * - If 'ON' is set during this process, which means at least one
12762 * interrupt is posted for this vCPU, we cannot block it, in
12763 * this case, return 1, otherwise, return 0.
12766 static int pi_pre_block(struct kvm_vcpu *vcpu)
12769 struct pi_desc old, new;
12770 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
12772 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
12773 !irq_remapping_cap(IRQ_POSTING_CAP) ||
12774 !kvm_vcpu_apicv_active(vcpu))
12777 WARN_ON(irqs_disabled());
12778 local_irq_disable();
12779 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
12780 vcpu->pre_pcpu = vcpu->cpu;
12781 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12782 list_add_tail(&vcpu->blocked_vcpu_list,
12783 &per_cpu(blocked_vcpu_on_cpu,
12785 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12789 old.control = new.control = pi_desc->control;
12791 WARN((pi_desc->sn == 1),
12792 "Warning: SN field of posted-interrupts "
12793 "is set before blocking\n");
12796 * Since vCPU can be preempted during this process,
12797 * vcpu->cpu could be different with pre_pcpu, we
12798 * need to set pre_pcpu as the destination of wakeup
12799 * notification event, then we can find the right vCPU
12800 * to wakeup in wakeup handler if interrupts happen
12801 * when the vCPU is in blocked state.
12803 dest = cpu_physical_id(vcpu->pre_pcpu);
12805 if (x2apic_enabled())
12808 new.ndst = (dest << 8) & 0xFF00;
12810 /* set 'NV' to 'wakeup vector' */
12811 new.nv = POSTED_INTR_WAKEUP_VECTOR;
12812 } while (cmpxchg64(&pi_desc->control, old.control,
12813 new.control) != old.control);
12815 /* We should not block the vCPU if an interrupt is posted for it. */
12816 if (pi_test_on(pi_desc) == 1)
12817 __pi_post_block(vcpu);
12819 local_irq_enable();
12820 return (vcpu->pre_pcpu == -1);
12823 static int vmx_pre_block(struct kvm_vcpu *vcpu)
12825 if (pi_pre_block(vcpu))
12828 if (kvm_lapic_hv_timer_in_use(vcpu))
12829 kvm_lapic_switch_to_sw_timer(vcpu);
12834 static void pi_post_block(struct kvm_vcpu *vcpu)
12836 if (vcpu->pre_pcpu == -1)
12839 WARN_ON(irqs_disabled());
12840 local_irq_disable();
12841 __pi_post_block(vcpu);
12842 local_irq_enable();
12845 static void vmx_post_block(struct kvm_vcpu *vcpu)
12847 if (kvm_x86_ops->set_hv_timer)
12848 kvm_lapic_switch_to_hv_timer(vcpu);
12850 pi_post_block(vcpu);
12854 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
12857 * @host_irq: host irq of the interrupt
12858 * @guest_irq: gsi of the interrupt
12859 * @set: set or unset PI
12860 * returns 0 on success, < 0 on failure
12862 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
12863 uint32_t guest_irq, bool set)
12865 struct kvm_kernel_irq_routing_entry *e;
12866 struct kvm_irq_routing_table *irq_rt;
12867 struct kvm_lapic_irq irq;
12868 struct kvm_vcpu *vcpu;
12869 struct vcpu_data vcpu_info;
12872 if (!kvm_arch_has_assigned_device(kvm) ||
12873 !irq_remapping_cap(IRQ_POSTING_CAP) ||
12874 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
12877 idx = srcu_read_lock(&kvm->irq_srcu);
12878 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
12879 if (guest_irq >= irq_rt->nr_rt_entries ||
12880 hlist_empty(&irq_rt->map[guest_irq])) {
12881 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
12882 guest_irq, irq_rt->nr_rt_entries);
12886 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
12887 if (e->type != KVM_IRQ_ROUTING_MSI)
12890 * VT-d PI cannot support posting multicast/broadcast
12891 * interrupts to a vCPU, we still use interrupt remapping
12892 * for these kind of interrupts.
12894 * For lowest-priority interrupts, we only support
12895 * those with single CPU as the destination, e.g. user
12896 * configures the interrupts via /proc/irq or uses
12897 * irqbalance to make the interrupts single-CPU.
12899 * We will support full lowest-priority interrupt later.
12902 kvm_set_msi_irq(kvm, e, &irq);
12903 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
12905 * Make sure the IRTE is in remapped mode if
12906 * we don't handle it in posted mode.
12908 ret = irq_set_vcpu_affinity(host_irq, NULL);
12911 "failed to back to remapped mode, irq: %u\n",
12919 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
12920 vcpu_info.vector = irq.vector;
12922 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
12923 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
12926 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
12928 ret = irq_set_vcpu_affinity(host_irq, NULL);
12931 printk(KERN_INFO "%s: failed to update PI IRTE\n",
12939 srcu_read_unlock(&kvm->irq_srcu, idx);
12943 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
12945 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
12946 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
12947 FEATURE_CONTROL_LMCE;
12949 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
12950 ~FEATURE_CONTROL_LMCE;
12953 static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
12955 /* we need a nested vmexit to enter SMM, postpone if run is pending */
12956 if (to_vmx(vcpu)->nested.nested_run_pending)
12961 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
12963 struct vcpu_vmx *vmx = to_vmx(vcpu);
12965 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
12966 if (vmx->nested.smm.guest_mode)
12967 nested_vmx_vmexit(vcpu, -1, 0, 0);
12969 vmx->nested.smm.vmxon = vmx->nested.vmxon;
12970 vmx->nested.vmxon = false;
12971 vmx_clear_hlt(vcpu);
12975 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
12977 struct vcpu_vmx *vmx = to_vmx(vcpu);
12980 if (vmx->nested.smm.vmxon) {
12981 vmx->nested.vmxon = true;
12982 vmx->nested.smm.vmxon = false;
12985 if (vmx->nested.smm.guest_mode) {
12986 vcpu->arch.hflags &= ~HF_SMM_MASK;
12987 ret = enter_vmx_non_root_mode(vcpu);
12988 vcpu->arch.hflags |= HF_SMM_MASK;
12992 vmx->nested.smm.guest_mode = false;
12997 static int enable_smi_window(struct kvm_vcpu *vcpu)
13002 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
13003 .cpu_has_kvm_support = cpu_has_kvm_support,
13004 .disabled_by_bios = vmx_disabled_by_bios,
13005 .hardware_setup = hardware_setup,
13006 .hardware_unsetup = hardware_unsetup,
13007 .check_processor_compatibility = vmx_check_processor_compat,
13008 .hardware_enable = hardware_enable,
13009 .hardware_disable = hardware_disable,
13010 .cpu_has_accelerated_tpr = report_flexpriority,
13011 .has_emulated_msr = vmx_has_emulated_msr,
13013 .vm_init = vmx_vm_init,
13014 .vm_alloc = vmx_vm_alloc,
13015 .vm_free = vmx_vm_free,
13017 .vcpu_create = vmx_create_vcpu,
13018 .vcpu_free = vmx_free_vcpu,
13019 .vcpu_reset = vmx_vcpu_reset,
13021 .prepare_guest_switch = vmx_save_host_state,
13022 .vcpu_load = vmx_vcpu_load,
13023 .vcpu_put = vmx_vcpu_put,
13025 .update_bp_intercept = update_exception_bitmap,
13026 .get_msr_feature = vmx_get_msr_feature,
13027 .get_msr = vmx_get_msr,
13028 .set_msr = vmx_set_msr,
13029 .get_segment_base = vmx_get_segment_base,
13030 .get_segment = vmx_get_segment,
13031 .set_segment = vmx_set_segment,
13032 .get_cpl = vmx_get_cpl,
13033 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
13034 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
13035 .decache_cr3 = vmx_decache_cr3,
13036 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
13037 .set_cr0 = vmx_set_cr0,
13038 .set_cr3 = vmx_set_cr3,
13039 .set_cr4 = vmx_set_cr4,
13040 .set_efer = vmx_set_efer,
13041 .get_idt = vmx_get_idt,
13042 .set_idt = vmx_set_idt,
13043 .get_gdt = vmx_get_gdt,
13044 .set_gdt = vmx_set_gdt,
13045 .get_dr6 = vmx_get_dr6,
13046 .set_dr6 = vmx_set_dr6,
13047 .set_dr7 = vmx_set_dr7,
13048 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
13049 .cache_reg = vmx_cache_reg,
13050 .get_rflags = vmx_get_rflags,
13051 .set_rflags = vmx_set_rflags,
13053 .tlb_flush = vmx_flush_tlb,
13055 .run = vmx_vcpu_run,
13056 .handle_exit = vmx_handle_exit,
13057 .skip_emulated_instruction = skip_emulated_instruction,
13058 .set_interrupt_shadow = vmx_set_interrupt_shadow,
13059 .get_interrupt_shadow = vmx_get_interrupt_shadow,
13060 .patch_hypercall = vmx_patch_hypercall,
13061 .set_irq = vmx_inject_irq,
13062 .set_nmi = vmx_inject_nmi,
13063 .queue_exception = vmx_queue_exception,
13064 .cancel_injection = vmx_cancel_injection,
13065 .interrupt_allowed = vmx_interrupt_allowed,
13066 .nmi_allowed = vmx_nmi_allowed,
13067 .get_nmi_mask = vmx_get_nmi_mask,
13068 .set_nmi_mask = vmx_set_nmi_mask,
13069 .enable_nmi_window = enable_nmi_window,
13070 .enable_irq_window = enable_irq_window,
13071 .update_cr8_intercept = update_cr8_intercept,
13072 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
13073 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
13074 .get_enable_apicv = vmx_get_enable_apicv,
13075 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
13076 .load_eoi_exitmap = vmx_load_eoi_exitmap,
13077 .apicv_post_state_restore = vmx_apicv_post_state_restore,
13078 .hwapic_irr_update = vmx_hwapic_irr_update,
13079 .hwapic_isr_update = vmx_hwapic_isr_update,
13080 .sync_pir_to_irr = vmx_sync_pir_to_irr,
13081 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
13083 .set_tss_addr = vmx_set_tss_addr,
13084 .set_identity_map_addr = vmx_set_identity_map_addr,
13085 .get_tdp_level = get_ept_level,
13086 .get_mt_mask = vmx_get_mt_mask,
13088 .get_exit_info = vmx_get_exit_info,
13090 .get_lpage_level = vmx_get_lpage_level,
13092 .cpuid_update = vmx_cpuid_update,
13094 .rdtscp_supported = vmx_rdtscp_supported,
13095 .invpcid_supported = vmx_invpcid_supported,
13097 .set_supported_cpuid = vmx_set_supported_cpuid,
13099 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
13101 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
13102 .write_tsc_offset = vmx_write_tsc_offset,
13104 .set_tdp_cr3 = vmx_set_cr3,
13106 .check_intercept = vmx_check_intercept,
13107 .handle_external_intr = vmx_handle_external_intr,
13108 .mpx_supported = vmx_mpx_supported,
13109 .xsaves_supported = vmx_xsaves_supported,
13110 .umip_emulated = vmx_umip_emulated,
13112 .check_nested_events = vmx_check_nested_events,
13114 .sched_in = vmx_sched_in,
13116 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
13117 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
13118 .flush_log_dirty = vmx_flush_log_dirty,
13119 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
13120 .write_log_dirty = vmx_write_pml_buffer,
13122 .pre_block = vmx_pre_block,
13123 .post_block = vmx_post_block,
13125 .pmu_ops = &intel_pmu_ops,
13127 .update_pi_irte = vmx_update_pi_irte,
13129 #ifdef CONFIG_X86_64
13130 .set_hv_timer = vmx_set_hv_timer,
13131 .cancel_hv_timer = vmx_cancel_hv_timer,
13134 .setup_mce = vmx_setup_mce,
13136 .smi_allowed = vmx_smi_allowed,
13137 .pre_enter_smm = vmx_pre_enter_smm,
13138 .pre_leave_smm = vmx_pre_leave_smm,
13139 .enable_smi_window = enable_smi_window,
13142 static int __init vmx_init(void)
13146 #if IS_ENABLED(CONFIG_HYPERV)
13148 * Enlightened VMCS usage should be recommended and the host needs
13149 * to support eVMCS v1 or above. We can also disable eVMCS support
13150 * with module parameter.
13152 if (enlightened_vmcs &&
13153 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
13154 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
13155 KVM_EVMCS_VERSION) {
13158 /* Check that we have assist pages on all online CPUs */
13159 for_each_online_cpu(cpu) {
13160 if (!hv_get_vp_assist_page(cpu)) {
13161 enlightened_vmcs = false;
13166 if (enlightened_vmcs) {
13167 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
13168 static_branch_enable(&enable_evmcs);
13171 enlightened_vmcs = false;
13175 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
13176 __alignof__(struct vcpu_vmx), THIS_MODULE);
13180 #ifdef CONFIG_KEXEC_CORE
13181 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
13182 crash_vmclear_local_loaded_vmcss);
13184 vmx_check_vmcs12_offsets();
13189 static void __exit vmx_exit(void)
13191 #ifdef CONFIG_KEXEC_CORE
13192 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
13198 #if IS_ENABLED(CONFIG_HYPERV)
13199 if (static_branch_unlikely(&enable_evmcs)) {
13201 struct hv_vp_assist_page *vp_ap;
13203 * Reset everything to support using non-enlightened VMCS
13204 * access later (e.g. when we reload the module with
13205 * enlightened_vmcs=0)
13207 for_each_online_cpu(cpu) {
13208 vp_ap = hv_get_vp_assist_page(cpu);
13213 vp_ap->current_nested_vmcs = 0;
13214 vp_ap->enlighten_vmentry = 0;
13217 static_branch_disable(&enable_evmcs);
13222 module_init(vmx_init)
13223 module_exit(vmx_exit)