arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/frame.h>
  37 #include "kvm_cache_regs.h"
  38 #include "x86.h"
  39
  40 #include <asm/cpu.h>
  41 #include <asm/io.h>
  42 #include <asm/desc.h>
  43 #include <asm/vmx.h>
  44 #include <asm/virtext.h>
  45 #include <asm/mce.h>
  46 #include <asm/fpu/internal.h>
  47 #include <asm/perf_event.h>
  48 #include <asm/debugreg.h>
  49 #include <asm/kexec.h>
  50 #include <asm/apic.h>
  51 #include <asm/irq_remapping.h>
  52 #include <asm/mmu_context.h>
  53 #include <asm/nospec-branch.h>
  54
  55 #include "trace.h"
  56 #include "pmu.h"
  57
  58 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  59 #define __ex_clear(x, reg) \
  60         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  61
  62 MODULE_AUTHOR("Qumranet");
  63 MODULE_LICENSE("GPL");
  64
  65 static const struct x86_cpu_id vmx_cpu_id[] = {
  66         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  67         {}
  68 };
  69 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  70
  71 static bool __read_mostly enable_vpid = 1;
  72 module_param_named(vpid, enable_vpid, bool, 0444);
  73
  74 static bool __read_mostly flexpriority_enabled = 1;
  75 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_ept = 1;
  78 module_param_named(ept, enable_ept, bool, S_IRUGO);
  79
  80 static bool __read_mostly enable_unrestricted_guest = 1;
  81 module_param_named(unrestricted_guest,
  82                         enable_unrestricted_guest, bool, S_IRUGO);
  83
  84 static bool __read_mostly enable_ept_ad_bits = 1;
  85 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  86
  87 static bool __read_mostly emulate_invalid_guest_state = true;
  88 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 114 static int __read_mostly cpu_preemption_timer_multi;
 115 static bool __read_mostly enable_preemption_timer = 1;
 116 #ifdef CONFIG_X86_64
 117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 118 #endif
 119
 120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 122 #define KVM_VM_CR0_ALWAYS_ON                                            \
 123         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 124 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 125         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 126          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 127
 128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 130
 131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 132
 133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 134
 135 /*
 136  * Hyper-V requires all of these, so mark them as supported even though
 137  * they are just treated the same as all-context.
 138  */
 139 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 140         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 141         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 142         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 143         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 144
 145 /*
 146  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 147  * ple_gap:    upper bound on the amount of time between two successive
 148  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 149  *             According to test, this time is usually smaller than 128 cycles.
 150  * ple_window: upper bound on the amount of time a guest is allowed to execute
 151  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 152  *             less than 2^12 cycles
 153  * Time is measured based on a counter that runs at the same rate as the TSC,
 154  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 155  */
 156 #define KVM_VMX_DEFAULT_PLE_GAP           128
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 158 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 160 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 161                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 162
 163 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 164 module_param(ple_gap, int, S_IRUGO);
 165
 166 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 167 module_param(ple_window, int, S_IRUGO);
 168
 169 /* Default doubles per-vcpu window every exit. */
 170 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 171 module_param(ple_window_grow, int, S_IRUGO);
 172
 173 /* Default resets per-vcpu window every exit to ple_window. */
 174 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 175 module_param(ple_window_shrink, int, S_IRUGO);
 176
 177 /* Default is to compute the maximum so we can never overflow. */
 178 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 180 module_param(ple_window_max, int, S_IRUGO);
 181
 182 extern const ulong vmx_return;
 183
 184 #define NR_AUTOLOAD_MSRS 8
 185 #define VMCS02_POOL_SIZE 1
 186
 187 struct vmcs {
 188         u32 revision_id;
 189         u32 abort;
 190         char data[0];
 191 };
 192
 193 /*
 194  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 195  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 196  * loaded on this CPU (so we can clear them if the CPU goes down).
 197  */
 198 struct loaded_vmcs {
 199         struct vmcs *vmcs;
 200         struct vmcs *shadow_vmcs;
 201         int cpu;
 202         bool launched;
 203         bool nmi_known_unmasked;
 204         unsigned long vmcs_host_cr3;    /* May not match real cr3 */
 205         unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 206         struct list_head loaded_vmcss_on_cpu_link;
 207 };
 208
 209 struct shared_msr_entry {
 210         unsigned index;
 211         u64 data;
 212         u64 mask;
 213 };
 214
 215 /*
 216  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 217  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 218  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 219  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 220  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 221  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 222  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 223  * underlying hardware which will be used to run L2.
 224  * This structure is packed to ensure that its layout is identical across
 225  * machines (necessary for live migration).
 226  * If there are changes in this struct, VMCS12_REVISION must be changed.
 227  */
 228 typedef u64 natural_width;
 229 struct __packed vmcs12 {
 230         /* According to the Intel spec, a VMCS region must start with the
 231          * following two fields. Then follow implementation-specific data.
 232          */
 233         u32 revision_id;
 234         u32 abort;
 235
 236         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 237         u32 padding[7]; /* room for future expansion */
 238
 239         u64 io_bitmap_a;
 240         u64 io_bitmap_b;
 241         u64 msr_bitmap;
 242         u64 vm_exit_msr_store_addr;
 243         u64 vm_exit_msr_load_addr;
 244         u64 vm_entry_msr_load_addr;
 245         u64 tsc_offset;
 246         u64 virtual_apic_page_addr;
 247         u64 apic_access_addr;
 248         u64 posted_intr_desc_addr;
 249         u64 vm_function_control;
 250         u64 ept_pointer;
 251         u64 eoi_exit_bitmap0;
 252         u64 eoi_exit_bitmap1;
 253         u64 eoi_exit_bitmap2;
 254         u64 eoi_exit_bitmap3;
 255         u64 eptp_list_address;
 256         u64 xss_exit_bitmap;
 257         u64 guest_physical_address;
 258         u64 vmcs_link_pointer;
 259         u64 pml_address;
 260         u64 guest_ia32_debugctl;
 261         u64 guest_ia32_pat;
 262         u64 guest_ia32_efer;
 263         u64 guest_ia32_perf_global_ctrl;
 264         u64 guest_pdptr0;
 265         u64 guest_pdptr1;
 266         u64 guest_pdptr2;
 267         u64 guest_pdptr3;
 268         u64 guest_bndcfgs;
 269         u64 host_ia32_pat;
 270         u64 host_ia32_efer;
 271         u64 host_ia32_perf_global_ctrl;
 272         u64 padding64[8]; /* room for future expansion */
 273         /*
 274          * To allow migration of L1 (complete with its L2 guests) between
 275          * machines of different natural widths (32 or 64 bit), we cannot have
 276          * unsigned long fields with no explict size. We use u64 (aliased
 277          * natural_width) instead. Luckily, x86 is little-endian.
 278          */
 279         natural_width cr0_guest_host_mask;
 280         natural_width cr4_guest_host_mask;
 281         natural_width cr0_read_shadow;
 282         natural_width cr4_read_shadow;
 283         natural_width cr3_target_value0;
 284         natural_width cr3_target_value1;
 285         natural_width cr3_target_value2;
 286         natural_width cr3_target_value3;
 287         natural_width exit_qualification;
 288         natural_width guest_linear_address;
 289         natural_width guest_cr0;
 290         natural_width guest_cr3;
 291         natural_width guest_cr4;
 292         natural_width guest_es_base;
 293         natural_width guest_cs_base;
 294         natural_width guest_ss_base;
 295         natural_width guest_ds_base;
 296         natural_width guest_fs_base;
 297         natural_width guest_gs_base;
 298         natural_width guest_ldtr_base;
 299         natural_width guest_tr_base;
 300         natural_width guest_gdtr_base;
 301         natural_width guest_idtr_base;
 302         natural_width guest_dr7;
 303         natural_width guest_rsp;
 304         natural_width guest_rip;
 305         natural_width guest_rflags;
 306         natural_width guest_pending_dbg_exceptions;
 307         natural_width guest_sysenter_esp;
 308         natural_width guest_sysenter_eip;
 309         natural_width host_cr0;
 310         natural_width host_cr3;
 311         natural_width host_cr4;
 312         natural_width host_fs_base;
 313         natural_width host_gs_base;
 314         natural_width host_tr_base;
 315         natural_width host_gdtr_base;
 316         natural_width host_idtr_base;
 317         natural_width host_ia32_sysenter_esp;
 318         natural_width host_ia32_sysenter_eip;
 319         natural_width host_rsp;
 320         natural_width host_rip;
 321         natural_width paddingl[8]; /* room for future expansion */
 322         u32 pin_based_vm_exec_control;
 323         u32 cpu_based_vm_exec_control;
 324         u32 exception_bitmap;
 325         u32 page_fault_error_code_mask;
 326         u32 page_fault_error_code_match;
 327         u32 cr3_target_count;
 328         u32 vm_exit_controls;
 329         u32 vm_exit_msr_store_count;
 330         u32 vm_exit_msr_load_count;
 331         u32 vm_entry_controls;
 332         u32 vm_entry_msr_load_count;
 333         u32 vm_entry_intr_info_field;
 334         u32 vm_entry_exception_error_code;
 335         u32 vm_entry_instruction_len;
 336         u32 tpr_threshold;
 337         u32 secondary_vm_exec_control;
 338         u32 vm_instruction_error;
 339         u32 vm_exit_reason;
 340         u32 vm_exit_intr_info;
 341         u32 vm_exit_intr_error_code;
 342         u32 idt_vectoring_info_field;
 343         u32 idt_vectoring_error_code;
 344         u32 vm_exit_instruction_len;
 345         u32 vmx_instruction_info;
 346         u32 guest_es_limit;
 347         u32 guest_cs_limit;
 348         u32 guest_ss_limit;
 349         u32 guest_ds_limit;
 350         u32 guest_fs_limit;
 351         u32 guest_gs_limit;
 352         u32 guest_ldtr_limit;
 353         u32 guest_tr_limit;
 354         u32 guest_gdtr_limit;
 355         u32 guest_idtr_limit;
 356         u32 guest_es_ar_bytes;
 357         u32 guest_cs_ar_bytes;
 358         u32 guest_ss_ar_bytes;
 359         u32 guest_ds_ar_bytes;
 360         u32 guest_fs_ar_bytes;
 361         u32 guest_gs_ar_bytes;
 362         u32 guest_ldtr_ar_bytes;
 363         u32 guest_tr_ar_bytes;
 364         u32 guest_interruptibility_info;
 365         u32 guest_activity_state;
 366         u32 guest_sysenter_cs;
 367         u32 host_ia32_sysenter_cs;
 368         u32 vmx_preemption_timer_value;
 369         u32 padding32[7]; /* room for future expansion */
 370         u16 virtual_processor_id;
 371         u16 posted_intr_nv;
 372         u16 guest_es_selector;
 373         u16 guest_cs_selector;
 374         u16 guest_ss_selector;
 375         u16 guest_ds_selector;
 376         u16 guest_fs_selector;
 377         u16 guest_gs_selector;
 378         u16 guest_ldtr_selector;
 379         u16 guest_tr_selector;
 380         u16 guest_intr_status;
 381         u16 guest_pml_index;
 382         u16 host_es_selector;
 383         u16 host_cs_selector;
 384         u16 host_ss_selector;
 385         u16 host_ds_selector;
 386         u16 host_fs_selector;
 387         u16 host_gs_selector;
 388         u16 host_tr_selector;
 389 };
 390
 391 /*
 392  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 393  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 394  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 395  */
 396 #define VMCS12_REVISION 0x11e57ed0
 397
 398 /*
 399  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 400  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 401  * current implementation, 4K are reserved to avoid future complications.
 402  */
 403 #define VMCS12_SIZE 0x1000
 404
 405 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 406 struct vmcs02_list {
 407         struct list_head list;
 408         gpa_t vmptr;
 409         struct loaded_vmcs vmcs02;
 410 };
 411
 412 /*
 413  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 414  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 415  */
 416 struct nested_vmx {
 417         /* Has the level1 guest done vmxon? */
 418         bool vmxon;
 419         gpa_t vmxon_ptr;
 420         bool pml_full;
 421
 422         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 423         gpa_t current_vmptr;
 424         /*
 425          * Cache of the guest's VMCS, existing outside of guest memory.
 426          * Loaded from guest memory during VMPTRLD. Flushed to guest
 427          * memory during VMCLEAR and VMPTRLD.
 428          */
 429         struct vmcs12 *cached_vmcs12;
 430         /*
 431          * Indicates if the shadow vmcs must be updated with the
 432          * data hold by vmcs12
 433          */
 434         bool sync_shadow_vmcs;
 435
 436         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 437         struct list_head vmcs02_pool;
 438         int vmcs02_num;
 439         bool change_vmcs01_virtual_x2apic_mode;
 440         /* L2 must run next, and mustn't decide to exit to L1. */
 441         bool nested_run_pending;
 442         /*
 443          * Guest pages referred to in vmcs02 with host-physical pointers, so
 444          * we must keep them pinned while L2 runs.
 445          */
 446         struct page *apic_access_page;
 447         struct page *virtual_apic_page;
 448         struct page *pi_desc_page;
 449         struct pi_desc *pi_desc;
 450         bool pi_pending;
 451         u16 posted_intr_nv;
 452
 453         unsigned long *msr_bitmap;
 454
 455         struct hrtimer preemption_timer;
 456         bool preemption_timer_expired;
 457
 458         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 459         u64 vmcs01_debugctl;
 460
 461         u16 vpid02;
 462         u16 last_vpid;
 463
 464         /*
 465          * We only store the "true" versions of the VMX capability MSRs. We
 466          * generate the "non-true" versions by setting the must-be-1 bits
 467          * according to the SDM.
 468          */
 469         u32 nested_vmx_procbased_ctls_low;
 470         u32 nested_vmx_procbased_ctls_high;
 471         u32 nested_vmx_secondary_ctls_low;
 472         u32 nested_vmx_secondary_ctls_high;
 473         u32 nested_vmx_pinbased_ctls_low;
 474         u32 nested_vmx_pinbased_ctls_high;
 475         u32 nested_vmx_exit_ctls_low;
 476         u32 nested_vmx_exit_ctls_high;
 477         u32 nested_vmx_entry_ctls_low;
 478         u32 nested_vmx_entry_ctls_high;
 479         u32 nested_vmx_misc_low;
 480         u32 nested_vmx_misc_high;
 481         u32 nested_vmx_ept_caps;
 482         u32 nested_vmx_vpid_caps;
 483         u64 nested_vmx_basic;
 484         u64 nested_vmx_cr0_fixed0;
 485         u64 nested_vmx_cr0_fixed1;
 486         u64 nested_vmx_cr4_fixed0;
 487         u64 nested_vmx_cr4_fixed1;
 488         u64 nested_vmx_vmcs_enum;
 489         u64 nested_vmx_vmfunc_controls;
 490 };
 491
 492 #define POSTED_INTR_ON  0
 493 #define POSTED_INTR_SN  1
 494
 495 /* Posted-Interrupt Descriptor */
 496 struct pi_desc {
 497         u32 pir[8];     /* Posted interrupt requested */
 498         union {
 499                 struct {
 500                                 /* bit 256 - Outstanding Notification */
 501                         u16     on      : 1,
 502                                 /* bit 257 - Suppress Notification */
 503                                 sn      : 1,
 504                                 /* bit 271:258 - Reserved */
 505                                 rsvd_1  : 14;
 506                                 /* bit 279:272 - Notification Vector */
 507                         u8      nv;
 508                                 /* bit 287:280 - Reserved */
 509                         u8      rsvd_2;
 510                                 /* bit 319:288 - Notification Destination */
 511                         u32     ndst;
 512                 };
 513                 u64 control;
 514         };
 515         u32 rsvd[6];
 516 } __aligned(64);
 517
 518 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 519 {
 520         return test_and_set_bit(POSTED_INTR_ON,
 521                         (unsigned long *)&pi_desc->control);
 522 }
 523
 524 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 525 {
 526         return test_and_clear_bit(POSTED_INTR_ON,
 527                         (unsigned long *)&pi_desc->control);
 528 }
 529
 530 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 531 {
 532         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 533 }
 534
 535 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 536 {
 537         return clear_bit(POSTED_INTR_SN,
 538                         (unsigned long *)&pi_desc->control);
 539 }
 540
 541 static inline void pi_set_sn(struct pi_desc *pi_desc)
 542 {
 543         return set_bit(POSTED_INTR_SN,
 544                         (unsigned long *)&pi_desc->control);
 545 }
 546
 547 static inline void pi_clear_on(struct pi_desc *pi_desc)
 548 {
 549         clear_bit(POSTED_INTR_ON,
 550                   (unsigned long *)&pi_desc->control);
 551 }
 552
 553 static inline int pi_test_on(struct pi_desc *pi_desc)
 554 {
 555         return test_bit(POSTED_INTR_ON,
 556                         (unsigned long *)&pi_desc->control);
 557 }
 558
 559 static inline int pi_test_sn(struct pi_desc *pi_desc)
 560 {
 561         return test_bit(POSTED_INTR_SN,
 562                         (unsigned long *)&pi_desc->control);
 563 }
 564
 565 struct vcpu_vmx {
 566         struct kvm_vcpu       vcpu;
 567         unsigned long         host_rsp;
 568         u8                    fail;
 569         u32                   exit_intr_info;
 570         u32                   idt_vectoring_info;
 571         ulong                 rflags;
 572         struct shared_msr_entry *guest_msrs;
 573         int                   nmsrs;
 574         int                   save_nmsrs;
 575         unsigned long         host_idt_base;
 576 #ifdef CONFIG_X86_64
 577         u64                   msr_host_kernel_gs_base;
 578         u64                   msr_guest_kernel_gs_base;
 579 #endif
 580         u32 vm_entry_controls_shadow;
 581         u32 vm_exit_controls_shadow;
 582         u32 secondary_exec_control;
 583
 584         /*
 585          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 586          * non-nested (L1) guest, it always points to vmcs01. For a nested
 587          * guest (L2), it points to a different VMCS.
 588          */
 589         struct loaded_vmcs    vmcs01;
 590         struct loaded_vmcs   *loaded_vmcs;
 591         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 592         struct msr_autoload {
 593                 unsigned nr;
 594                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 595                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 596         } msr_autoload;
 597         struct {
 598                 int           loaded;
 599                 u16           fs_sel, gs_sel, ldt_sel;
 600 #ifdef CONFIG_X86_64
 601                 u16           ds_sel, es_sel;
 602 #endif
 603                 int           gs_ldt_reload_needed;
 604                 int           fs_reload_needed;
 605                 u64           msr_host_bndcfgs;
 606         } host_state;
 607         struct {
 608                 int vm86_active;
 609                 ulong save_rflags;
 610                 struct kvm_segment segs[8];
 611         } rmode;
 612         struct {
 613                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 614                 struct kvm_save_segment {
 615                         u16 selector;
 616                         unsigned long base;
 617                         u32 limit;
 618                         u32 ar;
 619                 } seg[8];
 620         } segment_cache;
 621         int vpid;
 622         bool emulation_required;
 623
 624         u32 exit_reason;
 625
 626         /* Posted interrupt descriptor */
 627         struct pi_desc pi_desc;
 628
 629         /* Support for a guest hypervisor (nested VMX) */
 630         struct nested_vmx nested;
 631
 632         /* Dynamic PLE window. */
 633         int ple_window;
 634         bool ple_window_dirty;
 635
 636         /* Support for PML */
 637 #define PML_ENTITY_NUM          512
 638         struct page *pml_pg;
 639
 640         /* apic deadline value in host tsc */
 641         u64 hv_deadline_tsc;
 642
 643         u64 current_tsc_ratio;
 644
 645         u32 host_pkru;
 646
 647         /*
 648          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 649          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 650          * in msr_ia32_feature_control_valid_bits.
 651          */
 652         u64 msr_ia32_feature_control;
 653         u64 msr_ia32_feature_control_valid_bits;
 654 };
 655
 656 enum segment_cache_field {
 657         SEG_FIELD_SEL = 0,
 658         SEG_FIELD_BASE = 1,
 659         SEG_FIELD_LIMIT = 2,
 660         SEG_FIELD_AR = 3,
 661
 662         SEG_FIELD_NR = 4
 663 };
 664
 665 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 666 {
 667         return container_of(vcpu, struct vcpu_vmx, vcpu);
 668 }
 669
 670 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 671 {
 672         return &(to_vmx(vcpu)->pi_desc);
 673 }
 674
 675 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 676 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 677 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 678                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 679
 680
 681 static unsigned long shadow_read_only_fields[] = {
 682         /*
 683          * We do NOT shadow fields that are modified when L0
 684          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 685          * VMXON...) executed by L1.
 686          * For example, VM_INSTRUCTION_ERROR is read
 687          * by L1 if a vmx instruction fails (part of the error path).
 688          * Note the code assumes this logic. If for some reason
 689          * we start shadowing these fields then we need to
 690          * force a shadow sync when L0 emulates vmx instructions
 691          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 692          * by nested_vmx_failValid)
 693          */
 694         VM_EXIT_REASON,
 695         VM_EXIT_INTR_INFO,
 696         VM_EXIT_INSTRUCTION_LEN,
 697         IDT_VECTORING_INFO_FIELD,
 698         IDT_VECTORING_ERROR_CODE,
 699         VM_EXIT_INTR_ERROR_CODE,
 700         EXIT_QUALIFICATION,
 701         GUEST_LINEAR_ADDRESS,
 702         GUEST_PHYSICAL_ADDRESS
 703 };
 704 static int max_shadow_read_only_fields =
 705         ARRAY_SIZE(shadow_read_only_fields);
 706
 707 static unsigned long shadow_read_write_fields[] = {
 708         TPR_THRESHOLD,
 709         GUEST_RIP,
 710         GUEST_RSP,
 711         GUEST_CR0,
 712         GUEST_CR3,
 713         GUEST_CR4,
 714         GUEST_INTERRUPTIBILITY_INFO,
 715         GUEST_RFLAGS,
 716         GUEST_CS_SELECTOR,
 717         GUEST_CS_AR_BYTES,
 718         GUEST_CS_LIMIT,
 719         GUEST_CS_BASE,
 720         GUEST_ES_BASE,
 721         GUEST_BNDCFGS,
 722         CR0_GUEST_HOST_MASK,
 723         CR0_READ_SHADOW,
 724         CR4_READ_SHADOW,
 725         TSC_OFFSET,
 726         EXCEPTION_BITMAP,
 727         CPU_BASED_VM_EXEC_CONTROL,
 728         VM_ENTRY_EXCEPTION_ERROR_CODE,
 729         VM_ENTRY_INTR_INFO_FIELD,
 730         VM_ENTRY_INSTRUCTION_LEN,
 731         VM_ENTRY_EXCEPTION_ERROR_CODE,
 732         HOST_FS_BASE,
 733         HOST_GS_BASE,
 734         HOST_FS_SELECTOR,
 735         HOST_GS_SELECTOR
 736 };
 737 static int max_shadow_read_write_fields =
 738         ARRAY_SIZE(shadow_read_write_fields);
 739
 740 static const unsigned short vmcs_field_to_offset_table[] = {
 741         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 742         FIELD(POSTED_INTR_NV, posted_intr_nv),
 743         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 744         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 745         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 746         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 747         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 748         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 749         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 750         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 751         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 752         FIELD(GUEST_PML_INDEX, guest_pml_index),
 753         FIELD(HOST_ES_SELECTOR, host_es_selector),
 754         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 755         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 756         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 757         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 758         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 759         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 760         FIELD64(IO_BITMAP_A, io_bitmap_a),
 761         FIELD64(IO_BITMAP_B, io_bitmap_b),
 762         FIELD64(MSR_BITMAP, msr_bitmap),
 763         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 764         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 765         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 766         FIELD64(TSC_OFFSET, tsc_offset),
 767         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 768         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 769         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 770         FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
 771         FIELD64(EPT_POINTER, ept_pointer),
 772         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 773         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 774         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 775         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 776         FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
 777         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 778         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 779         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 780         FIELD64(PML_ADDRESS, pml_address),
 781         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 782         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 783         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 784         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 785         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 786         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 787         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 788         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 789         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 790         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 791         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 792         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 793         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 794         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 795         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 796         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 797         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 798         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 799         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 800         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 801         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 802         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 803         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 804         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 805         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 806         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 807         FIELD(TPR_THRESHOLD, tpr_threshold),
 808         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 809         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 810         FIELD(VM_EXIT_REASON, vm_exit_reason),
 811         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 812         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 813         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 814         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 815         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 816         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 817         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 818         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 819         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 820         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 821         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 822         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 823         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 824         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 825         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 826         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 827         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 828         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 829         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 830         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 831         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 832         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 833         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 834         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 835         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 836         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 837         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 838         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 839         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 840         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 841         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 842         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 843         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 844         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 845         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 846         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 847         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 848         FIELD(EXIT_QUALIFICATION, exit_qualification),
 849         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 850         FIELD(GUEST_CR0, guest_cr0),
 851         FIELD(GUEST_CR3, guest_cr3),
 852         FIELD(GUEST_CR4, guest_cr4),
 853         FIELD(GUEST_ES_BASE, guest_es_base),
 854         FIELD(GUEST_CS_BASE, guest_cs_base),
 855         FIELD(GUEST_SS_BASE, guest_ss_base),
 856         FIELD(GUEST_DS_BASE, guest_ds_base),
 857         FIELD(GUEST_FS_BASE, guest_fs_base),
 858         FIELD(GUEST_GS_BASE, guest_gs_base),
 859         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 860         FIELD(GUEST_TR_BASE, guest_tr_base),
 861         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 862         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 863         FIELD(GUEST_DR7, guest_dr7),
 864         FIELD(GUEST_RSP, guest_rsp),
 865         FIELD(GUEST_RIP, guest_rip),
 866         FIELD(GUEST_RFLAGS, guest_rflags),
 867         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 868         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 869         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 870         FIELD(HOST_CR0, host_cr0),
 871         FIELD(HOST_CR3, host_cr3),
 872         FIELD(HOST_CR4, host_cr4),
 873         FIELD(HOST_FS_BASE, host_fs_base),
 874         FIELD(HOST_GS_BASE, host_gs_base),
 875         FIELD(HOST_TR_BASE, host_tr_base),
 876         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 877         FIELD(HOST_IDTR_BASE, host_idtr_base),
 878         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 879         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 880         FIELD(HOST_RSP, host_rsp),
 881         FIELD(HOST_RIP, host_rip),
 882 };
 883
 884 static inline short vmcs_field_to_offset(unsigned long field)
 885 {
 886         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 887
 888         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 889             vmcs_field_to_offset_table[field] == 0)
 890                 return -ENOENT;
 891
 892         return vmcs_field_to_offset_table[field];
 893 }
 894
 895 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 896 {
 897         return to_vmx(vcpu)->nested.cached_vmcs12;
 898 }
 899
 900 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
 901 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 902 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 903 static bool vmx_xsaves_supported(void);
 904 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 905 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 906                             struct kvm_segment *var, int seg);
 907 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 908                             struct kvm_segment *var, int seg);
 909 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 910 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 911 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 912 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 913 static int alloc_identity_pagetable(struct kvm *kvm);
 914 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
 915 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
 916 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
 917                                             u16 error_code);
 918
 919 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 920 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 921 /*
 922  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 923  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 924  */
 925 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 926
 927 /*
 928  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 929  * can find which vCPU should be waken up.
 930  */
 931 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 932 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 933
 934 enum {
 935         VMX_IO_BITMAP_A,
 936         VMX_IO_BITMAP_B,
 937         VMX_MSR_BITMAP_LEGACY,
 938         VMX_MSR_BITMAP_LONGMODE,
 939         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 940         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 941         VMX_MSR_BITMAP_LEGACY_X2APIC,
 942         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 943         VMX_VMREAD_BITMAP,
 944         VMX_VMWRITE_BITMAP,
 945         VMX_BITMAP_NR
 946 };
 947
 948 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 949
 950 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 951 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 952 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 953 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 954 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 955 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 956 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 957 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 958 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 959 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 960
 961 static bool cpu_has_load_ia32_efer;
 962 static bool cpu_has_load_perf_global_ctrl;
 963
 964 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 965 static DEFINE_SPINLOCK(vmx_vpid_lock);
 966
 967 static struct vmcs_config {
 968         int size;
 969         int order;
 970         u32 basic_cap;
 971         u32 revision_id;
 972         u32 pin_based_exec_ctrl;
 973         u32 cpu_based_exec_ctrl;
 974         u32 cpu_based_2nd_exec_ctrl;
 975         u32 vmexit_ctrl;
 976         u32 vmentry_ctrl;
 977 } vmcs_config;
 978
 979 static struct vmx_capability {
 980         u32 ept;
 981         u32 vpid;
 982 } vmx_capability;
 983
 984 #define VMX_SEGMENT_FIELD(seg)                                  \
 985         [VCPU_SREG_##seg] = {                                   \
 986                 .selector = GUEST_##seg##_SELECTOR,             \
 987                 .base = GUEST_##seg##_BASE,                     \
 988                 .limit = GUEST_##seg##_LIMIT,                   \
 989                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 990         }
 991
 992 static const struct kvm_vmx_segment_field {
 993         unsigned selector;
 994         unsigned base;
 995         unsigned limit;
 996         unsigned ar_bytes;
 997 } kvm_vmx_segment_fields[] = {
 998         VMX_SEGMENT_FIELD(CS),
 999         VMX_SEGMENT_FIELD(DS),
1000         VMX_SEGMENT_FIELD(ES),
1001         VMX_SEGMENT_FIELD(FS),
1002         VMX_SEGMENT_FIELD(GS),
1003         VMX_SEGMENT_FIELD(SS),
1004         VMX_SEGMENT_FIELD(TR),
1005         VMX_SEGMENT_FIELD(LDTR),
1006 };
1007
1008 static u64 host_efer;
1009
1010 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1011
1012 /*
1013  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1014  * away by decrementing the array size.
1015  */
1016 static const u32 vmx_msr_index[] = {
1017 #ifdef CONFIG_X86_64
1018         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1019 #endif
1020         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1021 };
1022
1023 static inline bool is_exception_n(u32 intr_info, u8 vector)
1024 {
1025         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1026                              INTR_INFO_VALID_MASK)) ==
1027                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1028 }
1029
1030 static inline bool is_debug(u32 intr_info)
1031 {
1032         return is_exception_n(intr_info, DB_VECTOR);
1033 }
1034
1035 static inline bool is_breakpoint(u32 intr_info)
1036 {
1037         return is_exception_n(intr_info, BP_VECTOR);
1038 }
1039
1040 static inline bool is_page_fault(u32 intr_info)
1041 {
1042         return is_exception_n(intr_info, PF_VECTOR);
1043 }
1044
1045 static inline bool is_no_device(u32 intr_info)
1046 {
1047         return is_exception_n(intr_info, NM_VECTOR);
1048 }
1049
1050 static inline bool is_invalid_opcode(u32 intr_info)
1051 {
1052         return is_exception_n(intr_info, UD_VECTOR);
1053 }
1054
1055 static inline bool is_external_interrupt(u32 intr_info)
1056 {
1057         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1058                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1059 }
1060
1061 static inline bool is_machine_check(u32 intr_info)
1062 {
1063         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1064                              INTR_INFO_VALID_MASK)) ==
1065                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1066 }
1067
1068 static inline bool cpu_has_vmx_msr_bitmap(void)
1069 {
1070         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1071 }
1072
1073 static inline bool cpu_has_vmx_tpr_shadow(void)
1074 {
1075         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1076 }
1077
1078 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1079 {
1080         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1081 }
1082
1083 static inline bool cpu_has_secondary_exec_ctrls(void)
1084 {
1085         return vmcs_config.cpu_based_exec_ctrl &
1086                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1087 }
1088
1089 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1090 {
1091         return vmcs_config.cpu_based_2nd_exec_ctrl &
1092                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1093 }
1094
1095 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1096 {
1097         return vmcs_config.cpu_based_2nd_exec_ctrl &
1098                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1099 }
1100
1101 static inline bool cpu_has_vmx_apic_register_virt(void)
1102 {
1103         return vmcs_config.cpu_based_2nd_exec_ctrl &
1104                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1105 }
1106
1107 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1108 {
1109         return vmcs_config.cpu_based_2nd_exec_ctrl &
1110                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1111 }
1112
1113 /*
1114  * Comment's format: document - errata name - stepping - processor name.
1115  * Refer from
1116  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1117  */
1118 static u32 vmx_preemption_cpu_tfms[] = {
1119 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1120 0x000206E6,
1121 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1122 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1123 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1124 0x00020652,
1125 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1126 0x00020655,
1127 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1128 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1129 /*
1130  * 320767.pdf - AAP86  - B1 -
1131  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1132  */
1133 0x000106E5,
1134 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1135 0x000106A0,
1136 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1137 0x000106A1,
1138 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1139 0x000106A4,
1140  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1141  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1142  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1143 0x000106A5,
1144 };
1145
1146 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1147 {
1148         u32 eax = cpuid_eax(0x00000001), i;
1149
1150         /* Clear the reserved bits */
1151         eax &= ~(0x3U << 14 | 0xfU << 28);
1152         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1153                 if (eax == vmx_preemption_cpu_tfms[i])
1154                         return true;
1155
1156         return false;
1157 }
1158
1159 static inline bool cpu_has_vmx_preemption_timer(void)
1160 {
1161         return vmcs_config.pin_based_exec_ctrl &
1162                 PIN_BASED_VMX_PREEMPTION_TIMER;
1163 }
1164
1165 static inline bool cpu_has_vmx_posted_intr(void)
1166 {
1167         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1168                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1169 }
1170
1171 static inline bool cpu_has_vmx_apicv(void)
1172 {
1173         return cpu_has_vmx_apic_register_virt() &&
1174                 cpu_has_vmx_virtual_intr_delivery() &&
1175                 cpu_has_vmx_posted_intr();
1176 }
1177
1178 static inline bool cpu_has_vmx_flexpriority(void)
1179 {
1180         return cpu_has_vmx_tpr_shadow() &&
1181                 cpu_has_vmx_virtualize_apic_accesses();
1182 }
1183
1184 static inline bool cpu_has_vmx_ept_execute_only(void)
1185 {
1186         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1187 }
1188
1189 static inline bool cpu_has_vmx_ept_2m_page(void)
1190 {
1191         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1192 }
1193
1194 static inline bool cpu_has_vmx_ept_1g_page(void)
1195 {
1196         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1197 }
1198
1199 static inline bool cpu_has_vmx_ept_4levels(void)
1200 {
1201         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1202 }
1203
1204 static inline bool cpu_has_vmx_ept_mt_wb(void)
1205 {
1206         return vmx_capability.ept & VMX_EPTP_WB_BIT;
1207 }
1208
1209 static inline bool cpu_has_vmx_ept_5levels(void)
1210 {
1211         return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1212 }
1213
1214 static inline bool cpu_has_vmx_ept_ad_bits(void)
1215 {
1216         return vmx_capability.ept & VMX_EPT_AD_BIT;
1217 }
1218
1219 static inline bool cpu_has_vmx_invept_context(void)
1220 {
1221         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1222 }
1223
1224 static inline bool cpu_has_vmx_invept_global(void)
1225 {
1226         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1227 }
1228
1229 static inline bool cpu_has_vmx_invvpid_single(void)
1230 {
1231         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1232 }
1233
1234 static inline bool cpu_has_vmx_invvpid_global(void)
1235 {
1236         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1237 }
1238
1239 static inline bool cpu_has_vmx_invvpid(void)
1240 {
1241         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1242 }
1243
1244 static inline bool cpu_has_vmx_ept(void)
1245 {
1246         return vmcs_config.cpu_based_2nd_exec_ctrl &
1247                 SECONDARY_EXEC_ENABLE_EPT;
1248 }
1249
1250 static inline bool cpu_has_vmx_unrestricted_guest(void)
1251 {
1252         return vmcs_config.cpu_based_2nd_exec_ctrl &
1253                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1254 }
1255
1256 static inline bool cpu_has_vmx_ple(void)
1257 {
1258         return vmcs_config.cpu_based_2nd_exec_ctrl &
1259                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1260 }
1261
1262 static inline bool cpu_has_vmx_basic_inout(void)
1263 {
1264         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1265 }
1266
1267 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1268 {
1269         return flexpriority_enabled && lapic_in_kernel(vcpu);
1270 }
1271
1272 static inline bool cpu_has_vmx_vpid(void)
1273 {
1274         return vmcs_config.cpu_based_2nd_exec_ctrl &
1275                 SECONDARY_EXEC_ENABLE_VPID;
1276 }
1277
1278 static inline bool cpu_has_vmx_rdtscp(void)
1279 {
1280         return vmcs_config.cpu_based_2nd_exec_ctrl &
1281                 SECONDARY_EXEC_RDTSCP;
1282 }
1283
1284 static inline bool cpu_has_vmx_invpcid(void)
1285 {
1286         return vmcs_config.cpu_based_2nd_exec_ctrl &
1287                 SECONDARY_EXEC_ENABLE_INVPCID;
1288 }
1289
1290 static inline bool cpu_has_vmx_wbinvd_exit(void)
1291 {
1292         return vmcs_config.cpu_based_2nd_exec_ctrl &
1293                 SECONDARY_EXEC_WBINVD_EXITING;
1294 }
1295
1296 static inline bool cpu_has_vmx_shadow_vmcs(void)
1297 {
1298         u64 vmx_msr;
1299         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1300         /* check if the cpu supports writing r/o exit information fields */
1301         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1302                 return false;
1303
1304         return vmcs_config.cpu_based_2nd_exec_ctrl &
1305                 SECONDARY_EXEC_SHADOW_VMCS;
1306 }
1307
1308 static inline bool cpu_has_vmx_pml(void)
1309 {
1310         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1311 }
1312
1313 static inline bool cpu_has_vmx_tsc_scaling(void)
1314 {
1315         return vmcs_config.cpu_based_2nd_exec_ctrl &
1316                 SECONDARY_EXEC_TSC_SCALING;
1317 }
1318
1319 static inline bool cpu_has_vmx_vmfunc(void)
1320 {
1321         return vmcs_config.cpu_based_2nd_exec_ctrl &
1322                 SECONDARY_EXEC_ENABLE_VMFUNC;
1323 }
1324
1325 static inline bool report_flexpriority(void)
1326 {
1327         return flexpriority_enabled;
1328 }
1329
1330 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1331 {
1332         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1333 }
1334
1335 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1336 {
1337         return vmcs12->cpu_based_vm_exec_control & bit;
1338 }
1339
1340 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1341 {
1342         return (vmcs12->cpu_based_vm_exec_control &
1343                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1344                 (vmcs12->secondary_vm_exec_control & bit);
1345 }
1346
1347 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1348 {
1349         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1350 }
1351
1352 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1353 {
1354         return vmcs12->pin_based_vm_exec_control &
1355                 PIN_BASED_VMX_PREEMPTION_TIMER;
1356 }
1357
1358 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1359 {
1360         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1361 }
1362
1363 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1364 {
1365         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
1366 }
1367
1368 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1369 {
1370         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1371 }
1372
1373 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1374 {
1375         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1376 }
1377
1378 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1379 {
1380         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1381 }
1382
1383 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1384 {
1385         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1386 }
1387
1388 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1389 {
1390         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1391 }
1392
1393 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1394 {
1395         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1396 }
1397
1398 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1399 {
1400         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1401 }
1402
1403 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1404 {
1405         return nested_cpu_has_vmfunc(vmcs12) &&
1406                 (vmcs12->vm_function_control &
1407                  VMX_VMFUNC_EPTP_SWITCHING);
1408 }
1409
1410 static inline bool is_nmi(u32 intr_info)
1411 {
1412         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1413                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1414 }
1415
1416 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1417                               u32 exit_intr_info,
1418                               unsigned long exit_qualification);
1419 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1420                         struct vmcs12 *vmcs12,
1421                         u32 reason, unsigned long qualification);
1422
1423 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1424 {
1425         int i;
1426
1427         for (i = 0; i < vmx->nmsrs; ++i)
1428                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1429                         return i;
1430         return -1;
1431 }
1432
1433 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1434 {
1435     struct {
1436         u64 vpid : 16;
1437         u64 rsvd : 48;
1438         u64 gva;
1439     } operand = { vpid, 0, gva };
1440
1441     asm volatile (__ex(ASM_VMX_INVVPID)
1442                   /* CF==1 or ZF==1 --> rc = -1 */
1443                   "; ja 1f ; ud2 ; 1:"
1444                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1445 }
1446
1447 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1448 {
1449         struct {
1450                 u64 eptp, gpa;
1451         } operand = {eptp, gpa};
1452
1453         asm volatile (__ex(ASM_VMX_INVEPT)
1454                         /* CF==1 or ZF==1 --> rc = -1 */
1455                         "; ja 1f ; ud2 ; 1:\n"
1456                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1457 }
1458
1459 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1460 {
1461         int i;
1462
1463         i = __find_msr_index(vmx, msr);
1464         if (i >= 0)
1465                 return &vmx->guest_msrs[i];
1466         return NULL;
1467 }
1468
1469 static void vmcs_clear(struct vmcs *vmcs)
1470 {
1471         u64 phys_addr = __pa(vmcs);
1472         u8 error;
1473
1474         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1475                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1476                       : "cc", "memory");
1477         if (error)
1478                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1479                        vmcs, phys_addr);
1480 }
1481
1482 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1483 {
1484         vmcs_clear(loaded_vmcs->vmcs);
1485         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1486                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1487         loaded_vmcs->cpu = -1;
1488         loaded_vmcs->launched = 0;
1489 }
1490
1491 static void vmcs_load(struct vmcs *vmcs)
1492 {
1493         u64 phys_addr = __pa(vmcs);
1494         u8 error;
1495
1496         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1497                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1498                         : "cc", "memory");
1499         if (error)
1500                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1501                        vmcs, phys_addr);
1502 }
1503
1504 #ifdef CONFIG_KEXEC_CORE
1505 /*
1506  * This bitmap is used to indicate whether the vmclear
1507  * operation is enabled on all cpus. All disabled by
1508  * default.
1509  */
1510 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1511
1512 static inline void crash_enable_local_vmclear(int cpu)
1513 {
1514         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1515 }
1516
1517 static inline void crash_disable_local_vmclear(int cpu)
1518 {
1519         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1520 }
1521
1522 static inline int crash_local_vmclear_enabled(int cpu)
1523 {
1524         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1525 }
1526
1527 static void crash_vmclear_local_loaded_vmcss(void)
1528 {
1529         int cpu = raw_smp_processor_id();
1530         struct loaded_vmcs *v;
1531
1532         if (!crash_local_vmclear_enabled(cpu))
1533                 return;
1534
1535         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1536                             loaded_vmcss_on_cpu_link)
1537                 vmcs_clear(v->vmcs);
1538 }
1539 #else
1540 static inline void crash_enable_local_vmclear(int cpu) { }
1541 static inline void crash_disable_local_vmclear(int cpu) { }
1542 #endif /* CONFIG_KEXEC_CORE */
1543
1544 static void __loaded_vmcs_clear(void *arg)
1545 {
1546         struct loaded_vmcs *loaded_vmcs = arg;
1547         int cpu = raw_smp_processor_id();
1548
1549         if (loaded_vmcs->cpu != cpu)
1550                 return; /* vcpu migration can race with cpu offline */
1551         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1552                 per_cpu(current_vmcs, cpu) = NULL;
1553         crash_disable_local_vmclear(cpu);
1554         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1555
1556         /*
1557          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1558          * is before setting loaded_vmcs->vcpu to -1 which is done in
1559          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1560          * then adds the vmcs into percpu list before it is deleted.
1561          */
1562         smp_wmb();
1563
1564         loaded_vmcs_init(loaded_vmcs);
1565         crash_enable_local_vmclear(cpu);
1566 }
1567
1568 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1569 {
1570         int cpu = loaded_vmcs->cpu;
1571
1572         if (cpu != -1)
1573                 smp_call_function_single(cpu,
1574                          __loaded_vmcs_clear, loaded_vmcs, 1);
1575 }
1576
1577 static inline void vpid_sync_vcpu_single(int vpid)
1578 {
1579         if (vpid == 0)
1580                 return;
1581
1582         if (cpu_has_vmx_invvpid_single())
1583                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1584 }
1585
1586 static inline void vpid_sync_vcpu_global(void)
1587 {
1588         if (cpu_has_vmx_invvpid_global())
1589                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1590 }
1591
1592 static inline void vpid_sync_context(int vpid)
1593 {
1594         if (cpu_has_vmx_invvpid_single())
1595                 vpid_sync_vcpu_single(vpid);
1596         else
1597                 vpid_sync_vcpu_global();
1598 }
1599
1600 static inline void ept_sync_global(void)
1601 {
1602         if (cpu_has_vmx_invept_global())
1603                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1604 }
1605
1606 static inline void ept_sync_context(u64 eptp)
1607 {
1608         if (enable_ept) {
1609                 if (cpu_has_vmx_invept_context())
1610                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1611                 else
1612                         ept_sync_global();
1613         }
1614 }
1615
1616 static __always_inline void vmcs_check16(unsigned long field)
1617 {
1618         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1619                          "16-bit accessor invalid for 64-bit field");
1620         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1621                          "16-bit accessor invalid for 64-bit high field");
1622         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1623                          "16-bit accessor invalid for 32-bit high field");
1624         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1625                          "16-bit accessor invalid for natural width field");
1626 }
1627
1628 static __always_inline void vmcs_check32(unsigned long field)
1629 {
1630         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1631                          "32-bit accessor invalid for 16-bit field");
1632         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1633                          "32-bit accessor invalid for natural width field");
1634 }
1635
1636 static __always_inline void vmcs_check64(unsigned long field)
1637 {
1638         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1639                          "64-bit accessor invalid for 16-bit field");
1640         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1641                          "64-bit accessor invalid for 64-bit high field");
1642         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1643                          "64-bit accessor invalid for 32-bit field");
1644         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1645                          "64-bit accessor invalid for natural width field");
1646 }
1647
1648 static __always_inline void vmcs_checkl(unsigned long field)
1649 {
1650         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1651                          "Natural width accessor invalid for 16-bit field");
1652         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1653                          "Natural width accessor invalid for 64-bit field");
1654         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1655                          "Natural width accessor invalid for 64-bit high field");
1656         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1657                          "Natural width accessor invalid for 32-bit field");
1658 }
1659
1660 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1661 {
1662         unsigned long value;
1663
1664         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1665                       : "=a"(value) : "d"(field) : "cc");
1666         return value;
1667 }
1668
1669 static __always_inline u16 vmcs_read16(unsigned long field)
1670 {
1671         vmcs_check16(field);
1672         return __vmcs_readl(field);
1673 }
1674
1675 static __always_inline u32 vmcs_read32(unsigned long field)
1676 {
1677         vmcs_check32(field);
1678         return __vmcs_readl(field);
1679 }
1680
1681 static __always_inline u64 vmcs_read64(unsigned long field)
1682 {
1683         vmcs_check64(field);
1684 #ifdef CONFIG_X86_64
1685         return __vmcs_readl(field);
1686 #else
1687         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1688 #endif
1689 }
1690
1691 static __always_inline unsigned long vmcs_readl(unsigned long field)
1692 {
1693         vmcs_checkl(field);
1694         return __vmcs_readl(field);
1695 }
1696
1697 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1698 {
1699         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1700                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1701         dump_stack();
1702 }
1703
1704 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1705 {
1706         u8 error;
1707
1708         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1709                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1710         if (unlikely(error))
1711                 vmwrite_error(field, value);
1712 }
1713
1714 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1715 {
1716         vmcs_check16(field);
1717         __vmcs_writel(field, value);
1718 }
1719
1720 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1721 {
1722         vmcs_check32(field);
1723         __vmcs_writel(field, value);
1724 }
1725
1726 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1727 {
1728         vmcs_check64(field);
1729         __vmcs_writel(field, value);
1730 #ifndef CONFIG_X86_64
1731         asm volatile ("");
1732         __vmcs_writel(field+1, value >> 32);
1733 #endif
1734 }
1735
1736 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1737 {
1738         vmcs_checkl(field);
1739         __vmcs_writel(field, value);
1740 }
1741
1742 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1743 {
1744         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1745                          "vmcs_clear_bits does not support 64-bit fields");
1746         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1747 }
1748
1749 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1750 {
1751         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1752                          "vmcs_set_bits does not support 64-bit fields");
1753         __vmcs_writel(field, __vmcs_readl(field) | mask);
1754 }
1755
1756 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1757 {
1758         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1759 }
1760
1761 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1762 {
1763         vmcs_write32(VM_ENTRY_CONTROLS, val);
1764         vmx->vm_entry_controls_shadow = val;
1765 }
1766
1767 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1768 {
1769         if (vmx->vm_entry_controls_shadow != val)
1770                 vm_entry_controls_init(vmx, val);
1771 }
1772
1773 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1774 {
1775         return vmx->vm_entry_controls_shadow;
1776 }
1777
1778
1779 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1780 {
1781         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1782 }
1783
1784 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1785 {
1786         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1787 }
1788
1789 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1790 {
1791         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1792 }
1793
1794 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1795 {
1796         vmcs_write32(VM_EXIT_CONTROLS, val);
1797         vmx->vm_exit_controls_shadow = val;
1798 }
1799
1800 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1801 {
1802         if (vmx->vm_exit_controls_shadow != val)
1803                 vm_exit_controls_init(vmx, val);
1804 }
1805
1806 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1807 {
1808         return vmx->vm_exit_controls_shadow;
1809 }
1810
1811
1812 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1813 {
1814         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1815 }
1816
1817 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1818 {
1819         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1820 }
1821
1822 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1823 {
1824         vmx->segment_cache.bitmask = 0;
1825 }
1826
1827 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1828                                        unsigned field)
1829 {
1830         bool ret;
1831         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1832
1833         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1834                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1835                 vmx->segment_cache.bitmask = 0;
1836         }
1837         ret = vmx->segment_cache.bitmask & mask;
1838         vmx->segment_cache.bitmask |= mask;
1839         return ret;
1840 }
1841
1842 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1843 {
1844         u16 *p = &vmx->segment_cache.seg[seg].selector;
1845
1846         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1847                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1848         return *p;
1849 }
1850
1851 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1852 {
1853         ulong *p = &vmx->segment_cache.seg[seg].base;
1854
1855         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1856                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1857         return *p;
1858 }
1859
1860 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1861 {
1862         u32 *p = &vmx->segment_cache.seg[seg].limit;
1863
1864         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1865                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1866         return *p;
1867 }
1868
1869 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1870 {
1871         u32 *p = &vmx->segment_cache.seg[seg].ar;
1872
1873         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1874                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1875         return *p;
1876 }
1877
1878 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1879 {
1880         u32 eb;
1881
1882         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1883              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1884         if ((vcpu->guest_debug &
1885              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1886             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1887                 eb |= 1u << BP_VECTOR;
1888         if (to_vmx(vcpu)->rmode.vm86_active)
1889                 eb = ~0;
1890         if (enable_ept)
1891                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1892
1893         /* When we are running a nested L2 guest and L1 specified for it a
1894          * certain exception bitmap, we must trap the same exceptions and pass
1895          * them to L1. When running L2, we will only handle the exceptions
1896          * specified above if L1 did not want them.
1897          */
1898         if (is_guest_mode(vcpu))
1899                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1900
1901         vmcs_write32(EXCEPTION_BITMAP, eb);
1902 }
1903
1904 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1905                 unsigned long entry, unsigned long exit)
1906 {
1907         vm_entry_controls_clearbit(vmx, entry);
1908         vm_exit_controls_clearbit(vmx, exit);
1909 }
1910
1911 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1912 {
1913         unsigned i;
1914         struct msr_autoload *m = &vmx->msr_autoload;
1915
1916         switch (msr) {
1917         case MSR_EFER:
1918                 if (cpu_has_load_ia32_efer) {
1919                         clear_atomic_switch_msr_special(vmx,
1920                                         VM_ENTRY_LOAD_IA32_EFER,
1921                                         VM_EXIT_LOAD_IA32_EFER);
1922                         return;
1923                 }
1924                 break;
1925         case MSR_CORE_PERF_GLOBAL_CTRL:
1926                 if (cpu_has_load_perf_global_ctrl) {
1927                         clear_atomic_switch_msr_special(vmx,
1928                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1929                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1930                         return;
1931                 }
1932                 break;
1933         }
1934
1935         for (i = 0; i < m->nr; ++i)
1936                 if (m->guest[i].index == msr)
1937                         break;
1938
1939         if (i == m->nr)
1940                 return;
1941         --m->nr;
1942         m->guest[i] = m->guest[m->nr];
1943         m->host[i] = m->host[m->nr];
1944         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1945         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1946 }
1947
1948 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1949                 unsigned long entry, unsigned long exit,
1950                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1951                 u64 guest_val, u64 host_val)
1952 {
1953         vmcs_write64(guest_val_vmcs, guest_val);
1954         vmcs_write64(host_val_vmcs, host_val);
1955         vm_entry_controls_setbit(vmx, entry);
1956         vm_exit_controls_setbit(vmx, exit);
1957 }
1958
1959 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1960                                   u64 guest_val, u64 host_val)
1961 {
1962         unsigned i;
1963         struct msr_autoload *m = &vmx->msr_autoload;
1964
1965         switch (msr) {
1966         case MSR_EFER:
1967                 if (cpu_has_load_ia32_efer) {
1968                         add_atomic_switch_msr_special(vmx,
1969                                         VM_ENTRY_LOAD_IA32_EFER,
1970                                         VM_EXIT_LOAD_IA32_EFER,
1971                                         GUEST_IA32_EFER,
1972                                         HOST_IA32_EFER,
1973                                         guest_val, host_val);
1974                         return;
1975                 }
1976                 break;
1977         case MSR_CORE_PERF_GLOBAL_CTRL:
1978                 if (cpu_has_load_perf_global_ctrl) {
1979                         add_atomic_switch_msr_special(vmx,
1980                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1981                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1982                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1983                                         HOST_IA32_PERF_GLOBAL_CTRL,
1984                                         guest_val, host_val);
1985                         return;
1986                 }
1987                 break;
1988         case MSR_IA32_PEBS_ENABLE:
1989                 /* PEBS needs a quiescent period after being disabled (to write
1990                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1991                  * provide that period, so a CPU could write host's record into
1992                  * guest's memory.
1993                  */
1994                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1995         }
1996
1997         for (i = 0; i < m->nr; ++i)
1998                 if (m->guest[i].index == msr)
1999                         break;
2000
2001         if (i == NR_AUTOLOAD_MSRS) {
2002                 printk_once(KERN_WARNING "Not enough msr switch entries. "
2003                                 "Can't add msr %x\n", msr);
2004                 return;
2005         } else if (i == m->nr) {
2006                 ++m->nr;
2007                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2008                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2009         }
2010
2011         m->guest[i].index = msr;
2012         m->guest[i].value = guest_val;
2013         m->host[i].index = msr;
2014         m->host[i].value = host_val;
2015 }
2016
2017 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2018 {
2019         u64 guest_efer = vmx->vcpu.arch.efer;
2020         u64 ignore_bits = 0;
2021
2022         if (!enable_ept) {
2023                 /*
2024                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2025                  * host CPUID is more efficient than testing guest CPUID
2026                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2027                  */
2028                 if (boot_cpu_has(X86_FEATURE_SMEP))
2029                         guest_efer |= EFER_NX;
2030                 else if (!(guest_efer & EFER_NX))
2031                         ignore_bits |= EFER_NX;
2032         }
2033
2034         /*
2035          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2036          */
2037         ignore_bits |= EFER_SCE;
2038 #ifdef CONFIG_X86_64
2039         ignore_bits |= EFER_LMA | EFER_LME;
2040         /* SCE is meaningful only in long mode on Intel */
2041         if (guest_efer & EFER_LMA)
2042                 ignore_bits &= ~(u64)EFER_SCE;
2043 #endif
2044
2045         clear_atomic_switch_msr(vmx, MSR_EFER);
2046
2047         /*
2048          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2049          * On CPUs that support "load IA32_EFER", always switch EFER
2050          * atomically, since it's faster than switching it manually.
2051          */
2052         if (cpu_has_load_ia32_efer ||
2053             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2054                 if (!(guest_efer & EFER_LMA))
2055                         guest_efer &= ~EFER_LME;
2056                 if (guest_efer != host_efer)
2057                         add_atomic_switch_msr(vmx, MSR_EFER,
2058                                               guest_efer, host_efer);
2059                 return false;
2060         } else {
2061                 guest_efer &= ~ignore_bits;
2062                 guest_efer |= host_efer & ignore_bits;
2063
2064                 vmx->guest_msrs[efer_offset].data = guest_efer;
2065                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2066
2067                 return true;
2068         }
2069 }
2070
2071 #ifdef CONFIG_X86_32
2072 /*
2073  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2074  * VMCS rather than the segment table.  KVM uses this helper to figure
2075  * out the current bases to poke them into the VMCS before entry.
2076  */
2077 static unsigned long segment_base(u16 selector)
2078 {
2079         struct desc_struct *table;
2080         unsigned long v;
2081
2082         if (!(selector & ~SEGMENT_RPL_MASK))
2083                 return 0;
2084
2085         table = get_current_gdt_ro();
2086
2087         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2088                 u16 ldt_selector = kvm_read_ldt();
2089
2090                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2091                         return 0;
2092
2093                 table = (struct desc_struct *)segment_base(ldt_selector);
2094         }
2095         v = get_desc_base(&table[selector >> 3]);
2096         return v;
2097 }
2098 #endif
2099
2100 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2101 {
2102         struct vcpu_vmx *vmx = to_vmx(vcpu);
2103         int i;
2104
2105         if (vmx->host_state.loaded)
2106                 return;
2107
2108         vmx->host_state.loaded = 1;
2109         /*
2110          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2111          * allow segment selectors with cpl > 0 or ti == 1.
2112          */
2113         vmx->host_state.ldt_sel = kvm_read_ldt();
2114         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2115         savesegment(fs, vmx->host_state.fs_sel);
2116         if (!(vmx->host_state.fs_sel & 7)) {
2117                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2118                 vmx->host_state.fs_reload_needed = 0;
2119         } else {
2120                 vmcs_write16(HOST_FS_SELECTOR, 0);
2121                 vmx->host_state.fs_reload_needed = 1;
2122         }
2123         savesegment(gs, vmx->host_state.gs_sel);
2124         if (!(vmx->host_state.gs_sel & 7))
2125                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2126         else {
2127                 vmcs_write16(HOST_GS_SELECTOR, 0);
2128                 vmx->host_state.gs_ldt_reload_needed = 1;
2129         }
2130
2131 #ifdef CONFIG_X86_64
2132         savesegment(ds, vmx->host_state.ds_sel);
2133         savesegment(es, vmx->host_state.es_sel);
2134 #endif
2135
2136 #ifdef CONFIG_X86_64
2137         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2138         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2139 #else
2140         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2141         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2142 #endif
2143
2144 #ifdef CONFIG_X86_64
2145         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2146         if (is_long_mode(&vmx->vcpu))
2147                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2148 #endif
2149         if (boot_cpu_has(X86_FEATURE_MPX))
2150                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2151         for (i = 0; i < vmx->save_nmsrs; ++i)
2152                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2153                                    vmx->guest_msrs[i].data,
2154                                    vmx->guest_msrs[i].mask);
2155 }
2156
2157 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2158 {
2159         if (!vmx->host_state.loaded)
2160                 return;
2161
2162         ++vmx->vcpu.stat.host_state_reload;
2163         vmx->host_state.loaded = 0;
2164 #ifdef CONFIG_X86_64
2165         if (is_long_mode(&vmx->vcpu))
2166                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2167 #endif
2168         if (vmx->host_state.gs_ldt_reload_needed) {
2169                 kvm_load_ldt(vmx->host_state.ldt_sel);
2170 #ifdef CONFIG_X86_64
2171                 load_gs_index(vmx->host_state.gs_sel);
2172 #else
2173                 loadsegment(gs, vmx->host_state.gs_sel);
2174 #endif
2175         }
2176         if (vmx->host_state.fs_reload_needed)
2177                 loadsegment(fs, vmx->host_state.fs_sel);
2178 #ifdef CONFIG_X86_64
2179         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2180                 loadsegment(ds, vmx->host_state.ds_sel);
2181                 loadsegment(es, vmx->host_state.es_sel);
2182         }
2183 #endif
2184         invalidate_tss_limit();
2185 #ifdef CONFIG_X86_64
2186         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2187 #endif
2188         if (vmx->host_state.msr_host_bndcfgs)
2189                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2190         load_fixmap_gdt(raw_smp_processor_id());
2191 }
2192
2193 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2194 {
2195         preempt_disable();
2196         __vmx_load_host_state(vmx);
2197         preempt_enable();
2198 }
2199
2200 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2201 {
2202         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2203         struct pi_desc old, new;
2204         unsigned int dest;
2205
2206         /*
2207          * In case of hot-plug or hot-unplug, we may have to undo
2208          * vmx_vcpu_pi_put even if there is no assigned device.  And we
2209          * always keep PI.NDST up to date for simplicity: it makes the
2210          * code easier, and CPU migration is not a fast path.
2211          */
2212         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2213                 return;
2214
2215         /*
2216          * First handle the simple case where no cmpxchg is necessary; just
2217          * allow posting non-urgent interrupts.
2218          *
2219          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2220          * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2221          * expects the VCPU to be on the blocked_vcpu_list that matches
2222          * PI.NDST.
2223          */
2224         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2225             vcpu->cpu == cpu) {
2226                 pi_clear_sn(pi_desc);
2227                 return;
2228         }
2229
2230         /* The full case.  */
2231         do {
2232                 old.control = new.control = pi_desc->control;
2233
2234                 dest = cpu_physical_id(cpu);
2235
2236                 if (x2apic_enabled())
2237                         new.ndst = dest;
2238                 else
2239                         new.ndst = (dest << 8) & 0xFF00;
2240
2241                 new.sn = 0;
2242         } while (cmpxchg64(&pi_desc->control, old.control,
2243                            new.control) != old.control);
2244 }
2245
2246 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2247 {
2248         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2249         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2250 }
2251
2252 /*
2253  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2254  * vcpu mutex is already taken.
2255  */
2256 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2257 {
2258         struct vcpu_vmx *vmx = to_vmx(vcpu);
2259         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2260
2261         if (!already_loaded) {
2262                 loaded_vmcs_clear(vmx->loaded_vmcs);
2263                 local_irq_disable();
2264                 crash_disable_local_vmclear(cpu);
2265
2266                 /*
2267                  * Read loaded_vmcs->cpu should be before fetching
2268                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2269                  * See the comments in __loaded_vmcs_clear().
2270                  */
2271                 smp_rmb();
2272
2273                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2274                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2275                 crash_enable_local_vmclear(cpu);
2276                 local_irq_enable();
2277         }
2278
2279         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2280                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2281                 vmcs_load(vmx->loaded_vmcs->vmcs);
2282         }
2283
2284         if (!already_loaded) {
2285                 void *gdt = get_current_gdt_ro();
2286                 unsigned long sysenter_esp;
2287
2288                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2289
2290                 /*
2291                  * Linux uses per-cpu TSS and GDT, so set these when switching
2292                  * processors.  See 22.2.4.
2293                  */
2294                 vmcs_writel(HOST_TR_BASE,
2295                             (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
2296                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
2297
2298                 /*
2299                  * VM exits change the host TR limit to 0x67 after a VM
2300                  * exit.  This is okay, since 0x67 covers everything except
2301                  * the IO bitmap and have have code to handle the IO bitmap
2302                  * being lost after a VM exit.
2303                  */
2304                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2305
2306                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2307                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2308
2309                 vmx->loaded_vmcs->cpu = cpu;
2310         }
2311
2312         /* Setup TSC multiplier */
2313         if (kvm_has_tsc_control &&
2314             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2315                 decache_tsc_multiplier(vmx);
2316
2317         vmx_vcpu_pi_load(vcpu, cpu);
2318         vmx->host_pkru = read_pkru();
2319 }
2320
2321 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2322 {
2323         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2324
2325         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2326                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2327                 !kvm_vcpu_apicv_active(vcpu))
2328                 return;
2329
2330         /* Set SN when the vCPU is preempted */
2331         if (vcpu->preempted)
2332                 pi_set_sn(pi_desc);
2333 }
2334
2335 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2336 {
2337         vmx_vcpu_pi_put(vcpu);
2338
2339         __vmx_load_host_state(to_vmx(vcpu));
2340 }
2341
2342 static bool emulation_required(struct kvm_vcpu *vcpu)
2343 {
2344         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2345 }
2346
2347 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2348
2349 /*
2350  * Return the cr0 value that a nested guest would read. This is a combination
2351  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2352  * its hypervisor (cr0_read_shadow).
2353  */
2354 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2355 {
2356         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2357                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2358 }
2359 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2360 {
2361         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2362                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2363 }
2364
2365 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2366 {
2367         unsigned long rflags, save_rflags;
2368
2369         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2370                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2371                 rflags = vmcs_readl(GUEST_RFLAGS);
2372                 if (to_vmx(vcpu)->rmode.vm86_active) {
2373                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2374                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2375                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2376                 }
2377                 to_vmx(vcpu)->rflags = rflags;
2378         }
2379         return to_vmx(vcpu)->rflags;
2380 }
2381
2382 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2383 {
2384         unsigned long old_rflags = vmx_get_rflags(vcpu);
2385
2386         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2387         to_vmx(vcpu)->rflags = rflags;
2388         if (to_vmx(vcpu)->rmode.vm86_active) {
2389                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2390                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2391         }
2392         vmcs_writel(GUEST_RFLAGS, rflags);
2393
2394         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2395                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2396 }
2397
2398 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2399 {
2400         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2401         int ret = 0;
2402
2403         if (interruptibility & GUEST_INTR_STATE_STI)
2404                 ret |= KVM_X86_SHADOW_INT_STI;
2405         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2406                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2407
2408         return ret;
2409 }
2410
2411 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2412 {
2413         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2414         u32 interruptibility = interruptibility_old;
2415
2416         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2417
2418         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2419                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2420         else if (mask & KVM_X86_SHADOW_INT_STI)
2421                 interruptibility |= GUEST_INTR_STATE_STI;
2422
2423         if ((interruptibility != interruptibility_old))
2424                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2425 }
2426
2427 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2428 {
2429         unsigned long rip;
2430
2431         rip = kvm_rip_read(vcpu);
2432         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2433         kvm_rip_write(vcpu, rip);
2434
2435         /* skipping an emulated instruction also counts */
2436         vmx_set_interrupt_shadow(vcpu, 0);
2437 }
2438
2439 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2440                                                unsigned long exit_qual)
2441 {
2442         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2443         unsigned int nr = vcpu->arch.exception.nr;
2444         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2445
2446         if (vcpu->arch.exception.has_error_code) {
2447                 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2448                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2449         }
2450
2451         if (kvm_exception_is_soft(nr))
2452                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2453         else
2454                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2455
2456         if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2457             vmx_get_nmi_mask(vcpu))
2458                 intr_info |= INTR_INFO_UNBLOCK_NMI;
2459
2460         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2461 }
2462
2463 /*
2464  * KVM wants to inject page-faults which it got to the guest. This function
2465  * checks whether in a nested guest, we need to inject them to L1 or L2.
2466  */
2467 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
2468 {
2469         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2470         unsigned int nr = vcpu->arch.exception.nr;
2471
2472         if (nr == PF_VECTOR) {
2473                 if (vcpu->arch.exception.nested_apf) {
2474                         *exit_qual = vcpu->arch.apf.nested_apf_token;
2475                         return 1;
2476                 }
2477                 /*
2478                  * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2479                  * The fix is to add the ancillary datum (CR2 or DR6) to structs
2480                  * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2481                  * can be written only when inject_pending_event runs.  This should be
2482                  * conditional on a new capability---if the capability is disabled,
2483                  * kvm_multiple_exception would write the ancillary information to
2484                  * CR2 or DR6, for backwards ABI-compatibility.
2485                  */
2486                 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2487                                                     vcpu->arch.exception.error_code)) {
2488                         *exit_qual = vcpu->arch.cr2;
2489                         return 1;
2490                 }
2491         } else {
2492                 if (vmcs12->exception_bitmap & (1u << nr)) {
2493                         if (nr == DB_VECTOR)
2494                                 *exit_qual = vcpu->arch.dr6;
2495                         else
2496                                 *exit_qual = 0;
2497                         return 1;
2498                 }
2499         }
2500
2501         return 0;
2502 }
2503
2504 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2505 {
2506         struct vcpu_vmx *vmx = to_vmx(vcpu);
2507         unsigned nr = vcpu->arch.exception.nr;
2508         bool has_error_code = vcpu->arch.exception.has_error_code;
2509         u32 error_code = vcpu->arch.exception.error_code;
2510         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2511
2512         if (has_error_code) {
2513                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2514                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2515         }
2516
2517         if (vmx->rmode.vm86_active) {
2518                 int inc_eip = 0;
2519                 if (kvm_exception_is_soft(nr))
2520                         inc_eip = vcpu->arch.event_exit_inst_len;
2521                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2522                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2523                 return;
2524         }
2525
2526         if (kvm_exception_is_soft(nr)) {
2527                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2528                              vmx->vcpu.arch.event_exit_inst_len);
2529                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2530         } else
2531                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2532
2533         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2534 }
2535
2536 static bool vmx_rdtscp_supported(void)
2537 {
2538         return cpu_has_vmx_rdtscp();
2539 }
2540
2541 static bool vmx_invpcid_supported(void)
2542 {
2543         return cpu_has_vmx_invpcid() && enable_ept;
2544 }
2545
2546 /*
2547  * Swap MSR entry in host/guest MSR entry array.
2548  */
2549 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2550 {
2551         struct shared_msr_entry tmp;
2552
2553         tmp = vmx->guest_msrs[to];
2554         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2555         vmx->guest_msrs[from] = tmp;
2556 }
2557
2558 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2559 {
2560         unsigned long *msr_bitmap;
2561
2562         if (is_guest_mode(vcpu))
2563                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2564         else if (cpu_has_secondary_exec_ctrls() &&
2565                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2566                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2567                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2568                         if (is_long_mode(vcpu))
2569                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2570                         else
2571                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2572                 } else {
2573                         if (is_long_mode(vcpu))
2574                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2575                         else
2576                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2577                 }
2578         } else {
2579                 if (is_long_mode(vcpu))
2580                         msr_bitmap = vmx_msr_bitmap_longmode;
2581                 else
2582                         msr_bitmap = vmx_msr_bitmap_legacy;
2583         }
2584
2585         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2586 }
2587
2588 /*
2589  * Set up the vmcs to automatically save and restore system
2590  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2591  * mode, as fiddling with msrs is very expensive.
2592  */
2593 static void setup_msrs(struct vcpu_vmx *vmx)
2594 {
2595         int save_nmsrs, index;
2596
2597         save_nmsrs = 0;
2598 #ifdef CONFIG_X86_64
2599         if (is_long_mode(&vmx->vcpu)) {
2600                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2601                 if (index >= 0)
2602                         move_msr_up(vmx, index, save_nmsrs++);
2603                 index = __find_msr_index(vmx, MSR_LSTAR);
2604                 if (index >= 0)
2605                         move_msr_up(vmx, index, save_nmsrs++);
2606                 index = __find_msr_index(vmx, MSR_CSTAR);
2607                 if (index >= 0)
2608                         move_msr_up(vmx, index, save_nmsrs++);
2609                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2610                 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
2611                         move_msr_up(vmx, index, save_nmsrs++);
2612                 /*
2613                  * MSR_STAR is only needed on long mode guests, and only
2614                  * if efer.sce is enabled.
2615                  */
2616                 index = __find_msr_index(vmx, MSR_STAR);
2617                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2618                         move_msr_up(vmx, index, save_nmsrs++);
2619         }
2620 #endif
2621         index = __find_msr_index(vmx, MSR_EFER);
2622         if (index >= 0 && update_transition_efer(vmx, index))
2623                 move_msr_up(vmx, index, save_nmsrs++);
2624
2625         vmx->save_nmsrs = save_nmsrs;
2626
2627         if (cpu_has_vmx_msr_bitmap())
2628                 vmx_set_msr_bitmap(&vmx->vcpu);
2629 }
2630
2631 /*
2632  * reads and returns guest's timestamp counter "register"
2633  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2634  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2635  */
2636 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2637 {
2638         u64 host_tsc, tsc_offset;
2639
2640         host_tsc = rdtsc();
2641         tsc_offset = vmcs_read64(TSC_OFFSET);
2642         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2643 }
2644
2645 /*
2646  * writes 'offset' into guest's timestamp counter offset register
2647  */
2648 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2649 {
2650         if (is_guest_mode(vcpu)) {
2651                 /*
2652                  * We're here if L1 chose not to trap WRMSR to TSC. According
2653                  * to the spec, this should set L1's TSC; The offset that L1
2654                  * set for L2 remains unchanged, and still needs to be added
2655                  * to the newly set TSC to get L2's TSC.
2656                  */
2657                 struct vmcs12 *vmcs12;
2658                 /* recalculate vmcs02.TSC_OFFSET: */
2659                 vmcs12 = get_vmcs12(vcpu);
2660                 vmcs_write64(TSC_OFFSET, offset +
2661                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2662                          vmcs12->tsc_offset : 0));
2663         } else {
2664                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2665                                            vmcs_read64(TSC_OFFSET), offset);
2666                 vmcs_write64(TSC_OFFSET, offset);
2667         }
2668 }
2669
2670 /*
2671  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2672  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2673  * all guests if the "nested" module option is off, and can also be disabled
2674  * for a single guest by disabling its VMX cpuid bit.
2675  */
2676 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2677 {
2678         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
2679 }
2680
2681 /*
2682  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2683  * returned for the various VMX controls MSRs when nested VMX is enabled.
2684  * The same values should also be used to verify that vmcs12 control fields are
2685  * valid during nested entry from L1 to L2.
2686  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2687  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2688  * bit in the high half is on if the corresponding bit in the control field
2689  * may be on. See also vmx_control_verify().
2690  */
2691 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2692 {
2693         /*
2694          * Note that as a general rule, the high half of the MSRs (bits in
2695          * the control fields which may be 1) should be initialized by the
2696          * intersection of the underlying hardware's MSR (i.e., features which
2697          * can be supported) and the list of features we want to expose -
2698          * because they are known to be properly supported in our code.
2699          * Also, usually, the low half of the MSRs (bits which must be 1) can
2700          * be set to 0, meaning that L1 may turn off any of these bits. The
2701          * reason is that if one of these bits is necessary, it will appear
2702          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2703          * fields of vmcs01 and vmcs02, will turn these bits off - and
2704          * nested_vmx_exit_reflected() will not pass related exits to L1.
2705          * These rules have exceptions below.
2706          */
2707
2708         /* pin-based controls */
2709         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2710                 vmx->nested.nested_vmx_pinbased_ctls_low,
2711                 vmx->nested.nested_vmx_pinbased_ctls_high);
2712         vmx->nested.nested_vmx_pinbased_ctls_low |=
2713                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2714         vmx->nested.nested_vmx_pinbased_ctls_high &=
2715                 PIN_BASED_EXT_INTR_MASK |
2716                 PIN_BASED_NMI_EXITING |
2717                 PIN_BASED_VIRTUAL_NMIS;
2718         vmx->nested.nested_vmx_pinbased_ctls_high |=
2719                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2720                 PIN_BASED_VMX_PREEMPTION_TIMER;
2721         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2722                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2723                         PIN_BASED_POSTED_INTR;
2724
2725         /* exit controls */
2726         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2727                 vmx->nested.nested_vmx_exit_ctls_low,
2728                 vmx->nested.nested_vmx_exit_ctls_high);
2729         vmx->nested.nested_vmx_exit_ctls_low =
2730                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2731
2732         vmx->nested.nested_vmx_exit_ctls_high &=
2733 #ifdef CONFIG_X86_64
2734                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2735 #endif
2736                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2737         vmx->nested.nested_vmx_exit_ctls_high |=
2738                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2739                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2740                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2741
2742         if (kvm_mpx_supported())
2743                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2744
2745         /* We support free control of debug control saving. */
2746         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2747
2748         /* entry controls */
2749         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2750                 vmx->nested.nested_vmx_entry_ctls_low,
2751                 vmx->nested.nested_vmx_entry_ctls_high);
2752         vmx->nested.nested_vmx_entry_ctls_low =
2753                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2754         vmx->nested.nested_vmx_entry_ctls_high &=
2755 #ifdef CONFIG_X86_64
2756                 VM_ENTRY_IA32E_MODE |
2757 #endif
2758                 VM_ENTRY_LOAD_IA32_PAT;
2759         vmx->nested.nested_vmx_entry_ctls_high |=
2760                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2761         if (kvm_mpx_supported())
2762                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2763
2764         /* We support free control of debug control loading. */
2765         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2766
2767         /* cpu-based controls */
2768         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2769                 vmx->nested.nested_vmx_procbased_ctls_low,
2770                 vmx->nested.nested_vmx_procbased_ctls_high);
2771         vmx->nested.nested_vmx_procbased_ctls_low =
2772                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2773         vmx->nested.nested_vmx_procbased_ctls_high &=
2774                 CPU_BASED_VIRTUAL_INTR_PENDING |
2775                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2776                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2777                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2778                 CPU_BASED_CR3_STORE_EXITING |
2779 #ifdef CONFIG_X86_64
2780                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2781 #endif
2782                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2783                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2784                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2785                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2786                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2787         /*
2788          * We can allow some features even when not supported by the
2789          * hardware. For example, L1 can specify an MSR bitmap - and we
2790          * can use it to avoid exits to L1 - even when L0 runs L2
2791          * without MSR bitmaps.
2792          */
2793         vmx->nested.nested_vmx_procbased_ctls_high |=
2794                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2795                 CPU_BASED_USE_MSR_BITMAPS;
2796
2797         /* We support free control of CR3 access interception. */
2798         vmx->nested.nested_vmx_procbased_ctls_low &=
2799                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2800
2801         /*
2802          * secondary cpu-based controls.  Do not include those that
2803          * depend on CPUID bits, they are added later by vmx_cpuid_update.
2804          */
2805         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2806                 vmx->nested.nested_vmx_secondary_ctls_low,
2807                 vmx->nested.nested_vmx_secondary_ctls_high);
2808         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2809         vmx->nested.nested_vmx_secondary_ctls_high &=
2810                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2811                 SECONDARY_EXEC_DESC |
2812                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2813                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2814                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2815                 SECONDARY_EXEC_WBINVD_EXITING;
2816
2817         if (enable_ept) {
2818                 /* nested EPT: emulate EPT also to L1 */
2819                 vmx->nested.nested_vmx_secondary_ctls_high |=
2820                         SECONDARY_EXEC_ENABLE_EPT;
2821                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2822                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2823                 if (cpu_has_vmx_ept_execute_only())
2824                         vmx->nested.nested_vmx_ept_caps |=
2825                                 VMX_EPT_EXECUTE_ONLY_BIT;
2826                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2827                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2828                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2829                         VMX_EPT_1GB_PAGE_BIT;
2830                 if (enable_ept_ad_bits) {
2831                         vmx->nested.nested_vmx_secondary_ctls_high |=
2832                                 SECONDARY_EXEC_ENABLE_PML;
2833                         vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2834                 }
2835         } else
2836                 vmx->nested.nested_vmx_ept_caps = 0;
2837
2838         if (cpu_has_vmx_vmfunc()) {
2839                 vmx->nested.nested_vmx_secondary_ctls_high |=
2840                         SECONDARY_EXEC_ENABLE_VMFUNC;
2841                 /*
2842                  * Advertise EPTP switching unconditionally
2843                  * since we emulate it
2844                  */
2845                 vmx->nested.nested_vmx_vmfunc_controls =
2846                         VMX_VMFUNC_EPTP_SWITCHING;
2847         }
2848
2849         /*
2850          * Old versions of KVM use the single-context version without
2851          * checking for support, so declare that it is supported even
2852          * though it is treated as global context.  The alternative is
2853          * not failing the single-context invvpid, and it is worse.
2854          */
2855         if (enable_vpid) {
2856                 vmx->nested.nested_vmx_secondary_ctls_high |=
2857                         SECONDARY_EXEC_ENABLE_VPID;
2858                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2859                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2860         } else
2861                 vmx->nested.nested_vmx_vpid_caps = 0;
2862
2863         if (enable_unrestricted_guest)
2864                 vmx->nested.nested_vmx_secondary_ctls_high |=
2865                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2866
2867         /* miscellaneous data */
2868         rdmsr(MSR_IA32_VMX_MISC,
2869                 vmx->nested.nested_vmx_misc_low,
2870                 vmx->nested.nested_vmx_misc_high);
2871         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2872         vmx->nested.nested_vmx_misc_low |=
2873                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2874                 VMX_MISC_ACTIVITY_HLT;
2875         vmx->nested.nested_vmx_misc_high = 0;
2876
2877         /*
2878          * This MSR reports some information about VMX support. We
2879          * should return information about the VMX we emulate for the
2880          * guest, and the VMCS structure we give it - not about the
2881          * VMX support of the underlying hardware.
2882          */
2883         vmx->nested.nested_vmx_basic =
2884                 VMCS12_REVISION |
2885                 VMX_BASIC_TRUE_CTLS |
2886                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2887                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2888
2889         if (cpu_has_vmx_basic_inout())
2890                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2891
2892         /*
2893          * These MSRs specify bits which the guest must keep fixed on
2894          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2895          * We picked the standard core2 setting.
2896          */
2897 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2898 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2899         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2900         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2901
2902         /* These MSRs specify bits which the guest must keep fixed off. */
2903         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2904         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2905
2906         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2907         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2908 }
2909
2910 /*
2911  * if fixed0[i] == 1: val[i] must be 1
2912  * if fixed1[i] == 0: val[i] must be 0
2913  */
2914 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2915 {
2916         return ((val & fixed1) | fixed0) == val;
2917 }
2918
2919 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2920 {
2921         return fixed_bits_valid(control, low, high);
2922 }
2923
2924 static inline u64 vmx_control_msr(u32 low, u32 high)
2925 {
2926         return low | ((u64)high << 32);
2927 }
2928
2929 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2930 {
2931         superset &= mask;
2932         subset &= mask;
2933
2934         return (superset | subset) == superset;
2935 }
2936
2937 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2938 {
2939         const u64 feature_and_reserved =
2940                 /* feature (except bit 48; see below) */
2941                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2942                 /* reserved */
2943                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2944         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2945
2946         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2947                 return -EINVAL;
2948
2949         /*
2950          * KVM does not emulate a version of VMX that constrains physical
2951          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2952          */
2953         if (data & BIT_ULL(48))
2954                 return -EINVAL;
2955
2956         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2957             vmx_basic_vmcs_revision_id(data))
2958                 return -EINVAL;
2959
2960         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2961                 return -EINVAL;
2962
2963         vmx->nested.nested_vmx_basic = data;
2964         return 0;
2965 }
2966
2967 static int
2968 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2969 {
2970         u64 supported;
2971         u32 *lowp, *highp;
2972
2973         switch (msr_index) {
2974         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2975                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2976                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2977                 break;
2978         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2979                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2980                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2981                 break;
2982         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2983                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2984                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2985                 break;
2986         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2987                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2988                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2989                 break;
2990         case MSR_IA32_VMX_PROCBASED_CTLS2:
2991                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2992                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2993                 break;
2994         default:
2995                 BUG();
2996         }
2997
2998         supported = vmx_control_msr(*lowp, *highp);
2999
3000         /* Check must-be-1 bits are still 1. */
3001         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3002                 return -EINVAL;
3003
3004         /* Check must-be-0 bits are still 0. */
3005         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3006                 return -EINVAL;
3007
3008         *lowp = data;
3009         *highp = data >> 32;
3010         return 0;
3011 }
3012
3013 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3014 {
3015         const u64 feature_and_reserved_bits =
3016                 /* feature */
3017                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3018                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3019                 /* reserved */
3020                 GENMASK_ULL(13, 9) | BIT_ULL(31);
3021         u64 vmx_misc;
3022
3023         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
3024                                    vmx->nested.nested_vmx_misc_high);
3025
3026         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3027                 return -EINVAL;
3028
3029         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
3030              PIN_BASED_VMX_PREEMPTION_TIMER) &&
3031             vmx_misc_preemption_timer_rate(data) !=
3032             vmx_misc_preemption_timer_rate(vmx_misc))
3033                 return -EINVAL;
3034
3035         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3036                 return -EINVAL;
3037
3038         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3039                 return -EINVAL;
3040
3041         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3042                 return -EINVAL;
3043
3044         vmx->nested.nested_vmx_misc_low = data;
3045         vmx->nested.nested_vmx_misc_high = data >> 32;
3046         return 0;
3047 }
3048
3049 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3050 {
3051         u64 vmx_ept_vpid_cap;
3052
3053         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3054                                            vmx->nested.nested_vmx_vpid_caps);
3055
3056         /* Every bit is either reserved or a feature bit. */
3057         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3058                 return -EINVAL;
3059
3060         vmx->nested.nested_vmx_ept_caps = data;
3061         vmx->nested.nested_vmx_vpid_caps = data >> 32;
3062         return 0;
3063 }
3064
3065 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3066 {
3067         u64 *msr;
3068
3069         switch (msr_index) {
3070         case MSR_IA32_VMX_CR0_FIXED0:
3071                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3072                 break;
3073         case MSR_IA32_VMX_CR4_FIXED0:
3074                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3075                 break;
3076         default:
3077                 BUG();
3078         }
3079
3080         /*
3081          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3082          * must be 1 in the restored value.
3083          */
3084         if (!is_bitwise_subset(data, *msr, -1ULL))
3085                 return -EINVAL;
3086
3087         *msr = data;
3088         return 0;
3089 }
3090
3091 /*
3092  * Called when userspace is restoring VMX MSRs.
3093  *
3094  * Returns 0 on success, non-0 otherwise.
3095  */
3096 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3097 {
3098         struct vcpu_vmx *vmx = to_vmx(vcpu);
3099
3100         switch (msr_index) {
3101         case MSR_IA32_VMX_BASIC:
3102                 return vmx_restore_vmx_basic(vmx, data);
3103         case MSR_IA32_VMX_PINBASED_CTLS:
3104         case MSR_IA32_VMX_PROCBASED_CTLS:
3105         case MSR_IA32_VMX_EXIT_CTLS:
3106         case MSR_IA32_VMX_ENTRY_CTLS:
3107                 /*
3108                  * The "non-true" VMX capability MSRs are generated from the
3109                  * "true" MSRs, so we do not support restoring them directly.
3110                  *
3111                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3112                  * should restore the "true" MSRs with the must-be-1 bits
3113                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3114                  * DEFAULT SETTINGS".
3115                  */
3116                 return -EINVAL;
3117         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3118         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3119         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3120         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3121         case MSR_IA32_VMX_PROCBASED_CTLS2:
3122                 return vmx_restore_control_msr(vmx, msr_index, data);
3123         case MSR_IA32_VMX_MISC:
3124                 return vmx_restore_vmx_misc(vmx, data);
3125         case MSR_IA32_VMX_CR0_FIXED0:
3126         case MSR_IA32_VMX_CR4_FIXED0:
3127                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3128         case MSR_IA32_VMX_CR0_FIXED1:
3129         case MSR_IA32_VMX_CR4_FIXED1:
3130                 /*
3131                  * These MSRs are generated based on the vCPU's CPUID, so we
3132                  * do not support restoring them directly.
3133                  */
3134                 return -EINVAL;
3135         case MSR_IA32_VMX_EPT_VPID_CAP:
3136                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3137         case MSR_IA32_VMX_VMCS_ENUM:
3138                 vmx->nested.nested_vmx_vmcs_enum = data;
3139                 return 0;
3140         default:
3141                 /*
3142                  * The rest of the VMX capability MSRs do not support restore.
3143                  */
3144                 return -EINVAL;
3145         }
3146 }
3147
3148 /* Returns 0 on success, non-0 otherwise. */
3149 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3150 {
3151         struct vcpu_vmx *vmx = to_vmx(vcpu);
3152
3153         switch (msr_index) {
3154         case MSR_IA32_VMX_BASIC:
3155                 *pdata = vmx->nested.nested_vmx_basic;
3156                 break;
3157         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3158         case MSR_IA32_VMX_PINBASED_CTLS:
3159                 *pdata = vmx_control_msr(
3160                         vmx->nested.nested_vmx_pinbased_ctls_low,
3161                         vmx->nested.nested_vmx_pinbased_ctls_high);
3162                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3163                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3164                 break;
3165         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3166         case MSR_IA32_VMX_PROCBASED_CTLS:
3167                 *pdata = vmx_control_msr(
3168                         vmx->nested.nested_vmx_procbased_ctls_low,
3169                         vmx->nested.nested_vmx_procbased_ctls_high);
3170                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3171                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3172                 break;
3173         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3174         case MSR_IA32_VMX_EXIT_CTLS:
3175                 *pdata = vmx_control_msr(
3176                         vmx->nested.nested_vmx_exit_ctls_low,
3177                         vmx->nested.nested_vmx_exit_ctls_high);
3178                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3179                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3180                 break;
3181         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3182         case MSR_IA32_VMX_ENTRY_CTLS:
3183                 *pdata = vmx_control_msr(
3184                         vmx->nested.nested_vmx_entry_ctls_low,
3185                         vmx->nested.nested_vmx_entry_ctls_high);
3186                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3187                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3188                 break;
3189         case MSR_IA32_VMX_MISC:
3190                 *pdata = vmx_control_msr(
3191                         vmx->nested.nested_vmx_misc_low,
3192                         vmx->nested.nested_vmx_misc_high);
3193                 break;
3194         case MSR_IA32_VMX_CR0_FIXED0:
3195                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3196                 break;
3197         case MSR_IA32_VMX_CR0_FIXED1:
3198                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3199                 break;
3200         case MSR_IA32_VMX_CR4_FIXED0:
3201                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3202                 break;
3203         case MSR_IA32_VMX_CR4_FIXED1:
3204                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3205                 break;
3206         case MSR_IA32_VMX_VMCS_ENUM:
3207                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3208                 break;
3209         case MSR_IA32_VMX_PROCBASED_CTLS2:
3210                 *pdata = vmx_control_msr(
3211                         vmx->nested.nested_vmx_secondary_ctls_low,
3212                         vmx->nested.nested_vmx_secondary_ctls_high);
3213                 break;
3214         case MSR_IA32_VMX_EPT_VPID_CAP:
3215                 *pdata = vmx->nested.nested_vmx_ept_caps |
3216                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3217                 break;
3218         case MSR_IA32_VMX_VMFUNC:
3219                 *pdata = vmx->nested.nested_vmx_vmfunc_controls;
3220                 break;
3221         default:
3222                 return 1;
3223         }
3224
3225         return 0;
3226 }
3227
3228 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3229                                                  uint64_t val)
3230 {
3231         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3232
3233         return !(val & ~valid_bits);
3234 }
3235
3236 /*
3237  * Reads an msr value (of 'msr_index') into 'pdata'.
3238  * Returns 0 on success, non-0 otherwise.
3239  * Assumes vcpu_load() was already called.
3240  */
3241 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3242 {
3243         struct shared_msr_entry *msr;
3244
3245         switch (msr_info->index) {
3246 #ifdef CONFIG_X86_64
3247         case MSR_FS_BASE:
3248                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3249                 break;
3250         case MSR_GS_BASE:
3251                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3252                 break;
3253         case MSR_KERNEL_GS_BASE:
3254                 vmx_load_host_state(to_vmx(vcpu));
3255                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3256                 break;
3257 #endif
3258         case MSR_EFER:
3259                 return kvm_get_msr_common(vcpu, msr_info);
3260         case MSR_IA32_TSC:
3261                 msr_info->data = guest_read_tsc(vcpu);
3262                 break;
3263         case MSR_IA32_SYSENTER_CS:
3264                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3265                 break;
3266         case MSR_IA32_SYSENTER_EIP:
3267                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3268                 break;
3269         case MSR_IA32_SYSENTER_ESP:
3270                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3271                 break;
3272         case MSR_IA32_BNDCFGS:
3273                 if (!kvm_mpx_supported() ||
3274                     (!msr_info->host_initiated &&
3275                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3276                         return 1;
3277                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3278                 break;
3279         case MSR_IA32_MCG_EXT_CTL:
3280                 if (!msr_info->host_initiated &&
3281                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3282                       FEATURE_CONTROL_LMCE))
3283                         return 1;
3284                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3285                 break;
3286         case MSR_IA32_FEATURE_CONTROL:
3287                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3288                 break;
3289         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3290                 if (!nested_vmx_allowed(vcpu))
3291                         return 1;
3292                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3293         case MSR_IA32_XSS:
3294                 if (!vmx_xsaves_supported())
3295                         return 1;
3296                 msr_info->data = vcpu->arch.ia32_xss;
3297                 break;
3298         case MSR_TSC_AUX:
3299                 if (!msr_info->host_initiated &&
3300                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3301                         return 1;
3302                 /* Otherwise falls through */
3303         default:
3304                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3305                 if (msr) {
3306                         msr_info->data = msr->data;
3307                         break;
3308                 }
3309                 return kvm_get_msr_common(vcpu, msr_info);
3310         }
3311
3312         return 0;
3313 }
3314
3315 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3316
3317 /*
3318  * Writes msr value into into the appropriate "register".
3319  * Returns 0 on success, non-0 otherwise.
3320  * Assumes vcpu_load() was already called.
3321  */
3322 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3323 {
3324         struct vcpu_vmx *vmx = to_vmx(vcpu);
3325         struct shared_msr_entry *msr;
3326         int ret = 0;
3327         u32 msr_index = msr_info->index;
3328         u64 data = msr_info->data;
3329
3330         switch (msr_index) {
3331         case MSR_EFER:
3332                 ret = kvm_set_msr_common(vcpu, msr_info);
3333                 break;
3334 #ifdef CONFIG_X86_64
3335         case MSR_FS_BASE:
3336                 vmx_segment_cache_clear(vmx);
3337                 vmcs_writel(GUEST_FS_BASE, data);
3338                 break;
3339         case MSR_GS_BASE:
3340                 vmx_segment_cache_clear(vmx);
3341                 vmcs_writel(GUEST_GS_BASE, data);
3342                 break;
3343         case MSR_KERNEL_GS_BASE:
3344                 vmx_load_host_state(vmx);
3345                 vmx->msr_guest_kernel_gs_base = data;
3346                 break;
3347 #endif
3348         case MSR_IA32_SYSENTER_CS:
3349                 vmcs_write32(GUEST_SYSENTER_CS, data);
3350                 break;
3351         case MSR_IA32_SYSENTER_EIP:
3352                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3353                 break;
3354         case MSR_IA32_SYSENTER_ESP:
3355                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3356                 break;
3357         case MSR_IA32_BNDCFGS:
3358                 if (!kvm_mpx_supported() ||
3359                     (!msr_info->host_initiated &&
3360                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3361                         return 1;
3362                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
3363                     (data & MSR_IA32_BNDCFGS_RSVD))
3364                         return 1;
3365                 vmcs_write64(GUEST_BNDCFGS, data);
3366                 break;
3367         case MSR_IA32_TSC:
3368                 kvm_write_tsc(vcpu, msr_info);
3369                 break;
3370         case MSR_IA32_CR_PAT:
3371                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3372                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3373                                 return 1;
3374                         vmcs_write64(GUEST_IA32_PAT, data);
3375                         vcpu->arch.pat = data;
3376                         break;
3377                 }
3378                 ret = kvm_set_msr_common(vcpu, msr_info);
3379                 break;
3380         case MSR_IA32_TSC_ADJUST:
3381                 ret = kvm_set_msr_common(vcpu, msr_info);
3382                 break;
3383         case MSR_IA32_MCG_EXT_CTL:
3384                 if ((!msr_info->host_initiated &&
3385                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3386                        FEATURE_CONTROL_LMCE)) ||
3387                     (data & ~MCG_EXT_CTL_LMCE_EN))
3388                         return 1;
3389                 vcpu->arch.mcg_ext_ctl = data;
3390                 break;
3391         case MSR_IA32_FEATURE_CONTROL:
3392                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3393                     (to_vmx(vcpu)->msr_ia32_feature_control &
3394                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3395                         return 1;
3396                 vmx->msr_ia32_feature_control = data;
3397                 if (msr_info->host_initiated && data == 0)
3398                         vmx_leave_nested(vcpu);
3399                 break;
3400         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3401                 if (!msr_info->host_initiated)
3402                         return 1; /* they are read-only */
3403                 if (!nested_vmx_allowed(vcpu))
3404                         return 1;
3405                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3406         case MSR_IA32_XSS:
3407                 if (!vmx_xsaves_supported())
3408                         return 1;
3409                 /*
3410                  * The only supported bit as of Skylake is bit 8, but
3411                  * it is not supported on KVM.
3412                  */
3413                 if (data != 0)
3414                         return 1;
3415                 vcpu->arch.ia32_xss = data;
3416                 if (vcpu->arch.ia32_xss != host_xss)
3417                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3418                                 vcpu->arch.ia32_xss, host_xss);
3419                 else
3420                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3421                 break;
3422         case MSR_TSC_AUX:
3423                 if (!msr_info->host_initiated &&
3424                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3425                         return 1;
3426                 /* Check reserved bit, higher 32 bits should be zero */
3427                 if ((data >> 32) != 0)
3428                         return 1;
3429                 /* Otherwise falls through */
3430         default:
3431                 msr = find_msr_entry(vmx, msr_index);
3432                 if (msr) {
3433                         u64 old_msr_data = msr->data;
3434                         msr->data = data;
3435                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3436                                 preempt_disable();
3437                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3438                                                          msr->mask);
3439                                 preempt_enable();
3440                                 if (ret)
3441                                         msr->data = old_msr_data;
3442                         }
3443                         break;
3444                 }
3445                 ret = kvm_set_msr_common(vcpu, msr_info);
3446         }
3447
3448         return ret;
3449 }
3450
3451 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3452 {
3453         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3454         switch (reg) {
3455         case VCPU_REGS_RSP:
3456                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3457                 break;
3458         case VCPU_REGS_RIP:
3459                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3460                 break;
3461         case VCPU_EXREG_PDPTR:
3462                 if (enable_ept)
3463                         ept_save_pdptrs(vcpu);
3464                 break;
3465         default:
3466                 break;
3467         }
3468 }
3469
3470 static __init int cpu_has_kvm_support(void)
3471 {
3472         return cpu_has_vmx();
3473 }
3474
3475 static __init int vmx_disabled_by_bios(void)
3476 {
3477         u64 msr;
3478
3479         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3480         if (msr & FEATURE_CONTROL_LOCKED) {
3481                 /* launched w/ TXT and VMX disabled */
3482                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3483                         && tboot_enabled())
3484                         return 1;
3485                 /* launched w/o TXT and VMX only enabled w/ TXT */
3486                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3487                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3488                         && !tboot_enabled()) {
3489                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3490                                 "activate TXT before enabling KVM\n");
3491                         return 1;
3492                 }
3493                 /* launched w/o TXT and VMX disabled */
3494                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3495                         && !tboot_enabled())
3496                         return 1;
3497         }
3498
3499         return 0;
3500 }
3501
3502 static void kvm_cpu_vmxon(u64 addr)
3503 {
3504         cr4_set_bits(X86_CR4_VMXE);
3505         intel_pt_handle_vmx(1);
3506
3507         asm volatile (ASM_VMX_VMXON_RAX
3508                         : : "a"(&addr), "m"(addr)
3509                         : "memory", "cc");
3510 }
3511
3512 static int hardware_enable(void)
3513 {
3514         int cpu = raw_smp_processor_id();
3515         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3516         u64 old, test_bits;
3517
3518         if (cr4_read_shadow() & X86_CR4_VMXE)
3519                 return -EBUSY;
3520
3521         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3522         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3523         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3524
3525         /*
3526          * Now we can enable the vmclear operation in kdump
3527          * since the loaded_vmcss_on_cpu list on this cpu
3528          * has been initialized.
3529          *
3530          * Though the cpu is not in VMX operation now, there
3531          * is no problem to enable the vmclear operation
3532          * for the loaded_vmcss_on_cpu list is empty!
3533          */
3534         crash_enable_local_vmclear(cpu);
3535
3536         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3537
3538         test_bits = FEATURE_CONTROL_LOCKED;
3539         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3540         if (tboot_enabled())
3541                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3542
3543         if ((old & test_bits) != test_bits) {
3544                 /* enable and lock */
3545                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3546         }
3547         kvm_cpu_vmxon(phys_addr);
3548         ept_sync_global();
3549
3550         return 0;
3551 }
3552
3553 static void vmclear_local_loaded_vmcss(void)
3554 {
3555         int cpu = raw_smp_processor_id();
3556         struct loaded_vmcs *v, *n;
3557
3558         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3559                                  loaded_vmcss_on_cpu_link)
3560                 __loaded_vmcs_clear(v);
3561 }
3562
3563
3564 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3565  * tricks.
3566  */
3567 static void kvm_cpu_vmxoff(void)
3568 {
3569         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3570
3571         intel_pt_handle_vmx(0);
3572         cr4_clear_bits(X86_CR4_VMXE);
3573 }
3574
3575 static void hardware_disable(void)
3576 {
3577         vmclear_local_loaded_vmcss();
3578         kvm_cpu_vmxoff();
3579 }
3580
3581 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3582                                       u32 msr, u32 *result)
3583 {
3584         u32 vmx_msr_low, vmx_msr_high;
3585         u32 ctl = ctl_min | ctl_opt;
3586
3587         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3588
3589         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3590         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3591
3592         /* Ensure minimum (required) set of control bits are supported. */
3593         if (ctl_min & ~ctl)
3594                 return -EIO;
3595
3596         *result = ctl;
3597         return 0;
3598 }
3599
3600 static __init bool allow_1_setting(u32 msr, u32 ctl)
3601 {
3602         u32 vmx_msr_low, vmx_msr_high;
3603
3604         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3605         return vmx_msr_high & ctl;
3606 }
3607
3608 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3609 {
3610         u32 vmx_msr_low, vmx_msr_high;
3611         u32 min, opt, min2, opt2;
3612         u32 _pin_based_exec_control = 0;
3613         u32 _cpu_based_exec_control = 0;
3614         u32 _cpu_based_2nd_exec_control = 0;
3615         u32 _vmexit_control = 0;
3616         u32 _vmentry_control = 0;
3617
3618         min = CPU_BASED_HLT_EXITING |
3619 #ifdef CONFIG_X86_64
3620               CPU_BASED_CR8_LOAD_EXITING |
3621               CPU_BASED_CR8_STORE_EXITING |
3622 #endif
3623               CPU_BASED_CR3_LOAD_EXITING |
3624               CPU_BASED_CR3_STORE_EXITING |
3625               CPU_BASED_USE_IO_BITMAPS |
3626               CPU_BASED_MOV_DR_EXITING |
3627               CPU_BASED_USE_TSC_OFFSETING |
3628               CPU_BASED_INVLPG_EXITING |
3629               CPU_BASED_RDPMC_EXITING;
3630
3631         if (!kvm_mwait_in_guest())
3632                 min |= CPU_BASED_MWAIT_EXITING |
3633                         CPU_BASED_MONITOR_EXITING;
3634
3635         opt = CPU_BASED_TPR_SHADOW |
3636               CPU_BASED_USE_MSR_BITMAPS |
3637               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3638         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3639                                 &_cpu_based_exec_control) < 0)
3640                 return -EIO;
3641 #ifdef CONFIG_X86_64
3642         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3643                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3644                                            ~CPU_BASED_CR8_STORE_EXITING;
3645 #endif
3646         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3647                 min2 = 0;
3648                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3649                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3650                         SECONDARY_EXEC_WBINVD_EXITING |
3651                         SECONDARY_EXEC_ENABLE_VPID |
3652                         SECONDARY_EXEC_ENABLE_EPT |
3653                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3654                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3655                         SECONDARY_EXEC_RDTSCP |
3656                         SECONDARY_EXEC_ENABLE_INVPCID |
3657                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3658                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3659                         SECONDARY_EXEC_SHADOW_VMCS |
3660                         SECONDARY_EXEC_XSAVES |
3661                         SECONDARY_EXEC_RDSEED |
3662                         SECONDARY_EXEC_RDRAND |
3663                         SECONDARY_EXEC_ENABLE_PML |
3664                         SECONDARY_EXEC_TSC_SCALING |
3665                         SECONDARY_EXEC_ENABLE_VMFUNC;
3666                 if (adjust_vmx_controls(min2, opt2,
3667                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3668                                         &_cpu_based_2nd_exec_control) < 0)
3669                         return -EIO;
3670         }
3671 #ifndef CONFIG_X86_64
3672         if (!(_cpu_based_2nd_exec_control &
3673                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3674                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3675 #endif
3676
3677         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3678                 _cpu_based_2nd_exec_control &= ~(
3679                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3680                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3681                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3682
3683         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3684                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3685                    enabled */
3686                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3687                                              CPU_BASED_CR3_STORE_EXITING |
3688                                              CPU_BASED_INVLPG_EXITING);
3689                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3690                       vmx_capability.ept, vmx_capability.vpid);
3691         }
3692
3693         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3694 #ifdef CONFIG_X86_64
3695         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3696 #endif
3697         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3698                 VM_EXIT_CLEAR_BNDCFGS;
3699         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3700                                 &_vmexit_control) < 0)
3701                 return -EIO;
3702
3703         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3704                 PIN_BASED_VIRTUAL_NMIS;
3705         opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
3706         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3707                                 &_pin_based_exec_control) < 0)
3708                 return -EIO;
3709
3710         if (cpu_has_broken_vmx_preemption_timer())
3711                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3712         if (!(_cpu_based_2nd_exec_control &
3713                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3714                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3715
3716         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3717         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3718         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3719                                 &_vmentry_control) < 0)
3720                 return -EIO;
3721
3722         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3723
3724         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3725         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3726                 return -EIO;
3727
3728 #ifdef CONFIG_X86_64
3729         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3730         if (vmx_msr_high & (1u<<16))
3731                 return -EIO;
3732 #endif
3733
3734         /* Require Write-Back (WB) memory type for VMCS accesses. */
3735         if (((vmx_msr_high >> 18) & 15) != 6)
3736                 return -EIO;
3737
3738         vmcs_conf->size = vmx_msr_high & 0x1fff;
3739         vmcs_conf->order = get_order(vmcs_conf->size);
3740         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3741         vmcs_conf->revision_id = vmx_msr_low;
3742
3743         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3744         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3745         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3746         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3747         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3748
3749         cpu_has_load_ia32_efer =
3750                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3751                                 VM_ENTRY_LOAD_IA32_EFER)
3752                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3753                                    VM_EXIT_LOAD_IA32_EFER);
3754
3755         cpu_has_load_perf_global_ctrl =
3756                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3757                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3758                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3759                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3760
3761         /*
3762          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3763          * but due to errata below it can't be used. Workaround is to use
3764          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3765          *
3766          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3767          *
3768          * AAK155             (model 26)
3769          * AAP115             (model 30)
3770          * AAT100             (model 37)
3771          * BC86,AAY89,BD102   (model 44)
3772          * BA97               (model 46)
3773          *
3774          */
3775         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3776                 switch (boot_cpu_data.x86_model) {
3777                 case 26:
3778                 case 30:
3779                 case 37:
3780                 case 44:
3781                 case 46:
3782                         cpu_has_load_perf_global_ctrl = false;
3783                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3784                                         "does not work properly. Using workaround\n");
3785                         break;
3786                 default:
3787                         break;
3788                 }
3789         }
3790
3791         if (boot_cpu_has(X86_FEATURE_XSAVES))
3792                 rdmsrl(MSR_IA32_XSS, host_xss);
3793
3794         return 0;
3795 }
3796
3797 static struct vmcs *alloc_vmcs_cpu(int cpu)
3798 {
3799         int node = cpu_to_node(cpu);
3800         struct page *pages;
3801         struct vmcs *vmcs;
3802
3803         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3804         if (!pages)
3805                 return NULL;
3806         vmcs = page_address(pages);
3807         memset(vmcs, 0, vmcs_config.size);
3808         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3809         return vmcs;
3810 }
3811
3812 static struct vmcs *alloc_vmcs(void)
3813 {
3814         return alloc_vmcs_cpu(raw_smp_processor_id());
3815 }
3816
3817 static void free_vmcs(struct vmcs *vmcs)
3818 {
3819         free_pages((unsigned long)vmcs, vmcs_config.order);
3820 }
3821
3822 /*
3823  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3824  */
3825 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3826 {
3827         if (!loaded_vmcs->vmcs)
3828                 return;
3829         loaded_vmcs_clear(loaded_vmcs);
3830         free_vmcs(loaded_vmcs->vmcs);
3831         loaded_vmcs->vmcs = NULL;
3832         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3833 }
3834
3835 static void free_kvm_area(void)
3836 {
3837         int cpu;
3838
3839         for_each_possible_cpu(cpu) {
3840                 free_vmcs(per_cpu(vmxarea, cpu));
3841                 per_cpu(vmxarea, cpu) = NULL;
3842         }
3843 }
3844
3845 enum vmcs_field_type {
3846         VMCS_FIELD_TYPE_U16 = 0,
3847         VMCS_FIELD_TYPE_U64 = 1,
3848         VMCS_FIELD_TYPE_U32 = 2,
3849         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
3850 };
3851
3852 static inline int vmcs_field_type(unsigned long field)
3853 {
3854         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
3855                 return VMCS_FIELD_TYPE_U32;
3856         return (field >> 13) & 0x3 ;
3857 }
3858
3859 static inline int vmcs_field_readonly(unsigned long field)
3860 {
3861         return (((field >> 10) & 0x3) == 1);
3862 }
3863
3864 static void init_vmcs_shadow_fields(void)
3865 {
3866         int i, j;
3867
3868         /* No checks for read only fields yet */
3869
3870         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3871                 switch (shadow_read_write_fields[i]) {
3872                 case GUEST_BNDCFGS:
3873                         if (!kvm_mpx_supported())
3874                                 continue;
3875                         break;
3876                 default:
3877                         break;
3878                 }
3879
3880                 if (j < i)
3881                         shadow_read_write_fields[j] =
3882                                 shadow_read_write_fields[i];
3883                 j++;
3884         }
3885         max_shadow_read_write_fields = j;
3886
3887         /* shadowed fields guest access without vmexit */
3888         for (i = 0; i < max_shadow_read_write_fields; i++) {
3889                 unsigned long field = shadow_read_write_fields[i];
3890
3891                 clear_bit(field, vmx_vmwrite_bitmap);
3892                 clear_bit(field, vmx_vmread_bitmap);
3893                 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) {
3894                         clear_bit(field + 1, vmx_vmwrite_bitmap);
3895                         clear_bit(field + 1, vmx_vmread_bitmap);
3896                 }
3897         }
3898         for (i = 0; i < max_shadow_read_only_fields; i++) {
3899                 unsigned long field = shadow_read_only_fields[i];
3900
3901                 clear_bit(field, vmx_vmread_bitmap);
3902                 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64)
3903                         clear_bit(field + 1, vmx_vmread_bitmap);
3904         }
3905 }
3906
3907 static __init int alloc_kvm_area(void)
3908 {
3909         int cpu;
3910
3911         for_each_possible_cpu(cpu) {
3912                 struct vmcs *vmcs;
3913
3914                 vmcs = alloc_vmcs_cpu(cpu);
3915                 if (!vmcs) {
3916                         free_kvm_area();
3917                         return -ENOMEM;
3918                 }
3919
3920                 per_cpu(vmxarea, cpu) = vmcs;
3921         }
3922         return 0;
3923 }
3924
3925 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3926                 struct kvm_segment *save)
3927 {
3928         if (!emulate_invalid_guest_state) {
3929                 /*
3930                  * CS and SS RPL should be equal during guest entry according
3931                  * to VMX spec, but in reality it is not always so. Since vcpu
3932                  * is in the middle of the transition from real mode to
3933                  * protected mode it is safe to assume that RPL 0 is a good
3934                  * default value.
3935                  */
3936                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3937                         save->selector &= ~SEGMENT_RPL_MASK;
3938                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3939                 save->s = 1;
3940         }
3941         vmx_set_segment(vcpu, save, seg);
3942 }
3943
3944 static void enter_pmode(struct kvm_vcpu *vcpu)
3945 {
3946         unsigned long flags;
3947         struct vcpu_vmx *vmx = to_vmx(vcpu);
3948
3949         /*
3950          * Update real mode segment cache. It may be not up-to-date if sement
3951          * register was written while vcpu was in a guest mode.
3952          */
3953         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3954         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3955         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3956         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3957         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3958         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3959
3960         vmx->rmode.vm86_active = 0;
3961
3962         vmx_segment_cache_clear(vmx);
3963
3964         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3965
3966         flags = vmcs_readl(GUEST_RFLAGS);
3967         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3968         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3969         vmcs_writel(GUEST_RFLAGS, flags);
3970
3971         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3972                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3973
3974         update_exception_bitmap(vcpu);
3975
3976         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3977         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3978         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3979         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3980         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3981         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3982 }
3983
3984 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3985 {
3986         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3987         struct kvm_segment var = *save;
3988
3989         var.dpl = 0x3;
3990         if (seg == VCPU_SREG_CS)
3991                 var.type = 0x3;
3992
3993         if (!emulate_invalid_guest_state) {
3994                 var.selector = var.base >> 4;
3995                 var.base = var.base & 0xffff0;
3996                 var.limit = 0xffff;
3997                 var.g = 0;
3998                 var.db = 0;
3999                 var.present = 1;
4000                 var.s = 1;
4001                 var.l = 0;
4002                 var.unusable = 0;
4003                 var.type = 0x3;
4004                 var.avl = 0;
4005                 if (save->base & 0xf)
4006                         printk_once(KERN_WARNING "kvm: segment base is not "
4007                                         "paragraph aligned when entering "
4008                                         "protected mode (seg=%d)", seg);
4009         }
4010
4011         vmcs_write16(sf->selector, var.selector);
4012         vmcs_writel(sf->base, var.base);
4013         vmcs_write32(sf->limit, var.limit);
4014         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
4015 }
4016
4017 static void enter_rmode(struct kvm_vcpu *vcpu)
4018 {
4019         unsigned long flags;
4020         struct vcpu_vmx *vmx = to_vmx(vcpu);
4021
4022         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4023         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4024         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4025         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4026         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4027         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4028         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4029
4030         vmx->rmode.vm86_active = 1;
4031
4032         /*
4033          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4034          * vcpu. Warn the user that an update is overdue.
4035          */
4036         if (!vcpu->kvm->arch.tss_addr)
4037                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4038                              "called before entering vcpu\n");
4039
4040         vmx_segment_cache_clear(vmx);
4041
4042         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
4043         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4044         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4045
4046         flags = vmcs_readl(GUEST_RFLAGS);
4047         vmx->rmode.save_rflags = flags;
4048
4049         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4050
4051         vmcs_writel(GUEST_RFLAGS, flags);
4052         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4053         update_exception_bitmap(vcpu);
4054
4055         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4056         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4057         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4058         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4059         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4060         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4061
4062         kvm_mmu_reset_context(vcpu);
4063 }
4064
4065 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4066 {
4067         struct vcpu_vmx *vmx = to_vmx(vcpu);
4068         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4069
4070         if (!msr)
4071                 return;
4072
4073         /*
4074          * Force kernel_gs_base reloading before EFER changes, as control
4075          * of this msr depends on is_long_mode().
4076          */
4077         vmx_load_host_state(to_vmx(vcpu));
4078         vcpu->arch.efer = efer;
4079         if (efer & EFER_LMA) {
4080                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4081                 msr->data = efer;
4082         } else {
4083                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4084
4085                 msr->data = efer & ~EFER_LME;
4086         }
4087         setup_msrs(vmx);
4088 }
4089
4090 #ifdef CONFIG_X86_64
4091
4092 static void enter_lmode(struct kvm_vcpu *vcpu)
4093 {
4094         u32 guest_tr_ar;
4095
4096         vmx_segment_cache_clear(to_vmx(vcpu));
4097
4098         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4099         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4100                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4101                                      __func__);
4102                 vmcs_write32(GUEST_TR_AR_BYTES,
4103                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4104                              | VMX_AR_TYPE_BUSY_64_TSS);
4105         }
4106         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4107 }
4108
4109 static void exit_lmode(struct kvm_vcpu *vcpu)
4110 {
4111         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4112         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4113 }
4114
4115 #endif
4116
4117 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4118 {
4119         if (enable_ept) {
4120                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4121                         return;
4122                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4123         } else {
4124                 vpid_sync_context(vpid);
4125         }
4126 }
4127
4128 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4129 {
4130         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4131 }
4132
4133 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4134 {
4135         if (enable_ept)
4136                 vmx_flush_tlb(vcpu);
4137 }
4138
4139 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4140 {
4141         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4142
4143         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4144         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4145 }
4146
4147 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4148 {
4149         if (enable_ept && is_paging(vcpu))
4150                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4151         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4152 }
4153
4154 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4155 {
4156         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4157
4158         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4159         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4160 }
4161
4162 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4163 {
4164         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4165
4166         if (!test_bit(VCPU_EXREG_PDPTR,
4167                       (unsigned long *)&vcpu->arch.regs_dirty))
4168                 return;
4169
4170         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4171                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4172                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4173                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4174                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4175         }
4176 }
4177
4178 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4179 {
4180         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4181
4182         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4183                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4184                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4185                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4186                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4187         }
4188
4189         __set_bit(VCPU_EXREG_PDPTR,
4190                   (unsigned long *)&vcpu->arch.regs_avail);
4191         __set_bit(VCPU_EXREG_PDPTR,
4192                   (unsigned long *)&vcpu->arch.regs_dirty);
4193 }
4194
4195 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4196 {
4197         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4198         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4199         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4200
4201         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4202                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4203             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4204                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4205
4206         return fixed_bits_valid(val, fixed0, fixed1);
4207 }
4208
4209 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4210 {
4211         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4212         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4213
4214         return fixed_bits_valid(val, fixed0, fixed1);
4215 }
4216
4217 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4218 {
4219         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4220         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4221
4222         return fixed_bits_valid(val, fixed0, fixed1);
4223 }
4224
4225 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4226 #define nested_guest_cr4_valid  nested_cr4_valid
4227 #define nested_host_cr4_valid   nested_cr4_valid
4228
4229 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4230
4231 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4232                                         unsigned long cr0,
4233                                         struct kvm_vcpu *vcpu)
4234 {
4235         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4236                 vmx_decache_cr3(vcpu);
4237         if (!(cr0 & X86_CR0_PG)) {
4238                 /* From paging/starting to nonpaging */
4239                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4240                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4241                              (CPU_BASED_CR3_LOAD_EXITING |
4242                               CPU_BASED_CR3_STORE_EXITING));
4243                 vcpu->arch.cr0 = cr0;
4244                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4245         } else if (!is_paging(vcpu)) {
4246                 /* From nonpaging to paging */
4247                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4248                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4249                              ~(CPU_BASED_CR3_LOAD_EXITING |
4250                                CPU_BASED_CR3_STORE_EXITING));
4251                 vcpu->arch.cr0 = cr0;
4252                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4253         }
4254
4255         if (!(cr0 & X86_CR0_WP))
4256                 *hw_cr0 &= ~X86_CR0_WP;
4257 }
4258
4259 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4260 {
4261         struct vcpu_vmx *vmx = to_vmx(vcpu);
4262         unsigned long hw_cr0;
4263
4264         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4265         if (enable_unrestricted_guest)
4266                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4267         else {
4268                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4269
4270                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4271                         enter_pmode(vcpu);
4272
4273                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4274                         enter_rmode(vcpu);
4275         }
4276
4277 #ifdef CONFIG_X86_64
4278         if (vcpu->arch.efer & EFER_LME) {
4279                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4280                         enter_lmode(vcpu);
4281                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4282                         exit_lmode(vcpu);
4283         }
4284 #endif
4285
4286         if (enable_ept)
4287                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4288
4289         vmcs_writel(CR0_READ_SHADOW, cr0);
4290         vmcs_writel(GUEST_CR0, hw_cr0);
4291         vcpu->arch.cr0 = cr0;
4292
4293         /* depends on vcpu->arch.cr0 to be set to a new value */
4294         vmx->emulation_required = emulation_required(vcpu);
4295 }
4296
4297 static int get_ept_level(struct kvm_vcpu *vcpu)
4298 {
4299         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
4300                 return 5;
4301         return 4;
4302 }
4303
4304 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4305 {
4306         u64 eptp = VMX_EPTP_MT_WB;
4307
4308         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
4309
4310         if (enable_ept_ad_bits &&
4311             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4312                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
4313         eptp |= (root_hpa & PAGE_MASK);
4314
4315         return eptp;
4316 }
4317
4318 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4319 {
4320         unsigned long guest_cr3;
4321         u64 eptp;
4322
4323         guest_cr3 = cr3;
4324         if (enable_ept) {
4325                 eptp = construct_eptp(vcpu, cr3);
4326                 vmcs_write64(EPT_POINTER, eptp);
4327                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4328                         guest_cr3 = kvm_read_cr3(vcpu);
4329                 else
4330                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4331                 ept_load_pdptrs(vcpu);
4332         }
4333
4334         vmx_flush_tlb(vcpu);
4335         vmcs_writel(GUEST_CR3, guest_cr3);
4336 }
4337
4338 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4339 {
4340         /*
4341          * Pass through host's Machine Check Enable value to hw_cr4, which
4342          * is in force while we are in guest mode.  Do not let guests control
4343          * this bit, even if host CR4.MCE == 0.
4344          */
4345         unsigned long hw_cr4 =
4346                 (cr4_read_shadow() & X86_CR4_MCE) |
4347                 (cr4 & ~X86_CR4_MCE) |
4348                 (to_vmx(vcpu)->rmode.vm86_active ?
4349                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4350
4351         if (cr4 & X86_CR4_VMXE) {
4352                 /*
4353                  * To use VMXON (and later other VMX instructions), a guest
4354                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4355                  * So basically the check on whether to allow nested VMX
4356                  * is here.
4357                  */
4358                 if (!nested_vmx_allowed(vcpu))
4359                         return 1;
4360         }
4361
4362         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4363                 return 1;
4364
4365         vcpu->arch.cr4 = cr4;
4366         if (enable_ept) {
4367                 if (!is_paging(vcpu)) {
4368                         hw_cr4 &= ~X86_CR4_PAE;
4369                         hw_cr4 |= X86_CR4_PSE;
4370                 } else if (!(cr4 & X86_CR4_PAE)) {
4371                         hw_cr4 &= ~X86_CR4_PAE;
4372                 }
4373         }
4374
4375         if (!enable_unrestricted_guest && !is_paging(vcpu))
4376                 /*
4377                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4378                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4379                  * to be manually disabled when guest switches to non-paging
4380                  * mode.
4381                  *
4382                  * If !enable_unrestricted_guest, the CPU is always running
4383                  * with CR0.PG=1 and CR4 needs to be modified.
4384                  * If enable_unrestricted_guest, the CPU automatically
4385                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4386                  */
4387                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4388
4389         vmcs_writel(CR4_READ_SHADOW, cr4);
4390         vmcs_writel(GUEST_CR4, hw_cr4);
4391         return 0;
4392 }
4393
4394 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4395                             struct kvm_segment *var, int seg)
4396 {
4397         struct vcpu_vmx *vmx = to_vmx(vcpu);
4398         u32 ar;
4399
4400         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4401                 *var = vmx->rmode.segs[seg];
4402                 if (seg == VCPU_SREG_TR
4403                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4404                         return;
4405                 var->base = vmx_read_guest_seg_base(vmx, seg);
4406                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4407                 return;
4408         }
4409         var->base = vmx_read_guest_seg_base(vmx, seg);
4410         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4411         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4412         ar = vmx_read_guest_seg_ar(vmx, seg);
4413         var->unusable = (ar >> 16) & 1;
4414         var->type = ar & 15;
4415         var->s = (ar >> 4) & 1;
4416         var->dpl = (ar >> 5) & 3;
4417         /*
4418          * Some userspaces do not preserve unusable property. Since usable
4419          * segment has to be present according to VMX spec we can use present
4420          * property to amend userspace bug by making unusable segment always
4421          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4422          * segment as unusable.
4423          */
4424         var->present = !var->unusable;
4425         var->avl = (ar >> 12) & 1;
4426         var->l = (ar >> 13) & 1;
4427         var->db = (ar >> 14) & 1;
4428         var->g = (ar >> 15) & 1;
4429 }
4430
4431 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4432 {
4433         struct kvm_segment s;
4434
4435         if (to_vmx(vcpu)->rmode.vm86_active) {
4436                 vmx_get_segment(vcpu, &s, seg);
4437                 return s.base;
4438         }
4439         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4440 }
4441
4442 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4443 {
4444         struct vcpu_vmx *vmx = to_vmx(vcpu);
4445
4446         if (unlikely(vmx->rmode.vm86_active))
4447                 return 0;
4448         else {
4449                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4450                 return VMX_AR_DPL(ar);
4451         }
4452 }
4453
4454 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4455 {
4456         u32 ar;
4457
4458         if (var->unusable || !var->present)
4459                 ar = 1 << 16;
4460         else {
4461                 ar = var->type & 15;
4462                 ar |= (var->s & 1) << 4;
4463                 ar |= (var->dpl & 3) << 5;
4464                 ar |= (var->present & 1) << 7;
4465                 ar |= (var->avl & 1) << 12;
4466                 ar |= (var->l & 1) << 13;
4467                 ar |= (var->db & 1) << 14;
4468                 ar |= (var->g & 1) << 15;
4469         }
4470
4471         return ar;
4472 }
4473
4474 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4475                             struct kvm_segment *var, int seg)
4476 {
4477         struct vcpu_vmx *vmx = to_vmx(vcpu);
4478         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4479
4480         vmx_segment_cache_clear(vmx);
4481
4482         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4483                 vmx->rmode.segs[seg] = *var;
4484                 if (seg == VCPU_SREG_TR)
4485                         vmcs_write16(sf->selector, var->selector);
4486                 else if (var->s)
4487                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4488                 goto out;
4489         }
4490
4491         vmcs_writel(sf->base, var->base);
4492         vmcs_write32(sf->limit, var->limit);
4493         vmcs_write16(sf->selector, var->selector);
4494
4495         /*
4496          *   Fix the "Accessed" bit in AR field of segment registers for older
4497          * qemu binaries.
4498          *   IA32 arch specifies that at the time of processor reset the
4499          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4500          * is setting it to 0 in the userland code. This causes invalid guest
4501          * state vmexit when "unrestricted guest" mode is turned on.
4502          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4503          * tree. Newer qemu binaries with that qemu fix would not need this
4504          * kvm hack.
4505          */
4506         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4507                 var->type |= 0x1; /* Accessed */
4508
4509         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4510
4511 out:
4512         vmx->emulation_required = emulation_required(vcpu);
4513 }
4514
4515 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4516 {
4517         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4518
4519         *db = (ar >> 14) & 1;
4520         *l = (ar >> 13) & 1;
4521 }
4522
4523 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4524 {
4525         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4526         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4527 }
4528
4529 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4530 {
4531         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4532         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4533 }
4534
4535 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4536 {
4537         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4538         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4539 }
4540
4541 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4542 {
4543         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4544         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4545 }
4546
4547 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4548 {
4549         struct kvm_segment var;
4550         u32 ar;
4551
4552         vmx_get_segment(vcpu, &var, seg);
4553         var.dpl = 0x3;
4554         if (seg == VCPU_SREG_CS)
4555                 var.type = 0x3;
4556         ar = vmx_segment_access_rights(&var);
4557
4558         if (var.base != (var.selector << 4))
4559                 return false;
4560         if (var.limit != 0xffff)
4561                 return false;
4562         if (ar != 0xf3)
4563                 return false;
4564
4565         return true;
4566 }
4567
4568 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4569 {
4570         struct kvm_segment cs;
4571         unsigned int cs_rpl;
4572
4573         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4574         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4575
4576         if (cs.unusable)
4577                 return false;
4578         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4579                 return false;
4580         if (!cs.s)
4581                 return false;
4582         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4583                 if (cs.dpl > cs_rpl)
4584                         return false;
4585         } else {
4586                 if (cs.dpl != cs_rpl)
4587                         return false;
4588         }
4589         if (!cs.present)
4590                 return false;
4591
4592         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4593         return true;
4594 }
4595
4596 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4597 {
4598         struct kvm_segment ss;
4599         unsigned int ss_rpl;
4600
4601         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4602         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4603
4604         if (ss.unusable)
4605                 return true;
4606         if (ss.type != 3 && ss.type != 7)
4607                 return false;
4608         if (!ss.s)
4609                 return false;
4610         if (ss.dpl != ss_rpl) /* DPL != RPL */
4611                 return false;
4612         if (!ss.present)
4613                 return false;
4614
4615         return true;
4616 }
4617
4618 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4619 {
4620         struct kvm_segment var;
4621         unsigned int rpl;
4622
4623         vmx_get_segment(vcpu, &var, seg);
4624         rpl = var.selector & SEGMENT_RPL_MASK;
4625
4626         if (var.unusable)
4627                 return true;
4628         if (!var.s)
4629                 return false;
4630         if (!var.present)
4631                 return false;
4632         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4633                 if (var.dpl < rpl) /* DPL < RPL */
4634                         return false;
4635         }
4636
4637         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4638          * rights flags
4639          */
4640         return true;
4641 }
4642
4643 static bool tr_valid(struct kvm_vcpu *vcpu)
4644 {
4645         struct kvm_segment tr;
4646
4647         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4648
4649         if (tr.unusable)
4650                 return false;
4651         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4652                 return false;
4653         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4654                 return false;
4655         if (!tr.present)
4656                 return false;
4657
4658         return true;
4659 }
4660
4661 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4662 {
4663         struct kvm_segment ldtr;
4664
4665         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4666
4667         if (ldtr.unusable)
4668                 return true;
4669         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4670                 return false;
4671         if (ldtr.type != 2)
4672                 return false;
4673         if (!ldtr.present)
4674                 return false;
4675
4676         return true;
4677 }
4678
4679 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4680 {
4681         struct kvm_segment cs, ss;
4682
4683         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4684         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4685
4686         return ((cs.selector & SEGMENT_RPL_MASK) ==
4687                  (ss.selector & SEGMENT_RPL_MASK));
4688 }
4689
4690 /*
4691  * Check if guest state is valid. Returns true if valid, false if
4692  * not.
4693  * We assume that registers are always usable
4694  */
4695 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4696 {
4697         if (enable_unrestricted_guest)
4698                 return true;
4699
4700         /* real mode guest state checks */
4701         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4702                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4703                         return false;
4704                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4705                         return false;
4706                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4707                         return false;
4708                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4709                         return false;
4710                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4711                         return false;
4712                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4713                         return false;
4714         } else {
4715         /* protected mode guest state checks */
4716                 if (!cs_ss_rpl_check(vcpu))
4717                         return false;
4718                 if (!code_segment_valid(vcpu))
4719                         return false;
4720                 if (!stack_segment_valid(vcpu))
4721                         return false;
4722                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4723                         return false;
4724                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4725                         return false;
4726                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4727                         return false;
4728                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4729                         return false;
4730                 if (!tr_valid(vcpu))
4731                         return false;
4732                 if (!ldtr_valid(vcpu))
4733                         return false;
4734         }
4735         /* TODO:
4736          * - Add checks on RIP
4737          * - Add checks on RFLAGS
4738          */
4739
4740         return true;
4741 }
4742
4743 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4744 {
4745         return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4746 }
4747
4748 static int init_rmode_tss(struct kvm *kvm)
4749 {
4750         gfn_t fn;
4751         u16 data = 0;
4752         int idx, r;
4753
4754         idx = srcu_read_lock(&kvm->srcu);
4755         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4756         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4757         if (r < 0)
4758                 goto out;
4759         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4760         r = kvm_write_guest_page(kvm, fn++, &data,
4761                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4762         if (r < 0)
4763                 goto out;
4764         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4765         if (r < 0)
4766                 goto out;
4767         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4768         if (r < 0)
4769                 goto out;
4770         data = ~0;
4771         r = kvm_write_guest_page(kvm, fn, &data,
4772                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4773                                  sizeof(u8));
4774 out:
4775         srcu_read_unlock(&kvm->srcu, idx);
4776         return r;
4777 }
4778
4779 static int init_rmode_identity_map(struct kvm *kvm)
4780 {
4781         int i, idx, r = 0;
4782         kvm_pfn_t identity_map_pfn;
4783         u32 tmp;
4784
4785         if (!enable_ept)
4786                 return 0;
4787
4788         /* Protect kvm->arch.ept_identity_pagetable_done. */
4789         mutex_lock(&kvm->slots_lock);
4790
4791         if (likely(kvm->arch.ept_identity_pagetable_done))
4792                 goto out2;
4793
4794         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4795
4796         r = alloc_identity_pagetable(kvm);
4797         if (r < 0)
4798                 goto out2;
4799
4800         idx = srcu_read_lock(&kvm->srcu);
4801         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4802         if (r < 0)
4803                 goto out;
4804         /* Set up identity-mapping pagetable for EPT in real mode */
4805         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4806                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4807                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4808                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4809                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4810                 if (r < 0)
4811                         goto out;
4812         }
4813         kvm->arch.ept_identity_pagetable_done = true;
4814
4815 out:
4816         srcu_read_unlock(&kvm->srcu, idx);
4817
4818 out2:
4819         mutex_unlock(&kvm->slots_lock);
4820         return r;
4821 }
4822
4823 static void seg_setup(int seg)
4824 {
4825         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4826         unsigned int ar;
4827
4828         vmcs_write16(sf->selector, 0);
4829         vmcs_writel(sf->base, 0);
4830         vmcs_write32(sf->limit, 0xffff);
4831         ar = 0x93;
4832         if (seg == VCPU_SREG_CS)
4833                 ar |= 0x08; /* code segment */
4834
4835         vmcs_write32(sf->ar_bytes, ar);
4836 }
4837
4838 static int alloc_apic_access_page(struct kvm *kvm)
4839 {
4840         struct page *page;
4841         int r = 0;
4842
4843         mutex_lock(&kvm->slots_lock);
4844         if (kvm->arch.apic_access_page_done)
4845                 goto out;
4846         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4847                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4848         if (r)
4849                 goto out;
4850
4851         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4852         if (is_error_page(page)) {
4853                 r = -EFAULT;
4854                 goto out;
4855         }
4856
4857         /*
4858          * Do not pin the page in memory, so that memory hot-unplug
4859          * is able to migrate it.
4860          */
4861         put_page(page);
4862         kvm->arch.apic_access_page_done = true;
4863 out:
4864         mutex_unlock(&kvm->slots_lock);
4865         return r;
4866 }
4867
4868 static int alloc_identity_pagetable(struct kvm *kvm)
4869 {
4870         /* Called with kvm->slots_lock held. */
4871
4872         int r = 0;
4873
4874         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4875
4876         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4877                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4878
4879         return r;
4880 }
4881
4882 static int allocate_vpid(void)
4883 {
4884         int vpid;
4885
4886         if (!enable_vpid)
4887                 return 0;
4888         spin_lock(&vmx_vpid_lock);
4889         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4890         if (vpid < VMX_NR_VPIDS)
4891                 __set_bit(vpid, vmx_vpid_bitmap);
4892         else
4893                 vpid = 0;
4894         spin_unlock(&vmx_vpid_lock);
4895         return vpid;
4896 }
4897
4898 static void free_vpid(int vpid)
4899 {
4900         if (!enable_vpid || vpid == 0)
4901                 return;
4902         spin_lock(&vmx_vpid_lock);
4903         __clear_bit(vpid, vmx_vpid_bitmap);
4904         spin_unlock(&vmx_vpid_lock);
4905 }
4906
4907 #define MSR_TYPE_R      1
4908 #define MSR_TYPE_W      2
4909 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4910                                                 u32 msr, int type)
4911 {
4912         int f = sizeof(unsigned long);
4913
4914         if (!cpu_has_vmx_msr_bitmap())
4915                 return;
4916
4917         /*
4918          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4919          * have the write-low and read-high bitmap offsets the wrong way round.
4920          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4921          */
4922         if (msr <= 0x1fff) {
4923                 if (type & MSR_TYPE_R)
4924                         /* read-low */
4925                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4926
4927                 if (type & MSR_TYPE_W)
4928                         /* write-low */
4929                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4930
4931         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4932                 msr &= 0x1fff;
4933                 if (type & MSR_TYPE_R)
4934                         /* read-high */
4935                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4936
4937                 if (type & MSR_TYPE_W)
4938                         /* write-high */
4939                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4940
4941         }
4942 }
4943
4944 /*
4945  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4946  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4947  */
4948 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4949                                                unsigned long *msr_bitmap_nested,
4950                                                u32 msr, int type)
4951 {
4952         int f = sizeof(unsigned long);
4953
4954         if (!cpu_has_vmx_msr_bitmap()) {
4955                 WARN_ON(1);
4956                 return;
4957         }
4958
4959         /*
4960          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4961          * have the write-low and read-high bitmap offsets the wrong way round.
4962          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4963          */
4964         if (msr <= 0x1fff) {
4965                 if (type & MSR_TYPE_R &&
4966                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4967                         /* read-low */
4968                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4969
4970                 if (type & MSR_TYPE_W &&
4971                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4972                         /* write-low */
4973                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4974
4975         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4976                 msr &= 0x1fff;
4977                 if (type & MSR_TYPE_R &&
4978                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4979                         /* read-high */
4980                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4981
4982                 if (type & MSR_TYPE_W &&
4983                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4984                         /* write-high */
4985                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4986
4987         }
4988 }
4989
4990 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4991 {
4992         if (!longmode_only)
4993                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4994                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4995         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4996                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4997 }
4998
4999 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
5000 {
5001         if (apicv_active) {
5002                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
5003                                 msr, type);
5004                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
5005                                 msr, type);
5006         } else {
5007                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
5008                                 msr, type);
5009                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
5010                                 msr, type);
5011         }
5012 }
5013
5014 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
5015 {
5016         return enable_apicv;
5017 }
5018
5019 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5020 {
5021         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5022         gfn_t gfn;
5023
5024         /*
5025          * Don't need to mark the APIC access page dirty; it is never
5026          * written to by the CPU during APIC virtualization.
5027          */
5028
5029         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5030                 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5031                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5032         }
5033
5034         if (nested_cpu_has_posted_intr(vmcs12)) {
5035                 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5036                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5037         }
5038 }
5039
5040
5041 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5042 {
5043         struct vcpu_vmx *vmx = to_vmx(vcpu);
5044         int max_irr;
5045         void *vapic_page;
5046         u16 status;
5047
5048         if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5049                 return;
5050
5051         vmx->nested.pi_pending = false;
5052         if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5053                 return;
5054
5055         max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5056         if (max_irr != 256) {
5057                 vapic_page = kmap(vmx->nested.virtual_apic_page);
5058                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
5059                 kunmap(vmx->nested.virtual_apic_page);
5060
5061                 status = vmcs_read16(GUEST_INTR_STATUS);
5062                 if ((u8)max_irr > ((u8)status & 0xff)) {
5063                         status &= ~0xff;
5064                         status |= (u8)max_irr;
5065                         vmcs_write16(GUEST_INTR_STATUS, status);
5066                 }
5067         }
5068
5069         nested_mark_vmcs12_pages_dirty(vcpu);
5070 }
5071
5072 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5073                                                      bool nested)
5074 {
5075 #ifdef CONFIG_SMP
5076         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5077
5078         if (vcpu->mode == IN_GUEST_MODE) {
5079                 /*
5080                  * The vector of interrupt to be delivered to vcpu had
5081                  * been set in PIR before this function.
5082                  *
5083                  * Following cases will be reached in this block, and
5084                  * we always send a notification event in all cases as
5085                  * explained below.
5086                  *
5087                  * Case 1: vcpu keeps in non-root mode. Sending a
5088                  * notification event posts the interrupt to vcpu.
5089                  *
5090                  * Case 2: vcpu exits to root mode and is still
5091                  * runnable. PIR will be synced to vIRR before the
5092                  * next vcpu entry. Sending a notification event in
5093                  * this case has no effect, as vcpu is not in root
5094                  * mode.
5095                  *
5096                  * Case 3: vcpu exits to root mode and is blocked.
5097                  * vcpu_block() has already synced PIR to vIRR and
5098                  * never blocks vcpu if vIRR is not cleared. Therefore,
5099                  * a blocked vcpu here does not wait for any requested
5100                  * interrupts in PIR, and sending a notification event
5101                  * which has no effect is safe here.
5102                  */
5103
5104                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5105                 return true;
5106         }
5107 #endif
5108         return false;
5109 }
5110
5111 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5112                                                 int vector)
5113 {
5114         struct vcpu_vmx *vmx = to_vmx(vcpu);
5115
5116         if (is_guest_mode(vcpu) &&
5117             vector == vmx->nested.posted_intr_nv) {
5118                 /* the PIR and ON have been set by L1. */
5119                 kvm_vcpu_trigger_posted_interrupt(vcpu, true);
5120                 /*
5121                  * If a posted intr is not recognized by hardware,
5122                  * we will accomplish it in the next vmentry.
5123                  */
5124                 vmx->nested.pi_pending = true;
5125                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5126                 return 0;
5127         }
5128         return -1;
5129 }
5130 /*
5131  * Send interrupt to vcpu via posted interrupt way.
5132  * 1. If target vcpu is running(non-root mode), send posted interrupt
5133  * notification to vcpu and hardware will sync PIR to vIRR atomically.
5134  * 2. If target vcpu isn't running(root mode), kick it to pick up the
5135  * interrupt from PIR in next vmentry.
5136  */
5137 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5138 {
5139         struct vcpu_vmx *vmx = to_vmx(vcpu);
5140         int r;
5141
5142         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5143         if (!r)
5144                 return;
5145
5146         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5147                 return;
5148
5149         /* If a previous notification has sent the IPI, nothing to do.  */
5150         if (pi_test_and_set_on(&vmx->pi_desc))
5151                 return;
5152
5153         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5154                 kvm_vcpu_kick(vcpu);
5155 }
5156
5157 /*
5158  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5159  * will not change in the lifetime of the guest.
5160  * Note that host-state that does change is set elsewhere. E.g., host-state
5161  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5162  */
5163 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5164 {
5165         u32 low32, high32;
5166         unsigned long tmpl;
5167         struct desc_ptr dt;
5168         unsigned long cr0, cr3, cr4;
5169
5170         cr0 = read_cr0();
5171         WARN_ON(cr0 & X86_CR0_TS);
5172         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5173
5174         /*
5175          * Save the most likely value for this task's CR3 in the VMCS.
5176          * We can't use __get_current_cr3_fast() because we're not atomic.
5177          */
5178         cr3 = __read_cr3();
5179         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
5180         vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5181
5182         /* Save the most likely value for this task's CR4 in the VMCS. */
5183         cr4 = cr4_read_shadow();
5184         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5185         vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5186
5187         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5188 #ifdef CONFIG_X86_64
5189         /*
5190          * Load null selectors, so we can avoid reloading them in
5191          * __vmx_load_host_state(), in case userspace uses the null selectors
5192          * too (the expected case).
5193          */
5194         vmcs_write16(HOST_DS_SELECTOR, 0);
5195         vmcs_write16(HOST_ES_SELECTOR, 0);
5196 #else
5197         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5198         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5199 #endif
5200         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5201         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5202
5203         store_idt(&dt);
5204         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5205         vmx->host_idt_base = dt.address;
5206
5207         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5208
5209         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5210         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5211         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5212         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5213
5214         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5215                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5216                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5217         }
5218 }
5219
5220 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5221 {
5222         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5223         if (enable_ept)
5224                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5225         if (is_guest_mode(&vmx->vcpu))
5226                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5227                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5228         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5229 }
5230
5231 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5232 {
5233         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5234
5235         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5236                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5237         /* Enable the preemption timer dynamically */
5238         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5239         return pin_based_exec_ctrl;
5240 }
5241
5242 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5243 {
5244         struct vcpu_vmx *vmx = to_vmx(vcpu);
5245
5246         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5247         if (cpu_has_secondary_exec_ctrls()) {
5248                 if (kvm_vcpu_apicv_active(vcpu))
5249                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5250                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5251                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5252                 else
5253                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5254                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5255                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5256         }
5257
5258         if (cpu_has_vmx_msr_bitmap())
5259                 vmx_set_msr_bitmap(vcpu);
5260 }
5261
5262 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5263 {
5264         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5265
5266         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5267                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5268
5269         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5270                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5271 #ifdef CONFIG_X86_64
5272                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5273                                 CPU_BASED_CR8_LOAD_EXITING;
5274 #endif
5275         }
5276         if (!enable_ept)
5277                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5278                                 CPU_BASED_CR3_LOAD_EXITING  |
5279                                 CPU_BASED_INVLPG_EXITING;
5280         return exec_control;
5281 }
5282
5283 static bool vmx_rdrand_supported(void)
5284 {
5285         return vmcs_config.cpu_based_2nd_exec_ctrl &
5286                 SECONDARY_EXEC_RDRAND;
5287 }
5288
5289 static bool vmx_rdseed_supported(void)
5290 {
5291         return vmcs_config.cpu_based_2nd_exec_ctrl &
5292                 SECONDARY_EXEC_RDSEED;
5293 }
5294
5295 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
5296 {
5297         struct kvm_vcpu *vcpu = &vmx->vcpu;
5298
5299         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5300         if (!cpu_need_virtualize_apic_accesses(vcpu))
5301                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5302         if (vmx->vpid == 0)
5303                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5304         if (!enable_ept) {
5305                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5306                 enable_unrestricted_guest = 0;
5307                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5308                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5309         }
5310         if (!enable_unrestricted_guest)
5311                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5312         if (!ple_gap)
5313                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5314         if (!kvm_vcpu_apicv_active(vcpu))
5315                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5316                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5317         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5318         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5319            (handle_vmptrld).
5320            We can NOT enable shadow_vmcs here because we don't have yet
5321            a current VMCS12
5322         */
5323         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5324
5325         if (!enable_pml)
5326                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5327
5328         if (vmx_xsaves_supported()) {
5329                 /* Exposing XSAVES only when XSAVE is exposed */
5330                 bool xsaves_enabled =
5331                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
5332                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
5333
5334                 if (!xsaves_enabled)
5335                         exec_control &= ~SECONDARY_EXEC_XSAVES;
5336
5337                 if (nested) {
5338                         if (xsaves_enabled)
5339                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5340                                         SECONDARY_EXEC_XSAVES;
5341                         else
5342                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5343                                         ~SECONDARY_EXEC_XSAVES;
5344                 }
5345         }
5346
5347         if (vmx_rdtscp_supported()) {
5348                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
5349                 if (!rdtscp_enabled)
5350                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
5351
5352                 if (nested) {
5353                         if (rdtscp_enabled)
5354                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5355                                         SECONDARY_EXEC_RDTSCP;
5356                         else
5357                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5358                                         ~SECONDARY_EXEC_RDTSCP;
5359                 }
5360         }
5361
5362         if (vmx_invpcid_supported()) {
5363                 /* Exposing INVPCID only when PCID is exposed */
5364                 bool invpcid_enabled =
5365                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
5366                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
5367
5368                 if (!invpcid_enabled) {
5369                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5370                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
5371                 }
5372
5373                 if (nested) {
5374                         if (invpcid_enabled)
5375                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5376                                         SECONDARY_EXEC_ENABLE_INVPCID;
5377                         else
5378                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5379                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
5380                 }
5381         }
5382
5383         if (vmx_rdrand_supported()) {
5384                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
5385                 if (rdrand_enabled)
5386                         exec_control &= ~SECONDARY_EXEC_RDRAND;
5387
5388                 if (nested) {
5389                         if (rdrand_enabled)
5390                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5391                                         SECONDARY_EXEC_RDRAND;
5392                         else
5393                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5394                                         ~SECONDARY_EXEC_RDRAND;
5395                 }
5396         }
5397
5398         if (vmx_rdseed_supported()) {
5399                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
5400                 if (rdseed_enabled)
5401                         exec_control &= ~SECONDARY_EXEC_RDSEED;
5402
5403                 if (nested) {
5404                         if (rdseed_enabled)
5405                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5406                                         SECONDARY_EXEC_RDSEED;
5407                         else
5408                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5409                                         ~SECONDARY_EXEC_RDSEED;
5410                 }
5411         }
5412
5413         vmx->secondary_exec_control = exec_control;
5414 }
5415
5416 static void ept_set_mmio_spte_mask(void)
5417 {
5418         /*
5419          * EPT Misconfigurations can be generated if the value of bits 2:0
5420          * of an EPT paging-structure entry is 110b (write/execute).
5421          */
5422         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5423                                    VMX_EPT_MISCONFIG_WX_VALUE);
5424 }
5425
5426 #define VMX_XSS_EXIT_BITMAP 0
5427 /*
5428  * Sets up the vmcs for emulated real mode.
5429  */
5430 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5431 {
5432 #ifdef CONFIG_X86_64
5433         unsigned long a;
5434 #endif
5435         int i;
5436
5437         /* I/O */
5438         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5439         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5440
5441         if (enable_shadow_vmcs) {
5442                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5443                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5444         }
5445         if (cpu_has_vmx_msr_bitmap())
5446                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5447
5448         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5449
5450         /* Control */
5451         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5452         vmx->hv_deadline_tsc = -1;
5453
5454         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5455
5456         if (cpu_has_secondary_exec_ctrls()) {
5457                 vmx_compute_secondary_exec_control(vmx);
5458                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5459                              vmx->secondary_exec_control);
5460         }
5461
5462         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5463                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5464                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5465                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5466                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5467
5468                 vmcs_write16(GUEST_INTR_STATUS, 0);
5469
5470                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5471                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5472         }
5473
5474         if (ple_gap) {
5475                 vmcs_write32(PLE_GAP, ple_gap);
5476                 vmx->ple_window = ple_window;
5477                 vmx->ple_window_dirty = true;
5478         }
5479
5480         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5481         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5482         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5483
5484         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5485         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5486         vmx_set_constant_host_state(vmx);
5487 #ifdef CONFIG_X86_64
5488         rdmsrl(MSR_FS_BASE, a);
5489         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5490         rdmsrl(MSR_GS_BASE, a);
5491         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5492 #else
5493         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5494         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5495 #endif
5496
5497         if (cpu_has_vmx_vmfunc())
5498                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
5499
5500         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5501         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5502         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5503         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5504         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5505
5506         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5507                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5508
5509         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5510                 u32 index = vmx_msr_index[i];
5511                 u32 data_low, data_high;
5512                 int j = vmx->nmsrs;
5513
5514                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5515                         continue;
5516                 if (wrmsr_safe(index, data_low, data_high) < 0)
5517                         continue;
5518                 vmx->guest_msrs[j].index = i;
5519                 vmx->guest_msrs[j].data = 0;
5520                 vmx->guest_msrs[j].mask = -1ull;
5521                 ++vmx->nmsrs;
5522         }
5523
5524
5525         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5526
5527         /* 22.2.1, 20.8.1 */
5528         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5529
5530         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5531         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5532
5533         set_cr4_guest_host_mask(vmx);
5534
5535         if (vmx_xsaves_supported())
5536                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5537
5538         if (enable_pml) {
5539                 ASSERT(vmx->pml_pg);
5540                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5541                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5542         }
5543
5544         return 0;
5545 }
5546
5547 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5548 {
5549         struct vcpu_vmx *vmx = to_vmx(vcpu);
5550         struct msr_data apic_base_msr;
5551         u64 cr0;
5552
5553         vmx->rmode.vm86_active = 0;
5554
5555         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5556         kvm_set_cr8(vcpu, 0);
5557
5558         if (!init_event) {
5559                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5560                                      MSR_IA32_APICBASE_ENABLE;
5561                 if (kvm_vcpu_is_reset_bsp(vcpu))
5562                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5563                 apic_base_msr.host_initiated = true;
5564                 kvm_set_apic_base(vcpu, &apic_base_msr);
5565         }
5566
5567         vmx_segment_cache_clear(vmx);
5568
5569         seg_setup(VCPU_SREG_CS);
5570         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5571         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5572
5573         seg_setup(VCPU_SREG_DS);
5574         seg_setup(VCPU_SREG_ES);
5575         seg_setup(VCPU_SREG_FS);
5576         seg_setup(VCPU_SREG_GS);
5577         seg_setup(VCPU_SREG_SS);
5578
5579         vmcs_write16(GUEST_TR_SELECTOR, 0);
5580         vmcs_writel(GUEST_TR_BASE, 0);
5581         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5582         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5583
5584         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5585         vmcs_writel(GUEST_LDTR_BASE, 0);
5586         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5587         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5588
5589         if (!init_event) {
5590                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5591                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5592                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5593                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5594         }
5595
5596         vmcs_writel(GUEST_RFLAGS, 0x02);
5597         kvm_rip_write(vcpu, 0xfff0);
5598
5599         vmcs_writel(GUEST_GDTR_BASE, 0);
5600         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5601
5602         vmcs_writel(GUEST_IDTR_BASE, 0);
5603         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5604
5605         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5606         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5607         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5608
5609         setup_msrs(vmx);
5610
5611         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5612
5613         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5614                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5615                 if (cpu_need_tpr_shadow(vcpu))
5616                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5617                                      __pa(vcpu->arch.apic->regs));
5618                 vmcs_write32(TPR_THRESHOLD, 0);
5619         }
5620
5621         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5622
5623         if (vmx->vpid != 0)
5624                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5625
5626         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5627         vmx->vcpu.arch.cr0 = cr0;
5628         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5629         vmx_set_cr4(vcpu, 0);
5630         vmx_set_efer(vcpu, 0);
5631
5632         update_exception_bitmap(vcpu);
5633
5634         vpid_sync_context(vmx->vpid);
5635 }
5636
5637 /*
5638  * In nested virtualization, check if L1 asked to exit on external interrupts.
5639  * For most existing hypervisors, this will always return true.
5640  */
5641 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5642 {
5643         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5644                 PIN_BASED_EXT_INTR_MASK;
5645 }
5646
5647 /*
5648  * In nested virtualization, check if L1 has set
5649  * VM_EXIT_ACK_INTR_ON_EXIT
5650  */
5651 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5652 {
5653         return get_vmcs12(vcpu)->vm_exit_controls &
5654                 VM_EXIT_ACK_INTR_ON_EXIT;
5655 }
5656
5657 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5658 {
5659         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5660                 PIN_BASED_NMI_EXITING;
5661 }
5662
5663 static void enable_irq_window(struct kvm_vcpu *vcpu)
5664 {
5665         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5666                       CPU_BASED_VIRTUAL_INTR_PENDING);
5667 }
5668
5669 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5670 {
5671         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5672                 enable_irq_window(vcpu);
5673                 return;
5674         }
5675
5676         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5677                       CPU_BASED_VIRTUAL_NMI_PENDING);
5678 }
5679
5680 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5681 {
5682         struct vcpu_vmx *vmx = to_vmx(vcpu);
5683         uint32_t intr;
5684         int irq = vcpu->arch.interrupt.nr;
5685
5686         trace_kvm_inj_virq(irq);
5687
5688         ++vcpu->stat.irq_injections;
5689         if (vmx->rmode.vm86_active) {
5690                 int inc_eip = 0;
5691                 if (vcpu->arch.interrupt.soft)
5692                         inc_eip = vcpu->arch.event_exit_inst_len;
5693                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5694                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5695                 return;
5696         }
5697         intr = irq | INTR_INFO_VALID_MASK;
5698         if (vcpu->arch.interrupt.soft) {
5699                 intr |= INTR_TYPE_SOFT_INTR;
5700                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5701                              vmx->vcpu.arch.event_exit_inst_len);
5702         } else
5703                 intr |= INTR_TYPE_EXT_INTR;
5704         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5705 }
5706
5707 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5708 {
5709         struct vcpu_vmx *vmx = to_vmx(vcpu);
5710
5711         ++vcpu->stat.nmi_injections;
5712         vmx->loaded_vmcs->nmi_known_unmasked = false;
5713
5714         if (vmx->rmode.vm86_active) {
5715                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5716                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5717                 return;
5718         }
5719
5720         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5721                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5722 }
5723
5724 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5725 {
5726         struct vcpu_vmx *vmx = to_vmx(vcpu);
5727         bool masked;
5728
5729         if (vmx->loaded_vmcs->nmi_known_unmasked)
5730                 return false;
5731         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5732         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5733         return masked;
5734 }
5735
5736 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5737 {
5738         struct vcpu_vmx *vmx = to_vmx(vcpu);
5739
5740         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5741         if (masked)
5742                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5743                               GUEST_INTR_STATE_NMI);
5744         else
5745                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5746                                 GUEST_INTR_STATE_NMI);
5747 }
5748
5749 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5750 {
5751         if (to_vmx(vcpu)->nested.nested_run_pending)
5752                 return 0;
5753
5754         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5755                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5756                    | GUEST_INTR_STATE_NMI));
5757 }
5758
5759 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5760 {
5761         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5762                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5763                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5764                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5765 }
5766
5767 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5768 {
5769         int ret;
5770
5771         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5772                                     PAGE_SIZE * 3);
5773         if (ret)
5774                 return ret;
5775         kvm->arch.tss_addr = addr;
5776         return init_rmode_tss(kvm);
5777 }
5778
5779 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5780 {
5781         switch (vec) {
5782         case BP_VECTOR:
5783                 /*
5784                  * Update instruction length as we may reinject the exception
5785                  * from user space while in guest debugging mode.
5786                  */
5787                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5788                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5789                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5790                         return false;
5791                 /* fall through */
5792         case DB_VECTOR:
5793                 if (vcpu->guest_debug &
5794                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5795                         return false;
5796                 /* fall through */
5797         case DE_VECTOR:
5798         case OF_VECTOR:
5799         case BR_VECTOR:
5800         case UD_VECTOR:
5801         case DF_VECTOR:
5802         case SS_VECTOR:
5803         case GP_VECTOR:
5804         case MF_VECTOR:
5805                 return true;
5806         break;
5807         }
5808         return false;
5809 }
5810
5811 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5812                                   int vec, u32 err_code)
5813 {
5814         /*
5815          * Instruction with address size override prefix opcode 0x67
5816          * Cause the #SS fault with 0 error code in VM86 mode.
5817          */
5818         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5819                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5820                         if (vcpu->arch.halt_request) {
5821                                 vcpu->arch.halt_request = 0;
5822                                 return kvm_vcpu_halt(vcpu);
5823                         }
5824                         return 1;
5825                 }
5826                 return 0;
5827         }
5828
5829         /*
5830          * Forward all other exceptions that are valid in real mode.
5831          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5832          *        the required debugging infrastructure rework.
5833          */
5834         kvm_queue_exception(vcpu, vec);
5835         return 1;
5836 }
5837
5838 /*
5839  * Trigger machine check on the host. We assume all the MSRs are already set up
5840  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5841  * We pass a fake environment to the machine check handler because we want
5842  * the guest to be always treated like user space, no matter what context
5843  * it used internally.
5844  */
5845 static void kvm_machine_check(void)
5846 {
5847 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5848         struct pt_regs regs = {
5849                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5850                 .flags = X86_EFLAGS_IF,
5851         };
5852
5853         do_machine_check(&regs, 0);
5854 #endif
5855 }
5856
5857 static int handle_machine_check(struct kvm_vcpu *vcpu)
5858 {
5859         /* already handled by vcpu_run */
5860         return 1;
5861 }
5862
5863 static int handle_exception(struct kvm_vcpu *vcpu)
5864 {
5865         struct vcpu_vmx *vmx = to_vmx(vcpu);
5866         struct kvm_run *kvm_run = vcpu->run;
5867         u32 intr_info, ex_no, error_code;
5868         unsigned long cr2, rip, dr6;
5869         u32 vect_info;
5870         enum emulation_result er;
5871
5872         vect_info = vmx->idt_vectoring_info;
5873         intr_info = vmx->exit_intr_info;
5874
5875         if (is_machine_check(intr_info))
5876                 return handle_machine_check(vcpu);
5877
5878         if (is_nmi(intr_info))
5879                 return 1;  /* already handled by vmx_vcpu_run() */
5880
5881         if (is_invalid_opcode(intr_info)) {
5882                 if (is_guest_mode(vcpu)) {
5883                         kvm_queue_exception(vcpu, UD_VECTOR);
5884                         return 1;
5885                 }
5886                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5887                 if (er != EMULATE_DONE)
5888                         kvm_queue_exception(vcpu, UD_VECTOR);
5889                 return 1;
5890         }
5891
5892         error_code = 0;
5893         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5894                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5895
5896         /*
5897          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5898          * MMIO, it is better to report an internal error.
5899          * See the comments in vmx_handle_exit.
5900          */
5901         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5902             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5903                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5904                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5905                 vcpu->run->internal.ndata = 3;
5906                 vcpu->run->internal.data[0] = vect_info;
5907                 vcpu->run->internal.data[1] = intr_info;
5908                 vcpu->run->internal.data[2] = error_code;
5909                 return 0;
5910         }
5911
5912         if (is_page_fault(intr_info)) {
5913                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5914                 /* EPT won't cause page fault directly */
5915                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
5916                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0,
5917                                 true);
5918         }
5919
5920         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5921
5922         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5923                 return handle_rmode_exception(vcpu, ex_no, error_code);
5924
5925         switch (ex_no) {
5926         case AC_VECTOR:
5927                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5928                 return 1;
5929         case DB_VECTOR:
5930                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5931                 if (!(vcpu->guest_debug &
5932                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5933                         vcpu->arch.dr6 &= ~15;
5934                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5935                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5936                                 skip_emulated_instruction(vcpu);
5937
5938                         kvm_queue_exception(vcpu, DB_VECTOR);
5939                         return 1;
5940                 }
5941                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5942                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5943                 /* fall through */
5944         case BP_VECTOR:
5945                 /*
5946                  * Update instruction length as we may reinject #BP from
5947                  * user space while in guest debugging mode. Reading it for
5948                  * #DB as well causes no harm, it is not used in that case.
5949                  */
5950                 vmx->vcpu.arch.event_exit_inst_len =
5951                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5952                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5953                 rip = kvm_rip_read(vcpu);
5954                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5955                 kvm_run->debug.arch.exception = ex_no;
5956                 break;
5957         default:
5958                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5959                 kvm_run->ex.exception = ex_no;
5960                 kvm_run->ex.error_code = error_code;
5961                 break;
5962         }
5963         return 0;
5964 }
5965
5966 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5967 {
5968         ++vcpu->stat.irq_exits;
5969         return 1;
5970 }
5971
5972 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5973 {
5974         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5975         vcpu->mmio_needed = 0;
5976         return 0;
5977 }
5978
5979 static int handle_io(struct kvm_vcpu *vcpu)
5980 {
5981         unsigned long exit_qualification;
5982         int size, in, string, ret;
5983         unsigned port;
5984
5985         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5986         string = (exit_qualification & 16) != 0;
5987         in = (exit_qualification & 8) != 0;
5988
5989         ++vcpu->stat.io_exits;
5990
5991         if (string || in)
5992                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5993
5994         port = exit_qualification >> 16;
5995         size = (exit_qualification & 7) + 1;
5996
5997         ret = kvm_skip_emulated_instruction(vcpu);
5998
5999         /*
6000          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6001          * KVM_EXIT_DEBUG here.
6002          */
6003         return kvm_fast_pio_out(vcpu, size, port) && ret;
6004 }
6005
6006 static void
6007 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
6008 {
6009         /*
6010          * Patch in the VMCALL instruction:
6011          */
6012         hypercall[0] = 0x0f;
6013         hypercall[1] = 0x01;
6014         hypercall[2] = 0xc1;
6015 }
6016
6017 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6018 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
6019 {
6020         if (is_guest_mode(vcpu)) {
6021                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6022                 unsigned long orig_val = val;
6023
6024                 /*
6025                  * We get here when L2 changed cr0 in a way that did not change
6026                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6027                  * but did change L0 shadowed bits. So we first calculate the
6028                  * effective cr0 value that L1 would like to write into the
6029                  * hardware. It consists of the L2-owned bits from the new
6030                  * value combined with the L1-owned bits from L1's guest_cr0.
6031                  */
6032                 val = (val & ~vmcs12->cr0_guest_host_mask) |
6033                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
6034
6035                 if (!nested_guest_cr0_valid(vcpu, val))
6036                         return 1;
6037
6038                 if (kvm_set_cr0(vcpu, val))
6039                         return 1;
6040                 vmcs_writel(CR0_READ_SHADOW, orig_val);
6041                 return 0;
6042         } else {
6043                 if (to_vmx(vcpu)->nested.vmxon &&
6044                     !nested_host_cr0_valid(vcpu, val))
6045                         return 1;
6046
6047                 return kvm_set_cr0(vcpu, val);
6048         }
6049 }
6050
6051 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
6052 {
6053         if (is_guest_mode(vcpu)) {
6054                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6055                 unsigned long orig_val = val;
6056
6057                 /* analogously to handle_set_cr0 */
6058                 val = (val & ~vmcs12->cr4_guest_host_mask) |
6059                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
6060                 if (kvm_set_cr4(vcpu, val))
6061                         return 1;
6062                 vmcs_writel(CR4_READ_SHADOW, orig_val);
6063                 return 0;
6064         } else
6065                 return kvm_set_cr4(vcpu, val);
6066 }
6067
6068 static int handle_cr(struct kvm_vcpu *vcpu)
6069 {
6070         unsigned long exit_qualification, val;
6071         int cr;
6072         int reg;
6073         int err;
6074         int ret;
6075
6076         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6077         cr = exit_qualification & 15;
6078         reg = (exit_qualification >> 8) & 15;
6079         switch ((exit_qualification >> 4) & 3) {
6080         case 0: /* mov to cr */
6081                 val = kvm_register_readl(vcpu, reg);
6082                 trace_kvm_cr_write(cr, val);
6083                 switch (cr) {
6084                 case 0:
6085                         err = handle_set_cr0(vcpu, val);
6086                         return kvm_complete_insn_gp(vcpu, err);
6087                 case 3:
6088                         err = kvm_set_cr3(vcpu, val);
6089                         return kvm_complete_insn_gp(vcpu, err);
6090                 case 4:
6091                         err = handle_set_cr4(vcpu, val);
6092                         return kvm_complete_insn_gp(vcpu, err);
6093                 case 8: {
6094                                 u8 cr8_prev = kvm_get_cr8(vcpu);
6095                                 u8 cr8 = (u8)val;
6096                                 err = kvm_set_cr8(vcpu, cr8);
6097                                 ret = kvm_complete_insn_gp(vcpu, err);
6098                                 if (lapic_in_kernel(vcpu))
6099                                         return ret;
6100                                 if (cr8_prev <= cr8)
6101                                         return ret;
6102                                 /*
6103                                  * TODO: we might be squashing a
6104                                  * KVM_GUESTDBG_SINGLESTEP-triggered
6105                                  * KVM_EXIT_DEBUG here.
6106                                  */
6107                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
6108                                 return 0;
6109                         }
6110                 }
6111                 break;
6112         case 2: /* clts */
6113                 WARN_ONCE(1, "Guest should always own CR0.TS");
6114                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6115                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6116                 return kvm_skip_emulated_instruction(vcpu);
6117         case 1: /*mov from cr*/
6118                 switch (cr) {
6119                 case 3:
6120                         val = kvm_read_cr3(vcpu);
6121                         kvm_register_write(vcpu, reg, val);
6122                         trace_kvm_cr_read(cr, val);
6123                         return kvm_skip_emulated_instruction(vcpu);
6124                 case 8:
6125                         val = kvm_get_cr8(vcpu);
6126                         kvm_register_write(vcpu, reg, val);
6127                         trace_kvm_cr_read(cr, val);
6128                         return kvm_skip_emulated_instruction(vcpu);
6129                 }
6130                 break;
6131         case 3: /* lmsw */
6132                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6133                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6134                 kvm_lmsw(vcpu, val);
6135
6136                 return kvm_skip_emulated_instruction(vcpu);
6137         default:
6138                 break;
6139         }
6140         vcpu->run->exit_reason = 0;
6141         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6142                (int)(exit_qualification >> 4) & 3, cr);
6143         return 0;
6144 }
6145
6146 static int handle_dr(struct kvm_vcpu *vcpu)
6147 {
6148         unsigned long exit_qualification;
6149         int dr, dr7, reg;
6150
6151         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6152         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6153
6154         /* First, if DR does not exist, trigger UD */
6155         if (!kvm_require_dr(vcpu, dr))
6156                 return 1;
6157
6158         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6159         if (!kvm_require_cpl(vcpu, 0))
6160                 return 1;
6161         dr7 = vmcs_readl(GUEST_DR7);
6162         if (dr7 & DR7_GD) {
6163                 /*
6164                  * As the vm-exit takes precedence over the debug trap, we
6165                  * need to emulate the latter, either for the host or the
6166                  * guest debugging itself.
6167                  */
6168                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6169                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6170                         vcpu->run->debug.arch.dr7 = dr7;
6171                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6172                         vcpu->run->debug.arch.exception = DB_VECTOR;
6173                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6174                         return 0;
6175                 } else {
6176                         vcpu->arch.dr6 &= ~15;
6177                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6178                         kvm_queue_exception(vcpu, DB_VECTOR);
6179                         return 1;
6180                 }
6181         }
6182
6183         if (vcpu->guest_debug == 0) {
6184                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6185                                 CPU_BASED_MOV_DR_EXITING);
6186
6187                 /*
6188                  * No more DR vmexits; force a reload of the debug registers
6189                  * and reenter on this instruction.  The next vmexit will
6190                  * retrieve the full state of the debug registers.
6191                  */
6192                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6193                 return 1;
6194         }
6195
6196         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6197         if (exit_qualification & TYPE_MOV_FROM_DR) {
6198                 unsigned long val;
6199
6200                 if (kvm_get_dr(vcpu, dr, &val))
6201                         return 1;
6202                 kvm_register_write(vcpu, reg, val);
6203         } else
6204                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6205                         return 1;
6206
6207         return kvm_skip_emulated_instruction(vcpu);
6208 }
6209
6210 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6211 {
6212         return vcpu->arch.dr6;
6213 }
6214
6215 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6216 {
6217 }
6218
6219 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6220 {
6221         get_debugreg(vcpu->arch.db[0], 0);
6222         get_debugreg(vcpu->arch.db[1], 1);
6223         get_debugreg(vcpu->arch.db[2], 2);
6224         get_debugreg(vcpu->arch.db[3], 3);
6225         get_debugreg(vcpu->arch.dr6, 6);
6226         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6227
6228         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6229         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6230 }
6231
6232 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6233 {
6234         vmcs_writel(GUEST_DR7, val);
6235 }
6236
6237 static int handle_cpuid(struct kvm_vcpu *vcpu)
6238 {
6239         return kvm_emulate_cpuid(vcpu);
6240 }
6241
6242 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6243 {
6244         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6245         struct msr_data msr_info;
6246
6247         msr_info.index = ecx;
6248         msr_info.host_initiated = false;
6249         if (vmx_get_msr(vcpu, &msr_info)) {
6250                 trace_kvm_msr_read_ex(ecx);
6251                 kvm_inject_gp(vcpu, 0);
6252                 return 1;
6253         }
6254
6255         trace_kvm_msr_read(ecx, msr_info.data);
6256
6257         /* FIXME: handling of bits 32:63 of rax, rdx */
6258         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6259         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6260         return kvm_skip_emulated_instruction(vcpu);
6261 }
6262
6263 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6264 {
6265         struct msr_data msr;
6266         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6267         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6268                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6269
6270         msr.data = data;
6271         msr.index = ecx;
6272         msr.host_initiated = false;
6273         if (kvm_set_msr(vcpu, &msr) != 0) {
6274                 trace_kvm_msr_write_ex(ecx, data);
6275                 kvm_inject_gp(vcpu, 0);
6276                 return 1;
6277         }
6278
6279         trace_kvm_msr_write(ecx, data);
6280         return kvm_skip_emulated_instruction(vcpu);
6281 }
6282
6283 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6284 {
6285         kvm_apic_update_ppr(vcpu);
6286         return 1;
6287 }
6288
6289 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6290 {
6291         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6292                         CPU_BASED_VIRTUAL_INTR_PENDING);
6293
6294         kvm_make_request(KVM_REQ_EVENT, vcpu);
6295
6296         ++vcpu->stat.irq_window_exits;
6297         return 1;
6298 }
6299
6300 static int handle_halt(struct kvm_vcpu *vcpu)
6301 {
6302         return kvm_emulate_halt(vcpu);
6303 }
6304
6305 static int handle_vmcall(struct kvm_vcpu *vcpu)
6306 {
6307         return kvm_emulate_hypercall(vcpu);
6308 }
6309
6310 static int handle_invd(struct kvm_vcpu *vcpu)
6311 {
6312         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6313 }
6314
6315 static int handle_invlpg(struct kvm_vcpu *vcpu)
6316 {
6317         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6318
6319         kvm_mmu_invlpg(vcpu, exit_qualification);
6320         return kvm_skip_emulated_instruction(vcpu);
6321 }
6322
6323 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6324 {
6325         int err;
6326
6327         err = kvm_rdpmc(vcpu);
6328         return kvm_complete_insn_gp(vcpu, err);
6329 }
6330
6331 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6332 {
6333         return kvm_emulate_wbinvd(vcpu);
6334 }
6335
6336 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6337 {
6338         u64 new_bv = kvm_read_edx_eax(vcpu);
6339         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6340
6341         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6342                 return kvm_skip_emulated_instruction(vcpu);
6343         return 1;
6344 }
6345
6346 static int handle_xsaves(struct kvm_vcpu *vcpu)
6347 {
6348         kvm_skip_emulated_instruction(vcpu);
6349         WARN(1, "this should never happen\n");
6350         return 1;
6351 }
6352
6353 static int handle_xrstors(struct kvm_vcpu *vcpu)
6354 {
6355         kvm_skip_emulated_instruction(vcpu);
6356         WARN(1, "this should never happen\n");
6357         return 1;
6358 }
6359
6360 static int handle_apic_access(struct kvm_vcpu *vcpu)
6361 {
6362         if (likely(fasteoi)) {
6363                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6364                 int access_type, offset;
6365
6366                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6367                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6368                 /*
6369                  * Sane guest uses MOV to write EOI, with written value
6370                  * not cared. So make a short-circuit here by avoiding
6371                  * heavy instruction emulation.
6372                  */
6373                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6374                     (offset == APIC_EOI)) {
6375                         kvm_lapic_set_eoi(vcpu);
6376                         return kvm_skip_emulated_instruction(vcpu);
6377                 }
6378         }
6379         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6380 }
6381
6382 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6383 {
6384         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6385         int vector = exit_qualification & 0xff;
6386
6387         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6388         kvm_apic_set_eoi_accelerated(vcpu, vector);
6389         return 1;
6390 }
6391
6392 static int handle_apic_write(struct kvm_vcpu *vcpu)
6393 {
6394         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6395         u32 offset = exit_qualification & 0xfff;
6396
6397         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6398         kvm_apic_write_nodecode(vcpu, offset);
6399         return 1;
6400 }
6401
6402 static int handle_task_switch(struct kvm_vcpu *vcpu)
6403 {
6404         struct vcpu_vmx *vmx = to_vmx(vcpu);
6405         unsigned long exit_qualification;
6406         bool has_error_code = false;
6407         u32 error_code = 0;
6408         u16 tss_selector;
6409         int reason, type, idt_v, idt_index;
6410
6411         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6412         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6413         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6414
6415         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6416
6417         reason = (u32)exit_qualification >> 30;
6418         if (reason == TASK_SWITCH_GATE && idt_v) {
6419                 switch (type) {
6420                 case INTR_TYPE_NMI_INTR:
6421                         vcpu->arch.nmi_injected = false;
6422                         vmx_set_nmi_mask(vcpu, true);
6423                         break;
6424                 case INTR_TYPE_EXT_INTR:
6425                 case INTR_TYPE_SOFT_INTR:
6426                         kvm_clear_interrupt_queue(vcpu);
6427                         break;
6428                 case INTR_TYPE_HARD_EXCEPTION:
6429                         if (vmx->idt_vectoring_info &
6430                             VECTORING_INFO_DELIVER_CODE_MASK) {
6431                                 has_error_code = true;
6432                                 error_code =
6433                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6434                         }
6435                         /* fall through */
6436                 case INTR_TYPE_SOFT_EXCEPTION:
6437                         kvm_clear_exception_queue(vcpu);
6438                         break;
6439                 default:
6440                         break;
6441                 }
6442         }
6443         tss_selector = exit_qualification;
6444
6445         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6446                        type != INTR_TYPE_EXT_INTR &&
6447                        type != INTR_TYPE_NMI_INTR))
6448                 skip_emulated_instruction(vcpu);
6449
6450         if (kvm_task_switch(vcpu, tss_selector,
6451                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6452                             has_error_code, error_code) == EMULATE_FAIL) {
6453                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6454                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6455                 vcpu->run->internal.ndata = 0;
6456                 return 0;
6457         }
6458
6459         /*
6460          * TODO: What about debug traps on tss switch?
6461          *       Are we supposed to inject them and update dr6?
6462          */
6463
6464         return 1;
6465 }
6466
6467 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6468 {
6469         unsigned long exit_qualification;
6470         gpa_t gpa;
6471         u64 error_code;
6472
6473         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6474
6475         /*
6476          * EPT violation happened while executing iret from NMI,
6477          * "blocked by NMI" bit has to be set before next VM entry.
6478          * There are errata that may cause this bit to not be set:
6479          * AAK134, BY25.
6480          */
6481         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6482                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6483                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6484
6485         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6486         trace_kvm_page_fault(gpa, exit_qualification);
6487
6488         /* Is it a read fault? */
6489         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6490                      ? PFERR_USER_MASK : 0;
6491         /* Is it a write fault? */
6492         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6493                       ? PFERR_WRITE_MASK : 0;
6494         /* Is it a fetch fault? */
6495         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6496                       ? PFERR_FETCH_MASK : 0;
6497         /* ept page table entry is present? */
6498         error_code |= (exit_qualification &
6499                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6500                         EPT_VIOLATION_EXECUTABLE))
6501                       ? PFERR_PRESENT_MASK : 0;
6502
6503         error_code |= (exit_qualification & 0x100) != 0 ?
6504                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
6505
6506         vcpu->arch.exit_qualification = exit_qualification;
6507         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6508 }
6509
6510 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6511 {
6512         int ret;
6513         gpa_t gpa;
6514
6515         /*
6516          * A nested guest cannot optimize MMIO vmexits, because we have an
6517          * nGPA here instead of the required GPA.
6518          */
6519         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6520         if (!is_guest_mode(vcpu) &&
6521             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6522                 trace_kvm_fast_mmio(gpa);
6523                 return kvm_skip_emulated_instruction(vcpu);
6524         }
6525
6526         ret = kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
6527         if (ret >= 0)
6528                 return ret;
6529
6530         /* It is the real ept misconfig */
6531         WARN_ON(1);
6532
6533         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6534         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6535
6536         return 0;
6537 }
6538
6539 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6540 {
6541         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6542                         CPU_BASED_VIRTUAL_NMI_PENDING);
6543         ++vcpu->stat.nmi_window_exits;
6544         kvm_make_request(KVM_REQ_EVENT, vcpu);
6545
6546         return 1;
6547 }
6548
6549 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6550 {
6551         struct vcpu_vmx *vmx = to_vmx(vcpu);
6552         enum emulation_result err = EMULATE_DONE;
6553         int ret = 1;
6554         u32 cpu_exec_ctrl;
6555         bool intr_window_requested;
6556         unsigned count = 130;
6557
6558         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6559         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6560
6561         while (vmx->emulation_required && count-- != 0) {
6562                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6563                         return handle_interrupt_window(&vmx->vcpu);
6564
6565                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
6566                         return 1;
6567
6568                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6569
6570                 if (err == EMULATE_USER_EXIT) {
6571                         ++vcpu->stat.mmio_exits;
6572                         ret = 0;
6573                         goto out;
6574                 }
6575
6576                 if (err != EMULATE_DONE) {
6577                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6578                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6579                         vcpu->run->internal.ndata = 0;
6580                         return 0;
6581                 }
6582
6583                 if (vcpu->arch.halt_request) {
6584                         vcpu->arch.halt_request = 0;
6585                         ret = kvm_vcpu_halt(vcpu);
6586                         goto out;
6587                 }
6588
6589                 if (signal_pending(current))
6590                         goto out;
6591                 if (need_resched())
6592                         schedule();
6593         }
6594
6595 out:
6596         return ret;
6597 }
6598
6599 static int __grow_ple_window(int val)
6600 {
6601         if (ple_window_grow < 1)
6602                 return ple_window;
6603
6604         val = min(val, ple_window_actual_max);
6605
6606         if (ple_window_grow < ple_window)
6607                 val *= ple_window_grow;
6608         else
6609                 val += ple_window_grow;
6610
6611         return val;
6612 }
6613
6614 static int __shrink_ple_window(int val, int modifier, int minimum)
6615 {
6616         if (modifier < 1)
6617                 return ple_window;
6618
6619         if (modifier < ple_window)
6620                 val /= modifier;
6621         else
6622                 val -= modifier;
6623
6624         return max(val, minimum);
6625 }
6626
6627 static void grow_ple_window(struct kvm_vcpu *vcpu)
6628 {
6629         struct vcpu_vmx *vmx = to_vmx(vcpu);
6630         int old = vmx->ple_window;
6631
6632         vmx->ple_window = __grow_ple_window(old);
6633
6634         if (vmx->ple_window != old)
6635                 vmx->ple_window_dirty = true;
6636
6637         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6638 }
6639
6640 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6641 {
6642         struct vcpu_vmx *vmx = to_vmx(vcpu);
6643         int old = vmx->ple_window;
6644
6645         vmx->ple_window = __shrink_ple_window(old,
6646                                               ple_window_shrink, ple_window);
6647
6648         if (vmx->ple_window != old)
6649                 vmx->ple_window_dirty = true;
6650
6651         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6652 }
6653
6654 /*
6655  * ple_window_actual_max is computed to be one grow_ple_window() below
6656  * ple_window_max. (See __grow_ple_window for the reason.)
6657  * This prevents overflows, because ple_window_max is int.
6658  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6659  * this process.
6660  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6661  */
6662 static void update_ple_window_actual_max(void)
6663 {
6664         ple_window_actual_max =
6665                         __shrink_ple_window(max(ple_window_max, ple_window),
6666                                             ple_window_grow, INT_MIN);
6667 }
6668
6669 /*
6670  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6671  */
6672 static void wakeup_handler(void)
6673 {
6674         struct kvm_vcpu *vcpu;
6675         int cpu = smp_processor_id();
6676
6677         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6678         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6679                         blocked_vcpu_list) {
6680                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6681
6682                 if (pi_test_on(pi_desc) == 1)
6683                         kvm_vcpu_kick(vcpu);
6684         }
6685         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6686 }
6687
6688 void vmx_enable_tdp(void)
6689 {
6690         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6691                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6692                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6693                 0ull, VMX_EPT_EXECUTABLE_MASK,
6694                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6695                 VMX_EPT_RWX_MASK, 0ull);
6696
6697         ept_set_mmio_spte_mask();
6698         kvm_enable_tdp();
6699 }
6700
6701 static __init int hardware_setup(void)
6702 {
6703         int r = -ENOMEM, i, msr;
6704
6705         rdmsrl_safe(MSR_EFER, &host_efer);
6706
6707         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6708                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6709
6710         for (i = 0; i < VMX_BITMAP_NR; i++) {
6711                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6712                 if (!vmx_bitmap[i])
6713                         goto out;
6714         }
6715
6716         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6717         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6718         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6719
6720         /*
6721          * Allow direct access to the PC debug port (it is often used for I/O
6722          * delays, but the vmexits simply slow things down).
6723          */
6724         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6725         clear_bit(0x80, vmx_io_bitmap_a);
6726
6727         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6728
6729         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6730         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6731
6732         if (setup_vmcs_config(&vmcs_config) < 0) {
6733                 r = -EIO;
6734                 goto out;
6735         }
6736
6737         if (boot_cpu_has(X86_FEATURE_NX))
6738                 kvm_enable_efer_bits(EFER_NX);
6739
6740         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6741                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6742                 enable_vpid = 0;
6743
6744         if (!cpu_has_vmx_shadow_vmcs())
6745                 enable_shadow_vmcs = 0;
6746         if (enable_shadow_vmcs)
6747                 init_vmcs_shadow_fields();
6748
6749         if (!cpu_has_vmx_ept() ||
6750             !cpu_has_vmx_ept_4levels() ||
6751             !cpu_has_vmx_ept_mt_wb()) {
6752                 enable_ept = 0;
6753                 enable_unrestricted_guest = 0;
6754                 enable_ept_ad_bits = 0;
6755         }
6756
6757         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
6758                 enable_ept_ad_bits = 0;
6759
6760         if (!cpu_has_vmx_unrestricted_guest())
6761                 enable_unrestricted_guest = 0;
6762
6763         if (!cpu_has_vmx_flexpriority())
6764                 flexpriority_enabled = 0;
6765
6766         /*
6767          * set_apic_access_page_addr() is used to reload apic access
6768          * page upon invalidation.  No need to do anything if not
6769          * using the APIC_ACCESS_ADDR VMCS field.
6770          */
6771         if (!flexpriority_enabled)
6772                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6773
6774         if (!cpu_has_vmx_tpr_shadow())
6775                 kvm_x86_ops->update_cr8_intercept = NULL;
6776
6777         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6778                 kvm_disable_largepages();
6779
6780         if (!cpu_has_vmx_ple())
6781                 ple_gap = 0;
6782
6783         if (!cpu_has_vmx_apicv()) {
6784                 enable_apicv = 0;
6785                 kvm_x86_ops->sync_pir_to_irr = NULL;
6786         }
6787
6788         if (cpu_has_vmx_tsc_scaling()) {
6789                 kvm_has_tsc_control = true;
6790                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6791                 kvm_tsc_scaling_ratio_frac_bits = 48;
6792         }
6793
6794         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6795         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6796         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6797         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6798         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6799         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6800
6801         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6802                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6803         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6804                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6805         memcpy(vmx_msr_bitmap_legacy_x2apic,
6806                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6807         memcpy(vmx_msr_bitmap_longmode_x2apic,
6808                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6809
6810         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6811
6812         for (msr = 0x800; msr <= 0x8ff; msr++) {
6813                 if (msr == 0x839 /* TMCCT */)
6814                         continue;
6815                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6816         }
6817
6818         /*
6819          * TPR reads and writes can be virtualized even if virtual interrupt
6820          * delivery is not in use.
6821          */
6822         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6823         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6824
6825         /* EOI */
6826         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6827         /* SELF-IPI */
6828         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6829
6830         if (enable_ept)
6831                 vmx_enable_tdp();
6832         else
6833                 kvm_disable_tdp();
6834
6835         update_ple_window_actual_max();
6836
6837         /*
6838          * Only enable PML when hardware supports PML feature, and both EPT
6839          * and EPT A/D bit features are enabled -- PML depends on them to work.
6840          */
6841         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6842                 enable_pml = 0;
6843
6844         if (!enable_pml) {
6845                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6846                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6847                 kvm_x86_ops->flush_log_dirty = NULL;
6848                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6849         }
6850
6851         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6852                 u64 vmx_msr;
6853
6854                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6855                 cpu_preemption_timer_multi =
6856                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6857         } else {
6858                 kvm_x86_ops->set_hv_timer = NULL;
6859                 kvm_x86_ops->cancel_hv_timer = NULL;
6860         }
6861
6862         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6863
6864         kvm_mce_cap_supported |= MCG_LMCE_P;
6865
6866         return alloc_kvm_area();
6867
6868 out:
6869         for (i = 0; i < VMX_BITMAP_NR; i++)
6870                 free_page((unsigned long)vmx_bitmap[i]);
6871
6872     return r;
6873 }
6874
6875 static __exit void hardware_unsetup(void)
6876 {
6877         int i;
6878
6879         for (i = 0; i < VMX_BITMAP_NR; i++)
6880                 free_page((unsigned long)vmx_bitmap[i]);
6881
6882         free_kvm_area();
6883 }
6884
6885 /*
6886  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6887  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6888  */
6889 static int handle_pause(struct kvm_vcpu *vcpu)
6890 {
6891         if (ple_gap)
6892                 grow_ple_window(vcpu);
6893
6894         /*
6895          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
6896          * VM-execution control is ignored if CPL > 0. OTOH, KVM
6897          * never set PAUSE_EXITING and just set PLE if supported,
6898          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
6899          */
6900         kvm_vcpu_on_spin(vcpu, true);
6901         return kvm_skip_emulated_instruction(vcpu);
6902 }
6903
6904 static int handle_nop(struct kvm_vcpu *vcpu)
6905 {
6906         return kvm_skip_emulated_instruction(vcpu);
6907 }
6908
6909 static int handle_mwait(struct kvm_vcpu *vcpu)
6910 {
6911         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6912         return handle_nop(vcpu);
6913 }
6914
6915 static int handle_invalid_op(struct kvm_vcpu *vcpu)
6916 {
6917         kvm_queue_exception(vcpu, UD_VECTOR);
6918         return 1;
6919 }
6920
6921 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6922 {
6923         return 1;
6924 }
6925
6926 static int handle_monitor(struct kvm_vcpu *vcpu)
6927 {
6928         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6929         return handle_nop(vcpu);
6930 }
6931
6932 /*
6933  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6934  * We could reuse a single VMCS for all the L2 guests, but we also want the
6935  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6936  * allows keeping them loaded on the processor, and in the future will allow
6937  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6938  * every entry if they never change.
6939  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6940  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6941  *
6942  * The following functions allocate and free a vmcs02 in this pool.
6943  */
6944
6945 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6946 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6947 {
6948         struct vmcs02_list *item;
6949         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6950                 if (item->vmptr == vmx->nested.current_vmptr) {
6951                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6952                         return &item->vmcs02;
6953                 }
6954
6955         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6956                 /* Recycle the least recently used VMCS. */
6957                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6958                                        struct vmcs02_list, list);
6959                 item->vmptr = vmx->nested.current_vmptr;
6960                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6961                 return &item->vmcs02;
6962         }
6963
6964         /* Create a new VMCS */
6965         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6966         if (!item)
6967                 return NULL;
6968         item->vmcs02.vmcs = alloc_vmcs();
6969         item->vmcs02.shadow_vmcs = NULL;
6970         if (!item->vmcs02.vmcs) {
6971                 kfree(item);
6972                 return NULL;
6973         }
6974         loaded_vmcs_init(&item->vmcs02);
6975         item->vmptr = vmx->nested.current_vmptr;
6976         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6977         vmx->nested.vmcs02_num++;
6978         return &item->vmcs02;
6979 }
6980
6981 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6982 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6983 {
6984         struct vmcs02_list *item;
6985         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6986                 if (item->vmptr == vmptr) {
6987                         free_loaded_vmcs(&item->vmcs02);
6988                         list_del(&item->list);
6989                         kfree(item);
6990                         vmx->nested.vmcs02_num--;
6991                         return;
6992                 }
6993 }
6994
6995 /*
6996  * Free all VMCSs saved for this vcpu, except the one pointed by
6997  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6998  * must be &vmx->vmcs01.
6999  */
7000 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
7001 {
7002         struct vmcs02_list *item, *n;
7003
7004         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
7005         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
7006                 /*
7007                  * Something will leak if the above WARN triggers.  Better than
7008                  * a use-after-free.
7009                  */
7010                 if (vmx->loaded_vmcs == &item->vmcs02)
7011                         continue;
7012
7013                 free_loaded_vmcs(&item->vmcs02);
7014                 list_del(&item->list);
7015                 kfree(item);
7016                 vmx->nested.vmcs02_num--;
7017         }
7018 }
7019
7020 /*
7021  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7022  * set the success or error code of an emulated VMX instruction, as specified
7023  * by Vol 2B, VMX Instruction Reference, "Conventions".
7024  */
7025 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
7026 {
7027         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
7028                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7029                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
7030 }
7031
7032 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
7033 {
7034         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7035                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
7036                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7037                         | X86_EFLAGS_CF);
7038 }
7039
7040 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
7041                                         u32 vm_instruction_error)
7042 {
7043         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
7044                 /*
7045                  * failValid writes the error number to the current VMCS, which
7046                  * can't be done there isn't a current VMCS.
7047                  */
7048                 nested_vmx_failInvalid(vcpu);
7049                 return;
7050         }
7051         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7052                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7053                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7054                         | X86_EFLAGS_ZF);
7055         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
7056         /*
7057          * We don't need to force a shadow sync because
7058          * VM_INSTRUCTION_ERROR is not shadowed
7059          */
7060 }
7061
7062 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
7063 {
7064         /* TODO: not to reset guest simply here. */
7065         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7066         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
7067 }
7068
7069 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
7070 {
7071         struct vcpu_vmx *vmx =
7072                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
7073
7074         vmx->nested.preemption_timer_expired = true;
7075         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
7076         kvm_vcpu_kick(&vmx->vcpu);
7077
7078         return HRTIMER_NORESTART;
7079 }
7080
7081 /*
7082  * Decode the memory-address operand of a vmx instruction, as recorded on an
7083  * exit caused by such an instruction (run by a guest hypervisor).
7084  * On success, returns 0. When the operand is invalid, returns 1 and throws
7085  * #UD or #GP.
7086  */
7087 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
7088                                  unsigned long exit_qualification,
7089                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
7090 {
7091         gva_t off;
7092         bool exn;
7093         struct kvm_segment s;
7094
7095         /*
7096          * According to Vol. 3B, "Information for VM Exits Due to Instruction
7097          * Execution", on an exit, vmx_instruction_info holds most of the
7098          * addressing components of the operand. Only the displacement part
7099          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7100          * For how an actual address is calculated from all these components,
7101          * refer to Vol. 1, "Operand Addressing".
7102          */
7103         int  scaling = vmx_instruction_info & 3;
7104         int  addr_size = (vmx_instruction_info >> 7) & 7;
7105         bool is_reg = vmx_instruction_info & (1u << 10);
7106         int  seg_reg = (vmx_instruction_info >> 15) & 7;
7107         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
7108         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
7109         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
7110         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
7111
7112         if (is_reg) {
7113                 kvm_queue_exception(vcpu, UD_VECTOR);
7114                 return 1;
7115         }
7116
7117         /* Addr = segment_base + offset */
7118         /* offset = base + [index * scale] + displacement */
7119         off = exit_qualification; /* holds the displacement */
7120         if (base_is_valid)
7121                 off += kvm_register_read(vcpu, base_reg);
7122         if (index_is_valid)
7123                 off += kvm_register_read(vcpu, index_reg)<<scaling;
7124         vmx_get_segment(vcpu, &s, seg_reg);
7125         *ret = s.base + off;
7126
7127         if (addr_size == 1) /* 32 bit */
7128                 *ret &= 0xffffffff;
7129
7130         /* Checks for #GP/#SS exceptions. */
7131         exn = false;
7132         if (is_long_mode(vcpu)) {
7133                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7134                  * non-canonical form. This is the only check on the memory
7135                  * destination for long mode!
7136                  */
7137                 exn = is_noncanonical_address(*ret, vcpu);
7138         } else if (is_protmode(vcpu)) {
7139                 /* Protected mode: apply checks for segment validity in the
7140                  * following order:
7141                  * - segment type check (#GP(0) may be thrown)
7142                  * - usability check (#GP(0)/#SS(0))
7143                  * - limit check (#GP(0)/#SS(0))
7144                  */
7145                 if (wr)
7146                         /* #GP(0) if the destination operand is located in a
7147                          * read-only data segment or any code segment.
7148                          */
7149                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
7150                 else
7151                         /* #GP(0) if the source operand is located in an
7152                          * execute-only code segment
7153                          */
7154                         exn = ((s.type & 0xa) == 8);
7155                 if (exn) {
7156                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7157                         return 1;
7158                 }
7159                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7160                  */
7161                 exn = (s.unusable != 0);
7162                 /* Protected mode: #GP(0)/#SS(0) if the memory
7163                  * operand is outside the segment limit.
7164                  */
7165                 exn = exn || (off + sizeof(u64) > s.limit);
7166         }
7167         if (exn) {
7168                 kvm_queue_exception_e(vcpu,
7169                                       seg_reg == VCPU_SREG_SS ?
7170                                                 SS_VECTOR : GP_VECTOR,
7171                                       0);
7172                 return 1;
7173         }
7174
7175         return 0;
7176 }
7177
7178 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7179 {
7180         gva_t gva;
7181         struct x86_exception e;
7182
7183         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7184                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7185                 return 1;
7186
7187         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
7188                                 sizeof(*vmpointer), &e)) {
7189                 kvm_inject_page_fault(vcpu, &e);
7190                 return 1;
7191         }
7192
7193         return 0;
7194 }
7195
7196 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7197 {
7198         struct vcpu_vmx *vmx = to_vmx(vcpu);
7199         struct vmcs *shadow_vmcs;
7200
7201         if (cpu_has_vmx_msr_bitmap()) {
7202                 vmx->nested.msr_bitmap =
7203                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7204                 if (!vmx->nested.msr_bitmap)
7205                         goto out_msr_bitmap;
7206         }
7207
7208         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7209         if (!vmx->nested.cached_vmcs12)
7210                 goto out_cached_vmcs12;
7211
7212         if (enable_shadow_vmcs) {
7213                 shadow_vmcs = alloc_vmcs();
7214                 if (!shadow_vmcs)
7215                         goto out_shadow_vmcs;
7216                 /* mark vmcs as shadow */
7217                 shadow_vmcs->revision_id |= (1u << 31);
7218                 /* init shadow vmcs */
7219                 vmcs_clear(shadow_vmcs);
7220                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7221         }
7222
7223         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7224         vmx->nested.vmcs02_num = 0;
7225
7226         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7227                      HRTIMER_MODE_REL_PINNED);
7228         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7229
7230         vmx->nested.vmxon = true;
7231         return 0;
7232
7233 out_shadow_vmcs:
7234         kfree(vmx->nested.cached_vmcs12);
7235
7236 out_cached_vmcs12:
7237         free_page((unsigned long)vmx->nested.msr_bitmap);
7238
7239 out_msr_bitmap:
7240         return -ENOMEM;
7241 }
7242
7243 /*
7244  * Emulate the VMXON instruction.
7245  * Currently, we just remember that VMX is active, and do not save or even
7246  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7247  * do not currently need to store anything in that guest-allocated memory
7248  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7249  * argument is different from the VMXON pointer (which the spec says they do).
7250  */
7251 static int handle_vmon(struct kvm_vcpu *vcpu)
7252 {
7253         int ret;
7254         gpa_t vmptr;
7255         struct page *page;
7256         struct vcpu_vmx *vmx = to_vmx(vcpu);
7257         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7258                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7259
7260         /*
7261          * The Intel VMX Instruction Reference lists a bunch of bits that are
7262          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7263          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7264          * Otherwise, we should fail with #UD.  But most faulting conditions
7265          * have already been checked by hardware, prior to the VM-exit for
7266          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
7267          * that bit set to 1 in non-root mode.
7268          */
7269         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7270                 kvm_queue_exception(vcpu, UD_VECTOR);
7271                 return 1;
7272         }
7273
7274         if (vmx->nested.vmxon) {
7275                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7276                 return kvm_skip_emulated_instruction(vcpu);
7277         }
7278
7279         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7280                         != VMXON_NEEDED_FEATURES) {
7281                 kvm_inject_gp(vcpu, 0);
7282                 return 1;
7283         }
7284
7285         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7286                 return 1;
7287
7288         /*
7289          * SDM 3: 24.11.5
7290          * The first 4 bytes of VMXON region contain the supported
7291          * VMCS revision identifier
7292          *
7293          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7294          * which replaces physical address width with 32
7295          */
7296         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7297                 nested_vmx_failInvalid(vcpu);
7298                 return kvm_skip_emulated_instruction(vcpu);
7299         }
7300
7301         page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7302         if (is_error_page(page)) {
7303                 nested_vmx_failInvalid(vcpu);
7304                 return kvm_skip_emulated_instruction(vcpu);
7305         }
7306         if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7307                 kunmap(page);
7308                 kvm_release_page_clean(page);
7309                 nested_vmx_failInvalid(vcpu);
7310                 return kvm_skip_emulated_instruction(vcpu);
7311         }
7312         kunmap(page);
7313         kvm_release_page_clean(page);
7314
7315         vmx->nested.vmxon_ptr = vmptr;
7316         ret = enter_vmx_operation(vcpu);
7317         if (ret)
7318                 return ret;
7319
7320         nested_vmx_succeed(vcpu);
7321         return kvm_skip_emulated_instruction(vcpu);
7322 }
7323
7324 /*
7325  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7326  * for running VMX instructions (except VMXON, whose prerequisites are
7327  * slightly different). It also specifies what exception to inject otherwise.
7328  * Note that many of these exceptions have priority over VM exits, so they
7329  * don't have to be checked again here.
7330  */
7331 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7332 {
7333         if (!to_vmx(vcpu)->nested.vmxon) {
7334                 kvm_queue_exception(vcpu, UD_VECTOR);
7335                 return 0;
7336         }
7337         return 1;
7338 }
7339
7340 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
7341 {
7342         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
7343         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7344 }
7345
7346 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7347 {
7348         if (vmx->nested.current_vmptr == -1ull)
7349                 return;
7350
7351         if (enable_shadow_vmcs) {
7352                 /* copy to memory all shadowed fields in case
7353                    they were modified */
7354                 copy_shadow_to_vmcs12(vmx);
7355                 vmx->nested.sync_shadow_vmcs = false;
7356                 vmx_disable_shadow_vmcs(vmx);
7357         }
7358         vmx->nested.posted_intr_nv = -1;
7359
7360         /* Flush VMCS12 to guest memory */
7361         kvm_vcpu_write_guest_page(&vmx->vcpu,
7362                                   vmx->nested.current_vmptr >> PAGE_SHIFT,
7363                                   vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
7364
7365         vmx->nested.current_vmptr = -1ull;
7366 }
7367
7368 /*
7369  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7370  * just stops using VMX.
7371  */
7372 static void free_nested(struct vcpu_vmx *vmx)
7373 {
7374         if (!vmx->nested.vmxon)
7375                 return;
7376
7377         vmx->nested.vmxon = false;
7378         free_vpid(vmx->nested.vpid02);
7379         vmx->nested.posted_intr_nv = -1;
7380         vmx->nested.current_vmptr = -1ull;
7381         if (vmx->nested.msr_bitmap) {
7382                 free_page((unsigned long)vmx->nested.msr_bitmap);
7383                 vmx->nested.msr_bitmap = NULL;
7384         }
7385         if (enable_shadow_vmcs) {
7386                 vmx_disable_shadow_vmcs(vmx);
7387                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7388                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7389                 vmx->vmcs01.shadow_vmcs = NULL;
7390         }
7391         kfree(vmx->nested.cached_vmcs12);
7392         /* Unpin physical memory we referred to in current vmcs02 */
7393         if (vmx->nested.apic_access_page) {
7394                 kvm_release_page_dirty(vmx->nested.apic_access_page);
7395                 vmx->nested.apic_access_page = NULL;
7396         }
7397         if (vmx->nested.virtual_apic_page) {
7398                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
7399                 vmx->nested.virtual_apic_page = NULL;
7400         }
7401         if (vmx->nested.pi_desc_page) {
7402                 kunmap(vmx->nested.pi_desc_page);
7403                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
7404                 vmx->nested.pi_desc_page = NULL;
7405                 vmx->nested.pi_desc = NULL;
7406         }
7407
7408         nested_free_all_saved_vmcss(vmx);
7409 }
7410
7411 /* Emulate the VMXOFF instruction */
7412 static int handle_vmoff(struct kvm_vcpu *vcpu)
7413 {
7414         if (!nested_vmx_check_permission(vcpu))
7415                 return 1;
7416         free_nested(to_vmx(vcpu));
7417         nested_vmx_succeed(vcpu);
7418         return kvm_skip_emulated_instruction(vcpu);
7419 }
7420
7421 /* Emulate the VMCLEAR instruction */
7422 static int handle_vmclear(struct kvm_vcpu *vcpu)
7423 {
7424         struct vcpu_vmx *vmx = to_vmx(vcpu);
7425         u32 zero = 0;
7426         gpa_t vmptr;
7427
7428         if (!nested_vmx_check_permission(vcpu))
7429                 return 1;
7430
7431         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7432                 return 1;
7433
7434         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7435                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7436                 return kvm_skip_emulated_instruction(vcpu);
7437         }
7438
7439         if (vmptr == vmx->nested.vmxon_ptr) {
7440                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7441                 return kvm_skip_emulated_instruction(vcpu);
7442         }
7443
7444         if (vmptr == vmx->nested.current_vmptr)
7445                 nested_release_vmcs12(vmx);
7446
7447         kvm_vcpu_write_guest(vcpu,
7448                         vmptr + offsetof(struct vmcs12, launch_state),
7449                         &zero, sizeof(zero));
7450
7451         nested_free_vmcs02(vmx, vmptr);
7452
7453         nested_vmx_succeed(vcpu);
7454         return kvm_skip_emulated_instruction(vcpu);
7455 }
7456
7457 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7458
7459 /* Emulate the VMLAUNCH instruction */
7460 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7461 {
7462         return nested_vmx_run(vcpu, true);
7463 }
7464
7465 /* Emulate the VMRESUME instruction */
7466 static int handle_vmresume(struct kvm_vcpu *vcpu)
7467 {
7468
7469         return nested_vmx_run(vcpu, false);
7470 }
7471
7472 /*
7473  * Read a vmcs12 field. Since these can have varying lengths and we return
7474  * one type, we chose the biggest type (u64) and zero-extend the return value
7475  * to that size. Note that the caller, handle_vmread, might need to use only
7476  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7477  * 64-bit fields are to be returned).
7478  */
7479 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7480                                   unsigned long field, u64 *ret)
7481 {
7482         short offset = vmcs_field_to_offset(field);
7483         char *p;
7484
7485         if (offset < 0)
7486                 return offset;
7487
7488         p = ((char *)(get_vmcs12(vcpu))) + offset;
7489
7490         switch (vmcs_field_type(field)) {
7491         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7492                 *ret = *((natural_width *)p);
7493                 return 0;
7494         case VMCS_FIELD_TYPE_U16:
7495                 *ret = *((u16 *)p);
7496                 return 0;
7497         case VMCS_FIELD_TYPE_U32:
7498                 *ret = *((u32 *)p);
7499                 return 0;
7500         case VMCS_FIELD_TYPE_U64:
7501                 *ret = *((u64 *)p);
7502                 return 0;
7503         default:
7504                 WARN_ON(1);
7505                 return -ENOENT;
7506         }
7507 }
7508
7509
7510 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7511                                    unsigned long field, u64 field_value){
7512         short offset = vmcs_field_to_offset(field);
7513         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7514         if (offset < 0)
7515                 return offset;
7516
7517         switch (vmcs_field_type(field)) {
7518         case VMCS_FIELD_TYPE_U16:
7519                 *(u16 *)p = field_value;
7520                 return 0;
7521         case VMCS_FIELD_TYPE_U32:
7522                 *(u32 *)p = field_value;
7523                 return 0;
7524         case VMCS_FIELD_TYPE_U64:
7525                 *(u64 *)p = field_value;
7526                 return 0;
7527         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7528                 *(natural_width *)p = field_value;
7529                 return 0;
7530         default:
7531                 WARN_ON(1);
7532                 return -ENOENT;
7533         }
7534
7535 }
7536
7537 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7538 {
7539         int i;
7540         unsigned long field;
7541         u64 field_value;
7542         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7543         const unsigned long *fields = shadow_read_write_fields;
7544         const int num_fields = max_shadow_read_write_fields;
7545
7546         preempt_disable();
7547
7548         vmcs_load(shadow_vmcs);
7549
7550         for (i = 0; i < num_fields; i++) {
7551                 field = fields[i];
7552                 switch (vmcs_field_type(field)) {
7553                 case VMCS_FIELD_TYPE_U16:
7554                         field_value = vmcs_read16(field);
7555                         break;
7556                 case VMCS_FIELD_TYPE_U32:
7557                         field_value = vmcs_read32(field);
7558                         break;
7559                 case VMCS_FIELD_TYPE_U64:
7560                         field_value = vmcs_read64(field);
7561                         break;
7562                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7563                         field_value = vmcs_readl(field);
7564                         break;
7565                 default:
7566                         WARN_ON(1);
7567                         continue;
7568                 }
7569                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7570         }
7571
7572         vmcs_clear(shadow_vmcs);
7573         vmcs_load(vmx->loaded_vmcs->vmcs);
7574
7575         preempt_enable();
7576 }
7577
7578 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7579 {
7580         const unsigned long *fields[] = {
7581                 shadow_read_write_fields,
7582                 shadow_read_only_fields
7583         };
7584         const int max_fields[] = {
7585                 max_shadow_read_write_fields,
7586                 max_shadow_read_only_fields
7587         };
7588         int i, q;
7589         unsigned long field;
7590         u64 field_value = 0;
7591         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7592
7593         vmcs_load(shadow_vmcs);
7594
7595         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7596                 for (i = 0; i < max_fields[q]; i++) {
7597                         field = fields[q][i];
7598                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7599
7600                         switch (vmcs_field_type(field)) {
7601                         case VMCS_FIELD_TYPE_U16:
7602                                 vmcs_write16(field, (u16)field_value);
7603                                 break;
7604                         case VMCS_FIELD_TYPE_U32:
7605                                 vmcs_write32(field, (u32)field_value);
7606                                 break;
7607                         case VMCS_FIELD_TYPE_U64:
7608                                 vmcs_write64(field, (u64)field_value);
7609                                 break;
7610                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7611                                 vmcs_writel(field, (long)field_value);
7612                                 break;
7613                         default:
7614                                 WARN_ON(1);
7615                                 break;
7616                         }
7617                 }
7618         }
7619
7620         vmcs_clear(shadow_vmcs);
7621         vmcs_load(vmx->loaded_vmcs->vmcs);
7622 }
7623
7624 /*
7625  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7626  * used before) all generate the same failure when it is missing.
7627  */
7628 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7629 {
7630         struct vcpu_vmx *vmx = to_vmx(vcpu);
7631         if (vmx->nested.current_vmptr == -1ull) {
7632                 nested_vmx_failInvalid(vcpu);
7633                 return 0;
7634         }
7635         return 1;
7636 }
7637
7638 static int handle_vmread(struct kvm_vcpu *vcpu)
7639 {
7640         unsigned long field;
7641         u64 field_value;
7642         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7643         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7644         gva_t gva = 0;
7645
7646         if (!nested_vmx_check_permission(vcpu))
7647                 return 1;
7648
7649         if (!nested_vmx_check_vmcs12(vcpu))
7650                 return kvm_skip_emulated_instruction(vcpu);
7651
7652         /* Decode instruction info and find the field to read */
7653         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7654         /* Read the field, zero-extended to a u64 field_value */
7655         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7656                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7657                 return kvm_skip_emulated_instruction(vcpu);
7658         }
7659         /*
7660          * Now copy part of this value to register or memory, as requested.
7661          * Note that the number of bits actually copied is 32 or 64 depending
7662          * on the guest's mode (32 or 64 bit), not on the given field's length.
7663          */
7664         if (vmx_instruction_info & (1u << 10)) {
7665                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7666                         field_value);
7667         } else {
7668                 if (get_vmx_mem_address(vcpu, exit_qualification,
7669                                 vmx_instruction_info, true, &gva))
7670                         return 1;
7671                 /* _system ok, as hardware has verified cpl=0 */
7672                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7673                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7674         }
7675
7676         nested_vmx_succeed(vcpu);
7677         return kvm_skip_emulated_instruction(vcpu);
7678 }
7679
7680
7681 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7682 {
7683         unsigned long field;
7684         gva_t gva;
7685         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7686         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7687         /* The value to write might be 32 or 64 bits, depending on L1's long
7688          * mode, and eventually we need to write that into a field of several
7689          * possible lengths. The code below first zero-extends the value to 64
7690          * bit (field_value), and then copies only the appropriate number of
7691          * bits into the vmcs12 field.
7692          */
7693         u64 field_value = 0;
7694         struct x86_exception e;
7695
7696         if (!nested_vmx_check_permission(vcpu))
7697                 return 1;
7698
7699         if (!nested_vmx_check_vmcs12(vcpu))
7700                 return kvm_skip_emulated_instruction(vcpu);
7701
7702         if (vmx_instruction_info & (1u << 10))
7703                 field_value = kvm_register_readl(vcpu,
7704                         (((vmx_instruction_info) >> 3) & 0xf));
7705         else {
7706                 if (get_vmx_mem_address(vcpu, exit_qualification,
7707                                 vmx_instruction_info, false, &gva))
7708                         return 1;
7709                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7710                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7711                         kvm_inject_page_fault(vcpu, &e);
7712                         return 1;
7713                 }
7714         }
7715
7716
7717         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7718         if (vmcs_field_readonly(field)) {
7719                 nested_vmx_failValid(vcpu,
7720                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7721                 return kvm_skip_emulated_instruction(vcpu);
7722         }
7723
7724         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7725                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7726                 return kvm_skip_emulated_instruction(vcpu);
7727         }
7728
7729         nested_vmx_succeed(vcpu);
7730         return kvm_skip_emulated_instruction(vcpu);
7731 }
7732
7733 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7734 {
7735         vmx->nested.current_vmptr = vmptr;
7736         if (enable_shadow_vmcs) {
7737                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7738                               SECONDARY_EXEC_SHADOW_VMCS);
7739                 vmcs_write64(VMCS_LINK_POINTER,
7740                              __pa(vmx->vmcs01.shadow_vmcs));
7741                 vmx->nested.sync_shadow_vmcs = true;
7742         }
7743 }
7744
7745 /* Emulate the VMPTRLD instruction */
7746 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7747 {
7748         struct vcpu_vmx *vmx = to_vmx(vcpu);
7749         gpa_t vmptr;
7750
7751         if (!nested_vmx_check_permission(vcpu))
7752                 return 1;
7753
7754         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7755                 return 1;
7756
7757         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7758                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7759                 return kvm_skip_emulated_instruction(vcpu);
7760         }
7761
7762         if (vmptr == vmx->nested.vmxon_ptr) {
7763                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7764                 return kvm_skip_emulated_instruction(vcpu);
7765         }
7766
7767         if (vmx->nested.current_vmptr != vmptr) {
7768                 struct vmcs12 *new_vmcs12;
7769                 struct page *page;
7770                 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7771                 if (is_error_page(page)) {
7772                         nested_vmx_failInvalid(vcpu);
7773                         return kvm_skip_emulated_instruction(vcpu);
7774                 }
7775                 new_vmcs12 = kmap(page);
7776                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7777                         kunmap(page);
7778                         kvm_release_page_clean(page);
7779                         nested_vmx_failValid(vcpu,
7780                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7781                         return kvm_skip_emulated_instruction(vcpu);
7782                 }
7783
7784                 nested_release_vmcs12(vmx);
7785                 /*
7786                  * Load VMCS12 from guest memory since it is not already
7787                  * cached.
7788                  */
7789                 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
7790                 kunmap(page);
7791                 kvm_release_page_clean(page);
7792
7793                 set_current_vmptr(vmx, vmptr);
7794         }
7795
7796         nested_vmx_succeed(vcpu);
7797         return kvm_skip_emulated_instruction(vcpu);
7798 }
7799
7800 /* Emulate the VMPTRST instruction */
7801 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7802 {
7803         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7804         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7805         gva_t vmcs_gva;
7806         struct x86_exception e;
7807
7808         if (!nested_vmx_check_permission(vcpu))
7809                 return 1;
7810
7811         if (get_vmx_mem_address(vcpu, exit_qualification,
7812                         vmx_instruction_info, true, &vmcs_gva))
7813                 return 1;
7814         /* ok to use *_system, as hardware has verified cpl=0 */
7815         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7816                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7817                                  sizeof(u64), &e)) {
7818                 kvm_inject_page_fault(vcpu, &e);
7819                 return 1;
7820         }
7821         nested_vmx_succeed(vcpu);
7822         return kvm_skip_emulated_instruction(vcpu);
7823 }
7824
7825 /* Emulate the INVEPT instruction */
7826 static int handle_invept(struct kvm_vcpu *vcpu)
7827 {
7828         struct vcpu_vmx *vmx = to_vmx(vcpu);
7829         u32 vmx_instruction_info, types;
7830         unsigned long type;
7831         gva_t gva;
7832         struct x86_exception e;
7833         struct {
7834                 u64 eptp, gpa;
7835         } operand;
7836
7837         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7838               SECONDARY_EXEC_ENABLE_EPT) ||
7839             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7840                 kvm_queue_exception(vcpu, UD_VECTOR);
7841                 return 1;
7842         }
7843
7844         if (!nested_vmx_check_permission(vcpu))
7845                 return 1;
7846
7847         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7848         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7849
7850         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7851
7852         if (type >= 32 || !(types & (1 << type))) {
7853                 nested_vmx_failValid(vcpu,
7854                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7855                 return kvm_skip_emulated_instruction(vcpu);
7856         }
7857
7858         /* According to the Intel VMX instruction reference, the memory
7859          * operand is read even if it isn't needed (e.g., for type==global)
7860          */
7861         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7862                         vmx_instruction_info, false, &gva))
7863                 return 1;
7864         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7865                                 sizeof(operand), &e)) {
7866                 kvm_inject_page_fault(vcpu, &e);
7867                 return 1;
7868         }
7869
7870         switch (type) {
7871         case VMX_EPT_EXTENT_GLOBAL:
7872         /*
7873          * TODO: track mappings and invalidate
7874          * single context requests appropriately
7875          */
7876         case VMX_EPT_EXTENT_CONTEXT:
7877                 kvm_mmu_sync_roots(vcpu);
7878                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7879                 nested_vmx_succeed(vcpu);
7880                 break;
7881         default:
7882                 BUG_ON(1);
7883                 break;
7884         }
7885
7886         return kvm_skip_emulated_instruction(vcpu);
7887 }
7888
7889 static int handle_invvpid(struct kvm_vcpu *vcpu)
7890 {
7891         struct vcpu_vmx *vmx = to_vmx(vcpu);
7892         u32 vmx_instruction_info;
7893         unsigned long type, types;
7894         gva_t gva;
7895         struct x86_exception e;
7896         struct {
7897                 u64 vpid;
7898                 u64 gla;
7899         } operand;
7900
7901         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7902               SECONDARY_EXEC_ENABLE_VPID) ||
7903                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7904                 kvm_queue_exception(vcpu, UD_VECTOR);
7905                 return 1;
7906         }
7907
7908         if (!nested_vmx_check_permission(vcpu))
7909                 return 1;
7910
7911         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7912         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7913
7914         types = (vmx->nested.nested_vmx_vpid_caps &
7915                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7916
7917         if (type >= 32 || !(types & (1 << type))) {
7918                 nested_vmx_failValid(vcpu,
7919                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7920                 return kvm_skip_emulated_instruction(vcpu);
7921         }
7922
7923         /* according to the intel vmx instruction reference, the memory
7924          * operand is read even if it isn't needed (e.g., for type==global)
7925          */
7926         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7927                         vmx_instruction_info, false, &gva))
7928                 return 1;
7929         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7930                                 sizeof(operand), &e)) {
7931                 kvm_inject_page_fault(vcpu, &e);
7932                 return 1;
7933         }
7934         if (operand.vpid >> 16) {
7935                 nested_vmx_failValid(vcpu,
7936                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7937                 return kvm_skip_emulated_instruction(vcpu);
7938         }
7939
7940         switch (type) {
7941         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7942                 if (is_noncanonical_address(operand.gla, vcpu)) {
7943                         nested_vmx_failValid(vcpu,
7944                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7945                         return kvm_skip_emulated_instruction(vcpu);
7946                 }
7947                 /* fall through */
7948         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7949         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7950                 if (!operand.vpid) {
7951                         nested_vmx_failValid(vcpu,
7952                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7953                         return kvm_skip_emulated_instruction(vcpu);
7954                 }
7955                 break;
7956         case VMX_VPID_EXTENT_ALL_CONTEXT:
7957                 break;
7958         default:
7959                 WARN_ON_ONCE(1);
7960                 return kvm_skip_emulated_instruction(vcpu);
7961         }
7962
7963         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7964         nested_vmx_succeed(vcpu);
7965
7966         return kvm_skip_emulated_instruction(vcpu);
7967 }
7968
7969 static int handle_pml_full(struct kvm_vcpu *vcpu)
7970 {
7971         unsigned long exit_qualification;
7972
7973         trace_kvm_pml_full(vcpu->vcpu_id);
7974
7975         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7976
7977         /*
7978          * PML buffer FULL happened while executing iret from NMI,
7979          * "blocked by NMI" bit has to be set before next VM entry.
7980          */
7981         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7982                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7983                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7984                                 GUEST_INTR_STATE_NMI);
7985
7986         /*
7987          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7988          * here.., and there's no userspace involvement needed for PML.
7989          */
7990         return 1;
7991 }
7992
7993 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7994 {
7995         kvm_lapic_expired_hv_timer(vcpu);
7996         return 1;
7997 }
7998
7999 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
8000 {
8001         struct vcpu_vmx *vmx = to_vmx(vcpu);
8002         int maxphyaddr = cpuid_maxphyaddr(vcpu);
8003
8004         /* Check for memory type validity */
8005         switch (address & VMX_EPTP_MT_MASK) {
8006         case VMX_EPTP_MT_UC:
8007                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_UC_BIT))
8008                         return false;
8009                 break;
8010         case VMX_EPTP_MT_WB:
8011                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_WB_BIT))
8012                         return false;
8013                 break;
8014         default:
8015                 return false;
8016         }
8017
8018         /* only 4 levels page-walk length are valid */
8019         if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
8020                 return false;
8021
8022         /* Reserved bits should not be set */
8023         if (address >> maxphyaddr || ((address >> 7) & 0x1f))
8024                 return false;
8025
8026         /* AD, if set, should be supported */
8027         if (address & VMX_EPTP_AD_ENABLE_BIT) {
8028                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPT_AD_BIT))
8029                         return false;
8030         }
8031
8032         return true;
8033 }
8034
8035 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
8036                                      struct vmcs12 *vmcs12)
8037 {
8038         u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
8039         u64 address;
8040         bool accessed_dirty;
8041         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
8042
8043         if (!nested_cpu_has_eptp_switching(vmcs12) ||
8044             !nested_cpu_has_ept(vmcs12))
8045                 return 1;
8046
8047         if (index >= VMFUNC_EPTP_ENTRIES)
8048                 return 1;
8049
8050
8051         if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
8052                                      &address, index * 8, 8))
8053                 return 1;
8054
8055         accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
8056
8057         /*
8058          * If the (L2) guest does a vmfunc to the currently
8059          * active ept pointer, we don't have to do anything else
8060          */
8061         if (vmcs12->ept_pointer != address) {
8062                 if (!valid_ept_address(vcpu, address))
8063                         return 1;
8064
8065                 kvm_mmu_unload(vcpu);
8066                 mmu->ept_ad = accessed_dirty;
8067                 mmu->base_role.ad_disabled = !accessed_dirty;
8068                 vmcs12->ept_pointer = address;
8069                 /*
8070                  * TODO: Check what's the correct approach in case
8071                  * mmu reload fails. Currently, we just let the next
8072                  * reload potentially fail
8073                  */
8074                 kvm_mmu_reload(vcpu);
8075         }
8076
8077         return 0;
8078 }
8079
8080 static int handle_vmfunc(struct kvm_vcpu *vcpu)
8081 {
8082         struct vcpu_vmx *vmx = to_vmx(vcpu);
8083         struct vmcs12 *vmcs12;
8084         u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
8085
8086         /*
8087          * VMFUNC is only supported for nested guests, but we always enable the
8088          * secondary control for simplicity; for non-nested mode, fake that we
8089          * didn't by injecting #UD.
8090          */
8091         if (!is_guest_mode(vcpu)) {
8092                 kvm_queue_exception(vcpu, UD_VECTOR);
8093                 return 1;
8094         }
8095
8096         vmcs12 = get_vmcs12(vcpu);
8097         if ((vmcs12->vm_function_control & (1 << function)) == 0)
8098                 goto fail;
8099
8100         switch (function) {
8101         case 0:
8102                 if (nested_vmx_eptp_switching(vcpu, vmcs12))
8103                         goto fail;
8104                 break;
8105         default:
8106                 goto fail;
8107         }
8108         return kvm_skip_emulated_instruction(vcpu);
8109
8110 fail:
8111         nested_vmx_vmexit(vcpu, vmx->exit_reason,
8112                           vmcs_read32(VM_EXIT_INTR_INFO),
8113                           vmcs_readl(EXIT_QUALIFICATION));
8114         return 1;
8115 }
8116
8117 /*
8118  * The exit handlers return 1 if the exit was handled fully and guest execution
8119  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
8120  * to be done to userspace and return 0.
8121  */
8122 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
8123         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
8124         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
8125         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
8126         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
8127         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
8128         [EXIT_REASON_CR_ACCESS]               = handle_cr,
8129         [EXIT_REASON_DR_ACCESS]               = handle_dr,
8130         [EXIT_REASON_CPUID]                   = handle_cpuid,
8131         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
8132         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
8133         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
8134         [EXIT_REASON_HLT]                     = handle_halt,
8135         [EXIT_REASON_INVD]                    = handle_invd,
8136         [EXIT_REASON_INVLPG]                  = handle_invlpg,
8137         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
8138         [EXIT_REASON_VMCALL]                  = handle_vmcall,
8139         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
8140         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
8141         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
8142         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
8143         [EXIT_REASON_VMREAD]                  = handle_vmread,
8144         [EXIT_REASON_VMRESUME]                = handle_vmresume,
8145         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
8146         [EXIT_REASON_VMOFF]                   = handle_vmoff,
8147         [EXIT_REASON_VMON]                    = handle_vmon,
8148         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
8149         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
8150         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
8151         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
8152         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
8153         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
8154         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
8155         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
8156         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
8157         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
8158         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
8159         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
8160         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
8161         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
8162         [EXIT_REASON_INVEPT]                  = handle_invept,
8163         [EXIT_REASON_INVVPID]                 = handle_invvpid,
8164         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
8165         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
8166         [EXIT_REASON_XSAVES]                  = handle_xsaves,
8167         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
8168         [EXIT_REASON_PML_FULL]                = handle_pml_full,
8169         [EXIT_REASON_VMFUNC]                  = handle_vmfunc,
8170         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
8171 };
8172
8173 static const int kvm_vmx_max_exit_handlers =
8174         ARRAY_SIZE(kvm_vmx_exit_handlers);
8175
8176 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
8177                                        struct vmcs12 *vmcs12)
8178 {
8179         unsigned long exit_qualification;
8180         gpa_t bitmap, last_bitmap;
8181         unsigned int port;
8182         int size;
8183         u8 b;
8184
8185         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
8186                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
8187
8188         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8189
8190         port = exit_qualification >> 16;
8191         size = (exit_qualification & 7) + 1;
8192
8193         last_bitmap = (gpa_t)-1;
8194         b = -1;
8195
8196         while (size > 0) {
8197                 if (port < 0x8000)
8198                         bitmap = vmcs12->io_bitmap_a;
8199                 else if (port < 0x10000)
8200                         bitmap = vmcs12->io_bitmap_b;
8201                 else
8202                         return true;
8203                 bitmap += (port & 0x7fff) / 8;
8204
8205                 if (last_bitmap != bitmap)
8206                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8207                                 return true;
8208                 if (b & (1 << (port & 7)))
8209                         return true;
8210
8211                 port++;
8212                 size--;
8213                 last_bitmap = bitmap;
8214         }
8215
8216         return false;
8217 }
8218
8219 /*
8220  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8221  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8222  * disinterest in the current event (read or write a specific MSR) by using an
8223  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8224  */
8225 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8226         struct vmcs12 *vmcs12, u32 exit_reason)
8227 {
8228         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8229         gpa_t bitmap;
8230
8231         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8232                 return true;
8233
8234         /*
8235          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8236          * for the four combinations of read/write and low/high MSR numbers.
8237          * First we need to figure out which of the four to use:
8238          */
8239         bitmap = vmcs12->msr_bitmap;
8240         if (exit_reason == EXIT_REASON_MSR_WRITE)
8241                 bitmap += 2048;
8242         if (msr_index >= 0xc0000000) {
8243                 msr_index -= 0xc0000000;
8244                 bitmap += 1024;
8245         }
8246
8247         /* Then read the msr_index'th bit from this bitmap: */
8248         if (msr_index < 1024*8) {
8249                 unsigned char b;
8250                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8251                         return true;
8252                 return 1 & (b >> (msr_index & 7));
8253         } else
8254                 return true; /* let L1 handle the wrong parameter */
8255 }
8256
8257 /*
8258  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8259  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8260  * intercept (via guest_host_mask etc.) the current event.
8261  */
8262 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8263         struct vmcs12 *vmcs12)
8264 {
8265         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8266         int cr = exit_qualification & 15;
8267         int reg;
8268         unsigned long val;
8269
8270         switch ((exit_qualification >> 4) & 3) {
8271         case 0: /* mov to cr */
8272                 reg = (exit_qualification >> 8) & 15;
8273                 val = kvm_register_readl(vcpu, reg);
8274                 switch (cr) {
8275                 case 0:
8276                         if (vmcs12->cr0_guest_host_mask &
8277                             (val ^ vmcs12->cr0_read_shadow))
8278                                 return true;
8279                         break;
8280                 case 3:
8281                         if ((vmcs12->cr3_target_count >= 1 &&
8282                                         vmcs12->cr3_target_value0 == val) ||
8283                                 (vmcs12->cr3_target_count >= 2 &&
8284                                         vmcs12->cr3_target_value1 == val) ||
8285                                 (vmcs12->cr3_target_count >= 3 &&
8286                                         vmcs12->cr3_target_value2 == val) ||
8287                                 (vmcs12->cr3_target_count >= 4 &&
8288                                         vmcs12->cr3_target_value3 == val))
8289                                 return false;
8290                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8291                                 return true;
8292                         break;
8293                 case 4:
8294                         if (vmcs12->cr4_guest_host_mask &
8295                             (vmcs12->cr4_read_shadow ^ val))
8296                                 return true;
8297                         break;
8298                 case 8:
8299                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8300                                 return true;
8301                         break;
8302                 }
8303                 break;
8304         case 2: /* clts */
8305                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8306                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
8307                         return true;
8308                 break;
8309         case 1: /* mov from cr */
8310                 switch (cr) {
8311                 case 3:
8312                         if (vmcs12->cpu_based_vm_exec_control &
8313                             CPU_BASED_CR3_STORE_EXITING)
8314                                 return true;
8315                         break;
8316                 case 8:
8317                         if (vmcs12->cpu_based_vm_exec_control &
8318                             CPU_BASED_CR8_STORE_EXITING)
8319                                 return true;
8320                         break;
8321                 }
8322                 break;
8323         case 3: /* lmsw */
8324                 /*
8325                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8326                  * cr0. Other attempted changes are ignored, with no exit.
8327                  */
8328                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8329                 if (vmcs12->cr0_guest_host_mask & 0xe &
8330                     (val ^ vmcs12->cr0_read_shadow))
8331                         return true;
8332                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8333                     !(vmcs12->cr0_read_shadow & 0x1) &&
8334                     (val & 0x1))
8335                         return true;
8336                 break;
8337         }
8338         return false;
8339 }
8340
8341 /*
8342  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8343  * should handle it ourselves in L0 (and then continue L2). Only call this
8344  * when in is_guest_mode (L2).
8345  */
8346 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
8347 {
8348         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8349         struct vcpu_vmx *vmx = to_vmx(vcpu);
8350         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8351
8352         if (vmx->nested.nested_run_pending)
8353                 return false;
8354
8355         if (unlikely(vmx->fail)) {
8356                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8357                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8358                 return true;
8359         }
8360
8361         /*
8362          * The host physical addresses of some pages of guest memory
8363          * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU
8364          * may write to these pages via their host physical address while
8365          * L2 is running, bypassing any address-translation-based dirty
8366          * tracking (e.g. EPT write protection).
8367          *
8368          * Mark them dirty on every exit from L2 to prevent them from
8369          * getting out of sync with dirty tracking.
8370          */
8371         nested_mark_vmcs12_pages_dirty(vcpu);
8372
8373         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8374                                 vmcs_readl(EXIT_QUALIFICATION),
8375                                 vmx->idt_vectoring_info,
8376                                 intr_info,
8377                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8378                                 KVM_ISA_VMX);
8379
8380         switch (exit_reason) {
8381         case EXIT_REASON_EXCEPTION_NMI:
8382                 if (is_nmi(intr_info))
8383                         return false;
8384                 else if (is_page_fault(intr_info))
8385                         return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
8386                 else if (is_no_device(intr_info) &&
8387                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8388                         return false;
8389                 else if (is_debug(intr_info) &&
8390                          vcpu->guest_debug &
8391                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8392                         return false;
8393                 else if (is_breakpoint(intr_info) &&
8394                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8395                         return false;
8396                 return vmcs12->exception_bitmap &
8397                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8398         case EXIT_REASON_EXTERNAL_INTERRUPT:
8399                 return false;
8400         case EXIT_REASON_TRIPLE_FAULT:
8401                 return true;
8402         case EXIT_REASON_PENDING_INTERRUPT:
8403                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8404         case EXIT_REASON_NMI_WINDOW:
8405                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8406         case EXIT_REASON_TASK_SWITCH:
8407                 return true;
8408         case EXIT_REASON_CPUID:
8409                 return true;
8410         case EXIT_REASON_HLT:
8411                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8412         case EXIT_REASON_INVD:
8413                 return true;
8414         case EXIT_REASON_INVLPG:
8415                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8416         case EXIT_REASON_RDPMC:
8417                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8418         case EXIT_REASON_RDRAND:
8419                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8420         case EXIT_REASON_RDSEED:
8421                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
8422         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8423                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8424         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8425         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8426         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8427         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8428         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8429         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8430                 /*
8431                  * VMX instructions trap unconditionally. This allows L1 to
8432                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8433                  */
8434                 return true;
8435         case EXIT_REASON_CR_ACCESS:
8436                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8437         case EXIT_REASON_DR_ACCESS:
8438                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8439         case EXIT_REASON_IO_INSTRUCTION:
8440                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8441         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8442                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8443         case EXIT_REASON_MSR_READ:
8444         case EXIT_REASON_MSR_WRITE:
8445                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8446         case EXIT_REASON_INVALID_STATE:
8447                 return true;
8448         case EXIT_REASON_MWAIT_INSTRUCTION:
8449                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8450         case EXIT_REASON_MONITOR_TRAP_FLAG:
8451                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8452         case EXIT_REASON_MONITOR_INSTRUCTION:
8453                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8454         case EXIT_REASON_PAUSE_INSTRUCTION:
8455                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8456                         nested_cpu_has2(vmcs12,
8457                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8458         case EXIT_REASON_MCE_DURING_VMENTRY:
8459                 return false;
8460         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8461                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8462         case EXIT_REASON_APIC_ACCESS:
8463                 return nested_cpu_has2(vmcs12,
8464                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8465         case EXIT_REASON_APIC_WRITE:
8466         case EXIT_REASON_EOI_INDUCED:
8467                 /* apic_write and eoi_induced should exit unconditionally. */
8468                 return true;
8469         case EXIT_REASON_EPT_VIOLATION:
8470                 /*
8471                  * L0 always deals with the EPT violation. If nested EPT is
8472                  * used, and the nested mmu code discovers that the address is
8473                  * missing in the guest EPT table (EPT12), the EPT violation
8474                  * will be injected with nested_ept_inject_page_fault()
8475                  */
8476                 return false;
8477         case EXIT_REASON_EPT_MISCONFIG:
8478                 /*
8479                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8480                  * table (shadow on EPT) or a merged EPT table that L0 built
8481                  * (EPT on EPT). So any problems with the structure of the
8482                  * table is L0's fault.
8483                  */
8484                 return false;
8485         case EXIT_REASON_INVPCID:
8486                 return
8487                         nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
8488                         nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8489         case EXIT_REASON_WBINVD:
8490                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8491         case EXIT_REASON_XSETBV:
8492                 return true;
8493         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8494                 /*
8495                  * This should never happen, since it is not possible to
8496                  * set XSS to a non-zero value---neither in L1 nor in L2.
8497                  * If if it were, XSS would have to be checked against
8498                  * the XSS exit bitmap in vmcs12.
8499                  */
8500                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8501         case EXIT_REASON_PREEMPTION_TIMER:
8502                 return false;
8503         case EXIT_REASON_PML_FULL:
8504                 /* We emulate PML support to L1. */
8505                 return false;
8506         case EXIT_REASON_VMFUNC:
8507                 /* VM functions are emulated through L2->L0 vmexits. */
8508                 return false;
8509         default:
8510                 return true;
8511         }
8512 }
8513
8514 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
8515 {
8516         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8517
8518         /*
8519          * At this point, the exit interruption info in exit_intr_info
8520          * is only valid for EXCEPTION_NMI exits.  For EXTERNAL_INTERRUPT
8521          * we need to query the in-kernel LAPIC.
8522          */
8523         WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
8524         if ((exit_intr_info &
8525              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8526             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
8527                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8528                 vmcs12->vm_exit_intr_error_code =
8529                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8530         }
8531
8532         nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
8533                           vmcs_readl(EXIT_QUALIFICATION));
8534         return 1;
8535 }
8536
8537 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8538 {
8539         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8540         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8541 }
8542
8543 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8544 {
8545         if (vmx->pml_pg) {
8546                 __free_page(vmx->pml_pg);
8547                 vmx->pml_pg = NULL;
8548         }
8549 }
8550
8551 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8552 {
8553         struct vcpu_vmx *vmx = to_vmx(vcpu);
8554         u64 *pml_buf;
8555         u16 pml_idx;
8556
8557         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8558
8559         /* Do nothing if PML buffer is empty */
8560         if (pml_idx == (PML_ENTITY_NUM - 1))
8561                 return;
8562
8563         /* PML index always points to next available PML buffer entity */
8564         if (pml_idx >= PML_ENTITY_NUM)
8565                 pml_idx = 0;
8566         else
8567                 pml_idx++;
8568
8569         pml_buf = page_address(vmx->pml_pg);
8570         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8571                 u64 gpa;
8572
8573                 gpa = pml_buf[pml_idx];
8574                 WARN_ON(gpa & (PAGE_SIZE - 1));
8575                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8576         }
8577
8578         /* reset PML index */
8579         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8580 }
8581
8582 /*
8583  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8584  * Called before reporting dirty_bitmap to userspace.
8585  */
8586 static void kvm_flush_pml_buffers(struct kvm *kvm)
8587 {
8588         int i;
8589         struct kvm_vcpu *vcpu;
8590         /*
8591          * We only need to kick vcpu out of guest mode here, as PML buffer
8592          * is flushed at beginning of all VMEXITs, and it's obvious that only
8593          * vcpus running in guest are possible to have unflushed GPAs in PML
8594          * buffer.
8595          */
8596         kvm_for_each_vcpu(i, vcpu, kvm)
8597                 kvm_vcpu_kick(vcpu);
8598 }
8599
8600 static void vmx_dump_sel(char *name, uint32_t sel)
8601 {
8602         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8603                name, vmcs_read16(sel),
8604                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8605                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8606                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8607 }
8608
8609 static void vmx_dump_dtsel(char *name, uint32_t limit)
8610 {
8611         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8612                name, vmcs_read32(limit),
8613                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8614 }
8615
8616 static void dump_vmcs(void)
8617 {
8618         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8619         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8620         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8621         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8622         u32 secondary_exec_control = 0;
8623         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8624         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8625         int i, n;
8626
8627         if (cpu_has_secondary_exec_ctrls())
8628                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8629
8630         pr_err("*** Guest State ***\n");
8631         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8632                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8633                vmcs_readl(CR0_GUEST_HOST_MASK));
8634         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8635                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8636         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8637         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8638             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8639         {
8640                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8641                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8642                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8643                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8644         }
8645         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8646                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8647         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8648                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8649         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8650                vmcs_readl(GUEST_SYSENTER_ESP),
8651                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8652         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8653         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8654         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8655         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8656         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8657         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8658         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8659         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8660         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8661         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8662         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8663             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8664                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8665                        efer, vmcs_read64(GUEST_IA32_PAT));
8666         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8667                vmcs_read64(GUEST_IA32_DEBUGCTL),
8668                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8669         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8670                 pr_err("PerfGlobCtl = 0x%016llx\n",
8671                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8672         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8673                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8674         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8675                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8676                vmcs_read32(GUEST_ACTIVITY_STATE));
8677         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8678                 pr_err("InterruptStatus = %04x\n",
8679                        vmcs_read16(GUEST_INTR_STATUS));
8680
8681         pr_err("*** Host State ***\n");
8682         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8683                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8684         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8685                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8686                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8687                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8688                vmcs_read16(HOST_TR_SELECTOR));
8689         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8690                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8691                vmcs_readl(HOST_TR_BASE));
8692         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8693                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8694         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8695                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8696                vmcs_readl(HOST_CR4));
8697         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8698                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8699                vmcs_read32(HOST_IA32_SYSENTER_CS),
8700                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8701         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8702                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8703                        vmcs_read64(HOST_IA32_EFER),
8704                        vmcs_read64(HOST_IA32_PAT));
8705         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8706                 pr_err("PerfGlobCtl = 0x%016llx\n",
8707                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8708
8709         pr_err("*** Control State ***\n");
8710         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8711                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8712         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8713         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8714                vmcs_read32(EXCEPTION_BITMAP),
8715                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8716                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8717         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8718                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8719                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8720                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8721         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8722                vmcs_read32(VM_EXIT_INTR_INFO),
8723                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8724                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8725         pr_err("        reason=%08x qualification=%016lx\n",
8726                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8727         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8728                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8729                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8730         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8731         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8732                 pr_err("TSC Multiplier = 0x%016llx\n",
8733                        vmcs_read64(TSC_MULTIPLIER));
8734         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8735                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8736         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8737                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8738         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8739                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8740         n = vmcs_read32(CR3_TARGET_COUNT);
8741         for (i = 0; i + 1 < n; i += 4)
8742                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8743                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8744                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8745         if (i < n)
8746                 pr_err("CR3 target%u=%016lx\n",
8747                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8748         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8749                 pr_err("PLE Gap=%08x Window=%08x\n",
8750                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8751         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8752                 pr_err("Virtual processor ID = 0x%04x\n",
8753                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8754 }
8755
8756 /*
8757  * The guest has exited.  See if we can fix it or if we need userspace
8758  * assistance.
8759  */
8760 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8761 {
8762         struct vcpu_vmx *vmx = to_vmx(vcpu);
8763         u32 exit_reason = vmx->exit_reason;
8764         u32 vectoring_info = vmx->idt_vectoring_info;
8765
8766         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8767
8768         /*
8769          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8770          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8771          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8772          * mode as if vcpus is in root mode, the PML buffer must has been
8773          * flushed already.
8774          */
8775         if (enable_pml)
8776                 vmx_flush_pml_buffer(vcpu);
8777
8778         /* If guest state is invalid, start emulating */
8779         if (vmx->emulation_required)
8780                 return handle_invalid_guest_state(vcpu);
8781
8782         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
8783                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
8784
8785         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8786                 dump_vmcs();
8787                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8788                 vcpu->run->fail_entry.hardware_entry_failure_reason
8789                         = exit_reason;
8790                 return 0;
8791         }
8792
8793         if (unlikely(vmx->fail)) {
8794                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8795                 vcpu->run->fail_entry.hardware_entry_failure_reason
8796                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8797                 return 0;
8798         }
8799
8800         /*
8801          * Note:
8802          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8803          * delivery event since it indicates guest is accessing MMIO.
8804          * The vm-exit can be triggered again after return to guest that
8805          * will cause infinite loop.
8806          */
8807         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8808                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8809                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8810                         exit_reason != EXIT_REASON_PML_FULL &&
8811                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8812                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8813                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8814                 vcpu->run->internal.ndata = 3;
8815                 vcpu->run->internal.data[0] = vectoring_info;
8816                 vcpu->run->internal.data[1] = exit_reason;
8817                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8818                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8819                         vcpu->run->internal.ndata++;
8820                         vcpu->run->internal.data[3] =
8821                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8822                 }
8823                 return 0;
8824         }
8825
8826         if (exit_reason < kvm_vmx_max_exit_handlers
8827             && kvm_vmx_exit_handlers[exit_reason])
8828                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8829         else {
8830                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8831                                 exit_reason);
8832                 kvm_queue_exception(vcpu, UD_VECTOR);
8833                 return 1;
8834         }
8835 }
8836
8837 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8838 {
8839         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8840
8841         if (is_guest_mode(vcpu) &&
8842                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8843                 return;
8844
8845         if (irr == -1 || tpr < irr) {
8846                 vmcs_write32(TPR_THRESHOLD, 0);
8847                 return;
8848         }
8849
8850         vmcs_write32(TPR_THRESHOLD, irr);
8851 }
8852
8853 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8854 {
8855         u32 sec_exec_control;
8856
8857         /* Postpone execution until vmcs01 is the current VMCS. */
8858         if (is_guest_mode(vcpu)) {
8859                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8860                 return;
8861         }
8862
8863         if (!cpu_has_vmx_virtualize_x2apic_mode())
8864                 return;
8865
8866         if (!cpu_need_tpr_shadow(vcpu))
8867                 return;
8868
8869         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8870
8871         if (set) {
8872                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8873                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8874         } else {
8875                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8876                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8877                 vmx_flush_tlb_ept_only(vcpu);
8878         }
8879         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8880
8881         vmx_set_msr_bitmap(vcpu);
8882 }
8883
8884 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8885 {
8886         struct vcpu_vmx *vmx = to_vmx(vcpu);
8887
8888         /*
8889          * Currently we do not handle the nested case where L2 has an
8890          * APIC access page of its own; that page is still pinned.
8891          * Hence, we skip the case where the VCPU is in guest mode _and_
8892          * L1 prepared an APIC access page for L2.
8893          *
8894          * For the case where L1 and L2 share the same APIC access page
8895          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8896          * in the vmcs12), this function will only update either the vmcs01
8897          * or the vmcs02.  If the former, the vmcs02 will be updated by
8898          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8899          * the next L2->L1 exit.
8900          */
8901         if (!is_guest_mode(vcpu) ||
8902             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8903                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8904                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8905                 vmx_flush_tlb_ept_only(vcpu);
8906         }
8907 }
8908
8909 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8910 {
8911         u16 status;
8912         u8 old;
8913
8914         if (max_isr == -1)
8915                 max_isr = 0;
8916
8917         status = vmcs_read16(GUEST_INTR_STATUS);
8918         old = status >> 8;
8919         if (max_isr != old) {
8920                 status &= 0xff;
8921                 status |= max_isr << 8;
8922                 vmcs_write16(GUEST_INTR_STATUS, status);
8923         }
8924 }
8925
8926 static void vmx_set_rvi(int vector)
8927 {
8928         u16 status;
8929         u8 old;
8930
8931         if (vector == -1)
8932                 vector = 0;
8933
8934         status = vmcs_read16(GUEST_INTR_STATUS);
8935         old = (u8)status & 0xff;
8936         if ((u8)vector != old) {
8937                 status &= ~0xff;
8938                 status |= (u8)vector;
8939                 vmcs_write16(GUEST_INTR_STATUS, status);
8940         }
8941 }
8942
8943 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8944 {
8945         if (!is_guest_mode(vcpu)) {
8946                 vmx_set_rvi(max_irr);
8947                 return;
8948         }
8949
8950         if (max_irr == -1)
8951                 return;
8952
8953         /*
8954          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8955          * handles it.
8956          */
8957         if (nested_exit_on_intr(vcpu))
8958                 return;
8959
8960         /*
8961          * Else, fall back to pre-APICv interrupt injection since L2
8962          * is run without virtual interrupt delivery.
8963          */
8964         if (!kvm_event_needs_reinjection(vcpu) &&
8965             vmx_interrupt_allowed(vcpu)) {
8966                 kvm_queue_interrupt(vcpu, max_irr, false);
8967                 vmx_inject_irq(vcpu);
8968         }
8969 }
8970
8971 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8972 {
8973         struct vcpu_vmx *vmx = to_vmx(vcpu);
8974         int max_irr;
8975
8976         WARN_ON(!vcpu->arch.apicv_active);
8977         if (pi_test_on(&vmx->pi_desc)) {
8978                 pi_clear_on(&vmx->pi_desc);
8979                 /*
8980                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8981                  * But on x86 this is just a compiler barrier anyway.
8982                  */
8983                 smp_mb__after_atomic();
8984                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8985         } else {
8986                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8987         }
8988         vmx_hwapic_irr_update(vcpu, max_irr);
8989         return max_irr;
8990 }
8991
8992 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8993 {
8994         if (!kvm_vcpu_apicv_active(vcpu))
8995                 return;
8996
8997         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8998         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8999         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
9000         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
9001 }
9002
9003 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
9004 {
9005         struct vcpu_vmx *vmx = to_vmx(vcpu);
9006
9007         pi_clear_on(&vmx->pi_desc);
9008         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
9009 }
9010
9011 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
9012 {
9013         u32 exit_intr_info = 0;
9014         u16 basic_exit_reason = (u16)vmx->exit_reason;
9015
9016         if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
9017               || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
9018                 return;
9019
9020         if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9021                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9022         vmx->exit_intr_info = exit_intr_info;
9023
9024         /* if exit due to PF check for async PF */
9025         if (is_page_fault(exit_intr_info))
9026                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
9027
9028         /* Handle machine checks before interrupts are enabled */
9029         if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
9030             is_machine_check(exit_intr_info))
9031                 kvm_machine_check();
9032
9033         /* We need to handle NMIs before interrupts are enabled */
9034         if (is_nmi(exit_intr_info)) {
9035                 kvm_before_handle_nmi(&vmx->vcpu);
9036                 asm("int $2");
9037                 kvm_after_handle_nmi(&vmx->vcpu);
9038         }
9039 }
9040
9041 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
9042 {
9043         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9044
9045         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
9046                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
9047                 unsigned int vector;
9048                 unsigned long entry;
9049                 gate_desc *desc;
9050                 struct vcpu_vmx *vmx = to_vmx(vcpu);
9051 #ifdef CONFIG_X86_64
9052                 unsigned long tmp;
9053 #endif
9054
9055                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
9056                 desc = (gate_desc *)vmx->host_idt_base + vector;
9057                 entry = gate_offset(desc);
9058                 asm volatile(
9059 #ifdef CONFIG_X86_64
9060                         "mov %%" _ASM_SP ", %[sp]\n\t"
9061                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
9062                         "push $%c[ss]\n\t"
9063                         "push %[sp]\n\t"
9064 #endif
9065                         "pushf\n\t"
9066                         __ASM_SIZE(push) " $%c[cs]\n\t"
9067                         "call *%[entry]\n\t"
9068                         :
9069 #ifdef CONFIG_X86_64
9070                         [sp]"=&r"(tmp),
9071 #endif
9072                         ASM_CALL_CONSTRAINT
9073                         :
9074                         [entry]"r"(entry),
9075                         [ss]"i"(__KERNEL_DS),
9076                         [cs]"i"(__KERNEL_CS)
9077                         );
9078         }
9079 }
9080 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
9081
9082 static bool vmx_has_high_real_mode_segbase(void)
9083 {
9084         return enable_unrestricted_guest || emulate_invalid_guest_state;
9085 }
9086
9087 static bool vmx_mpx_supported(void)
9088 {
9089         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
9090                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
9091 }
9092
9093 static bool vmx_xsaves_supported(void)
9094 {
9095         return vmcs_config.cpu_based_2nd_exec_ctrl &
9096                 SECONDARY_EXEC_XSAVES;
9097 }
9098
9099 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
9100 {
9101         u32 exit_intr_info;
9102         bool unblock_nmi;
9103         u8 vector;
9104         bool idtv_info_valid;
9105
9106         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9107
9108         if (vmx->loaded_vmcs->nmi_known_unmasked)
9109                 return;
9110         /*
9111          * Can't use vmx->exit_intr_info since we're not sure what
9112          * the exit reason is.
9113          */
9114         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9115         unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
9116         vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9117         /*
9118          * SDM 3: 27.7.1.2 (September 2008)
9119          * Re-set bit "block by NMI" before VM entry if vmexit caused by
9120          * a guest IRET fault.
9121          * SDM 3: 23.2.2 (September 2008)
9122          * Bit 12 is undefined in any of the following cases:
9123          *  If the VM exit sets the valid bit in the IDT-vectoring
9124          *   information field.
9125          *  If the VM exit is due to a double fault.
9126          */
9127         if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
9128             vector != DF_VECTOR && !idtv_info_valid)
9129                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9130                               GUEST_INTR_STATE_NMI);
9131         else
9132                 vmx->loaded_vmcs->nmi_known_unmasked =
9133                         !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
9134                           & GUEST_INTR_STATE_NMI);
9135 }
9136
9137 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
9138                                       u32 idt_vectoring_info,
9139                                       int instr_len_field,
9140                                       int error_code_field)
9141 {
9142         u8 vector;
9143         int type;
9144         bool idtv_info_valid;
9145
9146         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9147
9148         vcpu->arch.nmi_injected = false;
9149         kvm_clear_exception_queue(vcpu);
9150         kvm_clear_interrupt_queue(vcpu);
9151
9152         if (!idtv_info_valid)
9153                 return;
9154
9155         kvm_make_request(KVM_REQ_EVENT, vcpu);
9156
9157         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
9158         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
9159
9160         switch (type) {
9161         case INTR_TYPE_NMI_INTR:
9162                 vcpu->arch.nmi_injected = true;
9163                 /*
9164                  * SDM 3: 27.7.1.2 (September 2008)
9165                  * Clear bit "block by NMI" before VM entry if a NMI
9166                  * delivery faulted.
9167                  */
9168                 vmx_set_nmi_mask(vcpu, false);
9169                 break;
9170         case INTR_TYPE_SOFT_EXCEPTION:
9171                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9172                 /* fall through */
9173         case INTR_TYPE_HARD_EXCEPTION:
9174                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
9175                         u32 err = vmcs_read32(error_code_field);
9176                         kvm_requeue_exception_e(vcpu, vector, err);
9177                 } else
9178                         kvm_requeue_exception(vcpu, vector);
9179                 break;
9180         case INTR_TYPE_SOFT_INTR:
9181                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9182                 /* fall through */
9183         case INTR_TYPE_EXT_INTR:
9184                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
9185                 break;
9186         default:
9187                 break;
9188         }
9189 }
9190
9191 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
9192 {
9193         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
9194                                   VM_EXIT_INSTRUCTION_LEN,
9195                                   IDT_VECTORING_ERROR_CODE);
9196 }
9197
9198 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
9199 {
9200         __vmx_complete_interrupts(vcpu,
9201                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9202                                   VM_ENTRY_INSTRUCTION_LEN,
9203                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
9204
9205         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9206 }
9207
9208 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
9209 {
9210         int i, nr_msrs;
9211         struct perf_guest_switch_msr *msrs;
9212
9213         msrs = perf_guest_get_msrs(&nr_msrs);
9214
9215         if (!msrs)
9216                 return;
9217
9218         for (i = 0; i < nr_msrs; i++)
9219                 if (msrs[i].host == msrs[i].guest)
9220                         clear_atomic_switch_msr(vmx, msrs[i].msr);
9221                 else
9222                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
9223                                         msrs[i].host);
9224 }
9225
9226 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
9227 {
9228         struct vcpu_vmx *vmx = to_vmx(vcpu);
9229         u64 tscl;
9230         u32 delta_tsc;
9231
9232         if (vmx->hv_deadline_tsc == -1)
9233                 return;
9234
9235         tscl = rdtsc();
9236         if (vmx->hv_deadline_tsc > tscl)
9237                 /* sure to be 32 bit only because checked on set_hv_timer */
9238                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
9239                         cpu_preemption_timer_multi);
9240         else
9241                 delta_tsc = 0;
9242
9243         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9244 }
9245
9246 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
9247 {
9248         struct vcpu_vmx *vmx = to_vmx(vcpu);
9249         unsigned long debugctlmsr, cr3, cr4;
9250
9251         /* Don't enter VMX if guest state is invalid, let the exit handler
9252            start emulation until we arrive back to a valid state */
9253         if (vmx->emulation_required)
9254                 return;
9255
9256         if (vmx->ple_window_dirty) {
9257                 vmx->ple_window_dirty = false;
9258                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9259         }
9260
9261         if (vmx->nested.sync_shadow_vmcs) {
9262                 copy_vmcs12_to_shadow(vmx);
9263                 vmx->nested.sync_shadow_vmcs = false;
9264         }
9265
9266         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9267                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9268         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9269                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9270
9271         cr3 = __get_current_cr3_fast();
9272         if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) {
9273                 vmcs_writel(HOST_CR3, cr3);
9274                 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
9275         }
9276
9277         cr4 = cr4_read_shadow();
9278         if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) {
9279                 vmcs_writel(HOST_CR4, cr4);
9280                 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
9281         }
9282
9283         /* When single-stepping over STI and MOV SS, we must clear the
9284          * corresponding interruptibility bits in the guest state. Otherwise
9285          * vmentry fails as it then expects bit 14 (BS) in pending debug
9286          * exceptions being set, but that's not correct for the guest debugging
9287          * case. */
9288         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9289                 vmx_set_interrupt_shadow(vcpu, 0);
9290
9291         if (static_cpu_has(X86_FEATURE_PKU) &&
9292             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
9293             vcpu->arch.pkru != vmx->host_pkru)
9294                 __write_pkru(vcpu->arch.pkru);
9295
9296         atomic_switch_perf_msrs(vmx);
9297         debugctlmsr = get_debugctlmsr();
9298
9299         vmx_arm_hv_timer(vcpu);
9300
9301         vmx->__launched = vmx->loaded_vmcs->launched;
9302         asm(
9303                 /* Store host registers */
9304                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9305                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9306                 "push %%" _ASM_CX " \n\t"
9307                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9308                 "je 1f \n\t"
9309                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9310                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
9311                 "1: \n\t"
9312                 /* Reload cr2 if changed */
9313                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9314                 "mov %%cr2, %%" _ASM_DX " \n\t"
9315                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
9316                 "je 2f \n\t"
9317                 "mov %%" _ASM_AX", %%cr2 \n\t"
9318                 "2: \n\t"
9319                 /* Check if vmlaunch of vmresume is needed */
9320                 "cmpl $0, %c[launched](%0) \n\t"
9321                 /* Load guest registers.  Don't clobber flags. */
9322                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9323                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9324                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9325                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9326                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9327                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9328 #ifdef CONFIG_X86_64
9329                 "mov %c[r8](%0),  %%r8  \n\t"
9330                 "mov %c[r9](%0),  %%r9  \n\t"
9331                 "mov %c[r10](%0), %%r10 \n\t"
9332                 "mov %c[r11](%0), %%r11 \n\t"
9333                 "mov %c[r12](%0), %%r12 \n\t"
9334                 "mov %c[r13](%0), %%r13 \n\t"
9335                 "mov %c[r14](%0), %%r14 \n\t"
9336                 "mov %c[r15](%0), %%r15 \n\t"
9337 #endif
9338                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9339
9340                 /* Enter guest mode */
9341                 "jne 1f \n\t"
9342                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9343                 "jmp 2f \n\t"
9344                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9345                 "2: "
9346                 /* Save guest registers, load host registers, keep flags */
9347                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9348                 "pop %0 \n\t"
9349                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9350                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9351                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9352                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9353                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9354                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9355                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9356 #ifdef CONFIG_X86_64
9357                 "mov %%r8,  %c[r8](%0) \n\t"
9358                 "mov %%r9,  %c[r9](%0) \n\t"
9359                 "mov %%r10, %c[r10](%0) \n\t"
9360                 "mov %%r11, %c[r11](%0) \n\t"
9361                 "mov %%r12, %c[r12](%0) \n\t"
9362                 "mov %%r13, %c[r13](%0) \n\t"
9363                 "mov %%r14, %c[r14](%0) \n\t"
9364                 "mov %%r15, %c[r15](%0) \n\t"
9365 #endif
9366                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9367                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9368
9369                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9370                 "setbe %c[fail](%0) \n\t"
9371                 ".pushsection .rodata \n\t"
9372                 ".global vmx_return \n\t"
9373                 "vmx_return: " _ASM_PTR " 2b \n\t"
9374                 ".popsection"
9375               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9376                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9377                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9378                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9379                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9380                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9381                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9382                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9383                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9384                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9385                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9386 #ifdef CONFIG_X86_64
9387                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9388                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9389                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9390                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9391                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9392                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9393                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9394                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9395 #endif
9396                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9397                 [wordsize]"i"(sizeof(ulong))
9398               : "cc", "memory"
9399 #ifdef CONFIG_X86_64
9400                 , "rax", "rbx", "rdi", "rsi"
9401                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9402 #else
9403                 , "eax", "ebx", "edi", "esi"
9404 #endif
9405               );
9406
9407         /* Eliminate branch target predictions from guest mode */
9408         vmexit_fill_RSB();
9409
9410         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9411         if (debugctlmsr)
9412                 update_debugctlmsr(debugctlmsr);
9413
9414 #ifndef CONFIG_X86_64
9415         /*
9416          * The sysexit path does not restore ds/es, so we must set them to
9417          * a reasonable value ourselves.
9418          *
9419          * We can't defer this to vmx_load_host_state() since that function
9420          * may be executed in interrupt context, which saves and restore segments
9421          * around it, nullifying its effect.
9422          */
9423         loadsegment(ds, __USER_DS);
9424         loadsegment(es, __USER_DS);
9425 #endif
9426
9427         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9428                                   | (1 << VCPU_EXREG_RFLAGS)
9429                                   | (1 << VCPU_EXREG_PDPTR)
9430                                   | (1 << VCPU_EXREG_SEGMENTS)
9431                                   | (1 << VCPU_EXREG_CR3));
9432         vcpu->arch.regs_dirty = 0;
9433
9434         /*
9435          * eager fpu is enabled if PKEY is supported and CR4 is switched
9436          * back on host, so it is safe to read guest PKRU from current
9437          * XSAVE.
9438          */
9439         if (static_cpu_has(X86_FEATURE_PKU) &&
9440             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
9441                 vcpu->arch.pkru = __read_pkru();
9442                 if (vcpu->arch.pkru != vmx->host_pkru)
9443                         __write_pkru(vmx->host_pkru);
9444         }
9445
9446         /*
9447          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9448          * we did not inject a still-pending event to L1 now because of
9449          * nested_run_pending, we need to re-enable this bit.
9450          */
9451         if (vmx->nested.nested_run_pending)
9452                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9453
9454         vmx->nested.nested_run_pending = 0;
9455         vmx->idt_vectoring_info = 0;
9456
9457         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
9458         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9459                 return;
9460
9461         vmx->loaded_vmcs->launched = 1;
9462         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9463
9464         vmx_complete_atomic_exit(vmx);
9465         vmx_recover_nmi_blocking(vmx);
9466         vmx_complete_interrupts(vmx);
9467 }
9468 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
9469
9470 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9471 {
9472         struct vcpu_vmx *vmx = to_vmx(vcpu);
9473         int cpu;
9474
9475         if (vmx->loaded_vmcs == vmcs)
9476                 return;
9477
9478         cpu = get_cpu();
9479         vmx->loaded_vmcs = vmcs;
9480         vmx_vcpu_put(vcpu);
9481         vmx_vcpu_load(vcpu, cpu);
9482         vcpu->cpu = cpu;
9483         put_cpu();
9484 }
9485
9486 /*
9487  * Ensure that the current vmcs of the logical processor is the
9488  * vmcs01 of the vcpu before calling free_nested().
9489  */
9490 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9491 {
9492        struct vcpu_vmx *vmx = to_vmx(vcpu);
9493        int r;
9494
9495        r = vcpu_load(vcpu);
9496        BUG_ON(r);
9497        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9498        free_nested(vmx);
9499        vcpu_put(vcpu);
9500 }
9501
9502 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9503 {
9504         struct vcpu_vmx *vmx = to_vmx(vcpu);
9505
9506         if (enable_pml)
9507                 vmx_destroy_pml_buffer(vmx);
9508         free_vpid(vmx->vpid);
9509         leave_guest_mode(vcpu);
9510         vmx_free_vcpu_nested(vcpu);
9511         free_loaded_vmcs(vmx->loaded_vmcs);
9512         kfree(vmx->guest_msrs);
9513         kvm_vcpu_uninit(vcpu);
9514         kmem_cache_free(kvm_vcpu_cache, vmx);
9515 }
9516
9517 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9518 {
9519         int err;
9520         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9521         int cpu;
9522
9523         if (!vmx)
9524                 return ERR_PTR(-ENOMEM);
9525
9526         vmx->vpid = allocate_vpid();
9527
9528         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9529         if (err)
9530                 goto free_vcpu;
9531
9532         err = -ENOMEM;
9533
9534         /*
9535          * If PML is turned on, failure on enabling PML just results in failure
9536          * of creating the vcpu, therefore we can simplify PML logic (by
9537          * avoiding dealing with cases, such as enabling PML partially on vcpus
9538          * for the guest, etc.
9539          */
9540         if (enable_pml) {
9541                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9542                 if (!vmx->pml_pg)
9543                         goto uninit_vcpu;
9544         }
9545
9546         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9547         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9548                      > PAGE_SIZE);
9549
9550         if (!vmx->guest_msrs)
9551                 goto free_pml;
9552
9553         vmx->loaded_vmcs = &vmx->vmcs01;
9554         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9555         vmx->loaded_vmcs->shadow_vmcs = NULL;
9556         if (!vmx->loaded_vmcs->vmcs)
9557                 goto free_msrs;
9558         loaded_vmcs_init(vmx->loaded_vmcs);
9559
9560         cpu = get_cpu();
9561         vmx_vcpu_load(&vmx->vcpu, cpu);
9562         vmx->vcpu.cpu = cpu;
9563         err = vmx_vcpu_setup(vmx);
9564         vmx_vcpu_put(&vmx->vcpu);
9565         put_cpu();
9566         if (err)
9567                 goto free_vmcs;
9568         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9569                 err = alloc_apic_access_page(kvm);
9570                 if (err)
9571                         goto free_vmcs;
9572         }
9573
9574         if (enable_ept) {
9575                 if (!kvm->arch.ept_identity_map_addr)
9576                         kvm->arch.ept_identity_map_addr =
9577                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9578                 err = init_rmode_identity_map(kvm);
9579                 if (err)
9580                         goto free_vmcs;
9581         }
9582
9583         if (nested) {
9584                 nested_vmx_setup_ctls_msrs(vmx);
9585                 vmx->nested.vpid02 = allocate_vpid();
9586         }
9587
9588         vmx->nested.posted_intr_nv = -1;
9589         vmx->nested.current_vmptr = -1ull;
9590
9591         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9592
9593         /*
9594          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9595          * or POSTED_INTR_WAKEUP_VECTOR.
9596          */
9597         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
9598         vmx->pi_desc.sn = 1;
9599
9600         return &vmx->vcpu;
9601
9602 free_vmcs:
9603         free_vpid(vmx->nested.vpid02);
9604         free_loaded_vmcs(vmx->loaded_vmcs);
9605 free_msrs:
9606         kfree(vmx->guest_msrs);
9607 free_pml:
9608         vmx_destroy_pml_buffer(vmx);
9609 uninit_vcpu:
9610         kvm_vcpu_uninit(&vmx->vcpu);
9611 free_vcpu:
9612         free_vpid(vmx->vpid);
9613         kmem_cache_free(kvm_vcpu_cache, vmx);
9614         return ERR_PTR(err);
9615 }
9616
9617 static void __init vmx_check_processor_compat(void *rtn)
9618 {
9619         struct vmcs_config vmcs_conf;
9620
9621         *(int *)rtn = 0;
9622         if (setup_vmcs_config(&vmcs_conf) < 0)
9623                 *(int *)rtn = -EIO;
9624         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9625                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9626                                 smp_processor_id());
9627                 *(int *)rtn = -EIO;
9628         }
9629 }
9630
9631 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9632 {
9633         u8 cache;
9634         u64 ipat = 0;
9635
9636         /* For VT-d and EPT combination
9637          * 1. MMIO: always map as UC
9638          * 2. EPT with VT-d:
9639          *   a. VT-d without snooping control feature: can't guarantee the
9640          *      result, try to trust guest.
9641          *   b. VT-d with snooping control feature: snooping control feature of
9642          *      VT-d engine can guarantee the cache correctness. Just set it
9643          *      to WB to keep consistent with host. So the same as item 3.
9644          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9645          *    consistent with host MTRR
9646          */
9647         if (is_mmio) {
9648                 cache = MTRR_TYPE_UNCACHABLE;
9649                 goto exit;
9650         }
9651
9652         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9653                 ipat = VMX_EPT_IPAT_BIT;
9654                 cache = MTRR_TYPE_WRBACK;
9655                 goto exit;
9656         }
9657
9658         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9659                 ipat = VMX_EPT_IPAT_BIT;
9660                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9661                         cache = MTRR_TYPE_WRBACK;
9662                 else
9663                         cache = MTRR_TYPE_UNCACHABLE;
9664                 goto exit;
9665         }
9666
9667         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9668
9669 exit:
9670         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9671 }
9672
9673 static int vmx_get_lpage_level(void)
9674 {
9675         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9676                 return PT_DIRECTORY_LEVEL;
9677         else
9678                 /* For shadow and EPT supported 1GB page */
9679                 return PT_PDPE_LEVEL;
9680 }
9681
9682 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9683 {
9684         /*
9685          * These bits in the secondary execution controls field
9686          * are dynamic, the others are mostly based on the hypervisor
9687          * architecture and the guest's CPUID.  Do not touch the
9688          * dynamic bits.
9689          */
9690         u32 mask =
9691                 SECONDARY_EXEC_SHADOW_VMCS |
9692                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9693                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9694
9695         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9696
9697         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9698                      (new_ctl & ~mask) | (cur_ctl & mask));
9699 }
9700
9701 /*
9702  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9703  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9704  */
9705 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9706 {
9707         struct vcpu_vmx *vmx = to_vmx(vcpu);
9708         struct kvm_cpuid_entry2 *entry;
9709
9710         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9711         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9712
9713 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9714         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9715                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9716 } while (0)
9717
9718         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9719         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9720         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9721         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9722         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9723         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9724         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9725         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9726         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9727         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9728         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9729         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9730         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9731         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9732         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9733
9734         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9735         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9736         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9737         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9738         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9739         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9740         cr4_fixed1_update(bit(11),            ecx, bit(2));
9741
9742 #undef cr4_fixed1_update
9743 }
9744
9745 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9746 {
9747         struct vcpu_vmx *vmx = to_vmx(vcpu);
9748
9749         if (cpu_has_secondary_exec_ctrls()) {
9750                 vmx_compute_secondary_exec_control(vmx);
9751                 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
9752         }
9753
9754         if (nested_vmx_allowed(vcpu))
9755                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9756                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9757         else
9758                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9759                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9760
9761         if (nested_vmx_allowed(vcpu))
9762                 nested_vmx_cr_fixed1_bits_update(vcpu);
9763 }
9764
9765 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9766 {
9767         if (func == 1 && nested)
9768                 entry->ecx |= bit(X86_FEATURE_VMX);
9769 }
9770
9771 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9772                 struct x86_exception *fault)
9773 {
9774         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9775         struct vcpu_vmx *vmx = to_vmx(vcpu);
9776         u32 exit_reason;
9777         unsigned long exit_qualification = vcpu->arch.exit_qualification;
9778
9779         if (vmx->nested.pml_full) {
9780                 exit_reason = EXIT_REASON_PML_FULL;
9781                 vmx->nested.pml_full = false;
9782                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9783         } else if (fault->error_code & PFERR_RSVD_MASK)
9784                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9785         else
9786                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9787
9788         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
9789         vmcs12->guest_physical_address = fault->address;
9790 }
9791
9792 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9793 {
9794         return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
9795 }
9796
9797 /* Callbacks for nested_ept_init_mmu_context: */
9798
9799 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9800 {
9801         /* return the page table to be shadowed - in our case, EPT12 */
9802         return get_vmcs12(vcpu)->ept_pointer;
9803 }
9804
9805 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9806 {
9807         WARN_ON(mmu_is_nested(vcpu));
9808         if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
9809                 return 1;
9810
9811         kvm_mmu_unload(vcpu);
9812         kvm_init_shadow_ept_mmu(vcpu,
9813                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9814                         VMX_EPT_EXECUTE_ONLY_BIT,
9815                         nested_ept_ad_enabled(vcpu));
9816         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9817         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9818         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9819
9820         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9821         return 0;
9822 }
9823
9824 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9825 {
9826         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9827 }
9828
9829 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9830                                             u16 error_code)
9831 {
9832         bool inequality, bit;
9833
9834         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9835         inequality =
9836                 (error_code & vmcs12->page_fault_error_code_mask) !=
9837                  vmcs12->page_fault_error_code_match;
9838         return inequality ^ bit;
9839 }
9840
9841 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9842                 struct x86_exception *fault)
9843 {
9844         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9845
9846         WARN_ON(!is_guest_mode(vcpu));
9847
9848         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
9849                 !to_vmx(vcpu)->nested.nested_run_pending) {
9850                 vmcs12->vm_exit_intr_error_code = fault->error_code;
9851                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9852                                   PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
9853                                   INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
9854                                   fault->address);
9855         } else {
9856                 kvm_inject_page_fault(vcpu, fault);
9857         }
9858 }
9859
9860 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9861                                                struct vmcs12 *vmcs12);
9862
9863 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9864                                         struct vmcs12 *vmcs12)
9865 {
9866         struct vcpu_vmx *vmx = to_vmx(vcpu);
9867         struct page *page;
9868         u64 hpa;
9869
9870         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9871                 /*
9872                  * Translate L1 physical address to host physical
9873                  * address for vmcs02. Keep the page pinned, so this
9874                  * physical address remains valid. We keep a reference
9875                  * to it so we can release it later.
9876                  */
9877                 if (vmx->nested.apic_access_page) { /* shouldn't happen */
9878                         kvm_release_page_dirty(vmx->nested.apic_access_page);
9879                         vmx->nested.apic_access_page = NULL;
9880                 }
9881                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
9882                 /*
9883                  * If translation failed, no matter: This feature asks
9884                  * to exit when accessing the given address, and if it
9885                  * can never be accessed, this feature won't do
9886                  * anything anyway.
9887                  */
9888                 if (!is_error_page(page)) {
9889                         vmx->nested.apic_access_page = page;
9890                         hpa = page_to_phys(vmx->nested.apic_access_page);
9891                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9892                 } else {
9893                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9894                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9895                 }
9896         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9897                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9898                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9899                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9900                 kvm_vcpu_reload_apic_access_page(vcpu);
9901         }
9902
9903         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9904                 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
9905                         kvm_release_page_dirty(vmx->nested.virtual_apic_page);
9906                         vmx->nested.virtual_apic_page = NULL;
9907                 }
9908                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
9909
9910                 /*
9911                  * If translation failed, VM entry will fail because
9912                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9913                  * Failing the vm entry is _not_ what the processor
9914                  * does but it's basically the only possibility we
9915                  * have.  We could still enter the guest if CR8 load
9916                  * exits are enabled, CR8 store exits are enabled, and
9917                  * virtualize APIC access is disabled; in this case
9918                  * the processor would never use the TPR shadow and we
9919                  * could simply clear the bit from the execution
9920                  * control.  But such a configuration is useless, so
9921                  * let's keep the code simple.
9922                  */
9923                 if (!is_error_page(page)) {
9924                         vmx->nested.virtual_apic_page = page;
9925                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9926                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9927                 }
9928         }
9929
9930         if (nested_cpu_has_posted_intr(vmcs12)) {
9931                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9932                         kunmap(vmx->nested.pi_desc_page);
9933                         kvm_release_page_dirty(vmx->nested.pi_desc_page);
9934                         vmx->nested.pi_desc_page = NULL;
9935                 }
9936                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
9937                 if (is_error_page(page))
9938                         return;
9939                 vmx->nested.pi_desc_page = page;
9940                 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
9941                 vmx->nested.pi_desc =
9942                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9943                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9944                         (PAGE_SIZE - 1)));
9945                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9946                         page_to_phys(vmx->nested.pi_desc_page) +
9947                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9948                         (PAGE_SIZE - 1)));
9949         }
9950         if (cpu_has_vmx_msr_bitmap() &&
9951             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9952             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9953                 ;
9954         else
9955                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9956                                 CPU_BASED_USE_MSR_BITMAPS);
9957 }
9958
9959 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9960 {
9961         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9962         struct vcpu_vmx *vmx = to_vmx(vcpu);
9963
9964         if (vcpu->arch.virtual_tsc_khz == 0)
9965                 return;
9966
9967         /* Make sure short timeouts reliably trigger an immediate vmexit.
9968          * hrtimer_start does not guarantee this. */
9969         if (preemption_timeout <= 1) {
9970                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9971                 return;
9972         }
9973
9974         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9975         preemption_timeout *= 1000000;
9976         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9977         hrtimer_start(&vmx->nested.preemption_timer,
9978                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9979 }
9980
9981 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
9982                                                struct vmcs12 *vmcs12)
9983 {
9984         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9985                 return 0;
9986
9987         if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
9988             !page_address_valid(vcpu, vmcs12->io_bitmap_b))
9989                 return -EINVAL;
9990
9991         return 0;
9992 }
9993
9994 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9995                                                 struct vmcs12 *vmcs12)
9996 {
9997         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9998                 return 0;
9999
10000         if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
10001                 return -EINVAL;
10002
10003         return 0;
10004 }
10005
10006 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
10007                                                 struct vmcs12 *vmcs12)
10008 {
10009         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10010                 return 0;
10011
10012         if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
10013                 return -EINVAL;
10014
10015         return 0;
10016 }
10017
10018 /*
10019  * Merge L0's and L1's MSR bitmap, return false to indicate that
10020  * we do not use the hardware.
10021  */
10022 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
10023                                                struct vmcs12 *vmcs12)
10024 {
10025         int msr;
10026         struct page *page;
10027         unsigned long *msr_bitmap_l1;
10028         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
10029
10030         /* This shortcut is ok because we support only x2APIC MSRs so far. */
10031         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
10032                 return false;
10033
10034         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
10035         if (is_error_page(page))
10036                 return false;
10037         msr_bitmap_l1 = (unsigned long *)kmap(page);
10038
10039         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
10040
10041         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
10042                 if (nested_cpu_has_apic_reg_virt(vmcs12))
10043                         for (msr = 0x800; msr <= 0x8ff; msr++)
10044                                 nested_vmx_disable_intercept_for_msr(
10045                                         msr_bitmap_l1, msr_bitmap_l0,
10046                                         msr, MSR_TYPE_R);
10047
10048                 nested_vmx_disable_intercept_for_msr(
10049                                 msr_bitmap_l1, msr_bitmap_l0,
10050                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
10051                                 MSR_TYPE_R | MSR_TYPE_W);
10052
10053                 if (nested_cpu_has_vid(vmcs12)) {
10054                         nested_vmx_disable_intercept_for_msr(
10055                                 msr_bitmap_l1, msr_bitmap_l0,
10056                                 APIC_BASE_MSR + (APIC_EOI >> 4),
10057                                 MSR_TYPE_W);
10058                         nested_vmx_disable_intercept_for_msr(
10059                                 msr_bitmap_l1, msr_bitmap_l0,
10060                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
10061                                 MSR_TYPE_W);
10062                 }
10063         }
10064         kunmap(page);
10065         kvm_release_page_clean(page);
10066
10067         return true;
10068 }
10069
10070 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
10071                                            struct vmcs12 *vmcs12)
10072 {
10073         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10074             !nested_cpu_has_apic_reg_virt(vmcs12) &&
10075             !nested_cpu_has_vid(vmcs12) &&
10076             !nested_cpu_has_posted_intr(vmcs12))
10077                 return 0;
10078
10079         /*
10080          * If virtualize x2apic mode is enabled,
10081          * virtualize apic access must be disabled.
10082          */
10083         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10084             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
10085                 return -EINVAL;
10086
10087         /*
10088          * If virtual interrupt delivery is enabled,
10089          * we must exit on external interrupts.
10090          */
10091         if (nested_cpu_has_vid(vmcs12) &&
10092            !nested_exit_on_intr(vcpu))
10093                 return -EINVAL;
10094
10095         /*
10096          * bits 15:8 should be zero in posted_intr_nv,
10097          * the descriptor address has been already checked
10098          * in nested_get_vmcs12_pages.
10099          */
10100         if (nested_cpu_has_posted_intr(vmcs12) &&
10101            (!nested_cpu_has_vid(vmcs12) ||
10102             !nested_exit_intr_ack_set(vcpu) ||
10103             vmcs12->posted_intr_nv & 0xff00))
10104                 return -EINVAL;
10105
10106         /* tpr shadow is needed by all apicv features. */
10107         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10108                 return -EINVAL;
10109
10110         return 0;
10111 }
10112
10113 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
10114                                        unsigned long count_field,
10115                                        unsigned long addr_field)
10116 {
10117         int maxphyaddr;
10118         u64 count, addr;
10119
10120         if (vmcs12_read_any(vcpu, count_field, &count) ||
10121             vmcs12_read_any(vcpu, addr_field, &addr)) {
10122                 WARN_ON(1);
10123                 return -EINVAL;
10124         }
10125         if (count == 0)
10126                 return 0;
10127         maxphyaddr = cpuid_maxphyaddr(vcpu);
10128         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
10129             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
10130                 pr_debug_ratelimited(
10131                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10132                         addr_field, maxphyaddr, count, addr);
10133                 return -EINVAL;
10134         }
10135         return 0;
10136 }
10137
10138 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
10139                                                 struct vmcs12 *vmcs12)
10140 {
10141         if (vmcs12->vm_exit_msr_load_count == 0 &&
10142             vmcs12->vm_exit_msr_store_count == 0 &&
10143             vmcs12->vm_entry_msr_load_count == 0)
10144                 return 0; /* Fast path */
10145         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
10146                                         VM_EXIT_MSR_LOAD_ADDR) ||
10147             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
10148                                         VM_EXIT_MSR_STORE_ADDR) ||
10149             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
10150                                         VM_ENTRY_MSR_LOAD_ADDR))
10151                 return -EINVAL;
10152         return 0;
10153 }
10154
10155 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
10156                                          struct vmcs12 *vmcs12)
10157 {
10158         u64 address = vmcs12->pml_address;
10159         int maxphyaddr = cpuid_maxphyaddr(vcpu);
10160
10161         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
10162                 if (!nested_cpu_has_ept(vmcs12) ||
10163                     !IS_ALIGNED(address, 4096)  ||
10164                     address >> maxphyaddr)
10165                         return -EINVAL;
10166         }
10167
10168         return 0;
10169 }
10170
10171 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
10172                                        struct vmx_msr_entry *e)
10173 {
10174         /* x2APIC MSR accesses are not allowed */
10175         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
10176                 return -EINVAL;
10177         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
10178             e->index == MSR_IA32_UCODE_REV)
10179                 return -EINVAL;
10180         if (e->reserved != 0)
10181                 return -EINVAL;
10182         return 0;
10183 }
10184
10185 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
10186                                      struct vmx_msr_entry *e)
10187 {
10188         if (e->index == MSR_FS_BASE ||
10189             e->index == MSR_GS_BASE ||
10190             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
10191             nested_vmx_msr_check_common(vcpu, e))
10192                 return -EINVAL;
10193         return 0;
10194 }
10195
10196 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
10197                                       struct vmx_msr_entry *e)
10198 {
10199         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
10200             nested_vmx_msr_check_common(vcpu, e))
10201                 return -EINVAL;
10202         return 0;
10203 }
10204
10205 /*
10206  * Load guest's/host's msr at nested entry/exit.
10207  * return 0 for success, entry index for failure.
10208  */
10209 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10210 {
10211         u32 i;
10212         struct vmx_msr_entry e;
10213         struct msr_data msr;
10214
10215         msr.host_initiated = false;
10216         for (i = 0; i < count; i++) {
10217                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
10218                                         &e, sizeof(e))) {
10219                         pr_debug_ratelimited(
10220                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10221                                 __func__, i, gpa + i * sizeof(e));
10222                         goto fail;
10223                 }
10224                 if (nested_vmx_load_msr_check(vcpu, &e)) {
10225                         pr_debug_ratelimited(
10226                                 "%s check failed (%u, 0x%x, 0x%x)\n",
10227                                 __func__, i, e.index, e.reserved);
10228                         goto fail;
10229                 }
10230                 msr.index = e.index;
10231                 msr.data = e.value;
10232                 if (kvm_set_msr(vcpu, &msr)) {
10233                         pr_debug_ratelimited(
10234                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10235                                 __func__, i, e.index, e.value);
10236                         goto fail;
10237                 }
10238         }
10239         return 0;
10240 fail:
10241         return i + 1;
10242 }
10243
10244 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10245 {
10246         u32 i;
10247         struct vmx_msr_entry e;
10248
10249         for (i = 0; i < count; i++) {
10250                 struct msr_data msr_info;
10251                 if (kvm_vcpu_read_guest(vcpu,
10252                                         gpa + i * sizeof(e),
10253                                         &e, 2 * sizeof(u32))) {
10254                         pr_debug_ratelimited(
10255                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10256                                 __func__, i, gpa + i * sizeof(e));
10257                         return -EINVAL;
10258                 }
10259                 if (nested_vmx_store_msr_check(vcpu, &e)) {
10260                         pr_debug_ratelimited(
10261                                 "%s check failed (%u, 0x%x, 0x%x)\n",
10262                                 __func__, i, e.index, e.reserved);
10263                         return -EINVAL;
10264                 }
10265                 msr_info.host_initiated = false;
10266                 msr_info.index = e.index;
10267                 if (kvm_get_msr(vcpu, &msr_info)) {
10268                         pr_debug_ratelimited(
10269                                 "%s cannot read MSR (%u, 0x%x)\n",
10270                                 __func__, i, e.index);
10271                         return -EINVAL;
10272                 }
10273                 if (kvm_vcpu_write_guest(vcpu,
10274                                          gpa + i * sizeof(e) +
10275                                              offsetof(struct vmx_msr_entry, value),
10276                                          &msr_info.data, sizeof(msr_info.data))) {
10277                         pr_debug_ratelimited(
10278                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10279                                 __func__, i, e.index, msr_info.data);
10280                         return -EINVAL;
10281                 }
10282         }
10283         return 0;
10284 }
10285
10286 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
10287 {
10288         unsigned long invalid_mask;
10289
10290         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
10291         return (val & invalid_mask) == 0;
10292 }
10293
10294 /*
10295  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10296  * emulating VM entry into a guest with EPT enabled.
10297  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10298  * is assigned to entry_failure_code on failure.
10299  */
10300 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
10301                                u32 *entry_failure_code)
10302 {
10303         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
10304                 if (!nested_cr3_valid(vcpu, cr3)) {
10305                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10306                         return 1;
10307                 }
10308
10309                 /*
10310                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10311                  * must not be dereferenced.
10312                  */
10313                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
10314                     !nested_ept) {
10315                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
10316                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
10317                                 return 1;
10318                         }
10319                 }
10320
10321                 vcpu->arch.cr3 = cr3;
10322                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
10323         }
10324
10325         kvm_mmu_reset_context(vcpu);
10326         return 0;
10327 }
10328
10329 /*
10330  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10331  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10332  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10333  * guest in a way that will both be appropriate to L1's requests, and our
10334  * needs. In addition to modifying the active vmcs (which is vmcs02), this
10335  * function also has additional necessary side-effects, like setting various
10336  * vcpu->arch fields.
10337  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10338  * is assigned to entry_failure_code on failure.
10339  */
10340 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10341                           bool from_vmentry, u32 *entry_failure_code)
10342 {
10343         struct vcpu_vmx *vmx = to_vmx(vcpu);
10344         u32 exec_control, vmcs12_exec_ctrl;
10345
10346         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10347         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10348         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10349         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10350         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10351         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10352         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10353         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10354         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10355         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10356         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10357         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10358         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10359         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10360         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10361         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10362         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10363         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10364         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10365         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10366         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10367         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10368         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10369         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10370         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10371         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10372         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10373         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10374         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10375         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10376         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10377         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10378         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10379         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10380         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10381         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10382
10383         if (from_vmentry &&
10384             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10385                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10386                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10387         } else {
10388                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10389                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10390         }
10391         if (from_vmentry) {
10392                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10393                              vmcs12->vm_entry_intr_info_field);
10394                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10395                              vmcs12->vm_entry_exception_error_code);
10396                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10397                              vmcs12->vm_entry_instruction_len);
10398                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10399                              vmcs12->guest_interruptibility_info);
10400                 vmx->loaded_vmcs->nmi_known_unmasked =
10401                         !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
10402         } else {
10403                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10404         }
10405         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10406         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10407         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10408                 vmcs12->guest_pending_dbg_exceptions);
10409         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10410         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10411
10412         if (nested_cpu_has_xsaves(vmcs12))
10413                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10414         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10415
10416         exec_control = vmcs12->pin_based_vm_exec_control;
10417
10418         /* Preemption timer setting is only taken from vmcs01.  */
10419         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10420         exec_control |= vmcs_config.pin_based_exec_ctrl;
10421         if (vmx->hv_deadline_tsc == -1)
10422                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10423
10424         /* Posted interrupts setting is only taken from vmcs12.  */
10425         if (nested_cpu_has_posted_intr(vmcs12)) {
10426                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10427                 vmx->nested.pi_pending = false;
10428                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
10429         } else {
10430                 exec_control &= ~PIN_BASED_POSTED_INTR;
10431         }
10432
10433         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10434
10435         vmx->nested.preemption_timer_expired = false;
10436         if (nested_cpu_has_preemption_timer(vmcs12))
10437                 vmx_start_preemption_timer(vcpu);
10438
10439         /*
10440          * Whether page-faults are trapped is determined by a combination of
10441          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10442          * If enable_ept, L0 doesn't care about page faults and we should
10443          * set all of these to L1's desires. However, if !enable_ept, L0 does
10444          * care about (at least some) page faults, and because it is not easy
10445          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10446          * to exit on each and every L2 page fault. This is done by setting
10447          * MASK=MATCH=0 and (see below) EB.PF=1.
10448          * Note that below we don't need special code to set EB.PF beyond the
10449          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10450          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10451          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10452          */
10453         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10454                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10455         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10456                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10457
10458         if (cpu_has_secondary_exec_ctrls()) {
10459                 exec_control = vmx->secondary_exec_control;
10460
10461                 /* Take the following fields only from vmcs12 */
10462                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10463                                   SECONDARY_EXEC_ENABLE_INVPCID |
10464                                   SECONDARY_EXEC_RDTSCP |
10465                                   SECONDARY_EXEC_XSAVES |
10466                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10467                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
10468                                   SECONDARY_EXEC_ENABLE_VMFUNC);
10469                 if (nested_cpu_has(vmcs12,
10470                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10471                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10472                                 ~SECONDARY_EXEC_ENABLE_PML;
10473                         exec_control |= vmcs12_exec_ctrl;
10474                 }
10475
10476                 /* All VMFUNCs are currently emulated through L0 vmexits.  */
10477                 if (exec_control & SECONDARY_EXEC_ENABLE_VMFUNC)
10478                         vmcs_write64(VM_FUNCTION_CONTROL, 0);
10479
10480                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10481                         vmcs_write64(EOI_EXIT_BITMAP0,
10482                                 vmcs12->eoi_exit_bitmap0);
10483                         vmcs_write64(EOI_EXIT_BITMAP1,
10484                                 vmcs12->eoi_exit_bitmap1);
10485                         vmcs_write64(EOI_EXIT_BITMAP2,
10486                                 vmcs12->eoi_exit_bitmap2);
10487                         vmcs_write64(EOI_EXIT_BITMAP3,
10488                                 vmcs12->eoi_exit_bitmap3);
10489                         vmcs_write16(GUEST_INTR_STATUS,
10490                                 vmcs12->guest_intr_status);
10491                 }
10492
10493                 /*
10494                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10495                  * nested_get_vmcs12_pages will either fix it up or
10496                  * remove the VM execution control.
10497                  */
10498                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10499                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10500
10501                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10502         }
10503
10504
10505         /*
10506          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10507          * Some constant fields are set here by vmx_set_constant_host_state().
10508          * Other fields are different per CPU, and will be set later when
10509          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10510          */
10511         vmx_set_constant_host_state(vmx);
10512
10513         /*
10514          * Set the MSR load/store lists to match L0's settings.
10515          */
10516         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10517         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10518         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10519         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10520         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10521
10522         /*
10523          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10524          * entry, but only if the current (host) sp changed from the value
10525          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10526          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10527          * here we just force the write to happen on entry.
10528          */
10529         vmx->host_rsp = 0;
10530
10531         exec_control = vmx_exec_control(vmx); /* L0's desires */
10532         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10533         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10534         exec_control &= ~CPU_BASED_TPR_SHADOW;
10535         exec_control |= vmcs12->cpu_based_vm_exec_control;
10536
10537         /*
10538          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10539          * nested_get_vmcs12_pages can't fix it up, the illegal value
10540          * will result in a VM entry failure.
10541          */
10542         if (exec_control & CPU_BASED_TPR_SHADOW) {
10543                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10544                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10545         } else {
10546 #ifdef CONFIG_X86_64
10547                 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
10548                                 CPU_BASED_CR8_STORE_EXITING;
10549 #endif
10550         }
10551
10552         /*
10553          * Merging of IO bitmap not currently supported.
10554          * Rather, exit every time.
10555          */
10556         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10557         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10558
10559         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10560
10561         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10562          * bitwise-or of what L1 wants to trap for L2, and what we want to
10563          * trap. Note that CR0.TS also needs updating - we do this later.
10564          */
10565         update_exception_bitmap(vcpu);
10566         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10567         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10568
10569         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10570          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10571          * bits are further modified by vmx_set_efer() below.
10572          */
10573         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10574
10575         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10576          * emulated by vmx_set_efer(), below.
10577          */
10578         vm_entry_controls_init(vmx,
10579                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10580                         ~VM_ENTRY_IA32E_MODE) |
10581                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10582
10583         if (from_vmentry &&
10584             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10585                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10586                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10587         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10588                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10589         }
10590
10591         set_cr4_guest_host_mask(vmx);
10592
10593         if (from_vmentry &&
10594             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10595                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10596
10597         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10598                 vmcs_write64(TSC_OFFSET,
10599                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10600         else
10601                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10602         if (kvm_has_tsc_control)
10603                 decache_tsc_multiplier(vmx);
10604
10605         if (enable_vpid) {
10606                 /*
10607                  * There is no direct mapping between vpid02 and vpid12, the
10608                  * vpid02 is per-vCPU for L0 and reused while the value of
10609                  * vpid12 is changed w/ one invvpid during nested vmentry.
10610                  * The vpid12 is allocated by L1 for L2, so it will not
10611                  * influence global bitmap(for vpid01 and vpid02 allocation)
10612                  * even if spawn a lot of nested vCPUs.
10613                  */
10614                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10615                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10616                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10617                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10618                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10619                         }
10620                 } else {
10621                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10622                         vmx_flush_tlb(vcpu);
10623                 }
10624
10625         }
10626
10627         if (enable_pml) {
10628                 /*
10629                  * Conceptually we want to copy the PML address and index from
10630                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10631                  * since we always flush the log on each vmexit, this happens
10632                  * to be equivalent to simply resetting the fields in vmcs02.
10633                  */
10634                 ASSERT(vmx->pml_pg);
10635                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10636                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10637         }
10638
10639         if (nested_cpu_has_ept(vmcs12)) {
10640                 if (nested_ept_init_mmu_context(vcpu)) {
10641                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10642                         return 1;
10643                 }
10644         } else if (nested_cpu_has2(vmcs12,
10645                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10646                 vmx_flush_tlb_ept_only(vcpu);
10647         }
10648
10649         /*
10650          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10651          * bits which we consider mandatory enabled.
10652          * The CR0_READ_SHADOW is what L2 should have expected to read given
10653          * the specifications by L1; It's not enough to take
10654          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10655          * have more bits than L1 expected.
10656          */
10657         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10658         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10659
10660         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10661         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10662
10663         if (from_vmentry &&
10664             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10665                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10666         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10667                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10668         else
10669                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10670         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10671         vmx_set_efer(vcpu, vcpu->arch.efer);
10672
10673         /* Shadow page tables on either EPT or shadow page tables. */
10674         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10675                                 entry_failure_code))
10676                 return 1;
10677
10678         if (!enable_ept)
10679                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10680
10681         /*
10682          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10683          */
10684         if (enable_ept) {
10685                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10686                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10687                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10688                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10689         }
10690
10691         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10692         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10693         return 0;
10694 }
10695
10696 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10697 {
10698         struct vcpu_vmx *vmx = to_vmx(vcpu);
10699
10700         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10701             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10702                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10703
10704         if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10705                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10706
10707         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10708                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10709
10710         if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
10711                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10712
10713         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10714                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10715
10716         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10717                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10718
10719         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10720                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10721
10722         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10723                                 vmx->nested.nested_vmx_procbased_ctls_low,
10724                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10725             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10726              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10727                                  vmx->nested.nested_vmx_secondary_ctls_low,
10728                                  vmx->nested.nested_vmx_secondary_ctls_high)) ||
10729             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10730                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10731                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10732             !vmx_control_verify(vmcs12->vm_exit_controls,
10733                                 vmx->nested.nested_vmx_exit_ctls_low,
10734                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10735             !vmx_control_verify(vmcs12->vm_entry_controls,
10736                                 vmx->nested.nested_vmx_entry_ctls_low,
10737                                 vmx->nested.nested_vmx_entry_ctls_high))
10738                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10739
10740         if (nested_cpu_has_vmfunc(vmcs12)) {
10741                 if (vmcs12->vm_function_control &
10742                     ~vmx->nested.nested_vmx_vmfunc_controls)
10743                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10744
10745                 if (nested_cpu_has_eptp_switching(vmcs12)) {
10746                         if (!nested_cpu_has_ept(vmcs12) ||
10747                             !page_address_valid(vcpu, vmcs12->eptp_list_address))
10748                                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10749                 }
10750         }
10751
10752         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10753                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10754
10755         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10756             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10757             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10758                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10759
10760         return 0;
10761 }
10762
10763 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10764                                   u32 *exit_qual)
10765 {
10766         bool ia32e;
10767
10768         *exit_qual = ENTRY_FAIL_DEFAULT;
10769
10770         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10771             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10772                 return 1;
10773
10774         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10775             vmcs12->vmcs_link_pointer != -1ull) {
10776                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10777                 return 1;
10778         }
10779
10780         /*
10781          * If the load IA32_EFER VM-entry control is 1, the following checks
10782          * are performed on the field for the IA32_EFER MSR:
10783          * - Bits reserved in the IA32_EFER MSR must be 0.
10784          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10785          *   the IA-32e mode guest VM-exit control. It must also be identical
10786          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10787          *   CR0.PG) is 1.
10788          */
10789         if (to_vmx(vcpu)->nested.nested_run_pending &&
10790             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10791                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10792                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10793                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10794                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10795                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10796                         return 1;
10797         }
10798
10799         /*
10800          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10801          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10802          * the values of the LMA and LME bits in the field must each be that of
10803          * the host address-space size VM-exit control.
10804          */
10805         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10806                 ia32e = (vmcs12->vm_exit_controls &
10807                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10808                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10809                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10810                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10811                         return 1;
10812         }
10813
10814         return 0;
10815 }
10816
10817 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10818 {
10819         struct vcpu_vmx *vmx = to_vmx(vcpu);
10820         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10821         struct loaded_vmcs *vmcs02;
10822         u32 msr_entry_idx;
10823         u32 exit_qual;
10824
10825         vmcs02 = nested_get_current_vmcs02(vmx);
10826         if (!vmcs02)
10827                 return -ENOMEM;
10828
10829         enter_guest_mode(vcpu);
10830
10831         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10832                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10833
10834         vmx_switch_vmcs(vcpu, vmcs02);
10835         vmx_segment_cache_clear(vmx);
10836
10837         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10838                 leave_guest_mode(vcpu);
10839                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10840                 nested_vmx_entry_failure(vcpu, vmcs12,
10841                                          EXIT_REASON_INVALID_STATE, exit_qual);
10842                 return 1;
10843         }
10844
10845         nested_get_vmcs12_pages(vcpu, vmcs12);
10846
10847         msr_entry_idx = nested_vmx_load_msr(vcpu,
10848                                             vmcs12->vm_entry_msr_load_addr,
10849                                             vmcs12->vm_entry_msr_load_count);
10850         if (msr_entry_idx) {
10851                 leave_guest_mode(vcpu);
10852                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10853                 nested_vmx_entry_failure(vcpu, vmcs12,
10854                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10855                 return 1;
10856         }
10857
10858         /*
10859          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10860          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10861          * returned as far as L1 is concerned. It will only return (and set
10862          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10863          */
10864         return 0;
10865 }
10866
10867 /*
10868  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10869  * for running an L2 nested guest.
10870  */
10871 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10872 {
10873         struct vmcs12 *vmcs12;
10874         struct vcpu_vmx *vmx = to_vmx(vcpu);
10875         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
10876         u32 exit_qual;
10877         int ret;
10878
10879         if (!nested_vmx_check_permission(vcpu))
10880                 return 1;
10881
10882         if (!nested_vmx_check_vmcs12(vcpu))
10883                 goto out;
10884
10885         vmcs12 = get_vmcs12(vcpu);
10886
10887         if (enable_shadow_vmcs)
10888                 copy_shadow_to_vmcs12(vmx);
10889
10890         /*
10891          * The nested entry process starts with enforcing various prerequisites
10892          * on vmcs12 as required by the Intel SDM, and act appropriately when
10893          * they fail: As the SDM explains, some conditions should cause the
10894          * instruction to fail, while others will cause the instruction to seem
10895          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10896          * To speed up the normal (success) code path, we should avoid checking
10897          * for misconfigurations which will anyway be caught by the processor
10898          * when using the merged vmcs02.
10899          */
10900         if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
10901                 nested_vmx_failValid(vcpu,
10902                                      VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
10903                 goto out;
10904         }
10905
10906         if (vmcs12->launch_state == launch) {
10907                 nested_vmx_failValid(vcpu,
10908                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10909                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10910                 goto out;
10911         }
10912
10913         ret = check_vmentry_prereqs(vcpu, vmcs12);
10914         if (ret) {
10915                 nested_vmx_failValid(vcpu, ret);
10916                 goto out;
10917         }
10918
10919         /*
10920          * After this point, the trap flag no longer triggers a singlestep trap
10921          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10922          * This is not 100% correct; for performance reasons, we delegate most
10923          * of the checks on host state to the processor.  If those fail,
10924          * the singlestep trap is missed.
10925          */
10926         skip_emulated_instruction(vcpu);
10927
10928         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10929         if (ret) {
10930                 nested_vmx_entry_failure(vcpu, vmcs12,
10931                                          EXIT_REASON_INVALID_STATE, exit_qual);
10932                 return 1;
10933         }
10934
10935         /*
10936          * We're finally done with prerequisite checking, and can start with
10937          * the nested entry.
10938          */
10939
10940         ret = enter_vmx_non_root_mode(vcpu, true);
10941         if (ret)
10942                 return ret;
10943
10944         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10945                 return kvm_vcpu_halt(vcpu);
10946
10947         vmx->nested.nested_run_pending = 1;
10948
10949         return 1;
10950
10951 out:
10952         return kvm_skip_emulated_instruction(vcpu);
10953 }
10954
10955 /*
10956  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10957  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10958  * This function returns the new value we should put in vmcs12.guest_cr0.
10959  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10960  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10961  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10962  *     didn't trap the bit, because if L1 did, so would L0).
10963  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10964  *     been modified by L2, and L1 knows it. So just leave the old value of
10965  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10966  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10967  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10968  *     changed these bits, and therefore they need to be updated, but L0
10969  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10970  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10971  */
10972 static inline unsigned long
10973 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10974 {
10975         return
10976         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10977         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10978         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10979                         vcpu->arch.cr0_guest_owned_bits));
10980 }
10981
10982 static inline unsigned long
10983 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10984 {
10985         return
10986         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10987         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10988         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10989                         vcpu->arch.cr4_guest_owned_bits));
10990 }
10991
10992 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10993                                        struct vmcs12 *vmcs12)
10994 {
10995         u32 idt_vectoring;
10996         unsigned int nr;
10997
10998         if (vcpu->arch.exception.injected) {
10999                 nr = vcpu->arch.exception.nr;
11000                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11001
11002                 if (kvm_exception_is_soft(nr)) {
11003                         vmcs12->vm_exit_instruction_len =
11004                                 vcpu->arch.event_exit_inst_len;
11005                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
11006                 } else
11007                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
11008
11009                 if (vcpu->arch.exception.has_error_code) {
11010                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
11011                         vmcs12->idt_vectoring_error_code =
11012                                 vcpu->arch.exception.error_code;
11013                 }
11014
11015                 vmcs12->idt_vectoring_info_field = idt_vectoring;
11016         } else if (vcpu->arch.nmi_injected) {
11017                 vmcs12->idt_vectoring_info_field =
11018                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
11019         } else if (vcpu->arch.interrupt.pending) {
11020                 nr = vcpu->arch.interrupt.nr;
11021                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11022
11023                 if (vcpu->arch.interrupt.soft) {
11024                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
11025                         vmcs12->vm_entry_instruction_len =
11026                                 vcpu->arch.event_exit_inst_len;
11027                 } else
11028                         idt_vectoring |= INTR_TYPE_EXT_INTR;
11029
11030                 vmcs12->idt_vectoring_info_field = idt_vectoring;
11031         }
11032 }
11033
11034 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
11035 {
11036         struct vcpu_vmx *vmx = to_vmx(vcpu);
11037         unsigned long exit_qual;
11038
11039         if (kvm_event_needs_reinjection(vcpu))
11040                 return -EBUSY;
11041
11042         if (vcpu->arch.exception.pending &&
11043                 nested_vmx_check_exception(vcpu, &exit_qual)) {
11044                 if (vmx->nested.nested_run_pending)
11045                         return -EBUSY;
11046                 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
11047                 vcpu->arch.exception.pending = false;
11048                 return 0;
11049         }
11050
11051         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
11052             vmx->nested.preemption_timer_expired) {
11053                 if (vmx->nested.nested_run_pending)
11054                         return -EBUSY;
11055                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
11056                 return 0;
11057         }
11058
11059         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
11060                 if (vmx->nested.nested_run_pending)
11061                         return -EBUSY;
11062                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
11063                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
11064                                   INTR_INFO_VALID_MASK, 0);
11065                 /*
11066                  * The NMI-triggered VM exit counts as injection:
11067                  * clear this one and block further NMIs.
11068                  */
11069                 vcpu->arch.nmi_pending = 0;
11070                 vmx_set_nmi_mask(vcpu, true);
11071                 return 0;
11072         }
11073
11074         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
11075             nested_exit_on_intr(vcpu)) {
11076                 if (vmx->nested.nested_run_pending)
11077                         return -EBUSY;
11078                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
11079                 return 0;
11080         }
11081
11082         vmx_complete_nested_posted_interrupt(vcpu);
11083         return 0;
11084 }
11085
11086 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
11087 {
11088         ktime_t remaining =
11089                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
11090         u64 value;
11091
11092         if (ktime_to_ns(remaining) <= 0)
11093                 return 0;
11094
11095         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
11096         do_div(value, 1000000);
11097         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
11098 }
11099
11100 /*
11101  * Update the guest state fields of vmcs12 to reflect changes that
11102  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11103  * VM-entry controls is also updated, since this is really a guest
11104  * state bit.)
11105  */
11106 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11107 {
11108         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
11109         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
11110
11111         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
11112         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
11113         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
11114
11115         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
11116         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
11117         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
11118         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
11119         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
11120         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
11121         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
11122         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
11123         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
11124         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
11125         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
11126         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
11127         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
11128         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
11129         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
11130         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
11131         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
11132         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
11133         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
11134         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
11135         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
11136         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
11137         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
11138         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
11139         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
11140         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
11141         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
11142         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
11143         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
11144         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
11145         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
11146         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
11147         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
11148         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
11149         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
11150         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
11151
11152         vmcs12->guest_interruptibility_info =
11153                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
11154         vmcs12->guest_pending_dbg_exceptions =
11155                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
11156         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
11157                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
11158         else
11159                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
11160
11161         if (nested_cpu_has_preemption_timer(vmcs12)) {
11162                 if (vmcs12->vm_exit_controls &
11163                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
11164                         vmcs12->vmx_preemption_timer_value =
11165                                 vmx_get_preemption_timer_value(vcpu);
11166                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
11167         }
11168
11169         /*
11170          * In some cases (usually, nested EPT), L2 is allowed to change its
11171          * own CR3 without exiting. If it has changed it, we must keep it.
11172          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11173          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11174          *
11175          * Additionally, restore L2's PDPTR to vmcs12.
11176          */
11177         if (enable_ept) {
11178                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
11179                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
11180                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
11181                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
11182                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
11183         }
11184
11185         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
11186
11187         if (nested_cpu_has_vid(vmcs12))
11188                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
11189
11190         vmcs12->vm_entry_controls =
11191                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
11192                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
11193
11194         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
11195                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
11196                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11197         }
11198
11199         /* TODO: These cannot have changed unless we have MSR bitmaps and
11200          * the relevant bit asks not to trap the change */
11201         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
11202                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
11203         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
11204                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
11205         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
11206         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
11207         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
11208         if (kvm_mpx_supported())
11209                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
11210 }
11211
11212 /*
11213  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11214  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11215  * and this function updates it to reflect the changes to the guest state while
11216  * L2 was running (and perhaps made some exits which were handled directly by L0
11217  * without going back to L1), and to reflect the exit reason.
11218  * Note that we do not have to copy here all VMCS fields, just those that
11219  * could have changed by the L2 guest or the exit - i.e., the guest-state and
11220  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11221  * which already writes to vmcs12 directly.
11222  */
11223 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11224                            u32 exit_reason, u32 exit_intr_info,
11225                            unsigned long exit_qualification)
11226 {
11227         /* update guest state fields: */
11228         sync_vmcs12(vcpu, vmcs12);
11229
11230         /* update exit information fields: */
11231
11232         vmcs12->vm_exit_reason = exit_reason;
11233         vmcs12->exit_qualification = exit_qualification;
11234         vmcs12->vm_exit_intr_info = exit_intr_info;
11235
11236         vmcs12->idt_vectoring_info_field = 0;
11237         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
11238         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
11239
11240         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
11241                 vmcs12->launch_state = 1;
11242
11243                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11244                  * instead of reading the real value. */
11245                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
11246
11247                 /*
11248                  * Transfer the event that L0 or L1 may wanted to inject into
11249                  * L2 to IDT_VECTORING_INFO_FIELD.
11250                  */
11251                 vmcs12_save_pending_event(vcpu, vmcs12);
11252         }
11253
11254         /*
11255          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11256          * preserved above and would only end up incorrectly in L1.
11257          */
11258         vcpu->arch.nmi_injected = false;
11259         kvm_clear_exception_queue(vcpu);
11260         kvm_clear_interrupt_queue(vcpu);
11261 }
11262
11263 /*
11264  * A part of what we need to when the nested L2 guest exits and we want to
11265  * run its L1 parent, is to reset L1's guest state to the host state specified
11266  * in vmcs12.
11267  * This function is to be called not only on normal nested exit, but also on
11268  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11269  * Failures During or After Loading Guest State").
11270  * This function should be called when the active VMCS is L1's (vmcs01).
11271  */
11272 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
11273                                    struct vmcs12 *vmcs12)
11274 {
11275         struct kvm_segment seg;
11276         u32 entry_failure_code;
11277
11278         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
11279                 vcpu->arch.efer = vmcs12->host_ia32_efer;
11280         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11281                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11282         else
11283                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11284         vmx_set_efer(vcpu, vcpu->arch.efer);
11285
11286         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
11287         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
11288         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
11289         /*
11290          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11291          * actually changed, because vmx_set_cr0 refers to efer set above.
11292          *
11293          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11294          * (KVM doesn't change it);
11295          */
11296         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
11297         vmx_set_cr0(vcpu, vmcs12->host_cr0);
11298
11299         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
11300         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
11301         vmx_set_cr4(vcpu, vmcs12->host_cr4);
11302
11303         nested_ept_uninit_mmu_context(vcpu);
11304
11305         /*
11306          * Only PDPTE load can fail as the value of cr3 was checked on entry and
11307          * couldn't have changed.
11308          */
11309         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
11310                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
11311
11312         if (!enable_ept)
11313                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
11314
11315         if (enable_vpid) {
11316                 /*
11317                  * Trivially support vpid by letting L2s share their parent
11318                  * L1's vpid. TODO: move to a more elaborate solution, giving
11319                  * each L2 its own vpid and exposing the vpid feature to L1.
11320                  */
11321                 vmx_flush_tlb(vcpu);
11322         }
11323         /* Restore posted intr vector. */
11324         if (nested_cpu_has_posted_intr(vmcs12))
11325                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
11326
11327         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
11328         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
11329         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
11330         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
11331         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
11332
11333         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
11334         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
11335                 vmcs_write64(GUEST_BNDCFGS, 0);
11336
11337         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
11338                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
11339                 vcpu->arch.pat = vmcs12->host_ia32_pat;
11340         }
11341         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
11342                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
11343                         vmcs12->host_ia32_perf_global_ctrl);
11344
11345         /* Set L1 segment info according to Intel SDM
11346             27.5.2 Loading Host Segment and Descriptor-Table Registers */
11347         seg = (struct kvm_segment) {
11348                 .base = 0,
11349                 .limit = 0xFFFFFFFF,
11350                 .selector = vmcs12->host_cs_selector,
11351                 .type = 11,
11352                 .present = 1,
11353                 .s = 1,
11354                 .g = 1
11355         };
11356         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11357                 seg.l = 1;
11358         else
11359                 seg.db = 1;
11360         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
11361         seg = (struct kvm_segment) {
11362                 .base = 0,
11363                 .limit = 0xFFFFFFFF,
11364                 .type = 3,
11365                 .present = 1,
11366                 .s = 1,
11367                 .db = 1,
11368                 .g = 1
11369         };
11370         seg.selector = vmcs12->host_ds_selector;
11371         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11372         seg.selector = vmcs12->host_es_selector;
11373         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11374         seg.selector = vmcs12->host_ss_selector;
11375         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11376         seg.selector = vmcs12->host_fs_selector;
11377         seg.base = vmcs12->host_fs_base;
11378         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11379         seg.selector = vmcs12->host_gs_selector;
11380         seg.base = vmcs12->host_gs_base;
11381         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11382         seg = (struct kvm_segment) {
11383                 .base = vmcs12->host_tr_base,
11384                 .limit = 0x67,
11385                 .selector = vmcs12->host_tr_selector,
11386                 .type = 11,
11387                 .present = 1
11388         };
11389         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11390
11391         kvm_set_dr(vcpu, 7, 0x400);
11392         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11393
11394         if (cpu_has_vmx_msr_bitmap())
11395                 vmx_set_msr_bitmap(vcpu);
11396
11397         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11398                                 vmcs12->vm_exit_msr_load_count))
11399                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11400 }
11401
11402 /*
11403  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11404  * and modify vmcs12 to make it see what it would expect to see there if
11405  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11406  */
11407 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11408                               u32 exit_intr_info,
11409                               unsigned long exit_qualification)
11410 {
11411         struct vcpu_vmx *vmx = to_vmx(vcpu);
11412         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11413
11414         /* trying to cancel vmlaunch/vmresume is a bug */
11415         WARN_ON_ONCE(vmx->nested.nested_run_pending);
11416
11417         /*
11418          * The only expected VM-instruction error is "VM entry with
11419          * invalid control field(s)." Anything else indicates a
11420          * problem with L0.
11421          */
11422         WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
11423                                    VMXERR_ENTRY_INVALID_CONTROL_FIELD));
11424
11425         leave_guest_mode(vcpu);
11426
11427         if (likely(!vmx->fail)) {
11428                 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11429                                exit_qualification);
11430
11431                 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11432                                          vmcs12->vm_exit_msr_store_count))
11433                         nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11434         }
11435
11436         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11437         vm_entry_controls_reset_shadow(vmx);
11438         vm_exit_controls_reset_shadow(vmx);
11439         vmx_segment_cache_clear(vmx);
11440
11441         /* if no vmcs02 cache requested, remove the one we used */
11442         if (VMCS02_POOL_SIZE == 0)
11443                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11444
11445         /* Update any VMCS fields that might have changed while L2 ran */
11446         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11447         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11448         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11449         if (vmx->hv_deadline_tsc == -1)
11450                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11451                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11452         else
11453                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11454                               PIN_BASED_VMX_PREEMPTION_TIMER);
11455         if (kvm_has_tsc_control)
11456                 decache_tsc_multiplier(vmx);
11457
11458         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11459                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11460                 vmx_set_virtual_x2apic_mode(vcpu,
11461                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11462         } else if (!nested_cpu_has_ept(vmcs12) &&
11463                    nested_cpu_has2(vmcs12,
11464                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11465                 vmx_flush_tlb_ept_only(vcpu);
11466         }
11467
11468         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11469         vmx->host_rsp = 0;
11470
11471         /* Unpin physical memory we referred to in vmcs02 */
11472         if (vmx->nested.apic_access_page) {
11473                 kvm_release_page_dirty(vmx->nested.apic_access_page);
11474                 vmx->nested.apic_access_page = NULL;
11475         }
11476         if (vmx->nested.virtual_apic_page) {
11477                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
11478                 vmx->nested.virtual_apic_page = NULL;
11479         }
11480         if (vmx->nested.pi_desc_page) {
11481                 kunmap(vmx->nested.pi_desc_page);
11482                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
11483                 vmx->nested.pi_desc_page = NULL;
11484                 vmx->nested.pi_desc = NULL;
11485         }
11486
11487         /*
11488          * We are now running in L2, mmu_notifier will force to reload the
11489          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11490          */
11491         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11492
11493         if (enable_shadow_vmcs)
11494                 vmx->nested.sync_shadow_vmcs = true;
11495
11496         /* in case we halted in L2 */
11497         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11498
11499         if (likely(!vmx->fail)) {
11500                 /*
11501                  * TODO: SDM says that with acknowledge interrupt on
11502                  * exit, bit 31 of the VM-exit interrupt information
11503                  * (valid interrupt) is always set to 1 on
11504                  * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
11505                  * need kvm_cpu_has_interrupt().  See the commit
11506                  * message for details.
11507                  */
11508                 if (nested_exit_intr_ack_set(vcpu) &&
11509                     exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
11510                     kvm_cpu_has_interrupt(vcpu)) {
11511                         int irq = kvm_cpu_get_interrupt(vcpu);
11512                         WARN_ON(irq < 0);
11513                         vmcs12->vm_exit_intr_info = irq |
11514                                 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11515                 }
11516
11517                 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11518                                                vmcs12->exit_qualification,
11519                                                vmcs12->idt_vectoring_info_field,
11520                                                vmcs12->vm_exit_intr_info,
11521                                                vmcs12->vm_exit_intr_error_code,
11522                                                KVM_ISA_VMX);
11523
11524                 load_vmcs12_host_state(vcpu, vmcs12);
11525
11526                 return;
11527         }
11528
11529         /*
11530          * After an early L2 VM-entry failure, we're now back
11531          * in L1 which thinks it just finished a VMLAUNCH or
11532          * VMRESUME instruction, so we need to set the failure
11533          * flag and the VM-instruction error field of the VMCS
11534          * accordingly.
11535          */
11536         nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
11537         /*
11538          * The emulated instruction was already skipped in
11539          * nested_vmx_run, but the updated RIP was never
11540          * written back to the vmcs01.
11541          */
11542         skip_emulated_instruction(vcpu);
11543         vmx->fail = 0;
11544 }
11545
11546 /*
11547  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11548  */
11549 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11550 {
11551         if (is_guest_mode(vcpu)) {
11552                 to_vmx(vcpu)->nested.nested_run_pending = 0;
11553                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11554         }
11555         free_nested(to_vmx(vcpu));
11556 }
11557
11558 /*
11559  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11560  * 23.7 "VM-entry failures during or after loading guest state" (this also
11561  * lists the acceptable exit-reason and exit-qualification parameters).
11562  * It should only be called before L2 actually succeeded to run, and when
11563  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11564  */
11565 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11566                         struct vmcs12 *vmcs12,
11567                         u32 reason, unsigned long qualification)
11568 {
11569         load_vmcs12_host_state(vcpu, vmcs12);
11570         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11571         vmcs12->exit_qualification = qualification;
11572         nested_vmx_succeed(vcpu);
11573         if (enable_shadow_vmcs)
11574                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11575 }
11576
11577 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11578                                struct x86_instruction_info *info,
11579                                enum x86_intercept_stage stage)
11580 {
11581         return X86EMUL_CONTINUE;
11582 }
11583
11584 #ifdef CONFIG_X86_64
11585 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11586 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11587                                   u64 divisor, u64 *result)
11588 {
11589         u64 low = a << shift, high = a >> (64 - shift);
11590
11591         /* To avoid the overflow on divq */
11592         if (high >= divisor)
11593                 return 1;
11594
11595         /* Low hold the result, high hold rem which is discarded */
11596         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11597             "rm" (divisor), "0" (low), "1" (high));
11598         *result = low;
11599
11600         return 0;
11601 }
11602
11603 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11604 {
11605         struct vcpu_vmx *vmx = to_vmx(vcpu);
11606         u64 tscl = rdtsc();
11607         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11608         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11609
11610         /* Convert to host delta tsc if tsc scaling is enabled */
11611         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11612                         u64_shl_div_u64(delta_tsc,
11613                                 kvm_tsc_scaling_ratio_frac_bits,
11614                                 vcpu->arch.tsc_scaling_ratio,
11615                                 &delta_tsc))
11616                 return -ERANGE;
11617
11618         /*
11619          * If the delta tsc can't fit in the 32 bit after the multi shift,
11620          * we can't use the preemption timer.
11621          * It's possible that it fits on later vmentries, but checking
11622          * on every vmentry is costly so we just use an hrtimer.
11623          */
11624         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11625                 return -ERANGE;
11626
11627         vmx->hv_deadline_tsc = tscl + delta_tsc;
11628         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11629                         PIN_BASED_VMX_PREEMPTION_TIMER);
11630
11631         return delta_tsc == 0;
11632 }
11633
11634 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11635 {
11636         struct vcpu_vmx *vmx = to_vmx(vcpu);
11637         vmx->hv_deadline_tsc = -1;
11638         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11639                         PIN_BASED_VMX_PREEMPTION_TIMER);
11640 }
11641 #endif
11642
11643 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11644 {
11645         if (ple_gap)
11646                 shrink_ple_window(vcpu);
11647 }
11648
11649 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11650                                      struct kvm_memory_slot *slot)
11651 {
11652         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11653         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11654 }
11655
11656 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11657                                        struct kvm_memory_slot *slot)
11658 {
11659         kvm_mmu_slot_set_dirty(kvm, slot);
11660 }
11661
11662 static void vmx_flush_log_dirty(struct kvm *kvm)
11663 {
11664         kvm_flush_pml_buffers(kvm);
11665 }
11666
11667 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11668 {
11669         struct vmcs12 *vmcs12;
11670         struct vcpu_vmx *vmx = to_vmx(vcpu);
11671         gpa_t gpa;
11672         struct page *page = NULL;
11673         u64 *pml_address;
11674
11675         if (is_guest_mode(vcpu)) {
11676                 WARN_ON_ONCE(vmx->nested.pml_full);
11677
11678                 /*
11679                  * Check if PML is enabled for the nested guest.
11680                  * Whether eptp bit 6 is set is already checked
11681                  * as part of A/D emulation.
11682                  */
11683                 vmcs12 = get_vmcs12(vcpu);
11684                 if (!nested_cpu_has_pml(vmcs12))
11685                         return 0;
11686
11687                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
11688                         vmx->nested.pml_full = true;
11689                         return 1;
11690                 }
11691
11692                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11693
11694                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
11695                 if (is_error_page(page))
11696                         return 0;
11697
11698                 pml_address = kmap(page);
11699                 pml_address[vmcs12->guest_pml_index--] = gpa;
11700                 kunmap(page);
11701                 kvm_release_page_clean(page);
11702         }
11703
11704         return 0;
11705 }
11706
11707 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11708                                            struct kvm_memory_slot *memslot,
11709                                            gfn_t offset, unsigned long mask)
11710 {
11711         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11712 }
11713
11714 static void __pi_post_block(struct kvm_vcpu *vcpu)
11715 {
11716         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11717         struct pi_desc old, new;
11718         unsigned int dest;
11719
11720         do {
11721                 old.control = new.control = pi_desc->control;
11722                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
11723                      "Wakeup handler not enabled while the VCPU is blocked\n");
11724
11725                 dest = cpu_physical_id(vcpu->cpu);
11726
11727                 if (x2apic_enabled())
11728                         new.ndst = dest;
11729                 else
11730                         new.ndst = (dest << 8) & 0xFF00;
11731
11732                 /* set 'NV' to 'notification vector' */
11733                 new.nv = POSTED_INTR_VECTOR;
11734         } while (cmpxchg64(&pi_desc->control, old.control,
11735                            new.control) != old.control);
11736
11737         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
11738                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11739                 list_del(&vcpu->blocked_vcpu_list);
11740                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11741                 vcpu->pre_pcpu = -1;
11742         }
11743 }
11744
11745 /*
11746  * This routine does the following things for vCPU which is going
11747  * to be blocked if VT-d PI is enabled.
11748  * - Store the vCPU to the wakeup list, so when interrupts happen
11749  *   we can find the right vCPU to wake up.
11750  * - Change the Posted-interrupt descriptor as below:
11751  *      'NDST' <-- vcpu->pre_pcpu
11752  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11753  * - If 'ON' is set during this process, which means at least one
11754  *   interrupt is posted for this vCPU, we cannot block it, in
11755  *   this case, return 1, otherwise, return 0.
11756  *
11757  */
11758 static int pi_pre_block(struct kvm_vcpu *vcpu)
11759 {
11760         unsigned int dest;
11761         struct pi_desc old, new;
11762         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11763
11764         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11765                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11766                 !kvm_vcpu_apicv_active(vcpu))
11767                 return 0;
11768
11769         WARN_ON(irqs_disabled());
11770         local_irq_disable();
11771         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
11772                 vcpu->pre_pcpu = vcpu->cpu;
11773                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11774                 list_add_tail(&vcpu->blocked_vcpu_list,
11775                               &per_cpu(blocked_vcpu_on_cpu,
11776                                        vcpu->pre_pcpu));
11777                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11778         }
11779
11780         do {
11781                 old.control = new.control = pi_desc->control;
11782
11783                 WARN((pi_desc->sn == 1),
11784                      "Warning: SN field of posted-interrupts "
11785                      "is set before blocking\n");
11786
11787                 /*
11788                  * Since vCPU can be preempted during this process,
11789                  * vcpu->cpu could be different with pre_pcpu, we
11790                  * need to set pre_pcpu as the destination of wakeup
11791                  * notification event, then we can find the right vCPU
11792                  * to wakeup in wakeup handler if interrupts happen
11793                  * when the vCPU is in blocked state.
11794                  */
11795                 dest = cpu_physical_id(vcpu->pre_pcpu);
11796
11797                 if (x2apic_enabled())
11798                         new.ndst = dest;
11799                 else
11800                         new.ndst = (dest << 8) & 0xFF00;
11801
11802                 /* set 'NV' to 'wakeup vector' */
11803                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11804         } while (cmpxchg64(&pi_desc->control, old.control,
11805                            new.control) != old.control);
11806
11807         /* We should not block the vCPU if an interrupt is posted for it.  */
11808         if (pi_test_on(pi_desc) == 1)
11809                 __pi_post_block(vcpu);
11810
11811         local_irq_enable();
11812         return (vcpu->pre_pcpu == -1);
11813 }
11814
11815 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11816 {
11817         if (pi_pre_block(vcpu))
11818                 return 1;
11819
11820         if (kvm_lapic_hv_timer_in_use(vcpu))
11821                 kvm_lapic_switch_to_sw_timer(vcpu);
11822
11823         return 0;
11824 }
11825
11826 static void pi_post_block(struct kvm_vcpu *vcpu)
11827 {
11828         if (vcpu->pre_pcpu == -1)
11829                 return;
11830
11831         WARN_ON(irqs_disabled());
11832         local_irq_disable();
11833         __pi_post_block(vcpu);
11834         local_irq_enable();
11835 }
11836
11837 static void vmx_post_block(struct kvm_vcpu *vcpu)
11838 {
11839         if (kvm_x86_ops->set_hv_timer)
11840                 kvm_lapic_switch_to_hv_timer(vcpu);
11841
11842         pi_post_block(vcpu);
11843 }
11844
11845 /*
11846  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11847  *
11848  * @kvm: kvm
11849  * @host_irq: host irq of the interrupt
11850  * @guest_irq: gsi of the interrupt
11851  * @set: set or unset PI
11852  * returns 0 on success, < 0 on failure
11853  */
11854 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11855                               uint32_t guest_irq, bool set)
11856 {
11857         struct kvm_kernel_irq_routing_entry *e;
11858         struct kvm_irq_routing_table *irq_rt;
11859         struct kvm_lapic_irq irq;
11860         struct kvm_vcpu *vcpu;
11861         struct vcpu_data vcpu_info;
11862         int idx, ret = 0;
11863
11864         if (!kvm_arch_has_assigned_device(kvm) ||
11865                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11866                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11867                 return 0;
11868
11869         idx = srcu_read_lock(&kvm->irq_srcu);
11870         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11871         if (guest_irq >= irq_rt->nr_rt_entries ||
11872             hlist_empty(&irq_rt->map[guest_irq])) {
11873                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
11874                              guest_irq, irq_rt->nr_rt_entries);
11875                 goto out;
11876         }
11877
11878         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11879                 if (e->type != KVM_IRQ_ROUTING_MSI)
11880                         continue;
11881                 /*
11882                  * VT-d PI cannot support posting multicast/broadcast
11883                  * interrupts to a vCPU, we still use interrupt remapping
11884                  * for these kind of interrupts.
11885                  *
11886                  * For lowest-priority interrupts, we only support
11887                  * those with single CPU as the destination, e.g. user
11888                  * configures the interrupts via /proc/irq or uses
11889                  * irqbalance to make the interrupts single-CPU.
11890                  *
11891                  * We will support full lowest-priority interrupt later.
11892                  */
11893
11894                 kvm_set_msi_irq(kvm, e, &irq);
11895                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11896                         /*
11897                          * Make sure the IRTE is in remapped mode if
11898                          * we don't handle it in posted mode.
11899                          */
11900                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11901                         if (ret < 0) {
11902                                 printk(KERN_INFO
11903                                    "failed to back to remapped mode, irq: %u\n",
11904                                    host_irq);
11905                                 goto out;
11906                         }
11907
11908                         continue;
11909                 }
11910
11911                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11912                 vcpu_info.vector = irq.vector;
11913
11914                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11915                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11916
11917                 if (set)
11918                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11919                 else
11920                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11921
11922                 if (ret < 0) {
11923                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11924                                         __func__);
11925                         goto out;
11926                 }
11927         }
11928
11929         ret = 0;
11930 out:
11931         srcu_read_unlock(&kvm->irq_srcu, idx);
11932         return ret;
11933 }
11934
11935 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11936 {
11937         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11938                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11939                         FEATURE_CONTROL_LMCE;
11940         else
11941                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11942                         ~FEATURE_CONTROL_LMCE;
11943 }
11944
11945 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11946         .cpu_has_kvm_support = cpu_has_kvm_support,
11947         .disabled_by_bios = vmx_disabled_by_bios,
11948         .hardware_setup = hardware_setup,
11949         .hardware_unsetup = hardware_unsetup,
11950         .check_processor_compatibility = vmx_check_processor_compat,
11951         .hardware_enable = hardware_enable,
11952         .hardware_disable = hardware_disable,
11953         .cpu_has_accelerated_tpr = report_flexpriority,
11954         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11955
11956         .vcpu_create = vmx_create_vcpu,
11957         .vcpu_free = vmx_free_vcpu,
11958         .vcpu_reset = vmx_vcpu_reset,
11959
11960         .prepare_guest_switch = vmx_save_host_state,
11961         .vcpu_load = vmx_vcpu_load,
11962         .vcpu_put = vmx_vcpu_put,
11963
11964         .update_bp_intercept = update_exception_bitmap,
11965         .get_msr = vmx_get_msr,
11966         .set_msr = vmx_set_msr,
11967         .get_segment_base = vmx_get_segment_base,
11968         .get_segment = vmx_get_segment,
11969         .set_segment = vmx_set_segment,
11970         .get_cpl = vmx_get_cpl,
11971         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11972         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11973         .decache_cr3 = vmx_decache_cr3,
11974         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11975         .set_cr0 = vmx_set_cr0,
11976         .set_cr3 = vmx_set_cr3,
11977         .set_cr4 = vmx_set_cr4,
11978         .set_efer = vmx_set_efer,
11979         .get_idt = vmx_get_idt,
11980         .set_idt = vmx_set_idt,
11981         .get_gdt = vmx_get_gdt,
11982         .set_gdt = vmx_set_gdt,
11983         .get_dr6 = vmx_get_dr6,
11984         .set_dr6 = vmx_set_dr6,
11985         .set_dr7 = vmx_set_dr7,
11986         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11987         .cache_reg = vmx_cache_reg,
11988         .get_rflags = vmx_get_rflags,
11989         .set_rflags = vmx_set_rflags,
11990
11991         .tlb_flush = vmx_flush_tlb,
11992
11993         .run = vmx_vcpu_run,
11994         .handle_exit = vmx_handle_exit,
11995         .skip_emulated_instruction = skip_emulated_instruction,
11996         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11997         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11998         .patch_hypercall = vmx_patch_hypercall,
11999         .set_irq = vmx_inject_irq,
12000         .set_nmi = vmx_inject_nmi,
12001         .queue_exception = vmx_queue_exception,
12002         .cancel_injection = vmx_cancel_injection,
12003         .interrupt_allowed = vmx_interrupt_allowed,
12004         .nmi_allowed = vmx_nmi_allowed,
12005         .get_nmi_mask = vmx_get_nmi_mask,
12006         .set_nmi_mask = vmx_set_nmi_mask,
12007         .enable_nmi_window = enable_nmi_window,
12008         .enable_irq_window = enable_irq_window,
12009         .update_cr8_intercept = update_cr8_intercept,
12010         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
12011         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
12012         .get_enable_apicv = vmx_get_enable_apicv,
12013         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
12014         .load_eoi_exitmap = vmx_load_eoi_exitmap,
12015         .apicv_post_state_restore = vmx_apicv_post_state_restore,
12016         .hwapic_irr_update = vmx_hwapic_irr_update,
12017         .hwapic_isr_update = vmx_hwapic_isr_update,
12018         .sync_pir_to_irr = vmx_sync_pir_to_irr,
12019         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
12020
12021         .set_tss_addr = vmx_set_tss_addr,
12022         .get_tdp_level = get_ept_level,
12023         .get_mt_mask = vmx_get_mt_mask,
12024
12025         .get_exit_info = vmx_get_exit_info,
12026
12027         .get_lpage_level = vmx_get_lpage_level,
12028
12029         .cpuid_update = vmx_cpuid_update,
12030
12031         .rdtscp_supported = vmx_rdtscp_supported,
12032         .invpcid_supported = vmx_invpcid_supported,
12033
12034         .set_supported_cpuid = vmx_set_supported_cpuid,
12035
12036         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
12037
12038         .write_tsc_offset = vmx_write_tsc_offset,
12039
12040         .set_tdp_cr3 = vmx_set_cr3,
12041
12042         .check_intercept = vmx_check_intercept,
12043         .handle_external_intr = vmx_handle_external_intr,
12044         .mpx_supported = vmx_mpx_supported,
12045         .xsaves_supported = vmx_xsaves_supported,
12046
12047         .check_nested_events = vmx_check_nested_events,
12048
12049         .sched_in = vmx_sched_in,
12050
12051         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
12052         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
12053         .flush_log_dirty = vmx_flush_log_dirty,
12054         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
12055         .write_log_dirty = vmx_write_pml_buffer,
12056
12057         .pre_block = vmx_pre_block,
12058         .post_block = vmx_post_block,
12059
12060         .pmu_ops = &intel_pmu_ops,
12061
12062         .update_pi_irte = vmx_update_pi_irte,
12063
12064 #ifdef CONFIG_X86_64
12065         .set_hv_timer = vmx_set_hv_timer,
12066         .cancel_hv_timer = vmx_cancel_hv_timer,
12067 #endif
12068
12069         .setup_mce = vmx_setup_mce,
12070 };
12071
12072 static int __init vmx_init(void)
12073 {
12074         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
12075                      __alignof__(struct vcpu_vmx), THIS_MODULE);
12076         if (r)
12077                 return r;
12078
12079 #ifdef CONFIG_KEXEC_CORE
12080         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
12081                            crash_vmclear_local_loaded_vmcss);
12082 #endif
12083
12084         return 0;
12085 }
12086
12087 static void __exit vmx_exit(void)
12088 {
12089 #ifdef CONFIG_KEXEC_CORE
12090         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
12091         synchronize_rcu();
12092 #endif
12093
12094         kvm_exit();
12095 }
12096
12097 module_init(vmx_init)
12098 module_exit(vmx_exit)