arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/frame.h>
  37 #include "kvm_cache_regs.h"
  38 #include "x86.h"
  39
  40 #include <asm/cpu.h>
  41 #include <asm/io.h>
  42 #include <asm/desc.h>
  43 #include <asm/vmx.h>
  44 #include <asm/virtext.h>
  45 #include <asm/mce.h>
  46 #include <asm/fpu/internal.h>
  47 #include <asm/perf_event.h>
  48 #include <asm/debugreg.h>
  49 #include <asm/kexec.h>
  50 #include <asm/apic.h>
  51 #include <asm/irq_remapping.h>
  52 #include <asm/mmu_context.h>
  53
  54 #include "trace.h"
  55 #include "pmu.h"
  56
  57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  58 #define __ex_clear(x, reg) \
  59         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  60
  61 MODULE_AUTHOR("Qumranet");
  62 MODULE_LICENSE("GPL");
  63
  64 static const struct x86_cpu_id vmx_cpu_id[] = {
  65         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  66         {}
  67 };
  68 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  69
  70 static bool __read_mostly enable_vpid = 1;
  71 module_param_named(vpid, enable_vpid, bool, 0444);
  72
  73 static bool __read_mostly flexpriority_enabled = 1;
  74 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  75
  76 static bool __read_mostly enable_ept = 1;
  77 module_param_named(ept, enable_ept, bool, S_IRUGO);
  78
  79 static bool __read_mostly enable_unrestricted_guest = 1;
  80 module_param_named(unrestricted_guest,
  81                         enable_unrestricted_guest, bool, S_IRUGO);
  82
  83 static bool __read_mostly enable_ept_ad_bits = 1;
  84 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  85
  86 static bool __read_mostly emulate_invalid_guest_state = true;
  87 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  88
  89 static bool __read_mostly fasteoi = 1;
  90 module_param(fasteoi, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_apicv = 1;
  93 module_param(enable_apicv, bool, S_IRUGO);
  94
  95 static bool __read_mostly enable_shadow_vmcs = 1;
  96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  97 /*
  98  * If nested=1, nested virtualization is supported, i.e., guests may use
  99  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 100  * use VMX instructions.
 101  */
 102 static bool __read_mostly nested = 0;
 103 module_param(nested, bool, S_IRUGO);
 104
 105 static u64 __read_mostly host_xss;
 106
 107 static bool __read_mostly enable_pml = 1;
 108 module_param_named(pml, enable_pml, bool, S_IRUGO);
 109
 110 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 111
 112 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 113 static int __read_mostly cpu_preemption_timer_multi;
 114 static bool __read_mostly enable_preemption_timer = 1;
 115 #ifdef CONFIG_X86_64
 116 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 117 #endif
 118
 119 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 120 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 121 #define KVM_VM_CR0_ALWAYS_ON                                            \
 122         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 123 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 124         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 125          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 126
 127 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 128 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 129
 130 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 131
 132 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 133
 134 /*
 135  * Hyper-V requires all of these, so mark them as supported even though
 136  * they are just treated the same as all-context.
 137  */
 138 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 139         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 140         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 141         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 142         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 143
 144 /*
 145  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 146  * ple_gap:    upper bound on the amount of time between two successive
 147  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 148  *             According to test, this time is usually smaller than 128 cycles.
 149  * ple_window: upper bound on the amount of time a guest is allowed to execute
 150  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 151  *             less than 2^12 cycles
 152  * Time is measured based on a counter that runs at the same rate as the TSC,
 153  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 154  */
 155 #define KVM_VMX_DEFAULT_PLE_GAP           128
 156 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 158 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 160                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 161
 162 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 163 module_param(ple_gap, int, S_IRUGO);
 164
 165 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 166 module_param(ple_window, int, S_IRUGO);
 167
 168 /* Default doubles per-vcpu window every exit. */
 169 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 170 module_param(ple_window_grow, int, S_IRUGO);
 171
 172 /* Default resets per-vcpu window every exit to ple_window. */
 173 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 174 module_param(ple_window_shrink, int, S_IRUGO);
 175
 176 /* Default is to compute the maximum so we can never overflow. */
 177 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 178 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 module_param(ple_window_max, int, S_IRUGO);
 180
 181 extern const ulong vmx_return;
 182
 183 #define NR_AUTOLOAD_MSRS 8
 184 #define VMCS02_POOL_SIZE 1
 185
 186 struct vmcs {
 187         u32 revision_id;
 188         u32 abort;
 189         char data[0];
 190 };
 191
 192 /*
 193  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 194  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 195  * loaded on this CPU (so we can clear them if the CPU goes down).
 196  */
 197 struct loaded_vmcs {
 198         struct vmcs *vmcs;
 199         struct vmcs *shadow_vmcs;
 200         int cpu;
 201         bool launched;
 202         bool nmi_known_unmasked;
 203         struct list_head loaded_vmcss_on_cpu_link;
 204 };
 205
 206 struct shared_msr_entry {
 207         unsigned index;
 208         u64 data;
 209         u64 mask;
 210 };
 211
 212 /*
 213  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 214  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 215  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 216  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 217  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 218  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 219  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 220  * underlying hardware which will be used to run L2.
 221  * This structure is packed to ensure that its layout is identical across
 222  * machines (necessary for live migration).
 223  * If there are changes in this struct, VMCS12_REVISION must be changed.
 224  */
 225 typedef u64 natural_width;
 226 struct __packed vmcs12 {
 227         /* According to the Intel spec, a VMCS region must start with the
 228          * following two fields. Then follow implementation-specific data.
 229          */
 230         u32 revision_id;
 231         u32 abort;
 232
 233         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 234         u32 padding[7]; /* room for future expansion */
 235
 236         u64 io_bitmap_a;
 237         u64 io_bitmap_b;
 238         u64 msr_bitmap;
 239         u64 vm_exit_msr_store_addr;
 240         u64 vm_exit_msr_load_addr;
 241         u64 vm_entry_msr_load_addr;
 242         u64 tsc_offset;
 243         u64 virtual_apic_page_addr;
 244         u64 apic_access_addr;
 245         u64 posted_intr_desc_addr;
 246         u64 ept_pointer;
 247         u64 eoi_exit_bitmap0;
 248         u64 eoi_exit_bitmap1;
 249         u64 eoi_exit_bitmap2;
 250         u64 eoi_exit_bitmap3;
 251         u64 xss_exit_bitmap;
 252         u64 guest_physical_address;
 253         u64 vmcs_link_pointer;
 254         u64 pml_address;
 255         u64 guest_ia32_debugctl;
 256         u64 guest_ia32_pat;
 257         u64 guest_ia32_efer;
 258         u64 guest_ia32_perf_global_ctrl;
 259         u64 guest_pdptr0;
 260         u64 guest_pdptr1;
 261         u64 guest_pdptr2;
 262         u64 guest_pdptr3;
 263         u64 guest_bndcfgs;
 264         u64 host_ia32_pat;
 265         u64 host_ia32_efer;
 266         u64 host_ia32_perf_global_ctrl;
 267         u64 padding64[8]; /* room for future expansion */
 268         /*
 269          * To allow migration of L1 (complete with its L2 guests) between
 270          * machines of different natural widths (32 or 64 bit), we cannot have
 271          * unsigned long fields with no explict size. We use u64 (aliased
 272          * natural_width) instead. Luckily, x86 is little-endian.
 273          */
 274         natural_width cr0_guest_host_mask;
 275         natural_width cr4_guest_host_mask;
 276         natural_width cr0_read_shadow;
 277         natural_width cr4_read_shadow;
 278         natural_width cr3_target_value0;
 279         natural_width cr3_target_value1;
 280         natural_width cr3_target_value2;
 281         natural_width cr3_target_value3;
 282         natural_width exit_qualification;
 283         natural_width guest_linear_address;
 284         natural_width guest_cr0;
 285         natural_width guest_cr3;
 286         natural_width guest_cr4;
 287         natural_width guest_es_base;
 288         natural_width guest_cs_base;
 289         natural_width guest_ss_base;
 290         natural_width guest_ds_base;
 291         natural_width guest_fs_base;
 292         natural_width guest_gs_base;
 293         natural_width guest_ldtr_base;
 294         natural_width guest_tr_base;
 295         natural_width guest_gdtr_base;
 296         natural_width guest_idtr_base;
 297         natural_width guest_dr7;
 298         natural_width guest_rsp;
 299         natural_width guest_rip;
 300         natural_width guest_rflags;
 301         natural_width guest_pending_dbg_exceptions;
 302         natural_width guest_sysenter_esp;
 303         natural_width guest_sysenter_eip;
 304         natural_width host_cr0;
 305         natural_width host_cr3;
 306         natural_width host_cr4;
 307         natural_width host_fs_base;
 308         natural_width host_gs_base;
 309         natural_width host_tr_base;
 310         natural_width host_gdtr_base;
 311         natural_width host_idtr_base;
 312         natural_width host_ia32_sysenter_esp;
 313         natural_width host_ia32_sysenter_eip;
 314         natural_width host_rsp;
 315         natural_width host_rip;
 316         natural_width paddingl[8]; /* room for future expansion */
 317         u32 pin_based_vm_exec_control;
 318         u32 cpu_based_vm_exec_control;
 319         u32 exception_bitmap;
 320         u32 page_fault_error_code_mask;
 321         u32 page_fault_error_code_match;
 322         u32 cr3_target_count;
 323         u32 vm_exit_controls;
 324         u32 vm_exit_msr_store_count;
 325         u32 vm_exit_msr_load_count;
 326         u32 vm_entry_controls;
 327         u32 vm_entry_msr_load_count;
 328         u32 vm_entry_intr_info_field;
 329         u32 vm_entry_exception_error_code;
 330         u32 vm_entry_instruction_len;
 331         u32 tpr_threshold;
 332         u32 secondary_vm_exec_control;
 333         u32 vm_instruction_error;
 334         u32 vm_exit_reason;
 335         u32 vm_exit_intr_info;
 336         u32 vm_exit_intr_error_code;
 337         u32 idt_vectoring_info_field;
 338         u32 idt_vectoring_error_code;
 339         u32 vm_exit_instruction_len;
 340         u32 vmx_instruction_info;
 341         u32 guest_es_limit;
 342         u32 guest_cs_limit;
 343         u32 guest_ss_limit;
 344         u32 guest_ds_limit;
 345         u32 guest_fs_limit;
 346         u32 guest_gs_limit;
 347         u32 guest_ldtr_limit;
 348         u32 guest_tr_limit;
 349         u32 guest_gdtr_limit;
 350         u32 guest_idtr_limit;
 351         u32 guest_es_ar_bytes;
 352         u32 guest_cs_ar_bytes;
 353         u32 guest_ss_ar_bytes;
 354         u32 guest_ds_ar_bytes;
 355         u32 guest_fs_ar_bytes;
 356         u32 guest_gs_ar_bytes;
 357         u32 guest_ldtr_ar_bytes;
 358         u32 guest_tr_ar_bytes;
 359         u32 guest_interruptibility_info;
 360         u32 guest_activity_state;
 361         u32 guest_sysenter_cs;
 362         u32 host_ia32_sysenter_cs;
 363         u32 vmx_preemption_timer_value;
 364         u32 padding32[7]; /* room for future expansion */
 365         u16 virtual_processor_id;
 366         u16 posted_intr_nv;
 367         u16 guest_es_selector;
 368         u16 guest_cs_selector;
 369         u16 guest_ss_selector;
 370         u16 guest_ds_selector;
 371         u16 guest_fs_selector;
 372         u16 guest_gs_selector;
 373         u16 guest_ldtr_selector;
 374         u16 guest_tr_selector;
 375         u16 guest_intr_status;
 376         u16 guest_pml_index;
 377         u16 host_es_selector;
 378         u16 host_cs_selector;
 379         u16 host_ss_selector;
 380         u16 host_ds_selector;
 381         u16 host_fs_selector;
 382         u16 host_gs_selector;
 383         u16 host_tr_selector;
 384 };
 385
 386 /*
 387  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 388  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 389  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 390  */
 391 #define VMCS12_REVISION 0x11e57ed0
 392
 393 /*
 394  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 395  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 396  * current implementation, 4K are reserved to avoid future complications.
 397  */
 398 #define VMCS12_SIZE 0x1000
 399
 400 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 401 struct vmcs02_list {
 402         struct list_head list;
 403         gpa_t vmptr;
 404         struct loaded_vmcs vmcs02;
 405 };
 406
 407 /*
 408  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 409  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 410  */
 411 struct nested_vmx {
 412         /* Has the level1 guest done vmxon? */
 413         bool vmxon;
 414         gpa_t vmxon_ptr;
 415         bool pml_full;
 416
 417         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 418         gpa_t current_vmptr;
 419         /* The host-usable pointer to the above */
 420         struct page *current_vmcs12_page;
 421         struct vmcs12 *current_vmcs12;
 422         /*
 423          * Cache of the guest's VMCS, existing outside of guest memory.
 424          * Loaded from guest memory during VMPTRLD. Flushed to guest
 425          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 426          */
 427         struct vmcs12 *cached_vmcs12;
 428         /*
 429          * Indicates if the shadow vmcs must be updated with the
 430          * data hold by vmcs12
 431          */
 432         bool sync_shadow_vmcs;
 433
 434         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 435         struct list_head vmcs02_pool;
 436         int vmcs02_num;
 437         bool change_vmcs01_virtual_x2apic_mode;
 438         /* L2 must run next, and mustn't decide to exit to L1. */
 439         bool nested_run_pending;
 440         /*
 441          * Guest pages referred to in vmcs02 with host-physical pointers, so
 442          * we must keep them pinned while L2 runs.
 443          */
 444         struct page *apic_access_page;
 445         struct page *virtual_apic_page;
 446         struct page *pi_desc_page;
 447         struct pi_desc *pi_desc;
 448         bool pi_pending;
 449         u16 posted_intr_nv;
 450
 451         unsigned long *msr_bitmap;
 452
 453         struct hrtimer preemption_timer;
 454         bool preemption_timer_expired;
 455
 456         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 457         u64 vmcs01_debugctl;
 458
 459         u16 vpid02;
 460         u16 last_vpid;
 461
 462         /*
 463          * We only store the "true" versions of the VMX capability MSRs. We
 464          * generate the "non-true" versions by setting the must-be-1 bits
 465          * according to the SDM.
 466          */
 467         u32 nested_vmx_procbased_ctls_low;
 468         u32 nested_vmx_procbased_ctls_high;
 469         u32 nested_vmx_secondary_ctls_low;
 470         u32 nested_vmx_secondary_ctls_high;
 471         u32 nested_vmx_pinbased_ctls_low;
 472         u32 nested_vmx_pinbased_ctls_high;
 473         u32 nested_vmx_exit_ctls_low;
 474         u32 nested_vmx_exit_ctls_high;
 475         u32 nested_vmx_entry_ctls_low;
 476         u32 nested_vmx_entry_ctls_high;
 477         u32 nested_vmx_misc_low;
 478         u32 nested_vmx_misc_high;
 479         u32 nested_vmx_ept_caps;
 480         u32 nested_vmx_vpid_caps;
 481         u64 nested_vmx_basic;
 482         u64 nested_vmx_cr0_fixed0;
 483         u64 nested_vmx_cr0_fixed1;
 484         u64 nested_vmx_cr4_fixed0;
 485         u64 nested_vmx_cr4_fixed1;
 486         u64 nested_vmx_vmcs_enum;
 487 };
 488
 489 #define POSTED_INTR_ON  0
 490 #define POSTED_INTR_SN  1
 491
 492 /* Posted-Interrupt Descriptor */
 493 struct pi_desc {
 494         u32 pir[8];     /* Posted interrupt requested */
 495         union {
 496                 struct {
 497                                 /* bit 256 - Outstanding Notification */
 498                         u16     on      : 1,
 499                                 /* bit 257 - Suppress Notification */
 500                                 sn      : 1,
 501                                 /* bit 271:258 - Reserved */
 502                                 rsvd_1  : 14;
 503                                 /* bit 279:272 - Notification Vector */
 504                         u8      nv;
 505                                 /* bit 287:280 - Reserved */
 506                         u8      rsvd_2;
 507                                 /* bit 319:288 - Notification Destination */
 508                         u32     ndst;
 509                 };
 510                 u64 control;
 511         };
 512         u32 rsvd[6];
 513 } __aligned(64);
 514
 515 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 516 {
 517         return test_and_set_bit(POSTED_INTR_ON,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 522 {
 523         return test_and_clear_bit(POSTED_INTR_ON,
 524                         (unsigned long *)&pi_desc->control);
 525 }
 526
 527 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 528 {
 529         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 530 }
 531
 532 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 533 {
 534         return clear_bit(POSTED_INTR_SN,
 535                         (unsigned long *)&pi_desc->control);
 536 }
 537
 538 static inline void pi_set_sn(struct pi_desc *pi_desc)
 539 {
 540         return set_bit(POSTED_INTR_SN,
 541                         (unsigned long *)&pi_desc->control);
 542 }
 543
 544 static inline void pi_clear_on(struct pi_desc *pi_desc)
 545 {
 546         clear_bit(POSTED_INTR_ON,
 547                   (unsigned long *)&pi_desc->control);
 548 }
 549
 550 static inline int pi_test_on(struct pi_desc *pi_desc)
 551 {
 552         return test_bit(POSTED_INTR_ON,
 553                         (unsigned long *)&pi_desc->control);
 554 }
 555
 556 static inline int pi_test_sn(struct pi_desc *pi_desc)
 557 {
 558         return test_bit(POSTED_INTR_SN,
 559                         (unsigned long *)&pi_desc->control);
 560 }
 561
 562 struct vcpu_vmx {
 563         struct kvm_vcpu       vcpu;
 564         unsigned long         host_rsp;
 565         u8                    fail;
 566         u32                   exit_intr_info;
 567         u32                   idt_vectoring_info;
 568         ulong                 rflags;
 569         struct shared_msr_entry *guest_msrs;
 570         int                   nmsrs;
 571         int                   save_nmsrs;
 572         unsigned long         host_idt_base;
 573 #ifdef CONFIG_X86_64
 574         u64                   msr_host_kernel_gs_base;
 575         u64                   msr_guest_kernel_gs_base;
 576 #endif
 577         u32 vm_entry_controls_shadow;
 578         u32 vm_exit_controls_shadow;
 579         /*
 580          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 581          * non-nested (L1) guest, it always points to vmcs01. For a nested
 582          * guest (L2), it points to a different VMCS.
 583          */
 584         struct loaded_vmcs    vmcs01;
 585         struct loaded_vmcs   *loaded_vmcs;
 586         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 587         struct msr_autoload {
 588                 unsigned nr;
 589                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 590                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 591         } msr_autoload;
 592         struct {
 593                 int           loaded;
 594                 u16           fs_sel, gs_sel, ldt_sel;
 595 #ifdef CONFIG_X86_64
 596                 u16           ds_sel, es_sel;
 597 #endif
 598                 int           gs_ldt_reload_needed;
 599                 int           fs_reload_needed;
 600                 u64           msr_host_bndcfgs;
 601                 unsigned long vmcs_host_cr3;    /* May not match real cr3 */
 602                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 603         } host_state;
 604         struct {
 605                 int vm86_active;
 606                 ulong save_rflags;
 607                 struct kvm_segment segs[8];
 608         } rmode;
 609         struct {
 610                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 611                 struct kvm_save_segment {
 612                         u16 selector;
 613                         unsigned long base;
 614                         u32 limit;
 615                         u32 ar;
 616                 } seg[8];
 617         } segment_cache;
 618         int vpid;
 619         bool emulation_required;
 620
 621         u32 exit_reason;
 622
 623         /* Posted interrupt descriptor */
 624         struct pi_desc pi_desc;
 625
 626         /* Support for a guest hypervisor (nested VMX) */
 627         struct nested_vmx nested;
 628
 629         /* Dynamic PLE window. */
 630         int ple_window;
 631         bool ple_window_dirty;
 632
 633         /* Support for PML */
 634 #define PML_ENTITY_NUM          512
 635         struct page *pml_pg;
 636
 637         /* apic deadline value in host tsc */
 638         u64 hv_deadline_tsc;
 639
 640         u64 current_tsc_ratio;
 641
 642         bool guest_pkru_valid;
 643         u32 guest_pkru;
 644         u32 host_pkru;
 645
 646         /*
 647          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 648          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 649          * in msr_ia32_feature_control_valid_bits.
 650          */
 651         u64 msr_ia32_feature_control;
 652         u64 msr_ia32_feature_control_valid_bits;
 653 };
 654
 655 enum segment_cache_field {
 656         SEG_FIELD_SEL = 0,
 657         SEG_FIELD_BASE = 1,
 658         SEG_FIELD_LIMIT = 2,
 659         SEG_FIELD_AR = 3,
 660
 661         SEG_FIELD_NR = 4
 662 };
 663
 664 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 665 {
 666         return container_of(vcpu, struct vcpu_vmx, vcpu);
 667 }
 668
 669 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 670 {
 671         return &(to_vmx(vcpu)->pi_desc);
 672 }
 673
 674 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 675 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 676 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 677                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 678
 679
 680 static unsigned long shadow_read_only_fields[] = {
 681         /*
 682          * We do NOT shadow fields that are modified when L0
 683          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 684          * VMXON...) executed by L1.
 685          * For example, VM_INSTRUCTION_ERROR is read
 686          * by L1 if a vmx instruction fails (part of the error path).
 687          * Note the code assumes this logic. If for some reason
 688          * we start shadowing these fields then we need to
 689          * force a shadow sync when L0 emulates vmx instructions
 690          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 691          * by nested_vmx_failValid)
 692          */
 693         VM_EXIT_REASON,
 694         VM_EXIT_INTR_INFO,
 695         VM_EXIT_INSTRUCTION_LEN,
 696         IDT_VECTORING_INFO_FIELD,
 697         IDT_VECTORING_ERROR_CODE,
 698         VM_EXIT_INTR_ERROR_CODE,
 699         EXIT_QUALIFICATION,
 700         GUEST_LINEAR_ADDRESS,
 701         GUEST_PHYSICAL_ADDRESS
 702 };
 703 static int max_shadow_read_only_fields =
 704         ARRAY_SIZE(shadow_read_only_fields);
 705
 706 static unsigned long shadow_read_write_fields[] = {
 707         TPR_THRESHOLD,
 708         GUEST_RIP,
 709         GUEST_RSP,
 710         GUEST_CR0,
 711         GUEST_CR3,
 712         GUEST_CR4,
 713         GUEST_INTERRUPTIBILITY_INFO,
 714         GUEST_RFLAGS,
 715         GUEST_CS_SELECTOR,
 716         GUEST_CS_AR_BYTES,
 717         GUEST_CS_LIMIT,
 718         GUEST_CS_BASE,
 719         GUEST_ES_BASE,
 720         GUEST_BNDCFGS,
 721         CR0_GUEST_HOST_MASK,
 722         CR0_READ_SHADOW,
 723         CR4_READ_SHADOW,
 724         TSC_OFFSET,
 725         EXCEPTION_BITMAP,
 726         CPU_BASED_VM_EXEC_CONTROL,
 727         VM_ENTRY_EXCEPTION_ERROR_CODE,
 728         VM_ENTRY_INTR_INFO_FIELD,
 729         VM_ENTRY_INSTRUCTION_LEN,
 730         VM_ENTRY_EXCEPTION_ERROR_CODE,
 731         HOST_FS_BASE,
 732         HOST_GS_BASE,
 733         HOST_FS_SELECTOR,
 734         HOST_GS_SELECTOR
 735 };
 736 static int max_shadow_read_write_fields =
 737         ARRAY_SIZE(shadow_read_write_fields);
 738
 739 static const unsigned short vmcs_field_to_offset_table[] = {
 740         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 741         FIELD(POSTED_INTR_NV, posted_intr_nv),
 742         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 743         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 744         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 745         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 746         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 747         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 748         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 749         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 750         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 751         FIELD(GUEST_PML_INDEX, guest_pml_index),
 752         FIELD(HOST_ES_SELECTOR, host_es_selector),
 753         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 754         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 755         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 756         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 757         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 758         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 759         FIELD64(IO_BITMAP_A, io_bitmap_a),
 760         FIELD64(IO_BITMAP_B, io_bitmap_b),
 761         FIELD64(MSR_BITMAP, msr_bitmap),
 762         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 763         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 764         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 765         FIELD64(TSC_OFFSET, tsc_offset),
 766         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 767         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 768         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 769         FIELD64(EPT_POINTER, ept_pointer),
 770         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 771         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 772         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 773         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 774         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 775         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 776         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 777         FIELD64(PML_ADDRESS, pml_address),
 778         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 779         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 780         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 781         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 782         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 783         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 784         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 785         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 786         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 787         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 788         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 789         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 790         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 791         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 792         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 793         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 794         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 795         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 796         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 797         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 798         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 799         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 800         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 801         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 802         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 803         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 804         FIELD(TPR_THRESHOLD, tpr_threshold),
 805         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 806         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 807         FIELD(VM_EXIT_REASON, vm_exit_reason),
 808         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 809         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 810         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 811         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 812         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 813         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 814         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 815         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 816         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 817         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 818         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 819         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 820         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 821         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 822         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 823         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 824         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 825         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 826         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 827         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 828         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 829         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 830         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 831         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 832         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 833         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 834         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 835         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 836         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 837         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 838         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 839         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 840         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 841         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 842         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 843         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 844         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 845         FIELD(EXIT_QUALIFICATION, exit_qualification),
 846         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 847         FIELD(GUEST_CR0, guest_cr0),
 848         FIELD(GUEST_CR3, guest_cr3),
 849         FIELD(GUEST_CR4, guest_cr4),
 850         FIELD(GUEST_ES_BASE, guest_es_base),
 851         FIELD(GUEST_CS_BASE, guest_cs_base),
 852         FIELD(GUEST_SS_BASE, guest_ss_base),
 853         FIELD(GUEST_DS_BASE, guest_ds_base),
 854         FIELD(GUEST_FS_BASE, guest_fs_base),
 855         FIELD(GUEST_GS_BASE, guest_gs_base),
 856         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 857         FIELD(GUEST_TR_BASE, guest_tr_base),
 858         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 859         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 860         FIELD(GUEST_DR7, guest_dr7),
 861         FIELD(GUEST_RSP, guest_rsp),
 862         FIELD(GUEST_RIP, guest_rip),
 863         FIELD(GUEST_RFLAGS, guest_rflags),
 864         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 865         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 866         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 867         FIELD(HOST_CR0, host_cr0),
 868         FIELD(HOST_CR3, host_cr3),
 869         FIELD(HOST_CR4, host_cr4),
 870         FIELD(HOST_FS_BASE, host_fs_base),
 871         FIELD(HOST_GS_BASE, host_gs_base),
 872         FIELD(HOST_TR_BASE, host_tr_base),
 873         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 874         FIELD(HOST_IDTR_BASE, host_idtr_base),
 875         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 876         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 877         FIELD(HOST_RSP, host_rsp),
 878         FIELD(HOST_RIP, host_rip),
 879 };
 880
 881 static inline short vmcs_field_to_offset(unsigned long field)
 882 {
 883         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 884
 885         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 886             vmcs_field_to_offset_table[field] == 0)
 887                 return -ENOENT;
 888
 889         return vmcs_field_to_offset_table[field];
 890 }
 891
 892 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 893 {
 894         return to_vmx(vcpu)->nested.cached_vmcs12;
 895 }
 896
 897 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 898 {
 899         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 900         if (is_error_page(page))
 901                 return NULL;
 902
 903         return page;
 904 }
 905
 906 static void nested_release_page(struct page *page)
 907 {
 908         kvm_release_page_dirty(page);
 909 }
 910
 911 static void nested_release_page_clean(struct page *page)
 912 {
 913         kvm_release_page_clean(page);
 914 }
 915
 916 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
 917 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 918 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 919 static bool vmx_xsaves_supported(void);
 920 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 921 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 922                             struct kvm_segment *var, int seg);
 923 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 924                             struct kvm_segment *var, int seg);
 925 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 926 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 927 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 928 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 929 static int alloc_identity_pagetable(struct kvm *kvm);
 930
 931 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 932 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 933 /*
 934  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 935  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 936  */
 937 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 938
 939 /*
 940  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 941  * can find which vCPU should be waken up.
 942  */
 943 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 944 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 945
 946 enum {
 947         VMX_IO_BITMAP_A,
 948         VMX_IO_BITMAP_B,
 949         VMX_MSR_BITMAP_LEGACY,
 950         VMX_MSR_BITMAP_LONGMODE,
 951         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 952         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 953         VMX_MSR_BITMAP_LEGACY_X2APIC,
 954         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 955         VMX_VMREAD_BITMAP,
 956         VMX_VMWRITE_BITMAP,
 957         VMX_BITMAP_NR
 958 };
 959
 960 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 961
 962 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 963 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 964 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 965 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 966 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 967 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 968 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 969 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 970 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 971 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 972
 973 static bool cpu_has_load_ia32_efer;
 974 static bool cpu_has_load_perf_global_ctrl;
 975
 976 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 977 static DEFINE_SPINLOCK(vmx_vpid_lock);
 978
 979 static struct vmcs_config {
 980         int size;
 981         int order;
 982         u32 basic_cap;
 983         u32 revision_id;
 984         u32 pin_based_exec_ctrl;
 985         u32 cpu_based_exec_ctrl;
 986         u32 cpu_based_2nd_exec_ctrl;
 987         u32 vmexit_ctrl;
 988         u32 vmentry_ctrl;
 989 } vmcs_config;
 990
 991 static struct vmx_capability {
 992         u32 ept;
 993         u32 vpid;
 994 } vmx_capability;
 995
 996 #define VMX_SEGMENT_FIELD(seg)                                  \
 997         [VCPU_SREG_##seg] = {                                   \
 998                 .selector = GUEST_##seg##_SELECTOR,             \
 999                 .base = GUEST_##seg##_BASE,                     \
1000                 .limit = GUEST_##seg##_LIMIT,                   \
1001                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1002         }
1003
1004 static const struct kvm_vmx_segment_field {
1005         unsigned selector;
1006         unsigned base;
1007         unsigned limit;
1008         unsigned ar_bytes;
1009 } kvm_vmx_segment_fields[] = {
1010         VMX_SEGMENT_FIELD(CS),
1011         VMX_SEGMENT_FIELD(DS),
1012         VMX_SEGMENT_FIELD(ES),
1013         VMX_SEGMENT_FIELD(FS),
1014         VMX_SEGMENT_FIELD(GS),
1015         VMX_SEGMENT_FIELD(SS),
1016         VMX_SEGMENT_FIELD(TR),
1017         VMX_SEGMENT_FIELD(LDTR),
1018 };
1019
1020 static u64 host_efer;
1021
1022 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1023
1024 /*
1025  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1026  * away by decrementing the array size.
1027  */
1028 static const u32 vmx_msr_index[] = {
1029 #ifdef CONFIG_X86_64
1030         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1031 #endif
1032         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1033 };
1034
1035 static inline bool is_exception_n(u32 intr_info, u8 vector)
1036 {
1037         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1038                              INTR_INFO_VALID_MASK)) ==
1039                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1040 }
1041
1042 static inline bool is_debug(u32 intr_info)
1043 {
1044         return is_exception_n(intr_info, DB_VECTOR);
1045 }
1046
1047 static inline bool is_breakpoint(u32 intr_info)
1048 {
1049         return is_exception_n(intr_info, BP_VECTOR);
1050 }
1051
1052 static inline bool is_page_fault(u32 intr_info)
1053 {
1054         return is_exception_n(intr_info, PF_VECTOR);
1055 }
1056
1057 static inline bool is_no_device(u32 intr_info)
1058 {
1059         return is_exception_n(intr_info, NM_VECTOR);
1060 }
1061
1062 static inline bool is_invalid_opcode(u32 intr_info)
1063 {
1064         return is_exception_n(intr_info, UD_VECTOR);
1065 }
1066
1067 static inline bool is_external_interrupt(u32 intr_info)
1068 {
1069         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1070                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1071 }
1072
1073 static inline bool is_machine_check(u32 intr_info)
1074 {
1075         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1076                              INTR_INFO_VALID_MASK)) ==
1077                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1078 }
1079
1080 static inline bool cpu_has_vmx_msr_bitmap(void)
1081 {
1082         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1083 }
1084
1085 static inline bool cpu_has_vmx_tpr_shadow(void)
1086 {
1087         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1088 }
1089
1090 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1091 {
1092         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1093 }
1094
1095 static inline bool cpu_has_secondary_exec_ctrls(void)
1096 {
1097         return vmcs_config.cpu_based_exec_ctrl &
1098                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1099 }
1100
1101 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1102 {
1103         return vmcs_config.cpu_based_2nd_exec_ctrl &
1104                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1105 }
1106
1107 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1108 {
1109         return vmcs_config.cpu_based_2nd_exec_ctrl &
1110                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1111 }
1112
1113 static inline bool cpu_has_vmx_apic_register_virt(void)
1114 {
1115         return vmcs_config.cpu_based_2nd_exec_ctrl &
1116                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1117 }
1118
1119 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1120 {
1121         return vmcs_config.cpu_based_2nd_exec_ctrl &
1122                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1123 }
1124
1125 /*
1126  * Comment's format: document - errata name - stepping - processor name.
1127  * Refer from
1128  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1129  */
1130 static u32 vmx_preemption_cpu_tfms[] = {
1131 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1132 0x000206E6,
1133 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1134 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1135 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1136 0x00020652,
1137 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1138 0x00020655,
1139 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1140 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1141 /*
1142  * 320767.pdf - AAP86  - B1 -
1143  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1144  */
1145 0x000106E5,
1146 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1147 0x000106A0,
1148 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1149 0x000106A1,
1150 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1151 0x000106A4,
1152  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1153  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1154  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1155 0x000106A5,
1156 };
1157
1158 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1159 {
1160         u32 eax = cpuid_eax(0x00000001), i;
1161
1162         /* Clear the reserved bits */
1163         eax &= ~(0x3U << 14 | 0xfU << 28);
1164         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1165                 if (eax == vmx_preemption_cpu_tfms[i])
1166                         return true;
1167
1168         return false;
1169 }
1170
1171 static inline bool cpu_has_vmx_preemption_timer(void)
1172 {
1173         return vmcs_config.pin_based_exec_ctrl &
1174                 PIN_BASED_VMX_PREEMPTION_TIMER;
1175 }
1176
1177 static inline bool cpu_has_vmx_posted_intr(void)
1178 {
1179         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1180                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1181 }
1182
1183 static inline bool cpu_has_vmx_apicv(void)
1184 {
1185         return cpu_has_vmx_apic_register_virt() &&
1186                 cpu_has_vmx_virtual_intr_delivery() &&
1187                 cpu_has_vmx_posted_intr();
1188 }
1189
1190 static inline bool cpu_has_vmx_flexpriority(void)
1191 {
1192         return cpu_has_vmx_tpr_shadow() &&
1193                 cpu_has_vmx_virtualize_apic_accesses();
1194 }
1195
1196 static inline bool cpu_has_vmx_ept_execute_only(void)
1197 {
1198         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1199 }
1200
1201 static inline bool cpu_has_vmx_ept_2m_page(void)
1202 {
1203         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1204 }
1205
1206 static inline bool cpu_has_vmx_ept_1g_page(void)
1207 {
1208         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1209 }
1210
1211 static inline bool cpu_has_vmx_ept_4levels(void)
1212 {
1213         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1214 }
1215
1216 static inline bool cpu_has_vmx_ept_ad_bits(void)
1217 {
1218         return vmx_capability.ept & VMX_EPT_AD_BIT;
1219 }
1220
1221 static inline bool cpu_has_vmx_invept_context(void)
1222 {
1223         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1224 }
1225
1226 static inline bool cpu_has_vmx_invept_global(void)
1227 {
1228         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1229 }
1230
1231 static inline bool cpu_has_vmx_invvpid_single(void)
1232 {
1233         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1234 }
1235
1236 static inline bool cpu_has_vmx_invvpid_global(void)
1237 {
1238         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1239 }
1240
1241 static inline bool cpu_has_vmx_invvpid(void)
1242 {
1243         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1244 }
1245
1246 static inline bool cpu_has_vmx_ept(void)
1247 {
1248         return vmcs_config.cpu_based_2nd_exec_ctrl &
1249                 SECONDARY_EXEC_ENABLE_EPT;
1250 }
1251
1252 static inline bool cpu_has_vmx_unrestricted_guest(void)
1253 {
1254         return vmcs_config.cpu_based_2nd_exec_ctrl &
1255                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1256 }
1257
1258 static inline bool cpu_has_vmx_ple(void)
1259 {
1260         return vmcs_config.cpu_based_2nd_exec_ctrl &
1261                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1262 }
1263
1264 static inline bool cpu_has_vmx_basic_inout(void)
1265 {
1266         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1267 }
1268
1269 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1270 {
1271         return flexpriority_enabled && lapic_in_kernel(vcpu);
1272 }
1273
1274 static inline bool cpu_has_vmx_vpid(void)
1275 {
1276         return vmcs_config.cpu_based_2nd_exec_ctrl &
1277                 SECONDARY_EXEC_ENABLE_VPID;
1278 }
1279
1280 static inline bool cpu_has_vmx_rdtscp(void)
1281 {
1282         return vmcs_config.cpu_based_2nd_exec_ctrl &
1283                 SECONDARY_EXEC_RDTSCP;
1284 }
1285
1286 static inline bool cpu_has_vmx_invpcid(void)
1287 {
1288         return vmcs_config.cpu_based_2nd_exec_ctrl &
1289                 SECONDARY_EXEC_ENABLE_INVPCID;
1290 }
1291
1292 static inline bool cpu_has_vmx_wbinvd_exit(void)
1293 {
1294         return vmcs_config.cpu_based_2nd_exec_ctrl &
1295                 SECONDARY_EXEC_WBINVD_EXITING;
1296 }
1297
1298 static inline bool cpu_has_vmx_shadow_vmcs(void)
1299 {
1300         u64 vmx_msr;
1301         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1302         /* check if the cpu supports writing r/o exit information fields */
1303         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1304                 return false;
1305
1306         return vmcs_config.cpu_based_2nd_exec_ctrl &
1307                 SECONDARY_EXEC_SHADOW_VMCS;
1308 }
1309
1310 static inline bool cpu_has_vmx_pml(void)
1311 {
1312         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1313 }
1314
1315 static inline bool cpu_has_vmx_tsc_scaling(void)
1316 {
1317         return vmcs_config.cpu_based_2nd_exec_ctrl &
1318                 SECONDARY_EXEC_TSC_SCALING;
1319 }
1320
1321 static inline bool report_flexpriority(void)
1322 {
1323         return flexpriority_enabled;
1324 }
1325
1326 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1327 {
1328         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1329 }
1330
1331 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1332 {
1333         return vmcs12->cpu_based_vm_exec_control & bit;
1334 }
1335
1336 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1337 {
1338         return (vmcs12->cpu_based_vm_exec_control &
1339                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1340                 (vmcs12->secondary_vm_exec_control & bit);
1341 }
1342
1343 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1344 {
1345         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1346 }
1347
1348 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1349 {
1350         return vmcs12->pin_based_vm_exec_control &
1351                 PIN_BASED_VMX_PREEMPTION_TIMER;
1352 }
1353
1354 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1355 {
1356         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1357 }
1358
1359 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1360 {
1361         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1362                 vmx_xsaves_supported();
1363 }
1364
1365 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1366 {
1367         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1368 }
1369
1370 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1371 {
1372         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1373 }
1374
1375 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1376 {
1377         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1378 }
1379
1380 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1381 {
1382         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1383 }
1384
1385 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1386 {
1387         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1388 }
1389
1390 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1391 {
1392         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1393 }
1394
1395 static inline bool is_nmi(u32 intr_info)
1396 {
1397         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1398                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1399 }
1400
1401 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1402                               u32 exit_intr_info,
1403                               unsigned long exit_qualification);
1404 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1405                         struct vmcs12 *vmcs12,
1406                         u32 reason, unsigned long qualification);
1407
1408 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1409 {
1410         int i;
1411
1412         for (i = 0; i < vmx->nmsrs; ++i)
1413                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1414                         return i;
1415         return -1;
1416 }
1417
1418 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1419 {
1420     struct {
1421         u64 vpid : 16;
1422         u64 rsvd : 48;
1423         u64 gva;
1424     } operand = { vpid, 0, gva };
1425
1426     asm volatile (__ex(ASM_VMX_INVVPID)
1427                   /* CF==1 or ZF==1 --> rc = -1 */
1428                   "; ja 1f ; ud2 ; 1:"
1429                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1430 }
1431
1432 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1433 {
1434         struct {
1435                 u64 eptp, gpa;
1436         } operand = {eptp, gpa};
1437
1438         asm volatile (__ex(ASM_VMX_INVEPT)
1439                         /* CF==1 or ZF==1 --> rc = -1 */
1440                         "; ja 1f ; ud2 ; 1:\n"
1441                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1442 }
1443
1444 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1445 {
1446         int i;
1447
1448         i = __find_msr_index(vmx, msr);
1449         if (i >= 0)
1450                 return &vmx->guest_msrs[i];
1451         return NULL;
1452 }
1453
1454 static void vmcs_clear(struct vmcs *vmcs)
1455 {
1456         u64 phys_addr = __pa(vmcs);
1457         u8 error;
1458
1459         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1460                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1461                       : "cc", "memory");
1462         if (error)
1463                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1464                        vmcs, phys_addr);
1465 }
1466
1467 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1468 {
1469         vmcs_clear(loaded_vmcs->vmcs);
1470         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1471                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1472         loaded_vmcs->cpu = -1;
1473         loaded_vmcs->launched = 0;
1474 }
1475
1476 static void vmcs_load(struct vmcs *vmcs)
1477 {
1478         u64 phys_addr = __pa(vmcs);
1479         u8 error;
1480
1481         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1482                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1483                         : "cc", "memory");
1484         if (error)
1485                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1486                        vmcs, phys_addr);
1487 }
1488
1489 #ifdef CONFIG_KEXEC_CORE
1490 /*
1491  * This bitmap is used to indicate whether the vmclear
1492  * operation is enabled on all cpus. All disabled by
1493  * default.
1494  */
1495 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1496
1497 static inline void crash_enable_local_vmclear(int cpu)
1498 {
1499         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1500 }
1501
1502 static inline void crash_disable_local_vmclear(int cpu)
1503 {
1504         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1505 }
1506
1507 static inline int crash_local_vmclear_enabled(int cpu)
1508 {
1509         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1510 }
1511
1512 static void crash_vmclear_local_loaded_vmcss(void)
1513 {
1514         int cpu = raw_smp_processor_id();
1515         struct loaded_vmcs *v;
1516
1517         if (!crash_local_vmclear_enabled(cpu))
1518                 return;
1519
1520         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1521                             loaded_vmcss_on_cpu_link)
1522                 vmcs_clear(v->vmcs);
1523 }
1524 #else
1525 static inline void crash_enable_local_vmclear(int cpu) { }
1526 static inline void crash_disable_local_vmclear(int cpu) { }
1527 #endif /* CONFIG_KEXEC_CORE */
1528
1529 static void __loaded_vmcs_clear(void *arg)
1530 {
1531         struct loaded_vmcs *loaded_vmcs = arg;
1532         int cpu = raw_smp_processor_id();
1533
1534         if (loaded_vmcs->cpu != cpu)
1535                 return; /* vcpu migration can race with cpu offline */
1536         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1537                 per_cpu(current_vmcs, cpu) = NULL;
1538         crash_disable_local_vmclear(cpu);
1539         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1540
1541         /*
1542          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1543          * is before setting loaded_vmcs->vcpu to -1 which is done in
1544          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1545          * then adds the vmcs into percpu list before it is deleted.
1546          */
1547         smp_wmb();
1548
1549         loaded_vmcs_init(loaded_vmcs);
1550         crash_enable_local_vmclear(cpu);
1551 }
1552
1553 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1554 {
1555         int cpu = loaded_vmcs->cpu;
1556
1557         if (cpu != -1)
1558                 smp_call_function_single(cpu,
1559                          __loaded_vmcs_clear, loaded_vmcs, 1);
1560 }
1561
1562 static inline void vpid_sync_vcpu_single(int vpid)
1563 {
1564         if (vpid == 0)
1565                 return;
1566
1567         if (cpu_has_vmx_invvpid_single())
1568                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1569 }
1570
1571 static inline void vpid_sync_vcpu_global(void)
1572 {
1573         if (cpu_has_vmx_invvpid_global())
1574                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1575 }
1576
1577 static inline void vpid_sync_context(int vpid)
1578 {
1579         if (cpu_has_vmx_invvpid_single())
1580                 vpid_sync_vcpu_single(vpid);
1581         else
1582                 vpid_sync_vcpu_global();
1583 }
1584
1585 static inline void ept_sync_global(void)
1586 {
1587         if (cpu_has_vmx_invept_global())
1588                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1589 }
1590
1591 static inline void ept_sync_context(u64 eptp)
1592 {
1593         if (enable_ept) {
1594                 if (cpu_has_vmx_invept_context())
1595                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1596                 else
1597                         ept_sync_global();
1598         }
1599 }
1600
1601 static __always_inline void vmcs_check16(unsigned long field)
1602 {
1603         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1604                          "16-bit accessor invalid for 64-bit field");
1605         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1606                          "16-bit accessor invalid for 64-bit high field");
1607         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1608                          "16-bit accessor invalid for 32-bit high field");
1609         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1610                          "16-bit accessor invalid for natural width field");
1611 }
1612
1613 static __always_inline void vmcs_check32(unsigned long field)
1614 {
1615         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1616                          "32-bit accessor invalid for 16-bit field");
1617         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1618                          "32-bit accessor invalid for natural width field");
1619 }
1620
1621 static __always_inline void vmcs_check64(unsigned long field)
1622 {
1623         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1624                          "64-bit accessor invalid for 16-bit field");
1625         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1626                          "64-bit accessor invalid for 64-bit high field");
1627         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1628                          "64-bit accessor invalid for 32-bit field");
1629         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1630                          "64-bit accessor invalid for natural width field");
1631 }
1632
1633 static __always_inline void vmcs_checkl(unsigned long field)
1634 {
1635         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1636                          "Natural width accessor invalid for 16-bit field");
1637         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1638                          "Natural width accessor invalid for 64-bit field");
1639         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1640                          "Natural width accessor invalid for 64-bit high field");
1641         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1642                          "Natural width accessor invalid for 32-bit field");
1643 }
1644
1645 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1646 {
1647         unsigned long value;
1648
1649         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1650                       : "=a"(value) : "d"(field) : "cc");
1651         return value;
1652 }
1653
1654 static __always_inline u16 vmcs_read16(unsigned long field)
1655 {
1656         vmcs_check16(field);
1657         return __vmcs_readl(field);
1658 }
1659
1660 static __always_inline u32 vmcs_read32(unsigned long field)
1661 {
1662         vmcs_check32(field);
1663         return __vmcs_readl(field);
1664 }
1665
1666 static __always_inline u64 vmcs_read64(unsigned long field)
1667 {
1668         vmcs_check64(field);
1669 #ifdef CONFIG_X86_64
1670         return __vmcs_readl(field);
1671 #else
1672         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1673 #endif
1674 }
1675
1676 static __always_inline unsigned long vmcs_readl(unsigned long field)
1677 {
1678         vmcs_checkl(field);
1679         return __vmcs_readl(field);
1680 }
1681
1682 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1683 {
1684         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1685                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1686         dump_stack();
1687 }
1688
1689 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1690 {
1691         u8 error;
1692
1693         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1694                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1695         if (unlikely(error))
1696                 vmwrite_error(field, value);
1697 }
1698
1699 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1700 {
1701         vmcs_check16(field);
1702         __vmcs_writel(field, value);
1703 }
1704
1705 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1706 {
1707         vmcs_check32(field);
1708         __vmcs_writel(field, value);
1709 }
1710
1711 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1712 {
1713         vmcs_check64(field);
1714         __vmcs_writel(field, value);
1715 #ifndef CONFIG_X86_64
1716         asm volatile ("");
1717         __vmcs_writel(field+1, value >> 32);
1718 #endif
1719 }
1720
1721 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1722 {
1723         vmcs_checkl(field);
1724         __vmcs_writel(field, value);
1725 }
1726
1727 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1728 {
1729         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1730                          "vmcs_clear_bits does not support 64-bit fields");
1731         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1732 }
1733
1734 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1735 {
1736         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1737                          "vmcs_set_bits does not support 64-bit fields");
1738         __vmcs_writel(field, __vmcs_readl(field) | mask);
1739 }
1740
1741 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1742 {
1743         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1744 }
1745
1746 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1747 {
1748         vmcs_write32(VM_ENTRY_CONTROLS, val);
1749         vmx->vm_entry_controls_shadow = val;
1750 }
1751
1752 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1753 {
1754         if (vmx->vm_entry_controls_shadow != val)
1755                 vm_entry_controls_init(vmx, val);
1756 }
1757
1758 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1759 {
1760         return vmx->vm_entry_controls_shadow;
1761 }
1762
1763
1764 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1765 {
1766         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1767 }
1768
1769 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1770 {
1771         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1772 }
1773
1774 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1775 {
1776         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1777 }
1778
1779 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1780 {
1781         vmcs_write32(VM_EXIT_CONTROLS, val);
1782         vmx->vm_exit_controls_shadow = val;
1783 }
1784
1785 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1786 {
1787         if (vmx->vm_exit_controls_shadow != val)
1788                 vm_exit_controls_init(vmx, val);
1789 }
1790
1791 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1792 {
1793         return vmx->vm_exit_controls_shadow;
1794 }
1795
1796
1797 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1798 {
1799         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1800 }
1801
1802 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1803 {
1804         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1805 }
1806
1807 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1808 {
1809         vmx->segment_cache.bitmask = 0;
1810 }
1811
1812 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1813                                        unsigned field)
1814 {
1815         bool ret;
1816         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1817
1818         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1819                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1820                 vmx->segment_cache.bitmask = 0;
1821         }
1822         ret = vmx->segment_cache.bitmask & mask;
1823         vmx->segment_cache.bitmask |= mask;
1824         return ret;
1825 }
1826
1827 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1828 {
1829         u16 *p = &vmx->segment_cache.seg[seg].selector;
1830
1831         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1832                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1833         return *p;
1834 }
1835
1836 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1837 {
1838         ulong *p = &vmx->segment_cache.seg[seg].base;
1839
1840         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1841                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1842         return *p;
1843 }
1844
1845 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1846 {
1847         u32 *p = &vmx->segment_cache.seg[seg].limit;
1848
1849         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1850                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1851         return *p;
1852 }
1853
1854 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1855 {
1856         u32 *p = &vmx->segment_cache.seg[seg].ar;
1857
1858         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1859                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1860         return *p;
1861 }
1862
1863 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1864 {
1865         u32 eb;
1866
1867         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1868              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1869         if ((vcpu->guest_debug &
1870              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1871             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1872                 eb |= 1u << BP_VECTOR;
1873         if (to_vmx(vcpu)->rmode.vm86_active)
1874                 eb = ~0;
1875         if (enable_ept)
1876                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1877
1878         /* When we are running a nested L2 guest and L1 specified for it a
1879          * certain exception bitmap, we must trap the same exceptions and pass
1880          * them to L1. When running L2, we will only handle the exceptions
1881          * specified above if L1 did not want them.
1882          */
1883         if (is_guest_mode(vcpu))
1884                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1885
1886         vmcs_write32(EXCEPTION_BITMAP, eb);
1887 }
1888
1889 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1890                 unsigned long entry, unsigned long exit)
1891 {
1892         vm_entry_controls_clearbit(vmx, entry);
1893         vm_exit_controls_clearbit(vmx, exit);
1894 }
1895
1896 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1897 {
1898         unsigned i;
1899         struct msr_autoload *m = &vmx->msr_autoload;
1900
1901         switch (msr) {
1902         case MSR_EFER:
1903                 if (cpu_has_load_ia32_efer) {
1904                         clear_atomic_switch_msr_special(vmx,
1905                                         VM_ENTRY_LOAD_IA32_EFER,
1906                                         VM_EXIT_LOAD_IA32_EFER);
1907                         return;
1908                 }
1909                 break;
1910         case MSR_CORE_PERF_GLOBAL_CTRL:
1911                 if (cpu_has_load_perf_global_ctrl) {
1912                         clear_atomic_switch_msr_special(vmx,
1913                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1914                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1915                         return;
1916                 }
1917                 break;
1918         }
1919
1920         for (i = 0; i < m->nr; ++i)
1921                 if (m->guest[i].index == msr)
1922                         break;
1923
1924         if (i == m->nr)
1925                 return;
1926         --m->nr;
1927         m->guest[i] = m->guest[m->nr];
1928         m->host[i] = m->host[m->nr];
1929         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1930         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1931 }
1932
1933 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1934                 unsigned long entry, unsigned long exit,
1935                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1936                 u64 guest_val, u64 host_val)
1937 {
1938         vmcs_write64(guest_val_vmcs, guest_val);
1939         vmcs_write64(host_val_vmcs, host_val);
1940         vm_entry_controls_setbit(vmx, entry);
1941         vm_exit_controls_setbit(vmx, exit);
1942 }
1943
1944 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1945                                   u64 guest_val, u64 host_val)
1946 {
1947         unsigned i;
1948         struct msr_autoload *m = &vmx->msr_autoload;
1949
1950         switch (msr) {
1951         case MSR_EFER:
1952                 if (cpu_has_load_ia32_efer) {
1953                         add_atomic_switch_msr_special(vmx,
1954                                         VM_ENTRY_LOAD_IA32_EFER,
1955                                         VM_EXIT_LOAD_IA32_EFER,
1956                                         GUEST_IA32_EFER,
1957                                         HOST_IA32_EFER,
1958                                         guest_val, host_val);
1959                         return;
1960                 }
1961                 break;
1962         case MSR_CORE_PERF_GLOBAL_CTRL:
1963                 if (cpu_has_load_perf_global_ctrl) {
1964                         add_atomic_switch_msr_special(vmx,
1965                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1966                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1967                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1968                                         HOST_IA32_PERF_GLOBAL_CTRL,
1969                                         guest_val, host_val);
1970                         return;
1971                 }
1972                 break;
1973         case MSR_IA32_PEBS_ENABLE:
1974                 /* PEBS needs a quiescent period after being disabled (to write
1975                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1976                  * provide that period, so a CPU could write host's record into
1977                  * guest's memory.
1978                  */
1979                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1980         }
1981
1982         for (i = 0; i < m->nr; ++i)
1983                 if (m->guest[i].index == msr)
1984                         break;
1985
1986         if (i == NR_AUTOLOAD_MSRS) {
1987                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1988                                 "Can't add msr %x\n", msr);
1989                 return;
1990         } else if (i == m->nr) {
1991                 ++m->nr;
1992                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1993                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1994         }
1995
1996         m->guest[i].index = msr;
1997         m->guest[i].value = guest_val;
1998         m->host[i].index = msr;
1999         m->host[i].value = host_val;
2000 }
2001
2002 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2003 {
2004         u64 guest_efer = vmx->vcpu.arch.efer;
2005         u64 ignore_bits = 0;
2006
2007         if (!enable_ept) {
2008                 /*
2009                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2010                  * host CPUID is more efficient than testing guest CPUID
2011                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2012                  */
2013                 if (boot_cpu_has(X86_FEATURE_SMEP))
2014                         guest_efer |= EFER_NX;
2015                 else if (!(guest_efer & EFER_NX))
2016                         ignore_bits |= EFER_NX;
2017         }
2018
2019         /*
2020          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2021          */
2022         ignore_bits |= EFER_SCE;
2023 #ifdef CONFIG_X86_64
2024         ignore_bits |= EFER_LMA | EFER_LME;
2025         /* SCE is meaningful only in long mode on Intel */
2026         if (guest_efer & EFER_LMA)
2027                 ignore_bits &= ~(u64)EFER_SCE;
2028 #endif
2029
2030         clear_atomic_switch_msr(vmx, MSR_EFER);
2031
2032         /*
2033          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2034          * On CPUs that support "load IA32_EFER", always switch EFER
2035          * atomically, since it's faster than switching it manually.
2036          */
2037         if (cpu_has_load_ia32_efer ||
2038             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2039                 if (!(guest_efer & EFER_LMA))
2040                         guest_efer &= ~EFER_LME;
2041                 if (guest_efer != host_efer)
2042                         add_atomic_switch_msr(vmx, MSR_EFER,
2043                                               guest_efer, host_efer);
2044                 return false;
2045         } else {
2046                 guest_efer &= ~ignore_bits;
2047                 guest_efer |= host_efer & ignore_bits;
2048
2049                 vmx->guest_msrs[efer_offset].data = guest_efer;
2050                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2051
2052                 return true;
2053         }
2054 }
2055
2056 #ifdef CONFIG_X86_32
2057 /*
2058  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2059  * VMCS rather than the segment table.  KVM uses this helper to figure
2060  * out the current bases to poke them into the VMCS before entry.
2061  */
2062 static unsigned long segment_base(u16 selector)
2063 {
2064         struct desc_struct *table;
2065         unsigned long v;
2066
2067         if (!(selector & ~SEGMENT_RPL_MASK))
2068                 return 0;
2069
2070         table = get_current_gdt_ro();
2071
2072         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2073                 u16 ldt_selector = kvm_read_ldt();
2074
2075                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2076                         return 0;
2077
2078                 table = (struct desc_struct *)segment_base(ldt_selector);
2079         }
2080         v = get_desc_base(&table[selector >> 3]);
2081         return v;
2082 }
2083 #endif
2084
2085 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2086 {
2087         struct vcpu_vmx *vmx = to_vmx(vcpu);
2088         int i;
2089
2090         if (vmx->host_state.loaded)
2091                 return;
2092
2093         vmx->host_state.loaded = 1;
2094         /*
2095          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2096          * allow segment selectors with cpl > 0 or ti == 1.
2097          */
2098         vmx->host_state.ldt_sel = kvm_read_ldt();
2099         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2100         savesegment(fs, vmx->host_state.fs_sel);
2101         if (!(vmx->host_state.fs_sel & 7)) {
2102                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2103                 vmx->host_state.fs_reload_needed = 0;
2104         } else {
2105                 vmcs_write16(HOST_FS_SELECTOR, 0);
2106                 vmx->host_state.fs_reload_needed = 1;
2107         }
2108         savesegment(gs, vmx->host_state.gs_sel);
2109         if (!(vmx->host_state.gs_sel & 7))
2110                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2111         else {
2112                 vmcs_write16(HOST_GS_SELECTOR, 0);
2113                 vmx->host_state.gs_ldt_reload_needed = 1;
2114         }
2115
2116 #ifdef CONFIG_X86_64
2117         savesegment(ds, vmx->host_state.ds_sel);
2118         savesegment(es, vmx->host_state.es_sel);
2119 #endif
2120
2121 #ifdef CONFIG_X86_64
2122         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2123         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2124 #else
2125         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2126         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2127 #endif
2128
2129 #ifdef CONFIG_X86_64
2130         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2131         if (is_long_mode(&vmx->vcpu))
2132                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2133 #endif
2134         if (boot_cpu_has(X86_FEATURE_MPX))
2135                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2136         for (i = 0; i < vmx->save_nmsrs; ++i)
2137                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2138                                    vmx->guest_msrs[i].data,
2139                                    vmx->guest_msrs[i].mask);
2140 }
2141
2142 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2143 {
2144         if (!vmx->host_state.loaded)
2145                 return;
2146
2147         ++vmx->vcpu.stat.host_state_reload;
2148         vmx->host_state.loaded = 0;
2149 #ifdef CONFIG_X86_64
2150         if (is_long_mode(&vmx->vcpu))
2151                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2152 #endif
2153         if (vmx->host_state.gs_ldt_reload_needed) {
2154                 kvm_load_ldt(vmx->host_state.ldt_sel);
2155 #ifdef CONFIG_X86_64
2156                 load_gs_index(vmx->host_state.gs_sel);
2157 #else
2158                 loadsegment(gs, vmx->host_state.gs_sel);
2159 #endif
2160         }
2161         if (vmx->host_state.fs_reload_needed)
2162                 loadsegment(fs, vmx->host_state.fs_sel);
2163 #ifdef CONFIG_X86_64
2164         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2165                 loadsegment(ds, vmx->host_state.ds_sel);
2166                 loadsegment(es, vmx->host_state.es_sel);
2167         }
2168 #endif
2169         invalidate_tss_limit();
2170 #ifdef CONFIG_X86_64
2171         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2172 #endif
2173         if (vmx->host_state.msr_host_bndcfgs)
2174                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2175         load_fixmap_gdt(raw_smp_processor_id());
2176 }
2177
2178 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2179 {
2180         preempt_disable();
2181         __vmx_load_host_state(vmx);
2182         preempt_enable();
2183 }
2184
2185 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2186 {
2187         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2188         struct pi_desc old, new;
2189         unsigned int dest;
2190
2191         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2192                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2193                 !kvm_vcpu_apicv_active(vcpu))
2194                 return;
2195
2196         do {
2197                 old.control = new.control = pi_desc->control;
2198
2199                 /*
2200                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2201                  * are two possible cases:
2202                  * 1. After running 'pre_block', context switch
2203                  *    happened. For this case, 'sn' was set in
2204                  *    vmx_vcpu_put(), so we need to clear it here.
2205                  * 2. After running 'pre_block', we were blocked,
2206                  *    and woken up by some other guy. For this case,
2207                  *    we don't need to do anything, 'pi_post_block'
2208                  *    will do everything for us. However, we cannot
2209                  *    check whether it is case #1 or case #2 here
2210                  *    (maybe, not needed), so we also clear sn here,
2211                  *    I think it is not a big deal.
2212                  */
2213                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2214                         if (vcpu->cpu != cpu) {
2215                                 dest = cpu_physical_id(cpu);
2216
2217                                 if (x2apic_enabled())
2218                                         new.ndst = dest;
2219                                 else
2220                                         new.ndst = (dest << 8) & 0xFF00;
2221                         }
2222
2223                         /* set 'NV' to 'notification vector' */
2224                         new.nv = POSTED_INTR_VECTOR;
2225                 }
2226
2227                 /* Allow posting non-urgent interrupts */
2228                 new.sn = 0;
2229         } while (cmpxchg(&pi_desc->control, old.control,
2230                         new.control) != old.control);
2231 }
2232
2233 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2234 {
2235         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2236         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2237 }
2238
2239 /*
2240  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2241  * vcpu mutex is already taken.
2242  */
2243 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2244 {
2245         struct vcpu_vmx *vmx = to_vmx(vcpu);
2246         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2247
2248         if (!already_loaded) {
2249                 loaded_vmcs_clear(vmx->loaded_vmcs);
2250                 local_irq_disable();
2251                 crash_disable_local_vmclear(cpu);
2252
2253                 /*
2254                  * Read loaded_vmcs->cpu should be before fetching
2255                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2256                  * See the comments in __loaded_vmcs_clear().
2257                  */
2258                 smp_rmb();
2259
2260                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2261                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2262                 crash_enable_local_vmclear(cpu);
2263                 local_irq_enable();
2264         }
2265
2266         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2267                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2268                 vmcs_load(vmx->loaded_vmcs->vmcs);
2269         }
2270
2271         if (!already_loaded) {
2272                 void *gdt = get_current_gdt_ro();
2273                 unsigned long sysenter_esp;
2274
2275                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2276
2277                 /*
2278                  * Linux uses per-cpu TSS and GDT, so set these when switching
2279                  * processors.  See 22.2.4.
2280                  */
2281                 vmcs_writel(HOST_TR_BASE,
2282                             (unsigned long)this_cpu_ptr(&cpu_tss));
2283                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
2284
2285                 /*
2286                  * VM exits change the host TR limit to 0x67 after a VM
2287                  * exit.  This is okay, since 0x67 covers everything except
2288                  * the IO bitmap and have have code to handle the IO bitmap
2289                  * being lost after a VM exit.
2290                  */
2291                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2292
2293                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2294                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2295
2296                 vmx->loaded_vmcs->cpu = cpu;
2297         }
2298
2299         /* Setup TSC multiplier */
2300         if (kvm_has_tsc_control &&
2301             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2302                 decache_tsc_multiplier(vmx);
2303
2304         vmx_vcpu_pi_load(vcpu, cpu);
2305         vmx->host_pkru = read_pkru();
2306 }
2307
2308 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2309 {
2310         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2311
2312         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2313                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2314                 !kvm_vcpu_apicv_active(vcpu))
2315                 return;
2316
2317         /* Set SN when the vCPU is preempted */
2318         if (vcpu->preempted)
2319                 pi_set_sn(pi_desc);
2320 }
2321
2322 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2323 {
2324         vmx_vcpu_pi_put(vcpu);
2325
2326         __vmx_load_host_state(to_vmx(vcpu));
2327 }
2328
2329 static bool emulation_required(struct kvm_vcpu *vcpu)
2330 {
2331         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2332 }
2333
2334 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2335
2336 /*
2337  * Return the cr0 value that a nested guest would read. This is a combination
2338  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2339  * its hypervisor (cr0_read_shadow).
2340  */
2341 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2342 {
2343         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2344                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2345 }
2346 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2347 {
2348         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2349                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2350 }
2351
2352 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2353 {
2354         unsigned long rflags, save_rflags;
2355
2356         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2357                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2358                 rflags = vmcs_readl(GUEST_RFLAGS);
2359                 if (to_vmx(vcpu)->rmode.vm86_active) {
2360                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2361                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2362                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2363                 }
2364                 to_vmx(vcpu)->rflags = rflags;
2365         }
2366         return to_vmx(vcpu)->rflags;
2367 }
2368
2369 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2370 {
2371         unsigned long old_rflags = vmx_get_rflags(vcpu);
2372
2373         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2374         to_vmx(vcpu)->rflags = rflags;
2375         if (to_vmx(vcpu)->rmode.vm86_active) {
2376                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2377                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2378         }
2379         vmcs_writel(GUEST_RFLAGS, rflags);
2380
2381         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2382                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2383 }
2384
2385 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2386 {
2387         return to_vmx(vcpu)->guest_pkru;
2388 }
2389
2390 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2391 {
2392         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2393         int ret = 0;
2394
2395         if (interruptibility & GUEST_INTR_STATE_STI)
2396                 ret |= KVM_X86_SHADOW_INT_STI;
2397         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2398                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2399
2400         return ret;
2401 }
2402
2403 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2404 {
2405         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2406         u32 interruptibility = interruptibility_old;
2407
2408         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2409
2410         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2411                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2412         else if (mask & KVM_X86_SHADOW_INT_STI)
2413                 interruptibility |= GUEST_INTR_STATE_STI;
2414
2415         if ((interruptibility != interruptibility_old))
2416                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2417 }
2418
2419 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2420 {
2421         unsigned long rip;
2422
2423         rip = kvm_rip_read(vcpu);
2424         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2425         kvm_rip_write(vcpu, rip);
2426
2427         /* skipping an emulated instruction also counts */
2428         vmx_set_interrupt_shadow(vcpu, 0);
2429 }
2430
2431 /*
2432  * KVM wants to inject page-faults which it got to the guest. This function
2433  * checks whether in a nested guest, we need to inject them to L1 or L2.
2434  */
2435 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu)
2436 {
2437         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2438         unsigned int nr = vcpu->arch.exception.nr;
2439
2440         if (!((vmcs12->exception_bitmap & (1u << nr)) ||
2441                 (nr == PF_VECTOR && vcpu->arch.exception.nested_apf)))
2442                 return 0;
2443
2444         if (vcpu->arch.exception.nested_apf) {
2445                 vmcs_write32(VM_EXIT_INTR_ERROR_CODE, vcpu->arch.exception.error_code);
2446                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
2447                         PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
2448                         INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
2449                         vcpu->arch.apf.nested_apf_token);
2450                 return 1;
2451         }
2452
2453         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
2454                           vmcs_read32(VM_EXIT_INTR_INFO),
2455                           vmcs_readl(EXIT_QUALIFICATION));
2456         return 1;
2457 }
2458
2459 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2460 {
2461         struct vcpu_vmx *vmx = to_vmx(vcpu);
2462         unsigned nr = vcpu->arch.exception.nr;
2463         bool has_error_code = vcpu->arch.exception.has_error_code;
2464         bool reinject = vcpu->arch.exception.reinject;
2465         u32 error_code = vcpu->arch.exception.error_code;
2466         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2467
2468         if (!reinject && is_guest_mode(vcpu) &&
2469             nested_vmx_check_exception(vcpu))
2470                 return;
2471
2472         if (has_error_code) {
2473                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2474                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2475         }
2476
2477         if (vmx->rmode.vm86_active) {
2478                 int inc_eip = 0;
2479                 if (kvm_exception_is_soft(nr))
2480                         inc_eip = vcpu->arch.event_exit_inst_len;
2481                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2482                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2483                 return;
2484         }
2485
2486         if (kvm_exception_is_soft(nr)) {
2487                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2488                              vmx->vcpu.arch.event_exit_inst_len);
2489                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2490         } else
2491                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2492
2493         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2494 }
2495
2496 static bool vmx_rdtscp_supported(void)
2497 {
2498         return cpu_has_vmx_rdtscp();
2499 }
2500
2501 static bool vmx_invpcid_supported(void)
2502 {
2503         return cpu_has_vmx_invpcid() && enable_ept;
2504 }
2505
2506 /*
2507  * Swap MSR entry in host/guest MSR entry array.
2508  */
2509 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2510 {
2511         struct shared_msr_entry tmp;
2512
2513         tmp = vmx->guest_msrs[to];
2514         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2515         vmx->guest_msrs[from] = tmp;
2516 }
2517
2518 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2519 {
2520         unsigned long *msr_bitmap;
2521
2522         if (is_guest_mode(vcpu))
2523                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2524         else if (cpu_has_secondary_exec_ctrls() &&
2525                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2526                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2527                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2528                         if (is_long_mode(vcpu))
2529                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2530                         else
2531                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2532                 } else {
2533                         if (is_long_mode(vcpu))
2534                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2535                         else
2536                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2537                 }
2538         } else {
2539                 if (is_long_mode(vcpu))
2540                         msr_bitmap = vmx_msr_bitmap_longmode;
2541                 else
2542                         msr_bitmap = vmx_msr_bitmap_legacy;
2543         }
2544
2545         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2546 }
2547
2548 /*
2549  * Set up the vmcs to automatically save and restore system
2550  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2551  * mode, as fiddling with msrs is very expensive.
2552  */
2553 static void setup_msrs(struct vcpu_vmx *vmx)
2554 {
2555         int save_nmsrs, index;
2556
2557         save_nmsrs = 0;
2558 #ifdef CONFIG_X86_64
2559         if (is_long_mode(&vmx->vcpu)) {
2560                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2561                 if (index >= 0)
2562                         move_msr_up(vmx, index, save_nmsrs++);
2563                 index = __find_msr_index(vmx, MSR_LSTAR);
2564                 if (index >= 0)
2565                         move_msr_up(vmx, index, save_nmsrs++);
2566                 index = __find_msr_index(vmx, MSR_CSTAR);
2567                 if (index >= 0)
2568                         move_msr_up(vmx, index, save_nmsrs++);
2569                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2570                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2571                         move_msr_up(vmx, index, save_nmsrs++);
2572                 /*
2573                  * MSR_STAR is only needed on long mode guests, and only
2574                  * if efer.sce is enabled.
2575                  */
2576                 index = __find_msr_index(vmx, MSR_STAR);
2577                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2578                         move_msr_up(vmx, index, save_nmsrs++);
2579         }
2580 #endif
2581         index = __find_msr_index(vmx, MSR_EFER);
2582         if (index >= 0 && update_transition_efer(vmx, index))
2583                 move_msr_up(vmx, index, save_nmsrs++);
2584
2585         vmx->save_nmsrs = save_nmsrs;
2586
2587         if (cpu_has_vmx_msr_bitmap())
2588                 vmx_set_msr_bitmap(&vmx->vcpu);
2589 }
2590
2591 /*
2592  * reads and returns guest's timestamp counter "register"
2593  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2594  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2595  */
2596 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2597 {
2598         u64 host_tsc, tsc_offset;
2599
2600         host_tsc = rdtsc();
2601         tsc_offset = vmcs_read64(TSC_OFFSET);
2602         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2603 }
2604
2605 /*
2606  * writes 'offset' into guest's timestamp counter offset register
2607  */
2608 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2609 {
2610         if (is_guest_mode(vcpu)) {
2611                 /*
2612                  * We're here if L1 chose not to trap WRMSR to TSC. According
2613                  * to the spec, this should set L1's TSC; The offset that L1
2614                  * set for L2 remains unchanged, and still needs to be added
2615                  * to the newly set TSC to get L2's TSC.
2616                  */
2617                 struct vmcs12 *vmcs12;
2618                 /* recalculate vmcs02.TSC_OFFSET: */
2619                 vmcs12 = get_vmcs12(vcpu);
2620                 vmcs_write64(TSC_OFFSET, offset +
2621                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2622                          vmcs12->tsc_offset : 0));
2623         } else {
2624                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2625                                            vmcs_read64(TSC_OFFSET), offset);
2626                 vmcs_write64(TSC_OFFSET, offset);
2627         }
2628 }
2629
2630 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2631 {
2632         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2633         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2634 }
2635
2636 /*
2637  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2638  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2639  * all guests if the "nested" module option is off, and can also be disabled
2640  * for a single guest by disabling its VMX cpuid bit.
2641  */
2642 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2643 {
2644         return nested && guest_cpuid_has_vmx(vcpu);
2645 }
2646
2647 /*
2648  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2649  * returned for the various VMX controls MSRs when nested VMX is enabled.
2650  * The same values should also be used to verify that vmcs12 control fields are
2651  * valid during nested entry from L1 to L2.
2652  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2653  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2654  * bit in the high half is on if the corresponding bit in the control field
2655  * may be on. See also vmx_control_verify().
2656  */
2657 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2658 {
2659         /*
2660          * Note that as a general rule, the high half of the MSRs (bits in
2661          * the control fields which may be 1) should be initialized by the
2662          * intersection of the underlying hardware's MSR (i.e., features which
2663          * can be supported) and the list of features we want to expose -
2664          * because they are known to be properly supported in our code.
2665          * Also, usually, the low half of the MSRs (bits which must be 1) can
2666          * be set to 0, meaning that L1 may turn off any of these bits. The
2667          * reason is that if one of these bits is necessary, it will appear
2668          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2669          * fields of vmcs01 and vmcs02, will turn these bits off - and
2670          * nested_vmx_exit_handled() will not pass related exits to L1.
2671          * These rules have exceptions below.
2672          */
2673
2674         /* pin-based controls */
2675         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2676                 vmx->nested.nested_vmx_pinbased_ctls_low,
2677                 vmx->nested.nested_vmx_pinbased_ctls_high);
2678         vmx->nested.nested_vmx_pinbased_ctls_low |=
2679                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2680         vmx->nested.nested_vmx_pinbased_ctls_high &=
2681                 PIN_BASED_EXT_INTR_MASK |
2682                 PIN_BASED_NMI_EXITING |
2683                 PIN_BASED_VIRTUAL_NMIS;
2684         vmx->nested.nested_vmx_pinbased_ctls_high |=
2685                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2686                 PIN_BASED_VMX_PREEMPTION_TIMER;
2687         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2688                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2689                         PIN_BASED_POSTED_INTR;
2690
2691         /* exit controls */
2692         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2693                 vmx->nested.nested_vmx_exit_ctls_low,
2694                 vmx->nested.nested_vmx_exit_ctls_high);
2695         vmx->nested.nested_vmx_exit_ctls_low =
2696                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2697
2698         vmx->nested.nested_vmx_exit_ctls_high &=
2699 #ifdef CONFIG_X86_64
2700                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2701 #endif
2702                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2703         vmx->nested.nested_vmx_exit_ctls_high |=
2704                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2705                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2706                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2707
2708         if (kvm_mpx_supported())
2709                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2710
2711         /* We support free control of debug control saving. */
2712         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2713
2714         /* entry controls */
2715         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2716                 vmx->nested.nested_vmx_entry_ctls_low,
2717                 vmx->nested.nested_vmx_entry_ctls_high);
2718         vmx->nested.nested_vmx_entry_ctls_low =
2719                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2720         vmx->nested.nested_vmx_entry_ctls_high &=
2721 #ifdef CONFIG_X86_64
2722                 VM_ENTRY_IA32E_MODE |
2723 #endif
2724                 VM_ENTRY_LOAD_IA32_PAT;
2725         vmx->nested.nested_vmx_entry_ctls_high |=
2726                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2727         if (kvm_mpx_supported())
2728                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2729
2730         /* We support free control of debug control loading. */
2731         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2732
2733         /* cpu-based controls */
2734         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2735                 vmx->nested.nested_vmx_procbased_ctls_low,
2736                 vmx->nested.nested_vmx_procbased_ctls_high);
2737         vmx->nested.nested_vmx_procbased_ctls_low =
2738                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2739         vmx->nested.nested_vmx_procbased_ctls_high &=
2740                 CPU_BASED_VIRTUAL_INTR_PENDING |
2741                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2742                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2743                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2744                 CPU_BASED_CR3_STORE_EXITING |
2745 #ifdef CONFIG_X86_64
2746                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2747 #endif
2748                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2749                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2750                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2751                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2752                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2753         /*
2754          * We can allow some features even when not supported by the
2755          * hardware. For example, L1 can specify an MSR bitmap - and we
2756          * can use it to avoid exits to L1 - even when L0 runs L2
2757          * without MSR bitmaps.
2758          */
2759         vmx->nested.nested_vmx_procbased_ctls_high |=
2760                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2761                 CPU_BASED_USE_MSR_BITMAPS;
2762
2763         /* We support free control of CR3 access interception. */
2764         vmx->nested.nested_vmx_procbased_ctls_low &=
2765                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2766
2767         /* secondary cpu-based controls */
2768         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2769                 vmx->nested.nested_vmx_secondary_ctls_low,
2770                 vmx->nested.nested_vmx_secondary_ctls_high);
2771         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2772         vmx->nested.nested_vmx_secondary_ctls_high &=
2773                 SECONDARY_EXEC_RDRAND | SECONDARY_EXEC_RDSEED |
2774                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2775                 SECONDARY_EXEC_RDTSCP |
2776                 SECONDARY_EXEC_DESC |
2777                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2778                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2779                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2780                 SECONDARY_EXEC_WBINVD_EXITING |
2781                 SECONDARY_EXEC_XSAVES;
2782
2783         if (enable_ept) {
2784                 /* nested EPT: emulate EPT also to L1 */
2785                 vmx->nested.nested_vmx_secondary_ctls_high |=
2786                         SECONDARY_EXEC_ENABLE_EPT;
2787                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2788                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2789                 if (cpu_has_vmx_ept_execute_only())
2790                         vmx->nested.nested_vmx_ept_caps |=
2791                                 VMX_EPT_EXECUTE_ONLY_BIT;
2792                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2793                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2794                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2795                         VMX_EPT_1GB_PAGE_BIT;
2796                 if (enable_ept_ad_bits) {
2797                         vmx->nested.nested_vmx_secondary_ctls_high |=
2798                                 SECONDARY_EXEC_ENABLE_PML;
2799                         vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2800                 }
2801         } else
2802                 vmx->nested.nested_vmx_ept_caps = 0;
2803
2804         /*
2805          * Old versions of KVM use the single-context version without
2806          * checking for support, so declare that it is supported even
2807          * though it is treated as global context.  The alternative is
2808          * not failing the single-context invvpid, and it is worse.
2809          */
2810         if (enable_vpid) {
2811                 vmx->nested.nested_vmx_secondary_ctls_high |=
2812                         SECONDARY_EXEC_ENABLE_VPID;
2813                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2814                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2815         } else
2816                 vmx->nested.nested_vmx_vpid_caps = 0;
2817
2818         if (enable_unrestricted_guest)
2819                 vmx->nested.nested_vmx_secondary_ctls_high |=
2820                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2821
2822         /* miscellaneous data */
2823         rdmsr(MSR_IA32_VMX_MISC,
2824                 vmx->nested.nested_vmx_misc_low,
2825                 vmx->nested.nested_vmx_misc_high);
2826         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2827         vmx->nested.nested_vmx_misc_low |=
2828                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2829                 VMX_MISC_ACTIVITY_HLT;
2830         vmx->nested.nested_vmx_misc_high = 0;
2831
2832         /*
2833          * This MSR reports some information about VMX support. We
2834          * should return information about the VMX we emulate for the
2835          * guest, and the VMCS structure we give it - not about the
2836          * VMX support of the underlying hardware.
2837          */
2838         vmx->nested.nested_vmx_basic =
2839                 VMCS12_REVISION |
2840                 VMX_BASIC_TRUE_CTLS |
2841                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2842                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2843
2844         if (cpu_has_vmx_basic_inout())
2845                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2846
2847         /*
2848          * These MSRs specify bits which the guest must keep fixed on
2849          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2850          * We picked the standard core2 setting.
2851          */
2852 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2853 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2854         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2855         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2856
2857         /* These MSRs specify bits which the guest must keep fixed off. */
2858         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2859         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2860
2861         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2862         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2863 }
2864
2865 /*
2866  * if fixed0[i] == 1: val[i] must be 1
2867  * if fixed1[i] == 0: val[i] must be 0
2868  */
2869 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2870 {
2871         return ((val & fixed1) | fixed0) == val;
2872 }
2873
2874 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2875 {
2876         return fixed_bits_valid(control, low, high);
2877 }
2878
2879 static inline u64 vmx_control_msr(u32 low, u32 high)
2880 {
2881         return low | ((u64)high << 32);
2882 }
2883
2884 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2885 {
2886         superset &= mask;
2887         subset &= mask;
2888
2889         return (superset | subset) == superset;
2890 }
2891
2892 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2893 {
2894         const u64 feature_and_reserved =
2895                 /* feature (except bit 48; see below) */
2896                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2897                 /* reserved */
2898                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2899         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2900
2901         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2902                 return -EINVAL;
2903
2904         /*
2905          * KVM does not emulate a version of VMX that constrains physical
2906          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2907          */
2908         if (data & BIT_ULL(48))
2909                 return -EINVAL;
2910
2911         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2912             vmx_basic_vmcs_revision_id(data))
2913                 return -EINVAL;
2914
2915         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2916                 return -EINVAL;
2917
2918         vmx->nested.nested_vmx_basic = data;
2919         return 0;
2920 }
2921
2922 static int
2923 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2924 {
2925         u64 supported;
2926         u32 *lowp, *highp;
2927
2928         switch (msr_index) {
2929         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2930                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2931                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2932                 break;
2933         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2934                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2935                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2936                 break;
2937         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2938                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2939                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2940                 break;
2941         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2942                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2943                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2944                 break;
2945         case MSR_IA32_VMX_PROCBASED_CTLS2:
2946                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2947                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2948                 break;
2949         default:
2950                 BUG();
2951         }
2952
2953         supported = vmx_control_msr(*lowp, *highp);
2954
2955         /* Check must-be-1 bits are still 1. */
2956         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2957                 return -EINVAL;
2958
2959         /* Check must-be-0 bits are still 0. */
2960         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2961                 return -EINVAL;
2962
2963         *lowp = data;
2964         *highp = data >> 32;
2965         return 0;
2966 }
2967
2968 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2969 {
2970         const u64 feature_and_reserved_bits =
2971                 /* feature */
2972                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2973                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2974                 /* reserved */
2975                 GENMASK_ULL(13, 9) | BIT_ULL(31);
2976         u64 vmx_misc;
2977
2978         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2979                                    vmx->nested.nested_vmx_misc_high);
2980
2981         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2982                 return -EINVAL;
2983
2984         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2985              PIN_BASED_VMX_PREEMPTION_TIMER) &&
2986             vmx_misc_preemption_timer_rate(data) !=
2987             vmx_misc_preemption_timer_rate(vmx_misc))
2988                 return -EINVAL;
2989
2990         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2991                 return -EINVAL;
2992
2993         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2994                 return -EINVAL;
2995
2996         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2997                 return -EINVAL;
2998
2999         vmx->nested.nested_vmx_misc_low = data;
3000         vmx->nested.nested_vmx_misc_high = data >> 32;
3001         return 0;
3002 }
3003
3004 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3005 {
3006         u64 vmx_ept_vpid_cap;
3007
3008         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3009                                            vmx->nested.nested_vmx_vpid_caps);
3010
3011         /* Every bit is either reserved or a feature bit. */
3012         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3013                 return -EINVAL;
3014
3015         vmx->nested.nested_vmx_ept_caps = data;
3016         vmx->nested.nested_vmx_vpid_caps = data >> 32;
3017         return 0;
3018 }
3019
3020 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3021 {
3022         u64 *msr;
3023
3024         switch (msr_index) {
3025         case MSR_IA32_VMX_CR0_FIXED0:
3026                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3027                 break;
3028         case MSR_IA32_VMX_CR4_FIXED0:
3029                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3030                 break;
3031         default:
3032                 BUG();
3033         }
3034
3035         /*
3036          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3037          * must be 1 in the restored value.
3038          */
3039         if (!is_bitwise_subset(data, *msr, -1ULL))
3040                 return -EINVAL;
3041
3042         *msr = data;
3043         return 0;
3044 }
3045
3046 /*
3047  * Called when userspace is restoring VMX MSRs.
3048  *
3049  * Returns 0 on success, non-0 otherwise.
3050  */
3051 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3052 {
3053         struct vcpu_vmx *vmx = to_vmx(vcpu);
3054
3055         switch (msr_index) {
3056         case MSR_IA32_VMX_BASIC:
3057                 return vmx_restore_vmx_basic(vmx, data);
3058         case MSR_IA32_VMX_PINBASED_CTLS:
3059         case MSR_IA32_VMX_PROCBASED_CTLS:
3060         case MSR_IA32_VMX_EXIT_CTLS:
3061         case MSR_IA32_VMX_ENTRY_CTLS:
3062                 /*
3063                  * The "non-true" VMX capability MSRs are generated from the
3064                  * "true" MSRs, so we do not support restoring them directly.
3065                  *
3066                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3067                  * should restore the "true" MSRs with the must-be-1 bits
3068                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3069                  * DEFAULT SETTINGS".
3070                  */
3071                 return -EINVAL;
3072         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3073         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3074         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3075         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3076         case MSR_IA32_VMX_PROCBASED_CTLS2:
3077                 return vmx_restore_control_msr(vmx, msr_index, data);
3078         case MSR_IA32_VMX_MISC:
3079                 return vmx_restore_vmx_misc(vmx, data);
3080         case MSR_IA32_VMX_CR0_FIXED0:
3081         case MSR_IA32_VMX_CR4_FIXED0:
3082                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3083         case MSR_IA32_VMX_CR0_FIXED1:
3084         case MSR_IA32_VMX_CR4_FIXED1:
3085                 /*
3086                  * These MSRs are generated based on the vCPU's CPUID, so we
3087                  * do not support restoring them directly.
3088                  */
3089                 return -EINVAL;
3090         case MSR_IA32_VMX_EPT_VPID_CAP:
3091                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3092         case MSR_IA32_VMX_VMCS_ENUM:
3093                 vmx->nested.nested_vmx_vmcs_enum = data;
3094                 return 0;
3095         default:
3096                 /*
3097                  * The rest of the VMX capability MSRs do not support restore.
3098                  */
3099                 return -EINVAL;
3100         }
3101 }
3102
3103 /* Returns 0 on success, non-0 otherwise. */
3104 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3105 {
3106         struct vcpu_vmx *vmx = to_vmx(vcpu);
3107
3108         switch (msr_index) {
3109         case MSR_IA32_VMX_BASIC:
3110                 *pdata = vmx->nested.nested_vmx_basic;
3111                 break;
3112         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3113         case MSR_IA32_VMX_PINBASED_CTLS:
3114                 *pdata = vmx_control_msr(
3115                         vmx->nested.nested_vmx_pinbased_ctls_low,
3116                         vmx->nested.nested_vmx_pinbased_ctls_high);
3117                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3118                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3119                 break;
3120         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3121         case MSR_IA32_VMX_PROCBASED_CTLS:
3122                 *pdata = vmx_control_msr(
3123                         vmx->nested.nested_vmx_procbased_ctls_low,
3124                         vmx->nested.nested_vmx_procbased_ctls_high);
3125                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3126                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3127                 break;
3128         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3129         case MSR_IA32_VMX_EXIT_CTLS:
3130                 *pdata = vmx_control_msr(
3131                         vmx->nested.nested_vmx_exit_ctls_low,
3132                         vmx->nested.nested_vmx_exit_ctls_high);
3133                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3134                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3135                 break;
3136         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3137         case MSR_IA32_VMX_ENTRY_CTLS:
3138                 *pdata = vmx_control_msr(
3139                         vmx->nested.nested_vmx_entry_ctls_low,
3140                         vmx->nested.nested_vmx_entry_ctls_high);
3141                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3142                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3143                 break;
3144         case MSR_IA32_VMX_MISC:
3145                 *pdata = vmx_control_msr(
3146                         vmx->nested.nested_vmx_misc_low,
3147                         vmx->nested.nested_vmx_misc_high);
3148                 break;
3149         case MSR_IA32_VMX_CR0_FIXED0:
3150                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3151                 break;
3152         case MSR_IA32_VMX_CR0_FIXED1:
3153                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3154                 break;
3155         case MSR_IA32_VMX_CR4_FIXED0:
3156                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3157                 break;
3158         case MSR_IA32_VMX_CR4_FIXED1:
3159                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3160                 break;
3161         case MSR_IA32_VMX_VMCS_ENUM:
3162                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3163                 break;
3164         case MSR_IA32_VMX_PROCBASED_CTLS2:
3165                 *pdata = vmx_control_msr(
3166                         vmx->nested.nested_vmx_secondary_ctls_low,
3167                         vmx->nested.nested_vmx_secondary_ctls_high);
3168                 break;
3169         case MSR_IA32_VMX_EPT_VPID_CAP:
3170                 *pdata = vmx->nested.nested_vmx_ept_caps |
3171                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3172                 break;
3173         default:
3174                 return 1;
3175         }
3176
3177         return 0;
3178 }
3179
3180 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3181                                                  uint64_t val)
3182 {
3183         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3184
3185         return !(val & ~valid_bits);
3186 }
3187
3188 /*
3189  * Reads an msr value (of 'msr_index') into 'pdata'.
3190  * Returns 0 on success, non-0 otherwise.
3191  * Assumes vcpu_load() was already called.
3192  */
3193 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3194 {
3195         struct shared_msr_entry *msr;
3196
3197         switch (msr_info->index) {
3198 #ifdef CONFIG_X86_64
3199         case MSR_FS_BASE:
3200                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3201                 break;
3202         case MSR_GS_BASE:
3203                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3204                 break;
3205         case MSR_KERNEL_GS_BASE:
3206                 vmx_load_host_state(to_vmx(vcpu));
3207                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3208                 break;
3209 #endif
3210         case MSR_EFER:
3211                 return kvm_get_msr_common(vcpu, msr_info);
3212         case MSR_IA32_TSC:
3213                 msr_info->data = guest_read_tsc(vcpu);
3214                 break;
3215         case MSR_IA32_SYSENTER_CS:
3216                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3217                 break;
3218         case MSR_IA32_SYSENTER_EIP:
3219                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3220                 break;
3221         case MSR_IA32_SYSENTER_ESP:
3222                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3223                 break;
3224         case MSR_IA32_BNDCFGS:
3225                 if (!kvm_mpx_supported() ||
3226                     (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
3227                         return 1;
3228                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3229                 break;
3230         case MSR_IA32_MCG_EXT_CTL:
3231                 if (!msr_info->host_initiated &&
3232                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3233                       FEATURE_CONTROL_LMCE))
3234                         return 1;
3235                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3236                 break;
3237         case MSR_IA32_FEATURE_CONTROL:
3238                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3239                 break;
3240         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3241                 if (!nested_vmx_allowed(vcpu))
3242                         return 1;
3243                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3244         case MSR_IA32_XSS:
3245                 if (!vmx_xsaves_supported())
3246                         return 1;
3247                 msr_info->data = vcpu->arch.ia32_xss;
3248                 break;
3249         case MSR_TSC_AUX:
3250                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3251                         return 1;
3252                 /* Otherwise falls through */
3253         default:
3254                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3255                 if (msr) {
3256                         msr_info->data = msr->data;
3257                         break;
3258                 }
3259                 return kvm_get_msr_common(vcpu, msr_info);
3260         }
3261
3262         return 0;
3263 }
3264
3265 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3266
3267 /*
3268  * Writes msr value into into the appropriate "register".
3269  * Returns 0 on success, non-0 otherwise.
3270  * Assumes vcpu_load() was already called.
3271  */
3272 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3273 {
3274         struct vcpu_vmx *vmx = to_vmx(vcpu);
3275         struct shared_msr_entry *msr;
3276         int ret = 0;
3277         u32 msr_index = msr_info->index;
3278         u64 data = msr_info->data;
3279
3280         switch (msr_index) {
3281         case MSR_EFER:
3282                 ret = kvm_set_msr_common(vcpu, msr_info);
3283                 break;
3284 #ifdef CONFIG_X86_64
3285         case MSR_FS_BASE:
3286                 vmx_segment_cache_clear(vmx);
3287                 vmcs_writel(GUEST_FS_BASE, data);
3288                 break;
3289         case MSR_GS_BASE:
3290                 vmx_segment_cache_clear(vmx);
3291                 vmcs_writel(GUEST_GS_BASE, data);
3292                 break;
3293         case MSR_KERNEL_GS_BASE:
3294                 vmx_load_host_state(vmx);
3295                 vmx->msr_guest_kernel_gs_base = data;
3296                 break;
3297 #endif
3298         case MSR_IA32_SYSENTER_CS:
3299                 vmcs_write32(GUEST_SYSENTER_CS, data);
3300                 break;
3301         case MSR_IA32_SYSENTER_EIP:
3302                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3303                 break;
3304         case MSR_IA32_SYSENTER_ESP:
3305                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3306                 break;
3307         case MSR_IA32_BNDCFGS:
3308                 if (!kvm_mpx_supported() ||
3309                     (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
3310                         return 1;
3311                 if (is_noncanonical_address(data & PAGE_MASK) ||
3312                     (data & MSR_IA32_BNDCFGS_RSVD))
3313                         return 1;
3314                 vmcs_write64(GUEST_BNDCFGS, data);
3315                 break;
3316         case MSR_IA32_TSC:
3317                 kvm_write_tsc(vcpu, msr_info);
3318                 break;
3319         case MSR_IA32_CR_PAT:
3320                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3321                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3322                                 return 1;
3323                         vmcs_write64(GUEST_IA32_PAT, data);
3324                         vcpu->arch.pat = data;
3325                         break;
3326                 }
3327                 ret = kvm_set_msr_common(vcpu, msr_info);
3328                 break;
3329         case MSR_IA32_TSC_ADJUST:
3330                 ret = kvm_set_msr_common(vcpu, msr_info);
3331                 break;
3332         case MSR_IA32_MCG_EXT_CTL:
3333                 if ((!msr_info->host_initiated &&
3334                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3335                        FEATURE_CONTROL_LMCE)) ||
3336                     (data & ~MCG_EXT_CTL_LMCE_EN))
3337                         return 1;
3338                 vcpu->arch.mcg_ext_ctl = data;
3339                 break;
3340         case MSR_IA32_FEATURE_CONTROL:
3341                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3342                     (to_vmx(vcpu)->msr_ia32_feature_control &
3343                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3344                         return 1;
3345                 vmx->msr_ia32_feature_control = data;
3346                 if (msr_info->host_initiated && data == 0)
3347                         vmx_leave_nested(vcpu);
3348                 break;
3349         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3350                 if (!msr_info->host_initiated)
3351                         return 1; /* they are read-only */
3352                 if (!nested_vmx_allowed(vcpu))
3353                         return 1;
3354                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3355         case MSR_IA32_XSS:
3356                 if (!vmx_xsaves_supported())
3357                         return 1;
3358                 /*
3359                  * The only supported bit as of Skylake is bit 8, but
3360                  * it is not supported on KVM.
3361                  */
3362                 if (data != 0)
3363                         return 1;
3364                 vcpu->arch.ia32_xss = data;
3365                 if (vcpu->arch.ia32_xss != host_xss)
3366                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3367                                 vcpu->arch.ia32_xss, host_xss);
3368                 else
3369                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3370                 break;
3371         case MSR_TSC_AUX:
3372                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3373                         return 1;
3374                 /* Check reserved bit, higher 32 bits should be zero */
3375                 if ((data >> 32) != 0)
3376                         return 1;
3377                 /* Otherwise falls through */
3378         default:
3379                 msr = find_msr_entry(vmx, msr_index);
3380                 if (msr) {
3381                         u64 old_msr_data = msr->data;
3382                         msr->data = data;
3383                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3384                                 preempt_disable();
3385                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3386                                                          msr->mask);
3387                                 preempt_enable();
3388                                 if (ret)
3389                                         msr->data = old_msr_data;
3390                         }
3391                         break;
3392                 }
3393                 ret = kvm_set_msr_common(vcpu, msr_info);
3394         }
3395
3396         return ret;
3397 }
3398
3399 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3400 {
3401         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3402         switch (reg) {
3403         case VCPU_REGS_RSP:
3404                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3405                 break;
3406         case VCPU_REGS_RIP:
3407                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3408                 break;
3409         case VCPU_EXREG_PDPTR:
3410                 if (enable_ept)
3411                         ept_save_pdptrs(vcpu);
3412                 break;
3413         default:
3414                 break;
3415         }
3416 }
3417
3418 static __init int cpu_has_kvm_support(void)
3419 {
3420         return cpu_has_vmx();
3421 }
3422
3423 static __init int vmx_disabled_by_bios(void)
3424 {
3425         u64 msr;
3426
3427         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3428         if (msr & FEATURE_CONTROL_LOCKED) {
3429                 /* launched w/ TXT and VMX disabled */
3430                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3431                         && tboot_enabled())
3432                         return 1;
3433                 /* launched w/o TXT and VMX only enabled w/ TXT */
3434                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3435                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3436                         && !tboot_enabled()) {
3437                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3438                                 "activate TXT before enabling KVM\n");
3439                         return 1;
3440                 }
3441                 /* launched w/o TXT and VMX disabled */
3442                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3443                         && !tboot_enabled())
3444                         return 1;
3445         }
3446
3447         return 0;
3448 }
3449
3450 static void kvm_cpu_vmxon(u64 addr)
3451 {
3452         cr4_set_bits(X86_CR4_VMXE);
3453         intel_pt_handle_vmx(1);
3454
3455         asm volatile (ASM_VMX_VMXON_RAX
3456                         : : "a"(&addr), "m"(addr)
3457                         : "memory", "cc");
3458 }
3459
3460 static int hardware_enable(void)
3461 {
3462         int cpu = raw_smp_processor_id();
3463         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3464         u64 old, test_bits;
3465
3466         if (cr4_read_shadow() & X86_CR4_VMXE)
3467                 return -EBUSY;
3468
3469         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3470         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3471         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3472
3473         /*
3474          * Now we can enable the vmclear operation in kdump
3475          * since the loaded_vmcss_on_cpu list on this cpu
3476          * has been initialized.
3477          *
3478          * Though the cpu is not in VMX operation now, there
3479          * is no problem to enable the vmclear operation
3480          * for the loaded_vmcss_on_cpu list is empty!
3481          */
3482         crash_enable_local_vmclear(cpu);
3483
3484         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3485
3486         test_bits = FEATURE_CONTROL_LOCKED;
3487         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3488         if (tboot_enabled())
3489                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3490
3491         if ((old & test_bits) != test_bits) {
3492                 /* enable and lock */
3493                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3494         }
3495         kvm_cpu_vmxon(phys_addr);
3496         ept_sync_global();
3497
3498         return 0;
3499 }
3500
3501 static void vmclear_local_loaded_vmcss(void)
3502 {
3503         int cpu = raw_smp_processor_id();
3504         struct loaded_vmcs *v, *n;
3505
3506         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3507                                  loaded_vmcss_on_cpu_link)
3508                 __loaded_vmcs_clear(v);
3509 }
3510
3511
3512 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3513  * tricks.
3514  */
3515 static void kvm_cpu_vmxoff(void)
3516 {
3517         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3518
3519         intel_pt_handle_vmx(0);
3520         cr4_clear_bits(X86_CR4_VMXE);
3521 }
3522
3523 static void hardware_disable(void)
3524 {
3525         vmclear_local_loaded_vmcss();
3526         kvm_cpu_vmxoff();
3527 }
3528
3529 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3530                                       u32 msr, u32 *result)
3531 {
3532         u32 vmx_msr_low, vmx_msr_high;
3533         u32 ctl = ctl_min | ctl_opt;
3534
3535         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3536
3537         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3538         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3539
3540         /* Ensure minimum (required) set of control bits are supported. */
3541         if (ctl_min & ~ctl)
3542                 return -EIO;
3543
3544         *result = ctl;
3545         return 0;
3546 }
3547
3548 static __init bool allow_1_setting(u32 msr, u32 ctl)
3549 {
3550         u32 vmx_msr_low, vmx_msr_high;
3551
3552         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3553         return vmx_msr_high & ctl;
3554 }
3555
3556 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3557 {
3558         u32 vmx_msr_low, vmx_msr_high;
3559         u32 min, opt, min2, opt2;
3560         u32 _pin_based_exec_control = 0;
3561         u32 _cpu_based_exec_control = 0;
3562         u32 _cpu_based_2nd_exec_control = 0;
3563         u32 _vmexit_control = 0;
3564         u32 _vmentry_control = 0;
3565
3566         min = CPU_BASED_HLT_EXITING |
3567 #ifdef CONFIG_X86_64
3568               CPU_BASED_CR8_LOAD_EXITING |
3569               CPU_BASED_CR8_STORE_EXITING |
3570 #endif
3571               CPU_BASED_CR3_LOAD_EXITING |
3572               CPU_BASED_CR3_STORE_EXITING |
3573               CPU_BASED_USE_IO_BITMAPS |
3574               CPU_BASED_MOV_DR_EXITING |
3575               CPU_BASED_USE_TSC_OFFSETING |
3576               CPU_BASED_INVLPG_EXITING |
3577               CPU_BASED_RDPMC_EXITING;
3578
3579         if (!kvm_mwait_in_guest())
3580                 min |= CPU_BASED_MWAIT_EXITING |
3581                         CPU_BASED_MONITOR_EXITING;
3582
3583         opt = CPU_BASED_TPR_SHADOW |
3584               CPU_BASED_USE_MSR_BITMAPS |
3585               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3586         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3587                                 &_cpu_based_exec_control) < 0)
3588                 return -EIO;
3589 #ifdef CONFIG_X86_64
3590         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3591                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3592                                            ~CPU_BASED_CR8_STORE_EXITING;
3593 #endif
3594         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3595                 min2 = 0;
3596                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3597                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3598                         SECONDARY_EXEC_WBINVD_EXITING |
3599                         SECONDARY_EXEC_ENABLE_VPID |
3600                         SECONDARY_EXEC_ENABLE_EPT |
3601                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3602                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3603                         SECONDARY_EXEC_RDTSCP |
3604                         SECONDARY_EXEC_ENABLE_INVPCID |
3605                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3606                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3607                         SECONDARY_EXEC_SHADOW_VMCS |
3608                         SECONDARY_EXEC_XSAVES |
3609                         SECONDARY_EXEC_ENABLE_PML |
3610                         SECONDARY_EXEC_TSC_SCALING;
3611                 if (adjust_vmx_controls(min2, opt2,
3612                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3613                                         &_cpu_based_2nd_exec_control) < 0)
3614                         return -EIO;
3615         }
3616 #ifndef CONFIG_X86_64
3617         if (!(_cpu_based_2nd_exec_control &
3618                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3619                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3620 #endif
3621
3622         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3623                 _cpu_based_2nd_exec_control &= ~(
3624                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3625                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3626                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3627
3628         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3629                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3630                    enabled */
3631                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3632                                              CPU_BASED_CR3_STORE_EXITING |
3633                                              CPU_BASED_INVLPG_EXITING);
3634                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3635                       vmx_capability.ept, vmx_capability.vpid);
3636         }
3637
3638         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3639 #ifdef CONFIG_X86_64
3640         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3641 #endif
3642         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3643                 VM_EXIT_CLEAR_BNDCFGS;
3644         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3645                                 &_vmexit_control) < 0)
3646                 return -EIO;
3647
3648         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3649                 PIN_BASED_VIRTUAL_NMIS;
3650         opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
3651         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3652                                 &_pin_based_exec_control) < 0)
3653                 return -EIO;
3654
3655         if (cpu_has_broken_vmx_preemption_timer())
3656                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3657         if (!(_cpu_based_2nd_exec_control &
3658                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3659                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3660
3661         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3662         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3663         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3664                                 &_vmentry_control) < 0)
3665                 return -EIO;
3666
3667         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3668
3669         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3670         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3671                 return -EIO;
3672
3673 #ifdef CONFIG_X86_64
3674         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3675         if (vmx_msr_high & (1u<<16))
3676                 return -EIO;
3677 #endif
3678
3679         /* Require Write-Back (WB) memory type for VMCS accesses. */
3680         if (((vmx_msr_high >> 18) & 15) != 6)
3681                 return -EIO;
3682
3683         vmcs_conf->size = vmx_msr_high & 0x1fff;
3684         vmcs_conf->order = get_order(vmcs_conf->size);
3685         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3686         vmcs_conf->revision_id = vmx_msr_low;
3687
3688         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3689         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3690         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3691         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3692         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3693
3694         cpu_has_load_ia32_efer =
3695                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3696                                 VM_ENTRY_LOAD_IA32_EFER)
3697                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3698                                    VM_EXIT_LOAD_IA32_EFER);
3699
3700         cpu_has_load_perf_global_ctrl =
3701                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3702                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3703                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3704                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3705
3706         /*
3707          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3708          * but due to errata below it can't be used. Workaround is to use
3709          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3710          *
3711          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3712          *
3713          * AAK155             (model 26)
3714          * AAP115             (model 30)
3715          * AAT100             (model 37)
3716          * BC86,AAY89,BD102   (model 44)
3717          * BA97               (model 46)
3718          *
3719          */
3720         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3721                 switch (boot_cpu_data.x86_model) {
3722                 case 26:
3723                 case 30:
3724                 case 37:
3725                 case 44:
3726                 case 46:
3727                         cpu_has_load_perf_global_ctrl = false;
3728                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3729                                         "does not work properly. Using workaround\n");
3730                         break;
3731                 default:
3732                         break;
3733                 }
3734         }
3735
3736         if (boot_cpu_has(X86_FEATURE_XSAVES))
3737                 rdmsrl(MSR_IA32_XSS, host_xss);
3738
3739         return 0;
3740 }
3741
3742 static struct vmcs *alloc_vmcs_cpu(int cpu)
3743 {
3744         int node = cpu_to_node(cpu);
3745         struct page *pages;
3746         struct vmcs *vmcs;
3747
3748         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3749         if (!pages)
3750                 return NULL;
3751         vmcs = page_address(pages);
3752         memset(vmcs, 0, vmcs_config.size);
3753         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3754         return vmcs;
3755 }
3756
3757 static struct vmcs *alloc_vmcs(void)
3758 {
3759         return alloc_vmcs_cpu(raw_smp_processor_id());
3760 }
3761
3762 static void free_vmcs(struct vmcs *vmcs)
3763 {
3764         free_pages((unsigned long)vmcs, vmcs_config.order);
3765 }
3766
3767 /*
3768  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3769  */
3770 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3771 {
3772         if (!loaded_vmcs->vmcs)
3773                 return;
3774         loaded_vmcs_clear(loaded_vmcs);
3775         free_vmcs(loaded_vmcs->vmcs);
3776         loaded_vmcs->vmcs = NULL;
3777         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3778 }
3779
3780 static void free_kvm_area(void)
3781 {
3782         int cpu;
3783
3784         for_each_possible_cpu(cpu) {
3785                 free_vmcs(per_cpu(vmxarea, cpu));
3786                 per_cpu(vmxarea, cpu) = NULL;
3787         }
3788 }
3789
3790 enum vmcs_field_type {
3791         VMCS_FIELD_TYPE_U16 = 0,
3792         VMCS_FIELD_TYPE_U64 = 1,
3793         VMCS_FIELD_TYPE_U32 = 2,
3794         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
3795 };
3796
3797 static inline int vmcs_field_type(unsigned long field)
3798 {
3799         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
3800                 return VMCS_FIELD_TYPE_U32;
3801         return (field >> 13) & 0x3 ;
3802 }
3803
3804 static inline int vmcs_field_readonly(unsigned long field)
3805 {
3806         return (((field >> 10) & 0x3) == 1);
3807 }
3808
3809 static void init_vmcs_shadow_fields(void)
3810 {
3811         int i, j;
3812
3813         /* No checks for read only fields yet */
3814
3815         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3816                 switch (shadow_read_write_fields[i]) {
3817                 case GUEST_BNDCFGS:
3818                         if (!kvm_mpx_supported())
3819                                 continue;
3820                         break;
3821                 default:
3822                         break;
3823                 }
3824
3825                 if (j < i)
3826                         shadow_read_write_fields[j] =
3827                                 shadow_read_write_fields[i];
3828                 j++;
3829         }
3830         max_shadow_read_write_fields = j;
3831
3832         /* shadowed fields guest access without vmexit */
3833         for (i = 0; i < max_shadow_read_write_fields; i++) {
3834                 unsigned long field = shadow_read_write_fields[i];
3835
3836                 clear_bit(field, vmx_vmwrite_bitmap);
3837                 clear_bit(field, vmx_vmread_bitmap);
3838                 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) {
3839                         clear_bit(field + 1, vmx_vmwrite_bitmap);
3840                         clear_bit(field + 1, vmx_vmread_bitmap);
3841                 }
3842         }
3843         for (i = 0; i < max_shadow_read_only_fields; i++) {
3844                 unsigned long field = shadow_read_only_fields[i];
3845
3846                 clear_bit(field, vmx_vmread_bitmap);
3847                 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64)
3848                         clear_bit(field + 1, vmx_vmread_bitmap);
3849         }
3850 }
3851
3852 static __init int alloc_kvm_area(void)
3853 {
3854         int cpu;
3855
3856         for_each_possible_cpu(cpu) {
3857                 struct vmcs *vmcs;
3858
3859                 vmcs = alloc_vmcs_cpu(cpu);
3860                 if (!vmcs) {
3861                         free_kvm_area();
3862                         return -ENOMEM;
3863                 }
3864
3865                 per_cpu(vmxarea, cpu) = vmcs;
3866         }
3867         return 0;
3868 }
3869
3870 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3871                 struct kvm_segment *save)
3872 {
3873         if (!emulate_invalid_guest_state) {
3874                 /*
3875                  * CS and SS RPL should be equal during guest entry according
3876                  * to VMX spec, but in reality it is not always so. Since vcpu
3877                  * is in the middle of the transition from real mode to
3878                  * protected mode it is safe to assume that RPL 0 is a good
3879                  * default value.
3880                  */
3881                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3882                         save->selector &= ~SEGMENT_RPL_MASK;
3883                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3884                 save->s = 1;
3885         }
3886         vmx_set_segment(vcpu, save, seg);
3887 }
3888
3889 static void enter_pmode(struct kvm_vcpu *vcpu)
3890 {
3891         unsigned long flags;
3892         struct vcpu_vmx *vmx = to_vmx(vcpu);
3893
3894         /*
3895          * Update real mode segment cache. It may be not up-to-date if sement
3896          * register was written while vcpu was in a guest mode.
3897          */
3898         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3899         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3900         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3901         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3902         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3903         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3904
3905         vmx->rmode.vm86_active = 0;
3906
3907         vmx_segment_cache_clear(vmx);
3908
3909         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3910
3911         flags = vmcs_readl(GUEST_RFLAGS);
3912         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3913         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3914         vmcs_writel(GUEST_RFLAGS, flags);
3915
3916         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3917                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3918
3919         update_exception_bitmap(vcpu);
3920
3921         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3922         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3923         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3924         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3925         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3926         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3927 }
3928
3929 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3930 {
3931         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3932         struct kvm_segment var = *save;
3933
3934         var.dpl = 0x3;
3935         if (seg == VCPU_SREG_CS)
3936                 var.type = 0x3;
3937
3938         if (!emulate_invalid_guest_state) {
3939                 var.selector = var.base >> 4;
3940                 var.base = var.base & 0xffff0;
3941                 var.limit = 0xffff;
3942                 var.g = 0;
3943                 var.db = 0;
3944                 var.present = 1;
3945                 var.s = 1;
3946                 var.l = 0;
3947                 var.unusable = 0;
3948                 var.type = 0x3;
3949                 var.avl = 0;
3950                 if (save->base & 0xf)
3951                         printk_once(KERN_WARNING "kvm: segment base is not "
3952                                         "paragraph aligned when entering "
3953                                         "protected mode (seg=%d)", seg);
3954         }
3955
3956         vmcs_write16(sf->selector, var.selector);
3957         vmcs_writel(sf->base, var.base);
3958         vmcs_write32(sf->limit, var.limit);
3959         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3960 }
3961
3962 static void enter_rmode(struct kvm_vcpu *vcpu)
3963 {
3964         unsigned long flags;
3965         struct vcpu_vmx *vmx = to_vmx(vcpu);
3966
3967         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3968         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3969         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3970         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3971         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3972         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3973         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3974
3975         vmx->rmode.vm86_active = 1;
3976
3977         /*
3978          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3979          * vcpu. Warn the user that an update is overdue.
3980          */
3981         if (!vcpu->kvm->arch.tss_addr)
3982                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3983                              "called before entering vcpu\n");
3984
3985         vmx_segment_cache_clear(vmx);
3986
3987         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3988         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3989         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3990
3991         flags = vmcs_readl(GUEST_RFLAGS);
3992         vmx->rmode.save_rflags = flags;
3993
3994         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3995
3996         vmcs_writel(GUEST_RFLAGS, flags);
3997         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3998         update_exception_bitmap(vcpu);
3999
4000         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4001         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4002         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4003         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4004         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4005         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4006
4007         kvm_mmu_reset_context(vcpu);
4008 }
4009
4010 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4011 {
4012         struct vcpu_vmx *vmx = to_vmx(vcpu);
4013         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4014
4015         if (!msr)
4016                 return;
4017
4018         /*
4019          * Force kernel_gs_base reloading before EFER changes, as control
4020          * of this msr depends on is_long_mode().
4021          */
4022         vmx_load_host_state(to_vmx(vcpu));
4023         vcpu->arch.efer = efer;
4024         if (efer & EFER_LMA) {
4025                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4026                 msr->data = efer;
4027         } else {
4028                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4029
4030                 msr->data = efer & ~EFER_LME;
4031         }
4032         setup_msrs(vmx);
4033 }
4034
4035 #ifdef CONFIG_X86_64
4036
4037 static void enter_lmode(struct kvm_vcpu *vcpu)
4038 {
4039         u32 guest_tr_ar;
4040
4041         vmx_segment_cache_clear(to_vmx(vcpu));
4042
4043         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4044         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4045                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4046                                      __func__);
4047                 vmcs_write32(GUEST_TR_AR_BYTES,
4048                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4049                              | VMX_AR_TYPE_BUSY_64_TSS);
4050         }
4051         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4052 }
4053
4054 static void exit_lmode(struct kvm_vcpu *vcpu)
4055 {
4056         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4057         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4058 }
4059
4060 #endif
4061
4062 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4063 {
4064         if (enable_ept) {
4065                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4066                         return;
4067                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4068         } else {
4069                 vpid_sync_context(vpid);
4070         }
4071 }
4072
4073 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4074 {
4075         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4076 }
4077
4078 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4079 {
4080         if (enable_ept)
4081                 vmx_flush_tlb(vcpu);
4082 }
4083
4084 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4085 {
4086         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4087
4088         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4089         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4090 }
4091
4092 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4093 {
4094         if (enable_ept && is_paging(vcpu))
4095                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4096         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4097 }
4098
4099 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4100 {
4101         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4102
4103         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4104         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4105 }
4106
4107 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4108 {
4109         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4110
4111         if (!test_bit(VCPU_EXREG_PDPTR,
4112                       (unsigned long *)&vcpu->arch.regs_dirty))
4113                 return;
4114
4115         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4116                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4117                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4118                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4119                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4120         }
4121 }
4122
4123 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4124 {
4125         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4126
4127         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4128                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4129                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4130                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4131                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4132         }
4133
4134         __set_bit(VCPU_EXREG_PDPTR,
4135                   (unsigned long *)&vcpu->arch.regs_avail);
4136         __set_bit(VCPU_EXREG_PDPTR,
4137                   (unsigned long *)&vcpu->arch.regs_dirty);
4138 }
4139
4140 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4141 {
4142         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4143         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4144         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4145
4146         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4147                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4148             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4149                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4150
4151         return fixed_bits_valid(val, fixed0, fixed1);
4152 }
4153
4154 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4155 {
4156         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4157         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4158
4159         return fixed_bits_valid(val, fixed0, fixed1);
4160 }
4161
4162 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4163 {
4164         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4165         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4166
4167         return fixed_bits_valid(val, fixed0, fixed1);
4168 }
4169
4170 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4171 #define nested_guest_cr4_valid  nested_cr4_valid
4172 #define nested_host_cr4_valid   nested_cr4_valid
4173
4174 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4175
4176 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4177                                         unsigned long cr0,
4178                                         struct kvm_vcpu *vcpu)
4179 {
4180         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4181                 vmx_decache_cr3(vcpu);
4182         if (!(cr0 & X86_CR0_PG)) {
4183                 /* From paging/starting to nonpaging */
4184                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4185                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4186                              (CPU_BASED_CR3_LOAD_EXITING |
4187                               CPU_BASED_CR3_STORE_EXITING));
4188                 vcpu->arch.cr0 = cr0;
4189                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4190         } else if (!is_paging(vcpu)) {
4191                 /* From nonpaging to paging */
4192                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4193                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4194                              ~(CPU_BASED_CR3_LOAD_EXITING |
4195                                CPU_BASED_CR3_STORE_EXITING));
4196                 vcpu->arch.cr0 = cr0;
4197                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4198         }
4199
4200         if (!(cr0 & X86_CR0_WP))
4201                 *hw_cr0 &= ~X86_CR0_WP;
4202 }
4203
4204 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4205 {
4206         struct vcpu_vmx *vmx = to_vmx(vcpu);
4207         unsigned long hw_cr0;
4208
4209         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4210         if (enable_unrestricted_guest)
4211                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4212         else {
4213                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4214
4215                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4216                         enter_pmode(vcpu);
4217
4218                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4219                         enter_rmode(vcpu);
4220         }
4221
4222 #ifdef CONFIG_X86_64
4223         if (vcpu->arch.efer & EFER_LME) {
4224                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4225                         enter_lmode(vcpu);
4226                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4227                         exit_lmode(vcpu);
4228         }
4229 #endif
4230
4231         if (enable_ept)
4232                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4233
4234         vmcs_writel(CR0_READ_SHADOW, cr0);
4235         vmcs_writel(GUEST_CR0, hw_cr0);
4236         vcpu->arch.cr0 = cr0;
4237
4238         /* depends on vcpu->arch.cr0 to be set to a new value */
4239         vmx->emulation_required = emulation_required(vcpu);
4240 }
4241
4242 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4243 {
4244         u64 eptp;
4245
4246         /* TODO write the value reading from MSR */
4247         eptp = VMX_EPT_DEFAULT_MT |
4248                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4249         if (enable_ept_ad_bits &&
4250             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4251                 eptp |= VMX_EPT_AD_ENABLE_BIT;
4252         eptp |= (root_hpa & PAGE_MASK);
4253
4254         return eptp;
4255 }
4256
4257 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4258 {
4259         unsigned long guest_cr3;
4260         u64 eptp;
4261
4262         guest_cr3 = cr3;
4263         if (enable_ept) {
4264                 eptp = construct_eptp(vcpu, cr3);
4265                 vmcs_write64(EPT_POINTER, eptp);
4266                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4267                         guest_cr3 = kvm_read_cr3(vcpu);
4268                 else
4269                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4270                 ept_load_pdptrs(vcpu);
4271         }
4272
4273         vmx_flush_tlb(vcpu);
4274         vmcs_writel(GUEST_CR3, guest_cr3);
4275 }
4276
4277 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4278 {
4279         /*
4280          * Pass through host's Machine Check Enable value to hw_cr4, which
4281          * is in force while we are in guest mode.  Do not let guests control
4282          * this bit, even if host CR4.MCE == 0.
4283          */
4284         unsigned long hw_cr4 =
4285                 (cr4_read_shadow() & X86_CR4_MCE) |
4286                 (cr4 & ~X86_CR4_MCE) |
4287                 (to_vmx(vcpu)->rmode.vm86_active ?
4288                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4289
4290         if (cr4 & X86_CR4_VMXE) {
4291                 /*
4292                  * To use VMXON (and later other VMX instructions), a guest
4293                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4294                  * So basically the check on whether to allow nested VMX
4295                  * is here.
4296                  */
4297                 if (!nested_vmx_allowed(vcpu))
4298                         return 1;
4299         }
4300
4301         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4302                 return 1;
4303
4304         vcpu->arch.cr4 = cr4;
4305         if (enable_ept) {
4306                 if (!is_paging(vcpu)) {
4307                         hw_cr4 &= ~X86_CR4_PAE;
4308                         hw_cr4 |= X86_CR4_PSE;
4309                 } else if (!(cr4 & X86_CR4_PAE)) {
4310                         hw_cr4 &= ~X86_CR4_PAE;
4311                 }
4312         }
4313
4314         if (!enable_unrestricted_guest && !is_paging(vcpu))
4315                 /*
4316                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4317                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4318                  * to be manually disabled when guest switches to non-paging
4319                  * mode.
4320                  *
4321                  * If !enable_unrestricted_guest, the CPU is always running
4322                  * with CR0.PG=1 and CR4 needs to be modified.
4323                  * If enable_unrestricted_guest, the CPU automatically
4324                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4325                  */
4326                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4327
4328         vmcs_writel(CR4_READ_SHADOW, cr4);
4329         vmcs_writel(GUEST_CR4, hw_cr4);
4330         return 0;
4331 }
4332
4333 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4334                             struct kvm_segment *var, int seg)
4335 {
4336         struct vcpu_vmx *vmx = to_vmx(vcpu);
4337         u32 ar;
4338
4339         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4340                 *var = vmx->rmode.segs[seg];
4341                 if (seg == VCPU_SREG_TR
4342                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4343                         return;
4344                 var->base = vmx_read_guest_seg_base(vmx, seg);
4345                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4346                 return;
4347         }
4348         var->base = vmx_read_guest_seg_base(vmx, seg);
4349         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4350         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4351         ar = vmx_read_guest_seg_ar(vmx, seg);
4352         var->unusable = (ar >> 16) & 1;
4353         var->type = ar & 15;
4354         var->s = (ar >> 4) & 1;
4355         var->dpl = (ar >> 5) & 3;
4356         /*
4357          * Some userspaces do not preserve unusable property. Since usable
4358          * segment has to be present according to VMX spec we can use present
4359          * property to amend userspace bug by making unusable segment always
4360          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4361          * segment as unusable.
4362          */
4363         var->present = !var->unusable;
4364         var->avl = (ar >> 12) & 1;
4365         var->l = (ar >> 13) & 1;
4366         var->db = (ar >> 14) & 1;
4367         var->g = (ar >> 15) & 1;
4368 }
4369
4370 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4371 {
4372         struct kvm_segment s;
4373
4374         if (to_vmx(vcpu)->rmode.vm86_active) {
4375                 vmx_get_segment(vcpu, &s, seg);
4376                 return s.base;
4377         }
4378         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4379 }
4380
4381 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4382 {
4383         struct vcpu_vmx *vmx = to_vmx(vcpu);
4384
4385         if (unlikely(vmx->rmode.vm86_active))
4386                 return 0;
4387         else {
4388                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4389                 return VMX_AR_DPL(ar);
4390         }
4391 }
4392
4393 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4394 {
4395         u32 ar;
4396
4397         if (var->unusable || !var->present)
4398                 ar = 1 << 16;
4399         else {
4400                 ar = var->type & 15;
4401                 ar |= (var->s & 1) << 4;
4402                 ar |= (var->dpl & 3) << 5;
4403                 ar |= (var->present & 1) << 7;
4404                 ar |= (var->avl & 1) << 12;
4405                 ar |= (var->l & 1) << 13;
4406                 ar |= (var->db & 1) << 14;
4407                 ar |= (var->g & 1) << 15;
4408         }
4409
4410         return ar;
4411 }
4412
4413 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4414                             struct kvm_segment *var, int seg)
4415 {
4416         struct vcpu_vmx *vmx = to_vmx(vcpu);
4417         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4418
4419         vmx_segment_cache_clear(vmx);
4420
4421         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4422                 vmx->rmode.segs[seg] = *var;
4423                 if (seg == VCPU_SREG_TR)
4424                         vmcs_write16(sf->selector, var->selector);
4425                 else if (var->s)
4426                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4427                 goto out;
4428         }
4429
4430         vmcs_writel(sf->base, var->base);
4431         vmcs_write32(sf->limit, var->limit);
4432         vmcs_write16(sf->selector, var->selector);
4433
4434         /*
4435          *   Fix the "Accessed" bit in AR field of segment registers for older
4436          * qemu binaries.
4437          *   IA32 arch specifies that at the time of processor reset the
4438          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4439          * is setting it to 0 in the userland code. This causes invalid guest
4440          * state vmexit when "unrestricted guest" mode is turned on.
4441          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4442          * tree. Newer qemu binaries with that qemu fix would not need this
4443          * kvm hack.
4444          */
4445         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4446                 var->type |= 0x1; /* Accessed */
4447
4448         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4449
4450 out:
4451         vmx->emulation_required = emulation_required(vcpu);
4452 }
4453
4454 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4455 {
4456         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4457
4458         *db = (ar >> 14) & 1;
4459         *l = (ar >> 13) & 1;
4460 }
4461
4462 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4463 {
4464         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4465         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4466 }
4467
4468 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4469 {
4470         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4471         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4472 }
4473
4474 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4475 {
4476         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4477         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4478 }
4479
4480 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4481 {
4482         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4483         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4484 }
4485
4486 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4487 {
4488         struct kvm_segment var;
4489         u32 ar;
4490
4491         vmx_get_segment(vcpu, &var, seg);
4492         var.dpl = 0x3;
4493         if (seg == VCPU_SREG_CS)
4494                 var.type = 0x3;
4495         ar = vmx_segment_access_rights(&var);
4496
4497         if (var.base != (var.selector << 4))
4498                 return false;
4499         if (var.limit != 0xffff)
4500                 return false;
4501         if (ar != 0xf3)
4502                 return false;
4503
4504         return true;
4505 }
4506
4507 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4508 {
4509         struct kvm_segment cs;
4510         unsigned int cs_rpl;
4511
4512         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4513         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4514
4515         if (cs.unusable)
4516                 return false;
4517         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4518                 return false;
4519         if (!cs.s)
4520                 return false;
4521         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4522                 if (cs.dpl > cs_rpl)
4523                         return false;
4524         } else {
4525                 if (cs.dpl != cs_rpl)
4526                         return false;
4527         }
4528         if (!cs.present)
4529                 return false;
4530
4531         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4532         return true;
4533 }
4534
4535 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4536 {
4537         struct kvm_segment ss;
4538         unsigned int ss_rpl;
4539
4540         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4541         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4542
4543         if (ss.unusable)
4544                 return true;
4545         if (ss.type != 3 && ss.type != 7)
4546                 return false;
4547         if (!ss.s)
4548                 return false;
4549         if (ss.dpl != ss_rpl) /* DPL != RPL */
4550                 return false;
4551         if (!ss.present)
4552                 return false;
4553
4554         return true;
4555 }
4556
4557 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4558 {
4559         struct kvm_segment var;
4560         unsigned int rpl;
4561
4562         vmx_get_segment(vcpu, &var, seg);
4563         rpl = var.selector & SEGMENT_RPL_MASK;
4564
4565         if (var.unusable)
4566                 return true;
4567         if (!var.s)
4568                 return false;
4569         if (!var.present)
4570                 return false;
4571         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4572                 if (var.dpl < rpl) /* DPL < RPL */
4573                         return false;
4574         }
4575
4576         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4577          * rights flags
4578          */
4579         return true;
4580 }
4581
4582 static bool tr_valid(struct kvm_vcpu *vcpu)
4583 {
4584         struct kvm_segment tr;
4585
4586         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4587
4588         if (tr.unusable)
4589                 return false;
4590         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4591                 return false;
4592         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4593                 return false;
4594         if (!tr.present)
4595                 return false;
4596
4597         return true;
4598 }
4599
4600 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4601 {
4602         struct kvm_segment ldtr;
4603
4604         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4605
4606         if (ldtr.unusable)
4607                 return true;
4608         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4609                 return false;
4610         if (ldtr.type != 2)
4611                 return false;
4612         if (!ldtr.present)
4613                 return false;
4614
4615         return true;
4616 }
4617
4618 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4619 {
4620         struct kvm_segment cs, ss;
4621
4622         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4623         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4624
4625         return ((cs.selector & SEGMENT_RPL_MASK) ==
4626                  (ss.selector & SEGMENT_RPL_MASK));
4627 }
4628
4629 /*
4630  * Check if guest state is valid. Returns true if valid, false if
4631  * not.
4632  * We assume that registers are always usable
4633  */
4634 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4635 {
4636         if (enable_unrestricted_guest)
4637                 return true;
4638
4639         /* real mode guest state checks */
4640         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4641                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4642                         return false;
4643                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4644                         return false;
4645                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4646                         return false;
4647                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4648                         return false;
4649                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4650                         return false;
4651                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4652                         return false;
4653         } else {
4654         /* protected mode guest state checks */
4655                 if (!cs_ss_rpl_check(vcpu))
4656                         return false;
4657                 if (!code_segment_valid(vcpu))
4658                         return false;
4659                 if (!stack_segment_valid(vcpu))
4660                         return false;
4661                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4662                         return false;
4663                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4664                         return false;
4665                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4666                         return false;
4667                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4668                         return false;
4669                 if (!tr_valid(vcpu))
4670                         return false;
4671                 if (!ldtr_valid(vcpu))
4672                         return false;
4673         }
4674         /* TODO:
4675          * - Add checks on RIP
4676          * - Add checks on RFLAGS
4677          */
4678
4679         return true;
4680 }
4681
4682 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4683 {
4684         return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4685 }
4686
4687 static int init_rmode_tss(struct kvm *kvm)
4688 {
4689         gfn_t fn;
4690         u16 data = 0;
4691         int idx, r;
4692
4693         idx = srcu_read_lock(&kvm->srcu);
4694         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4695         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4696         if (r < 0)
4697                 goto out;
4698         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4699         r = kvm_write_guest_page(kvm, fn++, &data,
4700                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4701         if (r < 0)
4702                 goto out;
4703         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4704         if (r < 0)
4705                 goto out;
4706         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4707         if (r < 0)
4708                 goto out;
4709         data = ~0;
4710         r = kvm_write_guest_page(kvm, fn, &data,
4711                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4712                                  sizeof(u8));
4713 out:
4714         srcu_read_unlock(&kvm->srcu, idx);
4715         return r;
4716 }
4717
4718 static int init_rmode_identity_map(struct kvm *kvm)
4719 {
4720         int i, idx, r = 0;
4721         kvm_pfn_t identity_map_pfn;
4722         u32 tmp;
4723
4724         if (!enable_ept)
4725                 return 0;
4726
4727         /* Protect kvm->arch.ept_identity_pagetable_done. */
4728         mutex_lock(&kvm->slots_lock);
4729
4730         if (likely(kvm->arch.ept_identity_pagetable_done))
4731                 goto out2;
4732
4733         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4734
4735         r = alloc_identity_pagetable(kvm);
4736         if (r < 0)
4737                 goto out2;
4738
4739         idx = srcu_read_lock(&kvm->srcu);
4740         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4741         if (r < 0)
4742                 goto out;
4743         /* Set up identity-mapping pagetable for EPT in real mode */
4744         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4745                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4746                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4747                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4748                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4749                 if (r < 0)
4750                         goto out;
4751         }
4752         kvm->arch.ept_identity_pagetable_done = true;
4753
4754 out:
4755         srcu_read_unlock(&kvm->srcu, idx);
4756
4757 out2:
4758         mutex_unlock(&kvm->slots_lock);
4759         return r;
4760 }
4761
4762 static void seg_setup(int seg)
4763 {
4764         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4765         unsigned int ar;
4766
4767         vmcs_write16(sf->selector, 0);
4768         vmcs_writel(sf->base, 0);
4769         vmcs_write32(sf->limit, 0xffff);
4770         ar = 0x93;
4771         if (seg == VCPU_SREG_CS)
4772                 ar |= 0x08; /* code segment */
4773
4774         vmcs_write32(sf->ar_bytes, ar);
4775 }
4776
4777 static int alloc_apic_access_page(struct kvm *kvm)
4778 {
4779         struct page *page;
4780         int r = 0;
4781
4782         mutex_lock(&kvm->slots_lock);
4783         if (kvm->arch.apic_access_page_done)
4784                 goto out;
4785         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4786                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4787         if (r)
4788                 goto out;
4789
4790         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4791         if (is_error_page(page)) {
4792                 r = -EFAULT;
4793                 goto out;
4794         }
4795
4796         /*
4797          * Do not pin the page in memory, so that memory hot-unplug
4798          * is able to migrate it.
4799          */
4800         put_page(page);
4801         kvm->arch.apic_access_page_done = true;
4802 out:
4803         mutex_unlock(&kvm->slots_lock);
4804         return r;
4805 }
4806
4807 static int alloc_identity_pagetable(struct kvm *kvm)
4808 {
4809         /* Called with kvm->slots_lock held. */
4810
4811         int r = 0;
4812
4813         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4814
4815         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4816                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4817
4818         return r;
4819 }
4820
4821 static int allocate_vpid(void)
4822 {
4823         int vpid;
4824
4825         if (!enable_vpid)
4826                 return 0;
4827         spin_lock(&vmx_vpid_lock);
4828         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4829         if (vpid < VMX_NR_VPIDS)
4830                 __set_bit(vpid, vmx_vpid_bitmap);
4831         else
4832                 vpid = 0;
4833         spin_unlock(&vmx_vpid_lock);
4834         return vpid;
4835 }
4836
4837 static void free_vpid(int vpid)
4838 {
4839         if (!enable_vpid || vpid == 0)
4840                 return;
4841         spin_lock(&vmx_vpid_lock);
4842         __clear_bit(vpid, vmx_vpid_bitmap);
4843         spin_unlock(&vmx_vpid_lock);
4844 }
4845
4846 #define MSR_TYPE_R      1
4847 #define MSR_TYPE_W      2
4848 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4849                                                 u32 msr, int type)
4850 {
4851         int f = sizeof(unsigned long);
4852
4853         if (!cpu_has_vmx_msr_bitmap())
4854                 return;
4855
4856         /*
4857          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4858          * have the write-low and read-high bitmap offsets the wrong way round.
4859          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4860          */
4861         if (msr <= 0x1fff) {
4862                 if (type & MSR_TYPE_R)
4863                         /* read-low */
4864                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4865
4866                 if (type & MSR_TYPE_W)
4867                         /* write-low */
4868                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4869
4870         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4871                 msr &= 0x1fff;
4872                 if (type & MSR_TYPE_R)
4873                         /* read-high */
4874                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4875
4876                 if (type & MSR_TYPE_W)
4877                         /* write-high */
4878                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4879
4880         }
4881 }
4882
4883 /*
4884  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4885  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4886  */
4887 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4888                                                unsigned long *msr_bitmap_nested,
4889                                                u32 msr, int type)
4890 {
4891         int f = sizeof(unsigned long);
4892
4893         if (!cpu_has_vmx_msr_bitmap()) {
4894                 WARN_ON(1);
4895                 return;
4896         }
4897
4898         /*
4899          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4900          * have the write-low and read-high bitmap offsets the wrong way round.
4901          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4902          */
4903         if (msr <= 0x1fff) {
4904                 if (type & MSR_TYPE_R &&
4905                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4906                         /* read-low */
4907                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4908
4909                 if (type & MSR_TYPE_W &&
4910                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4911                         /* write-low */
4912                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4913
4914         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4915                 msr &= 0x1fff;
4916                 if (type & MSR_TYPE_R &&
4917                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4918                         /* read-high */
4919                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4920
4921                 if (type & MSR_TYPE_W &&
4922                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4923                         /* write-high */
4924                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4925
4926         }
4927 }
4928
4929 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4930 {
4931         if (!longmode_only)
4932                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4933                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4934         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4935                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4936 }
4937
4938 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4939 {
4940         if (apicv_active) {
4941                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4942                                 msr, type);
4943                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4944                                 msr, type);
4945         } else {
4946                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4947                                 msr, type);
4948                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4949                                 msr, type);
4950         }
4951 }
4952
4953 static bool vmx_get_enable_apicv(void)
4954 {
4955         return enable_apicv;
4956 }
4957
4958 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4959 {
4960         struct vcpu_vmx *vmx = to_vmx(vcpu);
4961         int max_irr;
4962         void *vapic_page;
4963         u16 status;
4964
4965         if (vmx->nested.pi_desc &&
4966             vmx->nested.pi_pending) {
4967                 vmx->nested.pi_pending = false;
4968                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4969                         return;
4970
4971                 max_irr = find_last_bit(
4972                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4973
4974                 if (max_irr == 256)
4975                         return;
4976
4977                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4978                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4979                 kunmap(vmx->nested.virtual_apic_page);
4980
4981                 status = vmcs_read16(GUEST_INTR_STATUS);
4982                 if ((u8)max_irr > ((u8)status & 0xff)) {
4983                         status &= ~0xff;
4984                         status |= (u8)max_irr;
4985                         vmcs_write16(GUEST_INTR_STATUS, status);
4986                 }
4987         }
4988 }
4989
4990 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4991 {
4992 #ifdef CONFIG_SMP
4993         if (vcpu->mode == IN_GUEST_MODE) {
4994                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4995
4996                 /*
4997                  * Currently, we don't support urgent interrupt,
4998                  * all interrupts are recognized as non-urgent
4999                  * interrupt, so we cannot post interrupts when
5000                  * 'SN' is set.
5001                  *
5002                  * If the vcpu is in guest mode, it means it is
5003                  * running instead of being scheduled out and
5004                  * waiting in the run queue, and that's the only
5005                  * case when 'SN' is set currently, warning if
5006                  * 'SN' is set.
5007                  */
5008                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
5009
5010                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
5011                                 POSTED_INTR_VECTOR);
5012                 return true;
5013         }
5014 #endif
5015         return false;
5016 }
5017
5018 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5019                                                 int vector)
5020 {
5021         struct vcpu_vmx *vmx = to_vmx(vcpu);
5022
5023         if (is_guest_mode(vcpu) &&
5024             vector == vmx->nested.posted_intr_nv) {
5025                 /* the PIR and ON have been set by L1. */
5026                 kvm_vcpu_trigger_posted_interrupt(vcpu);
5027                 /*
5028                  * If a posted intr is not recognized by hardware,
5029                  * we will accomplish it in the next vmentry.
5030                  */
5031                 vmx->nested.pi_pending = true;
5032                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5033                 return 0;
5034         }
5035         return -1;
5036 }
5037 /*
5038  * Send interrupt to vcpu via posted interrupt way.
5039  * 1. If target vcpu is running(non-root mode), send posted interrupt
5040  * notification to vcpu and hardware will sync PIR to vIRR atomically.
5041  * 2. If target vcpu isn't running(root mode), kick it to pick up the
5042  * interrupt from PIR in next vmentry.
5043  */
5044 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5045 {
5046         struct vcpu_vmx *vmx = to_vmx(vcpu);
5047         int r;
5048
5049         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5050         if (!r)
5051                 return;
5052
5053         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5054                 return;
5055
5056         /* If a previous notification has sent the IPI, nothing to do.  */
5057         if (pi_test_and_set_on(&vmx->pi_desc))
5058                 return;
5059
5060         if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
5061                 kvm_vcpu_kick(vcpu);
5062 }
5063
5064 /*
5065  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5066  * will not change in the lifetime of the guest.
5067  * Note that host-state that does change is set elsewhere. E.g., host-state
5068  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5069  */
5070 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5071 {
5072         u32 low32, high32;
5073         unsigned long tmpl;
5074         struct desc_ptr dt;
5075         unsigned long cr0, cr3, cr4;
5076
5077         cr0 = read_cr0();
5078         WARN_ON(cr0 & X86_CR0_TS);
5079         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5080
5081         /*
5082          * Save the most likely value for this task's CR3 in the VMCS.
5083          * We can't use __get_current_cr3_fast() because we're not atomic.
5084          */
5085         cr3 = __read_cr3();
5086         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
5087         vmx->host_state.vmcs_host_cr3 = cr3;
5088
5089         /* Save the most likely value for this task's CR4 in the VMCS. */
5090         cr4 = cr4_read_shadow();
5091         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5092         vmx->host_state.vmcs_host_cr4 = cr4;
5093
5094         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5095 #ifdef CONFIG_X86_64
5096         /*
5097          * Load null selectors, so we can avoid reloading them in
5098          * __vmx_load_host_state(), in case userspace uses the null selectors
5099          * too (the expected case).
5100          */
5101         vmcs_write16(HOST_DS_SELECTOR, 0);
5102         vmcs_write16(HOST_ES_SELECTOR, 0);
5103 #else
5104         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5105         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5106 #endif
5107         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5108         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5109
5110         native_store_idt(&dt);
5111         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5112         vmx->host_idt_base = dt.address;
5113
5114         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5115
5116         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5117         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5118         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5119         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5120
5121         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5122                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5123                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5124         }
5125 }
5126
5127 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5128 {
5129         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5130         if (enable_ept)
5131                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5132         if (is_guest_mode(&vmx->vcpu))
5133                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5134                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5135         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5136 }
5137
5138 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5139 {
5140         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5141
5142         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5143                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5144         /* Enable the preemption timer dynamically */
5145         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5146         return pin_based_exec_ctrl;
5147 }
5148
5149 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5150 {
5151         struct vcpu_vmx *vmx = to_vmx(vcpu);
5152
5153         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5154         if (cpu_has_secondary_exec_ctrls()) {
5155                 if (kvm_vcpu_apicv_active(vcpu))
5156                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5157                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5158                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5159                 else
5160                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5161                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5162                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5163         }
5164
5165         if (cpu_has_vmx_msr_bitmap())
5166                 vmx_set_msr_bitmap(vcpu);
5167 }
5168
5169 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5170 {
5171         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5172
5173         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5174                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5175
5176         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5177                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5178 #ifdef CONFIG_X86_64
5179                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5180                                 CPU_BASED_CR8_LOAD_EXITING;
5181 #endif
5182         }
5183         if (!enable_ept)
5184                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5185                                 CPU_BASED_CR3_LOAD_EXITING  |
5186                                 CPU_BASED_INVLPG_EXITING;
5187         return exec_control;
5188 }
5189
5190 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5191 {
5192         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5193         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5194                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5195         if (vmx->vpid == 0)
5196                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5197         if (!enable_ept) {
5198                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5199                 enable_unrestricted_guest = 0;
5200                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5201                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5202         }
5203         if (!enable_unrestricted_guest)
5204                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5205         if (!ple_gap)
5206                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5207         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5208                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5209                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5210         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5211         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5212            (handle_vmptrld).
5213            We can NOT enable shadow_vmcs here because we don't have yet
5214            a current VMCS12
5215         */
5216         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5217
5218         if (!enable_pml)
5219                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5220
5221         return exec_control;
5222 }
5223
5224 static void ept_set_mmio_spte_mask(void)
5225 {
5226         /*
5227          * EPT Misconfigurations can be generated if the value of bits 2:0
5228          * of an EPT paging-structure entry is 110b (write/execute).
5229          */
5230         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5231                                    VMX_EPT_MISCONFIG_WX_VALUE);
5232 }
5233
5234 #define VMX_XSS_EXIT_BITMAP 0
5235 /*
5236  * Sets up the vmcs for emulated real mode.
5237  */
5238 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5239 {
5240 #ifdef CONFIG_X86_64
5241         unsigned long a;
5242 #endif
5243         int i;
5244
5245         /* I/O */
5246         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5247         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5248
5249         if (enable_shadow_vmcs) {
5250                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5251                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5252         }
5253         if (cpu_has_vmx_msr_bitmap())
5254                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5255
5256         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5257
5258         /* Control */
5259         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5260         vmx->hv_deadline_tsc = -1;
5261
5262         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5263
5264         if (cpu_has_secondary_exec_ctrls()) {
5265                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5266                                 vmx_secondary_exec_control(vmx));
5267         }
5268
5269         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5270                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5271                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5272                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5273                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5274
5275                 vmcs_write16(GUEST_INTR_STATUS, 0);
5276
5277                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5278                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5279         }
5280
5281         if (ple_gap) {
5282                 vmcs_write32(PLE_GAP, ple_gap);
5283                 vmx->ple_window = ple_window;
5284                 vmx->ple_window_dirty = true;
5285         }
5286
5287         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5288         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5289         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5290
5291         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5292         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5293         vmx_set_constant_host_state(vmx);
5294 #ifdef CONFIG_X86_64
5295         rdmsrl(MSR_FS_BASE, a);
5296         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5297         rdmsrl(MSR_GS_BASE, a);
5298         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5299 #else
5300         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5301         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5302 #endif
5303
5304         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5305         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5306         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5307         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5308         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5309
5310         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5311                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5312
5313         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5314                 u32 index = vmx_msr_index[i];
5315                 u32 data_low, data_high;
5316                 int j = vmx->nmsrs;
5317
5318                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5319                         continue;
5320                 if (wrmsr_safe(index, data_low, data_high) < 0)
5321                         continue;
5322                 vmx->guest_msrs[j].index = i;
5323                 vmx->guest_msrs[j].data = 0;
5324                 vmx->guest_msrs[j].mask = -1ull;
5325                 ++vmx->nmsrs;
5326         }
5327
5328
5329         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5330
5331         /* 22.2.1, 20.8.1 */
5332         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5333
5334         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5335         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5336
5337         set_cr4_guest_host_mask(vmx);
5338
5339         if (vmx_xsaves_supported())
5340                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5341
5342         if (enable_pml) {
5343                 ASSERT(vmx->pml_pg);
5344                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5345                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5346         }
5347
5348         return 0;
5349 }
5350
5351 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5352 {
5353         struct vcpu_vmx *vmx = to_vmx(vcpu);
5354         struct msr_data apic_base_msr;
5355         u64 cr0;
5356
5357         vmx->rmode.vm86_active = 0;
5358
5359         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5360         kvm_set_cr8(vcpu, 0);
5361
5362         if (!init_event) {
5363                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5364                                      MSR_IA32_APICBASE_ENABLE;
5365                 if (kvm_vcpu_is_reset_bsp(vcpu))
5366                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5367                 apic_base_msr.host_initiated = true;
5368                 kvm_set_apic_base(vcpu, &apic_base_msr);
5369         }
5370
5371         vmx_segment_cache_clear(vmx);
5372
5373         seg_setup(VCPU_SREG_CS);
5374         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5375         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5376
5377         seg_setup(VCPU_SREG_DS);
5378         seg_setup(VCPU_SREG_ES);
5379         seg_setup(VCPU_SREG_FS);
5380         seg_setup(VCPU_SREG_GS);
5381         seg_setup(VCPU_SREG_SS);
5382
5383         vmcs_write16(GUEST_TR_SELECTOR, 0);
5384         vmcs_writel(GUEST_TR_BASE, 0);
5385         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5386         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5387
5388         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5389         vmcs_writel(GUEST_LDTR_BASE, 0);
5390         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5391         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5392
5393         if (!init_event) {
5394                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5395                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5396                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5397                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5398         }
5399
5400         vmcs_writel(GUEST_RFLAGS, 0x02);
5401         kvm_rip_write(vcpu, 0xfff0);
5402
5403         vmcs_writel(GUEST_GDTR_BASE, 0);
5404         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5405
5406         vmcs_writel(GUEST_IDTR_BASE, 0);
5407         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5408
5409         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5410         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5411         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5412
5413         setup_msrs(vmx);
5414
5415         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5416
5417         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5418                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5419                 if (cpu_need_tpr_shadow(vcpu))
5420                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5421                                      __pa(vcpu->arch.apic->regs));
5422                 vmcs_write32(TPR_THRESHOLD, 0);
5423         }
5424
5425         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5426
5427         if (kvm_vcpu_apicv_active(vcpu))
5428                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5429
5430         if (vmx->vpid != 0)
5431                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5432
5433         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5434         vmx->vcpu.arch.cr0 = cr0;
5435         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5436         vmx_set_cr4(vcpu, 0);
5437         vmx_set_efer(vcpu, 0);
5438
5439         update_exception_bitmap(vcpu);
5440
5441         vpid_sync_context(vmx->vpid);
5442 }
5443
5444 /*
5445  * In nested virtualization, check if L1 asked to exit on external interrupts.
5446  * For most existing hypervisors, this will always return true.
5447  */
5448 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5449 {
5450         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5451                 PIN_BASED_EXT_INTR_MASK;
5452 }
5453
5454 /*
5455  * In nested virtualization, check if L1 has set
5456  * VM_EXIT_ACK_INTR_ON_EXIT
5457  */
5458 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5459 {
5460         return get_vmcs12(vcpu)->vm_exit_controls &
5461                 VM_EXIT_ACK_INTR_ON_EXIT;
5462 }
5463
5464 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5465 {
5466         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5467                 PIN_BASED_NMI_EXITING;
5468 }
5469
5470 static void enable_irq_window(struct kvm_vcpu *vcpu)
5471 {
5472         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5473                       CPU_BASED_VIRTUAL_INTR_PENDING);
5474 }
5475
5476 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5477 {
5478         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5479                 enable_irq_window(vcpu);
5480                 return;
5481         }
5482
5483         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5484                       CPU_BASED_VIRTUAL_NMI_PENDING);
5485 }
5486
5487 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5488 {
5489         struct vcpu_vmx *vmx = to_vmx(vcpu);
5490         uint32_t intr;
5491         int irq = vcpu->arch.interrupt.nr;
5492
5493         trace_kvm_inj_virq(irq);
5494
5495         ++vcpu->stat.irq_injections;
5496         if (vmx->rmode.vm86_active) {
5497                 int inc_eip = 0;
5498                 if (vcpu->arch.interrupt.soft)
5499                         inc_eip = vcpu->arch.event_exit_inst_len;
5500                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5501                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5502                 return;
5503         }
5504         intr = irq | INTR_INFO_VALID_MASK;
5505         if (vcpu->arch.interrupt.soft) {
5506                 intr |= INTR_TYPE_SOFT_INTR;
5507                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5508                              vmx->vcpu.arch.event_exit_inst_len);
5509         } else
5510                 intr |= INTR_TYPE_EXT_INTR;
5511         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5512 }
5513
5514 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5515 {
5516         struct vcpu_vmx *vmx = to_vmx(vcpu);
5517
5518         ++vcpu->stat.nmi_injections;
5519         vmx->loaded_vmcs->nmi_known_unmasked = false;
5520
5521         if (vmx->rmode.vm86_active) {
5522                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5523                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5524                 return;
5525         }
5526
5527         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5528                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5529 }
5530
5531 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5532 {
5533         struct vcpu_vmx *vmx = to_vmx(vcpu);
5534         bool masked;
5535
5536         if (vmx->loaded_vmcs->nmi_known_unmasked)
5537                 return false;
5538         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5539         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5540         return masked;
5541 }
5542
5543 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5544 {
5545         struct vcpu_vmx *vmx = to_vmx(vcpu);
5546
5547         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5548         if (masked)
5549                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5550                               GUEST_INTR_STATE_NMI);
5551         else
5552                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5553                                 GUEST_INTR_STATE_NMI);
5554 }
5555
5556 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5557 {
5558         if (to_vmx(vcpu)->nested.nested_run_pending)
5559                 return 0;
5560
5561         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5562                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5563                    | GUEST_INTR_STATE_NMI));
5564 }
5565
5566 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5567 {
5568         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5569                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5570                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5571                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5572 }
5573
5574 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5575 {
5576         int ret;
5577
5578         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5579                                     PAGE_SIZE * 3);
5580         if (ret)
5581                 return ret;
5582         kvm->arch.tss_addr = addr;
5583         return init_rmode_tss(kvm);
5584 }
5585
5586 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5587 {
5588         switch (vec) {
5589         case BP_VECTOR:
5590                 /*
5591                  * Update instruction length as we may reinject the exception
5592                  * from user space while in guest debugging mode.
5593                  */
5594                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5595                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5596                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5597                         return false;
5598                 /* fall through */
5599         case DB_VECTOR:
5600                 if (vcpu->guest_debug &
5601                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5602                         return false;
5603                 /* fall through */
5604         case DE_VECTOR:
5605         case OF_VECTOR:
5606         case BR_VECTOR:
5607         case UD_VECTOR:
5608         case DF_VECTOR:
5609         case SS_VECTOR:
5610         case GP_VECTOR:
5611         case MF_VECTOR:
5612                 return true;
5613         break;
5614         }
5615         return false;
5616 }
5617
5618 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5619                                   int vec, u32 err_code)
5620 {
5621         /*
5622          * Instruction with address size override prefix opcode 0x67
5623          * Cause the #SS fault with 0 error code in VM86 mode.
5624          */
5625         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5626                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5627                         if (vcpu->arch.halt_request) {
5628                                 vcpu->arch.halt_request = 0;
5629                                 return kvm_vcpu_halt(vcpu);
5630                         }
5631                         return 1;
5632                 }
5633                 return 0;
5634         }
5635
5636         /*
5637          * Forward all other exceptions that are valid in real mode.
5638          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5639          *        the required debugging infrastructure rework.
5640          */
5641         kvm_queue_exception(vcpu, vec);
5642         return 1;
5643 }
5644
5645 /*
5646  * Trigger machine check on the host. We assume all the MSRs are already set up
5647  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5648  * We pass a fake environment to the machine check handler because we want
5649  * the guest to be always treated like user space, no matter what context
5650  * it used internally.
5651  */
5652 static void kvm_machine_check(void)
5653 {
5654 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5655         struct pt_regs regs = {
5656                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5657                 .flags = X86_EFLAGS_IF,
5658         };
5659
5660         do_machine_check(&regs, 0);
5661 #endif
5662 }
5663
5664 static int handle_machine_check(struct kvm_vcpu *vcpu)
5665 {
5666         /* already handled by vcpu_run */
5667         return 1;
5668 }
5669
5670 static int handle_exception(struct kvm_vcpu *vcpu)
5671 {
5672         struct vcpu_vmx *vmx = to_vmx(vcpu);
5673         struct kvm_run *kvm_run = vcpu->run;
5674         u32 intr_info, ex_no, error_code;
5675         unsigned long cr2, rip, dr6;
5676         u32 vect_info;
5677         enum emulation_result er;
5678
5679         vect_info = vmx->idt_vectoring_info;
5680         intr_info = vmx->exit_intr_info;
5681
5682         if (is_machine_check(intr_info))
5683                 return handle_machine_check(vcpu);
5684
5685         if (is_nmi(intr_info))
5686                 return 1;  /* already handled by vmx_vcpu_run() */
5687
5688         if (is_invalid_opcode(intr_info)) {
5689                 if (is_guest_mode(vcpu)) {
5690                         kvm_queue_exception(vcpu, UD_VECTOR);
5691                         return 1;
5692                 }
5693                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5694                 if (er != EMULATE_DONE)
5695                         kvm_queue_exception(vcpu, UD_VECTOR);
5696                 return 1;
5697         }
5698
5699         error_code = 0;
5700         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5701                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5702
5703         /*
5704          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5705          * MMIO, it is better to report an internal error.
5706          * See the comments in vmx_handle_exit.
5707          */
5708         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5709             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5710                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5711                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5712                 vcpu->run->internal.ndata = 3;
5713                 vcpu->run->internal.data[0] = vect_info;
5714                 vcpu->run->internal.data[1] = intr_info;
5715                 vcpu->run->internal.data[2] = error_code;
5716                 return 0;
5717         }
5718
5719         if (is_page_fault(intr_info)) {
5720                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5721                 /* EPT won't cause page fault directly */
5722                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
5723                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0,
5724                                 true);
5725         }
5726
5727         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5728
5729         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5730                 return handle_rmode_exception(vcpu, ex_no, error_code);
5731
5732         switch (ex_no) {
5733         case AC_VECTOR:
5734                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5735                 return 1;
5736         case DB_VECTOR:
5737                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5738                 if (!(vcpu->guest_debug &
5739                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5740                         vcpu->arch.dr6 &= ~15;
5741                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5742                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5743                                 skip_emulated_instruction(vcpu);
5744
5745                         kvm_queue_exception(vcpu, DB_VECTOR);
5746                         return 1;
5747                 }
5748                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5749                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5750                 /* fall through */
5751         case BP_VECTOR:
5752                 /*
5753                  * Update instruction length as we may reinject #BP from
5754                  * user space while in guest debugging mode. Reading it for
5755                  * #DB as well causes no harm, it is not used in that case.
5756                  */
5757                 vmx->vcpu.arch.event_exit_inst_len =
5758                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5759                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5760                 rip = kvm_rip_read(vcpu);
5761                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5762                 kvm_run->debug.arch.exception = ex_no;
5763                 break;
5764         default:
5765                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5766                 kvm_run->ex.exception = ex_no;
5767                 kvm_run->ex.error_code = error_code;
5768                 break;
5769         }
5770         return 0;
5771 }
5772
5773 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5774 {
5775         ++vcpu->stat.irq_exits;
5776         return 1;
5777 }
5778
5779 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5780 {
5781         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5782         return 0;
5783 }
5784
5785 static int handle_io(struct kvm_vcpu *vcpu)
5786 {
5787         unsigned long exit_qualification;
5788         int size, in, string, ret;
5789         unsigned port;
5790
5791         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5792         string = (exit_qualification & 16) != 0;
5793         in = (exit_qualification & 8) != 0;
5794
5795         ++vcpu->stat.io_exits;
5796
5797         if (string || in)
5798                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5799
5800         port = exit_qualification >> 16;
5801         size = (exit_qualification & 7) + 1;
5802
5803         ret = kvm_skip_emulated_instruction(vcpu);
5804
5805         /*
5806          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5807          * KVM_EXIT_DEBUG here.
5808          */
5809         return kvm_fast_pio_out(vcpu, size, port) && ret;
5810 }
5811
5812 static void
5813 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5814 {
5815         /*
5816          * Patch in the VMCALL instruction:
5817          */
5818         hypercall[0] = 0x0f;
5819         hypercall[1] = 0x01;
5820         hypercall[2] = 0xc1;
5821 }
5822
5823 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5824 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5825 {
5826         if (is_guest_mode(vcpu)) {
5827                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5828                 unsigned long orig_val = val;
5829
5830                 /*
5831                  * We get here when L2 changed cr0 in a way that did not change
5832                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5833                  * but did change L0 shadowed bits. So we first calculate the
5834                  * effective cr0 value that L1 would like to write into the
5835                  * hardware. It consists of the L2-owned bits from the new
5836                  * value combined with the L1-owned bits from L1's guest_cr0.
5837                  */
5838                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5839                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5840
5841                 if (!nested_guest_cr0_valid(vcpu, val))
5842                         return 1;
5843
5844                 if (kvm_set_cr0(vcpu, val))
5845                         return 1;
5846                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5847                 return 0;
5848         } else {
5849                 if (to_vmx(vcpu)->nested.vmxon &&
5850                     !nested_host_cr0_valid(vcpu, val))
5851                         return 1;
5852
5853                 return kvm_set_cr0(vcpu, val);
5854         }
5855 }
5856
5857 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5858 {
5859         if (is_guest_mode(vcpu)) {
5860                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5861                 unsigned long orig_val = val;
5862
5863                 /* analogously to handle_set_cr0 */
5864                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5865                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5866                 if (kvm_set_cr4(vcpu, val))
5867                         return 1;
5868                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5869                 return 0;
5870         } else
5871                 return kvm_set_cr4(vcpu, val);
5872 }
5873
5874 static int handle_cr(struct kvm_vcpu *vcpu)
5875 {
5876         unsigned long exit_qualification, val;
5877         int cr;
5878         int reg;
5879         int err;
5880         int ret;
5881
5882         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5883         cr = exit_qualification & 15;
5884         reg = (exit_qualification >> 8) & 15;
5885         switch ((exit_qualification >> 4) & 3) {
5886         case 0: /* mov to cr */
5887                 val = kvm_register_readl(vcpu, reg);
5888                 trace_kvm_cr_write(cr, val);
5889                 switch (cr) {
5890                 case 0:
5891                         err = handle_set_cr0(vcpu, val);
5892                         return kvm_complete_insn_gp(vcpu, err);
5893                 case 3:
5894                         err = kvm_set_cr3(vcpu, val);
5895                         return kvm_complete_insn_gp(vcpu, err);
5896                 case 4:
5897                         err = handle_set_cr4(vcpu, val);
5898                         return kvm_complete_insn_gp(vcpu, err);
5899                 case 8: {
5900                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5901                                 u8 cr8 = (u8)val;
5902                                 err = kvm_set_cr8(vcpu, cr8);
5903                                 ret = kvm_complete_insn_gp(vcpu, err);
5904                                 if (lapic_in_kernel(vcpu))
5905                                         return ret;
5906                                 if (cr8_prev <= cr8)
5907                                         return ret;
5908                                 /*
5909                                  * TODO: we might be squashing a
5910                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5911                                  * KVM_EXIT_DEBUG here.
5912                                  */
5913                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5914                                 return 0;
5915                         }
5916                 }
5917                 break;
5918         case 2: /* clts */
5919                 WARN_ONCE(1, "Guest should always own CR0.TS");
5920                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5921                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5922                 return kvm_skip_emulated_instruction(vcpu);
5923         case 1: /*mov from cr*/
5924                 switch (cr) {
5925                 case 3:
5926                         val = kvm_read_cr3(vcpu);
5927                         kvm_register_write(vcpu, reg, val);
5928                         trace_kvm_cr_read(cr, val);
5929                         return kvm_skip_emulated_instruction(vcpu);
5930                 case 8:
5931                         val = kvm_get_cr8(vcpu);
5932                         kvm_register_write(vcpu, reg, val);
5933                         trace_kvm_cr_read(cr, val);
5934                         return kvm_skip_emulated_instruction(vcpu);
5935                 }
5936                 break;
5937         case 3: /* lmsw */
5938                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5939                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5940                 kvm_lmsw(vcpu, val);
5941
5942                 return kvm_skip_emulated_instruction(vcpu);
5943         default:
5944                 break;
5945         }
5946         vcpu->run->exit_reason = 0;
5947         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5948                (int)(exit_qualification >> 4) & 3, cr);
5949         return 0;
5950 }
5951
5952 static int handle_dr(struct kvm_vcpu *vcpu)
5953 {
5954         unsigned long exit_qualification;
5955         int dr, dr7, reg;
5956
5957         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5958         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5959
5960         /* First, if DR does not exist, trigger UD */
5961         if (!kvm_require_dr(vcpu, dr))
5962                 return 1;
5963
5964         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5965         if (!kvm_require_cpl(vcpu, 0))
5966                 return 1;
5967         dr7 = vmcs_readl(GUEST_DR7);
5968         if (dr7 & DR7_GD) {
5969                 /*
5970                  * As the vm-exit takes precedence over the debug trap, we
5971                  * need to emulate the latter, either for the host or the
5972                  * guest debugging itself.
5973                  */
5974                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5975                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5976                         vcpu->run->debug.arch.dr7 = dr7;
5977                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5978                         vcpu->run->debug.arch.exception = DB_VECTOR;
5979                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5980                         return 0;
5981                 } else {
5982                         vcpu->arch.dr6 &= ~15;
5983                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5984                         kvm_queue_exception(vcpu, DB_VECTOR);
5985                         return 1;
5986                 }
5987         }
5988
5989         if (vcpu->guest_debug == 0) {
5990                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5991                                 CPU_BASED_MOV_DR_EXITING);
5992
5993                 /*
5994                  * No more DR vmexits; force a reload of the debug registers
5995                  * and reenter on this instruction.  The next vmexit will
5996                  * retrieve the full state of the debug registers.
5997                  */
5998                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5999                 return 1;
6000         }
6001
6002         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6003         if (exit_qualification & TYPE_MOV_FROM_DR) {
6004                 unsigned long val;
6005
6006                 if (kvm_get_dr(vcpu, dr, &val))
6007                         return 1;
6008                 kvm_register_write(vcpu, reg, val);
6009         } else
6010                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6011                         return 1;
6012
6013         return kvm_skip_emulated_instruction(vcpu);
6014 }
6015
6016 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6017 {
6018         return vcpu->arch.dr6;
6019 }
6020
6021 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6022 {
6023 }
6024
6025 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6026 {
6027         get_debugreg(vcpu->arch.db[0], 0);
6028         get_debugreg(vcpu->arch.db[1], 1);
6029         get_debugreg(vcpu->arch.db[2], 2);
6030         get_debugreg(vcpu->arch.db[3], 3);
6031         get_debugreg(vcpu->arch.dr6, 6);
6032         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6033
6034         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6035         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6036 }
6037
6038 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6039 {
6040         vmcs_writel(GUEST_DR7, val);
6041 }
6042
6043 static int handle_cpuid(struct kvm_vcpu *vcpu)
6044 {
6045         return kvm_emulate_cpuid(vcpu);
6046 }
6047
6048 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6049 {
6050         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6051         struct msr_data msr_info;
6052
6053         msr_info.index = ecx;
6054         msr_info.host_initiated = false;
6055         if (vmx_get_msr(vcpu, &msr_info)) {
6056                 trace_kvm_msr_read_ex(ecx);
6057                 kvm_inject_gp(vcpu, 0);
6058                 return 1;
6059         }
6060
6061         trace_kvm_msr_read(ecx, msr_info.data);
6062
6063         /* FIXME: handling of bits 32:63 of rax, rdx */
6064         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6065         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6066         return kvm_skip_emulated_instruction(vcpu);
6067 }
6068
6069 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6070 {
6071         struct msr_data msr;
6072         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6073         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6074                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6075
6076         msr.data = data;
6077         msr.index = ecx;
6078         msr.host_initiated = false;
6079         if (kvm_set_msr(vcpu, &msr) != 0) {
6080                 trace_kvm_msr_write_ex(ecx, data);
6081                 kvm_inject_gp(vcpu, 0);
6082                 return 1;
6083         }
6084
6085         trace_kvm_msr_write(ecx, data);
6086         return kvm_skip_emulated_instruction(vcpu);
6087 }
6088
6089 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6090 {
6091         kvm_apic_update_ppr(vcpu);
6092         return 1;
6093 }
6094
6095 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6096 {
6097         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6098                         CPU_BASED_VIRTUAL_INTR_PENDING);
6099
6100         kvm_make_request(KVM_REQ_EVENT, vcpu);
6101
6102         ++vcpu->stat.irq_window_exits;
6103         return 1;
6104 }
6105
6106 static int handle_halt(struct kvm_vcpu *vcpu)
6107 {
6108         return kvm_emulate_halt(vcpu);
6109 }
6110
6111 static int handle_vmcall(struct kvm_vcpu *vcpu)
6112 {
6113         return kvm_emulate_hypercall(vcpu);
6114 }
6115
6116 static int handle_invd(struct kvm_vcpu *vcpu)
6117 {
6118         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6119 }
6120
6121 static int handle_invlpg(struct kvm_vcpu *vcpu)
6122 {
6123         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6124
6125         kvm_mmu_invlpg(vcpu, exit_qualification);
6126         return kvm_skip_emulated_instruction(vcpu);
6127 }
6128
6129 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6130 {
6131         int err;
6132
6133         err = kvm_rdpmc(vcpu);
6134         return kvm_complete_insn_gp(vcpu, err);
6135 }
6136
6137 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6138 {
6139         return kvm_emulate_wbinvd(vcpu);
6140 }
6141
6142 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6143 {
6144         u64 new_bv = kvm_read_edx_eax(vcpu);
6145         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6146
6147         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6148                 return kvm_skip_emulated_instruction(vcpu);
6149         return 1;
6150 }
6151
6152 static int handle_xsaves(struct kvm_vcpu *vcpu)
6153 {
6154         kvm_skip_emulated_instruction(vcpu);
6155         WARN(1, "this should never happen\n");
6156         return 1;
6157 }
6158
6159 static int handle_xrstors(struct kvm_vcpu *vcpu)
6160 {
6161         kvm_skip_emulated_instruction(vcpu);
6162         WARN(1, "this should never happen\n");
6163         return 1;
6164 }
6165
6166 static int handle_apic_access(struct kvm_vcpu *vcpu)
6167 {
6168         if (likely(fasteoi)) {
6169                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6170                 int access_type, offset;
6171
6172                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6173                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6174                 /*
6175                  * Sane guest uses MOV to write EOI, with written value
6176                  * not cared. So make a short-circuit here by avoiding
6177                  * heavy instruction emulation.
6178                  */
6179                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6180                     (offset == APIC_EOI)) {
6181                         kvm_lapic_set_eoi(vcpu);
6182                         return kvm_skip_emulated_instruction(vcpu);
6183                 }
6184         }
6185         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6186 }
6187
6188 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6189 {
6190         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6191         int vector = exit_qualification & 0xff;
6192
6193         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6194         kvm_apic_set_eoi_accelerated(vcpu, vector);
6195         return 1;
6196 }
6197
6198 static int handle_apic_write(struct kvm_vcpu *vcpu)
6199 {
6200         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6201         u32 offset = exit_qualification & 0xfff;
6202
6203         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6204         kvm_apic_write_nodecode(vcpu, offset);
6205         return 1;
6206 }
6207
6208 static int handle_task_switch(struct kvm_vcpu *vcpu)
6209 {
6210         struct vcpu_vmx *vmx = to_vmx(vcpu);
6211         unsigned long exit_qualification;
6212         bool has_error_code = false;
6213         u32 error_code = 0;
6214         u16 tss_selector;
6215         int reason, type, idt_v, idt_index;
6216
6217         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6218         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6219         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6220
6221         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6222
6223         reason = (u32)exit_qualification >> 30;
6224         if (reason == TASK_SWITCH_GATE && idt_v) {
6225                 switch (type) {
6226                 case INTR_TYPE_NMI_INTR:
6227                         vcpu->arch.nmi_injected = false;
6228                         vmx_set_nmi_mask(vcpu, true);
6229                         break;
6230                 case INTR_TYPE_EXT_INTR:
6231                 case INTR_TYPE_SOFT_INTR:
6232                         kvm_clear_interrupt_queue(vcpu);
6233                         break;
6234                 case INTR_TYPE_HARD_EXCEPTION:
6235                         if (vmx->idt_vectoring_info &
6236                             VECTORING_INFO_DELIVER_CODE_MASK) {
6237                                 has_error_code = true;
6238                                 error_code =
6239                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6240                         }
6241                         /* fall through */
6242                 case INTR_TYPE_SOFT_EXCEPTION:
6243                         kvm_clear_exception_queue(vcpu);
6244                         break;
6245                 default:
6246                         break;
6247                 }
6248         }
6249         tss_selector = exit_qualification;
6250
6251         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6252                        type != INTR_TYPE_EXT_INTR &&
6253                        type != INTR_TYPE_NMI_INTR))
6254                 skip_emulated_instruction(vcpu);
6255
6256         if (kvm_task_switch(vcpu, tss_selector,
6257                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6258                             has_error_code, error_code) == EMULATE_FAIL) {
6259                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6260                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6261                 vcpu->run->internal.ndata = 0;
6262                 return 0;
6263         }
6264
6265         /*
6266          * TODO: What about debug traps on tss switch?
6267          *       Are we supposed to inject them and update dr6?
6268          */
6269
6270         return 1;
6271 }
6272
6273 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6274 {
6275         unsigned long exit_qualification;
6276         gpa_t gpa;
6277         u32 error_code;
6278
6279         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6280
6281         /*
6282          * EPT violation happened while executing iret from NMI,
6283          * "blocked by NMI" bit has to be set before next VM entry.
6284          * There are errata that may cause this bit to not be set:
6285          * AAK134, BY25.
6286          */
6287         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6288                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6289                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6290
6291         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6292         trace_kvm_page_fault(gpa, exit_qualification);
6293
6294         /* Is it a read fault? */
6295         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6296                      ? PFERR_USER_MASK : 0;
6297         /* Is it a write fault? */
6298         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6299                       ? PFERR_WRITE_MASK : 0;
6300         /* Is it a fetch fault? */
6301         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6302                       ? PFERR_FETCH_MASK : 0;
6303         /* ept page table entry is present? */
6304         error_code |= (exit_qualification &
6305                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6306                         EPT_VIOLATION_EXECUTABLE))
6307                       ? PFERR_PRESENT_MASK : 0;
6308
6309         vcpu->arch.gpa_available = true;
6310         vcpu->arch.exit_qualification = exit_qualification;
6311
6312         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6313 }
6314
6315 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6316 {
6317         int ret;
6318         gpa_t gpa;
6319
6320         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6321         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6322                 trace_kvm_fast_mmio(gpa);
6323                 return kvm_skip_emulated_instruction(vcpu);
6324         }
6325
6326         ret = handle_mmio_page_fault(vcpu, gpa, true);
6327         vcpu->arch.gpa_available = true;
6328         if (likely(ret == RET_MMIO_PF_EMULATE))
6329                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6330                                               EMULATE_DONE;
6331
6332         if (unlikely(ret == RET_MMIO_PF_INVALID))
6333                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6334
6335         if (unlikely(ret == RET_MMIO_PF_RETRY))
6336                 return 1;
6337
6338         /* It is the real ept misconfig */
6339         WARN_ON(1);
6340
6341         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6342         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6343
6344         return 0;
6345 }
6346
6347 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6348 {
6349         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6350                         CPU_BASED_VIRTUAL_NMI_PENDING);
6351         ++vcpu->stat.nmi_window_exits;
6352         kvm_make_request(KVM_REQ_EVENT, vcpu);
6353
6354         return 1;
6355 }
6356
6357 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6358 {
6359         struct vcpu_vmx *vmx = to_vmx(vcpu);
6360         enum emulation_result err = EMULATE_DONE;
6361         int ret = 1;
6362         u32 cpu_exec_ctrl;
6363         bool intr_window_requested;
6364         unsigned count = 130;
6365
6366         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6367         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6368
6369         while (vmx->emulation_required && count-- != 0) {
6370                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6371                         return handle_interrupt_window(&vmx->vcpu);
6372
6373                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
6374                         return 1;
6375
6376                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6377
6378                 if (err == EMULATE_USER_EXIT) {
6379                         ++vcpu->stat.mmio_exits;
6380                         ret = 0;
6381                         goto out;
6382                 }
6383
6384                 if (err != EMULATE_DONE) {
6385                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6386                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6387                         vcpu->run->internal.ndata = 0;
6388                         return 0;
6389                 }
6390
6391                 if (vcpu->arch.halt_request) {
6392                         vcpu->arch.halt_request = 0;
6393                         ret = kvm_vcpu_halt(vcpu);
6394                         goto out;
6395                 }
6396
6397                 if (signal_pending(current))
6398                         goto out;
6399                 if (need_resched())
6400                         schedule();
6401         }
6402
6403 out:
6404         return ret;
6405 }
6406
6407 static int __grow_ple_window(int val)
6408 {
6409         if (ple_window_grow < 1)
6410                 return ple_window;
6411
6412         val = min(val, ple_window_actual_max);
6413
6414         if (ple_window_grow < ple_window)
6415                 val *= ple_window_grow;
6416         else
6417                 val += ple_window_grow;
6418
6419         return val;
6420 }
6421
6422 static int __shrink_ple_window(int val, int modifier, int minimum)
6423 {
6424         if (modifier < 1)
6425                 return ple_window;
6426
6427         if (modifier < ple_window)
6428                 val /= modifier;
6429         else
6430                 val -= modifier;
6431
6432         return max(val, minimum);
6433 }
6434
6435 static void grow_ple_window(struct kvm_vcpu *vcpu)
6436 {
6437         struct vcpu_vmx *vmx = to_vmx(vcpu);
6438         int old = vmx->ple_window;
6439
6440         vmx->ple_window = __grow_ple_window(old);
6441
6442         if (vmx->ple_window != old)
6443                 vmx->ple_window_dirty = true;
6444
6445         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6446 }
6447
6448 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6449 {
6450         struct vcpu_vmx *vmx = to_vmx(vcpu);
6451         int old = vmx->ple_window;
6452
6453         vmx->ple_window = __shrink_ple_window(old,
6454                                               ple_window_shrink, ple_window);
6455
6456         if (vmx->ple_window != old)
6457                 vmx->ple_window_dirty = true;
6458
6459         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6460 }
6461
6462 /*
6463  * ple_window_actual_max is computed to be one grow_ple_window() below
6464  * ple_window_max. (See __grow_ple_window for the reason.)
6465  * This prevents overflows, because ple_window_max is int.
6466  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6467  * this process.
6468  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6469  */
6470 static void update_ple_window_actual_max(void)
6471 {
6472         ple_window_actual_max =
6473                         __shrink_ple_window(max(ple_window_max, ple_window),
6474                                             ple_window_grow, INT_MIN);
6475 }
6476
6477 /*
6478  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6479  */
6480 static void wakeup_handler(void)
6481 {
6482         struct kvm_vcpu *vcpu;
6483         int cpu = smp_processor_id();
6484
6485         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6486         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6487                         blocked_vcpu_list) {
6488                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6489
6490                 if (pi_test_on(pi_desc) == 1)
6491                         kvm_vcpu_kick(vcpu);
6492         }
6493         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6494 }
6495
6496 void vmx_enable_tdp(void)
6497 {
6498         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6499                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6500                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6501                 0ull, VMX_EPT_EXECUTABLE_MASK,
6502                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6503                 VMX_EPT_RWX_MASK);
6504
6505         ept_set_mmio_spte_mask();
6506         kvm_enable_tdp();
6507 }
6508
6509 static __init int hardware_setup(void)
6510 {
6511         int r = -ENOMEM, i, msr;
6512
6513         rdmsrl_safe(MSR_EFER, &host_efer);
6514
6515         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6516                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6517
6518         for (i = 0; i < VMX_BITMAP_NR; i++) {
6519                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6520                 if (!vmx_bitmap[i])
6521                         goto out;
6522         }
6523
6524         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6525         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6526         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6527
6528         /*
6529          * Allow direct access to the PC debug port (it is often used for I/O
6530          * delays, but the vmexits simply slow things down).
6531          */
6532         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6533         clear_bit(0x80, vmx_io_bitmap_a);
6534
6535         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6536
6537         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6538         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6539
6540         if (setup_vmcs_config(&vmcs_config) < 0) {
6541                 r = -EIO;
6542                 goto out;
6543         }
6544
6545         if (boot_cpu_has(X86_FEATURE_NX))
6546                 kvm_enable_efer_bits(EFER_NX);
6547
6548         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6549                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6550                 enable_vpid = 0;
6551
6552         if (!cpu_has_vmx_shadow_vmcs())
6553                 enable_shadow_vmcs = 0;
6554         if (enable_shadow_vmcs)
6555                 init_vmcs_shadow_fields();
6556
6557         if (!cpu_has_vmx_ept() ||
6558             !cpu_has_vmx_ept_4levels()) {
6559                 enable_ept = 0;
6560                 enable_unrestricted_guest = 0;
6561                 enable_ept_ad_bits = 0;
6562         }
6563
6564         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
6565                 enable_ept_ad_bits = 0;
6566
6567         if (!cpu_has_vmx_unrestricted_guest())
6568                 enable_unrestricted_guest = 0;
6569
6570         if (!cpu_has_vmx_flexpriority())
6571                 flexpriority_enabled = 0;
6572
6573         /*
6574          * set_apic_access_page_addr() is used to reload apic access
6575          * page upon invalidation.  No need to do anything if not
6576          * using the APIC_ACCESS_ADDR VMCS field.
6577          */
6578         if (!flexpriority_enabled)
6579                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6580
6581         if (!cpu_has_vmx_tpr_shadow())
6582                 kvm_x86_ops->update_cr8_intercept = NULL;
6583
6584         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6585                 kvm_disable_largepages();
6586
6587         if (!cpu_has_vmx_ple())
6588                 ple_gap = 0;
6589
6590         if (!cpu_has_vmx_apicv()) {
6591                 enable_apicv = 0;
6592                 kvm_x86_ops->sync_pir_to_irr = NULL;
6593         }
6594
6595         if (cpu_has_vmx_tsc_scaling()) {
6596                 kvm_has_tsc_control = true;
6597                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6598                 kvm_tsc_scaling_ratio_frac_bits = 48;
6599         }
6600
6601         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6602         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6603         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6604         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6605         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6606         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6607
6608         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6609                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6610         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6611                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6612         memcpy(vmx_msr_bitmap_legacy_x2apic,
6613                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6614         memcpy(vmx_msr_bitmap_longmode_x2apic,
6615                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6616
6617         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6618
6619         for (msr = 0x800; msr <= 0x8ff; msr++) {
6620                 if (msr == 0x839 /* TMCCT */)
6621                         continue;
6622                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6623         }
6624
6625         /*
6626          * TPR reads and writes can be virtualized even if virtual interrupt
6627          * delivery is not in use.
6628          */
6629         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6630         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6631
6632         /* EOI */
6633         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6634         /* SELF-IPI */
6635         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6636
6637         if (enable_ept)
6638                 vmx_enable_tdp();
6639         else
6640                 kvm_disable_tdp();
6641
6642         update_ple_window_actual_max();
6643
6644         /*
6645          * Only enable PML when hardware supports PML feature, and both EPT
6646          * and EPT A/D bit features are enabled -- PML depends on them to work.
6647          */
6648         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6649                 enable_pml = 0;
6650
6651         if (!enable_pml) {
6652                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6653                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6654                 kvm_x86_ops->flush_log_dirty = NULL;
6655                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6656         }
6657
6658         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6659                 u64 vmx_msr;
6660
6661                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6662                 cpu_preemption_timer_multi =
6663                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6664         } else {
6665                 kvm_x86_ops->set_hv_timer = NULL;
6666                 kvm_x86_ops->cancel_hv_timer = NULL;
6667         }
6668
6669         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6670
6671         kvm_mce_cap_supported |= MCG_LMCE_P;
6672
6673         return alloc_kvm_area();
6674
6675 out:
6676         for (i = 0; i < VMX_BITMAP_NR; i++)
6677                 free_page((unsigned long)vmx_bitmap[i]);
6678
6679     return r;
6680 }
6681
6682 static __exit void hardware_unsetup(void)
6683 {
6684         int i;
6685
6686         for (i = 0; i < VMX_BITMAP_NR; i++)
6687                 free_page((unsigned long)vmx_bitmap[i]);
6688
6689         free_kvm_area();
6690 }
6691
6692 /*
6693  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6694  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6695  */
6696 static int handle_pause(struct kvm_vcpu *vcpu)
6697 {
6698         if (ple_gap)
6699                 grow_ple_window(vcpu);
6700
6701         kvm_vcpu_on_spin(vcpu);
6702         return kvm_skip_emulated_instruction(vcpu);
6703 }
6704
6705 static int handle_nop(struct kvm_vcpu *vcpu)
6706 {
6707         return kvm_skip_emulated_instruction(vcpu);
6708 }
6709
6710 static int handle_mwait(struct kvm_vcpu *vcpu)
6711 {
6712         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6713         return handle_nop(vcpu);
6714 }
6715
6716 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6717 {
6718         return 1;
6719 }
6720
6721 static int handle_monitor(struct kvm_vcpu *vcpu)
6722 {
6723         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6724         return handle_nop(vcpu);
6725 }
6726
6727 /*
6728  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6729  * We could reuse a single VMCS for all the L2 guests, but we also want the
6730  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6731  * allows keeping them loaded on the processor, and in the future will allow
6732  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6733  * every entry if they never change.
6734  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6735  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6736  *
6737  * The following functions allocate and free a vmcs02 in this pool.
6738  */
6739
6740 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6741 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6742 {
6743         struct vmcs02_list *item;
6744         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6745                 if (item->vmptr == vmx->nested.current_vmptr) {
6746                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6747                         return &item->vmcs02;
6748                 }
6749
6750         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6751                 /* Recycle the least recently used VMCS. */
6752                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6753                                        struct vmcs02_list, list);
6754                 item->vmptr = vmx->nested.current_vmptr;
6755                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6756                 return &item->vmcs02;
6757         }
6758
6759         /* Create a new VMCS */
6760         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6761         if (!item)
6762                 return NULL;
6763         item->vmcs02.vmcs = alloc_vmcs();
6764         item->vmcs02.shadow_vmcs = NULL;
6765         if (!item->vmcs02.vmcs) {
6766                 kfree(item);
6767                 return NULL;
6768         }
6769         loaded_vmcs_init(&item->vmcs02);
6770         item->vmptr = vmx->nested.current_vmptr;
6771         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6772         vmx->nested.vmcs02_num++;
6773         return &item->vmcs02;
6774 }
6775
6776 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6777 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6778 {
6779         struct vmcs02_list *item;
6780         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6781                 if (item->vmptr == vmptr) {
6782                         free_loaded_vmcs(&item->vmcs02);
6783                         list_del(&item->list);
6784                         kfree(item);
6785                         vmx->nested.vmcs02_num--;
6786                         return;
6787                 }
6788 }
6789
6790 /*
6791  * Free all VMCSs saved for this vcpu, except the one pointed by
6792  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6793  * must be &vmx->vmcs01.
6794  */
6795 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6796 {
6797         struct vmcs02_list *item, *n;
6798
6799         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6800         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6801                 /*
6802                  * Something will leak if the above WARN triggers.  Better than
6803                  * a use-after-free.
6804                  */
6805                 if (vmx->loaded_vmcs == &item->vmcs02)
6806                         continue;
6807
6808                 free_loaded_vmcs(&item->vmcs02);
6809                 list_del(&item->list);
6810                 kfree(item);
6811                 vmx->nested.vmcs02_num--;
6812         }
6813 }
6814
6815 /*
6816  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6817  * set the success or error code of an emulated VMX instruction, as specified
6818  * by Vol 2B, VMX Instruction Reference, "Conventions".
6819  */
6820 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6821 {
6822         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6823                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6824                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6825 }
6826
6827 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6828 {
6829         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6830                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6831                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6832                         | X86_EFLAGS_CF);
6833 }
6834
6835 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6836                                         u32 vm_instruction_error)
6837 {
6838         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6839                 /*
6840                  * failValid writes the error number to the current VMCS, which
6841                  * can't be done there isn't a current VMCS.
6842                  */
6843                 nested_vmx_failInvalid(vcpu);
6844                 return;
6845         }
6846         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6847                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6848                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6849                         | X86_EFLAGS_ZF);
6850         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6851         /*
6852          * We don't need to force a shadow sync because
6853          * VM_INSTRUCTION_ERROR is not shadowed
6854          */
6855 }
6856
6857 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6858 {
6859         /* TODO: not to reset guest simply here. */
6860         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6861         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6862 }
6863
6864 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6865 {
6866         struct vcpu_vmx *vmx =
6867                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6868
6869         vmx->nested.preemption_timer_expired = true;
6870         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6871         kvm_vcpu_kick(&vmx->vcpu);
6872
6873         return HRTIMER_NORESTART;
6874 }
6875
6876 /*
6877  * Decode the memory-address operand of a vmx instruction, as recorded on an
6878  * exit caused by such an instruction (run by a guest hypervisor).
6879  * On success, returns 0. When the operand is invalid, returns 1 and throws
6880  * #UD or #GP.
6881  */
6882 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6883                                  unsigned long exit_qualification,
6884                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6885 {
6886         gva_t off;
6887         bool exn;
6888         struct kvm_segment s;
6889
6890         /*
6891          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6892          * Execution", on an exit, vmx_instruction_info holds most of the
6893          * addressing components of the operand. Only the displacement part
6894          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6895          * For how an actual address is calculated from all these components,
6896          * refer to Vol. 1, "Operand Addressing".
6897          */
6898         int  scaling = vmx_instruction_info & 3;
6899         int  addr_size = (vmx_instruction_info >> 7) & 7;
6900         bool is_reg = vmx_instruction_info & (1u << 10);
6901         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6902         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6903         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6904         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6905         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6906
6907         if (is_reg) {
6908                 kvm_queue_exception(vcpu, UD_VECTOR);
6909                 return 1;
6910         }
6911
6912         /* Addr = segment_base + offset */
6913         /* offset = base + [index * scale] + displacement */
6914         off = exit_qualification; /* holds the displacement */
6915         if (base_is_valid)
6916                 off += kvm_register_read(vcpu, base_reg);
6917         if (index_is_valid)
6918                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6919         vmx_get_segment(vcpu, &s, seg_reg);
6920         *ret = s.base + off;
6921
6922         if (addr_size == 1) /* 32 bit */
6923                 *ret &= 0xffffffff;
6924
6925         /* Checks for #GP/#SS exceptions. */
6926         exn = false;
6927         if (is_long_mode(vcpu)) {
6928                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6929                  * non-canonical form. This is the only check on the memory
6930                  * destination for long mode!
6931                  */
6932                 exn = is_noncanonical_address(*ret);
6933         } else if (is_protmode(vcpu)) {
6934                 /* Protected mode: apply checks for segment validity in the
6935                  * following order:
6936                  * - segment type check (#GP(0) may be thrown)
6937                  * - usability check (#GP(0)/#SS(0))
6938                  * - limit check (#GP(0)/#SS(0))
6939                  */
6940                 if (wr)
6941                         /* #GP(0) if the destination operand is located in a
6942                          * read-only data segment or any code segment.
6943                          */
6944                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6945                 else
6946                         /* #GP(0) if the source operand is located in an
6947                          * execute-only code segment
6948                          */
6949                         exn = ((s.type & 0xa) == 8);
6950                 if (exn) {
6951                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6952                         return 1;
6953                 }
6954                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6955                  */
6956                 exn = (s.unusable != 0);
6957                 /* Protected mode: #GP(0)/#SS(0) if the memory
6958                  * operand is outside the segment limit.
6959                  */
6960                 exn = exn || (off + sizeof(u64) > s.limit);
6961         }
6962         if (exn) {
6963                 kvm_queue_exception_e(vcpu,
6964                                       seg_reg == VCPU_SREG_SS ?
6965                                                 SS_VECTOR : GP_VECTOR,
6966                                       0);
6967                 return 1;
6968         }
6969
6970         return 0;
6971 }
6972
6973 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
6974 {
6975         gva_t gva;
6976         struct x86_exception e;
6977
6978         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6979                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6980                 return 1;
6981
6982         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
6983                                 sizeof(*vmpointer), &e)) {
6984                 kvm_inject_page_fault(vcpu, &e);
6985                 return 1;
6986         }
6987
6988         return 0;
6989 }
6990
6991 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
6992 {
6993         struct vcpu_vmx *vmx = to_vmx(vcpu);
6994         struct vmcs *shadow_vmcs;
6995
6996         if (cpu_has_vmx_msr_bitmap()) {
6997                 vmx->nested.msr_bitmap =
6998                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6999                 if (!vmx->nested.msr_bitmap)
7000                         goto out_msr_bitmap;
7001         }
7002
7003         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7004         if (!vmx->nested.cached_vmcs12)
7005                 goto out_cached_vmcs12;
7006
7007         if (enable_shadow_vmcs) {
7008                 shadow_vmcs = alloc_vmcs();
7009                 if (!shadow_vmcs)
7010                         goto out_shadow_vmcs;
7011                 /* mark vmcs as shadow */
7012                 shadow_vmcs->revision_id |= (1u << 31);
7013                 /* init shadow vmcs */
7014                 vmcs_clear(shadow_vmcs);
7015                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7016         }
7017
7018         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7019         vmx->nested.vmcs02_num = 0;
7020
7021         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7022                      HRTIMER_MODE_REL_PINNED);
7023         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7024
7025         vmx->nested.vmxon = true;
7026         return 0;
7027
7028 out_shadow_vmcs:
7029         kfree(vmx->nested.cached_vmcs12);
7030
7031 out_cached_vmcs12:
7032         free_page((unsigned long)vmx->nested.msr_bitmap);
7033
7034 out_msr_bitmap:
7035         return -ENOMEM;
7036 }
7037
7038 /*
7039  * Emulate the VMXON instruction.
7040  * Currently, we just remember that VMX is active, and do not save or even
7041  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7042  * do not currently need to store anything in that guest-allocated memory
7043  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7044  * argument is different from the VMXON pointer (which the spec says they do).
7045  */
7046 static int handle_vmon(struct kvm_vcpu *vcpu)
7047 {
7048         int ret;
7049         gpa_t vmptr;
7050         struct page *page;
7051         struct vcpu_vmx *vmx = to_vmx(vcpu);
7052         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7053                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7054
7055         /*
7056          * The Intel VMX Instruction Reference lists a bunch of bits that are
7057          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7058          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7059          * Otherwise, we should fail with #UD.  But most faulting conditions
7060          * have already been checked by hardware, prior to the VM-exit for
7061          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
7062          * that bit set to 1 in non-root mode.
7063          */
7064         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7065                 kvm_queue_exception(vcpu, UD_VECTOR);
7066                 return 1;
7067         }
7068
7069         if (vmx->nested.vmxon) {
7070                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7071                 return kvm_skip_emulated_instruction(vcpu);
7072         }
7073
7074         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7075                         != VMXON_NEEDED_FEATURES) {
7076                 kvm_inject_gp(vcpu, 0);
7077                 return 1;
7078         }
7079
7080         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7081                 return 1;
7082
7083         /*
7084          * SDM 3: 24.11.5
7085          * The first 4 bytes of VMXON region contain the supported
7086          * VMCS revision identifier
7087          *
7088          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7089          * which replaces physical address width with 32
7090          */
7091         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7092                 nested_vmx_failInvalid(vcpu);
7093                 return kvm_skip_emulated_instruction(vcpu);
7094         }
7095
7096         page = nested_get_page(vcpu, vmptr);
7097         if (page == NULL) {
7098                 nested_vmx_failInvalid(vcpu);
7099                 return kvm_skip_emulated_instruction(vcpu);
7100         }
7101         if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7102                 kunmap(page);
7103                 nested_release_page_clean(page);
7104                 nested_vmx_failInvalid(vcpu);
7105                 return kvm_skip_emulated_instruction(vcpu);
7106         }
7107         kunmap(page);
7108         nested_release_page_clean(page);
7109
7110         vmx->nested.vmxon_ptr = vmptr;
7111         ret = enter_vmx_operation(vcpu);
7112         if (ret)
7113                 return ret;
7114
7115         nested_vmx_succeed(vcpu);
7116         return kvm_skip_emulated_instruction(vcpu);
7117 }
7118
7119 /*
7120  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7121  * for running VMX instructions (except VMXON, whose prerequisites are
7122  * slightly different). It also specifies what exception to inject otherwise.
7123  * Note that many of these exceptions have priority over VM exits, so they
7124  * don't have to be checked again here.
7125  */
7126 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7127 {
7128         if (!to_vmx(vcpu)->nested.vmxon) {
7129                 kvm_queue_exception(vcpu, UD_VECTOR);
7130                 return 0;
7131         }
7132         return 1;
7133 }
7134
7135 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7136 {
7137         if (vmx->nested.current_vmptr == -1ull)
7138                 return;
7139
7140         /* current_vmptr and current_vmcs12 are always set/reset together */
7141         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7142                 return;
7143
7144         if (enable_shadow_vmcs) {
7145                 /* copy to memory all shadowed fields in case
7146                    they were modified */
7147                 copy_shadow_to_vmcs12(vmx);
7148                 vmx->nested.sync_shadow_vmcs = false;
7149                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7150                                 SECONDARY_EXEC_SHADOW_VMCS);
7151                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7152         }
7153         vmx->nested.posted_intr_nv = -1;
7154
7155         /* Flush VMCS12 to guest memory */
7156         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7157                VMCS12_SIZE);
7158
7159         kunmap(vmx->nested.current_vmcs12_page);
7160         nested_release_page(vmx->nested.current_vmcs12_page);
7161         vmx->nested.current_vmptr = -1ull;
7162         vmx->nested.current_vmcs12 = NULL;
7163 }
7164
7165 /*
7166  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7167  * just stops using VMX.
7168  */
7169 static void free_nested(struct vcpu_vmx *vmx)
7170 {
7171         if (!vmx->nested.vmxon)
7172                 return;
7173
7174         vmx->nested.vmxon = false;
7175         free_vpid(vmx->nested.vpid02);
7176         nested_release_vmcs12(vmx);
7177         if (vmx->nested.msr_bitmap) {
7178                 free_page((unsigned long)vmx->nested.msr_bitmap);
7179                 vmx->nested.msr_bitmap = NULL;
7180         }
7181         if (enable_shadow_vmcs) {
7182                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7183                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7184                 vmx->vmcs01.shadow_vmcs = NULL;
7185         }
7186         kfree(vmx->nested.cached_vmcs12);
7187         /* Unpin physical memory we referred to in current vmcs02 */
7188         if (vmx->nested.apic_access_page) {
7189                 nested_release_page(vmx->nested.apic_access_page);
7190                 vmx->nested.apic_access_page = NULL;
7191         }
7192         if (vmx->nested.virtual_apic_page) {
7193                 nested_release_page(vmx->nested.virtual_apic_page);
7194                 vmx->nested.virtual_apic_page = NULL;
7195         }
7196         if (vmx->nested.pi_desc_page) {
7197                 kunmap(vmx->nested.pi_desc_page);
7198                 nested_release_page(vmx->nested.pi_desc_page);
7199                 vmx->nested.pi_desc_page = NULL;
7200                 vmx->nested.pi_desc = NULL;
7201         }
7202
7203         nested_free_all_saved_vmcss(vmx);
7204 }
7205
7206 /* Emulate the VMXOFF instruction */
7207 static int handle_vmoff(struct kvm_vcpu *vcpu)
7208 {
7209         if (!nested_vmx_check_permission(vcpu))
7210                 return 1;
7211         free_nested(to_vmx(vcpu));
7212         nested_vmx_succeed(vcpu);
7213         return kvm_skip_emulated_instruction(vcpu);
7214 }
7215
7216 /* Emulate the VMCLEAR instruction */
7217 static int handle_vmclear(struct kvm_vcpu *vcpu)
7218 {
7219         struct vcpu_vmx *vmx = to_vmx(vcpu);
7220         u32 zero = 0;
7221         gpa_t vmptr;
7222
7223         if (!nested_vmx_check_permission(vcpu))
7224                 return 1;
7225
7226         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7227                 return 1;
7228
7229         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7230                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7231                 return kvm_skip_emulated_instruction(vcpu);
7232         }
7233
7234         if (vmptr == vmx->nested.vmxon_ptr) {
7235                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7236                 return kvm_skip_emulated_instruction(vcpu);
7237         }
7238
7239         if (vmptr == vmx->nested.current_vmptr)
7240                 nested_release_vmcs12(vmx);
7241
7242         kvm_vcpu_write_guest(vcpu,
7243                         vmptr + offsetof(struct vmcs12, launch_state),
7244                         &zero, sizeof(zero));
7245
7246         nested_free_vmcs02(vmx, vmptr);
7247
7248         nested_vmx_succeed(vcpu);
7249         return kvm_skip_emulated_instruction(vcpu);
7250 }
7251
7252 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7253
7254 /* Emulate the VMLAUNCH instruction */
7255 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7256 {
7257         return nested_vmx_run(vcpu, true);
7258 }
7259
7260 /* Emulate the VMRESUME instruction */
7261 static int handle_vmresume(struct kvm_vcpu *vcpu)
7262 {
7263
7264         return nested_vmx_run(vcpu, false);
7265 }
7266
7267 /*
7268  * Read a vmcs12 field. Since these can have varying lengths and we return
7269  * one type, we chose the biggest type (u64) and zero-extend the return value
7270  * to that size. Note that the caller, handle_vmread, might need to use only
7271  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7272  * 64-bit fields are to be returned).
7273  */
7274 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7275                                   unsigned long field, u64 *ret)
7276 {
7277         short offset = vmcs_field_to_offset(field);
7278         char *p;
7279
7280         if (offset < 0)
7281                 return offset;
7282
7283         p = ((char *)(get_vmcs12(vcpu))) + offset;
7284
7285         switch (vmcs_field_type(field)) {
7286         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7287                 *ret = *((natural_width *)p);
7288                 return 0;
7289         case VMCS_FIELD_TYPE_U16:
7290                 *ret = *((u16 *)p);
7291                 return 0;
7292         case VMCS_FIELD_TYPE_U32:
7293                 *ret = *((u32 *)p);
7294                 return 0;
7295         case VMCS_FIELD_TYPE_U64:
7296                 *ret = *((u64 *)p);
7297                 return 0;
7298         default:
7299                 WARN_ON(1);
7300                 return -ENOENT;
7301         }
7302 }
7303
7304
7305 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7306                                    unsigned long field, u64 field_value){
7307         short offset = vmcs_field_to_offset(field);
7308         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7309         if (offset < 0)
7310                 return offset;
7311
7312         switch (vmcs_field_type(field)) {
7313         case VMCS_FIELD_TYPE_U16:
7314                 *(u16 *)p = field_value;
7315                 return 0;
7316         case VMCS_FIELD_TYPE_U32:
7317                 *(u32 *)p = field_value;
7318                 return 0;
7319         case VMCS_FIELD_TYPE_U64:
7320                 *(u64 *)p = field_value;
7321                 return 0;
7322         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7323                 *(natural_width *)p = field_value;
7324                 return 0;
7325         default:
7326                 WARN_ON(1);
7327                 return -ENOENT;
7328         }
7329
7330 }
7331
7332 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7333 {
7334         int i;
7335         unsigned long field;
7336         u64 field_value;
7337         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7338         const unsigned long *fields = shadow_read_write_fields;
7339         const int num_fields = max_shadow_read_write_fields;
7340
7341         preempt_disable();
7342
7343         vmcs_load(shadow_vmcs);
7344
7345         for (i = 0; i < num_fields; i++) {
7346                 field = fields[i];
7347                 switch (vmcs_field_type(field)) {
7348                 case VMCS_FIELD_TYPE_U16:
7349                         field_value = vmcs_read16(field);
7350                         break;
7351                 case VMCS_FIELD_TYPE_U32:
7352                         field_value = vmcs_read32(field);
7353                         break;
7354                 case VMCS_FIELD_TYPE_U64:
7355                         field_value = vmcs_read64(field);
7356                         break;
7357                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7358                         field_value = vmcs_readl(field);
7359                         break;
7360                 default:
7361                         WARN_ON(1);
7362                         continue;
7363                 }
7364                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7365         }
7366
7367         vmcs_clear(shadow_vmcs);
7368         vmcs_load(vmx->loaded_vmcs->vmcs);
7369
7370         preempt_enable();
7371 }
7372
7373 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7374 {
7375         const unsigned long *fields[] = {
7376                 shadow_read_write_fields,
7377                 shadow_read_only_fields
7378         };
7379         const int max_fields[] = {
7380                 max_shadow_read_write_fields,
7381                 max_shadow_read_only_fields
7382         };
7383         int i, q;
7384         unsigned long field;
7385         u64 field_value = 0;
7386         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7387
7388         vmcs_load(shadow_vmcs);
7389
7390         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7391                 for (i = 0; i < max_fields[q]; i++) {
7392                         field = fields[q][i];
7393                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7394
7395                         switch (vmcs_field_type(field)) {
7396                         case VMCS_FIELD_TYPE_U16:
7397                                 vmcs_write16(field, (u16)field_value);
7398                                 break;
7399                         case VMCS_FIELD_TYPE_U32:
7400                                 vmcs_write32(field, (u32)field_value);
7401                                 break;
7402                         case VMCS_FIELD_TYPE_U64:
7403                                 vmcs_write64(field, (u64)field_value);
7404                                 break;
7405                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7406                                 vmcs_writel(field, (long)field_value);
7407                                 break;
7408                         default:
7409                                 WARN_ON(1);
7410                                 break;
7411                         }
7412                 }
7413         }
7414
7415         vmcs_clear(shadow_vmcs);
7416         vmcs_load(vmx->loaded_vmcs->vmcs);
7417 }
7418
7419 /*
7420  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7421  * used before) all generate the same failure when it is missing.
7422  */
7423 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7424 {
7425         struct vcpu_vmx *vmx = to_vmx(vcpu);
7426         if (vmx->nested.current_vmptr == -1ull) {
7427                 nested_vmx_failInvalid(vcpu);
7428                 return 0;
7429         }
7430         return 1;
7431 }
7432
7433 static int handle_vmread(struct kvm_vcpu *vcpu)
7434 {
7435         unsigned long field;
7436         u64 field_value;
7437         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7438         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7439         gva_t gva = 0;
7440
7441         if (!nested_vmx_check_permission(vcpu))
7442                 return 1;
7443
7444         if (!nested_vmx_check_vmcs12(vcpu))
7445                 return kvm_skip_emulated_instruction(vcpu);
7446
7447         /* Decode instruction info and find the field to read */
7448         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7449         /* Read the field, zero-extended to a u64 field_value */
7450         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7451                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7452                 return kvm_skip_emulated_instruction(vcpu);
7453         }
7454         /*
7455          * Now copy part of this value to register or memory, as requested.
7456          * Note that the number of bits actually copied is 32 or 64 depending
7457          * on the guest's mode (32 or 64 bit), not on the given field's length.
7458          */
7459         if (vmx_instruction_info & (1u << 10)) {
7460                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7461                         field_value);
7462         } else {
7463                 if (get_vmx_mem_address(vcpu, exit_qualification,
7464                                 vmx_instruction_info, true, &gva))
7465                         return 1;
7466                 /* _system ok, as hardware has verified cpl=0 */
7467                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7468                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7469         }
7470
7471         nested_vmx_succeed(vcpu);
7472         return kvm_skip_emulated_instruction(vcpu);
7473 }
7474
7475
7476 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7477 {
7478         unsigned long field;
7479         gva_t gva;
7480         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7481         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7482         /* The value to write might be 32 or 64 bits, depending on L1's long
7483          * mode, and eventually we need to write that into a field of several
7484          * possible lengths. The code below first zero-extends the value to 64
7485          * bit (field_value), and then copies only the appropriate number of
7486          * bits into the vmcs12 field.
7487          */
7488         u64 field_value = 0;
7489         struct x86_exception e;
7490
7491         if (!nested_vmx_check_permission(vcpu))
7492                 return 1;
7493
7494         if (!nested_vmx_check_vmcs12(vcpu))
7495                 return kvm_skip_emulated_instruction(vcpu);
7496
7497         if (vmx_instruction_info & (1u << 10))
7498                 field_value = kvm_register_readl(vcpu,
7499                         (((vmx_instruction_info) >> 3) & 0xf));
7500         else {
7501                 if (get_vmx_mem_address(vcpu, exit_qualification,
7502                                 vmx_instruction_info, false, &gva))
7503                         return 1;
7504                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7505                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7506                         kvm_inject_page_fault(vcpu, &e);
7507                         return 1;
7508                 }
7509         }
7510
7511
7512         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7513         if (vmcs_field_readonly(field)) {
7514                 nested_vmx_failValid(vcpu,
7515                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7516                 return kvm_skip_emulated_instruction(vcpu);
7517         }
7518
7519         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7520                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7521                 return kvm_skip_emulated_instruction(vcpu);
7522         }
7523
7524         nested_vmx_succeed(vcpu);
7525         return kvm_skip_emulated_instruction(vcpu);
7526 }
7527
7528 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7529 {
7530         vmx->nested.current_vmptr = vmptr;
7531         if (enable_shadow_vmcs) {
7532                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7533                               SECONDARY_EXEC_SHADOW_VMCS);
7534                 vmcs_write64(VMCS_LINK_POINTER,
7535                              __pa(vmx->vmcs01.shadow_vmcs));
7536                 vmx->nested.sync_shadow_vmcs = true;
7537         }
7538 }
7539
7540 /* Emulate the VMPTRLD instruction */
7541 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7542 {
7543         struct vcpu_vmx *vmx = to_vmx(vcpu);
7544         gpa_t vmptr;
7545
7546         if (!nested_vmx_check_permission(vcpu))
7547                 return 1;
7548
7549         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7550                 return 1;
7551
7552         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7553                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7554                 return kvm_skip_emulated_instruction(vcpu);
7555         }
7556
7557         if (vmptr == vmx->nested.vmxon_ptr) {
7558                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7559                 return kvm_skip_emulated_instruction(vcpu);
7560         }
7561
7562         if (vmx->nested.current_vmptr != vmptr) {
7563                 struct vmcs12 *new_vmcs12;
7564                 struct page *page;
7565                 page = nested_get_page(vcpu, vmptr);
7566                 if (page == NULL) {
7567                         nested_vmx_failInvalid(vcpu);
7568                         return kvm_skip_emulated_instruction(vcpu);
7569                 }
7570                 new_vmcs12 = kmap(page);
7571                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7572                         kunmap(page);
7573                         nested_release_page_clean(page);
7574                         nested_vmx_failValid(vcpu,
7575                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7576                         return kvm_skip_emulated_instruction(vcpu);
7577                 }
7578
7579                 nested_release_vmcs12(vmx);
7580                 vmx->nested.current_vmcs12 = new_vmcs12;
7581                 vmx->nested.current_vmcs12_page = page;
7582                 /*
7583                  * Load VMCS12 from guest memory since it is not already
7584                  * cached.
7585                  */
7586                 memcpy(vmx->nested.cached_vmcs12,
7587                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7588                 set_current_vmptr(vmx, vmptr);
7589         }
7590
7591         nested_vmx_succeed(vcpu);
7592         return kvm_skip_emulated_instruction(vcpu);
7593 }
7594
7595 /* Emulate the VMPTRST instruction */
7596 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7597 {
7598         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7599         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7600         gva_t vmcs_gva;
7601         struct x86_exception e;
7602
7603         if (!nested_vmx_check_permission(vcpu))
7604                 return 1;
7605
7606         if (get_vmx_mem_address(vcpu, exit_qualification,
7607                         vmx_instruction_info, true, &vmcs_gva))
7608                 return 1;
7609         /* ok to use *_system, as hardware has verified cpl=0 */
7610         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7611                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7612                                  sizeof(u64), &e)) {
7613                 kvm_inject_page_fault(vcpu, &e);
7614                 return 1;
7615         }
7616         nested_vmx_succeed(vcpu);
7617         return kvm_skip_emulated_instruction(vcpu);
7618 }
7619
7620 /* Emulate the INVEPT instruction */
7621 static int handle_invept(struct kvm_vcpu *vcpu)
7622 {
7623         struct vcpu_vmx *vmx = to_vmx(vcpu);
7624         u32 vmx_instruction_info, types;
7625         unsigned long type;
7626         gva_t gva;
7627         struct x86_exception e;
7628         struct {
7629                 u64 eptp, gpa;
7630         } operand;
7631
7632         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7633               SECONDARY_EXEC_ENABLE_EPT) ||
7634             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7635                 kvm_queue_exception(vcpu, UD_VECTOR);
7636                 return 1;
7637         }
7638
7639         if (!nested_vmx_check_permission(vcpu))
7640                 return 1;
7641
7642         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7643         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7644
7645         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7646
7647         if (type >= 32 || !(types & (1 << type))) {
7648                 nested_vmx_failValid(vcpu,
7649                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7650                 return kvm_skip_emulated_instruction(vcpu);
7651         }
7652
7653         /* According to the Intel VMX instruction reference, the memory
7654          * operand is read even if it isn't needed (e.g., for type==global)
7655          */
7656         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7657                         vmx_instruction_info, false, &gva))
7658                 return 1;
7659         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7660                                 sizeof(operand), &e)) {
7661                 kvm_inject_page_fault(vcpu, &e);
7662                 return 1;
7663         }
7664
7665         switch (type) {
7666         case VMX_EPT_EXTENT_GLOBAL:
7667         /*
7668          * TODO: track mappings and invalidate
7669          * single context requests appropriately
7670          */
7671         case VMX_EPT_EXTENT_CONTEXT:
7672                 kvm_mmu_sync_roots(vcpu);
7673                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7674                 nested_vmx_succeed(vcpu);
7675                 break;
7676         default:
7677                 BUG_ON(1);
7678                 break;
7679         }
7680
7681         return kvm_skip_emulated_instruction(vcpu);
7682 }
7683
7684 static int handle_invvpid(struct kvm_vcpu *vcpu)
7685 {
7686         struct vcpu_vmx *vmx = to_vmx(vcpu);
7687         u32 vmx_instruction_info;
7688         unsigned long type, types;
7689         gva_t gva;
7690         struct x86_exception e;
7691         struct {
7692                 u64 vpid;
7693                 u64 gla;
7694         } operand;
7695
7696         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7697               SECONDARY_EXEC_ENABLE_VPID) ||
7698                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7699                 kvm_queue_exception(vcpu, UD_VECTOR);
7700                 return 1;
7701         }
7702
7703         if (!nested_vmx_check_permission(vcpu))
7704                 return 1;
7705
7706         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7707         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7708
7709         types = (vmx->nested.nested_vmx_vpid_caps &
7710                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7711
7712         if (type >= 32 || !(types & (1 << type))) {
7713                 nested_vmx_failValid(vcpu,
7714                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7715                 return kvm_skip_emulated_instruction(vcpu);
7716         }
7717
7718         /* according to the intel vmx instruction reference, the memory
7719          * operand is read even if it isn't needed (e.g., for type==global)
7720          */
7721         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7722                         vmx_instruction_info, false, &gva))
7723                 return 1;
7724         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7725                                 sizeof(operand), &e)) {
7726                 kvm_inject_page_fault(vcpu, &e);
7727                 return 1;
7728         }
7729         if (operand.vpid >> 16) {
7730                 nested_vmx_failValid(vcpu,
7731                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7732                 return kvm_skip_emulated_instruction(vcpu);
7733         }
7734
7735         switch (type) {
7736         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7737                 if (is_noncanonical_address(operand.gla)) {
7738                         nested_vmx_failValid(vcpu,
7739                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7740                         return kvm_skip_emulated_instruction(vcpu);
7741                 }
7742                 /* fall through */
7743         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7744         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7745                 if (!operand.vpid) {
7746                         nested_vmx_failValid(vcpu,
7747                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7748                         return kvm_skip_emulated_instruction(vcpu);
7749                 }
7750                 break;
7751         case VMX_VPID_EXTENT_ALL_CONTEXT:
7752                 break;
7753         default:
7754                 WARN_ON_ONCE(1);
7755                 return kvm_skip_emulated_instruction(vcpu);
7756         }
7757
7758         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7759         nested_vmx_succeed(vcpu);
7760
7761         return kvm_skip_emulated_instruction(vcpu);
7762 }
7763
7764 static int handle_pml_full(struct kvm_vcpu *vcpu)
7765 {
7766         unsigned long exit_qualification;
7767
7768         trace_kvm_pml_full(vcpu->vcpu_id);
7769
7770         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7771
7772         /*
7773          * PML buffer FULL happened while executing iret from NMI,
7774          * "blocked by NMI" bit has to be set before next VM entry.
7775          */
7776         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7777                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7778                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7779                                 GUEST_INTR_STATE_NMI);
7780
7781         /*
7782          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7783          * here.., and there's no userspace involvement needed for PML.
7784          */
7785         return 1;
7786 }
7787
7788 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7789 {
7790         kvm_lapic_expired_hv_timer(vcpu);
7791         return 1;
7792 }
7793
7794 /*
7795  * The exit handlers return 1 if the exit was handled fully and guest execution
7796  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7797  * to be done to userspace and return 0.
7798  */
7799 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7800         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7801         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7802         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7803         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7804         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7805         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7806         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7807         [EXIT_REASON_CPUID]                   = handle_cpuid,
7808         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7809         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7810         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7811         [EXIT_REASON_HLT]                     = handle_halt,
7812         [EXIT_REASON_INVD]                    = handle_invd,
7813         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7814         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7815         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7816         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7817         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7818         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7819         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7820         [EXIT_REASON_VMREAD]                  = handle_vmread,
7821         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7822         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7823         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7824         [EXIT_REASON_VMON]                    = handle_vmon,
7825         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7826         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7827         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7828         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7829         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7830         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7831         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7832         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7833         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7834         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7835         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7836         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7837         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7838         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7839         [EXIT_REASON_INVEPT]                  = handle_invept,
7840         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7841         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7842         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7843         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7844         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7845 };
7846
7847 static const int kvm_vmx_max_exit_handlers =
7848         ARRAY_SIZE(kvm_vmx_exit_handlers);
7849
7850 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7851                                        struct vmcs12 *vmcs12)
7852 {
7853         unsigned long exit_qualification;
7854         gpa_t bitmap, last_bitmap;
7855         unsigned int port;
7856         int size;
7857         u8 b;
7858
7859         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7860                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7861
7862         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7863
7864         port = exit_qualification >> 16;
7865         size = (exit_qualification & 7) + 1;
7866
7867         last_bitmap = (gpa_t)-1;
7868         b = -1;
7869
7870         while (size > 0) {
7871                 if (port < 0x8000)
7872                         bitmap = vmcs12->io_bitmap_a;
7873                 else if (port < 0x10000)
7874                         bitmap = vmcs12->io_bitmap_b;
7875                 else
7876                         return true;
7877                 bitmap += (port & 0x7fff) / 8;
7878
7879                 if (last_bitmap != bitmap)
7880                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7881                                 return true;
7882                 if (b & (1 << (port & 7)))
7883                         return true;
7884
7885                 port++;
7886                 size--;
7887                 last_bitmap = bitmap;
7888         }
7889
7890         return false;
7891 }
7892
7893 /*
7894  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7895  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7896  * disinterest in the current event (read or write a specific MSR) by using an
7897  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7898  */
7899 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7900         struct vmcs12 *vmcs12, u32 exit_reason)
7901 {
7902         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7903         gpa_t bitmap;
7904
7905         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7906                 return true;
7907
7908         /*
7909          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7910          * for the four combinations of read/write and low/high MSR numbers.
7911          * First we need to figure out which of the four to use:
7912          */
7913         bitmap = vmcs12->msr_bitmap;
7914         if (exit_reason == EXIT_REASON_MSR_WRITE)
7915                 bitmap += 2048;
7916         if (msr_index >= 0xc0000000) {
7917                 msr_index -= 0xc0000000;
7918                 bitmap += 1024;
7919         }
7920
7921         /* Then read the msr_index'th bit from this bitmap: */
7922         if (msr_index < 1024*8) {
7923                 unsigned char b;
7924                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7925                         return true;
7926                 return 1 & (b >> (msr_index & 7));
7927         } else
7928                 return true; /* let L1 handle the wrong parameter */
7929 }
7930
7931 /*
7932  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7933  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7934  * intercept (via guest_host_mask etc.) the current event.
7935  */
7936 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7937         struct vmcs12 *vmcs12)
7938 {
7939         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7940         int cr = exit_qualification & 15;
7941         int reg;
7942         unsigned long val;
7943
7944         switch ((exit_qualification >> 4) & 3) {
7945         case 0: /* mov to cr */
7946                 reg = (exit_qualification >> 8) & 15;
7947                 val = kvm_register_readl(vcpu, reg);
7948                 switch (cr) {
7949                 case 0:
7950                         if (vmcs12->cr0_guest_host_mask &
7951                             (val ^ vmcs12->cr0_read_shadow))
7952                                 return true;
7953                         break;
7954                 case 3:
7955                         if ((vmcs12->cr3_target_count >= 1 &&
7956                                         vmcs12->cr3_target_value0 == val) ||
7957                                 (vmcs12->cr3_target_count >= 2 &&
7958                                         vmcs12->cr3_target_value1 == val) ||
7959                                 (vmcs12->cr3_target_count >= 3 &&
7960                                         vmcs12->cr3_target_value2 == val) ||
7961                                 (vmcs12->cr3_target_count >= 4 &&
7962                                         vmcs12->cr3_target_value3 == val))
7963                                 return false;
7964                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7965                                 return true;
7966                         break;
7967                 case 4:
7968                         if (vmcs12->cr4_guest_host_mask &
7969                             (vmcs12->cr4_read_shadow ^ val))
7970                                 return true;
7971                         break;
7972                 case 8:
7973                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7974                                 return true;
7975                         break;
7976                 }
7977                 break;
7978         case 2: /* clts */
7979                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7980                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7981                         return true;
7982                 break;
7983         case 1: /* mov from cr */
7984                 switch (cr) {
7985                 case 3:
7986                         if (vmcs12->cpu_based_vm_exec_control &
7987                             CPU_BASED_CR3_STORE_EXITING)
7988                                 return true;
7989                         break;
7990                 case 8:
7991                         if (vmcs12->cpu_based_vm_exec_control &
7992                             CPU_BASED_CR8_STORE_EXITING)
7993                                 return true;
7994                         break;
7995                 }
7996                 break;
7997         case 3: /* lmsw */
7998                 /*
7999                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8000                  * cr0. Other attempted changes are ignored, with no exit.
8001                  */
8002                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8003                 if (vmcs12->cr0_guest_host_mask & 0xe &
8004                     (val ^ vmcs12->cr0_read_shadow))
8005                         return true;
8006                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8007                     !(vmcs12->cr0_read_shadow & 0x1) &&
8008                     (val & 0x1))
8009                         return true;
8010                 break;
8011         }
8012         return false;
8013 }
8014
8015 /*
8016  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8017  * should handle it ourselves in L0 (and then continue L2). Only call this
8018  * when in is_guest_mode (L2).
8019  */
8020 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8021 {
8022         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8023         struct vcpu_vmx *vmx = to_vmx(vcpu);
8024         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8025         u32 exit_reason = vmx->exit_reason;
8026
8027         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8028                                 vmcs_readl(EXIT_QUALIFICATION),
8029                                 vmx->idt_vectoring_info,
8030                                 intr_info,
8031                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8032                                 KVM_ISA_VMX);
8033
8034         if (vmx->nested.nested_run_pending)
8035                 return false;
8036
8037         if (unlikely(vmx->fail)) {
8038                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8039                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8040                 return true;
8041         }
8042
8043         switch (exit_reason) {
8044         case EXIT_REASON_EXCEPTION_NMI:
8045                 if (is_nmi(intr_info))
8046                         return false;
8047                 else if (is_page_fault(intr_info))
8048                         return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
8049                 else if (is_no_device(intr_info) &&
8050                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8051                         return false;
8052                 else if (is_debug(intr_info) &&
8053                          vcpu->guest_debug &
8054                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8055                         return false;
8056                 else if (is_breakpoint(intr_info) &&
8057                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8058                         return false;
8059                 return vmcs12->exception_bitmap &
8060                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8061         case EXIT_REASON_EXTERNAL_INTERRUPT:
8062                 return false;
8063         case EXIT_REASON_TRIPLE_FAULT:
8064                 return true;
8065         case EXIT_REASON_PENDING_INTERRUPT:
8066                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8067         case EXIT_REASON_NMI_WINDOW:
8068                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8069         case EXIT_REASON_TASK_SWITCH:
8070                 return true;
8071         case EXIT_REASON_CPUID:
8072                 return true;
8073         case EXIT_REASON_HLT:
8074                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8075         case EXIT_REASON_INVD:
8076                 return true;
8077         case EXIT_REASON_INVLPG:
8078                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8079         case EXIT_REASON_RDPMC:
8080                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8081         case EXIT_REASON_RDRAND:
8082                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8083         case EXIT_REASON_RDSEED:
8084                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
8085         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8086                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8087         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8088         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8089         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8090         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8091         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8092         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8093                 /*
8094                  * VMX instructions trap unconditionally. This allows L1 to
8095                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8096                  */
8097                 return true;
8098         case EXIT_REASON_CR_ACCESS:
8099                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8100         case EXIT_REASON_DR_ACCESS:
8101                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8102         case EXIT_REASON_IO_INSTRUCTION:
8103                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8104         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8105                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8106         case EXIT_REASON_MSR_READ:
8107         case EXIT_REASON_MSR_WRITE:
8108                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8109         case EXIT_REASON_INVALID_STATE:
8110                 return true;
8111         case EXIT_REASON_MWAIT_INSTRUCTION:
8112                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8113         case EXIT_REASON_MONITOR_TRAP_FLAG:
8114                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8115         case EXIT_REASON_MONITOR_INSTRUCTION:
8116                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8117         case EXIT_REASON_PAUSE_INSTRUCTION:
8118                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8119                         nested_cpu_has2(vmcs12,
8120                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8121         case EXIT_REASON_MCE_DURING_VMENTRY:
8122                 return false;
8123         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8124                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8125         case EXIT_REASON_APIC_ACCESS:
8126                 return nested_cpu_has2(vmcs12,
8127                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8128         case EXIT_REASON_APIC_WRITE:
8129         case EXIT_REASON_EOI_INDUCED:
8130                 /* apic_write and eoi_induced should exit unconditionally. */
8131                 return true;
8132         case EXIT_REASON_EPT_VIOLATION:
8133                 /*
8134                  * L0 always deals with the EPT violation. If nested EPT is
8135                  * used, and the nested mmu code discovers that the address is
8136                  * missing in the guest EPT table (EPT12), the EPT violation
8137                  * will be injected with nested_ept_inject_page_fault()
8138                  */
8139                 return false;
8140         case EXIT_REASON_EPT_MISCONFIG:
8141                 /*
8142                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8143                  * table (shadow on EPT) or a merged EPT table that L0 built
8144                  * (EPT on EPT). So any problems with the structure of the
8145                  * table is L0's fault.
8146                  */
8147                 return false;
8148         case EXIT_REASON_WBINVD:
8149                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8150         case EXIT_REASON_XSETBV:
8151                 return true;
8152         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8153                 /*
8154                  * This should never happen, since it is not possible to
8155                  * set XSS to a non-zero value---neither in L1 nor in L2.
8156                  * If if it were, XSS would have to be checked against
8157                  * the XSS exit bitmap in vmcs12.
8158                  */
8159                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8160         case EXIT_REASON_PREEMPTION_TIMER:
8161                 return false;
8162         case EXIT_REASON_PML_FULL:
8163                 /* We emulate PML support to L1. */
8164                 return false;
8165         default:
8166                 return true;
8167         }
8168 }
8169
8170 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8171 {
8172         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8173         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8174 }
8175
8176 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8177 {
8178         if (vmx->pml_pg) {
8179                 __free_page(vmx->pml_pg);
8180                 vmx->pml_pg = NULL;
8181         }
8182 }
8183
8184 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8185 {
8186         struct vcpu_vmx *vmx = to_vmx(vcpu);
8187         u64 *pml_buf;
8188         u16 pml_idx;
8189
8190         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8191
8192         /* Do nothing if PML buffer is empty */
8193         if (pml_idx == (PML_ENTITY_NUM - 1))
8194                 return;
8195
8196         /* PML index always points to next available PML buffer entity */
8197         if (pml_idx >= PML_ENTITY_NUM)
8198                 pml_idx = 0;
8199         else
8200                 pml_idx++;
8201
8202         pml_buf = page_address(vmx->pml_pg);
8203         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8204                 u64 gpa;
8205
8206                 gpa = pml_buf[pml_idx];
8207                 WARN_ON(gpa & (PAGE_SIZE - 1));
8208                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8209         }
8210
8211         /* reset PML index */
8212         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8213 }
8214
8215 /*
8216  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8217  * Called before reporting dirty_bitmap to userspace.
8218  */
8219 static void kvm_flush_pml_buffers(struct kvm *kvm)
8220 {
8221         int i;
8222         struct kvm_vcpu *vcpu;
8223         /*
8224          * We only need to kick vcpu out of guest mode here, as PML buffer
8225          * is flushed at beginning of all VMEXITs, and it's obvious that only
8226          * vcpus running in guest are possible to have unflushed GPAs in PML
8227          * buffer.
8228          */
8229         kvm_for_each_vcpu(i, vcpu, kvm)
8230                 kvm_vcpu_kick(vcpu);
8231 }
8232
8233 static void vmx_dump_sel(char *name, uint32_t sel)
8234 {
8235         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8236                name, vmcs_read16(sel),
8237                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8238                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8239                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8240 }
8241
8242 static void vmx_dump_dtsel(char *name, uint32_t limit)
8243 {
8244         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8245                name, vmcs_read32(limit),
8246                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8247 }
8248
8249 static void dump_vmcs(void)
8250 {
8251         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8252         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8253         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8254         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8255         u32 secondary_exec_control = 0;
8256         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8257         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8258         int i, n;
8259
8260         if (cpu_has_secondary_exec_ctrls())
8261                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8262
8263         pr_err("*** Guest State ***\n");
8264         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8265                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8266                vmcs_readl(CR0_GUEST_HOST_MASK));
8267         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8268                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8269         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8270         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8271             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8272         {
8273                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8274                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8275                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8276                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8277         }
8278         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8279                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8280         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8281                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8282         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8283                vmcs_readl(GUEST_SYSENTER_ESP),
8284                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8285         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8286         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8287         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8288         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8289         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8290         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8291         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8292         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8293         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8294         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8295         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8296             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8297                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8298                        efer, vmcs_read64(GUEST_IA32_PAT));
8299         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8300                vmcs_read64(GUEST_IA32_DEBUGCTL),
8301                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8302         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8303                 pr_err("PerfGlobCtl = 0x%016llx\n",
8304                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8305         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8306                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8307         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8308                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8309                vmcs_read32(GUEST_ACTIVITY_STATE));
8310         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8311                 pr_err("InterruptStatus = %04x\n",
8312                        vmcs_read16(GUEST_INTR_STATUS));
8313
8314         pr_err("*** Host State ***\n");
8315         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8316                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8317         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8318                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8319                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8320                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8321                vmcs_read16(HOST_TR_SELECTOR));
8322         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8323                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8324                vmcs_readl(HOST_TR_BASE));
8325         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8326                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8327         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8328                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8329                vmcs_readl(HOST_CR4));
8330         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8331                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8332                vmcs_read32(HOST_IA32_SYSENTER_CS),
8333                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8334         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8335                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8336                        vmcs_read64(HOST_IA32_EFER),
8337                        vmcs_read64(HOST_IA32_PAT));
8338         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8339                 pr_err("PerfGlobCtl = 0x%016llx\n",
8340                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8341
8342         pr_err("*** Control State ***\n");
8343         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8344                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8345         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8346         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8347                vmcs_read32(EXCEPTION_BITMAP),
8348                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8349                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8350         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8351                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8352                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8353                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8354         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8355                vmcs_read32(VM_EXIT_INTR_INFO),
8356                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8357                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8358         pr_err("        reason=%08x qualification=%016lx\n",
8359                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8360         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8361                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8362                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8363         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8364         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8365                 pr_err("TSC Multiplier = 0x%016llx\n",
8366                        vmcs_read64(TSC_MULTIPLIER));
8367         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8368                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8369         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8370                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8371         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8372                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8373         n = vmcs_read32(CR3_TARGET_COUNT);
8374         for (i = 0; i + 1 < n; i += 4)
8375                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8376                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8377                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8378         if (i < n)
8379                 pr_err("CR3 target%u=%016lx\n",
8380                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8381         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8382                 pr_err("PLE Gap=%08x Window=%08x\n",
8383                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8384         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8385                 pr_err("Virtual processor ID = 0x%04x\n",
8386                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8387 }
8388
8389 /*
8390  * The guest has exited.  See if we can fix it or if we need userspace
8391  * assistance.
8392  */
8393 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8394 {
8395         struct vcpu_vmx *vmx = to_vmx(vcpu);
8396         u32 exit_reason = vmx->exit_reason;
8397         u32 vectoring_info = vmx->idt_vectoring_info;
8398
8399         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8400         vcpu->arch.gpa_available = false;
8401
8402         /*
8403          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8404          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8405          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8406          * mode as if vcpus is in root mode, the PML buffer must has been
8407          * flushed already.
8408          */
8409         if (enable_pml)
8410                 vmx_flush_pml_buffer(vcpu);
8411
8412         /* If guest state is invalid, start emulating */
8413         if (vmx->emulation_required)
8414                 return handle_invalid_guest_state(vcpu);
8415
8416         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8417                 nested_vmx_vmexit(vcpu, exit_reason,
8418                                   vmcs_read32(VM_EXIT_INTR_INFO),
8419                                   vmcs_readl(EXIT_QUALIFICATION));
8420                 return 1;
8421         }
8422
8423         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8424                 dump_vmcs();
8425                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8426                 vcpu->run->fail_entry.hardware_entry_failure_reason
8427                         = exit_reason;
8428                 return 0;
8429         }
8430
8431         if (unlikely(vmx->fail)) {
8432                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8433                 vcpu->run->fail_entry.hardware_entry_failure_reason
8434                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8435                 return 0;
8436         }
8437
8438         /*
8439          * Note:
8440          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8441          * delivery event since it indicates guest is accessing MMIO.
8442          * The vm-exit can be triggered again after return to guest that
8443          * will cause infinite loop.
8444          */
8445         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8446                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8447                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8448                         exit_reason != EXIT_REASON_PML_FULL &&
8449                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8450                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8451                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8452                 vcpu->run->internal.ndata = 3;
8453                 vcpu->run->internal.data[0] = vectoring_info;
8454                 vcpu->run->internal.data[1] = exit_reason;
8455                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8456                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8457                         vcpu->run->internal.ndata++;
8458                         vcpu->run->internal.data[3] =
8459                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8460                 }
8461                 return 0;
8462         }
8463
8464         if (exit_reason < kvm_vmx_max_exit_handlers
8465             && kvm_vmx_exit_handlers[exit_reason])
8466                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8467         else {
8468                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8469                                 exit_reason);
8470                 kvm_queue_exception(vcpu, UD_VECTOR);
8471                 return 1;
8472         }
8473 }
8474
8475 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8476 {
8477         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8478
8479         if (is_guest_mode(vcpu) &&
8480                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8481                 return;
8482
8483         if (irr == -1 || tpr < irr) {
8484                 vmcs_write32(TPR_THRESHOLD, 0);
8485                 return;
8486         }
8487
8488         vmcs_write32(TPR_THRESHOLD, irr);
8489 }
8490
8491 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8492 {
8493         u32 sec_exec_control;
8494
8495         /* Postpone execution until vmcs01 is the current VMCS. */
8496         if (is_guest_mode(vcpu)) {
8497                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8498                 return;
8499         }
8500
8501         if (!cpu_has_vmx_virtualize_x2apic_mode())
8502                 return;
8503
8504         if (!cpu_need_tpr_shadow(vcpu))
8505                 return;
8506
8507         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8508
8509         if (set) {
8510                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8511                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8512         } else {
8513                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8514                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8515                 vmx_flush_tlb_ept_only(vcpu);
8516         }
8517         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8518
8519         vmx_set_msr_bitmap(vcpu);
8520 }
8521
8522 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8523 {
8524         struct vcpu_vmx *vmx = to_vmx(vcpu);
8525
8526         /*
8527          * Currently we do not handle the nested case where L2 has an
8528          * APIC access page of its own; that page is still pinned.
8529          * Hence, we skip the case where the VCPU is in guest mode _and_
8530          * L1 prepared an APIC access page for L2.
8531          *
8532          * For the case where L1 and L2 share the same APIC access page
8533          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8534          * in the vmcs12), this function will only update either the vmcs01
8535          * or the vmcs02.  If the former, the vmcs02 will be updated by
8536          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8537          * the next L2->L1 exit.
8538          */
8539         if (!is_guest_mode(vcpu) ||
8540             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8541                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8542                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8543                 vmx_flush_tlb_ept_only(vcpu);
8544         }
8545 }
8546
8547 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8548 {
8549         u16 status;
8550         u8 old;
8551
8552         if (max_isr == -1)
8553                 max_isr = 0;
8554
8555         status = vmcs_read16(GUEST_INTR_STATUS);
8556         old = status >> 8;
8557         if (max_isr != old) {
8558                 status &= 0xff;
8559                 status |= max_isr << 8;
8560                 vmcs_write16(GUEST_INTR_STATUS, status);
8561         }
8562 }
8563
8564 static void vmx_set_rvi(int vector)
8565 {
8566         u16 status;
8567         u8 old;
8568
8569         if (vector == -1)
8570                 vector = 0;
8571
8572         status = vmcs_read16(GUEST_INTR_STATUS);
8573         old = (u8)status & 0xff;
8574         if ((u8)vector != old) {
8575                 status &= ~0xff;
8576                 status |= (u8)vector;
8577                 vmcs_write16(GUEST_INTR_STATUS, status);
8578         }
8579 }
8580
8581 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8582 {
8583         if (!is_guest_mode(vcpu)) {
8584                 vmx_set_rvi(max_irr);
8585                 return;
8586         }
8587
8588         if (max_irr == -1)
8589                 return;
8590
8591         /*
8592          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8593          * handles it.
8594          */
8595         if (nested_exit_on_intr(vcpu))
8596                 return;
8597
8598         /*
8599          * Else, fall back to pre-APICv interrupt injection since L2
8600          * is run without virtual interrupt delivery.
8601          */
8602         if (!kvm_event_needs_reinjection(vcpu) &&
8603             vmx_interrupt_allowed(vcpu)) {
8604                 kvm_queue_interrupt(vcpu, max_irr, false);
8605                 vmx_inject_irq(vcpu);
8606         }
8607 }
8608
8609 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8610 {
8611         struct vcpu_vmx *vmx = to_vmx(vcpu);
8612         int max_irr;
8613
8614         WARN_ON(!vcpu->arch.apicv_active);
8615         if (pi_test_on(&vmx->pi_desc)) {
8616                 pi_clear_on(&vmx->pi_desc);
8617                 /*
8618                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8619                  * But on x86 this is just a compiler barrier anyway.
8620                  */
8621                 smp_mb__after_atomic();
8622                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8623         } else {
8624                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8625         }
8626         vmx_hwapic_irr_update(vcpu, max_irr);
8627         return max_irr;
8628 }
8629
8630 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8631 {
8632         if (!kvm_vcpu_apicv_active(vcpu))
8633                 return;
8634
8635         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8636         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8637         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8638         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8639 }
8640
8641 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8642 {
8643         struct vcpu_vmx *vmx = to_vmx(vcpu);
8644
8645         pi_clear_on(&vmx->pi_desc);
8646         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8647 }
8648
8649 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8650 {
8651         u32 exit_intr_info = 0;
8652         u16 basic_exit_reason = (u16)vmx->exit_reason;
8653
8654         if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8655               || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
8656                 return;
8657
8658         if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
8659                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8660         vmx->exit_intr_info = exit_intr_info;
8661
8662         /* if exit due to PF check for async PF */
8663         if (is_page_fault(exit_intr_info))
8664                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
8665
8666         /* Handle machine checks before interrupts are enabled */
8667         if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
8668             is_machine_check(exit_intr_info))
8669                 kvm_machine_check();
8670
8671         /* We need to handle NMIs before interrupts are enabled */
8672         if (is_nmi(exit_intr_info)) {
8673                 kvm_before_handle_nmi(&vmx->vcpu);
8674                 asm("int $2");
8675                 kvm_after_handle_nmi(&vmx->vcpu);
8676         }
8677 }
8678
8679 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8680 {
8681         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8682         register void *__sp asm(_ASM_SP);
8683
8684         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8685                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8686                 unsigned int vector;
8687                 unsigned long entry;
8688                 gate_desc *desc;
8689                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8690 #ifdef CONFIG_X86_64
8691                 unsigned long tmp;
8692 #endif
8693
8694                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8695                 desc = (gate_desc *)vmx->host_idt_base + vector;
8696                 entry = gate_offset(*desc);
8697                 asm volatile(
8698 #ifdef CONFIG_X86_64
8699                         "mov %%" _ASM_SP ", %[sp]\n\t"
8700                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8701                         "push $%c[ss]\n\t"
8702                         "push %[sp]\n\t"
8703 #endif
8704                         "pushf\n\t"
8705                         __ASM_SIZE(push) " $%c[cs]\n\t"
8706                         "call *%[entry]\n\t"
8707                         :
8708 #ifdef CONFIG_X86_64
8709                         [sp]"=&r"(tmp),
8710 #endif
8711                         "+r"(__sp)
8712                         :
8713                         [entry]"r"(entry),
8714                         [ss]"i"(__KERNEL_DS),
8715                         [cs]"i"(__KERNEL_CS)
8716                         );
8717         }
8718 }
8719 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
8720
8721 static bool vmx_has_high_real_mode_segbase(void)
8722 {
8723         return enable_unrestricted_guest || emulate_invalid_guest_state;
8724 }
8725
8726 static bool vmx_mpx_supported(void)
8727 {
8728         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8729                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8730 }
8731
8732 static bool vmx_xsaves_supported(void)
8733 {
8734         return vmcs_config.cpu_based_2nd_exec_ctrl &
8735                 SECONDARY_EXEC_XSAVES;
8736 }
8737
8738 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8739 {
8740         u32 exit_intr_info;
8741         bool unblock_nmi;
8742         u8 vector;
8743         bool idtv_info_valid;
8744
8745         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8746
8747         if (vmx->loaded_vmcs->nmi_known_unmasked)
8748                 return;
8749         /*
8750          * Can't use vmx->exit_intr_info since we're not sure what
8751          * the exit reason is.
8752          */
8753         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8754         unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8755         vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8756         /*
8757          * SDM 3: 27.7.1.2 (September 2008)
8758          * Re-set bit "block by NMI" before VM entry if vmexit caused by
8759          * a guest IRET fault.
8760          * SDM 3: 23.2.2 (September 2008)
8761          * Bit 12 is undefined in any of the following cases:
8762          *  If the VM exit sets the valid bit in the IDT-vectoring
8763          *   information field.
8764          *  If the VM exit is due to a double fault.
8765          */
8766         if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8767             vector != DF_VECTOR && !idtv_info_valid)
8768                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8769                               GUEST_INTR_STATE_NMI);
8770         else
8771                 vmx->loaded_vmcs->nmi_known_unmasked =
8772                         !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8773                           & GUEST_INTR_STATE_NMI);
8774 }
8775
8776 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8777                                       u32 idt_vectoring_info,
8778                                       int instr_len_field,
8779                                       int error_code_field)
8780 {
8781         u8 vector;
8782         int type;
8783         bool idtv_info_valid;
8784
8785         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8786
8787         vcpu->arch.nmi_injected = false;
8788         kvm_clear_exception_queue(vcpu);
8789         kvm_clear_interrupt_queue(vcpu);
8790
8791         if (!idtv_info_valid)
8792                 return;
8793
8794         kvm_make_request(KVM_REQ_EVENT, vcpu);
8795
8796         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8797         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8798
8799         switch (type) {
8800         case INTR_TYPE_NMI_INTR:
8801                 vcpu->arch.nmi_injected = true;
8802                 /*
8803                  * SDM 3: 27.7.1.2 (September 2008)
8804                  * Clear bit "block by NMI" before VM entry if a NMI
8805                  * delivery faulted.
8806                  */
8807                 vmx_set_nmi_mask(vcpu, false);
8808                 break;
8809         case INTR_TYPE_SOFT_EXCEPTION:
8810                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8811                 /* fall through */
8812         case INTR_TYPE_HARD_EXCEPTION:
8813                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8814                         u32 err = vmcs_read32(error_code_field);
8815                         kvm_requeue_exception_e(vcpu, vector, err);
8816                 } else
8817                         kvm_requeue_exception(vcpu, vector);
8818                 break;
8819         case INTR_TYPE_SOFT_INTR:
8820                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8821                 /* fall through */
8822         case INTR_TYPE_EXT_INTR:
8823                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8824                 break;
8825         default:
8826                 break;
8827         }
8828 }
8829
8830 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8831 {
8832         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8833                                   VM_EXIT_INSTRUCTION_LEN,
8834                                   IDT_VECTORING_ERROR_CODE);
8835 }
8836
8837 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8838 {
8839         __vmx_complete_interrupts(vcpu,
8840                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8841                                   VM_ENTRY_INSTRUCTION_LEN,
8842                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8843
8844         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8845 }
8846
8847 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8848 {
8849         int i, nr_msrs;
8850         struct perf_guest_switch_msr *msrs;
8851
8852         msrs = perf_guest_get_msrs(&nr_msrs);
8853
8854         if (!msrs)
8855                 return;
8856
8857         for (i = 0; i < nr_msrs; i++)
8858                 if (msrs[i].host == msrs[i].guest)
8859                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8860                 else
8861                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8862                                         msrs[i].host);
8863 }
8864
8865 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8866 {
8867         struct vcpu_vmx *vmx = to_vmx(vcpu);
8868         u64 tscl;
8869         u32 delta_tsc;
8870
8871         if (vmx->hv_deadline_tsc == -1)
8872                 return;
8873
8874         tscl = rdtsc();
8875         if (vmx->hv_deadline_tsc > tscl)
8876                 /* sure to be 32 bit only because checked on set_hv_timer */
8877                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8878                         cpu_preemption_timer_multi);
8879         else
8880                 delta_tsc = 0;
8881
8882         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8883 }
8884
8885 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8886 {
8887         struct vcpu_vmx *vmx = to_vmx(vcpu);
8888         unsigned long debugctlmsr, cr3, cr4;
8889
8890         /* Don't enter VMX if guest state is invalid, let the exit handler
8891            start emulation until we arrive back to a valid state */
8892         if (vmx->emulation_required)
8893                 return;
8894
8895         if (vmx->ple_window_dirty) {
8896                 vmx->ple_window_dirty = false;
8897                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8898         }
8899
8900         if (vmx->nested.sync_shadow_vmcs) {
8901                 copy_vmcs12_to_shadow(vmx);
8902                 vmx->nested.sync_shadow_vmcs = false;
8903         }
8904
8905         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8906                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8907         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8908                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8909
8910         cr3 = __get_current_cr3_fast();
8911         if (unlikely(cr3 != vmx->host_state.vmcs_host_cr3)) {
8912                 vmcs_writel(HOST_CR3, cr3);
8913                 vmx->host_state.vmcs_host_cr3 = cr3;
8914         }
8915
8916         cr4 = cr4_read_shadow();
8917         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8918                 vmcs_writel(HOST_CR4, cr4);
8919                 vmx->host_state.vmcs_host_cr4 = cr4;
8920         }
8921
8922         /* When single-stepping over STI and MOV SS, we must clear the
8923          * corresponding interruptibility bits in the guest state. Otherwise
8924          * vmentry fails as it then expects bit 14 (BS) in pending debug
8925          * exceptions being set, but that's not correct for the guest debugging
8926          * case. */
8927         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8928                 vmx_set_interrupt_shadow(vcpu, 0);
8929
8930         if (vmx->guest_pkru_valid)
8931                 __write_pkru(vmx->guest_pkru);
8932
8933         atomic_switch_perf_msrs(vmx);
8934         debugctlmsr = get_debugctlmsr();
8935
8936         vmx_arm_hv_timer(vcpu);
8937
8938         vmx->__launched = vmx->loaded_vmcs->launched;
8939         asm(
8940                 /* Store host registers */
8941                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8942                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8943                 "push %%" _ASM_CX " \n\t"
8944                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8945                 "je 1f \n\t"
8946                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8947                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8948                 "1: \n\t"
8949                 /* Reload cr2 if changed */
8950                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8951                 "mov %%cr2, %%" _ASM_DX " \n\t"
8952                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8953                 "je 2f \n\t"
8954                 "mov %%" _ASM_AX", %%cr2 \n\t"
8955                 "2: \n\t"
8956                 /* Check if vmlaunch of vmresume is needed */
8957                 "cmpl $0, %c[launched](%0) \n\t"
8958                 /* Load guest registers.  Don't clobber flags. */
8959                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8960                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8961                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8962                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8963                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8964                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8965 #ifdef CONFIG_X86_64
8966                 "mov %c[r8](%0),  %%r8  \n\t"
8967                 "mov %c[r9](%0),  %%r9  \n\t"
8968                 "mov %c[r10](%0), %%r10 \n\t"
8969                 "mov %c[r11](%0), %%r11 \n\t"
8970                 "mov %c[r12](%0), %%r12 \n\t"
8971                 "mov %c[r13](%0), %%r13 \n\t"
8972                 "mov %c[r14](%0), %%r14 \n\t"
8973                 "mov %c[r15](%0), %%r15 \n\t"
8974 #endif
8975                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8976
8977                 /* Enter guest mode */
8978                 "jne 1f \n\t"
8979                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8980                 "jmp 2f \n\t"
8981                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8982                 "2: "
8983                 /* Save guest registers, load host registers, keep flags */
8984                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8985                 "pop %0 \n\t"
8986                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8987                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8988                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8989                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8990                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8991                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8992                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8993 #ifdef CONFIG_X86_64
8994                 "mov %%r8,  %c[r8](%0) \n\t"
8995                 "mov %%r9,  %c[r9](%0) \n\t"
8996                 "mov %%r10, %c[r10](%0) \n\t"
8997                 "mov %%r11, %c[r11](%0) \n\t"
8998                 "mov %%r12, %c[r12](%0) \n\t"
8999                 "mov %%r13, %c[r13](%0) \n\t"
9000                 "mov %%r14, %c[r14](%0) \n\t"
9001                 "mov %%r15, %c[r15](%0) \n\t"
9002 #endif
9003                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9004                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9005
9006                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9007                 "setbe %c[fail](%0) \n\t"
9008                 ".pushsection .rodata \n\t"
9009                 ".global vmx_return \n\t"
9010                 "vmx_return: " _ASM_PTR " 2b \n\t"
9011                 ".popsection"
9012               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9013                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9014                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9015                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9016                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9017                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9018                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9019                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9020                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9021                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9022                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9023 #ifdef CONFIG_X86_64
9024                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9025                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9026                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9027                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9028                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9029                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9030                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9031                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9032 #endif
9033                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9034                 [wordsize]"i"(sizeof(ulong))
9035               : "cc", "memory"
9036 #ifdef CONFIG_X86_64
9037                 , "rax", "rbx", "rdi", "rsi"
9038                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9039 #else
9040                 , "eax", "ebx", "edi", "esi"
9041 #endif
9042               );
9043
9044         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9045         if (debugctlmsr)
9046                 update_debugctlmsr(debugctlmsr);
9047
9048 #ifndef CONFIG_X86_64
9049         /*
9050          * The sysexit path does not restore ds/es, so we must set them to
9051          * a reasonable value ourselves.
9052          *
9053          * We can't defer this to vmx_load_host_state() since that function
9054          * may be executed in interrupt context, which saves and restore segments
9055          * around it, nullifying its effect.
9056          */
9057         loadsegment(ds, __USER_DS);
9058         loadsegment(es, __USER_DS);
9059 #endif
9060
9061         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9062                                   | (1 << VCPU_EXREG_RFLAGS)
9063                                   | (1 << VCPU_EXREG_PDPTR)
9064                                   | (1 << VCPU_EXREG_SEGMENTS)
9065                                   | (1 << VCPU_EXREG_CR3));
9066         vcpu->arch.regs_dirty = 0;
9067
9068         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9069
9070         vmx->loaded_vmcs->launched = 1;
9071
9072         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9073
9074         /*
9075          * eager fpu is enabled if PKEY is supported and CR4 is switched
9076          * back on host, so it is safe to read guest PKRU from current
9077          * XSAVE.
9078          */
9079         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9080                 vmx->guest_pkru = __read_pkru();
9081                 if (vmx->guest_pkru != vmx->host_pkru) {
9082                         vmx->guest_pkru_valid = true;
9083                         __write_pkru(vmx->host_pkru);
9084                 } else
9085                         vmx->guest_pkru_valid = false;
9086         }
9087
9088         /*
9089          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9090          * we did not inject a still-pending event to L1 now because of
9091          * nested_run_pending, we need to re-enable this bit.
9092          */
9093         if (vmx->nested.nested_run_pending)
9094                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9095
9096         vmx->nested.nested_run_pending = 0;
9097
9098         vmx_complete_atomic_exit(vmx);
9099         vmx_recover_nmi_blocking(vmx);
9100         vmx_complete_interrupts(vmx);
9101 }
9102 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
9103
9104 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9105 {
9106         struct vcpu_vmx *vmx = to_vmx(vcpu);
9107         int cpu;
9108
9109         if (vmx->loaded_vmcs == vmcs)
9110                 return;
9111
9112         cpu = get_cpu();
9113         vmx->loaded_vmcs = vmcs;
9114         vmx_vcpu_put(vcpu);
9115         vmx_vcpu_load(vcpu, cpu);
9116         vcpu->cpu = cpu;
9117         put_cpu();
9118 }
9119
9120 /*
9121  * Ensure that the current vmcs of the logical processor is the
9122  * vmcs01 of the vcpu before calling free_nested().
9123  */
9124 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9125 {
9126        struct vcpu_vmx *vmx = to_vmx(vcpu);
9127        int r;
9128
9129        r = vcpu_load(vcpu);
9130        BUG_ON(r);
9131        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9132        free_nested(vmx);
9133        vcpu_put(vcpu);
9134 }
9135
9136 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9137 {
9138         struct vcpu_vmx *vmx = to_vmx(vcpu);
9139
9140         if (enable_pml)
9141                 vmx_destroy_pml_buffer(vmx);
9142         free_vpid(vmx->vpid);
9143         leave_guest_mode(vcpu);
9144         vmx_free_vcpu_nested(vcpu);
9145         free_loaded_vmcs(vmx->loaded_vmcs);
9146         kfree(vmx->guest_msrs);
9147         kvm_vcpu_uninit(vcpu);
9148         kmem_cache_free(kvm_vcpu_cache, vmx);
9149 }
9150
9151 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9152 {
9153         int err;
9154         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9155         int cpu;
9156
9157         if (!vmx)
9158                 return ERR_PTR(-ENOMEM);
9159
9160         vmx->vpid = allocate_vpid();
9161
9162         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9163         if (err)
9164                 goto free_vcpu;
9165
9166         err = -ENOMEM;
9167
9168         /*
9169          * If PML is turned on, failure on enabling PML just results in failure
9170          * of creating the vcpu, therefore we can simplify PML logic (by
9171          * avoiding dealing with cases, such as enabling PML partially on vcpus
9172          * for the guest, etc.
9173          */
9174         if (enable_pml) {
9175                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9176                 if (!vmx->pml_pg)
9177                         goto uninit_vcpu;
9178         }
9179
9180         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9181         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9182                      > PAGE_SIZE);
9183
9184         if (!vmx->guest_msrs)
9185                 goto free_pml;
9186
9187         vmx->loaded_vmcs = &vmx->vmcs01;
9188         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9189         vmx->loaded_vmcs->shadow_vmcs = NULL;
9190         if (!vmx->loaded_vmcs->vmcs)
9191                 goto free_msrs;
9192         loaded_vmcs_init(vmx->loaded_vmcs);
9193
9194         cpu = get_cpu();
9195         vmx_vcpu_load(&vmx->vcpu, cpu);
9196         vmx->vcpu.cpu = cpu;
9197         err = vmx_vcpu_setup(vmx);
9198         vmx_vcpu_put(&vmx->vcpu);
9199         put_cpu();
9200         if (err)
9201                 goto free_vmcs;
9202         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9203                 err = alloc_apic_access_page(kvm);
9204                 if (err)
9205                         goto free_vmcs;
9206         }
9207
9208         if (enable_ept) {
9209                 if (!kvm->arch.ept_identity_map_addr)
9210                         kvm->arch.ept_identity_map_addr =
9211                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9212                 err = init_rmode_identity_map(kvm);
9213                 if (err)
9214                         goto free_vmcs;
9215         }
9216
9217         if (nested) {
9218                 nested_vmx_setup_ctls_msrs(vmx);
9219                 vmx->nested.vpid02 = allocate_vpid();
9220         }
9221
9222         vmx->nested.posted_intr_nv = -1;
9223         vmx->nested.current_vmptr = -1ull;
9224         vmx->nested.current_vmcs12 = NULL;
9225
9226         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9227
9228         return &vmx->vcpu;
9229
9230 free_vmcs:
9231         free_vpid(vmx->nested.vpid02);
9232         free_loaded_vmcs(vmx->loaded_vmcs);
9233 free_msrs:
9234         kfree(vmx->guest_msrs);
9235 free_pml:
9236         vmx_destroy_pml_buffer(vmx);
9237 uninit_vcpu:
9238         kvm_vcpu_uninit(&vmx->vcpu);
9239 free_vcpu:
9240         free_vpid(vmx->vpid);
9241         kmem_cache_free(kvm_vcpu_cache, vmx);
9242         return ERR_PTR(err);
9243 }
9244
9245 static void __init vmx_check_processor_compat(void *rtn)
9246 {
9247         struct vmcs_config vmcs_conf;
9248
9249         *(int *)rtn = 0;
9250         if (setup_vmcs_config(&vmcs_conf) < 0)
9251                 *(int *)rtn = -EIO;
9252         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9253                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9254                                 smp_processor_id());
9255                 *(int *)rtn = -EIO;
9256         }
9257 }
9258
9259 static int get_ept_level(void)
9260 {
9261         return VMX_EPT_DEFAULT_GAW + 1;
9262 }
9263
9264 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9265 {
9266         u8 cache;
9267         u64 ipat = 0;
9268
9269         /* For VT-d and EPT combination
9270          * 1. MMIO: always map as UC
9271          * 2. EPT with VT-d:
9272          *   a. VT-d without snooping control feature: can't guarantee the
9273          *      result, try to trust guest.
9274          *   b. VT-d with snooping control feature: snooping control feature of
9275          *      VT-d engine can guarantee the cache correctness. Just set it
9276          *      to WB to keep consistent with host. So the same as item 3.
9277          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9278          *    consistent with host MTRR
9279          */
9280         if (is_mmio) {
9281                 cache = MTRR_TYPE_UNCACHABLE;
9282                 goto exit;
9283         }
9284
9285         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9286                 ipat = VMX_EPT_IPAT_BIT;
9287                 cache = MTRR_TYPE_WRBACK;
9288                 goto exit;
9289         }
9290
9291         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9292                 ipat = VMX_EPT_IPAT_BIT;
9293                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9294                         cache = MTRR_TYPE_WRBACK;
9295                 else
9296                         cache = MTRR_TYPE_UNCACHABLE;
9297                 goto exit;
9298         }
9299
9300         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9301
9302 exit:
9303         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9304 }
9305
9306 static int vmx_get_lpage_level(void)
9307 {
9308         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9309                 return PT_DIRECTORY_LEVEL;
9310         else
9311                 /* For shadow and EPT supported 1GB page */
9312                 return PT_PDPE_LEVEL;
9313 }
9314
9315 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9316 {
9317         /*
9318          * These bits in the secondary execution controls field
9319          * are dynamic, the others are mostly based on the hypervisor
9320          * architecture and the guest's CPUID.  Do not touch the
9321          * dynamic bits.
9322          */
9323         u32 mask =
9324                 SECONDARY_EXEC_SHADOW_VMCS |
9325                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9326                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9327
9328         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9329
9330         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9331                      (new_ctl & ~mask) | (cur_ctl & mask));
9332 }
9333
9334 /*
9335  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9336  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9337  */
9338 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9339 {
9340         struct vcpu_vmx *vmx = to_vmx(vcpu);
9341         struct kvm_cpuid_entry2 *entry;
9342
9343         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9344         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9345
9346 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9347         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9348                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9349 } while (0)
9350
9351         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9352         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9353         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9354         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9355         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9356         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9357         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9358         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9359         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9360         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9361         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9362         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9363         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9364         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9365         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9366
9367         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9368         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9369         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9370         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9371         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9372         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9373         cr4_fixed1_update(bit(11),            ecx, bit(2));
9374
9375 #undef cr4_fixed1_update
9376 }
9377
9378 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9379 {
9380         struct kvm_cpuid_entry2 *best;
9381         struct vcpu_vmx *vmx = to_vmx(vcpu);
9382         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9383
9384         if (vmx_rdtscp_supported()) {
9385                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9386                 if (!rdtscp_enabled)
9387                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9388
9389                 if (nested) {
9390                         if (rdtscp_enabled)
9391                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9392                                         SECONDARY_EXEC_RDTSCP;
9393                         else
9394                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9395                                         ~SECONDARY_EXEC_RDTSCP;
9396                 }
9397         }
9398
9399         /* Exposing INVPCID only when PCID is exposed */
9400         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9401         if (vmx_invpcid_supported() &&
9402             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9403             !guest_cpuid_has_pcid(vcpu))) {
9404                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9405
9406                 if (best)
9407                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9408         }
9409
9410         if (cpu_has_secondary_exec_ctrls())
9411                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9412
9413         if (nested_vmx_allowed(vcpu))
9414                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9415                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9416         else
9417                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9418                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9419
9420         if (nested_vmx_allowed(vcpu))
9421                 nested_vmx_cr_fixed1_bits_update(vcpu);
9422 }
9423
9424 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9425 {
9426         if (func == 1 && nested)
9427                 entry->ecx |= bit(X86_FEATURE_VMX);
9428 }
9429
9430 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9431                 struct x86_exception *fault)
9432 {
9433         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9434         struct vcpu_vmx *vmx = to_vmx(vcpu);
9435         u32 exit_reason;
9436         unsigned long exit_qualification = vcpu->arch.exit_qualification;
9437
9438         if (vmx->nested.pml_full) {
9439                 exit_reason = EXIT_REASON_PML_FULL;
9440                 vmx->nested.pml_full = false;
9441                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9442         } else if (fault->error_code & PFERR_RSVD_MASK)
9443                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9444         else
9445                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9446
9447         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
9448         vmcs12->guest_physical_address = fault->address;
9449 }
9450
9451 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9452 {
9453         return nested_ept_get_cr3(vcpu) & VMX_EPT_AD_ENABLE_BIT;
9454 }
9455
9456 /* Callbacks for nested_ept_init_mmu_context: */
9457
9458 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9459 {
9460         /* return the page table to be shadowed - in our case, EPT12 */
9461         return get_vmcs12(vcpu)->ept_pointer;
9462 }
9463
9464 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9465 {
9466         bool wants_ad;
9467
9468         WARN_ON(mmu_is_nested(vcpu));
9469         wants_ad = nested_ept_ad_enabled(vcpu);
9470         if (wants_ad && !enable_ept_ad_bits)
9471                 return 1;
9472
9473         kvm_mmu_unload(vcpu);
9474         kvm_init_shadow_ept_mmu(vcpu,
9475                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9476                         VMX_EPT_EXECUTE_ONLY_BIT,
9477                         wants_ad);
9478         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9479         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9480         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9481
9482         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9483         return 0;
9484 }
9485
9486 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9487 {
9488         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9489 }
9490
9491 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9492                                             u16 error_code)
9493 {
9494         bool inequality, bit;
9495
9496         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9497         inequality =
9498                 (error_code & vmcs12->page_fault_error_code_mask) !=
9499                  vmcs12->page_fault_error_code_match;
9500         return inequality ^ bit;
9501 }
9502
9503 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9504                 struct x86_exception *fault)
9505 {
9506         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9507
9508         WARN_ON(!is_guest_mode(vcpu));
9509
9510         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9511                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9512                                   vmcs_read32(VM_EXIT_INTR_INFO),
9513                                   vmcs_readl(EXIT_QUALIFICATION));
9514         else
9515                 kvm_inject_page_fault(vcpu, fault);
9516 }
9517
9518 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9519                                                struct vmcs12 *vmcs12);
9520
9521 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9522                                         struct vmcs12 *vmcs12)
9523 {
9524         struct vcpu_vmx *vmx = to_vmx(vcpu);
9525         u64 hpa;
9526
9527         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9528                 /*
9529                  * Translate L1 physical address to host physical
9530                  * address for vmcs02. Keep the page pinned, so this
9531                  * physical address remains valid. We keep a reference
9532                  * to it so we can release it later.
9533                  */
9534                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9535                         nested_release_page(vmx->nested.apic_access_page);
9536                 vmx->nested.apic_access_page =
9537                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9538                 /*
9539                  * If translation failed, no matter: This feature asks
9540                  * to exit when accessing the given address, and if it
9541                  * can never be accessed, this feature won't do
9542                  * anything anyway.
9543                  */
9544                 if (vmx->nested.apic_access_page) {
9545                         hpa = page_to_phys(vmx->nested.apic_access_page);
9546                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9547                 } else {
9548                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9549                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9550                 }
9551         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9552                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9553                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9554                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9555                 kvm_vcpu_reload_apic_access_page(vcpu);
9556         }
9557
9558         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9559                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9560                         nested_release_page(vmx->nested.virtual_apic_page);
9561                 vmx->nested.virtual_apic_page =
9562                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9563
9564                 /*
9565                  * If translation failed, VM entry will fail because
9566                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9567                  * Failing the vm entry is _not_ what the processor
9568                  * does but it's basically the only possibility we
9569                  * have.  We could still enter the guest if CR8 load
9570                  * exits are enabled, CR8 store exits are enabled, and
9571                  * virtualize APIC access is disabled; in this case
9572                  * the processor would never use the TPR shadow and we
9573                  * could simply clear the bit from the execution
9574                  * control.  But such a configuration is useless, so
9575                  * let's keep the code simple.
9576                  */
9577                 if (vmx->nested.virtual_apic_page) {
9578                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9579                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9580                 }
9581         }
9582
9583         if (nested_cpu_has_posted_intr(vmcs12)) {
9584                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9585                         kunmap(vmx->nested.pi_desc_page);
9586                         nested_release_page(vmx->nested.pi_desc_page);
9587                 }
9588                 vmx->nested.pi_desc_page =
9589                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9590                 vmx->nested.pi_desc =
9591                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9592                 if (!vmx->nested.pi_desc) {
9593                         nested_release_page_clean(vmx->nested.pi_desc_page);
9594                         return;
9595                 }
9596                 vmx->nested.pi_desc =
9597                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9598                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9599                         (PAGE_SIZE - 1)));
9600                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9601                         page_to_phys(vmx->nested.pi_desc_page) +
9602                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9603                         (PAGE_SIZE - 1)));
9604         }
9605         if (cpu_has_vmx_msr_bitmap() &&
9606             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9607             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9608                 ;
9609         else
9610                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9611                                 CPU_BASED_USE_MSR_BITMAPS);
9612 }
9613
9614 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9615 {
9616         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9617         struct vcpu_vmx *vmx = to_vmx(vcpu);
9618
9619         if (vcpu->arch.virtual_tsc_khz == 0)
9620                 return;
9621
9622         /* Make sure short timeouts reliably trigger an immediate vmexit.
9623          * hrtimer_start does not guarantee this. */
9624         if (preemption_timeout <= 1) {
9625                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9626                 return;
9627         }
9628
9629         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9630         preemption_timeout *= 1000000;
9631         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9632         hrtimer_start(&vmx->nested.preemption_timer,
9633                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9634 }
9635
9636 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
9637                                                struct vmcs12 *vmcs12)
9638 {
9639         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9640                 return 0;
9641
9642         if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
9643             !page_address_valid(vcpu, vmcs12->io_bitmap_b))
9644                 return -EINVAL;
9645
9646         return 0;
9647 }
9648
9649 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9650                                                 struct vmcs12 *vmcs12)
9651 {
9652         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9653                 return 0;
9654
9655         if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
9656                 return -EINVAL;
9657
9658         return 0;
9659 }
9660
9661 /*
9662  * Merge L0's and L1's MSR bitmap, return false to indicate that
9663  * we do not use the hardware.
9664  */
9665 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9666                                                struct vmcs12 *vmcs12)
9667 {
9668         int msr;
9669         struct page *page;
9670         unsigned long *msr_bitmap_l1;
9671         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9672
9673         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9674         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9675                 return false;
9676
9677         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9678         if (!page)
9679                 return false;
9680         msr_bitmap_l1 = (unsigned long *)kmap(page);
9681
9682         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9683
9684         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9685                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9686                         for (msr = 0x800; msr <= 0x8ff; msr++)
9687                                 nested_vmx_disable_intercept_for_msr(
9688                                         msr_bitmap_l1, msr_bitmap_l0,
9689                                         msr, MSR_TYPE_R);
9690
9691                 nested_vmx_disable_intercept_for_msr(
9692                                 msr_bitmap_l1, msr_bitmap_l0,
9693                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9694                                 MSR_TYPE_R | MSR_TYPE_W);
9695
9696                 if (nested_cpu_has_vid(vmcs12)) {
9697                         nested_vmx_disable_intercept_for_msr(
9698                                 msr_bitmap_l1, msr_bitmap_l0,
9699                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9700                                 MSR_TYPE_W);
9701                         nested_vmx_disable_intercept_for_msr(
9702                                 msr_bitmap_l1, msr_bitmap_l0,
9703                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9704                                 MSR_TYPE_W);
9705                 }
9706         }
9707         kunmap(page);
9708         nested_release_page_clean(page);
9709
9710         return true;
9711 }
9712
9713 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9714                                            struct vmcs12 *vmcs12)
9715 {
9716         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9717             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9718             !nested_cpu_has_vid(vmcs12) &&
9719             !nested_cpu_has_posted_intr(vmcs12))
9720                 return 0;
9721
9722         /*
9723          * If virtualize x2apic mode is enabled,
9724          * virtualize apic access must be disabled.
9725          */
9726         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9727             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9728                 return -EINVAL;
9729
9730         /*
9731          * If virtual interrupt delivery is enabled,
9732          * we must exit on external interrupts.
9733          */
9734         if (nested_cpu_has_vid(vmcs12) &&
9735            !nested_exit_on_intr(vcpu))
9736                 return -EINVAL;
9737
9738         /*
9739          * bits 15:8 should be zero in posted_intr_nv,
9740          * the descriptor address has been already checked
9741          * in nested_get_vmcs12_pages.
9742          */
9743         if (nested_cpu_has_posted_intr(vmcs12) &&
9744            (!nested_cpu_has_vid(vmcs12) ||
9745             !nested_exit_intr_ack_set(vcpu) ||
9746             vmcs12->posted_intr_nv & 0xff00))
9747                 return -EINVAL;
9748
9749         /* tpr shadow is needed by all apicv features. */
9750         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9751                 return -EINVAL;
9752
9753         return 0;
9754 }
9755
9756 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9757                                        unsigned long count_field,
9758                                        unsigned long addr_field)
9759 {
9760         int maxphyaddr;
9761         u64 count, addr;
9762
9763         if (vmcs12_read_any(vcpu, count_field, &count) ||
9764             vmcs12_read_any(vcpu, addr_field, &addr)) {
9765                 WARN_ON(1);
9766                 return -EINVAL;
9767         }
9768         if (count == 0)
9769                 return 0;
9770         maxphyaddr = cpuid_maxphyaddr(vcpu);
9771         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9772             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9773                 pr_debug_ratelimited(
9774                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9775                         addr_field, maxphyaddr, count, addr);
9776                 return -EINVAL;
9777         }
9778         return 0;
9779 }
9780
9781 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9782                                                 struct vmcs12 *vmcs12)
9783 {
9784         if (vmcs12->vm_exit_msr_load_count == 0 &&
9785             vmcs12->vm_exit_msr_store_count == 0 &&
9786             vmcs12->vm_entry_msr_load_count == 0)
9787                 return 0; /* Fast path */
9788         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9789                                         VM_EXIT_MSR_LOAD_ADDR) ||
9790             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9791                                         VM_EXIT_MSR_STORE_ADDR) ||
9792             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9793                                         VM_ENTRY_MSR_LOAD_ADDR))
9794                 return -EINVAL;
9795         return 0;
9796 }
9797
9798 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
9799                                          struct vmcs12 *vmcs12)
9800 {
9801         u64 address = vmcs12->pml_address;
9802         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9803
9804         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
9805                 if (!nested_cpu_has_ept(vmcs12) ||
9806                     !IS_ALIGNED(address, 4096)  ||
9807                     address >> maxphyaddr)
9808                         return -EINVAL;
9809         }
9810
9811         return 0;
9812 }
9813
9814 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9815                                        struct vmx_msr_entry *e)
9816 {
9817         /* x2APIC MSR accesses are not allowed */
9818         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9819                 return -EINVAL;
9820         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9821             e->index == MSR_IA32_UCODE_REV)
9822                 return -EINVAL;
9823         if (e->reserved != 0)
9824                 return -EINVAL;
9825         return 0;
9826 }
9827
9828 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9829                                      struct vmx_msr_entry *e)
9830 {
9831         if (e->index == MSR_FS_BASE ||
9832             e->index == MSR_GS_BASE ||
9833             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9834             nested_vmx_msr_check_common(vcpu, e))
9835                 return -EINVAL;
9836         return 0;
9837 }
9838
9839 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9840                                       struct vmx_msr_entry *e)
9841 {
9842         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9843             nested_vmx_msr_check_common(vcpu, e))
9844                 return -EINVAL;
9845         return 0;
9846 }
9847
9848 /*
9849  * Load guest's/host's msr at nested entry/exit.
9850  * return 0 for success, entry index for failure.
9851  */
9852 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9853 {
9854         u32 i;
9855         struct vmx_msr_entry e;
9856         struct msr_data msr;
9857
9858         msr.host_initiated = false;
9859         for (i = 0; i < count; i++) {
9860                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9861                                         &e, sizeof(e))) {
9862                         pr_debug_ratelimited(
9863                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9864                                 __func__, i, gpa + i * sizeof(e));
9865                         goto fail;
9866                 }
9867                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9868                         pr_debug_ratelimited(
9869                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9870                                 __func__, i, e.index, e.reserved);
9871                         goto fail;
9872                 }
9873                 msr.index = e.index;
9874                 msr.data = e.value;
9875                 if (kvm_set_msr(vcpu, &msr)) {
9876                         pr_debug_ratelimited(
9877                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9878                                 __func__, i, e.index, e.value);
9879                         goto fail;
9880                 }
9881         }
9882         return 0;
9883 fail:
9884         return i + 1;
9885 }
9886
9887 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9888 {
9889         u32 i;
9890         struct vmx_msr_entry e;
9891
9892         for (i = 0; i < count; i++) {
9893                 struct msr_data msr_info;
9894                 if (kvm_vcpu_read_guest(vcpu,
9895                                         gpa + i * sizeof(e),
9896                                         &e, 2 * sizeof(u32))) {
9897                         pr_debug_ratelimited(
9898                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9899                                 __func__, i, gpa + i * sizeof(e));
9900                         return -EINVAL;
9901                 }
9902                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9903                         pr_debug_ratelimited(
9904                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9905                                 __func__, i, e.index, e.reserved);
9906                         return -EINVAL;
9907                 }
9908                 msr_info.host_initiated = false;
9909                 msr_info.index = e.index;
9910                 if (kvm_get_msr(vcpu, &msr_info)) {
9911                         pr_debug_ratelimited(
9912                                 "%s cannot read MSR (%u, 0x%x)\n",
9913                                 __func__, i, e.index);
9914                         return -EINVAL;
9915                 }
9916                 if (kvm_vcpu_write_guest(vcpu,
9917                                          gpa + i * sizeof(e) +
9918                                              offsetof(struct vmx_msr_entry, value),
9919                                          &msr_info.data, sizeof(msr_info.data))) {
9920                         pr_debug_ratelimited(
9921                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9922                                 __func__, i, e.index, msr_info.data);
9923                         return -EINVAL;
9924                 }
9925         }
9926         return 0;
9927 }
9928
9929 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9930 {
9931         unsigned long invalid_mask;
9932
9933         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9934         return (val & invalid_mask) == 0;
9935 }
9936
9937 /*
9938  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9939  * emulating VM entry into a guest with EPT enabled.
9940  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9941  * is assigned to entry_failure_code on failure.
9942  */
9943 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
9944                                u32 *entry_failure_code)
9945 {
9946         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
9947                 if (!nested_cr3_valid(vcpu, cr3)) {
9948                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
9949                         return 1;
9950                 }
9951
9952                 /*
9953                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9954                  * must not be dereferenced.
9955                  */
9956                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9957                     !nested_ept) {
9958                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9959                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
9960                                 return 1;
9961                         }
9962                 }
9963
9964                 vcpu->arch.cr3 = cr3;
9965                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9966         }
9967
9968         kvm_mmu_reset_context(vcpu);
9969         return 0;
9970 }
9971
9972 /*
9973  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9974  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9975  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9976  * guest in a way that will both be appropriate to L1's requests, and our
9977  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9978  * function also has additional necessary side-effects, like setting various
9979  * vcpu->arch fields.
9980  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9981  * is assigned to entry_failure_code on failure.
9982  */
9983 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9984                           bool from_vmentry, u32 *entry_failure_code)
9985 {
9986         struct vcpu_vmx *vmx = to_vmx(vcpu);
9987         u32 exec_control, vmcs12_exec_ctrl;
9988
9989         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9990         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9991         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9992         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9993         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9994         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9995         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9996         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9997         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9998         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9999         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10000         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10001         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10002         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10003         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10004         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10005         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10006         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10007         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10008         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10009         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10010         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10011         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10012         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10013         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10014         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10015         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10016         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10017         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10018         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10019         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10020         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10021         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10022         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10023         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10024         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10025
10026         if (from_vmentry &&
10027             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10028                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10029                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10030         } else {
10031                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10032                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10033         }
10034         if (from_vmentry) {
10035                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10036                              vmcs12->vm_entry_intr_info_field);
10037                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10038                              vmcs12->vm_entry_exception_error_code);
10039                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10040                              vmcs12->vm_entry_instruction_len);
10041                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10042                              vmcs12->guest_interruptibility_info);
10043         } else {
10044                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10045         }
10046         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10047         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10048         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10049                 vmcs12->guest_pending_dbg_exceptions);
10050         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10051         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10052
10053         if (nested_cpu_has_xsaves(vmcs12))
10054                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10055         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10056
10057         exec_control = vmcs12->pin_based_vm_exec_control;
10058
10059         /* Preemption timer setting is only taken from vmcs01.  */
10060         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10061         exec_control |= vmcs_config.pin_based_exec_ctrl;
10062         if (vmx->hv_deadline_tsc == -1)
10063                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10064
10065         /* Posted interrupts setting is only taken from vmcs12.  */
10066         if (nested_cpu_has_posted_intr(vmcs12)) {
10067                 /*
10068                  * Note that we use L0's vector here and in
10069                  * vmx_deliver_nested_posted_interrupt.
10070                  */
10071                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10072                 vmx->nested.pi_pending = false;
10073                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10074         } else {
10075                 exec_control &= ~PIN_BASED_POSTED_INTR;
10076         }
10077
10078         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10079
10080         vmx->nested.preemption_timer_expired = false;
10081         if (nested_cpu_has_preemption_timer(vmcs12))
10082                 vmx_start_preemption_timer(vcpu);
10083
10084         /*
10085          * Whether page-faults are trapped is determined by a combination of
10086          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10087          * If enable_ept, L0 doesn't care about page faults and we should
10088          * set all of these to L1's desires. However, if !enable_ept, L0 does
10089          * care about (at least some) page faults, and because it is not easy
10090          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10091          * to exit on each and every L2 page fault. This is done by setting
10092          * MASK=MATCH=0 and (see below) EB.PF=1.
10093          * Note that below we don't need special code to set EB.PF beyond the
10094          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10095          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10096          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10097          *
10098          * A problem with this approach (when !enable_ept) is that L1 may be
10099          * injected with more page faults than it asked for. This could have
10100          * caused problems, but in practice existing hypervisors don't care.
10101          * To fix this, we will need to emulate the PFEC checking (on the L1
10102          * page tables), using walk_addr(), when injecting PFs to L1.
10103          */
10104         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10105                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10106         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10107                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10108
10109         if (cpu_has_secondary_exec_ctrls()) {
10110                 exec_control = vmx_secondary_exec_control(vmx);
10111
10112                 /* Take the following fields only from vmcs12 */
10113                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10114                                   SECONDARY_EXEC_RDTSCP |
10115                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10116                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
10117                 if (nested_cpu_has(vmcs12,
10118                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10119                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10120                                 ~SECONDARY_EXEC_ENABLE_PML;
10121                         exec_control |= vmcs12_exec_ctrl;
10122                 }
10123
10124                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10125                         vmcs_write64(EOI_EXIT_BITMAP0,
10126                                 vmcs12->eoi_exit_bitmap0);
10127                         vmcs_write64(EOI_EXIT_BITMAP1,
10128                                 vmcs12->eoi_exit_bitmap1);
10129                         vmcs_write64(EOI_EXIT_BITMAP2,
10130                                 vmcs12->eoi_exit_bitmap2);
10131                         vmcs_write64(EOI_EXIT_BITMAP3,
10132                                 vmcs12->eoi_exit_bitmap3);
10133                         vmcs_write16(GUEST_INTR_STATUS,
10134                                 vmcs12->guest_intr_status);
10135                 }
10136
10137                 /*
10138                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10139                  * nested_get_vmcs12_pages will either fix it up or
10140                  * remove the VM execution control.
10141                  */
10142                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10143                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10144
10145                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10146         }
10147
10148
10149         /*
10150          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10151          * Some constant fields are set here by vmx_set_constant_host_state().
10152          * Other fields are different per CPU, and will be set later when
10153          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10154          */
10155         vmx_set_constant_host_state(vmx);
10156
10157         /*
10158          * Set the MSR load/store lists to match L0's settings.
10159          */
10160         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10161         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10162         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10163         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10164         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10165
10166         /*
10167          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10168          * entry, but only if the current (host) sp changed from the value
10169          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10170          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10171          * here we just force the write to happen on entry.
10172          */
10173         vmx->host_rsp = 0;
10174
10175         exec_control = vmx_exec_control(vmx); /* L0's desires */
10176         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10177         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10178         exec_control &= ~CPU_BASED_TPR_SHADOW;
10179         exec_control |= vmcs12->cpu_based_vm_exec_control;
10180
10181         /*
10182          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10183          * nested_get_vmcs12_pages can't fix it up, the illegal value
10184          * will result in a VM entry failure.
10185          */
10186         if (exec_control & CPU_BASED_TPR_SHADOW) {
10187                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10188                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10189         }
10190
10191         /*
10192          * Merging of IO bitmap not currently supported.
10193          * Rather, exit every time.
10194          */
10195         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10196         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10197
10198         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10199
10200         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10201          * bitwise-or of what L1 wants to trap for L2, and what we want to
10202          * trap. Note that CR0.TS also needs updating - we do this later.
10203          */
10204         update_exception_bitmap(vcpu);
10205         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10206         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10207
10208         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10209          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10210          * bits are further modified by vmx_set_efer() below.
10211          */
10212         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10213
10214         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10215          * emulated by vmx_set_efer(), below.
10216          */
10217         vm_entry_controls_init(vmx,
10218                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10219                         ~VM_ENTRY_IA32E_MODE) |
10220                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10221
10222         if (from_vmentry &&
10223             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10224                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10225                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10226         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10227                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10228         }
10229
10230         set_cr4_guest_host_mask(vmx);
10231
10232         if (from_vmentry &&
10233             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10234                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10235
10236         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10237                 vmcs_write64(TSC_OFFSET,
10238                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10239         else
10240                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10241         if (kvm_has_tsc_control)
10242                 decache_tsc_multiplier(vmx);
10243
10244         if (enable_vpid) {
10245                 /*
10246                  * There is no direct mapping between vpid02 and vpid12, the
10247                  * vpid02 is per-vCPU for L0 and reused while the value of
10248                  * vpid12 is changed w/ one invvpid during nested vmentry.
10249                  * The vpid12 is allocated by L1 for L2, so it will not
10250                  * influence global bitmap(for vpid01 and vpid02 allocation)
10251                  * even if spawn a lot of nested vCPUs.
10252                  */
10253                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10254                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10255                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10256                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10257                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10258                         }
10259                 } else {
10260                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10261                         vmx_flush_tlb(vcpu);
10262                 }
10263
10264         }
10265
10266         if (enable_pml) {
10267                 /*
10268                  * Conceptually we want to copy the PML address and index from
10269                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10270                  * since we always flush the log on each vmexit, this happens
10271                  * to be equivalent to simply resetting the fields in vmcs02.
10272                  */
10273                 ASSERT(vmx->pml_pg);
10274                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10275                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10276         }
10277
10278         if (nested_cpu_has_ept(vmcs12)) {
10279                 if (nested_ept_init_mmu_context(vcpu)) {
10280                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10281                         return 1;
10282                 }
10283         } else if (nested_cpu_has2(vmcs12,
10284                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10285                 vmx_flush_tlb_ept_only(vcpu);
10286         }
10287
10288         /*
10289          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10290          * bits which we consider mandatory enabled.
10291          * The CR0_READ_SHADOW is what L2 should have expected to read given
10292          * the specifications by L1; It's not enough to take
10293          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10294          * have more bits than L1 expected.
10295          */
10296         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10297         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10298
10299         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10300         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10301
10302         if (from_vmentry &&
10303             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10304                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10305         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10306                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10307         else
10308                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10309         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10310         vmx_set_efer(vcpu, vcpu->arch.efer);
10311
10312         /* Shadow page tables on either EPT or shadow page tables. */
10313         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10314                                 entry_failure_code))
10315                 return 1;
10316
10317         if (!enable_ept)
10318                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10319
10320         /*
10321          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10322          */
10323         if (enable_ept) {
10324                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10325                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10326                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10327                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10328         }
10329
10330         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10331         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10332         return 0;
10333 }
10334
10335 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10336 {
10337         struct vcpu_vmx *vmx = to_vmx(vcpu);
10338
10339         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10340             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10341                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10342
10343         if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10344                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10345
10346         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10347                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10348
10349         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10350                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10351
10352         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10353                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10354
10355         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10356                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10357
10358         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10359                                 vmx->nested.nested_vmx_procbased_ctls_low,
10360                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10361             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10362              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10363                                  vmx->nested.nested_vmx_secondary_ctls_low,
10364                                  vmx->nested.nested_vmx_secondary_ctls_high)) ||
10365             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10366                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10367                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10368             !vmx_control_verify(vmcs12->vm_exit_controls,
10369                                 vmx->nested.nested_vmx_exit_ctls_low,
10370                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10371             !vmx_control_verify(vmcs12->vm_entry_controls,
10372                                 vmx->nested.nested_vmx_entry_ctls_low,
10373                                 vmx->nested.nested_vmx_entry_ctls_high))
10374                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10375
10376         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10377                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10378
10379         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10380             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10381             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10382                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10383
10384         return 0;
10385 }
10386
10387 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10388                                   u32 *exit_qual)
10389 {
10390         bool ia32e;
10391
10392         *exit_qual = ENTRY_FAIL_DEFAULT;
10393
10394         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10395             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10396                 return 1;
10397
10398         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10399             vmcs12->vmcs_link_pointer != -1ull) {
10400                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10401                 return 1;
10402         }
10403
10404         /*
10405          * If the load IA32_EFER VM-entry control is 1, the following checks
10406          * are performed on the field for the IA32_EFER MSR:
10407          * - Bits reserved in the IA32_EFER MSR must be 0.
10408          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10409          *   the IA-32e mode guest VM-exit control. It must also be identical
10410          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10411          *   CR0.PG) is 1.
10412          */
10413         if (to_vmx(vcpu)->nested.nested_run_pending &&
10414             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10415                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10416                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10417                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10418                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10419                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10420                         return 1;
10421         }
10422
10423         /*
10424          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10425          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10426          * the values of the LMA and LME bits in the field must each be that of
10427          * the host address-space size VM-exit control.
10428          */
10429         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10430                 ia32e = (vmcs12->vm_exit_controls &
10431                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10432                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10433                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10434                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10435                         return 1;
10436         }
10437
10438         return 0;
10439 }
10440
10441 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10442 {
10443         struct vcpu_vmx *vmx = to_vmx(vcpu);
10444         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10445         struct loaded_vmcs *vmcs02;
10446         u32 msr_entry_idx;
10447         u32 exit_qual;
10448
10449         vmcs02 = nested_get_current_vmcs02(vmx);
10450         if (!vmcs02)
10451                 return -ENOMEM;
10452
10453         enter_guest_mode(vcpu);
10454
10455         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10456                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10457
10458         vmx_switch_vmcs(vcpu, vmcs02);
10459         vmx_segment_cache_clear(vmx);
10460
10461         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10462                 leave_guest_mode(vcpu);
10463                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10464                 nested_vmx_entry_failure(vcpu, vmcs12,
10465                                          EXIT_REASON_INVALID_STATE, exit_qual);
10466                 return 1;
10467         }
10468
10469         nested_get_vmcs12_pages(vcpu, vmcs12);
10470
10471         msr_entry_idx = nested_vmx_load_msr(vcpu,
10472                                             vmcs12->vm_entry_msr_load_addr,
10473                                             vmcs12->vm_entry_msr_load_count);
10474         if (msr_entry_idx) {
10475                 leave_guest_mode(vcpu);
10476                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10477                 nested_vmx_entry_failure(vcpu, vmcs12,
10478                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10479                 return 1;
10480         }
10481
10482         /*
10483          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10484          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10485          * returned as far as L1 is concerned. It will only return (and set
10486          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10487          */
10488         return 0;
10489 }
10490
10491 /*
10492  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10493  * for running an L2 nested guest.
10494  */
10495 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10496 {
10497         struct vmcs12 *vmcs12;
10498         struct vcpu_vmx *vmx = to_vmx(vcpu);
10499         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
10500         u32 exit_qual;
10501         int ret;
10502
10503         if (!nested_vmx_check_permission(vcpu))
10504                 return 1;
10505
10506         if (!nested_vmx_check_vmcs12(vcpu))
10507                 goto out;
10508
10509         vmcs12 = get_vmcs12(vcpu);
10510
10511         if (enable_shadow_vmcs)
10512                 copy_shadow_to_vmcs12(vmx);
10513
10514         /*
10515          * The nested entry process starts with enforcing various prerequisites
10516          * on vmcs12 as required by the Intel SDM, and act appropriately when
10517          * they fail: As the SDM explains, some conditions should cause the
10518          * instruction to fail, while others will cause the instruction to seem
10519          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10520          * To speed up the normal (success) code path, we should avoid checking
10521          * for misconfigurations which will anyway be caught by the processor
10522          * when using the merged vmcs02.
10523          */
10524         if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
10525                 nested_vmx_failValid(vcpu,
10526                                      VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
10527                 goto out;
10528         }
10529
10530         if (vmcs12->launch_state == launch) {
10531                 nested_vmx_failValid(vcpu,
10532                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10533                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10534                 goto out;
10535         }
10536
10537         ret = check_vmentry_prereqs(vcpu, vmcs12);
10538         if (ret) {
10539                 nested_vmx_failValid(vcpu, ret);
10540                 goto out;
10541         }
10542
10543         /*
10544          * After this point, the trap flag no longer triggers a singlestep trap
10545          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10546          * This is not 100% correct; for performance reasons, we delegate most
10547          * of the checks on host state to the processor.  If those fail,
10548          * the singlestep trap is missed.
10549          */
10550         skip_emulated_instruction(vcpu);
10551
10552         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10553         if (ret) {
10554                 nested_vmx_entry_failure(vcpu, vmcs12,
10555                                          EXIT_REASON_INVALID_STATE, exit_qual);
10556                 return 1;
10557         }
10558
10559         /*
10560          * We're finally done with prerequisite checking, and can start with
10561          * the nested entry.
10562          */
10563
10564         ret = enter_vmx_non_root_mode(vcpu, true);
10565         if (ret)
10566                 return ret;
10567
10568         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10569                 return kvm_vcpu_halt(vcpu);
10570
10571         vmx->nested.nested_run_pending = 1;
10572
10573         return 1;
10574
10575 out:
10576         return kvm_skip_emulated_instruction(vcpu);
10577 }
10578
10579 /*
10580  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10581  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10582  * This function returns the new value we should put in vmcs12.guest_cr0.
10583  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10584  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10585  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10586  *     didn't trap the bit, because if L1 did, so would L0).
10587  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10588  *     been modified by L2, and L1 knows it. So just leave the old value of
10589  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10590  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10591  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10592  *     changed these bits, and therefore they need to be updated, but L0
10593  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10594  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10595  */
10596 static inline unsigned long
10597 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10598 {
10599         return
10600         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10601         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10602         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10603                         vcpu->arch.cr0_guest_owned_bits));
10604 }
10605
10606 static inline unsigned long
10607 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10608 {
10609         return
10610         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10611         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10612         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10613                         vcpu->arch.cr4_guest_owned_bits));
10614 }
10615
10616 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10617                                        struct vmcs12 *vmcs12)
10618 {
10619         u32 idt_vectoring;
10620         unsigned int nr;
10621
10622         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10623                 nr = vcpu->arch.exception.nr;
10624                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10625
10626                 if (kvm_exception_is_soft(nr)) {
10627                         vmcs12->vm_exit_instruction_len =
10628                                 vcpu->arch.event_exit_inst_len;
10629                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10630                 } else
10631                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10632
10633                 if (vcpu->arch.exception.has_error_code) {
10634                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10635                         vmcs12->idt_vectoring_error_code =
10636                                 vcpu->arch.exception.error_code;
10637                 }
10638
10639                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10640         } else if (vcpu->arch.nmi_injected) {
10641                 vmcs12->idt_vectoring_info_field =
10642                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10643         } else if (vcpu->arch.interrupt.pending) {
10644                 nr = vcpu->arch.interrupt.nr;
10645                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10646
10647                 if (vcpu->arch.interrupt.soft) {
10648                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10649                         vmcs12->vm_entry_instruction_len =
10650                                 vcpu->arch.event_exit_inst_len;
10651                 } else
10652                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10653
10654                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10655         }
10656 }
10657
10658 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10659 {
10660         struct vcpu_vmx *vmx = to_vmx(vcpu);
10661
10662         if (vcpu->arch.exception.pending ||
10663                 vcpu->arch.nmi_injected ||
10664                 vcpu->arch.interrupt.pending)
10665                 return -EBUSY;
10666
10667         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10668             vmx->nested.preemption_timer_expired) {
10669                 if (vmx->nested.nested_run_pending)
10670                         return -EBUSY;
10671                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10672                 return 0;
10673         }
10674
10675         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10676                 if (vmx->nested.nested_run_pending)
10677                         return -EBUSY;
10678                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10679                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10680                                   INTR_INFO_VALID_MASK, 0);
10681                 /*
10682                  * The NMI-triggered VM exit counts as injection:
10683                  * clear this one and block further NMIs.
10684                  */
10685                 vcpu->arch.nmi_pending = 0;
10686                 vmx_set_nmi_mask(vcpu, true);
10687                 return 0;
10688         }
10689
10690         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10691             nested_exit_on_intr(vcpu)) {
10692                 if (vmx->nested.nested_run_pending)
10693                         return -EBUSY;
10694                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10695                 return 0;
10696         }
10697
10698         vmx_complete_nested_posted_interrupt(vcpu);
10699         return 0;
10700 }
10701
10702 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10703 {
10704         ktime_t remaining =
10705                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10706         u64 value;
10707
10708         if (ktime_to_ns(remaining) <= 0)
10709                 return 0;
10710
10711         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10712         do_div(value, 1000000);
10713         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10714 }
10715
10716 /*
10717  * Update the guest state fields of vmcs12 to reflect changes that
10718  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10719  * VM-entry controls is also updated, since this is really a guest
10720  * state bit.)
10721  */
10722 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10723 {
10724         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10725         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10726
10727         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10728         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10729         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10730
10731         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10732         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10733         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10734         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10735         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10736         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10737         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10738         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10739         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10740         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10741         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10742         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10743         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10744         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10745         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10746         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10747         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10748         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10749         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10750         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10751         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10752         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10753         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10754         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10755         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10756         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10757         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10758         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10759         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10760         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10761         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10762         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10763         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10764         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10765         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10766         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10767
10768         vmcs12->guest_interruptibility_info =
10769                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10770         vmcs12->guest_pending_dbg_exceptions =
10771                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10772         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10773                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10774         else
10775                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10776
10777         if (nested_cpu_has_preemption_timer(vmcs12)) {
10778                 if (vmcs12->vm_exit_controls &
10779                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10780                         vmcs12->vmx_preemption_timer_value =
10781                                 vmx_get_preemption_timer_value(vcpu);
10782                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10783         }
10784
10785         /*
10786          * In some cases (usually, nested EPT), L2 is allowed to change its
10787          * own CR3 without exiting. If it has changed it, we must keep it.
10788          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10789          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10790          *
10791          * Additionally, restore L2's PDPTR to vmcs12.
10792          */
10793         if (enable_ept) {
10794                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10795                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10796                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10797                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10798                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10799         }
10800
10801         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10802
10803         if (nested_cpu_has_vid(vmcs12))
10804                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10805
10806         vmcs12->vm_entry_controls =
10807                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10808                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10809
10810         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10811                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10812                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10813         }
10814
10815         /* TODO: These cannot have changed unless we have MSR bitmaps and
10816          * the relevant bit asks not to trap the change */
10817         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10818                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10819         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10820                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10821         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10822         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10823         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10824         if (kvm_mpx_supported())
10825                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10826 }
10827
10828 /*
10829  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10830  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10831  * and this function updates it to reflect the changes to the guest state while
10832  * L2 was running (and perhaps made some exits which were handled directly by L0
10833  * without going back to L1), and to reflect the exit reason.
10834  * Note that we do not have to copy here all VMCS fields, just those that
10835  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10836  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10837  * which already writes to vmcs12 directly.
10838  */
10839 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10840                            u32 exit_reason, u32 exit_intr_info,
10841                            unsigned long exit_qualification)
10842 {
10843         /* update guest state fields: */
10844         sync_vmcs12(vcpu, vmcs12);
10845
10846         /* update exit information fields: */
10847
10848         vmcs12->vm_exit_reason = exit_reason;
10849         vmcs12->exit_qualification = exit_qualification;
10850
10851         vmcs12->vm_exit_intr_info = exit_intr_info;
10852         if ((vmcs12->vm_exit_intr_info &
10853              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10854             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10855                 vmcs12->vm_exit_intr_error_code =
10856                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10857         vmcs12->idt_vectoring_info_field = 0;
10858         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10859         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10860
10861         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10862                 vmcs12->launch_state = 1;
10863
10864                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10865                  * instead of reading the real value. */
10866                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10867
10868                 /*
10869                  * Transfer the event that L0 or L1 may wanted to inject into
10870                  * L2 to IDT_VECTORING_INFO_FIELD.
10871                  */
10872                 vmcs12_save_pending_event(vcpu, vmcs12);
10873         }
10874
10875         /*
10876          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10877          * preserved above and would only end up incorrectly in L1.
10878          */
10879         vcpu->arch.nmi_injected = false;
10880         kvm_clear_exception_queue(vcpu);
10881         kvm_clear_interrupt_queue(vcpu);
10882 }
10883
10884 /*
10885  * A part of what we need to when the nested L2 guest exits and we want to
10886  * run its L1 parent, is to reset L1's guest state to the host state specified
10887  * in vmcs12.
10888  * This function is to be called not only on normal nested exit, but also on
10889  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10890  * Failures During or After Loading Guest State").
10891  * This function should be called when the active VMCS is L1's (vmcs01).
10892  */
10893 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10894                                    struct vmcs12 *vmcs12)
10895 {
10896         struct kvm_segment seg;
10897         u32 entry_failure_code;
10898
10899         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10900                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10901         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10902                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10903         else
10904                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10905         vmx_set_efer(vcpu, vcpu->arch.efer);
10906
10907         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10908         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10909         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10910         /*
10911          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10912          * actually changed, because vmx_set_cr0 refers to efer set above.
10913          *
10914          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10915          * (KVM doesn't change it);
10916          */
10917         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
10918         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10919
10920         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
10921         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10922         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10923
10924         nested_ept_uninit_mmu_context(vcpu);
10925
10926         /*
10927          * Only PDPTE load can fail as the value of cr3 was checked on entry and
10928          * couldn't have changed.
10929          */
10930         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10931                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10932
10933         if (!enable_ept)
10934                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10935
10936         if (enable_vpid) {
10937                 /*
10938                  * Trivially support vpid by letting L2s share their parent
10939                  * L1's vpid. TODO: move to a more elaborate solution, giving
10940                  * each L2 its own vpid and exposing the vpid feature to L1.
10941                  */
10942                 vmx_flush_tlb(vcpu);
10943         }
10944
10945
10946         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10947         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10948         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10949         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10950         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10951
10952         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10953         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10954                 vmcs_write64(GUEST_BNDCFGS, 0);
10955
10956         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10957                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10958                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10959         }
10960         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10961                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10962                         vmcs12->host_ia32_perf_global_ctrl);
10963
10964         /* Set L1 segment info according to Intel SDM
10965             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10966         seg = (struct kvm_segment) {
10967                 .base = 0,
10968                 .limit = 0xFFFFFFFF,
10969                 .selector = vmcs12->host_cs_selector,
10970                 .type = 11,
10971                 .present = 1,
10972                 .s = 1,
10973                 .g = 1
10974         };
10975         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10976                 seg.l = 1;
10977         else
10978                 seg.db = 1;
10979         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10980         seg = (struct kvm_segment) {
10981                 .base = 0,
10982                 .limit = 0xFFFFFFFF,
10983                 .type = 3,
10984                 .present = 1,
10985                 .s = 1,
10986                 .db = 1,
10987                 .g = 1
10988         };
10989         seg.selector = vmcs12->host_ds_selector;
10990         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10991         seg.selector = vmcs12->host_es_selector;
10992         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10993         seg.selector = vmcs12->host_ss_selector;
10994         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10995         seg.selector = vmcs12->host_fs_selector;
10996         seg.base = vmcs12->host_fs_base;
10997         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10998         seg.selector = vmcs12->host_gs_selector;
10999         seg.base = vmcs12->host_gs_base;
11000         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11001         seg = (struct kvm_segment) {
11002                 .base = vmcs12->host_tr_base,
11003                 .limit = 0x67,
11004                 .selector = vmcs12->host_tr_selector,
11005                 .type = 11,
11006                 .present = 1
11007         };
11008         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11009
11010         kvm_set_dr(vcpu, 7, 0x400);
11011         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11012
11013         if (cpu_has_vmx_msr_bitmap())
11014                 vmx_set_msr_bitmap(vcpu);
11015
11016         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11017                                 vmcs12->vm_exit_msr_load_count))
11018                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11019 }
11020
11021 /*
11022  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11023  * and modify vmcs12 to make it see what it would expect to see there if
11024  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11025  */
11026 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11027                               u32 exit_intr_info,
11028                               unsigned long exit_qualification)
11029 {
11030         struct vcpu_vmx *vmx = to_vmx(vcpu);
11031         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11032         u32 vm_inst_error = 0;
11033
11034         /* trying to cancel vmlaunch/vmresume is a bug */
11035         WARN_ON_ONCE(vmx->nested.nested_run_pending);
11036
11037         leave_guest_mode(vcpu);
11038         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11039                        exit_qualification);
11040
11041         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11042                                  vmcs12->vm_exit_msr_store_count))
11043                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11044
11045         if (unlikely(vmx->fail))
11046                 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11047
11048         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11049
11050         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11051             && nested_exit_intr_ack_set(vcpu)) {
11052                 int irq = kvm_cpu_get_interrupt(vcpu);
11053                 WARN_ON(irq < 0);
11054                 vmcs12->vm_exit_intr_info = irq |
11055                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11056         }
11057
11058         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11059                                        vmcs12->exit_qualification,
11060                                        vmcs12->idt_vectoring_info_field,
11061                                        vmcs12->vm_exit_intr_info,
11062                                        vmcs12->vm_exit_intr_error_code,
11063                                        KVM_ISA_VMX);
11064
11065         vm_entry_controls_reset_shadow(vmx);
11066         vm_exit_controls_reset_shadow(vmx);
11067         vmx_segment_cache_clear(vmx);
11068
11069         /* if no vmcs02 cache requested, remove the one we used */
11070         if (VMCS02_POOL_SIZE == 0)
11071                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11072
11073         load_vmcs12_host_state(vcpu, vmcs12);
11074
11075         /* Update any VMCS fields that might have changed while L2 ran */
11076         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11077         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11078         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11079         if (vmx->hv_deadline_tsc == -1)
11080                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11081                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11082         else
11083                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11084                               PIN_BASED_VMX_PREEMPTION_TIMER);
11085         if (kvm_has_tsc_control)
11086                 decache_tsc_multiplier(vmx);
11087
11088         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11089                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11090                 vmx_set_virtual_x2apic_mode(vcpu,
11091                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11092         } else if (!nested_cpu_has_ept(vmcs12) &&
11093                    nested_cpu_has2(vmcs12,
11094                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11095                 vmx_flush_tlb_ept_only(vcpu);
11096         }
11097
11098         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11099         vmx->host_rsp = 0;
11100
11101         /* Unpin physical memory we referred to in vmcs02 */
11102         if (vmx->nested.apic_access_page) {
11103                 nested_release_page(vmx->nested.apic_access_page);
11104                 vmx->nested.apic_access_page = NULL;
11105         }
11106         if (vmx->nested.virtual_apic_page) {
11107                 nested_release_page(vmx->nested.virtual_apic_page);
11108                 vmx->nested.virtual_apic_page = NULL;
11109         }
11110         if (vmx->nested.pi_desc_page) {
11111                 kunmap(vmx->nested.pi_desc_page);
11112                 nested_release_page(vmx->nested.pi_desc_page);
11113                 vmx->nested.pi_desc_page = NULL;
11114                 vmx->nested.pi_desc = NULL;
11115         }
11116
11117         /*
11118          * We are now running in L2, mmu_notifier will force to reload the
11119          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11120          */
11121         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11122
11123         /*
11124          * Exiting from L2 to L1, we're now back to L1 which thinks it just
11125          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11126          * success or failure flag accordingly.
11127          */
11128         if (unlikely(vmx->fail)) {
11129                 vmx->fail = 0;
11130                 nested_vmx_failValid(vcpu, vm_inst_error);
11131         } else
11132                 nested_vmx_succeed(vcpu);
11133         if (enable_shadow_vmcs)
11134                 vmx->nested.sync_shadow_vmcs = true;
11135
11136         /* in case we halted in L2 */
11137         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11138 }
11139
11140 /*
11141  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11142  */
11143 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11144 {
11145         if (is_guest_mode(vcpu)) {
11146                 to_vmx(vcpu)->nested.nested_run_pending = 0;
11147                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11148         }
11149         free_nested(to_vmx(vcpu));
11150 }
11151
11152 /*
11153  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11154  * 23.7 "VM-entry failures during or after loading guest state" (this also
11155  * lists the acceptable exit-reason and exit-qualification parameters).
11156  * It should only be called before L2 actually succeeded to run, and when
11157  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11158  */
11159 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11160                         struct vmcs12 *vmcs12,
11161                         u32 reason, unsigned long qualification)
11162 {
11163         load_vmcs12_host_state(vcpu, vmcs12);
11164         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11165         vmcs12->exit_qualification = qualification;
11166         nested_vmx_succeed(vcpu);
11167         if (enable_shadow_vmcs)
11168                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11169 }
11170
11171 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11172                                struct x86_instruction_info *info,
11173                                enum x86_intercept_stage stage)
11174 {
11175         return X86EMUL_CONTINUE;
11176 }
11177
11178 #ifdef CONFIG_X86_64
11179 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11180 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11181                                   u64 divisor, u64 *result)
11182 {
11183         u64 low = a << shift, high = a >> (64 - shift);
11184
11185         /* To avoid the overflow on divq */
11186         if (high >= divisor)
11187                 return 1;
11188
11189         /* Low hold the result, high hold rem which is discarded */
11190         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11191             "rm" (divisor), "0" (low), "1" (high));
11192         *result = low;
11193
11194         return 0;
11195 }
11196
11197 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11198 {
11199         struct vcpu_vmx *vmx = to_vmx(vcpu);
11200         u64 tscl = rdtsc();
11201         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11202         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11203
11204         /* Convert to host delta tsc if tsc scaling is enabled */
11205         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11206                         u64_shl_div_u64(delta_tsc,
11207                                 kvm_tsc_scaling_ratio_frac_bits,
11208                                 vcpu->arch.tsc_scaling_ratio,
11209                                 &delta_tsc))
11210                 return -ERANGE;
11211
11212         /*
11213          * If the delta tsc can't fit in the 32 bit after the multi shift,
11214          * we can't use the preemption timer.
11215          * It's possible that it fits on later vmentries, but checking
11216          * on every vmentry is costly so we just use an hrtimer.
11217          */
11218         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11219                 return -ERANGE;
11220
11221         vmx->hv_deadline_tsc = tscl + delta_tsc;
11222         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11223                         PIN_BASED_VMX_PREEMPTION_TIMER);
11224
11225         return delta_tsc == 0;
11226 }
11227
11228 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11229 {
11230         struct vcpu_vmx *vmx = to_vmx(vcpu);
11231         vmx->hv_deadline_tsc = -1;
11232         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11233                         PIN_BASED_VMX_PREEMPTION_TIMER);
11234 }
11235 #endif
11236
11237 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11238 {
11239         if (ple_gap)
11240                 shrink_ple_window(vcpu);
11241 }
11242
11243 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11244                                      struct kvm_memory_slot *slot)
11245 {
11246         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11247         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11248 }
11249
11250 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11251                                        struct kvm_memory_slot *slot)
11252 {
11253         kvm_mmu_slot_set_dirty(kvm, slot);
11254 }
11255
11256 static void vmx_flush_log_dirty(struct kvm *kvm)
11257 {
11258         kvm_flush_pml_buffers(kvm);
11259 }
11260
11261 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11262 {
11263         struct vmcs12 *vmcs12;
11264         struct vcpu_vmx *vmx = to_vmx(vcpu);
11265         gpa_t gpa;
11266         struct page *page = NULL;
11267         u64 *pml_address;
11268
11269         if (is_guest_mode(vcpu)) {
11270                 WARN_ON_ONCE(vmx->nested.pml_full);
11271
11272                 /*
11273                  * Check if PML is enabled for the nested guest.
11274                  * Whether eptp bit 6 is set is already checked
11275                  * as part of A/D emulation.
11276                  */
11277                 vmcs12 = get_vmcs12(vcpu);
11278                 if (!nested_cpu_has_pml(vmcs12))
11279                         return 0;
11280
11281                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
11282                         vmx->nested.pml_full = true;
11283                         return 1;
11284                 }
11285
11286                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11287
11288                 page = nested_get_page(vcpu, vmcs12->pml_address);
11289                 if (!page)
11290                         return 0;
11291
11292                 pml_address = kmap(page);
11293                 pml_address[vmcs12->guest_pml_index--] = gpa;
11294                 kunmap(page);
11295                 nested_release_page_clean(page);
11296         }
11297
11298         return 0;
11299 }
11300
11301 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11302                                            struct kvm_memory_slot *memslot,
11303                                            gfn_t offset, unsigned long mask)
11304 {
11305         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11306 }
11307
11308 /*
11309  * This routine does the following things for vCPU which is going
11310  * to be blocked if VT-d PI is enabled.
11311  * - Store the vCPU to the wakeup list, so when interrupts happen
11312  *   we can find the right vCPU to wake up.
11313  * - Change the Posted-interrupt descriptor as below:
11314  *      'NDST' <-- vcpu->pre_pcpu
11315  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11316  * - If 'ON' is set during this process, which means at least one
11317  *   interrupt is posted for this vCPU, we cannot block it, in
11318  *   this case, return 1, otherwise, return 0.
11319  *
11320  */
11321 static int pi_pre_block(struct kvm_vcpu *vcpu)
11322 {
11323         unsigned long flags;
11324         unsigned int dest;
11325         struct pi_desc old, new;
11326         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11327
11328         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11329                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11330                 !kvm_vcpu_apicv_active(vcpu))
11331                 return 0;
11332
11333         vcpu->pre_pcpu = vcpu->cpu;
11334         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11335                           vcpu->pre_pcpu), flags);
11336         list_add_tail(&vcpu->blocked_vcpu_list,
11337                       &per_cpu(blocked_vcpu_on_cpu,
11338                       vcpu->pre_pcpu));
11339         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11340                                vcpu->pre_pcpu), flags);
11341
11342         do {
11343                 old.control = new.control = pi_desc->control;
11344
11345                 /*
11346                  * We should not block the vCPU if
11347                  * an interrupt is posted for it.
11348                  */
11349                 if (pi_test_on(pi_desc) == 1) {
11350                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11351                                           vcpu->pre_pcpu), flags);
11352                         list_del(&vcpu->blocked_vcpu_list);
11353                         spin_unlock_irqrestore(
11354                                         &per_cpu(blocked_vcpu_on_cpu_lock,
11355                                         vcpu->pre_pcpu), flags);
11356                         vcpu->pre_pcpu = -1;
11357
11358                         return 1;
11359                 }
11360
11361                 WARN((pi_desc->sn == 1),
11362                      "Warning: SN field of posted-interrupts "
11363                      "is set before blocking\n");
11364
11365                 /*
11366                  * Since vCPU can be preempted during this process,
11367                  * vcpu->cpu could be different with pre_pcpu, we
11368                  * need to set pre_pcpu as the destination of wakeup
11369                  * notification event, then we can find the right vCPU
11370                  * to wakeup in wakeup handler if interrupts happen
11371                  * when the vCPU is in blocked state.
11372                  */
11373                 dest = cpu_physical_id(vcpu->pre_pcpu);
11374
11375                 if (x2apic_enabled())
11376                         new.ndst = dest;
11377                 else
11378                         new.ndst = (dest << 8) & 0xFF00;
11379
11380                 /* set 'NV' to 'wakeup vector' */
11381                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11382         } while (cmpxchg(&pi_desc->control, old.control,
11383                         new.control) != old.control);
11384
11385         return 0;
11386 }
11387
11388 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11389 {
11390         if (pi_pre_block(vcpu))
11391                 return 1;
11392
11393         if (kvm_lapic_hv_timer_in_use(vcpu))
11394                 kvm_lapic_switch_to_sw_timer(vcpu);
11395
11396         return 0;
11397 }
11398
11399 static void pi_post_block(struct kvm_vcpu *vcpu)
11400 {
11401         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11402         struct pi_desc old, new;
11403         unsigned int dest;
11404         unsigned long flags;
11405
11406         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11407                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11408                 !kvm_vcpu_apicv_active(vcpu))
11409                 return;
11410
11411         do {
11412                 old.control = new.control = pi_desc->control;
11413
11414                 dest = cpu_physical_id(vcpu->cpu);
11415
11416                 if (x2apic_enabled())
11417                         new.ndst = dest;
11418                 else
11419                         new.ndst = (dest << 8) & 0xFF00;
11420
11421                 /* Allow posting non-urgent interrupts */
11422                 new.sn = 0;
11423
11424                 /* set 'NV' to 'notification vector' */
11425                 new.nv = POSTED_INTR_VECTOR;
11426         } while (cmpxchg(&pi_desc->control, old.control,
11427                         new.control) != old.control);
11428
11429         if(vcpu->pre_pcpu != -1) {
11430                 spin_lock_irqsave(
11431                         &per_cpu(blocked_vcpu_on_cpu_lock,
11432                         vcpu->pre_pcpu), flags);
11433                 list_del(&vcpu->blocked_vcpu_list);
11434                 spin_unlock_irqrestore(
11435                         &per_cpu(blocked_vcpu_on_cpu_lock,
11436                         vcpu->pre_pcpu), flags);
11437                 vcpu->pre_pcpu = -1;
11438         }
11439 }
11440
11441 static void vmx_post_block(struct kvm_vcpu *vcpu)
11442 {
11443         if (kvm_x86_ops->set_hv_timer)
11444                 kvm_lapic_switch_to_hv_timer(vcpu);
11445
11446         pi_post_block(vcpu);
11447 }
11448
11449 /*
11450  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11451  *
11452  * @kvm: kvm
11453  * @host_irq: host irq of the interrupt
11454  * @guest_irq: gsi of the interrupt
11455  * @set: set or unset PI
11456  * returns 0 on success, < 0 on failure
11457  */
11458 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11459                               uint32_t guest_irq, bool set)
11460 {
11461         struct kvm_kernel_irq_routing_entry *e;
11462         struct kvm_irq_routing_table *irq_rt;
11463         struct kvm_lapic_irq irq;
11464         struct kvm_vcpu *vcpu;
11465         struct vcpu_data vcpu_info;
11466         int idx, ret = -EINVAL;
11467
11468         if (!kvm_arch_has_assigned_device(kvm) ||
11469                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11470                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11471                 return 0;
11472
11473         idx = srcu_read_lock(&kvm->irq_srcu);
11474         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11475         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11476
11477         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11478                 if (e->type != KVM_IRQ_ROUTING_MSI)
11479                         continue;
11480                 /*
11481                  * VT-d PI cannot support posting multicast/broadcast
11482                  * interrupts to a vCPU, we still use interrupt remapping
11483                  * for these kind of interrupts.
11484                  *
11485                  * For lowest-priority interrupts, we only support
11486                  * those with single CPU as the destination, e.g. user
11487                  * configures the interrupts via /proc/irq or uses
11488                  * irqbalance to make the interrupts single-CPU.
11489                  *
11490                  * We will support full lowest-priority interrupt later.
11491                  */
11492
11493                 kvm_set_msi_irq(kvm, e, &irq);
11494                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11495                         /*
11496                          * Make sure the IRTE is in remapped mode if
11497                          * we don't handle it in posted mode.
11498                          */
11499                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11500                         if (ret < 0) {
11501                                 printk(KERN_INFO
11502                                    "failed to back to remapped mode, irq: %u\n",
11503                                    host_irq);
11504                                 goto out;
11505                         }
11506
11507                         continue;
11508                 }
11509
11510                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11511                 vcpu_info.vector = irq.vector;
11512
11513                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11514                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11515
11516                 if (set)
11517                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11518                 else {
11519                         /* suppress notification event before unposting */
11520                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11521                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11522                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11523                 }
11524
11525                 if (ret < 0) {
11526                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11527                                         __func__);
11528                         goto out;
11529                 }
11530         }
11531
11532         ret = 0;
11533 out:
11534         srcu_read_unlock(&kvm->irq_srcu, idx);
11535         return ret;
11536 }
11537
11538 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11539 {
11540         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11541                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11542                         FEATURE_CONTROL_LMCE;
11543         else
11544                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11545                         ~FEATURE_CONTROL_LMCE;
11546 }
11547
11548 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11549         .cpu_has_kvm_support = cpu_has_kvm_support,
11550         .disabled_by_bios = vmx_disabled_by_bios,
11551         .hardware_setup = hardware_setup,
11552         .hardware_unsetup = hardware_unsetup,
11553         .check_processor_compatibility = vmx_check_processor_compat,
11554         .hardware_enable = hardware_enable,
11555         .hardware_disable = hardware_disable,
11556         .cpu_has_accelerated_tpr = report_flexpriority,
11557         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11558
11559         .vcpu_create = vmx_create_vcpu,
11560         .vcpu_free = vmx_free_vcpu,
11561         .vcpu_reset = vmx_vcpu_reset,
11562
11563         .prepare_guest_switch = vmx_save_host_state,
11564         .vcpu_load = vmx_vcpu_load,
11565         .vcpu_put = vmx_vcpu_put,
11566
11567         .update_bp_intercept = update_exception_bitmap,
11568         .get_msr = vmx_get_msr,
11569         .set_msr = vmx_set_msr,
11570         .get_segment_base = vmx_get_segment_base,
11571         .get_segment = vmx_get_segment,
11572         .set_segment = vmx_set_segment,
11573         .get_cpl = vmx_get_cpl,
11574         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11575         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11576         .decache_cr3 = vmx_decache_cr3,
11577         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11578         .set_cr0 = vmx_set_cr0,
11579         .set_cr3 = vmx_set_cr3,
11580         .set_cr4 = vmx_set_cr4,
11581         .set_efer = vmx_set_efer,
11582         .get_idt = vmx_get_idt,
11583         .set_idt = vmx_set_idt,
11584         .get_gdt = vmx_get_gdt,
11585         .set_gdt = vmx_set_gdt,
11586         .get_dr6 = vmx_get_dr6,
11587         .set_dr6 = vmx_set_dr6,
11588         .set_dr7 = vmx_set_dr7,
11589         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11590         .cache_reg = vmx_cache_reg,
11591         .get_rflags = vmx_get_rflags,
11592         .set_rflags = vmx_set_rflags,
11593
11594         .get_pkru = vmx_get_pkru,
11595
11596         .tlb_flush = vmx_flush_tlb,
11597
11598         .run = vmx_vcpu_run,
11599         .handle_exit = vmx_handle_exit,
11600         .skip_emulated_instruction = skip_emulated_instruction,
11601         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11602         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11603         .patch_hypercall = vmx_patch_hypercall,
11604         .set_irq = vmx_inject_irq,
11605         .set_nmi = vmx_inject_nmi,
11606         .queue_exception = vmx_queue_exception,
11607         .cancel_injection = vmx_cancel_injection,
11608         .interrupt_allowed = vmx_interrupt_allowed,
11609         .nmi_allowed = vmx_nmi_allowed,
11610         .get_nmi_mask = vmx_get_nmi_mask,
11611         .set_nmi_mask = vmx_set_nmi_mask,
11612         .enable_nmi_window = enable_nmi_window,
11613         .enable_irq_window = enable_irq_window,
11614         .update_cr8_intercept = update_cr8_intercept,
11615         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11616         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11617         .get_enable_apicv = vmx_get_enable_apicv,
11618         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11619         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11620         .apicv_post_state_restore = vmx_apicv_post_state_restore,
11621         .hwapic_irr_update = vmx_hwapic_irr_update,
11622         .hwapic_isr_update = vmx_hwapic_isr_update,
11623         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11624         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11625
11626         .set_tss_addr = vmx_set_tss_addr,
11627         .get_tdp_level = get_ept_level,
11628         .get_mt_mask = vmx_get_mt_mask,
11629
11630         .get_exit_info = vmx_get_exit_info,
11631
11632         .get_lpage_level = vmx_get_lpage_level,
11633
11634         .cpuid_update = vmx_cpuid_update,
11635
11636         .rdtscp_supported = vmx_rdtscp_supported,
11637         .invpcid_supported = vmx_invpcid_supported,
11638
11639         .set_supported_cpuid = vmx_set_supported_cpuid,
11640
11641         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11642
11643         .write_tsc_offset = vmx_write_tsc_offset,
11644
11645         .set_tdp_cr3 = vmx_set_cr3,
11646
11647         .check_intercept = vmx_check_intercept,
11648         .handle_external_intr = vmx_handle_external_intr,
11649         .mpx_supported = vmx_mpx_supported,
11650         .xsaves_supported = vmx_xsaves_supported,
11651
11652         .check_nested_events = vmx_check_nested_events,
11653
11654         .sched_in = vmx_sched_in,
11655
11656         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11657         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11658         .flush_log_dirty = vmx_flush_log_dirty,
11659         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11660         .write_log_dirty = vmx_write_pml_buffer,
11661
11662         .pre_block = vmx_pre_block,
11663         .post_block = vmx_post_block,
11664
11665         .pmu_ops = &intel_pmu_ops,
11666
11667         .update_pi_irte = vmx_update_pi_irte,
11668
11669 #ifdef CONFIG_X86_64
11670         .set_hv_timer = vmx_set_hv_timer,
11671         .cancel_hv_timer = vmx_cancel_hv_timer,
11672 #endif
11673
11674         .setup_mce = vmx_setup_mce,
11675 };
11676
11677 static int __init vmx_init(void)
11678 {
11679         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11680                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11681         if (r)
11682                 return r;
11683
11684 #ifdef CONFIG_KEXEC_CORE
11685         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11686                            crash_vmclear_local_loaded_vmcss);
11687 #endif
11688
11689         return 0;
11690 }
11691
11692 static void __exit vmx_exit(void)
11693 {
11694 #ifdef CONFIG_KEXEC_CORE
11695         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11696         synchronize_rcu();
11697 #endif
11698
11699         kvm_exit();
11700 }
11701
11702 module_init(vmx_init)
11703 module_exit(vmx_exit)